SPI MASTER [MAINTENANCE]: Add some code tuning

Author: jakubcabal

rtl/spi_master.vhd

@@ -48,7 +48,7 @@ entity SPI_MASTER is
         MOSI     : out std_logic; -- SPI serial data from master to slave
         MISO     : in  std_logic; -- SPI serial data from slave to master
         -- INPUT USER INTERFACE
-        DIN_ADDR : in  std_logic_vector(integer(ceil(log2(real(SLAVE_COUNT))))-1 downto 0); -- SPI slave address
+        DIN_ADDR : in  std_logic_vector(natural(ceil(log2(real(SLAVE_COUNT))))-1 downto 0); -- SPI slave address
         DIN      : in  std_logic_vector(WORD_SIZE-1 downto 0); -- input data for SPI slave
         DIN_LAST : in  std_logic; -- when DIN_LAST = 1, after transmit these input data is asserted CS_N
         DIN_VLD  : in  std_logic; -- when DIN_VLD = 1, input data are valid
@@ -61,32 +61,31 @@ end entity;
 
 architecture RTL of SPI_MASTER is
 
-    constant DIVIDER_VALUE      : integer := (CLK_FREQ/SCLK_FREQ)/2;
-    constant WIDTH_CLK_CNT      : integer := integer(ceil(log2(real(DIVIDER_VALUE))));
-    constant WIDTH_ADDR         : integer := integer(ceil(log2(real(SLAVE_COUNT))));
-    constant BIT_CNT_WIDTH      : natural := natural(ceil(log2(real(WORD_SIZE))));
-
-    signal addr_reg             : std_logic_vector(WIDTH_ADDR-1 downto 0);
-    signal sys_clk_cnt          : unsigned(WIDTH_CLK_CNT-1 downto 0);
-    signal sys_clk_cnt_max      : std_logic;
-    signal sys_clk_cnt_rst      : std_logic;
-    signal spi_clk              : std_logic;
-    signal spi_clk_en           : std_logic;
-    signal din_last_reg_n       : std_logic;
-    signal first_edge_en        : std_logic;
-    signal second_edge_en       : std_logic;
-    signal chip_select_n        : std_logic;
-    signal load_data            : std_logic;
-    signal miso_reg             : std_logic;
-    signal shreg                : std_logic_vector(WORD_SIZE-1 downto 0);
-    signal bit_cnt              : unsigned(BIT_CNT_WIDTH-1 downto 0);
-    signal bit_cnt_max          : std_logic;
-    signal bit_cnt_rst          : std_logic;
-    signal rx_data_vld          : std_logic;
-    signal master_ready         : std_logic;
-
-    type state is (idle, first_edge, second_edge, transmit_end, transmit_gap);
-    signal present_state, next_state : state;
+    constant DIVIDER_VALUE : natural := (CLK_FREQ/SCLK_FREQ)/2;
+    constant WIDTH_CLK_CNT : natural := natural(ceil(log2(real(DIVIDER_VALUE))));
+    constant WIDTH_ADDR    : natural := natural(ceil(log2(real(SLAVE_COUNT))));
+    constant BIT_CNT_WIDTH : natural := natural(ceil(log2(real(WORD_SIZE))));
+
+    type state_t is (idle, first_edge, second_edge, transmit_end, transmit_gap);
+
+    signal addr_reg        : unsigned(WIDTH_ADDR-1 downto 0);
+    signal sys_clk_cnt     : unsigned(WIDTH_CLK_CNT-1 downto 0);
+    signal sys_clk_cnt_max : std_logic;
+    signal spi_clk         : std_logic;
+    signal spi_clk_rst     : std_logic;
+    signal din_last_reg_n  : std_logic;
+    signal first_edge_en   : std_logic;
+    signal second_edge_en  : std_logic;
+    signal chip_select_n   : std_logic;
+    signal load_data       : std_logic;
+    signal miso_reg        : std_logic;
+    signal shreg           : std_logic_vector(WORD_SIZE-1 downto 0);
+    signal bit_cnt         : unsigned(BIT_CNT_WIDTH-1 downto 0);
+    signal bit_cnt_max     : std_logic;
+    signal rx_data_vld     : std_logic;
+    signal master_ready    : std_logic;
+    signal present_state   : state_t;
+    signal next_state      : state_t;
 
 begin
 
@@ -100,12 +99,11 @@ begin
     -- -------------------------------------------------------------------------
 
     sys_clk_cnt_max <= '1' when (to_integer(sys_clk_cnt) = DIVIDER_VALUE-1) else '0';
-    sys_clk_cnt_rst <= RST or sys_clk_cnt_max;
 
     sys_clk_cnt_reg_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
-            if (sys_clk_cnt_rst = '1') then
+            if (RST = '1' or sys_clk_cnt_max = '1') then
                 sys_clk_cnt <= (others => '0');
             else
                 sys_clk_cnt <= sys_clk_cnt + 1;
@@ -120,7 +118,7 @@ begin
     spi_clk_gen_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
-            if (RST = '1' or spi_clk_en = '0') then
+            if (RST = '1' or spi_clk_rst = '1') then
                 spi_clk <= '0';
             elsif (sys_clk_cnt_max = '1') then
                 spi_clk <= not spi_clk;
@@ -135,12 +133,11 @@ begin
     -- -------------------------------------------------------------------------
 
     bit_cnt_max <= '1' when (bit_cnt = WORD_SIZE-1) else '0';
-    bit_cnt_rst <= RST or not spi_clk_en;
 
     bit_cnt_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
-            if (bit_cnt_rst = '1') then
+            if (RST = '1' or spi_clk_rst = '1') then
                 bit_cnt <= (others => '0');
             elsif (second_edge_en = '1') then
                 bit_cnt <= bit_cnt + 1;
@@ -158,15 +155,15 @@ begin
             if (RST = '1') then
                 addr_reg <= (others => '0');
             elsif (load_data = '1') then
-                addr_reg <= DIN_ADDR;
+                addr_reg <= unsigned(DIN_ADDR);
             end if;
         end if;
     end process;
 
     cs_n_g : for i in 0 to SLAVE_COUNT-1 generate
         cs_n_p : process (addr_reg, chip_select_n)
         begin
-            if (to_integer(unsigned(addr_reg)) = i) then
+            if (addr_reg = i) then
                 CS_N(i) <= chip_select_n;
             else
                 CS_N(i) <= '1';
@@ -307,47 +304,47 @@ begin
             when idle =>
                 master_ready   <= '1';
                 chip_select_n  <= not din_last_reg_n;
-                spi_clk_en     <= '0';
+                spi_clk_rst    <= '1';
                 first_edge_en  <= '0';
                 second_edge_en <= '0';
                 rx_data_vld    <= '0';
 
             when first_edge =>
                 master_ready   <= '0';
                 chip_select_n  <= '0';
-                spi_clk_en     <= '1';
+                spi_clk_rst    <= '0';
                 first_edge_en  <= sys_clk_cnt_max;
                 second_edge_en <= '0';
                 rx_data_vld    <= '0';
 
             when second_edge =>
                 master_ready   <= '0';
                 chip_select_n  <= '0';
-                spi_clk_en     <= '1';
+                spi_clk_rst    <= '0';
                 first_edge_en  <= '0';
                 second_edge_en <= sys_clk_cnt_max;
                 rx_data_vld    <= '0';
 
             when transmit_end =>
                 master_ready   <= '0';
                 chip_select_n  <= '0';
-                spi_clk_en     <= '0';
+                spi_clk_rst    <= '1';
                 first_edge_en  <= '0';
                 second_edge_en <= '0';
                 rx_data_vld    <= sys_clk_cnt_max;
 
             when transmit_gap =>
                 master_ready   <= '0';
                 chip_select_n  <= not din_last_reg_n;
-                spi_clk_en     <= '0';
+                spi_clk_rst    <= '1';
                 first_edge_en  <= '0';
                 second_edge_en <= '0';
                 rx_data_vld    <= '0';
 
             when others =>
                 master_ready   <= '0';
-                chip_select_n  <= '1';
-                spi_clk_en     <= '0';
+                chip_select_n  <= not din_last_reg_n;
+                spi_clk_rst    <= '1';
                 first_edge_en  <= '0';
                 second_edge_en <= '0';
                 rx_data_vld    <= '0';