SPI MASTER [MAINTENANCE]: Improve ports comments

Author: jakubcabal

rtl/spi_master.vhd

@@ -48,14 +48,14 @@ entity SPI_MASTER is
         MOSI     : out std_logic; -- SPI serial data from master to slave
         MISO     : in  std_logic; -- SPI serial data from slave to master
         -- INPUT USER INTERFACE
+        DIN      : in  std_logic_vector(WORD_SIZE-1 downto 0); -- data for transmission to SPI slave
         DIN_ADDR : in  std_logic_vector(natural(ceil(log2(real(SLAVE_COUNT))))-1 downto 0); -- SPI slave address
-        DIN      : in  std_logic_vector(WORD_SIZE-1 downto 0); -- input data for SPI slave
-        DIN_LAST : in  std_logic; -- when DIN_LAST = 1, after transmit these input data is asserted CS_N
-        DIN_VLD  : in  std_logic; -- when DIN_VLD = 1, input data are valid
-        DIN_RDY  : out std_logic; -- when DIN_RDY = 1, valid input data are accept
+        DIN_LAST : in  std_logic; -- when DIN_LAST = 1, last data word, after transmit will be asserted CS_N
+        DIN_VLD  : in  std_logic; -- when DIN_VLD = 1, data for transmission are valid
+        DIN_RDY  : out std_logic; -- when DIN_RDY = 1, SPI master is ready to accept valid data for transmission
         -- OUTPUT USER INTERFACE
-        DOUT     : out std_logic_vector(WORD_SIZE-1 downto 0); -- output data from SPI slave
-        DOUT_VLD : out std_logic  -- when DOUT_VLD = 1, output data are valid
+        DOUT     : out std_logic_vector(WORD_SIZE-1 downto 0); -- received data from SPI slave
+        DOUT_VLD : out std_logic  -- when DOUT_VLD = 1, received data are valid
     );
 end entity;