From 955dcbae1e8d7c5b4dd2aed9cf42b136a3419074 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jose=20=C3=81ngel=20Gumiel?= Date: Fri, 17 Jul 2020 18:15:29 +0200 Subject: [PATCH] ADC-UART: Voltimeter --- .../ADC-UART.cydsn/ADC-UART.cycdx | 736 + .../ADC-UART.cydsn/ADC-UART.cydwr | 1670 ++ .../ADC-UART.cydsn/ADC-UART.cyfit | Bin 0 -> 134062 bytes .../ADC-UART.cydsn/ADC-UART.cyprj | 2411 ++ .../ADC-UART.cydsn/ADC-UART.cyprj.jagumiel | 860 + TrainingProjects/ADC-UART.cydsn/ADC-UART.rpt | 830 + TrainingProjects/ADC-UART.cydsn/ADC-UART.svd | 4030 ++++ .../ADC-UART.cydsn/ADC-UART_timing.html | 672 + .../Debug/.deps/SOURCE_ASM__ARM_GCC_GENERIC.P | 8 + .../Debug/.deps/SOURCE_C__ARM_GCC_GENERIC.P | 84 + .../ARM_GCC_541/Debug/ADC-UART.a | Bin 0 -> 474168 bytes .../ARM_GCC_541/Debug/ADC-UART.elf | Bin 0 -> 336844 bytes .../ARM_GCC_541/Debug/ADC-UART.hex | 521 + .../ARM_GCC_541/Debug/ADC-UART.map | 1019 + .../ADC-UART.cydsn/ARM_GCC_541/Debug/ADC.lst | 3634 +++ .../ADC-UART.cydsn/ARM_GCC_541/Debug/ADC.o | Bin 0 -> 12380 bytes .../ARM_GCC_541/Debug/ADC_INT.lst | 503 + .../ARM_GCC_541/Debug/ADC_INT.o | Bin 0 -> 2880 bytes .../ARM_GCC_541/Debug/ADC_IRQ.lst | 1957 ++ .../ARM_GCC_541/Debug/ADC_IRQ.o | Bin 0 -> 8076 bytes .../ARM_GCC_541/Debug/ADC_PM.lst | 965 + .../ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_PM.o | Bin 0 -> 4484 bytes .../ARM_GCC_541/Debug/ADC_intClock.lst | 990 + .../ARM_GCC_541/Debug/ADC_intClock.o | Bin 0 -> 4616 bytes .../ARM_GCC_541/Debug/Cm0Start.lst | 2181 ++ .../ARM_GCC_541/Debug/Cm0Start.o | Bin 0 -> 7676 bytes .../ARM_GCC_541/Debug/CyBootAsmGnu.lst | 7505 ++++++ .../ARM_GCC_541/Debug/CyBootAsmGnu.o | Bin 0 -> 296016 bytes .../ARM_GCC_541/Debug/CyFlash.lst | 2596 +++ .../ARM_GCC_541/Debug/CyFlash.o | Bin 0 -> 6636 bytes .../ARM_GCC_541/Debug/CyLFClk.lst | 8505 +++++++ .../ARM_GCC_541/Debug/CyLFClk.o | Bin 0 -> 23108 bytes .../ARM_GCC_541/Debug/CyLib.lst | 8494 +++++++ .../ADC-UART.cydsn/ARM_GCC_541/Debug/CyLib.o | Bin 0 -> 24068 bytes .../ARM_GCC_541/Debug/Input_1.lst | 1193 + .../ARM_GCC_541/Debug/Input_1.o | Bin 0 -> 5016 bytes .../ARM_GCC_541/Debug/Input_1_PM.lst | 664 + .../ARM_GCC_541/Debug/Input_1_PM.o | Bin 0 -> 3528 bytes .../ADC-UART.cydsn/ARM_GCC_541/Debug/LED.lst | 1190 + .../ADC-UART.cydsn/ARM_GCC_541/Debug/LED.o | Bin 0 -> 4932 bytes .../ARM_GCC_541/Debug/LED_PM.lst | 658 + .../ADC-UART.cydsn/ARM_GCC_541/Debug/LED_PM.o | Bin 0 -> 3476 bytes .../ARM_GCC_541/Debug/LINK_options.txt | 1 + ...PSoC4_ADC_with_Differential_PreAmplifier.a | Bin 0 -> 475928 bytes ...oC4_ADC_with_Differential_PreAmplifier.elf | Bin 0 -> 338232 bytes ...oC4_ADC_with_Differential_PreAmplifier.hex | 521 + ...oC4_ADC_with_Differential_PreAmplifier.map | 1032 + .../Debug/SOURCE_ASM__ARM_GCC_GENERIC.txt | 1 + .../Debug/SOURCE_C__ARM_GCC_GENERIC.txt | 1 + .../ADC-UART.cydsn/ARM_GCC_541/Debug/UART.lst | 2062 ++ .../ADC-UART.cydsn/ARM_GCC_541/Debug/UART.o | Bin 0 -> 6824 bytes .../ARM_GCC_541/Debug/UART_BOOT.lst | 260 + .../ARM_GCC_541/Debug/UART_BOOT.o | Bin 0 -> 2032 bytes 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.../Generated_Source/PSoC4/UART.c | 818 + .../Generated_Source/PSoC4/UART.h | 2126 ++ .../Generated_Source/PSoC4/UART_BOOT.c | 236 + .../Generated_Source/PSoC4/UART_BOOT.h | 230 + .../Generated_Source/PSoC4/UART_PINS.h | 755 + .../Generated_Source/PSoC4/UART_PM.c | 223 + .../Generated_Source/PSoC4/UART_PVT.h | 123 + .../Generated_Source/PSoC4/UART_SCBCLK.c | 210 + .../Generated_Source/PSoC4/UART_SCBCLK.h | 91 + .../Generated_Source/PSoC4/UART_SPI_UART.c | 603 + .../Generated_Source/PSoC4/UART_SPI_UART.h | 1231 + .../PSoC4/UART_SPI_UART_INT.c | 158 + .../PSoC4/UART_SPI_UART_PVT.h | 117 + .../Generated_Source/PSoC4/UART_UART.c | 905 + .../Generated_Source/PSoC4/UART_UART_BOOT.c | 189 + .../Generated_Source/PSoC4/UART_tx.c | 244 + .../Generated_Source/PSoC4/UART_tx.h | 188 + .../Generated_Source/PSoC4/UART_tx_PM.c | 100 + .../Generated_Source/PSoC4/UART_tx_aliases.h | 42 + .../Generated_Source/PSoC4/cm0gcc.ld | 475 + .../Generated_Source/PSoC4/cmsis_armcc.h | 791 + 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.../ADC-UART.cydsn/codegentemp/ADC-UART_t.lib | 533 + .../ADC-UART.cydsn/codegentemp/ADC-UART_t.vh2 | 669 + .../codegentemp/ADC-UART_timing.html | 672 + .../ADC-UART.cydsn/codegentemp/ADC-UART_u.sdc | 3 + .../ADC-UART.cydsn/codegentemp/ADC.c | 881 + .../ADC-UART.cydsn/codegentemp/ADC.h | 713 + .../ADC-UART.cydsn/codegentemp/ADC_INT.c | 78 + .../ADC-UART.cydsn/codegentemp/ADC_IRQ.c | 406 + .../ADC-UART.cydsn/codegentemp/ADC_IRQ.h | 71 + .../ADC-UART.cydsn/codegentemp/ADC_PM.c | 158 + .../ADC-UART.cydsn/codegentemp/ADC_intClock.c | 210 + .../ADC-UART.cydsn/codegentemp/ADC_intClock.h | 91 + .../ADC-UART.cydsn/codegentemp/Cm0Iar.icf | 226 + .../codegentemp/Cm0RealView.scat | 245 + .../ADC-UART.cydsn/codegentemp/Cm0Start.c | 545 + .../ADC-UART.cydsn/codegentemp/CyBootAsmGnu.s | 140 + .../ADC-UART.cydsn/codegentemp/CyBootAsmIar.s | 132 + .../ADC-UART.cydsn/codegentemp/CyBootAsmRv.s | 136 + .../ADC-UART.cydsn/codegentemp/CyFlash.c | 803 + .../ADC-UART.cydsn/codegentemp/CyFlash.h | 293 + .../ADC-UART.cydsn/codegentemp/CyLFClk.c | 3230 +++ .../ADC-UART.cydsn/codegentemp/CyLFClk.h | 724 + .../ADC-UART.cydsn/codegentemp/CyLib.c | 3504 +++ .../ADC-UART.cydsn/codegentemp/CyLib.h | 1576 ++ .../ADC-UART.cydsn/codegentemp/Input_1.c | 244 + .../ADC-UART.cydsn/codegentemp/Input_1.h | 188 + .../ADC-UART.cydsn/codegentemp/Input_1_PM.c | 100 + .../codegentemp/Input_1_aliases.h | 42 + .../ADC-UART.cydsn/codegentemp/LED.c | 244 + .../ADC-UART.cydsn/codegentemp/LED.h | 188 + .../ADC-UART.cydsn/codegentemp/LED_PM.c | 100 + .../ADC-UART.cydsn/codegentemp/LED_aliases.h | 42 + .../ADC-UART.cydsn/codegentemp/UART.c | 818 + .../ADC-UART.cydsn/codegentemp/UART.h | 2126 ++ .../ADC-UART.cydsn/codegentemp/UART_BOOT.c | 236 + .../ADC-UART.cydsn/codegentemp/UART_BOOT.h | 230 + .../ADC-UART.cydsn/codegentemp/UART_PINS.h | 755 + .../ADC-UART.cydsn/codegentemp/UART_PM.c | 223 + .../ADC-UART.cydsn/codegentemp/UART_PVT.h | 123 + .../ADC-UART.cydsn/codegentemp/UART_SCBCLK.c | 210 + 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.../ADC-UART.cydsn/codegentemp/cyPm.h | 302 + .../ADC-UART.cydsn/codegentemp/cy_em_eeprom.c | 1416 ++ .../ADC-UART.cydsn/codegentemp/cy_em_eeprom.h | 556 + .../codegentemp/cycodeshareexport.ld | 0 .../codegentemp/cycodeshareimport.ld | 0 .../codegentemp/cycodeshareimport.scat | 0 .../ADC-UART.cydsn/codegentemp/cydevice_trm.h | 6497 ++++++ .../codegentemp/cydevicegnu_trm.inc | 6494 ++++++ .../codegentemp/cydeviceiar_trm.inc | 6493 ++++++ .../codegentemp/cydevicerv_trm.inc | 19450 ++++++++++++++++ .../codegentemp/cydisabledsheets.h | 5 + .../ADC-UART.cydsn/codegentemp/cyfitter.h | 502 + .../ADC-UART.cydsn/codegentemp/cyfitter_cfg.c | 315 + .../ADC-UART.cydsn/codegentemp/cyfitter_cfg.h | 29 + .../codegentemp/cyfittergnu.inc | 496 + .../codegentemp/cyfitteriar.inc | 496 + .../ADC-UART.cydsn/codegentemp/cyfitterrv.inc | 496 + .../ADC-UART.cydsn/codegentemp/cymetadata.c | 65 + .../ADC-UART.cydsn/codegentemp/cypins.h | 324 + .../ADC-UART.cydsn/codegentemp/cytypes.h | 1496 ++ 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+${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\Cm0Start.c +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cm0.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cm0_psoc4.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyBootAsmRv.s +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyFlash.c +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyFlash.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyLib.c +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyLib.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cyPm.c +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cyPm.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cytypes.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cyutils.c +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cypins.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cmFunc.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cmInstr.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\Cm0Iar.icf +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyBootAsmIar.s +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cmsis_armcc.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cmsis_gcc.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cm0plus.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cm0plus_psoc4.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cmsis_compiler.h +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyBootAsmGnu.s +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_lfclk_v1_20\PSoC4\API\CyLFClk.c +${CyRoot}\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_lfclk_v1_20\PSoC4\API\CyLFClk.h + + +Generated_Source\PSoC4\cyfitter_cfg.h +Generated_Source\PSoC4\cyfitter_cfg.c +Generated_Source\PSoC4\cymetadata.c +Generated_Source\PSoC4\cydevice_trm.h +Generated_Source\PSoC4\cydevicegnu_trm.inc +Generated_Source\PSoC4\cydevicerv_trm.inc +Generated_Source\PSoC4\cydeviceiar_trm.inc +Generated_Source\PSoC4\cyfittergnu.inc +Generated_Source\PSoC4\cyfitterrv.inc +Generated_Source\PSoC4\cyfitteriar.inc +Generated_Source\PSoC4\cyfitter.h +Generated_Source\PSoC4\cydisabledsheets.h +Generated_Source\PSoC4\LED.c +Generated_Source\PSoC4\LED.h +Generated_Source\PSoC4\LED_aliases.h +Generated_Source\PSoC4\LED_PM.c +Generated_Source\PSoC4\UART.c +Generated_Source\PSoC4\UART.h +Generated_Source\PSoC4\UART_SPI_UART.h +Generated_Source\PSoC4\UART_SPI_UART.c +Generated_Source\PSoC4\UART_SPI_UART_INT.c +Generated_Source\PSoC4\UART_PM.c +Generated_Source\PSoC4\UART_UART.c +Generated_Source\PSoC4\UART_BOOT.c +Generated_Source\PSoC4\UART_UART_BOOT.c +Generated_Source\PSoC4\UART_PINS.h +Generated_Source\PSoC4\UART_SPI_UART_PVT.h +Generated_Source\PSoC4\UART_PVT.h +Generated_Source\PSoC4\UART_BOOT.h +Generated_Source\PSoC4\Input_1.c +Generated_Source\PSoC4\Input_1.h +Generated_Source\PSoC4\Input_1_aliases.h +Generated_Source\PSoC4\Input_1_PM.c +Generated_Source\PSoC4\ADC.c +Generated_Source\PSoC4\ADC.h +Generated_Source\PSoC4\ADC_PM.c +Generated_Source\PSoC4\ADC_INT.c +Generated_Source\PSoC4\UART_SCBCLK.c +Generated_Source\PSoC4\UART_SCBCLK.h +Generated_Source\PSoC4\UART_tx.c +Generated_Source\PSoC4\UART_tx.h +Generated_Source\PSoC4\UART_tx_aliases.h +Generated_Source\PSoC4\UART_tx_PM.c +Generated_Source\PSoC4\ADC_IRQ.c +Generated_Source\PSoC4\ADC_IRQ.h +Generated_Source\PSoC4\ADC_intClock.c +Generated_Source\PSoC4\ADC_intClock.h +Generated_Source\PSoC4\cy_em_eeprom.c +Generated_Source\PSoC4\cy_em_eeprom.h +Generated_Source\PSoC4\cm0gcc.ld +Generated_Source\PSoC4\Cm0RealView.scat +Generated_Source\PSoC4\Cm0Start.c +Generated_Source\PSoC4\core_cm0.h +Generated_Source\PSoC4\core_cm0_psoc4.h +Generated_Source\PSoC4\CyBootAsmRv.s +Generated_Source\PSoC4\CyFlash.c +Generated_Source\PSoC4\CyFlash.h +Generated_Source\PSoC4\CyLib.c +Generated_Source\PSoC4\CyLib.h +Generated_Source\PSoC4\cyPm.c +Generated_Source\PSoC4\cyPm.h +Generated_Source\PSoC4\cytypes.h +Generated_Source\PSoC4\cyutils.c +Generated_Source\PSoC4\cypins.h +Generated_Source\PSoC4\core_cmFunc.h +Generated_Source\PSoC4\core_cmInstr.h +Generated_Source\PSoC4\Cm0Iar.icf +Generated_Source\PSoC4\CyBootAsmIar.s +Generated_Source\PSoC4\cmsis_armcc.h +Generated_Source\PSoC4\cmsis_gcc.h +Generated_Source\PSoC4\cmsis_compiler.h +Generated_Source\PSoC4\CyBootAsmGnu.s +Generated_Source\PSoC4\CyLFClk.c +Generated_Source\PSoC4\CyLFClk.h +Generated_Source\PSoC4\project.h +Generated_Source\PSoC4\cycodeshareimport.ld +Generated_Source\PSoC4\cycodeshareexport.ld +Generated_Source\PSoC4\cycodeshareimport.scat + + +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/ADC-UART.rpt b/TrainingProjects/ADC-UART.cydsn/ADC-UART.rpt new file mode 100644 index 0000000..6565bf3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ADC-UART.rpt @@ -0,0 +1,830 @@ +Loading plugins phase: Elapsed time ==> 0s.198ms + +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -d CY8C4245AXI-483 -s D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE + + + +Elaboration phase: Elapsed time ==> 1s.872ms + + +HDL generation phase: Elapsed time ==> 0s.056ms + + + | | | | | | | + _________________ + -| |- + -| |- + -| |- + -| CYPRESS |- + -| |- + -| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41 + -| |- Copyright (C) 1991-2001 Cypress Semiconductor + |_______________| + | | | | | | | + +====================================================================== +Compiling: ADC-UART.v +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 ADC-UART.v -verilog +====================================================================== + +====================================================================== +Compiling: ADC-UART.v +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 ADC-UART.v -verilog +====================================================================== + +====================================================================== +Compiling: ADC-UART.v +Program : vlogfe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 -verilog ADC-UART.v +====================================================================== + +vlogfe V6.3 IR 41: Verilog parser +Fri Jul 17 10:59:50 2020 + + +====================================================================== +Compiling: ADC-UART.v +Program : vpp +Options : -yv2 -q10 ADC-UART.v +====================================================================== + +vpp V6.3 IR 41: Verilog Pre-Processor +Fri Jul 17 10:59:50 2020 + +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v' + +vpp: No errors. + +Library 'work' => directory 'lcpsoc3' +General_symbol_table +General_symbol_table +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Using control file 'ADC-UART.ctl'. + +vlogfe: No errors. + + +====================================================================== +Compiling: ADC-UART.v +Program : tovif +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 -verilog ADC-UART.v +====================================================================== + +tovif V6.3 IR 41: High-level synthesis +Fri Jul 17 10:59:51 2020 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'. + +tovif: No errors. + + +====================================================================== +Compiling: ADC-UART.v +Program : topld +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 -verilog ADC-UART.v +====================================================================== + +topld V6.3 IR 41: Synthesis and optimization +Fri Jul 17 10:59:51 2020 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. + +---------------------------------------------------------- +Detecting unused logic. +---------------------------------------------------------- + User names + \UART:Net_1257\ + \UART:uncfg_rx_irq\ + \UART:Net_1099\ + \UART:Net_1258\ + Net_647 + Net_656 + Net_657 + Net_658 + Net_659 + Net_660 + Net_661 + Net_662 + Net_646 + Net_674 + \ADC:Net_3125\ + \ADC:Net_3126\ + + +Deleted 16 User equations/components. +Deleted 0 Synthesized equations/components. + +------------------------------------------------------ +Alias Detection +------------------------------------------------------ +Aliasing one to tmpOE__LED_net_0 +Aliasing \UART:select_s_wire\ to zero +Aliasing \UART:rx_wire\ to zero +Aliasing \UART:sclk_s_wire\ to zero +Aliasing \UART:mosi_s_wire\ to zero +Aliasing \UART:miso_m_wire\ to zero +Aliasing \UART:tmpOE__tx_net_0\ to tmpOE__LED_net_0 +Aliasing \UART:cts_wire\ to zero +Aliasing tmpOE__Input_1_net_0 to tmpOE__LED_net_0 +Aliasing \ADC:Net_3107\ to zero +Aliasing \ADC:Net_3106\ to zero +Aliasing \ADC:Net_3105\ to zero +Aliasing \ADC:Net_3104\ to zero +Aliasing \ADC:Net_3103\ to zero +Aliasing \ADC:Net_3207_1\ to zero +Aliasing \ADC:Net_3207_0\ to zero +Aliasing \ADC:Net_3235\ to zero +Removing Lhs of wire one[7] = tmpOE__LED_net_0[1] +Removing Lhs of wire \UART:select_s_wire\[11] = zero[2] +Removing Lhs of wire \UART:rx_wire\[12] = zero[2] +Removing Lhs of wire \UART:Net_1170\[15] = \UART:Net_847\[10] +Removing Lhs of wire \UART:sclk_s_wire\[16] = zero[2] +Removing Lhs of wire \UART:mosi_s_wire\[17] = zero[2] +Removing Lhs of wire \UART:miso_m_wire\[18] = zero[2] +Removing Lhs of wire \UART:tmpOE__tx_net_0\[20] = tmpOE__LED_net_0[1] +Removing Lhs of wire \UART:cts_wire\[28] = zero[2] +Removing Lhs of wire tmpOE__Input_1_net_0[59] = tmpOE__LED_net_0[1] +Removing Lhs of wire \ADC:Net_3107\[137] = zero[2] +Removing Lhs of wire \ADC:Net_3106\[138] = zero[2] +Removing Lhs of wire \ADC:Net_3105\[139] = zero[2] +Removing Lhs of wire \ADC:Net_3104\[140] = zero[2] +Removing Lhs of wire \ADC:Net_3103\[141] = zero[2] +Removing Lhs of wire \ADC:Net_17\[183] = \ADC:Net_1845\[68] +Removing Lhs of wire \ADC:Net_3207_1\[205] = zero[2] +Removing Lhs of wire \ADC:Net_3207_0\[206] = zero[2] +Removing Lhs of wire \ADC:Net_3235\[207] = zero[2] + +------------------------------------------------------ +Aliased 0 equations, 19 wires. +------------------------------------------------------ + +---------------------------------------------------------- +Circuit simplification +---------------------------------------------------------- + +Substituting virtuals - pass 1: + + +---------------------------------------------------------- +Circuit simplification results: + + Expanded 0 signals. + Turned 0 signals into soft nodes. + Maximum default expansion cost was set at 3. +---------------------------------------------------------- + +topld: No errors. + +CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp +Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya "-.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj" -dcpsoc3 ADC-UART.v -verilog + +Warp synthesis phase: Elapsed time ==> 2s.101ms + + +cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Friday, 17 July 2020 10:59:51 +Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -d CY8C4245AXI-483 ADC-UART.v -verilog + + +Design parsing phase: Elapsed time ==> 0s.009ms + + + +Info: mpr.M0053: Information from the design wide resources Pin Editor has overridden the control file entry for "\UART:tx(0)\". (App=cydsfit) + + Fixed Function Clock 7: Automatic-assigning clock 'ADC_intClock'. Signal=\ADC:Net_1845_ff7\ + Fixed Function Clock 2: Automatic-assigning clock 'UART_SCBCLK'. Signal=\UART:Net_847_ff2\ + + + +ADD: pft.M0040: information: The following 1 pin(s) will be assigned a location by the fitter: Input_1(0) + + +Removing unused cells resulting from optimization +Done removing unused cells. + + + + + + + +------------------------------------------------------------ +Design Equations +------------------------------------------------------------ + + + ------------------------------------------------------------ + Pin listing + ------------------------------------------------------------ + + Pin : Name = LED(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: OPEN_DRAIN_LO + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(0)__PA , + annotation => Net_644 , + pad => LED(0)_PAD ); + Properties: + { + port_location = "PORT(1,6)" + } + + Pin : Name = \UART:tx(0)\ + Attributes: + In Group/Port: True + In Sync Option: NOSYNC + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: CMOS + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => \UART:tx(0)\__PA , + pin_input => \UART:tx_wire\ , + pad => \UART:tx(0)_PAD\ ); + Properties: + { + port_location = "PORT(0,5)" + } + + Pin : Name = Input_1(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: HI_Z_ANALOG + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: True + Can contain Digital: False + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: ANALOG + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Input_1(0)__PA , + analog_term => Net_563 , + pad => Input_1(0)_PAD ); + + + + + + + + + + + + + + + + + + + + ------------------------------------------------------------ + Interrupt listing + ------------------------------------------------------------ + + interrupt: Name =\ADC:IRQ\ + PORT MAP ( + interrupt => \ADC:Net_3112\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + + + +------------------------------------------------------------ +Technology mapping summary +------------------------------------------------------------ + +Resource Type : Used : Free : Max : % Used +============================================================ +Digital Clocks : 0 : 4 : 4 : 0.00 % +Interrupts : 1 : 31 : 32 : 3.13 % +IO : 5 : 31 : 36 : 13.89 % +Segment LCD : 0 : 1 : 1 : 0.00 % +CapSense : 0 : 1 : 1 : 0.00 % +Die Temp : 0 : 1 : 1 : 0.00 % +Serial Communication (SCB) : 1 : 1 : 2 : 50.00 % +Timer/Counter/PWM : 0 : 4 : 4 : 0.00 % +UDB : : : : + Macrocells : 0 : 32 : 32 : 0.00 % + Unique P-terms : 0 : 64 : 64 : 0.00 % + Total P-terms : 0 : : : + Datapath Cells : 0 : 4 : 4 : 0.00 % + Status Cells : 0 : 4 : 4 : 0.00 % + Control Cells : 0 : 4 : 4 : 0.00 % +Comparator/Opamp : 0 : 2 : 2 : 0.00 % +LP Comparator : 0 : 2 : 2 : 0.00 % +SAR ADC : 1 : 0 : 1 : 100.00 % +DAC : : : : + 7-bit IDAC : 0 : 1 : 1 : 0.00 % + 8-bit IDAC : 0 : 1 : 1 : 0.00 % + +Technology Mapping: Elapsed time ==> 0s.011ms +Tech Mapping phase: Elapsed time ==> 0s.032ms + + + + + +Cell : Block +========================================================================= +LED(0) : [IOP=(1)][IoId=(6)] +\UART:tx(0)\ : [IOP=(4)][IoId=(1)] +ClockGenBlock : CLK_GEN_[FFB(CLK_GEN,0)] +\UART:SCB\ : SCB_[FFB(SCB,0)] +\ADC:cy_psoc4_sar\ : SARADC_[FFB(SARADC,0)] +Input_1(0) : [IOP=(2)][IoId=(0)] + + + + +Elapsed time ==> 0.1269260s + +Analog Placement phase: Elapsed time ==> 0s.262ms + + + +Route success=True, Iterations=1 Elapsed=0.0020510 secs + +Analog Routing phase: Elapsed time ==> 0s.002ms + + +============ Analog Final Answer Routes ============ +Dump of CyAnalogRoutingResultsDB +Map of net to items { + Net: Net_563 { + sarmux_vplus + SARMUX0_sw3 + p2_3 + } + Net: \ADC:Net_3113\ { + } + Net: \ADC:mux_bus_minus_0\ { + } + Net: \ADC:mux_bus_minus_1\ { + } + Net: \ADC:mux_bus_plus_1\ { + } +} +Map of item to net { + sarmux_vplus -> Net_563 + SARMUX0_sw3 -> Net_563 + p2_3 -> Net_563 +} +Mux Info { +} +Analog Code Generation phase: Elapsed time ==> 0s.018ms + + + +I2659: No Constrained paths were found. The placer will run in non-timing driven mode. +I2076: Total run-time: 0.2 sec. + + + + +No PLDs were packed. + +PLD Packing: Elapsed time ==> 0s.000ms + + + +Initial Partitioning Summary not displayed at this verbose level. + +Final Partitioning Summary not displayed at this verbose level. +Partitioning: Elapsed time ==> 0s.007ms + + + +------------------------------------------------------------ +Final Placement Summary +------------------------------------------------------------ + + Resource Type : Count : Avg Inputs : Avg Outputs + ======================================================== + UDB : 0 : 0.00 : 0.00 + + + +------------------------------------------------------------ +Component Placement Details +------------------------------------------------------------ +UDB [UDB=(0,0)] is empty. +UDB [UDB=(0,1)] is empty. +UDB [UDB=(1,0)] is empty. +UDB [UDB=(1,1)] is empty. +Intr container @ [IntrContainer=(0)]: + Intr@ [IntrContainer=(0)][IntrId=(14)] + interrupt: Name =\ADC:IRQ\ + PORT MAP ( + interrupt => \ADC:Net_3112\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } +Port 0 contains the following IO cells: +Port 1 contains the following IO cells: +[IoId=6]: +Pin : Name = LED(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: OPEN_DRAIN_LO + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(0)__PA , + annotation => Net_644 , + pad => LED(0)_PAD ); + Properties: + { + port_location = "PORT(1,6)" + } + +Port 2 contains the following IO cells: +[IoId=3]: +Pin : Name = Input_1(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: HI_Z_ANALOG + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: True + Can contain Digital: False + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: ANALOG + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Input_1(0)__PA , + analog_term => Net_563 , + pad => Input_1(0)_PAD ); + Properties: + { + } + +Port 3 contains the following IO cells: +Port 4 contains the following IO cells: +[IoId=1]: +Pin : Name = \UART:tx(0)\ + Attributes: + In Group/Port: True + In Sync Option: NOSYNC + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: CMOS + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => \UART:tx(0)\__PA , + pin_input => \UART:tx_wire\ , + pad => \UART:tx(0)_PAD\ ); + Properties: + { + port_location = "PORT(0,5)" + } + +ARM group 0: empty +Clock group 0: + Clock Block @ F(Clock,0): + m0s8clockblockcell: Name =ClockBlock + PORT MAP ( + hfclk => ClockBlock_HFCLK , + imo => ClockBlock_IMO , + ext => ClockBlock_EXTCLK , + sysclk => ClockBlock_SYSCLK , + ilo => ClockBlock_ILO , + lfclk => ClockBlock_LFCLK , + dsi_in_0 => ClockBlock_Routed1 , + ff_div_7 => \ADC:Net_1845_ff7\ , + ff_div_2 => \UART:Net_847_ff2\ ); + Properties: + { + } +LCD group 0: empty +PICU group 0: empty +LPCOMP group 0: empty +SCB group 0: + SCB Block @ F(SCB,0): + m0s8scbcell: Name =\UART:SCB\ + PORT MAP ( + clock => \UART:Net_847_ff2\ , + interrupt => Net_648 , + uart_tx => \UART:tx_wire\ , + uart_rts => \UART:rts_wire\ , + mosi_m => \UART:mosi_m_wire\ , + select_m_3 => \UART:select_m_wire_3\ , + select_m_2 => \UART:select_m_wire_2\ , + select_m_1 => \UART:select_m_wire_1\ , + select_m_0 => \UART:select_m_wire_0\ , + sclk_m => \UART:sclk_m_wire\ , + miso_s => \UART:miso_s_wire\ , + tr_tx_req => Net_671 , + tr_rx_req => Net_670 ); + Properties: + { + cy_registers = "" + scb_mode = 2 + } +CSD group 0: empty +CSIDAC8 group 0: empty +CSIDAC7 group 0: empty +TCPWM group 0: empty +OA group 0: empty +TEMP group 0: empty +SARADC group 0: + SAR ADC @ F(SARADC,0): + p4sarcell: Name =\ADC:cy_psoc4_sar\ + PORT MAP ( + vplus => Net_563 , + vminus => \ADC:mux_bus_minus_0\ , + vref => \ADC:Net_3113\ , + ext_vref => \ADC:Net_3225\ , + clock => \ADC:Net_1845_ff7\ , + sample_done => Net_666 , + chan_id_valid => \ADC:Net_3108\ , + chan_id_3 => \ADC:Net_3109_3\ , + chan_id_2 => \ADC:Net_3109_2\ , + chan_id_1 => \ADC:Net_3109_1\ , + chan_id_0 => \ADC:Net_3109_0\ , + data_valid => \ADC:Net_3110\ , + data_11 => \ADC:Net_3111_11\ , + data_10 => \ADC:Net_3111_10\ , + data_9 => \ADC:Net_3111_9\ , + data_8 => \ADC:Net_3111_8\ , + data_7 => \ADC:Net_3111_7\ , + data_6 => \ADC:Net_3111_6\ , + data_5 => \ADC:Net_3111_5\ , + data_4 => \ADC:Net_3111_4\ , + data_3 => \ADC:Net_3111_3\ , + data_2 => \ADC:Net_3111_2\ , + data_1 => \ADC:Net_3111_1\ , + data_0 => \ADC:Net_3111_0\ , + eos_intr => Net_667 , + irq => \ADC:Net_3112\ ); + Properties: + { + cy_registers = "" + } +CLK_GEN group 0: + M0S8 Clock Gen Block @ F(CLK_GEN,0): + m0s8clockgenblockcell: Name =ClockGenBlock + PORT MAP ( + ); + Properties: + { + } +LPCOMPBLOCK group 0: empty +PASSBLOCK group 0: empty +WCO group 0: empty +SRSS group 0: empty +CPUSS group 0: empty +EXCO group 0: empty + + + +------------------------------------------------------------ +Port Configuration report +------------------------------------------------------------ + | | | Interrupt | | | +Port | Pin | Fixed | Type | Drive Mode | Name | Connections +-----+-----+-------+-----------+------------------+--------------+------------------- + 1 | 6 | * | NONE | OPEN_DRAIN_LO | LED(0) | +-----+-----+-------+-----------+------------------+--------------+------------------- + 2 | 3 | | NONE | HI_Z_ANALOG | Input_1(0) | Analog(Net_563) +-----+-----+-------+-----------+------------------+--------------+------------------- + 4 | 1 | * | NONE | CMOS_OUT | \UART:tx(0)\ | In(\UART:tx_wire\) +------------------------------------------------------------------------------------- + + + +Digital component placer commit/Report: Elapsed time ==> 0s.005ms +Digital Placement phase: Elapsed time ==> 0s.876ms + + +"C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/route_arch-rrg.cydata" --vh2-path "ADC-UART_r.vh2" --pcf-path "ADC-UART.pco" --des-name "ADC-UART" --dsf-path "ADC-UART.dsf" --sdc-path "ADC-UART.sdc" --lib-path "ADC-UART_r.lib" +Routing successful. +Digital Routing phase: Elapsed time ==> 0s.748ms + + +Bitstream Generation phase: Elapsed time ==> 0s.160ms + + +Bitstream Verification phase: Elapsed time ==> 0s.019ms + + +Timing report is in ADC-UART_timing.html. +Static timing analysis phase: Elapsed time ==> 0s.625ms + + +Data reporting phase: Elapsed time ==> 0s.000ms + + +Design database save phase: Elapsed time ==> 0s.145ms + +cydsfit: Elapsed time ==> 2s.953ms + +Fitter phase: Elapsed time ==> 2s.953ms +API generation phase: Elapsed time ==> 1s.480ms +Dependency generation phase: Elapsed time ==> 0s.028ms +Cleanup phase: Elapsed time ==> 0s.004ms diff --git a/TrainingProjects/ADC-UART.cydsn/ADC-UART.svd b/TrainingProjects/ADC-UART.cydsn/ADC-UART.svd new file mode 100644 index 0000000..c545640 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ADC-UART.svd @@ -0,0 +1,4030 @@ + + + CY8C4245AXI_483 + 0.1 + PSoC 4200 + 8 + 32 + + + ADC + Sequencing SAR ADC + 0x0 + + 0 + 0x0 + registers + + + + CTRL + Analog control register + 0x401A0000 + 32 + read-write + 0 + 0 + + + VREF_SEL + SARADC internal VREF selection + 4 + 6 + read-write + + + VREF_BYP_CAP_EN + VREF bypass cap enable for when VREF buffer is on + 7 + 7 + read-write + + + NEG_SEL + SARADC internal NEG selection for Single ended conversion + 9 + 11 + read-write + + + SAR_HW_CTRL_NEGVREF + Hardware control: 0=firmware, 1=hardware. + 13 + 13 + read-write + + + PWR_CTRL_VREF + VREF buffer low power mode. + 14 + 15 + read-write + + + SPARE + Spare controls + 16 + 19 + read-write + + + ICONT_LV + SARADC low power mode + 24 + 25 + read-write + + + DSI_SYNC_CONFIG + Synchronize the DSI config signals to peripheral clock domain + 28 + 28 + read-write + + + DSI_MODE + SAR sequencer takes configuration from DSI signals + 29 + 29 + read-write + + + SWITCH_DISABLE + Disable SAR sequencer from enabling routing switches + 30 + 30 + read-write + + + ENABLED + 0: SAR IP disabled, 1: SAR IP enabled. + 31 + 31 + read-write + + + + + SAMPLE_CTRL + Sample control register + 0x401A0004 + 32 + read-write + 0 + 0 + + + SUB_RESOLUTION + Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit). + 0 + 0 + read-write + + + LEFT_ALIGN + Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. + 1 + 1 + read-write + + + SINGLE_ENDED_SIGNED + Output data from a single ended conversion as a signed value + 2 + 2 + read-write + + + DIFFERENTIAL_SIGNED + Output data from a differential conversion as a signed value + 3 + 3 + read-write + + + AVG_CNT + Averaging Count for channels that have over sampling enabled + 4 + 6 + read-write + + + AVG_SHIFT + Averaging shifting: after averaging the result is shifted right to fit in the sample resolution, i.e. 12 bits. + 7 + 7 + read-write + + + CONTINUOUS + 0: Wait for next FW_TRIGGER or hardware trigger before scanning enabled channels. 1: Continuously scan enabled channels.. + 16 + 16 + read-write + + + DSI_TRIGGER_EN + 0: firmware trigger only, 1: enable hardware (DSI) trigger. + 17 + 17 + read-write + + + DSI_TRIGGER_LEVEL + 0: DSI trigger signal is a pulse input, 1: DSI trigger signal is a level inpu.t + 18 + 18 + read-write + + + DSI_SYNC_TRIGGER + 0: bypass clock domain synchronisation of the DSI trigger signal, 1: synchronize the DSI trigger signal to the SAR clock domain. + 19 + 19 + read-write + + + EOS_DSI_OUT_EN + Enable to output EOS_INTR to DSI + 31 + 31 + read-write + + + + + SAMPLE_TIME01 + Sample time specification ST0 and ST1 + 0x401A0010 + 32 + read-write + 0 + 0 + + + SAMPLE_TIME0 + Sample time0 (aperture) in ADC clock cycles + 0 + 9 + read-write + + + SAMPLE_TIME1 + Sample time1 + 16 + 25 + read-write + + + + + SAMPLE_TIME23 + Sample time specification ST2 and ST3 + 0x401A0014 + 32 + read-write + 0 + 0 + + + SAMPLE_TIME2 + Sample time2 + 0 + 9 + read-write + + + SAMPLE_TIME3 + Sample time3 + 16 + 25 + read-write + + + + + RANGE_THRES + Global range detect threshold register + 0x401A0018 + 32 + read-write + 0 + 0 + + + RANGE_LOW + Low threshold for range detect + 0 + 15 + read-write + + + RANGE_HIGH + High threshold for range detect + 16 + 31 + read-write + + + + + RANGE_COND + Global range detect mode register + 0x401A001C + 32 + read-write + 0 + 0 + + + RANGE_COND + Range condition select + 30 + 31 + read-write + + + + + CHAN_EN + Enable bits for the channels + 0x401A0020 + 32 + read-write + 0 + 0 + + + CHAN_EN + Channel enable. 0: the corresponding channel is disabled. 1: the corresponding channel is enabled, it will be included in the next scan. + 0 + 15 + read-write + + + + + START_CTRL + Start control register (firmware trigger) + 0x401A0024 + 32 + read-write + 0 + 0 + + + FW_TRIGGER + When firmware writes a 1 here it will trigger the next scan of enabled channels + 0 + 0 + read-write + + + + + DFT_CTRL + DFT control register + 0x401A0030 + 32 + read-write + 0 + 0 + + + CHAN_CONFIG0 + Channel0 configuration register + 0x401A0080 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG1 + Channel1 configuration register + 0x401A0084 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG2 + Channel2 configuration register + 0x401A0088 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG3 + Channel3 configuration register + 0x401A008C + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG4 + Channel4 configuration register + 0x401A0090 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG5 + Channel5 configuration register + 0x401A0094 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG6 + Channel6 configuration register + 0x401A0098 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG7 + Channel7 configuration register + 0x401A009C + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_WORK0 + Channel0 working data register + 0x401A0100 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK1 + Channel1 working data register + 0x401A0104 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK2 + Channel2 working data register + 0x401A0108 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK3 + Channel3 working data register + 0x401A010C + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK4 + Channel4 working data register + 0x401A0110 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK5 + Channel5 working data register + 0x401A0114 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK6 + Channel6 working data register + 0x401A0118 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK7 + Channel7 working data register + 0x401A011C + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_RESULT0 + Channel0 result data register + 0x401A0180 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT1 + Channel1 result data register + 0x401A0184 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT2 + Channel2 result data register + 0x401A0188 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT3 + Channel3 result data register + 0x401A018C + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT4 + Channel4 result data register + 0x401A0190 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT5 + Channel5 result data register + 0x401A0194 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT6 + Channel6 result data register + 0x401A0198 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT7 + Channel7 result data register + 0x401A019C + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_WORK_VALID + Channel working data register valid bits + 0x401A0200 + 32 + read-write + 0 + 0 + + + CHAN_WORK_VALID + If set the corresponding WORK data is valid, i.e. was already sampled during the current scan. + 0 + 15 + read-only + + + + + CHAN_RESULT_VALID + Channel result data register valid bits + 0x401A0204 + 32 + read-write + 0 + 0 + + + CHAN_RESULT_VALID + If set the corresponding RESULT data is valid, i.e. was sampled during the last scan. + 0 + 15 + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x401A0208 + 32 + read-write + 0 + 0 + + + AVG_STAT + Current averaging status (for debug) + 0x401A020C + 32 + read-write + 0 + 0 + + + INTR + Interrupt request register + 0x401A0210 + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + INTR_SET + Not really a register, intended for verification/debug. When read, this register reflects the interrupt request register. + 0x401A0214 + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + INTR_MASK + Interrupt mask register + 0x401A0218 + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x401A021C + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + SATURATE_INTR + Saturate interrupt request register + 0x401A0220 + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + SATURATE_INTR_SET + Saturate interrupt set request register + 0x401A0224 + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + SATURATE_INTR_MASK + Saturate interrupt mask register + 0x401A0228 + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + SATURATE_INTR_MASKED + Saturate interrupt masked request register + 0x401A022C + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR + Range detect interrupt request register + 0x401A0230 + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR_SET + Range detect interrupt set request register + 0x401A0234 + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR_MASK + Range detect interrupt mask register + 0x401A0238 + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR_MASKED + Range interrupt masked request register + 0x401A023C + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + INTR_CAUSE + Interrupt cause register + 0x401A0240 + 32 + read-write + 0 + 0 + + + MUX_SWITCH0 + SARMUX Firmware switch controls + 0x401A0300 + 32 + read-write + 0 + 0 + + + MUX_SWITCH_CLEAR0 + SARMUX Firmware switch control clear + 0x401A0304 + 32 + read-write + 0 + 0 + + + MUX_SWITCH1 + SARMUX Firmware switch controls + 0x401A0308 + 32 + read-write + 0 + 0 + + + MUX_SWITCH_CLEAR1 + SARMUX Firmware switch control clear + 0x401A030C + 32 + read-write + 0 + 0 + + + MUX_SWITCH_HW_CTRL + SARMUX switch hardware control + 0x401A0340 + 32 + read-write + 0 + 0 + + + MUX_SWITCH_STATUS + SARMUX switch status + 0x401A0348 + 32 + read-write + 0 + 0 + + + PUMP_CTRL + Switch pump control + 0x401A0380 + 32 + read-write + 0 + 0 + + + ANA_TRIM + Analog trim register + 0x401A0F00 + 32 + read-write + 0 + 0 + + + WOUNDING + SAR wounding register + 0x401A0F04 + 32 + read-write + 0 + 0 + + + WOUND_RESOLUTION + Maximum SAR resolution allowed + 0 + 1 + read-only + + + + + + + UART + Serial Communication Block + 0x0 + + 0 + 0x0 + registers + + + + Cy_CTRL + Generic control register + 0x40060000 + 32 + read-write + 0 + 0 + + + OVS + Serial interface bit period oversampling factor expressed in lP clock cycles. Used for SPI and UART functionality. OVS + 1 IP clock cycles constitute a single serial interface clock/bit cycle. + 0 + 3 + read-write + + + EC_AM_MODE + Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI).In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. + 8 + 8 + read-write + + + EC_OP_MODE + Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. + 9 + 9 + read-write + + + EZ_MODE + Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. + 10 + 10 + read-write + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').his field is used in the I2C mode. + 16 + 16 + read-write + + + BLOCK + If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0') + 17 + 17 + read-write + + + MODE + Mode of operation: I2C = 0, SPI = 1, UART = 2 + 24 + 25 + read-write + + + ENABLED + IP enabled ('1') or not ('0'). + 31 + 31 + read-write + + + + + Cy_SPI_CTRL + SPI control register + 0x40060020 + 32 + read-write + 0 + 0 + + + CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). + 0 + 0 + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. + 1 + 1 + read-write + + + CPHA + Only applicable in SPI Motorola submode. Indicates the clock phase. + 2 + 2 + read-write + + + CPOL + Only applicable in SPI Motorola submode. Indicates the clock polarity. + 3 + 3 + read-write + + + LATE_MISO_SAMPLE + Only applicable in master mode. Changes the SCLK edge on which MISO is captured. + 4 + 4 + read-write + + + LOOPBACK + Local loopback control. + 16 + 16 + read-write + + + MODE + Submode of SPI operation: Motorola = 0, Texas Instruments = 1, National Semiconducturs = 2. + 24 + 25 + read-write + + + SLAVE_SELECT + Selects one of the four SPI slave select signals: SS0 = 0, SS1 = 1 , SS2 = 2, SS3 = 3. + 26 + 27 + read-write + + + MASTER_MODE + Master ('1') or slave ('0') mode. + 31 + 31 + read-write + + + + + Cy_SPI_STATUS + SPI status register + 0x40060024 + 32 + read-write + 0 + 0 + + + BUS_BUSY + SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction + 0 + 0 + read-only + + + + + Cy_UART_CTRL + Extended Configuration Register + 0x40060040 + 32 + read-write + 0 + 0 + + + LOOPBACK + Local loopback control. + 16 + 16 + read-write + + + MODE + Submode of UART operation: Standard = 0, Smart Card = 1, IrDA = 2. + 24 + 25 + read-write + + + + + Cy_UART_TX_CTRL + Extended Configuration Register + 0x40060044 + 32 + read-write + 0 + 0 + + + STOP_BTIS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. + 0 + 2 + read-write + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity + 4 + 4 + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware. + 5 + 5 + read-write + + + RETRY_ON_NACK + When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. + 8 + 8 + read-write + + + + + Cy_UART_RX_CTRL + Extended Configuration Register + 0x40060048 + 32 + read-write + 0 + 0 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. + 0 + 2 + read-write + + + PARITY + Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. + 4 + 4 + read-write + + + PARITY_ENABLED + Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. + 5 + 5 + read-write + + + POLARITY + Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. + 6 + 6 + read-write + + + DROP_ON_PARITY_ERR + Behaviour when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + 8 + 8 + read-write + + + DROP_ON_FRAME_ERR + Behaviour when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + 9 + 9 + read-write + + + MP_MODE + Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. + 10 + 10 + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data + 12 + 12 + read-write + + + SKIP_START + Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. + 13 + 13 + read-write + + + BREAK_WIDTH + Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. + 16 + 19 + read-write + + + + + Cy_I2C_CTRL + Slave address and mask register + 0x40060060 + 32 + read-write + 0 + 0 + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. + 0 + 3 + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period + 4 + 7 + read-write + + + M_READY_DATA_ACK + When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. + 8 + 8 + read-write + + + M_NOT_READY_DATA_NACK + When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). + 9 + 9 + read-write + + + S_GENERAL_IGNORE + When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. + 11 + 11 + read-write + + + S_READY_ADDR_ACK + When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full + 12 + 12 + read-write + + + S_READY_DATA_ACK + When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full + 13 + 13 + read-write + + + S_NOT_READY_ADDR_NACK + When '1', a received address by the slave is immediately ACK'd when the receiver FIFO is not full + 14 + 14 + read-write + + + S_NOT_READY_DATA_NACK + When '1' a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. When '1' clock stretching is performed (till the receiver FIFO is no longer full). + 15 + 15 + read-write + + + LOOPBACK + Local loopback control + 16 + 16 + read-write + + + SLAVE_MODE + Slave mode enabled ('1') or not ('0'). + 30 + 30 + read-write + + + MASTER_MODE + Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. + 31 + 31 + read-write + + + + + Cy_I2C_STATUS + Slave address and mask register + 0x40060064 + 32 + read-write + 0 + 0 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'). + 0 + 0 + read-only + + + S_READ + I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0'. + 4 + 4 + read-only + + + M_READ + I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. + 5 + 5 + read-only + + + + + Cy_I2C_M_CMD + Slave address and mask register + 0x40060068 + 32 + read-write + 0 + 0 + + + M_START + When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. When this action is performed, the hardware sets this field to '0'. + 0 + 0 + read-write + + + M_IDLE_START + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). When this action is performed, the hardware sets this field to '0'. + 1 + 1 + read-write + + + M_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + 2 + 2 + read-write + + + M_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. + 3 + 3 + read-write + + + M_STOP + When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. This command has a higher priority than I2C_M_CMD.M_START: in situations where both a STOP and a REPEATED START could be transmitted, M_STOP takes precedence over M_START. + 4 + 4 + read-write + + + + + Cy_I2C_S_CMD + I2C slave command register + 0x4006006C + 32 + read-write + 0 + 0 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + 0 + 0 + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0' + 1 + 1 + read-write + + + + + Cy_I2C_CFG + I2C control register + 0x40060070 + 32 + read-write + 0 + 0 + + + SDA_FILT_HYS + No description available + 0 + 1 + read-write + + + SDA_FILT_TRIM + No description available + 2 + 3 + read-write + + + SCL_FILT_HYS + No description available + 4 + 5 + read-write + + + SCL_FILT_TRIM + No description available + 6 + 7 + read-write + + + SDA_FILT_OUT_HYS + No description available + 8 + 8 + read-write + + + SDA_FILT_OUT_TRIM + No description available + 10 + 11 + read-write + + + SDA_FILT_HS + No description available + 16 + 16 + read-write + + + SDA_FILT_ENABLED + No description available + 17 + 17 + read-write + + + SCL_FILT_HS + No description available + 24 + 24 + read-write + + + SCL_FILT_ENABLED + No description available + 25 + 25 + read-write + + + SDA_FILT_OUT_HS + No description available + 26 + 26 + read-write + + + SDA_FILT_OUT_ENABLED + No description available + 27 + 27 + read-write + + + + + Cy_TX_CTRL + Transmitter control register + 0x40060200 + 32 + read-write + 0 + 0 + + + DATA_WIDTH + Data frame width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. + 0 + 3 + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + 8 + 8 + read-write + + + ENABLED + Transmitter enabled. + 31 + 31 + read-write + + + + + Cy_TX_FIFO_CTRL + Transmitter FIFO control register + 0x40060204 + 32 + read-write + 0 + 0 + + + TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the amount of this field, a transmitter trigger event is generated. + 0 + 2 + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + 16 + 16 + read-write + + + FREEZE + When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. + 17 + 17 + read-write + + + + + Cy_TX_FIFO_STATUS + Transmitter FIFO status register + 0x40060208 + 32 + read-write + 0 + 0 + + + USED + Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to 8. + 0 + 3 + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0') + 15 + 15 + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + 16 + 18 + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + 24 + 26 + read-only + + + + + Cy_TX_FIFO_WR + Transmitter FIFO write register + 0x40060240 + 32 + read-write + 0 + 0 + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. + 0 + 15 + write-only + + + + + Cy_RX_CTRL + Receiver control register + 0x40060300 + 32 + read-write + 0 + 0 + + + DATA_WIDTH + Data frame width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. + 0 + 3 + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). + 8 + 8 + read-write + + + MEDIAN + Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. + 9 + 9 + read-write + + + ENABLED + Receiver enabled + 31 + 31 + read-write + + + + + Cy_RX_FIFO_CTRL + Receiver FIFO control register + 0x40060304 + 32 + read-write + 0 + 0 + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the amount of this field, a receiver trigger event is generated. + 0 + 2 + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + 16 + 16 + read-write + + + FREEZE + When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. + 17 + 17 + read-write + + + + + Cy_RX_FIFO_STATUS + Receiver FIFO status registerS + 0x40060308 + 32 + read-write + 0 + 0 + + + USED + Amount of entries in the receiver FIFO. The value of this field ranges from 0 to 8. + 0 + 3 + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). + 15 + 15 + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + 16 + 18 + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + 24 + 26 + read-only + + + + + Cy_RX_MATCH + Slave address and mask register + 0x40060310 + 32 + read-write + 0 + 0 + + + ADDR + Slave device address. For UART multi-processor mode all eight bits a reused. For I2C, bit 0 of the register is not used. + 0 + 7 + read-write + + + MASK + Slave device address mask. This field is a 8 bit mask that specifies which of the ADDR field bits in the SCB_RX_MATCH_ADDR register take part in the matching of the slave address. + 16 + 23 + read-write + + + + + Cy_RX_FIFO_RD + Receiver FIFO read register + 0x40060340 + 32 + read-write + 0 + 0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO. + 0 + 15 + read-only + + + + + Cy_INTR_CAUSE + Interrupt cause register + 0x40060E00 + 32 + read-write + 0 + 0 + + + MASTER + Master interrupt active. + 0 + 0 + read-only + + + SLAVE + Slave interrupt active. + 1 + 1 + read-only + + + TX + Transmitter interrupt active. + 2 + 2 + read-only + + + RX + Receiver interrupt active. + 3 + 3 + read-only + + + I2C_EC + Externally clock I2C interrupt active. + 4 + 4 + read-only + + + SPI_EC + Externally clocked SPI interrupt active. + 5 + 5 + read-only + + + + + Cy_INTR_I2C_EC + Externally clocked I2C interrupt request register + 0x40060E80 + 32 + read-write + 0 + 0 + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). Only used when EC_AM is '1'. + 0 + 0 + read-write + + + + + Cy_INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask register + 0x40060E88 + 32 + read-write + 0 + 0 + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + + + Cy_INTR_I2C_EC_MASKED + Externally clocked SPI interrupt masked register + 0x40060E8C + 32 + read-write + 0 + 0 + + + WAKE_UP + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + + + Cy_INTR_INTR_SPI_EC + Externally clocked SPI interrupt request register + 0x40060EC0 + 32 + read-write + 0 + 0 + + + WAKE_UP + Wake up request. Active on incoming slave request when externally clocked selection is '1'. + 0 + 0 + read-write + + + + + Cy_INTR_INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask register + 0x40060EC8 + 32 + read-write + 0 + 0 + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + + + Cy_INTR_INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked register + 0x40060ECC + 32 + read-write + 0 + 0 + + + WAKE_UP + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + + + Cy_INTR_M + Master interrupt request register. + 0x40060F00 + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. + 0 + 0 + read-write + + + I2C_NACK + I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). + 1 + 1 + read-write + + + I2C_ACK + I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). + 2 + 2 + read-write + + + I2C_STOP + I2C master STOP. Set to '1', when the master has transmitted a STOP. + 4 + 4 + read-write + + + I2C_BUS_ERR + I2C master bus error (unexpected detection of START or STOP condition). + 8 + 8 + read-write + + + SPI_DONE + SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO is empty. + 9 + 9 + read-write + + + + + Cy_INTR_M_SET + Master interrupt set request register + 0x40060F04 + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_BUS_ERR + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + 9 + 9 + read-write + + + + + Cy_INTR_M_MASK + Master interrupt mask register + 0x40060F08 + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_BUS_ERR + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + 9 + 9 + read-write + + + + + Cy_INTR_M_MASKED + Master interrupt masked request register + 0x40060F0C + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + I2C_NACK + Logical and of corresponding request and mask bits. + 1 + 1 + read-write + + + I2C_ACK + Logical and of corresponding request and mask bits. + 2 + 2 + read-write + + + I2C_STOP + Logical and of corresponding request and mask bits. + 4 + 4 + read-write + + + I2C_BUS_ERR + Logical and of corresponding request and mask bits. + 8 + 8 + read-write + + + SPI_DONE + Logical and of corresponding request and mask bits. + 9 + 9 + read-write + + + + + Cy_INTR_S + Slave interrupt request register + 0x40060F40 + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). + 0 + 0 + read-write + + + I2C_NACK + I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). + 1 + 1 + read-write + + + I2C_ACK + I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). + 2 + 2 + read-write + + + I2C_WRITE_STOP + I2C STOP event for I2C write transfer intended for this slave (address matching is performed).Set to '1', when STOP or REPEATED START event is detected. + 3 + 3 + read-write + + + I2C_STOP + I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected + 4 + 4 + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. + 6 + 6 + read-write + + + I2C_GENERAL + I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO + 7 + 7 + read-write + + + I2C_BUS_ERR + I2C slave bus error (unexpected detection of START or STOP condition). + 8 + 8 + read-write + + + SPI_BUS_ERR + SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + 11 + 11 + read-write + + + + + Cy_INTR_S_SET + Slave interrupt set request register + 0x40060F44 + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + 3 + 3 + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + 6 + 6 + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + 7 + 7 + read-write + + + I2C_BUS_ERR + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_BUS_ERR + Write with '1' to set corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_S_MASK + Slave interrupt mask register + 0x40060F48 + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + 3 + 3 + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + 6 + 6 + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + 7 + 7 + read-write + + + I2C_BUS_ERR + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_BUS_ERR + Mask bit for corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_S_MASKED + Slave interrupt masked register + 0x40060F4C + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + I2C_NACK + Logical and of corresponding request and mask bits. + 1 + 1 + read-write + + + I2C_ACK + Logical and of corresponding request and mask bits. + 2 + 2 + read-write + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + 3 + 3 + read-write + + + I2C_STOP + Logical and of corresponding request and mask bits. + 4 + 4 + read-write + + + I2C_START + Logical and of corresponding request and mask bits. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + 6 + 6 + read-write + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + 7 + 7 + read-write + + + SPI_BUS_ERR + Logical and of corresponding request and mask bits. + 11 + 11 + read-write + + + + + Cy_INTR_TX + Transmitter interrupt request register + 0x40060F80 + 32 + read-write + 0 + 0 + + + TRIGGER + Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTL. + 0 + 0 + read-write + + + NOT_FULL + TX FIFO is not full. + 1 + 1 + read-write + + + EMPTY + TX FIFO is empty; i.e. it has 0 entries. + 4 + 4 + read-write + + + OVERFLOW + Attempt to write to a full TX FIFO. + 5 + 5 + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. + 6 + 6 + read-write + + + UART_NACK + UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. + 8 + 8 + read-write + + + UART_DONE + UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO; i.e. EMPTY is '1'. Set to '1', when event is detected. + 9 + 9 + read-write + + + UART_ARB_LOST + UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. + 10 + 10 + read-write + + + + + Cy_INTR_TX_SET + Transmitter interrupt set request register + 0x40060F84 + 32 + read-write + 0 + 0 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + 1 + 1 + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + 4 + 4 + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 6 + 6 + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + 9 + 9 + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + 10 + 10 + read-write + + + + + Cy_INTR_TX_MASK + Transmitter interrupt mask request register + 0x40060F88 + 32 + read-write + 0 + 0 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + 1 + 1 + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + 4 + 4 + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + 6 + 6 + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + 9 + 9 + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + 10 + 10 + read-write + + + + + Cy_INTR_TX_MASKED + Transmitter interrupt masked request register + 0x40060F8C + 32 + read-write + 0 + 0 + + + TRIGGER + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + NOT_FULL + Logical and of corresponding request and mask bits. + 1 + 1 + read-write + + + EMPTY + Logical and of corresponding request and mask bits. + 4 + 4 + read-write + + + OVERFLOW + Logical and of corresponding request and mask bits. + 5 + 5 + read-write + + + UNDERFLOW + Logical and of corresponding request and mask bits. + 6 + 6 + read-write + + + UART_NACK + Logical and of corresponding request and mask bits. + 8 + 8 + read-write + + + UART_DONE + Logical and of corresponding request and mask bits. + 9 + 9 + read-write + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + 10 + 10 + read-write + + + + + Cy_INTR_RX + Receiver interrupt request register + 0x40060FC0 + 32 + read-write + 0 + 0 + + + TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL. + 0 + 0 + read-write + + + NOT_EMPTY + RX FIFO is not empty. + 2 + 2 + read-write + + + FULL + RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. + 3 + 3 + read-write + + + OVERFLOW + Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. + 5 + 5 + read-write + + + UNDERFLOW + Attempt to read from an empty RX FIFO. + 6 + 6 + read-write + + + FRAME_ERR + Frame error in received data frame. Set to '1', when event is detected. + 8 + 8 + read-write + + + PARITY_ERR + Parity error in received data frame. Set to '1', when event is detected. + 9 + 9 + read-write + + + BAUD_DETECT + LIN baud rate detection is completed. + 10 + 10 + read-write + + + BREAK_DETECT + Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. + 11 + 11 + read-write + + + + + Cy_INTR_RX_SET + Receiver interrupt set request register + 0x40060FC4 + 32 + read-write + 0 + 0 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + 2 + 2 + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt request register. + 3 + 3 + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 6 + 6 + read-write + + + FRAME_ERR + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + PARITY_ERR + Write with '1' to set corresponding bit in interrupt request register. + 9 + 9 + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt request register. + 10 + 10 + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_RX_MASK + Receiver interrupt mask register + 0x40060FC8 + 32 + read-write + 0 + 0 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + 2 + 2 + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + 3 + 3 + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + 6 + 6 + read-write + + + FRAME_ERR + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + PARITY_ERR + Mask bit for corresponding bit in interrupt request register. + 9 + 9 + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + 10 + 10 + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_RX_MASKED + Receiver interrupt masked register + 0x40060FCC + 32 + read-write + 0 + 0 + + + TRIGGER + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + 2 + 2 + read-write + + + FULL + Logical and of corresponding request and mask bits. + 3 + 3 + read-write + + + OVERFLOW + Logical and of corresponding request and mask bits. + 5 + 5 + read-write + + + UNDERFLOW + Logical and of corresponding request and mask bits. + 6 + 6 + read-write + + + FRAME_ERR + Logical and of corresponding request and mask bits + 8 + 8 + read-write + + + PARITY_ERR + Logical and of corresponding request and mask bits + 9 + 9 + read-write + + + BAUD_DETECT + Logical and of corresponding request and mask bits + 10 + 10 + read-write + + + BREAK_DETECT + Logical and of corresponding request and mask bits + 11 + 11 + read-write + + + + + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/ADC-UART_timing.html b/TrainingProjects/ADC-UART.cydsn/ADC-UART_timing.html new file mode 100644 index 0000000..d5ea766 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ADC-UART_timing.html @@ -0,0 +1,672 @@ + + + + +Static Timing Analysis Report + + + + + + +

Static Timing Analysis

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Project : ADC-UART
Build Time : 07/17/20 10:59:54
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5.0
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No Timing Violations
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ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
ADC_intClock(FFB)ADC_intClock(FFB)1.000 MHz1.000 MHz N/A
CyHFCLKCyHFCLK24.000 MHz24.000 MHz N/A
ADC_intClockCyHFCLK1.000 MHz1.000 MHz N/A
UART_SCBCLKCyHFCLK76.677 kHz76.677 kHz N/A
CyILOCyILO32.000 kHz32.000 kHz N/A
CyIMOCyIMO24.000 MHz24.000 MHz N/A
CyLFCLKCyLFCLK32.000 kHz32.000 kHz N/A
CyRouted1CyRouted124.000 MHz24.000 MHz N/A
CySYSCLKCySYSCLK24.000 MHz24.000 MHz N/A
UART_SCBCLK(FFB)UART_SCBCLK(FFB)76.677 kHz76.677 kHz N/A
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+ + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/.deps/SOURCE_ASM__ARM_GCC_GENERIC.P b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/.deps/SOURCE_ASM__ARM_GCC_GENERIC.P new file mode 100644 index 0000000..8a00558 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/.deps/SOURCE_ASM__ARM_GCC_GENERIC.P @@ -0,0 +1,8 @@ +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyBootAsmGnu.o : D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfittergnu.inc + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfittergnu.inc : + diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/.deps/SOURCE_C__ARM_GCC_GENERIC.P b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/.deps/SOURCE_C__ARM_GCC_GENERIC.P new file mode 100644 index 0000000..fbcdd86 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/.deps/SOURCE_C__ARM_GCC_GENERIC.P @@ -0,0 +1,84 @@ +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC.o : D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.c D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevice_trm.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cytypes.h + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.c : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.h : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.h : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.h : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevice_trm.h : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter.h : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cytypes.h : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_INT.o : D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_INT.c D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevice_trm.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cytypes.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/cyapicallbacks.h + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_INT.c : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/cyapicallbacks.h : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_PM.o : D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_PM.c D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevice_trm.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cytypes.h + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_PM.c : + +D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/main.o : D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_IRQ.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_intClock.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyFlash.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1_aliases.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED_aliases.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_BOOT.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PINS.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PVT.h D:/Users/jagumiel/Documents/PSoC\ Creator/PSoC-101/PSoC-101/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SCBCLK.h D:/Users/jagumiel/Documents/PSoC\ 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creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libc_nano.a +END GROUP +START GROUP +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libc_nano.a +END GROUP +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtend.o +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtn.o +START GROUP +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libnosys.a +END GROUP + 0x00000000 CY_APPL_ORIGIN = 0x0 + 0x00000080 CY_FLASH_ROW_SIZE = 0x80 + 0x00000001 CY_APPL_NUM = 0x1 + 0x00000001 CY_APPL_MAX = 0x1 + 0x00000040 CY_METADATA_SIZE = 0x40 + 0x00000000 CY_APPL_LOADABLE = 0x0 + 0x00000000 CY_CHECKSUM_EXCLUDE_SIZE = ALIGN (0x0, CY_FLASH_ROW_SIZE) + 0x00000000 CY_APP_FOR_STACK_AND_COPIER = 0x0 + [!provide] PROVIDE (__cy_heap_start, _end) + 0x00000001 PROVIDE (__cy_region_num, ((__cy_regions_end - __cy_regions) / 0x10)) + 0x20001000 PROVIDE (__cy_stack, (ORIGIN (ram) + LENGTH (ram))) + [!provide] PROVIDE (__cy_heap_end, (__cy_stack - 0x400)) + +.cybootloader 0x00000000 0x0 + *(.cybootloader) + 0x00000000 appl1_start = CY_APPL_ORIGIN?CY_APPL_ORIGIN:ALIGN (CY_FLASH_ROW_SIZE) + 0x00003f80 appl2_start = (appl1_start + ALIGN ((((LENGTH (rom) - appl1_start) - (0x2 * CY_FLASH_ROW_SIZE)) / 0x2), CY_FLASH_ROW_SIZE)) + 0x00000000 appl_start = (CY_APPL_NUM == 0x1)?appl1_start:appl2_start + 0x00000001 cy_project_type_bootloader = (appl_start == 0x0)?0x1:0x0 + 0x00000000 cy_project_type_app_for_stack_and_copier = (CY_APP_FOR_STACK_AND_COPIER == 0x1)?0x1:0x0 + +.text 0x00000000 0x1288 + CREATE_OBJECT_SYMBOLS + 0x00000000 PROVIDE (__cy_interrupt_vector, RomVectors) + *(.romvectors) + .romvectors 0x00000000 0x10 .\ARM_GCC_541\Debug\Cm0Start.o + 0x00000000 RomVectors + 0x00000001 ASSERT ((. != __cy_interrupt_vector), No interrupt vector) + 0x00000001 ASSERT (CY_APPL_ORIGIN?(SIZEOF (.cybootloader) <= CY_APPL_ORIGIN):0x1, Wrong image location) + 0x00000010 PROVIDE (__cy_reset, Reset) + *(.text.Reset) + .text.Reset 0x00000010 0x8 .\ARM_GCC_541\Debug\Cm0Start.o + 0x00000010 Reset + 0x00000001 ASSERT ((. != __cy_reset), No reset code) + *(.psocinit) + .psocinit 0x00000018 0x1a0 .\ARM_GCC_541\Debug\cyfitter_cfg.o + 0x000000a4 cyfitter_cfg + 0x000001b8 . = MAX (., 0x100) + *(.text .text.* .gnu.linkonce.t.*) + .text 0x000001b8 0x60 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .text.main 0x00000218 0xdc .\ARM_GCC_541\Debug\main.o + 0x00000218 main + .text.SendChannelVoltage + 0x000002f4 0x128 .\ARM_GCC_541\Debug\main.o + .text.ADC_ISR_Handler + 0x0000041c 0x50 .\ARM_GCC_541\Debug\main.o + 0x0000041c ADC_ISR_Handler + .text.CYMEMZERO + 0x0000046c 0x20 .\ARM_GCC_541\Debug\cyfitter_cfg.o + .text.AnalogSetDefault + 0x0000048c 0x14 .\ARM_GCC_541\Debug\cyfitter_cfg.o + .text.IntDefaultHandler + 0x000004a0 0x14 .\ARM_GCC_541\Debug\Cm0Start.o + 0x000004a0 IntDefaultHandler + .text.Start_c 0x000004b4 0x98 .\ARM_GCC_541\Debug\Cm0Start.o + 0x000004b4 Start_c + .text.initialize_psoc + 0x0000054c 0x64 .\ARM_GCC_541\Debug\Cm0Start.o + 0x0000054c initialize_psoc + .text.LED_Write + 0x000005b0 0x50 .\ARM_GCC_541\Debug\ADC-UART.a(LED.o) + 0x000005b0 LED_Write + .text.UART_Init + 0x00000600 0x10 .\ARM_GCC_541\Debug\ADC-UART.a(UART.o) + 0x00000600 UART_Init + .text.UART_Enable + 0x00000610 0x24 .\ARM_GCC_541\Debug\ADC-UART.a(UART.o) + 0x00000610 UART_Enable + .text.UART_Start + 0x00000634 0x24 .\ARM_GCC_541\Debug\ADC-UART.a(UART.o) + 0x00000634 UART_Start + .text.UART_ScbEnableIntr + 0x00000658 0xc .\ARM_GCC_541\Debug\ADC-UART.a(UART.o) + .text.UART_ScbModePostEnable + 0x00000664 0x10 .\ARM_GCC_541\Debug\ADC-UART.a(UART.o) + .text.UART_SpiUartWriteTxData + 0x00000674 0x2c .\ARM_GCC_541\Debug\ADC-UART.a(UART_SPI_UART.o) + 0x00000674 UART_SpiUartWriteTxData + .text.UART_UartInit + 0x000006a0 0xbc .\ARM_GCC_541\Debug\ADC-UART.a(UART_UART.o) + 0x000006a0 UART_UartInit + .text.UART_UartPostEnable + 0x0000075c 0x30 .\ARM_GCC_541\Debug\ADC-UART.a(UART_UART.o) + 0x0000075c UART_UartPostEnable + .text.UART_UartPutString + 0x0000078c 0x38 .\ARM_GCC_541\Debug\ADC-UART.a(UART_UART.o) + 0x0000078c UART_UartPutString + .text.UART_UartPutCRLF + 0x000007c4 0x24 .\ARM_GCC_541\Debug\ADC-UART.a(UART_UART.o) + 0x000007c4 UART_UartPutCRLF + .text.ADC_Start + 0x000007e8 0x24 .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x000007e8 ADC_Start + .text.ADC_Init + 0x0000080c 0x1d8 .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x0000080c ADC_Init + .text.ADC_Enable + 0x000009e4 0x2c .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x000009e4 ADC_Enable + .text.ADC_StartConvert + 0x00000a10 0x1c .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x00000a10 ADC_StartConvert + .text.ADC_GetResult16 + 0x00000a2c 0x44 .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x00000a2c ADC_GetResult16 + .text.ADC_CountsTo_mVolts + 0x00000a70 0xa0 .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x00000a70 ADC_CountsTo_mVolts + .text.ADC_ISR 0x00000b10 0x20 .\ARM_GCC_541\Debug\ADC-UART.a(ADC_INT.o) + 0x00000b10 ADC_ISR + .text.ADC_IRQ_StartEx + 0x00000b30 0x28 .\ARM_GCC_541\Debug\ADC-UART.a(ADC_IRQ.o) + 0x00000b30 ADC_IRQ_StartEx + .text.ADC_IRQ_SetVector + 0x00000b58 0x1c .\ARM_GCC_541\Debug\ADC-UART.a(ADC_IRQ.o) + 0x00000b58 ADC_IRQ_SetVector + .text.ADC_IRQ_SetPriority + 0x00000b74 0x50 .\ARM_GCC_541\Debug\ADC-UART.a(ADC_IRQ.o) + 0x00000b74 ADC_IRQ_SetPriority + .text.ADC_IRQ_Enable + 0x00000bc4 0x18 .\ARM_GCC_541\Debug\ADC-UART.a(ADC_IRQ.o) + 0x00000bc4 ADC_IRQ_Enable + .text.ADC_IRQ_Disable + 0x00000bdc 0x18 .\ARM_GCC_541\Debug\ADC-UART.a(ADC_IRQ.o) + 0x00000bdc ADC_IRQ_Disable + .text.CySysClkWriteImoFreq + 0x00000bf4 0x1e4 .\ARM_GCC_541\Debug\ADC-UART.a(CyLib.o) + 0x00000bf4 CySysClkWriteImoFreq + .text.CyIntSetVector + 0x00000dd8 0x4c .\ARM_GCC_541\Debug\ADC-UART.a(CyLib.o) + 0x00000dd8 CyIntSetVector + .text.CyIntSetPriority + 0x00000e24 0xa8 .\ARM_GCC_541\Debug\ADC-UART.a(CyLib.o) + 0x00000e24 CyIntSetPriority + .text.CyHalt 0x00000ecc 0x18 .\ARM_GCC_541\Debug\ADC-UART.a(CyLib.o) + 0x00000ecc CyHalt + .text.CyDelayUs + 0x00000ee4 0x28 .\ARM_GCC_541\Debug\ADC-UART.a(CyLib.o) + 0x00000ee4 CyDelayUs + *fill* 0x00000f0c 0x4 + .text 0x00000f10 0x24 .\ARM_GCC_541\Debug\ADC-UART.a(CyBootAsmGnu.o) + 0x00000f10 CyDelayCycles + 0x00000f24 CyEnterCriticalSection + 0x00000f2c CyExitCriticalSection + .text 0x00000f34 0x114 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(_udivsi3.o) + 0x00000f34 __aeabi_uidiv + 0x00000f34 __udivsi3 + 0x00001040 __aeabi_uidivmod + .text 0x00001048 0x1d4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(_divsi3.o) + 0x00001048 __divsi3 + 0x00001048 __aeabi_idiv + 0x00001214 __aeabi_idivmod + .text 0x0000121c 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(_dvmd_tls.o) + 0x0000121c __aeabi_idiv0 + 0x0000121c __aeabi_ldiv0 + .text.__errno 0x00001220 0xc c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-errno.o) + 0x00001220 __errno + .text.__libc_init_array + 0x0000122c 0x4c c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-init.o) + 0x0000122c __libc_init_array + .text.memset 0x00001278 0x10 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-memset.o) + 0x00001278 memset + *(.plt) + *(.gnu.warning) + *(.glue_7t) + .glue_7t 0x00001288 0x0 linker stubs + *(.glue_7) + .glue_7 0x00001288 0x0 linker stubs + *(.vfp11_veneer) + .vfp11_veneer 0x00001288 0x0 linker stubs + *(.bootloader) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + +.v4_bx 0x00001288 0x0 + .v4_bx 0x00001288 0x0 linker stubs + +.iplt 0x00001288 0x0 + .iplt 0x00001288 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + +.eh_frame_hdr + *(.eh_frame_hdr) + +.eh_frame 0x00001288 0x4 + *(.eh_frame) + .eh_frame 0x00001288 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .eh_frame 0x00001288 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtend.o + [!provide] PROVIDE (__exidx_start, .) + +.ARM.exidx + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + 0x0000128c __exidx_end = . + +.rodata 0x0000128c 0x8c + *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata 0x0000128c 0x18 .\ARM_GCC_541\Debug\main.o + .rodata 0x000012a4 0xc .\ARM_GCC_541\Debug\cyfitter_cfg.o + .rodata 0x000012b0 0x2e .\ARM_GCC_541\Debug\ADC-UART.a(CyLib.o) + 0x000012b0 cyImoFreqMhz2Reg + .rodata.str1.1 + 0x000012de 0x2 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-impure.o) + 0x000012e0 . = ALIGN (0x4) + *(.init) + .init 0x000012e0 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crti.o + 0x000012e0 _init + .init 0x000012e4 0x8 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtn.o + 0x000012ec . = ALIGN (0x4) + 0x000012ec __preinit_array_start = . + *(.preinit_array) + 0x000012ec __preinit_array_end = . + 0x000012ec . = ALIGN (0x4) + 0x000012ec __init_array_start = . + *(SORT(.init_array.*)) + *(.init_array) + .init_array 0x000012ec 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .init_array 0x000012f0 0x4 .\ARM_GCC_541\Debug\Cm0Start.o + 0x000012f4 __init_array_end = . + 0x000012f4 . = ALIGN (0x4) + *(.fini) + .fini 0x000012f4 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crti.o + 0x000012f4 _fini + .fini 0x000012f8 0x8 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtn.o + 0x00001300 . = ALIGN (0x4) + 0x00001300 __fini_array_start = . + *(.fini_array) + .fini_array 0x00001300 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + *(SORT(.fini_array.*)) + 0x00001304 __fini_array_end = . + 0x00001304 . = ALIGN (0x4) + *crtbegin.o(.ctors) + *(EXCLUDE_FILE(*crtend.o) .ctors) + *(SORT(.ctors.*)) + *crtend.o(.ctors) + 0x00001304 . = ALIGN (0x4) + *crtbegin.o(.dtors) + *(EXCLUDE_FILE(*crtend.o) .dtors) + *(SORT(.dtors.*)) + *crtend.o(.dtors) + 0x00001304 . = ALIGN (0x4) + 0x00001304 __cy_regions = . + 0x00001304 0x4 LONG 0x1318 __cy_region_init_ram + 0x00001308 0x4 LONG 0x200000c8 __cy_region_start_data + 0x0000130c 0x4 LONG 0x80 __cy_region_init_size_ram + 0x00001310 0x4 LONG 0x30 __cy_region_zero_size_ram + 0x00001314 __cy_regions_end = . + 0x00001318 . = ALIGN (0x8) + *fill* 0x00001314 0x4 + 0x00001318 _etext = . + +.cy_checksum_exclude + 0x00001318 0x0 + *(.cy_checksum_exclude) + +.ramvectors 0x20000000 0xc0 + 0x20000000 __cy_region_start_ram = . + *(.ramvectors) + .ramvectors 0x20000000 0xc0 .\ARM_GCC_541\Debug\Cm0Start.o + 0x20000000 CyRamVectors + +.noinit 0x200000c0 0x4 + *(.noinit) + .noinit 0x200000c0 0x4 .\ARM_GCC_541\Debug\Cm0Start.o + +.data 0x200000c8 0x80 load address 0x00001318 + 0x200000c8 __cy_region_start_data = . + *(.jcr) + .jcr 0x200000c8 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .jcr 0x200000c8 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtend.o + *(.got.plt) + *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + .data 0x200000cc 0x14 .\ARM_GCC_541\Debug\ADC-UART.a(CyLib.o) + 0x200000cc cydelayFreqHz + 0x200000d0 cydelayFreqKhz + 0x200000d4 cydelayFreqMhz + 0x200000d8 cydelay32kMs + 0x200000dc CySysClkPumpConfig + .data.impure_data + 0x200000e0 0x60 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-impure.o) + .data._impure_ptr + 0x20000140 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-impure.o) + 0x20000140 _impure_ptr + 0x20000148 . = ALIGN (0x8) + *fill* 0x20000144 0x4 + *(.ram) + 0x20000148 _edata = . + +.igot.plt 0x20000148 0x0 load address 0x00001398 + .igot.plt 0x20000148 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + +.bss 0x20000148 0x30 load address 0x00001398 + 0x20000148 PROVIDE (__bss_start__, .) + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + .bss 0x20000148 0x1c c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .bss 0x20000164 0x6 .\ARM_GCC_541\Debug\main.o + 0x20000164 windowFlag + 0x20000168 dataReady + 0x20000169 channelFlag + .bss 0x2000016a 0x4 .\ARM_GCC_541\Debug\ADC-UART.a(UART.o) + 0x2000016a UART_initVar + 0x2000016c UART_IntrTxMask + .bss 0x2000016e 0x1 .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x2000016e ADC_initVar + *(COMMON) + *fill* 0x2000016f 0x1 + COMMON 0x20000170 0x6 .\ARM_GCC_541\Debug\ADC-UART.a(ADC.o) + 0x20000170 ADC_countsPer10Volt + 0x20000174 ADC_offset + 0x20000178 . = ALIGN (0x8) + *fill* 0x20000176 0x2 + *(.ram.b) + 0x20000178 _end = . + 0x20000178 __end = . + 0x20000178 PROVIDE (end, .) + 0x20000178 PROVIDE (__bss_end__, .) + 0x00001318 __cy_region_init_ram = LOADADDR (.data) + 0x00000080 __cy_region_init_size_ram = (_edata - ADDR (.data)) + 0x00000030 __cy_region_zero_size_ram = (_end - _edata) + +.heap 0x20000178 0x100 load address 0x00001398 + 0x20000178 . = _end + 0x20000278 . = (. + 0x100) + *fill* 0x20000178 0x100 + 0x20000278 __cy_heap_limit = . + +.stack 0x20000c00 0x400 + 0x20000c00 __cy_stack_limit = . + 0x20001000 . = (. + 0x400) + *fill* 0x20000c00 0x400 + 0x00000001 ASSERT ((__cy_stack_limit >= __cy_heap_limit), region RAM overflowed with stack) + 0x00000000 cy_checksum_exclude_size = (CY_APPL_LOADABLE == 0x1)?SIZEOF (.cy_checksum_exclude):0x0 + 0x00000001 ASSERT ((cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE), CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.) + 0x00007fc0 cyloadermeta_start = (cy_project_type_bootloader || cy_project_type_app_for_stack_and_copier)?(LENGTH (rom) - CY_METADATA_SIZE):0xf0000000 + +.cyloadermeta + *(.cyloadermeta) + 0x00007fc0 cyloadablemeta_start = cy_project_type_app_for_stack_and_copier?((LENGTH (rom) - CY_FLASH_ROW_SIZE) - CY_METADATA_SIZE):((LENGTH (rom) - (CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 0x1))) - CY_METADATA_SIZE) + +.cyloadablemeta + *(.cyloadablemeta) + +.cyflashprotect + 0x90400000 0x20 + *(.cyflashprotect) + .cyflashprotect + 0x90400000 0x20 .\ARM_GCC_541\Debug\cymetadata.o + 0x90400000 cy_meta_flashprotect + +.cymeta 0x90500000 0xc + *(.cymeta) + .cymeta 0x90500000 0xc .\ARM_GCC_541\Debug\cymetadata.o + 0x90500000 cy_metadata + +.cychipprotect 0x90600000 0x1 + *(.cychipprotect) + .cychipprotect + 0x90600000 0x1 .\ARM_GCC_541\Debug\cymetadata.o + 0x90600000 cy_meta_chipprotect + +.rel.dyn 0x00001398 0x0 load address 0x90600004 + .rel.iplt 0x00001398 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + +.stab + *(.stab) + +.stabstr + *(.stabstr) + +.debug + *(.debug) + +.line + *(.line) + +.debug_srcinfo + *(.debug_srcinfo) + +.debug_sfnames + *(.debug_sfnames) + +.debug_aranges 0x00000000 0x510 + *(.debug_aranges) + .debug_aranges + 0x00000000 0x30 .\ARM_GCC_541\Debug\main.o + .debug_aranges + 0x00000030 0x48 .\ARM_GCC_541\Debug\cyfitter_cfg.o + .debug_aranges + 0x00000078 0x18 .\ARM_GCC_541\Debug\cymetadata.o + .debug_aranges + 0x00000090 0x48 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Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ARM_GCC_541\Debug\ADC-UART.elf elf32-littlearm) diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC.lst new file mode 100644 index 0000000..2c1114a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC.lst @@ -0,0 +1,3634 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "ADC.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .global ADC_initVar + 20 .bss + 21 .type ADC_initVar, %object + 22 .size ADC_initVar, 1 + 23 ADC_initVar: + 24 0000 00 .space 1 + 25 .comm ADC_offset,2,4 + 26 .comm ADC_countsPer10Volt,4,4 + 27 .section .rodata + 28 .align 2 + 29 .type ADC_channelsConfig, %object + 30 .size ADC_channelsConfig, 4 + 31 ADC_channelsConfig: + 32 0000 02040000 .word 1026 + 33 .section .text.ADC_Start,"ax",%progbits + 34 .align 2 + 35 .global ADC_Start + 36 .code 16 + 37 .thumb_func + 38 .type ADC_Start, %function + 39 ADC_Start: + 40 .LFB0: + 41 .file 1 "Generated_Source\\PSoC4\\ADC.c" + 1:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/ADC.c **** * File Name: ADC.c + 3:Generated_Source\PSoC4/ADC.c **** * Version 2.50 + 4:Generated_Source\PSoC4/ADC.c **** * + 5:Generated_Source\PSoC4/ADC.c **** * Description: + 6:Generated_Source\PSoC4/ADC.c **** * This file provides the source code to the API for the Sequencing Successive + 7:Generated_Source\PSoC4/ADC.c **** * Approximation ADC Component Component. + 8:Generated_Source\PSoC4/ADC.c **** * + 9:Generated_Source\PSoC4/ADC.c **** * Note: + 10:Generated_Source\PSoC4/ADC.c **** * + 11:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 12:Generated_Source\PSoC4/ADC.c **** * Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. + 13:Generated_Source\PSoC4/ADC.c **** * You may use this file only in accordance with the license, terms, conditions, + 14:Generated_Source\PSoC4/ADC.c **** * disclaimers, and limitations in the end user license agreement accompanying + 15:Generated_Source\PSoC4/ADC.c **** * the software package with which this file was provided. + 16:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 2 + + + 17:Generated_Source\PSoC4/ADC.c **** + 18:Generated_Source\PSoC4/ADC.c **** #include "ADC.h" + 19:Generated_Source\PSoC4/ADC.c **** + 20:Generated_Source\PSoC4/ADC.c **** + 21:Generated_Source\PSoC4/ADC.c **** /*************************************** + 22:Generated_Source\PSoC4/ADC.c **** * Global data allocation + 23:Generated_Source\PSoC4/ADC.c **** ***************************************/ + 24:Generated_Source\PSoC4/ADC.c **** uint8 ADC_initVar = 0u; + 25:Generated_Source\PSoC4/ADC.c **** volatile int16 ADC_offset[ADC_TOTAL_CHANNELS_NUM]; + 26:Generated_Source\PSoC4/ADC.c **** volatile int32 ADC_countsPer10Volt[ADC_TOTAL_CHANNELS_NUM]; /* Gain compensation */ + 27:Generated_Source\PSoC4/ADC.c **** + 28:Generated_Source\PSoC4/ADC.c **** + 29:Generated_Source\PSoC4/ADC.c **** /*************************************** + 30:Generated_Source\PSoC4/ADC.c **** * Local data allocation + 31:Generated_Source\PSoC4/ADC.c **** ***************************************/ + 32:Generated_Source\PSoC4/ADC.c **** /* Channels configuration generated by customiser */ + 33:Generated_Source\PSoC4/ADC.c **** static const uint32 CYCODE ADC_channelsConfig[] = { 0x00000402u }; + 34:Generated_Source\PSoC4/ADC.c **** + 35:Generated_Source\PSoC4/ADC.c **** + 36:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 37:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_Start + 38:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 39:Generated_Source\PSoC4/ADC.c **** * + 40:Generated_Source\PSoC4/ADC.c **** * Summary: + 41:Generated_Source\PSoC4/ADC.c **** * Performs all required initialization for this component + 42:Generated_Source\PSoC4/ADC.c **** * and enables the power. The power will be set to the appropriate + 43:Generated_Source\PSoC4/ADC.c **** * power based on the clock frequency. + 44:Generated_Source\PSoC4/ADC.c **** * + 45:Generated_Source\PSoC4/ADC.c **** * Parameters: + 46:Generated_Source\PSoC4/ADC.c **** * None. + 47:Generated_Source\PSoC4/ADC.c **** * + 48:Generated_Source\PSoC4/ADC.c **** * Return: + 49:Generated_Source\PSoC4/ADC.c **** * None. + 50:Generated_Source\PSoC4/ADC.c **** * + 51:Generated_Source\PSoC4/ADC.c **** * Global variables: + 52:Generated_Source\PSoC4/ADC.c **** * The ADC_initVar variable is used to indicate when/if initial + 53:Generated_Source\PSoC4/ADC.c **** * configuration of this component has happened. The variable is initialized to + 54:Generated_Source\PSoC4/ADC.c **** * zero and set to 1 the first time ADC_Start() is called. This allows for + 55:Generated_Source\PSoC4/ADC.c **** * component Re-Start without re-initialization in all subsequent calls to the + 56:Generated_Source\PSoC4/ADC.c **** * ADC_Start() routine. + 57:Generated_Source\PSoC4/ADC.c **** * If re-initialization of the component is required the variable should be set + 58:Generated_Source\PSoC4/ADC.c **** * to zero before call of ADC_Start() routine, or the user may call + 59:Generated_Source\PSoC4/ADC.c **** * ADC_Init() and ADC_Enable() as done in the + 60:Generated_Source\PSoC4/ADC.c **** * ADC_Start() routine. + 61:Generated_Source\PSoC4/ADC.c **** * + 62:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 63:Generated_Source\PSoC4/ADC.c **** void ADC_Start(void) + 64:Generated_Source\PSoC4/ADC.c **** { + 42 .loc 1 64 0 + 43 .cfi_startproc + 44 @ args = 0, pretend = 0, frame = 0 + 45 @ frame_needed = 1, uses_anonymous_args = 0 + 46 0000 80B5 push {r7, lr} + 47 .cfi_def_cfa_offset 8 + 48 .cfi_offset 7, -8 + 49 .cfi_offset 14, -4 + 50 0002 00AF add r7, sp, #0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 3 + + + 51 .cfi_def_cfa_register 7 + 65:Generated_Source\PSoC4/ADC.c **** /* If not Initialized then initialize all required hardware and software */ + 66:Generated_Source\PSoC4/ADC.c **** if(ADC_initVar == 0u) + 52 .loc 1 66 0 + 53 0004 064B ldr r3, .L3 + 54 0006 1B78 ldrb r3, [r3] + 55 0008 002B cmp r3, #0 + 56 000a 04D1 bne .L2 + 67:Generated_Source\PSoC4/ADC.c **** { + 68:Generated_Source\PSoC4/ADC.c **** ADC_Init(); + 57 .loc 1 68 0 + 58 000c FFF7FEFF bl ADC_Init + 69:Generated_Source\PSoC4/ADC.c **** ADC_initVar = 1u; + 59 .loc 1 69 0 + 60 0010 034B ldr r3, .L3 + 61 0012 0122 movs r2, #1 + 62 0014 1A70 strb r2, [r3] + 63 .L2: + 70:Generated_Source\PSoC4/ADC.c **** } + 71:Generated_Source\PSoC4/ADC.c **** ADC_Enable(); + 64 .loc 1 71 0 + 65 0016 FFF7FEFF bl ADC_Enable + 72:Generated_Source\PSoC4/ADC.c **** } + 66 .loc 1 72 0 + 67 001a C046 nop + 68 001c BD46 mov sp, r7 + 69 @ sp needed + 70 001e 80BD pop {r7, pc} + 71 .L4: + 72 .align 2 + 73 .L3: + 74 0020 00000000 .word ADC_initVar + 75 .cfi_endproc + 76 .LFE0: + 77 .size ADC_Start, .-ADC_Start + 78 .global __aeabi_idiv + 79 .section .text.ADC_Init,"ax",%progbits + 80 .align 2 + 81 .global ADC_Init + 82 .code 16 + 83 .thumb_func + 84 .type ADC_Init, %function + 85 ADC_Init: + 86 .LFB1: + 73:Generated_Source\PSoC4/ADC.c **** + 74:Generated_Source\PSoC4/ADC.c **** + 75:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 76:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_Init + 77:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 78:Generated_Source\PSoC4/ADC.c **** * + 79:Generated_Source\PSoC4/ADC.c **** * Summary: + 80:Generated_Source\PSoC4/ADC.c **** * Initialize component's parameters to the parameters set by user in the + 81:Generated_Source\PSoC4/ADC.c **** * customizer of the component placed onto schematic. Usually called in + 82:Generated_Source\PSoC4/ADC.c **** * ADC_Start(). + 83:Generated_Source\PSoC4/ADC.c **** * + 84:Generated_Source\PSoC4/ADC.c **** * Parameters: + 85:Generated_Source\PSoC4/ADC.c **** * None. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 4 + + + 86:Generated_Source\PSoC4/ADC.c **** * + 87:Generated_Source\PSoC4/ADC.c **** * Return: + 88:Generated_Source\PSoC4/ADC.c **** * None. + 89:Generated_Source\PSoC4/ADC.c **** * + 90:Generated_Source\PSoC4/ADC.c **** * Global variables: + 91:Generated_Source\PSoC4/ADC.c **** * The ADC_offset variable is initialized. + 92:Generated_Source\PSoC4/ADC.c **** * + 93:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 94:Generated_Source\PSoC4/ADC.c **** void ADC_Init(void) + 95:Generated_Source\PSoC4/ADC.c **** { + 87 .loc 1 95 0 + 88 .cfi_startproc + 89 @ args = 0, pretend = 0, frame = 16 + 90 @ frame_needed = 1, uses_anonymous_args = 0 + 91 0000 80B5 push {r7, lr} + 92 .cfi_def_cfa_offset 8 + 93 .cfi_offset 7, -8 + 94 .cfi_offset 14, -4 + 95 0002 84B0 sub sp, sp, #16 + 96 .cfi_def_cfa_offset 24 + 97 0004 00AF add r7, sp, #0 + 98 .cfi_def_cfa_register 7 + 96:Generated_Source\PSoC4/ADC.c **** uint32 chNum; + 97:Generated_Source\PSoC4/ADC.c **** uint32 tmpRegVal; + 98:Generated_Source\PSoC4/ADC.c **** int32 counts; + 99:Generated_Source\PSoC4/ADC.c **** + 100:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 1u) + 101:Generated_Source\PSoC4/ADC.c **** static const uint8 CYCODE ADC_InputsPlacement[] = + 102:Generated_Source\PSoC4/ADC.c **** { + 103:Generated_Source\PSoC4/ADC.c **** (uint8)(ADC_cy_psoc4_sarmux_8__CH_0_PORT << 4u) | + 104:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_0_PIN + 105:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_1_PORT << 4u) | + 106:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_1_PIN + 107:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 2u) + 108:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_2_PORT << 4u) | + 109:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_2_PIN + 110:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 2u */ + 111:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 3u) + 112:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_3_PORT << 4u) | + 113:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_3_PIN + 114:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 3u */ + 115:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 4u) + 116:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_4_PORT << 4u) | + 117:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_4_PIN + 118:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 4u */ + 119:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 5u) + 120:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_5_PORT << 4u) | + 121:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_5_PIN + 122:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 5u */ + 123:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 6u) + 124:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_6_PORT << 4u) | + 125:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_6_PIN + 126:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 6u */ + 127:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 7u) + 128:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_7_PORT << 4u) | + 129:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_7_PIN + 130:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 7u */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 5 + + + 131:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 8u) + 132:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_8_PORT << 4u) | + 133:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_8_PIN + 134:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 8u */ + 135:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 9u) + 136:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_9_PORT << 4u) | + 137:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_9_PIN + 138:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 9u */ + 139:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 10u) + 140:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_10_PORT << 4u) | + 141:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_10_PIN + 142:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 10u */ + 143:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 11u) + 144:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_11_PORT << 4u) | + 145:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_11_PIN + 146:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 11u */ + 147:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 12u) + 148:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_12_PORT << 4u) | + 149:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_12_PIN + 150:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 12u */ + 151:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 13u) + 152:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_13_PORT << 4u) | + 153:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_13_PIN + 154:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 13u */ + 155:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 14u) + 156:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_14_PORT << 4u) | + 157:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_14_PIN + 158:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 14u */ + 159:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 15u) + 160:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_15_PORT << 4u) | + 161:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_15_PIN + 162:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 15u */ + 163:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 16u) + 164:Generated_Source\PSoC4/ADC.c **** ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_16_PORT << 4u) | + 165:Generated_Source\PSoC4/ADC.c **** (uint8)ADC_cy_psoc4_sarmux_8__CH_16_PIN + 166:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 16u */ + 167:Generated_Source\PSoC4/ADC.c **** }; + 168:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */ + 169:Generated_Source\PSoC4/ADC.c **** + 170:Generated_Source\PSoC4/ADC.c **** #if(ADC_IRQ_REMOVE == 0u) + 171:Generated_Source\PSoC4/ADC.c **** /* Start and set interrupt vector */ + 172:Generated_Source\PSoC4/ADC.c **** CyIntSetPriority(ADC_INTC_NUMBER, ADC_INTC_PRIOR_NUMBER); + 99 .loc 1 172 0 + 100 0006 0321 movs r1, #3 + 101 0008 0E20 movs r0, #14 + 102 000a FFF7FEFF bl CyIntSetPriority + 173:Generated_Source\PSoC4/ADC.c **** (void)CyIntSetVector(ADC_INTC_NUMBER, &ADC_ISR); + 103 .loc 1 173 0 + 104 000e 574B ldr r3, .L17 + 105 0010 1900 movs r1, r3 + 106 0012 0E20 movs r0, #14 + 107 0014 FFF7FEFF bl CyIntSetVector + 174:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_IRQ_REMOVE */ + 175:Generated_Source\PSoC4/ADC.c **** + 176:Generated_Source\PSoC4/ADC.c **** /* Init SAR and MUX registers */ + 177:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CHAN_EN_REG = ADC_DEFAULT_EN_CHANNELS; + 108 .loc 1 177 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 6 + + + 109 0018 554B ldr r3, .L17+4 + 110 001a 0122 movs r2, #1 + 111 001c 1A60 str r2, [r3] + 178:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | + 179:Generated_Source\PSoC4/ADC.c **** /* Enable the SAR internal pump when global pump is enabled */ + 180:Generated_Source\PSoC4/ADC.c **** (((ADC_PUMP_CTRL_REG & ADC_PUMP_CTRL_ENABLED) != 0u) ? + 112 .loc 1 180 0 + 113 001e 554B ldr r3, .L17+8 + 114 0020 1B68 ldr r3, [r3] + 178:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | + 115 .loc 1 178 0 + 116 0022 002B cmp r3, #0 + 117 0024 01DA bge .L6 + 178:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | + 118 .loc 1 178 0 is_stmt 0 discriminator 1 + 119 0026 5449 ldr r1, .L17+12 + 120 0028 00E0 b .L7 + 121 .L6: + 178:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | + 122 .loc 1 178 0 discriminator 2 + 123 002a 5449 ldr r1, .L17+16 + 124 .L7: + 178:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | + 125 .loc 1 178 0 discriminator 4 + 126 002c 544B ldr r3, .L17+20 + 127 002e 544A ldr r2, .L17+20 + 128 0030 1268 ldr r2, [r2] + 129 0032 0A43 orrs r2, r1 + 130 0034 1A60 str r2, [r3] + 181:Generated_Source\PSoC4/ADC.c **** ADC_BOOSTPUMP_EN : 0u); + 182:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SAMPLE_CTRL_REG = ADC_DEFAULT_SAMPLE_CTRL_REG_CFG; + 131 .loc 1 182 0 is_stmt 1 discriminator 4 + 132 0036 534B ldr r3, .L17+24 + 133 0038 534A ldr r2, .L17+28 + 134 003a 1A60 str r2, [r3] + 183:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_THRES_REG = ADC_DEFAULT_RANGE_THRES_REG_CFG; + 135 .loc 1 183 0 discriminator 4 + 136 003c 534B ldr r3, .L17+32 + 137 003e 544A ldr r2, .L17+36 + 138 0040 1A60 str r2, [r3] + 184:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_COND_REG = ADC_COMPARE_MODE; + 139 .loc 1 184 0 discriminator 4 + 140 0042 544B ldr r3, .L17+40 + 141 0044 C022 movs r2, #192 + 142 0046 1206 lsls r2, r2, #24 + 143 0048 1A60 str r2, [r3] + 185:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SAMPLE_TIME01_REG = ADC_DEFAULT_SAMPLE_TIME01_REG_CFG; + 144 .loc 1 185 0 discriminator 4 + 145 004a 534B ldr r3, .L17+44 + 146 004c 534A ldr r2, .L17+48 + 147 004e 1A60 str r2, [r3] + 186:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SAMPLE_TIME23_REG = ADC_DEFAULT_SAMPLE_TIME23_REG_CFG; + 148 .loc 1 186 0 discriminator 4 + 149 0050 534B ldr r3, .L17+52 + 150 0052 524A ldr r2, .L17+48 + 151 0054 1A60 str r2, [r3] + 187:Generated_Source\PSoC4/ADC.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 7 + + + 188:Generated_Source\PSoC4/ADC.c **** /* Connect Vm to VSSA when even one channel is single-ended or multiple channels configured */ + 189:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_MUX_SWITCH0 != 0u) + 190:Generated_Source\PSoC4/ADC.c **** ADC_MUX_SWITCH0_REG |= ADC_DEFAULT_MUX_SWITCH0; + 152 .loc 1 190 0 discriminator 4 + 153 0056 534B ldr r3, .L17+56 + 154 0058 524A ldr r2, .L17+56 + 155 005a 1268 ldr r2, [r2] + 156 005c 8021 movs r1, #128 + 157 005e 4902 lsls r1, r1, #9 + 158 0060 0A43 orrs r2, r1 + 159 0062 1A60 str r2, [r3] + 191:Generated_Source\PSoC4/ADC.c **** /* Set MUX_HW_CTRL_VSSA in MUX_SWITCH_HW_CTRL when multiple channels enabled */ + 192:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 1u) + 193:Generated_Source\PSoC4/ADC.c **** ADC_MUX_SWITCH_HW_CTRL_REG |= ADC_DEFAULT_MUX_SWITCH0; + 194:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_TOTAL_CHANNELS_NUM > 1u */ + 195:Generated_Source\PSoC4/ADC.c **** #endif /*ADC_CHANNELS_MODE !=0 */ + 196:Generated_Source\PSoC4/ADC.c **** + 197:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SATURATE_INTR_MASK_REG = 0u; + 160 .loc 1 197 0 discriminator 4 + 161 0064 504B ldr r3, .L17+60 + 162 0066 0022 movs r2, #0 + 163 0068 1A60 str r2, [r3] + 198:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_INTR_MASK_REG = 0u; + 164 .loc 1 198 0 discriminator 4 + 165 006a 504B ldr r3, .L17+64 + 166 006c 0022 movs r2, #0 + 167 006e 1A60 str r2, [r3] + 199:Generated_Source\PSoC4/ADC.c **** ADC_SAR_INTR_MASK_REG = ADC_SAR_INTR_MASK; + 168 .loc 1 199 0 discriminator 4 + 169 0070 4F4B ldr r3, .L17+68 + 170 0072 0122 movs r2, #1 + 171 0074 1A60 str r2, [r3] + 200:Generated_Source\PSoC4/ADC.c **** + 201:Generated_Source\PSoC4/ADC.c **** #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) + 202:Generated_Source\PSoC4/ADC.c **** ADC_ANA_TRIM_REG = ADC_TRIM_COEF; + 172 .loc 1 202 0 discriminator 4 + 173 0076 4F4B ldr r3, .L17+72 + 174 0078 0222 movs r2, #2 + 175 007a 1A60 str r2, [r3] + 203:Generated_Source\PSoC4/ADC.c **** #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */ + 204:Generated_Source\PSoC4/ADC.c **** + 205:Generated_Source\PSoC4/ADC.c **** /* Read and modify default configuration based on characterization */ + 206:Generated_Source\PSoC4/ADC.c **** tmpRegVal = ADC_SAR_DFT_CTRL_REG; + 176 .loc 1 206 0 discriminator 4 + 177 007c 4E4B ldr r3, .L17+76 + 178 007e 1B68 ldr r3, [r3] + 179 0080 7B60 str r3, [r7, #4] + 207:Generated_Source\PSoC4/ADC.c **** tmpRegVal &= (uint32)~ADC_DCEN; + 180 .loc 1 207 0 discriminator 4 + 181 0082 7B68 ldr r3, [r7, #4] + 182 0084 4D4A ldr r2, .L17+80 + 183 0086 1340 ands r3, r2 + 184 0088 7B60 str r3, [r7, #4] + 208:Generated_Source\PSoC4/ADC.c **** + 209:Generated_Source\PSoC4/ADC.c **** #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) + 210:Generated_Source\PSoC4/ADC.c **** #if(ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 2)) + 211:Generated_Source\PSoC4/ADC.c **** tmpRegVal |= ADC_SEL_CSEL_DFT_CHAR; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 8 + + + 212:Generated_Source\PSoC4/ADC.c **** #else /* clock speed < 9 Mhz */ + 213:Generated_Source\PSoC4/ADC.c **** tmpRegVal |= ADC_DLY_INC; + 185 .loc 1 213 0 discriminator 4 + 186 008a 7B68 ldr r3, [r7, #4] + 187 008c 0122 movs r2, #1 + 188 008e 1343 orrs r3, r2 + 189 0090 7B60 str r3, [r7, #4] + 214:Generated_Source\PSoC4/ADC.c **** #endif /* clock speed > 9 Mhz */ + 215:Generated_Source\PSoC4/ADC.c **** #else + 216:Generated_Source\PSoC4/ADC.c **** #if ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \ + 217:Generated_Source\PSoC4/ADC.c **** (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)) + 218:Generated_Source\PSoC4/ADC.c **** tmpRegVal |= ADC_DLY_INC; + 219:Generated_Source\PSoC4/ADC.c **** #else + 220:Generated_Source\PSoC4/ADC.c **** tmpRegVal |= ADC_DCEN; + 221:Generated_Source\PSoC4/ADC.c **** tmpRegVal &= (uint32)~ADC_DLY_INC; + 222:Generated_Source\PSoC4/ADC.c **** #endif /* ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \ + 223:Generated_Source\PSoC4/ADC.c **** (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)) */ + 224:Generated_Source\PSoC4/ADC.c **** #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */ + 225:Generated_Source\PSoC4/ADC.c **** + 226:Generated_Source\PSoC4/ADC.c **** ADC_SAR_DFT_CTRL_REG = tmpRegVal; + 190 .loc 1 226 0 discriminator 4 + 191 0092 494B ldr r3, .L17+76 + 192 0094 7A68 ldr r2, [r7, #4] + 193 0096 1A60 str r2, [r3] + 227:Generated_Source\PSoC4/ADC.c **** + 228:Generated_Source\PSoC4/ADC.c **** #if(ADC_MAX_RESOLUTION != ADC_RESOLUTION_12) + 229:Generated_Source\PSoC4/ADC.c **** ADC_WOUNDING_REG = ADC_ALT_WOUNDING; + 230:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */ + 231:Generated_Source\PSoC4/ADC.c **** + 232:Generated_Source\PSoC4/ADC.c **** for(chNum = 0u; chNum < ADC_TOTAL_CHANNELS_NUM; chNum++) + 194 .loc 1 232 0 discriminator 4 + 195 0098 0023 movs r3, #0 + 196 009a FB60 str r3, [r7, #12] + 197 009c 5EE0 b .L8 + 198 .L16: + 233:Generated_Source\PSoC4/ADC.c **** { + 234:Generated_Source\PSoC4/ADC.c **** tmpRegVal = (ADC_channelsConfig[chNum] & ADC_CHANNEL_CONFIG_MASK); + 199 .loc 1 234 0 + 200 009e 484A ldr r2, .L17+84 + 201 00a0 DC23 movs r3, #220 + 202 00a2 9B01 lsls r3, r3, #6 + 203 00a4 1340 ands r3, r2 + 204 00a6 7B60 str r3, [r7, #4] + 235:Generated_Source\PSoC4/ADC.c **** #if(ADC_TOTAL_CHANNELS_NUM > 1u) + 236:Generated_Source\PSoC4/ADC.c **** tmpRegVal |= ADC_InputsPlacement[chNum]; + 237:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */ + 238:Generated_Source\PSoC4/ADC.c **** + 239:Generated_Source\PSoC4/ADC.c **** + 240:Generated_Source\PSoC4/ADC.c **** /* When the part is limited to 10-bit then the SUB_RESOLUTION bit + 241:Generated_Source\PSoC4/ADC.c **** * will be ignored and the RESOLUTION bit selects between 10-bit + 242:Generated_Source\PSoC4/ADC.c **** * (0) and 8-bit (1) resolution. + 243:Generated_Source\PSoC4/ADC.c **** */ + 244:Generated_Source\PSoC4/ADC.c **** #if((ADC_MAX_RESOLUTION != ADC_RESOLUTION_12) && \ + 245:Generated_Source\PSoC4/ADC.c **** (ADC_ALT_WOUNDING == ADC_WOUNDING_10BIT)) + 246:Generated_Source\PSoC4/ADC.c **** tmpRegVal &= (uint32)(~ADC_ALT_RESOLUTION_ON); + 247:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */ + 248:Generated_Source\PSoC4/ADC.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 9 + + + 249:Generated_Source\PSoC4/ADC.c **** #if(ADC_INJ_CHANNEL_ENABLED) + 250:Generated_Source\PSoC4/ADC.c **** if(chNum < ADC_SEQUENCED_CHANNELS_NUM) + 251:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_INJ_CHANNEL_ENABLED */ + 252:Generated_Source\PSoC4/ADC.c **** { + 253:Generated_Source\PSoC4/ADC.c **** CY_SET_REG32((reg32 *)(ADC_SAR_CHAN_CONFIG_IND + (uint32)(chNum << 2)), tmpRegVal); + 205 .loc 1 253 0 + 206 00a8 FB68 ldr r3, [r7, #12] + 207 00aa 9B00 lsls r3, r3, #2 + 208 00ac 454A ldr r2, .L17+88 + 209 00ae 9446 mov ip, r2 + 210 00b0 6344 add r3, r3, ip + 211 00b2 7A68 ldr r2, [r7, #4] + 212 00b4 1A60 str r2, [r3] + 254:Generated_Source\PSoC4/ADC.c **** + 255:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u) + 213 .loc 1 255 0 + 214 00b6 424A ldr r2, .L17+84 + 215 00b8 0123 movs r3, #1 + 216 00ba 1340 ands r3, r2 + 217 00bc 0AD0 beq .L9 + 256:Generated_Source\PSoC4/ADC.c **** { + 257:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SATURATE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + 218 .loc 1 257 0 + 219 00be 3A4B ldr r3, .L17+60 + 220 00c0 394A ldr r2, .L17+60 + 221 00c2 1168 ldr r1, [r2] + 222 00c4 0120 movs r0, #1 + 223 00c6 FA68 ldr r2, [r7, #12] + 224 00c8 9040 lsls r0, r0, r2 + 225 00ca 0200 movs r2, r0 + 226 00cc 1204 lsls r2, r2, #16 + 227 00ce 120C lsrs r2, r2, #16 + 228 00d0 0A43 orrs r2, r1 + 229 00d2 1A60 str r2, [r3] + 230 .L9: + 258:Generated_Source\PSoC4/ADC.c **** } + 259:Generated_Source\PSoC4/ADC.c **** + 260:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u) + 231 .loc 1 260 0 + 232 00d4 3A4A ldr r2, .L17+84 + 233 00d6 0223 movs r3, #2 + 234 00d8 1340 ands r3, r2 + 235 00da 0AD0 beq .L10 + 261:Generated_Source\PSoC4/ADC.c **** { + 262:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + 236 .loc 1 262 0 + 237 00dc 334B ldr r3, .L17+64 + 238 00de 334A ldr r2, .L17+64 + 239 00e0 1168 ldr r1, [r2] + 240 00e2 0120 movs r0, #1 + 241 00e4 FA68 ldr r2, [r7, #12] + 242 00e6 9040 lsls r0, r0, r2 + 243 00e8 0200 movs r2, r0 + 244 00ea 1204 lsls r2, r2, #16 + 245 00ec 120C lsrs r2, r2, #16 + 246 00ee 0A43 orrs r2, r1 + 247 00f0 1A60 str r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 10 + + + 248 .L10: + 263:Generated_Source\PSoC4/ADC.c **** } + 264:Generated_Source\PSoC4/ADC.c **** } + 265:Generated_Source\PSoC4/ADC.c **** #if(ADC_INJ_CHANNEL_ENABLED) + 266:Generated_Source\PSoC4/ADC.c **** else + 267:Generated_Source\PSoC4/ADC.c **** { + 268:Generated_Source\PSoC4/ADC.c **** CY_SET_REG32(ADC_SAR_INJ_CHAN_CONFIG_PTR, tmpRegVal | ADC_INJ_TAILGATING); + 269:Generated_Source\PSoC4/ADC.c **** + 270:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u) + 271:Generated_Source\PSoC4/ADC.c **** { + 272:Generated_Source\PSoC4/ADC.c **** ADC_SAR_INTR_MASK_REG |= ADC_INJ_SATURATE_MASK; + 273:Generated_Source\PSoC4/ADC.c **** } + 274:Generated_Source\PSoC4/ADC.c **** + 275:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u) + 276:Generated_Source\PSoC4/ADC.c **** { + 277:Generated_Source\PSoC4/ADC.c **** ADC_SAR_INTR_MASK_REG |= ADC_INJ_RANGE_MASK; + 278:Generated_Source\PSoC4/ADC.c **** } + 279:Generated_Source\PSoC4/ADC.c **** } + 280:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_INJ_CHANNEL_ENABLED */ + 281:Generated_Source\PSoC4/ADC.c **** + 282:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chNum] & ADC_ALT_RESOLUTION_ON) != 0u) + 249 .loc 1 282 0 + 250 00f2 334A ldr r2, .L17+84 + 251 00f4 8023 movs r3, #128 + 252 00f6 9B00 lsls r3, r3, #2 + 253 00f8 1340 ands r3, r2 + 254 00fa 03D0 beq .L11 + 283:Generated_Source\PSoC4/ADC.c **** { + 284:Generated_Source\PSoC4/ADC.c **** counts = (int32)ADC_DEFAULT_MAX_WRK_ALT; + 255 .loc 1 284 0 + 256 00fc 8023 movs r3, #128 + 257 00fe 5B00 lsls r3, r3, #1 + 258 0100 BB60 str r3, [r7, #8] + 259 0102 02E0 b .L12 + 260 .L11: + 285:Generated_Source\PSoC4/ADC.c **** } + 286:Generated_Source\PSoC4/ADC.c **** else + 287:Generated_Source\PSoC4/ADC.c **** { + 288:Generated_Source\PSoC4/ADC.c **** counts = (int32)ADC_SAR_WRK_MAX_12BIT; + 261 .loc 1 288 0 + 262 0104 8023 movs r3, #128 + 263 0106 5B01 lsls r3, r3, #5 + 264 0108 BB60 str r3, [r7, #8] + 265 .L12: + 289:Generated_Source\PSoC4/ADC.c **** } + 290:Generated_Source\PSoC4/ADC.c **** + 291:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chNum] & ADC_DIFFERENTIAL_EN) == 0u) + 266 .loc 1 291 0 + 267 010a 2D4A ldr r2, .L17+84 + 268 010c 8023 movs r3, #128 + 269 010e 5B00 lsls r3, r3, #1 + 270 0110 1340 ands r3, r2 + 271 0112 05D1 bne .L13 + 292:Generated_Source\PSoC4/ADC.c **** { + 293:Generated_Source\PSoC4/ADC.c **** #if((ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED) && \ + 294:Generated_Source\PSoC4/ADC.c **** (ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF)) + 295:Generated_Source\PSoC4/ADC.c **** /* Set offset to the minus half scale to convert results to unsigned format */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 11 + + + 296:Generated_Source\PSoC4/ADC.c **** ADC_offset[chNum] = (int16)(counts / -2); + 297:Generated_Source\PSoC4/ADC.c **** #else + 298:Generated_Source\PSoC4/ADC.c **** ADC_offset[chNum] = 0; + 272 .loc 1 298 0 + 273 0114 2C4B ldr r3, .L17+92 + 274 0116 FA68 ldr r2, [r7, #12] + 275 0118 5200 lsls r2, r2, #1 + 276 011a 0021 movs r1, #0 + 277 011c D152 strh r1, [r2, r3] + 278 011e 09E0 b .L14 + 279 .L13: + 299:Generated_Source\PSoC4/ADC.c **** #endif /* end DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED */ + 300:Generated_Source\PSoC4/ADC.c **** } + 301:Generated_Source\PSoC4/ADC.c **** else /* Differential channel */ + 302:Generated_Source\PSoC4/ADC.c **** { + 303:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED) + 304:Generated_Source\PSoC4/ADC.c **** /* Set offset to the half scale to convert results to signed format */ + 305:Generated_Source\PSoC4/ADC.c **** ADC_offset[chNum] = (int16)(counts / 2); + 280 .loc 1 305 0 + 281 0120 BB68 ldr r3, [r7, #8] + 282 0122 002B cmp r3, #0 + 283 0124 00DA bge .L15 + 284 0126 0133 adds r3, r3, #1 + 285 .L15: + 286 0128 5B10 asrs r3, r3, #1 + 287 012a 19B2 sxth r1, r3 + 288 012c 264B ldr r3, .L17+92 + 289 012e FA68 ldr r2, [r7, #12] + 290 0130 5200 lsls r2, r2, #1 + 291 0132 D152 strh r1, [r2, r3] + 292 .L14: + 306:Generated_Source\PSoC4/ADC.c **** #else + 307:Generated_Source\PSoC4/ADC.c **** ADC_offset[chNum] = 0; + 308:Generated_Source\PSoC4/ADC.c **** #endif /* end ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED */ + 309:Generated_Source\PSoC4/ADC.c **** } + 310:Generated_Source\PSoC4/ADC.c **** /* Calculate gain in counts per 10 volts with rounding */ + 311:Generated_Source\PSoC4/ADC.c **** ADC_countsPer10Volt[chNum] = (int16)(((counts * ADC_10MV_COUNTS) + + 293 .loc 1 311 0 discriminator 2 + 294 0134 BB68 ldr r3, [r7, #8] + 295 0136 254A ldr r2, .L17+96 + 296 0138 5343 muls r3, r2 + 297 013a 254A ldr r2, .L17+100 + 298 013c 9446 mov ip, r2 + 299 013e 6344 add r3, r3, ip + 312:Generated_Source\PSoC4/ADC.c **** ADC_DEFAULT_VREF_MV_VALUE) / (ADC_DEFAULT_VREF_MV_VALUE * 2)); + 300 .loc 1 312 0 discriminator 2 + 301 0140 2249 ldr r1, .L17+96 + 302 0142 1800 movs r0, r3 + 303 0144 FFF7FEFF bl __aeabi_idiv + 304 0148 0300 movs r3, r0 + 311:Generated_Source\PSoC4/ADC.c **** ADC_DEFAULT_VREF_MV_VALUE) / (ADC_DEFAULT_VREF_MV_VALUE * 2)); + 305 .loc 1 311 0 discriminator 2 + 306 014a 1BB2 sxth r3, r3 + 307 014c 1900 movs r1, r3 + 308 014e 214B ldr r3, .L17+104 + 309 0150 FA68 ldr r2, [r7, #12] + 310 0152 9200 lsls r2, r2, #2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 12 + + + 311 0154 D150 str r1, [r2, r3] + 232:Generated_Source\PSoC4/ADC.c **** { + 312 .loc 1 232 0 discriminator 2 + 313 0156 FB68 ldr r3, [r7, #12] + 314 0158 0133 adds r3, r3, #1 + 315 015a FB60 str r3, [r7, #12] + 316 .L8: + 232:Generated_Source\PSoC4/ADC.c **** { + 317 .loc 1 232 0 is_stmt 0 discriminator 1 + 318 015c FB68 ldr r3, [r7, #12] + 319 015e 002B cmp r3, #0 + 320 0160 9DD0 beq .L16 + 313:Generated_Source\PSoC4/ADC.c **** } + 314:Generated_Source\PSoC4/ADC.c **** } + 321 .loc 1 314 0 is_stmt 1 + 322 0162 C046 nop + 323 0164 BD46 mov sp, r7 + 324 0166 04B0 add sp, sp, #16 + 325 @ sp needed + 326 0168 80BD pop {r7, pc} + 327 .L18: + 328 016a C046 .align 2 + 329 .L17: + 330 016c 00000000 .word ADC_ISR + 331 0170 20001A40 .word 1075445792 + 332 0174 80031A40 .word 1075446656 + 333 0178 70021053 .word 1393558128 + 334 017c 70020053 .word 1392509552 + 335 0180 00001A40 .word 1075445760 + 336 0184 04001A40 .word 1075445764 + 337 0188 F4000080 .word -2147483404 + 338 018c 18001A40 .word 1075445784 + 339 0190 FF01FE05 .word 100532735 + 340 0194 1C001A40 .word 1075445788 + 341 0198 10001A40 .word 1075445776 + 342 019c 02000200 .word 131074 + 343 01a0 14001A40 .word 1075445780 + 344 01a4 00031A40 .word 1075446528 + 345 01a8 28021A40 .word 1075446312 + 346 01ac 38021A40 .word 1075446328 + 347 01b0 18021A40 .word 1075446296 + 348 01b4 000F1A40 .word 1075449600 + 349 01b8 30001A40 .word 1075445808 + 350 01bc FFFFFFDF .word -536870913 + 351 01c0 02040000 .word 1026 + 352 01c4 80001A40 .word 1075445888 + 353 01c8 00000000 .word ADC_offset + 354 01cc 10270000 .word 10000 + 355 01d0 88130000 .word 5000 + 356 01d4 00000000 .word ADC_countsPer10Volt + 357 .cfi_endproc + 358 .LFE1: + 359 .size ADC_Init, .-ADC_Init + 360 .section .text.ADC_Enable,"ax",%progbits + 361 .align 2 + 362 .global ADC_Enable + 363 .code 16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 13 + + + 364 .thumb_func + 365 .type ADC_Enable, %function + 366 ADC_Enable: + 367 .LFB2: + 315:Generated_Source\PSoC4/ADC.c **** + 316:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 317:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SAR_1_Enable + 318:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 319:Generated_Source\PSoC4/ADC.c **** * + 320:Generated_Source\PSoC4/ADC.c **** * Summary: + 321:Generated_Source\PSoC4/ADC.c **** * Enables the clock and analog power for SAR ADC. + 322:Generated_Source\PSoC4/ADC.c **** * + 323:Generated_Source\PSoC4/ADC.c **** * Parameters: + 324:Generated_Source\PSoC4/ADC.c **** * None. + 325:Generated_Source\PSoC4/ADC.c **** * + 326:Generated_Source\PSoC4/ADC.c **** * Return: + 327:Generated_Source\PSoC4/ADC.c **** * None. + 328:Generated_Source\PSoC4/ADC.c **** * + 329:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 330:Generated_Source\PSoC4/ADC.c **** void ADC_Enable(void) + 331:Generated_Source\PSoC4/ADC.c **** { + 368 .loc 1 331 0 + 369 .cfi_startproc + 370 @ args = 0, pretend = 0, frame = 0 + 371 @ frame_needed = 1, uses_anonymous_args = 0 + 372 0000 80B5 push {r7, lr} + 373 .cfi_def_cfa_offset 8 + 374 .cfi_offset 7, -8 + 375 .cfi_offset 14, -4 + 376 0002 00AF add r7, sp, #0 + 377 .cfi_def_cfa_register 7 + 332:Generated_Source\PSoC4/ADC.c **** if (0u == (ADC_SAR_CTRL_REG & ADC_ENABLE)) + 378 .loc 1 332 0 + 379 0004 084B ldr r3, .L22 + 380 0006 1B68 ldr r3, [r3] + 381 0008 002B cmp r3, #0 + 382 000a 09DB blt .L21 + 333:Generated_Source\PSoC4/ADC.c **** { + 334:Generated_Source\PSoC4/ADC.c **** #if(ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) + 335:Generated_Source\PSoC4/ADC.c **** + 336:Generated_Source\PSoC4/ADC.c **** while (0u != (ADC_SAR_STATUS_REG & ADC_STATUS_BUSY)) + 337:Generated_Source\PSoC4/ADC.c **** { + 338:Generated_Source\PSoC4/ADC.c **** /* wait for SAR to go idle to avoid deadlock */ + 339:Generated_Source\PSoC4/ADC.c **** } + 340:Generated_Source\PSoC4/ADC.c **** #endif /* (ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) */ + 341:Generated_Source\PSoC4/ADC.c **** + 342:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CTRL_REG |= ADC_ENABLE; + 383 .loc 1 342 0 + 384 000c 064B ldr r3, .L22 + 385 000e 064A ldr r2, .L22 + 386 0010 1268 ldr r2, [r2] + 387 0012 8021 movs r1, #128 + 388 0014 0906 lsls r1, r1, #24 + 389 0016 0A43 orrs r2, r1 + 390 0018 1A60 str r2, [r3] + 343:Generated_Source\PSoC4/ADC.c **** + 344:Generated_Source\PSoC4/ADC.c **** /* The block is ready to use 10 us after the enable signal is set high. */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 14 + + + 345:Generated_Source\PSoC4/ADC.c **** CyDelayUs(ADC_10US_DELAY); + 391 .loc 1 345 0 + 392 001a 0A20 movs r0, #10 + 393 001c FFF7FEFF bl CyDelayUs + 394 .L21: + 346:Generated_Source\PSoC4/ADC.c **** } + 347:Generated_Source\PSoC4/ADC.c **** } + 395 .loc 1 347 0 + 396 0020 C046 nop + 397 0022 BD46 mov sp, r7 + 398 @ sp needed + 399 0024 80BD pop {r7, pc} + 400 .L23: + 401 0026 C046 .align 2 + 402 .L22: + 403 0028 00001A40 .word 1075445760 + 404 .cfi_endproc + 405 .LFE2: + 406 .size ADC_Enable, .-ADC_Enable + 407 .section .text.ADC_Stop,"ax",%progbits + 408 .align 2 + 409 .global ADC_Stop + 410 .code 16 + 411 .thumb_func + 412 .type ADC_Stop, %function + 413 ADC_Stop: + 414 .LFB3: + 348:Generated_Source\PSoC4/ADC.c **** + 349:Generated_Source\PSoC4/ADC.c **** + 350:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 351:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_Stop + 352:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 353:Generated_Source\PSoC4/ADC.c **** * + 354:Generated_Source\PSoC4/ADC.c **** * Summary: + 355:Generated_Source\PSoC4/ADC.c **** * This function stops ADC conversions and puts the ADC into its lowest power + 356:Generated_Source\PSoC4/ADC.c **** * mode. + 357:Generated_Source\PSoC4/ADC.c **** * + 358:Generated_Source\PSoC4/ADC.c **** * Parameters: + 359:Generated_Source\PSoC4/ADC.c **** * None. + 360:Generated_Source\PSoC4/ADC.c **** * + 361:Generated_Source\PSoC4/ADC.c **** * Return: + 362:Generated_Source\PSoC4/ADC.c **** * None. + 363:Generated_Source\PSoC4/ADC.c **** * + 364:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 365:Generated_Source\PSoC4/ADC.c **** void ADC_Stop(void) + 366:Generated_Source\PSoC4/ADC.c **** { + 415 .loc 1 366 0 + 416 .cfi_startproc + 417 @ args = 0, pretend = 0, frame = 0 + 418 @ frame_needed = 1, uses_anonymous_args = 0 + 419 0000 80B5 push {r7, lr} + 420 .cfi_def_cfa_offset 8 + 421 .cfi_offset 7, -8 + 422 .cfi_offset 14, -4 + 423 0002 00AF add r7, sp, #0 + 424 .cfi_def_cfa_register 7 + 367:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CTRL_REG &= (uint32)~ADC_ENABLE; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 15 + + + 425 .loc 1 367 0 + 426 0004 044B ldr r3, .L25 + 427 0006 044A ldr r2, .L25 + 428 0008 1268 ldr r2, [r2] + 429 000a 5200 lsls r2, r2, #1 + 430 000c 5208 lsrs r2, r2, #1 + 431 000e 1A60 str r2, [r3] + 368:Generated_Source\PSoC4/ADC.c **** } + 432 .loc 1 368 0 + 433 0010 C046 nop + 434 0012 BD46 mov sp, r7 + 435 @ sp needed + 436 0014 80BD pop {r7, pc} + 437 .L26: + 438 0016 C046 .align 2 + 439 .L25: + 440 0018 00001A40 .word 1075445760 + 441 .cfi_endproc + 442 .LFE3: + 443 .size ADC_Stop, .-ADC_Stop + 444 .section .text.ADC_StartConvert,"ax",%progbits + 445 .align 2 + 446 .global ADC_StartConvert + 447 .code 16 + 448 .thumb_func + 449 .type ADC_StartConvert, %function + 450 ADC_StartConvert: + 451 .LFB4: + 369:Generated_Source\PSoC4/ADC.c **** + 370:Generated_Source\PSoC4/ADC.c **** + 371:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 372:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_StartConvert + 373:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 374:Generated_Source\PSoC4/ADC.c **** * + 375:Generated_Source\PSoC4/ADC.c **** * Summary: + 376:Generated_Source\PSoC4/ADC.c **** * Description: + 377:Generated_Source\PSoC4/ADC.c **** * For free running mode, this API starts the conversion process and it + 378:Generated_Source\PSoC4/ADC.c **** * runs continuously. + 379:Generated_Source\PSoC4/ADC.c **** * + 380:Generated_Source\PSoC4/ADC.c **** * In a triggered mode, this routine triggers every conversion by + 381:Generated_Source\PSoC4/ADC.c **** * writing into the FW_TRIGGER bit in SAR_START_CTRL reg. In triggered mode, + 382:Generated_Source\PSoC4/ADC.c **** * every conversion has to start by this API. + 383:Generated_Source\PSoC4/ADC.c **** * + 384:Generated_Source\PSoC4/ADC.c **** * Parameters: + 385:Generated_Source\PSoC4/ADC.c **** * None. + 386:Generated_Source\PSoC4/ADC.c **** * + 387:Generated_Source\PSoC4/ADC.c **** * Return: + 388:Generated_Source\PSoC4/ADC.c **** * None. + 389:Generated_Source\PSoC4/ADC.c **** * + 390:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 391:Generated_Source\PSoC4/ADC.c **** void ADC_StartConvert(void) + 392:Generated_Source\PSoC4/ADC.c **** { + 452 .loc 1 392 0 + 453 .cfi_startproc + 454 @ args = 0, pretend = 0, frame = 0 + 455 @ frame_needed = 1, uses_anonymous_args = 0 + 456 0000 80B5 push {r7, lr} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 16 + + + 457 .cfi_def_cfa_offset 8 + 458 .cfi_offset 7, -8 + 459 .cfi_offset 14, -4 + 460 0002 00AF add r7, sp, #0 + 461 .cfi_def_cfa_register 7 + 393:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + 394:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SAMPLE_CTRL_REG |= ADC_CONTINUOUS_EN; + 462 .loc 1 394 0 + 463 0004 044B ldr r3, .L28 + 464 0006 044A ldr r2, .L28 + 465 0008 1268 ldr r2, [r2] + 466 000a 8021 movs r1, #128 + 467 000c 4902 lsls r1, r1, #9 + 468 000e 0A43 orrs r2, r1 + 469 0010 1A60 str r2, [r3] + 395:Generated_Source\PSoC4/ADC.c **** #else /* Firmware trigger */ + 396:Generated_Source\PSoC4/ADC.c **** ADC_SAR_START_CTRL_REG = ADC_FW_TRIGGER; + 397:Generated_Source\PSoC4/ADC.c **** #endif /* End ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ + 398:Generated_Source\PSoC4/ADC.c **** + 399:Generated_Source\PSoC4/ADC.c **** } + 470 .loc 1 399 0 + 471 0012 C046 nop + 472 0014 BD46 mov sp, r7 + 473 @ sp needed + 474 0016 80BD pop {r7, pc} + 475 .L29: + 476 .align 2 + 477 .L28: + 478 0018 04001A40 .word 1075445764 + 479 .cfi_endproc + 480 .LFE4: + 481 .size ADC_StartConvert, .-ADC_StartConvert + 482 .section .text.ADC_StopConvert,"ax",%progbits + 483 .align 2 + 484 .global ADC_StopConvert + 485 .code 16 + 486 .thumb_func + 487 .type ADC_StopConvert, %function + 488 ADC_StopConvert: + 489 .LFB5: + 400:Generated_Source\PSoC4/ADC.c **** + 401:Generated_Source\PSoC4/ADC.c **** + 402:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 403:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_StopConvert + 404:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 405:Generated_Source\PSoC4/ADC.c **** * + 406:Generated_Source\PSoC4/ADC.c **** * Summary: + 407:Generated_Source\PSoC4/ADC.c **** * Forces the ADC to stop all conversions. + 408:Generated_Source\PSoC4/ADC.c **** * + 409:Generated_Source\PSoC4/ADC.c **** * Parameters: + 410:Generated_Source\PSoC4/ADC.c **** * None. + 411:Generated_Source\PSoC4/ADC.c **** * + 412:Generated_Source\PSoC4/ADC.c **** * Return: + 413:Generated_Source\PSoC4/ADC.c **** * None. + 414:Generated_Source\PSoC4/ADC.c **** * + 415:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 416:Generated_Source\PSoC4/ADC.c **** void ADC_StopConvert(void) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 17 + + + 417:Generated_Source\PSoC4/ADC.c **** { + 490 .loc 1 417 0 + 491 .cfi_startproc + 492 @ args = 0, pretend = 0, frame = 0 + 493 @ frame_needed = 1, uses_anonymous_args = 0 + 494 0000 80B5 push {r7, lr} + 495 .cfi_def_cfa_offset 8 + 496 .cfi_offset 7, -8 + 497 .cfi_offset 14, -4 + 498 0002 00AF add r7, sp, #0 + 499 .cfi_def_cfa_register 7 + 418:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + 419:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SAMPLE_CTRL_REG &= (uint32)(~ADC_CONTINUOUS_EN); + 500 .loc 1 419 0 + 501 0004 044B ldr r3, .L31 + 502 0006 044A ldr r2, .L31 + 503 0008 1268 ldr r2, [r2] + 504 000a 0449 ldr r1, .L31+4 + 505 000c 0A40 ands r2, r1 + 506 000e 1A60 str r2, [r3] + 420:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ + 421:Generated_Source\PSoC4/ADC.c **** } + 507 .loc 1 421 0 + 508 0010 C046 nop + 509 0012 BD46 mov sp, r7 + 510 @ sp needed + 511 0014 80BD pop {r7, pc} + 512 .L32: + 513 0016 C046 .align 2 + 514 .L31: + 515 0018 04001A40 .word 1075445764 + 516 001c FFFFFEFF .word -65537 + 517 .cfi_endproc + 518 .LFE5: + 519 .size ADC_StopConvert, .-ADC_StopConvert + 520 .section .text.ADC_IsEndConversion,"ax",%progbits + 521 .align 2 + 522 .global ADC_IsEndConversion + 523 .code 16 + 524 .thumb_func + 525 .type ADC_IsEndConversion, %function + 526 ADC_IsEndConversion: + 527 .LFB6: + 422:Generated_Source\PSoC4/ADC.c **** + 423:Generated_Source\PSoC4/ADC.c **** + 424:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 425:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_IsEndConversion + 426:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 427:Generated_Source\PSoC4/ADC.c **** * + 428:Generated_Source\PSoC4/ADC.c **** * Summary: + 429:Generated_Source\PSoC4/ADC.c **** * Description: Checks for ADC end of conversion for the case one + 430:Generated_Source\PSoC4/ADC.c **** * channel and end of scan for the case of multiple channels. It acts + 431:Generated_Source\PSoC4/ADC.c **** * as a software version of the EOC. This function provides the + 432:Generated_Source\PSoC4/ADC.c **** * programmer with two options. In one mode this function + 433:Generated_Source\PSoC4/ADC.c **** * immediately returns with the conversion status. In the other mode, + 434:Generated_Source\PSoC4/ADC.c **** * the function does not return (blocking) until the conversion has + 435:Generated_Source\PSoC4/ADC.c **** * completed. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 18 + + + 436:Generated_Source\PSoC4/ADC.c **** * + 437:Generated_Source\PSoC4/ADC.c **** * Parameters: + 438:Generated_Source\PSoC4/ADC.c **** * ADC_RETURN_STATUS -> Immediately returns conversion result status + 439:Generated_Source\PSoC4/ADC.c **** * ADC_WAIT_FOR_RESULT -> Does not return until ADC complete + 440:Generated_Source\PSoC4/ADC.c **** * ADC_RETURN_STATUS_INJ -> Immediately returns conversion result status + 441:Generated_Source\PSoC4/ADC.c **** * for injection channel + 442:Generated_Source\PSoC4/ADC.c **** * ADC_WAIT_FOR_RESULT_INJ -> Does not return until ADC completes injection + 443:Generated_Source\PSoC4/ADC.c **** * channel conversion + 444:Generated_Source\PSoC4/ADC.c **** * + 445:Generated_Source\PSoC4/ADC.c **** * Return: + 446:Generated_Source\PSoC4/ADC.c **** * If a non-zero value is returned, the last conversion or scan has completed. + 447:Generated_Source\PSoC4/ADC.c **** * If the returned value is zero, the ADC is still in the process of a scan. + 448:Generated_Source\PSoC4/ADC.c **** * + 449:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 450:Generated_Source\PSoC4/ADC.c **** uint32 ADC_IsEndConversion(uint32 retMode) + 451:Generated_Source\PSoC4/ADC.c **** { + 528 .loc 1 451 0 + 529 .cfi_startproc + 530 @ args = 0, pretend = 0, frame = 16 + 531 @ frame_needed = 1, uses_anonymous_args = 0 + 532 0000 80B5 push {r7, lr} + 533 .cfi_def_cfa_offset 8 + 534 .cfi_offset 7, -8 + 535 .cfi_offset 14, -4 + 536 0002 84B0 sub sp, sp, #16 + 537 .cfi_def_cfa_offset 24 + 538 0004 00AF add r7, sp, #0 + 539 .cfi_def_cfa_register 7 + 540 0006 7860 str r0, [r7, #4] + 452:Generated_Source\PSoC4/ADC.c **** uint32 status = 0u; + 541 .loc 1 452 0 + 542 0008 0023 movs r3, #0 + 543 000a FB60 str r3, [r7, #12] + 453:Generated_Source\PSoC4/ADC.c **** + 454:Generated_Source\PSoC4/ADC.c **** if((retMode & (ADC_RETURN_STATUS | ADC_WAIT_FOR_RESULT)) != 0u) + 544 .loc 1 454 0 + 545 000c 7B68 ldr r3, [r7, #4] + 546 000e 0322 movs r2, #3 + 547 0010 1340 ands r3, r2 + 548 0012 11D0 beq .L34 + 549 .L36: + 455:Generated_Source\PSoC4/ADC.c **** { + 456:Generated_Source\PSoC4/ADC.c **** do + 457:Generated_Source\PSoC4/ADC.c **** { + 458:Generated_Source\PSoC4/ADC.c **** status = ADC_SAR_INTR_REG & ADC_EOS_MASK; + 550 .loc 1 458 0 discriminator 2 + 551 0014 0B4B ldr r3, .L38 + 552 0016 1B68 ldr r3, [r3] + 553 0018 0122 movs r2, #1 + 554 001a 1340 ands r3, r2 + 555 001c FB60 str r3, [r7, #12] + 459:Generated_Source\PSoC4/ADC.c **** }while((status == 0u) && ((retMode & ADC_WAIT_FOR_RESULT) != 0u)); + 556 .loc 1 459 0 discriminator 2 + 557 001e FB68 ldr r3, [r7, #12] + 558 0020 002B cmp r3, #0 + 559 0022 03D1 bne .L35 + 560 .loc 1 459 0 is_stmt 0 discriminator 1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 19 + + + 561 0024 7B68 ldr r3, [r7, #4] + 562 0026 0222 movs r2, #2 + 563 0028 1340 ands r3, r2 + 564 002a F3D1 bne .L36 + 565 .L35: + 460:Generated_Source\PSoC4/ADC.c **** + 461:Generated_Source\PSoC4/ADC.c **** if(status != 0u) + 566 .loc 1 461 0 is_stmt 1 + 567 002c FB68 ldr r3, [r7, #12] + 568 002e 002B cmp r3, #0 + 569 0030 02D0 beq .L34 + 462:Generated_Source\PSoC4/ADC.c **** { + 463:Generated_Source\PSoC4/ADC.c **** /* Clear EOS bit */ + 464:Generated_Source\PSoC4/ADC.c **** ADC_SAR_INTR_REG = ADC_EOS_MASK; + 570 .loc 1 464 0 + 571 0032 044B ldr r3, .L38 + 572 0034 0122 movs r2, #1 + 573 0036 1A60 str r2, [r3] + 574 .L34: + 465:Generated_Source\PSoC4/ADC.c **** } + 466:Generated_Source\PSoC4/ADC.c **** } + 467:Generated_Source\PSoC4/ADC.c **** + 468:Generated_Source\PSoC4/ADC.c **** #if(ADC_INJ_CHANNEL_ENABLED) + 469:Generated_Source\PSoC4/ADC.c **** if((retMode & (ADC_RETURN_STATUS_INJ | ADC_WAIT_FOR_RESULT_INJ)) != 0u) + 470:Generated_Source\PSoC4/ADC.c **** { + 471:Generated_Source\PSoC4/ADC.c **** do + 472:Generated_Source\PSoC4/ADC.c **** { + 473:Generated_Source\PSoC4/ADC.c **** status |= ADC_SAR_INTR_REG & ADC_INJ_EOC_MASK; + 474:Generated_Source\PSoC4/ADC.c **** }while(((status & ADC_INJ_EOC_MASK) == 0u) && + 475:Generated_Source\PSoC4/ADC.c **** ((retMode & ADC_WAIT_FOR_RESULT_INJ) != 0u)); + 476:Generated_Source\PSoC4/ADC.c **** + 477:Generated_Source\PSoC4/ADC.c **** if((status & ADC_INJ_EOC_MASK) != 0u) + 478:Generated_Source\PSoC4/ADC.c **** { + 479:Generated_Source\PSoC4/ADC.c **** /* Clear Injection EOS bit */ + 480:Generated_Source\PSoC4/ADC.c **** ADC_SAR_INTR_REG = ADC_INJ_EOC_MASK; + 481:Generated_Source\PSoC4/ADC.c **** } + 482:Generated_Source\PSoC4/ADC.c **** } + 483:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_INJ_CHANNEL_ENABLED */ + 484:Generated_Source\PSoC4/ADC.c **** + 485:Generated_Source\PSoC4/ADC.c **** return (status); + 575 .loc 1 485 0 + 576 0038 FB68 ldr r3, [r7, #12] + 486:Generated_Source\PSoC4/ADC.c **** } + 577 .loc 1 486 0 + 578 003a 1800 movs r0, r3 + 579 003c BD46 mov sp, r7 + 580 003e 04B0 add sp, sp, #16 + 581 @ sp needed + 582 0040 80BD pop {r7, pc} + 583 .L39: + 584 0042 C046 .align 2 + 585 .L38: + 586 0044 10021A40 .word 1075446288 + 587 .cfi_endproc + 588 .LFE6: + 589 .size ADC_IsEndConversion, .-ADC_IsEndConversion + 590 .section .text.ADC_GetResult16,"ax",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 20 + + + 591 .align 2 + 592 .global ADC_GetResult16 + 593 .code 16 + 594 .thumb_func + 595 .type ADC_GetResult16, %function + 596 ADC_GetResult16: + 597 .LFB7: + 487:Generated_Source\PSoC4/ADC.c **** + 488:Generated_Source\PSoC4/ADC.c **** + 489:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 490:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_GetResult16 + 491:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 492:Generated_Source\PSoC4/ADC.c **** * + 493:Generated_Source\PSoC4/ADC.c **** * Summary: + 494:Generated_Source\PSoC4/ADC.c **** * Gets the data available in the SAR DATA register. + 495:Generated_Source\PSoC4/ADC.c **** * + 496:Generated_Source\PSoC4/ADC.c **** * Parameters: + 497:Generated_Source\PSoC4/ADC.c **** * chan: The ADC channel in which to return the result. The first channel + 498:Generated_Source\PSoC4/ADC.c **** * is 0 and the injection channel if enabled is the number of valid channels. + 499:Generated_Source\PSoC4/ADC.c **** * + 500:Generated_Source\PSoC4/ADC.c **** * Return: + 501:Generated_Source\PSoC4/ADC.c **** * Returns converted data as a signed 16-bit integer + 502:Generated_Source\PSoC4/ADC.c **** * + 503:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 504:Generated_Source\PSoC4/ADC.c **** int16 ADC_GetResult16(uint32 chan) + 505:Generated_Source\PSoC4/ADC.c **** { + 598 .loc 1 505 0 + 599 .cfi_startproc + 600 @ args = 0, pretend = 0, frame = 16 + 601 @ frame_needed = 1, uses_anonymous_args = 0 + 602 0000 80B5 push {r7, lr} + 603 .cfi_def_cfa_offset 8 + 604 .cfi_offset 7, -8 + 605 .cfi_offset 14, -4 + 606 0002 84B0 sub sp, sp, #16 + 607 .cfi_def_cfa_offset 24 + 608 0004 00AF add r7, sp, #0 + 609 .cfi_def_cfa_register 7 + 610 0006 7860 str r0, [r7, #4] + 506:Generated_Source\PSoC4/ADC.c **** uint32 result; + 507:Generated_Source\PSoC4/ADC.c **** + 508:Generated_Source\PSoC4/ADC.c **** /* Halt CPU in debug mode if channel is out of valid range */ + 509:Generated_Source\PSoC4/ADC.c **** CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + 611 .loc 1 509 0 + 612 0008 7B68 ldr r3, [r7, #4] + 613 000a 002B cmp r3, #0 + 614 000c 02D0 beq .L41 + 615 .loc 1 509 0 is_stmt 0 discriminator 1 + 616 000e 0020 movs r0, #0 + 617 0010 FFF7FEFF bl CyHalt + 618 .L41: + 510:Generated_Source\PSoC4/ADC.c **** + 511:Generated_Source\PSoC4/ADC.c **** if(chan < ADC_SEQUENCED_CHANNELS_NUM) + 619 .loc 1 511 0 is_stmt 1 + 620 0014 7B68 ldr r3, [r7, #4] + 621 0016 002B cmp r3, #0 + 622 0018 09D1 bne .L42 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 21 + + + 512:Generated_Source\PSoC4/ADC.c **** { + 513:Generated_Source\PSoC4/ADC.c **** result = CY_GET_REG32((reg32 *)(ADC_SAR_CHAN_RESULT_IND + (uint32)(chan << 2u))) & + 623 .loc 1 513 0 + 624 001a 7B68 ldr r3, [r7, #4] + 625 001c 9B00 lsls r3, r3, #2 + 626 001e 084A ldr r2, .L45 + 627 0020 9446 mov ip, r2 + 628 0022 6344 add r3, r3, ip + 629 0024 1B68 ldr r3, [r3] + 630 0026 1B04 lsls r3, r3, #16 + 631 0028 1B0C lsrs r3, r3, #16 + 632 002a FB60 str r3, [r7, #12] + 633 002c 01E0 b .L43 + 634 .L42: + 514:Generated_Source\PSoC4/ADC.c **** ADC_RESULT_MASK; + 515:Generated_Source\PSoC4/ADC.c **** } + 516:Generated_Source\PSoC4/ADC.c **** else + 517:Generated_Source\PSoC4/ADC.c **** { + 518:Generated_Source\PSoC4/ADC.c **** #if(ADC_INJ_CHANNEL_ENABLED) + 519:Generated_Source\PSoC4/ADC.c **** result = ADC_SAR_INJ_RESULT_REG & ADC_RESULT_MASK; + 520:Generated_Source\PSoC4/ADC.c **** #else + 521:Generated_Source\PSoC4/ADC.c **** result = 0u; + 635 .loc 1 521 0 + 636 002e 0023 movs r3, #0 + 637 0030 FB60 str r3, [r7, #12] + 638 .L43: + 522:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_INJ_CHANNEL_ENABLED */ + 523:Generated_Source\PSoC4/ADC.c **** } + 524:Generated_Source\PSoC4/ADC.c **** + 525:Generated_Source\PSoC4/ADC.c **** return ( (int16)result ); + 639 .loc 1 525 0 + 640 0032 FB68 ldr r3, [r7, #12] + 641 0034 1BB2 sxth r3, r3 + 526:Generated_Source\PSoC4/ADC.c **** } + 642 .loc 1 526 0 + 643 0036 1800 movs r0, r3 + 644 0038 BD46 mov sp, r7 + 645 003a 04B0 add sp, sp, #16 + 646 @ sp needed + 647 003c 80BD pop {r7, pc} + 648 .L46: + 649 003e C046 .align 2 + 650 .L45: + 651 0040 80011A40 .word 1075446144 + 652 .cfi_endproc + 653 .LFE7: + 654 .size ADC_GetResult16, .-ADC_GetResult16 + 655 .section .text.ADC_SetChanMask,"ax",%progbits + 656 .align 2 + 657 .global ADC_SetChanMask + 658 .code 16 + 659 .thumb_func + 660 .type ADC_SetChanMask, %function + 661 ADC_SetChanMask: + 662 .LFB8: + 527:Generated_Source\PSoC4/ADC.c **** + 528:Generated_Source\PSoC4/ADC.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 22 + + + 529:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 530:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SetChanMask + 531:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 532:Generated_Source\PSoC4/ADC.c **** * + 533:Generated_Source\PSoC4/ADC.c **** * Summary: + 534:Generated_Source\PSoC4/ADC.c **** * Sets the channel enable mask. + 535:Generated_Source\PSoC4/ADC.c **** * + 536:Generated_Source\PSoC4/ADC.c **** * Parameters: + 537:Generated_Source\PSoC4/ADC.c **** * mask: Sets which channels that will be + 538:Generated_Source\PSoC4/ADC.c **** * scanned. Setting bits for channels that do not exist will have no + 539:Generated_Source\PSoC4/ADC.c **** * effect. For example, if only 6 channels were enabled, setting a + 540:Generated_Source\PSoC4/ADC.c **** * mask of 0x0103 would only enable the last two channels (0 and 1). + 541:Generated_Source\PSoC4/ADC.c **** * This API will not enable the injection channel. + 542:Generated_Source\PSoC4/ADC.c **** * Examples: If the component is setup to sequence through 8 + 543:Generated_Source\PSoC4/ADC.c **** * channels, a mask of 0x000F would enable channels 0, 1, 2, and 3. + 544:Generated_Source\PSoC4/ADC.c **** * + 545:Generated_Source\PSoC4/ADC.c **** * Return: + 546:Generated_Source\PSoC4/ADC.c **** * None. + 547:Generated_Source\PSoC4/ADC.c **** * + 548:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 549:Generated_Source\PSoC4/ADC.c **** void ADC_SetChanMask(uint32 mask) + 550:Generated_Source\PSoC4/ADC.c **** { + 663 .loc 1 550 0 + 664 .cfi_startproc + 665 @ args = 0, pretend = 0, frame = 8 + 666 @ frame_needed = 1, uses_anonymous_args = 0 + 667 0000 80B5 push {r7, lr} + 668 .cfi_def_cfa_offset 8 + 669 .cfi_offset 7, -8 + 670 .cfi_offset 14, -4 + 671 0002 82B0 sub sp, sp, #8 + 672 .cfi_def_cfa_offset 16 + 673 0004 00AF add r7, sp, #0 + 674 .cfi_def_cfa_register 7 + 675 0006 7860 str r0, [r7, #4] + 551:Generated_Source\PSoC4/ADC.c **** ADC_SAR_CHAN_EN_REG = mask & ADC_MAX_CHANNELS_EN_MASK; + 676 .loc 1 551 0 + 677 0008 044B ldr r3, .L48 + 678 000a 7A68 ldr r2, [r7, #4] + 679 000c 0121 movs r1, #1 + 680 000e 0A40 ands r2, r1 + 681 0010 1A60 str r2, [r3] + 552:Generated_Source\PSoC4/ADC.c **** } + 682 .loc 1 552 0 + 683 0012 C046 nop + 684 0014 BD46 mov sp, r7 + 685 0016 02B0 add sp, sp, #8 + 686 @ sp needed + 687 0018 80BD pop {r7, pc} + 688 .L49: + 689 001a C046 .align 2 + 690 .L48: + 691 001c 20001A40 .word 1075445792 + 692 .cfi_endproc + 693 .LFE8: + 694 .size ADC_SetChanMask, .-ADC_SetChanMask + 695 .section .text.ADC_SetLowLimit,"ax",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 23 + + + 696 .align 2 + 697 .global ADC_SetLowLimit + 698 .code 16 + 699 .thumb_func + 700 .type ADC_SetLowLimit, %function + 701 ADC_SetLowLimit: + 702 .LFB9: + 553:Generated_Source\PSoC4/ADC.c **** + 554:Generated_Source\PSoC4/ADC.c **** #if(ADC_INJ_CHANNEL_ENABLED) + 555:Generated_Source\PSoC4/ADC.c **** + 556:Generated_Source\PSoC4/ADC.c **** + 557:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 558:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_EnableInjection + 559:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 560:Generated_Source\PSoC4/ADC.c **** * + 561:Generated_Source\PSoC4/ADC.c **** * Summary: + 562:Generated_Source\PSoC4/ADC.c **** * Enables the injection channel for the next scan only. + 563:Generated_Source\PSoC4/ADC.c **** * + 564:Generated_Source\PSoC4/ADC.c **** * Parameters: + 565:Generated_Source\PSoC4/ADC.c **** * None. + 566:Generated_Source\PSoC4/ADC.c **** * + 567:Generated_Source\PSoC4/ADC.c **** * Return: + 568:Generated_Source\PSoC4/ADC.c **** * None. + 569:Generated_Source\PSoC4/ADC.c **** * + 570:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 571:Generated_Source\PSoC4/ADC.c **** void ADC_EnableInjection(void) + 572:Generated_Source\PSoC4/ADC.c **** { + 573:Generated_Source\PSoC4/ADC.c **** ADC_SAR_INJ_CHAN_CONFIG_REG |= ADC_INJ_CHAN_EN; + 574:Generated_Source\PSoC4/ADC.c **** } + 575:Generated_Source\PSoC4/ADC.c **** + 576:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_INJ_CHANNEL_ENABLED */ + 577:Generated_Source\PSoC4/ADC.c **** + 578:Generated_Source\PSoC4/ADC.c **** + 579:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 580:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SetLowLimit + 581:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 582:Generated_Source\PSoC4/ADC.c **** * + 583:Generated_Source\PSoC4/ADC.c **** * Summary: + 584:Generated_Source\PSoC4/ADC.c **** * Sets the low limit parameter for a limit condition. + 585:Generated_Source\PSoC4/ADC.c **** * + 586:Generated_Source\PSoC4/ADC.c **** * Parameters: + 587:Generated_Source\PSoC4/ADC.c **** * lowLimit: The low limit for a limit condition. + 588:Generated_Source\PSoC4/ADC.c **** * + 589:Generated_Source\PSoC4/ADC.c **** * Return: + 590:Generated_Source\PSoC4/ADC.c **** * None. + 591:Generated_Source\PSoC4/ADC.c **** * + 592:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 593:Generated_Source\PSoC4/ADC.c **** void ADC_SetLowLimit(uint32 lowLimit) + 594:Generated_Source\PSoC4/ADC.c **** { + 703 .loc 1 594 0 + 704 .cfi_startproc + 705 @ args = 0, pretend = 0, frame = 8 + 706 @ frame_needed = 1, uses_anonymous_args = 0 + 707 0000 80B5 push {r7, lr} + 708 .cfi_def_cfa_offset 8 + 709 .cfi_offset 7, -8 + 710 .cfi_offset 14, -4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 24 + + + 711 0002 82B0 sub sp, sp, #8 + 712 .cfi_def_cfa_offset 16 + 713 0004 00AF add r7, sp, #0 + 714 .cfi_def_cfa_register 7 + 715 0006 7860 str r0, [r7, #4] + 595:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_LOW_MASK); + 716 .loc 1 595 0 + 717 0008 084B ldr r3, .L51 + 718 000a 084A ldr r2, .L51 + 719 000c 1268 ldr r2, [r2] + 720 000e 120C lsrs r2, r2, #16 + 721 0010 1204 lsls r2, r2, #16 + 722 0012 1A60 str r2, [r3] + 596:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_THRES_REG |= lowLimit & ADC_RANGE_LOW_MASK; + 723 .loc 1 596 0 + 724 0014 054B ldr r3, .L51 + 725 0016 054A ldr r2, .L51 + 726 0018 1168 ldr r1, [r2] + 727 001a 7A68 ldr r2, [r7, #4] + 728 001c 1204 lsls r2, r2, #16 + 729 001e 120C lsrs r2, r2, #16 + 730 0020 0A43 orrs r2, r1 + 731 0022 1A60 str r2, [r3] + 597:Generated_Source\PSoC4/ADC.c **** } + 732 .loc 1 597 0 + 733 0024 C046 nop + 734 0026 BD46 mov sp, r7 + 735 0028 02B0 add sp, sp, #8 + 736 @ sp needed + 737 002a 80BD pop {r7, pc} + 738 .L52: + 739 .align 2 + 740 .L51: + 741 002c 18001A40 .word 1075445784 + 742 .cfi_endproc + 743 .LFE9: + 744 .size ADC_SetLowLimit, .-ADC_SetLowLimit + 745 .section .text.ADC_SetHighLimit,"ax",%progbits + 746 .align 2 + 747 .global ADC_SetHighLimit + 748 .code 16 + 749 .thumb_func + 750 .type ADC_SetHighLimit, %function + 751 ADC_SetHighLimit: + 752 .LFB10: + 598:Generated_Source\PSoC4/ADC.c **** + 599:Generated_Source\PSoC4/ADC.c **** + 600:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 601:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SetHighLimit + 602:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 603:Generated_Source\PSoC4/ADC.c **** * + 604:Generated_Source\PSoC4/ADC.c **** * Summary: + 605:Generated_Source\PSoC4/ADC.c **** * Sets the low limit parameter for a limit condition. + 606:Generated_Source\PSoC4/ADC.c **** * + 607:Generated_Source\PSoC4/ADC.c **** * Parameters: + 608:Generated_Source\PSoC4/ADC.c **** * highLimit: The high limit for a limit condition. + 609:Generated_Source\PSoC4/ADC.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 25 + + + 610:Generated_Source\PSoC4/ADC.c **** * Return: + 611:Generated_Source\PSoC4/ADC.c **** * None. + 612:Generated_Source\PSoC4/ADC.c **** * + 613:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 614:Generated_Source\PSoC4/ADC.c **** void ADC_SetHighLimit(uint32 highLimit) + 615:Generated_Source\PSoC4/ADC.c **** { + 753 .loc 1 615 0 + 754 .cfi_startproc + 755 @ args = 0, pretend = 0, frame = 8 + 756 @ frame_needed = 1, uses_anonymous_args = 0 + 757 0000 80B5 push {r7, lr} + 758 .cfi_def_cfa_offset 8 + 759 .cfi_offset 7, -8 + 760 .cfi_offset 14, -4 + 761 0002 82B0 sub sp, sp, #8 + 762 .cfi_def_cfa_offset 16 + 763 0004 00AF add r7, sp, #0 + 764 .cfi_def_cfa_register 7 + 765 0006 7860 str r0, [r7, #4] + 616:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_HIGH_MASK); + 766 .loc 1 616 0 + 767 0008 084B ldr r3, .L54 + 768 000a 084A ldr r2, .L54 + 769 000c 1268 ldr r2, [r2] + 770 000e 1204 lsls r2, r2, #16 + 771 0010 120C lsrs r2, r2, #16 + 772 0012 1A60 str r2, [r3] + 617:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_THRES_REG |= (uint32)(highLimit << ADC_RANGE_HIGH_OFFSET); + 773 .loc 1 617 0 + 774 0014 054B ldr r3, .L54 + 775 0016 054A ldr r2, .L54 + 776 0018 1168 ldr r1, [r2] + 777 001a 7A68 ldr r2, [r7, #4] + 778 001c 1204 lsls r2, r2, #16 + 779 001e 0A43 orrs r2, r1 + 780 0020 1A60 str r2, [r3] + 618:Generated_Source\PSoC4/ADC.c **** } + 781 .loc 1 618 0 + 782 0022 C046 nop + 783 0024 BD46 mov sp, r7 + 784 0026 02B0 add sp, sp, #8 + 785 @ sp needed + 786 0028 80BD pop {r7, pc} + 787 .L55: + 788 002a C046 .align 2 + 789 .L54: + 790 002c 18001A40 .word 1075445784 + 791 .cfi_endproc + 792 .LFE10: + 793 .size ADC_SetHighLimit, .-ADC_SetHighLimit + 794 .section .text.ADC_SetLimitMask,"ax",%progbits + 795 .align 2 + 796 .global ADC_SetLimitMask + 797 .code 16 + 798 .thumb_func + 799 .type ADC_SetLimitMask, %function + 800 ADC_SetLimitMask: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 26 + + + 801 .LFB11: + 619:Generated_Source\PSoC4/ADC.c **** + 620:Generated_Source\PSoC4/ADC.c **** + 621:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 622:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SetLimitMask + 623:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 624:Generated_Source\PSoC4/ADC.c **** * + 625:Generated_Source\PSoC4/ADC.c **** * Summary: + 626:Generated_Source\PSoC4/ADC.c **** * Sets the channel limit condition mask. + 627:Generated_Source\PSoC4/ADC.c **** * + 628:Generated_Source\PSoC4/ADC.c **** * Parameters: + 629:Generated_Source\PSoC4/ADC.c **** * mask: Sets which channels that may cause a + 630:Generated_Source\PSoC4/ADC.c **** * limit condition interrupt. Setting bits for channels that do not exist + 631:Generated_Source\PSoC4/ADC.c **** * will have no effect. For example, if only 6 channels were enabled, + 632:Generated_Source\PSoC4/ADC.c **** * setting a mask of 0x0103 would only enable the last two channels (0 and 1). + 633:Generated_Source\PSoC4/ADC.c **** * + 634:Generated_Source\PSoC4/ADC.c **** * Return: + 635:Generated_Source\PSoC4/ADC.c **** * None. + 636:Generated_Source\PSoC4/ADC.c **** * + 637:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 638:Generated_Source\PSoC4/ADC.c **** void ADC_SetLimitMask(uint32 mask) + 639:Generated_Source\PSoC4/ADC.c **** { + 802 .loc 1 639 0 + 803 .cfi_startproc + 804 @ args = 0, pretend = 0, frame = 8 + 805 @ frame_needed = 1, uses_anonymous_args = 0 + 806 0000 80B5 push {r7, lr} + 807 .cfi_def_cfa_offset 8 + 808 .cfi_offset 7, -8 + 809 .cfi_offset 14, -4 + 810 0002 82B0 sub sp, sp, #8 + 811 .cfi_def_cfa_offset 16 + 812 0004 00AF add r7, sp, #0 + 813 .cfi_def_cfa_register 7 + 814 0006 7860 str r0, [r7, #4] + 640:Generated_Source\PSoC4/ADC.c **** ADC_SAR_RANGE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK; + 815 .loc 1 640 0 + 816 0008 044B ldr r3, .L57 + 817 000a 7A68 ldr r2, [r7, #4] + 818 000c 0121 movs r1, #1 + 819 000e 0A40 ands r2, r1 + 820 0010 1A60 str r2, [r3] + 641:Generated_Source\PSoC4/ADC.c **** } + 821 .loc 1 641 0 + 822 0012 C046 nop + 823 0014 BD46 mov sp, r7 + 824 0016 02B0 add sp, sp, #8 + 825 @ sp needed + 826 0018 80BD pop {r7, pc} + 827 .L58: + 828 001a C046 .align 2 + 829 .L57: + 830 001c 38021A40 .word 1075446328 + 831 .cfi_endproc + 832 .LFE11: + 833 .size ADC_SetLimitMask, .-ADC_SetLimitMask + 834 .section .text.ADC_SetSatMask,"ax",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 27 + + + 835 .align 2 + 836 .global ADC_SetSatMask + 837 .code 16 + 838 .thumb_func + 839 .type ADC_SetSatMask, %function + 840 ADC_SetSatMask: + 841 .LFB12: + 642:Generated_Source\PSoC4/ADC.c **** + 643:Generated_Source\PSoC4/ADC.c **** + 644:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 645:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SetSatMask + 646:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 647:Generated_Source\PSoC4/ADC.c **** * + 648:Generated_Source\PSoC4/ADC.c **** * Summary: + 649:Generated_Source\PSoC4/ADC.c **** * Sets the channel saturation event mask. + 650:Generated_Source\PSoC4/ADC.c **** * + 651:Generated_Source\PSoC4/ADC.c **** * Parameters: + 652:Generated_Source\PSoC4/ADC.c **** * mask: Sets which channels that may cause a + 653:Generated_Source\PSoC4/ADC.c **** * saturation event interrupt. Setting bits for channels that do not exist + 654:Generated_Source\PSoC4/ADC.c **** * will have no effect. For example, if only 8 channels were enabled, + 655:Generated_Source\PSoC4/ADC.c **** * setting a mask of 0x01C0 would only enable two channels (6 and 7). + 656:Generated_Source\PSoC4/ADC.c **** * + 657:Generated_Source\PSoC4/ADC.c **** * Return: + 658:Generated_Source\PSoC4/ADC.c **** * None. + 659:Generated_Source\PSoC4/ADC.c **** * + 660:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 661:Generated_Source\PSoC4/ADC.c **** void ADC_SetSatMask(uint32 mask) + 662:Generated_Source\PSoC4/ADC.c **** { + 842 .loc 1 662 0 + 843 .cfi_startproc + 844 @ args = 0, pretend = 0, frame = 8 + 845 @ frame_needed = 1, uses_anonymous_args = 0 + 846 0000 80B5 push {r7, lr} + 847 .cfi_def_cfa_offset 8 + 848 .cfi_offset 7, -8 + 849 .cfi_offset 14, -4 + 850 0002 82B0 sub sp, sp, #8 + 851 .cfi_def_cfa_offset 16 + 852 0004 00AF add r7, sp, #0 + 853 .cfi_def_cfa_register 7 + 854 0006 7860 str r0, [r7, #4] + 663:Generated_Source\PSoC4/ADC.c **** ADC_SAR_SATURATE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK; + 855 .loc 1 663 0 + 856 0008 044B ldr r3, .L60 + 857 000a 7A68 ldr r2, [r7, #4] + 858 000c 0121 movs r1, #1 + 859 000e 0A40 ands r2, r1 + 860 0010 1A60 str r2, [r3] + 664:Generated_Source\PSoC4/ADC.c **** } + 861 .loc 1 664 0 + 862 0012 C046 nop + 863 0014 BD46 mov sp, r7 + 864 0016 02B0 add sp, sp, #8 + 865 @ sp needed + 866 0018 80BD pop {r7, pc} + 867 .L61: + 868 001a C046 .align 2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 28 + + + 869 .L60: + 870 001c 28021A40 .word 1075446312 + 871 .cfi_endproc + 872 .LFE12: + 873 .size ADC_SetSatMask, .-ADC_SetSatMask + 874 .section .text.ADC_SetOffset,"ax",%progbits + 875 .align 2 + 876 .global ADC_SetOffset + 877 .code 16 + 878 .thumb_func + 879 .type ADC_SetOffset, %function + 880 ADC_SetOffset: + 881 .LFB13: + 665:Generated_Source\PSoC4/ADC.c **** + 666:Generated_Source\PSoC4/ADC.c **** + 667:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 668:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SetOffset + 669:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 670:Generated_Source\PSoC4/ADC.c **** * + 671:Generated_Source\PSoC4/ADC.c **** * Summary: + 672:Generated_Source\PSoC4/ADC.c **** * Description: Sets the ADC offset which is used by the functions + 673:Generated_Source\PSoC4/ADC.c **** * ADC_CountsTo_uVolts, ADC_CountsTo_mVolts and ADC_CountsTo_Volts + 674:Generated_Source\PSoC4/ADC.c **** * to substract the offset from the given reading + 675:Generated_Source\PSoC4/ADC.c **** * before calculating the voltage conversion. + 676:Generated_Source\PSoC4/ADC.c **** * + 677:Generated_Source\PSoC4/ADC.c **** * Parameters: + 678:Generated_Source\PSoC4/ADC.c **** * chan: ADC channel number. + 679:Generated_Source\PSoC4/ADC.c **** * offset: This value is a measured value when the + 680:Generated_Source\PSoC4/ADC.c **** * inputs are shorted or connected to the same input voltage. + 681:Generated_Source\PSoC4/ADC.c **** * + 682:Generated_Source\PSoC4/ADC.c **** * Return: + 683:Generated_Source\PSoC4/ADC.c **** * None. + 684:Generated_Source\PSoC4/ADC.c **** * + 685:Generated_Source\PSoC4/ADC.c **** * Global variables: + 686:Generated_Source\PSoC4/ADC.c **** * ADC_Offset: Modified to set the user provided offset. + 687:Generated_Source\PSoC4/ADC.c **** * + 688:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 689:Generated_Source\PSoC4/ADC.c **** void ADC_SetOffset(uint32 chan, int16 offset) + 690:Generated_Source\PSoC4/ADC.c **** { + 882 .loc 1 690 0 + 883 .cfi_startproc + 884 @ args = 0, pretend = 0, frame = 8 + 885 @ frame_needed = 1, uses_anonymous_args = 0 + 886 0000 80B5 push {r7, lr} + 887 .cfi_def_cfa_offset 8 + 888 .cfi_offset 7, -8 + 889 .cfi_offset 14, -4 + 890 0002 82B0 sub sp, sp, #8 + 891 .cfi_def_cfa_offset 16 + 892 0004 00AF add r7, sp, #0 + 893 .cfi_def_cfa_register 7 + 894 0006 7860 str r0, [r7, #4] + 895 0008 0A00 movs r2, r1 + 896 000a BB1C adds r3, r7, #2 + 897 000c 1A80 strh r2, [r3] + 691:Generated_Source\PSoC4/ADC.c **** /* Halt CPU in debug mode if channel is out of valid range */ + 692:Generated_Source\PSoC4/ADC.c **** CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 29 + + + 898 .loc 1 692 0 + 899 000e 7B68 ldr r3, [r7, #4] + 900 0010 002B cmp r3, #0 + 901 0012 02D0 beq .L63 + 902 .loc 1 692 0 is_stmt 0 discriminator 1 + 903 0014 0020 movs r0, #0 + 904 0016 FFF7FEFF bl CyHalt + 905 .L63: + 693:Generated_Source\PSoC4/ADC.c **** + 694:Generated_Source\PSoC4/ADC.c **** ADC_offset[chan] = offset; + 906 .loc 1 694 0 is_stmt 1 + 907 001a 054B ldr r3, .L64 + 908 001c 7A68 ldr r2, [r7, #4] + 909 001e 5200 lsls r2, r2, #1 + 910 0020 B91C adds r1, r7, #2 + 911 0022 0988 ldrh r1, [r1] + 912 0024 D152 strh r1, [r2, r3] + 695:Generated_Source\PSoC4/ADC.c **** } + 913 .loc 1 695 0 + 914 0026 C046 nop + 915 0028 BD46 mov sp, r7 + 916 002a 02B0 add sp, sp, #8 + 917 @ sp needed + 918 002c 80BD pop {r7, pc} + 919 .L65: + 920 002e C046 .align 2 + 921 .L64: + 922 0030 00000000 .word ADC_offset + 923 .cfi_endproc + 924 .LFE13: + 925 .size ADC_SetOffset, .-ADC_SetOffset + 926 .section .text.ADC_SetGain,"ax",%progbits + 927 .align 2 + 928 .global ADC_SetGain + 929 .code 16 + 930 .thumb_func + 931 .type ADC_SetGain, %function + 932 ADC_SetGain: + 933 .LFB14: + 696:Generated_Source\PSoC4/ADC.c **** + 697:Generated_Source\PSoC4/ADC.c **** + 698:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 699:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_SetGain + 700:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 701:Generated_Source\PSoC4/ADC.c **** * + 702:Generated_Source\PSoC4/ADC.c **** * Summary: + 703:Generated_Source\PSoC4/ADC.c **** * Description: Sets the ADC gain in counts per 10 volt for the voltage + 704:Generated_Source\PSoC4/ADC.c **** * conversion functions below. This value is set by default by the + 705:Generated_Source\PSoC4/ADC.c **** * reference and input range settings. It should only be used to further + 706:Generated_Source\PSoC4/ADC.c **** * calibrate the ADC with a known input or if an external reference is + 707:Generated_Source\PSoC4/ADC.c **** * used. Affects the ADC_CountsTo_uVolts, ADC_CountsTo_mVolts + 708:Generated_Source\PSoC4/ADC.c **** * and ADC_CountsTo_Volts functions by supplying the correct + 709:Generated_Source\PSoC4/ADC.c **** * conversion between ADC counts and voltage. + 710:Generated_Source\PSoC4/ADC.c **** * + 711:Generated_Source\PSoC4/ADC.c **** * Parameters: + 712:Generated_Source\PSoC4/ADC.c **** * chan: ADC channel number. + 713:Generated_Source\PSoC4/ADC.c **** * adcGain: ADC gain in counts per 10 volts. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 30 + + + 714:Generated_Source\PSoC4/ADC.c **** * + 715:Generated_Source\PSoC4/ADC.c **** * Return: + 716:Generated_Source\PSoC4/ADC.c **** * None. + 717:Generated_Source\PSoC4/ADC.c **** * + 718:Generated_Source\PSoC4/ADC.c **** * Global variables: + 719:Generated_Source\PSoC4/ADC.c **** * ADC_CountsPer10Volt: modified to set the ADC gain in counts + 720:Generated_Source\PSoC4/ADC.c **** * per 10 volt. + 721:Generated_Source\PSoC4/ADC.c **** * + 722:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 723:Generated_Source\PSoC4/ADC.c **** void ADC_SetGain(uint32 chan, int32 adcGain) + 724:Generated_Source\PSoC4/ADC.c **** { + 934 .loc 1 724 0 + 935 .cfi_startproc + 936 @ args = 0, pretend = 0, frame = 8 + 937 @ frame_needed = 1, uses_anonymous_args = 0 + 938 0000 80B5 push {r7, lr} + 939 .cfi_def_cfa_offset 8 + 940 .cfi_offset 7, -8 + 941 .cfi_offset 14, -4 + 942 0002 82B0 sub sp, sp, #8 + 943 .cfi_def_cfa_offset 16 + 944 0004 00AF add r7, sp, #0 + 945 .cfi_def_cfa_register 7 + 946 0006 7860 str r0, [r7, #4] + 947 0008 3960 str r1, [r7] + 725:Generated_Source\PSoC4/ADC.c **** /* Halt CPU in debug mode if channel is out of valid range */ + 726:Generated_Source\PSoC4/ADC.c **** CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + 948 .loc 1 726 0 + 949 000a 7B68 ldr r3, [r7, #4] + 950 000c 002B cmp r3, #0 + 951 000e 02D0 beq .L67 + 952 .loc 1 726 0 is_stmt 0 discriminator 1 + 953 0010 0020 movs r0, #0 + 954 0012 FFF7FEFF bl CyHalt + 955 .L67: + 727:Generated_Source\PSoC4/ADC.c **** + 728:Generated_Source\PSoC4/ADC.c **** ADC_countsPer10Volt[chan] = adcGain; + 956 .loc 1 728 0 is_stmt 1 + 957 0016 044B ldr r3, .L68 + 958 0018 7A68 ldr r2, [r7, #4] + 959 001a 9200 lsls r2, r2, #2 + 960 001c 3968 ldr r1, [r7] + 961 001e D150 str r1, [r2, r3] + 729:Generated_Source\PSoC4/ADC.c **** } + 962 .loc 1 729 0 + 963 0020 C046 nop + 964 0022 BD46 mov sp, r7 + 965 0024 02B0 add sp, sp, #8 + 966 @ sp needed + 967 0026 80BD pop {r7, pc} + 968 .L69: + 969 .align 2 + 970 .L68: + 971 0028 00000000 .word ADC_countsPer10Volt + 972 .cfi_endproc + 973 .LFE14: + 974 .size ADC_SetGain, .-ADC_SetGain + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 31 + + + 975 .section .text.ADC_CountsTo_mVolts,"ax",%progbits + 976 .align 2 + 977 .global ADC_CountsTo_mVolts + 978 .code 16 + 979 .thumb_func + 980 .type ADC_CountsTo_mVolts, %function + 981 ADC_CountsTo_mVolts: + 982 .LFB15: + 730:Generated_Source\PSoC4/ADC.c **** + 731:Generated_Source\PSoC4/ADC.c **** + 732:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT) + 733:Generated_Source\PSoC4/ADC.c **** + 734:Generated_Source\PSoC4/ADC.c **** + 735:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 736:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_CountsTo_mVolts + 737:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 738:Generated_Source\PSoC4/ADC.c **** * + 739:Generated_Source\PSoC4/ADC.c **** * Summary: + 740:Generated_Source\PSoC4/ADC.c **** * This function converts ADC counts to mVolts + 741:Generated_Source\PSoC4/ADC.c **** * This function is not available when left data format justification selected. + 742:Generated_Source\PSoC4/ADC.c **** * + 743:Generated_Source\PSoC4/ADC.c **** * Parameters: + 744:Generated_Source\PSoC4/ADC.c **** * chan: The ADC channel number. + 745:Generated_Source\PSoC4/ADC.c **** * adcCounts: Result from the ADC conversion + 746:Generated_Source\PSoC4/ADC.c **** * + 747:Generated_Source\PSoC4/ADC.c **** * Return: + 748:Generated_Source\PSoC4/ADC.c **** * Results in mVolts + 749:Generated_Source\PSoC4/ADC.c **** * + 750:Generated_Source\PSoC4/ADC.c **** * Global variables: + 751:Generated_Source\PSoC4/ADC.c **** * ADC_countsPer10Volt: used to convert ADC counts to mVolts. + 752:Generated_Source\PSoC4/ADC.c **** * ADC_Offset: Used as the offset while converting ADC counts + 753:Generated_Source\PSoC4/ADC.c **** * to mVolts. + 754:Generated_Source\PSoC4/ADC.c **** * + 755:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 756:Generated_Source\PSoC4/ADC.c **** int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts) + 757:Generated_Source\PSoC4/ADC.c **** { + 983 .loc 1 757 0 + 984 .cfi_startproc + 985 @ args = 0, pretend = 0, frame = 16 + 986 @ frame_needed = 1, uses_anonymous_args = 0 + 987 0000 80B5 push {r7, lr} + 988 .cfi_def_cfa_offset 8 + 989 .cfi_offset 7, -8 + 990 .cfi_offset 14, -4 + 991 0002 84B0 sub sp, sp, #16 + 992 .cfi_def_cfa_offset 24 + 993 0004 00AF add r7, sp, #0 + 994 .cfi_def_cfa_register 7 + 995 0006 7860 str r0, [r7, #4] + 996 0008 0A00 movs r2, r1 + 997 000a BB1C adds r3, r7, #2 + 998 000c 1A80 strh r2, [r3] + 758:Generated_Source\PSoC4/ADC.c **** int16 mVolts; + 759:Generated_Source\PSoC4/ADC.c **** + 760:Generated_Source\PSoC4/ADC.c **** /* Halt CPU in debug mode if channel is out of valid range */ + 761:Generated_Source\PSoC4/ADC.c **** CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + 999 .loc 1 761 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 32 + + + 1000 000e 7B68 ldr r3, [r7, #4] + 1001 0010 002B cmp r3, #0 + 1002 0012 02D0 beq .L71 + 1003 .loc 1 761 0 is_stmt 0 discriminator 1 + 1004 0014 0020 movs r0, #0 + 1005 0016 FFF7FEFF bl CyHalt + 1006 .L71: + 762:Generated_Source\PSoC4/ADC.c **** + 763:Generated_Source\PSoC4/ADC.c **** /* Divide the adcCount when accumulate averaging mode selected */ + 764:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + 765:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + 766:Generated_Source\PSoC4/ADC.c **** { + 767:Generated_Source\PSoC4/ADC.c **** adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + 768:Generated_Source\PSoC4/ADC.c **** } + 769:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + 770:Generated_Source\PSoC4/ADC.c **** + 771:Generated_Source\PSoC4/ADC.c **** /* Subtract ADC offset */ + 772:Generated_Source\PSoC4/ADC.c **** adcCounts -= ADC_offset[chan]; + 1007 .loc 1 772 0 is_stmt 1 + 1008 001a 1E4B ldr r3, .L77 + 1009 001c 7A68 ldr r2, [r7, #4] + 1010 001e 5200 lsls r2, r2, #1 + 1011 0020 D35A ldrh r3, [r2, r3] + 1012 0022 19B2 sxth r1, r3 + 1013 0024 BB1C adds r3, r7, #2 + 1014 0026 1A88 ldrh r2, [r3] + 1015 0028 8BB2 uxth r3, r1 + 1016 002a D31A subs r3, r2, r3 + 1017 002c 9AB2 uxth r2, r3 + 1018 002e BB1C adds r3, r7, #2 + 1019 0030 1A80 strh r2, [r3] + 773:Generated_Source\PSoC4/ADC.c **** + 774:Generated_Source\PSoC4/ADC.c **** mVolts = (int16)((((int32)adcCounts * ADC_10MV_COUNTS) + ( (adcCounts > 0) ? + 1020 .loc 1 774 0 + 1021 0032 BB1C adds r3, r7, #2 + 1022 0034 0022 movs r2, #0 + 1023 0036 9B5E ldrsh r3, [r3, r2] + 1024 0038 174A ldr r2, .L77+4 + 1025 003a 5A43 muls r2, r3 + 775:Generated_Source\PSoC4/ADC.c **** (ADC_countsPer10Volt[chan] / 2) : (-(ADC_countsPer10Volt[chan] / 2)) )) + 1026 .loc 1 775 0 + 1027 003c BB1C adds r3, r7, #2 + 1028 003e 0021 movs r1, #0 + 1029 0040 5B5E ldrsh r3, [r3, r1] + 1030 0042 002B cmp r3, #0 + 1031 0044 08DD ble .L72 + 1032 .loc 1 775 0 is_stmt 0 discriminator 1 + 1033 0046 154B ldr r3, .L77+8 + 1034 0048 7968 ldr r1, [r7, #4] + 1035 004a 8900 lsls r1, r1, #2 + 1036 004c CB58 ldr r3, [r1, r3] + 1037 004e 002B cmp r3, #0 + 1038 0050 00DA bge .L73 + 1039 0052 0133 adds r3, r3, #1 + 1040 .L73: + 1041 0054 5B10 asrs r3, r3, #1 + 1042 0056 08E0 b .L74 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 33 + + + 1043 .L72: + 1044 .loc 1 775 0 discriminator 2 + 1045 0058 104B ldr r3, .L77+8 + 1046 005a 7968 ldr r1, [r7, #4] + 1047 005c 8900 lsls r1, r1, #2 + 1048 005e CB58 ldr r3, [r1, r3] + 1049 0060 002B cmp r3, #0 + 1050 0062 00DA bge .L75 + 1051 0064 0133 adds r3, r3, #1 + 1052 .L75: + 1053 0066 5B10 asrs r3, r3, #1 + 1054 0068 5B42 rsbs r3, r3, #0 + 1055 .L74: + 774:Generated_Source\PSoC4/ADC.c **** (ADC_countsPer10Volt[chan] / 2) : (-(ADC_countsPer10Volt[chan] / 2)) )) + 1056 .loc 1 774 0 is_stmt 1 + 1057 006a D018 adds r0, r2, r3 + 776:Generated_Source\PSoC4/ADC.c **** / ADC_countsPer10Volt[chan]); + 1058 .loc 1 776 0 + 1059 006c 0B4B ldr r3, .L77+8 + 1060 006e 7A68 ldr r2, [r7, #4] + 1061 0070 9200 lsls r2, r2, #2 + 1062 0072 D358 ldr r3, [r2, r3] + 1063 0074 1900 movs r1, r3 + 1064 0076 FFF7FEFF bl __aeabi_idiv + 1065 007a 0300 movs r3, r0 + 1066 007c 1A00 movs r2, r3 + 774:Generated_Source\PSoC4/ADC.c **** (ADC_countsPer10Volt[chan] / 2) : (-(ADC_countsPer10Volt[chan] / 2)) )) + 1067 .loc 1 774 0 + 1068 007e 0E23 movs r3, #14 + 1069 0080 FB18 adds r3, r7, r3 + 1070 0082 1A80 strh r2, [r3] + 777:Generated_Source\PSoC4/ADC.c **** + 778:Generated_Source\PSoC4/ADC.c **** return( mVolts ); + 1071 .loc 1 778 0 + 1072 0084 0E23 movs r3, #14 + 1073 0086 FB18 adds r3, r7, r3 + 1074 0088 0022 movs r2, #0 + 1075 008a 9B5E ldrsh r3, [r3, r2] + 779:Generated_Source\PSoC4/ADC.c **** } + 1076 .loc 1 779 0 + 1077 008c 1800 movs r0, r3 + 1078 008e BD46 mov sp, r7 + 1079 0090 04B0 add sp, sp, #16 + 1080 @ sp needed + 1081 0092 80BD pop {r7, pc} + 1082 .L78: + 1083 .align 2 + 1084 .L77: + 1085 0094 00000000 .word ADC_offset + 1086 0098 10270000 .word 10000 + 1087 009c 00000000 .word ADC_countsPer10Volt + 1088 .cfi_endproc + 1089 .LFE15: + 1090 .size ADC_CountsTo_mVolts, .-ADC_CountsTo_mVolts + 1091 .global __aeabi_lmul + 1092 .global __aeabi_ldivmod + 1093 .section .text.ADC_CountsTo_uVolts,"ax",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 34 + + + 1094 .align 2 + 1095 .global ADC_CountsTo_uVolts + 1096 .code 16 + 1097 .thumb_func + 1098 .type ADC_CountsTo_uVolts, %function + 1099 ADC_CountsTo_uVolts: + 1100 .LFB16: + 780:Generated_Source\PSoC4/ADC.c **** + 781:Generated_Source\PSoC4/ADC.c **** + 782:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 783:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_CountsTo_uVolts + 784:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 785:Generated_Source\PSoC4/ADC.c **** * + 786:Generated_Source\PSoC4/ADC.c **** * Summary: + 787:Generated_Source\PSoC4/ADC.c **** * This function converts ADC counts to micro Volts + 788:Generated_Source\PSoC4/ADC.c **** * This function is not available when left data format justification selected. + 789:Generated_Source\PSoC4/ADC.c **** * + 790:Generated_Source\PSoC4/ADC.c **** * Parameters: + 791:Generated_Source\PSoC4/ADC.c **** * chan: The ADC channel number. + 792:Generated_Source\PSoC4/ADC.c **** * adcCounts: Result from the ADC conversion + 793:Generated_Source\PSoC4/ADC.c **** * + 794:Generated_Source\PSoC4/ADC.c **** * Return: + 795:Generated_Source\PSoC4/ADC.c **** * Results in uVolts + 796:Generated_Source\PSoC4/ADC.c **** * + 797:Generated_Source\PSoC4/ADC.c **** * Global variables: + 798:Generated_Source\PSoC4/ADC.c **** * ADC_countsPer10Volt: used to convert ADC counts to uVolts. + 799:Generated_Source\PSoC4/ADC.c **** * ADC_Offset: Used as the offset while converting ADC counts + 800:Generated_Source\PSoC4/ADC.c **** * to mVolts. + 801:Generated_Source\PSoC4/ADC.c **** * + 802:Generated_Source\PSoC4/ADC.c **** * Theory: + 803:Generated_Source\PSoC4/ADC.c **** * Care must be taken to not exceed the maximum value for a 31 bit signed + 804:Generated_Source\PSoC4/ADC.c **** * number in the conversion to uVolts and at the same time not loose + 805:Generated_Source\PSoC4/ADC.c **** * resolution. + 806:Generated_Source\PSoC4/ADC.c **** * To convert adcCounts to microVolts it is required to be multiplied + 807:Generated_Source\PSoC4/ADC.c **** * on 10 million and later divide on gain in counts per 10V. + 808:Generated_Source\PSoC4/ADC.c **** * + 809:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 810:Generated_Source\PSoC4/ADC.c **** int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts) + 811:Generated_Source\PSoC4/ADC.c **** { + 1101 .loc 1 811 0 + 1102 .cfi_startproc + 1103 @ args = 0, pretend = 0, frame = 24 + 1104 @ frame_needed = 1, uses_anonymous_args = 0 + 1105 0000 B0B5 push {r4, r5, r7, lr} + 1106 .cfi_def_cfa_offset 16 + 1107 .cfi_offset 4, -16 + 1108 .cfi_offset 5, -12 + 1109 .cfi_offset 7, -8 + 1110 .cfi_offset 14, -4 + 1111 0002 86B0 sub sp, sp, #24 + 1112 .cfi_def_cfa_offset 40 + 1113 0004 00AF add r7, sp, #0 + 1114 .cfi_def_cfa_register 7 + 1115 0006 F860 str r0, [r7, #12] + 1116 0008 0A00 movs r2, r1 + 1117 000a 0A23 movs r3, #10 + 1118 000c FB18 adds r3, r7, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 35 + + + 1119 000e 1A80 strh r2, [r3] + 812:Generated_Source\PSoC4/ADC.c **** int64 uVolts; + 813:Generated_Source\PSoC4/ADC.c **** + 814:Generated_Source\PSoC4/ADC.c **** /* Halt CPU in debug mode if channel is out of valid range */ + 815:Generated_Source\PSoC4/ADC.c **** CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + 1120 .loc 1 815 0 + 1121 0010 FB68 ldr r3, [r7, #12] + 1122 0012 002B cmp r3, #0 + 1123 0014 02D0 beq .L80 + 1124 .loc 1 815 0 is_stmt 0 discriminator 1 + 1125 0016 0020 movs r0, #0 + 1126 0018 FFF7FEFF bl CyHalt + 1127 .L80: + 816:Generated_Source\PSoC4/ADC.c **** + 817:Generated_Source\PSoC4/ADC.c **** /* Divide the adcCount when accumulate averaging mode selected */ + 818:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + 819:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + 820:Generated_Source\PSoC4/ADC.c **** { + 821:Generated_Source\PSoC4/ADC.c **** adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + 822:Generated_Source\PSoC4/ADC.c **** } + 823:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + 824:Generated_Source\PSoC4/ADC.c **** + 825:Generated_Source\PSoC4/ADC.c **** /* Subtract ADC offset */ + 826:Generated_Source\PSoC4/ADC.c **** adcCounts -= ADC_offset[chan]; + 1128 .loc 1 826 0 is_stmt 1 + 1129 001c 194B ldr r3, .L82 + 1130 001e FA68 ldr r2, [r7, #12] + 1131 0020 5200 lsls r2, r2, #1 + 1132 0022 D35A ldrh r3, [r2, r3] + 1133 0024 19B2 sxth r1, r3 + 1134 0026 0A23 movs r3, #10 + 1135 0028 FB18 adds r3, r7, r3 + 1136 002a 1A88 ldrh r2, [r3] + 1137 002c 8BB2 uxth r3, r1 + 1138 002e D31A subs r3, r2, r3 + 1139 0030 9AB2 uxth r2, r3 + 1140 0032 0A23 movs r3, #10 + 1141 0034 FB18 adds r3, r7, r3 + 1142 0036 1A80 strh r2, [r3] + 827:Generated_Source\PSoC4/ADC.c **** + 828:Generated_Source\PSoC4/ADC.c **** uVolts = ((int64)adcCounts * ADC_10UV_COUNTS) / ADC_countsPer10Volt[chan]; + 1143 .loc 1 828 0 + 1144 0038 0A23 movs r3, #10 + 1145 003a FB18 adds r3, r7, r3 + 1146 003c 1B88 ldrh r3, [r3] + 1147 003e 1BB2 sxth r3, r3 + 1148 0040 3B60 str r3, [r7] + 1149 0042 DB17 asrs r3, r3, #31 + 1150 0044 7B60 str r3, [r7, #4] + 1151 0046 104A ldr r2, .L82+4 + 1152 0048 0023 movs r3, #0 + 1153 004a 3868 ldr r0, [r7] + 1154 004c 7968 ldr r1, [r7, #4] + 1155 004e FFF7FEFF bl __aeabi_lmul + 1156 0052 0200 movs r2, r0 + 1157 0054 0B00 movs r3, r1 + 1158 0056 1000 movs r0, r2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 36 + + + 1159 0058 1900 movs r1, r3 + 1160 005a 0C4B ldr r3, .L82+8 + 1161 005c FA68 ldr r2, [r7, #12] + 1162 005e 9200 lsls r2, r2, #2 + 1163 0060 D358 ldr r3, [r2, r3] + 1164 0062 1C00 movs r4, r3 + 1165 0064 DB17 asrs r3, r3, #31 + 1166 0066 1D00 movs r5, r3 + 1167 0068 2200 movs r2, r4 + 1168 006a 2B00 movs r3, r5 + 1169 006c FFF7FEFF bl __aeabi_ldivmod + 1170 0070 0300 movs r3, r0 + 1171 0072 0C00 movs r4, r1 + 1172 0074 3B61 str r3, [r7, #16] + 1173 0076 7C61 str r4, [r7, #20] + 829:Generated_Source\PSoC4/ADC.c **** + 830:Generated_Source\PSoC4/ADC.c **** return( (int32)uVolts ); + 1174 .loc 1 830 0 + 1175 0078 3B69 ldr r3, [r7, #16] + 831:Generated_Source\PSoC4/ADC.c **** } + 1176 .loc 1 831 0 + 1177 007a 1800 movs r0, r3 + 1178 007c BD46 mov sp, r7 + 1179 007e 06B0 add sp, sp, #24 + 1180 @ sp needed + 1181 0080 B0BD pop {r4, r5, r7, pc} + 1182 .L83: + 1183 0082 C046 .align 2 + 1184 .L82: + 1185 0084 00000000 .word ADC_offset + 1186 0088 80969800 .word 10000000 + 1187 008c 00000000 .word ADC_countsPer10Volt + 1188 .cfi_endproc + 1189 .LFE16: + 1190 .size ADC_CountsTo_uVolts, .-ADC_CountsTo_uVolts + 1191 .global __aeabi_i2f + 1192 .global __aeabi_fmul + 1193 .global __aeabi_fdiv + 1194 .section .text.ADC_CountsTo_Volts,"ax",%progbits + 1195 .align 2 + 1196 .global ADC_CountsTo_Volts + 1197 .code 16 + 1198 .thumb_func + 1199 .type ADC_CountsTo_Volts, %function + 1200 ADC_CountsTo_Volts: + 1201 .LFB17: + 832:Generated_Source\PSoC4/ADC.c **** + 833:Generated_Source\PSoC4/ADC.c **** + 834:Generated_Source\PSoC4/ADC.c **** /******************************************************************************* + 835:Generated_Source\PSoC4/ADC.c **** * Function Name: ADC_CountsTo_Volts + 836:Generated_Source\PSoC4/ADC.c **** ******************************************************************************** + 837:Generated_Source\PSoC4/ADC.c **** * + 838:Generated_Source\PSoC4/ADC.c **** * Summary: + 839:Generated_Source\PSoC4/ADC.c **** * Converts the ADC output to Volts as a floating point number. + 840:Generated_Source\PSoC4/ADC.c **** * This function is not available when left data format justification selected. + 841:Generated_Source\PSoC4/ADC.c **** * + 842:Generated_Source\PSoC4/ADC.c **** * Parameters: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 37 + + + 843:Generated_Source\PSoC4/ADC.c **** * chan: The ADC channel number. + 844:Generated_Source\PSoC4/ADC.c **** * Result from the ADC conversion + 845:Generated_Source\PSoC4/ADC.c **** * + 846:Generated_Source\PSoC4/ADC.c **** * Return: + 847:Generated_Source\PSoC4/ADC.c **** * Results in Volts + 848:Generated_Source\PSoC4/ADC.c **** * + 849:Generated_Source\PSoC4/ADC.c **** * Global variables: + 850:Generated_Source\PSoC4/ADC.c **** * ADC_countsPer10Volt: used to convert ADC counts to Volts. + 851:Generated_Source\PSoC4/ADC.c **** * ADC_Offset: Used as the offset while converting ADC counts + 852:Generated_Source\PSoC4/ADC.c **** * to mVolts. + 853:Generated_Source\PSoC4/ADC.c **** * + 854:Generated_Source\PSoC4/ADC.c **** *******************************************************************************/ + 855:Generated_Source\PSoC4/ADC.c **** float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts) + 856:Generated_Source\PSoC4/ADC.c **** { + 1202 .loc 1 856 0 + 1203 .cfi_startproc + 1204 @ args = 0, pretend = 0, frame = 16 + 1205 @ frame_needed = 1, uses_anonymous_args = 0 + 1206 0000 90B5 push {r4, r7, lr} + 1207 .cfi_def_cfa_offset 12 + 1208 .cfi_offset 4, -12 + 1209 .cfi_offset 7, -8 + 1210 .cfi_offset 14, -4 + 1211 0002 85B0 sub sp, sp, #20 + 1212 .cfi_def_cfa_offset 32 + 1213 0004 00AF add r7, sp, #0 + 1214 .cfi_def_cfa_register 7 + 1215 0006 7860 str r0, [r7, #4] + 1216 0008 0A00 movs r2, r1 + 1217 000a BB1C adds r3, r7, #2 + 1218 000c 1A80 strh r2, [r3] + 857:Generated_Source\PSoC4/ADC.c **** float32 volts; + 858:Generated_Source\PSoC4/ADC.c **** + 859:Generated_Source\PSoC4/ADC.c **** /* Halt CPU in debug mode if channel is out of valid range */ + 860:Generated_Source\PSoC4/ADC.c **** CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + 1219 .loc 1 860 0 + 1220 000e 7B68 ldr r3, [r7, #4] + 1221 0010 002B cmp r3, #0 + 1222 0012 02D0 beq .L85 + 1223 .loc 1 860 0 is_stmt 0 discriminator 1 + 1224 0014 0020 movs r0, #0 + 1225 0016 FFF7FEFF bl CyHalt + 1226 .L85: + 861:Generated_Source\PSoC4/ADC.c **** + 862:Generated_Source\PSoC4/ADC.c **** /* Divide the adcCount when accumulate averaging mode selected */ + 863:Generated_Source\PSoC4/ADC.c **** #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + 864:Generated_Source\PSoC4/ADC.c **** if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + 865:Generated_Source\PSoC4/ADC.c **** { + 866:Generated_Source\PSoC4/ADC.c **** adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + 867:Generated_Source\PSoC4/ADC.c **** } + 868:Generated_Source\PSoC4/ADC.c **** #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + 869:Generated_Source\PSoC4/ADC.c **** + 870:Generated_Source\PSoC4/ADC.c **** /* Subtract ADC offset */ + 871:Generated_Source\PSoC4/ADC.c **** adcCounts -= ADC_offset[chan]; + 1227 .loc 1 871 0 is_stmt 1 + 1228 001a 164B ldr r3, .L87 + 1229 001c 7A68 ldr r2, [r7, #4] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 38 + + + 1230 001e 5200 lsls r2, r2, #1 + 1231 0020 D35A ldrh r3, [r2, r3] + 1232 0022 19B2 sxth r1, r3 + 1233 0024 BB1C adds r3, r7, #2 + 1234 0026 1A88 ldrh r2, [r3] + 1235 0028 8BB2 uxth r3, r1 + 1236 002a D31A subs r3, r2, r3 + 1237 002c 9AB2 uxth r2, r3 + 1238 002e BB1C adds r3, r7, #2 + 1239 0030 1A80 strh r2, [r3] + 872:Generated_Source\PSoC4/ADC.c **** + 873:Generated_Source\PSoC4/ADC.c **** volts = ((float32)adcCounts * ADC_10V_COUNTS) / (float32)ADC_countsPer10Volt[chan]; + 1240 .loc 1 873 0 + 1241 0032 BB1C adds r3, r7, #2 + 1242 0034 0022 movs r2, #0 + 1243 0036 9B5E ldrsh r3, [r3, r2] + 1244 0038 1800 movs r0, r3 + 1245 003a FFF7FEFF bl __aeabi_i2f + 1246 003e 031C adds r3, r0, #0 + 1247 0040 0D49 ldr r1, .L87+4 + 1248 0042 181C adds r0, r3, #0 + 1249 0044 FFF7FEFF bl __aeabi_fmul + 1250 0048 031C adds r3, r0, #0 + 1251 004a 1C1C adds r4, r3, #0 + 1252 004c 0B4B ldr r3, .L87+8 + 1253 004e 7A68 ldr r2, [r7, #4] + 1254 0050 9200 lsls r2, r2, #2 + 1255 0052 D358 ldr r3, [r2, r3] + 1256 0054 1800 movs r0, r3 + 1257 0056 FFF7FEFF bl __aeabi_i2f + 1258 005a 031C adds r3, r0, #0 + 1259 005c 191C adds r1, r3, #0 + 1260 005e 201C adds r0, r4, #0 + 1261 0060 FFF7FEFF bl __aeabi_fdiv + 1262 0064 031C adds r3, r0, #0 + 1263 0066 FB60 str r3, [r7, #12] + 874:Generated_Source\PSoC4/ADC.c **** + 875:Generated_Source\PSoC4/ADC.c **** return( volts ); + 1264 .loc 1 875 0 + 1265 0068 FB68 ldr r3, [r7, #12] + 876:Generated_Source\PSoC4/ADC.c **** } + 1266 .loc 1 876 0 + 1267 006a 181C adds r0, r3, #0 + 1268 006c BD46 mov sp, r7 + 1269 006e 05B0 add sp, sp, #20 + 1270 @ sp needed + 1271 0070 90BD pop {r4, r7, pc} + 1272 .L88: + 1273 0072 C046 .align 2 + 1274 .L87: + 1275 0074 00000000 .word ADC_offset + 1276 0078 00002041 .word 1092616192 + 1277 007c 00000000 .word ADC_countsPer10Volt + 1278 .cfi_endproc + 1279 .LFE17: + 1280 .size ADC_CountsTo_Volts, .-ADC_CountsTo_Volts + 1281 .text + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 39 + + + 1282 .Letext0: + 1283 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 1284 .section .debug_info,"",%progbits + 1285 .Ldebug_info0: + 1286 0000 8D040000 .4byte 0x48d + 1287 0004 0400 .2byte 0x4 + 1288 0006 00000000 .4byte .Ldebug_abbrev0 + 1289 000a 04 .byte 0x4 + 1290 000b 01 .uleb128 0x1 + 1291 000c BD010000 .4byte .LASF60 + 1292 0010 0C .byte 0xc + 1293 0011 B9020000 .4byte .LASF61 + 1294 0015 D0000000 .4byte .LASF62 + 1295 0019 00000000 .4byte .Ldebug_ranges0+0 + 1296 001d 00000000 .4byte 0 + 1297 0021 00000000 .4byte .Ldebug_line0 + 1298 0025 02 .uleb128 0x2 + 1299 0026 01 .byte 0x1 + 1300 0027 06 .byte 0x6 + 1301 0028 68000000 .4byte .LASF0 + 1302 002c 02 .uleb128 0x2 + 1303 002d 01 .byte 0x1 + 1304 002e 08 .byte 0x8 + 1305 002f 16030000 .4byte .LASF1 + 1306 0033 02 .uleb128 0x2 + 1307 0034 02 .byte 0x2 + 1308 0035 05 .byte 0x5 + 1309 0036 2F030000 .4byte .LASF2 + 1310 003a 02 .uleb128 0x2 + 1311 003b 02 .byte 0x2 + 1312 003c 07 .byte 0x7 + 1313 003d 9A010000 .4byte .LASF3 + 1314 0041 02 .uleb128 0x2 + 1315 0042 04 .byte 0x4 + 1316 0043 05 .byte 0x5 + 1317 0044 8B000000 .4byte .LASF4 + 1318 0048 02 .uleb128 0x2 + 1319 0049 04 .byte 0x4 + 1320 004a 07 .byte 0x7 + 1321 004b 69010000 .4byte .LASF5 + 1322 004f 02 .uleb128 0x2 + 1323 0050 08 .byte 0x8 + 1324 0051 05 .byte 0x5 + 1325 0052 5A000000 .4byte .LASF6 + 1326 0056 02 .uleb128 0x2 + 1327 0057 08 .byte 0x8 + 1328 0058 07 .byte 0x7 + 1329 0059 32000000 .4byte .LASF7 + 1330 005d 03 .uleb128 0x3 + 1331 005e 04 .byte 0x4 + 1332 005f 05 .byte 0x5 + 1333 0060 696E7400 .ascii "int\000" + 1334 0064 02 .uleb128 0x2 + 1335 0065 04 .byte 0x4 + 1336 0066 07 .byte 0x7 + 1337 0067 55010000 .4byte .LASF8 + 1338 006b 04 .uleb128 0x4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 40 + + + 1339 006c BC000000 .4byte .LASF9 + 1340 0070 02 .byte 0x2 + 1341 0071 E401 .2byte 0x1e4 + 1342 0073 2C000000 .4byte 0x2c + 1343 0077 04 .uleb128 0x4 + 1344 0078 00000000 .4byte .LASF10 + 1345 007c 02 .byte 0x2 + 1346 007d E501 .2byte 0x1e5 + 1347 007f 3A000000 .4byte 0x3a + 1348 0083 04 .uleb128 0x4 + 1349 0084 C9000000 .4byte .LASF11 + 1350 0088 02 .byte 0x2 + 1351 0089 E601 .2byte 0x1e6 + 1352 008b 48000000 .4byte 0x48 + 1353 008f 04 .uleb128 0x4 + 1354 0090 81030000 .4byte .LASF12 + 1355 0094 02 .byte 0x2 + 1356 0095 E801 .2byte 0x1e8 + 1357 0097 33000000 .4byte 0x33 + 1358 009b 04 .uleb128 0x4 + 1359 009c 7B000000 .4byte .LASF13 + 1360 00a0 02 .byte 0x2 + 1361 00a1 E901 .2byte 0x1e9 + 1362 00a3 41000000 .4byte 0x41 + 1363 00a7 04 .uleb128 0x4 + 1364 00a8 58020000 .4byte .LASF14 + 1365 00ac 02 .byte 0x2 + 1366 00ad EA01 .2byte 0x1ea + 1367 00af B3000000 .4byte 0xb3 + 1368 00b3 02 .uleb128 0x2 + 1369 00b4 04 .byte 0x4 + 1370 00b5 04 .byte 0x4 + 1371 00b6 E2020000 .4byte .LASF15 + 1372 00ba 02 .uleb128 0x2 + 1373 00bb 08 .byte 0x8 + 1374 00bc 04 .byte 0x4 + 1375 00bd C2000000 .4byte .LASF16 + 1376 00c1 04 .uleb128 0x4 + 1377 00c2 A3020000 .4byte .LASF17 + 1378 00c6 02 .byte 0x2 + 1379 00c7 EF01 .2byte 0x1ef + 1380 00c9 4F000000 .4byte 0x4f + 1381 00cd 02 .uleb128 0x2 + 1382 00ce 01 .byte 0x1 + 1383 00cf 08 .byte 0x8 + 1384 00d0 4D030000 .4byte .LASF18 + 1385 00d4 04 .uleb128 0x4 + 1386 00d5 52020000 .4byte .LASF19 + 1387 00d9 02 .byte 0x2 + 1388 00da 9002 .2byte 0x290 + 1389 00dc E0000000 .4byte 0xe0 + 1390 00e0 05 .uleb128 0x5 + 1391 00e1 83000000 .4byte 0x83 + 1392 00e5 02 .uleb128 0x2 + 1393 00e6 08 .byte 0x8 + 1394 00e7 04 .byte 0x4 + 1395 00e8 72020000 .4byte .LASF20 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 41 + + + 1396 00ec 02 .uleb128 0x2 + 1397 00ed 04 .byte 0x4 + 1398 00ee 07 .byte 0x7 + 1399 00ef 60020000 .4byte .LASF21 + 1400 00f3 06 .uleb128 0x6 + 1401 00f4 81000000 .4byte .LASF25 + 1402 00f8 01 .byte 0x1 + 1403 00f9 3F .byte 0x3f + 1404 00fa 00000000 .4byte .LFB0 + 1405 00fe 24000000 .4byte .LFE0-.LFB0 + 1406 0102 01 .uleb128 0x1 + 1407 0103 9C .byte 0x9c + 1408 0104 07 .uleb128 0x7 + 1409 0105 29000000 .4byte .LASF36 + 1410 0109 01 .byte 0x1 + 1411 010a 5E .byte 0x5e + 1412 010b 00000000 .4byte .LFB1 + 1413 010f D8010000 .4byte .LFE1-.LFB1 + 1414 0113 01 .uleb128 0x1 + 1415 0114 9C .byte 0x9c + 1416 0115 44010000 .4byte 0x144 + 1417 0119 08 .uleb128 0x8 + 1418 011a 42030000 .4byte .LASF22 + 1419 011e 01 .byte 0x1 + 1420 011f 60 .byte 0x60 + 1421 0120 83000000 .4byte 0x83 + 1422 0124 02 .uleb128 0x2 + 1423 0125 91 .byte 0x91 + 1424 0126 74 .sleb128 -12 + 1425 0127 08 .uleb128 0x8 + 1426 0128 90010000 .4byte .LASF23 + 1427 012c 01 .byte 0x1 + 1428 012d 61 .byte 0x61 + 1429 012e 83000000 .4byte 0x83 + 1430 0132 02 .uleb128 0x2 + 1431 0133 91 .byte 0x91 + 1432 0134 6C .sleb128 -20 + 1433 0135 08 .uleb128 0x8 + 1434 0136 0F000000 .4byte .LASF24 + 1435 013a 01 .byte 0x1 + 1436 013b 62 .byte 0x62 + 1437 013c 9B000000 .4byte 0x9b + 1438 0140 02 .uleb128 0x2 + 1439 0141 91 .byte 0x91 + 1440 0142 70 .sleb128 -16 + 1441 0143 00 .byte 0 + 1442 0144 09 .uleb128 0x9 + 1443 0145 76030000 .4byte .LASF26 + 1444 0149 01 .byte 0x1 + 1445 014a 4A01 .2byte 0x14a + 1446 014c 00000000 .4byte .LFB2 + 1447 0150 2C000000 .4byte .LFE2-.LFB2 + 1448 0154 01 .uleb128 0x1 + 1449 0155 9C .byte 0x9c + 1450 0156 0A .uleb128 0xa + 1451 0157 39030000 .4byte .LASF27 + 1452 015b 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 42 + + + 1453 015c 6D01 .2byte 0x16d + 1454 015e 00000000 .4byte .LFB3 + 1455 0162 1C000000 .4byte .LFE3-.LFB3 + 1456 0166 01 .uleb128 0x1 + 1457 0167 9C .byte 0x9c + 1458 0168 0A .uleb128 0xa + 1459 0169 49000000 .4byte .LASF28 + 1460 016d 01 .byte 0x1 + 1461 016e 8701 .2byte 0x187 + 1462 0170 00000000 .4byte .LFB4 + 1463 0174 1C000000 .4byte .LFE4-.LFB4 + 1464 0178 01 .uleb128 0x1 + 1465 0179 9C .byte 0x9c + 1466 017a 0A .uleb128 0xa + 1467 017b AD010000 .4byte .LASF29 + 1468 017f 01 .byte 0x1 + 1469 0180 A001 .2byte 0x1a0 + 1470 0182 00000000 .4byte .LFB5 + 1471 0186 20000000 .4byte .LFE5-.LFB5 + 1472 018a 01 .uleb128 0x1 + 1473 018b 9C .byte 0x9c + 1474 018c 0B .uleb128 0xb + 1475 018d 8F020000 .4byte .LASF31 + 1476 0191 01 .byte 0x1 + 1477 0192 C201 .2byte 0x1c2 + 1478 0194 83000000 .4byte 0x83 + 1479 0198 00000000 .4byte .LFB6 + 1480 019c 48000000 .4byte .LFE6-.LFB6 + 1481 01a0 01 .uleb128 0x1 + 1482 01a1 9C .byte 0x9c + 1483 01a2 C5010000 .4byte 0x1c5 + 1484 01a6 0C .uleb128 0xc + 1485 01a7 3C010000 .4byte .LASF33 + 1486 01ab 01 .byte 0x1 + 1487 01ac C201 .2byte 0x1c2 + 1488 01ae 83000000 .4byte 0x83 + 1489 01b2 02 .uleb128 0x2 + 1490 01b3 91 .byte 0x91 + 1491 01b4 6C .sleb128 -20 + 1492 01b5 0D .uleb128 0xd + 1493 01b6 74000000 .4byte .LASF30 + 1494 01ba 01 .byte 0x1 + 1495 01bb C401 .2byte 0x1c4 + 1496 01bd 83000000 .4byte 0x83 + 1497 01c1 02 .uleb128 0x2 + 1498 01c2 91 .byte 0x91 + 1499 01c3 74 .sleb128 -12 + 1500 01c4 00 .byte 0 + 1501 01c5 0E .uleb128 0xe + 1502 01c6 9C030000 .4byte .LASF32 + 1503 01ca 01 .byte 0x1 + 1504 01cb F801 .2byte 0x1f8 + 1505 01cd 8F000000 .4byte 0x8f + 1506 01d1 00000000 .4byte .LFB7 + 1507 01d5 44000000 .4byte .LFE7-.LFB7 + 1508 01d9 01 .uleb128 0x1 + 1509 01da 9C .byte 0x9c + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 43 + + + 1510 01db FE010000 .4byte 0x1fe + 1511 01df 0C .uleb128 0xc + 1512 01e0 48030000 .4byte .LASF34 + 1513 01e4 01 .byte 0x1 + 1514 01e5 F801 .2byte 0x1f8 + 1515 01e7 83000000 .4byte 0x83 + 1516 01eb 02 .uleb128 0x2 + 1517 01ec 91 .byte 0x91 + 1518 01ed 6C .sleb128 -20 + 1519 01ee 0D .uleb128 0xd + 1520 01ef 95030000 .4byte .LASF35 + 1521 01f3 01 .byte 0x1 + 1522 01f4 FA01 .2byte 0x1fa + 1523 01f6 83000000 .4byte 0x83 + 1524 01fa 02 .uleb128 0x2 + 1525 01fb 91 .byte 0x91 + 1526 01fc 74 .sleb128 -12 + 1527 01fd 00 .byte 0 + 1528 01fe 0F .uleb128 0xf + 1529 01ff A9020000 .4byte .LASF37 + 1530 0203 01 .byte 0x1 + 1531 0204 2502 .2byte 0x225 + 1532 0206 00000000 .4byte .LFB8 + 1533 020a 20000000 .4byte .LFE8-.LFB8 + 1534 020e 01 .uleb128 0x1 + 1535 020f 9C .byte 0x9c + 1536 0210 24020000 .4byte 0x224 + 1537 0214 0C .uleb128 0xc + 1538 0215 2B010000 .4byte .LASF38 + 1539 0219 01 .byte 0x1 + 1540 021a 2502 .2byte 0x225 + 1541 021c 83000000 .4byte 0x83 + 1542 0220 02 .uleb128 0x2 + 1543 0221 91 .byte 0x91 + 1544 0222 74 .sleb128 -12 + 1545 0223 00 .byte 0 + 1546 0224 0F .uleb128 0xf + 1547 0225 06030000 .4byte .LASF39 + 1548 0229 01 .byte 0x1 + 1549 022a 5102 .2byte 0x251 + 1550 022c 00000000 .4byte .LFB9 + 1551 0230 30000000 .4byte .LFE9-.LFB9 + 1552 0234 01 .uleb128 0x1 + 1553 0235 9C .byte 0x9c + 1554 0236 4A020000 .4byte 0x24a + 1555 023a 0C .uleb128 0xc + 1556 023b 69020000 .4byte .LASF40 + 1557 023f 01 .byte 0x1 + 1558 0240 5102 .2byte 0x251 + 1559 0242 83000000 .4byte 0x83 + 1560 0246 02 .uleb128 0x2 + 1561 0247 91 .byte 0x91 + 1562 0248 74 .sleb128 -12 + 1563 0249 00 .byte 0 + 1564 024a 0F .uleb128 0xf + 1565 024b 7E020000 .4byte .LASF41 + 1566 024f 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 44 + + + 1567 0250 6602 .2byte 0x266 + 1568 0252 00000000 .4byte .LFB10 + 1569 0256 30000000 .4byte .LFE10-.LFB10 + 1570 025a 01 .uleb128 0x1 + 1571 025b 9C .byte 0x9c + 1572 025c 70020000 .4byte 0x270 + 1573 0260 0C .uleb128 0xc + 1574 0261 E8020000 .4byte .LASF42 + 1575 0265 01 .byte 0x1 + 1576 0266 6602 .2byte 0x266 + 1577 0268 83000000 .4byte 0x83 + 1578 026c 02 .uleb128 0x2 + 1579 026d 91 .byte 0x91 + 1580 026e 74 .sleb128 -12 + 1581 026f 00 .byte 0 + 1582 0270 0F .uleb128 0xf + 1583 0271 44010000 .4byte .LASF43 + 1584 0275 01 .byte 0x1 + 1585 0276 7E02 .2byte 0x27e + 1586 0278 00000000 .4byte .LFB11 + 1587 027c 20000000 .4byte .LFE11-.LFB11 + 1588 0280 01 .uleb128 0x1 + 1589 0281 9C .byte 0x9c + 1590 0282 96020000 .4byte 0x296 + 1591 0286 0C .uleb128 0xc + 1592 0287 2B010000 .4byte .LASF38 + 1593 028b 01 .byte 0x1 + 1594 028c 7E02 .2byte 0x27e + 1595 028e 83000000 .4byte 0x83 + 1596 0292 02 .uleb128 0x2 + 1597 0293 91 .byte 0x91 + 1598 0294 74 .sleb128 -12 + 1599 0295 00 .byte 0 + 1600 0296 0F .uleb128 0xf + 1601 0297 7B010000 .4byte .LASF44 + 1602 029b 01 .byte 0x1 + 1603 029c 9502 .2byte 0x295 + 1604 029e 00000000 .4byte .LFB12 + 1605 02a2 20000000 .4byte .LFE12-.LFB12 + 1606 02a6 01 .uleb128 0x1 + 1607 02a7 9C .byte 0x9c + 1608 02a8 BC020000 .4byte 0x2bc + 1609 02ac 0C .uleb128 0xc + 1610 02ad 2B010000 .4byte .LASF38 + 1611 02b1 01 .byte 0x1 + 1612 02b2 9502 .2byte 0x295 + 1613 02b4 83000000 .4byte 0x83 + 1614 02b8 02 .uleb128 0x2 + 1615 02b9 91 .byte 0x91 + 1616 02ba 74 .sleb128 -12 + 1617 02bb 00 .byte 0 + 1618 02bc 10 .uleb128 0x10 + 1619 02bd 87030000 .4byte .LASF45 + 1620 02c1 01 .byte 0x1 + 1621 02c2 B102 .2byte 0x2b1 + 1622 02c4 00000000 .4byte .LFB13 + 1623 02c8 34000000 .4byte .LFE13-.LFB13 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 45 + + + 1624 02cc 01 .uleb128 0x1 + 1625 02cd 9C .byte 0x9c + 1626 02ce F1020000 .4byte 0x2f1 + 1627 02d2 0C .uleb128 0xc + 1628 02d3 48030000 .4byte .LASF34 + 1629 02d7 01 .byte 0x1 + 1630 02d8 B102 .2byte 0x2b1 + 1631 02da 83000000 .4byte 0x83 + 1632 02de 02 .uleb128 0x2 + 1633 02df 91 .byte 0x91 + 1634 02e0 74 .sleb128 -12 + 1635 02e1 0C .uleb128 0xc + 1636 02e2 65030000 .4byte .LASF46 + 1637 02e6 01 .byte 0x1 + 1638 02e7 B102 .2byte 0x2b1 + 1639 02e9 8F000000 .4byte 0x8f + 1640 02ed 02 .uleb128 0x2 + 1641 02ee 91 .byte 0x91 + 1642 02ef 72 .sleb128 -14 + 1643 02f0 00 .byte 0 + 1644 02f1 10 .uleb128 0x10 + 1645 02f2 D6020000 .4byte .LASF47 + 1646 02f6 01 .byte 0x1 + 1647 02f7 D302 .2byte 0x2d3 + 1648 02f9 00000000 .4byte .LFB14 + 1649 02fd 2C000000 .4byte .LFE14-.LFB14 + 1650 0301 01 .uleb128 0x1 + 1651 0302 9C .byte 0x9c + 1652 0303 26030000 .4byte 0x326 + 1653 0307 0C .uleb128 0xc + 1654 0308 48030000 .4byte .LASF34 + 1655 030c 01 .byte 0x1 + 1656 030d D302 .2byte 0x2d3 + 1657 030f 83000000 .4byte 0x83 + 1658 0313 02 .uleb128 0x2 + 1659 0314 91 .byte 0x91 + 1660 0315 74 .sleb128 -12 + 1661 0316 0C .uleb128 0xc + 1662 0317 07000000 .4byte .LASF48 + 1663 031b 01 .byte 0x1 + 1664 031c D302 .2byte 0x2d3 + 1665 031e 9B000000 .4byte 0x9b + 1666 0322 02 .uleb128 0x2 + 1667 0323 91 .byte 0x91 + 1668 0324 70 .sleb128 -16 + 1669 0325 00 .byte 0 + 1670 0326 0E .uleb128 0xe + 1671 0327 F2020000 .4byte .LASF49 + 1672 032b 01 .byte 0x1 + 1673 032c F402 .2byte 0x2f4 + 1674 032e 8F000000 .4byte 0x8f + 1675 0332 00000000 .4byte .LFB15 + 1676 0336 A0000000 .4byte .LFE15-.LFB15 + 1677 033a 01 .uleb128 0x1 + 1678 033b 9C .byte 0x9c + 1679 033c 6E030000 .4byte 0x36e + 1680 0340 0C .uleb128 0xc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 46 + + + 1681 0341 48030000 .4byte .LASF34 + 1682 0345 01 .byte 0x1 + 1683 0346 F402 .2byte 0x2f4 + 1684 0348 83000000 .4byte 0x83 + 1685 034c 02 .uleb128 0x2 + 1686 034d 91 .byte 0x91 + 1687 034e 6C .sleb128 -20 + 1688 034f 0C .uleb128 0xc + 1689 0350 6C030000 .4byte .LASF50 + 1690 0354 01 .byte 0x1 + 1691 0355 F402 .2byte 0x2f4 + 1692 0357 8F000000 .4byte 0x8f + 1693 035b 02 .uleb128 0x2 + 1694 035c 91 .byte 0x91 + 1695 035d 6A .sleb128 -22 + 1696 035e 0D .uleb128 0xd + 1697 035f 4B020000 .4byte .LASF51 + 1698 0363 01 .byte 0x1 + 1699 0364 F602 .2byte 0x2f6 + 1700 0366 8F000000 .4byte 0x8f + 1701 036a 02 .uleb128 0x2 + 1702 036b 91 .byte 0x91 + 1703 036c 76 .sleb128 -10 + 1704 036d 00 .byte 0 + 1705 036e 0E .uleb128 0xe + 1706 036f 94000000 .4byte .LASF52 + 1707 0373 01 .byte 0x1 + 1708 0374 2A03 .2byte 0x32a + 1709 0376 9B000000 .4byte 0x9b + 1710 037a 00000000 .4byte .LFB16 + 1711 037e 90000000 .4byte .LFE16-.LFB16 + 1712 0382 01 .uleb128 0x1 + 1713 0383 9C .byte 0x9c + 1714 0384 B6030000 .4byte 0x3b6 + 1715 0388 0C .uleb128 0xc + 1716 0389 48030000 .4byte .LASF34 + 1717 038d 01 .byte 0x1 + 1718 038e 2A03 .2byte 0x32a + 1719 0390 83000000 .4byte 0x83 + 1720 0394 02 .uleb128 0x2 + 1721 0395 91 .byte 0x91 + 1722 0396 64 .sleb128 -28 + 1723 0397 0C .uleb128 0xc + 1724 0398 6C030000 .4byte .LASF50 + 1725 039c 01 .byte 0x1 + 1726 039d 2A03 .2byte 0x32a + 1727 039f 8F000000 .4byte 0x8f + 1728 03a3 02 .uleb128 0x2 + 1729 03a4 91 .byte 0x91 + 1730 03a5 62 .sleb128 -30 + 1731 03a6 0D .uleb128 0xd + 1732 03a7 62010000 .4byte .LASF53 + 1733 03ab 01 .byte 0x1 + 1734 03ac 2C03 .2byte 0x32c + 1735 03ae C1000000 .4byte 0xc1 + 1736 03b2 02 .uleb128 0x2 + 1737 03b3 91 .byte 0x91 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 47 + + + 1738 03b4 68 .sleb128 -24 + 1739 03b5 00 .byte 0 + 1740 03b6 0E .uleb128 0xe + 1741 03b7 16000000 .4byte .LASF54 + 1742 03bb 01 .byte 0x1 + 1743 03bc 5703 .2byte 0x357 + 1744 03be A7000000 .4byte 0xa7 + 1745 03c2 00000000 .4byte .LFB17 + 1746 03c6 80000000 .4byte .LFE17-.LFB17 + 1747 03ca 01 .uleb128 0x1 + 1748 03cb 9C .byte 0x9c + 1749 03cc FE030000 .4byte 0x3fe + 1750 03d0 0C .uleb128 0xc + 1751 03d1 48030000 .4byte .LASF34 + 1752 03d5 01 .byte 0x1 + 1753 03d6 5703 .2byte 0x357 + 1754 03d8 83000000 .4byte 0x83 + 1755 03dc 02 .uleb128 0x2 + 1756 03dd 91 .byte 0x91 + 1757 03de 64 .sleb128 -28 + 1758 03df 0C .uleb128 0xc + 1759 03e0 6C030000 .4byte .LASF50 + 1760 03e4 01 .byte 0x1 + 1761 03e5 5703 .2byte 0x357 + 1762 03e7 8F000000 .4byte 0x8f + 1763 03eb 02 .uleb128 0x2 + 1764 03ec 91 .byte 0x91 + 1765 03ed 62 .sleb128 -30 + 1766 03ee 0D .uleb128 0xd + 1767 03ef 8A010000 .4byte .LASF55 + 1768 03f3 01 .byte 0x1 + 1769 03f4 5903 .2byte 0x359 + 1770 03f6 A7000000 .4byte 0xa7 + 1771 03fa 02 .uleb128 0x2 + 1772 03fb 91 .byte 0x91 + 1773 03fc 6C .sleb128 -20 + 1774 03fd 00 .byte 0 + 1775 03fe 11 .uleb128 0x11 + 1776 03ff 0E040000 .4byte 0x40e + 1777 0403 0E040000 .4byte 0x40e + 1778 0407 12 .uleb128 0x12 + 1779 0408 EC000000 .4byte 0xec + 1780 040c 00 .byte 0 + 1781 040d 00 .byte 0 + 1782 040e 13 .uleb128 0x13 + 1783 040f 83000000 .4byte 0x83 + 1784 0413 08 .uleb128 0x8 + 1785 0414 52030000 .4byte .LASF56 + 1786 0418 01 .byte 0x1 + 1787 0419 21 .byte 0x21 + 1788 041a 24040000 .4byte 0x424 + 1789 041e 05 .uleb128 0x5 + 1790 041f 03 .byte 0x3 + 1791 0420 00000000 .4byte ADC_channelsConfig + 1792 0424 13 .uleb128 0x13 + 1793 0425 FE030000 .4byte 0x3fe + 1794 0429 14 .uleb128 0x14 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 48 + + + 1795 042a 30010000 .4byte .LASF57 + 1796 042e 01 .byte 0x1 + 1797 042f 18 .byte 0x18 + 1798 0430 6B000000 .4byte 0x6b + 1799 0434 05 .uleb128 0x5 + 1800 0435 03 .byte 0x3 + 1801 0436 00000000 .4byte ADC_initVar + 1802 043a 11 .uleb128 0x11 + 1803 043b 4A040000 .4byte 0x44a + 1804 043f 4A040000 .4byte 0x44a + 1805 0443 12 .uleb128 0x12 + 1806 0444 EC000000 .4byte 0xec + 1807 0448 00 .byte 0 + 1808 0449 00 .byte 0 + 1809 044a 05 .uleb128 0x5 + 1810 044b 8F000000 .4byte 0x8f + 1811 044f 14 .uleb128 0x14 + 1812 0450 24030000 .4byte .LASF58 + 1813 0454 01 .byte 0x1 + 1814 0455 19 .byte 0x19 + 1815 0456 60040000 .4byte 0x460 + 1816 045a 05 .uleb128 0x5 + 1817 045b 03 .byte 0x3 + 1818 045c 00000000 .4byte ADC_offset + 1819 0460 05 .uleb128 0x5 + 1820 0461 3A040000 .4byte 0x43a + 1821 0465 11 .uleb128 0x11 + 1822 0466 75040000 .4byte 0x475 + 1823 046a 75040000 .4byte 0x475 + 1824 046e 12 .uleb128 0x12 + 1825 046f EC000000 .4byte 0xec + 1826 0473 00 .byte 0 + 1827 0474 00 .byte 0 + 1828 0475 05 .uleb128 0x5 + 1829 0476 9B000000 .4byte 0x9b + 1830 047a 14 .uleb128 0x14 + 1831 047b A8000000 .4byte .LASF59 + 1832 047f 01 .byte 0x1 + 1833 0480 1A .byte 0x1a + 1834 0481 8B040000 .4byte 0x48b + 1835 0485 05 .uleb128 0x5 + 1836 0486 03 .byte 0x3 + 1837 0487 00000000 .4byte ADC_countsPer10Volt + 1838 048b 05 .uleb128 0x5 + 1839 048c 65040000 .4byte 0x465 + 1840 0490 00 .byte 0 + 1841 .section .debug_abbrev,"",%progbits + 1842 .Ldebug_abbrev0: + 1843 0000 01 .uleb128 0x1 + 1844 0001 11 .uleb128 0x11 + 1845 0002 01 .byte 0x1 + 1846 0003 25 .uleb128 0x25 + 1847 0004 0E .uleb128 0xe + 1848 0005 13 .uleb128 0x13 + 1849 0006 0B .uleb128 0xb + 1850 0007 03 .uleb128 0x3 + 1851 0008 0E .uleb128 0xe + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 49 + + + 1852 0009 1B .uleb128 0x1b + 1853 000a 0E .uleb128 0xe + 1854 000b 55 .uleb128 0x55 + 1855 000c 17 .uleb128 0x17 + 1856 000d 11 .uleb128 0x11 + 1857 000e 01 .uleb128 0x1 + 1858 000f 10 .uleb128 0x10 + 1859 0010 17 .uleb128 0x17 + 1860 0011 00 .byte 0 + 1861 0012 00 .byte 0 + 1862 0013 02 .uleb128 0x2 + 1863 0014 24 .uleb128 0x24 + 1864 0015 00 .byte 0 + 1865 0016 0B .uleb128 0xb + 1866 0017 0B .uleb128 0xb + 1867 0018 3E .uleb128 0x3e + 1868 0019 0B .uleb128 0xb + 1869 001a 03 .uleb128 0x3 + 1870 001b 0E .uleb128 0xe + 1871 001c 00 .byte 0 + 1872 001d 00 .byte 0 + 1873 001e 03 .uleb128 0x3 + 1874 001f 24 .uleb128 0x24 + 1875 0020 00 .byte 0 + 1876 0021 0B .uleb128 0xb + 1877 0022 0B .uleb128 0xb + 1878 0023 3E .uleb128 0x3e + 1879 0024 0B .uleb128 0xb + 1880 0025 03 .uleb128 0x3 + 1881 0026 08 .uleb128 0x8 + 1882 0027 00 .byte 0 + 1883 0028 00 .byte 0 + 1884 0029 04 .uleb128 0x4 + 1885 002a 16 .uleb128 0x16 + 1886 002b 00 .byte 0 + 1887 002c 03 .uleb128 0x3 + 1888 002d 0E .uleb128 0xe + 1889 002e 3A .uleb128 0x3a + 1890 002f 0B .uleb128 0xb + 1891 0030 3B .uleb128 0x3b + 1892 0031 05 .uleb128 0x5 + 1893 0032 49 .uleb128 0x49 + 1894 0033 13 .uleb128 0x13 + 1895 0034 00 .byte 0 + 1896 0035 00 .byte 0 + 1897 0036 05 .uleb128 0x5 + 1898 0037 35 .uleb128 0x35 + 1899 0038 00 .byte 0 + 1900 0039 49 .uleb128 0x49 + 1901 003a 13 .uleb128 0x13 + 1902 003b 00 .byte 0 + 1903 003c 00 .byte 0 + 1904 003d 06 .uleb128 0x6 + 1905 003e 2E .uleb128 0x2e + 1906 003f 00 .byte 0 + 1907 0040 3F .uleb128 0x3f + 1908 0041 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 50 + + + 1909 0042 03 .uleb128 0x3 + 1910 0043 0E .uleb128 0xe + 1911 0044 3A .uleb128 0x3a + 1912 0045 0B .uleb128 0xb + 1913 0046 3B .uleb128 0x3b + 1914 0047 0B .uleb128 0xb + 1915 0048 27 .uleb128 0x27 + 1916 0049 19 .uleb128 0x19 + 1917 004a 11 .uleb128 0x11 + 1918 004b 01 .uleb128 0x1 + 1919 004c 12 .uleb128 0x12 + 1920 004d 06 .uleb128 0x6 + 1921 004e 40 .uleb128 0x40 + 1922 004f 18 .uleb128 0x18 + 1923 0050 9642 .uleb128 0x2116 + 1924 0052 19 .uleb128 0x19 + 1925 0053 00 .byte 0 + 1926 0054 00 .byte 0 + 1927 0055 07 .uleb128 0x7 + 1928 0056 2E .uleb128 0x2e + 1929 0057 01 .byte 0x1 + 1930 0058 3F .uleb128 0x3f + 1931 0059 19 .uleb128 0x19 + 1932 005a 03 .uleb128 0x3 + 1933 005b 0E .uleb128 0xe + 1934 005c 3A .uleb128 0x3a + 1935 005d 0B .uleb128 0xb + 1936 005e 3B .uleb128 0x3b + 1937 005f 0B .uleb128 0xb + 1938 0060 27 .uleb128 0x27 + 1939 0061 19 .uleb128 0x19 + 1940 0062 11 .uleb128 0x11 + 1941 0063 01 .uleb128 0x1 + 1942 0064 12 .uleb128 0x12 + 1943 0065 06 .uleb128 0x6 + 1944 0066 40 .uleb128 0x40 + 1945 0067 18 .uleb128 0x18 + 1946 0068 9642 .uleb128 0x2116 + 1947 006a 19 .uleb128 0x19 + 1948 006b 01 .uleb128 0x1 + 1949 006c 13 .uleb128 0x13 + 1950 006d 00 .byte 0 + 1951 006e 00 .byte 0 + 1952 006f 08 .uleb128 0x8 + 1953 0070 34 .uleb128 0x34 + 1954 0071 00 .byte 0 + 1955 0072 03 .uleb128 0x3 + 1956 0073 0E .uleb128 0xe + 1957 0074 3A .uleb128 0x3a + 1958 0075 0B .uleb128 0xb + 1959 0076 3B .uleb128 0x3b + 1960 0077 0B .uleb128 0xb + 1961 0078 49 .uleb128 0x49 + 1962 0079 13 .uleb128 0x13 + 1963 007a 02 .uleb128 0x2 + 1964 007b 18 .uleb128 0x18 + 1965 007c 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 51 + + + 1966 007d 00 .byte 0 + 1967 007e 09 .uleb128 0x9 + 1968 007f 2E .uleb128 0x2e + 1969 0080 00 .byte 0 + 1970 0081 3F .uleb128 0x3f + 1971 0082 19 .uleb128 0x19 + 1972 0083 03 .uleb128 0x3 + 1973 0084 0E .uleb128 0xe + 1974 0085 3A .uleb128 0x3a + 1975 0086 0B .uleb128 0xb + 1976 0087 3B .uleb128 0x3b + 1977 0088 05 .uleb128 0x5 + 1978 0089 27 .uleb128 0x27 + 1979 008a 19 .uleb128 0x19 + 1980 008b 11 .uleb128 0x11 + 1981 008c 01 .uleb128 0x1 + 1982 008d 12 .uleb128 0x12 + 1983 008e 06 .uleb128 0x6 + 1984 008f 40 .uleb128 0x40 + 1985 0090 18 .uleb128 0x18 + 1986 0091 9642 .uleb128 0x2116 + 1987 0093 19 .uleb128 0x19 + 1988 0094 00 .byte 0 + 1989 0095 00 .byte 0 + 1990 0096 0A .uleb128 0xa + 1991 0097 2E .uleb128 0x2e + 1992 0098 00 .byte 0 + 1993 0099 3F .uleb128 0x3f + 1994 009a 19 .uleb128 0x19 + 1995 009b 03 .uleb128 0x3 + 1996 009c 0E .uleb128 0xe + 1997 009d 3A .uleb128 0x3a + 1998 009e 0B .uleb128 0xb + 1999 009f 3B .uleb128 0x3b + 2000 00a0 05 .uleb128 0x5 + 2001 00a1 27 .uleb128 0x27 + 2002 00a2 19 .uleb128 0x19 + 2003 00a3 11 .uleb128 0x11 + 2004 00a4 01 .uleb128 0x1 + 2005 00a5 12 .uleb128 0x12 + 2006 00a6 06 .uleb128 0x6 + 2007 00a7 40 .uleb128 0x40 + 2008 00a8 18 .uleb128 0x18 + 2009 00a9 9742 .uleb128 0x2117 + 2010 00ab 19 .uleb128 0x19 + 2011 00ac 00 .byte 0 + 2012 00ad 00 .byte 0 + 2013 00ae 0B .uleb128 0xb + 2014 00af 2E .uleb128 0x2e + 2015 00b0 01 .byte 0x1 + 2016 00b1 3F .uleb128 0x3f + 2017 00b2 19 .uleb128 0x19 + 2018 00b3 03 .uleb128 0x3 + 2019 00b4 0E .uleb128 0xe + 2020 00b5 3A .uleb128 0x3a + 2021 00b6 0B .uleb128 0xb + 2022 00b7 3B .uleb128 0x3b + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 52 + + + 2023 00b8 05 .uleb128 0x5 + 2024 00b9 27 .uleb128 0x27 + 2025 00ba 19 .uleb128 0x19 + 2026 00bb 49 .uleb128 0x49 + 2027 00bc 13 .uleb128 0x13 + 2028 00bd 11 .uleb128 0x11 + 2029 00be 01 .uleb128 0x1 + 2030 00bf 12 .uleb128 0x12 + 2031 00c0 06 .uleb128 0x6 + 2032 00c1 40 .uleb128 0x40 + 2033 00c2 18 .uleb128 0x18 + 2034 00c3 9742 .uleb128 0x2117 + 2035 00c5 19 .uleb128 0x19 + 2036 00c6 01 .uleb128 0x1 + 2037 00c7 13 .uleb128 0x13 + 2038 00c8 00 .byte 0 + 2039 00c9 00 .byte 0 + 2040 00ca 0C .uleb128 0xc + 2041 00cb 05 .uleb128 0x5 + 2042 00cc 00 .byte 0 + 2043 00cd 03 .uleb128 0x3 + 2044 00ce 0E .uleb128 0xe + 2045 00cf 3A .uleb128 0x3a + 2046 00d0 0B .uleb128 0xb + 2047 00d1 3B .uleb128 0x3b + 2048 00d2 05 .uleb128 0x5 + 2049 00d3 49 .uleb128 0x49 + 2050 00d4 13 .uleb128 0x13 + 2051 00d5 02 .uleb128 0x2 + 2052 00d6 18 .uleb128 0x18 + 2053 00d7 00 .byte 0 + 2054 00d8 00 .byte 0 + 2055 00d9 0D .uleb128 0xd + 2056 00da 34 .uleb128 0x34 + 2057 00db 00 .byte 0 + 2058 00dc 03 .uleb128 0x3 + 2059 00dd 0E .uleb128 0xe + 2060 00de 3A .uleb128 0x3a + 2061 00df 0B .uleb128 0xb + 2062 00e0 3B .uleb128 0x3b + 2063 00e1 05 .uleb128 0x5 + 2064 00e2 49 .uleb128 0x49 + 2065 00e3 13 .uleb128 0x13 + 2066 00e4 02 .uleb128 0x2 + 2067 00e5 18 .uleb128 0x18 + 2068 00e6 00 .byte 0 + 2069 00e7 00 .byte 0 + 2070 00e8 0E .uleb128 0xe + 2071 00e9 2E .uleb128 0x2e + 2072 00ea 01 .byte 0x1 + 2073 00eb 3F .uleb128 0x3f + 2074 00ec 19 .uleb128 0x19 + 2075 00ed 03 .uleb128 0x3 + 2076 00ee 0E .uleb128 0xe + 2077 00ef 3A .uleb128 0x3a + 2078 00f0 0B .uleb128 0xb + 2079 00f1 3B .uleb128 0x3b + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 53 + + + 2080 00f2 05 .uleb128 0x5 + 2081 00f3 27 .uleb128 0x27 + 2082 00f4 19 .uleb128 0x19 + 2083 00f5 49 .uleb128 0x49 + 2084 00f6 13 .uleb128 0x13 + 2085 00f7 11 .uleb128 0x11 + 2086 00f8 01 .uleb128 0x1 + 2087 00f9 12 .uleb128 0x12 + 2088 00fa 06 .uleb128 0x6 + 2089 00fb 40 .uleb128 0x40 + 2090 00fc 18 .uleb128 0x18 + 2091 00fd 9642 .uleb128 0x2116 + 2092 00ff 19 .uleb128 0x19 + 2093 0100 01 .uleb128 0x1 + 2094 0101 13 .uleb128 0x13 + 2095 0102 00 .byte 0 + 2096 0103 00 .byte 0 + 2097 0104 0F .uleb128 0xf + 2098 0105 2E .uleb128 0x2e + 2099 0106 01 .byte 0x1 + 2100 0107 3F .uleb128 0x3f + 2101 0108 19 .uleb128 0x19 + 2102 0109 03 .uleb128 0x3 + 2103 010a 0E .uleb128 0xe + 2104 010b 3A .uleb128 0x3a + 2105 010c 0B .uleb128 0xb + 2106 010d 3B .uleb128 0x3b + 2107 010e 05 .uleb128 0x5 + 2108 010f 27 .uleb128 0x27 + 2109 0110 19 .uleb128 0x19 + 2110 0111 11 .uleb128 0x11 + 2111 0112 01 .uleb128 0x1 + 2112 0113 12 .uleb128 0x12 + 2113 0114 06 .uleb128 0x6 + 2114 0115 40 .uleb128 0x40 + 2115 0116 18 .uleb128 0x18 + 2116 0117 9742 .uleb128 0x2117 + 2117 0119 19 .uleb128 0x19 + 2118 011a 01 .uleb128 0x1 + 2119 011b 13 .uleb128 0x13 + 2120 011c 00 .byte 0 + 2121 011d 00 .byte 0 + 2122 011e 10 .uleb128 0x10 + 2123 011f 2E .uleb128 0x2e + 2124 0120 01 .byte 0x1 + 2125 0121 3F .uleb128 0x3f + 2126 0122 19 .uleb128 0x19 + 2127 0123 03 .uleb128 0x3 + 2128 0124 0E .uleb128 0xe + 2129 0125 3A .uleb128 0x3a + 2130 0126 0B .uleb128 0xb + 2131 0127 3B .uleb128 0x3b + 2132 0128 05 .uleb128 0x5 + 2133 0129 27 .uleb128 0x27 + 2134 012a 19 .uleb128 0x19 + 2135 012b 11 .uleb128 0x11 + 2136 012c 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 54 + + + 2137 012d 12 .uleb128 0x12 + 2138 012e 06 .uleb128 0x6 + 2139 012f 40 .uleb128 0x40 + 2140 0130 18 .uleb128 0x18 + 2141 0131 9642 .uleb128 0x2116 + 2142 0133 19 .uleb128 0x19 + 2143 0134 01 .uleb128 0x1 + 2144 0135 13 .uleb128 0x13 + 2145 0136 00 .byte 0 + 2146 0137 00 .byte 0 + 2147 0138 11 .uleb128 0x11 + 2148 0139 01 .uleb128 0x1 + 2149 013a 01 .byte 0x1 + 2150 013b 49 .uleb128 0x49 + 2151 013c 13 .uleb128 0x13 + 2152 013d 01 .uleb128 0x1 + 2153 013e 13 .uleb128 0x13 + 2154 013f 00 .byte 0 + 2155 0140 00 .byte 0 + 2156 0141 12 .uleb128 0x12 + 2157 0142 21 .uleb128 0x21 + 2158 0143 00 .byte 0 + 2159 0144 49 .uleb128 0x49 + 2160 0145 13 .uleb128 0x13 + 2161 0146 2F .uleb128 0x2f + 2162 0147 0B .uleb128 0xb + 2163 0148 00 .byte 0 + 2164 0149 00 .byte 0 + 2165 014a 13 .uleb128 0x13 + 2166 014b 26 .uleb128 0x26 + 2167 014c 00 .byte 0 + 2168 014d 49 .uleb128 0x49 + 2169 014e 13 .uleb128 0x13 + 2170 014f 00 .byte 0 + 2171 0150 00 .byte 0 + 2172 0151 14 .uleb128 0x14 + 2173 0152 34 .uleb128 0x34 + 2174 0153 00 .byte 0 + 2175 0154 03 .uleb128 0x3 + 2176 0155 0E .uleb128 0xe + 2177 0156 3A .uleb128 0x3a + 2178 0157 0B .uleb128 0xb + 2179 0158 3B .uleb128 0x3b + 2180 0159 0B .uleb128 0xb + 2181 015a 49 .uleb128 0x49 + 2182 015b 13 .uleb128 0x13 + 2183 015c 3F .uleb128 0x3f + 2184 015d 19 .uleb128 0x19 + 2185 015e 02 .uleb128 0x2 + 2186 015f 18 .uleb128 0x18 + 2187 0160 00 .byte 0 + 2188 0161 00 .byte 0 + 2189 0162 00 .byte 0 + 2190 .section .debug_aranges,"",%progbits + 2191 0000 A4000000 .4byte 0xa4 + 2192 0004 0200 .2byte 0x2 + 2193 0006 00000000 .4byte .Ldebug_info0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 55 + + + 2194 000a 04 .byte 0x4 + 2195 000b 00 .byte 0 + 2196 000c 0000 .2byte 0 + 2197 000e 0000 .2byte 0 + 2198 0010 00000000 .4byte .LFB0 + 2199 0014 24000000 .4byte .LFE0-.LFB0 + 2200 0018 00000000 .4byte .LFB1 + 2201 001c D8010000 .4byte .LFE1-.LFB1 + 2202 0020 00000000 .4byte .LFB2 + 2203 0024 2C000000 .4byte .LFE2-.LFB2 + 2204 0028 00000000 .4byte .LFB3 + 2205 002c 1C000000 .4byte .LFE3-.LFB3 + 2206 0030 00000000 .4byte .LFB4 + 2207 0034 1C000000 .4byte .LFE4-.LFB4 + 2208 0038 00000000 .4byte .LFB5 + 2209 003c 20000000 .4byte .LFE5-.LFB5 + 2210 0040 00000000 .4byte .LFB6 + 2211 0044 48000000 .4byte .LFE6-.LFB6 + 2212 0048 00000000 .4byte .LFB7 + 2213 004c 44000000 .4byte .LFE7-.LFB7 + 2214 0050 00000000 .4byte .LFB8 + 2215 0054 20000000 .4byte .LFE8-.LFB8 + 2216 0058 00000000 .4byte .LFB9 + 2217 005c 30000000 .4byte .LFE9-.LFB9 + 2218 0060 00000000 .4byte .LFB10 + 2219 0064 30000000 .4byte .LFE10-.LFB10 + 2220 0068 00000000 .4byte .LFB11 + 2221 006c 20000000 .4byte .LFE11-.LFB11 + 2222 0070 00000000 .4byte .LFB12 + 2223 0074 20000000 .4byte .LFE12-.LFB12 + 2224 0078 00000000 .4byte .LFB13 + 2225 007c 34000000 .4byte .LFE13-.LFB13 + 2226 0080 00000000 .4byte .LFB14 + 2227 0084 2C000000 .4byte .LFE14-.LFB14 + 2228 0088 00000000 .4byte .LFB15 + 2229 008c A0000000 .4byte .LFE15-.LFB15 + 2230 0090 00000000 .4byte .LFB16 + 2231 0094 90000000 .4byte .LFE16-.LFB16 + 2232 0098 00000000 .4byte .LFB17 + 2233 009c 80000000 .4byte .LFE17-.LFB17 + 2234 00a0 00000000 .4byte 0 + 2235 00a4 00000000 .4byte 0 + 2236 .section .debug_ranges,"",%progbits + 2237 .Ldebug_ranges0: + 2238 0000 00000000 .4byte .LFB0 + 2239 0004 24000000 .4byte .LFE0 + 2240 0008 00000000 .4byte .LFB1 + 2241 000c D8010000 .4byte .LFE1 + 2242 0010 00000000 .4byte .LFB2 + 2243 0014 2C000000 .4byte .LFE2 + 2244 0018 00000000 .4byte .LFB3 + 2245 001c 1C000000 .4byte .LFE3 + 2246 0020 00000000 .4byte .LFB4 + 2247 0024 1C000000 .4byte .LFE4 + 2248 0028 00000000 .4byte .LFB5 + 2249 002c 20000000 .4byte .LFE5 + 2250 0030 00000000 .4byte .LFB6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 56 + + + 2251 0034 48000000 .4byte .LFE6 + 2252 0038 00000000 .4byte .LFB7 + 2253 003c 44000000 .4byte .LFE7 + 2254 0040 00000000 .4byte .LFB8 + 2255 0044 20000000 .4byte .LFE8 + 2256 0048 00000000 .4byte .LFB9 + 2257 004c 30000000 .4byte .LFE9 + 2258 0050 00000000 .4byte .LFB10 + 2259 0054 30000000 .4byte .LFE10 + 2260 0058 00000000 .4byte .LFB11 + 2261 005c 20000000 .4byte .LFE11 + 2262 0060 00000000 .4byte .LFB12 + 2263 0064 20000000 .4byte .LFE12 + 2264 0068 00000000 .4byte .LFB13 + 2265 006c 34000000 .4byte .LFE13 + 2266 0070 00000000 .4byte .LFB14 + 2267 0074 2C000000 .4byte .LFE14 + 2268 0078 00000000 .4byte .LFB15 + 2269 007c A0000000 .4byte .LFE15 + 2270 0080 00000000 .4byte .LFB16 + 2271 0084 90000000 .4byte .LFE16 + 2272 0088 00000000 .4byte .LFB17 + 2273 008c 80000000 .4byte .LFE17 + 2274 0090 00000000 .4byte 0 + 2275 0094 00000000 .4byte 0 + 2276 .section .debug_line,"",%progbits + 2277 .Ldebug_line0: + 2278 0000 90020000 .section .debug_str,"MS",%progbits,1 + 2278 02004000 + 2278 00000201 + 2278 FB0E0D00 + 2278 01010101 + 2279 .LASF10: + 2280 0000 75696E74 .ascii "uint16\000" + 2280 313600 + 2281 .LASF48: + 2282 0007 61646347 .ascii "adcGain\000" + 2282 61696E00 + 2283 .LASF24: + 2284 000f 636F756E .ascii "counts\000" + 2284 747300 + 2285 .LASF54: + 2286 0016 4144435F .ascii "ADC_CountsTo_Volts\000" + 2286 436F756E + 2286 7473546F + 2286 5F566F6C + 2286 747300 + 2287 .LASF36: + 2288 0029 4144435F .ascii "ADC_Init\000" + 2288 496E6974 + 2288 00 + 2289 .LASF7: + 2290 0032 6C6F6E67 .ascii "long long unsigned int\000" + 2290 206C6F6E + 2290 6720756E + 2290 7369676E + 2290 65642069 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 57 + + + 2291 .LASF28: + 2292 0049 4144435F .ascii "ADC_StartConvert\000" + 2292 53746172 + 2292 74436F6E + 2292 76657274 + 2292 00 + 2293 .LASF6: + 2294 005a 6C6F6E67 .ascii "long long int\000" + 2294 206C6F6E + 2294 6720696E + 2294 7400 + 2295 .LASF0: + 2296 0068 7369676E .ascii "signed char\000" + 2296 65642063 + 2296 68617200 + 2297 .LASF30: + 2298 0074 73746174 .ascii "status\000" + 2298 757300 + 2299 .LASF13: + 2300 007b 696E7433 .ascii "int32\000" + 2300 3200 + 2301 .LASF25: + 2302 0081 4144435F .ascii "ADC_Start\000" + 2302 53746172 + 2302 7400 + 2303 .LASF4: + 2304 008b 6C6F6E67 .ascii "long int\000" + 2304 20696E74 + 2304 00 + 2305 .LASF52: + 2306 0094 4144435F .ascii "ADC_CountsTo_uVolts\000" + 2306 436F756E + 2306 7473546F + 2306 5F75566F + 2306 6C747300 + 2307 .LASF59: + 2308 00a8 4144435F .ascii "ADC_countsPer10Volt\000" + 2308 636F756E + 2308 74735065 + 2308 72313056 + 2308 6F6C7400 + 2309 .LASF9: + 2310 00bc 75696E74 .ascii "uint8\000" + 2310 3800 + 2311 .LASF16: + 2312 00c2 646F7562 .ascii "double\000" + 2312 6C6500 + 2313 .LASF11: + 2314 00c9 75696E74 .ascii "uint32\000" + 2314 333200 + 2315 .LASF62: + 2316 00d0 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 2316 73657273 + 2316 5C6A6167 + 2316 756D6965 + 2316 6C5C446F + 2317 00fe 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 58 + + + 2317 50536F43 + 2317 2D313031 + 2317 5C547261 + 2317 696E696E + 2318 .LASF38: + 2319 012b 6D61736B .ascii "mask\000" + 2319 00 + 2320 .LASF57: + 2321 0130 4144435F .ascii "ADC_initVar\000" + 2321 696E6974 + 2321 56617200 + 2322 .LASF33: + 2323 013c 7265744D .ascii "retMode\000" + 2323 6F646500 + 2324 .LASF43: + 2325 0144 4144435F .ascii "ADC_SetLimitMask\000" + 2325 5365744C + 2325 696D6974 + 2325 4D61736B + 2325 00 + 2326 .LASF8: + 2327 0155 756E7369 .ascii "unsigned int\000" + 2327 676E6564 + 2327 20696E74 + 2327 00 + 2328 .LASF53: + 2329 0162 75566F6C .ascii "uVolts\000" + 2329 747300 + 2330 .LASF5: + 2331 0169 6C6F6E67 .ascii "long unsigned int\000" + 2331 20756E73 + 2331 69676E65 + 2331 6420696E + 2331 7400 + 2332 .LASF44: + 2333 017b 4144435F .ascii "ADC_SetSatMask\000" + 2333 53657453 + 2333 61744D61 + 2333 736B00 + 2334 .LASF55: + 2335 018a 766F6C74 .ascii "volts\000" + 2335 7300 + 2336 .LASF23: + 2337 0190 746D7052 .ascii "tmpRegVal\000" + 2337 65675661 + 2337 6C00 + 2338 .LASF3: + 2339 019a 73686F72 .ascii "short unsigned int\000" + 2339 7420756E + 2339 7369676E + 2339 65642069 + 2339 6E7400 + 2340 .LASF29: + 2341 01ad 4144435F .ascii "ADC_StopConvert\000" + 2341 53746F70 + 2341 436F6E76 + 2341 65727400 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 59 + + + 2342 .LASF60: + 2343 01bd 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 2343 43313120 + 2343 352E342E + 2343 31203230 + 2343 31363036 + 2344 01f0 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 2344 20726576 + 2344 6973696F + 2344 6E203233 + 2344 37373135 + 2345 0223 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 2345 66756E63 + 2345 74696F6E + 2345 2D736563 + 2345 74696F6E + 2346 .LASF51: + 2347 024b 6D566F6C .ascii "mVolts\000" + 2347 747300 + 2348 .LASF19: + 2349 0252 72656733 .ascii "reg32\000" + 2349 3200 + 2350 .LASF14: + 2351 0258 666C6F61 .ascii "float32\000" + 2351 74333200 + 2352 .LASF21: + 2353 0260 73697A65 .ascii "sizetype\000" + 2353 74797065 + 2353 00 + 2354 .LASF40: + 2355 0269 6C6F774C .ascii "lowLimit\000" + 2355 696D6974 + 2355 00 + 2356 .LASF20: + 2357 0272 6C6F6E67 .ascii "long double\000" + 2357 20646F75 + 2357 626C6500 + 2358 .LASF41: + 2359 027e 4144435F .ascii "ADC_SetHighLimit\000" + 2359 53657448 + 2359 6967684C + 2359 696D6974 + 2359 00 + 2360 .LASF31: + 2361 028f 4144435F .ascii "ADC_IsEndConversion\000" + 2361 4973456E + 2361 64436F6E + 2361 76657273 + 2361 696F6E00 + 2362 .LASF17: + 2363 02a3 696E7436 .ascii "int64\000" + 2363 3400 + 2364 .LASF37: + 2365 02a9 4144435F .ascii "ADC_SetChanMask\000" + 2365 53657443 + 2365 68616E4D + 2365 61736B00 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 60 + + + 2366 .LASF61: + 2367 02b9 47656E65 .ascii "Generated_Source\\PSoC4\\ADC.c\000" + 2367 72617465 + 2367 645F536F + 2367 75726365 + 2367 5C50536F + 2368 .LASF47: + 2369 02d6 4144435F .ascii "ADC_SetGain\000" + 2369 53657447 + 2369 61696E00 + 2370 .LASF15: + 2371 02e2 666C6F61 .ascii "float\000" + 2371 7400 + 2372 .LASF42: + 2373 02e8 68696768 .ascii "highLimit\000" + 2373 4C696D69 + 2373 7400 + 2374 .LASF49: + 2375 02f2 4144435F .ascii "ADC_CountsTo_mVolts\000" + 2375 436F756E + 2375 7473546F + 2375 5F6D566F + 2375 6C747300 + 2376 .LASF39: + 2377 0306 4144435F .ascii "ADC_SetLowLimit\000" + 2377 5365744C + 2377 6F774C69 + 2377 6D697400 + 2378 .LASF1: + 2379 0316 756E7369 .ascii "unsigned char\000" + 2379 676E6564 + 2379 20636861 + 2379 7200 + 2380 .LASF58: + 2381 0324 4144435F .ascii "ADC_offset\000" + 2381 6F666673 + 2381 657400 + 2382 .LASF2: + 2383 032f 73686F72 .ascii "short int\000" + 2383 7420696E + 2383 7400 + 2384 .LASF27: + 2385 0339 4144435F .ascii "ADC_Stop\000" + 2385 53746F70 + 2385 00 + 2386 .LASF22: + 2387 0342 63684E75 .ascii "chNum\000" + 2387 6D00 + 2388 .LASF34: + 2389 0348 6368616E .ascii "chan\000" + 2389 00 + 2390 .LASF18: + 2391 034d 63686172 .ascii "char\000" + 2391 00 + 2392 .LASF56: + 2393 0352 4144435F .ascii "ADC_channelsConfig\000" + 2393 6368616E + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJfbLwf.s page 61 + + + 2393 6E656C73 + 2393 436F6E66 + 2393 696700 + 2394 .LASF46: + 2395 0365 6F666673 .ascii "offset\000" + 2395 657400 + 2396 .LASF50: + 2397 036c 61646343 .ascii "adcCounts\000" + 2397 6F756E74 + 2397 7300 + 2398 .LASF26: + 2399 0376 4144435F .ascii "ADC_Enable\000" + 2399 456E6162 + 2399 6C6500 + 2400 .LASF12: + 2401 0381 696E7431 .ascii "int16\000" + 2401 3600 + 2402 .LASF45: + 2403 0387 4144435F .ascii "ADC_SetOffset\000" + 2403 5365744F + 2403 66667365 + 2403 7400 + 2404 .LASF35: + 2405 0395 72657375 .ascii "result\000" + 2405 6C7400 + 2406 .LASF32: + 2407 039c 4144435F .ascii "ADC_GetResult16\000" + 2407 47657452 + 2407 6573756C + 2407 74313600 + 2408 .ident "GCC: (GNU Tools for ARM Embedded Processors) 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.eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "ADC_INT.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.ADC_ISR,"ax",%progbits + 20 .align 2 + 21 .global ADC_ISR + 22 .code 16 + 23 .thumb_func + 24 .type ADC_ISR, %function + 25 ADC_ISR: + 26 .LFB0: + 27 .file 1 "Generated_Source\\PSoC4\\ADC_INT.c" + 1:Generated_Source\PSoC4/ADC_INT.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/ADC_INT.c **** * File Name: ADC_INT.c + 3:Generated_Source\PSoC4/ADC_INT.c **** * Version 2.50 + 4:Generated_Source\PSoC4/ADC_INT.c **** * + 5:Generated_Source\PSoC4/ADC_INT.c **** * Description: + 6:Generated_Source\PSoC4/ADC_INT.c **** * This file contains the code that operates during the ADC_SAR interrupt + 7:Generated_Source\PSoC4/ADC_INT.c **** * service routine. + 8:Generated_Source\PSoC4/ADC_INT.c **** * + 9:Generated_Source\PSoC4/ADC_INT.c **** * Note: + 10:Generated_Source\PSoC4/ADC_INT.c **** * + 11:Generated_Source\PSoC4/ADC_INT.c **** ******************************************************************************** + 12:Generated_Source\PSoC4/ADC_INT.c **** * Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. + 13:Generated_Source\PSoC4/ADC_INT.c **** * You may use this file only in accordance with the license, terms, conditions, + 14:Generated_Source\PSoC4/ADC_INT.c **** * disclaimers, and limitations in the end user license agreement accompanying + 15:Generated_Source\PSoC4/ADC_INT.c **** * the software package with which this file was provided. + 16:Generated_Source\PSoC4/ADC_INT.c **** *******************************************************************************/ + 17:Generated_Source\PSoC4/ADC_INT.c **** + 18:Generated_Source\PSoC4/ADC_INT.c **** #include "ADC.h" + 19:Generated_Source\PSoC4/ADC_INT.c **** #include "cyapicallbacks.h" + 20:Generated_Source\PSoC4/ADC_INT.c **** + 21:Generated_Source\PSoC4/ADC_INT.c **** + 22:Generated_Source\PSoC4/ADC_INT.c **** /****************************************************************************** + 23:Generated_Source\PSoC4/ADC_INT.c **** * Custom Declarations and Variables + 24:Generated_Source\PSoC4/ADC_INT.c **** * - add user inlcude files, prototypes and variables between the following + 25:Generated_Source\PSoC4/ADC_INT.c **** * #START and #END tags + 26:Generated_Source\PSoC4/ADC_INT.c **** ******************************************************************************/ + 27:Generated_Source\PSoC4/ADC_INT.c **** /* `#START ADC_SYS_VAR` */ + 28:Generated_Source\PSoC4/ADC_INT.c **** + 29:Generated_Source\PSoC4/ADC_INT.c **** /* `#END` */ + 30:Generated_Source\PSoC4/ADC_INT.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 2 + + + 31:Generated_Source\PSoC4/ADC_INT.c **** #if(ADC_IRQ_REMOVE == 0u) + 32:Generated_Source\PSoC4/ADC_INT.c **** + 33:Generated_Source\PSoC4/ADC_INT.c **** + 34:Generated_Source\PSoC4/ADC_INT.c **** /****************************************************************************** + 35:Generated_Source\PSoC4/ADC_INT.c **** * Function Name: ADC_ISR + 36:Generated_Source\PSoC4/ADC_INT.c **** ******************************************************************************* + 37:Generated_Source\PSoC4/ADC_INT.c **** * + 38:Generated_Source\PSoC4/ADC_INT.c **** * Summary: + 39:Generated_Source\PSoC4/ADC_INT.c **** * Handle Interrupt Service Routine. + 40:Generated_Source\PSoC4/ADC_INT.c **** * + 41:Generated_Source\PSoC4/ADC_INT.c **** * Parameters: + 42:Generated_Source\PSoC4/ADC_INT.c **** * None. + 43:Generated_Source\PSoC4/ADC_INT.c **** * + 44:Generated_Source\PSoC4/ADC_INT.c **** * Return: + 45:Generated_Source\PSoC4/ADC_INT.c **** * None. + 46:Generated_Source\PSoC4/ADC_INT.c **** * + 47:Generated_Source\PSoC4/ADC_INT.c **** * Reentrant: + 48:Generated_Source\PSoC4/ADC_INT.c **** * No. + 49:Generated_Source\PSoC4/ADC_INT.c **** * + 50:Generated_Source\PSoC4/ADC_INT.c **** ******************************************************************************/ + 51:Generated_Source\PSoC4/ADC_INT.c **** CY_ISR( ADC_ISR ) + 52:Generated_Source\PSoC4/ADC_INT.c **** { + 28 .loc 1 52 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 82B0 sub sp, sp, #8 + 37 .cfi_def_cfa_offset 16 + 38 0004 00AF add r7, sp, #0 + 39 .cfi_def_cfa_register 7 + 53:Generated_Source\PSoC4/ADC_INT.c **** uint32 intr_status; + 54:Generated_Source\PSoC4/ADC_INT.c **** + 55:Generated_Source\PSoC4/ADC_INT.c **** /* Read interrupt status register */ + 56:Generated_Source\PSoC4/ADC_INT.c **** intr_status = ADC_SAR_INTR_REG; + 40 .loc 1 56 0 + 41 0006 054B ldr r3, .L2 + 42 0008 1B68 ldr r3, [r3] + 43 000a 7B60 str r3, [r7, #4] + 57:Generated_Source\PSoC4/ADC_INT.c **** + 58:Generated_Source\PSoC4/ADC_INT.c **** #ifdef ADC_ISR_INTERRUPT_CALLBACK + 59:Generated_Source\PSoC4/ADC_INT.c **** ADC_ISR_InterruptCallback(); + 60:Generated_Source\PSoC4/ADC_INT.c **** #endif /* ADC_ISR_INTERRUPT_CALLBACK */ + 61:Generated_Source\PSoC4/ADC_INT.c **** + 62:Generated_Source\PSoC4/ADC_INT.c **** + 63:Generated_Source\PSoC4/ADC_INT.c **** /************************************************************************ + 64:Generated_Source\PSoC4/ADC_INT.c **** * Custom Code + 65:Generated_Source\PSoC4/ADC_INT.c **** * - add user ISR code between the following #START and #END tags + 66:Generated_Source\PSoC4/ADC_INT.c **** *************************************************************************/ + 67:Generated_Source\PSoC4/ADC_INT.c **** /* `#START MAIN_ADC_ISR` */ + 68:Generated_Source\PSoC4/ADC_INT.c **** + 69:Generated_Source\PSoC4/ADC_INT.c **** /* `#END` */ + 70:Generated_Source\PSoC4/ADC_INT.c **** + 71:Generated_Source\PSoC4/ADC_INT.c **** /* Clear handled interrupt */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 3 + + + 72:Generated_Source\PSoC4/ADC_INT.c **** ADC_SAR_INTR_REG = intr_status; + 44 .loc 1 72 0 + 45 000c 034B ldr r3, .L2 + 46 000e 7A68 ldr r2, [r7, #4] + 47 0010 1A60 str r2, [r3] + 73:Generated_Source\PSoC4/ADC_INT.c **** } + 48 .loc 1 73 0 + 49 0012 C046 nop + 50 0014 BD46 mov sp, r7 + 51 0016 02B0 add sp, sp, #8 + 52 @ sp needed + 53 0018 80BD pop {r7, pc} + 54 .L3: + 55 001a C046 .align 2 + 56 .L2: + 57 001c 10021A40 .word 1075446288 + 58 .cfi_endproc + 59 .LFE0: + 60 .size ADC_ISR, .-ADC_ISR + 61 .text + 62 .Letext0: + 63 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 64 .section .debug_info,"",%progbits + 65 .Ldebug_info0: + 66 0000 C8000000 .4byte 0xc8 + 67 0004 0400 .2byte 0x4 + 68 0006 00000000 .4byte .Ldebug_abbrev0 + 69 000a 04 .byte 0x4 + 70 000b 01 .uleb128 0x1 + 71 000c 3F010000 .4byte .LASF16 + 72 0010 0C .byte 0xc + 73 0011 C0000000 .4byte .LASF17 + 74 0015 22000000 .4byte .LASF18 + 75 0019 00000000 .4byte .Ldebug_ranges0+0 + 76 001d 00000000 .4byte 0 + 77 0021 00000000 .4byte .Ldebug_line0 + 78 0025 02 .uleb128 0x2 + 79 0026 01 .byte 0x1 + 80 0027 06 .byte 0x6 + 81 0028 1D010000 .4byte .LASF0 + 82 002c 02 .uleb128 0x2 + 83 002d 01 .byte 0x1 + 84 002e 08 .byte 0x8 + 85 002f E1000000 .4byte .LASF1 + 86 0033 02 .uleb128 0x2 + 87 0034 02 .byte 0x2 + 88 0035 05 .byte 0x5 + 89 0036 35010000 .4byte .LASF2 + 90 003a 02 .uleb128 0x2 + 91 003b 02 .byte 0x2 + 92 003c 07 .byte 0x7 + 93 003d 0A010000 .4byte .LASF3 + 94 0041 02 .uleb128 0x2 + 95 0042 04 .byte 0x4 + 96 0043 05 .byte 0x5 + 97 0044 F4000000 .4byte .LASF4 + 98 0048 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 4 + + + 99 0049 04 .byte 0x4 + 100 004a 07 .byte 0x7 + 101 004b 85000000 .4byte .LASF5 + 102 004f 02 .uleb128 0x2 + 103 0050 08 .byte 0x8 + 104 0051 05 .byte 0x5 + 105 0052 00000000 .4byte .LASF6 + 106 0056 02 .uleb128 0x2 + 107 0057 08 .byte 0x8 + 108 0058 07 .byte 0x7 + 109 0059 97000000 .4byte .LASF7 + 110 005d 03 .uleb128 0x3 + 111 005e 04 .byte 0x4 + 112 005f 05 .byte 0x5 + 113 0060 696E7400 .ascii "int\000" + 114 0064 02 .uleb128 0x2 + 115 0065 04 .byte 0x4 + 116 0066 07 .byte 0x7 + 117 0067 15000000 .4byte .LASF8 + 118 006b 04 .uleb128 0x4 + 119 006c 0E000000 .4byte .LASF12 + 120 0070 02 .byte 0x2 + 121 0071 E601 .2byte 0x1e6 + 122 0073 48000000 .4byte 0x48 + 123 0077 02 .uleb128 0x2 + 124 0078 04 .byte 0x4 + 125 0079 04 .byte 0x4 + 126 007a AE000000 .4byte .LASF9 + 127 007e 02 .uleb128 0x2 + 128 007f 08 .byte 0x8 + 129 0080 04 .byte 0x4 + 130 0081 FD000000 .4byte .LASF10 + 131 0085 02 .uleb128 0x2 + 132 0086 01 .byte 0x1 + 133 0087 08 .byte 0x8 + 134 0088 EF000000 .4byte .LASF11 + 135 008c 04 .uleb128 0x4 + 136 008d 04010000 .4byte .LASF13 + 137 0091 02 .byte 0x2 + 138 0092 9002 .2byte 0x290 + 139 0094 98000000 .4byte 0x98 + 140 0098 05 .uleb128 0x5 + 141 0099 6B000000 .4byte 0x6b + 142 009d 02 .uleb128 0x2 + 143 009e 08 .byte 0x8 + 144 009f 04 .byte 0x4 + 145 00a0 29010000 .4byte .LASF14 + 146 00a4 02 .uleb128 0x2 + 147 00a5 04 .byte 0x4 + 148 00a6 07 .byte 0x7 + 149 00a7 CD010000 .4byte .LASF15 + 150 00ab 06 .uleb128 0x6 + 151 00ac 7D000000 .4byte .LASF19 + 152 00b0 01 .byte 0x1 + 153 00b1 33 .byte 0x33 + 154 00b2 00000000 .4byte .LFB0 + 155 00b6 20000000 .4byte .LFE0-.LFB0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 5 + + + 156 00ba 01 .uleb128 0x1 + 157 00bb 9C .byte 0x9c + 158 00bc 07 .uleb128 0x7 + 159 00bd B4000000 .4byte .LASF20 + 160 00c1 01 .byte 0x1 + 161 00c2 35 .byte 0x35 + 162 00c3 6B000000 .4byte 0x6b + 163 00c7 02 .uleb128 0x2 + 164 00c8 91 .byte 0x91 + 165 00c9 74 .sleb128 -12 + 166 00ca 00 .byte 0 + 167 00cb 00 .byte 0 + 168 .section .debug_abbrev,"",%progbits + 169 .Ldebug_abbrev0: + 170 0000 01 .uleb128 0x1 + 171 0001 11 .uleb128 0x11 + 172 0002 01 .byte 0x1 + 173 0003 25 .uleb128 0x25 + 174 0004 0E .uleb128 0xe + 175 0005 13 .uleb128 0x13 + 176 0006 0B .uleb128 0xb + 177 0007 03 .uleb128 0x3 + 178 0008 0E .uleb128 0xe + 179 0009 1B .uleb128 0x1b + 180 000a 0E .uleb128 0xe + 181 000b 55 .uleb128 0x55 + 182 000c 17 .uleb128 0x17 + 183 000d 11 .uleb128 0x11 + 184 000e 01 .uleb128 0x1 + 185 000f 10 .uleb128 0x10 + 186 0010 17 .uleb128 0x17 + 187 0011 00 .byte 0 + 188 0012 00 .byte 0 + 189 0013 02 .uleb128 0x2 + 190 0014 24 .uleb128 0x24 + 191 0015 00 .byte 0 + 192 0016 0B .uleb128 0xb + 193 0017 0B .uleb128 0xb + 194 0018 3E .uleb128 0x3e + 195 0019 0B .uleb128 0xb + 196 001a 03 .uleb128 0x3 + 197 001b 0E .uleb128 0xe + 198 001c 00 .byte 0 + 199 001d 00 .byte 0 + 200 001e 03 .uleb128 0x3 + 201 001f 24 .uleb128 0x24 + 202 0020 00 .byte 0 + 203 0021 0B .uleb128 0xb + 204 0022 0B .uleb128 0xb + 205 0023 3E .uleb128 0x3e + 206 0024 0B .uleb128 0xb + 207 0025 03 .uleb128 0x3 + 208 0026 08 .uleb128 0x8 + 209 0027 00 .byte 0 + 210 0028 00 .byte 0 + 211 0029 04 .uleb128 0x4 + 212 002a 16 .uleb128 0x16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 6 + + + 213 002b 00 .byte 0 + 214 002c 03 .uleb128 0x3 + 215 002d 0E .uleb128 0xe + 216 002e 3A .uleb128 0x3a + 217 002f 0B .uleb128 0xb + 218 0030 3B .uleb128 0x3b + 219 0031 05 .uleb128 0x5 + 220 0032 49 .uleb128 0x49 + 221 0033 13 .uleb128 0x13 + 222 0034 00 .byte 0 + 223 0035 00 .byte 0 + 224 0036 05 .uleb128 0x5 + 225 0037 35 .uleb128 0x35 + 226 0038 00 .byte 0 + 227 0039 49 .uleb128 0x49 + 228 003a 13 .uleb128 0x13 + 229 003b 00 .byte 0 + 230 003c 00 .byte 0 + 231 003d 06 .uleb128 0x6 + 232 003e 2E .uleb128 0x2e + 233 003f 01 .byte 0x1 + 234 0040 3F .uleb128 0x3f + 235 0041 19 .uleb128 0x19 + 236 0042 03 .uleb128 0x3 + 237 0043 0E .uleb128 0xe + 238 0044 3A .uleb128 0x3a + 239 0045 0B .uleb128 0xb + 240 0046 3B .uleb128 0x3b + 241 0047 0B .uleb128 0xb + 242 0048 27 .uleb128 0x27 + 243 0049 19 .uleb128 0x19 + 244 004a 11 .uleb128 0x11 + 245 004b 01 .uleb128 0x1 + 246 004c 12 .uleb128 0x12 + 247 004d 06 .uleb128 0x6 + 248 004e 40 .uleb128 0x40 + 249 004f 18 .uleb128 0x18 + 250 0050 9742 .uleb128 0x2117 + 251 0052 19 .uleb128 0x19 + 252 0053 00 .byte 0 + 253 0054 00 .byte 0 + 254 0055 07 .uleb128 0x7 + 255 0056 34 .uleb128 0x34 + 256 0057 00 .byte 0 + 257 0058 03 .uleb128 0x3 + 258 0059 0E .uleb128 0xe + 259 005a 3A .uleb128 0x3a + 260 005b 0B .uleb128 0xb + 261 005c 3B .uleb128 0x3b + 262 005d 0B .uleb128 0xb + 263 005e 49 .uleb128 0x49 + 264 005f 13 .uleb128 0x13 + 265 0060 02 .uleb128 0x2 + 266 0061 18 .uleb128 0x18 + 267 0062 00 .byte 0 + 268 0063 00 .byte 0 + 269 0064 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 7 + + + 270 .section .debug_aranges,"",%progbits + 271 0000 1C000000 .4byte 0x1c + 272 0004 0200 .2byte 0x2 + 273 0006 00000000 .4byte .Ldebug_info0 + 274 000a 04 .byte 0x4 + 275 000b 00 .byte 0 + 276 000c 0000 .2byte 0 + 277 000e 0000 .2byte 0 + 278 0010 00000000 .4byte .LFB0 + 279 0014 20000000 .4byte .LFE0-.LFB0 + 280 0018 00000000 .4byte 0 + 281 001c 00000000 .4byte 0 + 282 .section .debug_ranges,"",%progbits + 283 .Ldebug_ranges0: + 284 0000 00000000 .4byte .LFB0 + 285 0004 20000000 .4byte .LFE0 + 286 0008 00000000 .4byte 0 + 287 000c 00000000 .4byte 0 + 288 .section .debug_line,"",%progbits + 289 .Ldebug_line0: + 290 0000 5E000000 .section .debug_str,"MS",%progbits,1 + 290 02004400 + 290 00000201 + 290 FB0E0D00 + 290 01010101 + 291 .LASF6: + 292 0000 6C6F6E67 .ascii "long long int\000" + 292 206C6F6E + 292 6720696E + 292 7400 + 293 .LASF12: + 294 000e 75696E74 .ascii "uint32\000" + 294 333200 + 295 .LASF8: + 296 0015 756E7369 .ascii "unsigned int\000" + 296 676E6564 + 296 20696E74 + 296 00 + 297 .LASF18: + 298 0022 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 298 73657273 + 298 5C6A6167 + 298 756D6965 + 298 6C5C446F + 299 0050 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 299 50536F43 + 299 2D313031 + 299 5C547261 + 299 696E696E + 300 .LASF19: + 301 007d 4144435F .ascii "ADC_ISR\000" + 301 49535200 + 302 .LASF5: + 303 0085 6C6F6E67 .ascii "long unsigned int\000" + 303 20756E73 + 303 69676E65 + 303 6420696E + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 8 + + + 303 7400 + 304 .LASF7: + 305 0097 6C6F6E67 .ascii "long long unsigned int\000" + 305 206C6F6E + 305 6720756E + 305 7369676E + 305 65642069 + 306 .LASF9: + 307 00ae 666C6F61 .ascii "float\000" + 307 7400 + 308 .LASF20: + 309 00b4 696E7472 .ascii "intr_status\000" + 309 5F737461 + 309 74757300 + 310 .LASF17: + 311 00c0 47656E65 .ascii "Generated_Source\\PSoC4\\ADC_INT.c\000" + 311 72617465 + 311 645F536F + 311 75726365 + 311 5C50536F + 312 .LASF1: + 313 00e1 756E7369 .ascii "unsigned char\000" + 313 676E6564 + 313 20636861 + 313 7200 + 314 .LASF11: + 315 00ef 63686172 .ascii "char\000" + 315 00 + 316 .LASF4: + 317 00f4 6C6F6E67 .ascii "long int\000" + 317 20696E74 + 317 00 + 318 .LASF10: + 319 00fd 646F7562 .ascii "double\000" + 319 6C6500 + 320 .LASF13: + 321 0104 72656733 .ascii "reg32\000" + 321 3200 + 322 .LASF3: + 323 010a 73686F72 .ascii "short unsigned int\000" + 323 7420756E + 323 7369676E + 323 65642069 + 323 6E7400 + 324 .LASF0: + 325 011d 7369676E .ascii "signed char\000" + 325 65642063 + 325 68617200 + 326 .LASF14: + 327 0129 6C6F6E67 .ascii "long double\000" + 327 20646F75 + 327 626C6500 + 328 .LASF2: + 329 0135 73686F72 .ascii "short int\000" + 329 7420696E + 329 7400 + 330 .LASF16: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccRK1JOZ.s page 9 + + + 331 013f 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 331 43313120 + 331 352E342E + 331 31203230 + 331 31363036 + 332 0172 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 332 20726576 + 332 6973696F + 332 6E203233 + 332 37373135 + 333 01a5 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 333 66756E63 + 333 74696F6E + 333 2D736563 + 333 74696F6E + 334 .LASF15: + 335 01cd 73697A65 .ascii "sizetype\000" + 335 74797065 + 335 00 + 336 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_INT.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_INT.o new file mode 100644 index 0000000000000000000000000000000000000000..bce57d20644b5d6a6d1686898bbcf48cef09d6b5 GIT binary patch literal 2880 zcmbtWO^j1j6u$4L(?UCSet=;>&DEgHB=*rV48&1jYKK8Y5a%b+I6AzxciLk69(nK8 zIH(a!h%VIV3KuSPLEIQ6MwTQKS1dGfVceS-cScRvslo5ucW?U!O*HW&_kHK@o^$Ts zXRrQ?DN#g-OX3dS|=|wcb(mszcFuK zyLe+`e#qQ4dlSC4^tX+p2$tJ`aKBXaKc+Eo4{WB9`2kAPOihzyrneHHc!eF>2Cl7 zuR&!@;lns_AEv(~n3kUJM_`AI2lAs?E5AFxJT`0$jUn0|mdzf43dJZkgG4)+m7mEz zk~%SpOw){Dz%h=FOKo=V_^>fDFuU{0W8;ja55&IN6Qkx%;qh0e`5E<6#qk*KdO`rV)=R?aN?6&zl9uCjXK^paB}uiARFeqMx5 zlLS;Nb6Zo!tTpuLVKa?*ZQpBf`Jv73;xo0Mb-l3F@I;-HZf<5}ITS&-a?WjZJ1x;( zne%Jij_{&T=H!(?xRD=7p-?K8`pi<`w!D_tI1~8iL=FBZuCQEQKy~Z&(2HwbTwpT) zrlkF{HmTRzz8f)A6|9Dl8+AkW&)YzW)GqYq*P3p?K95b>Tn zEnV$Gf0CLIyOPK8)62Y4D)DLOfK%f8i=~6bgT;sWL?GJ24aFpXuDoz+pXgLYy)Np7 z=|VMdy;_q8;-yyD@;$zP>d>Lm^z*#Xsh#g0uAv0+a-ma%95uV0Dlas6;VFn~YhAAv zVMZauP69*Hxly4V`31i!w-@zZ5Om;-9j{bo_ykqA{hZK(7Omr#-58J7W zYPYf4^45GfO5Uwj@uHJf7w^0wFugzF@0xbY6FLO)GpFWvsIewztp#oePI$bI8%05@ z+KmwQzte8G(!J1c2tN^K$&zk)7%ed2zY(#r8=yv~`-$U@ZGcSiulYUW0pwO|& zwuJFDF^aTp1~RTJn^pQ87IYIloh=XF^I-+@Zakokcp*1|DTe6KjWZjZJM;-RVawpw1PxBHt8rY z(Z?9c`u<3)m-a{3M{gUc&I2U94MRx_K%I;FoW6Tx&Y|^wMT{ctM~Ef%XoKp5l6u?- V2IZyvR9iCMueeOq|1{}%e*vd{eEa|a literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_IRQ.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_IRQ.lst new file mode 100644 index 0000000..ddf4744 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_IRQ.lst @@ -0,0 +1,1957 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "ADC_IRQ.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.ADC_IRQ_Start,"ax",%progbits + 20 .align 2 + 21 .global ADC_IRQ_Start + 22 .code 16 + 23 .thumb_func + 24 .type ADC_IRQ_Start, %function + 25 ADC_IRQ_Start: + 26 .LFB0: + 27 .file 1 "Generated_Source\\PSoC4\\ADC_IRQ.c" + 1:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/ADC_IRQ.c **** * File Name: ADC_IRQ.c + 3:Generated_Source\PSoC4/ADC_IRQ.c **** * Version 1.70 + 4:Generated_Source\PSoC4/ADC_IRQ.c **** * + 5:Generated_Source\PSoC4/ADC_IRQ.c **** * Description: + 6:Generated_Source\PSoC4/ADC_IRQ.c **** * API for controlling the state of an interrupt. + 7:Generated_Source\PSoC4/ADC_IRQ.c **** * + 8:Generated_Source\PSoC4/ADC_IRQ.c **** * + 9:Generated_Source\PSoC4/ADC_IRQ.c **** * Note: + 10:Generated_Source\PSoC4/ADC_IRQ.c **** * + 11:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 12:Generated_Source\PSoC4/ADC_IRQ.c **** * Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. + 13:Generated_Source\PSoC4/ADC_IRQ.c **** * You may use this file only in accordance with the license, terms, conditions, + 14:Generated_Source\PSoC4/ADC_IRQ.c **** * disclaimers, and limitations in the end user license agreement accompanying + 15:Generated_Source\PSoC4/ADC_IRQ.c **** * the software package with which this file was provided. + 16:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 17:Generated_Source\PSoC4/ADC_IRQ.c **** + 18:Generated_Source\PSoC4/ADC_IRQ.c **** + 19:Generated_Source\PSoC4/ADC_IRQ.c **** #include + 20:Generated_Source\PSoC4/ADC_IRQ.c **** #include + 21:Generated_Source\PSoC4/ADC_IRQ.c **** #include + 22:Generated_Source\PSoC4/ADC_IRQ.c **** #include "cyapicallbacks.h" + 23:Generated_Source\PSoC4/ADC_IRQ.c **** + 24:Generated_Source\PSoC4/ADC_IRQ.c **** #if !defined(ADC_IRQ__REMOVED) /* Check for removal by optimization */ + 25:Generated_Source\PSoC4/ADC_IRQ.c **** + 26:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 27:Generated_Source\PSoC4/ADC_IRQ.c **** * Place your includes, defines and code here + 28:Generated_Source\PSoC4/ADC_IRQ.c **** ********************************************************************************/ + 29:Generated_Source\PSoC4/ADC_IRQ.c **** /* `#START ADC_IRQ_intc` */ + 30:Generated_Source\PSoC4/ADC_IRQ.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 2 + + + 31:Generated_Source\PSoC4/ADC_IRQ.c **** /* `#END` */ + 32:Generated_Source\PSoC4/ADC_IRQ.c **** + 33:Generated_Source\PSoC4/ADC_IRQ.c **** extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + 34:Generated_Source\PSoC4/ADC_IRQ.c **** + 35:Generated_Source\PSoC4/ADC_IRQ.c **** /* Declared in startup, used to set unused interrupts to. */ + 36:Generated_Source\PSoC4/ADC_IRQ.c **** CY_ISR_PROTO(IntDefaultHandler); + 37:Generated_Source\PSoC4/ADC_IRQ.c **** + 38:Generated_Source\PSoC4/ADC_IRQ.c **** + 39:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 40:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_Start + 41:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 42:Generated_Source\PSoC4/ADC_IRQ.c **** * + 43:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 44:Generated_Source\PSoC4/ADC_IRQ.c **** * Set up the interrupt and enable it. This function disables the interrupt, + 45:Generated_Source\PSoC4/ADC_IRQ.c **** * sets the default interrupt vector, sets the priority from the value in the + 46:Generated_Source\PSoC4/ADC_IRQ.c **** * Design Wide Resources Interrupt Editor, then enables the interrupt to the + 47:Generated_Source\PSoC4/ADC_IRQ.c **** * interrupt controller. + 48:Generated_Source\PSoC4/ADC_IRQ.c **** * + 49:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 50:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 51:Generated_Source\PSoC4/ADC_IRQ.c **** * + 52:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 53:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 54:Generated_Source\PSoC4/ADC_IRQ.c **** * + 55:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 56:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_Start(void) + 57:Generated_Source\PSoC4/ADC_IRQ.c **** { + 28 .loc 1 57 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 00AF add r7, sp, #0 + 37 .cfi_def_cfa_register 7 + 58:Generated_Source\PSoC4/ADC_IRQ.c **** /* For all we know the interrupt is active. */ + 59:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_Disable(); + 38 .loc 1 59 0 + 39 0004 FFF7FEFF bl ADC_IRQ_Disable + 60:Generated_Source\PSoC4/ADC_IRQ.c **** + 61:Generated_Source\PSoC4/ADC_IRQ.c **** /* Set the ISR to point to the ADC_IRQ Interrupt. */ + 62:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_SetVector(&ADC_IRQ_Interrupt); + 40 .loc 1 62 0 + 41 0008 054B ldr r3, .L2 + 42 000a 1800 movs r0, r3 + 43 000c FFF7FEFF bl ADC_IRQ_SetVector + 63:Generated_Source\PSoC4/ADC_IRQ.c **** + 64:Generated_Source\PSoC4/ADC_IRQ.c **** /* Set the priority. */ + 65:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_SetPriority((uint8)ADC_IRQ_INTC_PRIOR_NUMBER); + 44 .loc 1 65 0 + 45 0010 0320 movs r0, #3 + 46 0012 FFF7FEFF bl ADC_IRQ_SetPriority + 66:Generated_Source\PSoC4/ADC_IRQ.c **** + 67:Generated_Source\PSoC4/ADC_IRQ.c **** /* Enable it. */ + 68:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_Enable(); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 3 + + + 47 .loc 1 68 0 + 48 0016 FFF7FEFF bl ADC_IRQ_Enable + 69:Generated_Source\PSoC4/ADC_IRQ.c **** } + 49 .loc 1 69 0 + 50 001a C046 nop + 51 001c BD46 mov sp, r7 + 52 @ sp needed + 53 001e 80BD pop {r7, pc} + 54 .L3: + 55 .align 2 + 56 .L2: + 57 0020 00000000 .word ADC_IRQ_Interrupt + 58 .cfi_endproc + 59 .LFE0: + 60 .size ADC_IRQ_Start, .-ADC_IRQ_Start + 61 .section .text.ADC_IRQ_StartEx,"ax",%progbits + 62 .align 2 + 63 .global ADC_IRQ_StartEx + 64 .code 16 + 65 .thumb_func + 66 .type ADC_IRQ_StartEx, %function + 67 ADC_IRQ_StartEx: + 68 .LFB1: + 70:Generated_Source\PSoC4/ADC_IRQ.c **** + 71:Generated_Source\PSoC4/ADC_IRQ.c **** + 72:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 73:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_StartEx + 74:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 75:Generated_Source\PSoC4/ADC_IRQ.c **** * + 76:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 77:Generated_Source\PSoC4/ADC_IRQ.c **** * Sets up the interrupt and enables it. This function disables the interrupt, + 78:Generated_Source\PSoC4/ADC_IRQ.c **** * sets the interrupt vector based on the address passed in, sets the priority + 79:Generated_Source\PSoC4/ADC_IRQ.c **** * from the value in the Design Wide Resources Interrupt Editor, then enables + 80:Generated_Source\PSoC4/ADC_IRQ.c **** * the interrupt to the interrupt controller. + 81:Generated_Source\PSoC4/ADC_IRQ.c **** * + 82:Generated_Source\PSoC4/ADC_IRQ.c **** * When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be + 83:Generated_Source\PSoC4/ADC_IRQ.c **** * used to provide consistent definition across compilers: + 84:Generated_Source\PSoC4/ADC_IRQ.c **** * + 85:Generated_Source\PSoC4/ADC_IRQ.c **** * Function definition example: + 86:Generated_Source\PSoC4/ADC_IRQ.c **** * CY_ISR(MyISR) + 87:Generated_Source\PSoC4/ADC_IRQ.c **** * { + 88:Generated_Source\PSoC4/ADC_IRQ.c **** * } + 89:Generated_Source\PSoC4/ADC_IRQ.c **** * Function prototype example: + 90:Generated_Source\PSoC4/ADC_IRQ.c **** * CY_ISR_PROTO(MyISR); + 91:Generated_Source\PSoC4/ADC_IRQ.c **** * + 92:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 93:Generated_Source\PSoC4/ADC_IRQ.c **** * address: Address of the ISR to set in the interrupt vector table. + 94:Generated_Source\PSoC4/ADC_IRQ.c **** * + 95:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 96:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 97:Generated_Source\PSoC4/ADC_IRQ.c **** * + 98:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 99:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_StartEx(cyisraddress address) + 100:Generated_Source\PSoC4/ADC_IRQ.c **** { + 69 .loc 1 100 0 + 70 .cfi_startproc + 71 @ args = 0, pretend = 0, frame = 8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 4 + + + 72 @ frame_needed = 1, uses_anonymous_args = 0 + 73 0000 80B5 push {r7, lr} + 74 .cfi_def_cfa_offset 8 + 75 .cfi_offset 7, -8 + 76 .cfi_offset 14, -4 + 77 0002 82B0 sub sp, sp, #8 + 78 .cfi_def_cfa_offset 16 + 79 0004 00AF add r7, sp, #0 + 80 .cfi_def_cfa_register 7 + 81 0006 7860 str r0, [r7, #4] + 101:Generated_Source\PSoC4/ADC_IRQ.c **** /* For all we know the interrupt is active. */ + 102:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_Disable(); + 82 .loc 1 102 0 + 83 0008 FFF7FEFF bl ADC_IRQ_Disable + 103:Generated_Source\PSoC4/ADC_IRQ.c **** + 104:Generated_Source\PSoC4/ADC_IRQ.c **** /* Set the ISR to point to the ADC_IRQ Interrupt. */ + 105:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_SetVector(address); + 84 .loc 1 105 0 + 85 000c 7B68 ldr r3, [r7, #4] + 86 000e 1800 movs r0, r3 + 87 0010 FFF7FEFF bl ADC_IRQ_SetVector + 106:Generated_Source\PSoC4/ADC_IRQ.c **** + 107:Generated_Source\PSoC4/ADC_IRQ.c **** /* Set the priority. */ + 108:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_SetPriority((uint8)ADC_IRQ_INTC_PRIOR_NUMBER); + 88 .loc 1 108 0 + 89 0014 0320 movs r0, #3 + 90 0016 FFF7FEFF bl ADC_IRQ_SetPriority + 109:Generated_Source\PSoC4/ADC_IRQ.c **** + 110:Generated_Source\PSoC4/ADC_IRQ.c **** /* Enable it. */ + 111:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_Enable(); + 91 .loc 1 111 0 + 92 001a FFF7FEFF bl ADC_IRQ_Enable + 112:Generated_Source\PSoC4/ADC_IRQ.c **** } + 93 .loc 1 112 0 + 94 001e C046 nop + 95 0020 BD46 mov sp, r7 + 96 0022 02B0 add sp, sp, #8 + 97 @ sp needed + 98 0024 80BD pop {r7, pc} + 99 .cfi_endproc + 100 .LFE1: + 101 .size ADC_IRQ_StartEx, .-ADC_IRQ_StartEx + 102 0026 C046 .section .text.ADC_IRQ_Stop,"ax",%progbits + 103 .align 2 + 104 .global ADC_IRQ_Stop + 105 .code 16 + 106 .thumb_func + 107 .type ADC_IRQ_Stop, %function + 108 ADC_IRQ_Stop: + 109 .LFB2: + 113:Generated_Source\PSoC4/ADC_IRQ.c **** + 114:Generated_Source\PSoC4/ADC_IRQ.c **** + 115:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 116:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_Stop + 117:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 118:Generated_Source\PSoC4/ADC_IRQ.c **** * + 119:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 5 + + + 120:Generated_Source\PSoC4/ADC_IRQ.c **** * Disables and removes the interrupt. + 121:Generated_Source\PSoC4/ADC_IRQ.c **** * + 122:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 123:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 124:Generated_Source\PSoC4/ADC_IRQ.c **** * + 125:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 126:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 127:Generated_Source\PSoC4/ADC_IRQ.c **** * + 128:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 129:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_Stop(void) + 130:Generated_Source\PSoC4/ADC_IRQ.c **** { + 110 .loc 1 130 0 + 111 .cfi_startproc + 112 @ args = 0, pretend = 0, frame = 0 + 113 @ frame_needed = 1, uses_anonymous_args = 0 + 114 0000 80B5 push {r7, lr} + 115 .cfi_def_cfa_offset 8 + 116 .cfi_offset 7, -8 + 117 .cfi_offset 14, -4 + 118 0002 00AF add r7, sp, #0 + 119 .cfi_def_cfa_register 7 + 131:Generated_Source\PSoC4/ADC_IRQ.c **** /* Disable this interrupt. */ + 132:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_Disable(); + 120 .loc 1 132 0 + 121 0004 FFF7FEFF bl ADC_IRQ_Disable + 133:Generated_Source\PSoC4/ADC_IRQ.c **** + 134:Generated_Source\PSoC4/ADC_IRQ.c **** /* Set the ISR to point to the passive one. */ + 135:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_SetVector(&IntDefaultHandler); + 122 .loc 1 135 0 + 123 0008 034B ldr r3, .L6 + 124 000a 1800 movs r0, r3 + 125 000c FFF7FEFF bl ADC_IRQ_SetVector + 136:Generated_Source\PSoC4/ADC_IRQ.c **** } + 126 .loc 1 136 0 + 127 0010 C046 nop + 128 0012 BD46 mov sp, r7 + 129 @ sp needed + 130 0014 80BD pop {r7, pc} + 131 .L7: + 132 0016 C046 .align 2 + 133 .L6: + 134 0018 00000000 .word IntDefaultHandler + 135 .cfi_endproc + 136 .LFE2: + 137 .size ADC_IRQ_Stop, .-ADC_IRQ_Stop + 138 .section .text.ADC_IRQ_Interrupt,"ax",%progbits + 139 .align 2 + 140 .global ADC_IRQ_Interrupt + 141 .code 16 + 142 .thumb_func + 143 .type ADC_IRQ_Interrupt, %function + 144 ADC_IRQ_Interrupt: + 145 .LFB3: + 137:Generated_Source\PSoC4/ADC_IRQ.c **** + 138:Generated_Source\PSoC4/ADC_IRQ.c **** + 139:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 140:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_Interrupt + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 6 + + + 141:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 142:Generated_Source\PSoC4/ADC_IRQ.c **** * + 143:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 144:Generated_Source\PSoC4/ADC_IRQ.c **** * The default Interrupt Service Routine for ADC_IRQ. + 145:Generated_Source\PSoC4/ADC_IRQ.c **** * + 146:Generated_Source\PSoC4/ADC_IRQ.c **** * Add custom code between the START and END comments to keep the next version + 147:Generated_Source\PSoC4/ADC_IRQ.c **** * of this file from over-writing your code. + 148:Generated_Source\PSoC4/ADC_IRQ.c **** * + 149:Generated_Source\PSoC4/ADC_IRQ.c **** * Note You may use either the default ISR by using this API, or you may define + 150:Generated_Source\PSoC4/ADC_IRQ.c **** * your own separate ISR through ISR_StartEx(). + 151:Generated_Source\PSoC4/ADC_IRQ.c **** * + 152:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 153:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 154:Generated_Source\PSoC4/ADC_IRQ.c **** * + 155:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 156:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 157:Generated_Source\PSoC4/ADC_IRQ.c **** * + 158:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 159:Generated_Source\PSoC4/ADC_IRQ.c **** CY_ISR(ADC_IRQ_Interrupt) + 160:Generated_Source\PSoC4/ADC_IRQ.c **** { + 146 .loc 1 160 0 + 147 .cfi_startproc + 148 @ args = 0, pretend = 0, frame = 0 + 149 @ frame_needed = 1, uses_anonymous_args = 0 + 150 0000 80B5 push {r7, lr} + 151 .cfi_def_cfa_offset 8 + 152 .cfi_offset 7, -8 + 153 .cfi_offset 14, -4 + 154 0002 00AF add r7, sp, #0 + 155 .cfi_def_cfa_register 7 + 161:Generated_Source\PSoC4/ADC_IRQ.c **** #ifdef ADC_IRQ_INTERRUPT_INTERRUPT_CALLBACK + 162:Generated_Source\PSoC4/ADC_IRQ.c **** ADC_IRQ_Interrupt_InterruptCallback(); + 163:Generated_Source\PSoC4/ADC_IRQ.c **** #endif /* ADC_IRQ_INTERRUPT_INTERRUPT_CALLBACK */ + 164:Generated_Source\PSoC4/ADC_IRQ.c **** + 165:Generated_Source\PSoC4/ADC_IRQ.c **** /* Place your Interrupt code here. */ + 166:Generated_Source\PSoC4/ADC_IRQ.c **** /* `#START ADC_IRQ_Interrupt` */ + 167:Generated_Source\PSoC4/ADC_IRQ.c **** + 168:Generated_Source\PSoC4/ADC_IRQ.c **** /* `#END` */ + 169:Generated_Source\PSoC4/ADC_IRQ.c **** } + 156 .loc 1 169 0 + 157 0004 C046 nop + 158 0006 BD46 mov sp, r7 + 159 @ sp needed + 160 0008 80BD pop {r7, pc} + 161 .cfi_endproc + 162 .LFE3: + 163 .size ADC_IRQ_Interrupt, .-ADC_IRQ_Interrupt + 164 .section .text.ADC_IRQ_SetVector,"ax",%progbits + 165 .align 2 + 166 .global ADC_IRQ_SetVector + 167 .code 16 + 168 .thumb_func + 169 .type ADC_IRQ_SetVector, %function + 170 ADC_IRQ_SetVector: + 171 .LFB4: + 170:Generated_Source\PSoC4/ADC_IRQ.c **** + 171:Generated_Source\PSoC4/ADC_IRQ.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 7 + + + 172:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 173:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_SetVector + 174:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 175:Generated_Source\PSoC4/ADC_IRQ.c **** * + 176:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 177:Generated_Source\PSoC4/ADC_IRQ.c **** * Change the ISR vector for the Interrupt. Note calling ADC_IRQ_Start + 178:Generated_Source\PSoC4/ADC_IRQ.c **** * will override any effect this method would have had. To set the vector + 179:Generated_Source\PSoC4/ADC_IRQ.c **** * before the component has been started use ADC_IRQ_StartEx instead. + 180:Generated_Source\PSoC4/ADC_IRQ.c **** * + 181:Generated_Source\PSoC4/ADC_IRQ.c **** * When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be + 182:Generated_Source\PSoC4/ADC_IRQ.c **** * used to provide consistent definition across compilers: + 183:Generated_Source\PSoC4/ADC_IRQ.c **** * + 184:Generated_Source\PSoC4/ADC_IRQ.c **** * Function definition example: + 185:Generated_Source\PSoC4/ADC_IRQ.c **** * CY_ISR(MyISR) + 186:Generated_Source\PSoC4/ADC_IRQ.c **** * { + 187:Generated_Source\PSoC4/ADC_IRQ.c **** * } + 188:Generated_Source\PSoC4/ADC_IRQ.c **** * + 189:Generated_Source\PSoC4/ADC_IRQ.c **** * Function prototype example: + 190:Generated_Source\PSoC4/ADC_IRQ.c **** * CY_ISR_PROTO(MyISR); + 191:Generated_Source\PSoC4/ADC_IRQ.c **** * + 192:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 193:Generated_Source\PSoC4/ADC_IRQ.c **** * address: Address of the ISR to set in the interrupt vector table. + 194:Generated_Source\PSoC4/ADC_IRQ.c **** * + 195:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 196:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 197:Generated_Source\PSoC4/ADC_IRQ.c **** * + 198:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 199:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_SetVector(cyisraddress address) + 200:Generated_Source\PSoC4/ADC_IRQ.c **** { + 172 .loc 1 200 0 + 173 .cfi_startproc + 174 @ args = 0, pretend = 0, frame = 8 + 175 @ frame_needed = 1, uses_anonymous_args = 0 + 176 0000 80B5 push {r7, lr} + 177 .cfi_def_cfa_offset 8 + 178 .cfi_offset 7, -8 + 179 .cfi_offset 14, -4 + 180 0002 82B0 sub sp, sp, #8 + 181 .cfi_def_cfa_offset 16 + 182 0004 00AF add r7, sp, #0 + 183 .cfi_def_cfa_register 7 + 184 0006 7860 str r0, [r7, #4] + 201:Generated_Source\PSoC4/ADC_IRQ.c **** CyRamVectors[CYINT_IRQ_BASE + ADC_IRQ__INTC_NUMBER] = address; + 185 .loc 1 201 0 + 186 0008 034B ldr r3, .L10 + 187 000a 7A68 ldr r2, [r7, #4] + 188 000c 9A67 str r2, [r3, #120] + 202:Generated_Source\PSoC4/ADC_IRQ.c **** } + 189 .loc 1 202 0 + 190 000e C046 nop + 191 0010 BD46 mov sp, r7 + 192 0012 02B0 add sp, sp, #8 + 193 @ sp needed + 194 0014 80BD pop {r7, pc} + 195 .L11: + 196 0016 C046 .align 2 + 197 .L10: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 8 + + + 198 0018 00000000 .word CyRamVectors + 199 .cfi_endproc + 200 .LFE4: + 201 .size ADC_IRQ_SetVector, .-ADC_IRQ_SetVector + 202 .section .text.ADC_IRQ_GetVector,"ax",%progbits + 203 .align 2 + 204 .global ADC_IRQ_GetVector + 205 .code 16 + 206 .thumb_func + 207 .type ADC_IRQ_GetVector, %function + 208 ADC_IRQ_GetVector: + 209 .LFB5: + 203:Generated_Source\PSoC4/ADC_IRQ.c **** + 204:Generated_Source\PSoC4/ADC_IRQ.c **** + 205:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 206:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_GetVector + 207:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 208:Generated_Source\PSoC4/ADC_IRQ.c **** * + 209:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 210:Generated_Source\PSoC4/ADC_IRQ.c **** * Gets the "address" of the current ISR vector for the Interrupt. + 211:Generated_Source\PSoC4/ADC_IRQ.c **** * + 212:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 213:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 214:Generated_Source\PSoC4/ADC_IRQ.c **** * + 215:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 216:Generated_Source\PSoC4/ADC_IRQ.c **** * Address of the ISR in the interrupt vector table. + 217:Generated_Source\PSoC4/ADC_IRQ.c **** * + 218:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 219:Generated_Source\PSoC4/ADC_IRQ.c **** cyisraddress ADC_IRQ_GetVector(void) + 220:Generated_Source\PSoC4/ADC_IRQ.c **** { + 210 .loc 1 220 0 + 211 .cfi_startproc + 212 @ args = 0, pretend = 0, frame = 0 + 213 @ frame_needed = 1, uses_anonymous_args = 0 + 214 0000 80B5 push {r7, lr} + 215 .cfi_def_cfa_offset 8 + 216 .cfi_offset 7, -8 + 217 .cfi_offset 14, -4 + 218 0002 00AF add r7, sp, #0 + 219 .cfi_def_cfa_register 7 + 221:Generated_Source\PSoC4/ADC_IRQ.c **** return CyRamVectors[CYINT_IRQ_BASE + ADC_IRQ__INTC_NUMBER]; + 220 .loc 1 221 0 + 221 0004 024B ldr r3, .L14 + 222 0006 9B6F ldr r3, [r3, #120] + 222:Generated_Source\PSoC4/ADC_IRQ.c **** } + 223 .loc 1 222 0 + 224 0008 1800 movs r0, r3 + 225 000a BD46 mov sp, r7 + 226 @ sp needed + 227 000c 80BD pop {r7, pc} + 228 .L15: + 229 000e C046 .align 2 + 230 .L14: + 231 0010 00000000 .word CyRamVectors + 232 .cfi_endproc + 233 .LFE5: + 234 .size ADC_IRQ_GetVector, .-ADC_IRQ_GetVector + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 9 + + + 235 .section .text.ADC_IRQ_SetPriority,"ax",%progbits + 236 .align 2 + 237 .global ADC_IRQ_SetPriority + 238 .code 16 + 239 .thumb_func + 240 .type ADC_IRQ_SetPriority, %function + 241 ADC_IRQ_SetPriority: + 242 .LFB6: + 223:Generated_Source\PSoC4/ADC_IRQ.c **** + 224:Generated_Source\PSoC4/ADC_IRQ.c **** + 225:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 226:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_SetPriority + 227:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 228:Generated_Source\PSoC4/ADC_IRQ.c **** * + 229:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 230:Generated_Source\PSoC4/ADC_IRQ.c **** * Sets the Priority of the Interrupt. + 231:Generated_Source\PSoC4/ADC_IRQ.c **** * + 232:Generated_Source\PSoC4/ADC_IRQ.c **** * Note calling ADC_IRQ_Start or ADC_IRQ_StartEx will + 233:Generated_Source\PSoC4/ADC_IRQ.c **** * override any effect this API would have had. This API should only be called + 234:Generated_Source\PSoC4/ADC_IRQ.c **** * after ADC_IRQ_Start or ADC_IRQ_StartEx has been called. + 235:Generated_Source\PSoC4/ADC_IRQ.c **** * To set the initial priority for the component, use the Design-Wide Resources + 236:Generated_Source\PSoC4/ADC_IRQ.c **** * Interrupt Editor. + 237:Generated_Source\PSoC4/ADC_IRQ.c **** * + 238:Generated_Source\PSoC4/ADC_IRQ.c **** * Note This API has no effect on Non-maskable interrupt NMI). + 239:Generated_Source\PSoC4/ADC_IRQ.c **** * + 240:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 241:Generated_Source\PSoC4/ADC_IRQ.c **** * priority: Priority of the interrupt, 0 being the highest priority + 242:Generated_Source\PSoC4/ADC_IRQ.c **** * PSoC 3 and PSoC 5LP: Priority is from 0 to 7. + 243:Generated_Source\PSoC4/ADC_IRQ.c **** * PSoC 4: Priority is from 0 to 3. + 244:Generated_Source\PSoC4/ADC_IRQ.c **** * + 245:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 246:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 247:Generated_Source\PSoC4/ADC_IRQ.c **** * + 248:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 249:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_SetPriority(uint8 priority) + 250:Generated_Source\PSoC4/ADC_IRQ.c **** { + 243 .loc 1 250 0 + 244 .cfi_startproc + 245 @ args = 0, pretend = 0, frame = 16 + 246 @ frame_needed = 1, uses_anonymous_args = 0 + 247 0000 90B5 push {r4, r7, lr} + 248 .cfi_def_cfa_offset 12 + 249 .cfi_offset 4, -12 + 250 .cfi_offset 7, -8 + 251 .cfi_offset 14, -4 + 252 0002 85B0 sub sp, sp, #20 + 253 .cfi_def_cfa_offset 32 + 254 0004 00AF add r7, sp, #0 + 255 .cfi_def_cfa_register 7 + 256 0006 0200 movs r2, r0 + 257 0008 FB1D adds r3, r7, #7 + 258 000a 1A70 strb r2, [r3] + 251:Generated_Source\PSoC4/ADC_IRQ.c **** uint8 interruptState; + 252:Generated_Source\PSoC4/ADC_IRQ.c **** uint32 priorityOffset = ((ADC_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + 259 .loc 1 252 0 + 260 000c 1623 movs r3, #22 + 261 000e FB60 str r3, [r7, #12] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 10 + + + 253:Generated_Source\PSoC4/ADC_IRQ.c **** + 254:Generated_Source\PSoC4/ADC_IRQ.c **** interruptState = CyEnterCriticalSection(); + 262 .loc 1 254 0 + 263 0010 0B23 movs r3, #11 + 264 0012 FC18 adds r4, r7, r3 + 265 0014 FFF7FEFF bl CyEnterCriticalSection + 266 0018 0300 movs r3, r0 + 267 001a 2370 strb r3, [r4] + 255:Generated_Source\PSoC4/ADC_IRQ.c **** *ADC_IRQ_INTC_PRIOR = (*ADC_IRQ_INTC_PRIOR & (uint32)(~ADC_IRQ__INTC_PRIOR_MASK)) | + 268 .loc 1 255 0 + 269 001c 0A4B ldr r3, .L17 + 270 001e 0A4A ldr r2, .L17 + 271 0020 1268 ldr r2, [r2] + 272 0022 0A49 ldr r1, .L17+4 + 273 0024 1140 ands r1, r2 + 256:Generated_Source\PSoC4/ADC_IRQ.c **** ((uint32)priority << priorityOffset); + 274 .loc 1 256 0 + 275 0026 FA1D adds r2, r7, #7 + 276 0028 1078 ldrb r0, [r2] + 277 002a FA68 ldr r2, [r7, #12] + 278 002c 9040 lsls r0, r0, r2 + 279 002e 0200 movs r2, r0 + 255:Generated_Source\PSoC4/ADC_IRQ.c **** *ADC_IRQ_INTC_PRIOR = (*ADC_IRQ_INTC_PRIOR & (uint32)(~ADC_IRQ__INTC_PRIOR_MASK)) | + 280 .loc 1 255 0 + 281 0030 0A43 orrs r2, r1 + 282 0032 1A60 str r2, [r3] + 257:Generated_Source\PSoC4/ADC_IRQ.c **** CyExitCriticalSection(interruptState); + 283 .loc 1 257 0 + 284 0034 0B23 movs r3, #11 + 285 0036 FB18 adds r3, r7, r3 + 286 0038 1B78 ldrb r3, [r3] + 287 003a 1800 movs r0, r3 + 288 003c FFF7FEFF bl CyExitCriticalSection + 258:Generated_Source\PSoC4/ADC_IRQ.c **** } + 289 .loc 1 258 0 + 290 0040 C046 nop + 291 0042 BD46 mov sp, r7 + 292 0044 05B0 add sp, sp, #20 + 293 @ sp needed + 294 0046 90BD pop {r4, r7, pc} + 295 .L18: + 296 .align 2 + 297 .L17: + 298 0048 0CE400E0 .word -536812532 + 299 004c FFFF3FFF .word -12582913 + 300 .cfi_endproc + 301 .LFE6: + 302 .size ADC_IRQ_SetPriority, .-ADC_IRQ_SetPriority + 303 .section .text.ADC_IRQ_GetPriority,"ax",%progbits + 304 .align 2 + 305 .global ADC_IRQ_GetPriority + 306 .code 16 + 307 .thumb_func + 308 .type ADC_IRQ_GetPriority, %function + 309 ADC_IRQ_GetPriority: + 310 .LFB7: + 259:Generated_Source\PSoC4/ADC_IRQ.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 11 + + + 260:Generated_Source\PSoC4/ADC_IRQ.c **** + 261:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 262:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_GetPriority + 263:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 264:Generated_Source\PSoC4/ADC_IRQ.c **** * + 265:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 266:Generated_Source\PSoC4/ADC_IRQ.c **** * Gets the Priority of the Interrupt. + 267:Generated_Source\PSoC4/ADC_IRQ.c **** * + 268:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 269:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 270:Generated_Source\PSoC4/ADC_IRQ.c **** * + 271:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 272:Generated_Source\PSoC4/ADC_IRQ.c **** * Priority of the interrupt, 0 being the highest priority + 273:Generated_Source\PSoC4/ADC_IRQ.c **** * PSoC 3 and PSoC 5LP: Priority is from 0 to 7. + 274:Generated_Source\PSoC4/ADC_IRQ.c **** * PSoC 4: Priority is from 0 to 3. + 275:Generated_Source\PSoC4/ADC_IRQ.c **** * + 276:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 277:Generated_Source\PSoC4/ADC_IRQ.c **** uint8 ADC_IRQ_GetPriority(void) + 278:Generated_Source\PSoC4/ADC_IRQ.c **** { + 311 .loc 1 278 0 + 312 .cfi_startproc + 313 @ args = 0, pretend = 0, frame = 8 + 314 @ frame_needed = 1, uses_anonymous_args = 0 + 315 0000 80B5 push {r7, lr} + 316 .cfi_def_cfa_offset 8 + 317 .cfi_offset 7, -8 + 318 .cfi_offset 14, -4 + 319 0002 82B0 sub sp, sp, #8 + 320 .cfi_def_cfa_offset 16 + 321 0004 00AF add r7, sp, #0 + 322 .cfi_def_cfa_register 7 + 279:Generated_Source\PSoC4/ADC_IRQ.c **** uint32 priority; + 280:Generated_Source\PSoC4/ADC_IRQ.c **** uint32 priorityOffset = ((ADC_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + 323 .loc 1 280 0 + 324 0006 1623 movs r3, #22 + 325 0008 7B60 str r3, [r7, #4] + 281:Generated_Source\PSoC4/ADC_IRQ.c **** + 282:Generated_Source\PSoC4/ADC_IRQ.c **** priority = (*ADC_IRQ_INTC_PRIOR & ADC_IRQ__INTC_PRIOR_MASK) >> priorityOffset; + 326 .loc 1 282 0 + 327 000a 074B ldr r3, .L21 + 328 000c 1A68 ldr r2, [r3] + 329 000e C023 movs r3, #192 + 330 0010 1B04 lsls r3, r3, #16 + 331 0012 1A40 ands r2, r3 + 332 0014 7B68 ldr r3, [r7, #4] + 333 0016 DA40 lsrs r2, r2, r3 + 334 0018 1300 movs r3, r2 + 335 001a 3B60 str r3, [r7] + 283:Generated_Source\PSoC4/ADC_IRQ.c **** + 284:Generated_Source\PSoC4/ADC_IRQ.c **** return (uint8)priority; + 336 .loc 1 284 0 + 337 001c 3B68 ldr r3, [r7] + 338 001e DBB2 uxtb r3, r3 + 285:Generated_Source\PSoC4/ADC_IRQ.c **** } + 339 .loc 1 285 0 + 340 0020 1800 movs r0, r3 + 341 0022 BD46 mov sp, r7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 12 + + + 342 0024 02B0 add sp, sp, #8 + 343 @ sp needed + 344 0026 80BD pop {r7, pc} + 345 .L22: + 346 .align 2 + 347 .L21: + 348 0028 0CE400E0 .word -536812532 + 349 .cfi_endproc + 350 .LFE7: + 351 .size ADC_IRQ_GetPriority, .-ADC_IRQ_GetPriority + 352 .section .text.ADC_IRQ_Enable,"ax",%progbits + 353 .align 2 + 354 .global ADC_IRQ_Enable + 355 .code 16 + 356 .thumb_func + 357 .type ADC_IRQ_Enable, %function + 358 ADC_IRQ_Enable: + 359 .LFB8: + 286:Generated_Source\PSoC4/ADC_IRQ.c **** + 287:Generated_Source\PSoC4/ADC_IRQ.c **** + 288:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 289:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_Enable + 290:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 291:Generated_Source\PSoC4/ADC_IRQ.c **** * + 292:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 293:Generated_Source\PSoC4/ADC_IRQ.c **** * Enables the interrupt to the interrupt controller. Do not call this function + 294:Generated_Source\PSoC4/ADC_IRQ.c **** * unless ISR_Start() has been called or the functionality of the ISR_Start() + 295:Generated_Source\PSoC4/ADC_IRQ.c **** * function, which sets the vector and the priority, has been called. + 296:Generated_Source\PSoC4/ADC_IRQ.c **** * + 297:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 298:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 299:Generated_Source\PSoC4/ADC_IRQ.c **** * + 300:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 301:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 302:Generated_Source\PSoC4/ADC_IRQ.c **** * + 303:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 304:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_Enable(void) + 305:Generated_Source\PSoC4/ADC_IRQ.c **** { + 360 .loc 1 305 0 + 361 .cfi_startproc + 362 @ args = 0, pretend = 0, frame = 0 + 363 @ frame_needed = 1, uses_anonymous_args = 0 + 364 0000 80B5 push {r7, lr} + 365 .cfi_def_cfa_offset 8 + 366 .cfi_offset 7, -8 + 367 .cfi_offset 14, -4 + 368 0002 00AF add r7, sp, #0 + 369 .cfi_def_cfa_register 7 + 306:Generated_Source\PSoC4/ADC_IRQ.c **** /* Enable the general interrupt. */ + 307:Generated_Source\PSoC4/ADC_IRQ.c **** *ADC_IRQ_INTC_SET_EN = ADC_IRQ__INTC_MASK; + 370 .loc 1 307 0 + 371 0004 034B ldr r3, .L24 + 372 0006 8022 movs r2, #128 + 373 0008 D201 lsls r2, r2, #7 + 374 000a 1A60 str r2, [r3] + 308:Generated_Source\PSoC4/ADC_IRQ.c **** } + 375 .loc 1 308 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 13 + + + 376 000c C046 nop + 377 000e BD46 mov sp, r7 + 378 @ sp needed + 379 0010 80BD pop {r7, pc} + 380 .L25: + 381 0012 C046 .align 2 + 382 .L24: + 383 0014 00E100E0 .word -536813312 + 384 .cfi_endproc + 385 .LFE8: + 386 .size ADC_IRQ_Enable, .-ADC_IRQ_Enable + 387 .section .text.ADC_IRQ_GetState,"ax",%progbits + 388 .align 2 + 389 .global ADC_IRQ_GetState + 390 .code 16 + 391 .thumb_func + 392 .type ADC_IRQ_GetState, %function + 393 ADC_IRQ_GetState: + 394 .LFB9: + 309:Generated_Source\PSoC4/ADC_IRQ.c **** + 310:Generated_Source\PSoC4/ADC_IRQ.c **** + 311:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 312:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_GetState + 313:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 314:Generated_Source\PSoC4/ADC_IRQ.c **** * + 315:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 316:Generated_Source\PSoC4/ADC_IRQ.c **** * Gets the state (enabled, disabled) of the Interrupt. + 317:Generated_Source\PSoC4/ADC_IRQ.c **** * + 318:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 319:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 320:Generated_Source\PSoC4/ADC_IRQ.c **** * + 321:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 322:Generated_Source\PSoC4/ADC_IRQ.c **** * 1 if enabled, 0 if disabled. + 323:Generated_Source\PSoC4/ADC_IRQ.c **** * + 324:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 325:Generated_Source\PSoC4/ADC_IRQ.c **** uint8 ADC_IRQ_GetState(void) + 326:Generated_Source\PSoC4/ADC_IRQ.c **** { + 395 .loc 1 326 0 + 396 .cfi_startproc + 397 @ args = 0, pretend = 0, frame = 0 + 398 @ frame_needed = 1, uses_anonymous_args = 0 + 399 0000 80B5 push {r7, lr} + 400 .cfi_def_cfa_offset 8 + 401 .cfi_offset 7, -8 + 402 .cfi_offset 14, -4 + 403 0002 00AF add r7, sp, #0 + 404 .cfi_def_cfa_register 7 + 327:Generated_Source\PSoC4/ADC_IRQ.c **** /* Get the state of the general interrupt. */ + 328:Generated_Source\PSoC4/ADC_IRQ.c **** return ((*ADC_IRQ_INTC_SET_EN & (uint32)ADC_IRQ__INTC_MASK) != 0u) ? 1u:0u; + 405 .loc 1 328 0 + 406 0004 054B ldr r3, .L30 + 407 0006 1A68 ldr r2, [r3] + 408 0008 8023 movs r3, #128 + 409 000a DB01 lsls r3, r3, #7 + 410 000c 1340 ands r3, r2 + 411 000e 01D0 beq .L27 + 412 .loc 1 328 0 is_stmt 0 discriminator 1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 14 + + + 413 0010 0123 movs r3, #1 + 414 0012 00E0 b .L28 + 415 .L27: + 416 .loc 1 328 0 discriminator 2 + 417 0014 0023 movs r3, #0 + 418 .L28: + 329:Generated_Source\PSoC4/ADC_IRQ.c **** } + 419 .loc 1 329 0 is_stmt 1 discriminator 4 + 420 0016 1800 movs r0, r3 + 421 0018 BD46 mov sp, r7 + 422 @ sp needed + 423 001a 80BD pop {r7, pc} + 424 .L31: + 425 .align 2 + 426 .L30: + 427 001c 00E100E0 .word -536813312 + 428 .cfi_endproc + 429 .LFE9: + 430 .size ADC_IRQ_GetState, .-ADC_IRQ_GetState + 431 .section .text.ADC_IRQ_Disable,"ax",%progbits + 432 .align 2 + 433 .global ADC_IRQ_Disable + 434 .code 16 + 435 .thumb_func + 436 .type ADC_IRQ_Disable, %function + 437 ADC_IRQ_Disable: + 438 .LFB10: + 330:Generated_Source\PSoC4/ADC_IRQ.c **** + 331:Generated_Source\PSoC4/ADC_IRQ.c **** + 332:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 333:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_Disable + 334:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 335:Generated_Source\PSoC4/ADC_IRQ.c **** * + 336:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 337:Generated_Source\PSoC4/ADC_IRQ.c **** * Disables the Interrupt in the interrupt controller. + 338:Generated_Source\PSoC4/ADC_IRQ.c **** * + 339:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 340:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 341:Generated_Source\PSoC4/ADC_IRQ.c **** * + 342:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 343:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 344:Generated_Source\PSoC4/ADC_IRQ.c **** * + 345:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 346:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_Disable(void) + 347:Generated_Source\PSoC4/ADC_IRQ.c **** { + 439 .loc 1 347 0 + 440 .cfi_startproc + 441 @ args = 0, pretend = 0, frame = 0 + 442 @ frame_needed = 1, uses_anonymous_args = 0 + 443 0000 80B5 push {r7, lr} + 444 .cfi_def_cfa_offset 8 + 445 .cfi_offset 7, -8 + 446 .cfi_offset 14, -4 + 447 0002 00AF add r7, sp, #0 + 448 .cfi_def_cfa_register 7 + 348:Generated_Source\PSoC4/ADC_IRQ.c **** /* Disable the general interrupt. */ + 349:Generated_Source\PSoC4/ADC_IRQ.c **** *ADC_IRQ_INTC_CLR_EN = ADC_IRQ__INTC_MASK; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 15 + + + 449 .loc 1 349 0 + 450 0004 034B ldr r3, .L33 + 451 0006 8022 movs r2, #128 + 452 0008 D201 lsls r2, r2, #7 + 453 000a 1A60 str r2, [r3] + 350:Generated_Source\PSoC4/ADC_IRQ.c **** } + 454 .loc 1 350 0 + 455 000c C046 nop + 456 000e BD46 mov sp, r7 + 457 @ sp needed + 458 0010 80BD pop {r7, pc} + 459 .L34: + 460 0012 C046 .align 2 + 461 .L33: + 462 0014 80E100E0 .word -536813184 + 463 .cfi_endproc + 464 .LFE10: + 465 .size ADC_IRQ_Disable, .-ADC_IRQ_Disable + 466 .section .text.ADC_IRQ_SetPending,"ax",%progbits + 467 .align 2 + 468 .global ADC_IRQ_SetPending + 469 .code 16 + 470 .thumb_func + 471 .type ADC_IRQ_SetPending, %function + 472 ADC_IRQ_SetPending: + 473 .LFB11: + 351:Generated_Source\PSoC4/ADC_IRQ.c **** + 352:Generated_Source\PSoC4/ADC_IRQ.c **** + 353:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 354:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_SetPending + 355:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 356:Generated_Source\PSoC4/ADC_IRQ.c **** * + 357:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 358:Generated_Source\PSoC4/ADC_IRQ.c **** * Causes the Interrupt to enter the pending state, a software method of + 359:Generated_Source\PSoC4/ADC_IRQ.c **** * generating the interrupt. + 360:Generated_Source\PSoC4/ADC_IRQ.c **** * + 361:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 362:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 363:Generated_Source\PSoC4/ADC_IRQ.c **** * + 364:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 365:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 366:Generated_Source\PSoC4/ADC_IRQ.c **** * + 367:Generated_Source\PSoC4/ADC_IRQ.c **** * Side Effects: + 368:Generated_Source\PSoC4/ADC_IRQ.c **** * If interrupts are enabled and the interrupt is set up properly, the ISR is + 369:Generated_Source\PSoC4/ADC_IRQ.c **** * entered (depending on the priority of this interrupt and other pending + 370:Generated_Source\PSoC4/ADC_IRQ.c **** * interrupts). + 371:Generated_Source\PSoC4/ADC_IRQ.c **** * + 372:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 373:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_SetPending(void) + 374:Generated_Source\PSoC4/ADC_IRQ.c **** { + 474 .loc 1 374 0 + 475 .cfi_startproc + 476 @ args = 0, pretend = 0, frame = 0 + 477 @ frame_needed = 1, uses_anonymous_args = 0 + 478 0000 80B5 push {r7, lr} + 479 .cfi_def_cfa_offset 8 + 480 .cfi_offset 7, -8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 16 + + + 481 .cfi_offset 14, -4 + 482 0002 00AF add r7, sp, #0 + 483 .cfi_def_cfa_register 7 + 375:Generated_Source\PSoC4/ADC_IRQ.c **** *ADC_IRQ_INTC_SET_PD = ADC_IRQ__INTC_MASK; + 484 .loc 1 375 0 + 485 0004 034B ldr r3, .L36 + 486 0006 8022 movs r2, #128 + 487 0008 D201 lsls r2, r2, #7 + 488 000a 1A60 str r2, [r3] + 376:Generated_Source\PSoC4/ADC_IRQ.c **** } + 489 .loc 1 376 0 + 490 000c C046 nop + 491 000e BD46 mov sp, r7 + 492 @ sp needed + 493 0010 80BD pop {r7, pc} + 494 .L37: + 495 0012 C046 .align 2 + 496 .L36: + 497 0014 00E200E0 .word -536813056 + 498 .cfi_endproc + 499 .LFE11: + 500 .size ADC_IRQ_SetPending, .-ADC_IRQ_SetPending + 501 .section .text.ADC_IRQ_ClearPending,"ax",%progbits + 502 .align 2 + 503 .global ADC_IRQ_ClearPending + 504 .code 16 + 505 .thumb_func + 506 .type ADC_IRQ_ClearPending, %function + 507 ADC_IRQ_ClearPending: + 508 .LFB12: + 377:Generated_Source\PSoC4/ADC_IRQ.c **** + 378:Generated_Source\PSoC4/ADC_IRQ.c **** + 379:Generated_Source\PSoC4/ADC_IRQ.c **** /******************************************************************************* + 380:Generated_Source\PSoC4/ADC_IRQ.c **** * Function Name: ADC_IRQ_ClearPending + 381:Generated_Source\PSoC4/ADC_IRQ.c **** ******************************************************************************** + 382:Generated_Source\PSoC4/ADC_IRQ.c **** * + 383:Generated_Source\PSoC4/ADC_IRQ.c **** * Summary: + 384:Generated_Source\PSoC4/ADC_IRQ.c **** * Clears a pending interrupt in the interrupt controller. + 385:Generated_Source\PSoC4/ADC_IRQ.c **** * + 386:Generated_Source\PSoC4/ADC_IRQ.c **** * Note Some interrupt sources are clear-on-read and require the block + 387:Generated_Source\PSoC4/ADC_IRQ.c **** * interrupt/status register to be read/cleared with the appropriate block API + 388:Generated_Source\PSoC4/ADC_IRQ.c **** * (GPIO, UART, and so on). Otherwise the ISR will continue to remain in + 389:Generated_Source\PSoC4/ADC_IRQ.c **** * pending state even though the interrupt itself is cleared using this API. + 390:Generated_Source\PSoC4/ADC_IRQ.c **** * + 391:Generated_Source\PSoC4/ADC_IRQ.c **** * Parameters: + 392:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 393:Generated_Source\PSoC4/ADC_IRQ.c **** * + 394:Generated_Source\PSoC4/ADC_IRQ.c **** * Return: + 395:Generated_Source\PSoC4/ADC_IRQ.c **** * None + 396:Generated_Source\PSoC4/ADC_IRQ.c **** * + 397:Generated_Source\PSoC4/ADC_IRQ.c **** *******************************************************************************/ + 398:Generated_Source\PSoC4/ADC_IRQ.c **** void ADC_IRQ_ClearPending(void) + 399:Generated_Source\PSoC4/ADC_IRQ.c **** { + 509 .loc 1 399 0 + 510 .cfi_startproc + 511 @ args = 0, pretend = 0, frame = 0 + 512 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 17 + + + 513 0000 80B5 push {r7, lr} + 514 .cfi_def_cfa_offset 8 + 515 .cfi_offset 7, -8 + 516 .cfi_offset 14, -4 + 517 0002 00AF add r7, sp, #0 + 518 .cfi_def_cfa_register 7 + 400:Generated_Source\PSoC4/ADC_IRQ.c **** *ADC_IRQ_INTC_CLR_PD = ADC_IRQ__INTC_MASK; + 519 .loc 1 400 0 + 520 0004 034B ldr r3, .L39 + 521 0006 8022 movs r2, #128 + 522 0008 D201 lsls r2, r2, #7 + 523 000a 1A60 str r2, [r3] + 401:Generated_Source\PSoC4/ADC_IRQ.c **** } + 524 .loc 1 401 0 + 525 000c C046 nop + 526 000e BD46 mov sp, r7 + 527 @ sp needed + 528 0010 80BD pop {r7, pc} + 529 .L40: + 530 0012 C046 .align 2 + 531 .L39: + 532 0014 80E200E0 .word -536812928 + 533 .cfi_endproc + 534 .LFE12: + 535 .size ADC_IRQ_ClearPending, .-ADC_IRQ_ClearPending + 536 .text + 537 .Letext0: + 538 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 539 .section .debug_info,"",%progbits + 540 .Ldebug_info0: + 541 0000 49020000 .4byte 0x249 + 542 0004 0400 .2byte 0x4 + 543 0006 00000000 .4byte .Ldebug_abbrev0 + 544 000a 04 .byte 0x4 + 545 000b 01 .uleb128 0x1 + 546 000c 10010000 .4byte .LASF34 + 547 0010 0C .byte 0xc + 548 0011 E4010000 .4byte .LASF35 + 549 0015 7A000000 .4byte .LASF36 + 550 0019 00000000 .4byte .Ldebug_ranges0+0 + 551 001d 00000000 .4byte 0 + 552 0021 00000000 .4byte .Ldebug_line0 + 553 0025 02 .uleb128 0x2 + 554 0026 01 .byte 0x1 + 555 0027 06 .byte 0x6 + 556 0028 C3020000 .4byte .LASF0 + 557 002c 02 .uleb128 0x2 + 558 002d 01 .byte 0x1 + 559 002e 08 .byte 0x8 + 560 002f DB000000 .4byte .LASF1 + 561 0033 02 .uleb128 0x2 + 562 0034 02 .byte 0x2 + 563 0035 05 .byte 0x5 + 564 0036 85020000 .4byte .LASF2 + 565 003a 02 .uleb128 0x2 + 566 003b 02 .byte 0x2 + 567 003c 07 .byte 0x7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 18 + + + 568 003d 44000000 .4byte .LASF3 + 569 0041 02 .uleb128 0x2 + 570 0042 04 .byte 0x4 + 571 0043 05 .byte 0x5 + 572 0044 AE020000 .4byte .LASF4 + 573 0048 02 .uleb128 0x2 + 574 0049 04 .byte 0x4 + 575 004a 07 .byte 0x7 + 576 004b F8000000 .4byte .LASF5 + 577 004f 02 .uleb128 0x2 + 578 0050 08 .byte 0x8 + 579 0051 05 .byte 0x5 + 580 0052 72020000 .4byte .LASF6 + 581 0056 02 .uleb128 0x2 + 582 0057 08 .byte 0x8 + 583 0058 07 .byte 0x7 + 584 0059 35020000 .4byte .LASF7 + 585 005d 03 .uleb128 0x3 + 586 005e 04 .byte 0x4 + 587 005f 05 .byte 0x5 + 588 0060 696E7400 .ascii "int\000" + 589 0064 02 .uleb128 0x2 + 590 0065 04 .byte 0x4 + 591 0066 07 .byte 0x7 + 592 0067 20020000 .4byte .LASF8 + 593 006b 04 .uleb128 0x4 + 594 006c 0A010000 .4byte .LASF9 + 595 0070 02 .byte 0x2 + 596 0071 E401 .2byte 0x1e4 + 597 0073 2C000000 .4byte 0x2c + 598 0077 04 .uleb128 0x4 + 599 0078 19020000 .4byte .LASF10 + 600 007c 02 .byte 0x2 + 601 007d E601 .2byte 0x1e6 + 602 007f 48000000 .4byte 0x48 + 603 0083 02 .uleb128 0x2 + 604 0084 04 .byte 0x4 + 605 0085 04 .byte 0x4 + 606 0086 D5000000 .4byte .LASF11 + 607 008a 02 .uleb128 0x2 + 608 008b 08 .byte 0x8 + 609 008c 04 .byte 0x4 + 610 008d CF010000 .4byte .LASF12 + 611 0091 02 .uleb128 0x2 + 612 0092 01 .byte 0x1 + 613 0093 08 .byte 0x8 + 614 0094 80020000 .4byte .LASF13 + 615 0098 04 .uleb128 0x4 + 616 0099 00000000 .4byte .LASF14 + 617 009d 02 .byte 0x2 + 618 009e 9002 .2byte 0x290 + 619 00a0 A4000000 .4byte 0xa4 + 620 00a4 05 .uleb128 0x5 + 621 00a5 77000000 .4byte 0x77 + 622 00a9 04 .uleb128 0x4 + 623 00aa 4C020000 .4byte .LASF15 + 624 00ae 02 .byte 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 19 + + + 625 00af A002 .2byte 0x2a0 + 626 00b1 B5000000 .4byte 0xb5 + 627 00b5 06 .uleb128 0x6 + 628 00b6 04 .byte 0x4 + 629 00b7 BB000000 .4byte 0xbb + 630 00bb 07 .uleb128 0x7 + 631 00bc 02 .uleb128 0x2 + 632 00bd 08 .byte 0x8 + 633 00be 04 .byte 0x4 + 634 00bf B7020000 .4byte .LASF16 + 635 00c3 02 .uleb128 0x2 + 636 00c4 04 .byte 0x4 + 637 00c5 07 .byte 0x7 + 638 00c6 69020000 .4byte .LASF17 + 639 00ca 08 .uleb128 0x8 + 640 00cb D6010000 .4byte .LASF18 + 641 00cf 01 .byte 0x1 + 642 00d0 38 .byte 0x38 + 643 00d1 00000000 .4byte .LFB0 + 644 00d5 24000000 .4byte .LFE0-.LFB0 + 645 00d9 01 .uleb128 0x1 + 646 00da 9C .byte 0x9c + 647 00db 09 .uleb128 0x9 + 648 00dc 59020000 .4byte .LASF21 + 649 00e0 01 .byte 0x1 + 650 00e1 63 .byte 0x63 + 651 00e2 00000000 .4byte .LFB1 + 652 00e6 26000000 .4byte .LFE1-.LFB1 + 653 00ea 01 .uleb128 0x1 + 654 00eb 9C .byte 0x9c + 655 00ec FF000000 .4byte 0xff + 656 00f0 0A .uleb128 0xa + 657 00f1 2D020000 .4byte .LASF23 + 658 00f5 01 .byte 0x1 + 659 00f6 63 .byte 0x63 + 660 00f7 A9000000 .4byte 0xa9 + 661 00fb 02 .uleb128 0x2 + 662 00fc 91 .byte 0x91 + 663 00fd 74 .sleb128 -12 + 664 00fe 00 .byte 0 + 665 00ff 08 .uleb128 0x8 + 666 0100 13000000 .4byte .LASF19 + 667 0104 01 .byte 0x1 + 668 0105 81 .byte 0x81 + 669 0106 00000000 .4byte .LFB2 + 670 010a 1C000000 .4byte .LFE2-.LFB2 + 671 010e 01 .uleb128 0x1 + 672 010f 9C .byte 0x9c + 673 0110 0B .uleb128 0xb + 674 0111 20000000 .4byte .LASF20 + 675 0115 01 .byte 0x1 + 676 0116 9F .byte 0x9f + 677 0117 00000000 .4byte .LFB3 + 678 011b 0A000000 .4byte .LFE3-.LFB3 + 679 011f 01 .uleb128 0x1 + 680 0120 9C .byte 0x9c + 681 0121 0C .uleb128 0xc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 20 + + + 682 0122 32000000 .4byte .LASF22 + 683 0126 01 .byte 0x1 + 684 0127 C7 .byte 0xc7 + 685 0128 00000000 .4byte .LFB4 + 686 012c 1C000000 .4byte .LFE4-.LFB4 + 687 0130 01 .uleb128 0x1 + 688 0131 9C .byte 0x9c + 689 0132 45010000 .4byte 0x145 + 690 0136 0A .uleb128 0xa + 691 0137 2D020000 .4byte .LASF23 + 692 013b 01 .byte 0x1 + 693 013c C7 .byte 0xc7 + 694 013d A9000000 .4byte 0xa9 + 695 0141 02 .uleb128 0x2 + 696 0142 91 .byte 0x91 + 697 0143 74 .sleb128 -12 + 698 0144 00 .byte 0 + 699 0145 0D .uleb128 0xd + 700 0146 68000000 .4byte .LASF29 + 701 014a 01 .byte 0x1 + 702 014b DB .byte 0xdb + 703 014c A9000000 .4byte 0xa9 + 704 0150 00000000 .4byte .LFB5 + 705 0154 14000000 .4byte .LFE5-.LFB5 + 706 0158 01 .uleb128 0x1 + 707 0159 9C .byte 0x9c + 708 015a 09 .uleb128 0x9 + 709 015b CF020000 .4byte .LASF24 + 710 015f 01 .byte 0x1 + 711 0160 F9 .byte 0xf9 + 712 0161 00000000 .4byte .LFB6 + 713 0165 50000000 .4byte .LFE6-.LFB6 + 714 0169 01 .uleb128 0x1 + 715 016a 9C .byte 0x9c + 716 016b 9A010000 .4byte 0x19a + 717 016f 0A .uleb128 0xa + 718 0170 9E010000 .4byte .LASF25 + 719 0174 01 .byte 0x1 + 720 0175 F9 .byte 0xf9 + 721 0176 6B000000 .4byte 0x6b + 722 017a 02 .uleb128 0x2 + 723 017b 91 .byte 0x91 + 724 017c 67 .sleb128 -25 + 725 017d 0E .uleb128 0xe + 726 017e E9000000 .4byte .LASF26 + 727 0182 01 .byte 0x1 + 728 0183 FB .byte 0xfb + 729 0184 6B000000 .4byte 0x6b + 730 0188 02 .uleb128 0x2 + 731 0189 91 .byte 0x91 + 732 018a 6B .sleb128 -21 + 733 018b 0E .uleb128 0xe + 734 018c 9F020000 .4byte .LASF27 + 735 0190 01 .byte 0x1 + 736 0191 FC .byte 0xfc + 737 0192 77000000 .4byte 0x77 + 738 0196 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 21 + + + 739 0197 91 .byte 0x91 + 740 0198 6C .sleb128 -20 + 741 0199 00 .byte 0 + 742 019a 0F .uleb128 0xf + 743 019b 05020000 .4byte .LASF37 + 744 019f 01 .byte 0x1 + 745 01a0 1501 .2byte 0x115 + 746 01a2 6B000000 .4byte 0x6b + 747 01a6 00000000 .4byte .LFB7 + 748 01aa 2C000000 .4byte .LFE7-.LFB7 + 749 01ae 01 .uleb128 0x1 + 750 01af 9C .byte 0x9c + 751 01b0 D3010000 .4byte 0x1d3 + 752 01b4 10 .uleb128 0x10 + 753 01b5 9E010000 .4byte .LASF25 + 754 01b9 01 .byte 0x1 + 755 01ba 1701 .2byte 0x117 + 756 01bc 77000000 .4byte 0x77 + 757 01c0 02 .uleb128 0x2 + 758 01c1 91 .byte 0x91 + 759 01c2 70 .sleb128 -16 + 760 01c3 10 .uleb128 0x10 + 761 01c4 9F020000 .4byte .LASF27 + 762 01c8 01 .byte 0x1 + 763 01c9 1801 .2byte 0x118 + 764 01cb 77000000 .4byte 0x77 + 765 01cf 02 .uleb128 0x2 + 766 01d0 91 .byte 0x91 + 767 01d1 74 .sleb128 -12 + 768 01d2 00 .byte 0 + 769 01d3 11 .uleb128 0x11 + 770 01d4 E3020000 .4byte .LASF28 + 771 01d8 01 .byte 0x1 + 772 01d9 3001 .2byte 0x130 + 773 01db 00000000 .4byte .LFB8 + 774 01df 18000000 .4byte .LFE8-.LFB8 + 775 01e3 01 .uleb128 0x1 + 776 01e4 9C .byte 0x9c + 777 01e5 12 .uleb128 0x12 + 778 01e6 57000000 .4byte .LASF30 + 779 01ea 01 .byte 0x1 + 780 01eb 4501 .2byte 0x145 + 781 01ed 6B000000 .4byte 0x6b + 782 01f1 00000000 .4byte .LFB9 + 783 01f5 20000000 .4byte .LFE9-.LFB9 + 784 01f9 01 .uleb128 0x1 + 785 01fa 9C .byte 0x9c + 786 01fb 11 .uleb128 0x11 + 787 01fc 8F020000 .4byte .LASF31 + 788 0200 01 .byte 0x1 + 789 0201 5A01 .2byte 0x15a + 790 0203 00000000 .4byte .LFB10 + 791 0207 18000000 .4byte .LFE10-.LFB10 + 792 020b 01 .uleb128 0x1 + 793 020c 9C .byte 0x9c + 794 020d 11 .uleb128 0x11 + 795 020e A7010000 .4byte .LASF32 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 22 + + + 796 0212 01 .byte 0x1 + 797 0213 7501 .2byte 0x175 + 798 0215 00000000 .4byte .LFB11 + 799 0219 18000000 .4byte .LFE11-.LFB11 + 800 021d 01 .uleb128 0x1 + 801 021e 9C .byte 0x9c + 802 021f 11 .uleb128 0x11 + 803 0220 BA010000 .4byte .LASF33 + 804 0224 01 .byte 0x1 + 805 0225 8E01 .2byte 0x18e + 806 0227 00000000 .4byte .LFB12 + 807 022b 18000000 .4byte .LFE12-.LFB12 + 808 022f 01 .uleb128 0x1 + 809 0230 9C .byte 0x9c + 810 0231 13 .uleb128 0x13 + 811 0232 A9000000 .4byte 0xa9 + 812 0236 41020000 .4byte 0x241 + 813 023a 14 .uleb128 0x14 + 814 023b C3000000 .4byte 0xc3 + 815 023f 2F .byte 0x2f + 816 0240 00 .byte 0 + 817 0241 15 .uleb128 0x15 + 818 0242 06000000 .4byte .LASF38 + 819 0246 01 .byte 0x1 + 820 0247 21 .byte 0x21 + 821 0248 31020000 .4byte 0x231 + 822 024c 00 .byte 0 + 823 .section .debug_abbrev,"",%progbits + 824 .Ldebug_abbrev0: + 825 0000 01 .uleb128 0x1 + 826 0001 11 .uleb128 0x11 + 827 0002 01 .byte 0x1 + 828 0003 25 .uleb128 0x25 + 829 0004 0E .uleb128 0xe + 830 0005 13 .uleb128 0x13 + 831 0006 0B .uleb128 0xb + 832 0007 03 .uleb128 0x3 + 833 0008 0E .uleb128 0xe + 834 0009 1B .uleb128 0x1b + 835 000a 0E .uleb128 0xe + 836 000b 55 .uleb128 0x55 + 837 000c 17 .uleb128 0x17 + 838 000d 11 .uleb128 0x11 + 839 000e 01 .uleb128 0x1 + 840 000f 10 .uleb128 0x10 + 841 0010 17 .uleb128 0x17 + 842 0011 00 .byte 0 + 843 0012 00 .byte 0 + 844 0013 02 .uleb128 0x2 + 845 0014 24 .uleb128 0x24 + 846 0015 00 .byte 0 + 847 0016 0B .uleb128 0xb + 848 0017 0B .uleb128 0xb + 849 0018 3E .uleb128 0x3e + 850 0019 0B .uleb128 0xb + 851 001a 03 .uleb128 0x3 + 852 001b 0E .uleb128 0xe + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 23 + + + 853 001c 00 .byte 0 + 854 001d 00 .byte 0 + 855 001e 03 .uleb128 0x3 + 856 001f 24 .uleb128 0x24 + 857 0020 00 .byte 0 + 858 0021 0B .uleb128 0xb + 859 0022 0B .uleb128 0xb + 860 0023 3E .uleb128 0x3e + 861 0024 0B .uleb128 0xb + 862 0025 03 .uleb128 0x3 + 863 0026 08 .uleb128 0x8 + 864 0027 00 .byte 0 + 865 0028 00 .byte 0 + 866 0029 04 .uleb128 0x4 + 867 002a 16 .uleb128 0x16 + 868 002b 00 .byte 0 + 869 002c 03 .uleb128 0x3 + 870 002d 0E .uleb128 0xe + 871 002e 3A .uleb128 0x3a + 872 002f 0B .uleb128 0xb + 873 0030 3B .uleb128 0x3b + 874 0031 05 .uleb128 0x5 + 875 0032 49 .uleb128 0x49 + 876 0033 13 .uleb128 0x13 + 877 0034 00 .byte 0 + 878 0035 00 .byte 0 + 879 0036 05 .uleb128 0x5 + 880 0037 35 .uleb128 0x35 + 881 0038 00 .byte 0 + 882 0039 49 .uleb128 0x49 + 883 003a 13 .uleb128 0x13 + 884 003b 00 .byte 0 + 885 003c 00 .byte 0 + 886 003d 06 .uleb128 0x6 + 887 003e 0F .uleb128 0xf + 888 003f 00 .byte 0 + 889 0040 0B .uleb128 0xb + 890 0041 0B .uleb128 0xb + 891 0042 49 .uleb128 0x49 + 892 0043 13 .uleb128 0x13 + 893 0044 00 .byte 0 + 894 0045 00 .byte 0 + 895 0046 07 .uleb128 0x7 + 896 0047 15 .uleb128 0x15 + 897 0048 00 .byte 0 + 898 0049 27 .uleb128 0x27 + 899 004a 19 .uleb128 0x19 + 900 004b 00 .byte 0 + 901 004c 00 .byte 0 + 902 004d 08 .uleb128 0x8 + 903 004e 2E .uleb128 0x2e + 904 004f 00 .byte 0 + 905 0050 3F .uleb128 0x3f + 906 0051 19 .uleb128 0x19 + 907 0052 03 .uleb128 0x3 + 908 0053 0E .uleb128 0xe + 909 0054 3A .uleb128 0x3a + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 24 + + + 910 0055 0B .uleb128 0xb + 911 0056 3B .uleb128 0x3b + 912 0057 0B .uleb128 0xb + 913 0058 27 .uleb128 0x27 + 914 0059 19 .uleb128 0x19 + 915 005a 11 .uleb128 0x11 + 916 005b 01 .uleb128 0x1 + 917 005c 12 .uleb128 0x12 + 918 005d 06 .uleb128 0x6 + 919 005e 40 .uleb128 0x40 + 920 005f 18 .uleb128 0x18 + 921 0060 9642 .uleb128 0x2116 + 922 0062 19 .uleb128 0x19 + 923 0063 00 .byte 0 + 924 0064 00 .byte 0 + 925 0065 09 .uleb128 0x9 + 926 0066 2E .uleb128 0x2e + 927 0067 01 .byte 0x1 + 928 0068 3F .uleb128 0x3f + 929 0069 19 .uleb128 0x19 + 930 006a 03 .uleb128 0x3 + 931 006b 0E .uleb128 0xe + 932 006c 3A .uleb128 0x3a + 933 006d 0B .uleb128 0xb + 934 006e 3B .uleb128 0x3b + 935 006f 0B .uleb128 0xb + 936 0070 27 .uleb128 0x27 + 937 0071 19 .uleb128 0x19 + 938 0072 11 .uleb128 0x11 + 939 0073 01 .uleb128 0x1 + 940 0074 12 .uleb128 0x12 + 941 0075 06 .uleb128 0x6 + 942 0076 40 .uleb128 0x40 + 943 0077 18 .uleb128 0x18 + 944 0078 9642 .uleb128 0x2116 + 945 007a 19 .uleb128 0x19 + 946 007b 01 .uleb128 0x1 + 947 007c 13 .uleb128 0x13 + 948 007d 00 .byte 0 + 949 007e 00 .byte 0 + 950 007f 0A .uleb128 0xa + 951 0080 05 .uleb128 0x5 + 952 0081 00 .byte 0 + 953 0082 03 .uleb128 0x3 + 954 0083 0E .uleb128 0xe + 955 0084 3A .uleb128 0x3a + 956 0085 0B .uleb128 0xb + 957 0086 3B .uleb128 0x3b + 958 0087 0B .uleb128 0xb + 959 0088 49 .uleb128 0x49 + 960 0089 13 .uleb128 0x13 + 961 008a 02 .uleb128 0x2 + 962 008b 18 .uleb128 0x18 + 963 008c 00 .byte 0 + 964 008d 00 .byte 0 + 965 008e 0B .uleb128 0xb + 966 008f 2E .uleb128 0x2e + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 25 + + + 967 0090 00 .byte 0 + 968 0091 3F .uleb128 0x3f + 969 0092 19 .uleb128 0x19 + 970 0093 03 .uleb128 0x3 + 971 0094 0E .uleb128 0xe + 972 0095 3A .uleb128 0x3a + 973 0096 0B .uleb128 0xb + 974 0097 3B .uleb128 0x3b + 975 0098 0B .uleb128 0xb + 976 0099 27 .uleb128 0x27 + 977 009a 19 .uleb128 0x19 + 978 009b 11 .uleb128 0x11 + 979 009c 01 .uleb128 0x1 + 980 009d 12 .uleb128 0x12 + 981 009e 06 .uleb128 0x6 + 982 009f 40 .uleb128 0x40 + 983 00a0 18 .uleb128 0x18 + 984 00a1 9742 .uleb128 0x2117 + 985 00a3 19 .uleb128 0x19 + 986 00a4 00 .byte 0 + 987 00a5 00 .byte 0 + 988 00a6 0C .uleb128 0xc + 989 00a7 2E .uleb128 0x2e + 990 00a8 01 .byte 0x1 + 991 00a9 3F .uleb128 0x3f + 992 00aa 19 .uleb128 0x19 + 993 00ab 03 .uleb128 0x3 + 994 00ac 0E .uleb128 0xe + 995 00ad 3A .uleb128 0x3a + 996 00ae 0B .uleb128 0xb + 997 00af 3B .uleb128 0x3b + 998 00b0 0B .uleb128 0xb + 999 00b1 27 .uleb128 0x27 + 1000 00b2 19 .uleb128 0x19 + 1001 00b3 11 .uleb128 0x11 + 1002 00b4 01 .uleb128 0x1 + 1003 00b5 12 .uleb128 0x12 + 1004 00b6 06 .uleb128 0x6 + 1005 00b7 40 .uleb128 0x40 + 1006 00b8 18 .uleb128 0x18 + 1007 00b9 9742 .uleb128 0x2117 + 1008 00bb 19 .uleb128 0x19 + 1009 00bc 01 .uleb128 0x1 + 1010 00bd 13 .uleb128 0x13 + 1011 00be 00 .byte 0 + 1012 00bf 00 .byte 0 + 1013 00c0 0D .uleb128 0xd + 1014 00c1 2E .uleb128 0x2e + 1015 00c2 00 .byte 0 + 1016 00c3 3F .uleb128 0x3f + 1017 00c4 19 .uleb128 0x19 + 1018 00c5 03 .uleb128 0x3 + 1019 00c6 0E .uleb128 0xe + 1020 00c7 3A .uleb128 0x3a + 1021 00c8 0B .uleb128 0xb + 1022 00c9 3B .uleb128 0x3b + 1023 00ca 0B .uleb128 0xb + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 26 + + + 1024 00cb 27 .uleb128 0x27 + 1025 00cc 19 .uleb128 0x19 + 1026 00cd 49 .uleb128 0x49 + 1027 00ce 13 .uleb128 0x13 + 1028 00cf 11 .uleb128 0x11 + 1029 00d0 01 .uleb128 0x1 + 1030 00d1 12 .uleb128 0x12 + 1031 00d2 06 .uleb128 0x6 + 1032 00d3 40 .uleb128 0x40 + 1033 00d4 18 .uleb128 0x18 + 1034 00d5 9742 .uleb128 0x2117 + 1035 00d7 19 .uleb128 0x19 + 1036 00d8 00 .byte 0 + 1037 00d9 00 .byte 0 + 1038 00da 0E .uleb128 0xe + 1039 00db 34 .uleb128 0x34 + 1040 00dc 00 .byte 0 + 1041 00dd 03 .uleb128 0x3 + 1042 00de 0E .uleb128 0xe + 1043 00df 3A .uleb128 0x3a + 1044 00e0 0B .uleb128 0xb + 1045 00e1 3B .uleb128 0x3b + 1046 00e2 0B .uleb128 0xb + 1047 00e3 49 .uleb128 0x49 + 1048 00e4 13 .uleb128 0x13 + 1049 00e5 02 .uleb128 0x2 + 1050 00e6 18 .uleb128 0x18 + 1051 00e7 00 .byte 0 + 1052 00e8 00 .byte 0 + 1053 00e9 0F .uleb128 0xf + 1054 00ea 2E .uleb128 0x2e + 1055 00eb 01 .byte 0x1 + 1056 00ec 3F .uleb128 0x3f + 1057 00ed 19 .uleb128 0x19 + 1058 00ee 03 .uleb128 0x3 + 1059 00ef 0E .uleb128 0xe + 1060 00f0 3A .uleb128 0x3a + 1061 00f1 0B .uleb128 0xb + 1062 00f2 3B .uleb128 0x3b + 1063 00f3 05 .uleb128 0x5 + 1064 00f4 27 .uleb128 0x27 + 1065 00f5 19 .uleb128 0x19 + 1066 00f6 49 .uleb128 0x49 + 1067 00f7 13 .uleb128 0x13 + 1068 00f8 11 .uleb128 0x11 + 1069 00f9 01 .uleb128 0x1 + 1070 00fa 12 .uleb128 0x12 + 1071 00fb 06 .uleb128 0x6 + 1072 00fc 40 .uleb128 0x40 + 1073 00fd 18 .uleb128 0x18 + 1074 00fe 9742 .uleb128 0x2117 + 1075 0100 19 .uleb128 0x19 + 1076 0101 01 .uleb128 0x1 + 1077 0102 13 .uleb128 0x13 + 1078 0103 00 .byte 0 + 1079 0104 00 .byte 0 + 1080 0105 10 .uleb128 0x10 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 27 + + + 1081 0106 34 .uleb128 0x34 + 1082 0107 00 .byte 0 + 1083 0108 03 .uleb128 0x3 + 1084 0109 0E .uleb128 0xe + 1085 010a 3A .uleb128 0x3a + 1086 010b 0B .uleb128 0xb + 1087 010c 3B .uleb128 0x3b + 1088 010d 05 .uleb128 0x5 + 1089 010e 49 .uleb128 0x49 + 1090 010f 13 .uleb128 0x13 + 1091 0110 02 .uleb128 0x2 + 1092 0111 18 .uleb128 0x18 + 1093 0112 00 .byte 0 + 1094 0113 00 .byte 0 + 1095 0114 11 .uleb128 0x11 + 1096 0115 2E .uleb128 0x2e + 1097 0116 00 .byte 0 + 1098 0117 3F .uleb128 0x3f + 1099 0118 19 .uleb128 0x19 + 1100 0119 03 .uleb128 0x3 + 1101 011a 0E .uleb128 0xe + 1102 011b 3A .uleb128 0x3a + 1103 011c 0B .uleb128 0xb + 1104 011d 3B .uleb128 0x3b + 1105 011e 05 .uleb128 0x5 + 1106 011f 27 .uleb128 0x27 + 1107 0120 19 .uleb128 0x19 + 1108 0121 11 .uleb128 0x11 + 1109 0122 01 .uleb128 0x1 + 1110 0123 12 .uleb128 0x12 + 1111 0124 06 .uleb128 0x6 + 1112 0125 40 .uleb128 0x40 + 1113 0126 18 .uleb128 0x18 + 1114 0127 9742 .uleb128 0x2117 + 1115 0129 19 .uleb128 0x19 + 1116 012a 00 .byte 0 + 1117 012b 00 .byte 0 + 1118 012c 12 .uleb128 0x12 + 1119 012d 2E .uleb128 0x2e + 1120 012e 00 .byte 0 + 1121 012f 3F .uleb128 0x3f + 1122 0130 19 .uleb128 0x19 + 1123 0131 03 .uleb128 0x3 + 1124 0132 0E .uleb128 0xe + 1125 0133 3A .uleb128 0x3a + 1126 0134 0B .uleb128 0xb + 1127 0135 3B .uleb128 0x3b + 1128 0136 05 .uleb128 0x5 + 1129 0137 27 .uleb128 0x27 + 1130 0138 19 .uleb128 0x19 + 1131 0139 49 .uleb128 0x49 + 1132 013a 13 .uleb128 0x13 + 1133 013b 11 .uleb128 0x11 + 1134 013c 01 .uleb128 0x1 + 1135 013d 12 .uleb128 0x12 + 1136 013e 06 .uleb128 0x6 + 1137 013f 40 .uleb128 0x40 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 28 + + + 1138 0140 18 .uleb128 0x18 + 1139 0141 9742 .uleb128 0x2117 + 1140 0143 19 .uleb128 0x19 + 1141 0144 00 .byte 0 + 1142 0145 00 .byte 0 + 1143 0146 13 .uleb128 0x13 + 1144 0147 01 .uleb128 0x1 + 1145 0148 01 .byte 0x1 + 1146 0149 49 .uleb128 0x49 + 1147 014a 13 .uleb128 0x13 + 1148 014b 01 .uleb128 0x1 + 1149 014c 13 .uleb128 0x13 + 1150 014d 00 .byte 0 + 1151 014e 00 .byte 0 + 1152 014f 14 .uleb128 0x14 + 1153 0150 21 .uleb128 0x21 + 1154 0151 00 .byte 0 + 1155 0152 49 .uleb128 0x49 + 1156 0153 13 .uleb128 0x13 + 1157 0154 2F .uleb128 0x2f + 1158 0155 0B .uleb128 0xb + 1159 0156 00 .byte 0 + 1160 0157 00 .byte 0 + 1161 0158 15 .uleb128 0x15 + 1162 0159 34 .uleb128 0x34 + 1163 015a 00 .byte 0 + 1164 015b 03 .uleb128 0x3 + 1165 015c 0E .uleb128 0xe + 1166 015d 3A .uleb128 0x3a + 1167 015e 0B .uleb128 0xb + 1168 015f 3B .uleb128 0x3b + 1169 0160 0B .uleb128 0xb + 1170 0161 49 .uleb128 0x49 + 1171 0162 13 .uleb128 0x13 + 1172 0163 3F .uleb128 0x3f + 1173 0164 19 .uleb128 0x19 + 1174 0165 3C .uleb128 0x3c + 1175 0166 19 .uleb128 0x19 + 1176 0167 00 .byte 0 + 1177 0168 00 .byte 0 + 1178 0169 00 .byte 0 + 1179 .section .debug_aranges,"",%progbits + 1180 0000 7C000000 .4byte 0x7c + 1181 0004 0200 .2byte 0x2 + 1182 0006 00000000 .4byte .Ldebug_info0 + 1183 000a 04 .byte 0x4 + 1184 000b 00 .byte 0 + 1185 000c 0000 .2byte 0 + 1186 000e 0000 .2byte 0 + 1187 0010 00000000 .4byte .LFB0 + 1188 0014 24000000 .4byte .LFE0-.LFB0 + 1189 0018 00000000 .4byte .LFB1 + 1190 001c 26000000 .4byte .LFE1-.LFB1 + 1191 0020 00000000 .4byte .LFB2 + 1192 0024 1C000000 .4byte .LFE2-.LFB2 + 1193 0028 00000000 .4byte .LFB3 + 1194 002c 0A000000 .4byte .LFE3-.LFB3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 29 + + + 1195 0030 00000000 .4byte .LFB4 + 1196 0034 1C000000 .4byte .LFE4-.LFB4 + 1197 0038 00000000 .4byte .LFB5 + 1198 003c 14000000 .4byte .LFE5-.LFB5 + 1199 0040 00000000 .4byte .LFB6 + 1200 0044 50000000 .4byte .LFE6-.LFB6 + 1201 0048 00000000 .4byte .LFB7 + 1202 004c 2C000000 .4byte .LFE7-.LFB7 + 1203 0050 00000000 .4byte .LFB8 + 1204 0054 18000000 .4byte .LFE8-.LFB8 + 1205 0058 00000000 .4byte .LFB9 + 1206 005c 20000000 .4byte .LFE9-.LFB9 + 1207 0060 00000000 .4byte .LFB10 + 1208 0064 18000000 .4byte .LFE10-.LFB10 + 1209 0068 00000000 .4byte .LFB11 + 1210 006c 18000000 .4byte .LFE11-.LFB11 + 1211 0070 00000000 .4byte .LFB12 + 1212 0074 18000000 .4byte .LFE12-.LFB12 + 1213 0078 00000000 .4byte 0 + 1214 007c 00000000 .4byte 0 + 1215 .section .debug_ranges,"",%progbits + 1216 .Ldebug_ranges0: + 1217 0000 00000000 .4byte .LFB0 + 1218 0004 24000000 .4byte .LFE0 + 1219 0008 00000000 .4byte .LFB1 + 1220 000c 26000000 .4byte .LFE1 + 1221 0010 00000000 .4byte .LFB2 + 1222 0014 1C000000 .4byte .LFE2 + 1223 0018 00000000 .4byte .LFB3 + 1224 001c 0A000000 .4byte .LFE3 + 1225 0020 00000000 .4byte .LFB4 + 1226 0024 1C000000 .4byte .LFE4 + 1227 0028 00000000 .4byte .LFB5 + 1228 002c 14000000 .4byte .LFE5 + 1229 0030 00000000 .4byte .LFB6 + 1230 0034 50000000 .4byte .LFE6 + 1231 0038 00000000 .4byte .LFB7 + 1232 003c 2C000000 .4byte .LFE7 + 1233 0040 00000000 .4byte .LFB8 + 1234 0044 18000000 .4byte .LFE8 + 1235 0048 00000000 .4byte .LFB9 + 1236 004c 20000000 .4byte .LFE9 + 1237 0050 00000000 .4byte .LFB10 + 1238 0054 18000000 .4byte .LFE10 + 1239 0058 00000000 .4byte .LFB11 + 1240 005c 18000000 .4byte .LFE11 + 1241 0060 00000000 .4byte .LFB12 + 1242 0064 18000000 .4byte .LFE12 + 1243 0068 00000000 .4byte 0 + 1244 006c 00000000 .4byte 0 + 1245 .section .debug_line,"",%progbits + 1246 .Ldebug_line0: + 1247 0000 52010000 .section .debug_str,"MS",%progbits,1 + 1247 02004400 + 1247 00000201 + 1247 FB0E0D00 + 1247 01010101 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 30 + + + 1248 .LASF14: + 1249 0000 72656733 .ascii "reg32\000" + 1249 3200 + 1250 .LASF38: + 1251 0006 43795261 .ascii "CyRamVectors\000" + 1251 6D566563 + 1251 746F7273 + 1251 00 + 1252 .LASF19: + 1253 0013 4144435F .ascii "ADC_IRQ_Stop\000" + 1253 4952515F + 1253 53746F70 + 1253 00 + 1254 .LASF20: + 1255 0020 4144435F .ascii "ADC_IRQ_Interrupt\000" + 1255 4952515F + 1255 496E7465 + 1255 72727570 + 1255 7400 + 1256 .LASF22: + 1257 0032 4144435F .ascii "ADC_IRQ_SetVector\000" + 1257 4952515F + 1257 53657456 + 1257 6563746F + 1257 7200 + 1258 .LASF3: + 1259 0044 73686F72 .ascii "short unsigned int\000" + 1259 7420756E + 1259 7369676E + 1259 65642069 + 1259 6E7400 + 1260 .LASF30: + 1261 0057 4144435F .ascii "ADC_IRQ_GetState\000" + 1261 4952515F + 1261 47657453 + 1261 74617465 + 1261 00 + 1262 .LASF29: + 1263 0068 4144435F .ascii "ADC_IRQ_GetVector\000" + 1263 4952515F + 1263 47657456 + 1263 6563746F + 1263 7200 + 1264 .LASF36: + 1265 007a 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 1265 73657273 + 1265 5C6A6167 + 1265 756D6965 + 1265 6C5C446F + 1266 00a8 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 1266 50536F43 + 1266 2D313031 + 1266 5C547261 + 1266 696E696E + 1267 .LASF11: + 1268 00d5 666C6F61 .ascii "float\000" + 1268 7400 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 31 + + + 1269 .LASF1: + 1270 00db 756E7369 .ascii "unsigned char\000" + 1270 676E6564 + 1270 20636861 + 1270 7200 + 1271 .LASF26: + 1272 00e9 696E7465 .ascii "interruptState\000" + 1272 72727570 + 1272 74537461 + 1272 746500 + 1273 .LASF5: + 1274 00f8 6C6F6E67 .ascii "long unsigned int\000" + 1274 20756E73 + 1274 69676E65 + 1274 6420696E + 1274 7400 + 1275 .LASF9: + 1276 010a 75696E74 .ascii "uint8\000" + 1276 3800 + 1277 .LASF34: + 1278 0110 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 1278 43313120 + 1278 352E342E + 1278 31203230 + 1278 31363036 + 1279 0143 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 1279 20726576 + 1279 6973696F + 1279 6E203233 + 1279 37373135 + 1280 0176 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 1280 66756E63 + 1280 74696F6E + 1280 2D736563 + 1280 74696F6E + 1281 .LASF25: + 1282 019e 7072696F .ascii "priority\000" + 1282 72697479 + 1282 00 + 1283 .LASF32: + 1284 01a7 4144435F .ascii "ADC_IRQ_SetPending\000" + 1284 4952515F + 1284 53657450 + 1284 656E6469 + 1284 6E6700 + 1285 .LASF33: + 1286 01ba 4144435F .ascii "ADC_IRQ_ClearPending\000" + 1286 4952515F + 1286 436C6561 + 1286 7250656E + 1286 64696E67 + 1287 .LASF12: + 1288 01cf 646F7562 .ascii "double\000" + 1288 6C6500 + 1289 .LASF18: + 1290 01d6 4144435F .ascii "ADC_IRQ_Start\000" + 1290 4952515F + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 32 + + + 1290 53746172 + 1290 7400 + 1291 .LASF35: + 1292 01e4 47656E65 .ascii "Generated_Source\\PSoC4\\ADC_IRQ.c\000" + 1292 72617465 + 1292 645F536F + 1292 75726365 + 1292 5C50536F + 1293 .LASF37: + 1294 0205 4144435F .ascii "ADC_IRQ_GetPriority\000" + 1294 4952515F + 1294 47657450 + 1294 72696F72 + 1294 69747900 + 1295 .LASF10: + 1296 0219 75696E74 .ascii "uint32\000" + 1296 333200 + 1297 .LASF8: + 1298 0220 756E7369 .ascii "unsigned int\000" + 1298 676E6564 + 1298 20696E74 + 1298 00 + 1299 .LASF23: + 1300 022d 61646472 .ascii "address\000" + 1300 65737300 + 1301 .LASF7: + 1302 0235 6C6F6E67 .ascii "long long unsigned int\000" + 1302 206C6F6E + 1302 6720756E + 1302 7369676E + 1302 65642069 + 1303 .LASF15: + 1304 024c 63796973 .ascii "cyisraddress\000" + 1304 72616464 + 1304 72657373 + 1304 00 + 1305 .LASF21: + 1306 0259 4144435F .ascii "ADC_IRQ_StartEx\000" + 1306 4952515F + 1306 53746172 + 1306 74457800 + 1307 .LASF17: + 1308 0269 73697A65 .ascii "sizetype\000" + 1308 74797065 + 1308 00 + 1309 .LASF6: + 1310 0272 6C6F6E67 .ascii "long long int\000" + 1310 206C6F6E + 1310 6720696E + 1310 7400 + 1311 .LASF13: + 1312 0280 63686172 .ascii "char\000" + 1312 00 + 1313 .LASF2: + 1314 0285 73686F72 .ascii "short int\000" + 1314 7420696E + 1314 7400 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdjxWQI.s page 33 + + + 1315 .LASF31: + 1316 028f 4144435F .ascii "ADC_IRQ_Disable\000" + 1316 4952515F + 1316 44697361 + 1316 626C6500 + 1317 .LASF27: + 1318 029f 7072696F .ascii "priorityOffset\000" + 1318 72697479 + 1318 4F666673 + 1318 657400 + 1319 .LASF4: + 1320 02ae 6C6F6E67 .ascii "long int\000" + 1320 20696E74 + 1320 00 + 1321 .LASF16: + 1322 02b7 6C6F6E67 .ascii "long double\000" + 1322 20646F75 + 1322 626C6500 + 1323 .LASF0: + 1324 02c3 7369676E .ascii "signed char\000" + 1324 65642063 + 1324 68617200 + 1325 .LASF24: + 1326 02cf 4144435F .ascii "ADC_IRQ_SetPriority\000" + 1326 4952515F + 1326 53657450 + 1326 72696F72 + 1326 69747900 + 1327 .LASF28: + 1328 02e3 4144435F .ascii "ADC_IRQ_Enable\000" + 1328 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b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_PM.lst @@ -0,0 +1,965 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "ADC_PM.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .bss + 20 .align 2 + 21 ADC_backup: + 22 0000 00000000 .space 8 + 22 00000000 + 23 .section .text.ADC_SaveConfig,"ax",%progbits + 24 .align 2 + 25 .global ADC_SaveConfig + 26 .code 16 + 27 .thumb_func + 28 .type ADC_SaveConfig, %function + 29 ADC_SaveConfig: + 30 .LFB0: + 31 .file 1 "Generated_Source\\PSoC4\\ADC_PM.c" + 1:Generated_Source\PSoC4/ADC_PM.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/ADC_PM.c **** * File Name: ADC_PM.c + 3:Generated_Source\PSoC4/ADC_PM.c **** * Version 2.50 + 4:Generated_Source\PSoC4/ADC_PM.c **** * + 5:Generated_Source\PSoC4/ADC_PM.c **** * Description: + 6:Generated_Source\PSoC4/ADC_PM.c **** * This file provides Sleep/WakeUp APIs functionality. + 7:Generated_Source\PSoC4/ADC_PM.c **** * + 8:Generated_Source\PSoC4/ADC_PM.c **** * Note: + 9:Generated_Source\PSoC4/ADC_PM.c **** * + 10:Generated_Source\PSoC4/ADC_PM.c **** ******************************************************************************** + 11:Generated_Source\PSoC4/ADC_PM.c **** * Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. + 12:Generated_Source\PSoC4/ADC_PM.c **** * You may use this file only in accordance with the license, terms, conditions, + 13:Generated_Source\PSoC4/ADC_PM.c **** * disclaimers, and limitations in the end user license agreement accompanying + 14:Generated_Source\PSoC4/ADC_PM.c **** * the software package with which this file was provided. + 15:Generated_Source\PSoC4/ADC_PM.c **** *******************************************************************************/ + 16:Generated_Source\PSoC4/ADC_PM.c **** + 17:Generated_Source\PSoC4/ADC_PM.c **** #include "ADC.h" + 18:Generated_Source\PSoC4/ADC_PM.c **** + 19:Generated_Source\PSoC4/ADC_PM.c **** + 20:Generated_Source\PSoC4/ADC_PM.c **** /*************************************** + 21:Generated_Source\PSoC4/ADC_PM.c **** * Local data allocation + 22:Generated_Source\PSoC4/ADC_PM.c **** ***************************************/ + 23:Generated_Source\PSoC4/ADC_PM.c **** + 24:Generated_Source\PSoC4/ADC_PM.c **** static ADC_BACKUP_STRUCT ADC_backup = + 25:Generated_Source\PSoC4/ADC_PM.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 2 + + + 26:Generated_Source\PSoC4/ADC_PM.c **** ADC_DISABLED, + 27:Generated_Source\PSoC4/ADC_PM.c **** 0u + 28:Generated_Source\PSoC4/ADC_PM.c **** }; + 29:Generated_Source\PSoC4/ADC_PM.c **** + 30:Generated_Source\PSoC4/ADC_PM.c **** + 31:Generated_Source\PSoC4/ADC_PM.c **** /******************************************************************************* + 32:Generated_Source\PSoC4/ADC_PM.c **** * Function Name: ADC_SaveConfig + 33:Generated_Source\PSoC4/ADC_PM.c **** ******************************************************************************** + 34:Generated_Source\PSoC4/ADC_PM.c **** * + 35:Generated_Source\PSoC4/ADC_PM.c **** * Summary: + 36:Generated_Source\PSoC4/ADC_PM.c **** * Saves the current user configuration. + 37:Generated_Source\PSoC4/ADC_PM.c **** * + 38:Generated_Source\PSoC4/ADC_PM.c **** * Parameters: + 39:Generated_Source\PSoC4/ADC_PM.c **** * None. + 40:Generated_Source\PSoC4/ADC_PM.c **** * + 41:Generated_Source\PSoC4/ADC_PM.c **** * Return: + 42:Generated_Source\PSoC4/ADC_PM.c **** * None. + 43:Generated_Source\PSoC4/ADC_PM.c **** * + 44:Generated_Source\PSoC4/ADC_PM.c **** *******************************************************************************/ + 45:Generated_Source\PSoC4/ADC_PM.c **** void ADC_SaveConfig(void) + 46:Generated_Source\PSoC4/ADC_PM.c **** { + 32 .loc 1 46 0 + 33 .cfi_startproc + 34 @ args = 0, pretend = 0, frame = 0 + 35 @ frame_needed = 1, uses_anonymous_args = 0 + 36 0000 80B5 push {r7, lr} + 37 .cfi_def_cfa_offset 8 + 38 .cfi_offset 7, -8 + 39 .cfi_offset 14, -4 + 40 0002 00AF add r7, sp, #0 + 41 .cfi_def_cfa_register 7 + 47:Generated_Source\PSoC4/ADC_PM.c **** /* All configuration registers are marked as [reset_all_retention] */ + 48:Generated_Source\PSoC4/ADC_PM.c **** } + 42 .loc 1 48 0 + 43 0004 C046 nop + 44 0006 BD46 mov sp, r7 + 45 @ sp needed + 46 0008 80BD pop {r7, pc} + 47 .cfi_endproc + 48 .LFE0: + 49 .size ADC_SaveConfig, .-ADC_SaveConfig + 50 000a C046 .section .text.ADC_RestoreConfig,"ax",%progbits + 51 .align 2 + 52 .global ADC_RestoreConfig + 53 .code 16 + 54 .thumb_func + 55 .type ADC_RestoreConfig, %function + 56 ADC_RestoreConfig: + 57 .LFB1: + 49:Generated_Source\PSoC4/ADC_PM.c **** + 50:Generated_Source\PSoC4/ADC_PM.c **** + 51:Generated_Source\PSoC4/ADC_PM.c **** /******************************************************************************* + 52:Generated_Source\PSoC4/ADC_PM.c **** * Function Name: ADC_RestoreConfig + 53:Generated_Source\PSoC4/ADC_PM.c **** ******************************************************************************** + 54:Generated_Source\PSoC4/ADC_PM.c **** * + 55:Generated_Source\PSoC4/ADC_PM.c **** * Summary: + 56:Generated_Source\PSoC4/ADC_PM.c **** * Restores the current user configuration. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 3 + + + 57:Generated_Source\PSoC4/ADC_PM.c **** * + 58:Generated_Source\PSoC4/ADC_PM.c **** * Parameters: + 59:Generated_Source\PSoC4/ADC_PM.c **** * None. + 60:Generated_Source\PSoC4/ADC_PM.c **** * + 61:Generated_Source\PSoC4/ADC_PM.c **** * Return: + 62:Generated_Source\PSoC4/ADC_PM.c **** * None. + 63:Generated_Source\PSoC4/ADC_PM.c **** * + 64:Generated_Source\PSoC4/ADC_PM.c **** *******************************************************************************/ + 65:Generated_Source\PSoC4/ADC_PM.c **** void ADC_RestoreConfig(void) + 66:Generated_Source\PSoC4/ADC_PM.c **** { + 58 .loc 1 66 0 + 59 .cfi_startproc + 60 @ args = 0, pretend = 0, frame = 0 + 61 @ frame_needed = 1, uses_anonymous_args = 0 + 62 0000 80B5 push {r7, lr} + 63 .cfi_def_cfa_offset 8 + 64 .cfi_offset 7, -8 + 65 .cfi_offset 14, -4 + 66 0002 00AF add r7, sp, #0 + 67 .cfi_def_cfa_register 7 + 67:Generated_Source\PSoC4/ADC_PM.c **** /* All configuration registers are marked as [reset_all_retention] */ + 68:Generated_Source\PSoC4/ADC_PM.c **** } + 68 .loc 1 68 0 + 69 0004 C046 nop + 70 0006 BD46 mov sp, r7 + 71 @ sp needed + 72 0008 80BD pop {r7, pc} + 73 .cfi_endproc + 74 .LFE1: + 75 .size ADC_RestoreConfig, .-ADC_RestoreConfig + 76 .section .text.ADC_Sleep,"ax",%progbits + 77 .align 2 + 78 .global ADC_Sleep + 79 .code 16 + 80 .thumb_func + 81 .type ADC_Sleep, %function + 82 ADC_Sleep: + 83 .LFB2: + 69:Generated_Source\PSoC4/ADC_PM.c **** + 70:Generated_Source\PSoC4/ADC_PM.c **** + 71:Generated_Source\PSoC4/ADC_PM.c **** /******************************************************************************* + 72:Generated_Source\PSoC4/ADC_PM.c **** * Function Name: ADC_Sleep + 73:Generated_Source\PSoC4/ADC_PM.c **** ******************************************************************************** + 74:Generated_Source\PSoC4/ADC_PM.c **** * + 75:Generated_Source\PSoC4/ADC_PM.c **** * Summary: + 76:Generated_Source\PSoC4/ADC_PM.c **** * Stops the ADC operation and saves the configuration registers and component + 77:Generated_Source\PSoC4/ADC_PM.c **** * enable state. Should be called just prior to entering sleep. + 78:Generated_Source\PSoC4/ADC_PM.c **** * + 79:Generated_Source\PSoC4/ADC_PM.c **** * Parameters: + 80:Generated_Source\PSoC4/ADC_PM.c **** * None. + 81:Generated_Source\PSoC4/ADC_PM.c **** * + 82:Generated_Source\PSoC4/ADC_PM.c **** * Return: + 83:Generated_Source\PSoC4/ADC_PM.c **** * None. + 84:Generated_Source\PSoC4/ADC_PM.c **** * + 85:Generated_Source\PSoC4/ADC_PM.c **** * Global Variables: + 86:Generated_Source\PSoC4/ADC_PM.c **** * ADC_backup - modified. + 87:Generated_Source\PSoC4/ADC_PM.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 4 + + + 88:Generated_Source\PSoC4/ADC_PM.c **** *******************************************************************************/ + 89:Generated_Source\PSoC4/ADC_PM.c **** void ADC_Sleep(void) + 90:Generated_Source\PSoC4/ADC_PM.c **** { + 84 .loc 1 90 0 + 85 .cfi_startproc + 86 @ args = 0, pretend = 0, frame = 0 + 87 @ frame_needed = 1, uses_anonymous_args = 0 + 88 0000 80B5 push {r7, lr} + 89 .cfi_def_cfa_offset 8 + 90 .cfi_offset 7, -8 + 91 .cfi_offset 14, -4 + 92 0002 00AF add r7, sp, #0 + 93 .cfi_def_cfa_register 7 + 91:Generated_Source\PSoC4/ADC_PM.c **** /* During deepsleep/ hibernate mode keep SARMUX active, i.e. do not open + 92:Generated_Source\PSoC4/ADC_PM.c **** * all switches (disconnect), to be used for ADFT + 93:Generated_Source\PSoC4/ADC_PM.c **** */ + 94:Generated_Source\PSoC4/ADC_PM.c **** ADC_backup.dftRegVal = ADC_SAR_DFT_CTRL_REG & (uint32)~ADC_ADFT_OVERRIDE; + 94 .loc 1 94 0 + 95 0004 1D4B ldr r3, .L10 + 96 0006 1B68 ldr r3, [r3] + 97 0008 5B00 lsls r3, r3, #1 + 98 000a 5A08 lsrs r2, r3, #1 + 99 000c 1C4B ldr r3, .L10+4 + 100 000e 5A60 str r2, [r3, #4] + 95:Generated_Source\PSoC4/ADC_PM.c **** ADC_SAR_DFT_CTRL_REG |= ADC_ADFT_OVERRIDE; + 101 .loc 1 95 0 + 102 0010 1A4B ldr r3, .L10 + 103 0012 1A4A ldr r2, .L10 + 104 0014 1268 ldr r2, [r2] + 105 0016 8021 movs r1, #128 + 106 0018 0906 lsls r1, r1, #24 + 107 001a 0A43 orrs r2, r1 + 108 001c 1A60 str r2, [r3] + 96:Generated_Source\PSoC4/ADC_PM.c **** if((ADC_SAR_CTRL_REG & ADC_ENABLE) != 0u) + 109 .loc 1 96 0 + 110 001e 194B ldr r3, .L10+8 + 111 0020 1B68 ldr r3, [r3] + 112 0022 002B cmp r3, #0 + 113 0024 24DA bge .L4 + 97:Generated_Source\PSoC4/ADC_PM.c **** { + 98:Generated_Source\PSoC4/ADC_PM.c **** if((ADC_SAR_SAMPLE_CTRL_REG & ADC_CONTINUOUS_EN) != 0u) + 114 .loc 1 98 0 + 115 0026 184B ldr r3, .L10+12 + 116 0028 1A68 ldr r2, [r3] + 117 002a 8023 movs r3, #128 + 118 002c 5B02 lsls r3, r3, #9 + 119 002e 1340 ands r3, r2 + 120 0030 03D0 beq .L5 + 99:Generated_Source\PSoC4/ADC_PM.c **** { + 100:Generated_Source\PSoC4/ADC_PM.c **** ADC_backup.enableState = ADC_ENABLED | ADC_STARTED; + 121 .loc 1 100 0 + 122 0032 134B ldr r3, .L10+4 + 123 0034 0322 movs r2, #3 + 124 0036 1A70 strb r2, [r3] + 125 0038 02E0 b .L6 + 126 .L5: + 101:Generated_Source\PSoC4/ADC_PM.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 5 + + + 102:Generated_Source\PSoC4/ADC_PM.c **** else + 103:Generated_Source\PSoC4/ADC_PM.c **** { + 104:Generated_Source\PSoC4/ADC_PM.c **** ADC_backup.enableState = ADC_ENABLED; + 127 .loc 1 104 0 + 128 003a 114B ldr r3, .L10+4 + 129 003c 0122 movs r2, #1 + 130 003e 1A70 strb r2, [r3] + 131 .L6: + 105:Generated_Source\PSoC4/ADC_PM.c **** } + 106:Generated_Source\PSoC4/ADC_PM.c **** ADC_StopConvert(); + 132 .loc 1 106 0 + 133 0040 FFF7FEFF bl ADC_StopConvert + 107:Generated_Source\PSoC4/ADC_PM.c **** ADC_Stop(); + 134 .loc 1 107 0 + 135 0044 FFF7FEFF bl ADC_Stop + 108:Generated_Source\PSoC4/ADC_PM.c **** + 109:Generated_Source\PSoC4/ADC_PM.c **** /* Disable the SAR internal pump before entering the chip low power mode */ + 110:Generated_Source\PSoC4/ADC_PM.c **** if((ADC_SAR_CTRL_REG & ADC_BOOSTPUMP_EN) != 0u) + 136 .loc 1 110 0 + 137 0048 0E4B ldr r3, .L10+8 + 138 004a 1A68 ldr r2, [r3] + 139 004c 8023 movs r3, #128 + 140 004e 5B03 lsls r3, r3, #13 + 141 0050 1340 ands r3, r2 + 142 0052 10D0 beq .L9 + 111:Generated_Source\PSoC4/ADC_PM.c **** { + 112:Generated_Source\PSoC4/ADC_PM.c **** ADC_SAR_CTRL_REG &= (uint32)~ADC_BOOSTPUMP_EN; + 143 .loc 1 112 0 + 144 0054 0B4B ldr r3, .L10+8 + 145 0056 0B4A ldr r2, .L10+8 + 146 0058 1268 ldr r2, [r2] + 147 005a 0C49 ldr r1, .L10+16 + 148 005c 0A40 ands r2, r1 + 149 005e 1A60 str r2, [r3] + 113:Generated_Source\PSoC4/ADC_PM.c **** ADC_backup.enableState |= ADC_BOOSTPUMP_ENABLED; + 150 .loc 1 113 0 + 151 0060 074B ldr r3, .L10+4 + 152 0062 1B78 ldrb r3, [r3] + 153 0064 0422 movs r2, #4 + 154 0066 1343 orrs r3, r2 + 155 0068 DAB2 uxtb r2, r3 + 156 006a 054B ldr r3, .L10+4 + 157 006c 1A70 strb r2, [r3] + 114:Generated_Source\PSoC4/ADC_PM.c **** } + 115:Generated_Source\PSoC4/ADC_PM.c **** } + 116:Generated_Source\PSoC4/ADC_PM.c **** else + 117:Generated_Source\PSoC4/ADC_PM.c **** { + 118:Generated_Source\PSoC4/ADC_PM.c **** ADC_backup.enableState = ADC_DISABLED; + 119:Generated_Source\PSoC4/ADC_PM.c **** } + 120:Generated_Source\PSoC4/ADC_PM.c **** } + 158 .loc 1 120 0 + 159 006e 02E0 b .L9 + 160 .L4: + 118:Generated_Source\PSoC4/ADC_PM.c **** } + 161 .loc 1 118 0 + 162 0070 034B ldr r3, .L10+4 + 163 0072 0022 movs r2, #0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 6 + + + 164 0074 1A70 strb r2, [r3] + 165 .L9: + 166 .loc 1 120 0 + 167 0076 C046 nop + 168 0078 BD46 mov sp, r7 + 169 @ sp needed + 170 007a 80BD pop {r7, pc} + 171 .L11: + 172 .align 2 + 173 .L10: + 174 007c 30001A40 .word 1075445808 + 175 0080 00000000 .word ADC_backup + 176 0084 00001A40 .word 1075445760 + 177 0088 04001A40 .word 1075445764 + 178 008c FFFFEFFF .word -1048577 + 179 .cfi_endproc + 180 .LFE2: + 181 .size ADC_Sleep, .-ADC_Sleep + 182 .section .text.ADC_Wakeup,"ax",%progbits + 183 .align 2 + 184 .global ADC_Wakeup + 185 .code 16 + 186 .thumb_func + 187 .type ADC_Wakeup, %function + 188 ADC_Wakeup: + 189 .LFB3: + 121:Generated_Source\PSoC4/ADC_PM.c **** + 122:Generated_Source\PSoC4/ADC_PM.c **** + 123:Generated_Source\PSoC4/ADC_PM.c **** /******************************************************************************* + 124:Generated_Source\PSoC4/ADC_PM.c **** * Function Name: ADC_Wakeup + 125:Generated_Source\PSoC4/ADC_PM.c **** ******************************************************************************** + 126:Generated_Source\PSoC4/ADC_PM.c **** * + 127:Generated_Source\PSoC4/ADC_PM.c **** * Summary: + 128:Generated_Source\PSoC4/ADC_PM.c **** * Restores the component enable state and configuration registers. + 129:Generated_Source\PSoC4/ADC_PM.c **** * This should be called just after awaking from sleep mode. + 130:Generated_Source\PSoC4/ADC_PM.c **** * + 131:Generated_Source\PSoC4/ADC_PM.c **** * Parameters: + 132:Generated_Source\PSoC4/ADC_PM.c **** * None. + 133:Generated_Source\PSoC4/ADC_PM.c **** * + 134:Generated_Source\PSoC4/ADC_PM.c **** * Return: + 135:Generated_Source\PSoC4/ADC_PM.c **** * None. + 136:Generated_Source\PSoC4/ADC_PM.c **** * + 137:Generated_Source\PSoC4/ADC_PM.c **** * Global Variables: + 138:Generated_Source\PSoC4/ADC_PM.c **** * ADC_backup - used. + 139:Generated_Source\PSoC4/ADC_PM.c **** * + 140:Generated_Source\PSoC4/ADC_PM.c **** *******************************************************************************/ + 141:Generated_Source\PSoC4/ADC_PM.c **** void ADC_Wakeup(void) + 142:Generated_Source\PSoC4/ADC_PM.c **** { + 190 .loc 1 142 0 + 191 .cfi_startproc + 192 @ args = 0, pretend = 0, frame = 0 + 193 @ frame_needed = 1, uses_anonymous_args = 0 + 194 0000 80B5 push {r7, lr} + 195 .cfi_def_cfa_offset 8 + 196 .cfi_offset 7, -8 + 197 .cfi_offset 14, -4 + 198 0002 00AF add r7, sp, #0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 7 + + + 199 .cfi_def_cfa_register 7 + 143:Generated_Source\PSoC4/ADC_PM.c **** ADC_SAR_DFT_CTRL_REG = ADC_backup.dftRegVal; + 200 .loc 1 143 0 + 201 0004 104A ldr r2, .L16 + 202 0006 114B ldr r3, .L16+4 + 203 0008 5B68 ldr r3, [r3, #4] + 204 000a 1360 str r3, [r2] + 144:Generated_Source\PSoC4/ADC_PM.c **** if(ADC_backup.enableState != ADC_DISABLED) + 205 .loc 1 144 0 + 206 000c 0F4B ldr r3, .L16+4 + 207 000e 1B78 ldrb r3, [r3] + 208 0010 002B cmp r3, #0 + 209 0012 16D0 beq .L15 + 145:Generated_Source\PSoC4/ADC_PM.c **** { + 146:Generated_Source\PSoC4/ADC_PM.c **** /* Enable the SAR internal pump */ + 147:Generated_Source\PSoC4/ADC_PM.c **** if((ADC_backup.enableState & ADC_BOOSTPUMP_ENABLED) != 0u) + 210 .loc 1 147 0 + 211 0014 0D4B ldr r3, .L16+4 + 212 0016 1B78 ldrb r3, [r3] + 213 0018 1A00 movs r2, r3 + 214 001a 0423 movs r3, #4 + 215 001c 1340 ands r3, r2 + 216 001e 06D0 beq .L14 + 148:Generated_Source\PSoC4/ADC_PM.c **** { + 149:Generated_Source\PSoC4/ADC_PM.c **** ADC_SAR_CTRL_REG |= ADC_BOOSTPUMP_EN; + 217 .loc 1 149 0 + 218 0020 0B4B ldr r3, .L16+8 + 219 0022 0B4A ldr r2, .L16+8 + 220 0024 1268 ldr r2, [r2] + 221 0026 8021 movs r1, #128 + 222 0028 4903 lsls r1, r1, #13 + 223 002a 0A43 orrs r2, r1 + 224 002c 1A60 str r2, [r3] + 225 .L14: + 150:Generated_Source\PSoC4/ADC_PM.c **** } + 151:Generated_Source\PSoC4/ADC_PM.c **** ADC_Enable(); + 226 .loc 1 151 0 + 227 002e FFF7FEFF bl ADC_Enable + 152:Generated_Source\PSoC4/ADC_PM.c **** if((ADC_backup.enableState & ADC_STARTED) != 0u) + 228 .loc 1 152 0 + 229 0032 064B ldr r3, .L16+4 + 230 0034 1B78 ldrb r3, [r3] + 231 0036 1A00 movs r2, r3 + 232 0038 0223 movs r3, #2 + 233 003a 1340 ands r3, r2 + 234 003c 01D0 beq .L15 + 153:Generated_Source\PSoC4/ADC_PM.c **** { + 154:Generated_Source\PSoC4/ADC_PM.c **** ADC_StartConvert(); + 235 .loc 1 154 0 + 236 003e FFF7FEFF bl ADC_StartConvert + 237 .L15: + 155:Generated_Source\PSoC4/ADC_PM.c **** } + 156:Generated_Source\PSoC4/ADC_PM.c **** } + 157:Generated_Source\PSoC4/ADC_PM.c **** } + 238 .loc 1 157 0 + 239 0042 C046 nop + 240 0044 BD46 mov sp, r7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 8 + + + 241 @ sp needed + 242 0046 80BD pop {r7, pc} + 243 .L17: + 244 .align 2 + 245 .L16: + 246 0048 30001A40 .word 1075445808 + 247 004c 00000000 .word ADC_backup + 248 0050 00001A40 .word 1075445760 + 249 .cfi_endproc + 250 .LFE3: + 251 .size ADC_Wakeup, .-ADC_Wakeup + 252 .text + 253 .Letext0: + 254 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 255 .file 3 "Generated_Source\\PSoC4\\ADC.h" + 256 .section .debug_info,"",%progbits + 257 .Ldebug_info0: + 258 0000 35010000 .4byte 0x135 + 259 0004 0400 .2byte 0x4 + 260 0006 00000000 .4byte .Ldebug_abbrev0 + 261 000a 04 .byte 0x4 + 262 000b 01 .uleb128 0x1 + 263 000c 99010000 .4byte .LASF24 + 264 0010 0C .byte 0xc + 265 0011 37010000 .4byte .LASF25 + 266 0015 2D000000 .4byte .LASF26 + 267 0019 00000000 .4byte .Ldebug_ranges0+0 + 268 001d 00000000 .4byte 0 + 269 0021 00000000 .4byte .Ldebug_line0 + 270 0025 02 .uleb128 0x2 + 271 0026 01 .byte 0x1 + 272 0027 06 .byte 0x6 + 273 0028 77010000 .4byte .LASF0 + 274 002c 02 .uleb128 0x2 + 275 002d 01 .byte 0x1 + 276 002e 08 .byte 0x8 + 277 002f 07010000 .4byte .LASF1 + 278 0033 02 .uleb128 0x2 + 279 0034 02 .byte 0x2 + 280 0035 05 .byte 0x5 + 281 0036 8F010000 .4byte .LASF2 + 282 003a 02 .uleb128 0x2 + 283 003b 02 .byte 0x2 + 284 003c 07 .byte 0x7 + 285 003d 64010000 .4byte .LASF3 + 286 0041 02 .uleb128 0x2 + 287 0042 04 .byte 0x4 + 288 0043 05 .byte 0x5 + 289 0044 24010000 .4byte .LASF4 + 290 0048 02 .uleb128 0x2 + 291 0049 04 .byte 0x4 + 292 004a 07 .byte 0x7 + 293 004b 9A000000 .4byte .LASF5 + 294 004f 02 .uleb128 0x2 + 295 0050 08 .byte 0x8 + 296 0051 05 .byte 0x5 + 297 0052 00000000 .4byte .LASF6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 9 + + + 298 0056 02 .uleb128 0x2 + 299 0057 08 .byte 0x8 + 300 0058 07 .byte 0x7 + 301 0059 AC000000 .4byte .LASF7 + 302 005d 03 .uleb128 0x3 + 303 005e 04 .byte 0x4 + 304 005f 05 .byte 0x5 + 305 0060 696E7400 .ascii "int\000" + 306 0064 02 .uleb128 0x2 + 307 0065 04 .byte 0x4 + 308 0066 07 .byte 0x7 + 309 0067 20000000 .4byte .LASF8 + 310 006b 04 .uleb128 0x4 + 311 006c 94000000 .4byte .LASF9 + 312 0070 02 .byte 0x2 + 313 0071 E401 .2byte 0x1e4 + 314 0073 2C000000 .4byte 0x2c + 315 0077 04 .uleb128 0x4 + 316 0078 0E000000 .4byte .LASF10 + 317 007c 02 .byte 0x2 + 318 007d E601 .2byte 0x1e6 + 319 007f 48000000 .4byte 0x48 + 320 0083 02 .uleb128 0x2 + 321 0084 04 .byte 0x4 + 322 0085 04 .byte 0x4 + 323 0086 D5000000 .4byte .LASF11 + 324 008a 02 .uleb128 0x2 + 325 008b 08 .byte 0x8 + 326 008c 04 .byte 0x4 + 327 008d 57010000 .4byte .LASF12 + 328 0091 02 .uleb128 0x2 + 329 0092 01 .byte 0x1 + 330 0093 08 .byte 0x8 + 331 0094 15010000 .4byte .LASF13 + 332 0098 04 .uleb128 0x4 + 333 0099 5E010000 .4byte .LASF14 + 334 009d 02 .byte 0x2 + 335 009e 9002 .2byte 0x290 + 336 00a0 A4000000 .4byte 0xa4 + 337 00a4 05 .uleb128 0x5 + 338 00a5 77000000 .4byte 0x77 + 339 00a9 02 .uleb128 0x2 + 340 00aa 08 .byte 0x8 + 341 00ab 04 .byte 0x4 + 342 00ac 83010000 .4byte .LASF15 + 343 00b0 02 .uleb128 0x2 + 344 00b1 04 .byte 0x4 + 345 00b2 07 .byte 0x7 + 346 00b3 27020000 .4byte .LASF16 + 347 00b7 06 .uleb128 0x6 + 348 00b8 08 .byte 0x8 + 349 00b9 03 .byte 0x3 + 350 00ba 1E .byte 0x1e + 351 00bb D8000000 .4byte 0xd8 + 352 00bf 07 .uleb128 0x7 + 353 00c0 88000000 .4byte .LASF17 + 354 00c4 03 .byte 0x3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 10 + + + 355 00c5 20 .byte 0x20 + 356 00c6 6B000000 .4byte 0x6b + 357 00ca 00 .byte 0 + 358 00cb 07 .uleb128 0x7 + 359 00cc 2D010000 .4byte .LASF18 + 360 00d0 03 .byte 0x3 + 361 00d1 21 .byte 0x21 + 362 00d2 77000000 .4byte 0x77 + 363 00d6 04 .byte 0x4 + 364 00d7 00 .byte 0 + 365 00d8 08 .uleb128 0x8 + 366 00d9 DB000000 .4byte .LASF19 + 367 00dd 03 .byte 0x3 + 368 00de 22 .byte 0x22 + 369 00df B7000000 .4byte 0xb7 + 370 00e3 09 .uleb128 0x9 + 371 00e4 F8000000 .4byte .LASF20 + 372 00e8 01 .byte 0x1 + 373 00e9 2D .byte 0x2d + 374 00ea 00000000 .4byte .LFB0 + 375 00ee 0A000000 .4byte .LFE0-.LFB0 + 376 00f2 01 .uleb128 0x1 + 377 00f3 9C .byte 0x9c + 378 00f4 09 .uleb128 0x9 + 379 00f5 C3000000 .4byte .LASF21 + 380 00f9 01 .byte 0x1 + 381 00fa 41 .byte 0x41 + 382 00fb 00000000 .4byte .LFB1 + 383 00ff 0A000000 .4byte .LFE1-.LFB1 + 384 0103 01 .uleb128 0x1 + 385 0104 9C .byte 0x9c + 386 0105 0A .uleb128 0xa + 387 0106 1A010000 .4byte .LASF22 + 388 010a 01 .byte 0x1 + 389 010b 59 .byte 0x59 + 390 010c 00000000 .4byte .LFB2 + 391 0110 90000000 .4byte .LFE2-.LFB2 + 392 0114 01 .uleb128 0x1 + 393 0115 9C .byte 0x9c + 394 0116 0A .uleb128 0xa + 395 0117 ED000000 .4byte .LASF23 + 396 011b 01 .byte 0x1 + 397 011c 8D .byte 0x8d + 398 011d 00000000 .4byte .LFB3 + 399 0121 54000000 .4byte .LFE3-.LFB3 + 400 0125 01 .uleb128 0x1 + 401 0126 9C .byte 0x9c + 402 0127 0B .uleb128 0xb + 403 0128 15000000 .4byte .LASF27 + 404 012c 01 .byte 0x1 + 405 012d 18 .byte 0x18 + 406 012e D8000000 .4byte 0xd8 + 407 0132 05 .uleb128 0x5 + 408 0133 03 .byte 0x3 + 409 0134 00000000 .4byte ADC_backup + 410 0138 00 .byte 0 + 411 .section .debug_abbrev,"",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 11 + + + 412 .Ldebug_abbrev0: + 413 0000 01 .uleb128 0x1 + 414 0001 11 .uleb128 0x11 + 415 0002 01 .byte 0x1 + 416 0003 25 .uleb128 0x25 + 417 0004 0E .uleb128 0xe + 418 0005 13 .uleb128 0x13 + 419 0006 0B .uleb128 0xb + 420 0007 03 .uleb128 0x3 + 421 0008 0E .uleb128 0xe + 422 0009 1B .uleb128 0x1b + 423 000a 0E .uleb128 0xe + 424 000b 55 .uleb128 0x55 + 425 000c 17 .uleb128 0x17 + 426 000d 11 .uleb128 0x11 + 427 000e 01 .uleb128 0x1 + 428 000f 10 .uleb128 0x10 + 429 0010 17 .uleb128 0x17 + 430 0011 00 .byte 0 + 431 0012 00 .byte 0 + 432 0013 02 .uleb128 0x2 + 433 0014 24 .uleb128 0x24 + 434 0015 00 .byte 0 + 435 0016 0B .uleb128 0xb + 436 0017 0B .uleb128 0xb + 437 0018 3E .uleb128 0x3e + 438 0019 0B .uleb128 0xb + 439 001a 03 .uleb128 0x3 + 440 001b 0E .uleb128 0xe + 441 001c 00 .byte 0 + 442 001d 00 .byte 0 + 443 001e 03 .uleb128 0x3 + 444 001f 24 .uleb128 0x24 + 445 0020 00 .byte 0 + 446 0021 0B .uleb128 0xb + 447 0022 0B .uleb128 0xb + 448 0023 3E .uleb128 0x3e + 449 0024 0B .uleb128 0xb + 450 0025 03 .uleb128 0x3 + 451 0026 08 .uleb128 0x8 + 452 0027 00 .byte 0 + 453 0028 00 .byte 0 + 454 0029 04 .uleb128 0x4 + 455 002a 16 .uleb128 0x16 + 456 002b 00 .byte 0 + 457 002c 03 .uleb128 0x3 + 458 002d 0E .uleb128 0xe + 459 002e 3A .uleb128 0x3a + 460 002f 0B .uleb128 0xb + 461 0030 3B .uleb128 0x3b + 462 0031 05 .uleb128 0x5 + 463 0032 49 .uleb128 0x49 + 464 0033 13 .uleb128 0x13 + 465 0034 00 .byte 0 + 466 0035 00 .byte 0 + 467 0036 05 .uleb128 0x5 + 468 0037 35 .uleb128 0x35 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 12 + + + 469 0038 00 .byte 0 + 470 0039 49 .uleb128 0x49 + 471 003a 13 .uleb128 0x13 + 472 003b 00 .byte 0 + 473 003c 00 .byte 0 + 474 003d 06 .uleb128 0x6 + 475 003e 13 .uleb128 0x13 + 476 003f 01 .byte 0x1 + 477 0040 0B .uleb128 0xb + 478 0041 0B .uleb128 0xb + 479 0042 3A .uleb128 0x3a + 480 0043 0B .uleb128 0xb + 481 0044 3B .uleb128 0x3b + 482 0045 0B .uleb128 0xb + 483 0046 01 .uleb128 0x1 + 484 0047 13 .uleb128 0x13 + 485 0048 00 .byte 0 + 486 0049 00 .byte 0 + 487 004a 07 .uleb128 0x7 + 488 004b 0D .uleb128 0xd + 489 004c 00 .byte 0 + 490 004d 03 .uleb128 0x3 + 491 004e 0E .uleb128 0xe + 492 004f 3A .uleb128 0x3a + 493 0050 0B .uleb128 0xb + 494 0051 3B .uleb128 0x3b + 495 0052 0B .uleb128 0xb + 496 0053 49 .uleb128 0x49 + 497 0054 13 .uleb128 0x13 + 498 0055 38 .uleb128 0x38 + 499 0056 0B .uleb128 0xb + 500 0057 00 .byte 0 + 501 0058 00 .byte 0 + 502 0059 08 .uleb128 0x8 + 503 005a 16 .uleb128 0x16 + 504 005b 00 .byte 0 + 505 005c 03 .uleb128 0x3 + 506 005d 0E .uleb128 0xe + 507 005e 3A .uleb128 0x3a + 508 005f 0B .uleb128 0xb + 509 0060 3B .uleb128 0x3b + 510 0061 0B .uleb128 0xb + 511 0062 49 .uleb128 0x49 + 512 0063 13 .uleb128 0x13 + 513 0064 00 .byte 0 + 514 0065 00 .byte 0 + 515 0066 09 .uleb128 0x9 + 516 0067 2E .uleb128 0x2e + 517 0068 00 .byte 0 + 518 0069 3F .uleb128 0x3f + 519 006a 19 .uleb128 0x19 + 520 006b 03 .uleb128 0x3 + 521 006c 0E .uleb128 0xe + 522 006d 3A .uleb128 0x3a + 523 006e 0B .uleb128 0xb + 524 006f 3B .uleb128 0x3b + 525 0070 0B .uleb128 0xb + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 13 + + + 526 0071 27 .uleb128 0x27 + 527 0072 19 .uleb128 0x19 + 528 0073 11 .uleb128 0x11 + 529 0074 01 .uleb128 0x1 + 530 0075 12 .uleb128 0x12 + 531 0076 06 .uleb128 0x6 + 532 0077 40 .uleb128 0x40 + 533 0078 18 .uleb128 0x18 + 534 0079 9742 .uleb128 0x2117 + 535 007b 19 .uleb128 0x19 + 536 007c 00 .byte 0 + 537 007d 00 .byte 0 + 538 007e 0A .uleb128 0xa + 539 007f 2E .uleb128 0x2e + 540 0080 00 .byte 0 + 541 0081 3F .uleb128 0x3f + 542 0082 19 .uleb128 0x19 + 543 0083 03 .uleb128 0x3 + 544 0084 0E .uleb128 0xe + 545 0085 3A .uleb128 0x3a + 546 0086 0B .uleb128 0xb + 547 0087 3B .uleb128 0x3b + 548 0088 0B .uleb128 0xb + 549 0089 27 .uleb128 0x27 + 550 008a 19 .uleb128 0x19 + 551 008b 11 .uleb128 0x11 + 552 008c 01 .uleb128 0x1 + 553 008d 12 .uleb128 0x12 + 554 008e 06 .uleb128 0x6 + 555 008f 40 .uleb128 0x40 + 556 0090 18 .uleb128 0x18 + 557 0091 9642 .uleb128 0x2116 + 558 0093 19 .uleb128 0x19 + 559 0094 00 .byte 0 + 560 0095 00 .byte 0 + 561 0096 0B .uleb128 0xb + 562 0097 34 .uleb128 0x34 + 563 0098 00 .byte 0 + 564 0099 03 .uleb128 0x3 + 565 009a 0E .uleb128 0xe + 566 009b 3A .uleb128 0x3a + 567 009c 0B .uleb128 0xb + 568 009d 3B .uleb128 0x3b + 569 009e 0B .uleb128 0xb + 570 009f 49 .uleb128 0x49 + 571 00a0 13 .uleb128 0x13 + 572 00a1 02 .uleb128 0x2 + 573 00a2 18 .uleb128 0x18 + 574 00a3 00 .byte 0 + 575 00a4 00 .byte 0 + 576 00a5 00 .byte 0 + 577 .section .debug_aranges,"",%progbits + 578 0000 34000000 .4byte 0x34 + 579 0004 0200 .2byte 0x2 + 580 0006 00000000 .4byte .Ldebug_info0 + 581 000a 04 .byte 0x4 + 582 000b 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 14 + + + 583 000c 0000 .2byte 0 + 584 000e 0000 .2byte 0 + 585 0010 00000000 .4byte .LFB0 + 586 0014 0A000000 .4byte .LFE0-.LFB0 + 587 0018 00000000 .4byte .LFB1 + 588 001c 0A000000 .4byte .LFE1-.LFB1 + 589 0020 00000000 .4byte .LFB2 + 590 0024 90000000 .4byte .LFE2-.LFB2 + 591 0028 00000000 .4byte .LFB3 + 592 002c 54000000 .4byte .LFE3-.LFB3 + 593 0030 00000000 .4byte 0 + 594 0034 00000000 .4byte 0 + 595 .section .debug_ranges,"",%progbits + 596 .Ldebug_ranges0: + 597 0000 00000000 .4byte .LFB0 + 598 0004 0A000000 .4byte .LFE0 + 599 0008 00000000 .4byte .LFB1 + 600 000c 0A000000 .4byte .LFE1 + 601 0010 00000000 .4byte .LFB2 + 602 0014 90000000 .4byte .LFE2 + 603 0018 00000000 .4byte .LFB3 + 604 001c 54000000 .4byte .LFE3 + 605 0020 00000000 .4byte 0 + 606 0024 00000000 .4byte 0 + 607 .section .debug_line,"",%progbits + 608 .Ldebug_line0: + 609 0000 A9000000 .section .debug_str,"MS",%progbits,1 + 609 02004C00 + 609 00000201 + 609 FB0E0D00 + 609 01010101 + 610 .LASF6: + 611 0000 6C6F6E67 .ascii "long long int\000" + 611 206C6F6E + 611 6720696E + 611 7400 + 612 .LASF10: + 613 000e 75696E74 .ascii "uint32\000" + 613 333200 + 614 .LASF27: + 615 0015 4144435F .ascii "ADC_backup\000" + 615 6261636B + 615 757000 + 616 .LASF8: + 617 0020 756E7369 .ascii "unsigned int\000" + 617 676E6564 + 617 20696E74 + 617 00 + 618 .LASF26: + 619 002d 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 619 73657273 + 619 5C6A6167 + 619 756D6965 + 619 6C5C446F + 620 005b 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 620 50536F43 + 620 2D313031 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 15 + + + 620 5C547261 + 620 696E696E + 621 .LASF17: + 622 0088 656E6162 .ascii "enableState\000" + 622 6C655374 + 622 61746500 + 623 .LASF9: + 624 0094 75696E74 .ascii "uint8\000" + 624 3800 + 625 .LASF5: + 626 009a 6C6F6E67 .ascii "long unsigned int\000" + 626 20756E73 + 626 69676E65 + 626 6420696E + 626 7400 + 627 .LASF7: + 628 00ac 6C6F6E67 .ascii "long long unsigned int\000" + 628 206C6F6E + 628 6720756E + 628 7369676E + 628 65642069 + 629 .LASF21: + 630 00c3 4144435F .ascii "ADC_RestoreConfig\000" + 630 52657374 + 630 6F726543 + 630 6F6E6669 + 630 6700 + 631 .LASF11: + 632 00d5 666C6F61 .ascii "float\000" + 632 7400 + 633 .LASF19: + 634 00db 4144435F .ascii "ADC_BACKUP_STRUCT\000" + 634 4241434B + 634 55505F53 + 634 54525543 + 634 5400 + 635 .LASF23: + 636 00ed 4144435F .ascii "ADC_Wakeup\000" + 636 57616B65 + 636 757000 + 637 .LASF20: + 638 00f8 4144435F .ascii "ADC_SaveConfig\000" + 638 53617665 + 638 436F6E66 + 638 696700 + 639 .LASF1: + 640 0107 756E7369 .ascii "unsigned char\000" + 640 676E6564 + 640 20636861 + 640 7200 + 641 .LASF13: + 642 0115 63686172 .ascii "char\000" + 642 00 + 643 .LASF22: + 644 011a 4144435F .ascii "ADC_Sleep\000" + 644 536C6565 + 644 7000 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 16 + + + 645 .LASF4: + 646 0124 6C6F6E67 .ascii "long int\000" + 646 20696E74 + 646 00 + 647 .LASF18: + 648 012d 64667452 .ascii "dftRegVal\000" + 648 65675661 + 648 6C00 + 649 .LASF25: + 650 0137 47656E65 .ascii "Generated_Source\\PSoC4\\ADC_PM.c\000" + 650 72617465 + 650 645F536F + 650 75726365 + 650 5C50536F + 651 .LASF12: + 652 0157 646F7562 .ascii "double\000" + 652 6C6500 + 653 .LASF14: + 654 015e 72656733 .ascii "reg32\000" + 654 3200 + 655 .LASF3: + 656 0164 73686F72 .ascii "short unsigned int\000" + 656 7420756E + 656 7369676E + 656 65642069 + 656 6E7400 + 657 .LASF0: + 658 0177 7369676E .ascii "signed char\000" + 658 65642063 + 658 68617200 + 659 .LASF15: + 660 0183 6C6F6E67 .ascii "long double\000" + 660 20646F75 + 660 626C6500 + 661 .LASF2: + 662 018f 73686F72 .ascii "short int\000" + 662 7420696E + 662 7400 + 663 .LASF24: + 664 0199 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 664 43313120 + 664 352E342E + 664 31203230 + 664 31363036 + 665 01cc 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 665 20726576 + 665 6973696F + 665 6E203233 + 665 37373135 + 666 01ff 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 666 66756E63 + 666 74696F6E + 666 2D736563 + 666 74696F6E + 667 .LASF16: + 668 0227 73697A65 .ascii "sizetype\000" + 668 74797065 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc66Jjhd.s page 17 + + + 668 00 + 669 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_PM.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_PM.o new file mode 100644 index 0000000000000000000000000000000000000000..7761b07fb165d92fcf7bc8110a9d715b989b26a6 GIT binary patch literal 4484 zcmbtXU2I!t8UD^W{!5&sNxU|R+m(~9(2UKl(l@dNCn^G$Ae!h)IO!`Of#n zCr*(j@k-}B@BjCHKj;1IZ=PM4Hw;5)GQ^bVNM6@#82CxKeWM8bmkiIeji+JSlhvUU`ZS$dvW-4#pO%<&} z=?(MVNYMap{qsLte1-xKE0rI31;+r65{AmNbChfzDE9*`3@}67X$Mv!8k`u zAz}&Z;2)rke+MtizJ|AmXJEG`=^PP>KhkjMmw5O63ok>?sh`~2eZL{h;Uxk^e;Sd- zSE;y#$9TK{W5R1xtVl(2FJYWRMlHM`j2NFCN+qqK{X?r`BgXI;$~`QS$> z%RXTZol1TodOn5VSwV=UjARnJqyZs57&s))r%on?NGN}Zs68vbI3dH6MrvIOn^nqeF*F4nFetxcPK&^Nqh)s`=w z$_`$S9h2phobt8KhUhfg^=i|t*fgIxb!oNjw%V7jI@Qj4-ECYtZqskenb?Jv z>-b(v3YqELbeCCaIrV0}S-sHmuDWITV`iDvxuunC`DUfv6mHWgHQZ$%izBNzDP&PQ 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zUg+^#fP4#&CY_IG5Jy(_5Zb12Y4N;G;9)KFW4&L;6CU?ZkXP_%()re*2e>!^rx;Zs&U)yp91Y>e#3skx`^=??Bc(O?$90CzTID z+irsok9$LX_Z*k^xSj|9l<63-;vDi#kx`^=>|x=2w~;Ro9rN*~)cJk~UdMnH9`gN! zj3RCOE#z>%d&p-)$9%kLb-wq(Glso`bO44N) + 20:Generated_Source\PSoC4/ADC_intClock.c **** #include "ADC_intClock.h" + 21:Generated_Source\PSoC4/ADC_intClock.c **** + 22:Generated_Source\PSoC4/ADC_intClock.c **** #if defined CYREG_PERI_DIV_CMD + 23:Generated_Source\PSoC4/ADC_intClock.c **** + 24:Generated_Source\PSoC4/ADC_intClock.c **** /******************************************************************************* + 25:Generated_Source\PSoC4/ADC_intClock.c **** * Function Name: ADC_intClock_StartEx + 26:Generated_Source\PSoC4/ADC_intClock.c **** ******************************************************************************** + 27:Generated_Source\PSoC4/ADC_intClock.c **** * + 28:Generated_Source\PSoC4/ADC_intClock.c **** * Summary: + 29:Generated_Source\PSoC4/ADC_intClock.c **** * Starts the clock, aligned to the specified running clock. + 30:Generated_Source\PSoC4/ADC_intClock.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 2 + + + 31:Generated_Source\PSoC4/ADC_intClock.c **** * Parameters: + 32:Generated_Source\PSoC4/ADC_intClock.c **** * alignClkDiv: The divider to which phase alignment is performed when the + 33:Generated_Source\PSoC4/ADC_intClock.c **** * clock is started. + 34:Generated_Source\PSoC4/ADC_intClock.c **** * + 35:Generated_Source\PSoC4/ADC_intClock.c **** * Returns: + 36:Generated_Source\PSoC4/ADC_intClock.c **** * None + 37:Generated_Source\PSoC4/ADC_intClock.c **** * + 38:Generated_Source\PSoC4/ADC_intClock.c **** *******************************************************************************/ + 39:Generated_Source\PSoC4/ADC_intClock.c **** void ADC_intClock_StartEx(uint32 alignClkDiv) + 40:Generated_Source\PSoC4/ADC_intClock.c **** { + 41:Generated_Source\PSoC4/ADC_intClock.c **** /* Make sure any previous start command has finished. */ + 42:Generated_Source\PSoC4/ADC_intClock.c **** while((ADC_intClock_CMD_REG & ADC_intClock_CMD_ENABLE_MASK) != 0u) + 43:Generated_Source\PSoC4/ADC_intClock.c **** { + 44:Generated_Source\PSoC4/ADC_intClock.c **** } + 45:Generated_Source\PSoC4/ADC_intClock.c **** + 46:Generated_Source\PSoC4/ADC_intClock.c **** /* Specify the target divider and it's alignment divider, and enable. */ + 47:Generated_Source\PSoC4/ADC_intClock.c **** ADC_intClock_CMD_REG = + 48:Generated_Source\PSoC4/ADC_intClock.c **** ((uint32)ADC_intClock__DIV_ID << ADC_intClock_CMD_DIV_SHIFT)| + 49:Generated_Source\PSoC4/ADC_intClock.c **** (alignClkDiv << ADC_intClock_CMD_PA_DIV_SHIFT) | + 50:Generated_Source\PSoC4/ADC_intClock.c **** (uint32)ADC_intClock_CMD_ENABLE_MASK; + 51:Generated_Source\PSoC4/ADC_intClock.c **** } + 52:Generated_Source\PSoC4/ADC_intClock.c **** + 53:Generated_Source\PSoC4/ADC_intClock.c **** #else + 54:Generated_Source\PSoC4/ADC_intClock.c **** + 55:Generated_Source\PSoC4/ADC_intClock.c **** /******************************************************************************* + 56:Generated_Source\PSoC4/ADC_intClock.c **** * Function Name: ADC_intClock_Start + 57:Generated_Source\PSoC4/ADC_intClock.c **** ******************************************************************************** + 58:Generated_Source\PSoC4/ADC_intClock.c **** * + 59:Generated_Source\PSoC4/ADC_intClock.c **** * Summary: + 60:Generated_Source\PSoC4/ADC_intClock.c **** * Starts the clock. + 61:Generated_Source\PSoC4/ADC_intClock.c **** * + 62:Generated_Source\PSoC4/ADC_intClock.c **** * Parameters: + 63:Generated_Source\PSoC4/ADC_intClock.c **** * None + 64:Generated_Source\PSoC4/ADC_intClock.c **** * + 65:Generated_Source\PSoC4/ADC_intClock.c **** * Returns: + 66:Generated_Source\PSoC4/ADC_intClock.c **** * None + 67:Generated_Source\PSoC4/ADC_intClock.c **** * + 68:Generated_Source\PSoC4/ADC_intClock.c **** *******************************************************************************/ + 69:Generated_Source\PSoC4/ADC_intClock.c **** + 70:Generated_Source\PSoC4/ADC_intClock.c **** void ADC_intClock_Start(void) + 71:Generated_Source\PSoC4/ADC_intClock.c **** { + 28 .loc 1 71 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 00AF add r7, sp, #0 + 37 .cfi_def_cfa_register 7 + 72:Generated_Source\PSoC4/ADC_intClock.c **** /* Set the bit to enable the clock. */ + 73:Generated_Source\PSoC4/ADC_intClock.c **** ADC_intClock_ENABLE_REG |= ADC_intClock__ENABLE_MASK; + 38 .loc 1 73 0 + 39 0004 044B ldr r3, .L2 + 40 0006 044A ldr r2, .L2 + 41 0008 1268 ldr r2, [r2] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 3 + + + 42 000a 8021 movs r1, #128 + 43 000c 0906 lsls r1, r1, #24 + 44 000e 0A43 orrs r2, r1 + 45 0010 1A60 str r2, [r3] + 74:Generated_Source\PSoC4/ADC_intClock.c **** } + 46 .loc 1 74 0 + 47 0012 C046 nop + 48 0014 BD46 mov sp, r7 + 49 @ sp needed + 50 0016 80BD pop {r7, pc} + 51 .L3: + 52 .align 2 + 53 .L2: + 54 0018 00000240 .word 1073872896 + 55 .cfi_endproc + 56 .LFE0: + 57 .size ADC_intClock_Start, .-ADC_intClock_Start + 58 .section .text.ADC_intClock_Stop,"ax",%progbits + 59 .align 2 + 60 .global ADC_intClock_Stop + 61 .code 16 + 62 .thumb_func + 63 .type ADC_intClock_Stop, %function + 64 ADC_intClock_Stop: + 65 .LFB1: + 75:Generated_Source\PSoC4/ADC_intClock.c **** + 76:Generated_Source\PSoC4/ADC_intClock.c **** #endif /* CYREG_PERI_DIV_CMD */ + 77:Generated_Source\PSoC4/ADC_intClock.c **** + 78:Generated_Source\PSoC4/ADC_intClock.c **** + 79:Generated_Source\PSoC4/ADC_intClock.c **** /******************************************************************************* + 80:Generated_Source\PSoC4/ADC_intClock.c **** * Function Name: ADC_intClock_Stop + 81:Generated_Source\PSoC4/ADC_intClock.c **** ******************************************************************************** + 82:Generated_Source\PSoC4/ADC_intClock.c **** * + 83:Generated_Source\PSoC4/ADC_intClock.c **** * Summary: + 84:Generated_Source\PSoC4/ADC_intClock.c **** * Stops the clock and returns immediately. This API does not require the + 85:Generated_Source\PSoC4/ADC_intClock.c **** * source clock to be running but may return before the hardware is actually + 86:Generated_Source\PSoC4/ADC_intClock.c **** * disabled. + 87:Generated_Source\PSoC4/ADC_intClock.c **** * + 88:Generated_Source\PSoC4/ADC_intClock.c **** * Parameters: + 89:Generated_Source\PSoC4/ADC_intClock.c **** * None + 90:Generated_Source\PSoC4/ADC_intClock.c **** * + 91:Generated_Source\PSoC4/ADC_intClock.c **** * Returns: + 92:Generated_Source\PSoC4/ADC_intClock.c **** * None + 93:Generated_Source\PSoC4/ADC_intClock.c **** * + 94:Generated_Source\PSoC4/ADC_intClock.c **** *******************************************************************************/ + 95:Generated_Source\PSoC4/ADC_intClock.c **** void ADC_intClock_Stop(void) + 96:Generated_Source\PSoC4/ADC_intClock.c **** { + 66 .loc 1 96 0 + 67 .cfi_startproc + 68 @ args = 0, pretend = 0, frame = 0 + 69 @ frame_needed = 1, uses_anonymous_args = 0 + 70 0000 80B5 push {r7, lr} + 71 .cfi_def_cfa_offset 8 + 72 .cfi_offset 7, -8 + 73 .cfi_offset 14, -4 + 74 0002 00AF add r7, sp, #0 + 75 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 4 + + + 97:Generated_Source\PSoC4/ADC_intClock.c **** #if defined CYREG_PERI_DIV_CMD + 98:Generated_Source\PSoC4/ADC_intClock.c **** + 99:Generated_Source\PSoC4/ADC_intClock.c **** /* Make sure any previous start command has finished. */ + 100:Generated_Source\PSoC4/ADC_intClock.c **** while((ADC_intClock_CMD_REG & ADC_intClock_CMD_ENABLE_MASK) != 0u) + 101:Generated_Source\PSoC4/ADC_intClock.c **** { + 102:Generated_Source\PSoC4/ADC_intClock.c **** } + 103:Generated_Source\PSoC4/ADC_intClock.c **** + 104:Generated_Source\PSoC4/ADC_intClock.c **** /* Specify the target divider and it's alignment divider, and disable. */ + 105:Generated_Source\PSoC4/ADC_intClock.c **** ADC_intClock_CMD_REG = + 106:Generated_Source\PSoC4/ADC_intClock.c **** ((uint32)ADC_intClock__DIV_ID << ADC_intClock_CMD_DIV_SHIFT)| + 107:Generated_Source\PSoC4/ADC_intClock.c **** ((uint32)ADC_intClock_CMD_DISABLE_MASK); + 108:Generated_Source\PSoC4/ADC_intClock.c **** + 109:Generated_Source\PSoC4/ADC_intClock.c **** #else + 110:Generated_Source\PSoC4/ADC_intClock.c **** + 111:Generated_Source\PSoC4/ADC_intClock.c **** /* Clear the bit to disable the clock. */ + 112:Generated_Source\PSoC4/ADC_intClock.c **** ADC_intClock_ENABLE_REG &= (uint32)(~ADC_intClock__ENABLE_MASK); + 76 .loc 1 112 0 + 77 0004 044B ldr r3, .L5 + 78 0006 044A ldr r2, .L5 + 79 0008 1268 ldr r2, [r2] + 80 000a 5200 lsls r2, r2, #1 + 81 000c 5208 lsrs r2, r2, #1 + 82 000e 1A60 str r2, [r3] + 113:Generated_Source\PSoC4/ADC_intClock.c **** + 114:Generated_Source\PSoC4/ADC_intClock.c **** #endif /* CYREG_PERI_DIV_CMD */ + 115:Generated_Source\PSoC4/ADC_intClock.c **** } + 83 .loc 1 115 0 + 84 0010 C046 nop + 85 0012 BD46 mov sp, r7 + 86 @ sp needed + 87 0014 80BD pop {r7, pc} + 88 .L6: + 89 0016 C046 .align 2 + 90 .L5: + 91 0018 00000240 .word 1073872896 + 92 .cfi_endproc + 93 .LFE1: + 94 .size ADC_intClock_Stop, .-ADC_intClock_Stop + 95 .section .text.ADC_intClock_SetFractionalDividerRegister,"ax",%progbits + 96 .align 2 + 97 .global ADC_intClock_SetFractionalDividerRegister + 98 .code 16 + 99 .thumb_func + 100 .type ADC_intClock_SetFractionalDividerRegister, %function + 101 ADC_intClock_SetFractionalDividerRegister: + 102 .LFB2: + 116:Generated_Source\PSoC4/ADC_intClock.c **** + 117:Generated_Source\PSoC4/ADC_intClock.c **** + 118:Generated_Source\PSoC4/ADC_intClock.c **** /******************************************************************************* + 119:Generated_Source\PSoC4/ADC_intClock.c **** * Function Name: ADC_intClock_SetFractionalDividerRegister + 120:Generated_Source\PSoC4/ADC_intClock.c **** ******************************************************************************** + 121:Generated_Source\PSoC4/ADC_intClock.c **** * + 122:Generated_Source\PSoC4/ADC_intClock.c **** * Summary: + 123:Generated_Source\PSoC4/ADC_intClock.c **** * Modifies the clock divider and the fractional divider. + 124:Generated_Source\PSoC4/ADC_intClock.c **** * + 125:Generated_Source\PSoC4/ADC_intClock.c **** * Parameters: + 126:Generated_Source\PSoC4/ADC_intClock.c **** * clkDivider: Divider register value (0-65535). This value is NOT the + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 5 + + + 127:Generated_Source\PSoC4/ADC_intClock.c **** * divider; the clock hardware divides by clkDivider plus one. For example, + 128:Generated_Source\PSoC4/ADC_intClock.c **** * to divide the clock by 2, this parameter should be set to 1. + 129:Generated_Source\PSoC4/ADC_intClock.c **** * fracDivider: Fractional Divider register value (0-31). + 130:Generated_Source\PSoC4/ADC_intClock.c **** * Returns: + 131:Generated_Source\PSoC4/ADC_intClock.c **** * None + 132:Generated_Source\PSoC4/ADC_intClock.c **** * + 133:Generated_Source\PSoC4/ADC_intClock.c **** *******************************************************************************/ + 134:Generated_Source\PSoC4/ADC_intClock.c **** void ADC_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) + 135:Generated_Source\PSoC4/ADC_intClock.c **** { + 103 .loc 1 135 0 + 104 .cfi_startproc + 105 @ args = 0, pretend = 0, frame = 16 + 106 @ frame_needed = 1, uses_anonymous_args = 0 + 107 0000 80B5 push {r7, lr} + 108 .cfi_def_cfa_offset 8 + 109 .cfi_offset 7, -8 + 110 .cfi_offset 14, -4 + 111 0002 84B0 sub sp, sp, #16 + 112 .cfi_def_cfa_offset 24 + 113 0004 00AF add r7, sp, #0 + 114 .cfi_def_cfa_register 7 + 115 0006 0200 movs r2, r0 + 116 0008 BB1D adds r3, r7, #6 + 117 000a 1A80 strh r2, [r3] + 118 000c 7B1D adds r3, r7, #5 + 119 000e 0A1C adds r2, r1, #0 + 120 0010 1A70 strb r2, [r3] + 136:Generated_Source\PSoC4/ADC_intClock.c **** uint32 maskVal; + 137:Generated_Source\PSoC4/ADC_intClock.c **** uint32 regVal; + 138:Generated_Source\PSoC4/ADC_intClock.c **** + 139:Generated_Source\PSoC4/ADC_intClock.c **** #if defined (ADC_intClock__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + 140:Generated_Source\PSoC4/ADC_intClock.c **** + 141:Generated_Source\PSoC4/ADC_intClock.c **** /* get all but divider bits */ + 142:Generated_Source\PSoC4/ADC_intClock.c **** maskVal = ADC_intClock_DIV_REG & + 143:Generated_Source\PSoC4/ADC_intClock.c **** (uint32)(~(uint32)(ADC_intClock_DIV_INT_MASK | ADC_intClock_DIV_FRAC_MASK)); + 144:Generated_Source\PSoC4/ADC_intClock.c **** /* combine mask and new divider vals into 32-bit value */ + 145:Generated_Source\PSoC4/ADC_intClock.c **** regVal = maskVal | + 146:Generated_Source\PSoC4/ADC_intClock.c **** ((uint32)((uint32)clkDivider << ADC_intClock_DIV_INT_SHIFT) & ADC_intClock_DIV_INT_MASK) | + 147:Generated_Source\PSoC4/ADC_intClock.c **** ((uint32)((uint32)clkFractional << ADC_intClock_DIV_FRAC_SHIFT) & ADC_intClock_DIV_FRAC_MAS + 148:Generated_Source\PSoC4/ADC_intClock.c **** + 149:Generated_Source\PSoC4/ADC_intClock.c **** #else + 150:Generated_Source\PSoC4/ADC_intClock.c **** /* get all but integer divider bits */ + 151:Generated_Source\PSoC4/ADC_intClock.c **** maskVal = ADC_intClock_DIV_REG & (uint32)(~(uint32)ADC_intClock__DIVIDER_MASK); + 121 .loc 1 151 0 + 122 0012 084B ldr r3, .L8 + 123 0014 1B68 ldr r3, [r3] + 124 0016 1B0C lsrs r3, r3, #16 + 125 0018 1B04 lsls r3, r3, #16 + 126 001a FB60 str r3, [r7, #12] + 152:Generated_Source\PSoC4/ADC_intClock.c **** /* combine mask and new divider val into 32-bit value */ + 153:Generated_Source\PSoC4/ADC_intClock.c **** regVal = clkDivider | maskVal; + 127 .loc 1 153 0 + 128 001c BB1D adds r3, r7, #6 + 129 001e 1A88 ldrh r2, [r3] + 130 0020 FB68 ldr r3, [r7, #12] + 131 0022 1343 orrs r3, r2 + 132 0024 BB60 str r3, [r7, #8] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 6 + + + 154:Generated_Source\PSoC4/ADC_intClock.c **** + 155:Generated_Source\PSoC4/ADC_intClock.c **** #endif /* ADC_intClock__FRAC_MASK || CYREG_PERI_DIV_CMD */ + 156:Generated_Source\PSoC4/ADC_intClock.c **** + 157:Generated_Source\PSoC4/ADC_intClock.c **** ADC_intClock_DIV_REG = regVal; + 133 .loc 1 157 0 + 134 0026 034B ldr r3, .L8 + 135 0028 BA68 ldr r2, [r7, #8] + 136 002a 1A60 str r2, [r3] + 158:Generated_Source\PSoC4/ADC_intClock.c **** } + 137 .loc 1 158 0 + 138 002c C046 nop + 139 002e BD46 mov sp, r7 + 140 0030 04B0 add sp, sp, #16 + 141 @ sp needed + 142 0032 80BD pop {r7, pc} + 143 .L9: + 144 .align 2 + 145 .L8: + 146 0034 00000240 .word 1073872896 + 147 .cfi_endproc + 148 .LFE2: + 149 .size ADC_intClock_SetFractionalDividerRegister, .-ADC_intClock_SetFractionalDividerRegister + 150 .section .text.ADC_intClock_GetDividerRegister,"ax",%progbits + 151 .align 2 + 152 .global ADC_intClock_GetDividerRegister + 153 .code 16 + 154 .thumb_func + 155 .type ADC_intClock_GetDividerRegister, %function + 156 ADC_intClock_GetDividerRegister: + 157 .LFB3: + 159:Generated_Source\PSoC4/ADC_intClock.c **** + 160:Generated_Source\PSoC4/ADC_intClock.c **** + 161:Generated_Source\PSoC4/ADC_intClock.c **** /******************************************************************************* + 162:Generated_Source\PSoC4/ADC_intClock.c **** * Function Name: ADC_intClock_GetDividerRegister + 163:Generated_Source\PSoC4/ADC_intClock.c **** ******************************************************************************** + 164:Generated_Source\PSoC4/ADC_intClock.c **** * + 165:Generated_Source\PSoC4/ADC_intClock.c **** * Summary: + 166:Generated_Source\PSoC4/ADC_intClock.c **** * Gets the clock divider register value. + 167:Generated_Source\PSoC4/ADC_intClock.c **** * + 168:Generated_Source\PSoC4/ADC_intClock.c **** * Parameters: + 169:Generated_Source\PSoC4/ADC_intClock.c **** * None + 170:Generated_Source\PSoC4/ADC_intClock.c **** * + 171:Generated_Source\PSoC4/ADC_intClock.c **** * Returns: + 172:Generated_Source\PSoC4/ADC_intClock.c **** * Divide value of the clock minus 1. For example, if the clock is set to + 173:Generated_Source\PSoC4/ADC_intClock.c **** * divide by 2, the return value will be 1. + 174:Generated_Source\PSoC4/ADC_intClock.c **** * + 175:Generated_Source\PSoC4/ADC_intClock.c **** *******************************************************************************/ + 176:Generated_Source\PSoC4/ADC_intClock.c **** uint16 ADC_intClock_GetDividerRegister(void) + 177:Generated_Source\PSoC4/ADC_intClock.c **** { + 158 .loc 1 177 0 + 159 .cfi_startproc + 160 @ args = 0, pretend = 0, frame = 0 + 161 @ frame_needed = 1, uses_anonymous_args = 0 + 162 0000 80B5 push {r7, lr} + 163 .cfi_def_cfa_offset 8 + 164 .cfi_offset 7, -8 + 165 .cfi_offset 14, -4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 7 + + + 166 0002 00AF add r7, sp, #0 + 167 .cfi_def_cfa_register 7 + 178:Generated_Source\PSoC4/ADC_intClock.c **** return (uint16)((ADC_intClock_DIV_REG & ADC_intClock_DIV_INT_MASK) + 168 .loc 1 178 0 + 169 0004 024B ldr r3, .L12 + 170 0006 1B68 ldr r3, [r3] + 171 0008 9BB2 uxth r3, r3 + 179:Generated_Source\PSoC4/ADC_intClock.c **** >> ADC_intClock_DIV_INT_SHIFT); + 180:Generated_Source\PSoC4/ADC_intClock.c **** } + 172 .loc 1 180 0 + 173 000a 1800 movs r0, r3 + 174 000c BD46 mov sp, r7 + 175 @ sp needed + 176 000e 80BD pop {r7, pc} + 177 .L13: + 178 .align 2 + 179 .L12: + 180 0010 00000240 .word 1073872896 + 181 .cfi_endproc + 182 .LFE3: + 183 .size ADC_intClock_GetDividerRegister, .-ADC_intClock_GetDividerRegister + 184 .section .text.ADC_intClock_GetFractionalDividerRegister,"ax",%progbits + 185 .align 2 + 186 .global ADC_intClock_GetFractionalDividerRegister + 187 .code 16 + 188 .thumb_func + 189 .type ADC_intClock_GetFractionalDividerRegister, %function + 190 ADC_intClock_GetFractionalDividerRegister: + 191 .LFB4: + 181:Generated_Source\PSoC4/ADC_intClock.c **** + 182:Generated_Source\PSoC4/ADC_intClock.c **** + 183:Generated_Source\PSoC4/ADC_intClock.c **** /******************************************************************************* + 184:Generated_Source\PSoC4/ADC_intClock.c **** * Function Name: ADC_intClock_GetFractionalDividerRegister + 185:Generated_Source\PSoC4/ADC_intClock.c **** ******************************************************************************** + 186:Generated_Source\PSoC4/ADC_intClock.c **** * + 187:Generated_Source\PSoC4/ADC_intClock.c **** * Summary: + 188:Generated_Source\PSoC4/ADC_intClock.c **** * Gets the clock fractional divider register value. + 189:Generated_Source\PSoC4/ADC_intClock.c **** * + 190:Generated_Source\PSoC4/ADC_intClock.c **** * Parameters: + 191:Generated_Source\PSoC4/ADC_intClock.c **** * None + 192:Generated_Source\PSoC4/ADC_intClock.c **** * + 193:Generated_Source\PSoC4/ADC_intClock.c **** * Returns: + 194:Generated_Source\PSoC4/ADC_intClock.c **** * Fractional Divide value of the clock + 195:Generated_Source\PSoC4/ADC_intClock.c **** * 0 if the fractional divider is not in use. + 196:Generated_Source\PSoC4/ADC_intClock.c **** * + 197:Generated_Source\PSoC4/ADC_intClock.c **** *******************************************************************************/ + 198:Generated_Source\PSoC4/ADC_intClock.c **** uint8 ADC_intClock_GetFractionalDividerRegister(void) + 199:Generated_Source\PSoC4/ADC_intClock.c **** { + 192 .loc 1 199 0 + 193 .cfi_startproc + 194 @ args = 0, pretend = 0, frame = 0 + 195 @ frame_needed = 1, uses_anonymous_args = 0 + 196 0000 80B5 push {r7, lr} + 197 .cfi_def_cfa_offset 8 + 198 .cfi_offset 7, -8 + 199 .cfi_offset 14, -4 + 200 0002 00AF add r7, sp, #0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 8 + + + 201 .cfi_def_cfa_register 7 + 200:Generated_Source\PSoC4/ADC_intClock.c **** #if defined (ADC_intClock__FRAC_MASK) + 201:Generated_Source\PSoC4/ADC_intClock.c **** /* return fractional divider bits */ + 202:Generated_Source\PSoC4/ADC_intClock.c **** return (uint8)((ADC_intClock_DIV_REG & ADC_intClock_DIV_FRAC_MASK) + 203:Generated_Source\PSoC4/ADC_intClock.c **** >> ADC_intClock_DIV_FRAC_SHIFT); + 204:Generated_Source\PSoC4/ADC_intClock.c **** #else + 205:Generated_Source\PSoC4/ADC_intClock.c **** return 0u; + 202 .loc 1 205 0 + 203 0004 0023 movs r3, #0 + 206:Generated_Source\PSoC4/ADC_intClock.c **** #endif /* ADC_intClock__FRAC_MASK */ + 207:Generated_Source\PSoC4/ADC_intClock.c **** } + 204 .loc 1 207 0 + 205 0006 1800 movs r0, r3 + 206 0008 BD46 mov sp, r7 + 207 @ sp needed + 208 000a 80BD pop {r7, pc} + 209 .cfi_endproc + 210 .LFE4: + 211 .size ADC_intClock_GetFractionalDividerRegister, .-ADC_intClock_GetFractionalDividerRegister + 212 .text + 213 .Letext0: + 214 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 215 .section .debug_info,"",%progbits + 216 .Ldebug_info0: + 217 0000 4C010000 .4byte 0x14c + 218 0004 0400 .2byte 0x4 + 219 0006 00000000 .4byte .Ldebug_abbrev0 + 220 000a 04 .byte 0x4 + 221 000b 01 .uleb128 0x1 + 222 000c 37010000 .4byte .LASF24 + 223 0010 0C .byte 0xc + 224 0011 5D000000 .4byte .LASF25 + 225 0015 A3000000 .4byte .LASF26 + 226 0019 00000000 .4byte .Ldebug_ranges0+0 + 227 001d 00000000 .4byte 0 + 228 0021 00000000 .4byte .Ldebug_line0 + 229 0025 02 .uleb128 0x2 + 230 0026 01 .byte 0x1 + 231 0027 06 .byte 0x6 + 232 0028 74020000 .4byte .LASF0 + 233 002c 02 .uleb128 0x2 + 234 002d 01 .byte 0x1 + 235 002e 08 .byte 0x8 + 236 002f 04010000 .4byte .LASF1 + 237 0033 02 .uleb128 0x2 + 238 0034 02 .byte 0x2 + 239 0035 05 .byte 0x5 + 240 0036 5B020000 .4byte .LASF2 + 241 003a 02 .uleb128 0x2 + 242 003b 02 .byte 0x2 + 243 003c 07 .byte 0x7 + 244 003d 24010000 .4byte .LASF3 + 245 0041 02 .uleb128 0x2 + 246 0042 04 .byte 0x4 + 247 0043 05 .byte 0x5 + 248 0044 6B020000 .4byte .LASF4 + 249 0048 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 9 + + + 250 0049 04 .byte 0x4 + 251 004a 07 .byte 0x7 + 252 004b 12010000 .4byte .LASF5 + 253 004f 02 .uleb128 0x2 + 254 0050 08 .byte 0x8 + 255 0051 05 .byte 0x5 + 256 0052 1E020000 .4byte .LASF6 + 257 0056 02 .uleb128 0x2 + 258 0057 08 .byte 0x8 + 259 0058 07 .byte 0x7 + 260 0059 07020000 .4byte .LASF7 + 261 005d 03 .uleb128 0x3 + 262 005e 04 .byte 0x4 + 263 005f 05 .byte 0x5 + 264 0060 696E7400 .ascii "int\000" + 265 0064 02 .uleb128 0x2 + 266 0065 04 .byte 0x4 + 267 0066 07 .byte 0x7 + 268 0067 FA010000 .4byte .LASF8 + 269 006b 04 .uleb128 0x4 + 270 006c 65020000 .4byte .LASF9 + 271 0070 02 .byte 0x2 + 272 0071 E401 .2byte 0x1e4 + 273 0073 2C000000 .4byte 0x2c + 274 0077 04 .uleb128 0x4 + 275 0078 EC010000 .4byte .LASF10 + 276 007c 02 .byte 0x2 + 277 007d E501 .2byte 0x1e5 + 278 007f 3A000000 .4byte 0x3a + 279 0083 04 .uleb128 0x4 + 280 0084 F3010000 .4byte .LASF11 + 281 0088 02 .byte 0x2 + 282 0089 E601 .2byte 0x1e6 + 283 008b 48000000 .4byte 0x48 + 284 008f 02 .uleb128 0x2 + 285 0090 04 .byte 0x4 + 286 0091 04 .byte 0x4 + 287 0092 FE000000 .4byte .LASF12 + 288 0096 02 .uleb128 0x2 + 289 0097 08 .byte 0x8 + 290 0098 04 .byte 0x4 + 291 0099 D0010000 .4byte .LASF13 + 292 009d 02 .uleb128 0x2 + 293 009e 01 .byte 0x1 + 294 009f 08 .byte 0x8 + 295 00a0 2C020000 .4byte .LASF14 + 296 00a4 04 .uleb128 0x4 + 297 00a5 00000000 .4byte .LASF15 + 298 00a9 02 .byte 0x2 + 299 00aa 9002 .2byte 0x290 + 300 00ac B0000000 .4byte 0xb0 + 301 00b0 05 .uleb128 0x5 + 302 00b1 83000000 .4byte 0x83 + 303 00b5 06 .uleb128 0x6 + 304 00b6 30000000 .4byte .LASF16 + 305 00ba 01 .byte 0x1 + 306 00bb 46 .byte 0x46 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 10 + + + 307 00bc 00000000 .4byte .LFB0 + 308 00c0 1C000000 .4byte .LFE0-.LFB0 + 309 00c4 01 .uleb128 0x1 + 310 00c5 9C .byte 0x9c + 311 00c6 06 .uleb128 0x6 + 312 00c7 4B000000 .4byte .LASF17 + 313 00cb 01 .byte 0x1 + 314 00cc 5F .byte 0x5f + 315 00cd 00000000 .4byte .LFB1 + 316 00d1 1C000000 .4byte .LFE1-.LFB1 + 317 00d5 01 .uleb128 0x1 + 318 00d6 9C .byte 0x9c + 319 00d7 07 .uleb128 0x7 + 320 00d8 06000000 .4byte .LASF27 + 321 00dc 01 .byte 0x1 + 322 00dd 86 .byte 0x86 + 323 00de 00000000 .4byte .LFB2 + 324 00e2 38000000 .4byte .LFE2-.LFB2 + 325 00e6 01 .uleb128 0x1 + 326 00e7 9C .byte 0x9c + 327 00e8 25010000 .4byte 0x125 + 328 00ec 08 .uleb128 0x8 + 329 00ed C5010000 .4byte .LASF18 + 330 00f1 01 .byte 0x1 + 331 00f2 86 .byte 0x86 + 332 00f3 77000000 .4byte 0x77 + 333 00f7 02 .uleb128 0x2 + 334 00f8 91 .byte 0x91 + 335 00f9 6E .sleb128 -18 + 336 00fa 08 .uleb128 0x8 + 337 00fb DE010000 .4byte .LASF19 + 338 00ff 01 .byte 0x1 + 339 0100 86 .byte 0x86 + 340 0101 6B000000 .4byte 0x6b + 341 0105 02 .uleb128 0x2 + 342 0106 91 .byte 0x91 + 343 0107 6D .sleb128 -19 + 344 0108 09 .uleb128 0x9 + 345 0109 43000000 .4byte .LASF20 + 346 010d 01 .byte 0x1 + 347 010e 88 .byte 0x88 + 348 010f 83000000 .4byte 0x83 + 349 0113 02 .uleb128 0x2 + 350 0114 91 .byte 0x91 + 351 0115 74 .sleb128 -12 + 352 0116 09 .uleb128 0x9 + 353 0117 D7010000 .4byte .LASF21 + 354 011b 01 .byte 0x1 + 355 011c 89 .byte 0x89 + 356 011d 83000000 .4byte 0x83 + 357 0121 02 .uleb128 0x2 + 358 0122 91 .byte 0x91 + 359 0123 70 .sleb128 -16 + 360 0124 00 .byte 0 + 361 0125 0A .uleb128 0xa + 362 0126 83000000 .4byte .LASF22 + 363 012a 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 11 + + + 364 012b B0 .byte 0xb0 + 365 012c 77000000 .4byte 0x77 + 366 0130 00000000 .4byte .LFB3 + 367 0134 14000000 .4byte .LFE3-.LFB3 + 368 0138 01 .uleb128 0x1 + 369 0139 9C .byte 0x9c + 370 013a 0A .uleb128 0xa + 371 013b 31020000 .4byte .LASF23 + 372 013f 01 .byte 0x1 + 373 0140 C6 .byte 0xc6 + 374 0141 6B000000 .4byte 0x6b + 375 0145 00000000 .4byte .LFB4 + 376 0149 0C000000 .4byte .LFE4-.LFB4 + 377 014d 01 .uleb128 0x1 + 378 014e 9C .byte 0x9c + 379 014f 00 .byte 0 + 380 .section .debug_abbrev,"",%progbits + 381 .Ldebug_abbrev0: + 382 0000 01 .uleb128 0x1 + 383 0001 11 .uleb128 0x11 + 384 0002 01 .byte 0x1 + 385 0003 25 .uleb128 0x25 + 386 0004 0E .uleb128 0xe + 387 0005 13 .uleb128 0x13 + 388 0006 0B .uleb128 0xb + 389 0007 03 .uleb128 0x3 + 390 0008 0E .uleb128 0xe + 391 0009 1B .uleb128 0x1b + 392 000a 0E .uleb128 0xe + 393 000b 55 .uleb128 0x55 + 394 000c 17 .uleb128 0x17 + 395 000d 11 .uleb128 0x11 + 396 000e 01 .uleb128 0x1 + 397 000f 10 .uleb128 0x10 + 398 0010 17 .uleb128 0x17 + 399 0011 00 .byte 0 + 400 0012 00 .byte 0 + 401 0013 02 .uleb128 0x2 + 402 0014 24 .uleb128 0x24 + 403 0015 00 .byte 0 + 404 0016 0B .uleb128 0xb + 405 0017 0B .uleb128 0xb + 406 0018 3E .uleb128 0x3e + 407 0019 0B .uleb128 0xb + 408 001a 03 .uleb128 0x3 + 409 001b 0E .uleb128 0xe + 410 001c 00 .byte 0 + 411 001d 00 .byte 0 + 412 001e 03 .uleb128 0x3 + 413 001f 24 .uleb128 0x24 + 414 0020 00 .byte 0 + 415 0021 0B .uleb128 0xb + 416 0022 0B .uleb128 0xb + 417 0023 3E .uleb128 0x3e + 418 0024 0B .uleb128 0xb + 419 0025 03 .uleb128 0x3 + 420 0026 08 .uleb128 0x8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 12 + + + 421 0027 00 .byte 0 + 422 0028 00 .byte 0 + 423 0029 04 .uleb128 0x4 + 424 002a 16 .uleb128 0x16 + 425 002b 00 .byte 0 + 426 002c 03 .uleb128 0x3 + 427 002d 0E .uleb128 0xe + 428 002e 3A .uleb128 0x3a + 429 002f 0B .uleb128 0xb + 430 0030 3B .uleb128 0x3b + 431 0031 05 .uleb128 0x5 + 432 0032 49 .uleb128 0x49 + 433 0033 13 .uleb128 0x13 + 434 0034 00 .byte 0 + 435 0035 00 .byte 0 + 436 0036 05 .uleb128 0x5 + 437 0037 35 .uleb128 0x35 + 438 0038 00 .byte 0 + 439 0039 49 .uleb128 0x49 + 440 003a 13 .uleb128 0x13 + 441 003b 00 .byte 0 + 442 003c 00 .byte 0 + 443 003d 06 .uleb128 0x6 + 444 003e 2E .uleb128 0x2e + 445 003f 00 .byte 0 + 446 0040 3F .uleb128 0x3f + 447 0041 19 .uleb128 0x19 + 448 0042 03 .uleb128 0x3 + 449 0043 0E .uleb128 0xe + 450 0044 3A .uleb128 0x3a + 451 0045 0B .uleb128 0xb + 452 0046 3B .uleb128 0x3b + 453 0047 0B .uleb128 0xb + 454 0048 27 .uleb128 0x27 + 455 0049 19 .uleb128 0x19 + 456 004a 11 .uleb128 0x11 + 457 004b 01 .uleb128 0x1 + 458 004c 12 .uleb128 0x12 + 459 004d 06 .uleb128 0x6 + 460 004e 40 .uleb128 0x40 + 461 004f 18 .uleb128 0x18 + 462 0050 9742 .uleb128 0x2117 + 463 0052 19 .uleb128 0x19 + 464 0053 00 .byte 0 + 465 0054 00 .byte 0 + 466 0055 07 .uleb128 0x7 + 467 0056 2E .uleb128 0x2e + 468 0057 01 .byte 0x1 + 469 0058 3F .uleb128 0x3f + 470 0059 19 .uleb128 0x19 + 471 005a 03 .uleb128 0x3 + 472 005b 0E .uleb128 0xe + 473 005c 3A .uleb128 0x3a + 474 005d 0B .uleb128 0xb + 475 005e 3B .uleb128 0x3b + 476 005f 0B .uleb128 0xb + 477 0060 27 .uleb128 0x27 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 13 + + + 478 0061 19 .uleb128 0x19 + 479 0062 11 .uleb128 0x11 + 480 0063 01 .uleb128 0x1 + 481 0064 12 .uleb128 0x12 + 482 0065 06 .uleb128 0x6 + 483 0066 40 .uleb128 0x40 + 484 0067 18 .uleb128 0x18 + 485 0068 9742 .uleb128 0x2117 + 486 006a 19 .uleb128 0x19 + 487 006b 01 .uleb128 0x1 + 488 006c 13 .uleb128 0x13 + 489 006d 00 .byte 0 + 490 006e 00 .byte 0 + 491 006f 08 .uleb128 0x8 + 492 0070 05 .uleb128 0x5 + 493 0071 00 .byte 0 + 494 0072 03 .uleb128 0x3 + 495 0073 0E .uleb128 0xe + 496 0074 3A .uleb128 0x3a + 497 0075 0B .uleb128 0xb + 498 0076 3B .uleb128 0x3b + 499 0077 0B .uleb128 0xb + 500 0078 49 .uleb128 0x49 + 501 0079 13 .uleb128 0x13 + 502 007a 02 .uleb128 0x2 + 503 007b 18 .uleb128 0x18 + 504 007c 00 .byte 0 + 505 007d 00 .byte 0 + 506 007e 09 .uleb128 0x9 + 507 007f 34 .uleb128 0x34 + 508 0080 00 .byte 0 + 509 0081 03 .uleb128 0x3 + 510 0082 0E .uleb128 0xe + 511 0083 3A .uleb128 0x3a + 512 0084 0B .uleb128 0xb + 513 0085 3B .uleb128 0x3b + 514 0086 0B .uleb128 0xb + 515 0087 49 .uleb128 0x49 + 516 0088 13 .uleb128 0x13 + 517 0089 02 .uleb128 0x2 + 518 008a 18 .uleb128 0x18 + 519 008b 00 .byte 0 + 520 008c 00 .byte 0 + 521 008d 0A .uleb128 0xa + 522 008e 2E .uleb128 0x2e + 523 008f 00 .byte 0 + 524 0090 3F .uleb128 0x3f + 525 0091 19 .uleb128 0x19 + 526 0092 03 .uleb128 0x3 + 527 0093 0E .uleb128 0xe + 528 0094 3A .uleb128 0x3a + 529 0095 0B .uleb128 0xb + 530 0096 3B .uleb128 0x3b + 531 0097 0B .uleb128 0xb + 532 0098 27 .uleb128 0x27 + 533 0099 19 .uleb128 0x19 + 534 009a 49 .uleb128 0x49 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 14 + + + 535 009b 13 .uleb128 0x13 + 536 009c 11 .uleb128 0x11 + 537 009d 01 .uleb128 0x1 + 538 009e 12 .uleb128 0x12 + 539 009f 06 .uleb128 0x6 + 540 00a0 40 .uleb128 0x40 + 541 00a1 18 .uleb128 0x18 + 542 00a2 9742 .uleb128 0x2117 + 543 00a4 19 .uleb128 0x19 + 544 00a5 00 .byte 0 + 545 00a6 00 .byte 0 + 546 00a7 00 .byte 0 + 547 .section .debug_aranges,"",%progbits + 548 0000 3C000000 .4byte 0x3c + 549 0004 0200 .2byte 0x2 + 550 0006 00000000 .4byte .Ldebug_info0 + 551 000a 04 .byte 0x4 + 552 000b 00 .byte 0 + 553 000c 0000 .2byte 0 + 554 000e 0000 .2byte 0 + 555 0010 00000000 .4byte .LFB0 + 556 0014 1C000000 .4byte .LFE0-.LFB0 + 557 0018 00000000 .4byte .LFB1 + 558 001c 1C000000 .4byte .LFE1-.LFB1 + 559 0020 00000000 .4byte .LFB2 + 560 0024 38000000 .4byte .LFE2-.LFB2 + 561 0028 00000000 .4byte .LFB3 + 562 002c 14000000 .4byte .LFE3-.LFB3 + 563 0030 00000000 .4byte .LFB4 + 564 0034 0C000000 .4byte .LFE4-.LFB4 + 565 0038 00000000 .4byte 0 + 566 003c 00000000 .4byte 0 + 567 .section .debug_ranges,"",%progbits + 568 .Ldebug_ranges0: + 569 0000 00000000 .4byte .LFB0 + 570 0004 1C000000 .4byte .LFE0 + 571 0008 00000000 .4byte .LFB1 + 572 000c 1C000000 .4byte .LFE1 + 573 0010 00000000 .4byte .LFB2 + 574 0014 38000000 .4byte .LFE2 + 575 0018 00000000 .4byte .LFB3 + 576 001c 14000000 .4byte .LFE3 + 577 0020 00000000 .4byte .LFB4 + 578 0024 0C000000 .4byte .LFE4 + 579 0028 00000000 .4byte 0 + 580 002c 00000000 .4byte 0 + 581 .section .debug_line,"",%progbits + 582 .Ldebug_line0: + 583 0000 AF000000 .section .debug_str,"MS",%progbits,1 + 583 02004900 + 583 00000201 + 583 FB0E0D00 + 583 01010101 + 584 .LASF15: + 585 0000 72656733 .ascii "reg32\000" + 585 3200 + 586 .LASF27: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 15 + + + 587 0006 4144435F .ascii "ADC_intClock_SetFractionalDividerRegister\000" + 587 696E7443 + 587 6C6F636B + 587 5F536574 + 587 46726163 + 588 .LASF16: + 589 0030 4144435F .ascii "ADC_intClock_Start\000" + 589 696E7443 + 589 6C6F636B + 589 5F537461 + 589 727400 + 590 .LASF20: + 591 0043 6D61736B .ascii "maskVal\000" + 591 56616C00 + 592 .LASF17: + 593 004b 4144435F .ascii "ADC_intClock_Stop\000" + 593 696E7443 + 593 6C6F636B + 593 5F53746F + 593 7000 + 594 .LASF25: + 595 005d 47656E65 .ascii "Generated_Source\\PSoC4\\ADC_intClock.c\000" + 595 72617465 + 595 645F536F + 595 75726365 + 595 5C50536F + 596 .LASF22: + 597 0083 4144435F .ascii "ADC_intClock_GetDividerRegister\000" + 597 696E7443 + 597 6C6F636B + 597 5F476574 + 597 44697669 + 598 .LASF26: + 599 00a3 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 599 73657273 + 599 5C6A6167 + 599 756D6965 + 599 6C5C446F + 600 00d1 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 600 50536F43 + 600 2D313031 + 600 5C547261 + 600 696E696E + 601 .LASF12: + 602 00fe 666C6F61 .ascii "float\000" + 602 7400 + 603 .LASF1: + 604 0104 756E7369 .ascii "unsigned char\000" + 604 676E6564 + 604 20636861 + 604 7200 + 605 .LASF5: + 606 0112 6C6F6E67 .ascii "long unsigned int\000" + 606 20756E73 + 606 69676E65 + 606 6420696E + 606 7400 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 16 + + + 607 .LASF3: + 608 0124 73686F72 .ascii "short unsigned int\000" + 608 7420756E + 608 7369676E + 608 65642069 + 608 6E7400 + 609 .LASF24: + 610 0137 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 610 43313120 + 610 352E342E + 610 31203230 + 610 31363036 + 611 016a 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 611 20726576 + 611 6973696F + 611 6E203233 + 611 37373135 + 612 019d 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 612 66756E63 + 612 74696F6E + 612 2D736563 + 612 74696F6E + 613 .LASF18: + 614 01c5 636C6B44 .ascii "clkDivider\000" + 614 69766964 + 614 657200 + 615 .LASF13: + 616 01d0 646F7562 .ascii "double\000" + 616 6C6500 + 617 .LASF21: + 618 01d7 72656756 .ascii "regVal\000" + 618 616C00 + 619 .LASF19: + 620 01de 636C6B46 .ascii "clkFractional\000" + 620 72616374 + 620 696F6E61 + 620 6C00 + 621 .LASF10: + 622 01ec 75696E74 .ascii "uint16\000" + 622 313600 + 623 .LASF11: + 624 01f3 75696E74 .ascii "uint32\000" + 624 333200 + 625 .LASF8: + 626 01fa 756E7369 .ascii "unsigned int\000" + 626 676E6564 + 626 20696E74 + 626 00 + 627 .LASF7: + 628 0207 6C6F6E67 .ascii "long long unsigned int\000" + 628 206C6F6E + 628 6720756E + 628 7369676E + 628 65642069 + 629 .LASF6: + 630 021e 6C6F6E67 .ascii "long long int\000" + 630 206C6F6E + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccqDbiaB.s page 17 + + + 630 6720696E + 630 7400 + 631 .LASF14: + 632 022c 63686172 .ascii "char\000" + 632 00 + 633 .LASF23: + 634 0231 4144435F .ascii "ADC_intClock_GetFractionalDividerRegister\000" + 634 696E7443 + 634 6C6F636B + 634 5F476574 + 634 46726163 + 635 .LASF2: + 636 025b 73686F72 .ascii "short int\000" + 636 7420696E + 636 7400 + 637 .LASF9: + 638 0265 75696E74 .ascii "uint8\000" + 638 3800 + 639 .LASF4: + 640 026b 6C6F6E67 .ascii "long int\000" + 640 20696E74 + 640 00 + 641 .LASF0: + 642 0274 7369676E .ascii "signed char\000" + 642 65642063 + 642 68617200 + 643 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_intClock.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/ADC_intClock.o new file mode 100644 index 0000000000000000000000000000000000000000..627d2eb16d12ee202cd0cd0c8d4b5d0447336edd GIT binary patch literal 4616 zcmbtXU2GiH6+U-n|NIjxSsU!w1Wl*`r^;@2gX5$Lp?24C8j?U{CrBkm&g|}Zck%9y zH8V?zid0LbX(~|!Ri&zG9+03?-(t0DRTYqU2;m8dxAqAhpzTZhQ1ODAs`NW|@Ab|M zON!KE&3^Zs`<-*oJ#&A?-#>M3NeDq&1kF%SBl>KY>`Bf_n4w7;r>)=7&BWQn;$Vp|5rIb4WNL^Gk@MXb(RF<#lQ3{TLz@ z7|23o5}+7H@-k~idYZLFa)Y%*I?Gxnc|U8JbQ)kLl8tu2eg8sV!r`7z#6bj3{GG{v z5y!dxDYySBzKyn#Nc@K(llXv*B6AQvGC$)LV;eomAK)idz>h#(i0;r}gPtU16ayXL3+KLk_d3GgexNW<+ z*m$l{b-ZP#*6;(zi!lS+3#euL8&BEIc$d3L{U^N|n{!xQJM9GVAs3IYUh*B!UwziD zby^Llxw`09IxVLi__B&t$#d+$^`w$37K**bMbB=u8|~T!&wbXZfRC|qmll>U<||jL zew)^tt{qUP?Kf&|r)pK|wnt63U9)yfytVzh>jhEM=_f8(rDD-KlAp~Nt;2=lTw$*8 z4Qs}8nvU%|2dv8r%jXX{t+G?CI@R2fT-meRmAd6Q&oz7$);j#i(WAv9&se!uWwUd# zf&rZ8bFBjOpx$Yftz6B@JqdMvz0;PjBIjcQ@buYc2f1e8=G?NJ6;+xWs%TVoJLRTB zc&+?O(9wI9)WKwma}w~*BU6-<{^HDgX0C%QPyB85;>X`xw`}al10U-amep{z>2#@d z+?wHfUUc22Z>_tYh1yxCRP8LhyNcucuIC^4zsrry$ouOp017$~ek1vd5 z=6__&zbqDZrSI0K&jWVmGoj}p?6P6Z8TvCi;1&ych~?O zXL4wMy|a~RCM9G1WQ?DTL^CNB3j)__&usV$wiJ zk%Gab-$HDX*_kwNxpdB3Oh_Zdlj>oqc z5ocQAQ;djHXN3O?jPR3n0{;!glkp~1Jn&^c&}Wt3IY#Igl)tP$^i9?g=ep{DiIL}# z_pi1By9^AxF4lDm_h&%)svX#rFZ({_*^rMcy6zh9+kutd&wjU6+K1m~)%Rz8`P$Fp z3nE{2%AFcM3)fxDNVe^A8J`Xm>b3DfQFAcQp2HU{%|_eNAy6pFSKJnVIEB5|J-Y=G z?%cc`1YV=u2@v)x%M_ScmU2z96TjQA=-XvKjLg%wOPt4jEDz(slKP*#gW$x+4d2PU z)>%&B3G;ZZ_2cosgkc`9#bbE1=y*SYA + 16:Generated_Source\PSoC4/Cm0Start.c **** #include "cydevice_trm.h" + 17:Generated_Source\PSoC4/Cm0Start.c **** #include "cytypes.h" + 18:Generated_Source\PSoC4/Cm0Start.c **** #include "cyfitter_cfg.h" + 19:Generated_Source\PSoC4/Cm0Start.c **** #include "CyLib.h" + 20:Generated_Source\PSoC4/Cm0Start.c **** #include "cyfitter.h" + 21:Generated_Source\PSoC4/Cm0Start.c **** #include "cyapicallbacks.h" + 22:Generated_Source\PSoC4/Cm0Start.c **** + 23:Generated_Source\PSoC4/Cm0Start.c **** #define CY_NUM_VECTORS (CY_INT_IRQ_BASE + CY_NUM_INTERRUPTS) + 24:Generated_Source\PSoC4/Cm0Start.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 2 + + + 25:Generated_Source\PSoC4/Cm0Start.c **** #if (CY_IP_CPUSS_CM0) + 26:Generated_Source\PSoC4/Cm0Start.c **** #define CY_CPUSS_CONFIG_VECT_IN_RAM (( uint32 ) 0x01) + 27:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_CPUSS_CM0) */ + 28:Generated_Source\PSoC4/Cm0Start.c **** + 29:Generated_Source\PSoC4/Cm0Start.c **** + 30:Generated_Source\PSoC4/Cm0Start.c **** #if (CY_IP_CPUSS_CM0) + 31:Generated_Source\PSoC4/Cm0Start.c **** /* CPUSS Configuration register */ + 32:Generated_Source\PSoC4/Cm0Start.c **** #define CY_CPUSS_CONFIG_REG (*(reg32 *) CYREG_CPUSS_CONFIG) + 33:Generated_Source\PSoC4/Cm0Start.c **** #define CY_CPUSS_CONFIG_PTR ( (reg32 *) CYREG_CPUSS_CONFIG) + 34:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_CPUSS_CM0) */ + 35:Generated_Source\PSoC4/Cm0Start.c **** + 36:Generated_Source\PSoC4/Cm0Start.c **** + 37:Generated_Source\PSoC4/Cm0Start.c **** #if defined (__ICCARM__) + 38:Generated_Source\PSoC4/Cm0Start.c **** #define CY_NUM_ROM_VECTORS (CY_NUM_VECTORS) + 39:Generated_Source\PSoC4/Cm0Start.c **** #else + 40:Generated_Source\PSoC4/Cm0Start.c **** #define CY_NUM_ROM_VECTORS (4u) + 41:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined (__ICCARM__) */ + 42:Generated_Source\PSoC4/Cm0Start.c **** + 43:Generated_Source\PSoC4/Cm0Start.c **** /* Vector table address in SRAM */ + 44:Generated_Source\PSoC4/Cm0Start.c **** #define CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM (0x20000000u) + 45:Generated_Source\PSoC4/Cm0Start.c **** + 46:Generated_Source\PSoC4/Cm0Start.c **** #ifndef CY_SYS_INITIAL_STACK_POINTER + 47:Generated_Source\PSoC4/Cm0Start.c **** + 48:Generated_Source\PSoC4/Cm0Start.c **** #if defined(__ARMCC_VERSION) + 49:Generated_Source\PSoC4/Cm0Start.c **** #define CY_SYS_INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limi + 50:Generated_Source\PSoC4/Cm0Start.c **** #elif defined (__GNUC__) + 51:Generated_Source\PSoC4/Cm0Start.c **** #define CY_SYS_INITIAL_STACK_POINTER (&__cy_stack) + 52:Generated_Source\PSoC4/Cm0Start.c **** #elif defined (__ICCARM__) + 53:Generated_Source\PSoC4/Cm0Start.c **** #pragma language=extended + 54:Generated_Source\PSoC4/Cm0Start.c **** #pragma segment="CSTACK" + 55:Generated_Source\PSoC4/Cm0Start.c **** #define CY_SYS_INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + 56:Generated_Source\PSoC4/Cm0Start.c **** + 57:Generated_Source\PSoC4/Cm0Start.c **** extern void __iar_program_start( void ); + 58:Generated_Source\PSoC4/Cm0Start.c **** extern void __iar_data_init3 (void); + 59:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (__ARMCC_VERSION) */ + 60:Generated_Source\PSoC4/Cm0Start.c **** + 61:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CY_SYS_INITIAL_STACK_POINTER */ + 62:Generated_Source\PSoC4/Cm0Start.c **** + 63:Generated_Source\PSoC4/Cm0Start.c **** + 64:Generated_Source\PSoC4/Cm0Start.c **** #if defined(__GNUC__) + 65:Generated_Source\PSoC4/Cm0Start.c **** #include + 66:Generated_Source\PSoC4/Cm0Start.c **** extern int end; + 67:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined(__GNUC__) */ + 68:Generated_Source\PSoC4/Cm0Start.c **** + 69:Generated_Source\PSoC4/Cm0Start.c **** /* Extern functions */ + 70:Generated_Source\PSoC4/Cm0Start.c **** extern void CyBtldr_CheckLaunch(void); + 71:Generated_Source\PSoC4/Cm0Start.c **** + 72:Generated_Source\PSoC4/Cm0Start.c **** /* Function prototypes */ + 73:Generated_Source\PSoC4/Cm0Start.c **** void initialize_psoc(void); + 74:Generated_Source\PSoC4/Cm0Start.c **** + 75:Generated_Source\PSoC4/Cm0Start.c **** /* Global variables */ + 76:Generated_Source\PSoC4/Cm0Start.c **** #if !defined (__ICCARM__) + 77:Generated_Source\PSoC4/Cm0Start.c **** CY_NOINIT static uint32 cySysNoInitDataValid; + 78:Generated_Source\PSoC4/Cm0Start.c **** #endif /* !defined (__ICCARM__) */ + 79:Generated_Source\PSoC4/Cm0Start.c **** + 80:Generated_Source\PSoC4/Cm0Start.c **** + 81:Generated_Source\PSoC4/Cm0Start.c **** #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 3 + + + 82:Generated_Source\PSoC4/Cm0Start.c **** + 83:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 84:Generated_Source\PSoC4/Cm0Start.c **** This variable is used by the Bootloader/Bootloadable components to schedule + 85:Generated_Source\PSoC4/Cm0Start.c **** what application will be started after a software reset. + 86:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 87:Generated_Source\PSoC4/Cm0Start.c **** #if (__ARMCC_VERSION) + 88:Generated_Source\PSoC4/Cm0Start.c **** __attribute__ ((section(".bootloaderruntype"), zero_init)) + 89:Generated_Source\PSoC4/Cm0Start.c **** #elif defined (__GNUC__) + 90:Generated_Source\PSoC4/Cm0Start.c **** __attribute__ ((section(".bootloaderruntype"))) + 91:Generated_Source\PSoC4/Cm0Start.c **** #elif defined (__ICCARM__) + 92:Generated_Source\PSoC4/Cm0Start.c **** #pragma location=".bootloaderruntype" + 93:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (__ARMCC_VERSION) */ + 94:Generated_Source\PSoC4/Cm0Start.c **** volatile uint32 cyBtldrRunType; + 95:Generated_Source\PSoC4/Cm0Start.c **** + 96:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + 97:Generated_Source\PSoC4/Cm0Start.c **** + 98:Generated_Source\PSoC4/Cm0Start.c **** + 99:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 100:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: IntDefaultHandler + 101:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 102:Generated_Source\PSoC4/Cm0Start.c **** * + 103:Generated_Source\PSoC4/Cm0Start.c **** * This function is called for all interrupts, other than a reset that is called + 104:Generated_Source\PSoC4/Cm0Start.c **** * before the system is setup. + 105:Generated_Source\PSoC4/Cm0Start.c **** * + 106:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 107:Generated_Source\PSoC4/Cm0Start.c **** CY_NORETURN + 108:Generated_Source\PSoC4/Cm0Start.c **** CY_ISR(IntDefaultHandler) + 109:Generated_Source\PSoC4/Cm0Start.c **** { + 34 .loc 1 109 0 + 35 .cfi_startproc + 36 @ args = 0, pretend = 0, frame = 0 + 37 @ frame_needed = 1, uses_anonymous_args = 0 + 38 0000 80B5 push {r7, lr} + 39 .cfi_def_cfa_offset 8 + 40 .cfi_offset 7, -8 + 41 .cfi_offset 14, -4 + 42 0002 00AF add r7, sp, #0 + 43 .cfi_def_cfa_register 7 + 110:Generated_Source\PSoC4/Cm0Start.c **** /*************************************************************************** + 111:Generated_Source\PSoC4/Cm0Start.c **** * We must not get here. If we do, a serious problem occurs, so go into + 112:Generated_Source\PSoC4/Cm0Start.c **** * an infinite loop. + 113:Generated_Source\PSoC4/Cm0Start.c **** ***************************************************************************/ + 114:Generated_Source\PSoC4/Cm0Start.c **** + 115:Generated_Source\PSoC4/Cm0Start.c **** #if defined(__GNUC__) + 116:Generated_Source\PSoC4/Cm0Start.c **** if (errno == ENOMEM) + 44 .loc 1 116 0 + 45 0004 FFF7FEFF bl __errno + 46 0008 0300 movs r3, r0 + 47 000a 1B68 ldr r3, [r3] + 48 000c 0C2B cmp r3, #12 + 49 000e 00D1 bne .L2 + 50 .L3: + 117:Generated_Source\PSoC4/Cm0Start.c **** { + 118:Generated_Source\PSoC4/Cm0Start.c **** #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK + 119:Generated_Source\PSoC4/Cm0Start.c **** CyBoot_IntDefaultHandler_Enomem_Exception_Callback(); + 120:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */ + 121:Generated_Source\PSoC4/Cm0Start.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 4 + + + 122:Generated_Source\PSoC4/Cm0Start.c **** while(1) + 123:Generated_Source\PSoC4/Cm0Start.c **** { + 124:Generated_Source\PSoC4/Cm0Start.c **** /* Out Of Heap Space + 125:Generated_Source\PSoC4/Cm0Start.c **** * This can be increased in the System tab of the Design Wide Resources. + 126:Generated_Source\PSoC4/Cm0Start.c **** */ + 127:Generated_Source\PSoC4/Cm0Start.c **** } + 51 .loc 1 127 0 discriminator 1 + 52 0010 FEE7 b .L3 + 53 .L2: + 128:Generated_Source\PSoC4/Cm0Start.c **** } + 129:Generated_Source\PSoC4/Cm0Start.c **** else + 130:Generated_Source\PSoC4/Cm0Start.c **** #endif + 131:Generated_Source\PSoC4/Cm0Start.c **** { + 132:Generated_Source\PSoC4/Cm0Start.c **** #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + 133:Generated_Source\PSoC4/Cm0Start.c **** CyBoot_IntDefaultHandler_Exception_EntryCallback(); + 134:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + 135:Generated_Source\PSoC4/Cm0Start.c **** + 136:Generated_Source\PSoC4/Cm0Start.c **** while(1) + 137:Generated_Source\PSoC4/Cm0Start.c **** { + 138:Generated_Source\PSoC4/Cm0Start.c **** + 139:Generated_Source\PSoC4/Cm0Start.c **** } + 54 .loc 1 139 0 discriminator 2 + 55 0012 FEE7 b .L2 + 56 .cfi_endproc + 57 .LFE0: + 58 .size IntDefaultHandler, .-IntDefaultHandler + 59 .section .text._exit,"ax",%progbits + 60 .align 2 + 61 .weak _exit + 62 .code 16 + 63 .thumb_func + 64 .type _exit, %function + 65 _exit: + 66 .LFB1: + 140:Generated_Source\PSoC4/Cm0Start.c **** } + 141:Generated_Source\PSoC4/Cm0Start.c **** } + 142:Generated_Source\PSoC4/Cm0Start.c **** + 143:Generated_Source\PSoC4/Cm0Start.c **** #if defined(__ARMCC_VERSION) + 144:Generated_Source\PSoC4/Cm0Start.c **** + 145:Generated_Source\PSoC4/Cm0Start.c **** /* Local function for device reset. */ + 146:Generated_Source\PSoC4/Cm0Start.c **** extern void Reset(void); + 147:Generated_Source\PSoC4/Cm0Start.c **** + 148:Generated_Source\PSoC4/Cm0Start.c **** /* Application entry point. */ + 149:Generated_Source\PSoC4/Cm0Start.c **** extern void $Super$$main(void); + 150:Generated_Source\PSoC4/Cm0Start.c **** + 151:Generated_Source\PSoC4/Cm0Start.c **** /* Linker-generated Stack Base addresses, Two Region and One Region */ + 152:Generated_Source\PSoC4/Cm0Start.c **** extern unsigned long Image$$ARM_LIB_STACK$$ZI$$Limit; + 153:Generated_Source\PSoC4/Cm0Start.c **** + 154:Generated_Source\PSoC4/Cm0Start.c **** /* RealView C Library initialization. */ + 155:Generated_Source\PSoC4/Cm0Start.c **** extern int __main(void); + 156:Generated_Source\PSoC4/Cm0Start.c **** + 157:Generated_Source\PSoC4/Cm0Start.c **** + 158:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 159:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: Reset + 160:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 161:Generated_Source\PSoC4/Cm0Start.c **** * + 162:Generated_Source\PSoC4/Cm0Start.c **** * This function handles the reset interrupt for the MDK toolchains. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 5 + + + 163:Generated_Source\PSoC4/Cm0Start.c **** * This is the first bit of code that is executed at startup. + 164:Generated_Source\PSoC4/Cm0Start.c **** * + 165:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 166:Generated_Source\PSoC4/Cm0Start.c **** void Reset(void) + 167:Generated_Source\PSoC4/Cm0Start.c **** { + 168:Generated_Source\PSoC4/Cm0Start.c **** #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE + 169:Generated_Source\PSoC4/Cm0Start.c **** /* The bootloadable application image is started at Reset() handler + 170:Generated_Source\PSoC4/Cm0Start.c **** * as a result of a branch instruction execution from the bootloader. + 171:Generated_Source\PSoC4/Cm0Start.c **** * So, the stack pointer needs to be reset to be sure that + 172:Generated_Source\PSoC4/Cm0Start.c **** * there is no garbage in the stack. + 173:Generated_Source\PSoC4/Cm0Start.c **** */ + 174:Generated_Source\PSoC4/Cm0Start.c **** register uint32_t msp __asm("msp"); + 175:Generated_Source\PSoC4/Cm0Start.c **** msp = (uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit; + 176:Generated_Source\PSoC4/Cm0Start.c **** #endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOA + 177:Generated_Source\PSoC4/Cm0Start.c **** + 178:Generated_Source\PSoC4/Cm0Start.c **** #if(CY_IP_SRSSLT) + 179:Generated_Source\PSoC4/Cm0Start.c **** CySysWdtDisable(); + 180:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_SRSSLT) */ + 181:Generated_Source\PSoC4/Cm0Start.c **** + 182:Generated_Source\PSoC4/Cm0Start.c **** #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + 183:Generated_Source\PSoC4/Cm0Start.c **** CyBtldr_CheckLaunch(); + 184:Generated_Source\PSoC4/Cm0Start.c **** #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOAD + 185:Generated_Source\PSoC4/Cm0Start.c **** + 186:Generated_Source\PSoC4/Cm0Start.c **** __main(); + 187:Generated_Source\PSoC4/Cm0Start.c **** } + 188:Generated_Source\PSoC4/Cm0Start.c **** + 189:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 190:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: $Sub$$main + 191:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 192:Generated_Source\PSoC4/Cm0Start.c **** * + 193:Generated_Source\PSoC4/Cm0Start.c **** * This function is called immediately before the users main + 194:Generated_Source\PSoC4/Cm0Start.c **** * + 195:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 196:Generated_Source\PSoC4/Cm0Start.c **** __attribute__ ((noreturn, __noinline__)) + 197:Generated_Source\PSoC4/Cm0Start.c **** void $Sub$$main(void) + 198:Generated_Source\PSoC4/Cm0Start.c **** { + 199:Generated_Source\PSoC4/Cm0Start.c **** initialize_psoc(); + 200:Generated_Source\PSoC4/Cm0Start.c **** + 201:Generated_Source\PSoC4/Cm0Start.c **** /* Call original main */ + 202:Generated_Source\PSoC4/Cm0Start.c **** $Super$$main(); + 203:Generated_Source\PSoC4/Cm0Start.c **** + 204:Generated_Source\PSoC4/Cm0Start.c **** while (1) + 205:Generated_Source\PSoC4/Cm0Start.c **** { + 206:Generated_Source\PSoC4/Cm0Start.c **** /* If main returns it is undefined what we should do. */ + 207:Generated_Source\PSoC4/Cm0Start.c **** } + 208:Generated_Source\PSoC4/Cm0Start.c **** } + 209:Generated_Source\PSoC4/Cm0Start.c **** + 210:Generated_Source\PSoC4/Cm0Start.c **** #elif defined(__GNUC__) + 211:Generated_Source\PSoC4/Cm0Start.c **** + 212:Generated_Source\PSoC4/Cm0Start.c **** /* Stack Base address */ + 213:Generated_Source\PSoC4/Cm0Start.c **** extern void __cy_stack(void); + 214:Generated_Source\PSoC4/Cm0Start.c **** + 215:Generated_Source\PSoC4/Cm0Start.c **** /* Application entry point. */ + 216:Generated_Source\PSoC4/Cm0Start.c **** extern int main(void); + 217:Generated_Source\PSoC4/Cm0Start.c **** + 218:Generated_Source\PSoC4/Cm0Start.c **** /* The static objects constructors initializer */ + 219:Generated_Source\PSoC4/Cm0Start.c **** extern void __libc_init_array(void); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 6 + + + 220:Generated_Source\PSoC4/Cm0Start.c **** + 221:Generated_Source\PSoC4/Cm0Start.c **** typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + 222:Generated_Source\PSoC4/Cm0Start.c **** + 223:Generated_Source\PSoC4/Cm0Start.c **** struct __cy_region + 224:Generated_Source\PSoC4/Cm0Start.c **** { + 225:Generated_Source\PSoC4/Cm0Start.c **** __cy_byte_align8 *init; /* Initial contents of this region. */ + 226:Generated_Source\PSoC4/Cm0Start.c **** __cy_byte_align8 *data; /* Start address of region. */ + 227:Generated_Source\PSoC4/Cm0Start.c **** size_t init_size; /* Size of initial data. */ + 228:Generated_Source\PSoC4/Cm0Start.c **** size_t zero_size; /* Additional size to be zeroed. */ + 229:Generated_Source\PSoC4/Cm0Start.c **** }; + 230:Generated_Source\PSoC4/Cm0Start.c **** + 231:Generated_Source\PSoC4/Cm0Start.c **** extern const struct __cy_region __cy_regions[]; + 232:Generated_Source\PSoC4/Cm0Start.c **** extern const char __cy_region_num __attribute__((weak)); + 233:Generated_Source\PSoC4/Cm0Start.c **** #define __cy_region_num ((size_t)&__cy_region_num) + 234:Generated_Source\PSoC4/Cm0Start.c **** + 235:Generated_Source\PSoC4/Cm0Start.c **** + 236:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 237:Generated_Source\PSoC4/Cm0Start.c **** * System Calls of the Red Hat newlib C Library + 238:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 239:Generated_Source\PSoC4/Cm0Start.c **** + 240:Generated_Source\PSoC4/Cm0Start.c **** + 241:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 242:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: _exit + 243:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 244:Generated_Source\PSoC4/Cm0Start.c **** * + 245:Generated_Source\PSoC4/Cm0Start.c **** * Exit a program without cleaning up files. If your system doesn't provide + 246:Generated_Source\PSoC4/Cm0Start.c **** * this, it is best to avoid linking with subroutines that require it (exit, + 247:Generated_Source\PSoC4/Cm0Start.c **** * system). + 248:Generated_Source\PSoC4/Cm0Start.c **** * + 249:Generated_Source\PSoC4/Cm0Start.c **** * \param status: Status caused program exit. + 250:Generated_Source\PSoC4/Cm0Start.c **** * + 251:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 252:Generated_Source\PSoC4/Cm0Start.c **** __attribute__((weak)) + 253:Generated_Source\PSoC4/Cm0Start.c **** void _exit(int status) + 254:Generated_Source\PSoC4/Cm0Start.c **** { + 67 .loc 1 254 0 + 68 .cfi_startproc + 69 @ args = 0, pretend = 0, frame = 8 + 70 @ frame_needed = 1, uses_anonymous_args = 0 + 71 0000 80B5 push {r7, lr} + 72 .cfi_def_cfa_offset 8 + 73 .cfi_offset 7, -8 + 74 .cfi_offset 14, -4 + 75 0002 82B0 sub sp, sp, #8 + 76 .cfi_def_cfa_offset 16 + 77 0004 00AF add r7, sp, #0 + 78 .cfi_def_cfa_register 7 + 79 0006 7860 str r0, [r7, #4] + 255:Generated_Source\PSoC4/Cm0Start.c **** CyHalt((uint8) status); + 80 .loc 1 255 0 + 81 0008 7B68 ldr r3, [r7, #4] + 82 000a DBB2 uxtb r3, r3 + 83 000c 1800 movs r0, r3 + 84 000e FFF7FEFF bl CyHalt + 85 .L5: + 256:Generated_Source\PSoC4/Cm0Start.c **** + 257:Generated_Source\PSoC4/Cm0Start.c **** while(1) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 7 + + + 258:Generated_Source\PSoC4/Cm0Start.c **** { + 259:Generated_Source\PSoC4/Cm0Start.c **** + 260:Generated_Source\PSoC4/Cm0Start.c **** } + 86 .loc 1 260 0 discriminator 1 + 87 0012 FEE7 b .L5 + 88 .cfi_endproc + 89 .LFE1: + 90 .size _exit, .-_exit + 91 .section .text._sbrk,"ax",%progbits + 92 .align 2 + 93 .weak _sbrk + 94 .code 16 + 95 .thumb_func + 96 .type _sbrk, %function + 97 _sbrk: + 98 .LFB2: + 261:Generated_Source\PSoC4/Cm0Start.c **** } + 262:Generated_Source\PSoC4/Cm0Start.c **** + 263:Generated_Source\PSoC4/Cm0Start.c **** + 264:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 265:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: _sbrk + 266:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 267:Generated_Source\PSoC4/Cm0Start.c **** * + 268:Generated_Source\PSoC4/Cm0Start.c **** * Increase program data space. As malloc and related functions depend on this, + 269:Generated_Source\PSoC4/Cm0Start.c **** * it is useful to have a working implementation. The following suffices for a + 270:Generated_Source\PSoC4/Cm0Start.c **** * standalone system; it exploits the symbol end automatically defined by the + 271:Generated_Source\PSoC4/Cm0Start.c **** * GNU linker. + 272:Generated_Source\PSoC4/Cm0Start.c **** * + 273:Generated_Source\PSoC4/Cm0Start.c **** * \param nbytes: The number of bytes requested (if the parameter value is positive) + 274:Generated_Source\PSoC4/Cm0Start.c **** * from the heap or returned back to the heap (if the parameter value is + 275:Generated_Source\PSoC4/Cm0Start.c **** * negative). + 276:Generated_Source\PSoC4/Cm0Start.c **** * + 277:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 278:Generated_Source\PSoC4/Cm0Start.c **** __attribute__((weak)) + 279:Generated_Source\PSoC4/Cm0Start.c **** void * _sbrk (int nbytes) + 280:Generated_Source\PSoC4/Cm0Start.c **** { + 99 .loc 1 280 0 + 100 .cfi_startproc + 101 @ args = 0, pretend = 0, frame = 16 + 102 @ frame_needed = 1, uses_anonymous_args = 0 + 103 0000 80B5 push {r7, lr} + 104 .cfi_def_cfa_offset 8 + 105 .cfi_offset 7, -8 + 106 .cfi_offset 14, -4 + 107 0002 84B0 sub sp, sp, #16 + 108 .cfi_def_cfa_offset 24 + 109 0004 00AF add r7, sp, #0 + 110 .cfi_def_cfa_register 7 + 111 0006 7860 str r0, [r7, #4] + 281:Generated_Source\PSoC4/Cm0Start.c **** extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). + 282:Generated_Source\PSoC4/Cm0Start.c **** void * returnValue; + 283:Generated_Source\PSoC4/Cm0Start.c **** + 284:Generated_Source\PSoC4/Cm0Start.c **** /* The statically held previous end of the heap, with its initialization. */ + 285:Generated_Source\PSoC4/Cm0Start.c **** static uint8 *heapPointer = (uint8 *) &end; /* Previous end */ + 286:Generated_Source\PSoC4/Cm0Start.c **** + 287:Generated_Source\PSoC4/Cm0Start.c **** if (((heapPointer + nbytes) - (uint8 *) &end) <= CYDEV_HEAP_SIZE) + 112 .loc 1 287 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 8 + + + 113 0008 104B ldr r3, .L10 + 114 000a 1A68 ldr r2, [r3] + 115 000c 7B68 ldr r3, [r7, #4] + 116 000e D318 adds r3, r2, r3 + 117 0010 1A00 movs r2, r3 + 118 0012 0F4B ldr r3, .L10+4 + 119 0014 D21A subs r2, r2, r3 + 120 0016 8023 movs r3, #128 + 121 0018 5B00 lsls r3, r3, #1 + 122 001a 9A42 cmp r2, r3 + 123 001c 09DC bgt .L7 + 288:Generated_Source\PSoC4/Cm0Start.c **** { + 289:Generated_Source\PSoC4/Cm0Start.c **** returnValue = (void *) heapPointer; + 124 .loc 1 289 0 + 125 001e 0B4B ldr r3, .L10 + 126 0020 1B68 ldr r3, [r3] + 127 0022 FB60 str r3, [r7, #12] + 290:Generated_Source\PSoC4/Cm0Start.c **** heapPointer += nbytes; + 128 .loc 1 290 0 + 129 0024 094B ldr r3, .L10 + 130 0026 1A68 ldr r2, [r3] + 131 0028 7B68 ldr r3, [r7, #4] + 132 002a D218 adds r2, r2, r3 + 133 002c 074B ldr r3, .L10 + 134 002e 1A60 str r2, [r3] + 135 0030 07E0 b .L8 + 136 .L7: + 291:Generated_Source\PSoC4/Cm0Start.c **** } + 292:Generated_Source\PSoC4/Cm0Start.c **** else + 293:Generated_Source\PSoC4/Cm0Start.c **** { + 294:Generated_Source\PSoC4/Cm0Start.c **** errno = ENOMEM; + 137 .loc 1 294 0 + 138 0032 FFF7FEFF bl __errno + 139 0036 0300 movs r3, r0 + 140 0038 0C22 movs r2, #12 + 141 003a 1A60 str r2, [r3] + 295:Generated_Source\PSoC4/Cm0Start.c **** returnValue = (void *) -1; + 142 .loc 1 295 0 + 143 003c 0123 movs r3, #1 + 144 003e 5B42 rsbs r3, r3, #0 + 145 0040 FB60 str r3, [r7, #12] + 146 .L8: + 296:Generated_Source\PSoC4/Cm0Start.c **** } + 297:Generated_Source\PSoC4/Cm0Start.c **** + 298:Generated_Source\PSoC4/Cm0Start.c **** return (returnValue); + 147 .loc 1 298 0 + 148 0042 FB68 ldr r3, [r7, #12] + 299:Generated_Source\PSoC4/Cm0Start.c **** } + 149 .loc 1 299 0 + 150 0044 1800 movs r0, r3 + 151 0046 BD46 mov sp, r7 + 152 0048 04B0 add sp, sp, #16 + 153 @ sp needed + 154 004a 80BD pop {r7, pc} + 155 .L11: + 156 .align 2 + 157 .L10: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 9 + + + 158 004c 00000000 .word heapPointer.4844 + 159 0050 00000000 .word end + 160 .cfi_endproc + 161 .LFE2: + 162 .size _sbrk, .-_sbrk + 163 .section .text.Start_c,"ax",%progbits + 164 .align 2 + 165 .global Start_c + 166 .code 16 + 167 .thumb_func + 168 .type Start_c, %function + 169 Start_c: + 170 .LFB3: + 300:Generated_Source\PSoC4/Cm0Start.c **** + 301:Generated_Source\PSoC4/Cm0Start.c **** + 302:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 303:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: Start_c + 304:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 305:Generated_Source\PSoC4/Cm0Start.c **** * + 306:Generated_Source\PSoC4/Cm0Start.c **** * This function handles initializing the .data and .bss sections in + 307:Generated_Source\PSoC4/Cm0Start.c **** * preparation for running the standard c code. Once initialization is complete + 308:Generated_Source\PSoC4/Cm0Start.c **** * it will call main(). This function will never return. + 309:Generated_Source\PSoC4/Cm0Start.c **** * + 310:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 311:Generated_Source\PSoC4/Cm0Start.c **** void Start_c(void) __attribute__ ((noreturn, noinline)); + 312:Generated_Source\PSoC4/Cm0Start.c **** void Start_c(void) + 313:Generated_Source\PSoC4/Cm0Start.c **** { + 171 .loc 1 313 0 + 172 .cfi_startproc + 173 @ args = 0, pretend = 0, frame = 24 + 174 @ frame_needed = 1, uses_anonymous_args = 0 + 175 0000 80B5 push {r7, lr} + 176 .cfi_def_cfa_offset 8 + 177 .cfi_offset 7, -8 + 178 .cfi_offset 14, -4 + 179 0002 86B0 sub sp, sp, #24 + 180 .cfi_def_cfa_offset 32 + 181 0004 00AF add r7, sp, #0 + 182 .cfi_def_cfa_register 7 + 314:Generated_Source\PSoC4/Cm0Start.c **** #ifdef CY_BOOT_START_C_CALLBACK + 315:Generated_Source\PSoC4/Cm0Start.c **** CyBoot_Start_c_Callback(); + 316:Generated_Source\PSoC4/Cm0Start.c **** #else + 317:Generated_Source\PSoC4/Cm0Start.c **** unsigned regions = __cy_region_num; + 183 .loc 1 317 0 + 184 0006 224B ldr r3, .L20 + 185 0008 7B61 str r3, [r7, #20] + 318:Generated_Source\PSoC4/Cm0Start.c **** const struct __cy_region *rptr = __cy_regions; + 186 .loc 1 318 0 + 187 000a 224B ldr r3, .L20+4 + 188 000c 3B61 str r3, [r7, #16] + 319:Generated_Source\PSoC4/Cm0Start.c **** + 320:Generated_Source\PSoC4/Cm0Start.c **** /* Initialize memory */ + 321:Generated_Source\PSoC4/Cm0Start.c **** for (regions = __cy_region_num; regions != 0u; regions--) + 189 .loc 1 321 0 + 190 000e 204B ldr r3, .L20 + 191 0010 7B61 str r3, [r7, #20] + 192 0012 35E0 b .L13 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 10 + + + 193 .L18: + 194 .LBB2: + 322:Generated_Source\PSoC4/Cm0Start.c **** { + 323:Generated_Source\PSoC4/Cm0Start.c **** uint32 *src = (uint32 *)rptr->init; + 195 .loc 1 323 0 + 196 0014 3B69 ldr r3, [r7, #16] + 197 0016 1B68 ldr r3, [r3] + 198 0018 FB60 str r3, [r7, #12] + 324:Generated_Source\PSoC4/Cm0Start.c **** uint32 *dst = (uint32 *)rptr->data; + 199 .loc 1 324 0 + 200 001a 3B69 ldr r3, [r7, #16] + 201 001c 5B68 ldr r3, [r3, #4] + 202 001e BB60 str r3, [r7, #8] + 325:Generated_Source\PSoC4/Cm0Start.c **** unsigned limit = rptr->init_size; + 203 .loc 1 325 0 + 204 0020 3B69 ldr r3, [r7, #16] + 205 0022 9B68 ldr r3, [r3, #8] + 206 0024 3B60 str r3, [r7] + 326:Generated_Source\PSoC4/Cm0Start.c **** unsigned count; + 327:Generated_Source\PSoC4/Cm0Start.c **** + 328:Generated_Source\PSoC4/Cm0Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) + 207 .loc 1 328 0 + 208 0026 0023 movs r3, #0 + 209 0028 7B60 str r3, [r7, #4] + 210 002a 0CE0 b .L14 + 211 .L15: + 329:Generated_Source\PSoC4/Cm0Start.c **** { + 330:Generated_Source\PSoC4/Cm0Start.c **** *dst = *src; + 212 .loc 1 330 0 discriminator 3 + 213 002c FB68 ldr r3, [r7, #12] + 214 002e 1A68 ldr r2, [r3] + 215 0030 BB68 ldr r3, [r7, #8] + 216 0032 1A60 str r2, [r3] + 331:Generated_Source\PSoC4/Cm0Start.c **** dst++; + 217 .loc 1 331 0 discriminator 3 + 218 0034 BB68 ldr r3, [r7, #8] + 219 0036 0433 adds r3, r3, #4 + 220 0038 BB60 str r3, [r7, #8] + 332:Generated_Source\PSoC4/Cm0Start.c **** src++; + 221 .loc 1 332 0 discriminator 3 + 222 003a FB68 ldr r3, [r7, #12] + 223 003c 0433 adds r3, r3, #4 + 224 003e FB60 str r3, [r7, #12] + 328:Generated_Source\PSoC4/Cm0Start.c **** { + 225 .loc 1 328 0 discriminator 3 + 226 0040 7B68 ldr r3, [r7, #4] + 227 0042 0433 adds r3, r3, #4 + 228 0044 7B60 str r3, [r7, #4] + 229 .L14: + 328:Generated_Source\PSoC4/Cm0Start.c **** { + 230 .loc 1 328 0 is_stmt 0 discriminator 1 + 231 0046 7A68 ldr r2, [r7, #4] + 232 0048 3B68 ldr r3, [r7] + 233 004a 9A42 cmp r2, r3 + 234 004c EED1 bne .L15 + 333:Generated_Source\PSoC4/Cm0Start.c **** } + 334:Generated_Source\PSoC4/Cm0Start.c **** limit = rptr->zero_size; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 11 + + + 235 .loc 1 334 0 is_stmt 1 + 236 004e 3B69 ldr r3, [r7, #16] + 237 0050 DB68 ldr r3, [r3, #12] + 238 0052 3B60 str r3, [r7] + 335:Generated_Source\PSoC4/Cm0Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) + 239 .loc 1 335 0 + 240 0054 0023 movs r3, #0 + 241 0056 7B60 str r3, [r7, #4] + 242 0058 08E0 b .L16 + 243 .L17: + 336:Generated_Source\PSoC4/Cm0Start.c **** { + 337:Generated_Source\PSoC4/Cm0Start.c **** *dst = 0u; + 244 .loc 1 337 0 discriminator 3 + 245 005a BB68 ldr r3, [r7, #8] + 246 005c 0022 movs r2, #0 + 247 005e 1A60 str r2, [r3] + 338:Generated_Source\PSoC4/Cm0Start.c **** dst++; + 248 .loc 1 338 0 discriminator 3 + 249 0060 BB68 ldr r3, [r7, #8] + 250 0062 0433 adds r3, r3, #4 + 251 0064 BB60 str r3, [r7, #8] + 335:Generated_Source\PSoC4/Cm0Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) + 252 .loc 1 335 0 discriminator 3 + 253 0066 7B68 ldr r3, [r7, #4] + 254 0068 0433 adds r3, r3, #4 + 255 006a 7B60 str r3, [r7, #4] + 256 .L16: + 335:Generated_Source\PSoC4/Cm0Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) + 257 .loc 1 335 0 is_stmt 0 discriminator 1 + 258 006c 7A68 ldr r2, [r7, #4] + 259 006e 3B68 ldr r3, [r7] + 260 0070 9A42 cmp r2, r3 + 261 0072 F2D1 bne .L17 + 339:Generated_Source\PSoC4/Cm0Start.c **** } + 340:Generated_Source\PSoC4/Cm0Start.c **** + 341:Generated_Source\PSoC4/Cm0Start.c **** rptr++; + 262 .loc 1 341 0 is_stmt 1 discriminator 2 + 263 0074 3B69 ldr r3, [r7, #16] + 264 0076 1033 adds r3, r3, #16 + 265 0078 3B61 str r3, [r7, #16] + 266 .LBE2: + 321:Generated_Source\PSoC4/Cm0Start.c **** { + 267 .loc 1 321 0 discriminator 2 + 268 007a 7B69 ldr r3, [r7, #20] + 269 007c 013B subs r3, r3, #1 + 270 007e 7B61 str r3, [r7, #20] + 271 .L13: + 321:Generated_Source\PSoC4/Cm0Start.c **** { + 272 .loc 1 321 0 is_stmt 0 discriminator 1 + 273 0080 7B69 ldr r3, [r7, #20] + 274 0082 002B cmp r3, #0 + 275 0084 C6D1 bne .L18 + 342:Generated_Source\PSoC4/Cm0Start.c **** } + 343:Generated_Source\PSoC4/Cm0Start.c **** + 344:Generated_Source\PSoC4/Cm0Start.c **** /* Invoke static objects constructors */ + 345:Generated_Source\PSoC4/Cm0Start.c **** __libc_init_array(); + 276 .loc 1 345 0 is_stmt 1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 12 + + + 277 0086 FFF7FEFF bl __libc_init_array + 346:Generated_Source\PSoC4/Cm0Start.c **** (void) main(); + 278 .loc 1 346 0 + 279 008a FFF7FEFF bl main + 280 .L19: + 347:Generated_Source\PSoC4/Cm0Start.c **** + 348:Generated_Source\PSoC4/Cm0Start.c **** while (1) + 349:Generated_Source\PSoC4/Cm0Start.c **** { + 350:Generated_Source\PSoC4/Cm0Start.c **** /* If main returns, make sure we don't return. */ + 351:Generated_Source\PSoC4/Cm0Start.c **** } + 281 .loc 1 351 0 discriminator 1 + 282 008e FEE7 b .L19 + 283 .L21: + 284 .align 2 + 285 .L20: + 286 0090 00000000 .word __cy_region_num + 287 0094 00000000 .word __cy_regions + 288 .cfi_endproc + 289 .LFE3: + 290 .size Start_c, .-Start_c + 291 .section .text.Reset,"ax",%progbits + 292 .align 2 + 293 .global Reset + 294 .code 16 + 295 .thumb_func + 296 .type Reset, %function + 297 Reset: + 298 .LFB4: + 352:Generated_Source\PSoC4/Cm0Start.c **** + 353:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CY_BOOT_START_C_CALLBACK */ + 354:Generated_Source\PSoC4/Cm0Start.c **** } + 355:Generated_Source\PSoC4/Cm0Start.c **** + 356:Generated_Source\PSoC4/Cm0Start.c **** + 357:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 358:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: Reset + 359:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 360:Generated_Source\PSoC4/Cm0Start.c **** * + 361:Generated_Source\PSoC4/Cm0Start.c **** * This function handles the reset interrupt for the GCC toolchain. This is + 362:Generated_Source\PSoC4/Cm0Start.c **** * the first bit of code that is executed at startup. + 363:Generated_Source\PSoC4/Cm0Start.c **** * + 364:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 365:Generated_Source\PSoC4/Cm0Start.c **** void Reset(void) + 366:Generated_Source\PSoC4/Cm0Start.c **** { + 299 .loc 1 366 0 + 300 .cfi_startproc + 301 @ args = 0, pretend = 0, frame = 0 + 302 @ frame_needed = 1, uses_anonymous_args = 0 + 303 0000 80B5 push {r7, lr} + 304 .cfi_def_cfa_offset 8 + 305 .cfi_offset 7, -8 + 306 .cfi_offset 14, -4 + 307 0002 00AF add r7, sp, #0 + 308 .cfi_def_cfa_register 7 + 367:Generated_Source\PSoC4/Cm0Start.c **** #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE + 368:Generated_Source\PSoC4/Cm0Start.c **** + 369:Generated_Source\PSoC4/Cm0Start.c **** /* The bootloadable application image is started at Reset() handler + 370:Generated_Source\PSoC4/Cm0Start.c **** * as a result of a branch instruction execution from the bootloader. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 13 + + + 371:Generated_Source\PSoC4/Cm0Start.c **** * So, the stack pointer needs to be reset to be sure that + 372:Generated_Source\PSoC4/Cm0Start.c **** * there is no garbage in the stack. + 373:Generated_Source\PSoC4/Cm0Start.c **** */ + 374:Generated_Source\PSoC4/Cm0Start.c **** __asm volatile ("MSR msp, %0\n" : : "r" ((uint32)&__cy_stack) : "sp"); + 375:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CYDEV_PROJ_TYPE_LOADABLE */ + 376:Generated_Source\PSoC4/Cm0Start.c **** + 377:Generated_Source\PSoC4/Cm0Start.c **** #if(CY_IP_SRSSLT) + 378:Generated_Source\PSoC4/Cm0Start.c **** CySysWdtDisable(); + 379:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_SRSSLT) */ + 380:Generated_Source\PSoC4/Cm0Start.c **** + 381:Generated_Source\PSoC4/Cm0Start.c **** #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + 382:Generated_Source\PSoC4/Cm0Start.c **** CyBtldr_CheckLaunch(); + 383:Generated_Source\PSoC4/Cm0Start.c **** #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOAD + 384:Generated_Source\PSoC4/Cm0Start.c **** Start_c(); + 309 .loc 1 384 0 + 310 0004 FFF7FEFF bl Start_c + 311 .cfi_endproc + 312 .LFE4: + 313 .size Reset, .-Reset + 314 .global CyRamVectors + 315 .section .ramvectors,"aw",%progbits + 316 .align 2 + 317 .type CyRamVectors, %object + 318 .size CyRamVectors, 192 + 319 CyRamVectors: + 320 0000 00000000 .space 192 + 320 00000000 + 320 00000000 + 320 00000000 + 320 00000000 + 321 .global RomVectors + 322 .section .romvectors,"a",%progbits + 323 .align 2 + 324 .type RomVectors, %object + 325 .size RomVectors, 16 + 326 RomVectors: + 327 0000 00000000 .word __cy_stack + 328 0004 00000000 .word Reset + 329 0008 00000000 .word IntDefaultHandler + 330 000c 00000000 .word IntDefaultHandler + 331 .section .text.initialize_psoc,"ax",%progbits + 332 .align 2 + 333 .global initialize_psoc + 334 .code 16 + 335 .thumb_func + 336 .type initialize_psoc, %function + 337 initialize_psoc: + 338 .LFB5: + 385:Generated_Source\PSoC4/Cm0Start.c **** } + 386:Generated_Source\PSoC4/Cm0Start.c **** + 387:Generated_Source\PSoC4/Cm0Start.c **** #elif defined (__ICCARM__) + 388:Generated_Source\PSoC4/Cm0Start.c **** + 389:Generated_Source\PSoC4/Cm0Start.c **** + 390:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 391:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: __low_level_init + 392:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 393:Generated_Source\PSoC4/Cm0Start.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 14 + + + 394:Generated_Source\PSoC4/Cm0Start.c **** * This function performs early initializations for the IAR Embedded + 395:Generated_Source\PSoC4/Cm0Start.c **** * Workbench IDE. It is executed in the context of reset interrupt handler + 396:Generated_Source\PSoC4/Cm0Start.c **** * before the data sections are initialized. + 397:Generated_Source\PSoC4/Cm0Start.c **** * + 398:Generated_Source\PSoC4/Cm0Start.c **** * \return The value that determines whether or not data sections should be + 399:Generated_Source\PSoC4/Cm0Start.c **** * initialized by the system startup code: + 400:Generated_Source\PSoC4/Cm0Start.c **** * 0 - skip data sections initialization; + 401:Generated_Source\PSoC4/Cm0Start.c **** * 1 - initialize data sections; + 402:Generated_Source\PSoC4/Cm0Start.c **** * + 403:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 404:Generated_Source\PSoC4/Cm0Start.c **** #pragma inline = never + 405:Generated_Source\PSoC4/Cm0Start.c **** int __low_level_init(void) + 406:Generated_Source\PSoC4/Cm0Start.c **** { + 407:Generated_Source\PSoC4/Cm0Start.c **** #if(CY_IP_SRSSLT) + 408:Generated_Source\PSoC4/Cm0Start.c **** CySysWdtDisable(); + 409:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_SRSSLT) */ + 410:Generated_Source\PSoC4/Cm0Start.c **** + 411:Generated_Source\PSoC4/Cm0Start.c **** #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + 412:Generated_Source\PSoC4/Cm0Start.c **** CyBtldr_CheckLaunch(); + 413:Generated_Source\PSoC4/Cm0Start.c **** #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + 414:Generated_Source\PSoC4/Cm0Start.c **** + 415:Generated_Source\PSoC4/Cm0Start.c **** /* Initialize data sections */ + 416:Generated_Source\PSoC4/Cm0Start.c **** __iar_data_init3(); + 417:Generated_Source\PSoC4/Cm0Start.c **** + 418:Generated_Source\PSoC4/Cm0Start.c **** initialize_psoc(); + 419:Generated_Source\PSoC4/Cm0Start.c **** + 420:Generated_Source\PSoC4/Cm0Start.c **** return 0; + 421:Generated_Source\PSoC4/Cm0Start.c **** } + 422:Generated_Source\PSoC4/Cm0Start.c **** + 423:Generated_Source\PSoC4/Cm0Start.c **** #endif /* __GNUC__ */ + 424:Generated_Source\PSoC4/Cm0Start.c **** + 425:Generated_Source\PSoC4/Cm0Start.c **** + 426:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 427:Generated_Source\PSoC4/Cm0Start.c **** * Ram Interrupt Vector table storage area. Must be placed at 0x20000000. + 428:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 429:Generated_Source\PSoC4/Cm0Start.c **** + 430:Generated_Source\PSoC4/Cm0Start.c **** #if defined (__ICCARM__) + 431:Generated_Source\PSoC4/Cm0Start.c **** #pragma location=".ramvectors" + 432:Generated_Source\PSoC4/Cm0Start.c **** #elif defined (__ARMCC_VERSION) + 433:Generated_Source\PSoC4/Cm0Start.c **** #ifndef CY_SYS_RAM_VECTOR_SECTION + 434:Generated_Source\PSoC4/Cm0Start.c **** #define CY_SYS_RAM_VECTOR_SECTION __attribute__((section(".ramvectors"), zero_init)) + 435:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CY_SYS_RAM_VECTOR_SECTION */ + 436:Generated_Source\PSoC4/Cm0Start.c **** CY_SYS_RAM_VECTOR_SECTION + 437:Generated_Source\PSoC4/Cm0Start.c **** #else + 438:Generated_Source\PSoC4/Cm0Start.c **** #ifndef CY_SYS_RAM_VECTOR_SECTION + 439:Generated_Source\PSoC4/Cm0Start.c **** #define CY_SYS_RAM_VECTOR_SECTION CY_SECTION(".ramvectors") + 440:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CY_SYS_RAM_VECTOR_SECTION */ + 441:Generated_Source\PSoC4/Cm0Start.c **** CY_SYS_RAM_VECTOR_SECTION + 442:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined (__ICCARM__) */ + 443:Generated_Source\PSoC4/Cm0Start.c **** cyisraddress CyRamVectors[CY_NUM_VECTORS]; + 444:Generated_Source\PSoC4/Cm0Start.c **** + 445:Generated_Source\PSoC4/Cm0Start.c **** + 446:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 447:Generated_Source\PSoC4/Cm0Start.c **** * Rom Interrupt Vector table storage area. Must be 256-byte aligned. + 448:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 449:Generated_Source\PSoC4/Cm0Start.c **** + 450:Generated_Source\PSoC4/Cm0Start.c **** #if defined(__ARMCC_VERSION) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 15 + + + 451:Generated_Source\PSoC4/Cm0Start.c **** /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + 452:Generated_Source\PSoC4/Cm0Start.c **** #pragma diag_suppress 1296 + 453:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined(__ARMCC_VERSION) */ + 454:Generated_Source\PSoC4/Cm0Start.c **** + 455:Generated_Source\PSoC4/Cm0Start.c **** #if defined (__ICCARM__) + 456:Generated_Source\PSoC4/Cm0Start.c **** #pragma location=".romvectors" + 457:Generated_Source\PSoC4/Cm0Start.c **** const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = + 458:Generated_Source\PSoC4/Cm0Start.c **** #else + 459:Generated_Source\PSoC4/Cm0Start.c **** #ifndef CY_SYS_ROM_VECTOR_SECTION + 460:Generated_Source\PSoC4/Cm0Start.c **** #define CY_SYS_ROM_VECTOR_SECTION CY_SECTION(".romvectors") + 461:Generated_Source\PSoC4/Cm0Start.c **** #endif /* CY_SYS_ROM_VECTOR_SECTION */ + 462:Generated_Source\PSoC4/Cm0Start.c **** CY_SYS_ROM_VECTOR_SECTION + 463:Generated_Source\PSoC4/Cm0Start.c **** const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = + 464:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined (__ICCARM__) */ + 465:Generated_Source\PSoC4/Cm0Start.c **** { + 466:Generated_Source\PSoC4/Cm0Start.c **** CY_SYS_INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + 467:Generated_Source\PSoC4/Cm0Start.c **** #if defined (__ICCARM__) /* The reset handler 1 */ + 468:Generated_Source\PSoC4/Cm0Start.c **** __iar_program_start, + 469:Generated_Source\PSoC4/Cm0Start.c **** #else + 470:Generated_Source\PSoC4/Cm0Start.c **** (cyisraddress)&Reset, + 471:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined (__ICCARM__) */ + 472:Generated_Source\PSoC4/Cm0Start.c **** &IntDefaultHandler, /* The NMI handler 2 */ + 473:Generated_Source\PSoC4/Cm0Start.c **** &IntDefaultHandler, /* The hard fault handler 3 */ + 474:Generated_Source\PSoC4/Cm0Start.c **** }; + 475:Generated_Source\PSoC4/Cm0Start.c **** + 476:Generated_Source\PSoC4/Cm0Start.c **** #if defined(__ARMCC_VERSION) + 477:Generated_Source\PSoC4/Cm0Start.c **** #pragma diag_default 1296 + 478:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined(__ARMCC_VERSION) */ + 479:Generated_Source\PSoC4/Cm0Start.c **** + 480:Generated_Source\PSoC4/Cm0Start.c **** + 481:Generated_Source\PSoC4/Cm0Start.c **** /******************************************************************************* + 482:Generated_Source\PSoC4/Cm0Start.c **** * Function Name: initialize_psoc + 483:Generated_Source\PSoC4/Cm0Start.c **** ****************************************************************************//** + 484:Generated_Source\PSoC4/Cm0Start.c **** * + 485:Generated_Source\PSoC4/Cm0Start.c **** * This function is used to initialize the PSoC chip before calling main. + 486:Generated_Source\PSoC4/Cm0Start.c **** * + 487:Generated_Source\PSoC4/Cm0Start.c **** *******************************************************************************/ + 488:Generated_Source\PSoC4/Cm0Start.c **** #if(defined(__GNUC__) && !defined(__ARMCC_VERSION)) + 489:Generated_Source\PSoC4/Cm0Start.c **** __attribute__ ((constructor(101))) + 490:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (defined(__GNUC__) && !defined(__ARMCC_VERSION)) */ + 491:Generated_Source\PSoC4/Cm0Start.c **** void initialize_psoc(void) + 492:Generated_Source\PSoC4/Cm0Start.c **** { + 339 .loc 1 492 0 + 340 .cfi_startproc + 341 @ args = 0, pretend = 0, frame = 8 + 342 @ frame_needed = 1, uses_anonymous_args = 0 + 343 0000 80B5 push {r7, lr} + 344 .cfi_def_cfa_offset 8 + 345 .cfi_offset 7, -8 + 346 .cfi_offset 14, -4 + 347 0002 82B0 sub sp, sp, #8 + 348 .cfi_def_cfa_offset 16 + 349 0004 00AF add r7, sp, #0 + 350 .cfi_def_cfa_register 7 + 493:Generated_Source\PSoC4/Cm0Start.c **** uint32 indexInit; + 494:Generated_Source\PSoC4/Cm0Start.c **** + 495:Generated_Source\PSoC4/Cm0Start.c **** #if(CY_IP_CPUSSV2) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 16 + + + 496:Generated_Source\PSoC4/Cm0Start.c **** #if (CY_IP_CPUSS_CM0) + 497:Generated_Source\PSoC4/Cm0Start.c **** /*********************************************************************** + 498:Generated_Source\PSoC4/Cm0Start.c **** * Make sure that Vector Table is located at 0000_0000 in Flash, before + 499:Generated_Source\PSoC4/Cm0Start.c **** * accessing RomVectors or calling functions that may be placed in + 500:Generated_Source\PSoC4/Cm0Start.c **** * .psocinit (cyfitter_cfg and ClockSetup). Note The CY_CPUSS_CONFIG_REG + 501:Generated_Source\PSoC4/Cm0Start.c **** * register is retention for the specified device family. + 502:Generated_Source\PSoC4/Cm0Start.c **** ***********************************************************************/ + 503:Generated_Source\PSoC4/Cm0Start.c **** CY_CPUSS_CONFIG_REG &= (uint32) ~CY_CPUSS_CONFIG_VECT_IN_RAM; + 504:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_CPUSS_CM0) */ + 505:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_CPUSSV2) */ + 506:Generated_Source\PSoC4/Cm0Start.c **** + 507:Generated_Source\PSoC4/Cm0Start.c **** /* Set Ram interrupt vectors to default functions. */ + 508:Generated_Source\PSoC4/Cm0Start.c **** for (indexInit = 0u; indexInit < CY_NUM_VECTORS; indexInit++) + 351 .loc 1 508 0 + 352 0006 0023 movs r3, #0 + 353 0008 7B60 str r3, [r7, #4] + 354 000a 0FE0 b .L24 + 355 .L27: + 509:Generated_Source\PSoC4/Cm0Start.c **** { + 510:Generated_Source\PSoC4/Cm0Start.c **** CyRamVectors[indexInit] = (indexInit < CY_NUM_ROM_VECTORS) ? + 511:Generated_Source\PSoC4/Cm0Start.c **** #if defined (__ICCARM__) + 512:Generated_Source\PSoC4/Cm0Start.c **** __vector_table[indexInit].__fun : &IntDefaultHandler; + 513:Generated_Source\PSoC4/Cm0Start.c **** #else + 514:Generated_Source\PSoC4/Cm0Start.c **** RomVectors[indexInit] : &IntDefaultHandler; + 356 .loc 1 514 0 + 357 000c 7B68 ldr r3, [r7, #4] + 358 000e 032B cmp r3, #3 + 359 0010 04D8 bhi .L25 + 360 .loc 1 514 0 is_stmt 0 discriminator 1 + 361 0012 104B ldr r3, .L28 + 362 0014 7A68 ldr r2, [r7, #4] + 363 0016 9200 lsls r2, r2, #2 + 364 0018 D358 ldr r3, [r2, r3] + 365 001a 00E0 b .L26 + 366 .L25: + 367 .loc 1 514 0 discriminator 2 + 368 001c 0E4B ldr r3, .L28+4 + 369 .L26: + 510:Generated_Source\PSoC4/Cm0Start.c **** #if defined (__ICCARM__) + 370 .loc 1 510 0 is_stmt 1 discriminator 2 + 371 001e 0F4A ldr r2, .L28+8 + 372 0020 7968 ldr r1, [r7, #4] + 373 0022 8900 lsls r1, r1, #2 + 374 0024 8B50 str r3, [r1, r2] + 508:Generated_Source\PSoC4/Cm0Start.c **** { + 375 .loc 1 508 0 discriminator 2 + 376 0026 7B68 ldr r3, [r7, #4] + 377 0028 0133 adds r3, r3, #1 + 378 002a 7B60 str r3, [r7, #4] + 379 .L24: + 508:Generated_Source\PSoC4/Cm0Start.c **** { + 380 .loc 1 508 0 is_stmt 0 discriminator 1 + 381 002c 7B68 ldr r3, [r7, #4] + 382 002e 2F2B cmp r3, #47 + 383 0030 ECD9 bls .L27 + 515:Generated_Source\PSoC4/Cm0Start.c **** #endif /* defined (__ICCARM__) */ + 516:Generated_Source\PSoC4/Cm0Start.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 17 + + + 517:Generated_Source\PSoC4/Cm0Start.c **** + 518:Generated_Source\PSoC4/Cm0Start.c **** /* Initialize configuration registers. */ + 519:Generated_Source\PSoC4/Cm0Start.c **** cyfitter_cfg(); + 384 .loc 1 519 0 is_stmt 1 + 385 0032 FFF7FEFF bl cyfitter_cfg + 520:Generated_Source\PSoC4/Cm0Start.c **** + 521:Generated_Source\PSoC4/Cm0Start.c **** #if !defined (__ICCARM__) + 522:Generated_Source\PSoC4/Cm0Start.c **** /* Actually, no need to clean this variable, just to make compiler happy. */ + 523:Generated_Source\PSoC4/Cm0Start.c **** cySysNoInitDataValid = 0u; + 386 .loc 1 523 0 + 387 0036 0A4B ldr r3, .L28+12 + 388 0038 0022 movs r2, #0 + 389 003a 1A60 str r2, [r3] + 524:Generated_Source\PSoC4/Cm0Start.c **** #endif /* !defined (__ICCARM__) */ + 525:Generated_Source\PSoC4/Cm0Start.c **** + 526:Generated_Source\PSoC4/Cm0Start.c **** #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + 527:Generated_Source\PSoC4/Cm0Start.c **** + 528:Generated_Source\PSoC4/Cm0Start.c **** /* Need to make sure that this variable will not be optimized out */ + 529:Generated_Source\PSoC4/Cm0Start.c **** if (0u == cyBtldrRunType) + 530:Generated_Source\PSoC4/Cm0Start.c **** { + 531:Generated_Source\PSoC4/Cm0Start.c **** cyBtldrRunType = 0u; + 532:Generated_Source\PSoC4/Cm0Start.c **** } + 533:Generated_Source\PSoC4/Cm0Start.c **** + 534:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + 535:Generated_Source\PSoC4/Cm0Start.c **** + 536:Generated_Source\PSoC4/Cm0Start.c **** #if (CY_IP_CPUSS_CM0) + 537:Generated_Source\PSoC4/Cm0Start.c **** /* Vector Table is located at 0x2000:0000 in SRAM */ + 538:Generated_Source\PSoC4/Cm0Start.c **** CY_CPUSS_CONFIG_REG |= CY_CPUSS_CONFIG_VECT_IN_RAM; + 390 .loc 1 538 0 + 391 003c 8023 movs r3, #128 + 392 003e DB05 lsls r3, r3, #23 + 393 0040 8022 movs r2, #128 + 394 0042 D205 lsls r2, r2, #23 + 395 0044 1268 ldr r2, [r2] + 396 0046 0121 movs r1, #1 + 397 0048 0A43 orrs r2, r1 + 398 004a 1A60 str r2, [r3] + 539:Generated_Source\PSoC4/Cm0Start.c **** #else + 540:Generated_Source\PSoC4/Cm0Start.c **** (*(uint32 *)CYREG_CM0P_VTOR) = CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM; + 541:Generated_Source\PSoC4/Cm0Start.c **** #endif /* (CY_IP_CPUSS_CM0) */ + 542:Generated_Source\PSoC4/Cm0Start.c **** } + 399 .loc 1 542 0 + 400 004c C046 nop + 401 004e BD46 mov sp, r7 + 402 0050 02B0 add sp, sp, #8 + 403 @ sp needed + 404 0052 80BD pop {r7, pc} + 405 .L29: + 406 .align 2 + 407 .L28: + 408 0054 00000000 .word RomVectors + 409 0058 00000000 .word IntDefaultHandler + 410 005c 00000000 .word CyRamVectors + 411 0060 00000000 .word cySysNoInitDataValid + 412 .cfi_endproc + 413 .LFE5: + 414 .size initialize_psoc, .-initialize_psoc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 18 + + + 415 .section .init_array,"aw",%init_array + 416 .align 2 + 417 0000 00000000 .word initialize_psoc(target1) + 418 .data + 419 .align 2 + 420 .type heapPointer.4844, %object + 421 .size heapPointer.4844, 4 + 422 heapPointer.4844: + 423 0000 00000000 .word end + 424 .weak __cy_region_num + 425 .text + 426 .Letext0: + 427 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\4.2\\psoc creator\\import\\gnu\\arm\\5.4. + 428 .file 3 "Generated_Source\\PSoC4\\cytypes.h" + 429 .section .debug_info,"",%progbits + 430 .Ldebug_info0: + 431 0000 0E030000 .4byte 0x30e + 432 0004 0400 .2byte 0x4 + 433 0006 00000000 .4byte .Ldebug_abbrev0 + 434 000a 04 .byte 0x4 + 435 000b 01 .uleb128 0x1 + 436 000c 30010000 .4byte .LASF41 + 437 0010 0C .byte 0xc + 438 0011 F3010000 .4byte .LASF42 + 439 0015 6D000000 .4byte .LASF43 + 440 0019 00000000 .4byte .Ldebug_ranges0+0 + 441 001d 00000000 .4byte 0 + 442 0021 00000000 .4byte .Ldebug_line0 + 443 0025 02 .uleb128 0x2 + 444 0026 01 .byte 0x1 + 445 0027 06 .byte 0x6 + 446 0028 B3020000 .4byte .LASF0 + 447 002c 02 .uleb128 0x2 + 448 002d 01 .byte 0x1 + 449 002e 08 .byte 0x8 + 450 002f D8000000 .4byte .LASF1 + 451 0033 02 .uleb128 0x2 + 452 0034 02 .byte 0x2 + 453 0035 05 .byte 0x5 + 454 0036 94020000 .4byte .LASF2 + 455 003a 02 .uleb128 0x2 + 456 003b 02 .byte 0x2 + 457 003c 07 .byte 0x7 + 458 003d 34000000 .4byte .LASF3 + 459 0041 02 .uleb128 0x2 + 460 0042 04 .byte 0x4 + 461 0043 05 .byte 0x5 + 462 0044 9E020000 .4byte .LASF4 + 463 0048 02 .uleb128 0x2 + 464 0049 04 .byte 0x4 + 465 004a 07 .byte 0x7 + 466 004b FD000000 .4byte .LASF5 + 467 004f 02 .uleb128 0x2 + 468 0050 08 .byte 0x8 + 469 0051 05 .byte 0x5 + 470 0052 81020000 .4byte .LASF6 + 471 0056 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 19 + + + 472 0057 08 .byte 0x8 + 473 0058 07 .byte 0x7 + 474 0059 33020000 .4byte .LASF7 + 475 005d 03 .uleb128 0x3 + 476 005e 04 .byte 0x4 + 477 005f 05 .byte 0x5 + 478 0060 696E7400 .ascii "int\000" + 479 0064 02 .uleb128 0x2 + 480 0065 04 .byte 0x4 + 481 0066 07 .byte 0x7 + 482 0067 26020000 .4byte .LASF8 + 483 006b 04 .uleb128 0x4 + 484 006c 06000000 .4byte .LASF10 + 485 0070 02 .byte 0x2 + 486 0071 D8 .byte 0xd8 + 487 0072 64000000 .4byte 0x64 + 488 0076 02 .uleb128 0x2 + 489 0077 08 .byte 0x8 + 490 0078 04 .byte 0x4 + 491 0079 A7020000 .4byte .LASF9 + 492 007d 05 .uleb128 0x5 + 493 007e 24010000 .4byte .LASF11 + 494 0082 03 .byte 0x3 + 495 0083 E401 .2byte 0x1e4 + 496 0085 2C000000 .4byte 0x2c + 497 0089 05 .uleb128 0x5 + 498 008a 15020000 .4byte .LASF12 + 499 008e 03 .byte 0x3 + 500 008f E601 .2byte 0x1e6 + 501 0091 48000000 .4byte 0x48 + 502 0095 02 .uleb128 0x2 + 503 0096 04 .byte 0x4 + 504 0097 04 .byte 0x4 + 505 0098 CD000000 .4byte .LASF13 + 506 009c 02 .uleb128 0x2 + 507 009d 08 .byte 0x8 + 508 009e 04 .byte 0x4 + 509 009f DC010000 .4byte .LASF14 + 510 00a3 02 .uleb128 0x2 + 511 00a4 01 .byte 0x1 + 512 00a5 08 .byte 0x8 + 513 00a6 8F020000 .4byte .LASF15 + 514 00aa 05 .uleb128 0x5 + 515 00ab 00000000 .4byte .LASF16 + 516 00af 03 .byte 0x3 + 517 00b0 9002 .2byte 0x290 + 518 00b2 B6000000 .4byte 0xb6 + 519 00b6 06 .uleb128 0x6 + 520 00b7 89000000 .4byte 0x89 + 521 00bb 05 .uleb128 0x5 + 522 00bc 50020000 .4byte .LASF17 + 523 00c0 03 .byte 0x3 + 524 00c1 A002 .2byte 0x2a0 + 525 00c3 C7000000 .4byte 0xc7 + 526 00c7 07 .uleb128 0x7 + 527 00c8 04 .byte 0x4 + 528 00c9 CD000000 .4byte 0xcd + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 20 + + + 529 00cd 08 .uleb128 0x8 + 530 00ce 02 .uleb128 0x2 + 531 00cf 04 .byte 0x4 + 532 00d0 07 .byte 0x7 + 533 00d1 78020000 .4byte .LASF18 + 534 00d5 09 .uleb128 0x9 + 535 00d6 04 .byte 0x4 + 536 00d7 0A .uleb128 0xa + 537 00d8 A3000000 .4byte 0xa3 + 538 00dc 04 .uleb128 0x4 + 539 00dd 67020000 .4byte .LASF19 + 540 00e1 01 .byte 0x1 + 541 00e2 DD .byte 0xdd + 542 00e3 2C000000 .4byte 0x2c + 543 00e7 0B .uleb128 0xb + 544 00e8 DB020000 .4byte .LASF44 + 545 00ec 10 .byte 0x10 + 546 00ed 01 .byte 0x1 + 547 00ee DF .byte 0xdf + 548 00ef 24010000 .4byte 0x124 + 549 00f3 0C .uleb128 0xc + 550 00f4 57000000 .4byte .LASF20 + 551 00f8 01 .byte 0x1 + 552 00f9 E1 .byte 0xe1 + 553 00fa 24010000 .4byte 0x124 + 554 00fe 00 .byte 0 + 555 00ff 0C .uleb128 0xc + 556 0100 D3000000 .4byte .LASF21 + 557 0104 01 .byte 0x1 + 558 0105 E2 .byte 0xe2 + 559 0106 24010000 .4byte 0x124 + 560 010a 04 .byte 0x4 + 561 010b 0C .uleb128 0xc + 562 010c 5D020000 .4byte .LASF22 + 563 0110 01 .byte 0x1 + 564 0111 E3 .byte 0xe3 + 565 0112 6B000000 .4byte 0x6b + 566 0116 08 .byte 0x8 + 567 0117 0C .uleb128 0xc + 568 0118 63000000 .4byte .LASF23 + 569 011c 01 .byte 0x1 + 570 011d E4 .byte 0xe4 + 571 011e 6B000000 .4byte 0x6b + 572 0122 0C .byte 0xc + 573 0123 00 .byte 0 + 574 0124 07 .uleb128 0x7 + 575 0125 04 .byte 0x4 + 576 0126 DC000000 .4byte 0xdc + 577 012a 0D .uleb128 0xd + 578 012b C4010000 .4byte .LASF45 + 579 012f 01 .byte 0x1 + 580 0130 6C .byte 0x6c + 581 0131 00000000 .4byte .LFB0 + 582 0135 14000000 .4byte .LFE0-.LFB0 + 583 0139 01 .uleb128 0x1 + 584 013a 9C .byte 0x9c + 585 013b 0E .uleb128 0xe + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 21 + + + 586 013c BE010000 .4byte .LASF24 + 587 0140 01 .byte 0x1 + 588 0141 FD .byte 0xfd + 589 0142 00000000 .4byte .LFB1 + 590 0146 14000000 .4byte .LFE1-.LFB1 + 591 014a 01 .uleb128 0x1 + 592 014b 9C .byte 0x9c + 593 014c 5F010000 .4byte 0x15f + 594 0150 0F .uleb128 0xf + 595 0151 5C000000 .4byte .LASF26 + 596 0155 01 .byte 0x1 + 597 0156 FD .byte 0xfd + 598 0157 5D000000 .4byte 0x5d + 599 015b 02 .uleb128 0x2 + 600 015c 91 .byte 0x91 + 601 015d 74 .sleb128 -12 + 602 015e 00 .byte 0 + 603 015f 10 .uleb128 0x10 + 604 0160 D6010000 .4byte .LASF25 + 605 0164 01 .byte 0x1 + 606 0165 1701 .2byte 0x117 + 607 0167 D5000000 .4byte 0xd5 + 608 016b 00000000 .4byte .LFB2 + 609 016f 54000000 .4byte .LFE2-.LFB2 + 610 0173 01 .uleb128 0x1 + 611 0174 9C .byte 0x9c + 612 0175 B6010000 .4byte 0x1b6 + 613 0179 11 .uleb128 0x11 + 614 017a D4020000 .4byte .LASF27 + 615 017e 01 .byte 0x1 + 616 017f 1701 .2byte 0x117 + 617 0181 5D000000 .4byte 0x5d + 618 0185 02 .uleb128 0x2 + 619 0186 91 .byte 0x91 + 620 0187 6C .sleb128 -20 + 621 0188 12 .uleb128 0x12 + 622 0189 656E6400 .ascii "end\000" + 623 018d 01 .byte 0x1 + 624 018e 1901 .2byte 0x119 + 625 0190 5D000000 .4byte 0x5d + 626 0194 13 .uleb128 0x13 + 627 0195 E6000000 .4byte .LASF28 + 628 0199 01 .byte 0x1 + 629 019a 1A01 .2byte 0x11a + 630 019c D5000000 .4byte 0xd5 + 631 01a0 02 .uleb128 0x2 + 632 01a1 91 .byte 0x91 + 633 01a2 74 .sleb128 -12 + 634 01a3 13 .uleb128 0x13 + 635 01a4 28000000 .4byte .LASF29 + 636 01a8 01 .byte 0x1 + 637 01a9 1D01 .2byte 0x11d + 638 01ab B6010000 .4byte 0x1b6 + 639 01af 05 .uleb128 0x5 + 640 01b0 03 .byte 0x3 + 641 01b1 00000000 .4byte heapPointer.4844 + 642 01b5 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 22 + + + 643 01b6 07 .uleb128 0x7 + 644 01b7 04 .byte 0x4 + 645 01b8 7D000000 .4byte 0x7d + 646 01bc 14 .uleb128 0x14 + 647 01bd 1A000000 .4byte .LASF30 + 648 01c1 01 .byte 0x1 + 649 01c2 3801 .2byte 0x138 + 650 01c4 00000000 .4byte .LFB3 + 651 01c8 98000000 .4byte .LFE3-.LFB3 + 652 01cc 01 .uleb128 0x1 + 653 01cd 9C .byte 0x9c + 654 01ce 37020000 .4byte 0x237 + 655 01d2 13 .uleb128 0x13 + 656 01d3 CC020000 .4byte .LASF31 + 657 01d7 01 .byte 0x1 + 658 01d8 3D01 .2byte 0x13d + 659 01da 64000000 .4byte 0x64 + 660 01de 02 .uleb128 0x2 + 661 01df 91 .byte 0x91 + 662 01e0 74 .sleb128 -12 + 663 01e1 13 .uleb128 0x13 + 664 01e2 C8000000 .4byte .LASF32 + 665 01e6 01 .byte 0x1 + 666 01e7 3E01 .2byte 0x13e + 667 01e9 37020000 .4byte 0x237 + 668 01ed 02 .uleb128 0x2 + 669 01ee 91 .byte 0x91 + 670 01ef 70 .sleb128 -16 + 671 01f0 15 .uleb128 0x15 + 672 01f1 14000000 .4byte .LBB2 + 673 01f5 66000000 .4byte .LBE2-.LBB2 + 674 01f9 16 .uleb128 0x16 + 675 01fa 73726300 .ascii "src\000" + 676 01fe 01 .byte 0x1 + 677 01ff 4301 .2byte 0x143 + 678 0201 42020000 .4byte 0x242 + 679 0205 02 .uleb128 0x2 + 680 0206 91 .byte 0x91 + 681 0207 6C .sleb128 -20 + 682 0208 16 .uleb128 0x16 + 683 0209 64737400 .ascii "dst\000" + 684 020d 01 .byte 0x1 + 685 020e 4401 .2byte 0x144 + 686 0210 42020000 .4byte 0x242 + 687 0214 02 .uleb128 0x2 + 688 0215 91 .byte 0x91 + 689 0216 68 .sleb128 -24 + 690 0217 13 .uleb128 0x13 + 691 0218 4A020000 .4byte .LASF33 + 692 021c 01 .byte 0x1 + 693 021d 4501 .2byte 0x145 + 694 021f 64000000 .4byte 0x64 + 695 0223 02 .uleb128 0x2 + 696 0224 91 .byte 0x91 + 697 0225 60 .sleb128 -32 + 698 0226 13 .uleb128 0x13 + 699 0227 22000000 .4byte .LASF34 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 23 + + + 700 022b 01 .byte 0x1 + 701 022c 4601 .2byte 0x146 + 702 022e 64000000 .4byte 0x64 + 703 0232 02 .uleb128 0x2 + 704 0233 91 .byte 0x91 + 705 0234 64 .sleb128 -28 + 706 0235 00 .byte 0 + 707 0236 00 .byte 0 + 708 0237 07 .uleb128 0x7 + 709 0238 04 .byte 0x4 + 710 0239 3D020000 .4byte 0x23d + 711 023d 0A .uleb128 0xa + 712 023e E7000000 .4byte 0xe7 + 713 0242 07 .uleb128 0x7 + 714 0243 04 .byte 0x4 + 715 0244 89000000 .4byte 0x89 + 716 0248 17 .uleb128 0x17 + 717 0249 2A010000 .4byte .LASF46 + 718 024d 01 .byte 0x1 + 719 024e 6D01 .2byte 0x16d + 720 0250 00000000 .4byte .LFB4 + 721 0254 08000000 .4byte .LFE4-.LFB4 + 722 0258 01 .uleb128 0x1 + 723 0259 9C .byte 0x9c + 724 025a 18 .uleb128 0x18 + 725 025b E3010000 .4byte .LASF47 + 726 025f 01 .byte 0x1 + 727 0260 EB01 .2byte 0x1eb + 728 0262 00000000 .4byte .LFB5 + 729 0266 64000000 .4byte .LFE5-.LFB5 + 730 026a 01 .uleb128 0x1 + 731 026b 9C .byte 0x9c + 732 026c 80020000 .4byte 0x280 + 733 0270 13 .uleb128 0x13 + 734 0271 1C020000 .4byte .LASF35 + 735 0275 01 .byte 0x1 + 736 0276 ED01 .2byte 0x1ed + 737 0278 89000000 .4byte 0x89 + 738 027c 02 .uleb128 0x2 + 739 027d 91 .byte 0x91 + 740 027e 74 .sleb128 -12 + 741 027f 00 .byte 0 + 742 0280 19 .uleb128 0x19 + 743 0281 0F010000 .4byte .LASF36 + 744 0285 01 .byte 0x1 + 745 0286 4D .byte 0x4d + 746 0287 89000000 .4byte 0x89 + 747 028b 05 .uleb128 0x5 + 748 028c 03 .byte 0x3 + 749 028d 00000000 .4byte cySysNoInitDataValid + 750 0291 12 .uleb128 0x12 + 751 0292 656E6400 .ascii "end\000" + 752 0296 01 .byte 0x1 + 753 0297 1901 .2byte 0x119 + 754 0299 5D000000 .4byte 0x5d + 755 029d 1A .uleb128 0x1a + 756 029e 3D020000 .4byte 0x23d + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 24 + + + 757 02a2 A8020000 .4byte 0x2a8 + 758 02a6 1B .uleb128 0x1b + 759 02a7 00 .byte 0 + 760 02a8 1C .uleb128 0x1c + 761 02a9 BF020000 .4byte .LASF37 + 762 02ad 01 .byte 0x1 + 763 02ae E7 .byte 0xe7 + 764 02af B3020000 .4byte 0x2b3 + 765 02b3 0A .uleb128 0xa + 766 02b4 9D020000 .4byte 0x29d + 767 02b8 1C .uleb128 0x1c + 768 02b9 47000000 .4byte .LASF38 + 769 02bd 01 .byte 0x1 + 770 02be E8 .byte 0xe8 + 771 02bf D7000000 .4byte 0xd7 + 772 02c3 1A .uleb128 0x1a + 773 02c4 BB000000 .4byte 0xbb + 774 02c8 D3020000 .4byte 0x2d3 + 775 02cc 1D .uleb128 0x1d + 776 02cd CE000000 .4byte 0xce + 777 02d1 2F .byte 0x2f + 778 02d2 00 .byte 0 + 779 02d3 1E .uleb128 0x1e + 780 02d4 0D000000 .4byte .LASF39 + 781 02d8 01 .byte 0x1 + 782 02d9 BB01 .2byte 0x1bb + 783 02db C3020000 .4byte 0x2c3 + 784 02df 05 .uleb128 0x5 + 785 02e0 03 .byte 0x3 + 786 02e1 00000000 .4byte CyRamVectors + 787 02e5 1A .uleb128 0x1a + 788 02e6 F5020000 .4byte 0x2f5 + 789 02ea F5020000 .4byte 0x2f5 + 790 02ee 1D .uleb128 0x1d + 791 02ef CE000000 .4byte 0xce + 792 02f3 03 .byte 0x3 + 793 02f4 00 .byte 0 + 794 02f5 0A .uleb128 0xa + 795 02f6 BB000000 .4byte 0xbb + 796 02fa 1E .uleb128 0x1e + 797 02fb F2000000 .4byte .LASF40 + 798 02ff 01 .byte 0x1 + 799 0300 CF01 .2byte 0x1cf + 800 0302 0C030000 .4byte 0x30c + 801 0306 05 .uleb128 0x5 + 802 0307 03 .byte 0x3 + 803 0308 00000000 .4byte RomVectors + 804 030c 0A .uleb128 0xa + 805 030d E5020000 .4byte 0x2e5 + 806 0311 00 .byte 0 + 807 .section .debug_abbrev,"",%progbits + 808 .Ldebug_abbrev0: + 809 0000 01 .uleb128 0x1 + 810 0001 11 .uleb128 0x11 + 811 0002 01 .byte 0x1 + 812 0003 25 .uleb128 0x25 + 813 0004 0E .uleb128 0xe + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 25 + + + 814 0005 13 .uleb128 0x13 + 815 0006 0B .uleb128 0xb + 816 0007 03 .uleb128 0x3 + 817 0008 0E .uleb128 0xe + 818 0009 1B .uleb128 0x1b + 819 000a 0E .uleb128 0xe + 820 000b 55 .uleb128 0x55 + 821 000c 17 .uleb128 0x17 + 822 000d 11 .uleb128 0x11 + 823 000e 01 .uleb128 0x1 + 824 000f 10 .uleb128 0x10 + 825 0010 17 .uleb128 0x17 + 826 0011 00 .byte 0 + 827 0012 00 .byte 0 + 828 0013 02 .uleb128 0x2 + 829 0014 24 .uleb128 0x24 + 830 0015 00 .byte 0 + 831 0016 0B .uleb128 0xb + 832 0017 0B .uleb128 0xb + 833 0018 3E .uleb128 0x3e + 834 0019 0B .uleb128 0xb + 835 001a 03 .uleb128 0x3 + 836 001b 0E .uleb128 0xe + 837 001c 00 .byte 0 + 838 001d 00 .byte 0 + 839 001e 03 .uleb128 0x3 + 840 001f 24 .uleb128 0x24 + 841 0020 00 .byte 0 + 842 0021 0B .uleb128 0xb + 843 0022 0B .uleb128 0xb + 844 0023 3E .uleb128 0x3e + 845 0024 0B .uleb128 0xb + 846 0025 03 .uleb128 0x3 + 847 0026 08 .uleb128 0x8 + 848 0027 00 .byte 0 + 849 0028 00 .byte 0 + 850 0029 04 .uleb128 0x4 + 851 002a 16 .uleb128 0x16 + 852 002b 00 .byte 0 + 853 002c 03 .uleb128 0x3 + 854 002d 0E .uleb128 0xe + 855 002e 3A .uleb128 0x3a + 856 002f 0B .uleb128 0xb + 857 0030 3B .uleb128 0x3b + 858 0031 0B .uleb128 0xb + 859 0032 49 .uleb128 0x49 + 860 0033 13 .uleb128 0x13 + 861 0034 00 .byte 0 + 862 0035 00 .byte 0 + 863 0036 05 .uleb128 0x5 + 864 0037 16 .uleb128 0x16 + 865 0038 00 .byte 0 + 866 0039 03 .uleb128 0x3 + 867 003a 0E .uleb128 0xe + 868 003b 3A .uleb128 0x3a + 869 003c 0B .uleb128 0xb + 870 003d 3B .uleb128 0x3b + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 26 + + + 871 003e 05 .uleb128 0x5 + 872 003f 49 .uleb128 0x49 + 873 0040 13 .uleb128 0x13 + 874 0041 00 .byte 0 + 875 0042 00 .byte 0 + 876 0043 06 .uleb128 0x6 + 877 0044 35 .uleb128 0x35 + 878 0045 00 .byte 0 + 879 0046 49 .uleb128 0x49 + 880 0047 13 .uleb128 0x13 + 881 0048 00 .byte 0 + 882 0049 00 .byte 0 + 883 004a 07 .uleb128 0x7 + 884 004b 0F .uleb128 0xf + 885 004c 00 .byte 0 + 886 004d 0B .uleb128 0xb + 887 004e 0B .uleb128 0xb + 888 004f 49 .uleb128 0x49 + 889 0050 13 .uleb128 0x13 + 890 0051 00 .byte 0 + 891 0052 00 .byte 0 + 892 0053 08 .uleb128 0x8 + 893 0054 15 .uleb128 0x15 + 894 0055 00 .byte 0 + 895 0056 27 .uleb128 0x27 + 896 0057 19 .uleb128 0x19 + 897 0058 00 .byte 0 + 898 0059 00 .byte 0 + 899 005a 09 .uleb128 0x9 + 900 005b 0F .uleb128 0xf + 901 005c 00 .byte 0 + 902 005d 0B .uleb128 0xb + 903 005e 0B .uleb128 0xb + 904 005f 00 .byte 0 + 905 0060 00 .byte 0 + 906 0061 0A .uleb128 0xa + 907 0062 26 .uleb128 0x26 + 908 0063 00 .byte 0 + 909 0064 49 .uleb128 0x49 + 910 0065 13 .uleb128 0x13 + 911 0066 00 .byte 0 + 912 0067 00 .byte 0 + 913 0068 0B .uleb128 0xb + 914 0069 13 .uleb128 0x13 + 915 006a 01 .byte 0x1 + 916 006b 03 .uleb128 0x3 + 917 006c 0E .uleb128 0xe + 918 006d 0B .uleb128 0xb + 919 006e 0B .uleb128 0xb + 920 006f 3A .uleb128 0x3a + 921 0070 0B .uleb128 0xb + 922 0071 3B .uleb128 0x3b + 923 0072 0B .uleb128 0xb + 924 0073 01 .uleb128 0x1 + 925 0074 13 .uleb128 0x13 + 926 0075 00 .byte 0 + 927 0076 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 27 + + + 928 0077 0C .uleb128 0xc + 929 0078 0D .uleb128 0xd + 930 0079 00 .byte 0 + 931 007a 03 .uleb128 0x3 + 932 007b 0E .uleb128 0xe + 933 007c 3A .uleb128 0x3a + 934 007d 0B .uleb128 0xb + 935 007e 3B .uleb128 0x3b + 936 007f 0B .uleb128 0xb + 937 0080 49 .uleb128 0x49 + 938 0081 13 .uleb128 0x13 + 939 0082 38 .uleb128 0x38 + 940 0083 0B .uleb128 0xb + 941 0084 00 .byte 0 + 942 0085 00 .byte 0 + 943 0086 0D .uleb128 0xd + 944 0087 2E .uleb128 0x2e + 945 0088 00 .byte 0 + 946 0089 3F .uleb128 0x3f + 947 008a 19 .uleb128 0x19 + 948 008b 03 .uleb128 0x3 + 949 008c 0E .uleb128 0xe + 950 008d 3A .uleb128 0x3a + 951 008e 0B .uleb128 0xb + 952 008f 3B .uleb128 0x3b + 953 0090 0B .uleb128 0xb + 954 0091 27 .uleb128 0x27 + 955 0092 19 .uleb128 0x19 + 956 0093 8701 .uleb128 0x87 + 957 0095 19 .uleb128 0x19 + 958 0096 11 .uleb128 0x11 + 959 0097 01 .uleb128 0x1 + 960 0098 12 .uleb128 0x12 + 961 0099 06 .uleb128 0x6 + 962 009a 40 .uleb128 0x40 + 963 009b 18 .uleb128 0x18 + 964 009c 9642 .uleb128 0x2116 + 965 009e 19 .uleb128 0x19 + 966 009f 00 .byte 0 + 967 00a0 00 .byte 0 + 968 00a1 0E .uleb128 0xe + 969 00a2 2E .uleb128 0x2e + 970 00a3 01 .byte 0x1 + 971 00a4 3F .uleb128 0x3f + 972 00a5 19 .uleb128 0x19 + 973 00a6 03 .uleb128 0x3 + 974 00a7 0E .uleb128 0xe + 975 00a8 3A .uleb128 0x3a + 976 00a9 0B .uleb128 0xb + 977 00aa 3B .uleb128 0x3b + 978 00ab 0B .uleb128 0xb + 979 00ac 27 .uleb128 0x27 + 980 00ad 19 .uleb128 0x19 + 981 00ae 8701 .uleb128 0x87 + 982 00b0 19 .uleb128 0x19 + 983 00b1 11 .uleb128 0x11 + 984 00b2 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 28 + + + 985 00b3 12 .uleb128 0x12 + 986 00b4 06 .uleb128 0x6 + 987 00b5 40 .uleb128 0x40 + 988 00b6 18 .uleb128 0x18 + 989 00b7 9642 .uleb128 0x2116 + 990 00b9 19 .uleb128 0x19 + 991 00ba 01 .uleb128 0x1 + 992 00bb 13 .uleb128 0x13 + 993 00bc 00 .byte 0 + 994 00bd 00 .byte 0 + 995 00be 0F .uleb128 0xf + 996 00bf 05 .uleb128 0x5 + 997 00c0 00 .byte 0 + 998 00c1 03 .uleb128 0x3 + 999 00c2 0E .uleb128 0xe + 1000 00c3 3A .uleb128 0x3a + 1001 00c4 0B .uleb128 0xb + 1002 00c5 3B .uleb128 0x3b + 1003 00c6 0B .uleb128 0xb + 1004 00c7 49 .uleb128 0x49 + 1005 00c8 13 .uleb128 0x13 + 1006 00c9 02 .uleb128 0x2 + 1007 00ca 18 .uleb128 0x18 + 1008 00cb 00 .byte 0 + 1009 00cc 00 .byte 0 + 1010 00cd 10 .uleb128 0x10 + 1011 00ce 2E .uleb128 0x2e + 1012 00cf 01 .byte 0x1 + 1013 00d0 3F .uleb128 0x3f + 1014 00d1 19 .uleb128 0x19 + 1015 00d2 03 .uleb128 0x3 + 1016 00d3 0E .uleb128 0xe + 1017 00d4 3A .uleb128 0x3a + 1018 00d5 0B .uleb128 0xb + 1019 00d6 3B .uleb128 0x3b + 1020 00d7 05 .uleb128 0x5 + 1021 00d8 27 .uleb128 0x27 + 1022 00d9 19 .uleb128 0x19 + 1023 00da 49 .uleb128 0x49 + 1024 00db 13 .uleb128 0x13 + 1025 00dc 11 .uleb128 0x11 + 1026 00dd 01 .uleb128 0x1 + 1027 00de 12 .uleb128 0x12 + 1028 00df 06 .uleb128 0x6 + 1029 00e0 40 .uleb128 0x40 + 1030 00e1 18 .uleb128 0x18 + 1031 00e2 9642 .uleb128 0x2116 + 1032 00e4 19 .uleb128 0x19 + 1033 00e5 01 .uleb128 0x1 + 1034 00e6 13 .uleb128 0x13 + 1035 00e7 00 .byte 0 + 1036 00e8 00 .byte 0 + 1037 00e9 11 .uleb128 0x11 + 1038 00ea 05 .uleb128 0x5 + 1039 00eb 00 .byte 0 + 1040 00ec 03 .uleb128 0x3 + 1041 00ed 0E .uleb128 0xe + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 29 + + + 1042 00ee 3A .uleb128 0x3a + 1043 00ef 0B .uleb128 0xb + 1044 00f0 3B .uleb128 0x3b + 1045 00f1 05 .uleb128 0x5 + 1046 00f2 49 .uleb128 0x49 + 1047 00f3 13 .uleb128 0x13 + 1048 00f4 02 .uleb128 0x2 + 1049 00f5 18 .uleb128 0x18 + 1050 00f6 00 .byte 0 + 1051 00f7 00 .byte 0 + 1052 00f8 12 .uleb128 0x12 + 1053 00f9 34 .uleb128 0x34 + 1054 00fa 00 .byte 0 + 1055 00fb 03 .uleb128 0x3 + 1056 00fc 08 .uleb128 0x8 + 1057 00fd 3A .uleb128 0x3a + 1058 00fe 0B .uleb128 0xb + 1059 00ff 3B .uleb128 0x3b + 1060 0100 05 .uleb128 0x5 + 1061 0101 49 .uleb128 0x49 + 1062 0102 13 .uleb128 0x13 + 1063 0103 3F .uleb128 0x3f + 1064 0104 19 .uleb128 0x19 + 1065 0105 3C .uleb128 0x3c + 1066 0106 19 .uleb128 0x19 + 1067 0107 00 .byte 0 + 1068 0108 00 .byte 0 + 1069 0109 13 .uleb128 0x13 + 1070 010a 34 .uleb128 0x34 + 1071 010b 00 .byte 0 + 1072 010c 03 .uleb128 0x3 + 1073 010d 0E .uleb128 0xe + 1074 010e 3A .uleb128 0x3a + 1075 010f 0B .uleb128 0xb + 1076 0110 3B .uleb128 0x3b + 1077 0111 05 .uleb128 0x5 + 1078 0112 49 .uleb128 0x49 + 1079 0113 13 .uleb128 0x13 + 1080 0114 02 .uleb128 0x2 + 1081 0115 18 .uleb128 0x18 + 1082 0116 00 .byte 0 + 1083 0117 00 .byte 0 + 1084 0118 14 .uleb128 0x14 + 1085 0119 2E .uleb128 0x2e + 1086 011a 01 .byte 0x1 + 1087 011b 3F .uleb128 0x3f + 1088 011c 19 .uleb128 0x19 + 1089 011d 03 .uleb128 0x3 + 1090 011e 0E .uleb128 0xe + 1091 011f 3A .uleb128 0x3a + 1092 0120 0B .uleb128 0xb + 1093 0121 3B .uleb128 0x3b + 1094 0122 05 .uleb128 0x5 + 1095 0123 27 .uleb128 0x27 + 1096 0124 19 .uleb128 0x19 + 1097 0125 8701 .uleb128 0x87 + 1098 0127 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 30 + + + 1099 0128 11 .uleb128 0x11 + 1100 0129 01 .uleb128 0x1 + 1101 012a 12 .uleb128 0x12 + 1102 012b 06 .uleb128 0x6 + 1103 012c 40 .uleb128 0x40 + 1104 012d 18 .uleb128 0x18 + 1105 012e 9642 .uleb128 0x2116 + 1106 0130 19 .uleb128 0x19 + 1107 0131 01 .uleb128 0x1 + 1108 0132 13 .uleb128 0x13 + 1109 0133 00 .byte 0 + 1110 0134 00 .byte 0 + 1111 0135 15 .uleb128 0x15 + 1112 0136 0B .uleb128 0xb + 1113 0137 01 .byte 0x1 + 1114 0138 11 .uleb128 0x11 + 1115 0139 01 .uleb128 0x1 + 1116 013a 12 .uleb128 0x12 + 1117 013b 06 .uleb128 0x6 + 1118 013c 00 .byte 0 + 1119 013d 00 .byte 0 + 1120 013e 16 .uleb128 0x16 + 1121 013f 34 .uleb128 0x34 + 1122 0140 00 .byte 0 + 1123 0141 03 .uleb128 0x3 + 1124 0142 08 .uleb128 0x8 + 1125 0143 3A .uleb128 0x3a + 1126 0144 0B .uleb128 0xb + 1127 0145 3B .uleb128 0x3b + 1128 0146 05 .uleb128 0x5 + 1129 0147 49 .uleb128 0x49 + 1130 0148 13 .uleb128 0x13 + 1131 0149 02 .uleb128 0x2 + 1132 014a 18 .uleb128 0x18 + 1133 014b 00 .byte 0 + 1134 014c 00 .byte 0 + 1135 014d 17 .uleb128 0x17 + 1136 014e 2E .uleb128 0x2e + 1137 014f 00 .byte 0 + 1138 0150 3F .uleb128 0x3f + 1139 0151 19 .uleb128 0x19 + 1140 0152 03 .uleb128 0x3 + 1141 0153 0E .uleb128 0xe + 1142 0154 3A .uleb128 0x3a + 1143 0155 0B .uleb128 0xb + 1144 0156 3B .uleb128 0x3b + 1145 0157 05 .uleb128 0x5 + 1146 0158 27 .uleb128 0x27 + 1147 0159 19 .uleb128 0x19 + 1148 015a 11 .uleb128 0x11 + 1149 015b 01 .uleb128 0x1 + 1150 015c 12 .uleb128 0x12 + 1151 015d 06 .uleb128 0x6 + 1152 015e 40 .uleb128 0x40 + 1153 015f 18 .uleb128 0x18 + 1154 0160 9642 .uleb128 0x2116 + 1155 0162 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 31 + + + 1156 0163 00 .byte 0 + 1157 0164 00 .byte 0 + 1158 0165 18 .uleb128 0x18 + 1159 0166 2E .uleb128 0x2e + 1160 0167 01 .byte 0x1 + 1161 0168 3F .uleb128 0x3f + 1162 0169 19 .uleb128 0x19 + 1163 016a 03 .uleb128 0x3 + 1164 016b 0E .uleb128 0xe + 1165 016c 3A .uleb128 0x3a + 1166 016d 0B .uleb128 0xb + 1167 016e 3B .uleb128 0x3b + 1168 016f 05 .uleb128 0x5 + 1169 0170 27 .uleb128 0x27 + 1170 0171 19 .uleb128 0x19 + 1171 0172 11 .uleb128 0x11 + 1172 0173 01 .uleb128 0x1 + 1173 0174 12 .uleb128 0x12 + 1174 0175 06 .uleb128 0x6 + 1175 0176 40 .uleb128 0x40 + 1176 0177 18 .uleb128 0x18 + 1177 0178 9642 .uleb128 0x2116 + 1178 017a 19 .uleb128 0x19 + 1179 017b 01 .uleb128 0x1 + 1180 017c 13 .uleb128 0x13 + 1181 017d 00 .byte 0 + 1182 017e 00 .byte 0 + 1183 017f 19 .uleb128 0x19 + 1184 0180 34 .uleb128 0x34 + 1185 0181 00 .byte 0 + 1186 0182 03 .uleb128 0x3 + 1187 0183 0E .uleb128 0xe + 1188 0184 3A .uleb128 0x3a + 1189 0185 0B .uleb128 0xb + 1190 0186 3B .uleb128 0x3b + 1191 0187 0B .uleb128 0xb + 1192 0188 49 .uleb128 0x49 + 1193 0189 13 .uleb128 0x13 + 1194 018a 02 .uleb128 0x2 + 1195 018b 18 .uleb128 0x18 + 1196 018c 00 .byte 0 + 1197 018d 00 .byte 0 + 1198 018e 1A .uleb128 0x1a + 1199 018f 01 .uleb128 0x1 + 1200 0190 01 .byte 0x1 + 1201 0191 49 .uleb128 0x49 + 1202 0192 13 .uleb128 0x13 + 1203 0193 01 .uleb128 0x1 + 1204 0194 13 .uleb128 0x13 + 1205 0195 00 .byte 0 + 1206 0196 00 .byte 0 + 1207 0197 1B .uleb128 0x1b + 1208 0198 21 .uleb128 0x21 + 1209 0199 00 .byte 0 + 1210 019a 00 .byte 0 + 1211 019b 00 .byte 0 + 1212 019c 1C .uleb128 0x1c + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 32 + + + 1213 019d 34 .uleb128 0x34 + 1214 019e 00 .byte 0 + 1215 019f 03 .uleb128 0x3 + 1216 01a0 0E .uleb128 0xe + 1217 01a1 3A .uleb128 0x3a + 1218 01a2 0B .uleb128 0xb + 1219 01a3 3B .uleb128 0x3b + 1220 01a4 0B .uleb128 0xb + 1221 01a5 49 .uleb128 0x49 + 1222 01a6 13 .uleb128 0x13 + 1223 01a7 3F .uleb128 0x3f + 1224 01a8 19 .uleb128 0x19 + 1225 01a9 3C .uleb128 0x3c + 1226 01aa 19 .uleb128 0x19 + 1227 01ab 00 .byte 0 + 1228 01ac 00 .byte 0 + 1229 01ad 1D .uleb128 0x1d + 1230 01ae 21 .uleb128 0x21 + 1231 01af 00 .byte 0 + 1232 01b0 49 .uleb128 0x49 + 1233 01b1 13 .uleb128 0x13 + 1234 01b2 2F .uleb128 0x2f + 1235 01b3 0B .uleb128 0xb + 1236 01b4 00 .byte 0 + 1237 01b5 00 .byte 0 + 1238 01b6 1E .uleb128 0x1e + 1239 01b7 34 .uleb128 0x34 + 1240 01b8 00 .byte 0 + 1241 01b9 03 .uleb128 0x3 + 1242 01ba 0E .uleb128 0xe + 1243 01bb 3A .uleb128 0x3a + 1244 01bc 0B .uleb128 0xb + 1245 01bd 3B .uleb128 0x3b + 1246 01be 05 .uleb128 0x5 + 1247 01bf 49 .uleb128 0x49 + 1248 01c0 13 .uleb128 0x13 + 1249 01c1 3F .uleb128 0x3f + 1250 01c2 19 .uleb128 0x19 + 1251 01c3 02 .uleb128 0x2 + 1252 01c4 18 .uleb128 0x18 + 1253 01c5 00 .byte 0 + 1254 01c6 00 .byte 0 + 1255 01c7 00 .byte 0 + 1256 .section .debug_aranges,"",%progbits + 1257 0000 44000000 .4byte 0x44 + 1258 0004 0200 .2byte 0x2 + 1259 0006 00000000 .4byte .Ldebug_info0 + 1260 000a 04 .byte 0x4 + 1261 000b 00 .byte 0 + 1262 000c 0000 .2byte 0 + 1263 000e 0000 .2byte 0 + 1264 0010 00000000 .4byte .LFB0 + 1265 0014 14000000 .4byte .LFE0-.LFB0 + 1266 0018 00000000 .4byte .LFB1 + 1267 001c 14000000 .4byte .LFE1-.LFB1 + 1268 0020 00000000 .4byte .LFB2 + 1269 0024 54000000 .4byte .LFE2-.LFB2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 33 + + + 1270 0028 00000000 .4byte .LFB3 + 1271 002c 98000000 .4byte .LFE3-.LFB3 + 1272 0030 00000000 .4byte .LFB4 + 1273 0034 08000000 .4byte .LFE4-.LFB4 + 1274 0038 00000000 .4byte .LFB5 + 1275 003c 64000000 .4byte .LFE5-.LFB5 + 1276 0040 00000000 .4byte 0 + 1277 0044 00000000 .4byte 0 + 1278 .section .debug_ranges,"",%progbits + 1279 .Ldebug_ranges0: + 1280 0000 00000000 .4byte .LFB0 + 1281 0004 14000000 .4byte .LFE0 + 1282 0008 00000000 .4byte .LFB1 + 1283 000c 14000000 .4byte .LFE1 + 1284 0010 00000000 .4byte .LFB2 + 1285 0014 54000000 .4byte .LFE2 + 1286 0018 00000000 .4byte .LFB3 + 1287 001c 98000000 .4byte .LFE3 + 1288 0020 00000000 .4byte .LFB4 + 1289 0024 08000000 .4byte .LFE4 + 1290 0028 00000000 .4byte .LFB5 + 1291 002c 64000000 .4byte .LFE5 + 1292 0030 00000000 .4byte 0 + 1293 0034 00000000 .4byte 0 + 1294 .section .debug_line,"",%progbits + 1295 .Ldebug_line0: + 1296 0000 CB010000 .section .debug_str,"MS",%progbits,1 + 1296 0200C700 + 1296 00000201 + 1296 FB0E0D00 + 1296 01010101 + 1297 .LASF16: + 1298 0000 72656733 .ascii "reg32\000" + 1298 3200 + 1299 .LASF10: + 1300 0006 73697A65 .ascii "size_t\000" + 1300 5F7400 + 1301 .LASF39: + 1302 000d 43795261 .ascii "CyRamVectors\000" + 1302 6D566563 + 1302 746F7273 + 1302 00 + 1303 .LASF30: + 1304 001a 53746172 .ascii "Start_c\000" + 1304 745F6300 + 1305 .LASF34: + 1306 0022 636F756E .ascii "count\000" + 1306 7400 + 1307 .LASF29: + 1308 0028 68656170 .ascii "heapPointer\000" + 1308 506F696E + 1308 74657200 + 1309 .LASF3: + 1310 0034 73686F72 .ascii "short unsigned int\000" + 1310 7420756E + 1310 7369676E + 1310 65642069 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 34 + + + 1310 6E7400 + 1311 .LASF38: + 1312 0047 5F5F6379 .ascii "__cy_region_num\000" + 1312 5F726567 + 1312 696F6E5F + 1312 6E756D00 + 1313 .LASF20: + 1314 0057 696E6974 .ascii "init\000" + 1314 00 + 1315 .LASF26: + 1316 005c 73746174 .ascii "status\000" + 1316 757300 + 1317 .LASF23: + 1318 0063 7A65726F .ascii "zero_size\000" + 1318 5F73697A + 1318 6500 + 1319 .LASF43: + 1320 006d 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 1320 73657273 + 1320 5C6A6167 + 1320 756D6965 + 1320 6C5C446F + 1321 009b 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 1321 50536F43 + 1321 2D313031 + 1321 5C547261 + 1321 696E696E + 1322 .LASF32: + 1323 00c8 72707472 .ascii "rptr\000" + 1323 00 + 1324 .LASF13: + 1325 00cd 666C6F61 .ascii "float\000" + 1325 7400 + 1326 .LASF21: + 1327 00d3 64617461 .ascii "data\000" + 1327 00 + 1328 .LASF1: + 1329 00d8 756E7369 .ascii "unsigned char\000" + 1329 676E6564 + 1329 20636861 + 1329 7200 + 1330 .LASF28: + 1331 00e6 72657475 .ascii "returnValue\000" + 1331 726E5661 + 1331 6C756500 + 1332 .LASF40: + 1333 00f2 526F6D56 .ascii "RomVectors\000" + 1333 6563746F + 1333 727300 + 1334 .LASF5: + 1335 00fd 6C6F6E67 .ascii "long unsigned int\000" + 1335 20756E73 + 1335 69676E65 + 1335 6420696E + 1335 7400 + 1336 .LASF36: + 1337 010f 63795379 .ascii "cySysNoInitDataValid\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 35 + + + 1337 734E6F49 + 1337 6E697444 + 1337 61746156 + 1337 616C6964 + 1338 .LASF11: + 1339 0124 75696E74 .ascii "uint8\000" + 1339 3800 + 1340 .LASF46: + 1341 012a 52657365 .ascii "Reset\000" + 1341 7400 + 1342 .LASF41: + 1343 0130 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 1343 43313120 + 1343 352E342E + 1343 31203230 + 1343 31363036 + 1344 0163 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 1344 20726576 + 1344 6973696F + 1344 6E203233 + 1344 37373135 + 1345 0196 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 1345 66756E63 + 1345 74696F6E + 1345 2D736563 + 1345 74696F6E + 1346 .LASF24: + 1347 01be 5F657869 .ascii "_exit\000" + 1347 7400 + 1348 .LASF45: + 1349 01c4 496E7444 .ascii "IntDefaultHandler\000" + 1349 65666175 + 1349 6C744861 + 1349 6E646C65 + 1349 7200 + 1350 .LASF25: + 1351 01d6 5F736272 .ascii "_sbrk\000" + 1351 6B00 + 1352 .LASF14: + 1353 01dc 646F7562 .ascii "double\000" + 1353 6C6500 + 1354 .LASF47: + 1355 01e3 696E6974 .ascii "initialize_psoc\000" + 1355 69616C69 + 1355 7A655F70 + 1355 736F6300 + 1356 .LASF42: + 1357 01f3 47656E65 .ascii "Generated_Source\\PSoC4\\Cm0Start.c\000" + 1357 72617465 + 1357 645F536F + 1357 75726365 + 1357 5C50536F + 1358 .LASF12: + 1359 0215 75696E74 .ascii "uint32\000" + 1359 333200 + 1360 .LASF35: + 1361 021c 696E6465 .ascii "indexInit\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 36 + + + 1361 78496E69 + 1361 7400 + 1362 .LASF8: + 1363 0226 756E7369 .ascii "unsigned int\000" + 1363 676E6564 + 1363 20696E74 + 1363 00 + 1364 .LASF7: + 1365 0233 6C6F6E67 .ascii "long long unsigned int\000" + 1365 206C6F6E + 1365 6720756E + 1365 7369676E + 1365 65642069 + 1366 .LASF33: + 1367 024a 6C696D69 .ascii "limit\000" + 1367 7400 + 1368 .LASF17: + 1369 0250 63796973 .ascii "cyisraddress\000" + 1369 72616464 + 1369 72657373 + 1369 00 + 1370 .LASF22: + 1371 025d 696E6974 .ascii "init_size\000" + 1371 5F73697A + 1371 6500 + 1372 .LASF19: + 1373 0267 5F5F6379 .ascii "__cy_byte_align8\000" + 1373 5F627974 + 1373 655F616C + 1373 69676E38 + 1373 00 + 1374 .LASF18: + 1375 0278 73697A65 .ascii "sizetype\000" + 1375 74797065 + 1375 00 + 1376 .LASF6: + 1377 0281 6C6F6E67 .ascii "long long int\000" + 1377 206C6F6E + 1377 6720696E + 1377 7400 + 1378 .LASF15: + 1379 028f 63686172 .ascii "char\000" + 1379 00 + 1380 .LASF2: + 1381 0294 73686F72 .ascii "short int\000" + 1381 7420696E + 1381 7400 + 1382 .LASF4: + 1383 029e 6C6F6E67 .ascii "long int\000" + 1383 20696E74 + 1383 00 + 1384 .LASF9: + 1385 02a7 6C6F6E67 .ascii "long double\000" + 1385 20646F75 + 1385 626C6500 + 1386 .LASF0: + 1387 02b3 7369676E .ascii "signed char\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cci2g6Lj.s page 37 + + + 1387 65642063 + 1387 68617200 + 1388 .LASF37: + 1389 02bf 5F5F6379 .ascii "__cy_regions\000" + 1389 5F726567 + 1389 696F6E73 + 1389 00 + 1390 .LASF31: + 1391 02cc 72656769 .ascii "regions\000" + 1391 6F6E7300 + 1392 .LASF27: + 1393 02d4 6E627974 .ascii "nbytes\000" + 1393 657300 + 1394 .LASF44: + 1395 02db 5F5F6379 .ascii "__cy_region\000" + 1395 5F726567 + 1395 696F6E00 + 1396 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/Cm0Start.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/Cm0Start.o new file mode 100644 index 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/***************************************************************************//** + 2 * \file CyBootAsmGnu.s + 3 * \version 5.70 + 4 * + 5 * \brief Assembly routines for GNU as. + 6 * + 7 ******************************************************************************** + 8 * \copyright + 9 * Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. + 10 * You may use this file only in accordance with the license, terms, conditions, + 11 * disclaimers, and limitations in the end user license agreement accompanying + 12 * the software package with which this file was provided. + 13 *******************************************************************************/ + 14 + 15 .syntax unified + 16 .text + 17 .thumb + 18 .include "cyfittergnu.inc" + 1 /******************************************************************************* + 2 * File Name: cyfittergnu.inc + 3 * + 4 * PSoC Creator 4.2 + 5 * + 6 * Description: + 7 * + 8 * This file is automatically generated by PSoC Creator. + 9 * + 10 ******************************************************************************** + 11 * Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. + 12 * You may use this file only in accordance with the license, terms, conditions, + 13 * disclaimers, and limitations in the end user license agreement accompanying + 14 * the software package with which this file was provided. + 15 ********************************************************************************/ + 16 + 17 .ifndef INCLUDED_CYFITTERGNU_INC + 18 .set INCLUDED_CYFITTERGNU_INC, 1 + 19 .include "cydevicegnu_trm.inc" + 1 /******************************************************************************* + 2 * File Name: cydevicegnu_trm.inc + 3 * + 4 * PSoC Creator 4.2 + 5 * + 6 * Description: + 7 * This file provides all of the address values for the entire PSoC device. + 8 * This file is automatically generated by PSoC Creator. + 9 * + 10 ******************************************************************************** + 11 * Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. + 12 * You may use this file only in accordance with the license, terms, conditions, + 13 * disclaimers, and limitations in the end user license agreement accompanying + 14 * the software package with which this file was provided. + 15 ********************************************************************************/ + 16 + 17 .set CYDEV_FLASH_BASE, 0x00000000 + 18 .set CYDEV_FLASH_SIZE, 0x00008000 + 19 .set CYREG_FLASH_DATA_MBASE, 0x00000000 + 20 .set CYREG_FLASH_DATA_MSIZE, 0x00008000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 2 + + + 21 .set CYDEV_SFLASH_BASE, 0x0ffff000 + 22 .set CYDEV_SFLASH_SIZE, 0x00000200 + 23 .set CYREG_SFLASH_PROT_ROW00, 0x0ffff000 + 24 .set CYFLD_SFLASH_DATA8__OFFSET, 0x00000000 + 25 .set CYFLD_SFLASH_DATA8__SIZE, 0x00000008 + 26 .set CYREG_SFLASH_PROT_ROW01, 0x0ffff001 + 27 .set CYREG_SFLASH_PROT_ROW02, 0x0ffff002 + 28 .set CYREG_SFLASH_PROT_ROW03, 0x0ffff003 + 29 .set CYREG_SFLASH_PROT_ROW04, 0x0ffff004 + 30 .set CYREG_SFLASH_PROT_ROW05, 0x0ffff005 + 31 .set CYREG_SFLASH_PROT_ROW06, 0x0ffff006 + 32 .set CYREG_SFLASH_PROT_ROW07, 0x0ffff007 + 33 .set CYREG_SFLASH_PROT_ROW08, 0x0ffff008 + 34 .set CYREG_SFLASH_PROT_ROW09, 0x0ffff009 + 35 .set CYREG_SFLASH_PROT_ROW10, 0x0ffff00a + 36 .set CYREG_SFLASH_PROT_ROW11, 0x0ffff00b + 37 .set CYREG_SFLASH_PROT_ROW12, 0x0ffff00c + 38 .set CYREG_SFLASH_PROT_ROW13, 0x0ffff00d + 39 .set CYREG_SFLASH_PROT_ROW14, 0x0ffff00e + 40 .set CYREG_SFLASH_PROT_ROW15, 0x0ffff00f + 41 .set CYREG_SFLASH_PROT_ROW16, 0x0ffff010 + 42 .set CYREG_SFLASH_PROT_ROW17, 0x0ffff011 + 43 .set CYREG_SFLASH_PROT_ROW18, 0x0ffff012 + 44 .set CYREG_SFLASH_PROT_ROW19, 0x0ffff013 + 45 .set CYREG_SFLASH_PROT_ROW20, 0x0ffff014 + 46 .set CYREG_SFLASH_PROT_ROW21, 0x0ffff015 + 47 .set CYREG_SFLASH_PROT_ROW22, 0x0ffff016 + 48 .set CYREG_SFLASH_PROT_ROW23, 0x0ffff017 + 49 .set CYREG_SFLASH_PROT_ROW24, 0x0ffff018 + 50 .set CYREG_SFLASH_PROT_ROW25, 0x0ffff019 + 51 .set CYREG_SFLASH_PROT_ROW26, 0x0ffff01a + 52 .set CYREG_SFLASH_PROT_ROW27, 0x0ffff01b + 53 .set CYREG_SFLASH_PROT_ROW28, 0x0ffff01c + 54 .set CYREG_SFLASH_PROT_ROW29, 0x0ffff01d + 55 .set CYREG_SFLASH_PROT_ROW30, 0x0ffff01e + 56 .set CYREG_SFLASH_PROT_ROW31, 0x0ffff01f + 57 .set CYREG_SFLASH_PROT_ROW32, 0x0ffff020 + 58 .set CYREG_SFLASH_PROT_ROW33, 0x0ffff021 + 59 .set CYREG_SFLASH_PROT_ROW34, 0x0ffff022 + 60 .set CYREG_SFLASH_PROT_ROW35, 0x0ffff023 + 61 .set CYREG_SFLASH_PROT_ROW36, 0x0ffff024 + 62 .set CYREG_SFLASH_PROT_ROW37, 0x0ffff025 + 63 .set CYREG_SFLASH_PROT_ROW38, 0x0ffff026 + 64 .set CYREG_SFLASH_PROT_ROW39, 0x0ffff027 + 65 .set CYREG_SFLASH_PROT_ROW40, 0x0ffff028 + 66 .set CYREG_SFLASH_PROT_ROW41, 0x0ffff029 + 67 .set CYREG_SFLASH_PROT_ROW42, 0x0ffff02a + 68 .set CYREG_SFLASH_PROT_ROW43, 0x0ffff02b + 69 .set CYREG_SFLASH_PROT_ROW44, 0x0ffff02c + 70 .set CYREG_SFLASH_PROT_ROW45, 0x0ffff02d + 71 .set CYREG_SFLASH_PROT_ROW46, 0x0ffff02e + 72 .set CYREG_SFLASH_PROT_ROW47, 0x0ffff02f + 73 .set CYREG_SFLASH_PROT_ROW48, 0x0ffff030 + 74 .set CYREG_SFLASH_PROT_ROW49, 0x0ffff031 + 75 .set CYREG_SFLASH_PROT_ROW50, 0x0ffff032 + 76 .set CYREG_SFLASH_PROT_ROW51, 0x0ffff033 + 77 .set CYREG_SFLASH_PROT_ROW52, 0x0ffff034 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 3 + + + 78 .set CYREG_SFLASH_PROT_ROW53, 0x0ffff035 + 79 .set CYREG_SFLASH_PROT_ROW54, 0x0ffff036 + 80 .set CYREG_SFLASH_PROT_ROW55, 0x0ffff037 + 81 .set CYREG_SFLASH_PROT_ROW56, 0x0ffff038 + 82 .set CYREG_SFLASH_PROT_ROW57, 0x0ffff039 + 83 .set CYREG_SFLASH_PROT_ROW58, 0x0ffff03a + 84 .set CYREG_SFLASH_PROT_ROW59, 0x0ffff03b + 85 .set CYREG_SFLASH_PROT_ROW60, 0x0ffff03c + 86 .set CYREG_SFLASH_PROT_ROW61, 0x0ffff03d + 87 .set CYREG_SFLASH_PROT_ROW62, 0x0ffff03e + 88 .set CYREG_SFLASH_PROT_ROW63, 0x0ffff03f + 89 .set CYREG_SFLASH_PROT_PROTECTION, 0x0ffff07f + 90 .set CYFLD_SFLASH_PROT_LEVEL__OFFSET, 0x00000000 + 91 .set CYFLD_SFLASH_PROT_LEVEL__SIZE, 0x00000002 + 92 .set CYVAL_SFLASH_PROT_LEVEL_VIRGIN, 0x00000001 + 93 .set CYVAL_SFLASH_PROT_LEVEL_OPEN, 0x00000000 + 94 .set CYVAL_SFLASH_PROT_LEVEL_PROTECTED, 0x00000002 + 95 .set CYVAL_SFLASH_PROT_LEVEL_KILL, 0x00000003 + 96 .set CYREG_SFLASH_AV_PAIRS_8B000, 0x0ffff080 + 97 .set CYREG_SFLASH_AV_PAIRS_8B001, 0x0ffff081 + 98 .set CYREG_SFLASH_AV_PAIRS_8B002, 0x0ffff082 + 99 .set CYREG_SFLASH_AV_PAIRS_8B003, 0x0ffff083 + 100 .set CYREG_SFLASH_AV_PAIRS_8B004, 0x0ffff084 + 101 .set CYREG_SFLASH_AV_PAIRS_8B005, 0x0ffff085 + 102 .set CYREG_SFLASH_AV_PAIRS_8B006, 0x0ffff086 + 103 .set CYREG_SFLASH_AV_PAIRS_8B007, 0x0ffff087 + 104 .set CYREG_SFLASH_AV_PAIRS_8B008, 0x0ffff088 + 105 .set CYREG_SFLASH_AV_PAIRS_8B009, 0x0ffff089 + 106 .set CYREG_SFLASH_AV_PAIRS_8B010, 0x0ffff08a + 107 .set CYREG_SFLASH_AV_PAIRS_8B011, 0x0ffff08b + 108 .set CYREG_SFLASH_AV_PAIRS_8B012, 0x0ffff08c + 109 .set CYREG_SFLASH_AV_PAIRS_8B013, 0x0ffff08d + 110 .set CYREG_SFLASH_AV_PAIRS_8B014, 0x0ffff08e + 111 .set CYREG_SFLASH_AV_PAIRS_8B015, 0x0ffff08f + 112 .set CYREG_SFLASH_AV_PAIRS_8B016, 0x0ffff090 + 113 .set CYREG_SFLASH_AV_PAIRS_8B017, 0x0ffff091 + 114 .set CYREG_SFLASH_AV_PAIRS_8B018, 0x0ffff092 + 115 .set CYREG_SFLASH_AV_PAIRS_8B019, 0x0ffff093 + 116 .set CYREG_SFLASH_AV_PAIRS_8B020, 0x0ffff094 + 117 .set CYREG_SFLASH_AV_PAIRS_8B021, 0x0ffff095 + 118 .set CYREG_SFLASH_AV_PAIRS_8B022, 0x0ffff096 + 119 .set CYREG_SFLASH_AV_PAIRS_8B023, 0x0ffff097 + 120 .set CYREG_SFLASH_AV_PAIRS_8B024, 0x0ffff098 + 121 .set CYREG_SFLASH_AV_PAIRS_8B025, 0x0ffff099 + 122 .set CYREG_SFLASH_AV_PAIRS_8B026, 0x0ffff09a + 123 .set CYREG_SFLASH_AV_PAIRS_8B027, 0x0ffff09b + 124 .set CYREG_SFLASH_AV_PAIRS_8B028, 0x0ffff09c + 125 .set CYREG_SFLASH_AV_PAIRS_8B029, 0x0ffff09d + 126 .set CYREG_SFLASH_AV_PAIRS_8B030, 0x0ffff09e + 127 .set CYREG_SFLASH_AV_PAIRS_8B031, 0x0ffff09f + 128 .set CYREG_SFLASH_AV_PAIRS_8B032, 0x0ffff0a0 + 129 .set CYREG_SFLASH_AV_PAIRS_8B033, 0x0ffff0a1 + 130 .set CYREG_SFLASH_AV_PAIRS_8B034, 0x0ffff0a2 + 131 .set CYREG_SFLASH_AV_PAIRS_8B035, 0x0ffff0a3 + 132 .set CYREG_SFLASH_AV_PAIRS_8B036, 0x0ffff0a4 + 133 .set CYREG_SFLASH_AV_PAIRS_8B037, 0x0ffff0a5 + 134 .set CYREG_SFLASH_AV_PAIRS_8B038, 0x0ffff0a6 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 4 + + + 135 .set CYREG_SFLASH_AV_PAIRS_8B039, 0x0ffff0a7 + 136 .set CYREG_SFLASH_AV_PAIRS_8B040, 0x0ffff0a8 + 137 .set CYREG_SFLASH_AV_PAIRS_8B041, 0x0ffff0a9 + 138 .set CYREG_SFLASH_AV_PAIRS_8B042, 0x0ffff0aa + 139 .set CYREG_SFLASH_AV_PAIRS_8B043, 0x0ffff0ab + 140 .set CYREG_SFLASH_AV_PAIRS_8B044, 0x0ffff0ac + 141 .set CYREG_SFLASH_AV_PAIRS_8B045, 0x0ffff0ad + 142 .set CYREG_SFLASH_AV_PAIRS_8B046, 0x0ffff0ae + 143 .set CYREG_SFLASH_AV_PAIRS_8B047, 0x0ffff0af + 144 .set CYREG_SFLASH_AV_PAIRS_8B048, 0x0ffff0b0 + 145 .set CYREG_SFLASH_AV_PAIRS_8B049, 0x0ffff0b1 + 146 .set CYREG_SFLASH_AV_PAIRS_8B050, 0x0ffff0b2 + 147 .set CYREG_SFLASH_AV_PAIRS_8B051, 0x0ffff0b3 + 148 .set CYREG_SFLASH_AV_PAIRS_8B052, 0x0ffff0b4 + 149 .set CYREG_SFLASH_AV_PAIRS_8B053, 0x0ffff0b5 + 150 .set CYREG_SFLASH_AV_PAIRS_8B054, 0x0ffff0b6 + 151 .set CYREG_SFLASH_AV_PAIRS_8B055, 0x0ffff0b7 + 152 .set CYREG_SFLASH_AV_PAIRS_8B056, 0x0ffff0b8 + 153 .set CYREG_SFLASH_AV_PAIRS_8B057, 0x0ffff0b9 + 154 .set CYREG_SFLASH_AV_PAIRS_8B058, 0x0ffff0ba + 155 .set CYREG_SFLASH_AV_PAIRS_8B059, 0x0ffff0bb + 156 .set CYREG_SFLASH_AV_PAIRS_8B060, 0x0ffff0bc + 157 .set CYREG_SFLASH_AV_PAIRS_8B061, 0x0ffff0bd + 158 .set CYREG_SFLASH_AV_PAIRS_8B062, 0x0ffff0be + 159 .set CYREG_SFLASH_AV_PAIRS_8B063, 0x0ffff0bf + 160 .set CYREG_SFLASH_AV_PAIRS_8B064, 0x0ffff0c0 + 161 .set CYREG_SFLASH_AV_PAIRS_8B065, 0x0ffff0c1 + 162 .set CYREG_SFLASH_AV_PAIRS_8B066, 0x0ffff0c2 + 163 .set CYREG_SFLASH_AV_PAIRS_8B067, 0x0ffff0c3 + 164 .set CYREG_SFLASH_AV_PAIRS_8B068, 0x0ffff0c4 + 165 .set CYREG_SFLASH_AV_PAIRS_8B069, 0x0ffff0c5 + 166 .set CYREG_SFLASH_AV_PAIRS_8B070, 0x0ffff0c6 + 167 .set CYREG_SFLASH_AV_PAIRS_8B071, 0x0ffff0c7 + 168 .set CYREG_SFLASH_AV_PAIRS_8B072, 0x0ffff0c8 + 169 .set CYREG_SFLASH_AV_PAIRS_8B073, 0x0ffff0c9 + 170 .set CYREG_SFLASH_AV_PAIRS_8B074, 0x0ffff0ca + 171 .set CYREG_SFLASH_AV_PAIRS_8B075, 0x0ffff0cb + 172 .set CYREG_SFLASH_AV_PAIRS_8B076, 0x0ffff0cc + 173 .set CYREG_SFLASH_AV_PAIRS_8B077, 0x0ffff0cd + 174 .set CYREG_SFLASH_AV_PAIRS_8B078, 0x0ffff0ce + 175 .set CYREG_SFLASH_AV_PAIRS_8B079, 0x0ffff0cf + 176 .set CYREG_SFLASH_AV_PAIRS_8B080, 0x0ffff0d0 + 177 .set CYREG_SFLASH_AV_PAIRS_8B081, 0x0ffff0d1 + 178 .set CYREG_SFLASH_AV_PAIRS_8B082, 0x0ffff0d2 + 179 .set CYREG_SFLASH_AV_PAIRS_8B083, 0x0ffff0d3 + 180 .set CYREG_SFLASH_AV_PAIRS_8B084, 0x0ffff0d4 + 181 .set CYREG_SFLASH_AV_PAIRS_8B085, 0x0ffff0d5 + 182 .set CYREG_SFLASH_AV_PAIRS_8B086, 0x0ffff0d6 + 183 .set CYREG_SFLASH_AV_PAIRS_8B087, 0x0ffff0d7 + 184 .set CYREG_SFLASH_AV_PAIRS_8B088, 0x0ffff0d8 + 185 .set CYREG_SFLASH_AV_PAIRS_8B089, 0x0ffff0d9 + 186 .set CYREG_SFLASH_AV_PAIRS_8B090, 0x0ffff0da + 187 .set CYREG_SFLASH_AV_PAIRS_8B091, 0x0ffff0db + 188 .set CYREG_SFLASH_AV_PAIRS_8B092, 0x0ffff0dc + 189 .set CYREG_SFLASH_AV_PAIRS_8B093, 0x0ffff0dd + 190 .set CYREG_SFLASH_AV_PAIRS_8B094, 0x0ffff0de + 191 .set CYREG_SFLASH_AV_PAIRS_8B095, 0x0ffff0df + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 5 + + + 192 .set CYREG_SFLASH_AV_PAIRS_8B096, 0x0ffff0e0 + 193 .set CYREG_SFLASH_AV_PAIRS_8B097, 0x0ffff0e1 + 194 .set CYREG_SFLASH_AV_PAIRS_8B098, 0x0ffff0e2 + 195 .set CYREG_SFLASH_AV_PAIRS_8B099, 0x0ffff0e3 + 196 .set CYREG_SFLASH_AV_PAIRS_8B100, 0x0ffff0e4 + 197 .set CYREG_SFLASH_AV_PAIRS_8B101, 0x0ffff0e5 + 198 .set CYREG_SFLASH_AV_PAIRS_8B102, 0x0ffff0e6 + 199 .set CYREG_SFLASH_AV_PAIRS_8B103, 0x0ffff0e7 + 200 .set CYREG_SFLASH_AV_PAIRS_8B104, 0x0ffff0e8 + 201 .set CYREG_SFLASH_AV_PAIRS_8B105, 0x0ffff0e9 + 202 .set CYREG_SFLASH_AV_PAIRS_8B106, 0x0ffff0ea + 203 .set CYREG_SFLASH_AV_PAIRS_8B107, 0x0ffff0eb + 204 .set CYREG_SFLASH_AV_PAIRS_8B108, 0x0ffff0ec + 205 .set CYREG_SFLASH_AV_PAIRS_8B109, 0x0ffff0ed + 206 .set CYREG_SFLASH_AV_PAIRS_8B110, 0x0ffff0ee + 207 .set CYREG_SFLASH_AV_PAIRS_8B111, 0x0ffff0ef + 208 .set CYREG_SFLASH_AV_PAIRS_8B112, 0x0ffff0f0 + 209 .set CYREG_SFLASH_AV_PAIRS_8B113, 0x0ffff0f1 + 210 .set CYREG_SFLASH_AV_PAIRS_8B114, 0x0ffff0f2 + 211 .set CYREG_SFLASH_AV_PAIRS_8B115, 0x0ffff0f3 + 212 .set CYREG_SFLASH_AV_PAIRS_8B116, 0x0ffff0f4 + 213 .set CYREG_SFLASH_AV_PAIRS_8B117, 0x0ffff0f5 + 214 .set CYREG_SFLASH_AV_PAIRS_8B118, 0x0ffff0f6 + 215 .set CYREG_SFLASH_AV_PAIRS_8B119, 0x0ffff0f7 + 216 .set CYREG_SFLASH_AV_PAIRS_8B120, 0x0ffff0f8 + 217 .set CYREG_SFLASH_AV_PAIRS_8B121, 0x0ffff0f9 + 218 .set CYREG_SFLASH_AV_PAIRS_8B122, 0x0ffff0fa + 219 .set CYREG_SFLASH_AV_PAIRS_8B123, 0x0ffff0fb + 220 .set CYREG_SFLASH_AV_PAIRS_8B124, 0x0ffff0fc + 221 .set CYREG_SFLASH_AV_PAIRS_8B125, 0x0ffff0fd + 222 .set CYREG_SFLASH_AV_PAIRS_8B126, 0x0ffff0fe + 223 .set CYREG_SFLASH_AV_PAIRS_8B127, 0x0ffff0ff + 224 .set CYREG_SFLASH_AV_PAIRS_32B00, 0x0ffff100 + 225 .set CYFLD_SFLASH_DATA32__OFFSET, 0x00000000 + 226 .set CYFLD_SFLASH_DATA32__SIZE, 0x00000020 + 227 .set CYREG_SFLASH_AV_PAIRS_32B01, 0x0ffff104 + 228 .set CYREG_SFLASH_AV_PAIRS_32B02, 0x0ffff108 + 229 .set CYREG_SFLASH_AV_PAIRS_32B03, 0x0ffff10c + 230 .set CYREG_SFLASH_AV_PAIRS_32B04, 0x0ffff110 + 231 .set CYREG_SFLASH_AV_PAIRS_32B05, 0x0ffff114 + 232 .set CYREG_SFLASH_AV_PAIRS_32B06, 0x0ffff118 + 233 .set CYREG_SFLASH_AV_PAIRS_32B07, 0x0ffff11c + 234 .set CYREG_SFLASH_AV_PAIRS_32B08, 0x0ffff120 + 235 .set CYREG_SFLASH_AV_PAIRS_32B09, 0x0ffff124 + 236 .set CYREG_SFLASH_AV_PAIRS_32B10, 0x0ffff128 + 237 .set CYREG_SFLASH_AV_PAIRS_32B11, 0x0ffff12c + 238 .set CYREG_SFLASH_AV_PAIRS_32B12, 0x0ffff130 + 239 .set CYREG_SFLASH_AV_PAIRS_32B13, 0x0ffff134 + 240 .set CYREG_SFLASH_AV_PAIRS_32B14, 0x0ffff138 + 241 .set CYREG_SFLASH_AV_PAIRS_32B15, 0x0ffff13c + 242 .set CYREG_SFLASH_CPUSS_WOUNDING, 0x0ffff140 + 243 .set CYREG_SFLASH_SILICON_ID, 0x0ffff144 + 244 .set CYFLD_SFLASH_ID__OFFSET, 0x00000000 + 245 .set CYFLD_SFLASH_ID__SIZE, 0x00000010 + 246 .set CYREG_SFLASH_CPUSS_PRIV_RAM, 0x0ffff148 + 247 .set CYREG_SFLASH_CPUSS_PRIV_FLASH, 0x0ffff14c + 248 .set CYREG_SFLASH_HIB_KEY_DELAY, 0x0ffff150 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 6 + + + 249 .set CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET, 0x00000000 + 250 .set CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE, 0x0000000a + 251 .set CYREG_SFLASH_DPSLP_KEY_DELAY, 0x0ffff152 + 252 .set CYREG_SFLASH_SWD_CONFIG, 0x0ffff154 + 253 .set CYFLD_SFLASH_SWD_SELECT__OFFSET, 0x00000000 + 254 .set CYFLD_SFLASH_SWD_SELECT__SIZE, 0x00000001 + 255 .set CYREG_SFLASH_SWD_LISTEN, 0x0ffff158 + 256 .set CYFLD_SFLASH_CYCLES__OFFSET, 0x00000000 + 257 .set CYFLD_SFLASH_CYCLES__SIZE, 0x00000020 + 258 .set CYREG_SFLASH_FLASH_START, 0x0ffff15c + 259 .set CYFLD_SFLASH_ADDRESS__OFFSET, 0x00000000 + 260 .set CYFLD_SFLASH_ADDRESS__SIZE, 0x00000020 + 261 .set CYREG_SFLASH_CSD_TRIM1_HVIDAC, 0x0ffff160 + 262 .set CYFLD_SFLASH_TRIM8__OFFSET, 0x00000000 + 263 .set CYFLD_SFLASH_TRIM8__SIZE, 0x00000008 + 264 .set CYREG_SFLASH_CSD_TRIM2_HVIDAC, 0x0ffff161 + 265 .set CYREG_SFLASH_CSD_TRIM1_CSD, 0x0ffff162 + 266 .set CYREG_SFLASH_CSD_TRIM2_CSD, 0x0ffff163 + 267 .set CYREG_SFLASH_SAR_TEMP_MULTIPLIER, 0x0ffff164 + 268 .set CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET, 0x00000000 + 269 .set CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE, 0x00000010 + 270 .set CYREG_SFLASH_SAR_TEMP_OFFSET, 0x0ffff166 + 271 .set CYFLD_SFLASH_TEMP_OFFSET__OFFSET, 0x00000000 + 272 .set CYFLD_SFLASH_TEMP_OFFSET__SIZE, 0x00000010 + 273 .set CYREG_SFLASH_SKIP_CHECKSUM, 0x0ffff169 + 274 .set CYFLD_SFLASH_SKIP__OFFSET, 0x00000000 + 275 .set CYFLD_SFLASH_SKIP__SIZE, 0x00000008 + 276 .set CYREG_SFLASH_PROT_VIRGINKEY0, 0x0ffff170 + 277 .set CYFLD_SFLASH_KEY8__OFFSET, 0x00000000 + 278 .set CYFLD_SFLASH_KEY8__SIZE, 0x00000008 + 279 .set CYREG_SFLASH_PROT_VIRGINKEY1, 0x0ffff171 + 280 .set CYREG_SFLASH_PROT_VIRGINKEY2, 0x0ffff172 + 281 .set CYREG_SFLASH_PROT_VIRGINKEY3, 0x0ffff173 + 282 .set CYREG_SFLASH_PROT_VIRGINKEY4, 0x0ffff174 + 283 .set CYREG_SFLASH_PROT_VIRGINKEY5, 0x0ffff175 + 284 .set CYREG_SFLASH_PROT_VIRGINKEY6, 0x0ffff176 + 285 .set CYREG_SFLASH_PROT_VIRGINKEY7, 0x0ffff177 + 286 .set CYREG_SFLASH_DIE_LOT0, 0x0ffff178 + 287 .set CYFLD_SFLASH_LOT__OFFSET, 0x00000000 + 288 .set CYFLD_SFLASH_LOT__SIZE, 0x00000008 + 289 .set CYREG_SFLASH_DIE_LOT1, 0x0ffff179 + 290 .set CYREG_SFLASH_DIE_LOT2, 0x0ffff17a + 291 .set CYREG_SFLASH_DIE_WAFER, 0x0ffff17b + 292 .set CYFLD_SFLASH_WAFER__OFFSET, 0x00000000 + 293 .set CYFLD_SFLASH_WAFER__SIZE, 0x00000008 + 294 .set CYREG_SFLASH_DIE_X, 0x0ffff17c + 295 .set CYFLD_SFLASH_X__OFFSET, 0x00000000 + 296 .set CYFLD_SFLASH_X__SIZE, 0x00000006 + 297 .set CYFLD_SFLASH_CRI_PASS__OFFSET, 0x00000006 + 298 .set CYFLD_SFLASH_CRI_PASS__SIZE, 0x00000002 + 299 .set CYREG_SFLASH_DIE_Y, 0x0ffff17d + 300 .set CYFLD_SFLASH_Y__OFFSET, 0x00000000 + 301 .set CYFLD_SFLASH_Y__SIZE, 0x00000006 + 302 .set CYFLD_SFLASH_CHI_PASS__OFFSET, 0x00000006 + 303 .set CYFLD_SFLASH_CHI_PASS__SIZE, 0x00000002 + 304 .set CYREG_SFLASH_DIE_SORT, 0x0ffff17e + 305 .set CYFLD_SFLASH_S1_PASS__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 7 + + + 306 .set CYFLD_SFLASH_S1_PASS__SIZE, 0x00000002 + 307 .set CYFLD_SFLASH_S2_PASS__OFFSET, 0x00000002 + 308 .set CYFLD_SFLASH_S2_PASS__SIZE, 0x00000002 + 309 .set CYFLD_SFLASH_S3_PASS__OFFSET, 0x00000004 + 310 .set CYFLD_SFLASH_S3_PASS__SIZE, 0x00000002 + 311 .set CYREG_SFLASH_DIE_MINOR, 0x0ffff17f + 312 .set CYFLD_SFLASH_MINOR__OFFSET, 0x00000000 + 313 .set CYFLD_SFLASH_MINOR__SIZE, 0x00000008 + 314 .set CYREG_SFLASH_PE_TE_DATA00, 0x0ffff180 + 315 .set CYREG_SFLASH_PE_TE_DATA01, 0x0ffff181 + 316 .set CYREG_SFLASH_PE_TE_DATA02, 0x0ffff182 + 317 .set CYREG_SFLASH_PE_TE_DATA03, 0x0ffff183 + 318 .set CYREG_SFLASH_PE_TE_DATA04, 0x0ffff184 + 319 .set CYREG_SFLASH_PE_TE_DATA05, 0x0ffff185 + 320 .set CYREG_SFLASH_PE_TE_DATA06, 0x0ffff186 + 321 .set CYREG_SFLASH_PE_TE_DATA07, 0x0ffff187 + 322 .set CYREG_SFLASH_PE_TE_DATA08, 0x0ffff188 + 323 .set CYREG_SFLASH_PE_TE_DATA09, 0x0ffff189 + 324 .set CYREG_SFLASH_PE_TE_DATA10, 0x0ffff18a + 325 .set CYREG_SFLASH_PE_TE_DATA11, 0x0ffff18b + 326 .set CYREG_SFLASH_PE_TE_DATA12, 0x0ffff18c + 327 .set CYREG_SFLASH_PE_TE_DATA13, 0x0ffff18d + 328 .set CYREG_SFLASH_PE_TE_DATA14, 0x0ffff18e + 329 .set CYREG_SFLASH_PE_TE_DATA15, 0x0ffff18f + 330 .set CYREG_SFLASH_PE_TE_DATA16, 0x0ffff190 + 331 .set CYREG_SFLASH_PE_TE_DATA17, 0x0ffff191 + 332 .set CYREG_SFLASH_PE_TE_DATA18, 0x0ffff192 + 333 .set CYREG_SFLASH_PE_TE_DATA19, 0x0ffff193 + 334 .set CYREG_SFLASH_PE_TE_DATA20, 0x0ffff194 + 335 .set CYREG_SFLASH_PE_TE_DATA21, 0x0ffff195 + 336 .set CYREG_SFLASH_PE_TE_DATA22, 0x0ffff196 + 337 .set CYREG_SFLASH_PE_TE_DATA23, 0x0ffff197 + 338 .set CYREG_SFLASH_PE_TE_DATA24, 0x0ffff198 + 339 .set CYREG_SFLASH_PE_TE_DATA25, 0x0ffff199 + 340 .set CYREG_SFLASH_PE_TE_DATA26, 0x0ffff19a + 341 .set CYREG_SFLASH_PE_TE_DATA27, 0x0ffff19b + 342 .set CYREG_SFLASH_PE_TE_DATA28, 0x0ffff19c + 343 .set CYREG_SFLASH_PE_TE_DATA29, 0x0ffff19d + 344 .set CYREG_SFLASH_PE_TE_DATA30, 0x0ffff19e + 345 .set CYREG_SFLASH_PE_TE_DATA31, 0x0ffff19f + 346 .set CYREG_SFLASH_PP, 0x0ffff1a0 + 347 .set CYFLD_SFLASH_PERIOD__OFFSET, 0x00000000 + 348 .set CYFLD_SFLASH_PERIOD__SIZE, 0x00000018 + 349 .set CYFLD_SFLASH_PDAC__OFFSET, 0x00000018 + 350 .set CYFLD_SFLASH_PDAC__SIZE, 0x00000004 + 351 .set CYFLD_SFLASH_NDAC__OFFSET, 0x0000001c + 352 .set CYFLD_SFLASH_NDAC__SIZE, 0x00000004 + 353 .set CYREG_SFLASH_E, 0x0ffff1a4 + 354 .set CYREG_SFLASH_P, 0x0ffff1a8 + 355 .set CYREG_SFLASH_EA_E, 0x0ffff1ac + 356 .set CYREG_SFLASH_EA_P, 0x0ffff1b0 + 357 .set CYREG_SFLASH_ES_E, 0x0ffff1b4 + 358 .set CYREG_SFLASH_ES_P_EO, 0x0ffff1b8 + 359 .set CYREG_SFLASH_E_VCTAT, 0x0ffff1bc + 360 .set CYFLD_SFLASH_VCTAT_SLOPE__OFFSET, 0x00000000 + 361 .set CYFLD_SFLASH_VCTAT_SLOPE__SIZE, 0x00000004 + 362 .set CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET, 0x00000004 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 8 + + + 363 .set CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE, 0x00000002 + 364 .set CYFLD_SFLASH_VCTAT_ENABLE__OFFSET, 0x00000006 + 365 .set CYFLD_SFLASH_VCTAT_ENABLE__SIZE, 0x00000001 + 366 .set CYREG_SFLASH_P_VCTAT, 0x0ffff1bd + 367 .set CYREG_SFLASH_MARGIN, 0x0ffff1be + 368 .set CYFLD_SFLASH_MDAC__OFFSET, 0x00000000 + 369 .set CYFLD_SFLASH_MDAC__SIZE, 0x00000008 + 370 .set CYREG_SFLASH_SPCIF_TRIM1, 0x0ffff1bf + 371 .set CYFLD_SFLASH_BDAC__OFFSET, 0x00000000 + 372 .set CYFLD_SFLASH_BDAC__SIZE, 0x00000004 + 373 .set CYREG_SFLASH_IMO_MAXF0, 0x0ffff1c0 + 374 .set CYFLD_SFLASH_MAXFREQ__OFFSET, 0x00000000 + 375 .set CYFLD_SFLASH_MAXFREQ__SIZE, 0x00000006 + 376 .set CYREG_SFLASH_IMO_ABS0, 0x0ffff1c1 + 377 .set CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET, 0x00000000 + 378 .set CYFLD_SFLASH_ABS_TRIM_IMO__SIZE, 0x00000006 + 379 .set CYREG_SFLASH_IMO_TMPCO0, 0x0ffff1c2 + 380 .set CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET, 0x00000000 + 381 .set CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE, 0x00000006 + 382 .set CYREG_SFLASH_IMO_MAXF1, 0x0ffff1c3 + 383 .set CYREG_SFLASH_IMO_ABS1, 0x0ffff1c4 + 384 .set CYREG_SFLASH_IMO_TMPCO1, 0x0ffff1c5 + 385 .set CYREG_SFLASH_IMO_MAXF2, 0x0ffff1c6 + 386 .set CYREG_SFLASH_IMO_ABS2, 0x0ffff1c7 + 387 .set CYREG_SFLASH_IMO_TMPCO2, 0x0ffff1c8 + 388 .set CYREG_SFLASH_IMO_MAXF3, 0x0ffff1c9 + 389 .set CYREG_SFLASH_IMO_ABS3, 0x0ffff1ca + 390 .set CYREG_SFLASH_IMO_TMPCO3, 0x0ffff1cb + 391 .set CYREG_SFLASH_IMO_ABS4, 0x0ffff1cc + 392 .set CYREG_SFLASH_IMO_TMPCO4, 0x0ffff1cd + 393 .set CYREG_SFLASH_IMO_TRIM00, 0x0ffff1d0 + 394 .set CYFLD_SFLASH_OFFSET__OFFSET, 0x00000000 + 395 .set CYFLD_SFLASH_OFFSET__SIZE, 0x00000008 + 396 .set CYREG_SFLASH_IMO_TRIM01, 0x0ffff1d1 + 397 .set CYREG_SFLASH_IMO_TRIM02, 0x0ffff1d2 + 398 .set CYREG_SFLASH_IMO_TRIM03, 0x0ffff1d3 + 399 .set CYREG_SFLASH_IMO_TRIM04, 0x0ffff1d4 + 400 .set CYREG_SFLASH_IMO_TRIM05, 0x0ffff1d5 + 401 .set CYREG_SFLASH_IMO_TRIM06, 0x0ffff1d6 + 402 .set CYREG_SFLASH_IMO_TRIM07, 0x0ffff1d7 + 403 .set CYREG_SFLASH_IMO_TRIM08, 0x0ffff1d8 + 404 .set CYREG_SFLASH_IMO_TRIM09, 0x0ffff1d9 + 405 .set CYREG_SFLASH_IMO_TRIM10, 0x0ffff1da + 406 .set CYREG_SFLASH_IMO_TRIM11, 0x0ffff1db + 407 .set CYREG_SFLASH_IMO_TRIM12, 0x0ffff1dc + 408 .set CYREG_SFLASH_IMO_TRIM13, 0x0ffff1dd + 409 .set CYREG_SFLASH_IMO_TRIM14, 0x0ffff1de + 410 .set CYREG_SFLASH_IMO_TRIM15, 0x0ffff1df + 411 .set CYREG_SFLASH_IMO_TRIM16, 0x0ffff1e0 + 412 .set CYREG_SFLASH_IMO_TRIM17, 0x0ffff1e1 + 413 .set CYREG_SFLASH_IMO_TRIM18, 0x0ffff1e2 + 414 .set CYREG_SFLASH_IMO_TRIM19, 0x0ffff1e3 + 415 .set CYREG_SFLASH_IMO_TRIM20, 0x0ffff1e4 + 416 .set CYREG_SFLASH_IMO_TRIM21, 0x0ffff1e5 + 417 .set CYREG_SFLASH_IMO_TRIM22, 0x0ffff1e6 + 418 .set CYREG_SFLASH_IMO_TRIM23, 0x0ffff1e7 + 419 .set CYREG_SFLASH_IMO_TRIM24, 0x0ffff1e8 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 9 + + + 420 .set CYREG_SFLASH_IMO_TRIM25, 0x0ffff1e9 + 421 .set CYREG_SFLASH_IMO_TRIM26, 0x0ffff1ea + 422 .set CYREG_SFLASH_IMO_TRIM27, 0x0ffff1eb + 423 .set CYREG_SFLASH_IMO_TRIM28, 0x0ffff1ec + 424 .set CYREG_SFLASH_IMO_TRIM29, 0x0ffff1ed + 425 .set CYREG_SFLASH_IMO_TRIM30, 0x0ffff1ee + 426 .set CYREG_SFLASH_IMO_TRIM31, 0x0ffff1ef + 427 .set CYREG_SFLASH_IMO_TRIM32, 0x0ffff1f0 + 428 .set CYREG_SFLASH_IMO_TRIM33, 0x0ffff1f1 + 429 .set CYREG_SFLASH_IMO_TRIM34, 0x0ffff1f2 + 430 .set CYREG_SFLASH_IMO_TRIM35, 0x0ffff1f3 + 431 .set CYREG_SFLASH_IMO_TRIM36, 0x0ffff1f4 + 432 .set CYREG_SFLASH_IMO_TRIM37, 0x0ffff1f5 + 433 .set CYREG_SFLASH_IMO_TRIM38, 0x0ffff1f6 + 434 .set CYREG_SFLASH_IMO_TRIM39, 0x0ffff1f7 + 435 .set CYREG_SFLASH_IMO_TRIM40, 0x0ffff1f8 + 436 .set CYREG_SFLASH_IMO_TRIM41, 0x0ffff1f9 + 437 .set CYREG_SFLASH_IMO_TRIM42, 0x0ffff1fa + 438 .set CYREG_SFLASH_IMO_TRIM43, 0x0ffff1fb + 439 .set CYREG_SFLASH_IMO_TRIM44, 0x0ffff1fc + 440 .set CYREG_SFLASH_IMO_TRIM45, 0x0ffff1fd + 441 .set CYREG_SFLASH_CHECKSUM, 0x0ffff1fe + 442 .set CYFLD_SFLASH_CHECKSUM__OFFSET, 0x00000000 + 443 .set CYFLD_SFLASH_CHECKSUM__SIZE, 0x00000010 + 444 .set CYDEV_SROM_BASE, 0x10000000 + 445 .set CYDEV_SROM_SIZE, 0x00001000 + 446 .set CYREG_SROM_DATA_MBASE, 0x10000000 + 447 .set CYREG_SROM_DATA_MSIZE, 0x00001000 + 448 .set CYDEV_SRAM_BASE, 0x20000000 + 449 .set CYDEV_SRAM_SIZE, 0x00001000 + 450 .set CYREG_SRAM_DATA_MBASE, 0x20000000 + 451 .set CYREG_SRAM_DATA_MSIZE, 0x00001000 + 452 .set CYDEV_CPUSS_BASE, 0x40000000 + 453 .set CYDEV_CPUSS_SIZE, 0x00010000 + 454 .set CYREG_CPUSS_CONFIG, 0x40000000 + 455 .set CYFLD_CPUSS_VECS_IN_RAM__OFFSET, 0x00000000 + 456 .set CYFLD_CPUSS_VECS_IN_RAM__SIZE, 0x00000001 + 457 .set CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET, 0x00000001 + 458 .set CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE, 0x00000001 + 459 .set CYREG_CPUSS_SYSREQ, 0x40000004 + 460 .set CYFLD_CPUSS_COMMAND__OFFSET, 0x00000000 + 461 .set CYFLD_CPUSS_COMMAND__SIZE, 0x00000010 + 462 .set CYFLD_CPUSS_NO_RST_OVR__OFFSET, 0x0000001b + 463 .set CYFLD_CPUSS_NO_RST_OVR__SIZE, 0x00000001 + 464 .set CYFLD_CPUSS_PRIVILEGED__OFFSET, 0x0000001c + 465 .set CYFLD_CPUSS_PRIVILEGED__SIZE, 0x00000001 + 466 .set CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET, 0x0000001d + 467 .set CYFLD_CPUSS_ROM_ACCESS_EN__SIZE, 0x00000001 + 468 .set CYFLD_CPUSS_HMASTER__OFFSET, 0x0000001e + 469 .set CYFLD_CPUSS_HMASTER__SIZE, 0x00000001 + 470 .set CYFLD_CPUSS_SYSREQ__OFFSET, 0x0000001f + 471 .set CYFLD_CPUSS_SYSREQ__SIZE, 0x00000001 + 472 .set CYREG_CPUSS_SYSARG, 0x40000008 + 473 .set CYFLD_CPUSS_ARG32__OFFSET, 0x00000000 + 474 .set CYFLD_CPUSS_ARG32__SIZE, 0x00000020 + 475 .set CYREG_CPUSS_PROTECTION, 0x4000000c + 476 .set CYFLD_CPUSS_PROT__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 10 + + + 477 .set CYFLD_CPUSS_PROT__SIZE, 0x00000004 + 478 .set CYVAL_CPUSS_PROT_VIRGIN, 0x00000000 + 479 .set CYVAL_CPUSS_PROT_OPEN, 0x00000001 + 480 .set CYVAL_CPUSS_PROT_PROTECTED, 0x00000002 + 481 .set CYVAL_CPUSS_PROT_KILL, 0x00000004 + 482 .set CYVAL_CPUSS_PROT_BOOT, 0x00000008 + 483 .set CYFLD_CPUSS_PROT_LOCK__OFFSET, 0x0000001f + 484 .set CYFLD_CPUSS_PROT_LOCK__SIZE, 0x00000001 + 485 .set CYREG_CPUSS_PRIV_ROM, 0x40000010 + 486 .set CYFLD_CPUSS_ROM_LIMIT__OFFSET, 0x00000000 + 487 .set CYFLD_CPUSS_ROM_LIMIT__SIZE, 0x00000008 + 488 .set CYREG_CPUSS_PRIV_RAM, 0x40000014 + 489 .set CYFLD_CPUSS_RAM_LIMIT__OFFSET, 0x00000000 + 490 .set CYFLD_CPUSS_RAM_LIMIT__SIZE, 0x00000009 + 491 .set CYREG_CPUSS_PRIV_FLASH, 0x40000018 + 492 .set CYFLD_CPUSS_FLASH_LIMIT__OFFSET, 0x00000000 + 493 .set CYFLD_CPUSS_FLASH_LIMIT__SIZE, 0x0000000b + 494 .set CYREG_CPUSS_WOUNDING, 0x4000001c + 495 .set CYFLD_CPUSS_RAM_SIZE__OFFSET, 0x00000000 + 496 .set CYFLD_CPUSS_RAM_SIZE__SIZE, 0x00000009 + 497 .set CYFLD_CPUSS_RAM_WOUND__OFFSET, 0x00000010 + 498 .set CYFLD_CPUSS_RAM_WOUND__SIZE, 0x00000003 + 499 .set CYVAL_CPUSS_RAM_WOUND_FULL, 0x00000000 + 500 .set CYVAL_CPUSS_RAM_WOUND_DIV_BY_2, 0x00000001 + 501 .set CYVAL_CPUSS_RAM_WOUND_DIV_BY_4, 0x00000002 + 502 .set CYVAL_CPUSS_RAM_WOUND_DIV_BY_8, 0x00000003 + 503 .set CYVAL_CPUSS_RAM_WOUND_DIV_BY_16, 0x00000004 + 504 .set CYVAL_CPUSS_RAM_WOUND_DIV_BY_32, 0x00000005 + 505 .set CYVAL_CPUSS_RAM_WOUND_DIV_BY_64, 0x00000006 + 506 .set CYVAL_CPUSS_RAM_WOUND_DIV_BY_128, 0x00000007 + 507 .set CYFLD_CPUSS_FLASH_WOUND__OFFSET, 0x00000014 + 508 .set CYFLD_CPUSS_FLASH_WOUND__SIZE, 0x00000003 + 509 .set CYVAL_CPUSS_FLASH_WOUND_FULL, 0x00000000 + 510 .set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2, 0x00000001 + 511 .set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4, 0x00000002 + 512 .set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8, 0x00000003 + 513 .set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16, 0x00000004 + 514 .set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32, 0x00000005 + 515 .set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64, 0x00000006 + 516 .set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128, 0x00000007 + 517 .set CYREG_CPUSS_INTR_SELECT, 0x40000020 + 518 .set CYFLD_CPUSS_SELECT32__OFFSET, 0x00000000 + 519 .set CYFLD_CPUSS_SELECT32__SIZE, 0x00000020 + 520 .set CYDEV_HSIOM_BASE, 0x40010000 + 521 .set CYDEV_HSIOM_SIZE, 0x00001000 + 522 .set CYREG_HSIOM_PORT_SEL0, 0x40010000 + 523 .set CYFLD_HSIOM_SEL0__OFFSET, 0x00000000 + 524 .set CYFLD_HSIOM_SEL0__SIZE, 0x00000004 + 525 .set CYVAL_HSIOM_SEL0_GPIO, 0x00000000 + 526 .set CYVAL_HSIOM_SEL0_GPIO_DSI, 0x00000001 + 527 .set CYVAL_HSIOM_SEL0_DSI_DSI, 0x00000002 + 528 .set CYVAL_HSIOM_SEL0_DSI_GPIO, 0x00000003 + 529 .set CYVAL_HSIOM_SEL0_CSD_SENSE, 0x00000004 + 530 .set CYVAL_HSIOM_SEL0_CSD_SHIELD, 0x00000005 + 531 .set CYVAL_HSIOM_SEL0_AMUXA, 0x00000006 + 532 .set CYVAL_HSIOM_SEL0_AMUXB, 0x00000007 + 533 .set CYVAL_HSIOM_SEL0_ACT_0, 0x00000008 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 11 + + + 534 .set CYVAL_HSIOM_SEL0_ACT_1, 0x00000009 + 535 .set CYVAL_HSIOM_SEL0_ACT_2, 0x0000000a + 536 .set CYVAL_HSIOM_SEL0_ACT_3, 0x0000000b + 537 .set CYVAL_HSIOM_SEL0_LCD_COM, 0x0000000c + 538 .set CYVAL_HSIOM_SEL0_LCD_SEG, 0x0000000d + 539 .set CYVAL_HSIOM_SEL0_DPSLP_0, 0x0000000e + 540 .set CYVAL_HSIOM_SEL0_DPSLP_1, 0x0000000f + 541 .set CYVAL_HSIOM_SEL0_COMP1_INP, 0x00000000 + 542 .set CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1, 0x0000000f + 543 .set CYFLD_HSIOM_SEL1__OFFSET, 0x00000004 + 544 .set CYFLD_HSIOM_SEL1__SIZE, 0x00000004 + 545 .set CYVAL_HSIOM_SEL1_COMP1_INN, 0x00000000 + 546 .set CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2, 0x0000000f + 547 .set CYFLD_HSIOM_SEL2__OFFSET, 0x00000008 + 548 .set CYFLD_HSIOM_SEL2__SIZE, 0x00000004 + 549 .set CYVAL_HSIOM_SEL2_COMP2_INP, 0x00000000 + 550 .set CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3, 0x0000000f + 551 .set CYFLD_HSIOM_SEL3__OFFSET, 0x0000000c + 552 .set CYFLD_HSIOM_SEL3__SIZE, 0x00000004 + 553 .set CYVAL_HSIOM_SEL3_COMP2_INN, 0x00000000 + 554 .set CYFLD_HSIOM_SEL4__OFFSET, 0x00000010 + 555 .set CYFLD_HSIOM_SEL4__SIZE, 0x00000004 + 556 .set CYVAL_HSIOM_SEL4_SCB1_UART_RX, 0x00000009 + 557 .set CYVAL_HSIOM_SEL4_SCB1_I2C_SCL, 0x0000000e + 558 .set CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI, 0x0000000f + 559 .set CYFLD_HSIOM_SEL5__OFFSET, 0x00000014 + 560 .set CYFLD_HSIOM_SEL5__SIZE, 0x00000004 + 561 .set CYVAL_HSIOM_SEL5_SCB1_UART_TX, 0x00000009 + 562 .set CYVAL_HSIOM_SEL5_SCB1_I2C_SDA, 0x0000000e + 563 .set CYVAL_HSIOM_SEL5_SCB1_SPI_MISO, 0x0000000f + 564 .set CYFLD_HSIOM_SEL6__OFFSET, 0x00000018 + 565 .set CYFLD_HSIOM_SEL6__SIZE, 0x00000004 + 566 .set CYVAL_HSIOM_SEL6_EXT_CLK, 0x00000008 + 567 .set CYVAL_HSIOM_SEL6_SCB1_SPI_CLK, 0x0000000f + 568 .set CYFLD_HSIOM_SEL7__OFFSET, 0x0000001c + 569 .set CYFLD_HSIOM_SEL7__SIZE, 0x00000004 + 570 .set CYVAL_HSIOM_SEL7_WAKEUP, 0x0000000e + 571 .set CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0, 0x0000000f + 572 .set CYREG_HSIOM_PORT_SEL1, 0x40010004 + 573 .set CYREG_HSIOM_PORT_SEL2, 0x40010008 + 574 .set CYREG_HSIOM_PORT_SEL3, 0x4001000c + 575 .set CYREG_HSIOM_PORT_SEL4, 0x40010010 + 576 .set CYDEV_CLK_BASE, 0x40020000 + 577 .set CYDEV_CLK_SIZE, 0x00010000 + 578 .set CYREG_CLK_DIVIDER_A00, 0x40020000 + 579 .set CYFLD_CLK_DIVIDER_A__OFFSET, 0x00000000 + 580 .set CYFLD_CLK_DIVIDER_A__SIZE, 0x00000010 + 581 .set CYFLD_CLK_ENABLE_A__OFFSET, 0x0000001f + 582 .set CYFLD_CLK_ENABLE_A__SIZE, 0x00000001 + 583 .set CYREG_CLK_DIVIDER_A01, 0x40020004 + 584 .set CYREG_CLK_DIVIDER_A02, 0x40020008 + 585 .set CYREG_CLK_DIVIDER_B00, 0x40020040 + 586 .set CYFLD_CLK_DIVIDER_B__OFFSET, 0x00000000 + 587 .set CYFLD_CLK_DIVIDER_B__SIZE, 0x00000010 + 588 .set CYFLD_CLK_CASCADE_A_B__OFFSET, 0x0000001e + 589 .set CYFLD_CLK_CASCADE_A_B__SIZE, 0x00000001 + 590 .set CYFLD_CLK_ENABLE_B__OFFSET, 0x0000001f + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 12 + + + 591 .set CYFLD_CLK_ENABLE_B__SIZE, 0x00000001 + 592 .set CYREG_CLK_DIVIDER_B01, 0x40020044 + 593 .set CYREG_CLK_DIVIDER_B02, 0x40020048 + 594 .set CYREG_CLK_DIVIDER_C00, 0x40020080 + 595 .set CYFLD_CLK_DIVIDER_C__OFFSET, 0x00000000 + 596 .set CYFLD_CLK_DIVIDER_C__SIZE, 0x00000010 + 597 .set CYFLD_CLK_CASCADE_B_C__OFFSET, 0x0000001e + 598 .set CYFLD_CLK_CASCADE_B_C__SIZE, 0x00000001 + 599 .set CYFLD_CLK_ENABLE_C__OFFSET, 0x0000001f + 600 .set CYFLD_CLK_ENABLE_C__SIZE, 0x00000001 + 601 .set CYREG_CLK_DIVIDER_C01, 0x40020084 + 602 .set CYREG_CLK_DIVIDER_C02, 0x40020088 + 603 .set CYREG_CLK_DIVIDER_FRAC_A00, 0x40020100 + 604 .set CYFLD_CLK_FRAC_A__OFFSET, 0x00000010 + 605 .set CYFLD_CLK_FRAC_A__SIZE, 0x00000005 + 606 .set CYREG_CLK_DIVIDER_FRAC_B00, 0x40020140 + 607 .set CYFLD_CLK_FRAC_B__OFFSET, 0x00000010 + 608 .set CYFLD_CLK_FRAC_B__SIZE, 0x00000005 + 609 .set CYREG_CLK_DIVIDER_FRAC_C00, 0x40020180 + 610 .set CYFLD_CLK_FRAC_C__OFFSET, 0x00000010 + 611 .set CYFLD_CLK_FRAC_C__SIZE, 0x00000005 + 612 .set CYREG_CLK_SELECT00, 0x40020200 + 613 .set CYFLD_CLK_DIVIDER_N__OFFSET, 0x00000000 + 614 .set CYFLD_CLK_DIVIDER_N__SIZE, 0x00000004 + 615 .set CYFLD_CLK_DIVIDER_ABC__OFFSET, 0x00000004 + 616 .set CYFLD_CLK_DIVIDER_ABC__SIZE, 0x00000002 + 617 .set CYVAL_CLK_DIVIDER_ABC_OFF, 0x00000000 + 618 .set CYVAL_CLK_DIVIDER_ABC_A, 0x00000001 + 619 .set CYVAL_CLK_DIVIDER_ABC_B, 0x00000002 + 620 .set CYVAL_CLK_DIVIDER_ABC_C, 0x00000003 + 621 .set CYREG_CLK_SELECT01, 0x40020204 + 622 .set CYREG_CLK_SELECT02, 0x40020208 + 623 .set CYREG_CLK_SELECT03, 0x4002020c + 624 .set CYREG_CLK_SELECT04, 0x40020210 + 625 .set CYREG_CLK_SELECT05, 0x40020214 + 626 .set CYREG_CLK_SELECT06, 0x40020218 + 627 .set CYREG_CLK_SELECT07, 0x4002021c + 628 .set CYREG_CLK_SELECT08, 0x40020220 + 629 .set CYREG_CLK_SELECT09, 0x40020224 + 630 .set CYREG_CLK_SELECT10, 0x40020228 + 631 .set CYREG_CLK_SELECT11, 0x4002022c + 632 .set CYREG_CLK_SELECT12, 0x40020230 + 633 .set CYREG_CLK_SELECT13, 0x40020234 + 634 .set CYREG_CLK_SELECT14, 0x40020238 + 635 .set CYREG_CLK_SELECT15, 0x4002023c + 636 .set CYDEV_TST_BASE, 0x40030000 + 637 .set CYDEV_TST_SIZE, 0x00010000 + 638 .set CYREG_TST_CTRL, 0x40030000 + 639 .set CYFLD_TST_DAP_NO_ACCESS__OFFSET, 0x00000000 + 640 .set CYFLD_TST_DAP_NO_ACCESS__SIZE, 0x00000001 + 641 .set CYFLD_TST_DAP_NO_DEBUG__OFFSET, 0x00000001 + 642 .set CYFLD_TST_DAP_NO_DEBUG__SIZE, 0x00000001 + 643 .set CYFLD_TST_SWD_CONNECTED__OFFSET, 0x00000002 + 644 .set CYFLD_TST_SWD_CONNECTED__SIZE, 0x00000001 + 645 .set CYFLD_TST_TEST_RESET_EN_N__OFFSET, 0x00000008 + 646 .set CYFLD_TST_TEST_RESET_EN_N__SIZE, 0x00000001 + 647 .set CYFLD_TST_TEST_SET_EN_N__OFFSET, 0x00000009 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 13 + + + 648 .set CYFLD_TST_TEST_SET_EN_N__SIZE, 0x00000001 + 649 .set CYFLD_TST_TEST_ICG_EN_N__OFFSET, 0x0000000a + 650 .set CYFLD_TST_TEST_ICG_EN_N__SIZE, 0x00000001 + 651 .set CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET, 0x0000000b + 652 .set CYFLD_TST_TEST_OCC0_1_EN_N__SIZE, 0x00000001 + 653 .set CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET, 0x0000000c + 654 .set CYFLD_TST_TEST_OCC0_2_EN_N__SIZE, 0x00000001 + 655 .set CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET, 0x0000000d + 656 .set CYFLD_TST_TEST_SLPISOLATE_EN__SIZE, 0x00000001 + 657 .set CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET, 0x0000000e + 658 .set CYFLD_TST_TEST_SYSISOLATE_EN__SIZE, 0x00000001 + 659 .set CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET, 0x0000000f + 660 .set CYFLD_TST_TEST_SLPRETAIN_EN__SIZE, 0x00000001 + 661 .set CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET, 0x00000010 + 662 .set CYFLD_TST_TEST_SYSRETAIN_EN__SIZE, 0x00000001 + 663 .set CYFLD_TST_TEST_SPARE1_EN__OFFSET, 0x00000011 + 664 .set CYFLD_TST_TEST_SPARE1_EN__SIZE, 0x00000001 + 665 .set CYFLD_TST_TEST_SPARE2_EN__OFFSET, 0x00000012 + 666 .set CYFLD_TST_TEST_SPARE2_EN__SIZE, 0x00000001 + 667 .set CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET, 0x00000018 + 668 .set CYFLD_TST_SCAN_OCC_OBSERVE__SIZE, 0x00000001 + 669 .set CYFLD_TST_SCAN_TRF1__OFFSET, 0x00000019 + 670 .set CYFLD_TST_SCAN_TRF1__SIZE, 0x00000001 + 671 .set CYFLD_TST_SCAN_TRF__OFFSET, 0x0000001a + 672 .set CYFLD_TST_SCAN_TRF__SIZE, 0x00000001 + 673 .set CYFLD_TST_SCAN_IDDQ__OFFSET, 0x0000001b + 674 .set CYFLD_TST_SCAN_IDDQ__SIZE, 0x00000001 + 675 .set CYFLD_TST_SCAN_COMPRESS__OFFSET, 0x0000001c + 676 .set CYFLD_TST_SCAN_COMPRESS__SIZE, 0x00000001 + 677 .set CYFLD_TST_SCAN_MODE__OFFSET, 0x0000001d + 678 .set CYFLD_TST_SCAN_MODE__SIZE, 0x00000001 + 679 .set CYFLD_TST_PTM_MODE_EN__OFFSET, 0x0000001e + 680 .set CYFLD_TST_PTM_MODE_EN__SIZE, 0x00000001 + 681 .set CYREG_TST_ADFT_CTRL, 0x40030004 + 682 .set CYFLD_TST_ENABLE__OFFSET, 0x0000001f + 683 .set CYFLD_TST_ENABLE__SIZE, 0x00000001 + 684 .set CYREG_TST_DDFT_CTRL, 0x40030008 + 685 .set CYFLD_TST_DFT_SEL1__OFFSET, 0x00000000 + 686 .set CYFLD_TST_DFT_SEL1__SIZE, 0x00000006 + 687 .set CYVAL_TST_DFT_SEL1_VSS, 0x00000000 + 688 .set CYVAL_TST_DFT_SEL1_CLK1, 0x00000001 + 689 .set CYVAL_TST_DFT_SEL1_CLK2, 0x00000002 + 690 .set CYVAL_TST_DFT_SEL1_PWR1, 0x00000003 + 691 .set CYVAL_TST_DFT_SEL1_PWR2, 0x00000004 + 692 .set CYVAL_TST_DFT_SEL1_VMON, 0x00000005 + 693 .set CYVAL_TST_DFT_SEL1_TSS_VDDA_OK, 0x00000006 + 694 .set CYVAL_TST_DFT_SEL1_ADFT_TRIP1, 0x00000007 + 695 .set CYVAL_TST_DFT_SEL1_ADFT_TRIP2, 0x00000008 + 696 .set CYVAL_TST_DFT_SEL1_TSS1, 0x00000009 + 697 .set CYVAL_TST_DFT_SEL1_TSS2, 0x0000000a + 698 .set CYVAL_TST_DFT_SEL1_TSS3, 0x0000000b + 699 .set CYVAL_TST_DFT_SEL1_TSS4, 0x0000000c + 700 .set CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS, 0x0000000d + 701 .set CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI, 0x0000000e + 702 .set CYFLD_TST_DFT_SEL2__OFFSET, 0x00000008 + 703 .set CYFLD_TST_DFT_SEL2__SIZE, 0x00000006 + 704 .set CYVAL_TST_DFT_SEL2_VSS, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 14 + + + 705 .set CYVAL_TST_DFT_SEL2_CLK1, 0x00000001 + 706 .set CYVAL_TST_DFT_SEL2_CLK2, 0x00000002 + 707 .set CYVAL_TST_DFT_SEL2_PWR1, 0x00000003 + 708 .set CYVAL_TST_DFT_SEL2_PWR2, 0x00000004 + 709 .set CYVAL_TST_DFT_SEL2_VMON, 0x00000005 + 710 .set CYVAL_TST_DFT_SEL2_TSS_VDDA_OK, 0x00000006 + 711 .set CYVAL_TST_DFT_SEL2_ADFT_TRIP1, 0x00000007 + 712 .set CYVAL_TST_DFT_SEL2_ADFT_TRIP2, 0x00000008 + 713 .set CYVAL_TST_DFT_SEL2_TSS1, 0x00000009 + 714 .set CYVAL_TST_DFT_SEL2_TSS2, 0x0000000a + 715 .set CYVAL_TST_DFT_SEL2_TSS3, 0x0000000b + 716 .set CYVAL_TST_DFT_SEL2_TSS4, 0x0000000c + 717 .set CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS, 0x0000000d + 718 .set CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI, 0x0000000e + 719 .set CYFLD_TST_EDGE__OFFSET, 0x0000001c + 720 .set CYFLD_TST_EDGE__SIZE, 0x00000001 + 721 .set CYVAL_TST_EDGE_POSEDGE, 0x00000000 + 722 .set CYVAL_TST_EDGE_NEGEDGE, 0x00000001 + 723 .set CYFLD_TST_DIVIDE__OFFSET, 0x0000001d + 724 .set CYFLD_TST_DIVIDE__SIZE, 0x00000002 + 725 .set CYVAL_TST_DIVIDE_DIRECT, 0x00000000 + 726 .set CYVAL_TST_DIVIDE_DIV_BY_2, 0x00000001 + 727 .set CYVAL_TST_DIVIDE_DIV_BY_4, 0x00000002 + 728 .set CYVAL_TST_DIVIDE_DIV_BY_8, 0x00000003 + 729 .set CYREG_TST_MODE, 0x40030014 + 730 .set CYFLD_TST_TEST_MODE__OFFSET, 0x0000001f + 731 .set CYFLD_TST_TEST_MODE__SIZE, 0x00000001 + 732 .set CYREG_TST_TRIM_CNTR1, 0x40030018 + 733 .set CYFLD_TST_COUNTER__OFFSET, 0x00000000 + 734 .set CYFLD_TST_COUNTER__SIZE, 0x00000010 + 735 .set CYFLD_TST_COUNTER_DONE__OFFSET, 0x0000001f + 736 .set CYFLD_TST_COUNTER_DONE__SIZE, 0x00000001 + 737 .set CYREG_TST_TRIM_CNTR2, 0x4003001c + 738 .set CYDEV_PRT0_BASE, 0x40040000 + 739 .set CYDEV_PRT0_SIZE, 0x00000100 + 740 .set CYREG_PRT0_DR, 0x40040000 + 741 .set CYFLD_PRT_DATAREG__OFFSET, 0x00000000 + 742 .set CYFLD_PRT_DATAREG__SIZE, 0x00000008 + 743 .set CYREG_PRT0_PS, 0x40040004 + 744 .set CYFLD_PRT_PINSTATE__OFFSET, 0x00000000 + 745 .set CYFLD_PRT_PINSTATE__SIZE, 0x00000008 + 746 .set CYFLD_PRT_PINSTATE_FLT__OFFSET, 0x00000008 + 747 .set CYFLD_PRT_PINSTATE_FLT__SIZE, 0x00000001 + 748 .set CYREG_PRT0_PC, 0x40040008 + 749 .set CYFLD_PRT_DM__OFFSET, 0x00000000 + 750 .set CYFLD_PRT_DM__SIZE, 0x00000018 + 751 .set CYVAL_PRT_DM_OFF, 0x00000000 + 752 .set CYVAL_PRT_DM_INPUT, 0x00000001 + 753 .set CYVAL_PRT_DM_0_PU, 0x00000002 + 754 .set CYVAL_PRT_DM_PD_1, 0x00000003 + 755 .set CYVAL_PRT_DM_0_Z, 0x00000004 + 756 .set CYVAL_PRT_DM_Z_1, 0x00000005 + 757 .set CYVAL_PRT_DM_0_1, 0x00000006 + 758 .set CYVAL_PRT_DM_PD_PU, 0x00000007 + 759 .set CYFLD_PRT_VTRIP_SEL__OFFSET, 0x00000018 + 760 .set CYFLD_PRT_VTRIP_SEL__SIZE, 0x00000001 + 761 .set CYFLD_PRT_SLOW__OFFSET, 0x00000019 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 15 + + + 762 .set CYFLD_PRT_SLOW__SIZE, 0x00000001 + 763 .set CYREG_PRT0_INTCFG, 0x4004000c + 764 .set CYFLD_PRT_INTTYPE__OFFSET, 0x00000000 + 765 .set CYFLD_PRT_INTTYPE__SIZE, 0x00000010 + 766 .set CYVAL_PRT_INTTYPE_DISABLE, 0x00000000 + 767 .set CYVAL_PRT_INTTYPE_RISING, 0x00000001 + 768 .set CYVAL_PRT_INTTYPE_FALLING, 0x00000002 + 769 .set CYVAL_PRT_INTTYPE_BOTH, 0x00000003 + 770 .set CYFLD_PRT_INTTYPE_FLT__OFFSET, 0x00000010 + 771 .set CYFLD_PRT_INTTYPE_FLT__SIZE, 0x00000002 + 772 .set CYVAL_PRT_INTTYPE_FLT_DISABLE, 0x00000000 + 773 .set CYVAL_PRT_INTTYPE_FLT_RISING, 0x00000001 + 774 .set CYVAL_PRT_INTTYPE_FLT_FALLING, 0x00000002 + 775 .set CYVAL_PRT_INTTYPE_FLT_BOTH, 0x00000003 + 776 .set CYFLD_PRT_FLT_SELECT__OFFSET, 0x00000012 + 777 .set CYFLD_PRT_FLT_SELECT__SIZE, 0x00000003 + 778 .set CYREG_PRT0_INTSTAT, 0x40040010 + 779 .set CYFLD_PRT_INTSTAT__OFFSET, 0x00000000 + 780 .set CYFLD_PRT_INTSTAT__SIZE, 0x00000008 + 781 .set CYFLD_PRT_INTSTAT_FLT__OFFSET, 0x00000008 + 782 .set CYFLD_PRT_INTSTAT_FLT__SIZE, 0x00000001 + 783 .set CYFLD_PRT_PS__OFFSET, 0x00000010 + 784 .set CYFLD_PRT_PS__SIZE, 0x00000008 + 785 .set CYFLD_PRT_PS_FLT__OFFSET, 0x00000018 + 786 .set CYFLD_PRT_PS_FLT__SIZE, 0x00000001 + 787 .set CYREG_PRT0_PC2, 0x40040018 + 788 .set CYFLD_PRT_INP_DIS__OFFSET, 0x00000000 + 789 .set CYFLD_PRT_INP_DIS__SIZE, 0x00000008 + 790 .set CYDEV_PRT1_BASE, 0x40040100 + 791 .set CYDEV_PRT1_SIZE, 0x00000100 + 792 .set CYREG_PRT1_DR, 0x40040100 + 793 .set CYREG_PRT1_PS, 0x40040104 + 794 .set CYREG_PRT1_PC, 0x40040108 + 795 .set CYREG_PRT1_INTCFG, 0x4004010c + 796 .set CYREG_PRT1_INTSTAT, 0x40040110 + 797 .set CYREG_PRT1_PC2, 0x40040118 + 798 .set CYDEV_PRT2_BASE, 0x40040200 + 799 .set CYDEV_PRT2_SIZE, 0x00000100 + 800 .set CYREG_PRT2_DR, 0x40040200 + 801 .set CYREG_PRT2_PS, 0x40040204 + 802 .set CYREG_PRT2_PC, 0x40040208 + 803 .set CYREG_PRT2_INTCFG, 0x4004020c + 804 .set CYREG_PRT2_INTSTAT, 0x40040210 + 805 .set CYREG_PRT2_PC2, 0x40040218 + 806 .set CYDEV_PRT3_BASE, 0x40040300 + 807 .set CYDEV_PRT3_SIZE, 0x00000100 + 808 .set CYREG_PRT3_DR, 0x40040300 + 809 .set CYREG_PRT3_PS, 0x40040304 + 810 .set CYREG_PRT3_PC, 0x40040308 + 811 .set CYREG_PRT3_INTCFG, 0x4004030c + 812 .set CYREG_PRT3_INTSTAT, 0x40040310 + 813 .set CYREG_PRT3_PC2, 0x40040318 + 814 .set CYDEV_PRT4_BASE, 0x40040400 + 815 .set CYDEV_PRT4_SIZE, 0x00000100 + 816 .set CYREG_PRT4_DR, 0x40040400 + 817 .set CYREG_PRT4_PS, 0x40040404 + 818 .set CYREG_PRT4_PC, 0x40040408 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 16 + + + 819 .set CYREG_PRT4_INTCFG, 0x4004040c + 820 .set CYREG_PRT4_INTSTAT, 0x40040410 + 821 .set CYREG_PRT4_PC2, 0x40040418 + 822 .set CYDEV_TCPWM_BASE, 0x40050000 + 823 .set CYDEV_TCPWM_SIZE, 0x00001000 + 824 .set CYREG_TCPWM_CTRL, 0x40050000 + 825 .set CYFLD_TCPWM_COUNTER_ENABLED__OFFSET, 0x00000000 + 826 .set CYFLD_TCPWM_COUNTER_ENABLED__SIZE, 0x00000008 + 827 .set CYREG_TCPWM_CMD, 0x40050008 + 828 .set CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET, 0x00000000 + 829 .set CYFLD_TCPWM_COUNTER_CAPTURE__SIZE, 0x00000008 + 830 .set CYFLD_TCPWM_COUNTER_RELOAD__OFFSET, 0x00000008 + 831 .set CYFLD_TCPWM_COUNTER_RELOAD__SIZE, 0x00000008 + 832 .set CYFLD_TCPWM_COUNTER_STOP__OFFSET, 0x00000010 + 833 .set CYFLD_TCPWM_COUNTER_STOP__SIZE, 0x00000008 + 834 .set CYFLD_TCPWM_COUNTER_START__OFFSET, 0x00000018 + 835 .set CYFLD_TCPWM_COUNTER_START__SIZE, 0x00000008 + 836 .set CYREG_TCPWM_INTR_CAUSE, 0x4005000c + 837 .set CYFLD_TCPWM_COUNTER_INT__OFFSET, 0x00000000 + 838 .set CYFLD_TCPWM_COUNTER_INT__SIZE, 0x00000008 + 839 .set CYDEV_TCPWM_CNT0_BASE, 0x40050100 + 840 .set CYDEV_TCPWM_CNT0_SIZE, 0x00000040 + 841 .set CYREG_TCPWM_CNT0_CTRL, 0x40050100 + 842 .set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET, 0x00000000 + 843 .set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE, 0x00000001 + 844 .set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET, 0x00000001 + 845 .set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE, 0x00000001 + 846 .set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET, 0x00000002 + 847 .set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE, 0x00000001 + 848 .set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET, 0x00000003 + 849 .set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE, 0x00000001 + 850 .set CYFLD_TCPWM_CNT_GENERIC__OFFSET, 0x00000008 + 851 .set CYFLD_TCPWM_CNT_GENERIC__SIZE, 0x00000008 + 852 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY1, 0x00000000 + 853 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY2, 0x00000001 + 854 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY4, 0x00000002 + 855 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY8, 0x00000003 + 856 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY16, 0x00000004 + 857 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY32, 0x00000005 + 858 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY64, 0x00000006 + 859 .set CYVAL_TCPWM_CNT_GENERIC_DIVBY128, 0x00000007 + 860 .set CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET, 0x00000010 + 861 .set CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE, 0x00000002 + 862 .set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP, 0x00000000 + 863 .set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN, 0x00000001 + 864 .set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1, 0x00000002 + 865 .set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2, 0x00000003 + 866 .set CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET, 0x00000012 + 867 .set CYFLD_TCPWM_CNT_ONE_SHOT__SIZE, 0x00000001 + 868 .set CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET, 0x00000014 + 869 .set CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE, 0x00000002 + 870 .set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1, 0x00000000 + 871 .set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2, 0x00000001 + 872 .set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4, 0x00000002 + 873 .set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT, 0x00000001 + 874 .set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT, 0x00000002 + 875 .set CYFLD_TCPWM_CNT_MODE__OFFSET, 0x00000018 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 17 + + + 876 .set CYFLD_TCPWM_CNT_MODE__SIZE, 0x00000003 + 877 .set CYVAL_TCPWM_CNT_MODE_TIMER, 0x00000000 + 878 .set CYVAL_TCPWM_CNT_MODE_CAPTURE, 0x00000002 + 879 .set CYVAL_TCPWM_CNT_MODE_QUAD, 0x00000003 + 880 .set CYVAL_TCPWM_CNT_MODE_PWM, 0x00000004 + 881 .set CYVAL_TCPWM_CNT_MODE_PWM_DT, 0x00000005 + 882 .set CYVAL_TCPWM_CNT_MODE_PWM_PR, 0x00000006 + 883 .set CYREG_TCPWM_CNT0_STATUS, 0x40050104 + 884 .set CYFLD_TCPWM_CNT_DOWN__OFFSET, 0x00000000 + 885 .set CYFLD_TCPWM_CNT_DOWN__SIZE, 0x00000001 + 886 .set CYFLD_TCPWM_CNT_RUNNING__OFFSET, 0x0000001f + 887 .set CYFLD_TCPWM_CNT_RUNNING__SIZE, 0x00000001 + 888 .set CYREG_TCPWM_CNT0_COUNTER, 0x40050108 + 889 .set CYFLD_TCPWM_CNT_COUNTER__OFFSET, 0x00000000 + 890 .set CYFLD_TCPWM_CNT_COUNTER__SIZE, 0x00000010 + 891 .set CYREG_TCPWM_CNT0_CC, 0x4005010c + 892 .set CYFLD_TCPWM_CNT_CC__OFFSET, 0x00000000 + 893 .set CYFLD_TCPWM_CNT_CC__SIZE, 0x00000010 + 894 .set CYREG_TCPWM_CNT0_CC_BUFF, 0x40050110 + 895 .set CYREG_TCPWM_CNT0_PERIOD, 0x40050114 + 896 .set CYFLD_TCPWM_CNT_PERIOD__OFFSET, 0x00000000 + 897 .set CYFLD_TCPWM_CNT_PERIOD__SIZE, 0x00000010 + 898 .set CYREG_TCPWM_CNT0_PERIOD_BUFF, 0x40050118 + 899 .set CYREG_TCPWM_CNT0_TR_CTRL0, 0x40050120 + 900 .set CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET, 0x00000000 + 901 .set CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE, 0x00000004 + 902 .set CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET, 0x00000004 + 903 .set CYFLD_TCPWM_CNT_COUNT_SEL__SIZE, 0x00000004 + 904 .set CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET, 0x00000008 + 905 .set CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE, 0x00000004 + 906 .set CYFLD_TCPWM_CNT_STOP_SEL__OFFSET, 0x0000000c + 907 .set CYFLD_TCPWM_CNT_STOP_SEL__SIZE, 0x00000004 + 908 .set CYFLD_TCPWM_CNT_START_SEL__OFFSET, 0x00000010 + 909 .set CYFLD_TCPWM_CNT_START_SEL__SIZE, 0x00000004 + 910 .set CYREG_TCPWM_CNT0_TR_CTRL1, 0x40050124 + 911 .set CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET, 0x00000000 + 912 .set CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE, 0x00000002 + 913 .set CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE, 0x00000000 + 914 .set CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE, 0x00000001 + 915 .set CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES, 0x00000002 + 916 .set CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET, 0x00000003 + 917 .set CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET, 0x00000002 + 918 .set CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE, 0x00000002 + 919 .set CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE, 0x00000000 + 920 .set CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE, 0x00000001 + 921 .set CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES, 0x00000002 + 922 .set CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET, 0x00000003 + 923 .set CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET, 0x00000004 + 924 .set CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE, 0x00000002 + 925 .set CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE, 0x00000000 + 926 .set CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE, 0x00000001 + 927 .set CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES, 0x00000002 + 928 .set CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET, 0x00000003 + 929 .set CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET, 0x00000006 + 930 .set CYFLD_TCPWM_CNT_STOP_EDGE__SIZE, 0x00000002 + 931 .set CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE, 0x00000000 + 932 .set CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 18 + + + 933 .set CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES, 0x00000002 + 934 .set CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET, 0x00000003 + 935 .set CYFLD_TCPWM_CNT_START_EDGE__OFFSET, 0x00000008 + 936 .set CYFLD_TCPWM_CNT_START_EDGE__SIZE, 0x00000002 + 937 .set CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE, 0x00000000 + 938 .set CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE, 0x00000001 + 939 .set CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES, 0x00000002 + 940 .set CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET, 0x00000003 + 941 .set CYREG_TCPWM_CNT0_TR_CTRL2, 0x40050128 + 942 .set CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET, 0x00000000 + 943 .set CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE, 0x00000002 + 944 .set CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET, 0x00000000 + 945 .set CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR, 0x00000001 + 946 .set CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT, 0x00000002 + 947 .set CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE, 0x00000003 + 948 .set CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET, 0x00000002 + 949 .set CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE, 0x00000002 + 950 .set CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET, 0x00000000 + 951 .set CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR, 0x00000001 + 952 .set CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT, 0x00000002 + 953 .set CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE, 0x00000003 + 954 .set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET, 0x00000004 + 955 .set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE, 0x00000002 + 956 .set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET, 0x00000000 + 957 .set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR, 0x00000001 + 958 .set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT, 0x00000002 + 959 .set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE, 0x00000003 + 960 .set CYREG_TCPWM_CNT0_INTR, 0x40050130 + 961 .set CYFLD_TCPWM_CNT_TC__OFFSET, 0x00000000 + 962 .set CYFLD_TCPWM_CNT_TC__SIZE, 0x00000001 + 963 .set CYFLD_TCPWM_CNT_CC_MATCH__OFFSET, 0x00000001 + 964 .set CYFLD_TCPWM_CNT_CC_MATCH__SIZE, 0x00000001 + 965 .set CYREG_TCPWM_CNT0_INTR_SET, 0x40050134 + 966 .set CYREG_TCPWM_CNT0_INTR_MASK, 0x40050138 + 967 .set CYREG_TCPWM_CNT0_INTR_MASKED, 0x4005013c + 968 .set CYDEV_TCPWM_CNT1_BASE, 0x40050140 + 969 .set CYDEV_TCPWM_CNT1_SIZE, 0x00000040 + 970 .set CYREG_TCPWM_CNT1_CTRL, 0x40050140 + 971 .set CYREG_TCPWM_CNT1_STATUS, 0x40050144 + 972 .set CYREG_TCPWM_CNT1_COUNTER, 0x40050148 + 973 .set CYREG_TCPWM_CNT1_CC, 0x4005014c + 974 .set CYREG_TCPWM_CNT1_CC_BUFF, 0x40050150 + 975 .set CYREG_TCPWM_CNT1_PERIOD, 0x40050154 + 976 .set CYREG_TCPWM_CNT1_PERIOD_BUFF, 0x40050158 + 977 .set CYREG_TCPWM_CNT1_TR_CTRL0, 0x40050160 + 978 .set CYREG_TCPWM_CNT1_TR_CTRL1, 0x40050164 + 979 .set CYREG_TCPWM_CNT1_TR_CTRL2, 0x40050168 + 980 .set CYREG_TCPWM_CNT1_INTR, 0x40050170 + 981 .set CYREG_TCPWM_CNT1_INTR_SET, 0x40050174 + 982 .set CYREG_TCPWM_CNT1_INTR_MASK, 0x40050178 + 983 .set CYREG_TCPWM_CNT1_INTR_MASKED, 0x4005017c + 984 .set CYDEV_TCPWM_CNT2_BASE, 0x40050180 + 985 .set CYDEV_TCPWM_CNT2_SIZE, 0x00000040 + 986 .set CYREG_TCPWM_CNT2_CTRL, 0x40050180 + 987 .set CYREG_TCPWM_CNT2_STATUS, 0x40050184 + 988 .set CYREG_TCPWM_CNT2_COUNTER, 0x40050188 + 989 .set CYREG_TCPWM_CNT2_CC, 0x4005018c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 19 + + + 990 .set CYREG_TCPWM_CNT2_CC_BUFF, 0x40050190 + 991 .set CYREG_TCPWM_CNT2_PERIOD, 0x40050194 + 992 .set CYREG_TCPWM_CNT2_PERIOD_BUFF, 0x40050198 + 993 .set CYREG_TCPWM_CNT2_TR_CTRL0, 0x400501a0 + 994 .set CYREG_TCPWM_CNT2_TR_CTRL1, 0x400501a4 + 995 .set CYREG_TCPWM_CNT2_TR_CTRL2, 0x400501a8 + 996 .set CYREG_TCPWM_CNT2_INTR, 0x400501b0 + 997 .set CYREG_TCPWM_CNT2_INTR_SET, 0x400501b4 + 998 .set CYREG_TCPWM_CNT2_INTR_MASK, 0x400501b8 + 999 .set CYREG_TCPWM_CNT2_INTR_MASKED, 0x400501bc + 1000 .set CYDEV_TCPWM_CNT3_BASE, 0x400501c0 + 1001 .set CYDEV_TCPWM_CNT3_SIZE, 0x00000040 + 1002 .set CYREG_TCPWM_CNT3_CTRL, 0x400501c0 + 1003 .set CYREG_TCPWM_CNT3_STATUS, 0x400501c4 + 1004 .set CYREG_TCPWM_CNT3_COUNTER, 0x400501c8 + 1005 .set CYREG_TCPWM_CNT3_CC, 0x400501cc + 1006 .set CYREG_TCPWM_CNT3_CC_BUFF, 0x400501d0 + 1007 .set CYREG_TCPWM_CNT3_PERIOD, 0x400501d4 + 1008 .set CYREG_TCPWM_CNT3_PERIOD_BUFF, 0x400501d8 + 1009 .set CYREG_TCPWM_CNT3_TR_CTRL0, 0x400501e0 + 1010 .set CYREG_TCPWM_CNT3_TR_CTRL1, 0x400501e4 + 1011 .set CYREG_TCPWM_CNT3_TR_CTRL2, 0x400501e8 + 1012 .set CYREG_TCPWM_CNT3_INTR, 0x400501f0 + 1013 .set CYREG_TCPWM_CNT3_INTR_SET, 0x400501f4 + 1014 .set CYREG_TCPWM_CNT3_INTR_MASK, 0x400501f8 + 1015 .set CYREG_TCPWM_CNT3_INTR_MASKED, 0x400501fc + 1016 .set CYDEV_SCB0_BASE, 0x40060000 + 1017 .set CYDEV_SCB0_SIZE, 0x00010000 + 1018 .set CYREG_SCB0_CTRL, 0x40060000 + 1019 .set CYFLD_SCB_OVS__OFFSET, 0x00000000 + 1020 .set CYFLD_SCB_OVS__SIZE, 0x00000004 + 1021 .set CYFLD_SCB_EC_AM_MODE__OFFSET, 0x00000008 + 1022 .set CYFLD_SCB_EC_AM_MODE__SIZE, 0x00000001 + 1023 .set CYFLD_SCB_EC_OP_MODE__OFFSET, 0x00000009 + 1024 .set CYFLD_SCB_EC_OP_MODE__SIZE, 0x00000001 + 1025 .set CYFLD_SCB_EZ_MODE__OFFSET, 0x0000000a + 1026 .set CYFLD_SCB_EZ_MODE__SIZE, 0x00000001 + 1027 .set CYFLD_SCB_ADDR_ACCEPT__OFFSET, 0x00000010 + 1028 .set CYFLD_SCB_ADDR_ACCEPT__SIZE, 0x00000001 + 1029 .set CYFLD_SCB_BLOCK__OFFSET, 0x00000011 + 1030 .set CYFLD_SCB_BLOCK__SIZE, 0x00000001 + 1031 .set CYFLD_SCB_MODE__OFFSET, 0x00000018 + 1032 .set CYFLD_SCB_MODE__SIZE, 0x00000002 + 1033 .set CYVAL_SCB_MODE_I2C, 0x00000000 + 1034 .set CYVAL_SCB_MODE_SPI, 0x00000001 + 1035 .set CYVAL_SCB_MODE_UART, 0x00000002 + 1036 .set CYFLD_SCB_ENABLED__OFFSET, 0x0000001f + 1037 .set CYFLD_SCB_ENABLED__SIZE, 0x00000001 + 1038 .set CYREG_SCB0_STATUS, 0x40060004 + 1039 .set CYFLD_SCB_EC_BUSY__OFFSET, 0x00000000 + 1040 .set CYFLD_SCB_EC_BUSY__SIZE, 0x00000001 + 1041 .set CYREG_SCB0_SPI_CTRL, 0x40060020 + 1042 .set CYFLD_SCB_CONTINUOUS__OFFSET, 0x00000000 + 1043 .set CYFLD_SCB_CONTINUOUS__SIZE, 0x00000001 + 1044 .set CYFLD_SCB_SELECT_PRECEDE__OFFSET, 0x00000001 + 1045 .set CYFLD_SCB_SELECT_PRECEDE__SIZE, 0x00000001 + 1046 .set CYFLD_SCB_CPHA__OFFSET, 0x00000002 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 20 + + + 1047 .set CYFLD_SCB_CPHA__SIZE, 0x00000001 + 1048 .set CYFLD_SCB_CPOL__OFFSET, 0x00000003 + 1049 .set CYFLD_SCB_CPOL__SIZE, 0x00000001 + 1050 .set CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET, 0x00000004 + 1051 .set CYFLD_SCB_LATE_MISO_SAMPLE__SIZE, 0x00000001 + 1052 .set CYFLD_SCB_LOOPBACK__OFFSET, 0x00000010 + 1053 .set CYFLD_SCB_LOOPBACK__SIZE, 0x00000001 + 1054 .set CYFLD_SCB_SLAVE_SELECT__OFFSET, 0x0000001a + 1055 .set CYFLD_SCB_SLAVE_SELECT__SIZE, 0x00000002 + 1056 .set CYFLD_SCB_MASTER_MODE__OFFSET, 0x0000001f + 1057 .set CYFLD_SCB_MASTER_MODE__SIZE, 0x00000001 + 1058 .set CYREG_SCB0_SPI_STATUS, 0x40060024 + 1059 .set CYFLD_SCB_BUS_BUSY__OFFSET, 0x00000000 + 1060 .set CYFLD_SCB_BUS_BUSY__SIZE, 0x00000001 + 1061 .set CYFLD_SCB_EZ_ADDR__OFFSET, 0x00000008 + 1062 .set CYFLD_SCB_EZ_ADDR__SIZE, 0x00000008 + 1063 .set CYREG_SCB0_UART_CTRL, 0x40060040 + 1064 .set CYREG_SCB0_UART_TX_CTRL, 0x40060044 + 1065 .set CYFLD_SCB_STOP_BITS__OFFSET, 0x00000000 + 1066 .set CYFLD_SCB_STOP_BITS__SIZE, 0x00000003 + 1067 .set CYFLD_SCB_PARITY__OFFSET, 0x00000004 + 1068 .set CYFLD_SCB_PARITY__SIZE, 0x00000001 + 1069 .set CYFLD_SCB_PARITY_ENABLED__OFFSET, 0x00000005 + 1070 .set CYFLD_SCB_PARITY_ENABLED__SIZE, 0x00000001 + 1071 .set CYFLD_SCB_RETRY_ON_NACK__OFFSET, 0x00000008 + 1072 .set CYFLD_SCB_RETRY_ON_NACK__SIZE, 0x00000001 + 1073 .set CYREG_SCB0_UART_RX_CTRL, 0x40060048 + 1074 .set CYFLD_SCB_POLARITY__OFFSET, 0x00000006 + 1075 .set CYFLD_SCB_POLARITY__SIZE, 0x00000001 + 1076 .set CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET, 0x00000008 + 1077 .set CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE, 0x00000001 + 1078 .set CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET, 0x00000009 + 1079 .set CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE, 0x00000001 + 1080 .set CYFLD_SCB_MP_MODE__OFFSET, 0x0000000a + 1081 .set CYFLD_SCB_MP_MODE__SIZE, 0x00000001 + 1082 .set CYFLD_SCB_LIN_MODE__OFFSET, 0x0000000c + 1083 .set CYFLD_SCB_LIN_MODE__SIZE, 0x00000001 + 1084 .set CYFLD_SCB_SKIP_START__OFFSET, 0x0000000d + 1085 .set CYFLD_SCB_SKIP_START__SIZE, 0x00000001 + 1086 .set CYFLD_SCB_BREAK_WIDTH__OFFSET, 0x00000010 + 1087 .set CYFLD_SCB_BREAK_WIDTH__SIZE, 0x00000004 + 1088 .set CYREG_SCB0_UART_RX_STATUS, 0x4006004c + 1089 .set CYFLD_SCB_BR_COUNTER__OFFSET, 0x00000000 + 1090 .set CYFLD_SCB_BR_COUNTER__SIZE, 0x0000000c + 1091 .set CYREG_SCB0_I2C_CTRL, 0x40060060 + 1092 .set CYFLD_SCB_HIGH_PHASE_OVS__OFFSET, 0x00000000 + 1093 .set CYFLD_SCB_HIGH_PHASE_OVS__SIZE, 0x00000004 + 1094 .set CYFLD_SCB_LOW_PHASE_OVS__OFFSET, 0x00000004 + 1095 .set CYFLD_SCB_LOW_PHASE_OVS__SIZE, 0x00000004 + 1096 .set CYFLD_SCB_M_READY_DATA_ACK__OFFSET, 0x00000008 + 1097 .set CYFLD_SCB_M_READY_DATA_ACK__SIZE, 0x00000001 + 1098 .set CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET, 0x00000009 + 1099 .set CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE, 0x00000001 + 1100 .set CYFLD_SCB_S_GENERAL_IGNORE__OFFSET, 0x0000000b + 1101 .set CYFLD_SCB_S_GENERAL_IGNORE__SIZE, 0x00000001 + 1102 .set CYFLD_SCB_S_READY_ADDR_ACK__OFFSET, 0x0000000c + 1103 .set CYFLD_SCB_S_READY_ADDR_ACK__SIZE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 21 + + + 1104 .set CYFLD_SCB_S_READY_DATA_ACK__OFFSET, 0x0000000d + 1105 .set CYFLD_SCB_S_READY_DATA_ACK__SIZE, 0x00000001 + 1106 .set CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET, 0x0000000e + 1107 .set CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE, 0x00000001 + 1108 .set CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET, 0x0000000f + 1109 .set CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE, 0x00000001 + 1110 .set CYFLD_SCB_SLAVE_MODE__OFFSET, 0x0000001e + 1111 .set CYFLD_SCB_SLAVE_MODE__SIZE, 0x00000001 + 1112 .set CYREG_SCB0_I2C_STATUS, 0x40060064 + 1113 .set CYFLD_SCB_S_READ__OFFSET, 0x00000004 + 1114 .set CYFLD_SCB_S_READ__SIZE, 0x00000001 + 1115 .set CYFLD_SCB_M_READ__OFFSET, 0x00000005 + 1116 .set CYFLD_SCB_M_READ__SIZE, 0x00000001 + 1117 .set CYREG_SCB0_I2C_M_CMD, 0x40060068 + 1118 .set CYFLD_SCB_M_START__OFFSET, 0x00000000 + 1119 .set CYFLD_SCB_M_START__SIZE, 0x00000001 + 1120 .set CYFLD_SCB_M_START_ON_IDLE__OFFSET, 0x00000001 + 1121 .set CYFLD_SCB_M_START_ON_IDLE__SIZE, 0x00000001 + 1122 .set CYFLD_SCB_M_ACK__OFFSET, 0x00000002 + 1123 .set CYFLD_SCB_M_ACK__SIZE, 0x00000001 + 1124 .set CYFLD_SCB_M_NACK__OFFSET, 0x00000003 + 1125 .set CYFLD_SCB_M_NACK__SIZE, 0x00000001 + 1126 .set CYFLD_SCB_M_STOP__OFFSET, 0x00000004 + 1127 .set CYFLD_SCB_M_STOP__SIZE, 0x00000001 + 1128 .set CYREG_SCB0_I2C_S_CMD, 0x4006006c + 1129 .set CYFLD_SCB_S_ACK__OFFSET, 0x00000000 + 1130 .set CYFLD_SCB_S_ACK__SIZE, 0x00000001 + 1131 .set CYFLD_SCB_S_NACK__OFFSET, 0x00000001 + 1132 .set CYFLD_SCB_S_NACK__SIZE, 0x00000001 + 1133 .set CYREG_SCB0_I2C_CFG, 0x40060070 + 1134 .set CYFLD_SCB_SDA_FILT_HYS__OFFSET, 0x00000000 + 1135 .set CYFLD_SCB_SDA_FILT_HYS__SIZE, 0x00000002 + 1136 .set CYFLD_SCB_SDA_FILT_TRIM__OFFSET, 0x00000002 + 1137 .set CYFLD_SCB_SDA_FILT_TRIM__SIZE, 0x00000002 + 1138 .set CYFLD_SCB_SCL_FILT_HYS__OFFSET, 0x00000004 + 1139 .set CYFLD_SCB_SCL_FILT_HYS__SIZE, 0x00000002 + 1140 .set CYFLD_SCB_SCL_FILT_TRIM__OFFSET, 0x00000006 + 1141 .set CYFLD_SCB_SCL_FILT_TRIM__SIZE, 0x00000002 + 1142 .set CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET, 0x00000008 + 1143 .set CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE, 0x00000002 + 1144 .set CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET, 0x0000000a + 1145 .set CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE, 0x00000002 + 1146 .set CYFLD_SCB_SDA_FILT_HS__OFFSET, 0x00000010 + 1147 .set CYFLD_SCB_SDA_FILT_HS__SIZE, 0x00000001 + 1148 .set CYFLD_SCB_SDA_FILT_ENABLED__OFFSET, 0x00000011 + 1149 .set CYFLD_SCB_SDA_FILT_ENABLED__SIZE, 0x00000001 + 1150 .set CYFLD_SCB_SCL_FILT_HS__OFFSET, 0x00000018 + 1151 .set CYFLD_SCB_SCL_FILT_HS__SIZE, 0x00000001 + 1152 .set CYFLD_SCB_SCL_FILT_ENABLED__OFFSET, 0x00000019 + 1153 .set CYFLD_SCB_SCL_FILT_ENABLED__SIZE, 0x00000001 + 1154 .set CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET, 0x0000001a + 1155 .set CYFLD_SCB_SDA_FILT_OUT_HS__SIZE, 0x00000001 + 1156 .set CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET, 0x0000001b + 1157 .set CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE, 0x00000001 + 1158 .set CYREG_SCB0_BIST_CONTROL, 0x40060100 + 1159 .set CYFLD_SCB_RAM_ADDR__OFFSET, 0x00000000 + 1160 .set CYFLD_SCB_RAM_ADDR__SIZE, 0x00000005 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 22 + + + 1161 .set CYFLD_SCB_RAM_OP1__OFFSET, 0x00000010 + 1162 .set CYFLD_SCB_RAM_OP1__SIZE, 0x00000002 + 1163 .set CYFLD_SCB_RAM_OP2__OFFSET, 0x00000012 + 1164 .set CYFLD_SCB_RAM_OP2__SIZE, 0x00000002 + 1165 .set CYFLD_SCB_RAM_OP3__OFFSET, 0x00000014 + 1166 .set CYFLD_SCB_RAM_OP3__SIZE, 0x00000002 + 1167 .set CYFLD_SCB_RAM_OP4__OFFSET, 0x00000016 + 1168 .set CYFLD_SCB_RAM_OP4__SIZE, 0x00000002 + 1169 .set CYFLD_SCB_RAM_OPCNT__OFFSET, 0x00000018 + 1170 .set CYFLD_SCB_RAM_OPCNT__SIZE, 0x00000002 + 1171 .set CYFLD_SCB_RAM_PREADR__OFFSET, 0x0000001a + 1172 .set CYFLD_SCB_RAM_PREADR__SIZE, 0x00000001 + 1173 .set CYFLD_SCB_RAM_WORD__OFFSET, 0x0000001b + 1174 .set CYFLD_SCB_RAM_WORD__SIZE, 0x00000001 + 1175 .set CYFLD_SCB_RAM_FAIL__OFFSET, 0x0000001c + 1176 .set CYFLD_SCB_RAM_FAIL__SIZE, 0x00000001 + 1177 .set CYFLD_SCB_RAM_GO__OFFSET, 0x0000001d + 1178 .set CYFLD_SCB_RAM_GO__SIZE, 0x00000001 + 1179 .set CYREG_SCB0_BIST_DATA, 0x40060104 + 1180 .set CYFLD_SCB_RAM_DATA__OFFSET, 0x00000000 + 1181 .set CYFLD_SCB_RAM_DATA__SIZE, 0x00000010 + 1182 .set CYREG_SCB0_TX_CTRL, 0x40060200 + 1183 .set CYFLD_SCB_DATA_WIDTH__OFFSET, 0x00000000 + 1184 .set CYFLD_SCB_DATA_WIDTH__SIZE, 0x00000004 + 1185 .set CYFLD_SCB_MSB_FIRST__OFFSET, 0x00000008 + 1186 .set CYFLD_SCB_MSB_FIRST__SIZE, 0x00000001 + 1187 .set CYREG_SCB0_TX_FIFO_CTRL, 0x40060204 + 1188 .set CYFLD_SCB_TRIGGER_LEVEL__OFFSET, 0x00000000 + 1189 .set CYFLD_SCB_TRIGGER_LEVEL__SIZE, 0x00000003 + 1190 .set CYFLD_SCB_CLEAR__OFFSET, 0x00000010 + 1191 .set CYFLD_SCB_CLEAR__SIZE, 0x00000001 + 1192 .set CYFLD_SCB_FREEZE__OFFSET, 0x00000011 + 1193 .set CYFLD_SCB_FREEZE__SIZE, 0x00000001 + 1194 .set CYREG_SCB0_TX_FIFO_STATUS, 0x40060208 + 1195 .set CYFLD_SCB_USED__OFFSET, 0x00000000 + 1196 .set CYFLD_SCB_USED__SIZE, 0x00000004 + 1197 .set CYFLD_SCB_SR_VALID__OFFSET, 0x0000000f + 1198 .set CYFLD_SCB_SR_VALID__SIZE, 0x00000001 + 1199 .set CYFLD_SCB_RD_PTR__OFFSET, 0x00000010 + 1200 .set CYFLD_SCB_RD_PTR__SIZE, 0x00000003 + 1201 .set CYFLD_SCB_WR_PTR__OFFSET, 0x00000018 + 1202 .set CYFLD_SCB_WR_PTR__SIZE, 0x00000003 + 1203 .set CYREG_SCB0_TX_FIFO_WR, 0x40060240 + 1204 .set CYFLD_SCB_DATA__OFFSET, 0x00000000 + 1205 .set CYFLD_SCB_DATA__SIZE, 0x00000010 + 1206 .set CYREG_SCB0_RX_CTRL, 0x40060300 + 1207 .set CYFLD_SCB_MEDIAN__OFFSET, 0x00000009 + 1208 .set CYFLD_SCB_MEDIAN__SIZE, 0x00000001 + 1209 .set CYREG_SCB0_RX_FIFO_CTRL, 0x40060304 + 1210 .set CYREG_SCB0_RX_FIFO_STATUS, 0x40060308 + 1211 .set CYREG_SCB0_RX_MATCH, 0x40060310 + 1212 .set CYFLD_SCB_ADDR__OFFSET, 0x00000000 + 1213 .set CYFLD_SCB_ADDR__SIZE, 0x00000008 + 1214 .set CYFLD_SCB_MASK__OFFSET, 0x00000010 + 1215 .set CYFLD_SCB_MASK__SIZE, 0x00000008 + 1216 .set CYREG_SCB0_RX_FIFO_RD, 0x40060340 + 1217 .set CYREG_SCB0_RX_FIFO_RD_SILENT, 0x40060344 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 23 + + + 1218 .set CYREG_SCB0_EZ_DATA00, 0x40060400 + 1219 .set CYFLD_SCB_EZ_DATA__OFFSET, 0x00000000 + 1220 .set CYFLD_SCB_EZ_DATA__SIZE, 0x00000008 + 1221 .set CYREG_SCB0_EZ_DATA01, 0x40060404 + 1222 .set CYREG_SCB0_EZ_DATA02, 0x40060408 + 1223 .set CYREG_SCB0_EZ_DATA03, 0x4006040c + 1224 .set CYREG_SCB0_EZ_DATA04, 0x40060410 + 1225 .set CYREG_SCB0_EZ_DATA05, 0x40060414 + 1226 .set CYREG_SCB0_EZ_DATA06, 0x40060418 + 1227 .set CYREG_SCB0_EZ_DATA07, 0x4006041c + 1228 .set CYREG_SCB0_EZ_DATA08, 0x40060420 + 1229 .set CYREG_SCB0_EZ_DATA09, 0x40060424 + 1230 .set CYREG_SCB0_EZ_DATA10, 0x40060428 + 1231 .set CYREG_SCB0_EZ_DATA11, 0x4006042c + 1232 .set CYREG_SCB0_EZ_DATA12, 0x40060430 + 1233 .set CYREG_SCB0_EZ_DATA13, 0x40060434 + 1234 .set CYREG_SCB0_EZ_DATA14, 0x40060438 + 1235 .set CYREG_SCB0_EZ_DATA15, 0x4006043c + 1236 .set CYREG_SCB0_EZ_DATA16, 0x40060440 + 1237 .set CYREG_SCB0_EZ_DATA17, 0x40060444 + 1238 .set CYREG_SCB0_EZ_DATA18, 0x40060448 + 1239 .set CYREG_SCB0_EZ_DATA19, 0x4006044c + 1240 .set CYREG_SCB0_EZ_DATA20, 0x40060450 + 1241 .set CYREG_SCB0_EZ_DATA21, 0x40060454 + 1242 .set CYREG_SCB0_EZ_DATA22, 0x40060458 + 1243 .set CYREG_SCB0_EZ_DATA23, 0x4006045c + 1244 .set CYREG_SCB0_EZ_DATA24, 0x40060460 + 1245 .set CYREG_SCB0_EZ_DATA25, 0x40060464 + 1246 .set CYREG_SCB0_EZ_DATA26, 0x40060468 + 1247 .set CYREG_SCB0_EZ_DATA27, 0x4006046c + 1248 .set CYREG_SCB0_EZ_DATA28, 0x40060470 + 1249 .set CYREG_SCB0_EZ_DATA29, 0x40060474 + 1250 .set CYREG_SCB0_EZ_DATA30, 0x40060478 + 1251 .set CYREG_SCB0_EZ_DATA31, 0x4006047c + 1252 .set CYREG_SCB0_INTR_CAUSE, 0x40060e00 + 1253 .set CYFLD_SCB_M__OFFSET, 0x00000000 + 1254 .set CYFLD_SCB_M__SIZE, 0x00000001 + 1255 .set CYFLD_SCB_S__OFFSET, 0x00000001 + 1256 .set CYFLD_SCB_S__SIZE, 0x00000001 + 1257 .set CYFLD_SCB_TX__OFFSET, 0x00000002 + 1258 .set CYFLD_SCB_TX__SIZE, 0x00000001 + 1259 .set CYFLD_SCB_RX__OFFSET, 0x00000003 + 1260 .set CYFLD_SCB_RX__SIZE, 0x00000001 + 1261 .set CYFLD_SCB_I2C_EC__OFFSET, 0x00000004 + 1262 .set CYFLD_SCB_I2C_EC__SIZE, 0x00000001 + 1263 .set CYFLD_SCB_SPI_EC__OFFSET, 0x00000005 + 1264 .set CYFLD_SCB_SPI_EC__SIZE, 0x00000001 + 1265 .set CYREG_SCB0_INTR_I2C_EC, 0x40060e80 + 1266 .set CYFLD_SCB_WAKE_UP__OFFSET, 0x00000000 + 1267 .set CYFLD_SCB_WAKE_UP__SIZE, 0x00000001 + 1268 .set CYFLD_SCB_EZ_STOP__OFFSET, 0x00000001 + 1269 .set CYFLD_SCB_EZ_STOP__SIZE, 0x00000001 + 1270 .set CYFLD_SCB_EZ_WRITE_STOP__OFFSET, 0x00000002 + 1271 .set CYFLD_SCB_EZ_WRITE_STOP__SIZE, 0x00000001 + 1272 .set CYREG_SCB0_INTR_I2C_EC_MASK, 0x40060e88 + 1273 .set CYREG_SCB0_INTR_I2C_EC_MASKED, 0x40060e8c + 1274 .set CYREG_SCB0_INTR_SPI_EC, 0x40060ec0 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 24 + + + 1275 .set CYREG_SCB0_INTR_SPI_EC_MASK, 0x40060ec8 + 1276 .set CYREG_SCB0_INTR_SPI_EC_MASKED, 0x40060ecc + 1277 .set CYREG_SCB0_INTR_M, 0x40060f00 + 1278 .set CYFLD_SCB_I2C_ARB_LOST__OFFSET, 0x00000000 + 1279 .set CYFLD_SCB_I2C_ARB_LOST__SIZE, 0x00000001 + 1280 .set CYFLD_SCB_I2C_NACK__OFFSET, 0x00000001 + 1281 .set CYFLD_SCB_I2C_NACK__SIZE, 0x00000001 + 1282 .set CYFLD_SCB_I2C_ACK__OFFSET, 0x00000002 + 1283 .set CYFLD_SCB_I2C_ACK__SIZE, 0x00000001 + 1284 .set CYFLD_SCB_I2C_STOP__OFFSET, 0x00000004 + 1285 .set CYFLD_SCB_I2C_STOP__SIZE, 0x00000001 + 1286 .set CYFLD_SCB_I2C_BUS_ERROR__OFFSET, 0x00000008 + 1287 .set CYFLD_SCB_I2C_BUS_ERROR__SIZE, 0x00000001 + 1288 .set CYFLD_SCB_SPI_DONE__OFFSET, 0x00000009 + 1289 .set CYFLD_SCB_SPI_DONE__SIZE, 0x00000001 + 1290 .set CYREG_SCB0_INTR_M_SET, 0x40060f04 + 1291 .set CYREG_SCB0_INTR_M_MASK, 0x40060f08 + 1292 .set CYREG_SCB0_INTR_M_MASKED, 0x40060f0c + 1293 .set CYREG_SCB0_INTR_S, 0x40060f40 + 1294 .set CYFLD_SCB_I2C_WRITE_STOP__OFFSET, 0x00000003 + 1295 .set CYFLD_SCB_I2C_WRITE_STOP__SIZE, 0x00000001 + 1296 .set CYFLD_SCB_I2C_START__OFFSET, 0x00000005 + 1297 .set CYFLD_SCB_I2C_START__SIZE, 0x00000001 + 1298 .set CYFLD_SCB_I2C_ADDR_MATCH__OFFSET, 0x00000006 + 1299 .set CYFLD_SCB_I2C_ADDR_MATCH__SIZE, 0x00000001 + 1300 .set CYFLD_SCB_I2C_GENERAL__OFFSET, 0x00000007 + 1301 .set CYFLD_SCB_I2C_GENERAL__SIZE, 0x00000001 + 1302 .set CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET, 0x00000009 + 1303 .set CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE, 0x00000001 + 1304 .set CYFLD_SCB_SPI_EZ_STOP__OFFSET, 0x0000000a + 1305 .set CYFLD_SCB_SPI_EZ_STOP__SIZE, 0x00000001 + 1306 .set CYFLD_SCB_SPI_BUS_ERROR__OFFSET, 0x0000000b + 1307 .set CYFLD_SCB_SPI_BUS_ERROR__SIZE, 0x00000001 + 1308 .set CYREG_SCB0_INTR_S_SET, 0x40060f44 + 1309 .set CYREG_SCB0_INTR_S_MASK, 0x40060f48 + 1310 .set CYREG_SCB0_INTR_S_MASKED, 0x40060f4c + 1311 .set CYREG_SCB0_INTR_TX, 0x40060f80 + 1312 .set CYFLD_SCB_TRIGGER__OFFSET, 0x00000000 + 1313 .set CYFLD_SCB_TRIGGER__SIZE, 0x00000001 + 1314 .set CYFLD_SCB_NOT_FULL__OFFSET, 0x00000001 + 1315 .set CYFLD_SCB_NOT_FULL__SIZE, 0x00000001 + 1316 .set CYFLD_SCB_EMPTY__OFFSET, 0x00000004 + 1317 .set CYFLD_SCB_EMPTY__SIZE, 0x00000001 + 1318 .set CYFLD_SCB_OVERFLOW__OFFSET, 0x00000005 + 1319 .set CYFLD_SCB_OVERFLOW__SIZE, 0x00000001 + 1320 .set CYFLD_SCB_UNDERFLOW__OFFSET, 0x00000006 + 1321 .set CYFLD_SCB_UNDERFLOW__SIZE, 0x00000001 + 1322 .set CYFLD_SCB_BLOCKED__OFFSET, 0x00000007 + 1323 .set CYFLD_SCB_BLOCKED__SIZE, 0x00000001 + 1324 .set CYFLD_SCB_UART_NACK__OFFSET, 0x00000008 + 1325 .set CYFLD_SCB_UART_NACK__SIZE, 0x00000001 + 1326 .set CYFLD_SCB_UART_DONE__OFFSET, 0x00000009 + 1327 .set CYFLD_SCB_UART_DONE__SIZE, 0x00000001 + 1328 .set CYFLD_SCB_UART_ARB_LOST__OFFSET, 0x0000000a + 1329 .set CYFLD_SCB_UART_ARB_LOST__SIZE, 0x00000001 + 1330 .set CYREG_SCB0_INTR_TX_SET, 0x40060f84 + 1331 .set CYREG_SCB0_INTR_TX_MASK, 0x40060f88 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 25 + + + 1332 .set CYREG_SCB0_INTR_TX_MASKED, 0x40060f8c + 1333 .set CYREG_SCB0_INTR_RX, 0x40060fc0 + 1334 .set CYFLD_SCB_NOT_EMPTY__OFFSET, 0x00000002 + 1335 .set CYFLD_SCB_NOT_EMPTY__SIZE, 0x00000001 + 1336 .set CYFLD_SCB_FULL__OFFSET, 0x00000003 + 1337 .set CYFLD_SCB_FULL__SIZE, 0x00000001 + 1338 .set CYFLD_SCB_FRAME_ERROR__OFFSET, 0x00000008 + 1339 .set CYFLD_SCB_FRAME_ERROR__SIZE, 0x00000001 + 1340 .set CYFLD_SCB_PARITY_ERROR__OFFSET, 0x00000009 + 1341 .set CYFLD_SCB_PARITY_ERROR__SIZE, 0x00000001 + 1342 .set CYFLD_SCB_BAUD_DETECT__OFFSET, 0x0000000a + 1343 .set CYFLD_SCB_BAUD_DETECT__SIZE, 0x00000001 + 1344 .set CYFLD_SCB_BREAK_DETECT__OFFSET, 0x0000000b + 1345 .set CYFLD_SCB_BREAK_DETECT__SIZE, 0x00000001 + 1346 .set CYREG_SCB0_INTR_RX_SET, 0x40060fc4 + 1347 .set CYREG_SCB0_INTR_RX_MASK, 0x40060fc8 + 1348 .set CYREG_SCB0_INTR_RX_MASKED, 0x40060fcc + 1349 .set CYDEV_SCB1_BASE, 0x40070000 + 1350 .set CYDEV_SCB1_SIZE, 0x00010000 + 1351 .set CYREG_SCB1_CTRL, 0x40070000 + 1352 .set CYREG_SCB1_STATUS, 0x40070004 + 1353 .set CYREG_SCB1_SPI_CTRL, 0x40070020 + 1354 .set CYREG_SCB1_SPI_STATUS, 0x40070024 + 1355 .set CYREG_SCB1_UART_CTRL, 0x40070040 + 1356 .set CYREG_SCB1_UART_TX_CTRL, 0x40070044 + 1357 .set CYREG_SCB1_UART_RX_CTRL, 0x40070048 + 1358 .set CYREG_SCB1_UART_RX_STATUS, 0x4007004c + 1359 .set CYREG_SCB1_I2C_CTRL, 0x40070060 + 1360 .set CYREG_SCB1_I2C_STATUS, 0x40070064 + 1361 .set CYREG_SCB1_I2C_M_CMD, 0x40070068 + 1362 .set CYREG_SCB1_I2C_S_CMD, 0x4007006c + 1363 .set CYREG_SCB1_I2C_CFG, 0x40070070 + 1364 .set CYREG_SCB1_BIST_CONTROL, 0x40070100 + 1365 .set CYREG_SCB1_BIST_DATA, 0x40070104 + 1366 .set CYREG_SCB1_TX_CTRL, 0x40070200 + 1367 .set CYREG_SCB1_TX_FIFO_CTRL, 0x40070204 + 1368 .set CYREG_SCB1_TX_FIFO_STATUS, 0x40070208 + 1369 .set CYREG_SCB1_TX_FIFO_WR, 0x40070240 + 1370 .set CYREG_SCB1_RX_CTRL, 0x40070300 + 1371 .set CYREG_SCB1_RX_FIFO_CTRL, 0x40070304 + 1372 .set CYREG_SCB1_RX_FIFO_STATUS, 0x40070308 + 1373 .set CYREG_SCB1_RX_MATCH, 0x40070310 + 1374 .set CYREG_SCB1_RX_FIFO_RD, 0x40070340 + 1375 .set CYREG_SCB1_RX_FIFO_RD_SILENT, 0x40070344 + 1376 .set CYREG_SCB1_EZ_DATA00, 0x40070400 + 1377 .set CYREG_SCB1_EZ_DATA01, 0x40070404 + 1378 .set CYREG_SCB1_EZ_DATA02, 0x40070408 + 1379 .set CYREG_SCB1_EZ_DATA03, 0x4007040c + 1380 .set CYREG_SCB1_EZ_DATA04, 0x40070410 + 1381 .set CYREG_SCB1_EZ_DATA05, 0x40070414 + 1382 .set CYREG_SCB1_EZ_DATA06, 0x40070418 + 1383 .set CYREG_SCB1_EZ_DATA07, 0x4007041c + 1384 .set CYREG_SCB1_EZ_DATA08, 0x40070420 + 1385 .set CYREG_SCB1_EZ_DATA09, 0x40070424 + 1386 .set CYREG_SCB1_EZ_DATA10, 0x40070428 + 1387 .set CYREG_SCB1_EZ_DATA11, 0x4007042c + 1388 .set CYREG_SCB1_EZ_DATA12, 0x40070430 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 26 + + + 1389 .set CYREG_SCB1_EZ_DATA13, 0x40070434 + 1390 .set CYREG_SCB1_EZ_DATA14, 0x40070438 + 1391 .set CYREG_SCB1_EZ_DATA15, 0x4007043c + 1392 .set CYREG_SCB1_EZ_DATA16, 0x40070440 + 1393 .set CYREG_SCB1_EZ_DATA17, 0x40070444 + 1394 .set CYREG_SCB1_EZ_DATA18, 0x40070448 + 1395 .set CYREG_SCB1_EZ_DATA19, 0x4007044c + 1396 .set CYREG_SCB1_EZ_DATA20, 0x40070450 + 1397 .set CYREG_SCB1_EZ_DATA21, 0x40070454 + 1398 .set CYREG_SCB1_EZ_DATA22, 0x40070458 + 1399 .set CYREG_SCB1_EZ_DATA23, 0x4007045c + 1400 .set CYREG_SCB1_EZ_DATA24, 0x40070460 + 1401 .set CYREG_SCB1_EZ_DATA25, 0x40070464 + 1402 .set CYREG_SCB1_EZ_DATA26, 0x40070468 + 1403 .set CYREG_SCB1_EZ_DATA27, 0x4007046c + 1404 .set CYREG_SCB1_EZ_DATA28, 0x40070470 + 1405 .set CYREG_SCB1_EZ_DATA29, 0x40070474 + 1406 .set CYREG_SCB1_EZ_DATA30, 0x40070478 + 1407 .set CYREG_SCB1_EZ_DATA31, 0x4007047c + 1408 .set CYREG_SCB1_INTR_CAUSE, 0x40070e00 + 1409 .set CYREG_SCB1_INTR_I2C_EC, 0x40070e80 + 1410 .set CYREG_SCB1_INTR_I2C_EC_MASK, 0x40070e88 + 1411 .set CYREG_SCB1_INTR_I2C_EC_MASKED, 0x40070e8c + 1412 .set CYREG_SCB1_INTR_SPI_EC, 0x40070ec0 + 1413 .set CYREG_SCB1_INTR_SPI_EC_MASK, 0x40070ec8 + 1414 .set CYREG_SCB1_INTR_SPI_EC_MASKED, 0x40070ecc + 1415 .set CYREG_SCB1_INTR_M, 0x40070f00 + 1416 .set CYREG_SCB1_INTR_M_SET, 0x40070f04 + 1417 .set CYREG_SCB1_INTR_M_MASK, 0x40070f08 + 1418 .set CYREG_SCB1_INTR_M_MASKED, 0x40070f0c + 1419 .set CYREG_SCB1_INTR_S, 0x40070f40 + 1420 .set CYREG_SCB1_INTR_S_SET, 0x40070f44 + 1421 .set CYREG_SCB1_INTR_S_MASK, 0x40070f48 + 1422 .set CYREG_SCB1_INTR_S_MASKED, 0x40070f4c + 1423 .set CYREG_SCB1_INTR_TX, 0x40070f80 + 1424 .set CYREG_SCB1_INTR_TX_SET, 0x40070f84 + 1425 .set CYREG_SCB1_INTR_TX_MASK, 0x40070f88 + 1426 .set CYREG_SCB1_INTR_TX_MASKED, 0x40070f8c + 1427 .set CYREG_SCB1_INTR_RX, 0x40070fc0 + 1428 .set CYREG_SCB1_INTR_RX_SET, 0x40070fc4 + 1429 .set CYREG_SCB1_INTR_RX_MASK, 0x40070fc8 + 1430 .set CYREG_SCB1_INTR_RX_MASKED, 0x40070fcc + 1431 .set CYDEV_CSD_BASE, 0x40080000 + 1432 .set CYDEV_CSD_SIZE, 0x00010000 + 1433 .set CYREG_CSD_ID, 0x40080000 + 1434 .set CYFLD_CSD_ID__OFFSET, 0x00000000 + 1435 .set CYFLD_CSD_ID__SIZE, 0x00000010 + 1436 .set CYFLD_CSD_REVISION__OFFSET, 0x00000010 + 1437 .set CYFLD_CSD_REVISION__SIZE, 0x00000010 + 1438 .set CYREG_CSD_CONFIG, 0x40080004 + 1439 .set CYFLD_CSD_DSI_SAMPLE_EN__OFFSET, 0x00000000 + 1440 .set CYFLD_CSD_DSI_SAMPLE_EN__SIZE, 0x00000001 + 1441 .set CYFLD_CSD_SAMPLE_SYNC__OFFSET, 0x00000001 + 1442 .set CYFLD_CSD_SAMPLE_SYNC__SIZE, 0x00000001 + 1443 .set CYFLD_CSD_PRS_CLEAR__OFFSET, 0x00000005 + 1444 .set CYFLD_CSD_PRS_CLEAR__SIZE, 0x00000001 + 1445 .set CYFLD_CSD_PRS_SELECT__OFFSET, 0x00000006 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 27 + + + 1446 .set CYFLD_CSD_PRS_SELECT__SIZE, 0x00000001 + 1447 .set CYVAL_CSD_PRS_SELECT_DIV2, 0x00000000 + 1448 .set CYVAL_CSD_PRS_SELECT_PRS, 0x00000001 + 1449 .set CYFLD_CSD_PRS_12_8__OFFSET, 0x00000007 + 1450 .set CYFLD_CSD_PRS_12_8__SIZE, 0x00000001 + 1451 .set CYVAL_CSD_PRS_12_8_8B, 0x00000000 + 1452 .set CYVAL_CSD_PRS_12_8_12B, 0x00000001 + 1453 .set CYFLD_CSD_DSI_SENSE_EN__OFFSET, 0x00000008 + 1454 .set CYFLD_CSD_DSI_SENSE_EN__SIZE, 0x00000001 + 1455 .set CYFLD_CSD_SHIELD_DELAY__OFFSET, 0x00000009 + 1456 .set CYFLD_CSD_SHIELD_DELAY__SIZE, 0x00000002 + 1457 .set CYFLD_CSD_SENSE_COMP_BW__OFFSET, 0x0000000b + 1458 .set CYFLD_CSD_SENSE_COMP_BW__SIZE, 0x00000001 + 1459 .set CYVAL_CSD_SENSE_COMP_BW_LOW, 0x00000000 + 1460 .set CYVAL_CSD_SENSE_COMP_BW_HIGH, 0x00000001 + 1461 .set CYFLD_CSD_SENSE_EN__OFFSET, 0x0000000c + 1462 .set CYFLD_CSD_SENSE_EN__SIZE, 0x00000001 + 1463 .set CYFLD_CSD_REFBUF_EN__OFFSET, 0x0000000d + 1464 .set CYFLD_CSD_REFBUF_EN__SIZE, 0x00000001 + 1465 .set CYFLD_CSD_COMP_MODE__OFFSET, 0x0000000e + 1466 .set CYFLD_CSD_COMP_MODE__SIZE, 0x00000001 + 1467 .set CYVAL_CSD_COMP_MODE_CHARGE_BUF, 0x00000000 + 1468 .set CYVAL_CSD_COMP_MODE_CHARGE_IO, 0x00000001 + 1469 .set CYFLD_CSD_COMP_PIN__OFFSET, 0x0000000f + 1470 .set CYFLD_CSD_COMP_PIN__SIZE, 0x00000001 + 1471 .set CYVAL_CSD_COMP_PIN_CHANNEL1, 0x00000000 + 1472 .set CYVAL_CSD_COMP_PIN_CHANNEL2, 0x00000001 + 1473 .set CYFLD_CSD_POLARITY__OFFSET, 0x00000010 + 1474 .set CYFLD_CSD_POLARITY__SIZE, 0x00000001 + 1475 .set CYVAL_CSD_POLARITY_VSSIO, 0x00000000 + 1476 .set CYVAL_CSD_POLARITY_VDDIO, 0x00000001 + 1477 .set CYFLD_CSD_POLARITY2__OFFSET, 0x00000011 + 1478 .set CYFLD_CSD_POLARITY2__SIZE, 0x00000001 + 1479 .set CYVAL_CSD_POLARITY2_VSSIO, 0x00000000 + 1480 .set CYVAL_CSD_POLARITY2_VDDIO, 0x00000001 + 1481 .set CYFLD_CSD_MUTUAL_CAP__OFFSET, 0x00000012 + 1482 .set CYFLD_CSD_MUTUAL_CAP__SIZE, 0x00000001 + 1483 .set CYVAL_CSD_MUTUAL_CAP_SELFCAP, 0x00000000 + 1484 .set CYVAL_CSD_MUTUAL_CAP_MUTUALCAP, 0x00000001 + 1485 .set CYFLD_CSD_SENSE_COMP_EN__OFFSET, 0x00000013 + 1486 .set CYFLD_CSD_SENSE_COMP_EN__SIZE, 0x00000001 + 1487 .set CYFLD_CSD_REBUF_OUTSEL__OFFSET, 0x00000015 + 1488 .set CYFLD_CSD_REBUF_OUTSEL__SIZE, 0x00000001 + 1489 .set CYVAL_CSD_REBUF_OUTSEL_AMUXA, 0x00000000 + 1490 .set CYVAL_CSD_REBUF_OUTSEL_AMUXB, 0x00000001 + 1491 .set CYFLD_CSD_SENSE_INSEL__OFFSET, 0x00000016 + 1492 .set CYFLD_CSD_SENSE_INSEL__SIZE, 0x00000001 + 1493 .set CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1, 0x00000000 + 1494 .set CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA, 0x00000001 + 1495 .set CYFLD_CSD_REFBUF_DRV__OFFSET, 0x00000017 + 1496 .set CYFLD_CSD_REFBUF_DRV__SIZE, 0x00000002 + 1497 .set CYVAL_CSD_REFBUF_DRV_OFF, 0x00000000 + 1498 .set CYVAL_CSD_REFBUF_DRV_DRV_1, 0x00000001 + 1499 .set CYVAL_CSD_REFBUF_DRV_DRV_2, 0x00000002 + 1500 .set CYVAL_CSD_REFBUF_DRV_DRV_3, 0x00000003 + 1501 .set CYFLD_CSD_DDFTSEL__OFFSET, 0x0000001a + 1502 .set CYFLD_CSD_DDFTSEL__SIZE, 0x00000003 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 28 + + + 1503 .set CYVAL_CSD_DDFTSEL_NORMAL, 0x00000000 + 1504 .set CYVAL_CSD_DDFTSEL_CSD_SENSE, 0x00000001 + 1505 .set CYVAL_CSD_DDFTSEL_CSD_SHIELD, 0x00000002 + 1506 .set CYVAL_CSD_DDFTSEL_CLK_SAMPLE, 0x00000003 + 1507 .set CYVAL_CSD_DDFTSEL_COMP_OUT, 0x00000004 + 1508 .set CYFLD_CSD_ADFTEN__OFFSET, 0x0000001d + 1509 .set CYFLD_CSD_ADFTEN__SIZE, 0x00000001 + 1510 .set CYFLD_CSD_DDFTCOMP__OFFSET, 0x0000001e + 1511 .set CYFLD_CSD_DDFTCOMP__SIZE, 0x00000001 + 1512 .set CYVAL_CSD_DDFTCOMP_REFBUFCOMP, 0x00000000 + 1513 .set CYVAL_CSD_DDFTCOMP_SENSECOMP, 0x00000001 + 1514 .set CYFLD_CSD_ENABLE__OFFSET, 0x0000001f + 1515 .set CYFLD_CSD_ENABLE__SIZE, 0x00000001 + 1516 .set CYREG_CSD_IDAC, 0x40080008 + 1517 .set CYFLD_CSD_IDAC1__OFFSET, 0x00000000 + 1518 .set CYFLD_CSD_IDAC1__SIZE, 0x00000008 + 1519 .set CYFLD_CSD_IDAC1_MODE__OFFSET, 0x00000008 + 1520 .set CYFLD_CSD_IDAC1_MODE__SIZE, 0x00000002 + 1521 .set CYVAL_CSD_IDAC1_MODE_OFF, 0x00000000 + 1522 .set CYVAL_CSD_IDAC1_MODE_FIXED, 0x00000001 + 1523 .set CYVAL_CSD_IDAC1_MODE_VARIABLE, 0x00000002 + 1524 .set CYVAL_CSD_IDAC1_MODE_DSI, 0x00000003 + 1525 .set CYFLD_CSD_IDAC1_RANGE__OFFSET, 0x0000000a + 1526 .set CYFLD_CSD_IDAC1_RANGE__SIZE, 0x00000001 + 1527 .set CYVAL_CSD_IDAC1_RANGE_4X, 0x00000000 + 1528 .set CYVAL_CSD_IDAC1_RANGE_8X, 0x00000001 + 1529 .set CYFLD_CSD_IDAC2__OFFSET, 0x00000010 + 1530 .set CYFLD_CSD_IDAC2__SIZE, 0x00000007 + 1531 .set CYFLD_CSD_IDAC2_MODE__OFFSET, 0x00000018 + 1532 .set CYFLD_CSD_IDAC2_MODE__SIZE, 0x00000002 + 1533 .set CYVAL_CSD_IDAC2_MODE_OFF, 0x00000000 + 1534 .set CYVAL_CSD_IDAC2_MODE_FIXED, 0x00000001 + 1535 .set CYVAL_CSD_IDAC2_MODE_VARIABLE, 0x00000002 + 1536 .set CYVAL_CSD_IDAC2_MODE_DSI, 0x00000003 + 1537 .set CYFLD_CSD_IDAC2_RANGE__OFFSET, 0x0000001a + 1538 .set CYFLD_CSD_IDAC2_RANGE__SIZE, 0x00000001 + 1539 .set CYVAL_CSD_IDAC2_RANGE_4X, 0x00000000 + 1540 .set CYVAL_CSD_IDAC2_RANGE_8X, 0x00000001 + 1541 .set CYFLD_CSD_FEEDBACK_MODE__OFFSET, 0x0000001e + 1542 .set CYFLD_CSD_FEEDBACK_MODE__SIZE, 0x00000001 + 1543 .set CYVAL_CSD_FEEDBACK_MODE_FLOP, 0x00000000 + 1544 .set CYVAL_CSD_FEEDBACK_MODE_COMP, 0x00000001 + 1545 .set CYREG_CSD_COUNTER, 0x4008000c + 1546 .set CYFLD_CSD_COUNTER__OFFSET, 0x00000000 + 1547 .set CYFLD_CSD_COUNTER__SIZE, 0x00000010 + 1548 .set CYFLD_CSD_PERIOD__OFFSET, 0x00000010 + 1549 .set CYFLD_CSD_PERIOD__SIZE, 0x00000010 + 1550 .set CYREG_CSD_STATUS, 0x40080010 + 1551 .set CYFLD_CSD_CSD_CHARGE__OFFSET, 0x00000000 + 1552 .set CYFLD_CSD_CSD_CHARGE__SIZE, 0x00000001 + 1553 .set CYFLD_CSD_CSD_SENSE__OFFSET, 0x00000001 + 1554 .set CYFLD_CSD_CSD_SENSE__SIZE, 0x00000001 + 1555 .set CYFLD_CSD_COMP_OUT__OFFSET, 0x00000002 + 1556 .set CYFLD_CSD_COMP_OUT__SIZE, 0x00000001 + 1557 .set CYVAL_CSD_COMP_OUT_C_LT_VREF, 0x00000000 + 1558 .set CYVAL_CSD_COMP_OUT_C_GT_VREF, 0x00000001 + 1559 .set CYFLD_CSD_SAMPLE__OFFSET, 0x00000003 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 29 + + + 1560 .set CYFLD_CSD_SAMPLE__SIZE, 0x00000001 + 1561 .set CYREG_CSD_INTR, 0x40080014 + 1562 .set CYFLD_CSD_CSD__OFFSET, 0x00000000 + 1563 .set CYFLD_CSD_CSD__SIZE, 0x00000001 + 1564 .set CYREG_CSD_INTR_SET, 0x40080018 + 1565 .set CYREG_CSD_TRIM1, 0x4008ff00 + 1566 .set CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET, 0x00000000 + 1567 .set CYFLD_CSD_IDAC1_SRC_TRIM__SIZE, 0x00000004 + 1568 .set CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET, 0x00000004 + 1569 .set CYFLD_CSD_IDAC2_SRC_TRIM__SIZE, 0x00000004 + 1570 .set CYREG_CSD_TRIM2, 0x4008ff04 + 1571 .set CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET, 0x00000000 + 1572 .set CYFLD_CSD_IDAC1_SNK_TRIM__SIZE, 0x00000004 + 1573 .set CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET, 0x00000004 + 1574 .set CYFLD_CSD_IDAC2_SNK_TRIM__SIZE, 0x00000004 + 1575 .set CYDEV_LCD_BASE, 0x40090000 + 1576 .set CYDEV_LCD_SIZE, 0x00010000 + 1577 .set CYREG_LCD_ID, 0x40090000 + 1578 .set CYFLD_LCD_ID__OFFSET, 0x00000000 + 1579 .set CYFLD_LCD_ID__SIZE, 0x00000010 + 1580 .set CYFLD_LCD_REVISION__OFFSET, 0x00000010 + 1581 .set CYFLD_LCD_REVISION__SIZE, 0x00000010 + 1582 .set CYREG_LCD_DIVIDER, 0x40090004 + 1583 .set CYFLD_LCD_SUBFR_DIV__OFFSET, 0x00000000 + 1584 .set CYFLD_LCD_SUBFR_DIV__SIZE, 0x00000010 + 1585 .set CYFLD_LCD_DEAD_DIV__OFFSET, 0x00000010 + 1586 .set CYFLD_LCD_DEAD_DIV__SIZE, 0x00000010 + 1587 .set CYREG_LCD_CONTROL, 0x40090008 + 1588 .set CYFLD_LCD_LS_EN__OFFSET, 0x00000000 + 1589 .set CYFLD_LCD_LS_EN__SIZE, 0x00000001 + 1590 .set CYFLD_LCD_HS_EN__OFFSET, 0x00000001 + 1591 .set CYFLD_LCD_HS_EN__SIZE, 0x00000001 + 1592 .set CYFLD_LCD_LCD_MODE__OFFSET, 0x00000002 + 1593 .set CYFLD_LCD_LCD_MODE__SIZE, 0x00000001 + 1594 .set CYVAL_LCD_LCD_MODE_LS, 0x00000000 + 1595 .set CYVAL_LCD_LCD_MODE_HS, 0x00000001 + 1596 .set CYFLD_LCD_TYPE__OFFSET, 0x00000003 + 1597 .set CYFLD_LCD_TYPE__SIZE, 0x00000001 + 1598 .set CYVAL_LCD_TYPE_A, 0x00000000 + 1599 .set CYVAL_LCD_TYPE_B, 0x00000001 + 1600 .set CYFLD_LCD_OP_MODE__OFFSET, 0x00000004 + 1601 .set CYFLD_LCD_OP_MODE__SIZE, 0x00000001 + 1602 .set CYVAL_LCD_OP_MODE_PWM, 0x00000000 + 1603 .set CYVAL_LCD_OP_MODE_CORRELATION, 0x00000001 + 1604 .set CYFLD_LCD_BIAS__OFFSET, 0x00000005 + 1605 .set CYFLD_LCD_BIAS__SIZE, 0x00000002 + 1606 .set CYVAL_LCD_BIAS_HALF, 0x00000000 + 1607 .set CYVAL_LCD_BIAS_THIRD, 0x00000001 + 1608 .set CYVAL_LCD_BIAS_FOURTH, 0x00000002 + 1609 .set CYVAL_LCD_BIAS_FIFTH, 0x00000003 + 1610 .set CYFLD_LCD_COM_NUM__OFFSET, 0x00000008 + 1611 .set CYFLD_LCD_COM_NUM__SIZE, 0x00000004 + 1612 .set CYFLD_LCD_LS_EN_STAT__OFFSET, 0x0000001f + 1613 .set CYFLD_LCD_LS_EN_STAT__SIZE, 0x00000001 + 1614 .set CYREG_LCD_DATA00, 0x40090100 + 1615 .set CYFLD_LCD_DATA__OFFSET, 0x00000000 + 1616 .set CYFLD_LCD_DATA__SIZE, 0x00000020 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 30 + + + 1617 .set CYREG_LCD_DATA01, 0x40090104 + 1618 .set CYREG_LCD_DATA02, 0x40090108 + 1619 .set CYREG_LCD_DATA03, 0x4009010c + 1620 .set CYREG_LCD_DATA04, 0x40090110 + 1621 .set CYDEV_LPCOMP_BASE, 0x400a0000 + 1622 .set CYDEV_LPCOMP_SIZE, 0x00010000 + 1623 .set CYREG_LPCOMP_ID, 0x400a0000 + 1624 .set CYFLD_LPCOMP_ID__OFFSET, 0x00000000 + 1625 .set CYFLD_LPCOMP_ID__SIZE, 0x00000010 + 1626 .set CYFLD_LPCOMP_REVISION__OFFSET, 0x00000010 + 1627 .set CYFLD_LPCOMP_REVISION__SIZE, 0x00000010 + 1628 .set CYREG_LPCOMP_CONFIG, 0x400a0004 + 1629 .set CYFLD_LPCOMP_MODE1__OFFSET, 0x00000000 + 1630 .set CYFLD_LPCOMP_MODE1__SIZE, 0x00000002 + 1631 .set CYVAL_LPCOMP_MODE1_SLOW, 0x00000000 + 1632 .set CYVAL_LPCOMP_MODE1_FAST, 0x00000001 + 1633 .set CYVAL_LPCOMP_MODE1_ULP, 0x00000002 + 1634 .set CYFLD_LPCOMP_HYST1__OFFSET, 0x00000002 + 1635 .set CYFLD_LPCOMP_HYST1__SIZE, 0x00000001 + 1636 .set CYFLD_LPCOMP_FILTER1__OFFSET, 0x00000003 + 1637 .set CYFLD_LPCOMP_FILTER1__SIZE, 0x00000001 + 1638 .set CYFLD_LPCOMP_INTTYPE1__OFFSET, 0x00000004 + 1639 .set CYFLD_LPCOMP_INTTYPE1__SIZE, 0x00000002 + 1640 .set CYVAL_LPCOMP_INTTYPE1_DISABLE, 0x00000000 + 1641 .set CYVAL_LPCOMP_INTTYPE1_RISING, 0x00000001 + 1642 .set CYVAL_LPCOMP_INTTYPE1_FALLING, 0x00000002 + 1643 .set CYVAL_LPCOMP_INTTYPE1_BOTH, 0x00000003 + 1644 .set CYFLD_LPCOMP_OUT1__OFFSET, 0x00000006 + 1645 .set CYFLD_LPCOMP_OUT1__SIZE, 0x00000001 + 1646 .set CYFLD_LPCOMP_ENABLE1__OFFSET, 0x00000007 + 1647 .set CYFLD_LPCOMP_ENABLE1__SIZE, 0x00000001 + 1648 .set CYFLD_LPCOMP_MODE2__OFFSET, 0x00000008 + 1649 .set CYFLD_LPCOMP_MODE2__SIZE, 0x00000002 + 1650 .set CYVAL_LPCOMP_MODE2_SLOW, 0x00000000 + 1651 .set CYVAL_LPCOMP_MODE2_FAST, 0x00000001 + 1652 .set CYVAL_LPCOMP_MODE2_ULP, 0x00000002 + 1653 .set CYFLD_LPCOMP_HYST2__OFFSET, 0x0000000a + 1654 .set CYFLD_LPCOMP_HYST2__SIZE, 0x00000001 + 1655 .set CYFLD_LPCOMP_FILTER2__OFFSET, 0x0000000b + 1656 .set CYFLD_LPCOMP_FILTER2__SIZE, 0x00000001 + 1657 .set CYFLD_LPCOMP_INTTYPE2__OFFSET, 0x0000000c + 1658 .set CYFLD_LPCOMP_INTTYPE2__SIZE, 0x00000002 + 1659 .set CYVAL_LPCOMP_INTTYPE2_DISABLE, 0x00000000 + 1660 .set CYVAL_LPCOMP_INTTYPE2_RISING, 0x00000001 + 1661 .set CYVAL_LPCOMP_INTTYPE2_FALLING, 0x00000002 + 1662 .set CYVAL_LPCOMP_INTTYPE2_BOTH, 0x00000003 + 1663 .set CYFLD_LPCOMP_OUT2__OFFSET, 0x0000000e + 1664 .set CYFLD_LPCOMP_OUT2__SIZE, 0x00000001 + 1665 .set CYFLD_LPCOMP_ENABLE2__OFFSET, 0x0000000f + 1666 .set CYFLD_LPCOMP_ENABLE2__SIZE, 0x00000001 + 1667 .set CYREG_LPCOMP_DFT, 0x400a0008 + 1668 .set CYFLD_LPCOMP_CAL_EN__OFFSET, 0x00000000 + 1669 .set CYFLD_LPCOMP_CAL_EN__SIZE, 0x00000001 + 1670 .set CYFLD_LPCOMP_BYPASS__OFFSET, 0x00000001 + 1671 .set CYFLD_LPCOMP_BYPASS__SIZE, 0x00000001 + 1672 .set CYREG_LPCOMP_INTR, 0x400a000c + 1673 .set CYFLD_LPCOMP_COMP1__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 31 + + + 1674 .set CYFLD_LPCOMP_COMP1__SIZE, 0x00000001 + 1675 .set CYFLD_LPCOMP_COMP2__OFFSET, 0x00000001 + 1676 .set CYFLD_LPCOMP_COMP2__SIZE, 0x00000001 + 1677 .set CYREG_LPCOMP_INTR_SET, 0x400a0010 + 1678 .set CYREG_LPCOMP_TRIM1, 0x400aff00 + 1679 .set CYFLD_LPCOMP_COMP1_TRIMA__OFFSET, 0x00000000 + 1680 .set CYFLD_LPCOMP_COMP1_TRIMA__SIZE, 0x00000005 + 1681 .set CYREG_LPCOMP_TRIM2, 0x400aff04 + 1682 .set CYFLD_LPCOMP_COMP1_TRIMB__OFFSET, 0x00000000 + 1683 .set CYFLD_LPCOMP_COMP1_TRIMB__SIZE, 0x00000005 + 1684 .set CYREG_LPCOMP_TRIM3, 0x400aff08 + 1685 .set CYFLD_LPCOMP_COMP2_TRIMA__OFFSET, 0x00000000 + 1686 .set CYFLD_LPCOMP_COMP2_TRIMA__SIZE, 0x00000005 + 1687 .set CYREG_LPCOMP_TRIM4, 0x400aff0c + 1688 .set CYFLD_LPCOMP_COMP2_TRIMB__OFFSET, 0x00000000 + 1689 .set CYFLD_LPCOMP_COMP2_TRIMB__SIZE, 0x00000005 + 1690 .set CYREG_PWR_CONTROL, 0x400b0000 + 1691 .set CYFLD__POWER_MODE__OFFSET, 0x00000000 + 1692 .set CYFLD__POWER_MODE__SIZE, 0x00000004 + 1693 .set CYVAL__POWER_MODE_RESET, 0x00000000 + 1694 .set CYVAL__POWER_MODE_ACTIVE, 0x00000001 + 1695 .set CYVAL__POWER_MODE_SLEEP, 0x00000002 + 1696 .set CYVAL__POWER_MODE_DEEP_SLEEP, 0x00000003 + 1697 .set CYVAL__POWER_MODE_HIBERNATE, 0x00000004 + 1698 .set CYFLD__DEBUG_SESSION__OFFSET, 0x00000004 + 1699 .set CYFLD__DEBUG_SESSION__SIZE, 0x00000001 + 1700 .set CYVAL__DEBUG_SESSION_NO_SESSION, 0x00000000 + 1701 .set CYVAL__DEBUG_SESSION_SESSION_ACTIVE, 0x00000001 + 1702 .set CYFLD__LPM_READY__OFFSET, 0x00000005 + 1703 .set CYFLD__LPM_READY__SIZE, 0x00000001 + 1704 .set CYFLD__EXT_VCCD__OFFSET, 0x00000017 + 1705 .set CYFLD__EXT_VCCD__SIZE, 0x00000001 + 1706 .set CYFLD__HVMON_ENABLE__OFFSET, 0x00000018 + 1707 .set CYFLD__HVMON_ENABLE__SIZE, 0x00000001 + 1708 .set CYFLD__HVMON_RELOAD__OFFSET, 0x00000019 + 1709 .set CYFLD__HVMON_RELOAD__SIZE, 0x00000001 + 1710 .set CYFLD__FIMO_DISABLE__OFFSET, 0x0000001b + 1711 .set CYFLD__FIMO_DISABLE__SIZE, 0x00000001 + 1712 .set CYFLD__HIBERNATE_DISABLE__OFFSET, 0x0000001c + 1713 .set CYFLD__HIBERNATE_DISABLE__SIZE, 0x00000001 + 1714 .set CYFLD__LFCLK_SHORT__OFFSET, 0x0000001d + 1715 .set CYFLD__LFCLK_SHORT__SIZE, 0x00000001 + 1716 .set CYFLD__HIBERNATE__OFFSET, 0x0000001f + 1717 .set CYFLD__HIBERNATE__SIZE, 0x00000001 + 1718 .set CYVAL__HIBERNATE_DEEP_SLEEP, 0x00000000 + 1719 .set CYVAL__HIBERNATE_HIBERNATE, 0x00000001 + 1720 .set CYREG_PWR_INTR, 0x400b0004 + 1721 .set CYFLD__LVD__OFFSET, 0x00000001 + 1722 .set CYFLD__LVD__SIZE, 0x00000001 + 1723 .set CYREG_PWR_INTR_MASK, 0x400b0008 + 1724 .set CYREG_PWR_KEY_DELAY, 0x400b000c + 1725 .set CYFLD__WAKEUP_HOLDOFF__OFFSET, 0x00000000 + 1726 .set CYFLD__WAKEUP_HOLDOFF__SIZE, 0x0000000a + 1727 .set CYREG_PWR_PWRSYS_CONFIG, 0x400b0010 + 1728 .set CYFLD__HIB_TEST_EN__OFFSET, 0x00000008 + 1729 .set CYFLD__HIB_TEST_EN__SIZE, 0x00000001 + 1730 .set CYFLD__HIB_TEST_REP__OFFSET, 0x00000009 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 32 + + + 1731 .set CYFLD__HIB_TEST_REP__SIZE, 0x00000001 + 1732 .set CYREG_PWR_BG_CONFIG, 0x400b0014 + 1733 .set CYFLD__BG_DFT_EN__OFFSET, 0x00000000 + 1734 .set CYFLD__BG_DFT_EN__SIZE, 0x00000001 + 1735 .set CYFLD__BG_DFT_VREF_SEL__OFFSET, 0x00000001 + 1736 .set CYFLD__BG_DFT_VREF_SEL__SIZE, 0x00000004 + 1737 .set CYFLD__BG_DFT_CORE_SEL__OFFSET, 0x00000005 + 1738 .set CYFLD__BG_DFT_CORE_SEL__SIZE, 0x00000001 + 1739 .set CYFLD__BG_DFT_ICORE_SEL__OFFSET, 0x00000006 + 1740 .set CYFLD__BG_DFT_ICORE_SEL__SIZE, 0x00000002 + 1741 .set CYFLD__BG_DFT_VCORE_SEL__OFFSET, 0x00000008 + 1742 .set CYFLD__BG_DFT_VCORE_SEL__SIZE, 0x00000001 + 1743 .set CYFLD__VREF_EN__OFFSET, 0x00000010 + 1744 .set CYFLD__VREF_EN__SIZE, 0x00000003 + 1745 .set CYREG_PWR_VMON_CONFIG, 0x400b0018 + 1746 .set CYFLD__LVD_EN__OFFSET, 0x00000000 + 1747 .set CYFLD__LVD_EN__SIZE, 0x00000001 + 1748 .set CYFLD__LVD_SEL__OFFSET, 0x00000001 + 1749 .set CYFLD__LVD_SEL__SIZE, 0x00000004 + 1750 .set CYFLD__VMON_DDFT_SEL__OFFSET, 0x00000005 + 1751 .set CYFLD__VMON_DDFT_SEL__SIZE, 0x00000003 + 1752 .set CYFLD__VMON_ADFT_SEL__OFFSET, 0x00000008 + 1753 .set CYFLD__VMON_ADFT_SEL__SIZE, 0x00000002 + 1754 .set CYREG_PWR_DFT_SELECT, 0x400b001c + 1755 .set CYFLD__TVMON1_SEL__OFFSET, 0x00000000 + 1756 .set CYFLD__TVMON1_SEL__SIZE, 0x00000003 + 1757 .set CYFLD__TVMON2_SEL__OFFSET, 0x00000003 + 1758 .set CYFLD__TVMON2_SEL__SIZE, 0x00000003 + 1759 .set CYFLD__BYPASS__OFFSET, 0x00000006 + 1760 .set CYFLD__BYPASS__SIZE, 0x00000001 + 1761 .set CYFLD__ACTIVE_EN__OFFSET, 0x00000007 + 1762 .set CYFLD__ACTIVE_EN__SIZE, 0x00000001 + 1763 .set CYFLD__ACTIVE_INRUSH_DIS__OFFSET, 0x00000008 + 1764 .set CYFLD__ACTIVE_INRUSH_DIS__SIZE, 0x00000001 + 1765 .set CYFLD__LPCOMP_DIS__OFFSET, 0x00000009 + 1766 .set CYFLD__LPCOMP_DIS__SIZE, 0x00000001 + 1767 .set CYFLD__BLEED_EN__OFFSET, 0x0000000a + 1768 .set CYFLD__BLEED_EN__SIZE, 0x00000001 + 1769 .set CYFLD__IPOR_EN__OFFSET, 0x0000000b + 1770 .set CYFLD__IPOR_EN__SIZE, 0x00000001 + 1771 .set CYFLD__POWER_UP_RAW_BYP__OFFSET, 0x0000000c + 1772 .set CYFLD__POWER_UP_RAW_BYP__SIZE, 0x00000001 + 1773 .set CYFLD__POWER_UP_RAW_CTL__OFFSET, 0x0000000d + 1774 .set CYFLD__POWER_UP_RAW_CTL__SIZE, 0x00000001 + 1775 .set CYFLD__DEEPSLEEP_EN__OFFSET, 0x0000000e + 1776 .set CYFLD__DEEPSLEEP_EN__SIZE, 0x00000001 + 1777 .set CYFLD__RSVD_BYPASS__OFFSET, 0x0000000f + 1778 .set CYFLD__RSVD_BYPASS__SIZE, 0x00000001 + 1779 .set CYFLD__NWELL_OPEN__OFFSET, 0x00000010 + 1780 .set CYFLD__NWELL_OPEN__SIZE, 0x00000001 + 1781 .set CYFLD__HIBERNATE_OPEN__OFFSET, 0x00000011 + 1782 .set CYFLD__HIBERNATE_OPEN__SIZE, 0x00000001 + 1783 .set CYFLD__DEEPSLEEP_OPEN__OFFSET, 0x00000012 + 1784 .set CYFLD__DEEPSLEEP_OPEN__SIZE, 0x00000001 + 1785 .set CYFLD__QUIET_OPEN__OFFSET, 0x00000013 + 1786 .set CYFLD__QUIET_OPEN__SIZE, 0x00000001 + 1787 .set CYFLD__LFCLK_OPEN__OFFSET, 0x00000014 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 33 + + + 1788 .set CYFLD__LFCLK_OPEN__SIZE, 0x00000001 + 1789 .set CYFLD__QUIET_EN__OFFSET, 0x00000016 + 1790 .set CYFLD__QUIET_EN__SIZE, 0x00000001 + 1791 .set CYFLD__BREF_EN__OFFSET, 0x00000017 + 1792 .set CYFLD__BREF_EN__SIZE, 0x00000001 + 1793 .set CYFLD__BREF_OUTEN__OFFSET, 0x00000018 + 1794 .set CYFLD__BREF_OUTEN__SIZE, 0x00000001 + 1795 .set CYFLD__BREF_REFSW__OFFSET, 0x00000019 + 1796 .set CYFLD__BREF_REFSW__SIZE, 0x00000001 + 1797 .set CYFLD__BREF_TESTMODE__OFFSET, 0x0000001a + 1798 .set CYFLD__BREF_TESTMODE__SIZE, 0x00000001 + 1799 .set CYFLD__NWELL_DIS__OFFSET, 0x0000001b + 1800 .set CYFLD__NWELL_DIS__SIZE, 0x00000001 + 1801 .set CYFLD__HVMON_DFT_OVR__OFFSET, 0x0000001c + 1802 .set CYFLD__HVMON_DFT_OVR__SIZE, 0x00000001 + 1803 .set CYFLD__IMO_REFGEN_DIS__OFFSET, 0x0000001d + 1804 .set CYFLD__IMO_REFGEN_DIS__SIZE, 0x00000001 + 1805 .set CYFLD__POWER_UP_ACTIVE__OFFSET, 0x0000001e + 1806 .set CYFLD__POWER_UP_ACTIVE__SIZE, 0x00000001 + 1807 .set CYFLD__POWER_UP_HIBDPSLP__OFFSET, 0x0000001f + 1808 .set CYFLD__POWER_UP_HIBDPSLP__SIZE, 0x00000001 + 1809 .set CYREG_PWR_DDFT_SELECT, 0x400b0020 + 1810 .set CYFLD__DDFT1_SEL__OFFSET, 0x00000000 + 1811 .set CYFLD__DDFT1_SEL__SIZE, 0x00000004 + 1812 .set CYFLD__DDFT2_SEL__OFFSET, 0x00000004 + 1813 .set CYFLD__DDFT2_SEL__SIZE, 0x00000004 + 1814 .set CYREG_PWR_DFT_KEY, 0x400b0024 + 1815 .set CYFLD__KEY16__OFFSET, 0x00000000 + 1816 .set CYFLD__KEY16__SIZE, 0x00000010 + 1817 .set CYFLD__HBOD_OFF_AWAKE__OFFSET, 0x00000010 + 1818 .set CYFLD__HBOD_OFF_AWAKE__SIZE, 0x00000001 + 1819 .set CYFLD__BODS_OFF__OFFSET, 0x00000011 + 1820 .set CYFLD__BODS_OFF__SIZE, 0x00000001 + 1821 .set CYFLD__DFT_MODE__OFFSET, 0x00000012 + 1822 .set CYFLD__DFT_MODE__SIZE, 0x00000001 + 1823 .set CYFLD__IO_DISABLE_BYPASS__OFFSET, 0x00000013 + 1824 .set CYFLD__IO_DISABLE_BYPASS__SIZE, 0x00000001 + 1825 .set CYFLD__VMON_PD__OFFSET, 0x00000014 + 1826 .set CYFLD__VMON_PD__SIZE, 0x00000001 + 1827 .set CYREG_PWR_BOD_KEY, 0x400b0028 + 1828 .set CYREG_PWR_STOP, 0x400b002c + 1829 .set CYFLD__TOKEN__OFFSET, 0x00000000 + 1830 .set CYFLD__TOKEN__SIZE, 0x00000008 + 1831 .set CYFLD__UNLOCK__OFFSET, 0x00000008 + 1832 .set CYFLD__UNLOCK__SIZE, 0x00000008 + 1833 .set CYFLD__POLARITY__OFFSET, 0x00000010 + 1834 .set CYFLD__POLARITY__SIZE, 0x00000001 + 1835 .set CYFLD__FREEZE__OFFSET, 0x00000011 + 1836 .set CYFLD__FREEZE__SIZE, 0x00000001 + 1837 .set CYFLD__STOP__OFFSET, 0x0000001f + 1838 .set CYFLD__STOP__SIZE, 0x00000001 + 1839 .set CYREG_CLK_SELECT, 0x400b0100 + 1840 .set CYFLD__DIRECT_SEL__OFFSET, 0x00000000 + 1841 .set CYFLD__DIRECT_SEL__SIZE, 0x00000003 + 1842 .set CYVAL__DIRECT_SEL_IMO, 0x00000000 + 1843 .set CYVAL__DIRECT_SEL_EXTCLK, 0x00000001 + 1844 .set CYVAL__DIRECT_SEL_ECO, 0x00000002 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 34 + + + 1845 .set CYVAL__DIRECT_SEL_DSI0, 0x00000004 + 1846 .set CYVAL__DIRECT_SEL_DSI1, 0x00000005 + 1847 .set CYVAL__DIRECT_SEL_DSI2, 0x00000006 + 1848 .set CYVAL__DIRECT_SEL_DSI3, 0x00000007 + 1849 .set CYFLD__DBL_SEL__OFFSET, 0x00000003 + 1850 .set CYFLD__DBL_SEL__SIZE, 0x00000003 + 1851 .set CYVAL__DBL_SEL_IMO, 0x00000000 + 1852 .set CYVAL__DBL_SEL_EXTCLK, 0x00000001 + 1853 .set CYVAL__DBL_SEL_ECO, 0x00000002 + 1854 .set CYVAL__DBL_SEL_DSI0, 0x00000004 + 1855 .set CYVAL__DBL_SEL_DSI1, 0x00000005 + 1856 .set CYVAL__DBL_SEL_DSI2, 0x00000006 + 1857 .set CYVAL__DBL_SEL_DSI3, 0x00000007 + 1858 .set CYFLD__PLL_SEL__OFFSET, 0x00000006 + 1859 .set CYFLD__PLL_SEL__SIZE, 0x00000003 + 1860 .set CYVAL__PLL_SEL_IMO, 0x00000000 + 1861 .set CYVAL__PLL_SEL_EXTCLK, 0x00000001 + 1862 .set CYVAL__PLL_SEL_ECO, 0x00000002 + 1863 .set CYVAL__PLL_SEL_DPLL, 0x00000003 + 1864 .set CYVAL__PLL_SEL_DSI0, 0x00000004 + 1865 .set CYVAL__PLL_SEL_DSI1, 0x00000005 + 1866 .set CYVAL__PLL_SEL_DSI2, 0x00000006 + 1867 .set CYVAL__PLL_SEL_DSI3, 0x00000007 + 1868 .set CYFLD__DPLLIN_SEL__OFFSET, 0x00000009 + 1869 .set CYFLD__DPLLIN_SEL__SIZE, 0x00000003 + 1870 .set CYVAL__DPLLIN_SEL_IMO, 0x00000000 + 1871 .set CYVAL__DPLLIN_SEL_EXTCLK, 0x00000001 + 1872 .set CYVAL__DPLLIN_SEL_ECO, 0x00000002 + 1873 .set CYVAL__DPLLIN_SEL_DSI0, 0x00000004 + 1874 .set CYVAL__DPLLIN_SEL_DSI1, 0x00000005 + 1875 .set CYVAL__DPLLIN_SEL_DSI2, 0x00000006 + 1876 .set CYVAL__DPLLIN_SEL_DSI3, 0x00000007 + 1877 .set CYFLD__DPLLREF_SEL__OFFSET, 0x0000000c + 1878 .set CYFLD__DPLLREF_SEL__SIZE, 0x00000002 + 1879 .set CYVAL__DPLLREF_SEL_DSI0, 0x00000000 + 1880 .set CYVAL__DPLLREF_SEL_DSI1, 0x00000001 + 1881 .set CYVAL__DPLLREF_SEL_DSI2, 0x00000002 + 1882 .set CYVAL__DPLLREF_SEL_DSI3, 0x00000003 + 1883 .set CYFLD__WDT_LOCK__OFFSET, 0x0000000e + 1884 .set CYFLD__WDT_LOCK__SIZE, 0x00000002 + 1885 .set CYVAL__WDT_LOCK_NO_CHG, 0x00000000 + 1886 .set CYVAL__WDT_LOCK_CLR0, 0x00000001 + 1887 .set CYVAL__WDT_LOCK_CLR1, 0x00000002 + 1888 .set CYVAL__WDT_LOCK_SET01, 0x00000003 + 1889 .set CYFLD__HFCLK_SEL__OFFSET, 0x00000010 + 1890 .set CYFLD__HFCLK_SEL__SIZE, 0x00000002 + 1891 .set CYVAL__HFCLK_SEL_DIRECT_SEL, 0x00000000 + 1892 .set CYVAL__HFCLK_SEL_DBL, 0x00000001 + 1893 .set CYVAL__HFCLK_SEL_PLL, 0x00000002 + 1894 .set CYFLD__HALF_EN__OFFSET, 0x00000012 + 1895 .set CYFLD__HALF_EN__SIZE, 0x00000001 + 1896 .set CYFLD__SYSCLK_DIV__OFFSET, 0x00000013 + 1897 .set CYFLD__SYSCLK_DIV__SIZE, 0x00000003 + 1898 .set CYVAL__SYSCLK_DIV_NO_DIV, 0x00000000 + 1899 .set CYVAL__SYSCLK_DIV_DIV_BY_2, 0x00000001 + 1900 .set CYVAL__SYSCLK_DIV_DIV_BY_4, 0x00000002 + 1901 .set CYVAL__SYSCLK_DIV_DIV_BY_8, 0x00000003 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 35 + + + 1902 .set CYVAL__SYSCLK_DIV_DIV_BY_16, 0x00000004 + 1903 .set CYVAL__SYSCLK_DIV_DIV_BY_32, 0x00000005 + 1904 .set CYVAL__SYSCLK_DIV_DIV_BY_64, 0x00000006 + 1905 .set CYVAL__SYSCLK_DIV_DIV_BY_128, 0x00000007 + 1906 .set CYREG_CLK_ILO_CONFIG, 0x400b0104 + 1907 .set CYFLD__PD_MODE__OFFSET, 0x00000000 + 1908 .set CYFLD__PD_MODE__SIZE, 0x00000001 + 1909 .set CYVAL__PD_MODE_SLEEP, 0x00000000 + 1910 .set CYVAL__PD_MODE_COMA, 0x00000001 + 1911 .set CYFLD__TURBO__OFFSET, 0x00000001 + 1912 .set CYFLD__TURBO__SIZE, 0x00000001 + 1913 .set CYFLD__SATBIAS__OFFSET, 0x00000002 + 1914 .set CYFLD__SATBIAS__SIZE, 0x00000001 + 1915 .set CYVAL__SATBIAS_SATURATED, 0x00000000 + 1916 .set CYVAL__SATBIAS_SUBTHRESHOLD, 0x00000001 + 1917 .set CYFLD__ENABLE__OFFSET, 0x0000001f + 1918 .set CYFLD__ENABLE__SIZE, 0x00000001 + 1919 .set CYREG_CLK_IMO_CONFIG, 0x400b0108 + 1920 .set CYFLD__FLASHPUMP_SEL__OFFSET, 0x00000016 + 1921 .set CYFLD__FLASHPUMP_SEL__SIZE, 0x00000001 + 1922 .set CYVAL__FLASHPUMP_SEL_GND, 0x00000000 + 1923 .set CYVAL__FLASHPUMP_SEL_CLK36, 0x00000001 + 1924 .set CYFLD__EN_FASTBIAS__OFFSET, 0x00000017 + 1925 .set CYFLD__EN_FASTBIAS__SIZE, 0x00000001 + 1926 .set CYFLD__TEST_FASTBIAS__OFFSET, 0x00000018 + 1927 .set CYFLD__TEST_FASTBIAS__SIZE, 0x00000001 + 1928 .set CYFLD__PUMP_SEL__OFFSET, 0x00000019 + 1929 .set CYFLD__PUMP_SEL__SIZE, 0x00000003 + 1930 .set CYVAL__PUMP_SEL_GND, 0x00000000 + 1931 .set CYVAL__PUMP_SEL_IMO, 0x00000001 + 1932 .set CYVAL__PUMP_SEL_DBL, 0x00000002 + 1933 .set CYVAL__PUMP_SEL_CLK36, 0x00000003 + 1934 .set CYVAL__PUMP_SEL_FF1, 0x00000004 + 1935 .set CYFLD__TEST_USB_MODE__OFFSET, 0x0000001c + 1936 .set CYFLD__TEST_USB_MODE__SIZE, 0x00000001 + 1937 .set CYFLD__EN_CLK36__OFFSET, 0x0000001d + 1938 .set CYFLD__EN_CLK36__SIZE, 0x00000001 + 1939 .set CYFLD__EN_CLK2X__OFFSET, 0x0000001e + 1940 .set CYFLD__EN_CLK2X__SIZE, 0x00000001 + 1941 .set CYREG_CLK_IMO_SPREAD, 0x400b010c + 1942 .set CYFLD__SS_VALUE__OFFSET, 0x00000000 + 1943 .set CYFLD__SS_VALUE__SIZE, 0x00000005 + 1944 .set CYFLD__SS_MAX__OFFSET, 0x00000008 + 1945 .set CYFLD__SS_MAX__SIZE, 0x00000005 + 1946 .set CYFLD__SS_RANGE__OFFSET, 0x0000001c + 1947 .set CYFLD__SS_RANGE__SIZE, 0x00000002 + 1948 .set CYVAL__SS_RANGE_M1, 0x00000000 + 1949 .set CYVAL__SS_RANGE_M2, 0x00000001 + 1950 .set CYVAL__SS_RANGE_M4, 0x00000002 + 1951 .set CYFLD__SS_MODE__OFFSET, 0x0000001e + 1952 .set CYFLD__SS_MODE__SIZE, 0x00000002 + 1953 .set CYVAL__SS_MODE_OFF, 0x00000000 + 1954 .set CYVAL__SS_MODE_TRIANGLE, 0x00000001 + 1955 .set CYVAL__SS_MODE_LFSR, 0x00000002 + 1956 .set CYVAL__SS_MODE_DSI, 0x00000003 + 1957 .set CYREG_CLK_DFT_SELECT, 0x400b0110 + 1958 .set CYFLD__DFT_SEL1__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 36 + + + 1959 .set CYFLD__DFT_SEL1__SIZE, 0x00000004 + 1960 .set CYVAL__DFT_SEL1_NC, 0x00000000 + 1961 .set CYVAL__DFT_SEL1_ILO, 0x00000001 + 1962 .set CYVAL__DFT_SEL1_WCO, 0x00000002 + 1963 .set CYVAL__DFT_SEL1_IMO, 0x00000003 + 1964 .set CYVAL__DFT_SEL1_ECO, 0x00000004 + 1965 .set CYVAL__DFT_SEL1_PLL, 0x00000005 + 1966 .set CYVAL__DFT_SEL1_DPLL_OUT, 0x00000006 + 1967 .set CYVAL__DFT_SEL1_DPLL_REF, 0x00000007 + 1968 .set CYVAL__DFT_SEL1_DBL, 0x00000008 + 1969 .set CYVAL__DFT_SEL1_IMO2X, 0x00000009 + 1970 .set CYVAL__DFT_SEL1_IMO36, 0x0000000a + 1971 .set CYVAL__DFT_SEL1_HFCLK, 0x0000000b + 1972 .set CYVAL__DFT_SEL1_LFCLK, 0x0000000c + 1973 .set CYVAL__DFT_SEL1_SYSCLK, 0x0000000d + 1974 .set CYVAL__DFT_SEL1_EXTCLK, 0x0000000e + 1975 .set CYVAL__DFT_SEL1_HALFSYSCLK, 0x0000000f + 1976 .set CYFLD__DFT_DIV1__OFFSET, 0x00000004 + 1977 .set CYFLD__DFT_DIV1__SIZE, 0x00000002 + 1978 .set CYVAL__DFT_DIV1_NO_DIV, 0x00000000 + 1979 .set CYVAL__DFT_DIV1_DIV_BY_2, 0x00000001 + 1980 .set CYVAL__DFT_DIV1_DIV_BY_4, 0x00000002 + 1981 .set CYVAL__DFT_DIV1_DIV_BY_8, 0x00000003 + 1982 .set CYFLD__DFT_SEL2__OFFSET, 0x00000008 + 1983 .set CYFLD__DFT_SEL2__SIZE, 0x00000004 + 1984 .set CYVAL__DFT_SEL2_NC, 0x00000000 + 1985 .set CYVAL__DFT_SEL2_ILO, 0x00000001 + 1986 .set CYVAL__DFT_SEL2_WCO, 0x00000002 + 1987 .set CYVAL__DFT_SEL2_IMO, 0x00000003 + 1988 .set CYVAL__DFT_SEL2_ECO, 0x00000004 + 1989 .set CYVAL__DFT_SEL2_PLL, 0x00000005 + 1990 .set CYVAL__DFT_SEL2_DPLL_OUT, 0x00000006 + 1991 .set CYVAL__DFT_SEL2_DPLL_REF, 0x00000007 + 1992 .set CYVAL__DFT_SEL2_DBL, 0x00000008 + 1993 .set CYVAL__DFT_SEL2_IMO2X, 0x00000009 + 1994 .set CYVAL__DFT_SEL2_IMO36, 0x0000000a + 1995 .set CYVAL__DFT_SEL2_HFCLK, 0x0000000b + 1996 .set CYVAL__DFT_SEL2_LFCLK, 0x0000000c + 1997 .set CYVAL__DFT_SEL2_SYSCLK, 0x0000000d + 1998 .set CYVAL__DFT_SEL2_EXTCLK, 0x0000000e + 1999 .set CYVAL__DFT_SEL2_HALFSYSCLK, 0x0000000f + 2000 .set CYFLD__DFT_DIV2__OFFSET, 0x0000000c + 2001 .set CYFLD__DFT_DIV2__SIZE, 0x00000002 + 2002 .set CYVAL__DFT_DIV2_NO_DIV, 0x00000000 + 2003 .set CYVAL__DFT_DIV2_DIV_BY_2, 0x00000001 + 2004 .set CYVAL__DFT_DIV2_DIV_BY_4, 0x00000002 + 2005 .set CYVAL__DFT_DIV2_DIV_BY_8, 0x00000003 + 2006 .set CYREG_WDT_CTRLOW, 0x400b0200 + 2007 .set CYFLD__WDT_CTR0__OFFSET, 0x00000000 + 2008 .set CYFLD__WDT_CTR0__SIZE, 0x00000010 + 2009 .set CYFLD__WDT_CTR1__OFFSET, 0x00000010 + 2010 .set CYFLD__WDT_CTR1__SIZE, 0x00000010 + 2011 .set CYREG_WDT_CTRHIGH, 0x400b0204 + 2012 .set CYFLD__WDT_CTR2__OFFSET, 0x00000000 + 2013 .set CYFLD__WDT_CTR2__SIZE, 0x00000020 + 2014 .set CYREG_WDT_MATCH, 0x400b0208 + 2015 .set CYFLD__WDT_MATCH0__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 37 + + + 2016 .set CYFLD__WDT_MATCH0__SIZE, 0x00000010 + 2017 .set CYFLD__WDT_MATCH1__OFFSET, 0x00000010 + 2018 .set CYFLD__WDT_MATCH1__SIZE, 0x00000010 + 2019 .set CYREG_WDT_CONFIG, 0x400b020c + 2020 .set CYFLD__WDT_MODE0__OFFSET, 0x00000000 + 2021 .set CYFLD__WDT_MODE0__SIZE, 0x00000002 + 2022 .set CYVAL__WDT_MODE0_NOTHING, 0x00000000 + 2023 .set CYVAL__WDT_MODE0_INT, 0x00000001 + 2024 .set CYVAL__WDT_MODE0_RESET, 0x00000002 + 2025 .set CYVAL__WDT_MODE0_INT_THEN_RESET, 0x00000003 + 2026 .set CYFLD__WDT_CLEAR0__OFFSET, 0x00000002 + 2027 .set CYFLD__WDT_CLEAR0__SIZE, 0x00000001 + 2028 .set CYFLD__WDT_CASCADE0_1__OFFSET, 0x00000003 + 2029 .set CYFLD__WDT_CASCADE0_1__SIZE, 0x00000001 + 2030 .set CYFLD__WDT_MODE1__OFFSET, 0x00000008 + 2031 .set CYFLD__WDT_MODE1__SIZE, 0x00000002 + 2032 .set CYVAL__WDT_MODE1_NOTHING, 0x00000000 + 2033 .set CYVAL__WDT_MODE1_INT, 0x00000001 + 2034 .set CYVAL__WDT_MODE1_RESET, 0x00000002 + 2035 .set CYVAL__WDT_MODE1_INT_THEN_RESET, 0x00000003 + 2036 .set CYFLD__WDT_CLEAR1__OFFSET, 0x0000000a + 2037 .set CYFLD__WDT_CLEAR1__SIZE, 0x00000001 + 2038 .set CYFLD__WDT_CASCADE1_2__OFFSET, 0x0000000b + 2039 .set CYFLD__WDT_CASCADE1_2__SIZE, 0x00000001 + 2040 .set CYFLD__WDT_MODE2__OFFSET, 0x00000010 + 2041 .set CYFLD__WDT_MODE2__SIZE, 0x00000001 + 2042 .set CYVAL__WDT_MODE2_NOTHING, 0x00000000 + 2043 .set CYVAL__WDT_MODE2_INT, 0x00000001 + 2044 .set CYFLD__WDT_BITS2__OFFSET, 0x00000018 + 2045 .set CYFLD__WDT_BITS2__SIZE, 0x00000005 + 2046 .set CYFLD__LFCLK_SEL__OFFSET, 0x0000001e + 2047 .set CYFLD__LFCLK_SEL__SIZE, 0x00000002 + 2048 .set CYREG_WDT_CONTROL, 0x400b0210 + 2049 .set CYFLD__WDT_ENABLE0__OFFSET, 0x00000000 + 2050 .set CYFLD__WDT_ENABLE0__SIZE, 0x00000001 + 2051 .set CYFLD__WDT_ENABLED0__OFFSET, 0x00000001 + 2052 .set CYFLD__WDT_ENABLED0__SIZE, 0x00000001 + 2053 .set CYFLD__WDT_INT0__OFFSET, 0x00000002 + 2054 .set CYFLD__WDT_INT0__SIZE, 0x00000001 + 2055 .set CYFLD__WDT_RESET0__OFFSET, 0x00000003 + 2056 .set CYFLD__WDT_RESET0__SIZE, 0x00000001 + 2057 .set CYFLD__WDT_ENABLE1__OFFSET, 0x00000008 + 2058 .set CYFLD__WDT_ENABLE1__SIZE, 0x00000001 + 2059 .set CYFLD__WDT_ENABLED1__OFFSET, 0x00000009 + 2060 .set CYFLD__WDT_ENABLED1__SIZE, 0x00000001 + 2061 .set CYFLD__WDT_INT1__OFFSET, 0x0000000a + 2062 .set CYFLD__WDT_INT1__SIZE, 0x00000001 + 2063 .set CYFLD__WDT_RESET1__OFFSET, 0x0000000b + 2064 .set CYFLD__WDT_RESET1__SIZE, 0x00000001 + 2065 .set CYFLD__WDT_ENABLE2__OFFSET, 0x00000010 + 2066 .set CYFLD__WDT_ENABLE2__SIZE, 0x00000001 + 2067 .set CYFLD__WDT_ENABLED2__OFFSET, 0x00000011 + 2068 .set CYFLD__WDT_ENABLED2__SIZE, 0x00000001 + 2069 .set CYFLD__WDT_INT2__OFFSET, 0x00000012 + 2070 .set CYFLD__WDT_INT2__SIZE, 0x00000001 + 2071 .set CYFLD__WDT_RESET2__OFFSET, 0x00000013 + 2072 .set CYFLD__WDT_RESET2__SIZE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 38 + + + 2073 .set CYREG_RES_CAUSE, 0x400b0300 + 2074 .set CYFLD__RESET_WDT__OFFSET, 0x00000000 + 2075 .set CYFLD__RESET_WDT__SIZE, 0x00000001 + 2076 .set CYFLD__RESET_DSBOD__OFFSET, 0x00000001 + 2077 .set CYFLD__RESET_DSBOD__SIZE, 0x00000001 + 2078 .set CYFLD__RESET_LOCKUP__OFFSET, 0x00000002 + 2079 .set CYFLD__RESET_LOCKUP__SIZE, 0x00000001 + 2080 .set CYFLD__RESET_PROT_FAULT__OFFSET, 0x00000003 + 2081 .set CYFLD__RESET_PROT_FAULT__SIZE, 0x00000001 + 2082 .set CYFLD__RESET_SOFT__OFFSET, 0x00000004 + 2083 .set CYFLD__RESET_SOFT__SIZE, 0x00000001 + 2084 .set CYFLD__RESET_HVBOD__OFFSET, 0x00000005 + 2085 .set CYFLD__RESET_HVBOD__SIZE, 0x00000001 + 2086 .set CYFLD__RESET_PBOD__OFFSET, 0x00000006 + 2087 .set CYFLD__RESET_PBOD__SIZE, 0x00000001 + 2088 .set CYFLD__RESET_XRES__OFFSET, 0x00000007 + 2089 .set CYFLD__RESET_XRES__SIZE, 0x00000001 + 2090 .set CYREG_PWR_PWRSYS_TRIM1, 0x400bff00 + 2091 .set CYFLD__HIB_BIAS_TRIM__OFFSET, 0x00000000 + 2092 .set CYFLD__HIB_BIAS_TRIM__SIZE, 0x00000003 + 2093 .set CYFLD__BOD_TURBO_THRESH__OFFSET, 0x00000003 + 2094 .set CYFLD__BOD_TURBO_THRESH__SIZE, 0x00000001 + 2095 .set CYFLD__BOD_TRIM_TRIP__OFFSET, 0x00000004 + 2096 .set CYFLD__BOD_TRIM_TRIP__SIZE, 0x00000004 + 2097 .set CYREG_PWR_PWRSYS_TRIM2, 0x400bff04 + 2098 .set CYFLD__LFCLK_TRIM_LOAD__OFFSET, 0x00000000 + 2099 .set CYFLD__LFCLK_TRIM_LOAD__SIZE, 0x00000002 + 2100 .set CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET, 0x00000002 + 2101 .set CYFLD__LFCLK_TRIM_VOLTAGE__SIZE, 0x00000002 + 2102 .set CYFLD__DPSLP_TRIM_LOAD__OFFSET, 0x00000004 + 2103 .set CYFLD__DPSLP_TRIM_LOAD__SIZE, 0x00000002 + 2104 .set CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET, 0x00000006 + 2105 .set CYFLD__DPSLP_TRIM_LEAKAGE__SIZE, 0x00000001 + 2106 .set CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET, 0x00000007 + 2107 .set CYFLD__DPSLP_TRIM_VOLTAGE__SIZE, 0x00000001 + 2108 .set CYREG_PWR_PWRSYS_TRIM3, 0x400bff08 + 2109 .set CYFLD__NWELL_TRIM__OFFSET, 0x00000000 + 2110 .set CYFLD__NWELL_TRIM__SIZE, 0x00000003 + 2111 .set CYFLD__QUIET_TRIM__OFFSET, 0x00000003 + 2112 .set CYFLD__QUIET_TRIM__SIZE, 0x00000005 + 2113 .set CYREG_PWR_PWRSYS_TRIM4, 0x400bff0c + 2114 .set CYFLD__HIB_TRIM_NWELL__OFFSET, 0x00000000 + 2115 .set CYFLD__HIB_TRIM_NWELL__SIZE, 0x00000002 + 2116 .set CYFLD__HIB_TRIM_LEAKAGE__OFFSET, 0x00000002 + 2117 .set CYFLD__HIB_TRIM_LEAKAGE__SIZE, 0x00000001 + 2118 .set CYFLD__HIB_TRIM_VOLTAGE__OFFSET, 0x00000003 + 2119 .set CYFLD__HIB_TRIM_VOLTAGE__SIZE, 0x00000001 + 2120 .set CYFLD__HIB_TRIM_REFERENCE__OFFSET, 0x00000004 + 2121 .set CYFLD__HIB_TRIM_REFERENCE__SIZE, 0x00000002 + 2122 .set CYREG_PWR_BG_TRIM1, 0x400bff10 + 2123 .set CYFLD__INL_TRIM_MAIN__OFFSET, 0x00000000 + 2124 .set CYFLD__INL_TRIM_MAIN__SIZE, 0x00000003 + 2125 .set CYFLD__INL_CROSS_MAIN__OFFSET, 0x00000003 + 2126 .set CYFLD__INL_CROSS_MAIN__SIZE, 0x00000004 + 2127 .set CYREG_PWR_BG_TRIM2, 0x400bff14 + 2128 .set CYFLD__VCTAT_SLOPE__OFFSET, 0x00000000 + 2129 .set CYFLD__VCTAT_SLOPE__SIZE, 0x00000004 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 39 + + + 2130 .set CYFLD__VCTAT_VOLTAGE__OFFSET, 0x00000004 + 2131 .set CYFLD__VCTAT_VOLTAGE__SIZE, 0x00000002 + 2132 .set CYFLD__VCTAT_ENABLE__OFFSET, 0x00000006 + 2133 .set CYFLD__VCTAT_ENABLE__SIZE, 0x00000001 + 2134 .set CYFLD__VCTAT_VOLTAGE_MSB__OFFSET, 0x00000007 + 2135 .set CYFLD__VCTAT_VOLTAGE_MSB__SIZE, 0x00000001 + 2136 .set CYREG_PWR_BG_TRIM3, 0x400bff18 + 2137 .set CYFLD__INL_TRIM_IMO__OFFSET, 0x00000000 + 2138 .set CYFLD__INL_TRIM_IMO__SIZE, 0x00000003 + 2139 .set CYFLD__INL_CROSS_IMO__OFFSET, 0x00000003 + 2140 .set CYFLD__INL_CROSS_IMO__SIZE, 0x00000004 + 2141 .set CYREG_PWR_BG_TRIM4, 0x400bff1c + 2142 .set CYFLD__ABS_TRIM_IMO__OFFSET, 0x00000000 + 2143 .set CYFLD__ABS_TRIM_IMO__SIZE, 0x00000006 + 2144 .set CYREG_PWR_BG_TRIM5, 0x400bff20 + 2145 .set CYFLD__TMPCO_TRIM_IMO__OFFSET, 0x00000000 + 2146 .set CYFLD__TMPCO_TRIM_IMO__SIZE, 0x00000006 + 2147 .set CYREG_CLK_ILO_TRIM, 0x400bff24 + 2148 .set CYFLD__TRIM__OFFSET, 0x00000000 + 2149 .set CYFLD__TRIM__SIZE, 0x00000004 + 2150 .set CYFLD__COARSE_TRIM__OFFSET, 0x00000004 + 2151 .set CYFLD__COARSE_TRIM__SIZE, 0x00000004 + 2152 .set CYREG_CLK_IMO_TRIM1, 0x400bff28 + 2153 .set CYFLD__OFFSET__OFFSET, 0x00000000 + 2154 .set CYFLD__OFFSET__SIZE, 0x00000008 + 2155 .set CYREG_CLK_IMO_TRIM2, 0x400bff2c + 2156 .set CYFLD__FREQ__OFFSET, 0x00000000 + 2157 .set CYFLD__FREQ__SIZE, 0x00000006 + 2158 .set CYREG_CLK_IMO_TRIM3, 0x400bff30 + 2159 .set CYFLD__TRIM_CLK36__OFFSET, 0x00000000 + 2160 .set CYFLD__TRIM_CLK36__SIZE, 0x00000004 + 2161 .set CYREG_CLK_IMO_TRIM4, 0x400bff34 + 2162 .set CYFLD__GAIN__OFFSET, 0x00000000 + 2163 .set CYFLD__GAIN__SIZE, 0x00000005 + 2164 .set CYFLD__FSOFFSET__OFFSET, 0x00000005 + 2165 .set CYFLD__FSOFFSET__SIZE, 0x00000003 + 2166 .set CYREG_PWR_RSVD_TRIM, 0x400bff38 + 2167 .set CYFLD__RSVD_TRIM__OFFSET, 0x00000000 + 2168 .set CYFLD__RSVD_TRIM__SIZE, 0x00000004 + 2169 .set CYDEV_SPCIF_BASE, 0x400e0000 + 2170 .set CYDEV_SPCIF_SIZE, 0x00010000 + 2171 .set CYREG_SPCIF_GEOMETRY, 0x400e0000 + 2172 .set CYFLD_SPCIF_FLASH__OFFSET, 0x00000000 + 2173 .set CYFLD_SPCIF_FLASH__SIZE, 0x00000010 + 2174 .set CYFLD_SPCIF_SFLASH__OFFSET, 0x00000010 + 2175 .set CYFLD_SPCIF_SFLASH__SIZE, 0x00000004 + 2176 .set CYFLD_SPCIF_NUM_FLASH__OFFSET, 0x00000014 + 2177 .set CYFLD_SPCIF_NUM_FLASH__SIZE, 0x00000002 + 2178 .set CYFLD_SPCIF_FLASH_ROW__OFFSET, 0x00000016 + 2179 .set CYFLD_SPCIF_FLASH_ROW__SIZE, 0x00000002 + 2180 .set CYFLD_SPCIF_NVL__OFFSET, 0x00000018 + 2181 .set CYFLD_SPCIF_NVL__SIZE, 0x00000007 + 2182 .set CYFLD_SPCIF_DE_CPD_LP__OFFSET, 0x0000001f + 2183 .set CYFLD_SPCIF_DE_CPD_LP__SIZE, 0x00000001 + 2184 .set CYREG_SPCIF_NVL_WR_DATA, 0x400e001c + 2185 .set CYFLD_SPCIF_DATA__OFFSET, 0x00000000 + 2186 .set CYFLD_SPCIF_DATA__SIZE, 0x00000008 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 40 + + + 2187 .set CYDEV_UDB_BASE, 0x400f0000 + 2188 .set CYDEV_UDB_SIZE, 0x00010000 + 2189 .set CYDEV_UDB_W8_BASE, 0x400f0000 + 2190 .set CYDEV_UDB_W8_SIZE, 0x00001000 + 2191 .set CYREG_UDB_W8_A0_00, 0x400f0000 + 2192 .set CYFLD_UDB_W8_A0__OFFSET, 0x00000000 + 2193 .set CYFLD_UDB_W8_A0__SIZE, 0x00000008 + 2194 .set CYREG_UDB_W8_A0_01, 0x400f0001 + 2195 .set CYREG_UDB_W8_A0_02, 0x400f0002 + 2196 .set CYREG_UDB_W8_A0_03, 0x400f0003 + 2197 .set CYREG_UDB_W8_A1_00, 0x400f0010 + 2198 .set CYFLD_UDB_W8_A1__OFFSET, 0x00000000 + 2199 .set CYFLD_UDB_W8_A1__SIZE, 0x00000008 + 2200 .set CYREG_UDB_W8_A1_01, 0x400f0011 + 2201 .set CYREG_UDB_W8_A1_02, 0x400f0012 + 2202 .set CYREG_UDB_W8_A1_03, 0x400f0013 + 2203 .set CYREG_UDB_W8_D0_00, 0x400f0020 + 2204 .set CYFLD_UDB_W8_D0__OFFSET, 0x00000000 + 2205 .set CYFLD_UDB_W8_D0__SIZE, 0x00000008 + 2206 .set CYREG_UDB_W8_D0_01, 0x400f0021 + 2207 .set CYREG_UDB_W8_D0_02, 0x400f0022 + 2208 .set CYREG_UDB_W8_D0_03, 0x400f0023 + 2209 .set CYREG_UDB_W8_D1_00, 0x400f0030 + 2210 .set CYFLD_UDB_W8_D1__OFFSET, 0x00000000 + 2211 .set CYFLD_UDB_W8_D1__SIZE, 0x00000008 + 2212 .set CYREG_UDB_W8_D1_01, 0x400f0031 + 2213 .set CYREG_UDB_W8_D1_02, 0x400f0032 + 2214 .set CYREG_UDB_W8_D1_03, 0x400f0033 + 2215 .set CYREG_UDB_W8_F0_00, 0x400f0040 + 2216 .set CYFLD_UDB_W8_F0__OFFSET, 0x00000000 + 2217 .set CYFLD_UDB_W8_F0__SIZE, 0x00000008 + 2218 .set CYREG_UDB_W8_F0_01, 0x400f0041 + 2219 .set CYREG_UDB_W8_F0_02, 0x400f0042 + 2220 .set CYREG_UDB_W8_F0_03, 0x400f0043 + 2221 .set CYREG_UDB_W8_F1_00, 0x400f0050 + 2222 .set CYFLD_UDB_W8_F1__OFFSET, 0x00000000 + 2223 .set CYFLD_UDB_W8_F1__SIZE, 0x00000008 + 2224 .set CYREG_UDB_W8_F1_01, 0x400f0051 + 2225 .set CYREG_UDB_W8_F1_02, 0x400f0052 + 2226 .set CYREG_UDB_W8_F1_03, 0x400f0053 + 2227 .set CYREG_UDB_W8_ST_00, 0x400f0060 + 2228 .set CYFLD_UDB_W8_ST__OFFSET, 0x00000000 + 2229 .set CYFLD_UDB_W8_ST__SIZE, 0x00000008 + 2230 .set CYREG_UDB_W8_ST_01, 0x400f0061 + 2231 .set CYREG_UDB_W8_ST_02, 0x400f0062 + 2232 .set CYREG_UDB_W8_ST_03, 0x400f0063 + 2233 .set CYREG_UDB_W8_CTL_00, 0x400f0070 + 2234 .set CYFLD_UDB_W8_CTL__OFFSET, 0x00000000 + 2235 .set CYFLD_UDB_W8_CTL__SIZE, 0x00000008 + 2236 .set CYREG_UDB_W8_CTL_01, 0x400f0071 + 2237 .set CYREG_UDB_W8_CTL_02, 0x400f0072 + 2238 .set CYREG_UDB_W8_CTL_03, 0x400f0073 + 2239 .set CYREG_UDB_W8_MSK_00, 0x400f0080 + 2240 .set CYFLD_UDB_W8_MSK__OFFSET, 0x00000000 + 2241 .set CYFLD_UDB_W8_MSK__SIZE, 0x00000007 + 2242 .set CYREG_UDB_W8_MSK_01, 0x400f0081 + 2243 .set CYREG_UDB_W8_MSK_02, 0x400f0082 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 41 + + + 2244 .set CYREG_UDB_W8_MSK_03, 0x400f0083 + 2245 .set CYREG_UDB_W8_ACTL_00, 0x400f0090 + 2246 .set CYFLD_UDB_W8_FIFO0_CLR__OFFSET, 0x00000000 + 2247 .set CYFLD_UDB_W8_FIFO0_CLR__SIZE, 0x00000001 + 2248 .set CYVAL_UDB_W8_FIFO0_CLR_NORMAL, 0x00000000 + 2249 .set CYVAL_UDB_W8_FIFO0_CLR_CLEAR, 0x00000001 + 2250 .set CYFLD_UDB_W8_FIFO1_CLR__OFFSET, 0x00000001 + 2251 .set CYFLD_UDB_W8_FIFO1_CLR__SIZE, 0x00000001 + 2252 .set CYVAL_UDB_W8_FIFO1_CLR_NORMAL, 0x00000000 + 2253 .set CYVAL_UDB_W8_FIFO1_CLR_CLEAR, 0x00000001 + 2254 .set CYFLD_UDB_W8_FIFO0_LVL__OFFSET, 0x00000002 + 2255 .set CYFLD_UDB_W8_FIFO0_LVL__SIZE, 0x00000001 + 2256 .set CYVAL_UDB_W8_FIFO0_LVL_NORMAL, 0x00000000 + 2257 .set CYVAL_UDB_W8_FIFO0_LVL_MID, 0x00000001 + 2258 .set CYFLD_UDB_W8_FIFO1_LVL__OFFSET, 0x00000003 + 2259 .set CYFLD_UDB_W8_FIFO1_LVL__SIZE, 0x00000001 + 2260 .set CYVAL_UDB_W8_FIFO1_LVL_NORMAL, 0x00000000 + 2261 .set CYVAL_UDB_W8_FIFO1_LVL_MID, 0x00000001 + 2262 .set CYFLD_UDB_W8_INT_EN__OFFSET, 0x00000004 + 2263 .set CYFLD_UDB_W8_INT_EN__SIZE, 0x00000001 + 2264 .set CYVAL_UDB_W8_INT_EN_DISABLE, 0x00000000 + 2265 .set CYVAL_UDB_W8_INT_EN_ENABLE, 0x00000001 + 2266 .set CYFLD_UDB_W8_CNT_START__OFFSET, 0x00000005 + 2267 .set CYFLD_UDB_W8_CNT_START__SIZE, 0x00000001 + 2268 .set CYVAL_UDB_W8_CNT_START_DISABLE, 0x00000000 + 2269 .set CYVAL_UDB_W8_CNT_START_ENABLE, 0x00000001 + 2270 .set CYREG_UDB_W8_ACTL_01, 0x400f0091 + 2271 .set CYREG_UDB_W8_ACTL_02, 0x400f0092 + 2272 .set CYREG_UDB_W8_ACTL_03, 0x400f0093 + 2273 .set CYREG_UDB_W8_MC_00, 0x400f00a0 + 2274 .set CYFLD_UDB_W8_PLD0_MC__OFFSET, 0x00000000 + 2275 .set CYFLD_UDB_W8_PLD0_MC__SIZE, 0x00000004 + 2276 .set CYFLD_UDB_W8_PLD1_MC__OFFSET, 0x00000004 + 2277 .set CYFLD_UDB_W8_PLD1_MC__SIZE, 0x00000004 + 2278 .set CYREG_UDB_W8_MC_01, 0x400f00a1 + 2279 .set CYREG_UDB_W8_MC_02, 0x400f00a2 + 2280 .set CYREG_UDB_W8_MC_03, 0x400f00a3 + 2281 .set CYDEV_UDB_CAT16_BASE, 0x400f1000 + 2282 .set CYDEV_UDB_CAT16_SIZE, 0x00001000 + 2283 .set CYREG_UDB_CAT16_A_00, 0x400f1000 + 2284 .set CYFLD_UDB_CAT16_A0__OFFSET, 0x00000000 + 2285 .set CYFLD_UDB_CAT16_A0__SIZE, 0x00000008 + 2286 .set CYFLD_UDB_CAT16_A1__OFFSET, 0x00000008 + 2287 .set CYFLD_UDB_CAT16_A1__SIZE, 0x00000008 + 2288 .set CYREG_UDB_CAT16_A_01, 0x400f1002 + 2289 .set CYREG_UDB_CAT16_A_02, 0x400f1004 + 2290 .set CYREG_UDB_CAT16_A_03, 0x400f1006 + 2291 .set CYREG_UDB_CAT16_D_00, 0x400f1040 + 2292 .set CYFLD_UDB_CAT16_D0__OFFSET, 0x00000000 + 2293 .set CYFLD_UDB_CAT16_D0__SIZE, 0x00000008 + 2294 .set CYFLD_UDB_CAT16_D1__OFFSET, 0x00000008 + 2295 .set CYFLD_UDB_CAT16_D1__SIZE, 0x00000008 + 2296 .set CYREG_UDB_CAT16_D_01, 0x400f1042 + 2297 .set CYREG_UDB_CAT16_D_02, 0x400f1044 + 2298 .set CYREG_UDB_CAT16_D_03, 0x400f1046 + 2299 .set CYREG_UDB_CAT16_F_00, 0x400f1080 + 2300 .set CYFLD_UDB_CAT16_F0__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 42 + + + 2301 .set CYFLD_UDB_CAT16_F0__SIZE, 0x00000008 + 2302 .set CYFLD_UDB_CAT16_F1__OFFSET, 0x00000008 + 2303 .set CYFLD_UDB_CAT16_F1__SIZE, 0x00000008 + 2304 .set CYREG_UDB_CAT16_F_01, 0x400f1082 + 2305 .set CYREG_UDB_CAT16_F_02, 0x400f1084 + 2306 .set CYREG_UDB_CAT16_F_03, 0x400f1086 + 2307 .set CYREG_UDB_CAT16_CTL_ST_00, 0x400f10c0 + 2308 .set CYFLD_UDB_CAT16_ST__OFFSET, 0x00000000 + 2309 .set CYFLD_UDB_CAT16_ST__SIZE, 0x00000008 + 2310 .set CYFLD_UDB_CAT16_CTL__OFFSET, 0x00000008 + 2311 .set CYFLD_UDB_CAT16_CTL__SIZE, 0x00000008 + 2312 .set CYREG_UDB_CAT16_CTL_ST_01, 0x400f10c2 + 2313 .set CYREG_UDB_CAT16_CTL_ST_02, 0x400f10c4 + 2314 .set CYREG_UDB_CAT16_CTL_ST_03, 0x400f10c6 + 2315 .set CYREG_UDB_CAT16_ACTL_MSK_00, 0x400f1100 + 2316 .set CYFLD_UDB_CAT16_MSK__OFFSET, 0x00000000 + 2317 .set CYFLD_UDB_CAT16_MSK__SIZE, 0x00000008 + 2318 .set CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET, 0x00000008 + 2319 .set CYFLD_UDB_CAT16_FIFO0_CLR__SIZE, 0x00000001 + 2320 .set CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL, 0x00000000 + 2321 .set CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR, 0x00000001 + 2322 .set CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET, 0x00000009 + 2323 .set CYFLD_UDB_CAT16_FIFO1_CLR__SIZE, 0x00000001 + 2324 .set CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL, 0x00000000 + 2325 .set CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR, 0x00000001 + 2326 .set CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET, 0x0000000a + 2327 .set CYFLD_UDB_CAT16_FIFO0_LVL__SIZE, 0x00000001 + 2328 .set CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL, 0x00000000 + 2329 .set CYVAL_UDB_CAT16_FIFO0_LVL_MID, 0x00000001 + 2330 .set CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET, 0x0000000b + 2331 .set CYFLD_UDB_CAT16_FIFO1_LVL__SIZE, 0x00000001 + 2332 .set CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL, 0x00000000 + 2333 .set CYVAL_UDB_CAT16_FIFO1_LVL_MID, 0x00000001 + 2334 .set CYFLD_UDB_CAT16_INT_EN__OFFSET, 0x0000000c + 2335 .set CYFLD_UDB_CAT16_INT_EN__SIZE, 0x00000001 + 2336 .set CYVAL_UDB_CAT16_INT_EN_DISABLE, 0x00000000 + 2337 .set CYVAL_UDB_CAT16_INT_EN_ENABLE, 0x00000001 + 2338 .set CYFLD_UDB_CAT16_CNT_START__OFFSET, 0x0000000d + 2339 .set CYFLD_UDB_CAT16_CNT_START__SIZE, 0x00000001 + 2340 .set CYVAL_UDB_CAT16_CNT_START_DISABLE, 0x00000000 + 2341 .set CYVAL_UDB_CAT16_CNT_START_ENABLE, 0x00000001 + 2342 .set CYREG_UDB_CAT16_ACTL_MSK_01, 0x400f1102 + 2343 .set CYREG_UDB_CAT16_ACTL_MSK_02, 0x400f1104 + 2344 .set CYREG_UDB_CAT16_ACTL_MSK_03, 0x400f1106 + 2345 .set CYREG_UDB_CAT16_MC_00, 0x400f1140 + 2346 .set CYFLD_UDB_CAT16_PLD0_MC__OFFSET, 0x00000000 + 2347 .set CYFLD_UDB_CAT16_PLD0_MC__SIZE, 0x00000004 + 2348 .set CYFLD_UDB_CAT16_PLD1_MC__OFFSET, 0x00000004 + 2349 .set CYFLD_UDB_CAT16_PLD1_MC__SIZE, 0x00000004 + 2350 .set CYREG_UDB_CAT16_MC_01, 0x400f1142 + 2351 .set CYREG_UDB_CAT16_MC_02, 0x400f1144 + 2352 .set CYREG_UDB_CAT16_MC_03, 0x400f1146 + 2353 .set CYDEV_UDB_W16_BASE, 0x400f1000 + 2354 .set CYDEV_UDB_W16_SIZE, 0x00001000 + 2355 .set CYREG_UDB_W16_A0_00, 0x400f1000 + 2356 .set CYFLD_UDB_W16_A0_LS__OFFSET, 0x00000000 + 2357 .set CYFLD_UDB_W16_A0_LS__SIZE, 0x00000008 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 43 + + + 2358 .set CYFLD_UDB_W16_A0_MS__OFFSET, 0x00000008 + 2359 .set CYFLD_UDB_W16_A0_MS__SIZE, 0x00000008 + 2360 .set CYREG_UDB_W16_A0_01, 0x400f1002 + 2361 .set CYREG_UDB_W16_A0_02, 0x400f1004 + 2362 .set CYREG_UDB_W16_A1_00, 0x400f1020 + 2363 .set CYFLD_UDB_W16_A1_LS__OFFSET, 0x00000000 + 2364 .set CYFLD_UDB_W16_A1_LS__SIZE, 0x00000008 + 2365 .set CYFLD_UDB_W16_A1_MS__OFFSET, 0x00000008 + 2366 .set CYFLD_UDB_W16_A1_MS__SIZE, 0x00000008 + 2367 .set CYREG_UDB_W16_A1_01, 0x400f1022 + 2368 .set CYREG_UDB_W16_A1_02, 0x400f1024 + 2369 .set CYREG_UDB_W16_D0_00, 0x400f1040 + 2370 .set CYFLD_UDB_W16_D0_LS__OFFSET, 0x00000000 + 2371 .set CYFLD_UDB_W16_D0_LS__SIZE, 0x00000008 + 2372 .set CYFLD_UDB_W16_D0_MS__OFFSET, 0x00000008 + 2373 .set CYFLD_UDB_W16_D0_MS__SIZE, 0x00000008 + 2374 .set CYREG_UDB_W16_D0_01, 0x400f1042 + 2375 .set CYREG_UDB_W16_D0_02, 0x400f1044 + 2376 .set CYREG_UDB_W16_D1_00, 0x400f1060 + 2377 .set CYFLD_UDB_W16_D1_LS__OFFSET, 0x00000000 + 2378 .set CYFLD_UDB_W16_D1_LS__SIZE, 0x00000008 + 2379 .set CYFLD_UDB_W16_D1_MS__OFFSET, 0x00000008 + 2380 .set CYFLD_UDB_W16_D1_MS__SIZE, 0x00000008 + 2381 .set CYREG_UDB_W16_D1_01, 0x400f1062 + 2382 .set CYREG_UDB_W16_D1_02, 0x400f1064 + 2383 .set CYREG_UDB_W16_F0_00, 0x400f1080 + 2384 .set CYFLD_UDB_W16_F0_LS__OFFSET, 0x00000000 + 2385 .set CYFLD_UDB_W16_F0_LS__SIZE, 0x00000008 + 2386 .set CYFLD_UDB_W16_F0_MS__OFFSET, 0x00000008 + 2387 .set CYFLD_UDB_W16_F0_MS__SIZE, 0x00000008 + 2388 .set CYREG_UDB_W16_F0_01, 0x400f1082 + 2389 .set CYREG_UDB_W16_F0_02, 0x400f1084 + 2390 .set CYREG_UDB_W16_F1_00, 0x400f10a0 + 2391 .set CYFLD_UDB_W16_F1_LS__OFFSET, 0x00000000 + 2392 .set CYFLD_UDB_W16_F1_LS__SIZE, 0x00000008 + 2393 .set CYFLD_UDB_W16_F1_MS__OFFSET, 0x00000008 + 2394 .set CYFLD_UDB_W16_F1_MS__SIZE, 0x00000008 + 2395 .set CYREG_UDB_W16_F1_01, 0x400f10a2 + 2396 .set CYREG_UDB_W16_F1_02, 0x400f10a4 + 2397 .set CYREG_UDB_W16_ST_00, 0x400f10c0 + 2398 .set CYFLD_UDB_W16_ST_LS__OFFSET, 0x00000000 + 2399 .set CYFLD_UDB_W16_ST_LS__SIZE, 0x00000008 + 2400 .set CYFLD_UDB_W16_ST_MS__OFFSET, 0x00000008 + 2401 .set CYFLD_UDB_W16_ST_MS__SIZE, 0x00000008 + 2402 .set CYREG_UDB_W16_ST_01, 0x400f10c2 + 2403 .set CYREG_UDB_W16_ST_02, 0x400f10c4 + 2404 .set CYREG_UDB_W16_CTL_00, 0x400f10e0 + 2405 .set CYFLD_UDB_W16_CTL_LS__OFFSET, 0x00000000 + 2406 .set CYFLD_UDB_W16_CTL_LS__SIZE, 0x00000008 + 2407 .set CYFLD_UDB_W16_CTL_MS__OFFSET, 0x00000008 + 2408 .set CYFLD_UDB_W16_CTL_MS__SIZE, 0x00000008 + 2409 .set CYREG_UDB_W16_CTL_01, 0x400f10e2 + 2410 .set CYREG_UDB_W16_CTL_02, 0x400f10e4 + 2411 .set CYREG_UDB_W16_MSK_00, 0x400f1100 + 2412 .set CYFLD_UDB_W16_MSK_LS__OFFSET, 0x00000000 + 2413 .set CYFLD_UDB_W16_MSK_LS__SIZE, 0x00000007 + 2414 .set CYFLD_UDB_W16_MSK_MS__OFFSET, 0x00000008 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 44 + + + 2415 .set CYFLD_UDB_W16_MSK_MS__SIZE, 0x00000007 + 2416 .set CYREG_UDB_W16_MSK_01, 0x400f1102 + 2417 .set CYREG_UDB_W16_MSK_02, 0x400f1104 + 2418 .set CYREG_UDB_W16_ACTL_00, 0x400f1120 + 2419 .set CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET, 0x00000000 + 2420 .set CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE, 0x00000001 + 2421 .set CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL, 0x00000000 + 2422 .set CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR, 0x00000001 + 2423 .set CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET, 0x00000001 + 2424 .set CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE, 0x00000001 + 2425 .set CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL, 0x00000000 + 2426 .set CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR, 0x00000001 + 2427 .set CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET, 0x00000002 + 2428 .set CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE, 0x00000001 + 2429 .set CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL, 0x00000000 + 2430 .set CYVAL_UDB_W16_FIFO0_LVL_LS_MID, 0x00000001 + 2431 .set CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET, 0x00000003 + 2432 .set CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE, 0x00000001 + 2433 .set CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL, 0x00000000 + 2434 .set CYVAL_UDB_W16_FIFO1_LVL_LS_MID, 0x00000001 + 2435 .set CYFLD_UDB_W16_INT_EN_LS__OFFSET, 0x00000004 + 2436 .set CYFLD_UDB_W16_INT_EN_LS__SIZE, 0x00000001 + 2437 .set CYVAL_UDB_W16_INT_EN_LS_DISABLE, 0x00000000 + 2438 .set CYVAL_UDB_W16_INT_EN_LS_ENABLE, 0x00000001 + 2439 .set CYFLD_UDB_W16_CNT_START_LS__OFFSET, 0x00000005 + 2440 .set CYFLD_UDB_W16_CNT_START_LS__SIZE, 0x00000001 + 2441 .set CYVAL_UDB_W16_CNT_START_LS_DISABLE, 0x00000000 + 2442 .set CYVAL_UDB_W16_CNT_START_LS_ENABLE, 0x00000001 + 2443 .set CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET, 0x00000008 + 2444 .set CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE, 0x00000001 + 2445 .set CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL, 0x00000000 + 2446 .set CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR, 0x00000001 + 2447 .set CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET, 0x00000009 + 2448 .set CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE, 0x00000001 + 2449 .set CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL, 0x00000000 + 2450 .set CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR, 0x00000001 + 2451 .set CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET, 0x0000000a + 2452 .set CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE, 0x00000001 + 2453 .set CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL, 0x00000000 + 2454 .set CYVAL_UDB_W16_FIFO0_LVL_MS_MID, 0x00000001 + 2455 .set CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET, 0x0000000b + 2456 .set CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE, 0x00000001 + 2457 .set CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL, 0x00000000 + 2458 .set CYVAL_UDB_W16_FIFO1_LVL_MS_MID, 0x00000001 + 2459 .set CYFLD_UDB_W16_INT_EN_MS__OFFSET, 0x0000000c + 2460 .set CYFLD_UDB_W16_INT_EN_MS__SIZE, 0x00000001 + 2461 .set CYVAL_UDB_W16_INT_EN_MS_DISABLE, 0x00000000 + 2462 .set CYVAL_UDB_W16_INT_EN_MS_ENABLE, 0x00000001 + 2463 .set CYFLD_UDB_W16_CNT_START_MS__OFFSET, 0x0000000d + 2464 .set CYFLD_UDB_W16_CNT_START_MS__SIZE, 0x00000001 + 2465 .set CYVAL_UDB_W16_CNT_START_MS_DISABLE, 0x00000000 + 2466 .set CYVAL_UDB_W16_CNT_START_MS_ENABLE, 0x00000001 + 2467 .set CYREG_UDB_W16_ACTL_01, 0x400f1122 + 2468 .set CYREG_UDB_W16_ACTL_02, 0x400f1124 + 2469 .set CYREG_UDB_W16_MC_00, 0x400f1140 + 2470 .set CYFLD_UDB_W16_PLD0_MC_LS__OFFSET, 0x00000000 + 2471 .set CYFLD_UDB_W16_PLD0_MC_LS__SIZE, 0x00000004 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 45 + + + 2472 .set CYFLD_UDB_W16_PLD1_MC_LS__OFFSET, 0x00000004 + 2473 .set CYFLD_UDB_W16_PLD1_MC_LS__SIZE, 0x00000004 + 2474 .set CYFLD_UDB_W16_PLD0_MC_MS__OFFSET, 0x00000008 + 2475 .set CYFLD_UDB_W16_PLD0_MC_MS__SIZE, 0x00000004 + 2476 .set CYFLD_UDB_W16_PLD1_MC_MS__OFFSET, 0x0000000c + 2477 .set CYFLD_UDB_W16_PLD1_MC_MS__SIZE, 0x00000004 + 2478 .set CYREG_UDB_W16_MC_01, 0x400f1142 + 2479 .set CYREG_UDB_W16_MC_02, 0x400f1144 + 2480 .set CYDEV_UDB_W32_BASE, 0x400f2000 + 2481 .set CYDEV_UDB_W32_SIZE, 0x00001000 + 2482 .set CYREG_UDB_W32_A0_00, 0x400f2000 + 2483 .set CYFLD_UDB_W32_A0_0__OFFSET, 0x00000000 + 2484 .set CYFLD_UDB_W32_A0_0__SIZE, 0x00000008 + 2485 .set CYFLD_UDB_W32_A0_1__OFFSET, 0x00000008 + 2486 .set CYFLD_UDB_W32_A0_1__SIZE, 0x00000008 + 2487 .set CYFLD_UDB_W32_A0_2__OFFSET, 0x00000010 + 2488 .set CYFLD_UDB_W32_A0_2__SIZE, 0x00000008 + 2489 .set CYFLD_UDB_W32_A0_3__OFFSET, 0x00000018 + 2490 .set CYFLD_UDB_W32_A0_3__SIZE, 0x00000008 + 2491 .set CYREG_UDB_W32_A1_00, 0x400f2040 + 2492 .set CYFLD_UDB_W32_A1_0__OFFSET, 0x00000000 + 2493 .set CYFLD_UDB_W32_A1_0__SIZE, 0x00000008 + 2494 .set CYFLD_UDB_W32_A1_1__OFFSET, 0x00000008 + 2495 .set CYFLD_UDB_W32_A1_1__SIZE, 0x00000008 + 2496 .set CYFLD_UDB_W32_A1_2__OFFSET, 0x00000010 + 2497 .set CYFLD_UDB_W32_A1_2__SIZE, 0x00000008 + 2498 .set CYFLD_UDB_W32_A1_3__OFFSET, 0x00000018 + 2499 .set CYFLD_UDB_W32_A1_3__SIZE, 0x00000008 + 2500 .set CYREG_UDB_W32_D0_00, 0x400f2080 + 2501 .set CYFLD_UDB_W32_D0_0__OFFSET, 0x00000000 + 2502 .set CYFLD_UDB_W32_D0_0__SIZE, 0x00000008 + 2503 .set CYFLD_UDB_W32_D0_1__OFFSET, 0x00000008 + 2504 .set CYFLD_UDB_W32_D0_1__SIZE, 0x00000008 + 2505 .set CYFLD_UDB_W32_D0_2__OFFSET, 0x00000010 + 2506 .set CYFLD_UDB_W32_D0_2__SIZE, 0x00000008 + 2507 .set CYFLD_UDB_W32_D0_3__OFFSET, 0x00000018 + 2508 .set CYFLD_UDB_W32_D0_3__SIZE, 0x00000008 + 2509 .set CYREG_UDB_W32_D1_00, 0x400f20c0 + 2510 .set CYFLD_UDB_W32_D1_0__OFFSET, 0x00000000 + 2511 .set CYFLD_UDB_W32_D1_0__SIZE, 0x00000008 + 2512 .set CYFLD_UDB_W32_D1_1__OFFSET, 0x00000008 + 2513 .set CYFLD_UDB_W32_D1_1__SIZE, 0x00000008 + 2514 .set CYFLD_UDB_W32_D1_2__OFFSET, 0x00000010 + 2515 .set CYFLD_UDB_W32_D1_2__SIZE, 0x00000008 + 2516 .set CYFLD_UDB_W32_D1_3__OFFSET, 0x00000018 + 2517 .set CYFLD_UDB_W32_D1_3__SIZE, 0x00000008 + 2518 .set CYREG_UDB_W32_F0_00, 0x400f2100 + 2519 .set CYFLD_UDB_W32_F0_0__OFFSET, 0x00000000 + 2520 .set CYFLD_UDB_W32_F0_0__SIZE, 0x00000008 + 2521 .set CYFLD_UDB_W32_F0_1__OFFSET, 0x00000008 + 2522 .set CYFLD_UDB_W32_F0_1__SIZE, 0x00000008 + 2523 .set CYFLD_UDB_W32_F0_2__OFFSET, 0x00000010 + 2524 .set CYFLD_UDB_W32_F0_2__SIZE, 0x00000008 + 2525 .set CYFLD_UDB_W32_F0_3__OFFSET, 0x00000018 + 2526 .set CYFLD_UDB_W32_F0_3__SIZE, 0x00000008 + 2527 .set CYREG_UDB_W32_F1_00, 0x400f2140 + 2528 .set CYFLD_UDB_W32_F1_0__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 46 + + + 2529 .set CYFLD_UDB_W32_F1_0__SIZE, 0x00000008 + 2530 .set CYFLD_UDB_W32_F1_1__OFFSET, 0x00000008 + 2531 .set CYFLD_UDB_W32_F1_1__SIZE, 0x00000008 + 2532 .set CYFLD_UDB_W32_F1_2__OFFSET, 0x00000010 + 2533 .set CYFLD_UDB_W32_F1_2__SIZE, 0x00000008 + 2534 .set CYFLD_UDB_W32_F1_3__OFFSET, 0x00000018 + 2535 .set CYFLD_UDB_W32_F1_3__SIZE, 0x00000008 + 2536 .set CYREG_UDB_W32_ST_00, 0x400f2180 + 2537 .set CYFLD_UDB_W32_ST_0__OFFSET, 0x00000000 + 2538 .set CYFLD_UDB_W32_ST_0__SIZE, 0x00000008 + 2539 .set CYFLD_UDB_W32_ST_1__OFFSET, 0x00000008 + 2540 .set CYFLD_UDB_W32_ST_1__SIZE, 0x00000008 + 2541 .set CYFLD_UDB_W32_ST_2__OFFSET, 0x00000010 + 2542 .set CYFLD_UDB_W32_ST_2__SIZE, 0x00000008 + 2543 .set CYFLD_UDB_W32_ST_3__OFFSET, 0x00000018 + 2544 .set CYFLD_UDB_W32_ST_3__SIZE, 0x00000008 + 2545 .set CYREG_UDB_W32_CTL_00, 0x400f21c0 + 2546 .set CYFLD_UDB_W32_CTL_0__OFFSET, 0x00000000 + 2547 .set CYFLD_UDB_W32_CTL_0__SIZE, 0x00000008 + 2548 .set CYFLD_UDB_W32_CTL_1__OFFSET, 0x00000008 + 2549 .set CYFLD_UDB_W32_CTL_1__SIZE, 0x00000008 + 2550 .set CYFLD_UDB_W32_CTL_2__OFFSET, 0x00000010 + 2551 .set CYFLD_UDB_W32_CTL_2__SIZE, 0x00000008 + 2552 .set CYFLD_UDB_W32_CTL_3__OFFSET, 0x00000018 + 2553 .set CYFLD_UDB_W32_CTL_3__SIZE, 0x00000008 + 2554 .set CYREG_UDB_W32_MSK_00, 0x400f2200 + 2555 .set CYFLD_UDB_W32_MSK_0__OFFSET, 0x00000000 + 2556 .set CYFLD_UDB_W32_MSK_0__SIZE, 0x00000007 + 2557 .set CYFLD_UDB_W32_MSK_1__OFFSET, 0x00000008 + 2558 .set CYFLD_UDB_W32_MSK_1__SIZE, 0x00000007 + 2559 .set CYFLD_UDB_W32_MSK_2__OFFSET, 0x00000010 + 2560 .set CYFLD_UDB_W32_MSK_2__SIZE, 0x00000007 + 2561 .set CYFLD_UDB_W32_MSK_3__OFFSET, 0x00000018 + 2562 .set CYFLD_UDB_W32_MSK_3__SIZE, 0x00000007 + 2563 .set CYREG_UDB_W32_ACTL_00, 0x400f2240 + 2564 .set CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET, 0x00000000 + 2565 .set CYFLD_UDB_W32_FIFO0_CLR_0__SIZE, 0x00000001 + 2566 .set CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL, 0x00000000 + 2567 .set CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR, 0x00000001 + 2568 .set CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET, 0x00000001 + 2569 .set CYFLD_UDB_W32_FIFO1_CLR_0__SIZE, 0x00000001 + 2570 .set CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL, 0x00000000 + 2571 .set CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR, 0x00000001 + 2572 .set CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET, 0x00000002 + 2573 .set CYFLD_UDB_W32_FIFO0_LVL_0__SIZE, 0x00000001 + 2574 .set CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL, 0x00000000 + 2575 .set CYVAL_UDB_W32_FIFO0_LVL_0_MID, 0x00000001 + 2576 .set CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET, 0x00000003 + 2577 .set CYFLD_UDB_W32_FIFO1_LVL_0__SIZE, 0x00000001 + 2578 .set CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL, 0x00000000 + 2579 .set CYVAL_UDB_W32_FIFO1_LVL_0_MID, 0x00000001 + 2580 .set CYFLD_UDB_W32_INT_EN_0__OFFSET, 0x00000004 + 2581 .set CYFLD_UDB_W32_INT_EN_0__SIZE, 0x00000001 + 2582 .set CYVAL_UDB_W32_INT_EN_0_DISABLE, 0x00000000 + 2583 .set CYVAL_UDB_W32_INT_EN_0_ENABLE, 0x00000001 + 2584 .set CYFLD_UDB_W32_CNT_START_0__OFFSET, 0x00000005 + 2585 .set CYFLD_UDB_W32_CNT_START_0__SIZE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 47 + + + 2586 .set CYVAL_UDB_W32_CNT_START_0_DISABLE, 0x00000000 + 2587 .set CYVAL_UDB_W32_CNT_START_0_ENABLE, 0x00000001 + 2588 .set CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET, 0x00000008 + 2589 .set CYFLD_UDB_W32_FIFO0_CLR_1__SIZE, 0x00000001 + 2590 .set CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL, 0x00000000 + 2591 .set CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR, 0x00000001 + 2592 .set CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET, 0x00000009 + 2593 .set CYFLD_UDB_W32_FIFO1_CLR_1__SIZE, 0x00000001 + 2594 .set CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL, 0x00000000 + 2595 .set CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR, 0x00000001 + 2596 .set CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET, 0x0000000a + 2597 .set CYFLD_UDB_W32_FIFO0_LVL_1__SIZE, 0x00000001 + 2598 .set CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL, 0x00000000 + 2599 .set CYVAL_UDB_W32_FIFO0_LVL_1_MID, 0x00000001 + 2600 .set CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET, 0x0000000b + 2601 .set CYFLD_UDB_W32_FIFO1_LVL_1__SIZE, 0x00000001 + 2602 .set CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL, 0x00000000 + 2603 .set CYVAL_UDB_W32_FIFO1_LVL_1_MID, 0x00000001 + 2604 .set CYFLD_UDB_W32_INT_EN_1__OFFSET, 0x0000000c + 2605 .set CYFLD_UDB_W32_INT_EN_1__SIZE, 0x00000001 + 2606 .set CYVAL_UDB_W32_INT_EN_1_DISABLE, 0x00000000 + 2607 .set CYVAL_UDB_W32_INT_EN_1_ENABLE, 0x00000001 + 2608 .set CYFLD_UDB_W32_CNT_START_1__OFFSET, 0x0000000d + 2609 .set CYFLD_UDB_W32_CNT_START_1__SIZE, 0x00000001 + 2610 .set CYVAL_UDB_W32_CNT_START_1_DISABLE, 0x00000000 + 2611 .set CYVAL_UDB_W32_CNT_START_1_ENABLE, 0x00000001 + 2612 .set CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET, 0x00000010 + 2613 .set CYFLD_UDB_W32_FIFO0_CLR_2__SIZE, 0x00000001 + 2614 .set CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL, 0x00000000 + 2615 .set CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR, 0x00000001 + 2616 .set CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET, 0x00000011 + 2617 .set CYFLD_UDB_W32_FIFO1_CLR_2__SIZE, 0x00000001 + 2618 .set CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL, 0x00000000 + 2619 .set CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR, 0x00000001 + 2620 .set CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET, 0x00000012 + 2621 .set CYFLD_UDB_W32_FIFO0_LVL_2__SIZE, 0x00000001 + 2622 .set CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL, 0x00000000 + 2623 .set CYVAL_UDB_W32_FIFO0_LVL_2_MID, 0x00000001 + 2624 .set CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET, 0x00000013 + 2625 .set CYFLD_UDB_W32_FIFO1_LVL_2__SIZE, 0x00000001 + 2626 .set CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL, 0x00000000 + 2627 .set CYVAL_UDB_W32_FIFO1_LVL_2_MID, 0x00000001 + 2628 .set CYFLD_UDB_W32_INT_EN_2__OFFSET, 0x00000014 + 2629 .set CYFLD_UDB_W32_INT_EN_2__SIZE, 0x00000001 + 2630 .set CYVAL_UDB_W32_INT_EN_2_DISABLE, 0x00000000 + 2631 .set CYVAL_UDB_W32_INT_EN_2_ENABLE, 0x00000001 + 2632 .set CYFLD_UDB_W32_CNT_START_2__OFFSET, 0x00000015 + 2633 .set CYFLD_UDB_W32_CNT_START_2__SIZE, 0x00000001 + 2634 .set CYVAL_UDB_W32_CNT_START_2_DISABLE, 0x00000000 + 2635 .set CYVAL_UDB_W32_CNT_START_2_ENABLE, 0x00000001 + 2636 .set CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET, 0x00000018 + 2637 .set CYFLD_UDB_W32_FIFO0_CLR_3__SIZE, 0x00000001 + 2638 .set CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL, 0x00000000 + 2639 .set CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR, 0x00000001 + 2640 .set CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET, 0x00000019 + 2641 .set CYFLD_UDB_W32_FIFO1_CLR_3__SIZE, 0x00000001 + 2642 .set CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 48 + + + 2643 .set CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR, 0x00000001 + 2644 .set CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET, 0x0000001a + 2645 .set CYFLD_UDB_W32_FIFO0_LVL_3__SIZE, 0x00000001 + 2646 .set CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL, 0x00000000 + 2647 .set CYVAL_UDB_W32_FIFO0_LVL_3_MID, 0x00000001 + 2648 .set CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET, 0x0000001b + 2649 .set CYFLD_UDB_W32_FIFO1_LVL_3__SIZE, 0x00000001 + 2650 .set CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL, 0x00000000 + 2651 .set CYVAL_UDB_W32_FIFO1_LVL_3_MID, 0x00000001 + 2652 .set CYFLD_UDB_W32_INT_EN_3__OFFSET, 0x0000001c + 2653 .set CYFLD_UDB_W32_INT_EN_3__SIZE, 0x00000001 + 2654 .set CYVAL_UDB_W32_INT_EN_3_DISABLE, 0x00000000 + 2655 .set CYVAL_UDB_W32_INT_EN_3_ENABLE, 0x00000001 + 2656 .set CYFLD_UDB_W32_CNT_START_3__OFFSET, 0x0000001d + 2657 .set CYFLD_UDB_W32_CNT_START_3__SIZE, 0x00000001 + 2658 .set CYVAL_UDB_W32_CNT_START_3_DISABLE, 0x00000000 + 2659 .set CYVAL_UDB_W32_CNT_START_3_ENABLE, 0x00000001 + 2660 .set CYREG_UDB_W32_MC_00, 0x400f2280 + 2661 .set CYFLD_UDB_W32_PLD0_MC_0__OFFSET, 0x00000000 + 2662 .set CYFLD_UDB_W32_PLD0_MC_0__SIZE, 0x00000004 + 2663 .set CYFLD_UDB_W32_PLD1_MC_0__OFFSET, 0x00000004 + 2664 .set CYFLD_UDB_W32_PLD1_MC_0__SIZE, 0x00000004 + 2665 .set CYFLD_UDB_W32_PLD0_MC_1__OFFSET, 0x00000008 + 2666 .set CYFLD_UDB_W32_PLD0_MC_1__SIZE, 0x00000004 + 2667 .set CYFLD_UDB_W32_PLD1_MC_1__OFFSET, 0x0000000c + 2668 .set CYFLD_UDB_W32_PLD1_MC_1__SIZE, 0x00000004 + 2669 .set CYFLD_UDB_W32_PLD0_MC_2__OFFSET, 0x00000010 + 2670 .set CYFLD_UDB_W32_PLD0_MC_2__SIZE, 0x00000004 + 2671 .set CYFLD_UDB_W32_PLD1_MC_2__OFFSET, 0x00000014 + 2672 .set CYFLD_UDB_W32_PLD1_MC_2__SIZE, 0x00000004 + 2673 .set CYFLD_UDB_W32_PLD0_MC_3__OFFSET, 0x00000018 + 2674 .set CYFLD_UDB_W32_PLD0_MC_3__SIZE, 0x00000004 + 2675 .set CYFLD_UDB_W32_PLD1_MC_3__OFFSET, 0x0000001c + 2676 .set CYFLD_UDB_W32_PLD1_MC_3__SIZE, 0x00000004 + 2677 .set CYDEV_UDB_P0_BASE, 0x400f3000 + 2678 .set CYDEV_UDB_P0_SIZE, 0x00000200 + 2679 .set CYDEV_UDB_P0_U0_BASE, 0x400f3000 + 2680 .set CYDEV_UDB_P0_U0_SIZE, 0x00000080 + 2681 .set CYREG_UDB_P0_U0_PLD_IT0, 0x400f3000 + 2682 .set CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET, 0x00000000 + 2683 .set CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE, 0x00000001 + 2684 .set CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET, 0x00000001 + 2685 .set CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE, 0x00000001 + 2686 .set CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET, 0x00000002 + 2687 .set CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE, 0x00000001 + 2688 .set CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET, 0x00000003 + 2689 .set CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE, 0x00000001 + 2690 .set CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET, 0x00000004 + 2691 .set CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE, 0x00000001 + 2692 .set CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET, 0x00000005 + 2693 .set CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE, 0x00000001 + 2694 .set CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET, 0x00000006 + 2695 .set CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE, 0x00000001 + 2696 .set CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET, 0x00000007 + 2697 .set CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE, 0x00000001 + 2698 .set CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET, 0x00000008 + 2699 .set CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 49 + + + 2700 .set CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET, 0x00000009 + 2701 .set CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE, 0x00000001 + 2702 .set CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET, 0x0000000a + 2703 .set CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE, 0x00000001 + 2704 .set CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET, 0x0000000b + 2705 .set CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE, 0x00000001 + 2706 .set CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET, 0x0000000c + 2707 .set CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE, 0x00000001 + 2708 .set CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET, 0x0000000d + 2709 .set CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE, 0x00000001 + 2710 .set CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET, 0x0000000e + 2711 .set CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE, 0x00000001 + 2712 .set CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET, 0x0000000f + 2713 .set CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE, 0x00000001 + 2714 .set CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET, 0x00000010 + 2715 .set CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE, 0x00000001 + 2716 .set CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET, 0x00000011 + 2717 .set CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE, 0x00000001 + 2718 .set CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET, 0x00000012 + 2719 .set CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE, 0x00000001 + 2720 .set CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET, 0x00000013 + 2721 .set CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE, 0x00000001 + 2722 .set CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET, 0x00000014 + 2723 .set CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE, 0x00000001 + 2724 .set CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET, 0x00000015 + 2725 .set CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE, 0x00000001 + 2726 .set CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET, 0x00000016 + 2727 .set CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE, 0x00000001 + 2728 .set CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET, 0x00000017 + 2729 .set CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE, 0x00000001 + 2730 .set CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET, 0x00000018 + 2731 .set CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE, 0x00000001 + 2732 .set CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET, 0x00000019 + 2733 .set CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE, 0x00000001 + 2734 .set CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET, 0x0000001a + 2735 .set CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE, 0x00000001 + 2736 .set CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET, 0x0000001b + 2737 .set CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE, 0x00000001 + 2738 .set CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET, 0x0000001c + 2739 .set CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE, 0x00000001 + 2740 .set CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET, 0x0000001d + 2741 .set CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE, 0x00000001 + 2742 .set CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET, 0x0000001e + 2743 .set CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE, 0x00000001 + 2744 .set CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET, 0x0000001f + 2745 .set CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE, 0x00000001 + 2746 .set CYREG_UDB_P0_U0_PLD_IT1, 0x400f3004 + 2747 .set CYREG_UDB_P0_U0_PLD_IT2, 0x400f3008 + 2748 .set CYREG_UDB_P0_U0_PLD_IT3, 0x400f300c + 2749 .set CYREG_UDB_P0_U0_PLD_IT4, 0x400f3010 + 2750 .set CYREG_UDB_P0_U0_PLD_IT5, 0x400f3014 + 2751 .set CYREG_UDB_P0_U0_PLD_IT6, 0x400f3018 + 2752 .set CYREG_UDB_P0_U0_PLD_IT7, 0x400f301c + 2753 .set CYREG_UDB_P0_U0_PLD_IT8, 0x400f3020 + 2754 .set CYREG_UDB_P0_U0_PLD_IT9, 0x400f3024 + 2755 .set CYREG_UDB_P0_U0_PLD_IT10, 0x400f3028 + 2756 .set CYREG_UDB_P0_U0_PLD_IT11, 0x400f302c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 50 + + + 2757 .set CYREG_UDB_P0_U0_PLD_ORT0, 0x400f3030 + 2758 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET, 0x00000000 + 2759 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE, 0x00000001 + 2760 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET, 0x00000001 + 2761 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE, 0x00000001 + 2762 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET, 0x00000002 + 2763 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE, 0x00000001 + 2764 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET, 0x00000003 + 2765 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE, 0x00000001 + 2766 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET, 0x00000004 + 2767 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE, 0x00000001 + 2768 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET, 0x00000005 + 2769 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE, 0x00000001 + 2770 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET, 0x00000006 + 2771 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE, 0x00000001 + 2772 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET, 0x00000007 + 2773 .set CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE, 0x00000001 + 2774 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET, 0x00000008 + 2775 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE, 0x00000001 + 2776 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET, 0x00000009 + 2777 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE, 0x00000001 + 2778 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET, 0x0000000a + 2779 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE, 0x00000001 + 2780 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET, 0x0000000b + 2781 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE, 0x00000001 + 2782 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET, 0x0000000c + 2783 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE, 0x00000001 + 2784 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET, 0x0000000d + 2785 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE, 0x00000001 + 2786 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET, 0x0000000e + 2787 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE, 0x00000001 + 2788 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET, 0x0000000f + 2789 .set CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE, 0x00000001 + 2790 .set CYREG_UDB_P0_U0_PLD_ORT1, 0x400f3032 + 2791 .set CYREG_UDB_P0_U0_PLD_ORT2, 0x400f3034 + 2792 .set CYREG_UDB_P0_U0_PLD_ORT3, 0x400f3036 + 2793 .set CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST, 0x400f3038 + 2794 .set CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET, 0x00000000 + 2795 .set CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE, 0x00000001 + 2796 .set CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE, 0x00000000 + 2797 .set CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE, 0x00000001 + 2798 .set CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET, 0x00000001 + 2799 .set CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE, 0x00000001 + 2800 .set CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV, 0x00000000 + 2801 .set CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED, 0x00000001 + 2802 .set CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET, 0x00000002 + 2803 .set CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE, 0x00000001 + 2804 .set CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE, 0x00000000 + 2805 .set CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE, 0x00000001 + 2806 .set CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET, 0x00000003 + 2807 .set CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE, 0x00000001 + 2808 .set CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV, 0x00000000 + 2809 .set CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED, 0x00000001 + 2810 .set CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET, 0x00000004 + 2811 .set CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE, 0x00000001 + 2812 .set CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE, 0x00000000 + 2813 .set CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 51 + + + 2814 .set CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET, 0x00000005 + 2815 .set CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE, 0x00000001 + 2816 .set CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV, 0x00000000 + 2817 .set CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED, 0x00000001 + 2818 .set CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET, 0x00000006 + 2819 .set CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE, 0x00000001 + 2820 .set CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE, 0x00000000 + 2821 .set CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE, 0x00000001 + 2822 .set CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET, 0x00000007 + 2823 .set CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE, 0x00000001 + 2824 .set CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV, 0x00000000 + 2825 .set CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED, 0x00000001 + 2826 .set CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET, 0x00000008 + 2827 .set CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE, 0x00000001 + 2828 .set CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE, 0x00000000 + 2829 .set CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE, 0x00000001 + 2830 .set CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET, 0x00000009 + 2831 .set CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE, 0x00000001 + 2832 .set CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV, 0x00000000 + 2833 .set CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED, 0x00000001 + 2834 .set CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET, 0x0000000a + 2835 .set CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE, 0x00000001 + 2836 .set CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE, 0x00000000 + 2837 .set CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE, 0x00000001 + 2838 .set CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET, 0x0000000b + 2839 .set CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE, 0x00000001 + 2840 .set CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV, 0x00000000 + 2841 .set CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED, 0x00000001 + 2842 .set CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET, 0x0000000c + 2843 .set CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE, 0x00000001 + 2844 .set CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE, 0x00000000 + 2845 .set CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE, 0x00000001 + 2846 .set CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET, 0x0000000d + 2847 .set CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE, 0x00000001 + 2848 .set CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV, 0x00000000 + 2849 .set CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED, 0x00000001 + 2850 .set CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET, 0x0000000e + 2851 .set CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE, 0x00000001 + 2852 .set CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE, 0x00000000 + 2853 .set CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE, 0x00000001 + 2854 .set CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET, 0x0000000f + 2855 .set CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE, 0x00000001 + 2856 .set CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV, 0x00000000 + 2857 .set CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED, 0x00000001 + 2858 .set CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB, 0x400f303a + 2859 .set CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET, 0x00000000 + 2860 .set CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE, 0x00000002 + 2861 .set CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF, 0x00000000 + 2862 .set CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY, 0x00000001 + 2863 .set CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H, 0x00000002 + 2864 .set CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L, 0x00000003 + 2865 .set CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET, 0x00000002 + 2866 .set CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE, 0x00000002 + 2867 .set CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF, 0x00000000 + 2868 .set CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY, 0x00000001 + 2869 .set CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H, 0x00000002 + 2870 .set CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L, 0x00000003 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 52 + + + 2871 .set CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET, 0x00000004 + 2872 .set CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE, 0x00000002 + 2873 .set CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF, 0x00000000 + 2874 .set CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY, 0x00000001 + 2875 .set CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H, 0x00000002 + 2876 .set CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L, 0x00000003 + 2877 .set CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET, 0x00000006 + 2878 .set CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE, 0x00000002 + 2879 .set CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF, 0x00000000 + 2880 .set CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY, 0x00000001 + 2881 .set CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H, 0x00000002 + 2882 .set CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L, 0x00000003 + 2883 .set CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET, 0x00000008 + 2884 .set CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE, 0x00000002 + 2885 .set CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF, 0x00000000 + 2886 .set CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY, 0x00000001 + 2887 .set CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H, 0x00000002 + 2888 .set CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L, 0x00000003 + 2889 .set CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET, 0x0000000a + 2890 .set CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE, 0x00000002 + 2891 .set CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF, 0x00000000 + 2892 .set CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY, 0x00000001 + 2893 .set CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H, 0x00000002 + 2894 .set CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L, 0x00000003 + 2895 .set CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET, 0x0000000c + 2896 .set CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE, 0x00000002 + 2897 .set CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF, 0x00000000 + 2898 .set CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY, 0x00000001 + 2899 .set CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H, 0x00000002 + 2900 .set CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L, 0x00000003 + 2901 .set CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET, 0x0000000e + 2902 .set CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE, 0x00000002 + 2903 .set CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF, 0x00000000 + 2904 .set CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY, 0x00000001 + 2905 .set CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H, 0x00000002 + 2906 .set CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L, 0x00000003 + 2907 .set CYREG_UDB_P0_U0_PLD_MC_SET_RESET, 0x400f303c + 2908 .set CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET, 0x00000000 + 2909 .set CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE, 0x00000001 + 2910 .set CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE, 0x00000000 + 2911 .set CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE, 0x00000001 + 2912 .set CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET, 0x00000001 + 2913 .set CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE, 0x00000001 + 2914 .set CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE, 0x00000000 + 2915 .set CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE, 0x00000001 + 2916 .set CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET, 0x00000002 + 2917 .set CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE, 0x00000001 + 2918 .set CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE, 0x00000000 + 2919 .set CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE, 0x00000001 + 2920 .set CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET, 0x00000003 + 2921 .set CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE, 0x00000001 + 2922 .set CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE, 0x00000000 + 2923 .set CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE, 0x00000001 + 2924 .set CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET, 0x00000004 + 2925 .set CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE, 0x00000001 + 2926 .set CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE, 0x00000000 + 2927 .set CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 53 + + + 2928 .set CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET, 0x00000005 + 2929 .set CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE, 0x00000001 + 2930 .set CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE, 0x00000000 + 2931 .set CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE, 0x00000001 + 2932 .set CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET, 0x00000006 + 2933 .set CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE, 0x00000001 + 2934 .set CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE, 0x00000000 + 2935 .set CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE, 0x00000001 + 2936 .set CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET, 0x00000007 + 2937 .set CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE, 0x00000001 + 2938 .set CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE, 0x00000000 + 2939 .set CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE, 0x00000001 + 2940 .set CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET, 0x00000008 + 2941 .set CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE, 0x00000001 + 2942 .set CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE, 0x00000000 + 2943 .set CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE, 0x00000001 + 2944 .set CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET, 0x00000009 + 2945 .set CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE, 0x00000001 + 2946 .set CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE, 0x00000000 + 2947 .set CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE, 0x00000001 + 2948 .set CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET, 0x0000000a + 2949 .set CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE, 0x00000001 + 2950 .set CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE, 0x00000000 + 2951 .set CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE, 0x00000001 + 2952 .set CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET, 0x0000000b + 2953 .set CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE, 0x00000001 + 2954 .set CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE, 0x00000000 + 2955 .set CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE, 0x00000001 + 2956 .set CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET, 0x0000000c + 2957 .set CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE, 0x00000001 + 2958 .set CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE, 0x00000000 + 2959 .set CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE, 0x00000001 + 2960 .set CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET, 0x0000000d + 2961 .set CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE, 0x00000001 + 2962 .set CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE, 0x00000000 + 2963 .set CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE, 0x00000001 + 2964 .set CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET, 0x0000000e + 2965 .set CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE, 0x00000001 + 2966 .set CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE, 0x00000000 + 2967 .set CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE, 0x00000001 + 2968 .set CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET, 0x0000000f + 2969 .set CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE, 0x00000001 + 2970 .set CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE, 0x00000000 + 2971 .set CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE, 0x00000001 + 2972 .set CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS, 0x400f303e + 2973 .set CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET, 0x00000000 + 2974 .set CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE, 0x00000001 + 2975 .set CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER, 0x00000000 + 2976 .set CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL, 0x00000001 + 2977 .set CYFLD_UDB_P_U_NC1__OFFSET, 0x00000001 + 2978 .set CYFLD_UDB_P_U_NC1__SIZE, 0x00000001 + 2979 .set CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET, 0x00000002 + 2980 .set CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE, 0x00000001 + 2981 .set CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER, 0x00000000 + 2982 .set CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL, 0x00000001 + 2983 .set CYFLD_UDB_P_U_NC3__OFFSET, 0x00000003 + 2984 .set CYFLD_UDB_P_U_NC3__SIZE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 54 + + + 2985 .set CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET, 0x00000004 + 2986 .set CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE, 0x00000001 + 2987 .set CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER, 0x00000000 + 2988 .set CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL, 0x00000001 + 2989 .set CYFLD_UDB_P_U_NC5__OFFSET, 0x00000005 + 2990 .set CYFLD_UDB_P_U_NC5__SIZE, 0x00000001 + 2991 .set CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET, 0x00000006 + 2992 .set CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE, 0x00000001 + 2993 .set CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER, 0x00000000 + 2994 .set CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL, 0x00000001 + 2995 .set CYFLD_UDB_P_U_NC7__OFFSET, 0x00000007 + 2996 .set CYFLD_UDB_P_U_NC7__SIZE, 0x00000001 + 2997 .set CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET, 0x00000008 + 2998 .set CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE, 0x00000001 + 2999 .set CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER, 0x00000000 + 3000 .set CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL, 0x00000001 + 3001 .set CYFLD_UDB_P_U_NC9__OFFSET, 0x00000009 + 3002 .set CYFLD_UDB_P_U_NC9__SIZE, 0x00000001 + 3003 .set CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET, 0x0000000a + 3004 .set CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE, 0x00000001 + 3005 .set CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER, 0x00000000 + 3006 .set CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL, 0x00000001 + 3007 .set CYFLD_UDB_P_U_NC11__OFFSET, 0x0000000b + 3008 .set CYFLD_UDB_P_U_NC11__SIZE, 0x00000001 + 3009 .set CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET, 0x0000000c + 3010 .set CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE, 0x00000001 + 3011 .set CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER, 0x00000000 + 3012 .set CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL, 0x00000001 + 3013 .set CYFLD_UDB_P_U_NC13__OFFSET, 0x0000000d + 3014 .set CYFLD_UDB_P_U_NC13__SIZE, 0x00000001 + 3015 .set CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET, 0x0000000e + 3016 .set CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE, 0x00000001 + 3017 .set CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER, 0x00000000 + 3018 .set CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL, 0x00000001 + 3019 .set CYFLD_UDB_P_U_NC15__OFFSET, 0x0000000f + 3020 .set CYFLD_UDB_P_U_NC15__SIZE, 0x00000001 + 3021 .set CYREG_UDB_P0_U0_CFG0, 0x400f3040 + 3022 .set CYFLD_UDB_P_U_RAD0__OFFSET, 0x00000000 + 3023 .set CYFLD_UDB_P_U_RAD0__SIZE, 0x00000003 + 3024 .set CYVAL_UDB_P_U_RAD0_OFF, 0x00000000 + 3025 .set CYVAL_UDB_P_U_RAD0_DP_IN0, 0x00000001 + 3026 .set CYVAL_UDB_P_U_RAD0_DP_IN1, 0x00000002 + 3027 .set CYVAL_UDB_P_U_RAD0_DP_IN2, 0x00000003 + 3028 .set CYVAL_UDB_P_U_RAD0_DP_IN3, 0x00000004 + 3029 .set CYVAL_UDB_P_U_RAD0_DP_IN4, 0x00000005 + 3030 .set CYVAL_UDB_P_U_RAD0_DP_IN5, 0x00000006 + 3031 .set CYVAL_UDB_P_U_RAD0_RESERVED, 0x00000007 + 3032 .set CYFLD_UDB_P_U_RAD1__OFFSET, 0x00000004 + 3033 .set CYFLD_UDB_P_U_RAD1__SIZE, 0x00000003 + 3034 .set CYVAL_UDB_P_U_RAD1_OFF, 0x00000000 + 3035 .set CYVAL_UDB_P_U_RAD1_DP_IN0, 0x00000001 + 3036 .set CYVAL_UDB_P_U_RAD1_DP_IN1, 0x00000002 + 3037 .set CYVAL_UDB_P_U_RAD1_DP_IN2, 0x00000003 + 3038 .set CYVAL_UDB_P_U_RAD1_DP_IN3, 0x00000004 + 3039 .set CYVAL_UDB_P_U_RAD1_DP_IN4, 0x00000005 + 3040 .set CYVAL_UDB_P_U_RAD1_DP_IN5, 0x00000006 + 3041 .set CYVAL_UDB_P_U_RAD1_RESERVED, 0x00000007 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 55 + + + 3042 .set CYREG_UDB_P0_U0_CFG1, 0x400f3041 + 3043 .set CYFLD_UDB_P_U_RAD2__OFFSET, 0x00000000 + 3044 .set CYFLD_UDB_P_U_RAD2__SIZE, 0x00000003 + 3045 .set CYVAL_UDB_P_U_RAD2_OFF, 0x00000000 + 3046 .set CYVAL_UDB_P_U_RAD2_DP_IN0, 0x00000001 + 3047 .set CYVAL_UDB_P_U_RAD2_DP_IN1, 0x00000002 + 3048 .set CYVAL_UDB_P_U_RAD2_DP_IN2, 0x00000003 + 3049 .set CYVAL_UDB_P_U_RAD2_DP_IN3, 0x00000004 + 3050 .set CYVAL_UDB_P_U_RAD2_DP_IN4, 0x00000005 + 3051 .set CYVAL_UDB_P_U_RAD2_DP_IN5, 0x00000006 + 3052 .set CYVAL_UDB_P_U_RAD2_RESERVED, 0x00000007 + 3053 .set CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET, 0x00000003 + 3054 .set CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE, 0x00000001 + 3055 .set CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE, 0x00000000 + 3056 .set CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS, 0x00000001 + 3057 .set CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET, 0x00000004 + 3058 .set CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE, 0x00000001 + 3059 .set CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE, 0x00000000 + 3060 .set CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS, 0x00000001 + 3061 .set CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET, 0x00000005 + 3062 .set CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE, 0x00000001 + 3063 .set CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE, 0x00000000 + 3064 .set CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS, 0x00000001 + 3065 .set CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET, 0x00000006 + 3066 .set CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE, 0x00000001 + 3067 .set CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE, 0x00000000 + 3068 .set CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS, 0x00000001 + 3069 .set CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET, 0x00000007 + 3070 .set CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE, 0x00000001 + 3071 .set CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE, 0x00000000 + 3072 .set CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS, 0x00000001 + 3073 .set CYREG_UDB_P0_U0_CFG2, 0x400f3042 + 3074 .set CYFLD_UDB_P_U_F0_LD__OFFSET, 0x00000000 + 3075 .set CYFLD_UDB_P_U_F0_LD__SIZE, 0x00000003 + 3076 .set CYVAL_UDB_P_U_F0_LD_OFF, 0x00000000 + 3077 .set CYVAL_UDB_P_U_F0_LD_DP_IN0, 0x00000001 + 3078 .set CYVAL_UDB_P_U_F0_LD_DP_IN1, 0x00000002 + 3079 .set CYVAL_UDB_P_U_F0_LD_DP_IN2, 0x00000003 + 3080 .set CYVAL_UDB_P_U_F0_LD_DP_IN3, 0x00000004 + 3081 .set CYVAL_UDB_P_U_F0_LD_DP_IN4, 0x00000005 + 3082 .set CYVAL_UDB_P_U_F0_LD_DP_IN5, 0x00000006 + 3083 .set CYVAL_UDB_P_U_F0_LD_RESERVED, 0x00000007 + 3084 .set CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET, 0x00000003 + 3085 .set CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE, 0x00000001 + 3086 .set CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE, 0x00000000 + 3087 .set CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS, 0x00000001 + 3088 .set CYFLD_UDB_P_U_F1_LD__OFFSET, 0x00000004 + 3089 .set CYFLD_UDB_P_U_F1_LD__SIZE, 0x00000003 + 3090 .set CYVAL_UDB_P_U_F1_LD_OFF, 0x00000000 + 3091 .set CYVAL_UDB_P_U_F1_LD_DP_IN0, 0x00000001 + 3092 .set CYVAL_UDB_P_U_F1_LD_DP_IN1, 0x00000002 + 3093 .set CYVAL_UDB_P_U_F1_LD_DP_IN2, 0x00000003 + 3094 .set CYVAL_UDB_P_U_F1_LD_DP_IN3, 0x00000004 + 3095 .set CYVAL_UDB_P_U_F1_LD_DP_IN4, 0x00000005 + 3096 .set CYVAL_UDB_P_U_F1_LD_DP_IN5, 0x00000006 + 3097 .set CYVAL_UDB_P_U_F1_LD_RESERVED, 0x00000007 + 3098 .set CYREG_UDB_P0_U0_CFG3, 0x400f3043 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 56 + + + 3099 .set CYFLD_UDB_P_U_D0_LD__OFFSET, 0x00000000 + 3100 .set CYFLD_UDB_P_U_D0_LD__SIZE, 0x00000003 + 3101 .set CYVAL_UDB_P_U_D0_LD_OFF, 0x00000000 + 3102 .set CYVAL_UDB_P_U_D0_LD_DP_IN0, 0x00000001 + 3103 .set CYVAL_UDB_P_U_D0_LD_DP_IN1, 0x00000002 + 3104 .set CYVAL_UDB_P_U_D0_LD_DP_IN2, 0x00000003 + 3105 .set CYVAL_UDB_P_U_D0_LD_DP_IN3, 0x00000004 + 3106 .set CYVAL_UDB_P_U_D0_LD_DP_IN4, 0x00000005 + 3107 .set CYVAL_UDB_P_U_D0_LD_DP_IN5, 0x00000006 + 3108 .set CYVAL_UDB_P_U_D0_LD_RESERVED, 0x00000007 + 3109 .set CYFLD_UDB_P_U_D1_LD__OFFSET, 0x00000004 + 3110 .set CYFLD_UDB_P_U_D1_LD__SIZE, 0x00000003 + 3111 .set CYVAL_UDB_P_U_D1_LD_OFF, 0x00000000 + 3112 .set CYVAL_UDB_P_U_D1_LD_DP_IN0, 0x00000001 + 3113 .set CYVAL_UDB_P_U_D1_LD_DP_IN1, 0x00000002 + 3114 .set CYVAL_UDB_P_U_D1_LD_DP_IN2, 0x00000003 + 3115 .set CYVAL_UDB_P_U_D1_LD_DP_IN3, 0x00000004 + 3116 .set CYVAL_UDB_P_U_D1_LD_DP_IN4, 0x00000005 + 3117 .set CYVAL_UDB_P_U_D1_LD_DP_IN5, 0x00000006 + 3118 .set CYVAL_UDB_P_U_D1_LD_RESERVED, 0x00000007 + 3119 .set CYREG_UDB_P0_U0_CFG4, 0x400f3044 + 3120 .set CYFLD_UDB_P_U_SI_MUX__OFFSET, 0x00000000 + 3121 .set CYFLD_UDB_P_U_SI_MUX__SIZE, 0x00000003 + 3122 .set CYVAL_UDB_P_U_SI_MUX_OFF, 0x00000000 + 3123 .set CYVAL_UDB_P_U_SI_MUX_DP_IN0, 0x00000001 + 3124 .set CYVAL_UDB_P_U_SI_MUX_DP_IN1, 0x00000002 + 3125 .set CYVAL_UDB_P_U_SI_MUX_DP_IN2, 0x00000003 + 3126 .set CYVAL_UDB_P_U_SI_MUX_DP_IN3, 0x00000004 + 3127 .set CYVAL_UDB_P_U_SI_MUX_DP_IN4, 0x00000005 + 3128 .set CYVAL_UDB_P_U_SI_MUX_DP_IN5, 0x00000006 + 3129 .set CYVAL_UDB_P_U_SI_MUX_RESERVED, 0x00000007 + 3130 .set CYFLD_UDB_P_U_CI_MUX__OFFSET, 0x00000004 + 3131 .set CYFLD_UDB_P_U_CI_MUX__SIZE, 0x00000003 + 3132 .set CYVAL_UDB_P_U_CI_MUX_OFF, 0x00000000 + 3133 .set CYVAL_UDB_P_U_CI_MUX_DP_IN0, 0x00000001 + 3134 .set CYVAL_UDB_P_U_CI_MUX_DP_IN1, 0x00000002 + 3135 .set CYVAL_UDB_P_U_CI_MUX_DP_IN2, 0x00000003 + 3136 .set CYVAL_UDB_P_U_CI_MUX_DP_IN3, 0x00000004 + 3137 .set CYVAL_UDB_P_U_CI_MUX_DP_IN4, 0x00000005 + 3138 .set CYVAL_UDB_P_U_CI_MUX_DP_IN5, 0x00000006 + 3139 .set CYVAL_UDB_P_U_CI_MUX_RESERVED, 0x00000007 + 3140 .set CYREG_UDB_P0_U0_CFG5, 0x400f3045 + 3141 .set CYFLD_UDB_P_U_OUT0__OFFSET, 0x00000000 + 3142 .set CYFLD_UDB_P_U_OUT0__SIZE, 0x00000004 + 3143 .set CYVAL_UDB_P_U_OUT0_CE0, 0x00000000 + 3144 .set CYVAL_UDB_P_U_OUT0_CL0, 0x00000001 + 3145 .set CYVAL_UDB_P_U_OUT0_Z0, 0x00000002 + 3146 .set CYVAL_UDB_P_U_OUT0_FF0, 0x00000003 + 3147 .set CYVAL_UDB_P_U_OUT0_CE1, 0x00000004 + 3148 .set CYVAL_UDB_P_U_OUT0_CL1, 0x00000005 + 3149 .set CYVAL_UDB_P_U_OUT0_Z1, 0x00000006 + 3150 .set CYVAL_UDB_P_U_OUT0_FF1, 0x00000007 + 3151 .set CYVAL_UDB_P_U_OUT0_OV_MSB, 0x00000008 + 3152 .set CYVAL_UDB_P_U_OUT0_CO_MSB, 0x00000009 + 3153 .set CYVAL_UDB_P_U_OUT0_CMSBO, 0x0000000a + 3154 .set CYVAL_UDB_P_U_OUT0_SO, 0x0000000b + 3155 .set CYVAL_UDB_P_U_OUT0_F0_BLK_STAT, 0x0000000c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 57 + + + 3156 .set CYVAL_UDB_P_U_OUT0_F1_BLK_STAT, 0x0000000d + 3157 .set CYVAL_UDB_P_U_OUT0_F0_BUS_STAT, 0x0000000e + 3158 .set CYVAL_UDB_P_U_OUT0_F1_BUS_STAT, 0x0000000f + 3159 .set CYFLD_UDB_P_U_OUT1__OFFSET, 0x00000004 + 3160 .set CYFLD_UDB_P_U_OUT1__SIZE, 0x00000004 + 3161 .set CYVAL_UDB_P_U_OUT1_CE0, 0x00000000 + 3162 .set CYVAL_UDB_P_U_OUT1_CL0, 0x00000001 + 3163 .set CYVAL_UDB_P_U_OUT1_Z0, 0x00000002 + 3164 .set CYVAL_UDB_P_U_OUT1_FF0, 0x00000003 + 3165 .set CYVAL_UDB_P_U_OUT1_CE1, 0x00000004 + 3166 .set CYVAL_UDB_P_U_OUT1_CL1, 0x00000005 + 3167 .set CYVAL_UDB_P_U_OUT1_Z1, 0x00000006 + 3168 .set CYVAL_UDB_P_U_OUT1_FF1, 0x00000007 + 3169 .set CYVAL_UDB_P_U_OUT1_OV_MSB, 0x00000008 + 3170 .set CYVAL_UDB_P_U_OUT1_CO_MSB, 0x00000009 + 3171 .set CYVAL_UDB_P_U_OUT1_CMSBO, 0x0000000a + 3172 .set CYVAL_UDB_P_U_OUT1_SO, 0x0000000b + 3173 .set CYVAL_UDB_P_U_OUT1_F0_BLK_STAT, 0x0000000c + 3174 .set CYVAL_UDB_P_U_OUT1_F1_BLK_STAT, 0x0000000d + 3175 .set CYVAL_UDB_P_U_OUT1_F0_BUS_STAT, 0x0000000e + 3176 .set CYVAL_UDB_P_U_OUT1_F1_BUS_STAT, 0x0000000f + 3177 .set CYREG_UDB_P0_U0_CFG6, 0x400f3046 + 3178 .set CYFLD_UDB_P_U_OUT2__OFFSET, 0x00000000 + 3179 .set CYFLD_UDB_P_U_OUT2__SIZE, 0x00000004 + 3180 .set CYVAL_UDB_P_U_OUT2_CE0, 0x00000000 + 3181 .set CYVAL_UDB_P_U_OUT2_CL0, 0x00000001 + 3182 .set CYVAL_UDB_P_U_OUT2_Z0, 0x00000002 + 3183 .set CYVAL_UDB_P_U_OUT2_FF0, 0x00000003 + 3184 .set CYVAL_UDB_P_U_OUT2_CE1, 0x00000004 + 3185 .set CYVAL_UDB_P_U_OUT2_CL1, 0x00000005 + 3186 .set CYVAL_UDB_P_U_OUT2_Z1, 0x00000006 + 3187 .set CYVAL_UDB_P_U_OUT2_FF1, 0x00000007 + 3188 .set CYVAL_UDB_P_U_OUT2_OV_MSB, 0x00000008 + 3189 .set CYVAL_UDB_P_U_OUT2_CO_MSB, 0x00000009 + 3190 .set CYVAL_UDB_P_U_OUT2_CMSBO, 0x0000000a + 3191 .set CYVAL_UDB_P_U_OUT2_SO, 0x0000000b + 3192 .set CYVAL_UDB_P_U_OUT2_F0_BLK_STAT, 0x0000000c + 3193 .set CYVAL_UDB_P_U_OUT2_F1_BLK_STAT, 0x0000000d + 3194 .set CYVAL_UDB_P_U_OUT2_F0_BUS_STAT, 0x0000000e + 3195 .set CYVAL_UDB_P_U_OUT2_F1_BUS_STAT, 0x0000000f + 3196 .set CYFLD_UDB_P_U_OUT3__OFFSET, 0x00000004 + 3197 .set CYFLD_UDB_P_U_OUT3__SIZE, 0x00000004 + 3198 .set CYVAL_UDB_P_U_OUT3_CE0, 0x00000000 + 3199 .set CYVAL_UDB_P_U_OUT3_CL0, 0x00000001 + 3200 .set CYVAL_UDB_P_U_OUT3_Z0, 0x00000002 + 3201 .set CYVAL_UDB_P_U_OUT3_FF0, 0x00000003 + 3202 .set CYVAL_UDB_P_U_OUT3_CE1, 0x00000004 + 3203 .set CYVAL_UDB_P_U_OUT3_CL1, 0x00000005 + 3204 .set CYVAL_UDB_P_U_OUT3_Z1, 0x00000006 + 3205 .set CYVAL_UDB_P_U_OUT3_FF1, 0x00000007 + 3206 .set CYVAL_UDB_P_U_OUT3_OV_MSB, 0x00000008 + 3207 .set CYVAL_UDB_P_U_OUT3_CO_MSB, 0x00000009 + 3208 .set CYVAL_UDB_P_U_OUT3_CMSBO, 0x0000000a + 3209 .set CYVAL_UDB_P_U_OUT3_SO, 0x0000000b + 3210 .set CYVAL_UDB_P_U_OUT3_F0_BLK_STAT, 0x0000000c + 3211 .set CYVAL_UDB_P_U_OUT3_F1_BLK_STAT, 0x0000000d + 3212 .set CYVAL_UDB_P_U_OUT3_F0_BUS_STAT, 0x0000000e + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 58 + + + 3213 .set CYVAL_UDB_P_U_OUT3_F1_BUS_STAT, 0x0000000f + 3214 .set CYREG_UDB_P0_U0_CFG7, 0x400f3047 + 3215 .set CYFLD_UDB_P_U_OUT4__OFFSET, 0x00000000 + 3216 .set CYFLD_UDB_P_U_OUT4__SIZE, 0x00000004 + 3217 .set CYVAL_UDB_P_U_OUT4_CE0, 0x00000000 + 3218 .set CYVAL_UDB_P_U_OUT4_CL0, 0x00000001 + 3219 .set CYVAL_UDB_P_U_OUT4_Z0, 0x00000002 + 3220 .set CYVAL_UDB_P_U_OUT4_FF0, 0x00000003 + 3221 .set CYVAL_UDB_P_U_OUT4_CE1, 0x00000004 + 3222 .set CYVAL_UDB_P_U_OUT4_CL1, 0x00000005 + 3223 .set CYVAL_UDB_P_U_OUT4_Z1, 0x00000006 + 3224 .set CYVAL_UDB_P_U_OUT4_FF1, 0x00000007 + 3225 .set CYVAL_UDB_P_U_OUT4_OV_MSB, 0x00000008 + 3226 .set CYVAL_UDB_P_U_OUT4_CO_MSB, 0x00000009 + 3227 .set CYVAL_UDB_P_U_OUT4_CMSBO, 0x0000000a + 3228 .set CYVAL_UDB_P_U_OUT4_SO, 0x0000000b + 3229 .set CYVAL_UDB_P_U_OUT4_F0_BLK_STAT, 0x0000000c + 3230 .set CYVAL_UDB_P_U_OUT4_F1_BLK_STAT, 0x0000000d + 3231 .set CYVAL_UDB_P_U_OUT4_F0_BUS_STAT, 0x0000000e + 3232 .set CYVAL_UDB_P_U_OUT4_F1_BUS_STAT, 0x0000000f + 3233 .set CYFLD_UDB_P_U_OUT5__OFFSET, 0x00000004 + 3234 .set CYFLD_UDB_P_U_OUT5__SIZE, 0x00000004 + 3235 .set CYVAL_UDB_P_U_OUT5_CE0, 0x00000000 + 3236 .set CYVAL_UDB_P_U_OUT5_CL0, 0x00000001 + 3237 .set CYVAL_UDB_P_U_OUT5_Z0, 0x00000002 + 3238 .set CYVAL_UDB_P_U_OUT5_FF0, 0x00000003 + 3239 .set CYVAL_UDB_P_U_OUT5_CE1, 0x00000004 + 3240 .set CYVAL_UDB_P_U_OUT5_CL1, 0x00000005 + 3241 .set CYVAL_UDB_P_U_OUT5_Z1, 0x00000006 + 3242 .set CYVAL_UDB_P_U_OUT5_FF1, 0x00000007 + 3243 .set CYVAL_UDB_P_U_OUT5_OV_MSB, 0x00000008 + 3244 .set CYVAL_UDB_P_U_OUT5_CO_MSB, 0x00000009 + 3245 .set CYVAL_UDB_P_U_OUT5_CMSBO, 0x0000000a + 3246 .set CYVAL_UDB_P_U_OUT5_SO, 0x0000000b + 3247 .set CYVAL_UDB_P_U_OUT5_F0_BLK_STAT, 0x0000000c + 3248 .set CYVAL_UDB_P_U_OUT5_F1_BLK_STAT, 0x0000000d + 3249 .set CYVAL_UDB_P_U_OUT5_F0_BUS_STAT, 0x0000000e + 3250 .set CYVAL_UDB_P_U_OUT5_F1_BUS_STAT, 0x0000000f + 3251 .set CYREG_UDB_P0_U0_CFG8, 0x400f3048 + 3252 .set CYFLD_UDB_P_U_OUT_SYNC__OFFSET, 0x00000000 + 3253 .set CYFLD_UDB_P_U_OUT_SYNC__SIZE, 0x00000006 + 3254 .set CYVAL_UDB_P_U_OUT_SYNC_REGISTERED, 0x00000000 + 3255 .set CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL, 0x00000001 + 3256 .set CYFLD_UDB_P_U_NC6__OFFSET, 0x00000006 + 3257 .set CYFLD_UDB_P_U_NC6__SIZE, 0x00000001 + 3258 .set CYREG_UDB_P0_U0_CFG9, 0x400f3049 + 3259 .set CYFLD_UDB_P_U_AMASK__OFFSET, 0x00000000 + 3260 .set CYFLD_UDB_P_U_AMASK__SIZE, 0x00000008 + 3261 .set CYREG_UDB_P0_U0_CFG10, 0x400f304a + 3262 .set CYFLD_UDB_P_U_CMASK0__OFFSET, 0x00000000 + 3263 .set CYFLD_UDB_P_U_CMASK0__SIZE, 0x00000008 + 3264 .set CYREG_UDB_P0_U0_CFG11, 0x400f304b + 3265 .set CYREG_UDB_P0_U0_CFG12, 0x400f304c + 3266 .set CYFLD_UDB_P_U_SI_SELA__OFFSET, 0x00000000 + 3267 .set CYFLD_UDB_P_U_SI_SELA__SIZE, 0x00000002 + 3268 .set CYVAL_UDB_P_U_SI_SELA_DEFAULT, 0x00000000 + 3269 .set CYVAL_UDB_P_U_SI_SELA_REGISTERED, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 59 + + + 3270 .set CYVAL_UDB_P_U_SI_SELA_ROUTE, 0x00000002 + 3271 .set CYVAL_UDB_P_U_SI_SELA_CHAIN, 0x00000003 + 3272 .set CYFLD_UDB_P_U_SI_SELB__OFFSET, 0x00000002 + 3273 .set CYFLD_UDB_P_U_SI_SELB__SIZE, 0x00000002 + 3274 .set CYVAL_UDB_P_U_SI_SELB_DEFAULT, 0x00000000 + 3275 .set CYVAL_UDB_P_U_SI_SELB_REGISTERED, 0x00000001 + 3276 .set CYVAL_UDB_P_U_SI_SELB_ROUTE, 0x00000002 + 3277 .set CYVAL_UDB_P_U_SI_SELB_CHAIN, 0x00000003 + 3278 .set CYFLD_UDB_P_U_DEF_SI__OFFSET, 0x00000004 + 3279 .set CYFLD_UDB_P_U_DEF_SI__SIZE, 0x00000001 + 3280 .set CYVAL_UDB_P_U_DEF_SI_DEFAULT_0, 0x00000000 + 3281 .set CYVAL_UDB_P_U_DEF_SI_DEFAULT_1, 0x00000001 + 3282 .set CYFLD_UDB_P_U_AMASK_EN__OFFSET, 0x00000005 + 3283 .set CYFLD_UDB_P_U_AMASK_EN__SIZE, 0x00000001 + 3284 .set CYVAL_UDB_P_U_AMASK_EN_DISABLE, 0x00000000 + 3285 .set CYVAL_UDB_P_U_AMASK_EN_ENABLE, 0x00000001 + 3286 .set CYFLD_UDB_P_U_CMASK0_EN__OFFSET, 0x00000006 + 3287 .set CYFLD_UDB_P_U_CMASK0_EN__SIZE, 0x00000001 + 3288 .set CYVAL_UDB_P_U_CMASK0_EN_DISABLE, 0x00000000 + 3289 .set CYVAL_UDB_P_U_CMASK0_EN_ENABLE, 0x00000001 + 3290 .set CYFLD_UDB_P_U_CMASK1_EN__OFFSET, 0x00000007 + 3291 .set CYFLD_UDB_P_U_CMASK1_EN__SIZE, 0x00000001 + 3292 .set CYVAL_UDB_P_U_CMASK1_EN_DISABLE, 0x00000000 + 3293 .set CYVAL_UDB_P_U_CMASK1_EN_ENABLE, 0x00000001 + 3294 .set CYREG_UDB_P0_U0_CFG13, 0x400f304d + 3295 .set CYFLD_UDB_P_U_CI_SELA__OFFSET, 0x00000000 + 3296 .set CYFLD_UDB_P_U_CI_SELA__SIZE, 0x00000002 + 3297 .set CYVAL_UDB_P_U_CI_SELA_DEFAULT, 0x00000000 + 3298 .set CYVAL_UDB_P_U_CI_SELA_REGISTERED, 0x00000001 + 3299 .set CYVAL_UDB_P_U_CI_SELA_ROUTE, 0x00000002 + 3300 .set CYVAL_UDB_P_U_CI_SELA_CHAIN, 0x00000003 + 3301 .set CYFLD_UDB_P_U_CI_SELB__OFFSET, 0x00000002 + 3302 .set CYFLD_UDB_P_U_CI_SELB__SIZE, 0x00000002 + 3303 .set CYVAL_UDB_P_U_CI_SELB_DEFAULT, 0x00000000 + 3304 .set CYVAL_UDB_P_U_CI_SELB_REGISTERED, 0x00000001 + 3305 .set CYVAL_UDB_P_U_CI_SELB_ROUTE, 0x00000002 + 3306 .set CYVAL_UDB_P_U_CI_SELB_CHAIN, 0x00000003 + 3307 .set CYFLD_UDB_P_U_CMP_SELA__OFFSET, 0x00000004 + 3308 .set CYFLD_UDB_P_U_CMP_SELA__SIZE, 0x00000002 + 3309 .set CYVAL_UDB_P_U_CMP_SELA_A1_D1, 0x00000000 + 3310 .set CYVAL_UDB_P_U_CMP_SELA_A1_A0, 0x00000001 + 3311 .set CYVAL_UDB_P_U_CMP_SELA_A0_D1, 0x00000002 + 3312 .set CYVAL_UDB_P_U_CMP_SELA_A0_A0, 0x00000003 + 3313 .set CYFLD_UDB_P_U_CMP_SELB__OFFSET, 0x00000006 + 3314 .set CYFLD_UDB_P_U_CMP_SELB__SIZE, 0x00000002 + 3315 .set CYVAL_UDB_P_U_CMP_SELB_A1_D1, 0x00000000 + 3316 .set CYVAL_UDB_P_U_CMP_SELB_A1_A0, 0x00000001 + 3317 .set CYVAL_UDB_P_U_CMP_SELB_A0_D1, 0x00000002 + 3318 .set CYVAL_UDB_P_U_CMP_SELB_A0_A0, 0x00000003 + 3319 .set CYREG_UDB_P0_U0_CFG14, 0x400f304e + 3320 .set CYFLD_UDB_P_U_CHAIN0__OFFSET, 0x00000000 + 3321 .set CYFLD_UDB_P_U_CHAIN0__SIZE, 0x00000001 + 3322 .set CYVAL_UDB_P_U_CHAIN0_DISABLE, 0x00000000 + 3323 .set CYVAL_UDB_P_U_CHAIN0_ENABLE, 0x00000001 + 3324 .set CYFLD_UDB_P_U_CHAIN1__OFFSET, 0x00000001 + 3325 .set CYFLD_UDB_P_U_CHAIN1__SIZE, 0x00000001 + 3326 .set CYVAL_UDB_P_U_CHAIN1_DISABLE, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 60 + + + 3327 .set CYVAL_UDB_P_U_CHAIN1_ENABLE, 0x00000001 + 3328 .set CYFLD_UDB_P_U_CHAIN_FB__OFFSET, 0x00000002 + 3329 .set CYFLD_UDB_P_U_CHAIN_FB__SIZE, 0x00000001 + 3330 .set CYVAL_UDB_P_U_CHAIN_FB_DISABLE, 0x00000000 + 3331 .set CYVAL_UDB_P_U_CHAIN_FB_ENABLE, 0x00000001 + 3332 .set CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET, 0x00000003 + 3333 .set CYFLD_UDB_P_U_CHAIN_CMSB__SIZE, 0x00000001 + 3334 .set CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE, 0x00000000 + 3335 .set CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE, 0x00000001 + 3336 .set CYFLD_UDB_P_U_MSB_SEL__OFFSET, 0x00000004 + 3337 .set CYFLD_UDB_P_U_MSB_SEL__SIZE, 0x00000003 + 3338 .set CYVAL_UDB_P_U_MSB_SEL_BIT0, 0x00000000 + 3339 .set CYVAL_UDB_P_U_MSB_SEL_BIT1, 0x00000001 + 3340 .set CYVAL_UDB_P_U_MSB_SEL_BIT2, 0x00000002 + 3341 .set CYVAL_UDB_P_U_MSB_SEL_BIT3, 0x00000003 + 3342 .set CYVAL_UDB_P_U_MSB_SEL_BIT4, 0x00000004 + 3343 .set CYVAL_UDB_P_U_MSB_SEL_BIT5, 0x00000005 + 3344 .set CYVAL_UDB_P_U_MSB_SEL_BIT6, 0x00000006 + 3345 .set CYVAL_UDB_P_U_MSB_SEL_BIT7, 0x00000007 + 3346 .set CYFLD_UDB_P_U_MSB_EN__OFFSET, 0x00000007 + 3347 .set CYFLD_UDB_P_U_MSB_EN__SIZE, 0x00000001 + 3348 .set CYVAL_UDB_P_U_MSB_EN_DISABLE, 0x00000000 + 3349 .set CYVAL_UDB_P_U_MSB_EN_ENABLE, 0x00000001 + 3350 .set CYREG_UDB_P0_U0_CFG15, 0x400f304f + 3351 .set CYFLD_UDB_P_U_F0_INSEL__OFFSET, 0x00000000 + 3352 .set CYFLD_UDB_P_U_F0_INSEL__SIZE, 0x00000002 + 3353 .set CYVAL_UDB_P_U_F0_INSEL_INPUT, 0x00000000 + 3354 .set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0, 0x00000001 + 3355 .set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1, 0x00000002 + 3356 .set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU, 0x00000003 + 3357 .set CYFLD_UDB_P_U_F1_INSEL__OFFSET, 0x00000002 + 3358 .set CYFLD_UDB_P_U_F1_INSEL__SIZE, 0x00000002 + 3359 .set CYVAL_UDB_P_U_F1_INSEL_INPUT, 0x00000000 + 3360 .set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0, 0x00000001 + 3361 .set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1, 0x00000002 + 3362 .set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU, 0x00000003 + 3363 .set CYFLD_UDB_P_U_MSB_SI__OFFSET, 0x00000004 + 3364 .set CYFLD_UDB_P_U_MSB_SI__SIZE, 0x00000001 + 3365 .set CYVAL_UDB_P_U_MSB_SI_DEFAULT, 0x00000000 + 3366 .set CYVAL_UDB_P_U_MSB_SI_MSB, 0x00000001 + 3367 .set CYFLD_UDB_P_U_PI_DYN__OFFSET, 0x00000005 + 3368 .set CYFLD_UDB_P_U_PI_DYN__SIZE, 0x00000001 + 3369 .set CYVAL_UDB_P_U_PI_DYN_DISABLE, 0x00000000 + 3370 .set CYVAL_UDB_P_U_PI_DYN_ENABLE, 0x00000001 + 3371 .set CYFLD_UDB_P_U_SHIFT_SEL__OFFSET, 0x00000006 + 3372 .set CYFLD_UDB_P_U_SHIFT_SEL__SIZE, 0x00000001 + 3373 .set CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB, 0x00000000 + 3374 .set CYVAL_UDB_P_U_SHIFT_SEL_SOR, 0x00000001 + 3375 .set CYFLD_UDB_P_U_PI_SEL__OFFSET, 0x00000007 + 3376 .set CYFLD_UDB_P_U_PI_SEL__SIZE, 0x00000001 + 3377 .set CYVAL_UDB_P_U_PI_SEL_NORMAL, 0x00000000 + 3378 .set CYVAL_UDB_P_U_PI_SEL_PARALLEL, 0x00000001 + 3379 .set CYREG_UDB_P0_U0_CFG16, 0x400f3050 + 3380 .set CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET, 0x00000000 + 3381 .set CYFLD_UDB_P_U_WRK16_CONCAT__SIZE, 0x00000001 + 3382 .set CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT, 0x00000000 + 3383 .set CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 61 + + + 3384 .set CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET, 0x00000001 + 3385 .set CYFLD_UDB_P_U_EXT_CRCPRS__SIZE, 0x00000001 + 3386 .set CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL, 0x00000000 + 3387 .set CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL, 0x00000001 + 3388 .set CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET, 0x00000002 + 3389 .set CYFLD_UDB_P_U_FIFO_ASYNC__SIZE, 0x00000001 + 3390 .set CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE, 0x00000000 + 3391 .set CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE, 0x00000001 + 3392 .set CYFLD_UDB_P_U_FIFO_EDGE__OFFSET, 0x00000003 + 3393 .set CYFLD_UDB_P_U_FIFO_EDGE__SIZE, 0x00000001 + 3394 .set CYVAL_UDB_P_U_FIFO_EDGE_LEVEL, 0x00000000 + 3395 .set CYVAL_UDB_P_U_FIFO_EDGE_EDGE, 0x00000001 + 3396 .set CYFLD_UDB_P_U_FIFO_CAP__OFFSET, 0x00000004 + 3397 .set CYFLD_UDB_P_U_FIFO_CAP__SIZE, 0x00000001 + 3398 .set CYVAL_UDB_P_U_FIFO_CAP_DISABLE, 0x00000000 + 3399 .set CYVAL_UDB_P_U_FIFO_CAP_ENABLE, 0x00000001 + 3400 .set CYFLD_UDB_P_U_FIFO_FAST__OFFSET, 0x00000005 + 3401 .set CYFLD_UDB_P_U_FIFO_FAST__SIZE, 0x00000001 + 3402 .set CYVAL_UDB_P_U_FIFO_FAST_DISABLE, 0x00000000 + 3403 .set CYVAL_UDB_P_U_FIFO_FAST_ENABLE, 0x00000001 + 3404 .set CYFLD_UDB_P_U_F0_CK_INV__OFFSET, 0x00000006 + 3405 .set CYFLD_UDB_P_U_F0_CK_INV__SIZE, 0x00000001 + 3406 .set CYVAL_UDB_P_U_F0_CK_INV_NORMAL, 0x00000000 + 3407 .set CYVAL_UDB_P_U_F0_CK_INV_INVERT, 0x00000001 + 3408 .set CYFLD_UDB_P_U_F1_CK_INV__OFFSET, 0x00000007 + 3409 .set CYFLD_UDB_P_U_F1_CK_INV__SIZE, 0x00000001 + 3410 .set CYVAL_UDB_P_U_F1_CK_INV_NORMAL, 0x00000000 + 3411 .set CYVAL_UDB_P_U_F1_CK_INV_INVERT, 0x00000001 + 3412 .set CYREG_UDB_P0_U0_CFG17, 0x400f3051 + 3413 .set CYFLD_UDB_P_U_F0_DYN__OFFSET, 0x00000000 + 3414 .set CYFLD_UDB_P_U_F0_DYN__SIZE, 0x00000001 + 3415 .set CYVAL_UDB_P_U_F0_DYN_STATIC, 0x00000000 + 3416 .set CYVAL_UDB_P_U_F0_DYN_DYNAMIC, 0x00000001 + 3417 .set CYFLD_UDB_P_U_F1_DYN__OFFSET, 0x00000001 + 3418 .set CYFLD_UDB_P_U_F1_DYN__SIZE, 0x00000001 + 3419 .set CYVAL_UDB_P_U_F1_DYN_STATIC, 0x00000000 + 3420 .set CYVAL_UDB_P_U_F1_DYN_DYNAMIC, 0x00000001 + 3421 .set CYFLD_UDB_P_U_NC2__OFFSET, 0x00000002 + 3422 .set CYFLD_UDB_P_U_NC2__SIZE, 0x00000001 + 3423 .set CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET, 0x00000004 + 3424 .set CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE, 0x00000001 + 3425 .set CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE, 0x00000000 + 3426 .set CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE, 0x00000001 + 3427 .set CYREG_UDB_P0_U0_CFG18, 0x400f3052 + 3428 .set CYFLD_UDB_P_U_CTL_MD0__OFFSET, 0x00000000 + 3429 .set CYFLD_UDB_P_U_CTL_MD0__SIZE, 0x00000008 + 3430 .set CYVAL_UDB_P_U_CTL_MD0_DIRECT, 0x00000000 + 3431 .set CYVAL_UDB_P_U_CTL_MD0_SYNC, 0x00000001 + 3432 .set CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC, 0x00000002 + 3433 .set CYVAL_UDB_P_U_CTL_MD0_PULSE, 0x00000003 + 3434 .set CYREG_UDB_P0_U0_CFG19, 0x400f3053 + 3435 .set CYFLD_UDB_P_U_CTL_MD1__OFFSET, 0x00000000 + 3436 .set CYFLD_UDB_P_U_CTL_MD1__SIZE, 0x00000008 + 3437 .set CYVAL_UDB_P_U_CTL_MD1_DIRECT, 0x00000000 + 3438 .set CYVAL_UDB_P_U_CTL_MD1_SYNC, 0x00000001 + 3439 .set CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC, 0x00000002 + 3440 .set CYVAL_UDB_P_U_CTL_MD1_PULSE, 0x00000003 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 62 + + + 3441 .set CYREG_UDB_P0_U0_CFG20, 0x400f3054 + 3442 .set CYFLD_UDB_P_U_STAT_MD__OFFSET, 0x00000000 + 3443 .set CYFLD_UDB_P_U_STAT_MD__SIZE, 0x00000008 + 3444 .set CYREG_UDB_P0_U0_CFG21, 0x400f3055 + 3445 .set CYFLD_UDB_P_U_NC0__OFFSET, 0x00000000 + 3446 .set CYFLD_UDB_P_U_NC0__SIZE, 0x00000001 + 3447 .set CYREG_UDB_P0_U0_CFG22, 0x400f3056 + 3448 .set CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET, 0x00000000 + 3449 .set CYFLD_UDB_P_U_SC_OUT_CTL__SIZE, 0x00000002 + 3450 .set CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL, 0x00000000 + 3451 .set CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL, 0x00000001 + 3452 .set CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER, 0x00000002 + 3453 .set CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED, 0x00000003 + 3454 .set CYFLD_UDB_P_U_SC_INT_MD__OFFSET, 0x00000002 + 3455 .set CYFLD_UDB_P_U_SC_INT_MD__SIZE, 0x00000001 + 3456 .set CYVAL_UDB_P_U_SC_INT_MD_NORMAL, 0x00000000 + 3457 .set CYVAL_UDB_P_U_SC_INT_MD_INT_MODE, 0x00000001 + 3458 .set CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET, 0x00000003 + 3459 .set CYFLD_UDB_P_U_SC_SYNC_MD__SIZE, 0x00000001 + 3460 .set CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL, 0x00000000 + 3461 .set CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE, 0x00000001 + 3462 .set CYFLD_UDB_P_U_SC_EXT_RES__OFFSET, 0x00000004 + 3463 .set CYFLD_UDB_P_U_SC_EXT_RES__SIZE, 0x00000001 + 3464 .set CYVAL_UDB_P_U_SC_EXT_RES_DISABLED, 0x00000000 + 3465 .set CYVAL_UDB_P_U_SC_EXT_RES_ENABLED, 0x00000001 + 3466 .set CYREG_UDB_P0_U0_CFG23, 0x400f3057 + 3467 .set CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET, 0x00000000 + 3468 .set CYFLD_UDB_P_U_CNT_LD_SEL__SIZE, 0x00000002 + 3469 .set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0, 0x00000000 + 3470 .set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1, 0x00000001 + 3471 .set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2, 0x00000002 + 3472 .set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3, 0x00000003 + 3473 .set CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET, 0x00000002 + 3474 .set CYFLD_UDB_P_U_CNT_EN_SEL__SIZE, 0x00000002 + 3475 .set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4, 0x00000000 + 3476 .set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5, 0x00000001 + 3477 .set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6, 0x00000002 + 3478 .set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO, 0x00000003 + 3479 .set CYFLD_UDB_P_U_ROUTE_LD__OFFSET, 0x00000004 + 3480 .set CYFLD_UDB_P_U_ROUTE_LD__SIZE, 0x00000001 + 3481 .set CYVAL_UDB_P_U_ROUTE_LD_DISABLE, 0x00000000 + 3482 .set CYVAL_UDB_P_U_ROUTE_LD_ROUTED, 0x00000001 + 3483 .set CYFLD_UDB_P_U_ROUTE_EN__OFFSET, 0x00000005 + 3484 .set CYFLD_UDB_P_U_ROUTE_EN__SIZE, 0x00000001 + 3485 .set CYVAL_UDB_P_U_ROUTE_EN_DISABLE, 0x00000000 + 3486 .set CYVAL_UDB_P_U_ROUTE_EN_ROUTED, 0x00000001 + 3487 .set CYFLD_UDB_P_U_ALT_CNT__OFFSET, 0x00000006 + 3488 .set CYFLD_UDB_P_U_ALT_CNT__SIZE, 0x00000001 + 3489 .set CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE, 0x00000000 + 3490 .set CYVAL_UDB_P_U_ALT_CNT_ALT_MODE, 0x00000001 + 3491 .set CYREG_UDB_P0_U0_CFG24, 0x400f3058 + 3492 .set CYFLD_UDB_P_U_RC_EN_SEL__OFFSET, 0x00000000 + 3493 .set CYFLD_UDB_P_U_RC_EN_SEL__SIZE, 0x00000002 + 3494 .set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0, 0x00000000 + 3495 .set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1, 0x00000001 + 3496 .set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2, 0x00000002 + 3497 .set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3, 0x00000003 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 63 + + + 3498 .set CYFLD_UDB_P_U_RC_EN_MODE__OFFSET, 0x00000002 + 3499 .set CYFLD_UDB_P_U_RC_EN_MODE__SIZE, 0x00000002 + 3500 .set CYVAL_UDB_P_U_RC_EN_MODE_OFF, 0x00000000 + 3501 .set CYVAL_UDB_P_U_RC_EN_MODE_ON, 0x00000001 + 3502 .set CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE, 0x00000002 + 3503 .set CYVAL_UDB_P_U_RC_EN_MODE_LEVEL, 0x00000003 + 3504 .set CYFLD_UDB_P_U_RC_EN_INV__OFFSET, 0x00000004 + 3505 .set CYFLD_UDB_P_U_RC_EN_INV__SIZE, 0x00000001 + 3506 .set CYVAL_UDB_P_U_RC_EN_INV_NOINV, 0x00000000 + 3507 .set CYVAL_UDB_P_U_RC_EN_INV_INVERT, 0x00000001 + 3508 .set CYFLD_UDB_P_U_RC_INV__OFFSET, 0x00000005 + 3509 .set CYFLD_UDB_P_U_RC_INV__SIZE, 0x00000001 + 3510 .set CYVAL_UDB_P_U_RC_INV_NOINV, 0x00000000 + 3511 .set CYVAL_UDB_P_U_RC_INV_INVERT, 0x00000001 + 3512 .set CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET, 0x00000006 + 3513 .set CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE, 0x00000001 + 3514 .set CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET, 0x00000007 + 3515 .set CYFLD_UDB_P_U_RC_RES_SEL1__SIZE, 0x00000001 + 3516 .set CYREG_UDB_P0_U0_CFG25, 0x400f3059 + 3517 .set CYREG_UDB_P0_U0_CFG26, 0x400f305a + 3518 .set CYREG_UDB_P0_U0_CFG27, 0x400f305b + 3519 .set CYREG_UDB_P0_U0_CFG28, 0x400f305c + 3520 .set CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET, 0x00000000 + 3521 .set CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE, 0x00000004 + 3522 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0, 0x00000000 + 3523 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1, 0x00000001 + 3524 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2, 0x00000002 + 3525 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3, 0x00000003 + 3526 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4, 0x00000004 + 3527 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5, 0x00000005 + 3528 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6, 0x00000006 + 3529 .set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7, 0x00000007 + 3530 .set CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK, 0x00000008 + 3531 .set CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK, 0x00000009 + 3532 .set CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET, 0x00000004 + 3533 .set CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE, 0x00000004 + 3534 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0, 0x00000000 + 3535 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1, 0x00000001 + 3536 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2, 0x00000002 + 3537 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3, 0x00000003 + 3538 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4, 0x00000004 + 3539 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5, 0x00000005 + 3540 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6, 0x00000006 + 3541 .set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7, 0x00000007 + 3542 .set CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK, 0x00000008 + 3543 .set CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK, 0x00000009 + 3544 .set CYREG_UDB_P0_U0_CFG29, 0x400f305d + 3545 .set CYFLD_UDB_P_U_DP_CK_SEL__OFFSET, 0x00000000 + 3546 .set CYFLD_UDB_P_U_DP_CK_SEL__SIZE, 0x00000004 + 3547 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK0, 0x00000000 + 3548 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK1, 0x00000001 + 3549 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK2, 0x00000002 + 3550 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK3, 0x00000003 + 3551 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK4, 0x00000004 + 3552 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK5, 0x00000005 + 3553 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK6, 0x00000006 + 3554 .set CYVAL_UDB_P_U_DP_CK_SEL_GCLK7, 0x00000007 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 64 + + + 3555 .set CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK, 0x00000008 + 3556 .set CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK, 0x00000009 + 3557 .set CYFLD_UDB_P_U_SC_CK_SEL__OFFSET, 0x00000004 + 3558 .set CYFLD_UDB_P_U_SC_CK_SEL__SIZE, 0x00000004 + 3559 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK0, 0x00000000 + 3560 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK1, 0x00000001 + 3561 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK2, 0x00000002 + 3562 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK3, 0x00000003 + 3563 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK4, 0x00000004 + 3564 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK5, 0x00000005 + 3565 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK6, 0x00000006 + 3566 .set CYVAL_UDB_P_U_SC_CK_SEL_GCLK7, 0x00000007 + 3567 .set CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK, 0x00000008 + 3568 .set CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK, 0x00000009 + 3569 .set CYREG_UDB_P0_U0_CFG30, 0x400f305e + 3570 .set CYFLD_UDB_P_U_RES_SEL__OFFSET, 0x00000000 + 3571 .set CYFLD_UDB_P_U_RES_SEL__SIZE, 0x00000002 + 3572 .set CYVAL_UDB_P_U_RES_SEL_RC_IN0, 0x00000000 + 3573 .set CYVAL_UDB_P_U_RES_SEL_RC_IN1, 0x00000001 + 3574 .set CYVAL_UDB_P_U_RES_SEL_RC_IN2, 0x00000002 + 3575 .set CYVAL_UDB_P_U_RES_SEL_RC_IN3, 0x00000003 + 3576 .set CYFLD_UDB_P_U_RES_POL__OFFSET, 0x00000002 + 3577 .set CYFLD_UDB_P_U_RES_POL__SIZE, 0x00000001 + 3578 .set CYVAL_UDB_P_U_RES_POL_NEGATED, 0x00000000 + 3579 .set CYVAL_UDB_P_U_RES_POL_ASSERTED, 0x00000001 + 3580 .set CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET, 0x00000003 + 3581 .set CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE, 0x00000001 + 3582 .set CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE, 0x00000000 + 3583 .set CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE, 0x00000001 + 3584 .set CYFLD_UDB_P_U_GUDB_WR__OFFSET, 0x00000004 + 3585 .set CYFLD_UDB_P_U_GUDB_WR__SIZE, 0x00000001 + 3586 .set CYVAL_UDB_P_U_GUDB_WR_DISABLE, 0x00000000 + 3587 .set CYVAL_UDB_P_U_GUDB_WR_ENABLE, 0x00000001 + 3588 .set CYFLD_UDB_P_U_DP_RES_POL__OFFSET, 0x00000006 + 3589 .set CYFLD_UDB_P_U_DP_RES_POL__SIZE, 0x00000001 + 3590 .set CYVAL_UDB_P_U_DP_RES_POL_NOINV, 0x00000000 + 3591 .set CYVAL_UDB_P_U_DP_RES_POL_INVERT, 0x00000001 + 3592 .set CYFLD_UDB_P_U_SC_RES_POL__OFFSET, 0x00000007 + 3593 .set CYFLD_UDB_P_U_SC_RES_POL__SIZE, 0x00000001 + 3594 .set CYVAL_UDB_P_U_SC_RES_POL_NOINV, 0x00000000 + 3595 .set CYVAL_UDB_P_U_SC_RES_POL_INVERT, 0x00000001 + 3596 .set CYREG_UDB_P0_U0_CFG31, 0x400f305f + 3597 .set CYFLD_UDB_P_U_ALT_RES__OFFSET, 0x00000000 + 3598 .set CYFLD_UDB_P_U_ALT_RES__SIZE, 0x00000001 + 3599 .set CYVAL_UDB_P_U_ALT_RES_COMPATIBLE, 0x00000000 + 3600 .set CYVAL_UDB_P_U_ALT_RES_ALTERNATE, 0x00000001 + 3601 .set CYFLD_UDB_P_U_EXT_SYNC__OFFSET, 0x00000001 + 3602 .set CYFLD_UDB_P_U_EXT_SYNC__SIZE, 0x00000001 + 3603 .set CYVAL_UDB_P_U_EXT_SYNC_DISABLE, 0x00000000 + 3604 .set CYVAL_UDB_P_U_EXT_SYNC_ENABLE, 0x00000001 + 3605 .set CYFLD_UDB_P_U_EN_RES_STAT__OFFSET, 0x00000002 + 3606 .set CYFLD_UDB_P_U_EN_RES_STAT__SIZE, 0x00000001 + 3607 .set CYVAL_UDB_P_U_EN_RES_STAT_NEGATED, 0x00000000 + 3608 .set CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED, 0x00000001 + 3609 .set CYFLD_UDB_P_U_EN_RES_DP__OFFSET, 0x00000003 + 3610 .set CYFLD_UDB_P_U_EN_RES_DP__SIZE, 0x00000001 + 3611 .set CYVAL_UDB_P_U_EN_RES_DP_DISABLE, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 65 + + + 3612 .set CYVAL_UDB_P_U_EN_RES_DP_ENABLE, 0x00000001 + 3613 .set CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET, 0x00000004 + 3614 .set CYFLD_UDB_P_U_EXT_CK_SEL__SIZE, 0x00000002 + 3615 .set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0, 0x00000000 + 3616 .set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1, 0x00000001 + 3617 .set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2, 0x00000002 + 3618 .set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3, 0x00000003 + 3619 .set CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET, 0x00000006 + 3620 .set CYFLD_UDB_P_U_PLD0_RES_POL__SIZE, 0x00000001 + 3621 .set CYVAL_UDB_P_U_PLD0_RES_POL_NOINV, 0x00000000 + 3622 .set CYVAL_UDB_P_U_PLD0_RES_POL_INVERT, 0x00000001 + 3623 .set CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET, 0x00000007 + 3624 .set CYFLD_UDB_P_U_PLD1_RES_POL__SIZE, 0x00000001 + 3625 .set CYVAL_UDB_P_U_PLD1_RES_POL_NOINV, 0x00000000 + 3626 .set CYVAL_UDB_P_U_PLD1_RES_POL_INVERT, 0x00000001 + 3627 .set CYREG_UDB_P0_U0_DCFG0, 0x400f3060 + 3628 .set CYFLD_UDB_P_U_CMP_SEL__OFFSET, 0x00000000 + 3629 .set CYFLD_UDB_P_U_CMP_SEL__SIZE, 0x00000001 + 3630 .set CYVAL_UDB_P_U_CMP_SEL_CFG_A, 0x00000000 + 3631 .set CYVAL_UDB_P_U_CMP_SEL_CFG_B, 0x00000001 + 3632 .set CYFLD_UDB_P_U_SI_SEL__OFFSET, 0x00000001 + 3633 .set CYFLD_UDB_P_U_SI_SEL__SIZE, 0x00000001 + 3634 .set CYVAL_UDB_P_U_SI_SEL_CFG_A, 0x00000000 + 3635 .set CYVAL_UDB_P_U_SI_SEL_CFG_B, 0x00000001 + 3636 .set CYFLD_UDB_P_U_CI_SEL__OFFSET, 0x00000002 + 3637 .set CYFLD_UDB_P_U_CI_SEL__SIZE, 0x00000001 + 3638 .set CYVAL_UDB_P_U_CI_SEL_CFG_A, 0x00000000 + 3639 .set CYVAL_UDB_P_U_CI_SEL_CFG_B, 0x00000001 + 3640 .set CYFLD_UDB_P_U_CFB_EN__OFFSET, 0x00000003 + 3641 .set CYFLD_UDB_P_U_CFB_EN__SIZE, 0x00000001 + 3642 .set CYVAL_UDB_P_U_CFB_EN_DISABLE, 0x00000000 + 3643 .set CYVAL_UDB_P_U_CFB_EN_ENABLE, 0x00000001 + 3644 .set CYFLD_UDB_P_U_A1_WR_SRC__OFFSET, 0x00000004 + 3645 .set CYFLD_UDB_P_U_A1_WR_SRC__SIZE, 0x00000002 + 3646 .set CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE, 0x00000000 + 3647 .set CYVAL_UDB_P_U_A1_WR_SRC_ALU, 0x00000001 + 3648 .set CYVAL_UDB_P_U_A1_WR_SRC_D1, 0x00000002 + 3649 .set CYVAL_UDB_P_U_A1_WR_SRC_F1, 0x00000003 + 3650 .set CYFLD_UDB_P_U_A0_WR_SRC__OFFSET, 0x00000006 + 3651 .set CYFLD_UDB_P_U_A0_WR_SRC__SIZE, 0x00000002 + 3652 .set CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE, 0x00000000 + 3653 .set CYVAL_UDB_P_U_A0_WR_SRC_ALU, 0x00000001 + 3654 .set CYVAL_UDB_P_U_A0_WR_SRC_D0, 0x00000002 + 3655 .set CYVAL_UDB_P_U_A0_WR_SRC_F0, 0x00000003 + 3656 .set CYFLD_UDB_P_U_SHIFT__OFFSET, 0x00000008 + 3657 .set CYFLD_UDB_P_U_SHIFT__SIZE, 0x00000002 + 3658 .set CYVAL_UDB_P_U_SHIFT_NOSHIFT, 0x00000000 + 3659 .set CYVAL_UDB_P_U_SHIFT_LEFT, 0x00000001 + 3660 .set CYVAL_UDB_P_U_SHIFT_RIGHT, 0x00000002 + 3661 .set CYVAL_UDB_P_U_SHIFT_SWAP, 0x00000003 + 3662 .set CYFLD_UDB_P_U_SRC_B__OFFSET, 0x0000000a + 3663 .set CYFLD_UDB_P_U_SRC_B__SIZE, 0x00000002 + 3664 .set CYVAL_UDB_P_U_SRC_B_D0, 0x00000000 + 3665 .set CYVAL_UDB_P_U_SRC_B_D1, 0x00000001 + 3666 .set CYVAL_UDB_P_U_SRC_B_A0, 0x00000002 + 3667 .set CYVAL_UDB_P_U_SRC_B_A1, 0x00000003 + 3668 .set CYFLD_UDB_P_U_SRC_A__OFFSET, 0x0000000c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 66 + + + 3669 .set CYFLD_UDB_P_U_SRC_A__SIZE, 0x00000001 + 3670 .set CYVAL_UDB_P_U_SRC_A_A0, 0x00000000 + 3671 .set CYVAL_UDB_P_U_SRC_A_A1, 0x00000001 + 3672 .set CYFLD_UDB_P_U_FUNC__OFFSET, 0x0000000d + 3673 .set CYFLD_UDB_P_U_FUNC__SIZE, 0x00000003 + 3674 .set CYVAL_UDB_P_U_FUNC_PASS, 0x00000000 + 3675 .set CYVAL_UDB_P_U_FUNC_INC_A, 0x00000001 + 3676 .set CYVAL_UDB_P_U_FUNC_DEC_A, 0x00000002 + 3677 .set CYVAL_UDB_P_U_FUNC_ADD, 0x00000003 + 3678 .set CYVAL_UDB_P_U_FUNC_SUB, 0x00000004 + 3679 .set CYVAL_UDB_P_U_FUNC_XOR, 0x00000005 + 3680 .set CYVAL_UDB_P_U_FUNC_AND, 0x00000006 + 3681 .set CYVAL_UDB_P_U_FUNC_OR, 0x00000007 + 3682 .set CYREG_UDB_P0_U0_DCFG1, 0x400f3062 + 3683 .set CYREG_UDB_P0_U0_DCFG2, 0x400f3064 + 3684 .set CYREG_UDB_P0_U0_DCFG3, 0x400f3066 + 3685 .set CYREG_UDB_P0_U0_DCFG4, 0x400f3068 + 3686 .set CYREG_UDB_P0_U0_DCFG5, 0x400f306a + 3687 .set CYREG_UDB_P0_U0_DCFG6, 0x400f306c + 3688 .set CYREG_UDB_P0_U0_DCFG7, 0x400f306e + 3689 .set CYDEV_UDB_P0_U1_BASE, 0x400f3080 + 3690 .set CYDEV_UDB_P0_U1_SIZE, 0x00000080 + 3691 .set CYREG_UDB_P0_U1_PLD_IT0, 0x400f3080 + 3692 .set CYREG_UDB_P0_U1_PLD_IT1, 0x400f3084 + 3693 .set CYREG_UDB_P0_U1_PLD_IT2, 0x400f3088 + 3694 .set CYREG_UDB_P0_U1_PLD_IT3, 0x400f308c + 3695 .set CYREG_UDB_P0_U1_PLD_IT4, 0x400f3090 + 3696 .set CYREG_UDB_P0_U1_PLD_IT5, 0x400f3094 + 3697 .set CYREG_UDB_P0_U1_PLD_IT6, 0x400f3098 + 3698 .set CYREG_UDB_P0_U1_PLD_IT7, 0x400f309c + 3699 .set CYREG_UDB_P0_U1_PLD_IT8, 0x400f30a0 + 3700 .set CYREG_UDB_P0_U1_PLD_IT9, 0x400f30a4 + 3701 .set CYREG_UDB_P0_U1_PLD_IT10, 0x400f30a8 + 3702 .set CYREG_UDB_P0_U1_PLD_IT11, 0x400f30ac + 3703 .set CYREG_UDB_P0_U1_PLD_ORT0, 0x400f30b0 + 3704 .set CYREG_UDB_P0_U1_PLD_ORT1, 0x400f30b2 + 3705 .set CYREG_UDB_P0_U1_PLD_ORT2, 0x400f30b4 + 3706 .set CYREG_UDB_P0_U1_PLD_ORT3, 0x400f30b6 + 3707 .set CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST, 0x400f30b8 + 3708 .set CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB, 0x400f30ba + 3709 .set CYREG_UDB_P0_U1_PLD_MC_SET_RESET, 0x400f30bc + 3710 .set CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS, 0x400f30be + 3711 .set CYREG_UDB_P0_U1_CFG0, 0x400f30c0 + 3712 .set CYREG_UDB_P0_U1_CFG1, 0x400f30c1 + 3713 .set CYREG_UDB_P0_U1_CFG2, 0x400f30c2 + 3714 .set CYREG_UDB_P0_U1_CFG3, 0x400f30c3 + 3715 .set CYREG_UDB_P0_U1_CFG4, 0x400f30c4 + 3716 .set CYREG_UDB_P0_U1_CFG5, 0x400f30c5 + 3717 .set CYREG_UDB_P0_U1_CFG6, 0x400f30c6 + 3718 .set CYREG_UDB_P0_U1_CFG7, 0x400f30c7 + 3719 .set CYREG_UDB_P0_U1_CFG8, 0x400f30c8 + 3720 .set CYREG_UDB_P0_U1_CFG9, 0x400f30c9 + 3721 .set CYREG_UDB_P0_U1_CFG10, 0x400f30ca + 3722 .set CYREG_UDB_P0_U1_CFG11, 0x400f30cb + 3723 .set CYREG_UDB_P0_U1_CFG12, 0x400f30cc + 3724 .set CYREG_UDB_P0_U1_CFG13, 0x400f30cd + 3725 .set CYREG_UDB_P0_U1_CFG14, 0x400f30ce + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 67 + + + 3726 .set CYREG_UDB_P0_U1_CFG15, 0x400f30cf + 3727 .set CYREG_UDB_P0_U1_CFG16, 0x400f30d0 + 3728 .set CYREG_UDB_P0_U1_CFG17, 0x400f30d1 + 3729 .set CYREG_UDB_P0_U1_CFG18, 0x400f30d2 + 3730 .set CYREG_UDB_P0_U1_CFG19, 0x400f30d3 + 3731 .set CYREG_UDB_P0_U1_CFG20, 0x400f30d4 + 3732 .set CYREG_UDB_P0_U1_CFG21, 0x400f30d5 + 3733 .set CYREG_UDB_P0_U1_CFG22, 0x400f30d6 + 3734 .set CYREG_UDB_P0_U1_CFG23, 0x400f30d7 + 3735 .set CYREG_UDB_P0_U1_CFG24, 0x400f30d8 + 3736 .set CYREG_UDB_P0_U1_CFG25, 0x400f30d9 + 3737 .set CYREG_UDB_P0_U1_CFG26, 0x400f30da + 3738 .set CYREG_UDB_P0_U1_CFG27, 0x400f30db + 3739 .set CYREG_UDB_P0_U1_CFG28, 0x400f30dc + 3740 .set CYREG_UDB_P0_U1_CFG29, 0x400f30dd + 3741 .set CYREG_UDB_P0_U1_CFG30, 0x400f30de + 3742 .set CYREG_UDB_P0_U1_CFG31, 0x400f30df + 3743 .set CYREG_UDB_P0_U1_DCFG0, 0x400f30e0 + 3744 .set CYREG_UDB_P0_U1_DCFG1, 0x400f30e2 + 3745 .set CYREG_UDB_P0_U1_DCFG2, 0x400f30e4 + 3746 .set CYREG_UDB_P0_U1_DCFG3, 0x400f30e6 + 3747 .set CYREG_UDB_P0_U1_DCFG4, 0x400f30e8 + 3748 .set CYREG_UDB_P0_U1_DCFG5, 0x400f30ea + 3749 .set CYREG_UDB_P0_U1_DCFG6, 0x400f30ec + 3750 .set CYREG_UDB_P0_U1_DCFG7, 0x400f30ee + 3751 .set CYDEV_UDB_P0_ROUTE_BASE, 0x400f3100 + 3752 .set CYDEV_UDB_P0_ROUTE_SIZE, 0x00000100 + 3753 .set CYREG_UDB_P0_ROUTE_HC0, 0x400f3100 + 3754 .set CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET, 0x00000000 + 3755 .set CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE, 0x00000008 + 3756 .set CYREG_UDB_P0_ROUTE_HC1, 0x400f3101 + 3757 .set CYREG_UDB_P0_ROUTE_HC2, 0x400f3102 + 3758 .set CYREG_UDB_P0_ROUTE_HC3, 0x400f3103 + 3759 .set CYREG_UDB_P0_ROUTE_HC4, 0x400f3104 + 3760 .set CYREG_UDB_P0_ROUTE_HC5, 0x400f3105 + 3761 .set CYREG_UDB_P0_ROUTE_HC6, 0x400f3106 + 3762 .set CYREG_UDB_P0_ROUTE_HC7, 0x400f3107 + 3763 .set CYREG_UDB_P0_ROUTE_HC8, 0x400f3108 + 3764 .set CYREG_UDB_P0_ROUTE_HC9, 0x400f3109 + 3765 .set CYREG_UDB_P0_ROUTE_HC10, 0x400f310a + 3766 .set CYREG_UDB_P0_ROUTE_HC11, 0x400f310b + 3767 .set CYREG_UDB_P0_ROUTE_HC12, 0x400f310c + 3768 .set CYREG_UDB_P0_ROUTE_HC13, 0x400f310d + 3769 .set CYREG_UDB_P0_ROUTE_HC14, 0x400f310e + 3770 .set CYREG_UDB_P0_ROUTE_HC15, 0x400f310f + 3771 .set CYREG_UDB_P0_ROUTE_HC16, 0x400f3110 + 3772 .set CYREG_UDB_P0_ROUTE_HC17, 0x400f3111 + 3773 .set CYREG_UDB_P0_ROUTE_HC18, 0x400f3112 + 3774 .set CYREG_UDB_P0_ROUTE_HC19, 0x400f3113 + 3775 .set CYREG_UDB_P0_ROUTE_HC20, 0x400f3114 + 3776 .set CYREG_UDB_P0_ROUTE_HC21, 0x400f3115 + 3777 .set CYREG_UDB_P0_ROUTE_HC22, 0x400f3116 + 3778 .set CYREG_UDB_P0_ROUTE_HC23, 0x400f3117 + 3779 .set CYREG_UDB_P0_ROUTE_HC24, 0x400f3118 + 3780 .set CYREG_UDB_P0_ROUTE_HC25, 0x400f3119 + 3781 .set CYREG_UDB_P0_ROUTE_HC26, 0x400f311a + 3782 .set CYREG_UDB_P0_ROUTE_HC27, 0x400f311b + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 68 + + + 3783 .set CYREG_UDB_P0_ROUTE_HC28, 0x400f311c + 3784 .set CYREG_UDB_P0_ROUTE_HC29, 0x400f311d + 3785 .set CYREG_UDB_P0_ROUTE_HC30, 0x400f311e + 3786 .set CYREG_UDB_P0_ROUTE_HC31, 0x400f311f + 3787 .set CYREG_UDB_P0_ROUTE_HC32, 0x400f3120 + 3788 .set CYREG_UDB_P0_ROUTE_HC33, 0x400f3121 + 3789 .set CYREG_UDB_P0_ROUTE_HC34, 0x400f3122 + 3790 .set CYREG_UDB_P0_ROUTE_HC35, 0x400f3123 + 3791 .set CYREG_UDB_P0_ROUTE_HC36, 0x400f3124 + 3792 .set CYREG_UDB_P0_ROUTE_HC37, 0x400f3125 + 3793 .set CYREG_UDB_P0_ROUTE_HC38, 0x400f3126 + 3794 .set CYREG_UDB_P0_ROUTE_HC39, 0x400f3127 + 3795 .set CYREG_UDB_P0_ROUTE_HC40, 0x400f3128 + 3796 .set CYREG_UDB_P0_ROUTE_HC41, 0x400f3129 + 3797 .set CYREG_UDB_P0_ROUTE_HC42, 0x400f312a + 3798 .set CYREG_UDB_P0_ROUTE_HC43, 0x400f312b + 3799 .set CYREG_UDB_P0_ROUTE_HC44, 0x400f312c + 3800 .set CYREG_UDB_P0_ROUTE_HC45, 0x400f312d + 3801 .set CYREG_UDB_P0_ROUTE_HC46, 0x400f312e + 3802 .set CYREG_UDB_P0_ROUTE_HC47, 0x400f312f + 3803 .set CYREG_UDB_P0_ROUTE_HC48, 0x400f3130 + 3804 .set CYREG_UDB_P0_ROUTE_HC49, 0x400f3131 + 3805 .set CYREG_UDB_P0_ROUTE_HC50, 0x400f3132 + 3806 .set CYREG_UDB_P0_ROUTE_HC51, 0x400f3133 + 3807 .set CYREG_UDB_P0_ROUTE_HC52, 0x400f3134 + 3808 .set CYREG_UDB_P0_ROUTE_HC53, 0x400f3135 + 3809 .set CYREG_UDB_P0_ROUTE_HC54, 0x400f3136 + 3810 .set CYREG_UDB_P0_ROUTE_HC55, 0x400f3137 + 3811 .set CYREG_UDB_P0_ROUTE_HC56, 0x400f3138 + 3812 .set CYREG_UDB_P0_ROUTE_HC57, 0x400f3139 + 3813 .set CYREG_UDB_P0_ROUTE_HC58, 0x400f313a + 3814 .set CYREG_UDB_P0_ROUTE_HC59, 0x400f313b + 3815 .set CYREG_UDB_P0_ROUTE_HC60, 0x400f313c + 3816 .set CYREG_UDB_P0_ROUTE_HC61, 0x400f313d + 3817 .set CYREG_UDB_P0_ROUTE_HC62, 0x400f313e + 3818 .set CYREG_UDB_P0_ROUTE_HC63, 0x400f313f + 3819 .set CYREG_UDB_P0_ROUTE_HC64, 0x400f3140 + 3820 .set CYREG_UDB_P0_ROUTE_HC65, 0x400f3141 + 3821 .set CYREG_UDB_P0_ROUTE_HC66, 0x400f3142 + 3822 .set CYREG_UDB_P0_ROUTE_HC67, 0x400f3143 + 3823 .set CYREG_UDB_P0_ROUTE_HC68, 0x400f3144 + 3824 .set CYREG_UDB_P0_ROUTE_HC69, 0x400f3145 + 3825 .set CYREG_UDB_P0_ROUTE_HC70, 0x400f3146 + 3826 .set CYREG_UDB_P0_ROUTE_HC71, 0x400f3147 + 3827 .set CYREG_UDB_P0_ROUTE_HC72, 0x400f3148 + 3828 .set CYREG_UDB_P0_ROUTE_HC73, 0x400f3149 + 3829 .set CYREG_UDB_P0_ROUTE_HC74, 0x400f314a + 3830 .set CYREG_UDB_P0_ROUTE_HC75, 0x400f314b + 3831 .set CYREG_UDB_P0_ROUTE_HC76, 0x400f314c + 3832 .set CYREG_UDB_P0_ROUTE_HC77, 0x400f314d + 3833 .set CYREG_UDB_P0_ROUTE_HC78, 0x400f314e + 3834 .set CYREG_UDB_P0_ROUTE_HC79, 0x400f314f + 3835 .set CYREG_UDB_P0_ROUTE_HC80, 0x400f3150 + 3836 .set CYREG_UDB_P0_ROUTE_HC81, 0x400f3151 + 3837 .set CYREG_UDB_P0_ROUTE_HC82, 0x400f3152 + 3838 .set CYREG_UDB_P0_ROUTE_HC83, 0x400f3153 + 3839 .set CYREG_UDB_P0_ROUTE_HC84, 0x400f3154 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 69 + + + 3840 .set CYREG_UDB_P0_ROUTE_HC85, 0x400f3155 + 3841 .set CYREG_UDB_P0_ROUTE_HC86, 0x400f3156 + 3842 .set CYREG_UDB_P0_ROUTE_HC87, 0x400f3157 + 3843 .set CYREG_UDB_P0_ROUTE_HC88, 0x400f3158 + 3844 .set CYREG_UDB_P0_ROUTE_HC89, 0x400f3159 + 3845 .set CYREG_UDB_P0_ROUTE_HC90, 0x400f315a + 3846 .set CYREG_UDB_P0_ROUTE_HC91, 0x400f315b + 3847 .set CYREG_UDB_P0_ROUTE_HC92, 0x400f315c + 3848 .set CYREG_UDB_P0_ROUTE_HC93, 0x400f315d + 3849 .set CYREG_UDB_P0_ROUTE_HC94, 0x400f315e + 3850 .set CYREG_UDB_P0_ROUTE_HC95, 0x400f315f + 3851 .set CYREG_UDB_P0_ROUTE_HC96, 0x400f3160 + 3852 .set CYREG_UDB_P0_ROUTE_HC97, 0x400f3161 + 3853 .set CYREG_UDB_P0_ROUTE_HC98, 0x400f3162 + 3854 .set CYREG_UDB_P0_ROUTE_HC99, 0x400f3163 + 3855 .set CYREG_UDB_P0_ROUTE_HC100, 0x400f3164 + 3856 .set CYREG_UDB_P0_ROUTE_HC101, 0x400f3165 + 3857 .set CYREG_UDB_P0_ROUTE_HC102, 0x400f3166 + 3858 .set CYREG_UDB_P0_ROUTE_HC103, 0x400f3167 + 3859 .set CYREG_UDB_P0_ROUTE_HC104, 0x400f3168 + 3860 .set CYREG_UDB_P0_ROUTE_HC105, 0x400f3169 + 3861 .set CYREG_UDB_P0_ROUTE_HC106, 0x400f316a + 3862 .set CYREG_UDB_P0_ROUTE_HC107, 0x400f316b + 3863 .set CYREG_UDB_P0_ROUTE_HC108, 0x400f316c + 3864 .set CYREG_UDB_P0_ROUTE_HC109, 0x400f316d + 3865 .set CYREG_UDB_P0_ROUTE_HC110, 0x400f316e + 3866 .set CYREG_UDB_P0_ROUTE_HC111, 0x400f316f + 3867 .set CYREG_UDB_P0_ROUTE_HC112, 0x400f3170 + 3868 .set CYREG_UDB_P0_ROUTE_HC113, 0x400f3171 + 3869 .set CYREG_UDB_P0_ROUTE_HC114, 0x400f3172 + 3870 .set CYREG_UDB_P0_ROUTE_HC115, 0x400f3173 + 3871 .set CYREG_UDB_P0_ROUTE_HC116, 0x400f3174 + 3872 .set CYREG_UDB_P0_ROUTE_HC117, 0x400f3175 + 3873 .set CYREG_UDB_P0_ROUTE_HC118, 0x400f3176 + 3874 .set CYREG_UDB_P0_ROUTE_HC119, 0x400f3177 + 3875 .set CYREG_UDB_P0_ROUTE_HC120, 0x400f3178 + 3876 .set CYREG_UDB_P0_ROUTE_HC121, 0x400f3179 + 3877 .set CYREG_UDB_P0_ROUTE_HC122, 0x400f317a + 3878 .set CYREG_UDB_P0_ROUTE_HC123, 0x400f317b + 3879 .set CYREG_UDB_P0_ROUTE_HC124, 0x400f317c + 3880 .set CYREG_UDB_P0_ROUTE_HC125, 0x400f317d + 3881 .set CYREG_UDB_P0_ROUTE_HC126, 0x400f317e + 3882 .set CYREG_UDB_P0_ROUTE_HC127, 0x400f317f + 3883 .set CYREG_UDB_P0_ROUTE_HV_L0, 0x400f3180 + 3884 .set CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET, 0x00000000 + 3885 .set CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE, 0x00000008 + 3886 .set CYREG_UDB_P0_ROUTE_HV_L1, 0x400f3181 + 3887 .set CYREG_UDB_P0_ROUTE_HV_L2, 0x400f3182 + 3888 .set CYREG_UDB_P0_ROUTE_HV_L3, 0x400f3183 + 3889 .set CYREG_UDB_P0_ROUTE_HV_L4, 0x400f3184 + 3890 .set CYREG_UDB_P0_ROUTE_HV_L5, 0x400f3185 + 3891 .set CYREG_UDB_P0_ROUTE_HV_L6, 0x400f3186 + 3892 .set CYREG_UDB_P0_ROUTE_HV_L7, 0x400f3187 + 3893 .set CYREG_UDB_P0_ROUTE_HV_L8, 0x400f3188 + 3894 .set CYREG_UDB_P0_ROUTE_HV_L9, 0x400f3189 + 3895 .set CYREG_UDB_P0_ROUTE_HV_L10, 0x400f318a + 3896 .set CYREG_UDB_P0_ROUTE_HV_L11, 0x400f318b + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 70 + + + 3897 .set CYREG_UDB_P0_ROUTE_HV_L12, 0x400f318c + 3898 .set CYREG_UDB_P0_ROUTE_HV_L13, 0x400f318d + 3899 .set CYREG_UDB_P0_ROUTE_HV_L14, 0x400f318e + 3900 .set CYREG_UDB_P0_ROUTE_HV_L15, 0x400f318f + 3901 .set CYREG_UDB_P0_ROUTE_HS0, 0x400f3190 + 3902 .set CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET, 0x00000000 + 3903 .set CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE, 0x00000008 + 3904 .set CYREG_UDB_P0_ROUTE_HS1, 0x400f3191 + 3905 .set CYREG_UDB_P0_ROUTE_HS2, 0x400f3192 + 3906 .set CYREG_UDB_P0_ROUTE_HS3, 0x400f3193 + 3907 .set CYREG_UDB_P0_ROUTE_HS4, 0x400f3194 + 3908 .set CYREG_UDB_P0_ROUTE_HS5, 0x400f3195 + 3909 .set CYREG_UDB_P0_ROUTE_HS6, 0x400f3196 + 3910 .set CYREG_UDB_P0_ROUTE_HS7, 0x400f3197 + 3911 .set CYREG_UDB_P0_ROUTE_HS8, 0x400f3198 + 3912 .set CYREG_UDB_P0_ROUTE_HS9, 0x400f3199 + 3913 .set CYREG_UDB_P0_ROUTE_HS10, 0x400f319a + 3914 .set CYREG_UDB_P0_ROUTE_HS11, 0x400f319b + 3915 .set CYREG_UDB_P0_ROUTE_HS12, 0x400f319c + 3916 .set CYREG_UDB_P0_ROUTE_HS13, 0x400f319d + 3917 .set CYREG_UDB_P0_ROUTE_HS14, 0x400f319e + 3918 .set CYREG_UDB_P0_ROUTE_HS15, 0x400f319f + 3919 .set CYREG_UDB_P0_ROUTE_HS16, 0x400f31a0 + 3920 .set CYREG_UDB_P0_ROUTE_HS17, 0x400f31a1 + 3921 .set CYREG_UDB_P0_ROUTE_HS18, 0x400f31a2 + 3922 .set CYREG_UDB_P0_ROUTE_HS19, 0x400f31a3 + 3923 .set CYREG_UDB_P0_ROUTE_HS20, 0x400f31a4 + 3924 .set CYREG_UDB_P0_ROUTE_HS21, 0x400f31a5 + 3925 .set CYREG_UDB_P0_ROUTE_HS22, 0x400f31a6 + 3926 .set CYREG_UDB_P0_ROUTE_HS23, 0x400f31a7 + 3927 .set CYREG_UDB_P0_ROUTE_HV_R0, 0x400f31a8 + 3928 .set CYREG_UDB_P0_ROUTE_HV_R1, 0x400f31a9 + 3929 .set CYREG_UDB_P0_ROUTE_HV_R2, 0x400f31aa + 3930 .set CYREG_UDB_P0_ROUTE_HV_R3, 0x400f31ab + 3931 .set CYREG_UDB_P0_ROUTE_HV_R4, 0x400f31ac + 3932 .set CYREG_UDB_P0_ROUTE_HV_R5, 0x400f31ad + 3933 .set CYREG_UDB_P0_ROUTE_HV_R6, 0x400f31ae + 3934 .set CYREG_UDB_P0_ROUTE_HV_R7, 0x400f31af + 3935 .set CYREG_UDB_P0_ROUTE_HV_R8, 0x400f31b0 + 3936 .set CYREG_UDB_P0_ROUTE_HV_R9, 0x400f31b1 + 3937 .set CYREG_UDB_P0_ROUTE_HV_R10, 0x400f31b2 + 3938 .set CYREG_UDB_P0_ROUTE_HV_R11, 0x400f31b3 + 3939 .set CYREG_UDB_P0_ROUTE_HV_R12, 0x400f31b4 + 3940 .set CYREG_UDB_P0_ROUTE_HV_R13, 0x400f31b5 + 3941 .set CYREG_UDB_P0_ROUTE_HV_R14, 0x400f31b6 + 3942 .set CYREG_UDB_P0_ROUTE_HV_R15, 0x400f31b7 + 3943 .set CYREG_UDB_P0_ROUTE_PLD0IN0, 0x400f31c0 + 3944 .set CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET, 0x00000000 + 3945 .set CYFLD_UDB_P_ROUTE_PI_TOP__SIZE, 0x00000004 + 3946 .set CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET, 0x00000004 + 3947 .set CYFLD_UDB_P_ROUTE_PI_BOT__SIZE, 0x00000004 + 3948 .set CYREG_UDB_P0_ROUTE_PLD0IN1, 0x400f31c2 + 3949 .set CYREG_UDB_P0_ROUTE_PLD0IN2, 0x400f31c4 + 3950 .set CYREG_UDB_P0_ROUTE_PLD1IN0, 0x400f31ca + 3951 .set CYREG_UDB_P0_ROUTE_PLD1IN1, 0x400f31cc + 3952 .set CYREG_UDB_P0_ROUTE_PLD1IN2, 0x400f31ce + 3953 .set CYREG_UDB_P0_ROUTE_DPIN0, 0x400f31d0 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 71 + + + 3954 .set CYREG_UDB_P0_ROUTE_DPIN1, 0x400f31d2 + 3955 .set CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET, 0x00000002 + 3956 .set CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE, 0x00000002 + 3957 .set CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET, 0x00000004 + 3958 .set CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE, 0x00000002 + 3959 .set CYREG_UDB_P0_ROUTE_SCIN, 0x400f31d6 + 3960 .set CYREG_UDB_P0_ROUTE_SCIOIN, 0x400f31d8 + 3961 .set CYREG_UDB_P0_ROUTE_RCIN, 0x400f31de + 3962 .set CYREG_UDB_P0_ROUTE_VS0, 0x400f31e0 + 3963 .set CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET, 0x00000000 + 3964 .set CYFLD_UDB_P_ROUTE_VS_TOP__SIZE, 0x00000004 + 3965 .set CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET, 0x00000004 + 3966 .set CYFLD_UDB_P_ROUTE_VS_BOT__SIZE, 0x00000004 + 3967 .set CYREG_UDB_P0_ROUTE_VS1, 0x400f31e2 + 3968 .set CYREG_UDB_P0_ROUTE_VS2, 0x400f31e4 + 3969 .set CYREG_UDB_P0_ROUTE_VS3, 0x400f31e6 + 3970 .set CYREG_UDB_P0_ROUTE_VS4, 0x400f31e8 + 3971 .set CYREG_UDB_P0_ROUTE_VS5, 0x400f31ea + 3972 .set CYREG_UDB_P0_ROUTE_VS6, 0x400f31ec + 3973 .set CYREG_UDB_P0_ROUTE_VS7, 0x400f31ee + 3974 .set CYDEV_UDB_P1_BASE, 0x400f3200 + 3975 .set CYDEV_UDB_P1_SIZE, 0x00000200 + 3976 .set CYDEV_UDB_P1_U0_BASE, 0x400f3200 + 3977 .set CYDEV_UDB_P1_U0_SIZE, 0x00000080 + 3978 .set CYREG_UDB_P1_U0_PLD_IT0, 0x400f3200 + 3979 .set CYREG_UDB_P1_U0_PLD_IT1, 0x400f3204 + 3980 .set CYREG_UDB_P1_U0_PLD_IT2, 0x400f3208 + 3981 .set CYREG_UDB_P1_U0_PLD_IT3, 0x400f320c + 3982 .set CYREG_UDB_P1_U0_PLD_IT4, 0x400f3210 + 3983 .set CYREG_UDB_P1_U0_PLD_IT5, 0x400f3214 + 3984 .set CYREG_UDB_P1_U0_PLD_IT6, 0x400f3218 + 3985 .set CYREG_UDB_P1_U0_PLD_IT7, 0x400f321c + 3986 .set CYREG_UDB_P1_U0_PLD_IT8, 0x400f3220 + 3987 .set CYREG_UDB_P1_U0_PLD_IT9, 0x400f3224 + 3988 .set CYREG_UDB_P1_U0_PLD_IT10, 0x400f3228 + 3989 .set CYREG_UDB_P1_U0_PLD_IT11, 0x400f322c + 3990 .set CYREG_UDB_P1_U0_PLD_ORT0, 0x400f3230 + 3991 .set CYREG_UDB_P1_U0_PLD_ORT1, 0x400f3232 + 3992 .set CYREG_UDB_P1_U0_PLD_ORT2, 0x400f3234 + 3993 .set CYREG_UDB_P1_U0_PLD_ORT3, 0x400f3236 + 3994 .set CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST, 0x400f3238 + 3995 .set CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB, 0x400f323a + 3996 .set CYREG_UDB_P1_U0_PLD_MC_SET_RESET, 0x400f323c + 3997 .set CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS, 0x400f323e + 3998 .set CYREG_UDB_P1_U0_CFG0, 0x400f3240 + 3999 .set CYREG_UDB_P1_U0_CFG1, 0x400f3241 + 4000 .set CYREG_UDB_P1_U0_CFG2, 0x400f3242 + 4001 .set CYREG_UDB_P1_U0_CFG3, 0x400f3243 + 4002 .set CYREG_UDB_P1_U0_CFG4, 0x400f3244 + 4003 .set CYREG_UDB_P1_U0_CFG5, 0x400f3245 + 4004 .set CYREG_UDB_P1_U0_CFG6, 0x400f3246 + 4005 .set CYREG_UDB_P1_U0_CFG7, 0x400f3247 + 4006 .set CYREG_UDB_P1_U0_CFG8, 0x400f3248 + 4007 .set CYREG_UDB_P1_U0_CFG9, 0x400f3249 + 4008 .set CYREG_UDB_P1_U0_CFG10, 0x400f324a + 4009 .set CYREG_UDB_P1_U0_CFG11, 0x400f324b + 4010 .set CYREG_UDB_P1_U0_CFG12, 0x400f324c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 72 + + + 4011 .set CYREG_UDB_P1_U0_CFG13, 0x400f324d + 4012 .set CYREG_UDB_P1_U0_CFG14, 0x400f324e + 4013 .set CYREG_UDB_P1_U0_CFG15, 0x400f324f + 4014 .set CYREG_UDB_P1_U0_CFG16, 0x400f3250 + 4015 .set CYREG_UDB_P1_U0_CFG17, 0x400f3251 + 4016 .set CYREG_UDB_P1_U0_CFG18, 0x400f3252 + 4017 .set CYREG_UDB_P1_U0_CFG19, 0x400f3253 + 4018 .set CYREG_UDB_P1_U0_CFG20, 0x400f3254 + 4019 .set CYREG_UDB_P1_U0_CFG21, 0x400f3255 + 4020 .set CYREG_UDB_P1_U0_CFG22, 0x400f3256 + 4021 .set CYREG_UDB_P1_U0_CFG23, 0x400f3257 + 4022 .set CYREG_UDB_P1_U0_CFG24, 0x400f3258 + 4023 .set CYREG_UDB_P1_U0_CFG25, 0x400f3259 + 4024 .set CYREG_UDB_P1_U0_CFG26, 0x400f325a + 4025 .set CYREG_UDB_P1_U0_CFG27, 0x400f325b + 4026 .set CYREG_UDB_P1_U0_CFG28, 0x400f325c + 4027 .set CYREG_UDB_P1_U0_CFG29, 0x400f325d + 4028 .set CYREG_UDB_P1_U0_CFG30, 0x400f325e + 4029 .set CYREG_UDB_P1_U0_CFG31, 0x400f325f + 4030 .set CYREG_UDB_P1_U0_DCFG0, 0x400f3260 + 4031 .set CYREG_UDB_P1_U0_DCFG1, 0x400f3262 + 4032 .set CYREG_UDB_P1_U0_DCFG2, 0x400f3264 + 4033 .set CYREG_UDB_P1_U0_DCFG3, 0x400f3266 + 4034 .set CYREG_UDB_P1_U0_DCFG4, 0x400f3268 + 4035 .set CYREG_UDB_P1_U0_DCFG5, 0x400f326a + 4036 .set CYREG_UDB_P1_U0_DCFG6, 0x400f326c + 4037 .set CYREG_UDB_P1_U0_DCFG7, 0x400f326e + 4038 .set CYDEV_UDB_P1_U1_BASE, 0x400f3280 + 4039 .set CYDEV_UDB_P1_U1_SIZE, 0x00000080 + 4040 .set CYREG_UDB_P1_U1_PLD_IT0, 0x400f3280 + 4041 .set CYREG_UDB_P1_U1_PLD_IT1, 0x400f3284 + 4042 .set CYREG_UDB_P1_U1_PLD_IT2, 0x400f3288 + 4043 .set CYREG_UDB_P1_U1_PLD_IT3, 0x400f328c + 4044 .set CYREG_UDB_P1_U1_PLD_IT4, 0x400f3290 + 4045 .set CYREG_UDB_P1_U1_PLD_IT5, 0x400f3294 + 4046 .set CYREG_UDB_P1_U1_PLD_IT6, 0x400f3298 + 4047 .set CYREG_UDB_P1_U1_PLD_IT7, 0x400f329c + 4048 .set CYREG_UDB_P1_U1_PLD_IT8, 0x400f32a0 + 4049 .set CYREG_UDB_P1_U1_PLD_IT9, 0x400f32a4 + 4050 .set CYREG_UDB_P1_U1_PLD_IT10, 0x400f32a8 + 4051 .set CYREG_UDB_P1_U1_PLD_IT11, 0x400f32ac + 4052 .set CYREG_UDB_P1_U1_PLD_ORT0, 0x400f32b0 + 4053 .set CYREG_UDB_P1_U1_PLD_ORT1, 0x400f32b2 + 4054 .set CYREG_UDB_P1_U1_PLD_ORT2, 0x400f32b4 + 4055 .set CYREG_UDB_P1_U1_PLD_ORT3, 0x400f32b6 + 4056 .set CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST, 0x400f32b8 + 4057 .set CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB, 0x400f32ba + 4058 .set CYREG_UDB_P1_U1_PLD_MC_SET_RESET, 0x400f32bc + 4059 .set CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS, 0x400f32be + 4060 .set CYREG_UDB_P1_U1_CFG0, 0x400f32c0 + 4061 .set CYREG_UDB_P1_U1_CFG1, 0x400f32c1 + 4062 .set CYREG_UDB_P1_U1_CFG2, 0x400f32c2 + 4063 .set CYREG_UDB_P1_U1_CFG3, 0x400f32c3 + 4064 .set CYREG_UDB_P1_U1_CFG4, 0x400f32c4 + 4065 .set CYREG_UDB_P1_U1_CFG5, 0x400f32c5 + 4066 .set CYREG_UDB_P1_U1_CFG6, 0x400f32c6 + 4067 .set CYREG_UDB_P1_U1_CFG7, 0x400f32c7 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 73 + + + 4068 .set CYREG_UDB_P1_U1_CFG8, 0x400f32c8 + 4069 .set CYREG_UDB_P1_U1_CFG9, 0x400f32c9 + 4070 .set CYREG_UDB_P1_U1_CFG10, 0x400f32ca + 4071 .set CYREG_UDB_P1_U1_CFG11, 0x400f32cb + 4072 .set CYREG_UDB_P1_U1_CFG12, 0x400f32cc + 4073 .set CYREG_UDB_P1_U1_CFG13, 0x400f32cd + 4074 .set CYREG_UDB_P1_U1_CFG14, 0x400f32ce + 4075 .set CYREG_UDB_P1_U1_CFG15, 0x400f32cf + 4076 .set CYREG_UDB_P1_U1_CFG16, 0x400f32d0 + 4077 .set CYREG_UDB_P1_U1_CFG17, 0x400f32d1 + 4078 .set CYREG_UDB_P1_U1_CFG18, 0x400f32d2 + 4079 .set CYREG_UDB_P1_U1_CFG19, 0x400f32d3 + 4080 .set CYREG_UDB_P1_U1_CFG20, 0x400f32d4 + 4081 .set CYREG_UDB_P1_U1_CFG21, 0x400f32d5 + 4082 .set CYREG_UDB_P1_U1_CFG22, 0x400f32d6 + 4083 .set CYREG_UDB_P1_U1_CFG23, 0x400f32d7 + 4084 .set CYREG_UDB_P1_U1_CFG24, 0x400f32d8 + 4085 .set CYREG_UDB_P1_U1_CFG25, 0x400f32d9 + 4086 .set CYREG_UDB_P1_U1_CFG26, 0x400f32da + 4087 .set CYREG_UDB_P1_U1_CFG27, 0x400f32db + 4088 .set CYREG_UDB_P1_U1_CFG28, 0x400f32dc + 4089 .set CYREG_UDB_P1_U1_CFG29, 0x400f32dd + 4090 .set CYREG_UDB_P1_U1_CFG30, 0x400f32de + 4091 .set CYREG_UDB_P1_U1_CFG31, 0x400f32df + 4092 .set CYREG_UDB_P1_U1_DCFG0, 0x400f32e0 + 4093 .set CYREG_UDB_P1_U1_DCFG1, 0x400f32e2 + 4094 .set CYREG_UDB_P1_U1_DCFG2, 0x400f32e4 + 4095 .set CYREG_UDB_P1_U1_DCFG3, 0x400f32e6 + 4096 .set CYREG_UDB_P1_U1_DCFG4, 0x400f32e8 + 4097 .set CYREG_UDB_P1_U1_DCFG5, 0x400f32ea + 4098 .set CYREG_UDB_P1_U1_DCFG6, 0x400f32ec + 4099 .set CYREG_UDB_P1_U1_DCFG7, 0x400f32ee + 4100 .set CYDEV_UDB_P1_ROUTE_BASE, 0x400f3300 + 4101 .set CYDEV_UDB_P1_ROUTE_SIZE, 0x00000100 + 4102 .set CYREG_UDB_P1_ROUTE_HC0, 0x400f3300 + 4103 .set CYREG_UDB_P1_ROUTE_HC1, 0x400f3301 + 4104 .set CYREG_UDB_P1_ROUTE_HC2, 0x400f3302 + 4105 .set CYREG_UDB_P1_ROUTE_HC3, 0x400f3303 + 4106 .set CYREG_UDB_P1_ROUTE_HC4, 0x400f3304 + 4107 .set CYREG_UDB_P1_ROUTE_HC5, 0x400f3305 + 4108 .set CYREG_UDB_P1_ROUTE_HC6, 0x400f3306 + 4109 .set CYREG_UDB_P1_ROUTE_HC7, 0x400f3307 + 4110 .set CYREG_UDB_P1_ROUTE_HC8, 0x400f3308 + 4111 .set CYREG_UDB_P1_ROUTE_HC9, 0x400f3309 + 4112 .set CYREG_UDB_P1_ROUTE_HC10, 0x400f330a + 4113 .set CYREG_UDB_P1_ROUTE_HC11, 0x400f330b + 4114 .set CYREG_UDB_P1_ROUTE_HC12, 0x400f330c + 4115 .set CYREG_UDB_P1_ROUTE_HC13, 0x400f330d + 4116 .set CYREG_UDB_P1_ROUTE_HC14, 0x400f330e + 4117 .set CYREG_UDB_P1_ROUTE_HC15, 0x400f330f + 4118 .set CYREG_UDB_P1_ROUTE_HC16, 0x400f3310 + 4119 .set CYREG_UDB_P1_ROUTE_HC17, 0x400f3311 + 4120 .set CYREG_UDB_P1_ROUTE_HC18, 0x400f3312 + 4121 .set CYREG_UDB_P1_ROUTE_HC19, 0x400f3313 + 4122 .set CYREG_UDB_P1_ROUTE_HC20, 0x400f3314 + 4123 .set CYREG_UDB_P1_ROUTE_HC21, 0x400f3315 + 4124 .set CYREG_UDB_P1_ROUTE_HC22, 0x400f3316 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 74 + + + 4125 .set CYREG_UDB_P1_ROUTE_HC23, 0x400f3317 + 4126 .set CYREG_UDB_P1_ROUTE_HC24, 0x400f3318 + 4127 .set CYREG_UDB_P1_ROUTE_HC25, 0x400f3319 + 4128 .set CYREG_UDB_P1_ROUTE_HC26, 0x400f331a + 4129 .set CYREG_UDB_P1_ROUTE_HC27, 0x400f331b + 4130 .set CYREG_UDB_P1_ROUTE_HC28, 0x400f331c + 4131 .set CYREG_UDB_P1_ROUTE_HC29, 0x400f331d + 4132 .set CYREG_UDB_P1_ROUTE_HC30, 0x400f331e + 4133 .set CYREG_UDB_P1_ROUTE_HC31, 0x400f331f + 4134 .set CYREG_UDB_P1_ROUTE_HC32, 0x400f3320 + 4135 .set CYREG_UDB_P1_ROUTE_HC33, 0x400f3321 + 4136 .set CYREG_UDB_P1_ROUTE_HC34, 0x400f3322 + 4137 .set CYREG_UDB_P1_ROUTE_HC35, 0x400f3323 + 4138 .set CYREG_UDB_P1_ROUTE_HC36, 0x400f3324 + 4139 .set CYREG_UDB_P1_ROUTE_HC37, 0x400f3325 + 4140 .set CYREG_UDB_P1_ROUTE_HC38, 0x400f3326 + 4141 .set CYREG_UDB_P1_ROUTE_HC39, 0x400f3327 + 4142 .set CYREG_UDB_P1_ROUTE_HC40, 0x400f3328 + 4143 .set CYREG_UDB_P1_ROUTE_HC41, 0x400f3329 + 4144 .set CYREG_UDB_P1_ROUTE_HC42, 0x400f332a + 4145 .set CYREG_UDB_P1_ROUTE_HC43, 0x400f332b + 4146 .set CYREG_UDB_P1_ROUTE_HC44, 0x400f332c + 4147 .set CYREG_UDB_P1_ROUTE_HC45, 0x400f332d + 4148 .set CYREG_UDB_P1_ROUTE_HC46, 0x400f332e + 4149 .set CYREG_UDB_P1_ROUTE_HC47, 0x400f332f + 4150 .set CYREG_UDB_P1_ROUTE_HC48, 0x400f3330 + 4151 .set CYREG_UDB_P1_ROUTE_HC49, 0x400f3331 + 4152 .set CYREG_UDB_P1_ROUTE_HC50, 0x400f3332 + 4153 .set CYREG_UDB_P1_ROUTE_HC51, 0x400f3333 + 4154 .set CYREG_UDB_P1_ROUTE_HC52, 0x400f3334 + 4155 .set CYREG_UDB_P1_ROUTE_HC53, 0x400f3335 + 4156 .set CYREG_UDB_P1_ROUTE_HC54, 0x400f3336 + 4157 .set CYREG_UDB_P1_ROUTE_HC55, 0x400f3337 + 4158 .set CYREG_UDB_P1_ROUTE_HC56, 0x400f3338 + 4159 .set CYREG_UDB_P1_ROUTE_HC57, 0x400f3339 + 4160 .set CYREG_UDB_P1_ROUTE_HC58, 0x400f333a + 4161 .set CYREG_UDB_P1_ROUTE_HC59, 0x400f333b + 4162 .set CYREG_UDB_P1_ROUTE_HC60, 0x400f333c + 4163 .set CYREG_UDB_P1_ROUTE_HC61, 0x400f333d + 4164 .set CYREG_UDB_P1_ROUTE_HC62, 0x400f333e + 4165 .set CYREG_UDB_P1_ROUTE_HC63, 0x400f333f + 4166 .set CYREG_UDB_P1_ROUTE_HC64, 0x400f3340 + 4167 .set CYREG_UDB_P1_ROUTE_HC65, 0x400f3341 + 4168 .set CYREG_UDB_P1_ROUTE_HC66, 0x400f3342 + 4169 .set CYREG_UDB_P1_ROUTE_HC67, 0x400f3343 + 4170 .set CYREG_UDB_P1_ROUTE_HC68, 0x400f3344 + 4171 .set CYREG_UDB_P1_ROUTE_HC69, 0x400f3345 + 4172 .set CYREG_UDB_P1_ROUTE_HC70, 0x400f3346 + 4173 .set CYREG_UDB_P1_ROUTE_HC71, 0x400f3347 + 4174 .set CYREG_UDB_P1_ROUTE_HC72, 0x400f3348 + 4175 .set CYREG_UDB_P1_ROUTE_HC73, 0x400f3349 + 4176 .set CYREG_UDB_P1_ROUTE_HC74, 0x400f334a + 4177 .set CYREG_UDB_P1_ROUTE_HC75, 0x400f334b + 4178 .set CYREG_UDB_P1_ROUTE_HC76, 0x400f334c + 4179 .set CYREG_UDB_P1_ROUTE_HC77, 0x400f334d + 4180 .set CYREG_UDB_P1_ROUTE_HC78, 0x400f334e + 4181 .set CYREG_UDB_P1_ROUTE_HC79, 0x400f334f + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 75 + + + 4182 .set CYREG_UDB_P1_ROUTE_HC80, 0x400f3350 + 4183 .set CYREG_UDB_P1_ROUTE_HC81, 0x400f3351 + 4184 .set CYREG_UDB_P1_ROUTE_HC82, 0x400f3352 + 4185 .set CYREG_UDB_P1_ROUTE_HC83, 0x400f3353 + 4186 .set CYREG_UDB_P1_ROUTE_HC84, 0x400f3354 + 4187 .set CYREG_UDB_P1_ROUTE_HC85, 0x400f3355 + 4188 .set CYREG_UDB_P1_ROUTE_HC86, 0x400f3356 + 4189 .set CYREG_UDB_P1_ROUTE_HC87, 0x400f3357 + 4190 .set CYREG_UDB_P1_ROUTE_HC88, 0x400f3358 + 4191 .set CYREG_UDB_P1_ROUTE_HC89, 0x400f3359 + 4192 .set CYREG_UDB_P1_ROUTE_HC90, 0x400f335a + 4193 .set CYREG_UDB_P1_ROUTE_HC91, 0x400f335b + 4194 .set CYREG_UDB_P1_ROUTE_HC92, 0x400f335c + 4195 .set CYREG_UDB_P1_ROUTE_HC93, 0x400f335d + 4196 .set CYREG_UDB_P1_ROUTE_HC94, 0x400f335e + 4197 .set CYREG_UDB_P1_ROUTE_HC95, 0x400f335f + 4198 .set CYREG_UDB_P1_ROUTE_HC96, 0x400f3360 + 4199 .set CYREG_UDB_P1_ROUTE_HC97, 0x400f3361 + 4200 .set CYREG_UDB_P1_ROUTE_HC98, 0x400f3362 + 4201 .set CYREG_UDB_P1_ROUTE_HC99, 0x400f3363 + 4202 .set CYREG_UDB_P1_ROUTE_HC100, 0x400f3364 + 4203 .set CYREG_UDB_P1_ROUTE_HC101, 0x400f3365 + 4204 .set CYREG_UDB_P1_ROUTE_HC102, 0x400f3366 + 4205 .set CYREG_UDB_P1_ROUTE_HC103, 0x400f3367 + 4206 .set CYREG_UDB_P1_ROUTE_HC104, 0x400f3368 + 4207 .set CYREG_UDB_P1_ROUTE_HC105, 0x400f3369 + 4208 .set CYREG_UDB_P1_ROUTE_HC106, 0x400f336a + 4209 .set CYREG_UDB_P1_ROUTE_HC107, 0x400f336b + 4210 .set CYREG_UDB_P1_ROUTE_HC108, 0x400f336c + 4211 .set CYREG_UDB_P1_ROUTE_HC109, 0x400f336d + 4212 .set CYREG_UDB_P1_ROUTE_HC110, 0x400f336e + 4213 .set CYREG_UDB_P1_ROUTE_HC111, 0x400f336f + 4214 .set CYREG_UDB_P1_ROUTE_HC112, 0x400f3370 + 4215 .set CYREG_UDB_P1_ROUTE_HC113, 0x400f3371 + 4216 .set CYREG_UDB_P1_ROUTE_HC114, 0x400f3372 + 4217 .set CYREG_UDB_P1_ROUTE_HC115, 0x400f3373 + 4218 .set CYREG_UDB_P1_ROUTE_HC116, 0x400f3374 + 4219 .set CYREG_UDB_P1_ROUTE_HC117, 0x400f3375 + 4220 .set CYREG_UDB_P1_ROUTE_HC118, 0x400f3376 + 4221 .set CYREG_UDB_P1_ROUTE_HC119, 0x400f3377 + 4222 .set CYREG_UDB_P1_ROUTE_HC120, 0x400f3378 + 4223 .set CYREG_UDB_P1_ROUTE_HC121, 0x400f3379 + 4224 .set CYREG_UDB_P1_ROUTE_HC122, 0x400f337a + 4225 .set CYREG_UDB_P1_ROUTE_HC123, 0x400f337b + 4226 .set CYREG_UDB_P1_ROUTE_HC124, 0x400f337c + 4227 .set CYREG_UDB_P1_ROUTE_HC125, 0x400f337d + 4228 .set CYREG_UDB_P1_ROUTE_HC126, 0x400f337e + 4229 .set CYREG_UDB_P1_ROUTE_HC127, 0x400f337f + 4230 .set CYREG_UDB_P1_ROUTE_HV_L0, 0x400f3380 + 4231 .set CYREG_UDB_P1_ROUTE_HV_L1, 0x400f3381 + 4232 .set CYREG_UDB_P1_ROUTE_HV_L2, 0x400f3382 + 4233 .set CYREG_UDB_P1_ROUTE_HV_L3, 0x400f3383 + 4234 .set CYREG_UDB_P1_ROUTE_HV_L4, 0x400f3384 + 4235 .set CYREG_UDB_P1_ROUTE_HV_L5, 0x400f3385 + 4236 .set CYREG_UDB_P1_ROUTE_HV_L6, 0x400f3386 + 4237 .set CYREG_UDB_P1_ROUTE_HV_L7, 0x400f3387 + 4238 .set CYREG_UDB_P1_ROUTE_HV_L8, 0x400f3388 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 76 + + + 4239 .set CYREG_UDB_P1_ROUTE_HV_L9, 0x400f3389 + 4240 .set CYREG_UDB_P1_ROUTE_HV_L10, 0x400f338a + 4241 .set CYREG_UDB_P1_ROUTE_HV_L11, 0x400f338b + 4242 .set CYREG_UDB_P1_ROUTE_HV_L12, 0x400f338c + 4243 .set CYREG_UDB_P1_ROUTE_HV_L13, 0x400f338d + 4244 .set CYREG_UDB_P1_ROUTE_HV_L14, 0x400f338e + 4245 .set CYREG_UDB_P1_ROUTE_HV_L15, 0x400f338f + 4246 .set CYREG_UDB_P1_ROUTE_HS0, 0x400f3390 + 4247 .set CYREG_UDB_P1_ROUTE_HS1, 0x400f3391 + 4248 .set CYREG_UDB_P1_ROUTE_HS2, 0x400f3392 + 4249 .set CYREG_UDB_P1_ROUTE_HS3, 0x400f3393 + 4250 .set CYREG_UDB_P1_ROUTE_HS4, 0x400f3394 + 4251 .set CYREG_UDB_P1_ROUTE_HS5, 0x400f3395 + 4252 .set CYREG_UDB_P1_ROUTE_HS6, 0x400f3396 + 4253 .set CYREG_UDB_P1_ROUTE_HS7, 0x400f3397 + 4254 .set CYREG_UDB_P1_ROUTE_HS8, 0x400f3398 + 4255 .set CYREG_UDB_P1_ROUTE_HS9, 0x400f3399 + 4256 .set CYREG_UDB_P1_ROUTE_HS10, 0x400f339a + 4257 .set CYREG_UDB_P1_ROUTE_HS11, 0x400f339b + 4258 .set CYREG_UDB_P1_ROUTE_HS12, 0x400f339c + 4259 .set CYREG_UDB_P1_ROUTE_HS13, 0x400f339d + 4260 .set CYREG_UDB_P1_ROUTE_HS14, 0x400f339e + 4261 .set CYREG_UDB_P1_ROUTE_HS15, 0x400f339f + 4262 .set CYREG_UDB_P1_ROUTE_HS16, 0x400f33a0 + 4263 .set CYREG_UDB_P1_ROUTE_HS17, 0x400f33a1 + 4264 .set CYREG_UDB_P1_ROUTE_HS18, 0x400f33a2 + 4265 .set CYREG_UDB_P1_ROUTE_HS19, 0x400f33a3 + 4266 .set CYREG_UDB_P1_ROUTE_HS20, 0x400f33a4 + 4267 .set CYREG_UDB_P1_ROUTE_HS21, 0x400f33a5 + 4268 .set CYREG_UDB_P1_ROUTE_HS22, 0x400f33a6 + 4269 .set CYREG_UDB_P1_ROUTE_HS23, 0x400f33a7 + 4270 .set CYREG_UDB_P1_ROUTE_HV_R0, 0x400f33a8 + 4271 .set CYREG_UDB_P1_ROUTE_HV_R1, 0x400f33a9 + 4272 .set CYREG_UDB_P1_ROUTE_HV_R2, 0x400f33aa + 4273 .set CYREG_UDB_P1_ROUTE_HV_R3, 0x400f33ab + 4274 .set CYREG_UDB_P1_ROUTE_HV_R4, 0x400f33ac + 4275 .set CYREG_UDB_P1_ROUTE_HV_R5, 0x400f33ad + 4276 .set CYREG_UDB_P1_ROUTE_HV_R6, 0x400f33ae + 4277 .set CYREG_UDB_P1_ROUTE_HV_R7, 0x400f33af + 4278 .set CYREG_UDB_P1_ROUTE_HV_R8, 0x400f33b0 + 4279 .set CYREG_UDB_P1_ROUTE_HV_R9, 0x400f33b1 + 4280 .set CYREG_UDB_P1_ROUTE_HV_R10, 0x400f33b2 + 4281 .set CYREG_UDB_P1_ROUTE_HV_R11, 0x400f33b3 + 4282 .set CYREG_UDB_P1_ROUTE_HV_R12, 0x400f33b4 + 4283 .set CYREG_UDB_P1_ROUTE_HV_R13, 0x400f33b5 + 4284 .set CYREG_UDB_P1_ROUTE_HV_R14, 0x400f33b6 + 4285 .set CYREG_UDB_P1_ROUTE_HV_R15, 0x400f33b7 + 4286 .set CYREG_UDB_P1_ROUTE_PLD0IN0, 0x400f33c0 + 4287 .set CYREG_UDB_P1_ROUTE_PLD0IN1, 0x400f33c2 + 4288 .set CYREG_UDB_P1_ROUTE_PLD0IN2, 0x400f33c4 + 4289 .set CYREG_UDB_P1_ROUTE_PLD1IN0, 0x400f33ca + 4290 .set CYREG_UDB_P1_ROUTE_PLD1IN1, 0x400f33cc + 4291 .set CYREG_UDB_P1_ROUTE_PLD1IN2, 0x400f33ce + 4292 .set CYREG_UDB_P1_ROUTE_DPIN0, 0x400f33d0 + 4293 .set CYREG_UDB_P1_ROUTE_DPIN1, 0x400f33d2 + 4294 .set CYREG_UDB_P1_ROUTE_SCIN, 0x400f33d6 + 4295 .set CYREG_UDB_P1_ROUTE_SCIOIN, 0x400f33d8 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 77 + + + 4296 .set CYREG_UDB_P1_ROUTE_RCIN, 0x400f33de + 4297 .set CYREG_UDB_P1_ROUTE_VS0, 0x400f33e0 + 4298 .set CYREG_UDB_P1_ROUTE_VS1, 0x400f33e2 + 4299 .set CYREG_UDB_P1_ROUTE_VS2, 0x400f33e4 + 4300 .set CYREG_UDB_P1_ROUTE_VS3, 0x400f33e6 + 4301 .set CYREG_UDB_P1_ROUTE_VS4, 0x400f33e8 + 4302 .set CYREG_UDB_P1_ROUTE_VS5, 0x400f33ea + 4303 .set CYREG_UDB_P1_ROUTE_VS6, 0x400f33ec + 4304 .set CYREG_UDB_P1_ROUTE_VS7, 0x400f33ee + 4305 .set CYDEV_UDB_DSI0_BASE, 0x400f4000 + 4306 .set CYDEV_UDB_DSI0_SIZE, 0x00000100 + 4307 .set CYREG_UDB_DSI0_HC0, 0x400f4000 + 4308 .set CYFLD_UDB_DSI_HC_BYTE__OFFSET, 0x00000000 + 4309 .set CYFLD_UDB_DSI_HC_BYTE__SIZE, 0x00000008 + 4310 .set CYREG_UDB_DSI0_HC1, 0x400f4001 + 4311 .set CYREG_UDB_DSI0_HC2, 0x400f4002 + 4312 .set CYREG_UDB_DSI0_HC3, 0x400f4003 + 4313 .set CYREG_UDB_DSI0_HC4, 0x400f4004 + 4314 .set CYREG_UDB_DSI0_HC5, 0x400f4005 + 4315 .set CYREG_UDB_DSI0_HC6, 0x400f4006 + 4316 .set CYREG_UDB_DSI0_HC7, 0x400f4007 + 4317 .set CYREG_UDB_DSI0_HC8, 0x400f4008 + 4318 .set CYREG_UDB_DSI0_HC9, 0x400f4009 + 4319 .set CYREG_UDB_DSI0_HC10, 0x400f400a + 4320 .set CYREG_UDB_DSI0_HC11, 0x400f400b + 4321 .set CYREG_UDB_DSI0_HC12, 0x400f400c + 4322 .set CYREG_UDB_DSI0_HC13, 0x400f400d + 4323 .set CYREG_UDB_DSI0_HC14, 0x400f400e + 4324 .set CYREG_UDB_DSI0_HC15, 0x400f400f + 4325 .set CYREG_UDB_DSI0_HC16, 0x400f4010 + 4326 .set CYREG_UDB_DSI0_HC17, 0x400f4011 + 4327 .set CYREG_UDB_DSI0_HC18, 0x400f4012 + 4328 .set CYREG_UDB_DSI0_HC19, 0x400f4013 + 4329 .set CYREG_UDB_DSI0_HC20, 0x400f4014 + 4330 .set CYREG_UDB_DSI0_HC21, 0x400f4015 + 4331 .set CYREG_UDB_DSI0_HC22, 0x400f4016 + 4332 .set CYREG_UDB_DSI0_HC23, 0x400f4017 + 4333 .set CYREG_UDB_DSI0_HC24, 0x400f4018 + 4334 .set CYREG_UDB_DSI0_HC25, 0x400f4019 + 4335 .set CYREG_UDB_DSI0_HC26, 0x400f401a + 4336 .set CYREG_UDB_DSI0_HC27, 0x400f401b + 4337 .set CYREG_UDB_DSI0_HC28, 0x400f401c + 4338 .set CYREG_UDB_DSI0_HC29, 0x400f401d + 4339 .set CYREG_UDB_DSI0_HC30, 0x400f401e + 4340 .set CYREG_UDB_DSI0_HC31, 0x400f401f + 4341 .set CYREG_UDB_DSI0_HC32, 0x400f4020 + 4342 .set CYREG_UDB_DSI0_HC33, 0x400f4021 + 4343 .set CYREG_UDB_DSI0_HC34, 0x400f4022 + 4344 .set CYREG_UDB_DSI0_HC35, 0x400f4023 + 4345 .set CYREG_UDB_DSI0_HC36, 0x400f4024 + 4346 .set CYREG_UDB_DSI0_HC37, 0x400f4025 + 4347 .set CYREG_UDB_DSI0_HC38, 0x400f4026 + 4348 .set CYREG_UDB_DSI0_HC39, 0x400f4027 + 4349 .set CYREG_UDB_DSI0_HC40, 0x400f4028 + 4350 .set CYREG_UDB_DSI0_HC41, 0x400f4029 + 4351 .set CYREG_UDB_DSI0_HC42, 0x400f402a + 4352 .set CYREG_UDB_DSI0_HC43, 0x400f402b + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 78 + + + 4353 .set CYREG_UDB_DSI0_HC44, 0x400f402c + 4354 .set CYREG_UDB_DSI0_HC45, 0x400f402d + 4355 .set CYREG_UDB_DSI0_HC46, 0x400f402e + 4356 .set CYREG_UDB_DSI0_HC47, 0x400f402f + 4357 .set CYREG_UDB_DSI0_HC48, 0x400f4030 + 4358 .set CYREG_UDB_DSI0_HC49, 0x400f4031 + 4359 .set CYREG_UDB_DSI0_HC50, 0x400f4032 + 4360 .set CYREG_UDB_DSI0_HC51, 0x400f4033 + 4361 .set CYREG_UDB_DSI0_HC52, 0x400f4034 + 4362 .set CYREG_UDB_DSI0_HC53, 0x400f4035 + 4363 .set CYREG_UDB_DSI0_HC54, 0x400f4036 + 4364 .set CYREG_UDB_DSI0_HC55, 0x400f4037 + 4365 .set CYREG_UDB_DSI0_HC56, 0x400f4038 + 4366 .set CYREG_UDB_DSI0_HC57, 0x400f4039 + 4367 .set CYREG_UDB_DSI0_HC58, 0x400f403a + 4368 .set CYREG_UDB_DSI0_HC59, 0x400f403b + 4369 .set CYREG_UDB_DSI0_HC60, 0x400f403c + 4370 .set CYREG_UDB_DSI0_HC61, 0x400f403d + 4371 .set CYREG_UDB_DSI0_HC62, 0x400f403e + 4372 .set CYREG_UDB_DSI0_HC63, 0x400f403f + 4373 .set CYREG_UDB_DSI0_HC64, 0x400f4040 + 4374 .set CYREG_UDB_DSI0_HC65, 0x400f4041 + 4375 .set CYREG_UDB_DSI0_HC66, 0x400f4042 + 4376 .set CYREG_UDB_DSI0_HC67, 0x400f4043 + 4377 .set CYREG_UDB_DSI0_HC68, 0x400f4044 + 4378 .set CYREG_UDB_DSI0_HC69, 0x400f4045 + 4379 .set CYREG_UDB_DSI0_HC70, 0x400f4046 + 4380 .set CYREG_UDB_DSI0_HC71, 0x400f4047 + 4381 .set CYREG_UDB_DSI0_HC72, 0x400f4048 + 4382 .set CYREG_UDB_DSI0_HC73, 0x400f4049 + 4383 .set CYREG_UDB_DSI0_HC74, 0x400f404a + 4384 .set CYREG_UDB_DSI0_HC75, 0x400f404b + 4385 .set CYREG_UDB_DSI0_HC76, 0x400f404c + 4386 .set CYREG_UDB_DSI0_HC77, 0x400f404d + 4387 .set CYREG_UDB_DSI0_HC78, 0x400f404e + 4388 .set CYREG_UDB_DSI0_HC79, 0x400f404f + 4389 .set CYREG_UDB_DSI0_HC80, 0x400f4050 + 4390 .set CYREG_UDB_DSI0_HC81, 0x400f4051 + 4391 .set CYREG_UDB_DSI0_HC82, 0x400f4052 + 4392 .set CYREG_UDB_DSI0_HC83, 0x400f4053 + 4393 .set CYREG_UDB_DSI0_HC84, 0x400f4054 + 4394 .set CYREG_UDB_DSI0_HC85, 0x400f4055 + 4395 .set CYREG_UDB_DSI0_HC86, 0x400f4056 + 4396 .set CYREG_UDB_DSI0_HC87, 0x400f4057 + 4397 .set CYREG_UDB_DSI0_HC88, 0x400f4058 + 4398 .set CYREG_UDB_DSI0_HC89, 0x400f4059 + 4399 .set CYREG_UDB_DSI0_HC90, 0x400f405a + 4400 .set CYREG_UDB_DSI0_HC91, 0x400f405b + 4401 .set CYREG_UDB_DSI0_HC92, 0x400f405c + 4402 .set CYREG_UDB_DSI0_HC93, 0x400f405d + 4403 .set CYREG_UDB_DSI0_HC94, 0x400f405e + 4404 .set CYREG_UDB_DSI0_HC95, 0x400f405f + 4405 .set CYREG_UDB_DSI0_HC96, 0x400f4060 + 4406 .set CYREG_UDB_DSI0_HC97, 0x400f4061 + 4407 .set CYREG_UDB_DSI0_HC98, 0x400f4062 + 4408 .set CYREG_UDB_DSI0_HC99, 0x400f4063 + 4409 .set CYREG_UDB_DSI0_HC100, 0x400f4064 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 79 + + + 4410 .set CYREG_UDB_DSI0_HC101, 0x400f4065 + 4411 .set CYREG_UDB_DSI0_HC102, 0x400f4066 + 4412 .set CYREG_UDB_DSI0_HC103, 0x400f4067 + 4413 .set CYREG_UDB_DSI0_HC104, 0x400f4068 + 4414 .set CYREG_UDB_DSI0_HC105, 0x400f4069 + 4415 .set CYREG_UDB_DSI0_HC106, 0x400f406a + 4416 .set CYREG_UDB_DSI0_HC107, 0x400f406b + 4417 .set CYREG_UDB_DSI0_HC108, 0x400f406c + 4418 .set CYREG_UDB_DSI0_HC109, 0x400f406d + 4419 .set CYREG_UDB_DSI0_HC110, 0x400f406e + 4420 .set CYREG_UDB_DSI0_HC111, 0x400f406f + 4421 .set CYREG_UDB_DSI0_HC112, 0x400f4070 + 4422 .set CYREG_UDB_DSI0_HC113, 0x400f4071 + 4423 .set CYREG_UDB_DSI0_HC114, 0x400f4072 + 4424 .set CYREG_UDB_DSI0_HC115, 0x400f4073 + 4425 .set CYREG_UDB_DSI0_HC116, 0x400f4074 + 4426 .set CYREG_UDB_DSI0_HC117, 0x400f4075 + 4427 .set CYREG_UDB_DSI0_HC118, 0x400f4076 + 4428 .set CYREG_UDB_DSI0_HC119, 0x400f4077 + 4429 .set CYREG_UDB_DSI0_HC120, 0x400f4078 + 4430 .set CYREG_UDB_DSI0_HC121, 0x400f4079 + 4431 .set CYREG_UDB_DSI0_HC122, 0x400f407a + 4432 .set CYREG_UDB_DSI0_HC123, 0x400f407b + 4433 .set CYREG_UDB_DSI0_HC124, 0x400f407c + 4434 .set CYREG_UDB_DSI0_HC125, 0x400f407d + 4435 .set CYREG_UDB_DSI0_HC126, 0x400f407e + 4436 .set CYREG_UDB_DSI0_HC127, 0x400f407f + 4437 .set CYREG_UDB_DSI0_HV_L0, 0x400f4080 + 4438 .set CYFLD_UDB_DSI_HV_BYTE__OFFSET, 0x00000000 + 4439 .set CYFLD_UDB_DSI_HV_BYTE__SIZE, 0x00000008 + 4440 .set CYREG_UDB_DSI0_HV_L1, 0x400f4081 + 4441 .set CYREG_UDB_DSI0_HV_L2, 0x400f4082 + 4442 .set CYREG_UDB_DSI0_HV_L3, 0x400f4083 + 4443 .set CYREG_UDB_DSI0_HV_L4, 0x400f4084 + 4444 .set CYREG_UDB_DSI0_HV_L5, 0x400f4085 + 4445 .set CYREG_UDB_DSI0_HV_L6, 0x400f4086 + 4446 .set CYREG_UDB_DSI0_HV_L7, 0x400f4087 + 4447 .set CYREG_UDB_DSI0_HV_L8, 0x400f4088 + 4448 .set CYREG_UDB_DSI0_HV_L9, 0x400f4089 + 4449 .set CYREG_UDB_DSI0_HV_L10, 0x400f408a + 4450 .set CYREG_UDB_DSI0_HV_L11, 0x400f408b + 4451 .set CYREG_UDB_DSI0_HV_L12, 0x400f408c + 4452 .set CYREG_UDB_DSI0_HV_L13, 0x400f408d + 4453 .set CYREG_UDB_DSI0_HV_L14, 0x400f408e + 4454 .set CYREG_UDB_DSI0_HV_L15, 0x400f408f + 4455 .set CYREG_UDB_DSI0_HS0, 0x400f4090 + 4456 .set CYFLD_UDB_DSI_HS_BYTE__OFFSET, 0x00000000 + 4457 .set CYFLD_UDB_DSI_HS_BYTE__SIZE, 0x00000008 + 4458 .set CYREG_UDB_DSI0_HS1, 0x400f4091 + 4459 .set CYREG_UDB_DSI0_HS2, 0x400f4092 + 4460 .set CYREG_UDB_DSI0_HS3, 0x400f4093 + 4461 .set CYREG_UDB_DSI0_HS4, 0x400f4094 + 4462 .set CYREG_UDB_DSI0_HS5, 0x400f4095 + 4463 .set CYREG_UDB_DSI0_HS6, 0x400f4096 + 4464 .set CYREG_UDB_DSI0_HS7, 0x400f4097 + 4465 .set CYREG_UDB_DSI0_HS8, 0x400f4098 + 4466 .set CYREG_UDB_DSI0_HS9, 0x400f4099 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 80 + + + 4467 .set CYREG_UDB_DSI0_HS10, 0x400f409a + 4468 .set CYREG_UDB_DSI0_HS11, 0x400f409b + 4469 .set CYREG_UDB_DSI0_HS12, 0x400f409c + 4470 .set CYREG_UDB_DSI0_HS13, 0x400f409d + 4471 .set CYREG_UDB_DSI0_HS14, 0x400f409e + 4472 .set CYREG_UDB_DSI0_HS15, 0x400f409f + 4473 .set CYREG_UDB_DSI0_HS16, 0x400f40a0 + 4474 .set CYREG_UDB_DSI0_HS17, 0x400f40a1 + 4475 .set CYREG_UDB_DSI0_HS18, 0x400f40a2 + 4476 .set CYREG_UDB_DSI0_HS19, 0x400f40a3 + 4477 .set CYREG_UDB_DSI0_HS20, 0x400f40a4 + 4478 .set CYREG_UDB_DSI0_HS21, 0x400f40a5 + 4479 .set CYREG_UDB_DSI0_HS22, 0x400f40a6 + 4480 .set CYREG_UDB_DSI0_HS23, 0x400f40a7 + 4481 .set CYREG_UDB_DSI0_HV_R0, 0x400f40a8 + 4482 .set CYREG_UDB_DSI0_HV_R1, 0x400f40a9 + 4483 .set CYREG_UDB_DSI0_HV_R2, 0x400f40aa + 4484 .set CYREG_UDB_DSI0_HV_R3, 0x400f40ab + 4485 .set CYREG_UDB_DSI0_HV_R4, 0x400f40ac + 4486 .set CYREG_UDB_DSI0_HV_R5, 0x400f40ad + 4487 .set CYREG_UDB_DSI0_HV_R6, 0x400f40ae + 4488 .set CYREG_UDB_DSI0_HV_R7, 0x400f40af + 4489 .set CYREG_UDB_DSI0_HV_R8, 0x400f40b0 + 4490 .set CYREG_UDB_DSI0_HV_R9, 0x400f40b1 + 4491 .set CYREG_UDB_DSI0_HV_R10, 0x400f40b2 + 4492 .set CYREG_UDB_DSI0_HV_R11, 0x400f40b3 + 4493 .set CYREG_UDB_DSI0_HV_R12, 0x400f40b4 + 4494 .set CYREG_UDB_DSI0_HV_R13, 0x400f40b5 + 4495 .set CYREG_UDB_DSI0_HV_R14, 0x400f40b6 + 4496 .set CYREG_UDB_DSI0_HV_R15, 0x400f40b7 + 4497 .set CYREG_UDB_DSI0_DSIINP0, 0x400f40c0 + 4498 .set CYFLD_UDB_DSI_PI_TOP__OFFSET, 0x00000000 + 4499 .set CYFLD_UDB_DSI_PI_TOP__SIZE, 0x00000004 + 4500 .set CYFLD_UDB_DSI_PI_BOT__OFFSET, 0x00000004 + 4501 .set CYFLD_UDB_DSI_PI_BOT__SIZE, 0x00000004 + 4502 .set CYREG_UDB_DSI0_DSIINP1, 0x400f40c2 + 4503 .set CYREG_UDB_DSI0_DSIINP2, 0x400f40c4 + 4504 .set CYREG_UDB_DSI0_DSIINP3, 0x400f40c6 + 4505 .set CYREG_UDB_DSI0_DSIINP4, 0x400f40c8 + 4506 .set CYREG_UDB_DSI0_DSIINP5, 0x400f40ca + 4507 .set CYREG_UDB_DSI0_DSIOUTP0, 0x400f40cc + 4508 .set CYREG_UDB_DSI0_DSIOUTP1, 0x400f40ce + 4509 .set CYREG_UDB_DSI0_DSIOUTP2, 0x400f40d0 + 4510 .set CYREG_UDB_DSI0_DSIOUTP3, 0x400f40d2 + 4511 .set CYREG_UDB_DSI0_DSIOUTT0, 0x400f40d4 + 4512 .set CYREG_UDB_DSI0_DSIOUTT1, 0x400f40d6 + 4513 .set CYREG_UDB_DSI0_DSIOUTT2, 0x400f40d8 + 4514 .set CYREG_UDB_DSI0_DSIOUTT3, 0x400f40da + 4515 .set CYREG_UDB_DSI0_DSIOUTT4, 0x400f40dc + 4516 .set CYREG_UDB_DSI0_DSIOUTT5, 0x400f40de + 4517 .set CYREG_UDB_DSI0_VS0, 0x400f40e0 + 4518 .set CYFLD_UDB_DSI_VS_TOP__OFFSET, 0x00000000 + 4519 .set CYFLD_UDB_DSI_VS_TOP__SIZE, 0x00000004 + 4520 .set CYFLD_UDB_DSI_VS_BOT__OFFSET, 0x00000004 + 4521 .set CYFLD_UDB_DSI_VS_BOT__SIZE, 0x00000004 + 4522 .set CYREG_UDB_DSI0_VS1, 0x400f40e2 + 4523 .set CYREG_UDB_DSI0_VS2, 0x400f40e4 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 81 + + + 4524 .set CYREG_UDB_DSI0_VS3, 0x400f40e6 + 4525 .set CYREG_UDB_DSI0_VS4, 0x400f40e8 + 4526 .set CYREG_UDB_DSI0_VS5, 0x400f40ea + 4527 .set CYREG_UDB_DSI0_VS6, 0x400f40ec + 4528 .set CYREG_UDB_DSI0_VS7, 0x400f40ee + 4529 .set CYDEV_UDB_DSI1_BASE, 0x400f4100 + 4530 .set CYDEV_UDB_DSI1_SIZE, 0x00000100 + 4531 .set CYREG_UDB_DSI1_HC0, 0x400f4100 + 4532 .set CYREG_UDB_DSI1_HC1, 0x400f4101 + 4533 .set CYREG_UDB_DSI1_HC2, 0x400f4102 + 4534 .set CYREG_UDB_DSI1_HC3, 0x400f4103 + 4535 .set CYREG_UDB_DSI1_HC4, 0x400f4104 + 4536 .set CYREG_UDB_DSI1_HC5, 0x400f4105 + 4537 .set CYREG_UDB_DSI1_HC6, 0x400f4106 + 4538 .set CYREG_UDB_DSI1_HC7, 0x400f4107 + 4539 .set CYREG_UDB_DSI1_HC8, 0x400f4108 + 4540 .set CYREG_UDB_DSI1_HC9, 0x400f4109 + 4541 .set CYREG_UDB_DSI1_HC10, 0x400f410a + 4542 .set CYREG_UDB_DSI1_HC11, 0x400f410b + 4543 .set CYREG_UDB_DSI1_HC12, 0x400f410c + 4544 .set CYREG_UDB_DSI1_HC13, 0x400f410d + 4545 .set CYREG_UDB_DSI1_HC14, 0x400f410e + 4546 .set CYREG_UDB_DSI1_HC15, 0x400f410f + 4547 .set CYREG_UDB_DSI1_HC16, 0x400f4110 + 4548 .set CYREG_UDB_DSI1_HC17, 0x400f4111 + 4549 .set CYREG_UDB_DSI1_HC18, 0x400f4112 + 4550 .set CYREG_UDB_DSI1_HC19, 0x400f4113 + 4551 .set CYREG_UDB_DSI1_HC20, 0x400f4114 + 4552 .set CYREG_UDB_DSI1_HC21, 0x400f4115 + 4553 .set CYREG_UDB_DSI1_HC22, 0x400f4116 + 4554 .set CYREG_UDB_DSI1_HC23, 0x400f4117 + 4555 .set CYREG_UDB_DSI1_HC24, 0x400f4118 + 4556 .set CYREG_UDB_DSI1_HC25, 0x400f4119 + 4557 .set CYREG_UDB_DSI1_HC26, 0x400f411a + 4558 .set CYREG_UDB_DSI1_HC27, 0x400f411b + 4559 .set CYREG_UDB_DSI1_HC28, 0x400f411c + 4560 .set CYREG_UDB_DSI1_HC29, 0x400f411d + 4561 .set CYREG_UDB_DSI1_HC30, 0x400f411e + 4562 .set CYREG_UDB_DSI1_HC31, 0x400f411f + 4563 .set CYREG_UDB_DSI1_HC32, 0x400f4120 + 4564 .set CYREG_UDB_DSI1_HC33, 0x400f4121 + 4565 .set CYREG_UDB_DSI1_HC34, 0x400f4122 + 4566 .set CYREG_UDB_DSI1_HC35, 0x400f4123 + 4567 .set CYREG_UDB_DSI1_HC36, 0x400f4124 + 4568 .set CYREG_UDB_DSI1_HC37, 0x400f4125 + 4569 .set CYREG_UDB_DSI1_HC38, 0x400f4126 + 4570 .set CYREG_UDB_DSI1_HC39, 0x400f4127 + 4571 .set CYREG_UDB_DSI1_HC40, 0x400f4128 + 4572 .set CYREG_UDB_DSI1_HC41, 0x400f4129 + 4573 .set CYREG_UDB_DSI1_HC42, 0x400f412a + 4574 .set CYREG_UDB_DSI1_HC43, 0x400f412b + 4575 .set CYREG_UDB_DSI1_HC44, 0x400f412c + 4576 .set CYREG_UDB_DSI1_HC45, 0x400f412d + 4577 .set CYREG_UDB_DSI1_HC46, 0x400f412e + 4578 .set CYREG_UDB_DSI1_HC47, 0x400f412f + 4579 .set CYREG_UDB_DSI1_HC48, 0x400f4130 + 4580 .set CYREG_UDB_DSI1_HC49, 0x400f4131 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 82 + + + 4581 .set CYREG_UDB_DSI1_HC50, 0x400f4132 + 4582 .set CYREG_UDB_DSI1_HC51, 0x400f4133 + 4583 .set CYREG_UDB_DSI1_HC52, 0x400f4134 + 4584 .set CYREG_UDB_DSI1_HC53, 0x400f4135 + 4585 .set CYREG_UDB_DSI1_HC54, 0x400f4136 + 4586 .set CYREG_UDB_DSI1_HC55, 0x400f4137 + 4587 .set CYREG_UDB_DSI1_HC56, 0x400f4138 + 4588 .set CYREG_UDB_DSI1_HC57, 0x400f4139 + 4589 .set CYREG_UDB_DSI1_HC58, 0x400f413a + 4590 .set CYREG_UDB_DSI1_HC59, 0x400f413b + 4591 .set CYREG_UDB_DSI1_HC60, 0x400f413c + 4592 .set CYREG_UDB_DSI1_HC61, 0x400f413d + 4593 .set CYREG_UDB_DSI1_HC62, 0x400f413e + 4594 .set CYREG_UDB_DSI1_HC63, 0x400f413f + 4595 .set CYREG_UDB_DSI1_HC64, 0x400f4140 + 4596 .set CYREG_UDB_DSI1_HC65, 0x400f4141 + 4597 .set CYREG_UDB_DSI1_HC66, 0x400f4142 + 4598 .set CYREG_UDB_DSI1_HC67, 0x400f4143 + 4599 .set CYREG_UDB_DSI1_HC68, 0x400f4144 + 4600 .set CYREG_UDB_DSI1_HC69, 0x400f4145 + 4601 .set CYREG_UDB_DSI1_HC70, 0x400f4146 + 4602 .set CYREG_UDB_DSI1_HC71, 0x400f4147 + 4603 .set CYREG_UDB_DSI1_HC72, 0x400f4148 + 4604 .set CYREG_UDB_DSI1_HC73, 0x400f4149 + 4605 .set CYREG_UDB_DSI1_HC74, 0x400f414a + 4606 .set CYREG_UDB_DSI1_HC75, 0x400f414b + 4607 .set CYREG_UDB_DSI1_HC76, 0x400f414c + 4608 .set CYREG_UDB_DSI1_HC77, 0x400f414d + 4609 .set CYREG_UDB_DSI1_HC78, 0x400f414e + 4610 .set CYREG_UDB_DSI1_HC79, 0x400f414f + 4611 .set CYREG_UDB_DSI1_HC80, 0x400f4150 + 4612 .set CYREG_UDB_DSI1_HC81, 0x400f4151 + 4613 .set CYREG_UDB_DSI1_HC82, 0x400f4152 + 4614 .set CYREG_UDB_DSI1_HC83, 0x400f4153 + 4615 .set CYREG_UDB_DSI1_HC84, 0x400f4154 + 4616 .set CYREG_UDB_DSI1_HC85, 0x400f4155 + 4617 .set CYREG_UDB_DSI1_HC86, 0x400f4156 + 4618 .set CYREG_UDB_DSI1_HC87, 0x400f4157 + 4619 .set CYREG_UDB_DSI1_HC88, 0x400f4158 + 4620 .set CYREG_UDB_DSI1_HC89, 0x400f4159 + 4621 .set CYREG_UDB_DSI1_HC90, 0x400f415a + 4622 .set CYREG_UDB_DSI1_HC91, 0x400f415b + 4623 .set CYREG_UDB_DSI1_HC92, 0x400f415c + 4624 .set CYREG_UDB_DSI1_HC93, 0x400f415d + 4625 .set CYREG_UDB_DSI1_HC94, 0x400f415e + 4626 .set CYREG_UDB_DSI1_HC95, 0x400f415f + 4627 .set CYREG_UDB_DSI1_HC96, 0x400f4160 + 4628 .set CYREG_UDB_DSI1_HC97, 0x400f4161 + 4629 .set CYREG_UDB_DSI1_HC98, 0x400f4162 + 4630 .set CYREG_UDB_DSI1_HC99, 0x400f4163 + 4631 .set CYREG_UDB_DSI1_HC100, 0x400f4164 + 4632 .set CYREG_UDB_DSI1_HC101, 0x400f4165 + 4633 .set CYREG_UDB_DSI1_HC102, 0x400f4166 + 4634 .set CYREG_UDB_DSI1_HC103, 0x400f4167 + 4635 .set CYREG_UDB_DSI1_HC104, 0x400f4168 + 4636 .set CYREG_UDB_DSI1_HC105, 0x400f4169 + 4637 .set CYREG_UDB_DSI1_HC106, 0x400f416a + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 83 + + + 4638 .set CYREG_UDB_DSI1_HC107, 0x400f416b + 4639 .set CYREG_UDB_DSI1_HC108, 0x400f416c + 4640 .set CYREG_UDB_DSI1_HC109, 0x400f416d + 4641 .set CYREG_UDB_DSI1_HC110, 0x400f416e + 4642 .set CYREG_UDB_DSI1_HC111, 0x400f416f + 4643 .set CYREG_UDB_DSI1_HC112, 0x400f4170 + 4644 .set CYREG_UDB_DSI1_HC113, 0x400f4171 + 4645 .set CYREG_UDB_DSI1_HC114, 0x400f4172 + 4646 .set CYREG_UDB_DSI1_HC115, 0x400f4173 + 4647 .set CYREG_UDB_DSI1_HC116, 0x400f4174 + 4648 .set CYREG_UDB_DSI1_HC117, 0x400f4175 + 4649 .set CYREG_UDB_DSI1_HC118, 0x400f4176 + 4650 .set CYREG_UDB_DSI1_HC119, 0x400f4177 + 4651 .set CYREG_UDB_DSI1_HC120, 0x400f4178 + 4652 .set CYREG_UDB_DSI1_HC121, 0x400f4179 + 4653 .set CYREG_UDB_DSI1_HC122, 0x400f417a + 4654 .set CYREG_UDB_DSI1_HC123, 0x400f417b + 4655 .set CYREG_UDB_DSI1_HC124, 0x400f417c + 4656 .set CYREG_UDB_DSI1_HC125, 0x400f417d + 4657 .set CYREG_UDB_DSI1_HC126, 0x400f417e + 4658 .set CYREG_UDB_DSI1_HC127, 0x400f417f + 4659 .set CYREG_UDB_DSI1_HV_L0, 0x400f4180 + 4660 .set CYREG_UDB_DSI1_HV_L1, 0x400f4181 + 4661 .set CYREG_UDB_DSI1_HV_L2, 0x400f4182 + 4662 .set CYREG_UDB_DSI1_HV_L3, 0x400f4183 + 4663 .set CYREG_UDB_DSI1_HV_L4, 0x400f4184 + 4664 .set CYREG_UDB_DSI1_HV_L5, 0x400f4185 + 4665 .set CYREG_UDB_DSI1_HV_L6, 0x400f4186 + 4666 .set CYREG_UDB_DSI1_HV_L7, 0x400f4187 + 4667 .set CYREG_UDB_DSI1_HV_L8, 0x400f4188 + 4668 .set CYREG_UDB_DSI1_HV_L9, 0x400f4189 + 4669 .set CYREG_UDB_DSI1_HV_L10, 0x400f418a + 4670 .set CYREG_UDB_DSI1_HV_L11, 0x400f418b + 4671 .set CYREG_UDB_DSI1_HV_L12, 0x400f418c + 4672 .set CYREG_UDB_DSI1_HV_L13, 0x400f418d + 4673 .set CYREG_UDB_DSI1_HV_L14, 0x400f418e + 4674 .set CYREG_UDB_DSI1_HV_L15, 0x400f418f + 4675 .set CYREG_UDB_DSI1_HS0, 0x400f4190 + 4676 .set CYREG_UDB_DSI1_HS1, 0x400f4191 + 4677 .set CYREG_UDB_DSI1_HS2, 0x400f4192 + 4678 .set CYREG_UDB_DSI1_HS3, 0x400f4193 + 4679 .set CYREG_UDB_DSI1_HS4, 0x400f4194 + 4680 .set CYREG_UDB_DSI1_HS5, 0x400f4195 + 4681 .set CYREG_UDB_DSI1_HS6, 0x400f4196 + 4682 .set CYREG_UDB_DSI1_HS7, 0x400f4197 + 4683 .set CYREG_UDB_DSI1_HS8, 0x400f4198 + 4684 .set CYREG_UDB_DSI1_HS9, 0x400f4199 + 4685 .set CYREG_UDB_DSI1_HS10, 0x400f419a + 4686 .set CYREG_UDB_DSI1_HS11, 0x400f419b + 4687 .set CYREG_UDB_DSI1_HS12, 0x400f419c + 4688 .set CYREG_UDB_DSI1_HS13, 0x400f419d + 4689 .set CYREG_UDB_DSI1_HS14, 0x400f419e + 4690 .set CYREG_UDB_DSI1_HS15, 0x400f419f + 4691 .set CYREG_UDB_DSI1_HS16, 0x400f41a0 + 4692 .set CYREG_UDB_DSI1_HS17, 0x400f41a1 + 4693 .set CYREG_UDB_DSI1_HS18, 0x400f41a2 + 4694 .set CYREG_UDB_DSI1_HS19, 0x400f41a3 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 84 + + + 4695 .set CYREG_UDB_DSI1_HS20, 0x400f41a4 + 4696 .set CYREG_UDB_DSI1_HS21, 0x400f41a5 + 4697 .set CYREG_UDB_DSI1_HS22, 0x400f41a6 + 4698 .set CYREG_UDB_DSI1_HS23, 0x400f41a7 + 4699 .set CYREG_UDB_DSI1_HV_R0, 0x400f41a8 + 4700 .set CYREG_UDB_DSI1_HV_R1, 0x400f41a9 + 4701 .set CYREG_UDB_DSI1_HV_R2, 0x400f41aa + 4702 .set CYREG_UDB_DSI1_HV_R3, 0x400f41ab + 4703 .set CYREG_UDB_DSI1_HV_R4, 0x400f41ac + 4704 .set CYREG_UDB_DSI1_HV_R5, 0x400f41ad + 4705 .set CYREG_UDB_DSI1_HV_R6, 0x400f41ae + 4706 .set CYREG_UDB_DSI1_HV_R7, 0x400f41af + 4707 .set CYREG_UDB_DSI1_HV_R8, 0x400f41b0 + 4708 .set CYREG_UDB_DSI1_HV_R9, 0x400f41b1 + 4709 .set CYREG_UDB_DSI1_HV_R10, 0x400f41b2 + 4710 .set CYREG_UDB_DSI1_HV_R11, 0x400f41b3 + 4711 .set CYREG_UDB_DSI1_HV_R12, 0x400f41b4 + 4712 .set CYREG_UDB_DSI1_HV_R13, 0x400f41b5 + 4713 .set CYREG_UDB_DSI1_HV_R14, 0x400f41b6 + 4714 .set CYREG_UDB_DSI1_HV_R15, 0x400f41b7 + 4715 .set CYREG_UDB_DSI1_DSIINP0, 0x400f41c0 + 4716 .set CYREG_UDB_DSI1_DSIINP1, 0x400f41c2 + 4717 .set CYREG_UDB_DSI1_DSIINP2, 0x400f41c4 + 4718 .set CYREG_UDB_DSI1_DSIINP3, 0x400f41c6 + 4719 .set CYREG_UDB_DSI1_DSIINP4, 0x400f41c8 + 4720 .set CYREG_UDB_DSI1_DSIINP5, 0x400f41ca + 4721 .set CYREG_UDB_DSI1_DSIOUTP0, 0x400f41cc + 4722 .set CYREG_UDB_DSI1_DSIOUTP1, 0x400f41ce + 4723 .set CYREG_UDB_DSI1_DSIOUTP2, 0x400f41d0 + 4724 .set CYREG_UDB_DSI1_DSIOUTP3, 0x400f41d2 + 4725 .set CYREG_UDB_DSI1_DSIOUTT0, 0x400f41d4 + 4726 .set CYREG_UDB_DSI1_DSIOUTT1, 0x400f41d6 + 4727 .set CYREG_UDB_DSI1_DSIOUTT2, 0x400f41d8 + 4728 .set CYREG_UDB_DSI1_DSIOUTT3, 0x400f41da + 4729 .set CYREG_UDB_DSI1_DSIOUTT4, 0x400f41dc + 4730 .set CYREG_UDB_DSI1_DSIOUTT5, 0x400f41de + 4731 .set CYREG_UDB_DSI1_VS0, 0x400f41e0 + 4732 .set CYREG_UDB_DSI1_VS1, 0x400f41e2 + 4733 .set CYREG_UDB_DSI1_VS2, 0x400f41e4 + 4734 .set CYREG_UDB_DSI1_VS3, 0x400f41e6 + 4735 .set CYREG_UDB_DSI1_VS4, 0x400f41e8 + 4736 .set CYREG_UDB_DSI1_VS5, 0x400f41ea + 4737 .set CYREG_UDB_DSI1_VS6, 0x400f41ec + 4738 .set CYREG_UDB_DSI1_VS7, 0x400f41ee + 4739 .set CYDEV_UDB_DSI2_BASE, 0x400f4200 + 4740 .set CYDEV_UDB_DSI2_SIZE, 0x00000100 + 4741 .set CYREG_UDB_DSI2_HC0, 0x400f4200 + 4742 .set CYREG_UDB_DSI2_HC1, 0x400f4201 + 4743 .set CYREG_UDB_DSI2_HC2, 0x400f4202 + 4744 .set CYREG_UDB_DSI2_HC3, 0x400f4203 + 4745 .set CYREG_UDB_DSI2_HC4, 0x400f4204 + 4746 .set CYREG_UDB_DSI2_HC5, 0x400f4205 + 4747 .set CYREG_UDB_DSI2_HC6, 0x400f4206 + 4748 .set CYREG_UDB_DSI2_HC7, 0x400f4207 + 4749 .set CYREG_UDB_DSI2_HC8, 0x400f4208 + 4750 .set CYREG_UDB_DSI2_HC9, 0x400f4209 + 4751 .set CYREG_UDB_DSI2_HC10, 0x400f420a + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 85 + + + 4752 .set CYREG_UDB_DSI2_HC11, 0x400f420b + 4753 .set CYREG_UDB_DSI2_HC12, 0x400f420c + 4754 .set CYREG_UDB_DSI2_HC13, 0x400f420d + 4755 .set CYREG_UDB_DSI2_HC14, 0x400f420e + 4756 .set CYREG_UDB_DSI2_HC15, 0x400f420f + 4757 .set CYREG_UDB_DSI2_HC16, 0x400f4210 + 4758 .set CYREG_UDB_DSI2_HC17, 0x400f4211 + 4759 .set CYREG_UDB_DSI2_HC18, 0x400f4212 + 4760 .set CYREG_UDB_DSI2_HC19, 0x400f4213 + 4761 .set CYREG_UDB_DSI2_HC20, 0x400f4214 + 4762 .set CYREG_UDB_DSI2_HC21, 0x400f4215 + 4763 .set CYREG_UDB_DSI2_HC22, 0x400f4216 + 4764 .set CYREG_UDB_DSI2_HC23, 0x400f4217 + 4765 .set CYREG_UDB_DSI2_HC24, 0x400f4218 + 4766 .set CYREG_UDB_DSI2_HC25, 0x400f4219 + 4767 .set CYREG_UDB_DSI2_HC26, 0x400f421a + 4768 .set CYREG_UDB_DSI2_HC27, 0x400f421b + 4769 .set CYREG_UDB_DSI2_HC28, 0x400f421c + 4770 .set CYREG_UDB_DSI2_HC29, 0x400f421d + 4771 .set CYREG_UDB_DSI2_HC30, 0x400f421e + 4772 .set CYREG_UDB_DSI2_HC31, 0x400f421f + 4773 .set CYREG_UDB_DSI2_HC32, 0x400f4220 + 4774 .set CYREG_UDB_DSI2_HC33, 0x400f4221 + 4775 .set CYREG_UDB_DSI2_HC34, 0x400f4222 + 4776 .set CYREG_UDB_DSI2_HC35, 0x400f4223 + 4777 .set CYREG_UDB_DSI2_HC36, 0x400f4224 + 4778 .set CYREG_UDB_DSI2_HC37, 0x400f4225 + 4779 .set CYREG_UDB_DSI2_HC38, 0x400f4226 + 4780 .set CYREG_UDB_DSI2_HC39, 0x400f4227 + 4781 .set CYREG_UDB_DSI2_HC40, 0x400f4228 + 4782 .set CYREG_UDB_DSI2_HC41, 0x400f4229 + 4783 .set CYREG_UDB_DSI2_HC42, 0x400f422a + 4784 .set CYREG_UDB_DSI2_HC43, 0x400f422b + 4785 .set CYREG_UDB_DSI2_HC44, 0x400f422c + 4786 .set CYREG_UDB_DSI2_HC45, 0x400f422d + 4787 .set CYREG_UDB_DSI2_HC46, 0x400f422e + 4788 .set CYREG_UDB_DSI2_HC47, 0x400f422f + 4789 .set CYREG_UDB_DSI2_HC48, 0x400f4230 + 4790 .set CYREG_UDB_DSI2_HC49, 0x400f4231 + 4791 .set CYREG_UDB_DSI2_HC50, 0x400f4232 + 4792 .set CYREG_UDB_DSI2_HC51, 0x400f4233 + 4793 .set CYREG_UDB_DSI2_HC52, 0x400f4234 + 4794 .set CYREG_UDB_DSI2_HC53, 0x400f4235 + 4795 .set CYREG_UDB_DSI2_HC54, 0x400f4236 + 4796 .set CYREG_UDB_DSI2_HC55, 0x400f4237 + 4797 .set CYREG_UDB_DSI2_HC56, 0x400f4238 + 4798 .set CYREG_UDB_DSI2_HC57, 0x400f4239 + 4799 .set CYREG_UDB_DSI2_HC58, 0x400f423a + 4800 .set CYREG_UDB_DSI2_HC59, 0x400f423b + 4801 .set CYREG_UDB_DSI2_HC60, 0x400f423c + 4802 .set CYREG_UDB_DSI2_HC61, 0x400f423d + 4803 .set CYREG_UDB_DSI2_HC62, 0x400f423e + 4804 .set CYREG_UDB_DSI2_HC63, 0x400f423f + 4805 .set CYREG_UDB_DSI2_HC64, 0x400f4240 + 4806 .set CYREG_UDB_DSI2_HC65, 0x400f4241 + 4807 .set CYREG_UDB_DSI2_HC66, 0x400f4242 + 4808 .set CYREG_UDB_DSI2_HC67, 0x400f4243 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 86 + + + 4809 .set CYREG_UDB_DSI2_HC68, 0x400f4244 + 4810 .set CYREG_UDB_DSI2_HC69, 0x400f4245 + 4811 .set CYREG_UDB_DSI2_HC70, 0x400f4246 + 4812 .set CYREG_UDB_DSI2_HC71, 0x400f4247 + 4813 .set CYREG_UDB_DSI2_HC72, 0x400f4248 + 4814 .set CYREG_UDB_DSI2_HC73, 0x400f4249 + 4815 .set CYREG_UDB_DSI2_HC74, 0x400f424a + 4816 .set CYREG_UDB_DSI2_HC75, 0x400f424b + 4817 .set CYREG_UDB_DSI2_HC76, 0x400f424c + 4818 .set CYREG_UDB_DSI2_HC77, 0x400f424d + 4819 .set CYREG_UDB_DSI2_HC78, 0x400f424e + 4820 .set CYREG_UDB_DSI2_HC79, 0x400f424f + 4821 .set CYREG_UDB_DSI2_HC80, 0x400f4250 + 4822 .set CYREG_UDB_DSI2_HC81, 0x400f4251 + 4823 .set CYREG_UDB_DSI2_HC82, 0x400f4252 + 4824 .set CYREG_UDB_DSI2_HC83, 0x400f4253 + 4825 .set CYREG_UDB_DSI2_HC84, 0x400f4254 + 4826 .set CYREG_UDB_DSI2_HC85, 0x400f4255 + 4827 .set CYREG_UDB_DSI2_HC86, 0x400f4256 + 4828 .set CYREG_UDB_DSI2_HC87, 0x400f4257 + 4829 .set CYREG_UDB_DSI2_HC88, 0x400f4258 + 4830 .set CYREG_UDB_DSI2_HC89, 0x400f4259 + 4831 .set CYREG_UDB_DSI2_HC90, 0x400f425a + 4832 .set CYREG_UDB_DSI2_HC91, 0x400f425b + 4833 .set CYREG_UDB_DSI2_HC92, 0x400f425c + 4834 .set CYREG_UDB_DSI2_HC93, 0x400f425d + 4835 .set CYREG_UDB_DSI2_HC94, 0x400f425e + 4836 .set CYREG_UDB_DSI2_HC95, 0x400f425f + 4837 .set CYREG_UDB_DSI2_HC96, 0x400f4260 + 4838 .set CYREG_UDB_DSI2_HC97, 0x400f4261 + 4839 .set CYREG_UDB_DSI2_HC98, 0x400f4262 + 4840 .set CYREG_UDB_DSI2_HC99, 0x400f4263 + 4841 .set CYREG_UDB_DSI2_HC100, 0x400f4264 + 4842 .set CYREG_UDB_DSI2_HC101, 0x400f4265 + 4843 .set CYREG_UDB_DSI2_HC102, 0x400f4266 + 4844 .set CYREG_UDB_DSI2_HC103, 0x400f4267 + 4845 .set CYREG_UDB_DSI2_HC104, 0x400f4268 + 4846 .set CYREG_UDB_DSI2_HC105, 0x400f4269 + 4847 .set CYREG_UDB_DSI2_HC106, 0x400f426a + 4848 .set CYREG_UDB_DSI2_HC107, 0x400f426b + 4849 .set CYREG_UDB_DSI2_HC108, 0x400f426c + 4850 .set CYREG_UDB_DSI2_HC109, 0x400f426d + 4851 .set CYREG_UDB_DSI2_HC110, 0x400f426e + 4852 .set CYREG_UDB_DSI2_HC111, 0x400f426f + 4853 .set CYREG_UDB_DSI2_HC112, 0x400f4270 + 4854 .set CYREG_UDB_DSI2_HC113, 0x400f4271 + 4855 .set CYREG_UDB_DSI2_HC114, 0x400f4272 + 4856 .set CYREG_UDB_DSI2_HC115, 0x400f4273 + 4857 .set CYREG_UDB_DSI2_HC116, 0x400f4274 + 4858 .set CYREG_UDB_DSI2_HC117, 0x400f4275 + 4859 .set CYREG_UDB_DSI2_HC118, 0x400f4276 + 4860 .set CYREG_UDB_DSI2_HC119, 0x400f4277 + 4861 .set CYREG_UDB_DSI2_HC120, 0x400f4278 + 4862 .set CYREG_UDB_DSI2_HC121, 0x400f4279 + 4863 .set CYREG_UDB_DSI2_HC122, 0x400f427a + 4864 .set CYREG_UDB_DSI2_HC123, 0x400f427b + 4865 .set CYREG_UDB_DSI2_HC124, 0x400f427c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 87 + + + 4866 .set CYREG_UDB_DSI2_HC125, 0x400f427d + 4867 .set CYREG_UDB_DSI2_HC126, 0x400f427e + 4868 .set CYREG_UDB_DSI2_HC127, 0x400f427f + 4869 .set CYREG_UDB_DSI2_HV_L0, 0x400f4280 + 4870 .set CYREG_UDB_DSI2_HV_L1, 0x400f4281 + 4871 .set CYREG_UDB_DSI2_HV_L2, 0x400f4282 + 4872 .set CYREG_UDB_DSI2_HV_L3, 0x400f4283 + 4873 .set CYREG_UDB_DSI2_HV_L4, 0x400f4284 + 4874 .set CYREG_UDB_DSI2_HV_L5, 0x400f4285 + 4875 .set CYREG_UDB_DSI2_HV_L6, 0x400f4286 + 4876 .set CYREG_UDB_DSI2_HV_L7, 0x400f4287 + 4877 .set CYREG_UDB_DSI2_HV_L8, 0x400f4288 + 4878 .set CYREG_UDB_DSI2_HV_L9, 0x400f4289 + 4879 .set CYREG_UDB_DSI2_HV_L10, 0x400f428a + 4880 .set CYREG_UDB_DSI2_HV_L11, 0x400f428b + 4881 .set CYREG_UDB_DSI2_HV_L12, 0x400f428c + 4882 .set CYREG_UDB_DSI2_HV_L13, 0x400f428d + 4883 .set CYREG_UDB_DSI2_HV_L14, 0x400f428e + 4884 .set CYREG_UDB_DSI2_HV_L15, 0x400f428f + 4885 .set CYREG_UDB_DSI2_HS0, 0x400f4290 + 4886 .set CYREG_UDB_DSI2_HS1, 0x400f4291 + 4887 .set CYREG_UDB_DSI2_HS2, 0x400f4292 + 4888 .set CYREG_UDB_DSI2_HS3, 0x400f4293 + 4889 .set CYREG_UDB_DSI2_HS4, 0x400f4294 + 4890 .set CYREG_UDB_DSI2_HS5, 0x400f4295 + 4891 .set CYREG_UDB_DSI2_HS6, 0x400f4296 + 4892 .set CYREG_UDB_DSI2_HS7, 0x400f4297 + 4893 .set CYREG_UDB_DSI2_HS8, 0x400f4298 + 4894 .set CYREG_UDB_DSI2_HS9, 0x400f4299 + 4895 .set CYREG_UDB_DSI2_HS10, 0x400f429a + 4896 .set CYREG_UDB_DSI2_HS11, 0x400f429b + 4897 .set CYREG_UDB_DSI2_HS12, 0x400f429c + 4898 .set CYREG_UDB_DSI2_HS13, 0x400f429d + 4899 .set CYREG_UDB_DSI2_HS14, 0x400f429e + 4900 .set CYREG_UDB_DSI2_HS15, 0x400f429f + 4901 .set CYREG_UDB_DSI2_HS16, 0x400f42a0 + 4902 .set CYREG_UDB_DSI2_HS17, 0x400f42a1 + 4903 .set CYREG_UDB_DSI2_HS18, 0x400f42a2 + 4904 .set CYREG_UDB_DSI2_HS19, 0x400f42a3 + 4905 .set CYREG_UDB_DSI2_HS20, 0x400f42a4 + 4906 .set CYREG_UDB_DSI2_HS21, 0x400f42a5 + 4907 .set CYREG_UDB_DSI2_HS22, 0x400f42a6 + 4908 .set CYREG_UDB_DSI2_HS23, 0x400f42a7 + 4909 .set CYREG_UDB_DSI2_HV_R0, 0x400f42a8 + 4910 .set CYREG_UDB_DSI2_HV_R1, 0x400f42a9 + 4911 .set CYREG_UDB_DSI2_HV_R2, 0x400f42aa + 4912 .set CYREG_UDB_DSI2_HV_R3, 0x400f42ab + 4913 .set CYREG_UDB_DSI2_HV_R4, 0x400f42ac + 4914 .set CYREG_UDB_DSI2_HV_R5, 0x400f42ad + 4915 .set CYREG_UDB_DSI2_HV_R6, 0x400f42ae + 4916 .set CYREG_UDB_DSI2_HV_R7, 0x400f42af + 4917 .set CYREG_UDB_DSI2_HV_R8, 0x400f42b0 + 4918 .set CYREG_UDB_DSI2_HV_R9, 0x400f42b1 + 4919 .set CYREG_UDB_DSI2_HV_R10, 0x400f42b2 + 4920 .set CYREG_UDB_DSI2_HV_R11, 0x400f42b3 + 4921 .set CYREG_UDB_DSI2_HV_R12, 0x400f42b4 + 4922 .set CYREG_UDB_DSI2_HV_R13, 0x400f42b5 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 88 + + + 4923 .set CYREG_UDB_DSI2_HV_R14, 0x400f42b6 + 4924 .set CYREG_UDB_DSI2_HV_R15, 0x400f42b7 + 4925 .set CYREG_UDB_DSI2_DSIINP0, 0x400f42c0 + 4926 .set CYREG_UDB_DSI2_DSIINP1, 0x400f42c2 + 4927 .set CYREG_UDB_DSI2_DSIINP2, 0x400f42c4 + 4928 .set CYREG_UDB_DSI2_DSIINP3, 0x400f42c6 + 4929 .set CYREG_UDB_DSI2_DSIINP4, 0x400f42c8 + 4930 .set CYREG_UDB_DSI2_DSIINP5, 0x400f42ca + 4931 .set CYREG_UDB_DSI2_DSIOUTP0, 0x400f42cc + 4932 .set CYREG_UDB_DSI2_DSIOUTP1, 0x400f42ce + 4933 .set CYREG_UDB_DSI2_DSIOUTP2, 0x400f42d0 + 4934 .set CYREG_UDB_DSI2_DSIOUTP3, 0x400f42d2 + 4935 .set CYREG_UDB_DSI2_DSIOUTT0, 0x400f42d4 + 4936 .set CYREG_UDB_DSI2_DSIOUTT1, 0x400f42d6 + 4937 .set CYREG_UDB_DSI2_DSIOUTT2, 0x400f42d8 + 4938 .set CYREG_UDB_DSI2_DSIOUTT3, 0x400f42da + 4939 .set CYREG_UDB_DSI2_DSIOUTT4, 0x400f42dc + 4940 .set CYREG_UDB_DSI2_DSIOUTT5, 0x400f42de + 4941 .set CYREG_UDB_DSI2_VS0, 0x400f42e0 + 4942 .set CYREG_UDB_DSI2_VS1, 0x400f42e2 + 4943 .set CYREG_UDB_DSI2_VS2, 0x400f42e4 + 4944 .set CYREG_UDB_DSI2_VS3, 0x400f42e6 + 4945 .set CYREG_UDB_DSI2_VS4, 0x400f42e8 + 4946 .set CYREG_UDB_DSI2_VS5, 0x400f42ea + 4947 .set CYREG_UDB_DSI2_VS6, 0x400f42ec + 4948 .set CYREG_UDB_DSI2_VS7, 0x400f42ee + 4949 .set CYDEV_UDB_DSI3_BASE, 0x400f4300 + 4950 .set CYDEV_UDB_DSI3_SIZE, 0x00000100 + 4951 .set CYREG_UDB_DSI3_HC0, 0x400f4300 + 4952 .set CYREG_UDB_DSI3_HC1, 0x400f4301 + 4953 .set CYREG_UDB_DSI3_HC2, 0x400f4302 + 4954 .set CYREG_UDB_DSI3_HC3, 0x400f4303 + 4955 .set CYREG_UDB_DSI3_HC4, 0x400f4304 + 4956 .set CYREG_UDB_DSI3_HC5, 0x400f4305 + 4957 .set CYREG_UDB_DSI3_HC6, 0x400f4306 + 4958 .set CYREG_UDB_DSI3_HC7, 0x400f4307 + 4959 .set CYREG_UDB_DSI3_HC8, 0x400f4308 + 4960 .set CYREG_UDB_DSI3_HC9, 0x400f4309 + 4961 .set CYREG_UDB_DSI3_HC10, 0x400f430a + 4962 .set CYREG_UDB_DSI3_HC11, 0x400f430b + 4963 .set CYREG_UDB_DSI3_HC12, 0x400f430c + 4964 .set CYREG_UDB_DSI3_HC13, 0x400f430d + 4965 .set CYREG_UDB_DSI3_HC14, 0x400f430e + 4966 .set CYREG_UDB_DSI3_HC15, 0x400f430f + 4967 .set CYREG_UDB_DSI3_HC16, 0x400f4310 + 4968 .set CYREG_UDB_DSI3_HC17, 0x400f4311 + 4969 .set CYREG_UDB_DSI3_HC18, 0x400f4312 + 4970 .set CYREG_UDB_DSI3_HC19, 0x400f4313 + 4971 .set CYREG_UDB_DSI3_HC20, 0x400f4314 + 4972 .set CYREG_UDB_DSI3_HC21, 0x400f4315 + 4973 .set CYREG_UDB_DSI3_HC22, 0x400f4316 + 4974 .set CYREG_UDB_DSI3_HC23, 0x400f4317 + 4975 .set CYREG_UDB_DSI3_HC24, 0x400f4318 + 4976 .set CYREG_UDB_DSI3_HC25, 0x400f4319 + 4977 .set CYREG_UDB_DSI3_HC26, 0x400f431a + 4978 .set CYREG_UDB_DSI3_HC27, 0x400f431b + 4979 .set CYREG_UDB_DSI3_HC28, 0x400f431c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 89 + + + 4980 .set CYREG_UDB_DSI3_HC29, 0x400f431d + 4981 .set CYREG_UDB_DSI3_HC30, 0x400f431e + 4982 .set CYREG_UDB_DSI3_HC31, 0x400f431f + 4983 .set CYREG_UDB_DSI3_HC32, 0x400f4320 + 4984 .set CYREG_UDB_DSI3_HC33, 0x400f4321 + 4985 .set CYREG_UDB_DSI3_HC34, 0x400f4322 + 4986 .set CYREG_UDB_DSI3_HC35, 0x400f4323 + 4987 .set CYREG_UDB_DSI3_HC36, 0x400f4324 + 4988 .set CYREG_UDB_DSI3_HC37, 0x400f4325 + 4989 .set CYREG_UDB_DSI3_HC38, 0x400f4326 + 4990 .set CYREG_UDB_DSI3_HC39, 0x400f4327 + 4991 .set CYREG_UDB_DSI3_HC40, 0x400f4328 + 4992 .set CYREG_UDB_DSI3_HC41, 0x400f4329 + 4993 .set CYREG_UDB_DSI3_HC42, 0x400f432a + 4994 .set CYREG_UDB_DSI3_HC43, 0x400f432b + 4995 .set CYREG_UDB_DSI3_HC44, 0x400f432c + 4996 .set CYREG_UDB_DSI3_HC45, 0x400f432d + 4997 .set CYREG_UDB_DSI3_HC46, 0x400f432e + 4998 .set CYREG_UDB_DSI3_HC47, 0x400f432f + 4999 .set CYREG_UDB_DSI3_HC48, 0x400f4330 + 5000 .set CYREG_UDB_DSI3_HC49, 0x400f4331 + 5001 .set CYREG_UDB_DSI3_HC50, 0x400f4332 + 5002 .set CYREG_UDB_DSI3_HC51, 0x400f4333 + 5003 .set CYREG_UDB_DSI3_HC52, 0x400f4334 + 5004 .set CYREG_UDB_DSI3_HC53, 0x400f4335 + 5005 .set CYREG_UDB_DSI3_HC54, 0x400f4336 + 5006 .set CYREG_UDB_DSI3_HC55, 0x400f4337 + 5007 .set CYREG_UDB_DSI3_HC56, 0x400f4338 + 5008 .set CYREG_UDB_DSI3_HC57, 0x400f4339 + 5009 .set CYREG_UDB_DSI3_HC58, 0x400f433a + 5010 .set CYREG_UDB_DSI3_HC59, 0x400f433b + 5011 .set CYREG_UDB_DSI3_HC60, 0x400f433c + 5012 .set CYREG_UDB_DSI3_HC61, 0x400f433d + 5013 .set CYREG_UDB_DSI3_HC62, 0x400f433e + 5014 .set CYREG_UDB_DSI3_HC63, 0x400f433f + 5015 .set CYREG_UDB_DSI3_HC64, 0x400f4340 + 5016 .set CYREG_UDB_DSI3_HC65, 0x400f4341 + 5017 .set CYREG_UDB_DSI3_HC66, 0x400f4342 + 5018 .set CYREG_UDB_DSI3_HC67, 0x400f4343 + 5019 .set CYREG_UDB_DSI3_HC68, 0x400f4344 + 5020 .set CYREG_UDB_DSI3_HC69, 0x400f4345 + 5021 .set CYREG_UDB_DSI3_HC70, 0x400f4346 + 5022 .set CYREG_UDB_DSI3_HC71, 0x400f4347 + 5023 .set CYREG_UDB_DSI3_HC72, 0x400f4348 + 5024 .set CYREG_UDB_DSI3_HC73, 0x400f4349 + 5025 .set CYREG_UDB_DSI3_HC74, 0x400f434a + 5026 .set CYREG_UDB_DSI3_HC75, 0x400f434b + 5027 .set CYREG_UDB_DSI3_HC76, 0x400f434c + 5028 .set CYREG_UDB_DSI3_HC77, 0x400f434d + 5029 .set CYREG_UDB_DSI3_HC78, 0x400f434e + 5030 .set CYREG_UDB_DSI3_HC79, 0x400f434f + 5031 .set CYREG_UDB_DSI3_HC80, 0x400f4350 + 5032 .set CYREG_UDB_DSI3_HC81, 0x400f4351 + 5033 .set CYREG_UDB_DSI3_HC82, 0x400f4352 + 5034 .set CYREG_UDB_DSI3_HC83, 0x400f4353 + 5035 .set CYREG_UDB_DSI3_HC84, 0x400f4354 + 5036 .set CYREG_UDB_DSI3_HC85, 0x400f4355 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 90 + + + 5037 .set CYREG_UDB_DSI3_HC86, 0x400f4356 + 5038 .set CYREG_UDB_DSI3_HC87, 0x400f4357 + 5039 .set CYREG_UDB_DSI3_HC88, 0x400f4358 + 5040 .set CYREG_UDB_DSI3_HC89, 0x400f4359 + 5041 .set CYREG_UDB_DSI3_HC90, 0x400f435a + 5042 .set CYREG_UDB_DSI3_HC91, 0x400f435b + 5043 .set CYREG_UDB_DSI3_HC92, 0x400f435c + 5044 .set CYREG_UDB_DSI3_HC93, 0x400f435d + 5045 .set CYREG_UDB_DSI3_HC94, 0x400f435e + 5046 .set CYREG_UDB_DSI3_HC95, 0x400f435f + 5047 .set CYREG_UDB_DSI3_HC96, 0x400f4360 + 5048 .set CYREG_UDB_DSI3_HC97, 0x400f4361 + 5049 .set CYREG_UDB_DSI3_HC98, 0x400f4362 + 5050 .set CYREG_UDB_DSI3_HC99, 0x400f4363 + 5051 .set CYREG_UDB_DSI3_HC100, 0x400f4364 + 5052 .set CYREG_UDB_DSI3_HC101, 0x400f4365 + 5053 .set CYREG_UDB_DSI3_HC102, 0x400f4366 + 5054 .set CYREG_UDB_DSI3_HC103, 0x400f4367 + 5055 .set CYREG_UDB_DSI3_HC104, 0x400f4368 + 5056 .set CYREG_UDB_DSI3_HC105, 0x400f4369 + 5057 .set CYREG_UDB_DSI3_HC106, 0x400f436a + 5058 .set CYREG_UDB_DSI3_HC107, 0x400f436b + 5059 .set CYREG_UDB_DSI3_HC108, 0x400f436c + 5060 .set CYREG_UDB_DSI3_HC109, 0x400f436d + 5061 .set CYREG_UDB_DSI3_HC110, 0x400f436e + 5062 .set CYREG_UDB_DSI3_HC111, 0x400f436f + 5063 .set CYREG_UDB_DSI3_HC112, 0x400f4370 + 5064 .set CYREG_UDB_DSI3_HC113, 0x400f4371 + 5065 .set CYREG_UDB_DSI3_HC114, 0x400f4372 + 5066 .set CYREG_UDB_DSI3_HC115, 0x400f4373 + 5067 .set CYREG_UDB_DSI3_HC116, 0x400f4374 + 5068 .set CYREG_UDB_DSI3_HC117, 0x400f4375 + 5069 .set CYREG_UDB_DSI3_HC118, 0x400f4376 + 5070 .set CYREG_UDB_DSI3_HC119, 0x400f4377 + 5071 .set CYREG_UDB_DSI3_HC120, 0x400f4378 + 5072 .set CYREG_UDB_DSI3_HC121, 0x400f4379 + 5073 .set CYREG_UDB_DSI3_HC122, 0x400f437a + 5074 .set CYREG_UDB_DSI3_HC123, 0x400f437b + 5075 .set CYREG_UDB_DSI3_HC124, 0x400f437c + 5076 .set CYREG_UDB_DSI3_HC125, 0x400f437d + 5077 .set CYREG_UDB_DSI3_HC126, 0x400f437e + 5078 .set CYREG_UDB_DSI3_HC127, 0x400f437f + 5079 .set CYREG_UDB_DSI3_HV_L0, 0x400f4380 + 5080 .set CYREG_UDB_DSI3_HV_L1, 0x400f4381 + 5081 .set CYREG_UDB_DSI3_HV_L2, 0x400f4382 + 5082 .set CYREG_UDB_DSI3_HV_L3, 0x400f4383 + 5083 .set CYREG_UDB_DSI3_HV_L4, 0x400f4384 + 5084 .set CYREG_UDB_DSI3_HV_L5, 0x400f4385 + 5085 .set CYREG_UDB_DSI3_HV_L6, 0x400f4386 + 5086 .set CYREG_UDB_DSI3_HV_L7, 0x400f4387 + 5087 .set CYREG_UDB_DSI3_HV_L8, 0x400f4388 + 5088 .set CYREG_UDB_DSI3_HV_L9, 0x400f4389 + 5089 .set CYREG_UDB_DSI3_HV_L10, 0x400f438a + 5090 .set CYREG_UDB_DSI3_HV_L11, 0x400f438b + 5091 .set CYREG_UDB_DSI3_HV_L12, 0x400f438c + 5092 .set CYREG_UDB_DSI3_HV_L13, 0x400f438d + 5093 .set CYREG_UDB_DSI3_HV_L14, 0x400f438e + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 91 + + + 5094 .set CYREG_UDB_DSI3_HV_L15, 0x400f438f + 5095 .set CYREG_UDB_DSI3_HS0, 0x400f4390 + 5096 .set CYREG_UDB_DSI3_HS1, 0x400f4391 + 5097 .set CYREG_UDB_DSI3_HS2, 0x400f4392 + 5098 .set CYREG_UDB_DSI3_HS3, 0x400f4393 + 5099 .set CYREG_UDB_DSI3_HS4, 0x400f4394 + 5100 .set CYREG_UDB_DSI3_HS5, 0x400f4395 + 5101 .set CYREG_UDB_DSI3_HS6, 0x400f4396 + 5102 .set CYREG_UDB_DSI3_HS7, 0x400f4397 + 5103 .set CYREG_UDB_DSI3_HS8, 0x400f4398 + 5104 .set CYREG_UDB_DSI3_HS9, 0x400f4399 + 5105 .set CYREG_UDB_DSI3_HS10, 0x400f439a + 5106 .set CYREG_UDB_DSI3_HS11, 0x400f439b + 5107 .set CYREG_UDB_DSI3_HS12, 0x400f439c + 5108 .set CYREG_UDB_DSI3_HS13, 0x400f439d + 5109 .set CYREG_UDB_DSI3_HS14, 0x400f439e + 5110 .set CYREG_UDB_DSI3_HS15, 0x400f439f + 5111 .set CYREG_UDB_DSI3_HS16, 0x400f43a0 + 5112 .set CYREG_UDB_DSI3_HS17, 0x400f43a1 + 5113 .set CYREG_UDB_DSI3_HS18, 0x400f43a2 + 5114 .set CYREG_UDB_DSI3_HS19, 0x400f43a3 + 5115 .set CYREG_UDB_DSI3_HS20, 0x400f43a4 + 5116 .set CYREG_UDB_DSI3_HS21, 0x400f43a5 + 5117 .set CYREG_UDB_DSI3_HS22, 0x400f43a6 + 5118 .set CYREG_UDB_DSI3_HS23, 0x400f43a7 + 5119 .set CYREG_UDB_DSI3_HV_R0, 0x400f43a8 + 5120 .set CYREG_UDB_DSI3_HV_R1, 0x400f43a9 + 5121 .set CYREG_UDB_DSI3_HV_R2, 0x400f43aa + 5122 .set CYREG_UDB_DSI3_HV_R3, 0x400f43ab + 5123 .set CYREG_UDB_DSI3_HV_R4, 0x400f43ac + 5124 .set CYREG_UDB_DSI3_HV_R5, 0x400f43ad + 5125 .set CYREG_UDB_DSI3_HV_R6, 0x400f43ae + 5126 .set CYREG_UDB_DSI3_HV_R7, 0x400f43af + 5127 .set CYREG_UDB_DSI3_HV_R8, 0x400f43b0 + 5128 .set CYREG_UDB_DSI3_HV_R9, 0x400f43b1 + 5129 .set CYREG_UDB_DSI3_HV_R10, 0x400f43b2 + 5130 .set CYREG_UDB_DSI3_HV_R11, 0x400f43b3 + 5131 .set CYREG_UDB_DSI3_HV_R12, 0x400f43b4 + 5132 .set CYREG_UDB_DSI3_HV_R13, 0x400f43b5 + 5133 .set CYREG_UDB_DSI3_HV_R14, 0x400f43b6 + 5134 .set CYREG_UDB_DSI3_HV_R15, 0x400f43b7 + 5135 .set CYREG_UDB_DSI3_DSIINP0, 0x400f43c0 + 5136 .set CYREG_UDB_DSI3_DSIINP1, 0x400f43c2 + 5137 .set CYREG_UDB_DSI3_DSIINP2, 0x400f43c4 + 5138 .set CYREG_UDB_DSI3_DSIINP3, 0x400f43c6 + 5139 .set CYREG_UDB_DSI3_DSIINP4, 0x400f43c8 + 5140 .set CYREG_UDB_DSI3_DSIINP5, 0x400f43ca + 5141 .set CYREG_UDB_DSI3_DSIOUTP0, 0x400f43cc + 5142 .set CYREG_UDB_DSI3_DSIOUTP1, 0x400f43ce + 5143 .set CYREG_UDB_DSI3_DSIOUTP2, 0x400f43d0 + 5144 .set CYREG_UDB_DSI3_DSIOUTP3, 0x400f43d2 + 5145 .set CYREG_UDB_DSI3_DSIOUTT0, 0x400f43d4 + 5146 .set CYREG_UDB_DSI3_DSIOUTT1, 0x400f43d6 + 5147 .set CYREG_UDB_DSI3_DSIOUTT2, 0x400f43d8 + 5148 .set CYREG_UDB_DSI3_DSIOUTT3, 0x400f43da + 5149 .set CYREG_UDB_DSI3_DSIOUTT4, 0x400f43dc + 5150 .set CYREG_UDB_DSI3_DSIOUTT5, 0x400f43de + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 92 + + + 5151 .set CYREG_UDB_DSI3_VS0, 0x400f43e0 + 5152 .set CYREG_UDB_DSI3_VS1, 0x400f43e2 + 5153 .set CYREG_UDB_DSI3_VS2, 0x400f43e4 + 5154 .set CYREG_UDB_DSI3_VS3, 0x400f43e6 + 5155 .set CYREG_UDB_DSI3_VS4, 0x400f43e8 + 5156 .set CYREG_UDB_DSI3_VS5, 0x400f43ea + 5157 .set CYREG_UDB_DSI3_VS6, 0x400f43ec + 5158 .set CYREG_UDB_DSI3_VS7, 0x400f43ee + 5159 .set CYDEV_UDB_PA0_BASE, 0x400f5000 + 5160 .set CYDEV_UDB_PA0_SIZE, 0x00000010 + 5161 .set CYREG_UDB_PA0_CFG0, 0x400f5000 + 5162 .set CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET, 0x00000000 + 5163 .set CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE, 0x00000002 + 5164 .set CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC, 0x00000000 + 5165 .set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0, 0x00000001 + 5166 .set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1, 0x00000002 + 5167 .set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2, 0x00000003 + 5168 .set CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET, 0x00000002 + 5169 .set CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE, 0x00000002 + 5170 .set CYVAL_UDB_PA_CLKIN_EN_MODE_OFF, 0x00000000 + 5171 .set CYVAL_UDB_PA_CLKIN_EN_MODE_ON, 0x00000001 + 5172 .set CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE, 0x00000002 + 5173 .set CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL, 0x00000003 + 5174 .set CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET, 0x00000004 + 5175 .set CYFLD_UDB_PA_CLKIN_EN_INV__SIZE, 0x00000001 + 5176 .set CYVAL_UDB_PA_CLKIN_EN_INV_NOINV, 0x00000000 + 5177 .set CYVAL_UDB_PA_CLKIN_EN_INV_INV, 0x00000001 + 5178 .set CYFLD_UDB_PA_CLKIN_INV__OFFSET, 0x00000005 + 5179 .set CYFLD_UDB_PA_CLKIN_INV__SIZE, 0x00000001 + 5180 .set CYVAL_UDB_PA_CLKIN_INV_NOINV, 0x00000000 + 5181 .set CYVAL_UDB_PA_CLKIN_INV_INV, 0x00000001 + 5182 .set CYFLD_UDB_PA_NC__OFFSET, 0x00000006 + 5183 .set CYFLD_UDB_PA_NC__SIZE, 0x00000002 + 5184 .set CYREG_UDB_PA0_CFG1, 0x400f5001 + 5185 .set CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET, 0x00000000 + 5186 .set CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE, 0x00000002 + 5187 .set CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC, 0x00000000 + 5188 .set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0, 0x00000001 + 5189 .set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1, 0x00000002 + 5190 .set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2, 0x00000003 + 5191 .set CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET, 0x00000002 + 5192 .set CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE, 0x00000002 + 5193 .set CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF, 0x00000000 + 5194 .set CYVAL_UDB_PA_CLKOUT_EN_MODE_ON, 0x00000001 + 5195 .set CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE, 0x00000002 + 5196 .set CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL, 0x00000003 + 5197 .set CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET, 0x00000004 + 5198 .set CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE, 0x00000001 + 5199 .set CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV, 0x00000000 + 5200 .set CYVAL_UDB_PA_CLKOUT_EN_INV_INV, 0x00000001 + 5201 .set CYFLD_UDB_PA_CLKOUT_INV__OFFSET, 0x00000005 + 5202 .set CYFLD_UDB_PA_CLKOUT_INV__SIZE, 0x00000001 + 5203 .set CYVAL_UDB_PA_CLKOUT_INV_NOINV, 0x00000000 + 5204 .set CYVAL_UDB_PA_CLKOUT_INV_INV, 0x00000001 + 5205 .set CYREG_UDB_PA0_CFG2, 0x400f5002 + 5206 .set CYFLD_UDB_PA_CLKIN_SEL__OFFSET, 0x00000000 + 5207 .set CYFLD_UDB_PA_CLKIN_SEL__SIZE, 0x00000004 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 93 + + + 5208 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK0, 0x00000000 + 5209 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK1, 0x00000001 + 5210 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK2, 0x00000002 + 5211 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK3, 0x00000003 + 5212 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK4, 0x00000004 + 5213 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK5, 0x00000005 + 5214 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK6, 0x00000006 + 5215 .set CYVAL_UDB_PA_CLKIN_SEL_GCLK7, 0x00000007 + 5216 .set CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP, 0x00000009 + 5217 .set CYVAL_UDB_PA_CLKIN_SEL_PIN_RC, 0x0000000c + 5218 .set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0, 0x0000000d + 5219 .set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1, 0x0000000e + 5220 .set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2, 0x0000000f + 5221 .set CYFLD_UDB_PA_CLKOUT_SEL__OFFSET, 0x00000004 + 5222 .set CYFLD_UDB_PA_CLKOUT_SEL__SIZE, 0x00000004 + 5223 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK0, 0x00000000 + 5224 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK1, 0x00000001 + 5225 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK2, 0x00000002 + 5226 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK3, 0x00000003 + 5227 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK4, 0x00000004 + 5228 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK5, 0x00000005 + 5229 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK6, 0x00000006 + 5230 .set CYVAL_UDB_PA_CLKOUT_SEL_GCLK7, 0x00000007 + 5231 .set CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP, 0x00000009 + 5232 .set CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC, 0x0000000c + 5233 .set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0, 0x0000000d + 5234 .set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1, 0x0000000e + 5235 .set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2, 0x0000000f + 5236 .set CYREG_UDB_PA0_CFG3, 0x400f5003 + 5237 .set CYFLD_UDB_PA_RES_IN_SEL__OFFSET, 0x00000000 + 5238 .set CYFLD_UDB_PA_RES_IN_SEL__SIZE, 0x00000002 + 5239 .set CYVAL_UDB_PA_RES_IN_SEL_PIN_RC, 0x00000000 + 5240 .set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0, 0x00000001 + 5241 .set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1, 0x00000002 + 5242 .set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2, 0x00000003 + 5243 .set CYFLD_UDB_PA_RES_IN_INV__OFFSET, 0x00000002 + 5244 .set CYFLD_UDB_PA_RES_IN_INV__SIZE, 0x00000001 + 5245 .set CYVAL_UDB_PA_RES_IN_INV_NOINV, 0x00000000 + 5246 .set CYVAL_UDB_PA_RES_IN_INV_INV, 0x00000001 + 5247 .set CYFLD_UDB_PA_NC0__OFFSET, 0x00000003 + 5248 .set CYFLD_UDB_PA_NC0__SIZE, 0x00000001 + 5249 .set CYFLD_UDB_PA_RES_OUT_SEL__OFFSET, 0x00000004 + 5250 .set CYFLD_UDB_PA_RES_OUT_SEL__SIZE, 0x00000002 + 5251 .set CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC, 0x00000000 + 5252 .set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0, 0x00000001 + 5253 .set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1, 0x00000002 + 5254 .set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2, 0x00000003 + 5255 .set CYFLD_UDB_PA_RES_OUT_INV__OFFSET, 0x00000006 + 5256 .set CYFLD_UDB_PA_RES_OUT_INV__SIZE, 0x00000001 + 5257 .set CYVAL_UDB_PA_RES_OUT_INV_NOINV, 0x00000000 + 5258 .set CYVAL_UDB_PA_RES_OUT_INV_INV, 0x00000001 + 5259 .set CYFLD_UDB_PA_NC7__OFFSET, 0x00000007 + 5260 .set CYFLD_UDB_PA_NC7__SIZE, 0x00000001 + 5261 .set CYREG_UDB_PA0_CFG4, 0x400f5004 + 5262 .set CYFLD_UDB_PA_RES_IN_EN__OFFSET, 0x00000000 + 5263 .set CYFLD_UDB_PA_RES_IN_EN__SIZE, 0x00000001 + 5264 .set CYVAL_UDB_PA_RES_IN_EN_DISABLE, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 94 + + + 5265 .set CYVAL_UDB_PA_RES_IN_EN_ENABLE, 0x00000001 + 5266 .set CYFLD_UDB_PA_RES_OUT_EN__OFFSET, 0x00000001 + 5267 .set CYFLD_UDB_PA_RES_OUT_EN__SIZE, 0x00000001 + 5268 .set CYVAL_UDB_PA_RES_OUT_EN_DISABLE, 0x00000000 + 5269 .set CYVAL_UDB_PA_RES_OUT_EN_ENABLE, 0x00000001 + 5270 .set CYFLD_UDB_PA_RES_OE_EN__OFFSET, 0x00000002 + 5271 .set CYFLD_UDB_PA_RES_OE_EN__SIZE, 0x00000001 + 5272 .set CYVAL_UDB_PA_RES_OE_EN_DISABLE, 0x00000000 + 5273 .set CYVAL_UDB_PA_RES_OE_EN_ENABLE, 0x00000001 + 5274 .set CYFLD_UDB_PA_NC7654__OFFSET, 0x00000003 + 5275 .set CYFLD_UDB_PA_NC7654__SIZE, 0x00000005 + 5276 .set CYREG_UDB_PA0_CFG5, 0x400f5005 + 5277 .set CYFLD_UDB_PA_PIN_SEL__OFFSET, 0x00000000 + 5278 .set CYFLD_UDB_PA_PIN_SEL__SIZE, 0x00000001 + 5279 .set CYVAL_UDB_PA_PIN_SEL_PIN0, 0x00000000 + 5280 .set CYVAL_UDB_PA_PIN_SEL_PIN1, 0x00000001 + 5281 .set CYVAL_UDB_PA_PIN_SEL_PIN2, 0x00000002 + 5282 .set CYVAL_UDB_PA_PIN_SEL_PIN3, 0x00000003 + 5283 .set CYVAL_UDB_PA_PIN_SEL_PIN4, 0x00000004 + 5284 .set CYVAL_UDB_PA_PIN_SEL_PIN5, 0x00000005 + 5285 .set CYVAL_UDB_PA_PIN_SEL_PIN6, 0x00000006 + 5286 .set CYVAL_UDB_PA_PIN_SEL_PIN7, 0x00000007 + 5287 .set CYREG_UDB_PA0_CFG6, 0x400f5006 + 5288 .set CYFLD_UDB_PA_IN_SYNC0__OFFSET, 0x00000000 + 5289 .set CYFLD_UDB_PA_IN_SYNC0__SIZE, 0x00000002 + 5290 .set CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT, 0x00000000 + 5291 .set CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC, 0x00000001 + 5292 .set CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC, 0x00000002 + 5293 .set CYVAL_UDB_PA_IN_SYNC0_RSVD, 0x00000003 + 5294 .set CYFLD_UDB_PA_IN_SYNC1__OFFSET, 0x00000002 + 5295 .set CYFLD_UDB_PA_IN_SYNC1__SIZE, 0x00000002 + 5296 .set CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT, 0x00000000 + 5297 .set CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC, 0x00000001 + 5298 .set CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC, 0x00000002 + 5299 .set CYVAL_UDB_PA_IN_SYNC1_RSVD, 0x00000003 + 5300 .set CYFLD_UDB_PA_IN_SYNC2__OFFSET, 0x00000004 + 5301 .set CYFLD_UDB_PA_IN_SYNC2__SIZE, 0x00000002 + 5302 .set CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT, 0x00000000 + 5303 .set CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC, 0x00000001 + 5304 .set CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC, 0x00000002 + 5305 .set CYVAL_UDB_PA_IN_SYNC2_RSVD, 0x00000003 + 5306 .set CYFLD_UDB_PA_IN_SYNC3__OFFSET, 0x00000006 + 5307 .set CYFLD_UDB_PA_IN_SYNC3__SIZE, 0x00000002 + 5308 .set CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT, 0x00000000 + 5309 .set CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC, 0x00000001 + 5310 .set CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC, 0x00000002 + 5311 .set CYVAL_UDB_PA_IN_SYNC3_RSVD, 0x00000003 + 5312 .set CYREG_UDB_PA0_CFG7, 0x400f5007 + 5313 .set CYFLD_UDB_PA_IN_SYNC4__OFFSET, 0x00000000 + 5314 .set CYFLD_UDB_PA_IN_SYNC4__SIZE, 0x00000002 + 5315 .set CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT, 0x00000000 + 5316 .set CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC, 0x00000001 + 5317 .set CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC, 0x00000002 + 5318 .set CYVAL_UDB_PA_IN_SYNC4_RSVD, 0x00000003 + 5319 .set CYFLD_UDB_PA_IN_SYNC5__OFFSET, 0x00000002 + 5320 .set CYFLD_UDB_PA_IN_SYNC5__SIZE, 0x00000002 + 5321 .set CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 95 + + + 5322 .set CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC, 0x00000001 + 5323 .set CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC, 0x00000002 + 5324 .set CYVAL_UDB_PA_IN_SYNC5_RSVD, 0x00000003 + 5325 .set CYFLD_UDB_PA_IN_SYNC6__OFFSET, 0x00000004 + 5326 .set CYFLD_UDB_PA_IN_SYNC6__SIZE, 0x00000002 + 5327 .set CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT, 0x00000000 + 5328 .set CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC, 0x00000001 + 5329 .set CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC, 0x00000002 + 5330 .set CYVAL_UDB_PA_IN_SYNC6_RSVD, 0x00000003 + 5331 .set CYFLD_UDB_PA_IN_SYNC7__OFFSET, 0x00000006 + 5332 .set CYFLD_UDB_PA_IN_SYNC7__SIZE, 0x00000002 + 5333 .set CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT, 0x00000000 + 5334 .set CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC, 0x00000001 + 5335 .set CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC, 0x00000002 + 5336 .set CYVAL_UDB_PA_IN_SYNC7_RSVD, 0x00000003 + 5337 .set CYREG_UDB_PA0_CFG8, 0x400f5008 + 5338 .set CYFLD_UDB_PA_OUT_SYNC0__OFFSET, 0x00000000 + 5339 .set CYFLD_UDB_PA_OUT_SYNC0__SIZE, 0x00000002 + 5340 .set CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT, 0x00000000 + 5341 .set CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC, 0x00000001 + 5342 .set CYVAL_UDB_PA_OUT_SYNC0_CLOCK, 0x00000002 + 5343 .set CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV, 0x00000003 + 5344 .set CYFLD_UDB_PA_OUT_SYNC1__OFFSET, 0x00000002 + 5345 .set CYFLD_UDB_PA_OUT_SYNC1__SIZE, 0x00000002 + 5346 .set CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT, 0x00000000 + 5347 .set CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC, 0x00000001 + 5348 .set CYVAL_UDB_PA_OUT_SYNC1_CLOCK, 0x00000002 + 5349 .set CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV, 0x00000003 + 5350 .set CYFLD_UDB_PA_OUT_SYNC2__OFFSET, 0x00000004 + 5351 .set CYFLD_UDB_PA_OUT_SYNC2__SIZE, 0x00000002 + 5352 .set CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT, 0x00000000 + 5353 .set CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC, 0x00000001 + 5354 .set CYVAL_UDB_PA_OUT_SYNC2_CLOCK, 0x00000002 + 5355 .set CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV, 0x00000003 + 5356 .set CYFLD_UDB_PA_OUT_SYNC3__OFFSET, 0x00000006 + 5357 .set CYFLD_UDB_PA_OUT_SYNC3__SIZE, 0x00000002 + 5358 .set CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT, 0x00000000 + 5359 .set CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC, 0x00000001 + 5360 .set CYVAL_UDB_PA_OUT_SYNC3_CLOCK, 0x00000002 + 5361 .set CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV, 0x00000003 + 5362 .set CYREG_UDB_PA0_CFG9, 0x400f5009 + 5363 .set CYFLD_UDB_PA_OUT_SYNC4__OFFSET, 0x00000000 + 5364 .set CYFLD_UDB_PA_OUT_SYNC4__SIZE, 0x00000002 + 5365 .set CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT, 0x00000000 + 5366 .set CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC, 0x00000001 + 5367 .set CYVAL_UDB_PA_OUT_SYNC4_CLOCK, 0x00000002 + 5368 .set CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV, 0x00000003 + 5369 .set CYFLD_UDB_PA_OUT_SYNC5__OFFSET, 0x00000002 + 5370 .set CYFLD_UDB_PA_OUT_SYNC5__SIZE, 0x00000002 + 5371 .set CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT, 0x00000000 + 5372 .set CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC, 0x00000001 + 5373 .set CYVAL_UDB_PA_OUT_SYNC5_CLOCK, 0x00000002 + 5374 .set CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV, 0x00000003 + 5375 .set CYFLD_UDB_PA_OUT_SYNC6__OFFSET, 0x00000004 + 5376 .set CYFLD_UDB_PA_OUT_SYNC6__SIZE, 0x00000002 + 5377 .set CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT, 0x00000000 + 5378 .set CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 96 + + + 5379 .set CYVAL_UDB_PA_OUT_SYNC6_CLOCK, 0x00000002 + 5380 .set CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV, 0x00000003 + 5381 .set CYFLD_UDB_PA_OUT_SYNC7__OFFSET, 0x00000006 + 5382 .set CYFLD_UDB_PA_OUT_SYNC7__SIZE, 0x00000002 + 5383 .set CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT, 0x00000000 + 5384 .set CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC, 0x00000001 + 5385 .set CYVAL_UDB_PA_OUT_SYNC7_CLOCK, 0x00000002 + 5386 .set CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV, 0x00000003 + 5387 .set CYREG_UDB_PA0_CFG10, 0x400f500a + 5388 .set CYFLD_UDB_PA_DATA_SEL0__OFFSET, 0x00000000 + 5389 .set CYFLD_UDB_PA_DATA_SEL0__SIZE, 0x00000002 + 5390 .set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0, 0x00000000 + 5391 .set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1, 0x00000001 + 5392 .set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2, 0x00000002 + 5393 .set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3, 0x00000003 + 5394 .set CYFLD_UDB_PA_DATA_SEL1__OFFSET, 0x00000002 + 5395 .set CYFLD_UDB_PA_DATA_SEL1__SIZE, 0x00000002 + 5396 .set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0, 0x00000000 + 5397 .set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1, 0x00000001 + 5398 .set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2, 0x00000002 + 5399 .set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3, 0x00000003 + 5400 .set CYFLD_UDB_PA_DATA_SEL2__OFFSET, 0x00000004 + 5401 .set CYFLD_UDB_PA_DATA_SEL2__SIZE, 0x00000002 + 5402 .set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0, 0x00000000 + 5403 .set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1, 0x00000001 + 5404 .set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2, 0x00000002 + 5405 .set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3, 0x00000003 + 5406 .set CYFLD_UDB_PA_DATA_SEL3__OFFSET, 0x00000006 + 5407 .set CYFLD_UDB_PA_DATA_SEL3__SIZE, 0x00000002 + 5408 .set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0, 0x00000000 + 5409 .set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1, 0x00000001 + 5410 .set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2, 0x00000002 + 5411 .set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3, 0x00000003 + 5412 .set CYREG_UDB_PA0_CFG11, 0x400f500b + 5413 .set CYFLD_UDB_PA_DATA_SEL4__OFFSET, 0x00000000 + 5414 .set CYFLD_UDB_PA_DATA_SEL4__SIZE, 0x00000002 + 5415 .set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0, 0x00000000 + 5416 .set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1, 0x00000001 + 5417 .set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2, 0x00000002 + 5418 .set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3, 0x00000003 + 5419 .set CYFLD_UDB_PA_DATA_SEL5__OFFSET, 0x00000002 + 5420 .set CYFLD_UDB_PA_DATA_SEL5__SIZE, 0x00000002 + 5421 .set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0, 0x00000000 + 5422 .set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1, 0x00000001 + 5423 .set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2, 0x00000002 + 5424 .set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3, 0x00000003 + 5425 .set CYFLD_UDB_PA_DATA_SEL6__OFFSET, 0x00000004 + 5426 .set CYFLD_UDB_PA_DATA_SEL6__SIZE, 0x00000002 + 5427 .set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0, 0x00000000 + 5428 .set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1, 0x00000001 + 5429 .set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2, 0x00000002 + 5430 .set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3, 0x00000003 + 5431 .set CYFLD_UDB_PA_DATA_SEL7__OFFSET, 0x00000006 + 5432 .set CYFLD_UDB_PA_DATA_SEL7__SIZE, 0x00000002 + 5433 .set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0, 0x00000000 + 5434 .set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1, 0x00000001 + 5435 .set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2, 0x00000002 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 97 + + + 5436 .set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3, 0x00000003 + 5437 .set CYREG_UDB_PA0_CFG12, 0x400f500c + 5438 .set CYFLD_UDB_PA_OE_SEL0__OFFSET, 0x00000000 + 5439 .set CYFLD_UDB_PA_OE_SEL0__SIZE, 0x00000002 + 5440 .set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0, 0x00000000 + 5441 .set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1, 0x00000001 + 5442 .set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2, 0x00000002 + 5443 .set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3, 0x00000003 + 5444 .set CYFLD_UDB_PA_OE_SEL1__OFFSET, 0x00000002 + 5445 .set CYFLD_UDB_PA_OE_SEL1__SIZE, 0x00000002 + 5446 .set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0, 0x00000000 + 5447 .set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1, 0x00000001 + 5448 .set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2, 0x00000002 + 5449 .set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3, 0x00000003 + 5450 .set CYFLD_UDB_PA_OE_SEL2__OFFSET, 0x00000004 + 5451 .set CYFLD_UDB_PA_OE_SEL2__SIZE, 0x00000002 + 5452 .set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0, 0x00000000 + 5453 .set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1, 0x00000001 + 5454 .set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2, 0x00000002 + 5455 .set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3, 0x00000003 + 5456 .set CYFLD_UDB_PA_OE_SEL3__OFFSET, 0x00000006 + 5457 .set CYFLD_UDB_PA_OE_SEL3__SIZE, 0x00000002 + 5458 .set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0, 0x00000000 + 5459 .set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1, 0x00000001 + 5460 .set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2, 0x00000002 + 5461 .set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3, 0x00000003 + 5462 .set CYREG_UDB_PA0_CFG13, 0x400f500d + 5463 .set CYFLD_UDB_PA_OE_SEL4__OFFSET, 0x00000000 + 5464 .set CYFLD_UDB_PA_OE_SEL4__SIZE, 0x00000002 + 5465 .set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0, 0x00000000 + 5466 .set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1, 0x00000001 + 5467 .set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2, 0x00000002 + 5468 .set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3, 0x00000003 + 5469 .set CYFLD_UDB_PA_OE_SEL5__OFFSET, 0x00000002 + 5470 .set CYFLD_UDB_PA_OE_SEL5__SIZE, 0x00000002 + 5471 .set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0, 0x00000000 + 5472 .set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1, 0x00000001 + 5473 .set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2, 0x00000002 + 5474 .set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3, 0x00000003 + 5475 .set CYFLD_UDB_PA_OE_SEL6__OFFSET, 0x00000004 + 5476 .set CYFLD_UDB_PA_OE_SEL6__SIZE, 0x00000002 + 5477 .set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0, 0x00000000 + 5478 .set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1, 0x00000001 + 5479 .set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2, 0x00000002 + 5480 .set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3, 0x00000003 + 5481 .set CYFLD_UDB_PA_OE_SEL7__OFFSET, 0x00000006 + 5482 .set CYFLD_UDB_PA_OE_SEL7__SIZE, 0x00000002 + 5483 .set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0, 0x00000000 + 5484 .set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1, 0x00000001 + 5485 .set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2, 0x00000002 + 5486 .set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3, 0x00000003 + 5487 .set CYREG_UDB_PA0_CFG14, 0x400f500e + 5488 .set CYFLD_UDB_PA_OE_SYNC0__OFFSET, 0x00000000 + 5489 .set CYFLD_UDB_PA_OE_SYNC0__SIZE, 0x00000002 + 5490 .set CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT, 0x00000000 + 5491 .set CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC, 0x00000001 + 5492 .set CYVAL_UDB_PA_OE_SYNC0_CONSTANT1, 0x00000002 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 98 + + + 5493 .set CYVAL_UDB_PA_OE_SYNC0_CONSTANT0, 0x00000003 + 5494 .set CYFLD_UDB_PA_OE_SYNC1__OFFSET, 0x00000002 + 5495 .set CYFLD_UDB_PA_OE_SYNC1__SIZE, 0x00000002 + 5496 .set CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT, 0x00000000 + 5497 .set CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC, 0x00000001 + 5498 .set CYVAL_UDB_PA_OE_SYNC1_CONSTANT1, 0x00000002 + 5499 .set CYVAL_UDB_PA_OE_SYNC1_CONSTANT0, 0x00000003 + 5500 .set CYFLD_UDB_PA_OE_SYNC2__OFFSET, 0x00000004 + 5501 .set CYFLD_UDB_PA_OE_SYNC2__SIZE, 0x00000002 + 5502 .set CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT, 0x00000000 + 5503 .set CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC, 0x00000001 + 5504 .set CYVAL_UDB_PA_OE_SYNC2_CONSTANT1, 0x00000002 + 5505 .set CYVAL_UDB_PA_OE_SYNC2_CONSTANT0, 0x00000003 + 5506 .set CYFLD_UDB_PA_OE_SYNC3__OFFSET, 0x00000006 + 5507 .set CYFLD_UDB_PA_OE_SYNC3__SIZE, 0x00000002 + 5508 .set CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT, 0x00000000 + 5509 .set CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC, 0x00000001 + 5510 .set CYVAL_UDB_PA_OE_SYNC3_CONSTANT1, 0x00000002 + 5511 .set CYVAL_UDB_PA_OE_SYNC3_CONSTANT0, 0x00000003 + 5512 .set CYDEV_UDB_PA1_BASE, 0x400f5010 + 5513 .set CYDEV_UDB_PA1_SIZE, 0x00000010 + 5514 .set CYREG_UDB_PA1_CFG0, 0x400f5010 + 5515 .set CYREG_UDB_PA1_CFG1, 0x400f5011 + 5516 .set CYREG_UDB_PA1_CFG2, 0x400f5012 + 5517 .set CYREG_UDB_PA1_CFG3, 0x400f5013 + 5518 .set CYREG_UDB_PA1_CFG4, 0x400f5014 + 5519 .set CYREG_UDB_PA1_CFG5, 0x400f5015 + 5520 .set CYREG_UDB_PA1_CFG6, 0x400f5016 + 5521 .set CYREG_UDB_PA1_CFG7, 0x400f5017 + 5522 .set CYREG_UDB_PA1_CFG8, 0x400f5018 + 5523 .set CYREG_UDB_PA1_CFG9, 0x400f5019 + 5524 .set CYREG_UDB_PA1_CFG10, 0x400f501a + 5525 .set CYREG_UDB_PA1_CFG11, 0x400f501b + 5526 .set CYREG_UDB_PA1_CFG12, 0x400f501c + 5527 .set CYREG_UDB_PA1_CFG13, 0x400f501d + 5528 .set CYREG_UDB_PA1_CFG14, 0x400f501e + 5529 .set CYDEV_UDB_PA2_BASE, 0x400f5020 + 5530 .set CYDEV_UDB_PA2_SIZE, 0x00000010 + 5531 .set CYREG_UDB_PA2_CFG0, 0x400f5020 + 5532 .set CYREG_UDB_PA2_CFG1, 0x400f5021 + 5533 .set CYREG_UDB_PA2_CFG2, 0x400f5022 + 5534 .set CYREG_UDB_PA2_CFG3, 0x400f5023 + 5535 .set CYREG_UDB_PA2_CFG4, 0x400f5024 + 5536 .set CYREG_UDB_PA2_CFG5, 0x400f5025 + 5537 .set CYREG_UDB_PA2_CFG6, 0x400f5026 + 5538 .set CYREG_UDB_PA2_CFG7, 0x400f5027 + 5539 .set CYREG_UDB_PA2_CFG8, 0x400f5028 + 5540 .set CYREG_UDB_PA2_CFG9, 0x400f5029 + 5541 .set CYREG_UDB_PA2_CFG10, 0x400f502a + 5542 .set CYREG_UDB_PA2_CFG11, 0x400f502b + 5543 .set CYREG_UDB_PA2_CFG12, 0x400f502c + 5544 .set CYREG_UDB_PA2_CFG13, 0x400f502d + 5545 .set CYREG_UDB_PA2_CFG14, 0x400f502e + 5546 .set CYDEV_UDB_PA3_BASE, 0x400f5030 + 5547 .set CYDEV_UDB_PA3_SIZE, 0x00000010 + 5548 .set CYREG_UDB_PA3_CFG0, 0x400f5030 + 5549 .set CYREG_UDB_PA3_CFG1, 0x400f5031 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 99 + + + 5550 .set CYREG_UDB_PA3_CFG2, 0x400f5032 + 5551 .set CYREG_UDB_PA3_CFG3, 0x400f5033 + 5552 .set CYREG_UDB_PA3_CFG4, 0x400f5034 + 5553 .set CYREG_UDB_PA3_CFG5, 0x400f5035 + 5554 .set CYREG_UDB_PA3_CFG6, 0x400f5036 + 5555 .set CYREG_UDB_PA3_CFG7, 0x400f5037 + 5556 .set CYREG_UDB_PA3_CFG8, 0x400f5038 + 5557 .set CYREG_UDB_PA3_CFG9, 0x400f5039 + 5558 .set CYREG_UDB_PA3_CFG10, 0x400f503a + 5559 .set CYREG_UDB_PA3_CFG11, 0x400f503b + 5560 .set CYREG_UDB_PA3_CFG12, 0x400f503c + 5561 .set CYREG_UDB_PA3_CFG13, 0x400f503d + 5562 .set CYREG_UDB_PA3_CFG14, 0x400f503e + 5563 .set CYDEV_UDB_BCTL0_BASE, 0x400f6000 + 5564 .set CYDEV_UDB_BCTL0_SIZE, 0x00001000 + 5565 .set CYREG_UDB_BCTL0_DRV, 0x400f6000 + 5566 .set CYFLD_UDB_BCTL0_DRV__OFFSET, 0x00000000 + 5567 .set CYFLD_UDB_BCTL0_DRV__SIZE, 0x00000008 + 5568 .set CYVAL_UDB_BCTL0_DRV_DISABLE, 0x00000000 + 5569 .set CYVAL_UDB_BCTL0_DRV_ENABLE, 0x00000001 + 5570 .set CYREG_UDB_BCTL0_MDCLK_EN, 0x400f6001 + 5571 .set CYFLD_UDB_BCTL0_DCEN__OFFSET, 0x00000000 + 5572 .set CYFLD_UDB_BCTL0_DCEN__SIZE, 0x00000008 + 5573 .set CYVAL_UDB_BCTL0_DCEN_DISABLE, 0x00000000 + 5574 .set CYVAL_UDB_BCTL0_DCEN_ENABLE, 0x00000001 + 5575 .set CYREG_UDB_BCTL0_MBCLK_EN, 0x400f6002 + 5576 .set CYFLD_UDB_BCTL0_BCEN__OFFSET, 0x00000000 + 5577 .set CYFLD_UDB_BCTL0_BCEN__SIZE, 0x00000001 + 5578 .set CYVAL_UDB_BCTL0_BCEN_DISABLE, 0x00000000 + 5579 .set CYVAL_UDB_BCTL0_BCEN_ENABLE, 0x00000001 + 5580 .set CYREG_UDB_BCTL0_BOTSEL_L, 0x400f6008 + 5581 .set CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET, 0x00000000 + 5582 .set CYFLD_UDB_BCTL0_CLK_SEL0__SIZE, 0x00000002 + 5583 .set CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES, 0x00000000 + 5584 .set CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT, 0x00000001 + 5585 .set CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT, 0x00000002 + 5586 .set CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT, 0x00000003 + 5587 .set CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET, 0x00000002 + 5588 .set CYFLD_UDB_BCTL0_CLK_SEL1__SIZE, 0x00000002 + 5589 .set CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES, 0x00000000 + 5590 .set CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT, 0x00000001 + 5591 .set CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT, 0x00000002 + 5592 .set CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT, 0x00000003 + 5593 .set CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET, 0x00000004 + 5594 .set CYFLD_UDB_BCTL0_CLK_SEL2__SIZE, 0x00000002 + 5595 .set CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES, 0x00000000 + 5596 .set CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT, 0x00000001 + 5597 .set CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT, 0x00000002 + 5598 .set CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT, 0x00000003 + 5599 .set CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET, 0x00000006 + 5600 .set CYFLD_UDB_BCTL0_CLK_SEL3__SIZE, 0x00000002 + 5601 .set CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES, 0x00000000 + 5602 .set CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT, 0x00000001 + 5603 .set CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT, 0x00000002 + 5604 .set CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT, 0x00000003 + 5605 .set CYREG_UDB_BCTL0_BOTSEL_U, 0x400f6009 + 5606 .set CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 100 + + + 5607 .set CYFLD_UDB_BCTL0_CLK_SEL4__SIZE, 0x00000002 + 5608 .set CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES, 0x00000000 + 5609 .set CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT, 0x00000001 + 5610 .set CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT, 0x00000002 + 5611 .set CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT, 0x00000003 + 5612 .set CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET, 0x00000002 + 5613 .set CYFLD_UDB_BCTL0_CLK_SEL5__SIZE, 0x00000002 + 5614 .set CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES, 0x00000000 + 5615 .set CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT, 0x00000001 + 5616 .set CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT, 0x00000002 + 5617 .set CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT, 0x00000003 + 5618 .set CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET, 0x00000004 + 5619 .set CYFLD_UDB_BCTL0_CLK_SEL6__SIZE, 0x00000002 + 5620 .set CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES, 0x00000000 + 5621 .set CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT, 0x00000001 + 5622 .set CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT, 0x00000002 + 5623 .set CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT, 0x00000003 + 5624 .set CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET, 0x00000006 + 5625 .set CYFLD_UDB_BCTL0_CLK_SEL7__SIZE, 0x00000002 + 5626 .set CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES, 0x00000000 + 5627 .set CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT, 0x00000001 + 5628 .set CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT, 0x00000002 + 5629 .set CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT, 0x00000003 + 5630 .set CYREG_UDB_BCTL0_TOPSEL_L, 0x400f600a + 5631 .set CYREG_UDB_BCTL0_TOPSEL_U, 0x400f600b + 5632 .set CYREG_UDB_BCTL0_QCLK_EN0, 0x400f6010 + 5633 .set CYFLD_UDB_BCTL0_DCEN_Q__OFFSET, 0x00000000 + 5634 .set CYFLD_UDB_BCTL0_DCEN_Q__SIZE, 0x00000008 + 5635 .set CYVAL_UDB_BCTL0_DCEN_Q_DISABLE, 0x00000000 + 5636 .set CYVAL_UDB_BCTL0_DCEN_Q_ENABLE, 0x00000001 + 5637 .set CYFLD_UDB_BCTL0_BCEN_Q__OFFSET, 0x00000008 + 5638 .set CYFLD_UDB_BCTL0_BCEN_Q__SIZE, 0x00000001 + 5639 .set CYVAL_UDB_BCTL0_BCEN_Q_DISABLE, 0x00000000 + 5640 .set CYVAL_UDB_BCTL0_BCEN_Q_ENABLE, 0x00000001 + 5641 .set CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET, 0x00000009 + 5642 .set CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE, 0x00000001 + 5643 .set CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE, 0x00000000 + 5644 .set CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE, 0x00000001 + 5645 .set CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET, 0x0000000a + 5646 .set CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE, 0x00000001 + 5647 .set CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE, 0x00000000 + 5648 .set CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE, 0x00000001 + 5649 .set CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET, 0x0000000b + 5650 .set CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE, 0x00000001 + 5651 .set CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE, 0x00000000 + 5652 .set CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE, 0x00000001 + 5653 .set CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET, 0x0000000c + 5654 .set CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE, 0x00000001 + 5655 .set CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE, 0x00000000 + 5656 .set CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE, 0x00000001 + 5657 .set CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET, 0x0000000d + 5658 .set CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE, 0x00000001 + 5659 .set CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB, 0x00000000 + 5660 .set CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB, 0x00000001 + 5661 .set CYFLD_UDB_BCTL0_NC0__OFFSET, 0x0000000e + 5662 .set CYFLD_UDB_BCTL0_NC0__SIZE, 0x00000001 + 5663 .set CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET, 0x0000000f + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 101 + + + 5664 .set CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE, 0x00000001 + 5665 .set CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE, 0x00000000 + 5666 .set CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE, 0x00000001 + 5667 .set CYREG_UDB_BCTL0_QCLK_EN1, 0x400f6012 + 5668 .set CYDEV_UDB_UDBIF_BASE, 0x400f7000 + 5669 .set CYDEV_UDB_UDBIF_SIZE, 0x00001000 + 5670 .set CYREG_UDB_UDBIF_BANK_CTL, 0x400f7000 + 5671 .set CYFLD_UDB_UDBIF_DIS_COR__OFFSET, 0x00000000 + 5672 .set CYFLD_UDB_UDBIF_DIS_COR__SIZE, 0x00000001 + 5673 .set CYVAL_UDB_UDBIF_DIS_COR_NORMAL, 0x00000000 + 5674 .set CYVAL_UDB_UDBIF_DIS_COR_DISABLE, 0x00000001 + 5675 .set CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET, 0x00000001 + 5676 .set CYFLD_UDB_UDBIF_ROUTE_EN__SIZE, 0x00000001 + 5677 .set CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE, 0x00000000 + 5678 .set CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE, 0x00000001 + 5679 .set CYFLD_UDB_UDBIF_BANK_EN__OFFSET, 0x00000002 + 5680 .set CYFLD_UDB_UDBIF_BANK_EN__SIZE, 0x00000001 + 5681 .set CYVAL_UDB_UDBIF_BANK_EN_DISABLE, 0x00000000 + 5682 .set CYVAL_UDB_UDBIF_BANK_EN_ENABLE, 0x00000001 + 5683 .set CYFLD_UDB_UDBIF_LOCK__OFFSET, 0x00000003 + 5684 .set CYFLD_UDB_UDBIF_LOCK__SIZE, 0x00000001 + 5685 .set CYVAL_UDB_UDBIF_LOCK_MUTABLE, 0x00000000 + 5686 .set CYVAL_UDB_UDBIF_LOCK_LOCKED, 0x00000001 + 5687 .set CYFLD_UDB_UDBIF_PIPE__OFFSET, 0x00000004 + 5688 .set CYFLD_UDB_UDBIF_PIPE__SIZE, 0x00000001 + 5689 .set CYVAL_UDB_UDBIF_PIPE_BYPASS, 0x00000000 + 5690 .set CYVAL_UDB_UDBIF_PIPE_PIPELINED, 0x00000001 + 5691 .set CYFLD_UDB_UDBIF_GLBL_WR__OFFSET, 0x00000007 + 5692 .set CYFLD_UDB_UDBIF_GLBL_WR__SIZE, 0x00000001 + 5693 .set CYVAL_UDB_UDBIF_GLBL_WR_DISABLE, 0x00000000 + 5694 .set CYVAL_UDB_UDBIF_GLBL_WR_ENABLE, 0x00000001 + 5695 .set CYREG_UDB_UDBIF_WAIT_CFG, 0x400f7001 + 5696 .set CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET, 0x00000000 + 5697 .set CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE, 0x00000002 + 5698 .set CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS, 0x00000000 + 5699 .set CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS, 0x00000001 + 5700 .set CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS, 0x00000002 + 5701 .set CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT, 0x00000003 + 5702 .set CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET, 0x00000002 + 5703 .set CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE, 0x00000002 + 5704 .set CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT, 0x00000000 + 5705 .set CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS, 0x00000001 + 5706 .set CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS, 0x00000002 + 5707 .set CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS, 0x00000003 + 5708 .set CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET, 0x00000004 + 5709 .set CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE, 0x00000002 + 5710 .set CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT, 0x00000000 + 5711 .set CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS, 0x00000001 + 5712 .set CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS, 0x00000002 + 5713 .set CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS, 0x00000003 + 5714 .set CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET, 0x00000006 + 5715 .set CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE, 0x00000002 + 5716 .set CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT, 0x00000000 + 5717 .set CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS, 0x00000001 + 5718 .set CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS, 0x00000002 + 5719 .set CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS, 0x00000003 + 5720 .set CYREG_UDB_UDBIF_INT_CLK_CTL, 0x400f701c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 102 + + + 5721 .set CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET, 0x00000000 + 5722 .set CYFLD_UDB_UDBIF_EN_HFCLK__SIZE, 0x00000001 + 5723 .set CYREG_UDB_INT_CFG, 0x400f8000 + 5724 .set CYFLD_UDB_INT_MODE_CFG__OFFSET, 0x00000000 + 5725 .set CYFLD_UDB_INT_MODE_CFG__SIZE, 0x00000020 + 5726 .set CYVAL_UDB_INT_MODE_CFG_LEVEL, 0x00000000 + 5727 .set CYVAL_UDB_INT_MODE_CFG_PULSE, 0x00000001 + 5728 .set CYDEV_CTBM_BASE, 0x40100000 + 5729 .set CYDEV_CTBM_SIZE, 0x00010000 + 5730 .set CYREG_CTBM_CTB_CTRL, 0x40100000 + 5731 .set CYFLD_CTBM_ENABLED__OFFSET, 0x0000001f + 5732 .set CYFLD_CTBM_ENABLED__SIZE, 0x00000001 + 5733 .set CYREG_CTBM_OA_RES0_CTRL, 0x40100004 + 5734 .set CYFLD_CTBM_OA0_PWR_MODE__OFFSET, 0x00000000 + 5735 .set CYFLD_CTBM_OA0_PWR_MODE__SIZE, 0x00000002 + 5736 .set CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET, 0x00000002 + 5737 .set CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE, 0x00000001 + 5738 .set CYFLD_CTBM_OA0_COMP_EN__OFFSET, 0x00000004 + 5739 .set CYFLD_CTBM_OA0_COMP_EN__SIZE, 0x00000001 + 5740 .set CYFLD_CTBM_OA0_HYST_EN__OFFSET, 0x00000005 + 5741 .set CYFLD_CTBM_OA0_HYST_EN__SIZE, 0x00000001 + 5742 .set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET, 0x00000006 + 5743 .set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE, 0x00000001 + 5744 .set CYFLD_CTBM_OA0_COMPINT__OFFSET, 0x00000008 + 5745 .set CYFLD_CTBM_OA0_COMPINT__SIZE, 0x00000002 + 5746 .set CYVAL_CTBM_OA0_COMPINT_DISABLE, 0x00000000 + 5747 .set CYVAL_CTBM_OA0_COMPINT_RISING, 0x00000001 + 5748 .set CYVAL_CTBM_OA0_COMPINT_FALLING, 0x00000002 + 5749 .set CYVAL_CTBM_OA0_COMPINT_BOTH, 0x00000003 + 5750 .set CYFLD_CTBM_OA0_PUMP_EN__OFFSET, 0x0000000b + 5751 .set CYFLD_CTBM_OA0_PUMP_EN__SIZE, 0x00000001 + 5752 .set CYREG_CTBM_OA_RES1_CTRL, 0x40100008 + 5753 .set CYFLD_CTBM_OA1_PWR_MODE__OFFSET, 0x00000000 + 5754 .set CYFLD_CTBM_OA1_PWR_MODE__SIZE, 0x00000002 + 5755 .set CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET, 0x00000002 + 5756 .set CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE, 0x00000001 + 5757 .set CYFLD_CTBM_OA1_COMP_EN__OFFSET, 0x00000004 + 5758 .set CYFLD_CTBM_OA1_COMP_EN__SIZE, 0x00000001 + 5759 .set CYFLD_CTBM_OA1_HYST_EN__OFFSET, 0x00000005 + 5760 .set CYFLD_CTBM_OA1_HYST_EN__SIZE, 0x00000001 + 5761 .set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET, 0x00000006 + 5762 .set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE, 0x00000001 + 5763 .set CYFLD_CTBM_OA1_COMPINT__OFFSET, 0x00000008 + 5764 .set CYFLD_CTBM_OA1_COMPINT__SIZE, 0x00000002 + 5765 .set CYVAL_CTBM_OA1_COMPINT_DISABLE, 0x00000000 + 5766 .set CYVAL_CTBM_OA1_COMPINT_RISING, 0x00000001 + 5767 .set CYVAL_CTBM_OA1_COMPINT_FALLING, 0x00000002 + 5768 .set CYVAL_CTBM_OA1_COMPINT_BOTH, 0x00000003 + 5769 .set CYFLD_CTBM_OA1_PUMP_EN__OFFSET, 0x0000000b + 5770 .set CYFLD_CTBM_OA1_PUMP_EN__SIZE, 0x00000001 + 5771 .set CYREG_CTBM_COMP_STAT, 0x4010000c + 5772 .set CYFLD_CTBM_OA0_COMP__OFFSET, 0x00000000 + 5773 .set CYFLD_CTBM_OA0_COMP__SIZE, 0x00000001 + 5774 .set CYFLD_CTBM_OA1_COMP__OFFSET, 0x00000010 + 5775 .set CYFLD_CTBM_OA1_COMP__SIZE, 0x00000001 + 5776 .set CYREG_CTBM_INTR, 0x40100020 + 5777 .set CYFLD_CTBM_COMP0__OFFSET, 0x00000000 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 103 + + + 5778 .set CYFLD_CTBM_COMP0__SIZE, 0x00000001 + 5779 .set CYFLD_CTBM_COMP1__OFFSET, 0x00000001 + 5780 .set CYFLD_CTBM_COMP1__SIZE, 0x00000001 + 5781 .set CYREG_CTBM_INTR_SET, 0x40100024 + 5782 .set CYFLD_CTBM_COMP0_SET__OFFSET, 0x00000000 + 5783 .set CYFLD_CTBM_COMP0_SET__SIZE, 0x00000001 + 5784 .set CYFLD_CTBM_COMP1_SET__OFFSET, 0x00000001 + 5785 .set CYFLD_CTBM_COMP1_SET__SIZE, 0x00000001 + 5786 .set CYREG_CTBM_INTR_MASK, 0x40100028 + 5787 .set CYFLD_CTBM_COMP0_MASK__OFFSET, 0x00000000 + 5788 .set CYFLD_CTBM_COMP0_MASK__SIZE, 0x00000001 + 5789 .set CYFLD_CTBM_COMP1_MASK__OFFSET, 0x00000001 + 5790 .set CYFLD_CTBM_COMP1_MASK__SIZE, 0x00000001 + 5791 .set CYREG_CTBM_INTR_MASKED, 0x4010002c + 5792 .set CYFLD_CTBM_COMP0_MASKED__OFFSET, 0x00000000 + 5793 .set CYFLD_CTBM_COMP0_MASKED__SIZE, 0x00000001 + 5794 .set CYFLD_CTBM_COMP1_MASKED__OFFSET, 0x00000001 + 5795 .set CYFLD_CTBM_COMP1_MASKED__SIZE, 0x00000001 + 5796 .set CYREG_CTBM_DFT_CTRL, 0x40100030 + 5797 .set CYFLD_CTBM_DFT_MODE__OFFSET, 0x00000000 + 5798 .set CYFLD_CTBM_DFT_MODE__SIZE, 0x00000003 + 5799 .set CYFLD_CTBM_DFT_EN__OFFSET, 0x0000001f + 5800 .set CYFLD_CTBM_DFT_EN__SIZE, 0x00000001 + 5801 .set CYREG_CTBM_OA0_SW, 0x40100080 + 5802 .set CYFLD_CTBM_OA0P_A00__OFFSET, 0x00000000 + 5803 .set CYFLD_CTBM_OA0P_A00__SIZE, 0x00000001 + 5804 .set CYFLD_CTBM_OA0P_A20__OFFSET, 0x00000002 + 5805 .set CYFLD_CTBM_OA0P_A20__SIZE, 0x00000001 + 5806 .set CYFLD_CTBM_OA0P_A30__OFFSET, 0x00000003 + 5807 .set CYFLD_CTBM_OA0P_A30__SIZE, 0x00000001 + 5808 .set CYFLD_CTBM_OA0M_A11__OFFSET, 0x00000008 + 5809 .set CYFLD_CTBM_OA0M_A11__SIZE, 0x00000001 + 5810 .set CYFLD_CTBM_OA0M_A81__OFFSET, 0x0000000e + 5811 .set CYFLD_CTBM_OA0M_A81__SIZE, 0x00000001 + 5812 .set CYFLD_CTBM_OA0O_D51__OFFSET, 0x00000012 + 5813 .set CYFLD_CTBM_OA0O_D51__SIZE, 0x00000001 + 5814 .set CYFLD_CTBM_OA0O_D81__OFFSET, 0x00000015 + 5815 .set CYFLD_CTBM_OA0O_D81__SIZE, 0x00000001 + 5816 .set CYREG_CTBM_OA0_SW_CLEAR, 0x40100084 + 5817 .set CYREG_CTBM_OA1_SW, 0x40100088 + 5818 .set CYFLD_CTBM_OA1P_A03__OFFSET, 0x00000000 + 5819 .set CYFLD_CTBM_OA1P_A03__SIZE, 0x00000001 + 5820 .set CYFLD_CTBM_OA1P_A13__OFFSET, 0x00000001 + 5821 .set CYFLD_CTBM_OA1P_A13__SIZE, 0x00000001 + 5822 .set CYFLD_CTBM_OA1P_A43__OFFSET, 0x00000004 + 5823 .set CYFLD_CTBM_OA1P_A43__SIZE, 0x00000001 + 5824 .set CYFLD_CTBM_OA1M_A22__OFFSET, 0x00000008 + 5825 .set CYFLD_CTBM_OA1M_A22__SIZE, 0x00000001 + 5826 .set CYFLD_CTBM_OA1M_A82__OFFSET, 0x0000000e + 5827 .set CYFLD_CTBM_OA1M_A82__SIZE, 0x00000001 + 5828 .set CYFLD_CTBM_OA1O_D52__OFFSET, 0x00000012 + 5829 .set CYFLD_CTBM_OA1O_D52__SIZE, 0x00000001 + 5830 .set CYFLD_CTBM_OA1O_D62__OFFSET, 0x00000013 + 5831 .set CYFLD_CTBM_OA1O_D62__SIZE, 0x00000001 + 5832 .set CYFLD_CTBM_OA1O_D82__OFFSET, 0x00000015 + 5833 .set CYFLD_CTBM_OA1O_D82__SIZE, 0x00000001 + 5834 .set CYREG_CTBM_OA1_SW_CLEAR, 0x4010008c + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 104 + + + 5835 .set CYREG_CTBM_CTB_SW_HW_CTRL, 0x401000c0 + 5836 .set CYFLD_CTBM_P2_HW_CTRL__OFFSET, 0x00000002 + 5837 .set CYFLD_CTBM_P2_HW_CTRL__SIZE, 0x00000001 + 5838 .set CYFLD_CTBM_P3_HW_CTRL__OFFSET, 0x00000003 + 5839 .set CYFLD_CTBM_P3_HW_CTRL__SIZE, 0x00000001 + 5840 .set CYREG_CTBM_CTB_SW_STATUS, 0x401000c4 + 5841 .set CYFLD_CTBM_OA0O_D51_STAT__OFFSET, 0x0000001c + 5842 .set CYFLD_CTBM_OA0O_D51_STAT__SIZE, 0x00000001 + 5843 .set CYFLD_CTBM_OA1O_D52_STAT__OFFSET, 0x0000001d + 5844 .set CYFLD_CTBM_OA1O_D52_STAT__SIZE, 0x00000001 + 5845 .set CYFLD_CTBM_OA1O_D62_STAT__OFFSET, 0x0000001e + 5846 .set CYFLD_CTBM_OA1O_D62_STAT__SIZE, 0x00000001 + 5847 .set CYREG_CTBM_OA0_OFFSET_TRIM, 0x40100f00 + 5848 .set CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET, 0x00000000 + 5849 .set CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE, 0x00000006 + 5850 .set CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM, 0x40100f04 + 5851 .set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 + 5852 .set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 + 5853 .set CYREG_CTBM_OA0_COMP_TRIM, 0x40100f08 + 5854 .set CYFLD_CTBM_OA0_COMP_TRIM__OFFSET, 0x00000000 + 5855 .set CYFLD_CTBM_OA0_COMP_TRIM__SIZE, 0x00000002 + 5856 .set CYREG_CTBM_OA1_OFFSET_TRIM, 0x40100f0c + 5857 .set CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET, 0x00000000 + 5858 .set CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE, 0x00000006 + 5859 .set CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM, 0x40100f10 + 5860 .set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 + 5861 .set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 + 5862 .set CYREG_CTBM_OA1_COMP_TRIM, 0x40100f14 + 5863 .set CYFLD_CTBM_OA1_COMP_TRIM__OFFSET, 0x00000000 + 5864 .set CYFLD_CTBM_OA1_COMP_TRIM__SIZE, 0x00000002 + 5865 .set CYDEV_SAR_BASE, 0x401a0000 + 5866 .set CYDEV_SAR_SIZE, 0x00010000 + 5867 .set CYREG_SAR_CTRL, 0x401a0000 + 5868 .set CYFLD_SAR_VREF_SEL__OFFSET, 0x00000004 + 5869 .set CYFLD_SAR_VREF_SEL__SIZE, 0x00000003 + 5870 .set CYVAL_SAR_VREF_SEL_VREF0, 0x00000000 + 5871 .set CYVAL_SAR_VREF_SEL_VREF1, 0x00000001 + 5872 .set CYVAL_SAR_VREF_SEL_VREF2, 0x00000002 + 5873 .set CYVAL_SAR_VREF_SEL_VREF_AROUTE, 0x00000003 + 5874 .set CYVAL_SAR_VREF_SEL_VBGR, 0x00000004 + 5875 .set CYVAL_SAR_VREF_SEL_VREF_EXT, 0x00000005 + 5876 .set CYVAL_SAR_VREF_SEL_VDDA_DIV_2, 0x00000006 + 5877 .set CYVAL_SAR_VREF_SEL_VDDA, 0x00000007 + 5878 .set CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET, 0x00000007 + 5879 .set CYFLD_SAR_VREF_BYP_CAP_EN__SIZE, 0x00000001 + 5880 .set CYFLD_SAR_NEG_SEL__OFFSET, 0x00000009 + 5881 .set CYFLD_SAR_NEG_SEL__SIZE, 0x00000003 + 5882 .set CYVAL_SAR_NEG_SEL_VSSA_KELVIN, 0x00000000 + 5883 .set CYVAL_SAR_NEG_SEL_ART_VSSA, 0x00000001 + 5884 .set CYVAL_SAR_NEG_SEL_P1, 0x00000002 + 5885 .set CYVAL_SAR_NEG_SEL_P3, 0x00000003 + 5886 .set CYVAL_SAR_NEG_SEL_P5, 0x00000004 + 5887 .set CYVAL_SAR_NEG_SEL_P7, 0x00000005 + 5888 .set CYVAL_SAR_NEG_SEL_ACORE, 0x00000006 + 5889 .set CYVAL_SAR_NEG_SEL_VREF, 0x00000007 + 5890 .set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET, 0x0000000d + 5891 .set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 105 + + + 5892 .set CYFLD_SAR_PWR_CTRL_VREF__OFFSET, 0x0000000e + 5893 .set CYFLD_SAR_PWR_CTRL_VREF__SIZE, 0x00000002 + 5894 .set CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR, 0x00000000 + 5895 .set CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR, 0x00000001 + 5896 .set CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR, 0x00000002 + 5897 .set CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR, 0x00000003 + 5898 .set CYFLD_SAR_SPARE__OFFSET, 0x00000010 + 5899 .set CYFLD_SAR_SPARE__SIZE, 0x00000004 + 5900 .set CYFLD_SAR_ICONT_LV__OFFSET, 0x00000018 + 5901 .set CYFLD_SAR_ICONT_LV__SIZE, 0x00000002 + 5902 .set CYVAL_SAR_ICONT_LV_NORMAL_PWR, 0x00000000 + 5903 .set CYVAL_SAR_ICONT_LV_HALF_PWR, 0x00000001 + 5904 .set CYVAL_SAR_ICONT_LV_MORE_PWR, 0x00000002 + 5905 .set CYVAL_SAR_ICONT_LV_QUARTER_PWR, 0x00000003 + 5906 .set CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET, 0x0000001c + 5907 .set CYFLD_SAR_DSI_SYNC_CONFIG__SIZE, 0x00000001 + 5908 .set CYFLD_SAR_DSI_MODE__OFFSET, 0x0000001d + 5909 .set CYFLD_SAR_DSI_MODE__SIZE, 0x00000001 + 5910 .set CYFLD_SAR_SWITCH_DISABLE__OFFSET, 0x0000001e + 5911 .set CYFLD_SAR_SWITCH_DISABLE__SIZE, 0x00000001 + 5912 .set CYFLD_SAR_ENABLED__OFFSET, 0x0000001f + 5913 .set CYFLD_SAR_ENABLED__SIZE, 0x00000001 + 5914 .set CYREG_SAR_SAMPLE_CTRL, 0x401a0004 + 5915 .set CYFLD_SAR_SUB_RESOLUTION__OFFSET, 0x00000000 + 5916 .set CYFLD_SAR_SUB_RESOLUTION__SIZE, 0x00000001 + 5917 .set CYVAL_SAR_SUB_RESOLUTION_8B, 0x00000000 + 5918 .set CYVAL_SAR_SUB_RESOLUTION_10B, 0x00000001 + 5919 .set CYFLD_SAR_LEFT_ALIGN__OFFSET, 0x00000001 + 5920 .set CYFLD_SAR_LEFT_ALIGN__SIZE, 0x00000001 + 5921 .set CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET, 0x00000002 + 5922 .set CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE, 0x00000001 + 5923 .set CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED, 0x00000000 + 5924 .set CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED, 0x00000001 + 5925 .set CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET, 0x00000003 + 5926 .set CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE, 0x00000001 + 5927 .set CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED, 0x00000000 + 5928 .set CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED, 0x00000001 + 5929 .set CYFLD_SAR_AVG_CNT__OFFSET, 0x00000004 + 5930 .set CYFLD_SAR_AVG_CNT__SIZE, 0x00000003 + 5931 .set CYFLD_SAR_AVG_SHIFT__OFFSET, 0x00000007 + 5932 .set CYFLD_SAR_AVG_SHIFT__SIZE, 0x00000001 + 5933 .set CYFLD_SAR_CONTINUOUS__OFFSET, 0x00000010 + 5934 .set CYFLD_SAR_CONTINUOUS__SIZE, 0x00000001 + 5935 .set CYFLD_SAR_DSI_TRIGGER_EN__OFFSET, 0x00000011 + 5936 .set CYFLD_SAR_DSI_TRIGGER_EN__SIZE, 0x00000001 + 5937 .set CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET, 0x00000012 + 5938 .set CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE, 0x00000001 + 5939 .set CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET, 0x00000013 + 5940 .set CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE, 0x00000001 + 5941 .set CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET, 0x0000001f + 5942 .set CYFLD_SAR_EOS_DSI_OUT_EN__SIZE, 0x00000001 + 5943 .set CYREG_SAR_SAMPLE_TIME01, 0x401a0010 + 5944 .set CYFLD_SAR_SAMPLE_TIME0__OFFSET, 0x00000000 + 5945 .set CYFLD_SAR_SAMPLE_TIME0__SIZE, 0x0000000a + 5946 .set CYFLD_SAR_SAMPLE_TIME1__OFFSET, 0x00000010 + 5947 .set CYFLD_SAR_SAMPLE_TIME1__SIZE, 0x0000000a + 5948 .set CYREG_SAR_SAMPLE_TIME23, 0x401a0014 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 106 + + + 5949 .set CYFLD_SAR_SAMPLE_TIME2__OFFSET, 0x00000000 + 5950 .set CYFLD_SAR_SAMPLE_TIME2__SIZE, 0x0000000a + 5951 .set CYFLD_SAR_SAMPLE_TIME3__OFFSET, 0x00000010 + 5952 .set CYFLD_SAR_SAMPLE_TIME3__SIZE, 0x0000000a + 5953 .set CYREG_SAR_RANGE_THRES, 0x401a0018 + 5954 .set CYFLD_SAR_RANGE_LOW__OFFSET, 0x00000000 + 5955 .set CYFLD_SAR_RANGE_LOW__SIZE, 0x00000010 + 5956 .set CYFLD_SAR_RANGE_HIGH__OFFSET, 0x00000010 + 5957 .set CYFLD_SAR_RANGE_HIGH__SIZE, 0x00000010 + 5958 .set CYREG_SAR_RANGE_COND, 0x401a001c + 5959 .set CYFLD_SAR_RANGE_COND__OFFSET, 0x0000001e + 5960 .set CYFLD_SAR_RANGE_COND__SIZE, 0x00000002 + 5961 .set CYVAL_SAR_RANGE_COND_BELOW, 0x00000000 + 5962 .set CYVAL_SAR_RANGE_COND_INSIDE, 0x00000001 + 5963 .set CYVAL_SAR_RANGE_COND_ABOVE, 0x00000002 + 5964 .set CYVAL_SAR_RANGE_COND_OUTSIDE, 0x00000003 + 5965 .set CYREG_SAR_CHAN_EN, 0x401a0020 + 5966 .set CYFLD_SAR_CHAN_EN__OFFSET, 0x00000000 + 5967 .set CYFLD_SAR_CHAN_EN__SIZE, 0x00000010 + 5968 .set CYREG_SAR_START_CTRL, 0x401a0024 + 5969 .set CYFLD_SAR_FW_TRIGGER__OFFSET, 0x00000000 + 5970 .set CYFLD_SAR_FW_TRIGGER__SIZE, 0x00000001 + 5971 .set CYREG_SAR_DFT_CTRL, 0x401a0030 + 5972 .set CYFLD_SAR_DLY_INC__OFFSET, 0x00000000 + 5973 .set CYFLD_SAR_DLY_INC__SIZE, 0x00000001 + 5974 .set CYFLD_SAR_HIZ__OFFSET, 0x00000001 + 5975 .set CYFLD_SAR_HIZ__SIZE, 0x00000001 + 5976 .set CYFLD_SAR_DFT_INC__OFFSET, 0x00000010 + 5977 .set CYFLD_SAR_DFT_INC__SIZE, 0x00000004 + 5978 .set CYFLD_SAR_DFT_OUTC__OFFSET, 0x00000014 + 5979 .set CYFLD_SAR_DFT_OUTC__SIZE, 0x00000003 + 5980 .set CYFLD_SAR_SEL_CSEL_DFT__OFFSET, 0x00000018 + 5981 .set CYFLD_SAR_SEL_CSEL_DFT__SIZE, 0x00000004 + 5982 .set CYFLD_SAR_EN_CSEL_DFT__OFFSET, 0x0000001c + 5983 .set CYFLD_SAR_EN_CSEL_DFT__SIZE, 0x00000001 + 5984 .set CYFLD_SAR_DCEN__OFFSET, 0x0000001d + 5985 .set CYFLD_SAR_DCEN__SIZE, 0x00000001 + 5986 .set CYFLD_SAR_ADFT_OVERRIDE__OFFSET, 0x0000001f + 5987 .set CYFLD_SAR_ADFT_OVERRIDE__SIZE, 0x00000001 + 5988 .set CYREG_SAR_CHAN_CONFIG00, 0x401a0080 + 5989 .set CYFLD_SAR_PIN_ADDR__OFFSET, 0x00000000 + 5990 .set CYFLD_SAR_PIN_ADDR__SIZE, 0x00000003 + 5991 .set CYFLD_SAR_PORT_ADDR__OFFSET, 0x00000004 + 5992 .set CYFLD_SAR_PORT_ADDR__SIZE, 0x00000003 + 5993 .set CYVAL_SAR_PORT_ADDR_SARMUX, 0x00000000 + 5994 .set CYVAL_SAR_PORT_ADDR_CTB0, 0x00000001 + 5995 .set CYVAL_SAR_PORT_ADDR_CTB1, 0x00000002 + 5996 .set CYVAL_SAR_PORT_ADDR_CTB2, 0x00000003 + 5997 .set CYVAL_SAR_PORT_ADDR_CTB3, 0x00000004 + 5998 .set CYVAL_SAR_PORT_ADDR_AROUTE_VIRT, 0x00000006 + 5999 .set CYVAL_SAR_PORT_ADDR_SARMUX_VIRT, 0x00000007 + 6000 .set CYFLD_SAR_DIFFERENTIAL_EN__OFFSET, 0x00000008 + 6001 .set CYFLD_SAR_DIFFERENTIAL_EN__SIZE, 0x00000001 + 6002 .set CYFLD_SAR_RESOLUTION__OFFSET, 0x00000009 + 6003 .set CYFLD_SAR_RESOLUTION__SIZE, 0x00000001 + 6004 .set CYVAL_SAR_RESOLUTION_12B, 0x00000000 + 6005 .set CYVAL_SAR_RESOLUTION_SUBRES, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 107 + + + 6006 .set CYFLD_SAR_AVG_EN__OFFSET, 0x0000000a + 6007 .set CYFLD_SAR_AVG_EN__SIZE, 0x00000001 + 6008 .set CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET, 0x0000000c + 6009 .set CYFLD_SAR_SAMPLE_TIME_SEL__SIZE, 0x00000002 + 6010 .set CYFLD_SAR_DSI_OUT_EN__OFFSET, 0x0000001f + 6011 .set CYFLD_SAR_DSI_OUT_EN__SIZE, 0x00000001 + 6012 .set CYREG_SAR_CHAN_CONFIG01, 0x401a0084 + 6013 .set CYREG_SAR_CHAN_CONFIG02, 0x401a0088 + 6014 .set CYREG_SAR_CHAN_CONFIG03, 0x401a008c + 6015 .set CYREG_SAR_CHAN_CONFIG04, 0x401a0090 + 6016 .set CYREG_SAR_CHAN_CONFIG05, 0x401a0094 + 6017 .set CYREG_SAR_CHAN_CONFIG06, 0x401a0098 + 6018 .set CYREG_SAR_CHAN_CONFIG07, 0x401a009c + 6019 .set CYREG_SAR_CHAN_WORK00, 0x401a0100 + 6020 .set CYFLD_SAR_WORK__OFFSET, 0x00000000 + 6021 .set CYFLD_SAR_WORK__SIZE, 0x00000010 + 6022 .set CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET, 0x0000001f + 6023 .set CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE, 0x00000001 + 6024 .set CYREG_SAR_CHAN_WORK01, 0x401a0104 + 6025 .set CYREG_SAR_CHAN_WORK02, 0x401a0108 + 6026 .set CYREG_SAR_CHAN_WORK03, 0x401a010c + 6027 .set CYREG_SAR_CHAN_WORK04, 0x401a0110 + 6028 .set CYREG_SAR_CHAN_WORK05, 0x401a0114 + 6029 .set CYREG_SAR_CHAN_WORK06, 0x401a0118 + 6030 .set CYREG_SAR_CHAN_WORK07, 0x401a011c + 6031 .set CYREG_SAR_CHAN_RESULT00, 0x401a0180 + 6032 .set CYFLD_SAR_RESULT__OFFSET, 0x00000000 + 6033 .set CYFLD_SAR_RESULT__SIZE, 0x00000010 + 6034 .set CYFLD_SAR_SATURATE_INTR_MIR__OFFSET, 0x0000001d + 6035 .set CYFLD_SAR_SATURATE_INTR_MIR__SIZE, 0x00000001 + 6036 .set CYFLD_SAR_RANGE_INTR_MIR__OFFSET, 0x0000001e + 6037 .set CYFLD_SAR_RANGE_INTR_MIR__SIZE, 0x00000001 + 6038 .set CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET, 0x0000001f + 6039 .set CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE, 0x00000001 + 6040 .set CYREG_SAR_CHAN_RESULT01, 0x401a0184 + 6041 .set CYREG_SAR_CHAN_RESULT02, 0x401a0188 + 6042 .set CYREG_SAR_CHAN_RESULT03, 0x401a018c + 6043 .set CYREG_SAR_CHAN_RESULT04, 0x401a0190 + 6044 .set CYREG_SAR_CHAN_RESULT05, 0x401a0194 + 6045 .set CYREG_SAR_CHAN_RESULT06, 0x401a0198 + 6046 .set CYREG_SAR_CHAN_RESULT07, 0x401a019c + 6047 .set CYREG_SAR_CHAN_WORK_VALID, 0x401a0200 + 6048 .set CYFLD_SAR_CHAN_WORK_VALID__OFFSET, 0x00000000 + 6049 .set CYFLD_SAR_CHAN_WORK_VALID__SIZE, 0x00000010 + 6050 .set CYREG_SAR_CHAN_RESULT_VALID, 0x401a0204 + 6051 .set CYFLD_SAR_CHAN_RESULT_VALID__OFFSET, 0x00000000 + 6052 .set CYFLD_SAR_CHAN_RESULT_VALID__SIZE, 0x00000010 + 6053 .set CYREG_SAR_STATUS, 0x401a0208 + 6054 .set CYFLD_SAR_CUR_CHAN__OFFSET, 0x00000000 + 6055 .set CYFLD_SAR_CUR_CHAN__SIZE, 0x00000005 + 6056 .set CYFLD_SAR_SW_VREF_NEG__OFFSET, 0x0000001e + 6057 .set CYFLD_SAR_SW_VREF_NEG__SIZE, 0x00000001 + 6058 .set CYFLD_SAR_BUSY__OFFSET, 0x0000001f + 6059 .set CYFLD_SAR_BUSY__SIZE, 0x00000001 + 6060 .set CYREG_SAR_AVG_STAT, 0x401a020c + 6061 .set CYFLD_SAR_CUR_AVG_ACCU__OFFSET, 0x00000000 + 6062 .set CYFLD_SAR_CUR_AVG_ACCU__SIZE, 0x00000014 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 108 + + + 6063 .set CYFLD_SAR_CUR_AVG_CNT__OFFSET, 0x00000018 + 6064 .set CYFLD_SAR_CUR_AVG_CNT__SIZE, 0x00000008 + 6065 .set CYREG_SAR_INTR, 0x401a0210 + 6066 .set CYFLD_SAR_EOS_INTR__OFFSET, 0x00000000 + 6067 .set CYFLD_SAR_EOS_INTR__SIZE, 0x00000001 + 6068 .set CYFLD_SAR_OVERFLOW_INTR__OFFSET, 0x00000001 + 6069 .set CYFLD_SAR_OVERFLOW_INTR__SIZE, 0x00000001 + 6070 .set CYFLD_SAR_FW_COLLISION_INTR__OFFSET, 0x00000002 + 6071 .set CYFLD_SAR_FW_COLLISION_INTR__SIZE, 0x00000001 + 6072 .set CYFLD_SAR_DSI_COLLISION_INTR__OFFSET, 0x00000003 + 6073 .set CYFLD_SAR_DSI_COLLISION_INTR__SIZE, 0x00000001 + 6074 .set CYFLD_SAR_INJ_EOC_INTR__OFFSET, 0x00000004 + 6075 .set CYFLD_SAR_INJ_EOC_INTR__SIZE, 0x00000001 + 6076 .set CYFLD_SAR_INJ_SATURATE_INTR__OFFSET, 0x00000005 + 6077 .set CYFLD_SAR_INJ_SATURATE_INTR__SIZE, 0x00000001 + 6078 .set CYFLD_SAR_INJ_RANGE_INTR__OFFSET, 0x00000006 + 6079 .set CYFLD_SAR_INJ_RANGE_INTR__SIZE, 0x00000001 + 6080 .set CYFLD_SAR_INJ_COLLISION_INTR__OFFSET, 0x00000007 + 6081 .set CYFLD_SAR_INJ_COLLISION_INTR__SIZE, 0x00000001 + 6082 .set CYREG_SAR_INTR_SET, 0x401a0214 + 6083 .set CYFLD_SAR_EOS_SET__OFFSET, 0x00000000 + 6084 .set CYFLD_SAR_EOS_SET__SIZE, 0x00000001 + 6085 .set CYFLD_SAR_OVERFLOW_SET__OFFSET, 0x00000001 + 6086 .set CYFLD_SAR_OVERFLOW_SET__SIZE, 0x00000001 + 6087 .set CYFLD_SAR_FW_COLLISION_SET__OFFSET, 0x00000002 + 6088 .set CYFLD_SAR_FW_COLLISION_SET__SIZE, 0x00000001 + 6089 .set CYFLD_SAR_DSI_COLLISION_SET__OFFSET, 0x00000003 + 6090 .set CYFLD_SAR_DSI_COLLISION_SET__SIZE, 0x00000001 + 6091 .set CYFLD_SAR_INJ_EOC_SET__OFFSET, 0x00000004 + 6092 .set CYFLD_SAR_INJ_EOC_SET__SIZE, 0x00000001 + 6093 .set CYFLD_SAR_INJ_SATURATE_SET__OFFSET, 0x00000005 + 6094 .set CYFLD_SAR_INJ_SATURATE_SET__SIZE, 0x00000001 + 6095 .set CYFLD_SAR_INJ_RANGE_SET__OFFSET, 0x00000006 + 6096 .set CYFLD_SAR_INJ_RANGE_SET__SIZE, 0x00000001 + 6097 .set CYFLD_SAR_INJ_COLLISION_SET__OFFSET, 0x00000007 + 6098 .set CYFLD_SAR_INJ_COLLISION_SET__SIZE, 0x00000001 + 6099 .set CYREG_SAR_INTR_MASK, 0x401a0218 + 6100 .set CYFLD_SAR_EOS_MASK__OFFSET, 0x00000000 + 6101 .set CYFLD_SAR_EOS_MASK__SIZE, 0x00000001 + 6102 .set CYFLD_SAR_OVERFLOW_MASK__OFFSET, 0x00000001 + 6103 .set CYFLD_SAR_OVERFLOW_MASK__SIZE, 0x00000001 + 6104 .set CYFLD_SAR_FW_COLLISION_MASK__OFFSET, 0x00000002 + 6105 .set CYFLD_SAR_FW_COLLISION_MASK__SIZE, 0x00000001 + 6106 .set CYFLD_SAR_DSI_COLLISION_MASK__OFFSET, 0x00000003 + 6107 .set CYFLD_SAR_DSI_COLLISION_MASK__SIZE, 0x00000001 + 6108 .set CYFLD_SAR_INJ_EOC_MASK__OFFSET, 0x00000004 + 6109 .set CYFLD_SAR_INJ_EOC_MASK__SIZE, 0x00000001 + 6110 .set CYFLD_SAR_INJ_SATURATE_MASK__OFFSET, 0x00000005 + 6111 .set CYFLD_SAR_INJ_SATURATE_MASK__SIZE, 0x00000001 + 6112 .set CYFLD_SAR_INJ_RANGE_MASK__OFFSET, 0x00000006 + 6113 .set CYFLD_SAR_INJ_RANGE_MASK__SIZE, 0x00000001 + 6114 .set CYFLD_SAR_INJ_COLLISION_MASK__OFFSET, 0x00000007 + 6115 .set CYFLD_SAR_INJ_COLLISION_MASK__SIZE, 0x00000001 + 6116 .set CYREG_SAR_INTR_MASKED, 0x401a021c + 6117 .set CYFLD_SAR_EOS_MASKED__OFFSET, 0x00000000 + 6118 .set CYFLD_SAR_EOS_MASKED__SIZE, 0x00000001 + 6119 .set CYFLD_SAR_OVERFLOW_MASKED__OFFSET, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 109 + + + 6120 .set CYFLD_SAR_OVERFLOW_MASKED__SIZE, 0x00000001 + 6121 .set CYFLD_SAR_FW_COLLISION_MASKED__OFFSET, 0x00000002 + 6122 .set CYFLD_SAR_FW_COLLISION_MASKED__SIZE, 0x00000001 + 6123 .set CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET, 0x00000003 + 6124 .set CYFLD_SAR_DSI_COLLISION_MASKED__SIZE, 0x00000001 + 6125 .set CYFLD_SAR_INJ_EOC_MASKED__OFFSET, 0x00000004 + 6126 .set CYFLD_SAR_INJ_EOC_MASKED__SIZE, 0x00000001 + 6127 .set CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET, 0x00000005 + 6128 .set CYFLD_SAR_INJ_SATURATE_MASKED__SIZE, 0x00000001 + 6129 .set CYFLD_SAR_INJ_RANGE_MASKED__OFFSET, 0x00000006 + 6130 .set CYFLD_SAR_INJ_RANGE_MASKED__SIZE, 0x00000001 + 6131 .set CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET, 0x00000007 + 6132 .set CYFLD_SAR_INJ_COLLISION_MASKED__SIZE, 0x00000001 + 6133 .set CYREG_SAR_SATURATE_INTR, 0x401a0220 + 6134 .set CYFLD_SAR_SATURATE_INTR__OFFSET, 0x00000000 + 6135 .set CYFLD_SAR_SATURATE_INTR__SIZE, 0x00000010 + 6136 .set CYREG_SAR_SATURATE_INTR_SET, 0x401a0224 + 6137 .set CYFLD_SAR_SATURATE_SET__OFFSET, 0x00000000 + 6138 .set CYFLD_SAR_SATURATE_SET__SIZE, 0x00000010 + 6139 .set CYREG_SAR_SATURATE_INTR_MASK, 0x401a0228 + 6140 .set CYFLD_SAR_SATURATE_MASK__OFFSET, 0x00000000 + 6141 .set CYFLD_SAR_SATURATE_MASK__SIZE, 0x00000010 + 6142 .set CYREG_SAR_SATURATE_INTR_MASKED, 0x401a022c + 6143 .set CYFLD_SAR_SATURATE_MASKED__OFFSET, 0x00000000 + 6144 .set CYFLD_SAR_SATURATE_MASKED__SIZE, 0x00000010 + 6145 .set CYREG_SAR_RANGE_INTR, 0x401a0230 + 6146 .set CYFLD_SAR_RANGE_INTR__OFFSET, 0x00000000 + 6147 .set CYFLD_SAR_RANGE_INTR__SIZE, 0x00000010 + 6148 .set CYREG_SAR_RANGE_INTR_SET, 0x401a0234 + 6149 .set CYFLD_SAR_RANGE_SET__OFFSET, 0x00000000 + 6150 .set CYFLD_SAR_RANGE_SET__SIZE, 0x00000010 + 6151 .set CYREG_SAR_RANGE_INTR_MASK, 0x401a0238 + 6152 .set CYFLD_SAR_RANGE_MASK__OFFSET, 0x00000000 + 6153 .set CYFLD_SAR_RANGE_MASK__SIZE, 0x00000010 + 6154 .set CYREG_SAR_RANGE_INTR_MASKED, 0x401a023c + 6155 .set CYFLD_SAR_RANGE_MASKED__OFFSET, 0x00000000 + 6156 .set CYFLD_SAR_RANGE_MASKED__SIZE, 0x00000010 + 6157 .set CYREG_SAR_INTR_CAUSE, 0x401a0240 + 6158 .set CYFLD_SAR_EOS_MASKED_MIR__OFFSET, 0x00000000 + 6159 .set CYFLD_SAR_EOS_MASKED_MIR__SIZE, 0x00000001 + 6160 .set CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET, 0x00000001 + 6161 .set CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE, 0x00000001 + 6162 .set CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET, 0x00000002 + 6163 .set CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE, 0x00000001 + 6164 .set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET, 0x00000003 + 6165 .set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE, 0x00000001 + 6166 .set CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET, 0x00000004 + 6167 .set CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE, 0x00000001 + 6168 .set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET, 0x00000005 + 6169 .set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE, 0x00000001 + 6170 .set CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET, 0x00000006 + 6171 .set CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE, 0x00000001 + 6172 .set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET, 0x00000007 + 6173 .set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE, 0x00000001 + 6174 .set CYFLD_SAR_SATURATE_MASKED_RED__OFFSET, 0x0000001e + 6175 .set CYFLD_SAR_SATURATE_MASKED_RED__SIZE, 0x00000001 + 6176 .set CYFLD_SAR_RANGE_MASKED_RED__OFFSET, 0x0000001f + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 110 + + + 6177 .set CYFLD_SAR_RANGE_MASKED_RED__SIZE, 0x00000001 + 6178 .set CYREG_SAR_INJ_CHAN_CONFIG, 0x401a0280 + 6179 .set CYFLD_SAR_INJ_PIN_ADDR__OFFSET, 0x00000000 + 6180 .set CYFLD_SAR_INJ_PIN_ADDR__SIZE, 0x00000003 + 6181 .set CYFLD_SAR_INJ_PORT_ADDR__OFFSET, 0x00000004 + 6182 .set CYFLD_SAR_INJ_PORT_ADDR__SIZE, 0x00000003 + 6183 .set CYVAL_SAR_INJ_PORT_ADDR_SARMUX, 0x00000000 + 6184 .set CYVAL_SAR_INJ_PORT_ADDR_CTB0, 0x00000001 + 6185 .set CYVAL_SAR_INJ_PORT_ADDR_CTB1, 0x00000002 + 6186 .set CYVAL_SAR_INJ_PORT_ADDR_CTB2, 0x00000003 + 6187 .set CYVAL_SAR_INJ_PORT_ADDR_CTB3, 0x00000004 + 6188 .set CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT, 0x00000006 + 6189 .set CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT, 0x00000007 + 6190 .set CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET, 0x00000008 + 6191 .set CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE, 0x00000001 + 6192 .set CYFLD_SAR_INJ_RESOLUTION__OFFSET, 0x00000009 + 6193 .set CYFLD_SAR_INJ_RESOLUTION__SIZE, 0x00000001 + 6194 .set CYVAL_SAR_INJ_RESOLUTION_12B, 0x00000000 + 6195 .set CYVAL_SAR_INJ_RESOLUTION_SUBRES, 0x00000001 + 6196 .set CYFLD_SAR_INJ_AVG_EN__OFFSET, 0x0000000a + 6197 .set CYFLD_SAR_INJ_AVG_EN__SIZE, 0x00000001 + 6198 .set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET, 0x0000000c + 6199 .set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE, 0x00000002 + 6200 .set CYFLD_SAR_INJ_TAILGATING__OFFSET, 0x0000001e + 6201 .set CYFLD_SAR_INJ_TAILGATING__SIZE, 0x00000001 + 6202 .set CYFLD_SAR_INJ_START_EN__OFFSET, 0x0000001f + 6203 .set CYFLD_SAR_INJ_START_EN__SIZE, 0x00000001 + 6204 .set CYREG_SAR_INJ_RESULT, 0x401a0290 + 6205 .set CYFLD_SAR_INJ_RESULT__OFFSET, 0x00000000 + 6206 .set CYFLD_SAR_INJ_RESULT__SIZE, 0x00000010 + 6207 .set CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET, 0x0000001c + 6208 .set CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE, 0x00000001 + 6209 .set CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET, 0x0000001d + 6210 .set CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE, 0x00000001 + 6211 .set CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET, 0x0000001e + 6212 .set CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE, 0x00000001 + 6213 .set CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET, 0x0000001f + 6214 .set CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE, 0x00000001 + 6215 .set CYREG_SAR_MUX_SWITCH0, 0x401a0300 + 6216 .set CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET, 0x00000000 + 6217 .set CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE, 0x00000001 + 6218 .set CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET, 0x00000001 + 6219 .set CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE, 0x00000001 + 6220 .set CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET, 0x00000002 + 6221 .set CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE, 0x00000001 + 6222 .set CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET, 0x00000003 + 6223 .set CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE, 0x00000001 + 6224 .set CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET, 0x00000004 + 6225 .set CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE, 0x00000001 + 6226 .set CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET, 0x00000005 + 6227 .set CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE, 0x00000001 + 6228 .set CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET, 0x00000006 + 6229 .set CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE, 0x00000001 + 6230 .set CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET, 0x00000007 + 6231 .set CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE, 0x00000001 + 6232 .set CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET, 0x00000008 + 6233 .set CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 111 + + + 6234 .set CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET, 0x00000009 + 6235 .set CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE, 0x00000001 + 6236 .set CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET, 0x0000000a + 6237 .set CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE, 0x00000001 + 6238 .set CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET, 0x0000000b + 6239 .set CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE, 0x00000001 + 6240 .set CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET, 0x0000000c + 6241 .set CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE, 0x00000001 + 6242 .set CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET, 0x0000000d + 6243 .set CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE, 0x00000001 + 6244 .set CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET, 0x0000000e + 6245 .set CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE, 0x00000001 + 6246 .set CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET, 0x0000000f + 6247 .set CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE, 0x00000001 + 6248 .set CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET, 0x00000010 + 6249 .set CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE, 0x00000001 + 6250 .set CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET, 0x00000011 + 6251 .set CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE, 0x00000001 + 6252 .set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET, 0x00000012 + 6253 .set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE, 0x00000001 + 6254 .set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET, 0x00000013 + 6255 .set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE, 0x00000001 + 6256 .set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET, 0x00000014 + 6257 .set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE, 0x00000001 + 6258 .set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET, 0x00000015 + 6259 .set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE, 0x00000001 + 6260 .set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET, 0x00000016 + 6261 .set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE, 0x00000001 + 6262 .set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET, 0x00000017 + 6263 .set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE, 0x00000001 + 6264 .set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET, 0x00000018 + 6265 .set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE, 0x00000001 + 6266 .set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET, 0x00000019 + 6267 .set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE, 0x00000001 + 6268 .set CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET, 0x0000001a + 6269 .set CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE, 0x00000001 + 6270 .set CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET, 0x0000001b + 6271 .set CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE, 0x00000001 + 6272 .set CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET, 0x0000001c + 6273 .set CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE, 0x00000001 + 6274 .set CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET, 0x0000001d + 6275 .set CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE, 0x00000001 + 6276 .set CYREG_SAR_MUX_SWITCH_CLEAR0, 0x401a0304 + 6277 .set CYREG_SAR_MUX_SWITCH1, 0x401a0308 + 6278 .set CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET, 0x00000000 + 6279 .set CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE, 0x00000001 + 6280 .set CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET, 0x00000001 + 6281 .set CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE, 0x00000001 + 6282 .set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET, 0x00000002 + 6283 .set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE, 0x00000001 + 6284 .set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET, 0x00000003 + 6285 .set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE, 0x00000001 + 6286 .set CYREG_SAR_MUX_SWITCH_CLEAR1, 0x401a030c + 6287 .set CYREG_SAR_MUX_SWITCH_HW_CTRL, 0x401a0340 + 6288 .set CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET, 0x00000000 + 6289 .set CYFLD_SAR_MUX_HW_CTRL_P0__SIZE, 0x00000001 + 6290 .set CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET, 0x00000001 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 112 + + + 6291 .set CYFLD_SAR_MUX_HW_CTRL_P1__SIZE, 0x00000001 + 6292 .set CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET, 0x00000002 + 6293 .set CYFLD_SAR_MUX_HW_CTRL_P2__SIZE, 0x00000001 + 6294 .set CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET, 0x00000003 + 6295 .set CYFLD_SAR_MUX_HW_CTRL_P3__SIZE, 0x00000001 + 6296 .set CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET, 0x00000004 + 6297 .set CYFLD_SAR_MUX_HW_CTRL_P4__SIZE, 0x00000001 + 6298 .set CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET, 0x00000005 + 6299 .set CYFLD_SAR_MUX_HW_CTRL_P5__SIZE, 0x00000001 + 6300 .set CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET, 0x00000006 + 6301 .set CYFLD_SAR_MUX_HW_CTRL_P6__SIZE, 0x00000001 + 6302 .set CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET, 0x00000007 + 6303 .set CYFLD_SAR_MUX_HW_CTRL_P7__SIZE, 0x00000001 + 6304 .set CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET, 0x00000010 + 6305 .set CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE, 0x00000001 + 6306 .set CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET, 0x00000011 + 6307 .set CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE, 0x00000001 + 6308 .set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET, 0x00000012 + 6309 .set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE, 0x00000001 + 6310 .set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET, 0x00000013 + 6311 .set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE, 0x00000001 + 6312 .set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET, 0x00000016 + 6313 .set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE, 0x00000001 + 6314 .set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET, 0x00000017 + 6315 .set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE, 0x00000001 + 6316 .set CYREG_SAR_MUX_SWITCH_STATUS, 0x401a0348 + 6317 .set CYREG_SAR_PUMP_CTRL, 0x401a0380 + 6318 .set CYFLD_SAR_CLOCK_SEL__OFFSET, 0x00000000 + 6319 .set CYFLD_SAR_CLOCK_SEL__SIZE, 0x00000001 + 6320 .set CYREG_SAR_ANA_TRIM, 0x401a0f00 + 6321 .set CYFLD_SAR_CAP_TRIM__OFFSET, 0x00000000 + 6322 .set CYFLD_SAR_CAP_TRIM__SIZE, 0x00000003 + 6323 .set CYFLD_SAR_TRIMUNIT__OFFSET, 0x00000003 + 6324 .set CYFLD_SAR_TRIMUNIT__SIZE, 0x00000001 + 6325 .set CYREG_SAR_WOUNDING, 0x401a0f04 + 6326 .set CYFLD_SAR_WOUND_RESOLUTION__OFFSET, 0x00000000 + 6327 .set CYFLD_SAR_WOUND_RESOLUTION__SIZE, 0x00000002 + 6328 .set CYVAL_SAR_WOUND_RESOLUTION_12BIT, 0x00000000 + 6329 .set CYVAL_SAR_WOUND_RESOLUTION_10BIT, 0x00000001 + 6330 .set CYVAL_SAR_WOUND_RESOLUTION_8BIT, 0x00000002 + 6331 .set CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO, 0x00000003 + 6332 .set CYDEV_CM0_BASE, 0xe0000000 + 6333 .set CYDEV_CM0_SIZE, 0x00100000 + 6334 .set CYREG_CM0_DWT_PID4, 0xe0001fd0 + 6335 .set CYFLD_CM0_VALUE__OFFSET, 0x00000000 + 6336 .set CYFLD_CM0_VALUE__SIZE, 0x00000020 + 6337 .set CYREG_CM0_DWT_PID0, 0xe0001fe0 + 6338 .set CYREG_CM0_DWT_PID1, 0xe0001fe4 + 6339 .set CYREG_CM0_DWT_PID2, 0xe0001fe8 + 6340 .set CYREG_CM0_DWT_PID3, 0xe0001fec + 6341 .set CYREG_CM0_DWT_CID0, 0xe0001ff0 + 6342 .set CYREG_CM0_DWT_CID1, 0xe0001ff4 + 6343 .set CYREG_CM0_DWT_CID2, 0xe0001ff8 + 6344 .set CYREG_CM0_DWT_CID3, 0xe0001ffc + 6345 .set CYREG_CM0_BP_PID4, 0xe0002fd0 + 6346 .set CYREG_CM0_BP_PID0, 0xe0002fe0 + 6347 .set CYREG_CM0_BP_PID1, 0xe0002fe4 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 113 + + + 6348 .set CYREG_CM0_BP_PID2, 0xe0002fe8 + 6349 .set CYREG_CM0_BP_PID3, 0xe0002fec + 6350 .set CYREG_CM0_BP_CID0, 0xe0002ff0 + 6351 .set CYREG_CM0_BP_CID1, 0xe0002ff4 + 6352 .set CYREG_CM0_BP_CID2, 0xe0002ff8 + 6353 .set CYREG_CM0_BP_CID3, 0xe0002ffc + 6354 .set CYREG_CM0_SYST_CSR, 0xe000e010 + 6355 .set CYFLD_CM0_ENABLE__OFFSET, 0x00000000 + 6356 .set CYFLD_CM0_ENABLE__SIZE, 0x00000001 + 6357 .set CYFLD_CM0_TICKINT__OFFSET, 0x00000001 + 6358 .set CYFLD_CM0_TICKINT__SIZE, 0x00000001 + 6359 .set CYFLD_CM0_CLKSOURCE__OFFSET, 0x00000002 + 6360 .set CYFLD_CM0_CLKSOURCE__SIZE, 0x00000001 + 6361 .set CYFLD_CM0_COUNTFLAG__OFFSET, 0x00000010 + 6362 .set CYFLD_CM0_COUNTFLAG__SIZE, 0x00000001 + 6363 .set CYREG_CM0_SYST_RVR, 0xe000e014 + 6364 .set CYFLD_CM0_RELOAD__OFFSET, 0x00000000 + 6365 .set CYFLD_CM0_RELOAD__SIZE, 0x00000018 + 6366 .set CYREG_CM0_SYST_CVR, 0xe000e018 + 6367 .set CYFLD_CM0_CURRENT__OFFSET, 0x00000000 + 6368 .set CYFLD_CM0_CURRENT__SIZE, 0x00000018 + 6369 .set CYREG_CM0_SYST_CALIB, 0xe000e01c + 6370 .set CYFLD_CM0_TENMS__OFFSET, 0x00000000 + 6371 .set CYFLD_CM0_TENMS__SIZE, 0x00000018 + 6372 .set CYFLD_CM0_SKEW__OFFSET, 0x0000001e + 6373 .set CYFLD_CM0_SKEW__SIZE, 0x00000001 + 6374 .set CYFLD_CM0_NOREF__OFFSET, 0x0000001f + 6375 .set CYFLD_CM0_NOREF__SIZE, 0x00000001 + 6376 .set CYREG_CM0_ISER, 0xe000e100 + 6377 .set CYFLD_CM0_SETENA__OFFSET, 0x00000000 + 6378 .set CYFLD_CM0_SETENA__SIZE, 0x00000020 + 6379 .set CYREG_CM0_ICER, 0xe000e180 + 6380 .set CYFLD_CM0_CLRENA__OFFSET, 0x00000000 + 6381 .set CYFLD_CM0_CLRENA__SIZE, 0x00000020 + 6382 .set CYREG_CM0_ISPR, 0xe000e200 + 6383 .set CYFLD_CM0_SETPEND__OFFSET, 0x00000000 + 6384 .set CYFLD_CM0_SETPEND__SIZE, 0x00000020 + 6385 .set CYREG_CM0_ICPR, 0xe000e280 + 6386 .set CYFLD_CM0_CLRPEND__OFFSET, 0x00000000 + 6387 .set CYFLD_CM0_CLRPEND__SIZE, 0x00000020 + 6388 .set CYREG_CM0_IPR0, 0xe000e400 + 6389 .set CYFLD_CM0_PRI_N0__OFFSET, 0x00000006 + 6390 .set CYFLD_CM0_PRI_N0__SIZE, 0x00000002 + 6391 .set CYFLD_CM0_PRI_N1__OFFSET, 0x0000000e + 6392 .set CYFLD_CM0_PRI_N1__SIZE, 0x00000002 + 6393 .set CYFLD_CM0_PRI_N2__OFFSET, 0x00000016 + 6394 .set CYFLD_CM0_PRI_N2__SIZE, 0x00000002 + 6395 .set CYFLD_CM0_PRI_N3__OFFSET, 0x0000001e + 6396 .set CYFLD_CM0_PRI_N3__SIZE, 0x00000002 + 6397 .set CYREG_CM0_IPR1, 0xe000e404 + 6398 .set CYREG_CM0_IPR2, 0xe000e408 + 6399 .set CYREG_CM0_IPR3, 0xe000e40c + 6400 .set CYREG_CM0_IPR4, 0xe000e410 + 6401 .set CYREG_CM0_IPR5, 0xe000e414 + 6402 .set CYREG_CM0_IPR6, 0xe000e418 + 6403 .set CYREG_CM0_IPR7, 0xe000e41c + 6404 .set CYREG_CM0_CPUID, 0xe000ed00 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 114 + + + 6405 .set CYFLD_CM0_REVISION__OFFSET, 0x00000000 + 6406 .set CYFLD_CM0_REVISION__SIZE, 0x00000004 + 6407 .set CYFLD_CM0_PARTNO__OFFSET, 0x00000004 + 6408 .set CYFLD_CM0_PARTNO__SIZE, 0x0000000c + 6409 .set CYFLD_CM0_CONSTANT__OFFSET, 0x00000010 + 6410 .set CYFLD_CM0_CONSTANT__SIZE, 0x00000004 + 6411 .set CYFLD_CM0_VARIANT__OFFSET, 0x00000014 + 6412 .set CYFLD_CM0_VARIANT__SIZE, 0x00000004 + 6413 .set CYFLD_CM0_IMPLEMENTER__OFFSET, 0x00000018 + 6414 .set CYFLD_CM0_IMPLEMENTER__SIZE, 0x00000008 + 6415 .set CYREG_CM0_ICSR, 0xe000ed04 + 6416 .set CYFLD_CM0_VECTACTIVE__OFFSET, 0x00000000 + 6417 .set CYFLD_CM0_VECTACTIVE__SIZE, 0x00000009 + 6418 .set CYFLD_CM0_VECTPENDING__OFFSET, 0x0000000c + 6419 .set CYFLD_CM0_VECTPENDING__SIZE, 0x00000009 + 6420 .set CYFLD_CM0_ISRPENDING__OFFSET, 0x00000016 + 6421 .set CYFLD_CM0_ISRPENDING__SIZE, 0x00000001 + 6422 .set CYFLD_CM0_ISRPREEMPT__OFFSET, 0x00000017 + 6423 .set CYFLD_CM0_ISRPREEMPT__SIZE, 0x00000001 + 6424 .set CYFLD_CM0_PENDSTCLR__OFFSET, 0x00000019 + 6425 .set CYFLD_CM0_PENDSTCLR__SIZE, 0x00000001 + 6426 .set CYFLD_CM0_PENDSTSETb__OFFSET, 0x0000001a + 6427 .set CYFLD_CM0_PENDSTSETb__SIZE, 0x00000001 + 6428 .set CYFLD_CM0_PENDSVCLR__OFFSET, 0x0000001b + 6429 .set CYFLD_CM0_PENDSVCLR__SIZE, 0x00000001 + 6430 .set CYFLD_CM0_PENDSVSET__OFFSET, 0x0000001c + 6431 .set CYFLD_CM0_PENDSVSET__SIZE, 0x00000001 + 6432 .set CYFLD_CM0_NMIPENDSET__OFFSET, 0x0000001f + 6433 .set CYFLD_CM0_NMIPENDSET__SIZE, 0x00000001 + 6434 .set CYREG_CM0_AIRCR, 0xe000ed0c + 6435 .set CYFLD_CM0_VECTCLRACTIVE__OFFSET, 0x00000001 + 6436 .set CYFLD_CM0_VECTCLRACTIVE__SIZE, 0x00000001 + 6437 .set CYFLD_CM0_SYSRESETREQ__OFFSET, 0x00000002 + 6438 .set CYFLD_CM0_SYSRESETREQ__SIZE, 0x00000001 + 6439 .set CYFLD_CM0_ENDIANNESS__OFFSET, 0x0000000f + 6440 .set CYFLD_CM0_ENDIANNESS__SIZE, 0x00000001 + 6441 .set CYFLD_CM0_VECTKEY__OFFSET, 0x00000010 + 6442 .set CYFLD_CM0_VECTKEY__SIZE, 0x00000010 + 6443 .set CYREG_CM0_SCR, 0xe000ed10 + 6444 .set CYFLD_CM0_SLEEPONEXIT__OFFSET, 0x00000001 + 6445 .set CYFLD_CM0_SLEEPONEXIT__SIZE, 0x00000001 + 6446 .set CYFLD_CM0_SLEEPDEEP__OFFSET, 0x00000002 + 6447 .set CYFLD_CM0_SLEEPDEEP__SIZE, 0x00000001 + 6448 .set CYFLD_CM0_SEVONPEND__OFFSET, 0x00000004 + 6449 .set CYFLD_CM0_SEVONPEND__SIZE, 0x00000001 + 6450 .set CYREG_CM0_CCR, 0xe000ed14 + 6451 .set CYFLD_CM0_UNALIGN_TRP__OFFSET, 0x00000003 + 6452 .set CYFLD_CM0_UNALIGN_TRP__SIZE, 0x00000001 + 6453 .set CYFLD_CM0_STKALIGN__OFFSET, 0x00000009 + 6454 .set CYFLD_CM0_STKALIGN__SIZE, 0x00000001 + 6455 .set CYREG_CM0_SHPR2, 0xe000ed1c + 6456 .set CYFLD_CM0_PRI_11__OFFSET, 0x0000001e + 6457 .set CYFLD_CM0_PRI_11__SIZE, 0x00000002 + 6458 .set CYREG_CM0_SHPR3, 0xe000ed20 + 6459 .set CYFLD_CM0_PRI_14__OFFSET, 0x00000016 + 6460 .set CYFLD_CM0_PRI_14__SIZE, 0x00000002 + 6461 .set CYFLD_CM0_PRI_15__OFFSET, 0x0000001e + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 115 + + + 6462 .set CYFLD_CM0_PRI_15__SIZE, 0x00000002 + 6463 .set CYREG_CM0_SHCSR, 0xe000ed24 + 6464 .set CYFLD_CM0_SVCALLPENDED__OFFSET, 0x0000000f + 6465 .set CYFLD_CM0_SVCALLPENDED__SIZE, 0x00000001 + 6466 .set CYREG_CM0_SCS_PID4, 0xe000efd0 + 6467 .set CYREG_CM0_SCS_PID0, 0xe000efe0 + 6468 .set CYREG_CM0_SCS_PID1, 0xe000efe4 + 6469 .set CYREG_CM0_SCS_PID2, 0xe000efe8 + 6470 .set CYREG_CM0_SCS_PID3, 0xe000efec + 6471 .set CYREG_CM0_SCS_CID0, 0xe000eff0 + 6472 .set CYREG_CM0_SCS_CID1, 0xe000eff4 + 6473 .set CYREG_CM0_SCS_CID2, 0xe000eff8 + 6474 .set CYREG_CM0_SCS_CID3, 0xe000effc + 6475 .set CYREG_CM0_ROM_SCS, 0xe00ff000 + 6476 .set CYREG_CM0_ROM_DWT, 0xe00ff004 + 6477 .set CYREG_CM0_ROM_BPU, 0xe00ff008 + 6478 .set CYREG_CM0_ROM_END, 0xe00ff00c + 6479 .set CYREG_CM0_ROM_CSMT, 0xe00fffcc + 6480 .set CYREG_CM0_ROM_PID4, 0xe00fffd0 + 6481 .set CYREG_CM0_ROM_PID0, 0xe00fffe0 + 6482 .set CYREG_CM0_ROM_PID1, 0xe00fffe4 + 6483 .set CYREG_CM0_ROM_PID2, 0xe00fffe8 + 6484 .set CYREG_CM0_ROM_PID3, 0xe00fffec + 6485 .set CYREG_CM0_ROM_CID0, 0xe00ffff0 + 6486 .set CYREG_CM0_ROM_CID1, 0xe00ffff4 + 6487 .set CYREG_CM0_ROM_CID2, 0xe00ffff8 + 6488 .set CYREG_CM0_ROM_CID3, 0xe00ffffc + 6489 .set CYDEV_CoreSightTable_BASE, 0xf0000000 + 6490 .set CYDEV_CoreSightTable_SIZE, 0x00001000 + 6491 .set CYREG_CoreSightTable_DATA_MBASE, 0xf0000000 + 6492 .set CYREG_CoreSightTable_DATA_MSIZE, 0x00001000 + 6493 .set CYDEV_FLS_SECTOR_SIZE, 0x00008000 + 6494 .set CYDEV_FLS_ROW_SIZE, 0x00000080 + 20 + 21 /* ADC */ + 22 .set ADC_cy_psoc4_sar__SAR_ANA_TRIM, CYREG_SAR_ANA_TRIM + 23 .set ADC_cy_psoc4_sar__SAR_AVG_STAT, CYREG_SAR_AVG_STAT + 24 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00, CYREG_SAR_CHAN_CONFIG00 + 25 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01, CYREG_SAR_CHAN_CONFIG01 + 26 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02, CYREG_SAR_CHAN_CONFIG02 + 27 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03, CYREG_SAR_CHAN_CONFIG03 + 28 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04, CYREG_SAR_CHAN_CONFIG04 + 29 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05, CYREG_SAR_CHAN_CONFIG05 + 30 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06, CYREG_SAR_CHAN_CONFIG06 + 31 .set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07, CYREG_SAR_CHAN_CONFIG07 + 32 .set ADC_cy_psoc4_sar__SAR_CHAN_EN, CYREG_SAR_CHAN_EN + 33 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID, CYREG_SAR_CHAN_RESULT_VALID + 34 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT00, CYREG_SAR_CHAN_RESULT00 + 35 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT01, CYREG_SAR_CHAN_RESULT01 + 36 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT02, CYREG_SAR_CHAN_RESULT02 + 37 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT03, CYREG_SAR_CHAN_RESULT03 + 38 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT04, CYREG_SAR_CHAN_RESULT04 + 39 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT05, CYREG_SAR_CHAN_RESULT05 + 40 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT06, CYREG_SAR_CHAN_RESULT06 + 41 .set ADC_cy_psoc4_sar__SAR_CHAN_RESULT07, CYREG_SAR_CHAN_RESULT07 + 42 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID, CYREG_SAR_CHAN_WORK_VALID + 43 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK00, CYREG_SAR_CHAN_WORK00 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 116 + + + 44 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK01, CYREG_SAR_CHAN_WORK01 + 45 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK02, CYREG_SAR_CHAN_WORK02 + 46 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK03, CYREG_SAR_CHAN_WORK03 + 47 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK04, CYREG_SAR_CHAN_WORK04 + 48 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK05, CYREG_SAR_CHAN_WORK05 + 49 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK06, CYREG_SAR_CHAN_WORK06 + 50 .set ADC_cy_psoc4_sar__SAR_CHAN_WORK07, CYREG_SAR_CHAN_WORK07 + 51 .set ADC_cy_psoc4_sar__SAR_CTRL, CYREG_SAR_CTRL + 52 .set ADC_cy_psoc4_sar__SAR_DFT_CTRL, CYREG_SAR_DFT_CTRL + 53 .set ADC_cy_psoc4_sar__SAR_INTR, CYREG_SAR_INTR + 54 .set ADC_cy_psoc4_sar__SAR_INTR_CAUSE, CYREG_SAR_INTR_CAUSE + 55 .set ADC_cy_psoc4_sar__SAR_INTR_MASK, CYREG_SAR_INTR_MASK + 56 .set ADC_cy_psoc4_sar__SAR_INTR_MASKED, CYREG_SAR_INTR_MASKED + 57 .set ADC_cy_psoc4_sar__SAR_INTR_SET, CYREG_SAR_INTR_SET + 58 .set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0, CYREG_SAR_MUX_SWITCH_CLEAR0 + 59 .set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1, CYREG_SAR_MUX_SWITCH_CLEAR1 + 60 .set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL, CYREG_SAR_MUX_SWITCH_HW_CTRL + 61 .set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS, CYREG_SAR_MUX_SWITCH_STATUS + 62 .set ADC_cy_psoc4_sar__SAR_MUX_SWITCH0, CYREG_SAR_MUX_SWITCH0 + 63 .set ADC_cy_psoc4_sar__SAR_MUX_SWITCH1, CYREG_SAR_MUX_SWITCH1 + 64 .set ADC_cy_psoc4_sar__SAR_NUMBER, 0 + 65 .set ADC_cy_psoc4_sar__SAR_PUMP_CTRL, CYREG_SAR_PUMP_CTRL + 66 .set ADC_cy_psoc4_sar__SAR_RANGE_COND, CYREG_SAR_RANGE_COND + 67 .set ADC_cy_psoc4_sar__SAR_RANGE_INTR, CYREG_SAR_RANGE_INTR + 68 .set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK, CYREG_SAR_RANGE_INTR_MASK + 69 .set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED, CYREG_SAR_RANGE_INTR_MASKED + 70 .set ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET, CYREG_SAR_RANGE_INTR_SET + 71 .set ADC_cy_psoc4_sar__SAR_RANGE_THRES, CYREG_SAR_RANGE_THRES + 72 .set ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL, CYREG_SAR_SAMPLE_CTRL + 73 .set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01, CYREG_SAR_SAMPLE_TIME01 + 74 .set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23, CYREG_SAR_SAMPLE_TIME23 + 75 .set ADC_cy_psoc4_sar__SAR_SATURATE_INTR, CYREG_SAR_SATURATE_INTR + 76 .set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK, CYREG_SAR_SATURATE_INTR_MASK + 77 .set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED, CYREG_SAR_SATURATE_INTR_MASKED + 78 .set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET, CYREG_SAR_SATURATE_INTR_SET + 79 .set ADC_cy_psoc4_sar__SAR_START_CTRL, CYREG_SAR_START_CTRL + 80 .set ADC_cy_psoc4_sar__SAR_STATUS, CYREG_SAR_STATUS + 81 .set ADC_cy_psoc4_sar__SAR_WOUNDING, CYREG_SAR_WOUNDING + 82 .set ADC_intClock__DIVIDER_MASK, 0x0000FFFF + 83 .set ADC_intClock__ENABLE, CYREG_CLK_DIVIDER_A00 + 84 .set ADC_intClock__ENABLE_MASK, 0x80000000 + 85 .set ADC_intClock__MASK, 0x80000000 + 86 .set ADC_intClock__REGISTER, CYREG_CLK_DIVIDER_A00 + 87 .set ADC_IRQ__INTC_CLR_EN_REG, CYREG_CM0_ICER + 88 .set ADC_IRQ__INTC_CLR_PD_REG, CYREG_CM0_ICPR + 89 .set ADC_IRQ__INTC_MASK, 0x4000 + 90 .set ADC_IRQ__INTC_NUMBER, 14 + 91 .set ADC_IRQ__INTC_PRIOR_MASK, 0xC00000 + 92 .set ADC_IRQ__INTC_PRIOR_NUM, 3 + 93 .set ADC_IRQ__INTC_PRIOR_REG, CYREG_CM0_IPR3 + 94 .set ADC_IRQ__INTC_SET_EN_REG, CYREG_CM0_ISER + 95 .set ADC_IRQ__INTC_SET_PD_REG, CYREG_CM0_ISPR + 96 + 97 /* LED */ + 98 .set LED__0__DM__MASK, 0x1C0000 + 99 .set LED__0__DM__SHIFT, 18 + 100 .set LED__0__DR, CYREG_PRT1_DR + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 117 + + + 101 .set LED__0__HSIOM, CYREG_HSIOM_PORT_SEL1 + 102 .set LED__0__HSIOM_MASK, 0x0F000000 + 103 .set LED__0__HSIOM_SHIFT, 24 + 104 .set LED__0__INTCFG, CYREG_PRT1_INTCFG + 105 .set LED__0__INTSTAT, CYREG_PRT1_INTSTAT + 106 .set LED__0__MASK, 0x40 + 107 .set LED__0__PA__CFG0, CYREG_UDB_PA1_CFG0 + 108 .set LED__0__PA__CFG1, CYREG_UDB_PA1_CFG1 + 109 .set LED__0__PA__CFG10, CYREG_UDB_PA1_CFG10 + 110 .set LED__0__PA__CFG11, CYREG_UDB_PA1_CFG11 + 111 .set LED__0__PA__CFG12, CYREG_UDB_PA1_CFG12 + 112 .set LED__0__PA__CFG13, CYREG_UDB_PA1_CFG13 + 113 .set LED__0__PA__CFG14, CYREG_UDB_PA1_CFG14 + 114 .set LED__0__PA__CFG2, CYREG_UDB_PA1_CFG2 + 115 .set LED__0__PA__CFG3, CYREG_UDB_PA1_CFG3 + 116 .set LED__0__PA__CFG4, CYREG_UDB_PA1_CFG4 + 117 .set LED__0__PA__CFG5, CYREG_UDB_PA1_CFG5 + 118 .set LED__0__PA__CFG6, CYREG_UDB_PA1_CFG6 + 119 .set LED__0__PA__CFG7, CYREG_UDB_PA1_CFG7 + 120 .set LED__0__PA__CFG8, CYREG_UDB_PA1_CFG8 + 121 .set LED__0__PA__CFG9, CYREG_UDB_PA1_CFG9 + 122 .set LED__0__PC, CYREG_PRT1_PC + 123 .set LED__0__PC2, CYREG_PRT1_PC2 + 124 .set LED__0__PORT, 1 + 125 .set LED__0__PS, CYREG_PRT1_PS + 126 .set LED__0__SHIFT, 6 + 127 .set LED__DR, CYREG_PRT1_DR + 128 .set LED__INTCFG, CYREG_PRT1_INTCFG + 129 .set LED__INTSTAT, CYREG_PRT1_INTSTAT + 130 .set LED__MASK, 0x40 + 131 .set LED__PA__CFG0, CYREG_UDB_PA1_CFG0 + 132 .set LED__PA__CFG1, CYREG_UDB_PA1_CFG1 + 133 .set LED__PA__CFG10, CYREG_UDB_PA1_CFG10 + 134 .set LED__PA__CFG11, CYREG_UDB_PA1_CFG11 + 135 .set LED__PA__CFG12, CYREG_UDB_PA1_CFG12 + 136 .set LED__PA__CFG13, CYREG_UDB_PA1_CFG13 + 137 .set LED__PA__CFG14, CYREG_UDB_PA1_CFG14 + 138 .set LED__PA__CFG2, CYREG_UDB_PA1_CFG2 + 139 .set LED__PA__CFG3, CYREG_UDB_PA1_CFG3 + 140 .set LED__PA__CFG4, CYREG_UDB_PA1_CFG4 + 141 .set LED__PA__CFG5, CYREG_UDB_PA1_CFG5 + 142 .set LED__PA__CFG6, CYREG_UDB_PA1_CFG6 + 143 .set LED__PA__CFG7, CYREG_UDB_PA1_CFG7 + 144 .set LED__PA__CFG8, CYREG_UDB_PA1_CFG8 + 145 .set LED__PA__CFG9, CYREG_UDB_PA1_CFG9 + 146 .set LED__PC, CYREG_PRT1_PC + 147 .set LED__PC2, CYREG_PRT1_PC2 + 148 .set LED__PORT, 1 + 149 .set LED__PS, CYREG_PRT1_PS + 150 .set LED__SHIFT, 6 + 151 + 152 /* UART */ + 153 .set UART_SCB__BIST_CONTROL, CYREG_SCB0_BIST_CONTROL + 154 .set UART_SCB__BIST_DATA, CYREG_SCB0_BIST_DATA + 155 .set UART_SCB__CTRL, CYREG_SCB0_CTRL + 156 .set UART_SCB__EZ_DATA00, CYREG_SCB0_EZ_DATA00 + 157 .set UART_SCB__EZ_DATA01, CYREG_SCB0_EZ_DATA01 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 118 + + + 158 .set UART_SCB__EZ_DATA02, CYREG_SCB0_EZ_DATA02 + 159 .set UART_SCB__EZ_DATA03, CYREG_SCB0_EZ_DATA03 + 160 .set UART_SCB__EZ_DATA04, CYREG_SCB0_EZ_DATA04 + 161 .set UART_SCB__EZ_DATA05, CYREG_SCB0_EZ_DATA05 + 162 .set UART_SCB__EZ_DATA06, CYREG_SCB0_EZ_DATA06 + 163 .set UART_SCB__EZ_DATA07, CYREG_SCB0_EZ_DATA07 + 164 .set UART_SCB__EZ_DATA08, CYREG_SCB0_EZ_DATA08 + 165 .set UART_SCB__EZ_DATA09, CYREG_SCB0_EZ_DATA09 + 166 .set UART_SCB__EZ_DATA10, CYREG_SCB0_EZ_DATA10 + 167 .set UART_SCB__EZ_DATA11, CYREG_SCB0_EZ_DATA11 + 168 .set UART_SCB__EZ_DATA12, CYREG_SCB0_EZ_DATA12 + 169 .set UART_SCB__EZ_DATA13, CYREG_SCB0_EZ_DATA13 + 170 .set UART_SCB__EZ_DATA14, CYREG_SCB0_EZ_DATA14 + 171 .set UART_SCB__EZ_DATA15, CYREG_SCB0_EZ_DATA15 + 172 .set UART_SCB__EZ_DATA16, CYREG_SCB0_EZ_DATA16 + 173 .set UART_SCB__EZ_DATA17, CYREG_SCB0_EZ_DATA17 + 174 .set UART_SCB__EZ_DATA18, CYREG_SCB0_EZ_DATA18 + 175 .set UART_SCB__EZ_DATA19, CYREG_SCB0_EZ_DATA19 + 176 .set UART_SCB__EZ_DATA20, CYREG_SCB0_EZ_DATA20 + 177 .set UART_SCB__EZ_DATA21, CYREG_SCB0_EZ_DATA21 + 178 .set UART_SCB__EZ_DATA22, CYREG_SCB0_EZ_DATA22 + 179 .set UART_SCB__EZ_DATA23, CYREG_SCB0_EZ_DATA23 + 180 .set UART_SCB__EZ_DATA24, CYREG_SCB0_EZ_DATA24 + 181 .set UART_SCB__EZ_DATA25, CYREG_SCB0_EZ_DATA25 + 182 .set UART_SCB__EZ_DATA26, CYREG_SCB0_EZ_DATA26 + 183 .set UART_SCB__EZ_DATA27, CYREG_SCB0_EZ_DATA27 + 184 .set UART_SCB__EZ_DATA28, CYREG_SCB0_EZ_DATA28 + 185 .set UART_SCB__EZ_DATA29, CYREG_SCB0_EZ_DATA29 + 186 .set UART_SCB__EZ_DATA30, CYREG_SCB0_EZ_DATA30 + 187 .set UART_SCB__EZ_DATA31, CYREG_SCB0_EZ_DATA31 + 188 .set UART_SCB__I2C_CFG, CYREG_SCB0_I2C_CFG + 189 .set UART_SCB__I2C_CTRL, CYREG_SCB0_I2C_CTRL + 190 .set UART_SCB__I2C_M_CMD, CYREG_SCB0_I2C_M_CMD + 191 .set UART_SCB__I2C_S_CMD, CYREG_SCB0_I2C_S_CMD + 192 .set UART_SCB__I2C_STATUS, CYREG_SCB0_I2C_STATUS + 193 .set UART_SCB__INTR_CAUSE, CYREG_SCB0_INTR_CAUSE + 194 .set UART_SCB__INTR_I2C_EC, CYREG_SCB0_INTR_I2C_EC + 195 .set UART_SCB__INTR_I2C_EC_MASK, CYREG_SCB0_INTR_I2C_EC_MASK + 196 .set UART_SCB__INTR_I2C_EC_MASKED, CYREG_SCB0_INTR_I2C_EC_MASKED + 197 .set UART_SCB__INTR_M, CYREG_SCB0_INTR_M + 198 .set UART_SCB__INTR_M_MASK, CYREG_SCB0_INTR_M_MASK + 199 .set UART_SCB__INTR_M_MASKED, CYREG_SCB0_INTR_M_MASKED + 200 .set UART_SCB__INTR_M_SET, CYREG_SCB0_INTR_M_SET + 201 .set UART_SCB__INTR_RX, CYREG_SCB0_INTR_RX + 202 .set UART_SCB__INTR_RX_MASK, CYREG_SCB0_INTR_RX_MASK + 203 .set UART_SCB__INTR_RX_MASKED, CYREG_SCB0_INTR_RX_MASKED + 204 .set UART_SCB__INTR_RX_SET, CYREG_SCB0_INTR_RX_SET + 205 .set UART_SCB__INTR_S, CYREG_SCB0_INTR_S + 206 .set UART_SCB__INTR_S_MASK, CYREG_SCB0_INTR_S_MASK + 207 .set UART_SCB__INTR_S_MASKED, CYREG_SCB0_INTR_S_MASKED + 208 .set UART_SCB__INTR_S_SET, CYREG_SCB0_INTR_S_SET + 209 .set UART_SCB__INTR_SPI_EC, CYREG_SCB0_INTR_SPI_EC + 210 .set UART_SCB__INTR_SPI_EC_MASK, CYREG_SCB0_INTR_SPI_EC_MASK + 211 .set UART_SCB__INTR_SPI_EC_MASKED, CYREG_SCB0_INTR_SPI_EC_MASKED + 212 .set UART_SCB__INTR_TX, CYREG_SCB0_INTR_TX + 213 .set UART_SCB__INTR_TX_MASK, CYREG_SCB0_INTR_TX_MASK + 214 .set UART_SCB__INTR_TX_MASKED, CYREG_SCB0_INTR_TX_MASKED + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 119 + + + 215 .set UART_SCB__INTR_TX_SET, CYREG_SCB0_INTR_TX_SET + 216 .set UART_SCB__RX_CTRL, CYREG_SCB0_RX_CTRL + 217 .set UART_SCB__RX_FIFO_CTRL, CYREG_SCB0_RX_FIFO_CTRL + 218 .set UART_SCB__RX_FIFO_RD, CYREG_SCB0_RX_FIFO_RD + 219 .set UART_SCB__RX_FIFO_RD_SILENT, CYREG_SCB0_RX_FIFO_RD_SILENT + 220 .set UART_SCB__RX_FIFO_STATUS, CYREG_SCB0_RX_FIFO_STATUS + 221 .set UART_SCB__RX_MATCH, CYREG_SCB0_RX_MATCH + 222 .set UART_SCB__SPI_CTRL, CYREG_SCB0_SPI_CTRL + 223 .set UART_SCB__SPI_STATUS, CYREG_SCB0_SPI_STATUS + 224 .set UART_SCB__SS0_POSISTION, 0 + 225 .set UART_SCB__SS1_POSISTION, 1 + 226 .set UART_SCB__SS2_POSISTION, 2 + 227 .set UART_SCB__SS3_POSISTION, 3 + 228 .set UART_SCB__STATUS, CYREG_SCB0_STATUS + 229 .set UART_SCB__TX_CTRL, CYREG_SCB0_TX_CTRL + 230 .set UART_SCB__TX_FIFO_CTRL, CYREG_SCB0_TX_FIFO_CTRL + 231 .set UART_SCB__TX_FIFO_STATUS, CYREG_SCB0_TX_FIFO_STATUS + 232 .set UART_SCB__TX_FIFO_WR, CYREG_SCB0_TX_FIFO_WR + 233 .set UART_SCB__UART_CTRL, CYREG_SCB0_UART_CTRL + 234 .set UART_SCB__UART_RX_CTRL, CYREG_SCB0_UART_RX_CTRL + 235 .set UART_SCB__UART_RX_STATUS, CYREG_SCB0_UART_RX_STATUS + 236 .set UART_SCB__UART_TX_CTRL, CYREG_SCB0_UART_TX_CTRL + 237 .set UART_SCBCLK__DIVIDER_MASK, 0x0000FFFF + 238 .set UART_SCBCLK__ENABLE, CYREG_CLK_DIVIDER_B00 + 239 .set UART_SCBCLK__ENABLE_MASK, 0x80000000 + 240 .set UART_SCBCLK__MASK, 0x80000000 + 241 .set UART_SCBCLK__REGISTER, CYREG_CLK_DIVIDER_B00 + 242 .set UART_tx__0__DM__MASK, 0x38 + 243 .set UART_tx__0__DM__SHIFT, 3 + 244 .set UART_tx__0__DR, CYREG_PRT4_DR + 245 .set UART_tx__0__HSIOM, CYREG_HSIOM_PORT_SEL4 + 246 .set UART_tx__0__HSIOM_GPIO, 0 + 247 .set UART_tx__0__HSIOM_I2C, 14 + 248 .set UART_tx__0__HSIOM_I2C_SDA, 14 + 249 .set UART_tx__0__HSIOM_MASK, 0x000000F0 + 250 .set UART_tx__0__HSIOM_SHIFT, 4 + 251 .set UART_tx__0__HSIOM_SPI, 15 + 252 .set UART_tx__0__HSIOM_SPI_MISO, 15 + 253 .set UART_tx__0__HSIOM_UART, 9 + 254 .set UART_tx__0__HSIOM_UART_TX, 9 + 255 .set UART_tx__0__INTCFG, CYREG_PRT4_INTCFG + 256 .set UART_tx__0__INTSTAT, CYREG_PRT4_INTSTAT + 257 .set UART_tx__0__MASK, 0x02 + 258 .set UART_tx__0__PC, CYREG_PRT4_PC + 259 .set UART_tx__0__PC2, CYREG_PRT4_PC2 + 260 .set UART_tx__0__PORT, 4 + 261 .set UART_tx__0__PS, CYREG_PRT4_PS + 262 .set UART_tx__0__SHIFT, 1 + 263 .set UART_tx__DR, CYREG_PRT4_DR + 264 .set UART_tx__INTCFG, CYREG_PRT4_INTCFG + 265 .set UART_tx__INTSTAT, CYREG_PRT4_INTSTAT + 266 .set UART_tx__MASK, 0x02 + 267 .set UART_tx__PC, CYREG_PRT4_PC + 268 .set UART_tx__PC2, CYREG_PRT4_PC2 + 269 .set UART_tx__PORT, 4 + 270 .set UART_tx__PS, CYREG_PRT4_PS + 271 .set UART_tx__SHIFT, 1 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 120 + + + 272 + 273 /* Input_1 */ + 274 .set Input_1__0__DM__MASK, 0xE00 + 275 .set Input_1__0__DM__SHIFT, 9 + 276 .set Input_1__0__DR, CYREG_PRT2_DR + 277 .set Input_1__0__HSIOM, CYREG_HSIOM_PORT_SEL2 + 278 .set Input_1__0__HSIOM_MASK, 0x0000F000 + 279 .set Input_1__0__HSIOM_SHIFT, 12 + 280 .set Input_1__0__INTCFG, CYREG_PRT2_INTCFG + 281 .set Input_1__0__INTSTAT, CYREG_PRT2_INTSTAT + 282 .set Input_1__0__MASK, 0x08 + 283 .set Input_1__0__PA__CFG0, CYREG_UDB_PA2_CFG0 + 284 .set Input_1__0__PA__CFG1, CYREG_UDB_PA2_CFG1 + 285 .set Input_1__0__PA__CFG10, CYREG_UDB_PA2_CFG10 + 286 .set Input_1__0__PA__CFG11, CYREG_UDB_PA2_CFG11 + 287 .set Input_1__0__PA__CFG12, CYREG_UDB_PA2_CFG12 + 288 .set Input_1__0__PA__CFG13, CYREG_UDB_PA2_CFG13 + 289 .set Input_1__0__PA__CFG14, CYREG_UDB_PA2_CFG14 + 290 .set Input_1__0__PA__CFG2, CYREG_UDB_PA2_CFG2 + 291 .set Input_1__0__PA__CFG3, CYREG_UDB_PA2_CFG3 + 292 .set Input_1__0__PA__CFG4, CYREG_UDB_PA2_CFG4 + 293 .set Input_1__0__PA__CFG5, CYREG_UDB_PA2_CFG5 + 294 .set Input_1__0__PA__CFG6, CYREG_UDB_PA2_CFG6 + 295 .set Input_1__0__PA__CFG7, CYREG_UDB_PA2_CFG7 + 296 .set Input_1__0__PA__CFG8, CYREG_UDB_PA2_CFG8 + 297 .set Input_1__0__PA__CFG9, CYREG_UDB_PA2_CFG9 + 298 .set Input_1__0__PC, CYREG_PRT2_PC + 299 .set Input_1__0__PC2, CYREG_PRT2_PC2 + 300 .set Input_1__0__PORT, 2 + 301 .set Input_1__0__PS, CYREG_PRT2_PS + 302 .set Input_1__0__SHIFT, 3 + 303 .set Input_1__DR, CYREG_PRT2_DR + 304 .set Input_1__INTCFG, CYREG_PRT2_INTCFG + 305 .set Input_1__INTSTAT, CYREG_PRT2_INTSTAT + 306 .set Input_1__MASK, 0x08 + 307 .set Input_1__PA__CFG0, CYREG_UDB_PA2_CFG0 + 308 .set Input_1__PA__CFG1, CYREG_UDB_PA2_CFG1 + 309 .set Input_1__PA__CFG10, CYREG_UDB_PA2_CFG10 + 310 .set Input_1__PA__CFG11, CYREG_UDB_PA2_CFG11 + 311 .set Input_1__PA__CFG12, CYREG_UDB_PA2_CFG12 + 312 .set Input_1__PA__CFG13, CYREG_UDB_PA2_CFG13 + 313 .set Input_1__PA__CFG14, CYREG_UDB_PA2_CFG14 + 314 .set Input_1__PA__CFG2, CYREG_UDB_PA2_CFG2 + 315 .set Input_1__PA__CFG3, CYREG_UDB_PA2_CFG3 + 316 .set Input_1__PA__CFG4, CYREG_UDB_PA2_CFG4 + 317 .set Input_1__PA__CFG5, CYREG_UDB_PA2_CFG5 + 318 .set Input_1__PA__CFG6, CYREG_UDB_PA2_CFG6 + 319 .set Input_1__PA__CFG7, CYREG_UDB_PA2_CFG7 + 320 .set Input_1__PA__CFG8, CYREG_UDB_PA2_CFG8 + 321 .set Input_1__PA__CFG9, CYREG_UDB_PA2_CFG9 + 322 .set Input_1__PC, CYREG_PRT2_PC + 323 .set Input_1__PC2, CYREG_PRT2_PC2 + 324 .set Input_1__PORT, 2 + 325 .set Input_1__PS, CYREG_PRT2_PS + 326 .set Input_1__SHIFT, 3 + 327 + 328 /* Miscellaneous */ + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 121 + + + 329 .set CYDEV_BCLK__HFCLK__HZ, 24000000 + 330 .set CYDEV_BCLK__HFCLK__KHZ, 24000 + 331 .set CYDEV_BCLK__HFCLK__MHZ, 24 + 332 .set CYDEV_BCLK__SYSCLK__HZ, 24000000 + 333 .set CYDEV_BCLK__SYSCLK__KHZ, 24000 + 334 .set CYDEV_BCLK__SYSCLK__MHZ, 24 + 335 .set CYDEV_CHIP_DIE_LEOPARD, 1 + 336 .set CYDEV_CHIP_DIE_PSOC4A, 18 + 337 .set CYDEV_CHIP_DIE_PSOC5LP, 2 + 338 .set CYDEV_CHIP_DIE_PSOC5TM, 3 + 339 .set CYDEV_CHIP_DIE_TMA4, 4 + 340 .set CYDEV_CHIP_DIE_UNKNOWN, 0 + 341 .set CYDEV_CHIP_FAMILY_FM0P, 5 + 342 .set CYDEV_CHIP_FAMILY_FM3, 6 + 343 .set CYDEV_CHIP_FAMILY_FM4, 7 + 344 .set CYDEV_CHIP_FAMILY_PSOC3, 1 + 345 .set CYDEV_CHIP_FAMILY_PSOC4, 2 + 346 .set CYDEV_CHIP_FAMILY_PSOC5, 3 + 347 .set CYDEV_CHIP_FAMILY_PSOC6, 4 + 348 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 + 349 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4 + 350 .set CYDEV_CHIP_JTAG_ID, 0x04C81193 + 351 .set CYDEV_CHIP_MEMBER_3A, 1 + 352 .set CYDEV_CHIP_MEMBER_4A, 18 + 353 .set CYDEV_CHIP_MEMBER_4D, 13 + 354 .set CYDEV_CHIP_MEMBER_4E, 6 + 355 .set CYDEV_CHIP_MEMBER_4F, 19 + 356 .set CYDEV_CHIP_MEMBER_4G, 4 + 357 .set CYDEV_CHIP_MEMBER_4H, 17 + 358 .set CYDEV_CHIP_MEMBER_4I, 23 + 359 .set CYDEV_CHIP_MEMBER_4J, 14 + 360 .set CYDEV_CHIP_MEMBER_4K, 15 + 361 .set CYDEV_CHIP_MEMBER_4L, 22 + 362 .set CYDEV_CHIP_MEMBER_4M, 21 + 363 .set CYDEV_CHIP_MEMBER_4N, 10 + 364 .set CYDEV_CHIP_MEMBER_4O, 7 + 365 .set CYDEV_CHIP_MEMBER_4P, 20 + 366 .set CYDEV_CHIP_MEMBER_4Q, 12 + 367 .set CYDEV_CHIP_MEMBER_4R, 8 + 368 .set CYDEV_CHIP_MEMBER_4S, 11 + 369 .set CYDEV_CHIP_MEMBER_4T, 9 + 370 .set CYDEV_CHIP_MEMBER_4U, 5 + 371 .set CYDEV_CHIP_MEMBER_4V, 16 + 372 .set CYDEV_CHIP_MEMBER_5A, 3 + 373 .set CYDEV_CHIP_MEMBER_5B, 2 + 374 .set CYDEV_CHIP_MEMBER_6A, 24 + 375 .set CYDEV_CHIP_MEMBER_FM3, 28 + 376 .set CYDEV_CHIP_MEMBER_FM4, 29 + 377 .set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 + 378 .set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 + 379 .set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 + 380 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 + 381 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4A + 382 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED + 383 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT + 384 .set CYDEV_CHIP_REV_LEOPARD_ES1, 0 + 385 .set CYDEV_CHIP_REV_LEOPARD_ES2, 1 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 122 + + + 386 .set CYDEV_CHIP_REV_LEOPARD_ES3, 3 + 387 .set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 + 388 .set CYDEV_CHIP_REV_PSOC4A_ES0, 17 + 389 .set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 + 390 .set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 + 391 .set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 + 392 .set CYDEV_CHIP_REV_PSOC5TM_ES0, 0 + 393 .set CYDEV_CHIP_REV_PSOC5TM_ES1, 1 + 394 .set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1 + 395 .set CYDEV_CHIP_REV_TMA4_ES, 17 + 396 .set CYDEV_CHIP_REV_TMA4_ES2, 33 + 397 .set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17 + 398 .set CYDEV_CHIP_REVISION_3A_ES1, 0 + 399 .set CYDEV_CHIP_REVISION_3A_ES2, 1 + 400 .set CYDEV_CHIP_REVISION_3A_ES3, 3 + 401 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 + 402 .set CYDEV_CHIP_REVISION_4A_ES0, 17 + 403 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 + 404 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 + 405 .set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 + 406 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 + 407 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 + 408 .set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 + 409 .set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0 + 410 .set CYDEV_CHIP_REVISION_4G_ES, 17 + 411 .set CYDEV_CHIP_REVISION_4G_ES2, 33 + 412 .set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17 + 413 .set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0 + 414 .set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0 + 415 .set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0 + 416 .set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0 + 417 .set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0 + 418 .set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0 + 419 .set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0 + 420 .set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 + 421 .set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 + 422 .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 + 423 .set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 + 424 .set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 + 425 .set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 + 426 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 + 427 .set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 + 428 .set CYDEV_CHIP_REVISION_5A_ES0, 0 + 429 .set CYDEV_CHIP_REVISION_5A_ES1, 1 + 430 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 + 431 .set CYDEV_CHIP_REVISION_5B_ES0, 0 + 432 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 + 433 .set CYDEV_CHIP_REVISION_6A_ES, 17 + 434 .set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 + 435 .set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 + 436 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 + 437 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 + 438 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 + 439 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 + 440 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 + 441 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4A_PRODUCTION + 442 .set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 123 + + + 443 .set CYDEV_CONFIG_READ_ACCELERATOR, 1 + 444 .set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 + 445 .set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 + 446 .set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowWithInfo + 447 .set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 + 448 .set CYDEV_CONFIGURATION_COMPRESSED, 1 + 449 .set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 + 450 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED + 451 .set CYDEV_CONFIGURATION_MODE_DMA, 2 + 452 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 + 453 .set CYDEV_DEBUG_PROTECT_KILL, 4 + 454 .set CYDEV_DEBUG_PROTECT_OPEN, 1 + 455 .set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_OPEN + 456 .set CYDEV_DEBUG_PROTECT_PROTECTED, 2 + 457 .set CYDEV_DEBUGGING_DPS_Disable, 3 + 458 .set CYDEV_DEBUGGING_DPS_SWD, 2 + 459 .set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD + 460 .set CYDEV_DEBUGGING_ENABLE, 1 + 461 .set CYDEV_DFT_SELECT_CLK0, 1 + 462 .set CYDEV_DFT_SELECT_CLK1, 2 + 463 .set CYDEV_HEAP_SIZE, 0x0100 + 464 .set CYDEV_IMO_TRIMMED_BY_USB, 0 + 465 .set CYDEV_IMO_TRIMMED_BY_WCO, 0 + 466 .set CYDEV_IS_EXPORTING_CODE, 0 + 467 .set CYDEV_IS_IMPORTING_CODE, 0 + 468 .set CYDEV_PROJ_TYPE, 0 + 469 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 + 470 .set CYDEV_PROJ_TYPE_LAUNCHER, 5 + 471 .set CYDEV_PROJ_TYPE_LOADABLE, 2 + 472 .set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4 + 473 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 + 474 .set CYDEV_PROJ_TYPE_STANDARD, 0 + 475 .set CYDEV_STACK_SIZE, 0x0400 + 476 .set CYDEV_USE_BUNDLED_CMSIS, 1 + 477 .set CYDEV_VARIABLE_VDDA, 0 + 478 .set CYDEV_VDDA_MV, 5000 + 479 .set CYDEV_VDDD_MV, 5000 + 480 .set CYDEV_WDT_GENERATE_ISR, 0 + 481 .set CYIPBLOCK_M0S8_CTBM_VERSION, 0 + 482 .set CYIPBLOCK_m0s8cpuss_VERSION, 0 + 483 .set CYIPBLOCK_m0s8csd_VERSION, 0 + 484 .set CYIPBLOCK_m0s8gpio2_VERSION, 0 + 485 .set CYIPBLOCK_m0s8hsiom4a_VERSION, 0 + 486 .set CYIPBLOCK_m0s8lcd_VERSION, 0 + 487 .set CYIPBLOCK_m0s8lpcomp_VERSION, 0 + 488 .set CYIPBLOCK_m0s8pclk_VERSION, 0 + 489 .set CYIPBLOCK_m0s8sar_VERSION, 0 + 490 .set CYIPBLOCK_m0s8scb_VERSION, 0 + 491 .set CYIPBLOCK_m0s8srssv2_VERSION, 1 + 492 .set CYIPBLOCK_m0s8tcpwm_VERSION, 0 + 493 .set CYIPBLOCK_m0s8udbif_VERSION, 0 + 494 .set CYIPBLOCK_S8_GPIO_VERSION, 2 + 495 .set CYDEV_BOOTLOADER_ENABLE, 0 + 496 .endif + 19 + 20 + 21 /******************************************************************************* + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 124 + + + 22 * Function Name: CyDelayCycles + 23 ****************************************************************************//** + 24 * + 25 * Delays for the specified number of cycles. + 26 * + 27 * \param uint32 cycles: number of cycles to delay. + 28 * + 29 * \return + 30 * None + 31 * + 32 *******************************************************************************/ + 33 /* void CyDelayCycles(uint32 cycles) */ + 34 .align 3 /* Align to 8 byte boundary (2^n) */ + 35 .global CyDelayCycles + 36 .func CyDelayCycles, CyDelayCycles + 37 .type CyDelayCycles, %function + 38 .thumb_func + 39 CyDelayCycles: /* cycles bytes */ + 40 0000 0230 ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + 41 0002 8008 LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + 42 0004 04D0 BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ + 43 .IFDEF CYIPBLOCK_m0s8cpuss_VERSION + 44 0006 C046 NOP /* 1 2 Loop alignment padding */ + 45 .ELSE + 46 .IFDEF CYIPBLOCK_s8srsslt_VERSION + 47 .IFDEF CYIPBLOCK_m0s8cpussv2_VERSION + 48 .IFDEF CYIPBLOCK_mxusbpd_VERSION + 49 /* Do nothing */ + 50 .ELSE + 51 .IFDEF CYIPBLOCK_m0s8usbpd_VERSION + 52 /* Do nothing */ + 53 .ELSE + 54 NOP /* 1 2 Loop alignment padding */ + 55 .ENDIF + 56 .ENDIF + 57 .ENDIF + 58 .ENDIF + 59 /* Leave loop unaligned */ + 60 .ENDIF + 61 CyDelayCycles_loop: + 62 /* For CM0+ branch instruction takes 2 CPU cycles, for CM0 it takes 3 cycles */ + 63 .IFDEF CYDEV_CM0P_BASE + 64 ADDS r0, r0, #1 /* 1 2 Increment counter */ + 65 SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + 66 BNE CyDelayCycles_loop /* 2 2 2 CPU cycles (if branche is taken)*/ + 67 NOP /* 1 2 Loop alignment padding */ + 68 .ELSE + 69 0008 0138 SUBS r0, r0, #1 /* 1 2 Decrement counter */ + 70 000a FDD1 BNE CyDelayCycles_loop /* 3 2 3 CPU cycles (if branche is taken)*/ + 71 000c C046 NOP /* 1 2 Loop alignment padding */ + 72 000e C046 NOP /* 1 2 Loop alignment padding */ + 73 .ENDIF + 74 CyDelayCycles_done: + 75 0010 C046 NOP /* 1 2 Loop alignment padding */ + 76 0012 7047 BX lr /* 3 2 */ + 77 .endfunc + 78 + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 125 + + + 79 + 80 /******************************************************************************* + 81 * Function Name: CyEnterCriticalSection + 82 ****************************************************************************//** + 83 * + 84 * CyEnterCriticalSection disables interrupts and returns a value indicating + 85 * whether interrupts were previously enabled (the actual value depends on + 86 * whether the device is PSoC 3 or PSoC 5). + 87 * + 88 * Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit + 89 * with interrupts still enabled. The test and set of the interrupt bits is not + 90 * atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a + 91 * corrupting processor state, it must be the policy that all interrupt routines + 92 * restore the interrupt enable bits as they were found on entry. + 93 * + 94 * \return + 95 * uint8 + 96 * Returns 0 if interrupts were previously enabled or 1 if interrupts + 97 * were previously disabled. + 98 * + 99 *******************************************************************************/ + 100 /* uint8 CyEnterCriticalSection(void) */ + 101 .global CyEnterCriticalSection + 102 .func CyEnterCriticalSection, CyEnterCriticalSection + 103 .type CyEnterCriticalSection, %function + 104 .thumb_func + 105 CyEnterCriticalSection: + 106 0014 EFF31080 MRS r0, PRIMASK /* Save and return interrupt state */ + 107 0018 72B6 CPSID I /* Disable interrupts */ + 108 001a 7047 BX lr + 109 .endfunc + 110 + 111 + 112 /******************************************************************************* + 113 * Function Name: CyExitCriticalSection + 114 ****************************************************************************//** + 115 * + 116 * CyExitCriticalSection re-enables interrupts if they were enabled before + 117 * CyEnterCriticalSection was called. The argument should be the value returned + 118 * from CyEnterCriticalSection. + 119 * + 120 * \param uint8 savedIntrStatus: + 121 * Saved interrupt status returned by the CyEnterCriticalSection function. + 122 * + 123 * \return + 124 * None + 125 * + 126 *******************************************************************************/ + 127 /* void CyExitCriticalSection(uint8 savedIntrStatus) */ + 128 .global CyExitCriticalSection + 129 .func CyExitCriticalSection, CyExitCriticalSection + 130 .type CyExitCriticalSection, %function + 131 .thumb_func + 132 CyExitCriticalSection: + 133 001c 80F31088 MSR PRIMASK, r0 /* Restore interrupt state */ + 134 0020 7047 BX lr + 135 .endfunc + ARM GAS Generated_Source\PSoC4\CyBootAsmGnu.s page 126 + + + 136 + 137 0022 C046 .end diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyBootAsmGnu.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyBootAsmGnu.o new file mode 100644 index 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zzyDjnqabs2TyZ#OL)WO!06zPhPtO*=F2DQm?$^by-+cJ)z5kKs++SCJdjH8&pFLYYd-m)ve)H_vKjpvw!*8Gc z3;z2*{`T3wuJnJa`Tu^PKl|+Cuit-q_ci_f>F4tIAKSk^efOtN&p!M1-KTfYKKuIP z$7i4Y{N0DozWwg&U;c3V@Sc27zu)szUwQAo{`%+d{$6w6{rv8SKYT|D=mm10z5Dd( z=l5U#@`--`BmVm>VaYx5kHucnpTFUM)c^ij{rj)!Z^r$T`uo4uzuRBTmP3Kcl4*p&_AF3Kl<~( z`5*Pa#``byTkE?eeSbwX*2g(!ovd#|f0_*a^VtvdgLB>fYrOwPg!XUd{ZIPwSNxCq zUyI*Y^jo+4M{1Y*5Vy 1u)) + 226:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 227:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysFlashStartWriteRow + 228:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 229:Generated_Source\PSoC4/CyFlash.c **** * + 230:Generated_Source\PSoC4/CyFlash.c **** * Initiates a write to a row of Flash. A call to this API is non-blocking. + 231:Generated_Source\PSoC4/CyFlash.c **** * Use CySysFlashResumeWriteRow() to resume flash writes and + 232:Generated_Source\PSoC4/CyFlash.c **** * CySysFlashGetWriteRowStatus() to ascertain status of the write operation. + 233:Generated_Source\PSoC4/CyFlash.c **** * + 234:Generated_Source\PSoC4/CyFlash.c **** * The devices require HFCLK to be sourced by 48 MHz IMO during flash write. + 235:Generated_Source\PSoC4/CyFlash.c **** * This API will modify IMO configuration; it can be later restored to original + 236:Generated_Source\PSoC4/CyFlash.c **** * configuration by calling \ref CySysFlashGetWriteRowStatus(). + 237:Generated_Source\PSoC4/CyFlash.c **** * + 238:Generated_Source\PSoC4/CyFlash.c **** * \note The non-blocking operation does not return success status + 239:Generated_Source\PSoC4/CyFlash.c **** * CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API + 240:Generated_Source\PSoC4/CyFlash.c **** * is complete. The CPUSS_SYSARG register will be reflecting the SRAM address + 241:Generated_Source\PSoC4/CyFlash.c **** * during an ongoing non-blocking operation. + 242:Generated_Source\PSoC4/CyFlash.c **** * + 243:Generated_Source\PSoC4/CyFlash.c **** * \param rowNum The flash row number. The number of the flash rows is defined by + 244:Generated_Source\PSoC4/CyFlash.c **** * the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. Refer to the + 245:Generated_Source\PSoC4/CyFlash.c **** * device datasheet for the details. + 246:Generated_Source\PSoC4/CyFlash.c **** * \note The target flash array is calculated based on the specified flash row. + 247:Generated_Source\PSoC4/CyFlash.c **** * + 248:Generated_Source\PSoC4/CyFlash.c **** * \param rowData Array of bytes to write. The size of the array must be equal to + 249:Generated_Source\PSoC4/CyFlash.c **** * the flash row size. The flash row size for the selected device is defined by + 250:Generated_Source\PSoC4/CyFlash.c **** * the \ref CY_FLASH_SIZEOF_ROW macro. Refer to the device datasheet for the + 251:Generated_Source\PSoC4/CyFlash.c **** * details. + 252:Generated_Source\PSoC4/CyFlash.c **** * + 253:Generated_Source\PSoC4/CyFlash.c **** * \return \ref group_flash_status_codes + 254:Generated_Source\PSoC4/CyFlash.c **** * + 255:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 256:Generated_Source\PSoC4/CyFlash.c **** uint32 CySysFlashStartWriteRow(uint32 rowNum, const uint8 rowData[]) + 257:Generated_Source\PSoC4/CyFlash.c **** { + 258:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + 259:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA) / sizeof(uint32)]; + 260:Generated_Source\PSoC4/CyFlash.c **** uint8 interruptState; + 261:Generated_Source\PSoC4/CyFlash.c **** + 262:Generated_Source\PSoC4/CyFlash.c **** #if(CY_IP_SPCIF_SYNCHRONOUS) + 263:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + 264:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 265:Generated_Source\PSoC4/CyFlash.c **** + 266:Generated_Source\PSoC4/CyFlash.c **** if ((rowNum < CY_FLASH_NUMBER_ROWS) && (rowData != 0u)) + 267:Generated_Source\PSoC4/CyFlash.c **** { + 268:Generated_Source\PSoC4/CyFlash.c **** /* Copy data to be written into internal variable */ + 269:Generated_Source\PSoC4/CyFlash.c **** (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + 270:Generated_Source\PSoC4/CyFlash.c **** + 271:Generated_Source\PSoC4/CyFlash.c **** /* Load Flash Bytes */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 17 + + + 272:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MAC + 273:Generated_Source\PSoC4/CyFlash.c **** (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADD + 274:Generated_Source\PSoC4/CyFlash.c **** (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY + 275:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_KEY_ONE; + 276:Generated_Source\PSoC4/CyFlash.c **** parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + 277:Generated_Source\PSoC4/CyFlash.c **** + 278:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 279:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + 280:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 281:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 282:Generated_Source\PSoC4/CyFlash.c **** + 283:Generated_Source\PSoC4/CyFlash.c **** if(retValue == CY_SYS_FLASH_SUCCESS) + 284:Generated_Source\PSoC4/CyFlash.c **** { + 285:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************** + 286:Generated_Source\PSoC4/CyFlash.c **** * Mask all the exceptions to guarantee that Flash write will + 287:Generated_Source\PSoC4/CyFlash.c **** * occur in the atomic way. It will not affect system call + 288:Generated_Source\PSoC4/CyFlash.c **** * execution (flash row write) since it is executed in the NMI + 289:Generated_Source\PSoC4/CyFlash.c **** * context. + 290:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************/ + 291:Generated_Source\PSoC4/CyFlash.c **** interruptState = CyEnterCriticalSection(); + 292:Generated_Source\PSoC4/CyFlash.c **** + 293:Generated_Source\PSoC4/CyFlash.c **** #if(CY_IP_SPCIF_SYNCHRONOUS) + 294:Generated_Source\PSoC4/CyFlash.c **** clkCnfRetValue = CySysFlashClockBackup(); + 295:Generated_Source\PSoC4/CyFlash.c **** + 296:Generated_Source\PSoC4/CyFlash.c **** if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + 297:Generated_Source\PSoC4/CyFlash.c **** { + 298:Generated_Source\PSoC4/CyFlash.c **** retValue = CySysFlashClockConfig(); + 299:Generated_Source\PSoC4/CyFlash.c **** } + 300:Generated_Source\PSoC4/CyFlash.c **** #else + 301:Generated_Source\PSoC4/CyFlash.c **** (void)CySysFlashClockBackup(); + 302:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 303:Generated_Source\PSoC4/CyFlash.c **** + 304:Generated_Source\PSoC4/CyFlash.c **** if(retValue == CY_SYS_FLASH_SUCCESS) + 305:Generated_Source\PSoC4/CyFlash.c **** { + 306:Generated_Source\PSoC4/CyFlash.c **** /* Non-blocking Write Row */ + 307:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_NON_BLOC + 308:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_K + 309:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] |= (uint32)(rowNum << 16u); + 310:Generated_Source\PSoC4/CyFlash.c **** + 311:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 312:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_NON_BLOC + 313:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 314:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 315:Generated_Source\PSoC4/CyFlash.c **** } + 316:Generated_Source\PSoC4/CyFlash.c **** + 317:Generated_Source\PSoC4/CyFlash.c **** CyExitCriticalSection(interruptState); + 318:Generated_Source\PSoC4/CyFlash.c **** } + 319:Generated_Source\PSoC4/CyFlash.c **** } + 320:Generated_Source\PSoC4/CyFlash.c **** else + 321:Generated_Source\PSoC4/CyFlash.c **** { + 322:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_SYS_FLASH_INVALID_ADDR; + 323:Generated_Source\PSoC4/CyFlash.c **** } + 324:Generated_Source\PSoC4/CyFlash.c **** + 325:Generated_Source\PSoC4/CyFlash.c **** return (retValue); + 326:Generated_Source\PSoC4/CyFlash.c **** } + 327:Generated_Source\PSoC4/CyFlash.c **** + 328:Generated_Source\PSoC4/CyFlash.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 18 + + + 329:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 330:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysFlashGetWriteRowStatus + 331:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 332:Generated_Source\PSoC4/CyFlash.c **** * + 333:Generated_Source\PSoC4/CyFlash.c **** * Returns the current status of the flash write operation. + 334:Generated_Source\PSoC4/CyFlash.c **** * + 335:Generated_Source\PSoC4/CyFlash.c **** ** \note The non-blocking operation does not return success status + 336:Generated_Source\PSoC4/CyFlash.c **** * CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API + 337:Generated_Source\PSoC4/CyFlash.c **** * is complete. The CPUSS_SYSARG register will be reflecting the SRAM address + 338:Generated_Source\PSoC4/CyFlash.c **** * during an ongoing non-blocking operation. + 339:Generated_Source\PSoC4/CyFlash.c **** * Calling this API before starting a non-blocking write row operation + 340:Generated_Source\PSoC4/CyFlash.c **** * using the \ref CySysFlashStartWriteRow() API will cause improper operation. + 341:Generated_Source\PSoC4/CyFlash.c **** * + 342:Generated_Source\PSoC4/CyFlash.c **** * \return \ref group_flash_status_codes + 343:Generated_Source\PSoC4/CyFlash.c **** * + 344:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 345:Generated_Source\PSoC4/CyFlash.c **** uint32 CySysFlashGetWriteRowStatus(void) + 346:Generated_Source\PSoC4/CyFlash.c **** { + 347:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + 348:Generated_Source\PSoC4/CyFlash.c **** + 349:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 350:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 351:Generated_Source\PSoC4/CyFlash.c **** + 352:Generated_Source\PSoC4/CyFlash.c **** (void) CySysFlashClockRestore(); + 353:Generated_Source\PSoC4/CyFlash.c **** + 354:Generated_Source\PSoC4/CyFlash.c **** return (retValue); + 355:Generated_Source\PSoC4/CyFlash.c **** } + 356:Generated_Source\PSoC4/CyFlash.c **** + 357:Generated_Source\PSoC4/CyFlash.c **** + 358:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 359:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysFlashResumeWriteRow + 360:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 361:Generated_Source\PSoC4/CyFlash.c **** * + 362:Generated_Source\PSoC4/CyFlash.c **** * This API must be called, once the SPC interrupt is triggered to complete the + 363:Generated_Source\PSoC4/CyFlash.c **** * non-blocking operation. It is advised not to prolong calling this API for + 364:Generated_Source\PSoC4/CyFlash.c **** * more than 25 ms. + 365:Generated_Source\PSoC4/CyFlash.c **** * + 366:Generated_Source\PSoC4/CyFlash.c **** * The non-blocking write row API \ref CySysFlashStartWriteRow() requires that + 367:Generated_Source\PSoC4/CyFlash.c **** * this API be called 3 times to complete the write. This can be done by + 368:Generated_Source\PSoC4/CyFlash.c **** * configuring SPCIF interrupt and placing a call to this API. + 369:Generated_Source\PSoC4/CyFlash.c **** * + 370:Generated_Source\PSoC4/CyFlash.c **** * For CM0 based device, a non-blocking call to program a row of macro 0 + 371:Generated_Source\PSoC4/CyFlash.c **** * requires the user to set the CPUSS_CONFIG.VECS_IN_RAM bit so that the + 372:Generated_Source\PSoC4/CyFlash.c **** * interrupt vector for the SPC is fetched from the SRAM rather than the FLASH. + 373:Generated_Source\PSoC4/CyFlash.c **** * + 374:Generated_Source\PSoC4/CyFlash.c **** * For CM0+ based device, if the user wants to keep the vector table in flash + 375:Generated_Source\PSoC4/CyFlash.c **** * when performing non-blocking flash write then they need to make sure the + 376:Generated_Source\PSoC4/CyFlash.c **** * vector table is placed in the flash macro which is not getting programmed by + 377:Generated_Source\PSoC4/CyFlash.c **** * configuring the VTOR register. + 378:Generated_Source\PSoC4/CyFlash.c **** * + 379:Generated_Source\PSoC4/CyFlash.c **** * \note The non-blocking operation does not return success status + 380:Generated_Source\PSoC4/CyFlash.c **** * CY_SYS_FLASH_SUCCESS until the last Resume API is complete. + 381:Generated_Source\PSoC4/CyFlash.c **** * The CPUSS_SYSARG register will be reflecting the SRAM address during an + 382:Generated_Source\PSoC4/CyFlash.c **** * ongoing non-blocking operation. + 383:Generated_Source\PSoC4/CyFlash.c **** * + 384:Generated_Source\PSoC4/CyFlash.c **** * \return \ref group_flash_status_codes + 385:Generated_Source\PSoC4/CyFlash.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 19 + + + 386:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 387:Generated_Source\PSoC4/CyFlash.c **** uint32 CySysFlashResumeWriteRow(void) + 388:Generated_Source\PSoC4/CyFlash.c **** { + 389:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + 390:Generated_Source\PSoC4/CyFlash.c **** static volatile uint32 parameters[1u]; + 391:Generated_Source\PSoC4/CyFlash.c **** + 392:Generated_Source\PSoC4/CyFlash.c **** /* Resume */ + 393:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING) + 394:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + 395:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 396:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING; + 397:Generated_Source\PSoC4/CyFlash.c **** + 398:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 399:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 400:Generated_Source\PSoC4/CyFlash.c **** + 401:Generated_Source\PSoC4/CyFlash.c **** return (retValue); + 402:Generated_Source\PSoC4/CyFlash.c **** } + 403:Generated_Source\PSoC4/CyFlash.c **** + 404:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) */ + 405:Generated_Source\PSoC4/CyFlash.c **** + 406:Generated_Source\PSoC4/CyFlash.c **** + 407:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 408:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysFlashSetWaitCycles + 409:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 410:Generated_Source\PSoC4/CyFlash.c **** * + 411:Generated_Source\PSoC4/CyFlash.c **** * Sets the number of clock cycles the cache will wait before it samples data + 412:Generated_Source\PSoC4/CyFlash.c **** * coming back from Flash. This function must be called before increasing the + 413:Generated_Source\PSoC4/CyFlash.c **** * SYSCLK clock frequency. It can optionally be called after lowering SYSCLK + 414:Generated_Source\PSoC4/CyFlash.c **** * clock frequency in order to improve the CPU performance. + 415:Generated_Source\PSoC4/CyFlash.c **** * + 416:Generated_Source\PSoC4/CyFlash.c **** * \param freq The System clock frequency in MHz. + 417:Generated_Source\PSoC4/CyFlash.c **** * + 418:Generated_Source\PSoC4/CyFlash.c **** * \note Invalid frequency will be ignored in Release mode and the CPU will be + 419:Generated_Source\PSoC4/CyFlash.c **** * halted if project is compiled in Debug mode. + 420:Generated_Source\PSoC4/CyFlash.c **** * + 421:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 422:Generated_Source\PSoC4/CyFlash.c **** void CySysFlashSetWaitCycles(uint32 freq) + 423:Generated_Source\PSoC4/CyFlash.c **** { + 639 .loc 1 423 0 + 640 .cfi_startproc + 641 @ args = 0, pretend = 0, frame = 16 + 642 @ frame_needed = 1, uses_anonymous_args = 0 + 643 0000 90B5 push {r4, r7, lr} + 644 .cfi_def_cfa_offset 12 + 645 .cfi_offset 4, -12 + 646 .cfi_offset 7, -8 + 647 .cfi_offset 14, -4 + 648 0002 85B0 sub sp, sp, #20 + 649 .cfi_def_cfa_offset 32 + 650 0004 00AF add r7, sp, #0 + 651 .cfi_def_cfa_register 7 + 652 0006 7860 str r0, [r7, #4] + 424:Generated_Source\PSoC4/CyFlash.c **** uint8 interruptState; + 425:Generated_Source\PSoC4/CyFlash.c **** + 426:Generated_Source\PSoC4/CyFlash.c **** interruptState = CyEnterCriticalSection(); + 653 .loc 1 426 0 + 654 0008 0F23 movs r3, #15 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 20 + + + 655 000a FC18 adds r4, r7, r3 + 656 000c FFF7FEFF bl CyEnterCriticalSection + 657 0010 0300 movs r3, r0 + 658 0012 2370 strb r3, [r4] + 427:Generated_Source\PSoC4/CyFlash.c **** + 428:Generated_Source\PSoC4/CyFlash.c **** #if (CY_IP_CPUSS) + 429:Generated_Source\PSoC4/CyFlash.c **** + 430:Generated_Source\PSoC4/CyFlash.c **** if ( freq <= CY_FLASH_SYSCLK_BOUNDARY_MHZ ) + 659 .loc 1 430 0 + 660 0014 7B68 ldr r3, [r7, #4] + 661 0016 182B cmp r3, #24 + 662 0018 06D8 bhi .L34 + 431:Generated_Source\PSoC4/CyFlash.c **** { + 432:Generated_Source\PSoC4/CyFlash.c **** CY_SYS_CLK_SELECT_REG &= (uint32)(~CY_FLASH_WAIT_STATE_EN); + 663 .loc 1 432 0 + 664 001a 0C4B ldr r3, .L36 + 665 001c 0B4A ldr r2, .L36 + 666 001e 1268 ldr r2, [r2] + 667 0020 0B49 ldr r1, .L36+4 + 668 0022 0A40 ands r2, r1 + 669 0024 1A60 str r2, [r3] + 670 0026 06E0 b .L35 + 671 .L34: + 433:Generated_Source\PSoC4/CyFlash.c **** } + 434:Generated_Source\PSoC4/CyFlash.c **** else + 435:Generated_Source\PSoC4/CyFlash.c **** { + 436:Generated_Source\PSoC4/CyFlash.c **** CY_SYS_CLK_SELECT_REG |= CY_FLASH_WAIT_STATE_EN; + 672 .loc 1 436 0 + 673 0028 084B ldr r3, .L36 + 674 002a 084A ldr r2, .L36 + 675 002c 1268 ldr r2, [r2] + 676 002e 8021 movs r1, #128 + 677 0030 C902 lsls r1, r1, #11 + 678 0032 0A43 orrs r2, r1 + 679 0034 1A60 str r2, [r3] + 680 .L35: + 437:Generated_Source\PSoC4/CyFlash.c **** } + 438:Generated_Source\PSoC4/CyFlash.c **** #else + 439:Generated_Source\PSoC4/CyFlash.c **** #if (CY_IP_CPUSS_FLASHC_PRESENT) + 440:Generated_Source\PSoC4/CyFlash.c **** /* CY_IP_FM and CY_IP_FS */ + 441:Generated_Source\PSoC4/CyFlash.c **** if (freq <= CY_FLASH_CTL_WS_0_FREQ_MAX) + 442:Generated_Source\PSoC4/CyFlash.c **** { + 443:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_0_V + 444:Generated_Source\PSoC4/CyFlash.c **** } else + 445:Generated_Source\PSoC4/CyFlash.c **** if (freq <= CY_FLASH_CTL_WS_1_FREQ_MAX) + 446:Generated_Source\PSoC4/CyFlash.c **** { + 447:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_1_V + 448:Generated_Source\PSoC4/CyFlash.c **** } else + 449:Generated_Source\PSoC4/CyFlash.c **** #if (CY_IP_FMLT || CY_IP_FSLT) + 450:Generated_Source\PSoC4/CyFlash.c **** if (freq <= CY_FLASH_CTL_WS_2_FREQ_MAX) + 451:Generated_Source\PSoC4/CyFlash.c **** { + 452:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS + 453:Generated_Source\PSoC4/CyFlash.c **** } + 454:Generated_Source\PSoC4/CyFlash.c **** else + 455:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_FMLT || CY_IP_FSLT) */ + 456:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + 457:Generated_Source\PSoC4/CyFlash.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 21 + + + 458:Generated_Source\PSoC4/CyFlash.c **** /* Halt CPU in debug mode if frequency is invalid */ + 459:Generated_Source\PSoC4/CyFlash.c **** CYASSERT(0u != 0u); + 460:Generated_Source\PSoC4/CyFlash.c **** } + 461:Generated_Source\PSoC4/CyFlash.c **** + 462:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_CPUSS) */ + 463:Generated_Source\PSoC4/CyFlash.c **** + 464:Generated_Source\PSoC4/CyFlash.c **** CyExitCriticalSection(interruptState); + 681 .loc 1 464 0 + 682 0036 0F23 movs r3, #15 + 683 0038 FB18 adds r3, r7, r3 + 684 003a 1B78 ldrb r3, [r3] + 685 003c 1800 movs r0, r3 + 686 003e FFF7FEFF bl CyExitCriticalSection + 465:Generated_Source\PSoC4/CyFlash.c **** } + 687 .loc 1 465 0 + 688 0042 C046 nop + 689 0044 BD46 mov sp, r7 + 690 0046 05B0 add sp, sp, #20 + 691 @ sp needed + 692 0048 90BD pop {r4, r7, pc} + 693 .L37: + 694 004a C046 .align 2 + 695 .L36: + 696 004c 00010B40 .word 1074462976 + 697 0050 FFFFFBFF .word -262145 + 698 .cfi_endproc + 699 .LFE1: + 700 .size CySysFlashSetWaitCycles, .-CySysFlashSetWaitCycles + 701 .section .text.CySysFlashClockBackup,"ax",%progbits + 702 .align 2 + 703 .code 16 + 704 .thumb_func + 705 .type CySysFlashClockBackup, %function + 706 CySysFlashClockBackup: + 707 .LFB2: + 466:Generated_Source\PSoC4/CyFlash.c **** + 467:Generated_Source\PSoC4/CyFlash.c **** + 468:Generated_Source\PSoC4/CyFlash.c **** #if (CY_SFLASH_XTRA_ROWS) + 469:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 470:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysSFlashWriteUserRow + 471:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 472:Generated_Source\PSoC4/CyFlash.c **** * + 473:Generated_Source\PSoC4/CyFlash.c **** * Writes data to a row of SFlash user configurable area. + 474:Generated_Source\PSoC4/CyFlash.c **** * + 475:Generated_Source\PSoC4/CyFlash.c **** * This API is applicable for PSoC 4100 BLE, PSoC 4200 BLE, PSoC 4100M, + 476:Generated_Source\PSoC4/CyFlash.c **** * PSoC 4200M, and PSoC 4200L family of devices. + 477:Generated_Source\PSoC4/CyFlash.c **** * + 478:Generated_Source\PSoC4/CyFlash.c **** * \param rowNum The flash row number. The flash row number. The number of the + 479:Generated_Source\PSoC4/CyFlash.c **** * flash rows is defined by the CY_SFLASH_NUMBER_USERROWS macro for the selected + 480:Generated_Source\PSoC4/CyFlash.c **** * device. Valid range is 0-3. Refer to the device TRM for details. + 481:Generated_Source\PSoC4/CyFlash.c **** * + 482:Generated_Source\PSoC4/CyFlash.c **** * \param rowData Array of bytes to write. The size of the array must be equal to + 483:Generated_Source\PSoC4/CyFlash.c **** * the flash row size. The flash row size for the selected device is defined by + 484:Generated_Source\PSoC4/CyFlash.c **** * the \ref CY_SFLASH_SIZEOF_USERROW macro. Refer to the device TRM for the + 485:Generated_Source\PSoC4/CyFlash.c **** * details. + 486:Generated_Source\PSoC4/CyFlash.c **** * + 487:Generated_Source\PSoC4/CyFlash.c **** * \return \ref group_flash_status_codes + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 22 + + + 488:Generated_Source\PSoC4/CyFlash.c **** * + 489:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 490:Generated_Source\PSoC4/CyFlash.c **** uint32 CySysSFlashWriteUserRow(uint32 rowNum, const uint8 rowData[]) + 491:Generated_Source\PSoC4/CyFlash.c **** { + 492:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + 493:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + 494:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA)/4u]; + 495:Generated_Source\PSoC4/CyFlash.c **** uint8 interruptState; + 496:Generated_Source\PSoC4/CyFlash.c **** + 497:Generated_Source\PSoC4/CyFlash.c **** + 498:Generated_Source\PSoC4/CyFlash.c **** if ((rowNum < CY_SFLASH_NUMBER_USERROWS) && (rowData != 0u)) + 499:Generated_Source\PSoC4/CyFlash.c **** { + 500:Generated_Source\PSoC4/CyFlash.c **** /* Load Flash Bytes */ + 501:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MAC + 502:Generated_Source\PSoC4/CyFlash.c **** (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADD + 503:Generated_Source\PSoC4/CyFlash.c **** (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY + 504:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_KEY_ONE; + 505:Generated_Source\PSoC4/CyFlash.c **** parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + 506:Generated_Source\PSoC4/CyFlash.c **** + 507:Generated_Source\PSoC4/CyFlash.c **** (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + 508:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 509:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + 510:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 511:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 512:Generated_Source\PSoC4/CyFlash.c **** + 513:Generated_Source\PSoC4/CyFlash.c **** if(retValue == CY_SYS_FLASH_SUCCESS) + 514:Generated_Source\PSoC4/CyFlash.c **** { + 515:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************** + 516:Generated_Source\PSoC4/CyFlash.c **** * Mask all the exceptions to guarantee that Flash write will + 517:Generated_Source\PSoC4/CyFlash.c **** * occur in the atomic way. It will not affect system call + 518:Generated_Source\PSoC4/CyFlash.c **** * execution (flash row write) since it is executed in the NMI + 519:Generated_Source\PSoC4/CyFlash.c **** * context. + 520:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************/ + 521:Generated_Source\PSoC4/CyFlash.c **** interruptState = CyEnterCriticalSection(); + 522:Generated_Source\PSoC4/CyFlash.c **** + 523:Generated_Source\PSoC4/CyFlash.c **** clkCnfRetValue = CySysFlashClockBackup(); + 524:Generated_Source\PSoC4/CyFlash.c **** + 525:Generated_Source\PSoC4/CyFlash.c **** #if(CY_IP_SPCIF_SYNCHRONOUS) + 526:Generated_Source\PSoC4/CyFlash.c **** if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + 527:Generated_Source\PSoC4/CyFlash.c **** { + 528:Generated_Source\PSoC4/CyFlash.c **** retValue = CySysFlashClockConfig(); + 529:Generated_Source\PSoC4/CyFlash.c **** } + 530:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 531:Generated_Source\PSoC4/CyFlash.c **** + 532:Generated_Source\PSoC4/CyFlash.c **** if(retValue == CY_SYS_FLASH_SUCCESS) + 533:Generated_Source\PSoC4/CyFlash.c **** { + 534:Generated_Source\PSoC4/CyFlash.c **** /* Write User Sflash Row */ + 535:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_WRITE_SF + 536:Generated_Source\PSoC4/CyFlash.c **** parameters[1u] = (uint32) rowNum; + 537:Generated_Source\PSoC4/CyFlash.c **** + 538:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 539:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_WRITE_SF + 540:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 541:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 542:Generated_Source\PSoC4/CyFlash.c **** } + 543:Generated_Source\PSoC4/CyFlash.c **** + 544:Generated_Source\PSoC4/CyFlash.c **** if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 23 + + + 545:Generated_Source\PSoC4/CyFlash.c **** { + 546:Generated_Source\PSoC4/CyFlash.c **** clkCnfRetValue = CySysFlashClockRestore(); + 547:Generated_Source\PSoC4/CyFlash.c **** } + 548:Generated_Source\PSoC4/CyFlash.c **** CyExitCriticalSection(interruptState); + 549:Generated_Source\PSoC4/CyFlash.c **** } + 550:Generated_Source\PSoC4/CyFlash.c **** } + 551:Generated_Source\PSoC4/CyFlash.c **** else + 552:Generated_Source\PSoC4/CyFlash.c **** { + 553:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_SYS_FLASH_INVALID_ADDR; + 554:Generated_Source\PSoC4/CyFlash.c **** } + 555:Generated_Source\PSoC4/CyFlash.c **** + 556:Generated_Source\PSoC4/CyFlash.c **** return (retValue); + 557:Generated_Source\PSoC4/CyFlash.c **** } + 558:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_SFLASH_XTRA_ROWS) */ + 559:Generated_Source\PSoC4/CyFlash.c **** + 560:Generated_Source\PSoC4/CyFlash.c **** + 561:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 562:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysFlashClockBackup + 563:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 564:Generated_Source\PSoC4/CyFlash.c **** * + 565:Generated_Source\PSoC4/CyFlash.c **** * Backups the device clock configuration. + 566:Generated_Source\PSoC4/CyFlash.c **** * + 567:Generated_Source\PSoC4/CyFlash.c **** * \return The same as \ref CySysFlashWriteRow(). + 568:Generated_Source\PSoC4/CyFlash.c **** * + 569:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 570:Generated_Source\PSoC4/CyFlash.c **** static cystatus CySysFlashClockBackup(void) + 571:Generated_Source\PSoC4/CyFlash.c **** { + 708 .loc 1 571 0 + 709 .cfi_startproc + 710 @ args = 0, pretend = 0, frame = 8 + 711 @ frame_needed = 1, uses_anonymous_args = 0 + 712 0000 80B5 push {r7, lr} + 713 .cfi_def_cfa_offset 8 + 714 .cfi_offset 7, -8 + 715 .cfi_offset 14, -4 + 716 0002 82B0 sub sp, sp, #8 + 717 .cfi_def_cfa_offset 16 + 718 0004 00AF add r7, sp, #0 + 719 .cfi_def_cfa_register 7 + 572:Generated_Source\PSoC4/CyFlash.c **** cystatus retValue = CY_SYS_FLASH_SUCCESS; + 720 .loc 1 572 0 + 721 0006 0023 movs r3, #0 + 722 0008 7B60 str r3, [r7, #4] + 573:Generated_Source\PSoC4/CyFlash.c **** #if(!CY_IP_FM) + 574:Generated_Source\PSoC4/CyFlash.c **** #if !(CY_PSOC4_4000) + 575:Generated_Source\PSoC4/CyFlash.c **** #if (CY_IP_SPCIF_SYNCHRONOUS) + 576:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 parameters[2u]; + 577:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 578:Generated_Source\PSoC4/CyFlash.c **** #endif /* !(CY_PSOC4_4000) */ + 579:Generated_Source\PSoC4/CyFlash.c **** #endif /* (!CY_IP_FM) */ + 580:Generated_Source\PSoC4/CyFlash.c **** + 581:Generated_Source\PSoC4/CyFlash.c **** #if(CY_IP_FM) + 582:Generated_Source\PSoC4/CyFlash.c **** + 583:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************** + 584:Generated_Source\PSoC4/CyFlash.c **** * Preserve IMO configuration that could be changed during + 585:Generated_Source\PSoC4/CyFlash.c **** * system call execution (Cypress ID #150448). + 586:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************/ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 24 + + + 587:Generated_Source\PSoC4/CyFlash.c **** cySysFlashBackup.imoConfigReg = CY_SYS_CLK_IMO_CONFIG_REG; + 723 .loc 1 587 0 + 724 000a 044B ldr r3, .L40 + 725 000c 1A68 ldr r2, [r3] + 726 000e 044B ldr r3, .L40+4 + 727 0010 1A60 str r2, [r3] + 588:Generated_Source\PSoC4/CyFlash.c **** + 589:Generated_Source\PSoC4/CyFlash.c **** #else /* (CY_IP_FMLT) */ + 590:Generated_Source\PSoC4/CyFlash.c **** + 591:Generated_Source\PSoC4/CyFlash.c **** #if (CY_PSOC4_4000) + 592:Generated_Source\PSoC4/CyFlash.c **** + 593:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************************** + 594:Generated_Source\PSoC4/CyFlash.c **** * Perform firmware clock settings backup for the PSOC4 4000 devices (the + 595:Generated_Source\PSoC4/CyFlash.c **** * corresponding system call is not available). + 596:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************************/ + 597:Generated_Source\PSoC4/CyFlash.c **** + 598:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************************** + 599:Generated_Source\PSoC4/CyFlash.c **** * The registers listed below are modified by CySysFlashClockConfig(). + 600:Generated_Source\PSoC4/CyFlash.c **** * + 601:Generated_Source\PSoC4/CyFlash.c **** * The registers to be saved: + 602:Generated_Source\PSoC4/CyFlash.c **** * - CY_SYS_CLK_IMO_CONFIG_REG - IMO enable state. + 603:Generated_Source\PSoC4/CyFlash.c **** * - CY_SYS_CLK_SELECT_REG - HFCLK source, divider, pump source. Save + 604:Generated_Source\PSoC4/CyFlash.c **** * entire register as it can be directly + 605:Generated_Source\PSoC4/CyFlash.c **** * written on restore (no special + 606:Generated_Source\PSoC4/CyFlash.c **** * requirements). + 607:Generated_Source\PSoC4/CyFlash.c **** * - CY_SYS_CLK_IMO_SELECT_REG - Save IMO frequency. + 608:Generated_Source\PSoC4/CyFlash.c **** * + 609:Generated_Source\PSoC4/CyFlash.c **** * The registers not to be saved: + 610:Generated_Source\PSoC4/CyFlash.c **** * - CY_SYS_CLK_IMO_TRIM1_REG - No need to save. Function of frequency. + 611:Generated_Source\PSoC4/CyFlash.c **** * Restored by CySysClkWriteImoFreq(). + 612:Generated_Source\PSoC4/CyFlash.c **** * - CY_SYS_CLK_IMO_TRIM3_REG - No need to save. Function of frequency. + 613:Generated_Source\PSoC4/CyFlash.c **** * Restored by CySysClkWriteImoFreq(). + 614:Generated_Source\PSoC4/CyFlash.c **** * - REG_CPUSS_FLASH_CTL - Flash wait cycles. Unmodified due to system + 615:Generated_Source\PSoC4/CyFlash.c **** * clock 16 MHz limit. + 616:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************************/ + 617:Generated_Source\PSoC4/CyFlash.c **** + 618:Generated_Source\PSoC4/CyFlash.c **** cySysFlashBackup.clkSelectReg = CY_SYS_CLK_SELECT_REG; + 619:Generated_Source\PSoC4/CyFlash.c **** cySysFlashBackup.clkImoEna = CY_SYS_CLK_IMO_CONFIG_REG & CY_SYS_CLK_IMO_CONFIG_ENABLE; + 620:Generated_Source\PSoC4/CyFlash.c **** cySysFlashBackup.clkImoFreq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ + (CY_SYS_CLK_IMO_SELECT_REG << + 621:Generated_Source\PSoC4/CyFlash.c **** + 622:Generated_Source\PSoC4/CyFlash.c **** #else + 623:Generated_Source\PSoC4/CyFlash.c **** + 624:Generated_Source\PSoC4/CyFlash.c **** #if (CY_IP_SPCIF_SYNCHRONOUS) + 625:Generated_Source\PSoC4/CyFlash.c **** /* FM-Lite Clock Backup System Call */ + 626:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] = + 627:Generated_Source\PSoC4/CyFlash.c **** (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_BACKUP) << CY_FLASH_PARAM_KEY_ + 628:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_KEY_ONE); + 629:Generated_Source\PSoC4/CyFlash.c **** parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + 630:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 631:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_BACKUP; + 632:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 633:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 634:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 635:Generated_Source\PSoC4/CyFlash.c **** + 636:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_PSOC4_4000) */ + 637:Generated_Source\PSoC4/CyFlash.c **** + 638:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_FM) */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 25 + + + 639:Generated_Source\PSoC4/CyFlash.c **** + 640:Generated_Source\PSoC4/CyFlash.c **** return (retValue); + 728 .loc 1 640 0 + 729 0012 7B68 ldr r3, [r7, #4] + 641:Generated_Source\PSoC4/CyFlash.c **** } + 730 .loc 1 641 0 + 731 0014 1800 movs r0, r3 + 732 0016 BD46 mov sp, r7 + 733 0018 02B0 add sp, sp, #8 + 734 @ sp needed + 735 001a 80BD pop {r7, pc} + 736 .L41: + 737 .align 2 + 738 .L40: + 739 001c 08010B40 .word 1074462984 + 740 0020 00000000 .word cySysFlashBackup + 741 .cfi_endproc + 742 .LFE2: + 743 .size CySysFlashClockBackup, .-CySysFlashClockBackup + 744 .section .text.CySysFlashClockRestore,"ax",%progbits + 745 .align 2 + 746 .code 16 + 747 .thumb_func + 748 .type CySysFlashClockRestore, %function + 749 CySysFlashClockRestore: + 750 .LFB3: + 642:Generated_Source\PSoC4/CyFlash.c **** + 643:Generated_Source\PSoC4/CyFlash.c **** + 644:Generated_Source\PSoC4/CyFlash.c **** #if(CY_IP_SPCIF_SYNCHRONOUS) + 645:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 646:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysFlashClockConfig + 647:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 648:Generated_Source\PSoC4/CyFlash.c **** * + 649:Generated_Source\PSoC4/CyFlash.c **** * Configures the device clocks for the flash writing. + 650:Generated_Source\PSoC4/CyFlash.c **** * + 651:Generated_Source\PSoC4/CyFlash.c **** * \return The same as \ref CySysFlashWriteRow(). + 652:Generated_Source\PSoC4/CyFlash.c **** * + 653:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 654:Generated_Source\PSoC4/CyFlash.c **** static cystatus CySysFlashClockConfig(void) + 655:Generated_Source\PSoC4/CyFlash.c **** { + 656:Generated_Source\PSoC4/CyFlash.c **** cystatus retValue = CY_SYS_FLASH_SUCCESS; + 657:Generated_Source\PSoC4/CyFlash.c **** + 658:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************************** + 659:Generated_Source\PSoC4/CyFlash.c **** * The FM-Lite IP uses the IMO at 48MHz for the pump clock and SPC timer + 660:Generated_Source\PSoC4/CyFlash.c **** * clock. The PUMP_SEL and HF clock must be set to IMO before calling Flash + 661:Generated_Source\PSoC4/CyFlash.c **** * write or erase operation. + 662:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************************/ + 663:Generated_Source\PSoC4/CyFlash.c **** #if (CY_PSOC4_4000) + 664:Generated_Source\PSoC4/CyFlash.c **** + 665:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************************** + 666:Generated_Source\PSoC4/CyFlash.c **** * Perform firmware clock settings setup for the PSOC4 4000 devices (the + 667:Generated_Source\PSoC4/CyFlash.c **** * corresponding system call is not reliable): + 668:Generated_Source\PSoC4/CyFlash.c **** * - The IMO frequency should be 48 MHz + 669:Generated_Source\PSoC4/CyFlash.c **** * - The IMO should be source for the HFCLK + 670:Generated_Source\PSoC4/CyFlash.c **** * - The IMO should be the source for the charge pump clock + 671:Generated_Source\PSoC4/CyFlash.c **** * + 672:Generated_Source\PSoC4/CyFlash.c **** * Note The structure members used below are initialized by + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 26 + + + 673:Generated_Source\PSoC4/CyFlash.c **** * the CySysFlashClockBackup() function. + 674:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************************/ + 675:Generated_Source\PSoC4/CyFlash.c **** if ((cySysFlashBackup.clkImoFreq != 48u) || + 676:Generated_Source\PSoC4/CyFlash.c **** ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCLK_IM + 677:Generated_Source\PSoC4/CyFlash.c **** (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELECT_P + 678:Generated_Source\PSoC4/CyFlash.c **** CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + 679:Generated_Source\PSoC4/CyFlash.c **** { + 680:Generated_Source\PSoC4/CyFlash.c **** /*********************************************************************** + 681:Generated_Source\PSoC4/CyFlash.c **** Set HFCLK divider to divide-by-4 to ensure that System clock frequency + 682:Generated_Source\PSoC4/CyFlash.c **** * is within the valid limit (16 MHz for the PSoC4 4000). + 683:Generated_Source\PSoC4/CyFlash.c **** ***********************************************************************/ + 684:Generated_Source\PSoC4/CyFlash.c **** CySysClkWriteHfclkDiv(CY_SYS_CLK_HFCLK_DIV_4); + 685:Generated_Source\PSoC4/CyFlash.c **** + 686:Generated_Source\PSoC4/CyFlash.c **** /* The IMO frequency should be 48 MHz */ + 687:Generated_Source\PSoC4/CyFlash.c **** if (cySysFlashBackup.clkImoFreq != 48u) + 688:Generated_Source\PSoC4/CyFlash.c **** { + 689:Generated_Source\PSoC4/CyFlash.c **** CySysClkWriteImoFreq(48u); + 690:Generated_Source\PSoC4/CyFlash.c **** } + 691:Generated_Source\PSoC4/CyFlash.c **** CySysClkImoStart(); + 692:Generated_Source\PSoC4/CyFlash.c **** + 693:Generated_Source\PSoC4/CyFlash.c **** /* The IMO should be source for the HFCLK */ + 694:Generated_Source\PSoC4/CyFlash.c **** CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO); + 695:Generated_Source\PSoC4/CyFlash.c **** + 696:Generated_Source\PSoC4/CyFlash.c **** /* The IMO should be the source for the charge pump clock */ + 697:Generated_Source\PSoC4/CyFlash.c **** CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & + 698:Generated_Source\PSoC4/CyFlash.c **** ((uint32)~(uint32)(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) + 699:Generated_Source\PSoC4/CyFlash.c **** ((uint32)((uint32)1u << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT)); + 700:Generated_Source\PSoC4/CyFlash.c **** } + 701:Generated_Source\PSoC4/CyFlash.c **** + 702:Generated_Source\PSoC4/CyFlash.c **** #else + 703:Generated_Source\PSoC4/CyFlash.c **** + 704:Generated_Source\PSoC4/CyFlash.c **** /* FM-Lite Clock Configuration */ + 705:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = + 706:Generated_Source\PSoC4/CyFlash.c **** (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_CONFIG) << CY_FLASH_PARAM_KEY_TWO_OFFS + 707:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_KEY_ONE); + 708:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_CONFIG; + 709:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 710:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 711:Generated_Source\PSoC4/CyFlash.c **** + 712:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_PSOC4_4000) */ + 713:Generated_Source\PSoC4/CyFlash.c **** + 714:Generated_Source\PSoC4/CyFlash.c **** return (retValue); + 715:Generated_Source\PSoC4/CyFlash.c **** } + 716:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 717:Generated_Source\PSoC4/CyFlash.c **** + 718:Generated_Source\PSoC4/CyFlash.c **** + 719:Generated_Source\PSoC4/CyFlash.c **** /******************************************************************************* + 720:Generated_Source\PSoC4/CyFlash.c **** * Function Name: CySysFlashClockRestore + 721:Generated_Source\PSoC4/CyFlash.c **** ****************************************************************************//** + 722:Generated_Source\PSoC4/CyFlash.c **** * + 723:Generated_Source\PSoC4/CyFlash.c **** * Restores the device clock configuration. + 724:Generated_Source\PSoC4/CyFlash.c **** * + 725:Generated_Source\PSoC4/CyFlash.c **** * \return The same as \ref CySysFlashWriteRow(). + 726:Generated_Source\PSoC4/CyFlash.c **** * + 727:Generated_Source\PSoC4/CyFlash.c **** *******************************************************************************/ + 728:Generated_Source\PSoC4/CyFlash.c **** static cystatus CySysFlashClockRestore(void) + 729:Generated_Source\PSoC4/CyFlash.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 27 + + + 751 .loc 1 729 0 + 752 .cfi_startproc + 753 @ args = 0, pretend = 0, frame = 8 + 754 @ frame_needed = 1, uses_anonymous_args = 0 + 755 0000 80B5 push {r7, lr} + 756 .cfi_def_cfa_offset 8 + 757 .cfi_offset 7, -8 + 758 .cfi_offset 14, -4 + 759 0002 82B0 sub sp, sp, #8 + 760 .cfi_def_cfa_offset 16 + 761 0004 00AF add r7, sp, #0 + 762 .cfi_def_cfa_register 7 + 730:Generated_Source\PSoC4/CyFlash.c **** cystatus retValue = CY_SYS_FLASH_SUCCESS; + 763 .loc 1 730 0 + 764 0006 0023 movs r3, #0 + 765 0008 7B60 str r3, [r7, #4] + 731:Generated_Source\PSoC4/CyFlash.c **** #if(!CY_IP_FM) + 732:Generated_Source\PSoC4/CyFlash.c **** #if !(CY_PSOC4_4000) + 733:Generated_Source\PSoC4/CyFlash.c **** #if (CY_IP_SPCIF_SYNCHRONOUS) + 734:Generated_Source\PSoC4/CyFlash.c **** volatile uint32 parameters[2u]; + 735:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 736:Generated_Source\PSoC4/CyFlash.c **** #endif /* !(CY_PSOC4_4000) */ + 737:Generated_Source\PSoC4/CyFlash.c **** #endif /* (!CY_IP_FM) */ + 738:Generated_Source\PSoC4/CyFlash.c **** + 739:Generated_Source\PSoC4/CyFlash.c **** #if(CY_IP_FM) + 740:Generated_Source\PSoC4/CyFlash.c **** + 741:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************** + 742:Generated_Source\PSoC4/CyFlash.c **** * Restore IMO configuration that could be changed during + 743:Generated_Source\PSoC4/CyFlash.c **** * system call execution (Cypress ID #150448). + 744:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************/ + 745:Generated_Source\PSoC4/CyFlash.c **** CY_SYS_CLK_IMO_CONFIG_REG = cySysFlashBackup.imoConfigReg; + 766 .loc 1 745 0 + 767 000a 044A ldr r2, .L44 + 768 000c 044B ldr r3, .L44+4 + 769 000e 1B68 ldr r3, [r3] + 770 0010 1360 str r3, [r2] + 746:Generated_Source\PSoC4/CyFlash.c **** + 747:Generated_Source\PSoC4/CyFlash.c **** #else + 748:Generated_Source\PSoC4/CyFlash.c **** + 749:Generated_Source\PSoC4/CyFlash.c **** #if (CY_PSOC4_4000) + 750:Generated_Source\PSoC4/CyFlash.c **** + 751:Generated_Source\PSoC4/CyFlash.c **** /*************************************************************************** + 752:Generated_Source\PSoC4/CyFlash.c **** * Perform firmware clock settings restore for the PSOC4 4000 devices (the + 753:Generated_Source\PSoC4/CyFlash.c **** * corresponding system call is not available). + 754:Generated_Source\PSoC4/CyFlash.c **** ***************************************************************************/ + 755:Generated_Source\PSoC4/CyFlash.c **** + 756:Generated_Source\PSoC4/CyFlash.c **** /* Restore clock settings */ + 757:Generated_Source\PSoC4/CyFlash.c **** if ((cySysFlashBackup.clkImoFreq != 48u) || + 758:Generated_Source\PSoC4/CyFlash.c **** ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCL + 759:Generated_Source\PSoC4/CyFlash.c **** (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELE + 760:Generated_Source\PSoC4/CyFlash.c **** CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + 761:Generated_Source\PSoC4/CyFlash.c **** { + 762:Generated_Source\PSoC4/CyFlash.c **** /* Restore IMO frequency if needed */ + 763:Generated_Source\PSoC4/CyFlash.c **** if (cySysFlashBackup.clkImoFreq != 48u) + 764:Generated_Source\PSoC4/CyFlash.c **** { + 765:Generated_Source\PSoC4/CyFlash.c **** CySysClkWriteImoFreq(cySysFlashBackup.clkImoFreq); + 766:Generated_Source\PSoC4/CyFlash.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 28 + + + 767:Generated_Source\PSoC4/CyFlash.c **** + 768:Generated_Source\PSoC4/CyFlash.c **** /* Restore HFCLK clock source */ + 769:Generated_Source\PSoC4/CyFlash.c **** CySysClkWriteHfclkDirect(cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_M + 770:Generated_Source\PSoC4/CyFlash.c **** + 771:Generated_Source\PSoC4/CyFlash.c **** /* Restore HFCLK divider and source for pump */ + 772:Generated_Source\PSoC4/CyFlash.c **** CY_SYS_CLK_SELECT_REG = cySysFlashBackup.clkSelectReg; + 773:Generated_Source\PSoC4/CyFlash.c **** + 774:Generated_Source\PSoC4/CyFlash.c **** /* Stop IMO if needed */ + 775:Generated_Source\PSoC4/CyFlash.c **** if (0u == cySysFlashBackup.clkImoEna) + 776:Generated_Source\PSoC4/CyFlash.c **** { + 777:Generated_Source\PSoC4/CyFlash.c **** CySysClkImoStop(); + 778:Generated_Source\PSoC4/CyFlash.c **** } + 779:Generated_Source\PSoC4/CyFlash.c **** } + 780:Generated_Source\PSoC4/CyFlash.c **** + 781:Generated_Source\PSoC4/CyFlash.c **** #else + 782:Generated_Source\PSoC4/CyFlash.c **** + 783:Generated_Source\PSoC4/CyFlash.c **** #if (CY_IP_SPCIF_SYNCHRONOUS) + 784:Generated_Source\PSoC4/CyFlash.c **** /* FM-Lite Clock Restore */ + 785:Generated_Source\PSoC4/CyFlash.c **** parameters[0u] = + 786:Generated_Source\PSoC4/CyFlash.c **** (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY + 787:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_KEY_ONE); + 788:Generated_Source\PSoC4/CyFlash.c **** parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + 789:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 790:Generated_Source\PSoC4/CyFlash.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + 791:Generated_Source\PSoC4/CyFlash.c **** CY_NOP; + 792:Generated_Source\PSoC4/CyFlash.c **** retValue = CY_FLASH_API_RETURN; + 793:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + 794:Generated_Source\PSoC4/CyFlash.c **** + 795:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_PSOC4_4000) */ + 796:Generated_Source\PSoC4/CyFlash.c **** + 797:Generated_Source\PSoC4/CyFlash.c **** #endif /* (CY_IP_FM) */ + 798:Generated_Source\PSoC4/CyFlash.c **** + 799:Generated_Source\PSoC4/CyFlash.c **** return (retValue); + 771 .loc 1 799 0 + 772 0012 7B68 ldr r3, [r7, #4] + 800:Generated_Source\PSoC4/CyFlash.c **** } + 773 .loc 1 800 0 + 774 0014 1800 movs r0, r3 + 775 0016 BD46 mov sp, r7 + 776 0018 02B0 add sp, sp, #8 + 777 @ sp needed + 778 001a 80BD pop {r7, pc} + 779 .L45: + 780 .align 2 + 781 .L44: + 782 001c 08010B40 .word 1074462984 + 783 0020 00000000 .word cySysFlashBackup + 784 .cfi_endproc + 785 .LFE3: + 786 .size CySysFlashClockRestore, .-CySysFlashClockRestore + 787 .text + 788 .Letext0: + 789 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 790 .file 3 "Generated_Source\\PSoC4\\CyFlash.h" + 791 .section .debug_info,"",%progbits + 792 .Ldebug_info0: + 793 0000 85020000 .4byte 0x285 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 29 + + + 794 0004 0400 .2byte 0x4 + 795 0006 00000000 .4byte .Ldebug_abbrev0 + 796 000a 04 .byte 0x4 + 797 000b 01 .uleb128 0x1 + 798 000c 1A010000 .4byte .LASF35 + 799 0010 0C .byte 0xc + 800 0011 DE010000 .4byte .LASF36 + 801 0015 77000000 .4byte .LASF37 + 802 0019 00000000 .4byte .Ldebug_ranges0+0 + 803 001d 00000000 .4byte 0 + 804 0021 00000000 .4byte .Ldebug_line0 + 805 0025 02 .uleb128 0x2 + 806 0026 01 .byte 0x1 + 807 0027 06 .byte 0x6 + 808 0028 D5020000 .4byte .LASF0 + 809 002c 02 .uleb128 0x2 + 810 002d 01 .byte 0x1 + 811 002e 08 .byte 0x8 + 812 002f E1000000 .4byte .LASF1 + 813 0033 02 .uleb128 0x2 + 814 0034 02 .byte 0x2 + 815 0035 05 .byte 0x5 + 816 0036 AF010000 .4byte .LASF2 + 817 003a 02 .uleb128 0x2 + 818 003b 02 .byte 0x2 + 819 003c 07 .byte 0x7 + 820 003d 57000000 .4byte .LASF3 + 821 0041 02 .uleb128 0x2 + 822 0042 04 .byte 0x4 + 823 0043 05 .byte 0x5 + 824 0044 C0020000 .4byte .LASF4 + 825 0048 02 .uleb128 0x2 + 826 0049 04 .byte 0x4 + 827 004a 07 .byte 0x7 + 828 004b 02010000 .4byte .LASF5 + 829 004f 02 .uleb128 0x2 + 830 0050 08 .byte 0x8 + 831 0051 05 .byte 0x5 + 832 0052 45020000 .4byte .LASF6 + 833 0056 02 .uleb128 0x2 + 834 0057 08 .byte 0x8 + 835 0058 07 .byte 0x7 + 836 0059 FF010000 .4byte .LASF7 + 837 005d 03 .uleb128 0x3 + 838 005e 04 .byte 0x4 + 839 005f 05 .byte 0x5 + 840 0060 696E7400 .ascii "int\000" + 841 0064 02 .uleb128 0x2 + 842 0065 04 .byte 0x4 + 843 0066 07 .byte 0x7 + 844 0067 6A000000 .4byte .LASF8 + 845 006b 04 .uleb128 0x4 + 846 006c 14010000 .4byte .LASF9 + 847 0070 02 .byte 0x2 + 848 0071 E401 .2byte 0x1e4 + 849 0073 2C000000 .4byte 0x2c + 850 0077 04 .uleb128 0x4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 30 + + + 851 0078 D0010000 .4byte .LASF10 + 852 007c 02 .byte 0x2 + 853 007d E501 .2byte 0x1e5 + 854 007f 3A000000 .4byte 0x3a + 855 0083 04 .uleb128 0x4 + 856 0084 D7010000 .4byte .LASF11 + 857 0088 02 .byte 0x2 + 858 0089 E601 .2byte 0x1e6 + 859 008b 48000000 .4byte 0x48 + 860 008f 02 .uleb128 0x2 + 861 0090 04 .byte 0x4 + 862 0091 04 .byte 0x4 + 863 0092 D2000000 .4byte .LASF12 + 864 0096 02 .uleb128 0x2 + 865 0097 08 .byte 0x8 + 866 0098 04 .byte 0x4 + 867 0099 A8010000 .4byte .LASF13 + 868 009d 02 .uleb128 0x2 + 869 009e 01 .byte 0x1 + 870 009f 08 .byte 0x8 + 871 00a0 60020000 .4byte .LASF14 + 872 00a4 04 .uleb128 0x4 + 873 00a5 00000000 .4byte .LASF15 + 874 00a9 02 .byte 0x2 + 875 00aa 8602 .2byte 0x286 + 876 00ac 48000000 .4byte 0x48 + 877 00b0 04 .uleb128 0x4 + 878 00b1 09000000 .4byte .LASF16 + 879 00b5 02 .byte 0x2 + 880 00b6 9002 .2byte 0x290 + 881 00b8 BC000000 .4byte 0xbc + 882 00bc 05 .uleb128 0x5 + 883 00bd 83000000 .4byte 0x83 + 884 00c1 02 .uleb128 0x2 + 885 00c2 08 .byte 0x8 + 886 00c3 04 .byte 0x4 + 887 00c4 C9020000 .4byte .LASF17 + 888 00c8 02 .uleb128 0x2 + 889 00c9 04 .byte 0x4 + 890 00ca 07 .byte 0x7 + 891 00cb 3C020000 .4byte .LASF18 + 892 00cf 06 .uleb128 0x6 + 893 00d0 2A000000 .4byte .LASF38 + 894 00d4 04 .byte 0x4 + 895 00d5 03 .byte 0x3 + 896 00d6 D7 .byte 0xd7 + 897 00d7 E8000000 .4byte 0xe8 + 898 00db 07 .uleb128 0x7 + 899 00dc 53020000 .4byte .LASF39 + 900 00e0 03 .byte 0x3 + 901 00e1 DA .byte 0xda + 902 00e2 83000000 .4byte 0x83 + 903 00e6 00 .byte 0 + 904 00e7 00 .byte 0 + 905 00e8 08 .uleb128 0x8 + 906 00e9 9F020000 .4byte .LASF19 + 907 00ed 03 .byte 0x3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 31 + + + 908 00ee ED .byte 0xed + 909 00ef CF000000 .4byte 0xcf + 910 00f3 09 .uleb128 0x9 + 911 00f4 E1020000 .4byte .LASF40 + 912 00f8 01 .byte 0x1 + 913 00f9 51 .byte 0x51 + 914 00fa 83000000 .4byte 0x83 + 915 00fe 00000000 .4byte .LFB0 + 916 0102 8C030000 .4byte .LFE0-.LFB0 + 917 0106 01 .uleb128 0x1 + 918 0107 9C .byte 0x9c + 919 0108 CE010000 .4byte 0x1ce + 920 010c 0A .uleb128 0xa + 921 010d 23000000 .4byte .LASF20 + 922 0111 01 .byte 0x1 + 923 0112 51 .byte 0x51 + 924 0113 83000000 .4byte 0x83 + 925 0117 03 .uleb128 0x3 + 926 0118 91 .byte 0x91 + 927 0119 BC7E .sleb128 -196 + 928 011b 0A .uleb128 0xa + 929 011c EF000000 .4byte .LASF21 + 930 0120 01 .byte 0x1 + 931 0121 51 .byte 0x51 + 932 0122 CE010000 .4byte 0x1ce + 933 0126 03 .uleb128 0x3 + 934 0127 91 .byte 0x91 + 935 0128 B87E .sleb128 -200 + 936 012a 0B .uleb128 0xb + 937 012b 1A000000 .4byte .LASF22 + 938 012f 01 .byte 0x1 + 939 0130 53 .byte 0x53 + 940 0131 BC000000 .4byte 0xbc + 941 0135 02 .uleb128 0x2 + 942 0136 91 .byte 0x91 + 943 0137 4C .sleb128 -52 + 944 0138 0B .uleb128 0xb + 945 0139 6F020000 .4byte .LASF23 + 946 013d 01 .byte 0x1 + 947 013e 54 .byte 0x54 + 948 013f BC000000 .4byte 0xbc + 949 0143 02 .uleb128 0x2 + 950 0144 91 .byte 0x91 + 951 0145 48 .sleb128 -56 + 952 0146 0B .uleb128 0xb + 953 0147 F7000000 .4byte .LASF24 + 954 014b 01 .byte 0x1 + 955 014c 55 .byte 0x55 + 956 014d E9010000 .4byte 0x1e9 + 957 0151 03 .uleb128 0x3 + 958 0152 91 .byte 0x91 + 959 0153 C07E .sleb128 -192 + 960 0155 0B .uleb128 0xb + 961 0156 2D020000 .4byte .LASF25 + 962 015a 01 .byte 0x1 + 963 015b 56 .byte 0x56 + 964 015c 6B000000 .4byte 0x6b + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 32 + + + 965 0160 02 .uleb128 0x2 + 966 0161 91 .byte 0x91 + 967 0162 53 .sleb128 -45 + 968 0163 0B .uleb128 0xb + 969 0164 16020000 .4byte .LASF26 + 970 0168 01 .byte 0x1 + 971 0169 59 .byte 0x59 + 972 016a 83000000 .4byte 0x83 + 973 016e 02 .uleb128 0x2 + 974 016f 91 .byte 0x91 + 975 0170 58 .sleb128 -40 + 976 0171 0B .uleb128 0xb + 977 0172 0F000000 .4byte .LASF27 + 978 0176 01 .byte 0x1 + 979 0177 5A .byte 0x5a + 980 0178 83000000 .4byte 0x83 + 981 017c 02 .uleb128 0x2 + 982 017d 91 .byte 0x91 + 983 017e 6C .sleb128 -20 + 984 017f 0B .uleb128 0xb + 985 0180 7E020000 .4byte .LASF28 + 986 0184 01 .byte 0x1 + 987 0185 5B .byte 0x5b + 988 0186 83000000 .4byte 0x83 + 989 018a 02 .uleb128 0x2 + 990 018b 91 .byte 0x91 + 991 018c 68 .sleb128 -24 + 992 018d 0B .uleb128 0xb + 993 018e D8000000 .4byte .LASF29 + 994 0192 01 .byte 0x1 + 995 0193 5C .byte 0x5c + 996 0194 83000000 .4byte 0x83 + 997 0198 02 .uleb128 0x2 + 998 0199 91 .byte 0x91 + 999 019a 64 .sleb128 -28 + 1000 019b 0B .uleb128 0xb + 1001 019c 65020000 .4byte .LASF30 + 1002 01a0 01 .byte 0x1 + 1003 01a1 5D .byte 0x5d + 1004 01a2 83000000 .4byte 0x83 + 1005 01a6 02 .uleb128 0x2 + 1006 01a7 91 .byte 0x91 + 1007 01a8 60 .sleb128 -32 + 1008 01a9 0C .uleb128 0xc + 1009 01aa 6900 .ascii "i\000" + 1010 01ac 01 .byte 0x1 + 1011 01ad 5E .byte 0x5e + 1012 01ae 83000000 .4byte 0x83 + 1013 01b2 02 .uleb128 0x2 + 1014 01b3 91 .byte 0x91 + 1015 01b4 5C .sleb128 -36 + 1016 01b5 0D .uleb128 0xd + 1017 01b6 6C000000 .4byte .LBB2 + 1018 01ba 52000000 .4byte .LBE2-.LBB2 + 1019 01be 0C .uleb128 0xc + 1020 01bf 746D7000 .ascii "tmp\000" + 1021 01c3 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 33 + + + 1022 01c4 6A .byte 0x6a + 1023 01c5 83000000 .4byte 0x83 + 1024 01c9 02 .uleb128 0x2 + 1025 01ca 91 .byte 0x91 + 1026 01cb 54 .sleb128 -44 + 1027 01cc 00 .byte 0 + 1028 01cd 00 .byte 0 + 1029 01ce 0E .uleb128 0xe + 1030 01cf 04 .byte 0x4 + 1031 01d0 D4010000 .4byte 0x1d4 + 1032 01d4 0F .uleb128 0xf + 1033 01d5 6B000000 .4byte 0x6b + 1034 01d9 10 .uleb128 0x10 + 1035 01da BC000000 .4byte 0xbc + 1036 01de E9010000 .4byte 0x1e9 + 1037 01e2 11 .uleb128 0x11 + 1038 01e3 C8000000 .4byte 0xc8 + 1039 01e7 21 .byte 0x21 + 1040 01e8 00 .byte 0 + 1041 01e9 05 .uleb128 0x5 + 1042 01ea D9010000 .4byte 0x1d9 + 1043 01ee 12 .uleb128 0x12 + 1044 01ef F4020000 .4byte .LASF41 + 1045 01f3 01 .byte 0x1 + 1046 01f4 A601 .2byte 0x1a6 + 1047 01f6 00000000 .4byte .LFB1 + 1048 01fa 54000000 .4byte .LFE1-.LFB1 + 1049 01fe 01 .uleb128 0x1 + 1050 01ff 9C .byte 0x9c + 1051 0200 23020000 .4byte 0x223 + 1052 0204 13 .uleb128 0x13 + 1053 0205 6A020000 .4byte .LASF31 + 1054 0209 01 .byte 0x1 + 1055 020a A601 .2byte 0x1a6 + 1056 020c 83000000 .4byte 0x83 + 1057 0210 02 .uleb128 0x2 + 1058 0211 91 .byte 0x91 + 1059 0212 64 .sleb128 -28 + 1060 0213 14 .uleb128 0x14 + 1061 0214 2D020000 .4byte .LASF25 + 1062 0218 01 .byte 0x1 + 1063 0219 A801 .2byte 0x1a8 + 1064 021b 6B000000 .4byte 0x6b + 1065 021f 02 .uleb128 0x2 + 1066 0220 91 .byte 0x91 + 1067 0221 6F .sleb128 -17 + 1068 0222 00 .byte 0 + 1069 0223 15 .uleb128 0x15 + 1070 0224 89020000 .4byte .LASF32 + 1071 0228 01 .byte 0x1 + 1072 0229 3A02 .2byte 0x23a + 1073 022b A4000000 .4byte 0xa4 + 1074 022f 00000000 .4byte .LFB2 + 1075 0233 24000000 .4byte .LFE2-.LFB2 + 1076 0237 01 .uleb128 0x1 + 1077 0238 9C .byte 0x9c + 1078 0239 4D020000 .4byte 0x24d + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 34 + + + 1079 023d 14 .uleb128 0x14 + 1080 023e 1A000000 .4byte .LASF22 + 1081 0242 01 .byte 0x1 + 1082 0243 3C02 .2byte 0x23c + 1083 0245 A4000000 .4byte 0xa4 + 1084 0249 02 .uleb128 0x2 + 1085 024a 91 .byte 0x91 + 1086 024b 74 .sleb128 -12 + 1087 024c 00 .byte 0 + 1088 024d 15 .uleb128 0x15 + 1089 024e B9010000 .4byte .LASF33 + 1090 0252 01 .byte 0x1 + 1091 0253 D802 .2byte 0x2d8 + 1092 0255 A4000000 .4byte 0xa4 + 1093 0259 00000000 .4byte .LFB3 + 1094 025d 24000000 .4byte .LFE3-.LFB3 + 1095 0261 01 .uleb128 0x1 + 1096 0262 9C .byte 0x9c + 1097 0263 77020000 .4byte 0x277 + 1098 0267 14 .uleb128 0x14 + 1099 0268 1A000000 .4byte .LASF22 + 1100 026c 01 .byte 0x1 + 1101 026d DA02 .2byte 0x2da + 1102 026f A4000000 .4byte 0xa4 + 1103 0273 02 .uleb128 0x2 + 1104 0274 91 .byte 0x91 + 1105 0275 74 .sleb128 -12 + 1106 0276 00 .byte 0 + 1107 0277 0B .uleb128 0xb + 1108 0278 46000000 .4byte .LASF34 + 1109 027c 01 .byte 0x1 + 1110 027d 22 .byte 0x22 + 1111 027e E8000000 .4byte 0xe8 + 1112 0282 05 .uleb128 0x5 + 1113 0283 03 .byte 0x3 + 1114 0284 00000000 .4byte cySysFlashBackup + 1115 0288 00 .byte 0 + 1116 .section .debug_abbrev,"",%progbits + 1117 .Ldebug_abbrev0: + 1118 0000 01 .uleb128 0x1 + 1119 0001 11 .uleb128 0x11 + 1120 0002 01 .byte 0x1 + 1121 0003 25 .uleb128 0x25 + 1122 0004 0E .uleb128 0xe + 1123 0005 13 .uleb128 0x13 + 1124 0006 0B .uleb128 0xb + 1125 0007 03 .uleb128 0x3 + 1126 0008 0E .uleb128 0xe + 1127 0009 1B .uleb128 0x1b + 1128 000a 0E .uleb128 0xe + 1129 000b 55 .uleb128 0x55 + 1130 000c 17 .uleb128 0x17 + 1131 000d 11 .uleb128 0x11 + 1132 000e 01 .uleb128 0x1 + 1133 000f 10 .uleb128 0x10 + 1134 0010 17 .uleb128 0x17 + 1135 0011 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 35 + + + 1136 0012 00 .byte 0 + 1137 0013 02 .uleb128 0x2 + 1138 0014 24 .uleb128 0x24 + 1139 0015 00 .byte 0 + 1140 0016 0B .uleb128 0xb + 1141 0017 0B .uleb128 0xb + 1142 0018 3E .uleb128 0x3e + 1143 0019 0B .uleb128 0xb + 1144 001a 03 .uleb128 0x3 + 1145 001b 0E .uleb128 0xe + 1146 001c 00 .byte 0 + 1147 001d 00 .byte 0 + 1148 001e 03 .uleb128 0x3 + 1149 001f 24 .uleb128 0x24 + 1150 0020 00 .byte 0 + 1151 0021 0B .uleb128 0xb + 1152 0022 0B .uleb128 0xb + 1153 0023 3E .uleb128 0x3e + 1154 0024 0B .uleb128 0xb + 1155 0025 03 .uleb128 0x3 + 1156 0026 08 .uleb128 0x8 + 1157 0027 00 .byte 0 + 1158 0028 00 .byte 0 + 1159 0029 04 .uleb128 0x4 + 1160 002a 16 .uleb128 0x16 + 1161 002b 00 .byte 0 + 1162 002c 03 .uleb128 0x3 + 1163 002d 0E .uleb128 0xe + 1164 002e 3A .uleb128 0x3a + 1165 002f 0B .uleb128 0xb + 1166 0030 3B .uleb128 0x3b + 1167 0031 05 .uleb128 0x5 + 1168 0032 49 .uleb128 0x49 + 1169 0033 13 .uleb128 0x13 + 1170 0034 00 .byte 0 + 1171 0035 00 .byte 0 + 1172 0036 05 .uleb128 0x5 + 1173 0037 35 .uleb128 0x35 + 1174 0038 00 .byte 0 + 1175 0039 49 .uleb128 0x49 + 1176 003a 13 .uleb128 0x13 + 1177 003b 00 .byte 0 + 1178 003c 00 .byte 0 + 1179 003d 06 .uleb128 0x6 + 1180 003e 13 .uleb128 0x13 + 1181 003f 01 .byte 0x1 + 1182 0040 03 .uleb128 0x3 + 1183 0041 0E .uleb128 0xe + 1184 0042 0B .uleb128 0xb + 1185 0043 0B .uleb128 0xb + 1186 0044 3A .uleb128 0x3a + 1187 0045 0B .uleb128 0xb + 1188 0046 3B .uleb128 0x3b + 1189 0047 0B .uleb128 0xb + 1190 0048 01 .uleb128 0x1 + 1191 0049 13 .uleb128 0x13 + 1192 004a 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 36 + + + 1193 004b 00 .byte 0 + 1194 004c 07 .uleb128 0x7 + 1195 004d 0D .uleb128 0xd + 1196 004e 00 .byte 0 + 1197 004f 03 .uleb128 0x3 + 1198 0050 0E .uleb128 0xe + 1199 0051 3A .uleb128 0x3a + 1200 0052 0B .uleb128 0xb + 1201 0053 3B .uleb128 0x3b + 1202 0054 0B .uleb128 0xb + 1203 0055 49 .uleb128 0x49 + 1204 0056 13 .uleb128 0x13 + 1205 0057 38 .uleb128 0x38 + 1206 0058 0B .uleb128 0xb + 1207 0059 00 .byte 0 + 1208 005a 00 .byte 0 + 1209 005b 08 .uleb128 0x8 + 1210 005c 16 .uleb128 0x16 + 1211 005d 00 .byte 0 + 1212 005e 03 .uleb128 0x3 + 1213 005f 0E .uleb128 0xe + 1214 0060 3A .uleb128 0x3a + 1215 0061 0B .uleb128 0xb + 1216 0062 3B .uleb128 0x3b + 1217 0063 0B .uleb128 0xb + 1218 0064 49 .uleb128 0x49 + 1219 0065 13 .uleb128 0x13 + 1220 0066 00 .byte 0 + 1221 0067 00 .byte 0 + 1222 0068 09 .uleb128 0x9 + 1223 0069 2E .uleb128 0x2e + 1224 006a 01 .byte 0x1 + 1225 006b 3F .uleb128 0x3f + 1226 006c 19 .uleb128 0x19 + 1227 006d 03 .uleb128 0x3 + 1228 006e 0E .uleb128 0xe + 1229 006f 3A .uleb128 0x3a + 1230 0070 0B .uleb128 0xb + 1231 0071 3B .uleb128 0x3b + 1232 0072 0B .uleb128 0xb + 1233 0073 27 .uleb128 0x27 + 1234 0074 19 .uleb128 0x19 + 1235 0075 49 .uleb128 0x49 + 1236 0076 13 .uleb128 0x13 + 1237 0077 11 .uleb128 0x11 + 1238 0078 01 .uleb128 0x1 + 1239 0079 12 .uleb128 0x12 + 1240 007a 06 .uleb128 0x6 + 1241 007b 40 .uleb128 0x40 + 1242 007c 18 .uleb128 0x18 + 1243 007d 9642 .uleb128 0x2116 + 1244 007f 19 .uleb128 0x19 + 1245 0080 01 .uleb128 0x1 + 1246 0081 13 .uleb128 0x13 + 1247 0082 00 .byte 0 + 1248 0083 00 .byte 0 + 1249 0084 0A .uleb128 0xa + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 37 + + + 1250 0085 05 .uleb128 0x5 + 1251 0086 00 .byte 0 + 1252 0087 03 .uleb128 0x3 + 1253 0088 0E .uleb128 0xe + 1254 0089 3A .uleb128 0x3a + 1255 008a 0B .uleb128 0xb + 1256 008b 3B .uleb128 0x3b + 1257 008c 0B .uleb128 0xb + 1258 008d 49 .uleb128 0x49 + 1259 008e 13 .uleb128 0x13 + 1260 008f 02 .uleb128 0x2 + 1261 0090 18 .uleb128 0x18 + 1262 0091 00 .byte 0 + 1263 0092 00 .byte 0 + 1264 0093 0B .uleb128 0xb + 1265 0094 34 .uleb128 0x34 + 1266 0095 00 .byte 0 + 1267 0096 03 .uleb128 0x3 + 1268 0097 0E .uleb128 0xe + 1269 0098 3A .uleb128 0x3a + 1270 0099 0B .uleb128 0xb + 1271 009a 3B .uleb128 0x3b + 1272 009b 0B .uleb128 0xb + 1273 009c 49 .uleb128 0x49 + 1274 009d 13 .uleb128 0x13 + 1275 009e 02 .uleb128 0x2 + 1276 009f 18 .uleb128 0x18 + 1277 00a0 00 .byte 0 + 1278 00a1 00 .byte 0 + 1279 00a2 0C .uleb128 0xc + 1280 00a3 34 .uleb128 0x34 + 1281 00a4 00 .byte 0 + 1282 00a5 03 .uleb128 0x3 + 1283 00a6 08 .uleb128 0x8 + 1284 00a7 3A .uleb128 0x3a + 1285 00a8 0B .uleb128 0xb + 1286 00a9 3B .uleb128 0x3b + 1287 00aa 0B .uleb128 0xb + 1288 00ab 49 .uleb128 0x49 + 1289 00ac 13 .uleb128 0x13 + 1290 00ad 02 .uleb128 0x2 + 1291 00ae 18 .uleb128 0x18 + 1292 00af 00 .byte 0 + 1293 00b0 00 .byte 0 + 1294 00b1 0D .uleb128 0xd + 1295 00b2 0B .uleb128 0xb + 1296 00b3 01 .byte 0x1 + 1297 00b4 11 .uleb128 0x11 + 1298 00b5 01 .uleb128 0x1 + 1299 00b6 12 .uleb128 0x12 + 1300 00b7 06 .uleb128 0x6 + 1301 00b8 00 .byte 0 + 1302 00b9 00 .byte 0 + 1303 00ba 0E .uleb128 0xe + 1304 00bb 0F .uleb128 0xf + 1305 00bc 00 .byte 0 + 1306 00bd 0B .uleb128 0xb + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 38 + + + 1307 00be 0B .uleb128 0xb + 1308 00bf 49 .uleb128 0x49 + 1309 00c0 13 .uleb128 0x13 + 1310 00c1 00 .byte 0 + 1311 00c2 00 .byte 0 + 1312 00c3 0F .uleb128 0xf + 1313 00c4 26 .uleb128 0x26 + 1314 00c5 00 .byte 0 + 1315 00c6 49 .uleb128 0x49 + 1316 00c7 13 .uleb128 0x13 + 1317 00c8 00 .byte 0 + 1318 00c9 00 .byte 0 + 1319 00ca 10 .uleb128 0x10 + 1320 00cb 01 .uleb128 0x1 + 1321 00cc 01 .byte 0x1 + 1322 00cd 49 .uleb128 0x49 + 1323 00ce 13 .uleb128 0x13 + 1324 00cf 01 .uleb128 0x1 + 1325 00d0 13 .uleb128 0x13 + 1326 00d1 00 .byte 0 + 1327 00d2 00 .byte 0 + 1328 00d3 11 .uleb128 0x11 + 1329 00d4 21 .uleb128 0x21 + 1330 00d5 00 .byte 0 + 1331 00d6 49 .uleb128 0x49 + 1332 00d7 13 .uleb128 0x13 + 1333 00d8 2F .uleb128 0x2f + 1334 00d9 0B .uleb128 0xb + 1335 00da 00 .byte 0 + 1336 00db 00 .byte 0 + 1337 00dc 12 .uleb128 0x12 + 1338 00dd 2E .uleb128 0x2e + 1339 00de 01 .byte 0x1 + 1340 00df 3F .uleb128 0x3f + 1341 00e0 19 .uleb128 0x19 + 1342 00e1 03 .uleb128 0x3 + 1343 00e2 0E .uleb128 0xe + 1344 00e3 3A .uleb128 0x3a + 1345 00e4 0B .uleb128 0xb + 1346 00e5 3B .uleb128 0x3b + 1347 00e6 05 .uleb128 0x5 + 1348 00e7 27 .uleb128 0x27 + 1349 00e8 19 .uleb128 0x19 + 1350 00e9 11 .uleb128 0x11 + 1351 00ea 01 .uleb128 0x1 + 1352 00eb 12 .uleb128 0x12 + 1353 00ec 06 .uleb128 0x6 + 1354 00ed 40 .uleb128 0x40 + 1355 00ee 18 .uleb128 0x18 + 1356 00ef 9642 .uleb128 0x2116 + 1357 00f1 19 .uleb128 0x19 + 1358 00f2 01 .uleb128 0x1 + 1359 00f3 13 .uleb128 0x13 + 1360 00f4 00 .byte 0 + 1361 00f5 00 .byte 0 + 1362 00f6 13 .uleb128 0x13 + 1363 00f7 05 .uleb128 0x5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 39 + + + 1364 00f8 00 .byte 0 + 1365 00f9 03 .uleb128 0x3 + 1366 00fa 0E .uleb128 0xe + 1367 00fb 3A .uleb128 0x3a + 1368 00fc 0B .uleb128 0xb + 1369 00fd 3B .uleb128 0x3b + 1370 00fe 05 .uleb128 0x5 + 1371 00ff 49 .uleb128 0x49 + 1372 0100 13 .uleb128 0x13 + 1373 0101 02 .uleb128 0x2 + 1374 0102 18 .uleb128 0x18 + 1375 0103 00 .byte 0 + 1376 0104 00 .byte 0 + 1377 0105 14 .uleb128 0x14 + 1378 0106 34 .uleb128 0x34 + 1379 0107 00 .byte 0 + 1380 0108 03 .uleb128 0x3 + 1381 0109 0E .uleb128 0xe + 1382 010a 3A .uleb128 0x3a + 1383 010b 0B .uleb128 0xb + 1384 010c 3B .uleb128 0x3b + 1385 010d 05 .uleb128 0x5 + 1386 010e 49 .uleb128 0x49 + 1387 010f 13 .uleb128 0x13 + 1388 0110 02 .uleb128 0x2 + 1389 0111 18 .uleb128 0x18 + 1390 0112 00 .byte 0 + 1391 0113 00 .byte 0 + 1392 0114 15 .uleb128 0x15 + 1393 0115 2E .uleb128 0x2e + 1394 0116 01 .byte 0x1 + 1395 0117 03 .uleb128 0x3 + 1396 0118 0E .uleb128 0xe + 1397 0119 3A .uleb128 0x3a + 1398 011a 0B .uleb128 0xb + 1399 011b 3B .uleb128 0x3b + 1400 011c 05 .uleb128 0x5 + 1401 011d 27 .uleb128 0x27 + 1402 011e 19 .uleb128 0x19 + 1403 011f 49 .uleb128 0x49 + 1404 0120 13 .uleb128 0x13 + 1405 0121 11 .uleb128 0x11 + 1406 0122 01 .uleb128 0x1 + 1407 0123 12 .uleb128 0x12 + 1408 0124 06 .uleb128 0x6 + 1409 0125 40 .uleb128 0x40 + 1410 0126 18 .uleb128 0x18 + 1411 0127 9742 .uleb128 0x2117 + 1412 0129 19 .uleb128 0x19 + 1413 012a 01 .uleb128 0x1 + 1414 012b 13 .uleb128 0x13 + 1415 012c 00 .byte 0 + 1416 012d 00 .byte 0 + 1417 012e 00 .byte 0 + 1418 .section .debug_aranges,"",%progbits + 1419 0000 34000000 .4byte 0x34 + 1420 0004 0200 .2byte 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 40 + + + 1421 0006 00000000 .4byte .Ldebug_info0 + 1422 000a 04 .byte 0x4 + 1423 000b 00 .byte 0 + 1424 000c 0000 .2byte 0 + 1425 000e 0000 .2byte 0 + 1426 0010 00000000 .4byte .LFB0 + 1427 0014 8C030000 .4byte .LFE0-.LFB0 + 1428 0018 00000000 .4byte .LFB1 + 1429 001c 54000000 .4byte .LFE1-.LFB1 + 1430 0020 00000000 .4byte .LFB2 + 1431 0024 24000000 .4byte .LFE2-.LFB2 + 1432 0028 00000000 .4byte .LFB3 + 1433 002c 24000000 .4byte .LFE3-.LFB3 + 1434 0030 00000000 .4byte 0 + 1435 0034 00000000 .4byte 0 + 1436 .section .debug_ranges,"",%progbits + 1437 .Ldebug_ranges0: + 1438 0000 00000000 .4byte .LFB0 + 1439 0004 8C030000 .4byte .LFE0 + 1440 0008 00000000 .4byte .LFB1 + 1441 000c 54000000 .4byte .LFE1 + 1442 0010 00000000 .4byte .LFB2 + 1443 0014 24000000 .4byte .LFE2 + 1444 0018 00000000 .4byte .LFB3 + 1445 001c 24000000 .4byte .LFE3 + 1446 0020 00000000 .4byte 0 + 1447 0024 00000000 .4byte 0 + 1448 .section .debug_line,"",%progbits + 1449 .Ldebug_line0: + 1450 0000 9F010000 .section .debug_str,"MS",%progbits,1 + 1450 02005100 + 1450 00000201 + 1450 FB0E0D00 + 1450 01010101 + 1451 .LASF15: + 1452 0000 63797374 .ascii "cystatus\000" + 1452 61747573 + 1452 00 + 1453 .LASF16: + 1454 0009 72656733 .ascii "reg32\000" + 1454 3200 + 1455 .LASF27: + 1456 000f 73617665 .ascii "savedIndex\000" + 1456 64496E64 + 1456 657800 + 1457 .LASF22: + 1458 001a 72657456 .ascii "retValue\000" + 1458 616C7565 + 1458 00 + 1459 .LASF20: + 1460 0023 726F774E .ascii "rowNum\000" + 1460 756D00 + 1461 .LASF38: + 1462 002a 63795379 .ascii "cySysFlashClockBackupStruct\000" + 1462 73466C61 + 1462 7368436C + 1462 6F636B42 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 41 + + + 1462 61636B75 + 1463 .LASF34: + 1464 0046 63795379 .ascii "cySysFlashBackup\000" + 1464 73466C61 + 1464 73684261 + 1464 636B7570 + 1464 00 + 1465 .LASF3: + 1466 0057 73686F72 .ascii "short unsigned int\000" + 1466 7420756E + 1466 7369676E + 1466 65642069 + 1466 6E7400 + 1467 .LASF8: + 1468 006a 756E7369 .ascii "unsigned int\000" + 1468 676E6564 + 1468 20696E74 + 1468 00 + 1469 .LASF37: + 1470 0077 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 1470 73657273 + 1470 5C6A6167 + 1470 756D6965 + 1470 6C5C446F + 1471 00a5 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 1471 50536F43 + 1471 2D313031 + 1471 5C547261 + 1471 696E696E + 1472 .LASF12: + 1473 00d2 666C6F61 .ascii "float\000" + 1473 7400 + 1474 .LASF29: + 1475 00d8 63686563 .ascii "checksum\000" + 1475 6B73756D + 1475 00 + 1476 .LASF1: + 1477 00e1 756E7369 .ascii "unsigned char\000" + 1477 676E6564 + 1477 20636861 + 1477 7200 + 1478 .LASF21: + 1479 00ef 726F7744 .ascii "rowData\000" + 1479 61746100 + 1480 .LASF24: + 1481 00f7 70617261 .ascii "parameters\000" + 1481 6D657465 + 1481 727300 + 1482 .LASF5: + 1483 0102 6C6F6E67 .ascii "long unsigned int\000" + 1483 20756E73 + 1483 69676E65 + 1483 6420696E + 1483 7400 + 1484 .LASF9: + 1485 0114 75696E74 .ascii "uint8\000" + 1485 3800 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 42 + + + 1486 .LASF35: + 1487 011a 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 1487 43313120 + 1487 352E342E + 1487 31203230 + 1487 31363036 + 1488 014d 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 1488 20726576 + 1488 6973696F + 1488 6E203233 + 1488 37373135 + 1489 0180 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 1489 66756E63 + 1489 74696F6E + 1489 2D736563 + 1489 74696F6E + 1490 .LASF13: + 1491 01a8 646F7562 .ascii "double\000" + 1491 6C6500 + 1492 .LASF2: + 1493 01af 73686F72 .ascii "short int\000" + 1493 7420696E + 1493 7400 + 1494 .LASF33: + 1495 01b9 43795379 .ascii "CySysFlashClockRestore\000" + 1495 73466C61 + 1495 7368436C + 1495 6F636B52 + 1495 6573746F + 1496 .LASF10: + 1497 01d0 75696E74 .ascii "uint16\000" + 1497 313600 + 1498 .LASF11: + 1499 01d7 75696E74 .ascii "uint32\000" + 1499 333200 + 1500 .LASF36: + 1501 01de 47656E65 .ascii "Generated_Source\\PSoC4\\CyFlash.c\000" + 1501 72617465 + 1501 645F536F + 1501 75726365 + 1501 5C50536F + 1502 .LASF7: + 1503 01ff 6C6F6E67 .ascii "long long unsigned int\000" + 1503 206C6F6E + 1503 6720756E + 1503 7369676E + 1503 65642069 + 1504 .LASF26: + 1505 0216 6E656564 .ascii "needChecksumWorkaround\000" + 1505 43686563 + 1505 6B73756D + 1505 576F726B + 1505 61726F75 + 1506 .LASF25: + 1507 022d 696E7465 .ascii "interruptState\000" + 1507 72727570 + 1507 74537461 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 43 + + + 1507 746500 + 1508 .LASF18: + 1509 023c 73697A65 .ascii "sizetype\000" + 1509 74797065 + 1509 00 + 1510 .LASF6: + 1511 0245 6C6F6E67 .ascii "long long int\000" + 1511 206C6F6E + 1511 6720696E + 1511 7400 + 1512 .LASF39: + 1513 0253 696D6F43 .ascii "imoConfigReg\000" + 1513 6F6E6669 + 1513 67526567 + 1513 00 + 1514 .LASF14: + 1515 0260 63686172 .ascii "char\000" + 1515 00 + 1516 .LASF30: + 1517 0265 62697473 .ascii "bits\000" + 1517 00 + 1518 .LASF31: + 1519 026a 66726571 .ascii "freq\000" + 1519 00 + 1520 .LASF23: + 1521 026f 636C6B43 .ascii "clkCnfRetValue\000" + 1521 6E665265 + 1521 7456616C + 1521 756500 + 1522 .LASF28: + 1523 027e 73617665 .ascii "savedValue\000" + 1523 6456616C + 1523 756500 + 1524 .LASF32: + 1525 0289 43795379 .ascii "CySysFlashClockBackup\000" + 1525 73466C61 + 1525 7368436C + 1525 6F636B42 + 1525 61636B75 + 1526 .LASF19: + 1527 029f 43595F53 .ascii "CY_SYS_FLASH_CLOCK_BACKUP_STRUCT\000" + 1527 59535F46 + 1527 4C415348 + 1527 5F434C4F + 1527 434B5F42 + 1528 .LASF4: + 1529 02c0 6C6F6E67 .ascii "long int\000" + 1529 20696E74 + 1529 00 + 1530 .LASF17: + 1531 02c9 6C6F6E67 .ascii "long double\000" + 1531 20646F75 + 1531 626C6500 + 1532 .LASF0: + 1533 02d5 7369676E .ascii "signed char\000" + 1533 65642063 + 1533 68617200 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccV9dQ0b.s page 44 + + + 1534 .LASF40: + 1535 02e1 43795379 .ascii "CySysFlashWriteRow\000" + 1535 73466C61 + 1535 73685772 + 1535 69746552 + 1535 6F7700 + 1536 .LASF41: + 1537 02f4 43795379 .ascii "CySysFlashSetWaitCycles\000" + 1537 73466C61 + 1537 73685365 + 1537 74576169 + 1537 74437963 + 1538 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyFlash.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyFlash.o new file mode 100644 index 0000000000000000000000000000000000000000..3ec0bd5626454d2ba1d5e8d3bf070db4e4433dea GIT binary patch literal 6636 zcmbtYYiu0V6}~gGyWV*Hh`kQ+Bb0U4O+tg$c3vcb1Us8JIBO@tYZKxaysxom?e&g3 zGfV7-1_J@qSLz_t(vm8vN>P3w;i^qU5s~tvKY&WqhE^n~tsJRT@S}pNsQjS9{m#st z-SOHKq#kMKJFk1rx%b?;bL~eDbax7Zz-$uOCRUIbORX_2?rkP)Vz;t-HgoyqS@!Z| zY*&m0pI!fItsgkU@gm3HaGd4%630s>o>CS!vl~y|yh~x5+5BTScPZZBXSLp~)9Y*5 z;-{Z4ioq95zm^5k6JM=7!`^w|ys148T?0ne&AkM!Ua{nNYONfX96Ep4%J+gf!m7#Q zg{@WwOKRNw<_(HPQ9bh%fjD7K2(kqhwB~e?Ypdp{CW>X%WX;g2V~z7iNuD`WA0vEp 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zL%y33@dvpaBgD8zxI9fr^@a4QaU-4p8k&WQ&EXk?AyS44FGl`r zyOMF~TeFgfX3t#SKGCCvpZ|Aig3szz^**_X-W!Mh^#JE1A@YC;8#1 zFsay&Y(yLJqy6LbqkUzQ&9_2PoY($)k9=*vJHX?}V(s`5DL8a!EY(du^rL(|_&MWU zLjirz*<{D-g2EZ^ImDy=P4Vb`vE!-Wo$+d5XoAirJKh)+&Ulv)kLsa#gm%0if_KK- z`33R52R~=LSw}qj65H`+c|3qggD}wlHEg0>L@(jzjQ0xS&B93a;nmB>dkwrj1}u9Y zi_zjx*z8+Hel?gRz0Wq;es4nI%&XwDzX>|Zi&s3K_a=CI3|Q8Uc;si3ZTkxp&UiD3 z*A5-U!<6#z{srD11C|+x_X~%@W8E+2p0?<)Bu=#j&S)?(v=ZMy#31#-?hDfye~J9?bJq8IS7wCa5-(W z1t8@mqBU}q&029NZ?lcC*({-B8?hMT9fe{Y^mMPJy!5_MZO(YJP+o@4COh7L0dv7` A6#xJL literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyLFClk.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyLFClk.lst new file mode 100644 index 0000000..a624cdf --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/CyLFClk.lst @@ -0,0 +1,8505 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "CyLFClk.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .bss + 20 .align 2 + 21 lfclkPosedgeWdtCounter0Enabled: + 22 0000 00000000 .space 4 + 23 .align 2 + 24 lfclkPosedgeWdtCounter0Mode: + 25 0004 00000000 .space 4 + 26 .align 2 + 27 disableServicedIsr: + 28 0008 00000000 .space 4 + 29 .data + 30 .align 2 + 31 .type wdtIsrMask, %object + 32 .size wdtIsrMask, 4 + 33 wdtIsrMask: + 34 0000 04040400 .word 263172 + 35 .section .rodata + 36 .align 2 + 37 .type counterIntMaskTbl, %object + 38 .size counterIntMaskTbl, 12 + 39 counterIntMaskTbl: + 40 0000 04000000 .word 4 + 41 0004 00040000 .word 1024 + 42 0008 00000400 .word 262144 + 43 .bss + 44 .align 2 + 45 cySysWdtCallback: + 46 000c 00000000 .space 12 + 46 00000000 + 46 00000000 + 47 .section .text.CySysClkIloStart,"ax",%progbits + 48 .align 2 + 49 .global CySysClkIloStart + 50 .code 16 + 51 .thumb_func + 52 .type CySysClkIloStart, %function + 53 CySysClkIloStart: + 54 .LFB0: + 55 .file 1 "Generated_Source\\PSoC4\\CyLFClk.c" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 2 + + + 1:Generated_Source\PSoC4/CyLFClk.c **** /***************************************************************************//** + 2:Generated_Source\PSoC4/CyLFClk.c **** * \file .c + 3:Generated_Source\PSoC4/CyLFClk.c **** * \version 1.20 + 4:Generated_Source\PSoC4/CyLFClk.c **** * + 5:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 6:Generated_Source\PSoC4/CyLFClk.c **** * This file provides the source code for configuring watchdog timers WDTs, + 7:Generated_Source\PSoC4/CyLFClk.c **** * low frequency clocks (LFCLK) and the Real-time Clock (RTC) component in + 8:Generated_Source\PSoC4/CyLFClk.c **** * PSoC Creator for the PSoC 4 families. + 9:Generated_Source\PSoC4/CyLFClk.c **** * + 10:Generated_Source\PSoC4/CyLFClk.c **** ******************************************************************************** + 11:Generated_Source\PSoC4/CyLFClk.c **** * \copyright + 12:Generated_Source\PSoC4/CyLFClk.c **** * Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. + 13:Generated_Source\PSoC4/CyLFClk.c **** * You may use this file only in accordance with the license, terms, conditions, + 14:Generated_Source\PSoC4/CyLFClk.c **** * disclaimers, and limitations in the end user license agreement accompanying + 15:Generated_Source\PSoC4/CyLFClk.c **** * the software package with which this file was provided. + 16:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 17:Generated_Source\PSoC4/CyLFClk.c **** + 18:Generated_Source\PSoC4/CyLFClk.c **** + 19:Generated_Source\PSoC4/CyLFClk.c **** #include "CyLFClk.h" + 20:Generated_Source\PSoC4/CyLFClk.c **** #include "CyLib.h" + 21:Generated_Source\PSoC4/CyLFClk.c **** + 22:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_WCO && CY_IP_SRSSV2) + 23:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysClkGetLfclkSource(void); + 24:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + 25:Generated_Source\PSoC4/CyLFClk.c **** + 26:Generated_Source\PSoC4/CyLFClk.c **** + 27:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + 28:Generated_Source\PSoC4/CyLFClk.c **** /* Default Ilo Trim Register value for ILO trimming*/ + 29:Generated_Source\PSoC4/CyLFClk.c **** static volatile uint16 defaultIloTrimRegValue = CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE; + 30:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + 31:Generated_Source\PSoC4/CyLFClk.c **** + 32:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) + 33:Generated_Source\PSoC4/CyLFClk.c **** /* CySysClkLfclkPosedgeCatch() / CySysClkLfclkPosedgeRestore() */ + 34:Generated_Source\PSoC4/CyLFClk.c **** static uint32 lfclkPosedgeWdtCounter0Enabled = 0u; + 35:Generated_Source\PSoC4/CyLFClk.c **** static uint32 lfclkPosedgeWdtCounter0Mode = CY_SYS_WDT_MODE_NONE; + 36:Generated_Source\PSoC4/CyLFClk.c **** + 37:Generated_Source\PSoC4/CyLFClk.c **** static volatile uint32 disableServicedIsr = 0uL; + 38:Generated_Source\PSoC4/CyLFClk.c **** static volatile uint32 wdtIsrMask = CY_SYS_WDT_COUNTER0_INT |\ + 39:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER1_INT |\ + 40:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER2_INT; + 41:Generated_Source\PSoC4/CyLFClk.c **** + 42:Generated_Source\PSoC4/CyLFClk.c **** static const uint32 counterIntMaskTbl[CY_WDT_NUM_OF_WDT] = {CY_SYS_WDT_COUNTER0_INT, + 43:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER1_INT, + 44:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER2_INT}; + 45:Generated_Source\PSoC4/CyLFClk.c **** + 46:Generated_Source\PSoC4/CyLFClk.c **** static void CySysClkLfclkPosedgeCatch(void); + 47:Generated_Source\PSoC4/CyLFClk.c **** static void CySysClkLfclkPosedgeRestore(void); + 48:Generated_Source\PSoC4/CyLFClk.c **** + 49:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysWdtLocked(void); + 50:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysClkIloEnabled(void); + 51:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ + 52:Generated_Source\PSoC4/CyLFClk.c **** + 53:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + 54:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysClkGetTimerSource(void); + 55:Generated_Source\PSoC4/CyLFClk.c **** static volatile uint32 disableTimerServicedIsr = 0uL; + 56:Generated_Source\PSoC4/CyLFClk.c **** static volatile uint32 timerIsrMask = CY_SYS_TIMER0_INT |\ + 57:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER1_INT |\ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 3 + + + 58:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER2_INT; + 59:Generated_Source\PSoC4/CyLFClk.c **** + 60:Generated_Source\PSoC4/CyLFClk.c **** static const uint32 counterTimerIntMaskTbl[CY_SYS_NUM_OF_TIMERS] = {CY_SYS_TIMER0_INT, + 61:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER1_INT, + 62:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER2_INT}; + 63:Generated_Source\PSoC4/CyLFClk.c **** + 64:Generated_Source\PSoC4/CyLFClk.c **** static cyTimerCallback cySysTimerCallback[CY_SYS_NUM_OF_TIMERS] = {(void *)0, (void *)0, (void + 65:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_DWT_EN) */ + 66:Generated_Source\PSoC4/CyLFClk.c **** + 67:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) + 68:Generated_Source\PSoC4/CyLFClk.c **** static cyWdtCallback cySysWdtCallback[CY_WDT_NUM_OF_WDT] = {(void *)0, (void *)0, (void *)0}; + 69:Generated_Source\PSoC4/CyLFClk.c **** #else + 70:Generated_Source\PSoC4/CyLFClk.c **** static cyWdtCallback cySysWdtCallback = (void *)0; + 71:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ + 72:Generated_Source\PSoC4/CyLFClk.c **** + 73:Generated_Source\PSoC4/CyLFClk.c **** + 74:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 75:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloStart + 76:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 77:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 78:Generated_Source\PSoC4/CyLFClk.c **** * Enables ILO. + 79:Generated_Source\PSoC4/CyLFClk.c **** * + 80:Generated_Source\PSoC4/CyLFClk.c **** * Refer to the device datasheet for the ILO startup time. + 81:Generated_Source\PSoC4/CyLFClk.c **** * + 82:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 83:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkIloStart(void) + 84:Generated_Source\PSoC4/CyLFClk.c **** { + 56 .loc 1 84 0 + 57 .cfi_startproc + 58 @ args = 0, pretend = 0, frame = 0 + 59 @ frame_needed = 1, uses_anonymous_args = 0 + 60 0000 80B5 push {r7, lr} + 61 .cfi_def_cfa_offset 8 + 62 .cfi_offset 7, -8 + 63 .cfi_offset 14, -4 + 64 0002 00AF add r7, sp, #0 + 65 .cfi_def_cfa_register 7 + 85:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_ILO_CONFIG_REG |= CY_SYS_CLK_ILO_CONFIG_ENABLE; + 66 .loc 1 85 0 + 67 0004 044B ldr r3, .L2 + 68 0006 044A ldr r2, .L2 + 69 0008 1268 ldr r2, [r2] + 70 000a 8021 movs r1, #128 + 71 000c 0906 lsls r1, r1, #24 + 72 000e 0A43 orrs r2, r1 + 73 0010 1A60 str r2, [r3] + 86:Generated_Source\PSoC4/CyLFClk.c **** } + 74 .loc 1 86 0 + 75 0012 C046 nop + 76 0014 BD46 mov sp, r7 + 77 @ sp needed + 78 0016 80BD pop {r7, pc} + 79 .L3: + 80 .align 2 + 81 .L2: + 82 0018 04010B40 .word 1074462980 + 83 .cfi_endproc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 4 + + + 84 .LFE0: + 85 .size CySysClkIloStart, .-CySysClkIloStart + 86 .section .text.CySysClkIloStop,"ax",%progbits + 87 .align 2 + 88 .global CySysClkIloStop + 89 .code 16 + 90 .thumb_func + 91 .type CySysClkIloStop, %function + 92 CySysClkIloStop: + 93 .LFB1: + 87:Generated_Source\PSoC4/CyLFClk.c **** + 88:Generated_Source\PSoC4/CyLFClk.c **** + 89:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 90:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloStop + 91:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 92:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 93:Generated_Source\PSoC4/CyLFClk.c **** * Disables the ILO. + 94:Generated_Source\PSoC4/CyLFClk.c **** * + 95:Generated_Source\PSoC4/CyLFClk.c **** * This function has no effect if WDT is locked (CySysWdtLock() is + 96:Generated_Source\PSoC4/CyLFClk.c **** * called). Call CySysWdtUnlock() to unlock WDT and stop ILO. + 97:Generated_Source\PSoC4/CyLFClk.c **** * + 98:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4100 / PSoC 4200: Note that ILO is required for WDT's operation. + 99:Generated_Source\PSoC4/CyLFClk.c **** * + 100:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / + 101:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4200M: + 102:Generated_Source\PSoC4/CyLFClk.c **** * Stopping ILO affects the peripheral clocked by LFCLK, if + 103:Generated_Source\PSoC4/CyLFClk.c **** * LFCLK is configured to be sourced by ILO. + 104:Generated_Source\PSoC4/CyLFClk.c **** * + 105:Generated_Source\PSoC4/CyLFClk.c **** * If the ILO is disabled, all blocks run by ILO will stop functioning. + 106:Generated_Source\PSoC4/CyLFClk.c **** * + 107:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 108:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkIloStop(void) + 109:Generated_Source\PSoC4/CyLFClk.c **** { + 94 .loc 1 109 0 + 95 .cfi_startproc + 96 @ args = 0, pretend = 0, frame = 8 + 97 @ frame_needed = 1, uses_anonymous_args = 0 + 98 0000 90B5 push {r4, r7, lr} + 99 .cfi_def_cfa_offset 12 + 100 .cfi_offset 4, -12 + 101 .cfi_offset 7, -8 + 102 .cfi_offset 14, -4 + 103 0002 83B0 sub sp, sp, #12 + 104 .cfi_def_cfa_offset 24 + 105 0004 00AF add r7, sp, #0 + 106 .cfi_def_cfa_register 7 + 110:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) + 111:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; + 112:Generated_Source\PSoC4/CyLFClk.c **** + 113:Generated_Source\PSoC4/CyLFClk.c **** /* Do nothing if WDT is locked or ILO is disabled */ + 114:Generated_Source\PSoC4/CyLFClk.c **** if (0u == CySysWdtLocked()) + 107 .loc 1 114 0 + 108 0006 FFF7FEFF bl CySysWdtLocked + 109 000a 031E subs r3, r0, #0 + 110 000c 17D1 bne .L6 + 115:Generated_Source\PSoC4/CyLFClk.c **** { + 116:Generated_Source\PSoC4/CyLFClk.c **** if (0u != CySysClkIloEnabled()) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 5 + + + 111 .loc 1 116 0 + 112 000e FFF7FEFF bl CySysClkIloEnabled + 113 0012 031E subs r3, r0, #0 + 114 0014 13D0 beq .L6 + 117:Generated_Source\PSoC4/CyLFClk.c **** { + 118:Generated_Source\PSoC4/CyLFClk.c **** + 119:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_WCO) + 120:Generated_Source\PSoC4/CyLFClk.c **** if (CY_SYS_CLK_LFCLK_SRC_ILO == CySysClkGetLfclkSource()) + 121:Generated_Source\PSoC4/CyLFClk.c **** { + 122:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_WCO) */ + 123:Generated_Source\PSoC4/CyLFClk.c **** + 124:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); + 115 .loc 1 124 0 + 116 0016 FC1D adds r4, r7, #7 + 117 0018 FFF7FEFF bl CyEnterCriticalSection + 118 001c 0300 movs r3, r0 + 119 001e 2370 strb r3, [r4] + 125:Generated_Source\PSoC4/CyLFClk.c **** CySysClkLfclkPosedgeCatch(); + 120 .loc 1 125 0 + 121 0020 FFF7FEFF bl CySysClkLfclkPosedgeCatch + 126:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + 122 .loc 1 126 0 + 123 0024 084B ldr r3, .L7 + 124 0026 084A ldr r2, .L7 + 125 0028 1268 ldr r2, [r2] + 126 002a 5200 lsls r2, r2, #1 + 127 002c 5208 lsrs r2, r2, #1 + 128 002e 1A60 str r2, [r3] + 127:Generated_Source\PSoC4/CyLFClk.c **** CySysClkLfclkPosedgeRestore(); + 129 .loc 1 127 0 + 130 0030 FFF7FEFF bl CySysClkLfclkPosedgeRestore + 128:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); + 131 .loc 1 128 0 + 132 0034 FB1D adds r3, r7, #7 + 133 0036 1B78 ldrb r3, [r3] + 134 0038 1800 movs r0, r3 + 135 003a FFF7FEFF bl CyExitCriticalSection + 136 .L6: + 129:Generated_Source\PSoC4/CyLFClk.c **** + 130:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_WCO) + 131:Generated_Source\PSoC4/CyLFClk.c **** } + 132:Generated_Source\PSoC4/CyLFClk.c **** else /* Safe to disable - shortened pulse does not impact peripheral */ + 133:Generated_Source\PSoC4/CyLFClk.c **** { + 134:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + 135:Generated_Source\PSoC4/CyLFClk.c **** } + 136:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_WCO) */ + 137:Generated_Source\PSoC4/CyLFClk.c **** + 138:Generated_Source\PSoC4/CyLFClk.c **** } + 139:Generated_Source\PSoC4/CyLFClk.c **** } + 140:Generated_Source\PSoC4/CyLFClk.c **** #else + 141:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_ILO_CONFIG_REG &= ( uint32 ) ( ~( uint32 )CY_SYS_CLK_ILO_CONFIG_ENABLE); + 142:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ + 143:Generated_Source\PSoC4/CyLFClk.c **** } + 137 .loc 1 143 0 + 138 003e C046 nop + 139 0040 BD46 mov sp, r7 + 140 0042 03B0 add sp, sp, #12 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 6 + + + 141 @ sp needed + 142 0044 90BD pop {r4, r7, pc} + 143 .L8: + 144 0046 C046 .align 2 + 145 .L7: + 146 0048 04010B40 .word 1074462980 + 147 .cfi_endproc + 148 .LFE1: + 149 .size CySysClkIloStop, .-CySysClkIloStop + 150 .section .text.CySysClkIloStartMeasurement,"ax",%progbits + 151 .align 2 + 152 .global CySysClkIloStartMeasurement + 153 .code 16 + 154 .thumb_func + 155 .type CySysClkIloStartMeasurement, %function + 156 CySysClkIloStartMeasurement: + 157 .LFB2: + 144:Generated_Source\PSoC4/CyLFClk.c **** + 145:Generated_Source\PSoC4/CyLFClk.c **** + 146:Generated_Source\PSoC4/CyLFClk.c **** /****************************************************************************** + 147:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloStartMeasurement + 148:Generated_Source\PSoC4/CyLFClk.c **** ***************************************************************************//** + 149:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 150:Generated_Source\PSoC4/CyLFClk.c **** * Starts the ILO accuracy measurement. + 151:Generated_Source\PSoC4/CyLFClk.c **** * + 152:Generated_Source\PSoC4/CyLFClk.c **** * This function is non-blocking and needs to be called before using the + 153:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkIloTrim() and CySysClkIloCompensate() API. + 154:Generated_Source\PSoC4/CyLFClk.c **** * + 155:Generated_Source\PSoC4/CyLFClk.c **** * This API configures measurement counters to be sourced by SysClk (Counter 1) + 156:Generated_Source\PSoC4/CyLFClk.c **** * and ILO (Counter 2). + 157:Generated_Source\PSoC4/CyLFClk.c **** * + 158:Generated_Source\PSoC4/CyLFClk.c **** * \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and + 159:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkIloCompensate() API can give incorrect results. + 160:Generated_Source\PSoC4/CyLFClk.c **** * + 161:Generated_Source\PSoC4/CyLFClk.c **** * In addition, this API stores the factory ILO trim settings on the first call + 162:Generated_Source\PSoC4/CyLFClk.c **** * after reset. This stored factory setting is used by the + 163:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkIloRestoreFactoryTrim() API to restore the ILO factory trim. + 164:Generated_Source\PSoC4/CyLFClk.c **** * Hence, it is important to call this API before restoring the ILO + 165:Generated_Source\PSoC4/CyLFClk.c **** * factory trim settings. + 166:Generated_Source\PSoC4/CyLFClk.c **** * + 167:Generated_Source\PSoC4/CyLFClk.c **** ******************************************************************************/ + 168:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkIloStartMeasurement(void) + 169:Generated_Source\PSoC4/CyLFClk.c **** { + 158 .loc 1 169 0 + 159 .cfi_startproc + 160 @ args = 0, pretend = 0, frame = 0 + 161 @ frame_needed = 1, uses_anonymous_args = 0 + 162 0000 80B5 push {r7, lr} + 163 .cfi_def_cfa_offset 8 + 164 .cfi_offset 7, -8 + 165 .cfi_offset 14, -4 + 166 0002 00AF add r7, sp, #0 + 167 .cfi_def_cfa_register 7 + 170:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + 171:Generated_Source\PSoC4/CyLFClk.c **** static uint8 iloTrimTrig = 0u; + 172:Generated_Source\PSoC4/CyLFClk.c **** + 173:Generated_Source\PSoC4/CyLFClk.c **** /* Write default ILO trim value while ILO starting ( Cypress ID 225244 )*/ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 7 + + + 174:Generated_Source\PSoC4/CyLFClk.c **** if (0u == iloTrimTrig) + 175:Generated_Source\PSoC4/CyLFClk.c **** { + 176:Generated_Source\PSoC4/CyLFClk.c **** defaultIloTrimRegValue = ((uint8)(CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK)); + 177:Generated_Source\PSoC4/CyLFClk.c **** iloTrimTrig = 1u; + 178:Generated_Source\PSoC4/CyLFClk.c **** } + 179:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + 180:Generated_Source\PSoC4/CyLFClk.c **** + 181:Generated_Source\PSoC4/CyLFClk.c **** /* Configure measurement counters to source by SysClk (Counter 1) and ILO (Counter 2)*/ + 182:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_DFT_REG = (CY_SYS_CLK_DFT_REG & (uint32) ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK) | + 168 .loc 1 182 0 + 169 0004 094B ldr r3, .L10 + 170 0006 094A ldr r2, .L10 + 171 0008 1268 ldr r2, [r2] + 172 000a 0949 ldr r1, .L10+4 + 173 000c 0A40 ands r2, r1 + 174 000e 8021 movs r1, #128 + 175 0010 4900 lsls r1, r1, #1 + 176 0012 0A43 orrs r2, r1 + 177 0014 1A60 str r2, [r3] + 183:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_SEL_ILO_DFT_SOURCE; + 184:Generated_Source\PSoC4/CyLFClk.c **** + 185:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TST_DDFT_CTRL_REG = (CY_SYS_TST_DDFT_CTRL_REG & (uint32) ~ CY_SYS_TST_DDFT_CTRL_REG_DEFA + 178 .loc 1 185 0 + 179 0016 074B ldr r3, .L10+8 + 180 0018 064A ldr r2, .L10+8 + 181 001a 1268 ldr r2, [r2] + 182 001c 0649 ldr r1, .L10+12 + 183 001e 0A40 ands r2, r1 + 184 0020 0649 ldr r1, .L10+16 + 185 0022 0A43 orrs r2, r1 + 186 0024 1A60 str r2, [r3] + 186:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1; + 187:Generated_Source\PSoC4/CyLFClk.c **** } + 187 .loc 1 187 0 + 188 0026 C046 nop + 189 0028 BD46 mov sp, r7 + 190 @ sp needed + 191 002a 80BD pop {r7, pc} + 192 .L11: + 193 .align 2 + 194 .L10: + 195 002c 10010B40 .word 1074462992 + 196 0030 FFF0FFFF .word -3841 + 197 0034 08000340 .word 1073938440 + 198 0038 C0C0FFFF .word -16192 + 199 003c 01020000 .word 513 + 200 .cfi_endproc + 201 .LFE2: + 202 .size CySysClkIloStartMeasurement, .-CySysClkIloStartMeasurement + 203 .section .text.CySysClkIloStopMeasurement,"ax",%progbits + 204 .align 2 + 205 .global CySysClkIloStopMeasurement + 206 .code 16 + 207 .thumb_func + 208 .type CySysClkIloStopMeasurement, %function + 209 CySysClkIloStopMeasurement: + 210 .LFB3: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 8 + + + 188:Generated_Source\PSoC4/CyLFClk.c **** + 189:Generated_Source\PSoC4/CyLFClk.c **** + 190:Generated_Source\PSoC4/CyLFClk.c **** /****************************************************************************** + 191:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloStopMeasurement + 192:Generated_Source\PSoC4/CyLFClk.c **** ***************************************************************************//** + 193:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 194:Generated_Source\PSoC4/CyLFClk.c **** * Stops the ILO accuracy measurement. + 195:Generated_Source\PSoC4/CyLFClk.c **** * + 196:Generated_Source\PSoC4/CyLFClk.c **** * Calling this function immediately stops the the ILO frequency measurement. + 197:Generated_Source\PSoC4/CyLFClk.c **** * This function should be called before placing the device to deepsleep, if + 198:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkIloStartMeasurement() API was called before. + 199:Generated_Source\PSoC4/CyLFClk.c **** * + 200:Generated_Source\PSoC4/CyLFClk.c **** ******************************************************************************/ + 201:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkIloStopMeasurement(void) + 202:Generated_Source\PSoC4/CyLFClk.c **** { + 211 .loc 1 202 0 + 212 .cfi_startproc + 213 @ args = 0, pretend = 0, frame = 0 + 214 @ frame_needed = 1, uses_anonymous_args = 0 + 215 0000 80B5 push {r7, lr} + 216 .cfi_def_cfa_offset 8 + 217 .cfi_offset 7, -8 + 218 .cfi_offset 14, -4 + 219 0002 00AF add r7, sp, #0 + 220 .cfi_def_cfa_register 7 + 203:Generated_Source\PSoC4/CyLFClk.c **** /* Set default configurations in 11...8 DFT register bits to zero */ + 204:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_DFT_REG &= ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK; + 221 .loc 1 204 0 + 222 0004 044B ldr r3, .L13 + 223 0006 044A ldr r2, .L13 + 224 0008 1268 ldr r2, [r2] + 225 000a 0449 ldr r1, .L13+4 + 226 000c 0A40 ands r2, r1 + 227 000e 1A60 str r2, [r3] + 205:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSLT) + 206:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TST_DDFT_CTRL_REG &= ((uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + 207:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSLT) */ + 208:Generated_Source\PSoC4/CyLFClk.c **** } + 228 .loc 1 208 0 + 229 0010 C046 nop + 230 0012 BD46 mov sp, r7 + 231 @ sp needed + 232 0014 80BD pop {r7, pc} + 233 .L14: + 234 0016 C046 .align 2 + 235 .L13: + 236 0018 10010B40 .word 1074462992 + 237 001c FFF0FFFF .word -3841 + 238 .cfi_endproc + 239 .LFE3: + 240 .size CySysClkIloStopMeasurement, .-CySysClkIloStopMeasurement + 241 .global __aeabi_uidiv + 242 .section .text.CySysClkIloCompensate,"ax",%progbits + 243 .align 2 + 244 .global CySysClkIloCompensate + 245 .code 16 + 246 .thumb_func + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 9 + + + 247 .type CySysClkIloCompensate, %function + 248 CySysClkIloCompensate: + 249 .LFB4: + 209:Generated_Source\PSoC4/CyLFClk.c **** + 210:Generated_Source\PSoC4/CyLFClk.c **** + 211:Generated_Source\PSoC4/CyLFClk.c **** /****************************************************************************** + 212:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloCompensate + 213:Generated_Source\PSoC4/CyLFClk.c **** ***************************************************************************//** + 214:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 215:Generated_Source\PSoC4/CyLFClk.c **** * This API measures the current ILO accuracy. + 216:Generated_Source\PSoC4/CyLFClk.c **** * + 217:Generated_Source\PSoC4/CyLFClk.c **** * Basing on the measured frequency the required number of ILO cycles for a + 218:Generated_Source\PSoC4/CyLFClk.c **** * given delay (in microseconds) is obtained. The desired delay that needs to + 219:Generated_Source\PSoC4/CyLFClk.c **** * be compensated is passed through the desiredDelay parameter. The compensated + 220:Generated_Source\PSoC4/CyLFClk.c **** * cycle count is returned through the compesatedCycles pointer. + 221:Generated_Source\PSoC4/CyLFClk.c **** * The compensated ILO cycles can then be used to define the WDT period value, + 222:Generated_Source\PSoC4/CyLFClk.c **** * effectively compensating for the ILO inaccuracy and allowing a more + 223:Generated_Source\PSoC4/CyLFClk.c **** * accurate WDT interrupt generation. + 224:Generated_Source\PSoC4/CyLFClk.c **** * + 225:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkIloStartMeasurement() API should be called prior to calling this API. + 226:Generated_Source\PSoC4/CyLFClk.c **** * + 227:Generated_Source\PSoC4/CyLFClk.c **** * \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and + 228:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkIloCompensate() API can give incorrect results. + 229:Generated_Source\PSoC4/CyLFClk.c **** * + 230:Generated_Source\PSoC4/CyLFClk.c **** * \note If the System clock frequency is changed in runtime, the CyDelayFreq() + 231:Generated_Source\PSoC4/CyLFClk.c **** * with the appropriate parameter (Frequency of bus clock in Hertz) should be + 232:Generated_Source\PSoC4/CyLFClk.c **** * called before calling a next CySysClkIloCompensate(). + 233:Generated_Source\PSoC4/CyLFClk.c **** * + 234:Generated_Source\PSoC4/CyLFClk.c **** * \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS. + 235:Generated_Source\PSoC4/CyLFClk.c **** * + 236:Generated_Source\PSoC4/CyLFClk.c **** * \param desiredDelay Required delay in microseconds. + 237:Generated_Source\PSoC4/CyLFClk.c **** * + 238:Generated_Source\PSoC4/CyLFClk.c **** * \param *compensatedCycles The pointer to the variable in which the required + 239:Generated_Source\PSoC4/CyLFClk.c **** * number of ILO cycles for the given delay will be returned. + 240:Generated_Source\PSoC4/CyLFClk.c **** * + 241:Generated_Source\PSoC4/CyLFClk.c **** * \details + 242:Generated_Source\PSoC4/CyLFClk.c **** * The value returned in *compensatedCycles pointer is not valid until the + 243:Generated_Source\PSoC4/CyLFClk.c **** * function returns CYRET_SUCCESS. + 244:Generated_Source\PSoC4/CyLFClk.c **** * + 245:Generated_Source\PSoC4/CyLFClk.c **** * The desiredDelay parameter value should be in next range:
From 100 to + 246:Generated_Source\PSoC4/CyLFClk.c **** * 2 000 000 microseconds for PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog + 247:Generated_Source\PSoC4/CyLFClk.c **** * Coprocessor devices.
From 100 to 4 000 000 000 microseconds for + 248:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / + 249:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4200L / PSoC 4100M /PSoC 4200M devices. + 250:Generated_Source\PSoC4/CyLFClk.c **** * + 251:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_SUCCESS - The compensation process is complete and the + 252:Generated_Source\PSoC4/CyLFClk.c **** * compensated cycles value is returned in the compensatedCycles pointer. + 253:Generated_Source\PSoC4/CyLFClk.c **** * + 254:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_STARTED - Indicates measurement is in progress. It is + 255:Generated_Source\PSoC4/CyLFClk.c **** * strongly recommended to do not make pauses between API calling. The + 256:Generated_Source\PSoC4/CyLFClk.c **** * function should be called repeatedly until the API returns CYRET_SUCCESS. + 257:Generated_Source\PSoC4/CyLFClk.c **** * + 258:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_INVALID_STATE - Indicates that measurement not started. + 259:Generated_Source\PSoC4/CyLFClk.c **** * The user should call CySysClkIloStartMeasurement() API before calling + 260:Generated_Source\PSoC4/CyLFClk.c **** * this API. + 261:Generated_Source\PSoC4/CyLFClk.c **** * + 262:Generated_Source\PSoC4/CyLFClk.c **** * \note For a correct WDT or DeepSleep Timers functioning with ILO compensating + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 10 + + + 263:Generated_Source\PSoC4/CyLFClk.c **** * the CySysClkIloCompensate() should be called before WDT or DeepSleep Timers + 264:Generated_Source\PSoC4/CyLFClk.c **** * enabling. + 265:Generated_Source\PSoC4/CyLFClk.c **** * + 266:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 267:Generated_Source\PSoC4/CyLFClk.c **** cystatus CySysClkIloCompensate(uint32 desiredDelay , uint32* compensatedCycles) + 268:Generated_Source\PSoC4/CyLFClk.c **** { + 250 .loc 1 268 0 + 251 .cfi_startproc + 252 @ args = 0, pretend = 0, frame = 24 + 253 @ frame_needed = 1, uses_anonymous_args = 0 + 254 0000 90B5 push {r4, r7, lr} + 255 .cfi_def_cfa_offset 12 + 256 .cfi_offset 4, -12 + 257 .cfi_offset 7, -8 + 258 .cfi_offset 14, -4 + 259 0002 87B0 sub sp, sp, #28 + 260 .cfi_def_cfa_offset 40 + 261 0004 00AF add r7, sp, #0 + 262 .cfi_def_cfa_register 7 + 263 0006 7860 str r0, [r7, #4] + 264 0008 3960 str r1, [r7] + 269:Generated_Source\PSoC4/CyLFClk.c **** uint32 iloCompensatedCycles; + 270:Generated_Source\PSoC4/CyLFClk.c **** uint32 desiredDelayInCounts; + 271:Generated_Source\PSoC4/CyLFClk.c **** static uint32 compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + 272:Generated_Source\PSoC4/CyLFClk.c **** uint32 checkStatus; + 273:Generated_Source\PSoC4/CyLFClk.c **** cystatus returnStatus; + 274:Generated_Source\PSoC4/CyLFClk.c **** + 275:Generated_Source\PSoC4/CyLFClk.c **** checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + 265 .loc 1 275 0 + 266 000a 474B ldr r3, .L27 + 267 000c 1B68 ldr r3, [r3] + 268 000e 474A ldr r2, .L27+4 + 269 0010 1340 ands r3, r2 + 270 0012 FB60 str r3, [r7, #12] + 276:Generated_Source\PSoC4/CyLFClk.c **** + 277:Generated_Source\PSoC4/CyLFClk.c **** /* Check if CySysStartMeasurement was called before */ + 278:Generated_Source\PSoC4/CyLFClk.c **** if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + 271 .loc 1 278 0 + 272 0014 FA68 ldr r2, [r7, #12] + 273 0016 8023 movs r3, #128 + 274 0018 5B00 lsls r3, r3, #1 + 275 001a 9A42 cmp r2, r3 + 276 001c 00D0 beq .LCB190 + 277 001e 7CE0 b .L16 @long jump + 278 .LCB190: + 279:Generated_Source\PSoC4/CyLFClk.c **** (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + 279 .loc 1 279 0 discriminator 1 + 280 0020 434B ldr r3, .L27+8 + 281 0022 1B68 ldr r3, [r3] + 278:Generated_Source\PSoC4/CyLFClk.c **** (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + 282 .loc 1 278 0 discriminator 1 + 283 0024 434A ldr r2, .L27+12 + 284 0026 9342 cmp r3, r2 + 285 0028 00D0 beq .LCB195 + 286 002a 76E0 b .L16 @long jump + 287 .LCB195: + 288 .loc 1 279 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 11 + + + 289 002c 7B68 ldr r3, [r7, #4] + 290 002e 424A ldr r2, .L27+16 + 291 0030 9342 cmp r3, r2 + 292 0032 00D9 bls .LCB199 + 293 0034 71E0 b .L16 @long jump + 294 .LCB199: + 280:Generated_Source\PSoC4/CyLFClk.c **** (CY_SYS_CLK_MAX_DELAY_US >= desiredDelay) && + 295 .loc 1 280 0 + 296 0036 7B68 ldr r3, [r7, #4] + 297 0038 632B cmp r3, #99 + 298 003a 6ED9 bls .L16 + 281:Generated_Source\PSoC4/CyLFClk.c **** (CY_SYS_CLK_MIN_DELAY_US <= desiredDelay) && + 299 .loc 1 281 0 + 300 003c 3B68 ldr r3, [r7] + 301 003e 002B cmp r3, #0 + 302 0040 6BD0 beq .L16 + 282:Generated_Source\PSoC4/CyLFClk.c **** (compensatedCycles != NULL)) + 283:Generated_Source\PSoC4/CyLFClk.c **** { + 284:Generated_Source\PSoC4/CyLFClk.c **** if(CY_SYS_CLK_TRIM_OR_COMP_FINISHED != compensateRunningStatus) + 303 .loc 1 284 0 + 304 0042 3E4B ldr r3, .L27+20 + 305 0044 1B68 ldr r3, [r3] + 306 0046 002B cmp r3, #0 + 307 0048 5CD0 beq .L17 + 285:Generated_Source\PSoC4/CyLFClk.c **** { + 286:Generated_Source\PSoC4/CyLFClk.c **** /* Wait until counter 1 stopped counting and after it calculate compensated cycles */ + 287:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + 308 .loc 1 287 0 + 309 004a 3D4B ldr r3, .L27+24 + 310 004c 1B68 ldr r3, [r3] + 311 004e 002B cmp r3, #0 + 312 0050 55DA bge .L18 + 288:Generated_Source\PSoC4/CyLFClk.c **** { + 289:Generated_Source\PSoC4/CyLFClk.c **** if (0u != CY_SYS_CNT_REG2_REG) + 313 .loc 1 289 0 + 314 0052 3C4B ldr r3, .L27+28 + 315 0054 1B68 ldr r3, [r3] + 316 0056 002B cmp r3, #0 + 317 0058 4ED0 beq .L19 + 290:Generated_Source\PSoC4/CyLFClk.c **** { + 291:Generated_Source\PSoC4/CyLFClk.c **** /* Calculate required number of ILO cycles for given delay */ + 292:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) + 293:Generated_Source\PSoC4/CyLFClk.c **** if (CY_SYS_CLK_DELAY_COUNTS_LIMIT < desiredDelay) + 318 .loc 1 293 0 + 319 005a 7B68 ldr r3, [r7, #4] + 320 005c 3A4A ldr r2, .L27+32 + 321 005e 9342 cmp r3, r2 + 322 0060 1ED9 bls .L20 + 294:Generated_Source\PSoC4/CyLFClk.c **** { + 295:Generated_Source\PSoC4/CyLFClk.c **** desiredDelayInCounts = (desiredDelay / CY_SYS_CLK_ILO_PERIOD); + 323 .loc 1 295 0 + 324 0062 7B68 ldr r3, [r7, #4] + 325 0064 1F21 movs r1, #31 + 326 0066 1800 movs r0, r3 + 327 0068 FFF7FEFF bl __aeabi_uidiv + 328 006c 0300 movs r3, r0 + 329 006e BB60 str r3, [r7, #8] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 12 + + + 296:Generated_Source\PSoC4/CyLFClk.c **** iloCompensatedCycles = + 297:Generated_Source\PSoC4/CyLFClk.c **** (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_ + 330 .loc 1 297 0 + 331 0070 344B ldr r3, .L27+28 + 332 0072 1A68 ldr r2, [r3] + 333 0074 354B ldr r3, .L27+36 + 334 0076 1B68 ldr r3, [r3] + 335 0078 5A43 muls r2, r3 + 336 007a 344B ldr r3, .L27+36 + 337 007c 1B68 ldr r3, [r3] + 338 007e 9B0A lsrs r3, r3, #10 + 339 0080 1900 movs r1, r3 + 340 0082 1000 movs r0, r2 + 341 0084 FFF7FEFF bl __aeabi_uidiv + 342 0088 0300 movs r3, r0 + 343 008a 5C09 lsrs r4, r3, #5 + 298:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_ILO_FREQ_2MSB) * (desiredDelayInCounts / CY_SYS_CLK_ILO_ + 344 .loc 1 298 0 + 345 008c BA68 ldr r2, [r7, #8] + 346 008e FA23 movs r3, #250 + 347 0090 9900 lsls r1, r3, #2 + 348 0092 1000 movs r0, r2 + 349 0094 FFF7FEFF bl __aeabi_uidiv + 350 0098 0300 movs r3, r0 + 296:Generated_Source\PSoC4/CyLFClk.c **** iloCompensatedCycles = + 351 .loc 1 296 0 + 352 009a 6343 muls r3, r4 + 353 009c 7B61 str r3, [r7, #20] + 354 009e 22E0 b .L21 + 355 .L20: + 299:Generated_Source\PSoC4/CyLFClk.c **** } + 300:Generated_Source\PSoC4/CyLFClk.c **** else + 301:Generated_Source\PSoC4/CyLFClk.c **** { + 302:Generated_Source\PSoC4/CyLFClk.c **** desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + + 356 .loc 1 302 0 + 357 00a0 7B68 ldr r3, [r7, #4] + 358 00a2 6422 movs r2, #100 + 359 00a4 5343 muls r3, r2 + 360 00a6 2A4A ldr r2, .L27+40 + 361 00a8 9446 mov ip, r2 + 362 00aa 6344 add r3, r3, ip + 363 00ac 2949 ldr r1, .L27+44 + 364 00ae 1800 movs r0, r3 + 365 00b0 FFF7FEFF bl __aeabi_uidiv + 366 00b4 0300 movs r3, r0 + 367 00b6 BB60 str r3, [r7, #8] + 303:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_HALF_OF_CLOCK) / CY_SYS_CLK_ILO_PER + 304:Generated_Source\PSoC4/CyLFClk.c **** + 305:Generated_Source\PSoC4/CyLFClk.c **** iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + 368 .loc 1 305 0 + 369 00b8 224B ldr r3, .L27+28 + 370 00ba 1A68 ldr r2, [r3] + 371 00bc 234B ldr r3, .L27+36 + 372 00be 1B68 ldr r3, [r3] + 373 00c0 5A43 muls r2, r3 + 306:Generated_Source\PSoC4/CyLFClk.c **** (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) + 374 .loc 1 306 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 13 + + + 375 00c2 224B ldr r3, .L27+36 + 376 00c4 1B68 ldr r3, [r3] + 377 00c6 9B0A lsrs r3, r3, #10 + 305:Generated_Source\PSoC4/CyLFClk.c **** (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) + 378 .loc 1 305 0 + 379 00c8 1900 movs r1, r3 + 380 00ca 1000 movs r0, r2 + 381 00cc FFF7FEFF bl __aeabi_uidiv + 382 00d0 0300 movs r3, r0 + 383 00d2 1A00 movs r2, r3 + 384 .loc 1 306 0 + 385 00d4 BB68 ldr r3, [r7, #8] + 386 00d6 5A43 muls r2, r3 + 305:Generated_Source\PSoC4/CyLFClk.c **** (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) + 387 .loc 1 305 0 + 388 00d8 FA23 movs r3, #250 + 389 00da D901 lsls r1, r3, #7 + 390 00dc 1000 movs r0, r2 + 391 00de FFF7FEFF bl __aeabi_uidiv + 392 00e2 0300 movs r3, r0 + 393 00e4 7B61 str r3, [r7, #20] + 394 .L21: + 307:Generated_Source\PSoC4/CyLFClk.c **** desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED + 308:Generated_Source\PSoC4/CyLFClk.c **** } + 309:Generated_Source\PSoC4/CyLFClk.c **** #else /* (CY_IP_SRSSLT) */ + 310:Generated_Source\PSoC4/CyLFClk.c **** desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + CY_SYS_ + 311:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_C + 312:Generated_Source\PSoC4/CyLFClk.c **** if(CY_SYS_CLK_MAX_LITE_NUMBER < desiredDelayInCounts) + 313:Generated_Source\PSoC4/CyLFClk.c **** { + 314:Generated_Source\PSoC4/CyLFClk.c **** iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydel + 315:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_SYS_CLK_DEVIDER)) / CY_SYS_CLK_ILO_FR + 316:Generated_Source\PSoC4/CyLFClk.c **** (desiredDelayInCounts / CY_SYS_CLK_ILO_FREQ_3LSB + 317:Generated_Source\PSoC4/CyLFClk.c **** } + 318:Generated_Source\PSoC4/CyLFClk.c **** else + 319:Generated_Source\PSoC4/CyLFClk.c **** { + 320:Generated_Source\PSoC4/CyLFClk.c **** iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + 321:Generated_Source\PSoC4/CyLFClk.c **** (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) + 322:Generated_Source\PSoC4/CyLFClk.c **** desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED + 323:Generated_Source\PSoC4/CyLFClk.c **** } + 324:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ + 325:Generated_Source\PSoC4/CyLFClk.c **** + 326:Generated_Source\PSoC4/CyLFClk.c **** *compensatedCycles = iloCompensatedCycles; + 395 .loc 1 326 0 + 396 00e6 3B68 ldr r3, [r7] + 397 00e8 7A69 ldr r2, [r7, #20] + 398 00ea 1A60 str r2, [r3] + 327:Generated_Source\PSoC4/CyLFClk.c **** compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + 399 .loc 1 327 0 + 400 00ec 134B ldr r3, .L27+20 + 401 00ee 0022 movs r2, #0 + 402 00f0 1A60 str r2, [r3] + 328:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_SUCCESS; + 403 .loc 1 328 0 + 404 00f2 0023 movs r3, #0 + 405 00f4 3B61 str r3, [r7, #16] + 284:Generated_Source\PSoC4/CyLFClk.c **** { + 406 .loc 1 284 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 14 + + + 407 00f6 12E0 b .L25 + 408 .L19: + 329:Generated_Source\PSoC4/CyLFClk.c **** } + 330:Generated_Source\PSoC4/CyLFClk.c **** else + 331:Generated_Source\PSoC4/CyLFClk.c **** { + 332:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_INVALID_STATE; + 409 .loc 1 332 0 + 410 00f8 1123 movs r3, #17 + 411 00fa 3B61 str r3, [r7, #16] + 284:Generated_Source\PSoC4/CyLFClk.c **** { + 412 .loc 1 284 0 + 413 00fc 0FE0 b .L25 + 414 .L18: + 333:Generated_Source\PSoC4/CyLFClk.c **** } + 334:Generated_Source\PSoC4/CyLFClk.c **** } + 335:Generated_Source\PSoC4/CyLFClk.c **** else + 336:Generated_Source\PSoC4/CyLFClk.c **** { + 337:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_STARTED; + 415 .loc 1 337 0 + 416 00fe 0723 movs r3, #7 + 417 0100 3B61 str r3, [r7, #16] + 284:Generated_Source\PSoC4/CyLFClk.c **** { + 418 .loc 1 284 0 + 419 0102 0CE0 b .L25 + 420 .L17: + 338:Generated_Source\PSoC4/CyLFClk.c **** } + 339:Generated_Source\PSoC4/CyLFClk.c **** } + 340:Generated_Source\PSoC4/CyLFClk.c **** else + 341:Generated_Source\PSoC4/CyLFClk.c **** { + 342:Generated_Source\PSoC4/CyLFClk.c **** /* Reload CNTR 1 count value for next measurement cycle*/ + 343:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CNT_REG1_REG = (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER); + 421 .loc 1 343 0 + 422 0104 0E4A ldr r2, .L27+24 + 423 0106 114B ldr r3, .L27+36 + 424 0108 1B68 ldr r3, [r3] + 425 010a 9B0A lsrs r3, r3, #10 + 426 010c 1360 str r3, [r2] + 344:Generated_Source\PSoC4/CyLFClk.c **** compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + 427 .loc 1 344 0 + 428 010e 0B4B ldr r3, .L27+20 + 429 0110 0122 movs r2, #1 + 430 0112 1A60 str r2, [r3] + 345:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_STARTED; + 431 .loc 1 345 0 + 432 0114 0723 movs r3, #7 + 433 0116 3B61 str r3, [r7, #16] + 284:Generated_Source\PSoC4/CyLFClk.c **** { + 434 .loc 1 284 0 + 435 0118 01E0 b .L25 + 436 .L16: + 346:Generated_Source\PSoC4/CyLFClk.c **** } + 347:Generated_Source\PSoC4/CyLFClk.c **** } + 348:Generated_Source\PSoC4/CyLFClk.c **** else + 349:Generated_Source\PSoC4/CyLFClk.c **** { + 350:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_INVALID_STATE; + 437 .loc 1 350 0 + 438 011a 1123 movs r3, #17 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 15 + + + 439 011c 3B61 str r3, [r7, #16] + 440 .L25: + 351:Generated_Source\PSoC4/CyLFClk.c **** } + 352:Generated_Source\PSoC4/CyLFClk.c **** + 353:Generated_Source\PSoC4/CyLFClk.c **** return (returnStatus); + 441 .loc 1 353 0 + 442 011e 3B69 ldr r3, [r7, #16] + 354:Generated_Source\PSoC4/CyLFClk.c **** } + 443 .loc 1 354 0 + 444 0120 1800 movs r0, r3 + 445 0122 BD46 mov sp, r7 + 446 0124 07B0 add sp, sp, #28 + 447 @ sp needed + 448 0126 90BD pop {r4, r7, pc} + 449 .L28: + 450 .align 2 + 451 .L27: + 452 0128 10010B40 .word 1074462992 + 453 012c 3F3F0000 .word 16191 + 454 0130 08000340 .word 1073938440 + 455 0134 01020000 .word 513 + 456 0138 00286BEE .word -294967296 + 457 013c 18000000 .word compensateRunningStatus.4836 + 458 0140 18000340 .word 1073938456 + 459 0144 1C000340 .word 1073938460 + 460 0148 60D10000 .word 53600 + 461 014c 00000000 .word cydelayFreqHz + 462 0150 0D030000 .word 781 + 463 0154 350C0000 .word 3125 + 464 .cfi_endproc + 465 .LFE4: + 466 .size CySysClkIloCompensate, .-CySysClkIloCompensate + 467 .section .text.CySysClkIloEnabled,"ax",%progbits + 468 .align 2 + 469 .code 16 + 470 .thumb_func + 471 .type CySysClkIloEnabled, %function + 472 CySysClkIloEnabled: + 473 .LFB5: + 355:Generated_Source\PSoC4/CyLFClk.c **** + 356:Generated_Source\PSoC4/CyLFClk.c **** + 357:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) + 358:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 359:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloEnabled + 360:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 361:Generated_Source\PSoC4/CyLFClk.c **** * + 362:Generated_Source\PSoC4/CyLFClk.c **** * \internal + 363:Generated_Source\PSoC4/CyLFClk.c **** * Reports the ILO enable state. + 364:Generated_Source\PSoC4/CyLFClk.c **** * + 365:Generated_Source\PSoC4/CyLFClk.c **** * \return + 366:Generated_Source\PSoC4/CyLFClk.c **** * 1 if ILO is enabled, and 0 if ILO is disabled. + 367:Generated_Source\PSoC4/CyLFClk.c **** * + 368:Generated_Source\PSoC4/CyLFClk.c **** * \endinternal + 369:Generated_Source\PSoC4/CyLFClk.c **** ********************************************************************************/ + 370:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysClkIloEnabled(void) + 371:Generated_Source\PSoC4/CyLFClk.c **** { + 474 .loc 1 371 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 16 + + + 475 .cfi_startproc + 476 @ args = 0, pretend = 0, frame = 0 + 477 @ frame_needed = 1, uses_anonymous_args = 0 + 478 0000 80B5 push {r7, lr} + 479 .cfi_def_cfa_offset 8 + 480 .cfi_offset 7, -8 + 481 .cfi_offset 14, -4 + 482 0002 00AF add r7, sp, #0 + 483 .cfi_def_cfa_register 7 + 372:Generated_Source\PSoC4/CyLFClk.c **** /* Prohibits writing to WDT registers and ILO/WCO registers when not equal to 0 */ + 373:Generated_Source\PSoC4/CyLFClk.c **** return ((0u != (CY_SYS_CLK_ILO_CONFIG_REG & (uint32)(CY_SYS_CLK_ILO_CONFIG_ENABLE))) ? + 484 .loc 1 373 0 + 485 0004 044B ldr r3, .L33 + 486 0006 1B68 ldr r3, [r3] + 374:Generated_Source\PSoC4/CyLFClk.c **** (uint32) 1u : + 487 .loc 1 374 0 + 488 0008 002B cmp r3, #0 + 489 000a 01DA bge .L30 + 490 .loc 1 374 0 is_stmt 0 discriminator 1 + 491 000c 0123 movs r3, #1 + 373:Generated_Source\PSoC4/CyLFClk.c **** (uint32) 1u : + 492 .loc 1 373 0 is_stmt 1 discriminator 1 + 493 000e 00E0 b .L32 + 494 .L30: + 495 .loc 1 374 0 discriminator 2 + 496 0010 0023 movs r3, #0 + 497 .L32: + 375:Generated_Source\PSoC4/CyLFClk.c **** (uint32) 0u); + 376:Generated_Source\PSoC4/CyLFClk.c **** } + 498 .loc 1 376 0 discriminator 1 + 499 0012 1800 movs r0, r3 + 500 0014 BD46 mov sp, r7 + 501 @ sp needed + 502 0016 80BD pop {r7, pc} + 503 .L34: + 504 .align 2 + 505 .L33: + 506 0018 04010B40 .word 1074462980 + 507 .cfi_endproc + 508 .LFE5: + 509 .size CySysClkIloEnabled, .-CySysClkIloEnabled + 510 .section .text.CySysWdtLock,"ax",%progbits + 511 .align 2 + 512 .global CySysWdtLock + 513 .code 16 + 514 .thumb_func + 515 .type CySysWdtLock, %function + 516 CySysWdtLock: + 517 .LFB6: + 377:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ + 378:Generated_Source\PSoC4/CyLFClk.c **** + 379:Generated_Source\PSoC4/CyLFClk.c **** + 380:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + 381:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************** + 382:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloTrim + 383:Generated_Source\PSoC4/CyLFClk.c **** *****************************************************************************//** + 384:Generated_Source\PSoC4/CyLFClk.c **** * \brief + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 17 + + + 385:Generated_Source\PSoC4/CyLFClk.c **** * The API trims the ILO frequency to +/- 10% accuracy range using accurate + 386:Generated_Source\PSoC4/CyLFClk.c **** * SysClk. + 387:Generated_Source\PSoC4/CyLFClk.c **** * + 388:Generated_Source\PSoC4/CyLFClk.c **** * The API can be blocking or non-blocking depending on the value of the mode + 389:Generated_Source\PSoC4/CyLFClk.c **** * parameter passed. The accuracy of ILO after trimming in parts per thousand + 390:Generated_Source\PSoC4/CyLFClk.c **** * is returned through the iloAccuracyInPPT pointer. A positive number indicates + 391:Generated_Source\PSoC4/CyLFClk.c **** * that the ILO is running fast and a negative number indicates that the ILO is + 392:Generated_Source\PSoC4/CyLFClk.c **** * running slowly. This error is relative to the error in the reference clock + 393:Generated_Source\PSoC4/CyLFClk.c **** * (SysClk), so the absolute error will be higher and depends on the accuracy + 394:Generated_Source\PSoC4/CyLFClk.c **** * of the reference. + 395:Generated_Source\PSoC4/CyLFClk.c **** * + 396:Generated_Source\PSoC4/CyLFClk.c **** * The CySysClkIloStartMeasurement() API should be called prior to calling this + 397:Generated_Source\PSoC4/CyLFClk.c **** * API. Otherwise it will return CYRET_INVALID_STATE as the measurement was not + 398:Generated_Source\PSoC4/CyLFClk.c **** * started. + 399:Generated_Source\PSoC4/CyLFClk.c **** * + 400:Generated_Source\PSoC4/CyLFClk.c **** * \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and + 401:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkIloCompensate() API can give incorrect results. + 402:Generated_Source\PSoC4/CyLFClk.c **** * + 403:Generated_Source\PSoC4/CyLFClk.c **** * \note If System clock frequency is changed in runtime, the CyDelayFreq() + 404:Generated_Source\PSoC4/CyLFClk.c **** * with the appropriate parameter (Frequency of bus clock in Hertz) should be + 405:Generated_Source\PSoC4/CyLFClk.c **** * called before next CySysClkIloCompensate() usage. + 406:Generated_Source\PSoC4/CyLFClk.c **** * + 407:Generated_Source\PSoC4/CyLFClk.c **** * \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS + 408:Generated_Source\PSoC4/CyLFClk.c **** * or CYRET_TIMEOUT. + 409:Generated_Source\PSoC4/CyLFClk.c **** * + 410:Generated_Source\PSoC4/CyLFClk.c **** * Available for all PSoC 4 devices with ILO trim capability. This excludes + 411:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4000 / PSoC 4100 / PSoC 4200 / PSoC 4000S / PSoC 4100S / PSoC + 412:Generated_Source\PSoC4/CyLFClk.c **** * Analog Coprocessor devices. + 413:Generated_Source\PSoC4/CyLFClk.c **** * + 414:Generated_Source\PSoC4/CyLFClk.c **** * \param mode + 415:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_BLOCKING - The function does not return until the ILO is + 416:Generated_Source\PSoC4/CyLFClk.c **** * within +/-10% accuracy range or time out has occurred.
+ 417:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_NON_BLOCKING - The function returns immediately after + 418:Generated_Source\PSoC4/CyLFClk.c **** * performing a single iteration of the trim process. The function should be + 419:Generated_Source\PSoC4/CyLFClk.c **** * called repeatedly until the trimming is completed successfully. + 420:Generated_Source\PSoC4/CyLFClk.c **** * + 421:Generated_Source\PSoC4/CyLFClk.c **** * \param *iloAccuracyInPPT Pointer to an integer in which the trimmed ILO + 422:Generated_Source\PSoC4/CyLFClk.c **** * accuracy will be returned. + 423:Generated_Source\PSoC4/CyLFClk.c **** * + 424:Generated_Source\PSoC4/CyLFClk.c **** * \details The value returned in *iloAccuracyInPPT pointer is not valid + 425:Generated_Source\PSoC4/CyLFClk.c **** * until the function returns CYRET_SUCCESS. ILO accuracy in PPT is given by: + 426:Generated_Source\PSoC4/CyLFClk.c **** * + 427:Generated_Source\PSoC4/CyLFClk.c **** * IloAccuracyInPPT = ((MeasuredIloFreq - DesiredIloFreq) * + 428:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_PERTHOUSAND) / DesiredIloFreq); + 429:Generated_Source\PSoC4/CyLFClk.c **** * + 430:Generated_Source\PSoC4/CyLFClk.c **** * DesiredIloFreq = 32000, CY_SYS_CLK_PERTHOUSAND = 1000; + 431:Generated_Source\PSoC4/CyLFClk.c **** * + 432:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_SUCCESS - Indicates trimming is complete. This value indicates + 433:Generated_Source\PSoC4/CyLFClk.c **** * trimming is successful and iloAccuracyInPPT is within +/- 10%. + 434:Generated_Source\PSoC4/CyLFClk.c **** * + 435:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_STARTED - Indicates measurement is in progress. This is applicable + 436:Generated_Source\PSoC4/CyLFClk.c **** * only for non-blocking mode. + 437:Generated_Source\PSoC4/CyLFClk.c **** * + 438:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. You should + 439:Generated_Source\PSoC4/CyLFClk.c **** * call CySysClkIloStartMeasurement() before calling this API. + 440:Generated_Source\PSoC4/CyLFClk.c **** * + 441:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_TIMEOUT - Indicates trimming was unsuccessful. This is applicable + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 18 + + + 442:Generated_Source\PSoC4/CyLFClk.c **** * only for blocking mode. Timeout means the trimming was tried 5 times without + 443:Generated_Source\PSoC4/CyLFClk.c **** * success (i.e. ILO accuracy > +/- 10%). The user can call the API again for + 444:Generated_Source\PSoC4/CyLFClk.c **** * another try or wait for some time before calling it again (to let the system + 445:Generated_Source\PSoC4/CyLFClk.c **** * to settle to another operating point change in temperature etc.) and continue + 446:Generated_Source\PSoC4/CyLFClk.c **** * using the previous trim value till the next call. + 447:Generated_Source\PSoC4/CyLFClk.c **** * + 448:Generated_Source\PSoC4/CyLFClk.c **** **********************************************************************************/ + 449:Generated_Source\PSoC4/CyLFClk.c **** cystatus CySysClkIloTrim(uint32 mode, int32* iloAccuracyInPPT) + 450:Generated_Source\PSoC4/CyLFClk.c **** { + 451:Generated_Source\PSoC4/CyLFClk.c **** uint32 timeOutClocks = CY_SYS_CLK_TIMEOUT; + 452:Generated_Source\PSoC4/CyLFClk.c **** uint32 waitUntilCntr1Stops; + 453:Generated_Source\PSoC4/CyLFClk.c **** static uint32 trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + 454:Generated_Source\PSoC4/CyLFClk.c **** uint32 checkStatus; + 455:Generated_Source\PSoC4/CyLFClk.c **** cystatus returnStatus; + 456:Generated_Source\PSoC4/CyLFClk.c **** + 457:Generated_Source\PSoC4/CyLFClk.c **** checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + 458:Generated_Source\PSoC4/CyLFClk.c **** + 459:Generated_Source\PSoC4/CyLFClk.c **** /* Check if DFT and CTRL registers were configures in CySysStartMeasurement*/ + 460:Generated_Source\PSoC4/CyLFClk.c **** if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + 461:Generated_Source\PSoC4/CyLFClk.c **** (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + 462:Generated_Source\PSoC4/CyLFClk.c **** (iloAccuracyInPPT != NULL)) + 463:Generated_Source\PSoC4/CyLFClk.c **** { + 464:Generated_Source\PSoC4/CyLFClk.c **** if(CY_SYS_CLK_BLOCKING == mode) + 465:Generated_Source\PSoC4/CyLFClk.c **** { + 466:Generated_Source\PSoC4/CyLFClk.c **** waitUntilCntr1Stops = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + 467:Generated_Source\PSoC4/CyLFClk.c **** do + 468:Generated_Source\PSoC4/CyLFClk.c **** { + 469:Generated_Source\PSoC4/CyLFClk.c **** /* Reload CNTR 1 count value for measuring cycle*/ + 470:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + 471:Generated_Source\PSoC4/CyLFClk.c **** + 472:Generated_Source\PSoC4/CyLFClk.c **** /* Wait until counter CNTR 1 will finish down-counting */ + 473:Generated_Source\PSoC4/CyLFClk.c **** while (0u == (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + 474:Generated_Source\PSoC4/CyLFClk.c **** { + 475:Generated_Source\PSoC4/CyLFClk.c **** waitUntilCntr1Stops--; + 476:Generated_Source\PSoC4/CyLFClk.c **** if (0u == waitUntilCntr1Stops) + 477:Generated_Source\PSoC4/CyLFClk.c **** { + 478:Generated_Source\PSoC4/CyLFClk.c **** break; + 479:Generated_Source\PSoC4/CyLFClk.c **** } + 480:Generated_Source\PSoC4/CyLFClk.c **** } + 481:Generated_Source\PSoC4/CyLFClk.c **** trimRunningStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + 482:Generated_Source\PSoC4/CyLFClk.c **** timeOutClocks--; + 483:Generated_Source\PSoC4/CyLFClk.c **** + 484:Generated_Source\PSoC4/CyLFClk.c **** /* Untill ILO accuracy will be in range less than +/- 10% or timeout occurs*/ + 485:Generated_Source\PSoC4/CyLFClk.c **** } while((CYRET_SUCCESS != trimRunningStatus) && + 486:Generated_Source\PSoC4/CyLFClk.c **** (CYRET_INVALID_STATE != trimRunningStatus) && + 487:Generated_Source\PSoC4/CyLFClk.c **** (0u != timeOutClocks)); + 488:Generated_Source\PSoC4/CyLFClk.c **** + 489:Generated_Source\PSoC4/CyLFClk.c **** if (CYRET_SUCCESS == trimRunningStatus) + 490:Generated_Source\PSoC4/CyLFClk.c **** { + 491:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_SUCCESS; + 492:Generated_Source\PSoC4/CyLFClk.c **** } + 493:Generated_Source\PSoC4/CyLFClk.c **** else + 494:Generated_Source\PSoC4/CyLFClk.c **** { + 495:Generated_Source\PSoC4/CyLFClk.c **** if(0u == timeOutClocks) + 496:Generated_Source\PSoC4/CyLFClk.c **** { + 497:Generated_Source\PSoC4/CyLFClk.c **** trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + 498:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_TIMEOUT; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 19 + + + 499:Generated_Source\PSoC4/CyLFClk.c **** } + 500:Generated_Source\PSoC4/CyLFClk.c **** else + 501:Generated_Source\PSoC4/CyLFClk.c **** { + 502:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_INVALID_STATE; + 503:Generated_Source\PSoC4/CyLFClk.c **** } + 504:Generated_Source\PSoC4/CyLFClk.c **** } + 505:Generated_Source\PSoC4/CyLFClk.c **** } + 506:Generated_Source\PSoC4/CyLFClk.c **** /* Non - blocking mode */ + 507:Generated_Source\PSoC4/CyLFClk.c **** else + 508:Generated_Source\PSoC4/CyLFClk.c **** { + 509:Generated_Source\PSoC4/CyLFClk.c **** if (CY_SYS_CLK_TRIM_OR_COMP_FINISHED != trimRunningStatus) + 510:Generated_Source\PSoC4/CyLFClk.c **** { + 511:Generated_Source\PSoC4/CyLFClk.c **** /* Checking if the counter CNTR 1 finished down-counting */ + 512:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + 513:Generated_Source\PSoC4/CyLFClk.c **** { + 514:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + 515:Generated_Source\PSoC4/CyLFClk.c **** trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + 516:Generated_Source\PSoC4/CyLFClk.c **** } + 517:Generated_Source\PSoC4/CyLFClk.c **** else + 518:Generated_Source\PSoC4/CyLFClk.c **** { + 519:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_STARTED; + 520:Generated_Source\PSoC4/CyLFClk.c **** } + 521:Generated_Source\PSoC4/CyLFClk.c **** } + 522:Generated_Source\PSoC4/CyLFClk.c **** else + 523:Generated_Source\PSoC4/CyLFClk.c **** { + 524:Generated_Source\PSoC4/CyLFClk.c **** /* Reload CNTR 1 count value for next measuring */ + 525:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + 526:Generated_Source\PSoC4/CyLFClk.c **** trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + 527:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_STARTED; + 528:Generated_Source\PSoC4/CyLFClk.c **** } + 529:Generated_Source\PSoC4/CyLFClk.c **** } + 530:Generated_Source\PSoC4/CyLFClk.c **** } + 531:Generated_Source\PSoC4/CyLFClk.c **** else + 532:Generated_Source\PSoC4/CyLFClk.c **** { + 533:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_INVALID_STATE; + 534:Generated_Source\PSoC4/CyLFClk.c **** } + 535:Generated_Source\PSoC4/CyLFClk.c **** + 536:Generated_Source\PSoC4/CyLFClk.c **** return (returnStatus); + 537:Generated_Source\PSoC4/CyLFClk.c **** } + 538:Generated_Source\PSoC4/CyLFClk.c **** + 539:Generated_Source\PSoC4/CyLFClk.c **** + 540:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************** + 541:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloUpdateTrimReg + 542:Generated_Source\PSoC4/CyLFClk.c **** ********************************************************************************* + 543:Generated_Source\PSoC4/CyLFClk.c **** * + 544:Generated_Source\PSoC4/CyLFClk.c **** * \internal + 545:Generated_Source\PSoC4/CyLFClk.c **** * Function calculates ILO accuracy and check is error range is higher than + 546:Generated_Source\PSoC4/CyLFClk.c **** * +/- 10%. If Measured frequency is higher than +/- 10% function updates + 547:Generated_Source\PSoC4/CyLFClk.c **** * ILO Trim register. + 548:Generated_Source\PSoC4/CyLFClk.c **** * + 549:Generated_Source\PSoC4/CyLFClk.c **** * \param + 550:Generated_Source\PSoC4/CyLFClk.c **** * iloAccuracyInPPT Pointer to an integer in which the trimmed ILO + 551:Generated_Source\PSoC4/CyLFClk.c **** * accuracy will be returned. The value returned in this pointer is not valid + 552:Generated_Source\PSoC4/CyLFClk.c **** * until the function returns CYRET_SUCCESS. If ILO frequency error is lower + 553:Generated_Source\PSoC4/CyLFClk.c **** * than +/- 10% then the value returned in this pointer will be updated. + 554:Generated_Source\PSoC4/CyLFClk.c **** * + 555:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_SUCCESS - Indicates that ILO frequency error is lower than + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 20 + + + 556:Generated_Source\PSoC4/CyLFClk.c **** * +/- 10% and no actions are required. + 557:Generated_Source\PSoC4/CyLFClk.c **** * + 558:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_STARTED - Indicates that ILO frequency error is higher than + 559:Generated_Source\PSoC4/CyLFClk.c **** * +/- 10% and ILO Trim register was updated. + 560:Generated_Source\PSoC4/CyLFClk.c **** * + 561:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. + 562:Generated_Source\PSoC4/CyLFClk.c **** * + 563:Generated_Source\PSoC4/CyLFClk.c **** * Post #1 - To obtain 10% ILO accuracy the calculated accuracy should be equal + 564:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_ERROR_RANGE = 5.6%. Error value should take to account IMO error of + 565:Generated_Source\PSoC4/CyLFClk.c **** * +/-2% (+/-0.64kHz), trim step of 2.36kHz (+/-1.18kHz) and error while ILO + 566:Generated_Source\PSoC4/CyLFClk.c **** * frequency measuring. + 567:Generated_Source\PSoC4/CyLFClk.c **** * + 568:Generated_Source\PSoC4/CyLFClk.c **** * \endinternal + 569:Generated_Source\PSoC4/CyLFClk.c **** * + 570:Generated_Source\PSoC4/CyLFClk.c **** **********************************************************************************/ + 571:Generated_Source\PSoC4/CyLFClk.c **** cystatus CySysClkIloUpdateTrimReg(int32* iloAccuracyInPPT) + 572:Generated_Source\PSoC4/CyLFClk.c **** { + 573:Generated_Source\PSoC4/CyLFClk.c **** uint32 measuredIloFreq; + 574:Generated_Source\PSoC4/CyLFClk.c **** uint32 currentIloTrimValue; + 575:Generated_Source\PSoC4/CyLFClk.c **** int32 iloAccuracyValue; + 576:Generated_Source\PSoC4/CyLFClk.c **** int32 trimStep; + 577:Generated_Source\PSoC4/CyLFClk.c **** cystatus errorRangeStatus; + 578:Generated_Source\PSoC4/CyLFClk.c **** + 579:Generated_Source\PSoC4/CyLFClk.c **** if(0u != CY_SYS_CNT_REG2_REG) + 580:Generated_Source\PSoC4/CyLFClk.c **** { + 581:Generated_Source\PSoC4/CyLFClk.c **** measuredIloFreq = (CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_SYS_ + 582:Generated_Source\PSoC4/CyLFClk.c **** + 583:Generated_Source\PSoC4/CyLFClk.c **** /* Calculate value of error in PPT according to formula - + 584:Generated_Source\PSoC4/CyLFClk.c **** * ((measuredIlofrequency - iloDesired frequency) * 1000 / iloDesired frequency) */ + 585:Generated_Source\PSoC4/CyLFClk.c **** iloAccuracyValue = (((int32) measuredIloFreq - (int32) CY_SYS_CLK_ILO_DESIRED_FREQ_HZ) * \ + 586:Generated_Source\PSoC4/CyLFClk.c **** ((int32) CY_SYS_CLK_PERTHOUSAND)) / ((int32) CY_SYS_CLK_ILO_DESIRED_FRE + 587:Generated_Source\PSoC4/CyLFClk.c **** + 588:Generated_Source\PSoC4/CyLFClk.c **** /* Check if ILO accuracy is more than +/- CY_SYS_CLK_ERROR_RANGE. See post #1 of API descri + 589:Generated_Source\PSoC4/CyLFClk.c **** if(CY_SYS_CLK_ERROR_RANGE < (uint32) (CY_SYS_CLK_ABS_MACRO(iloAccuracyValue))) + 590:Generated_Source\PSoC4/CyLFClk.c **** { + 591:Generated_Source\PSoC4/CyLFClk.c **** if (0 < iloAccuracyValue) + 592:Generated_Source\PSoC4/CyLFClk.c **** { + 593:Generated_Source\PSoC4/CyLFClk.c **** trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) + + 594:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + 595:Generated_Source\PSoC4/CyLFClk.c **** } + 596:Generated_Source\PSoC4/CyLFClk.c **** else + 597:Generated_Source\PSoC4/CyLFClk.c **** { + 598:Generated_Source\PSoC4/CyLFClk.c **** trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) - + 599:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + 600:Generated_Source\PSoC4/CyLFClk.c **** } + 601:Generated_Source\PSoC4/CyLFClk.c **** currentIloTrimValue = (CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK); + 602:Generated_Source\PSoC4/CyLFClk.c **** trimStep = (int32) currentIloTrimValue - trimStep; + 603:Generated_Source\PSoC4/CyLFClk.c **** + 604:Generated_Source\PSoC4/CyLFClk.c **** if(trimStep > CY_SYS_CLK_FOURBITS_MAX) + 605:Generated_Source\PSoC4/CyLFClk.c **** { + 606:Generated_Source\PSoC4/CyLFClk.c **** trimStep = CY_SYS_CLK_FOURBITS_MAX; + 607:Generated_Source\PSoC4/CyLFClk.c **** } + 608:Generated_Source\PSoC4/CyLFClk.c **** if(trimStep < 0) + 609:Generated_Source\PSoC4/CyLFClk.c **** { + 610:Generated_Source\PSoC4/CyLFClk.c **** trimStep = 0; + 611:Generated_Source\PSoC4/CyLFClk.c **** } + 612:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_ILO_TRIM_REG = (CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MASK + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 21 + + + 613:Generated_Source\PSoC4/CyLFClk.c **** ((uint32) trimStep); + 614:Generated_Source\PSoC4/CyLFClk.c **** errorRangeStatus = CYRET_STARTED; + 615:Generated_Source\PSoC4/CyLFClk.c **** } /* Else return success because error is in +/- 10% range*/ + 616:Generated_Source\PSoC4/CyLFClk.c **** else + 617:Generated_Source\PSoC4/CyLFClk.c **** { + 618:Generated_Source\PSoC4/CyLFClk.c **** /* Write trimmed ILO accuracy through pointer. */ + 619:Generated_Source\PSoC4/CyLFClk.c **** *iloAccuracyInPPT = iloAccuracyValue; + 620:Generated_Source\PSoC4/CyLFClk.c **** errorRangeStatus = CYRET_SUCCESS; + 621:Generated_Source\PSoC4/CyLFClk.c **** } + 622:Generated_Source\PSoC4/CyLFClk.c **** } + 623:Generated_Source\PSoC4/CyLFClk.c **** else + 624:Generated_Source\PSoC4/CyLFClk.c **** { + 625:Generated_Source\PSoC4/CyLFClk.c **** errorRangeStatus = CYRET_INVALID_STATE; + 626:Generated_Source\PSoC4/CyLFClk.c **** } + 627:Generated_Source\PSoC4/CyLFClk.c **** return (errorRangeStatus); + 628:Generated_Source\PSoC4/CyLFClk.c **** } + 629:Generated_Source\PSoC4/CyLFClk.c **** + 630:Generated_Source\PSoC4/CyLFClk.c **** + 631:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 632:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkIloRestoreFactoryTrim + 633:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 634:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 635:Generated_Source\PSoC4/CyLFClk.c **** * Restores the ILO Trim Register to factory value. + 636:Generated_Source\PSoC4/CyLFClk.c **** * + 637:Generated_Source\PSoC4/CyLFClk.c **** * The CySysClkIloStartMeasurement() API should be called prior to + 638:Generated_Source\PSoC4/CyLFClk.c **** * calling this API. Otherwise CYRET_UNKNOWN will be returned. + 639:Generated_Source\PSoC4/CyLFClk.c **** * + 640:Generated_Source\PSoC4/CyLFClk.c **** * Available for all PSoC 4 devices except for PSoC 4000 / PSoC 4100 / PSoC 4200 + 641:Generated_Source\PSoC4/CyLFClk.c **** * / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + 642:Generated_Source\PSoC4/CyLFClk.c **** * + 643:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_SUCCESS - Operation was successful. + 644:Generated_Source\PSoC4/CyLFClk.c **** * \return CYRET_UNKNOWN - CySysClkIloStartMeasurement() was not called + 645:Generated_Source\PSoC4/CyLFClk.c **** * before this API. Hence the trim value cannot be updated. + 646:Generated_Source\PSoC4/CyLFClk.c **** * + 647:Generated_Source\PSoC4/CyLFClk.c **** ******************************************************************************/ + 648:Generated_Source\PSoC4/CyLFClk.c **** cystatus CySysClkIloRestoreFactoryTrim(void) + 649:Generated_Source\PSoC4/CyLFClk.c **** { + 650:Generated_Source\PSoC4/CyLFClk.c **** cystatus returnStatus = CYRET_SUCCESS; + 651:Generated_Source\PSoC4/CyLFClk.c **** + 652:Generated_Source\PSoC4/CyLFClk.c **** /* Check was defaultIloTrimRegValue modified in CySysClkIloStartMeasurement */ + 653:Generated_Source\PSoC4/CyLFClk.c **** if(CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE != defaultIloTrimRegValue) + 654:Generated_Source\PSoC4/CyLFClk.c **** { + 655:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_ILO_TRIM_REG = ((CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MAS + 656:Generated_Source\PSoC4/CyLFClk.c **** (defaultIloTrimRegValue & CY_SYS_CLK_ILO_TRIM_MASK)); + 657:Generated_Source\PSoC4/CyLFClk.c **** } + 658:Generated_Source\PSoC4/CyLFClk.c **** else + 659:Generated_Source\PSoC4/CyLFClk.c **** { + 660:Generated_Source\PSoC4/CyLFClk.c **** returnStatus = CYRET_UNKNOWN; + 661:Generated_Source\PSoC4/CyLFClk.c **** } + 662:Generated_Source\PSoC4/CyLFClk.c **** + 663:Generated_Source\PSoC4/CyLFClk.c **** return (returnStatus); + 664:Generated_Source\PSoC4/CyLFClk.c **** } + 665:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + 666:Generated_Source\PSoC4/CyLFClk.c **** + 667:Generated_Source\PSoC4/CyLFClk.c **** + 668:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_WCO && CY_IP_SRSSV2) + 669:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 22 + + + 670:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkGetLfclkSource + 671:Generated_Source\PSoC4/CyLFClk.c **** ******************************************************************************** + 672:Generated_Source\PSoC4/CyLFClk.c **** * + 673:Generated_Source\PSoC4/CyLFClk.c **** * \internal + 674:Generated_Source\PSoC4/CyLFClk.c **** * Gets the clock source for the LFCLK clock. + 675:Generated_Source\PSoC4/CyLFClk.c **** * The function is applicable only for PSoC 4100 BLE / PSoC 4200 BLE / + 676:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4100M / PSoC 4200M / PSoC 4200L. + 677:Generated_Source\PSoC4/CyLFClk.c **** * + 678:Generated_Source\PSoC4/CyLFClk.c **** * \return The LFCLK source: + 679:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_LFCLK_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) + 680:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_LFCLK_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) + 681:Generated_Source\PSoC4/CyLFClk.c **** * + 682:Generated_Source\PSoC4/CyLFClk.c **** * \endinternal + 683:Generated_Source\PSoC4/CyLFClk.c **** * + 684:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 685:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysClkGetLfclkSource(void) + 686:Generated_Source\PSoC4/CyLFClk.c **** { + 687:Generated_Source\PSoC4/CyLFClk.c **** uint32 lfclkSource; + 688:Generated_Source\PSoC4/CyLFClk.c **** lfclkSource = CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK; + 689:Generated_Source\PSoC4/CyLFClk.c **** return (lfclkSource); + 690:Generated_Source\PSoC4/CyLFClk.c **** } + 691:Generated_Source\PSoC4/CyLFClk.c **** + 692:Generated_Source\PSoC4/CyLFClk.c **** + 693:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 694:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkSetLfclkSource + 695:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 696:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 697:Generated_Source\PSoC4/CyLFClk.c **** * Sets the clock source for the LFCLK clock. + 698:Generated_Source\PSoC4/CyLFClk.c **** * + 699:Generated_Source\PSoC4/CyLFClk.c **** * The switch between LFCLK sources must be done between the positive edges of + 700:Generated_Source\PSoC4/CyLFClk.c **** * LFCLK, because the glitch risk is around the LFCLK positive edge. To ensure + 701:Generated_Source\PSoC4/CyLFClk.c **** * that the switch can be done safely, the WDT counter value is read until it + 702:Generated_Source\PSoC4/CyLFClk.c **** * changes. + 703:Generated_Source\PSoC4/CyLFClk.c **** * + 704:Generated_Source\PSoC4/CyLFClk.c **** * That means that the positive edge just finished and the switch is performed. + 705:Generated_Source\PSoC4/CyLFClk.c **** * The enabled WDT counter is used for that purpose. If no counters are enabled, + 706:Generated_Source\PSoC4/CyLFClk.c **** * counter 0 is enabled. And after the LFCLK source is switched, counter 0 + 707:Generated_Source\PSoC4/CyLFClk.c **** * configuration is restored. + 708:Generated_Source\PSoC4/CyLFClk.c **** * + 709:Generated_Source\PSoC4/CyLFClk.c **** * The function is applicable only for devices with more than one source for + 710:Generated_Source\PSoC4/CyLFClk.c **** * LFCLK - PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC 4100M / PSoC 4200M / + 711:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4200L. + 712:Generated_Source\PSoC4/CyLFClk.c **** * + 713:Generated_Source\PSoC4/CyLFClk.c **** * \note For PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices LFCLK can + 714:Generated_Source\PSoC4/CyLFClk.c **** * only be sourced from ILO even though WCO is available. + 715:Generated_Source\PSoC4/CyLFClk.c **** * + 716:Generated_Source\PSoC4/CyLFClk.c **** * \param + 717:Generated_Source\PSoC4/CyLFClk.c **** * source + 718:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_LFCLK_SRC_ILO - Internal Low Frequency (32 kHz) + 719:Generated_Source\PSoC4/CyLFClk.c **** * Oscillator (ILO).
+ 720:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_LFCLK_SRC_WCO - Low Frequency Watch Crystal Oscillator (WCO). + 721:Generated_Source\PSoC4/CyLFClk.c **** * + 722:Generated_Source\PSoC4/CyLFClk.c **** * \details + 723:Generated_Source\PSoC4/CyLFClk.c **** * This function has no effect if WDT is locked (CySysWdtLock() is called). + 724:Generated_Source\PSoC4/CyLFClk.c **** * Call CySysWdtUnlock() to unlock WDT. + 725:Generated_Source\PSoC4/CyLFClk.c **** * + 726:Generated_Source\PSoC4/CyLFClk.c **** * Both the current source and the new source must be running and stable before + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 23 + + + 727:Generated_Source\PSoC4/CyLFClk.c **** * calling this function. + 728:Generated_Source\PSoC4/CyLFClk.c **** * + 729:Generated_Source\PSoC4/CyLFClk.c **** * Changing the LFCLK clock source may change the LFCLK clock frequency and + 730:Generated_Source\PSoC4/CyLFClk.c **** * affect the functionality that uses this clock. For example, watchdog timer + 731:Generated_Source\PSoC4/CyLFClk.c **** * "uses this clock" or "this clock uses" (WDT) is clocked by LFCLK. + 732:Generated_Source\PSoC4/CyLFClk.c **** * + 733:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 734:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkSetLfclkSource(uint32 source) + 735:Generated_Source\PSoC4/CyLFClk.c **** { + 736:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; + 737:Generated_Source\PSoC4/CyLFClk.c **** + 738:Generated_Source\PSoC4/CyLFClk.c **** if (CySysClkGetLfclkSource() != source) + 739:Generated_Source\PSoC4/CyLFClk.c **** { + 740:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); + 741:Generated_Source\PSoC4/CyLFClk.c **** CySysClkLfclkPosedgeCatch(); + 742:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONFIG_REG = (CY_SYS_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_LFCLK_SEL_MASK)) + 743:Generated_Source\PSoC4/CyLFClk.c **** (source & CY_SYS_CLK_LFCLK_SEL_MASK); + 744:Generated_Source\PSoC4/CyLFClk.c **** CySysClkLfclkPosedgeRestore(); + 745:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); + 746:Generated_Source\PSoC4/CyLFClk.c **** } + 747:Generated_Source\PSoC4/CyLFClk.c **** } + 748:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + 749:Generated_Source\PSoC4/CyLFClk.c **** + 750:Generated_Source\PSoC4/CyLFClk.c **** + 751:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_WCO) + 752:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 753:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkWcoStart + 754:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 755:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 756:Generated_Source\PSoC4/CyLFClk.c **** * Enables Watch Crystal Oscillator (WCO). + 757:Generated_Source\PSoC4/CyLFClk.c **** * + 758:Generated_Source\PSoC4/CyLFClk.c **** * This API enables WCO which is used as a source for LFCLK. Similar to ILO, + 759:Generated_Source\PSoC4/CyLFClk.c **** * WCO is also available in all modes except Hibernate and Stop modes. + 760:Generated_Source\PSoC4/CyLFClk.c **** * \note In PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices + 761:Generated_Source\PSoC4/CyLFClk.c **** * WCO cannot be a source for the LFCLK. + 762:Generated_Source\PSoC4/CyLFClk.c **** * + 763:Generated_Source\PSoC4/CyLFClk.c **** * WCO is always enabled in High Power Mode (HPM). Refer to the device + 764:Generated_Source\PSoC4/CyLFClk.c **** * datasheet for the WCO startup time. Once WCO becomes stable it can be + 765:Generated_Source\PSoC4/CyLFClk.c **** * switched to Low Power Mode (LPM). Note that oscillator can be unstable + 766:Generated_Source\PSoC4/CyLFClk.c **** * during a switch and hence its output should not be used at that moment. + 767:Generated_Source\PSoC4/CyLFClk.c **** * + 768:Generated_Source\PSoC4/CyLFClk.c **** * The CySysClkWcoSetPowerMode() function configures the WCO power mode. + 769:Generated_Source\PSoC4/CyLFClk.c **** * + 770:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 771:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkWcoStart(void) + 772:Generated_Source\PSoC4/CyLFClk.c **** { + 773:Generated_Source\PSoC4/CyLFClk.c **** CySysClkWcoSetHighPowerMode(); + 774:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + 775:Generated_Source\PSoC4/CyLFClk.c **** } + 776:Generated_Source\PSoC4/CyLFClk.c **** + 777:Generated_Source\PSoC4/CyLFClk.c **** + 778:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 779:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkWcoStop + 780:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 781:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 782:Generated_Source\PSoC4/CyLFClk.c **** * Disables the 32 KHz Crystal Oscillator. + 783:Generated_Source\PSoC4/CyLFClk.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 24 + + + 784:Generated_Source\PSoC4/CyLFClk.c **** * API switch of WCO. + 785:Generated_Source\PSoC4/CyLFClk.c **** * \note PSoC 4100S / PSoC Analog Coprocessor: WCO is required for DeepSleep + 786:Generated_Source\PSoC4/CyLFClk.c **** * Timer's operation. + 787:Generated_Source\PSoC4/CyLFClk.c **** * + 788:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 789:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkWcoStop(void) + 790:Generated_Source\PSoC4/CyLFClk.c **** { + 791:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_SRSSV2) + 792:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; + 793:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ + 794:Generated_Source\PSoC4/CyLFClk.c **** + 795:Generated_Source\PSoC4/CyLFClk.c **** if (0u != CySysClkWcoEnabled()) + 796:Generated_Source\PSoC4/CyLFClk.c **** { + 797:Generated_Source\PSoC4/CyLFClk.c **** #if (CY_IP_SRSSV2) + 798:Generated_Source\PSoC4/CyLFClk.c **** if (CY_SYS_CLK_LFCLK_SRC_WCO == CySysClkGetLfclkSource()) + 799:Generated_Source\PSoC4/CyLFClk.c **** { + 800:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); + 801:Generated_Source\PSoC4/CyLFClk.c **** CySysClkLfclkPosedgeCatch(); + 802:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + 803:Generated_Source\PSoC4/CyLFClk.c **** CySysClkLfclkPosedgeRestore(); + 804:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); + 805:Generated_Source\PSoC4/CyLFClk.c **** } + 806:Generated_Source\PSoC4/CyLFClk.c **** else /* Safe to disable - shortened pulse does not impact peripheral */ + 807:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ + 808:Generated_Source\PSoC4/CyLFClk.c **** { + 809:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + 810:Generated_Source\PSoC4/CyLFClk.c **** } + 811:Generated_Source\PSoC4/CyLFClk.c **** } /* Otherwise do nothing. WCO configuration cannot be changed. */ + 812:Generated_Source\PSoC4/CyLFClk.c **** } + 813:Generated_Source\PSoC4/CyLFClk.c **** + 814:Generated_Source\PSoC4/CyLFClk.c **** + 815:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 816:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkWcoEnabled + 817:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 818:Generated_Source\PSoC4/CyLFClk.c **** * \internal Reports the WCO enable state. + 819:Generated_Source\PSoC4/CyLFClk.c **** * + 820:Generated_Source\PSoC4/CyLFClk.c **** * \return 1 if WCO is enabled + 821:Generated_Source\PSoC4/CyLFClk.c **** * \return 0 if WCO is disabled. + 822:Generated_Source\PSoC4/CyLFClk.c **** * \endinternal + 823:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 824:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysClkWcoEnabled(void) + 825:Generated_Source\PSoC4/CyLFClk.c **** { + 826:Generated_Source\PSoC4/CyLFClk.c **** return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE))) ? + 827:Generated_Source\PSoC4/CyLFClk.c **** (uint32) 1u : + 828:Generated_Source\PSoC4/CyLFClk.c **** (uint32) 0u); + 829:Generated_Source\PSoC4/CyLFClk.c **** } + 830:Generated_Source\PSoC4/CyLFClk.c **** + 831:Generated_Source\PSoC4/CyLFClk.c **** + 832:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 833:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkWcoSetPowerMode + 834:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 835:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 836:Generated_Source\PSoC4/CyLFClk.c **** * Sets the power mode for the 32 KHz WCO. + 837:Generated_Source\PSoC4/CyLFClk.c **** * + 838:Generated_Source\PSoC4/CyLFClk.c **** * By default (if this function is not called), the WCO is in High power mode + 839:Generated_Source\PSoC4/CyLFClk.c **** * during Active and device's low power modes + 840:Generated_Source\PSoC4/CyLFClk.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 25 + + + 841:Generated_Source\PSoC4/CyLFClk.c **** * \param mode + 842:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_WCO_HPM - The High Power mode.
+ 843:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_WCO_LPM - The Low Power mode. + 844:Generated_Source\PSoC4/CyLFClk.c **** * + 845:Generated_Source\PSoC4/CyLFClk.c **** * \return A previous power mode. The same as the parameters. + 846:Generated_Source\PSoC4/CyLFClk.c **** * + 847:Generated_Source\PSoC4/CyLFClk.c **** * \note + 848:Generated_Source\PSoC4/CyLFClk.c **** * The WCO Low Power mode is applicable for PSoC 4100 BLE / PSoC 4200 BLE devices. + 849:Generated_Source\PSoC4/CyLFClk.c **** * + 850:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 851:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysClkWcoSetPowerMode(uint32 mode) + 852:Generated_Source\PSoC4/CyLFClk.c **** { + 853:Generated_Source\PSoC4/CyLFClk.c **** uint32 powerModeStatus; + 854:Generated_Source\PSoC4/CyLFClk.c **** + 855:Generated_Source\PSoC4/CyLFClk.c **** powerModeStatus = CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_LPM_EN; + 856:Generated_Source\PSoC4/CyLFClk.c **** + 857:Generated_Source\PSoC4/CyLFClk.c **** switch(mode) + 858:Generated_Source\PSoC4/CyLFClk.c **** { + 859:Generated_Source\PSoC4/CyLFClk.c **** case CY_SYS_CLK_WCO_HPM: + 860:Generated_Source\PSoC4/CyLFClk.c **** CySysClkWcoSetHighPowerMode(); + 861:Generated_Source\PSoC4/CyLFClk.c **** break; + 862:Generated_Source\PSoC4/CyLFClk.c **** + 863:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_BLESS) + 864:Generated_Source\PSoC4/CyLFClk.c **** case CY_SYS_CLK_WCO_LPM: + 865:Generated_Source\PSoC4/CyLFClk.c **** CySysClkWcoSetLowPowerMode(); + 866:Generated_Source\PSoC4/CyLFClk.c **** break; + 867:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_BLESS) */ + 868:Generated_Source\PSoC4/CyLFClk.c **** + 869:Generated_Source\PSoC4/CyLFClk.c **** default: + 870:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); + 871:Generated_Source\PSoC4/CyLFClk.c **** break; + 872:Generated_Source\PSoC4/CyLFClk.c **** } + 873:Generated_Source\PSoC4/CyLFClk.c **** + 874:Generated_Source\PSoC4/CyLFClk.c **** return (powerModeStatus); + 875:Generated_Source\PSoC4/CyLFClk.c **** } + 876:Generated_Source\PSoC4/CyLFClk.c **** + 877:Generated_Source\PSoC4/CyLFClk.c **** + 878:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 879:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkWcoClockOutSelect + 880:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 881:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 882:Generated_Source\PSoC4/CyLFClk.c **** * Selects the WCO block output source. + 883:Generated_Source\PSoC4/CyLFClk.c **** * + 884:Generated_Source\PSoC4/CyLFClk.c **** * In addition to generating 32.768 kHz clock from external crystals, WCO + 885:Generated_Source\PSoC4/CyLFClk.c **** * can be sourced by external clock source using wco_out pin. The API help to + 886:Generated_Source\PSoC4/CyLFClk.c **** * lets you select between the sources: External crystal or external pin. + 887:Generated_Source\PSoC4/CyLFClk.c **** * + 888:Generated_Source\PSoC4/CyLFClk.c **** * If you want to use external pin to drive WCO the next procedure is required: + 889:Generated_Source\PSoC4/CyLFClk.c **** *
1) Disable the WCO. + 890:Generated_Source\PSoC4/CyLFClk.c **** *
2) Drive the wco_out pin to an external signal source. + 891:Generated_Source\PSoC4/CyLFClk.c **** *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_PIN). + 892:Generated_Source\PSoC4/CyLFClk.c **** *
4) Enable the WCO and wait for 15 us before clocking the XO pad at the high + 893:Generated_Source\PSoC4/CyLFClk.c **** * potential. Let's assume you are using the 1.6v clock amplitude, then the + 894:Generated_Source\PSoC4/CyLFClk.c **** * sequence would start at 1.6v, then 0v, then 1.6v etc at a chosen frequency. + 895:Generated_Source\PSoC4/CyLFClk.c **** * + 896:Generated_Source\PSoC4/CyLFClk.c **** * If you want to use WCO after using an external pin source: + 897:Generated_Source\PSoC4/CyLFClk.c **** *
1) Disable the WCO. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 26 + + + 898:Generated_Source\PSoC4/CyLFClk.c **** *
2) Drive off wco_out pin with external signal source. + 899:Generated_Source\PSoC4/CyLFClk.c **** *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_CRYSTAL). + 900:Generated_Source\PSoC4/CyLFClk.c **** *
4) Enable the WCO. + 901:Generated_Source\PSoC4/CyLFClk.c **** * + 902:Generated_Source\PSoC4/CyLFClk.c **** * \warning + 903:Generated_Source\PSoC4/CyLFClk.c **** * Do not use the oscillator output clock prior to a 15uS delay in your system. + 904:Generated_Source\PSoC4/CyLFClk.c **** * There are no limitations on the external clock frequency. + 905:Generated_Source\PSoC4/CyLFClk.c **** * \warning + 906:Generated_Source\PSoC4/CyLFClk.c **** * When external clock source was selected to drive WCO block the IMO can be + 907:Generated_Source\PSoC4/CyLFClk.c **** * trimmed only when external clock source period is equal to WCO external + 908:Generated_Source\PSoC4/CyLFClk.c **** * crystal period. Also external clock source accuracy should be higher + 909:Generated_Source\PSoC4/CyLFClk.c **** * or equal to WCO external crystal accuracy. + 910:Generated_Source\PSoC4/CyLFClk.c **** * + 911:Generated_Source\PSoC4/CyLFClk.c **** * \param clockSel + 912:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_WCO_SEL_CRYSTAL - Selects External crystal as clock + 913:Generated_Source\PSoC4/CyLFClk.c **** * source of WCO.
+ 914:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_WCO_SEL_PIN - Selects External clock input on wco_in pin as + 915:Generated_Source\PSoC4/CyLFClk.c **** * clock source of WCO. + 916:Generated_Source\PSoC4/CyLFClk.c **** * + 917:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 918:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkWcoClockOutSelect(uint32 clockSel) + 919:Generated_Source\PSoC4/CyLFClk.c **** { + 920:Generated_Source\PSoC4/CyLFClk.c **** if (0u != CySysClkWcoEnabled()) + 921:Generated_Source\PSoC4/CyLFClk.c **** { + 922:Generated_Source\PSoC4/CyLFClk.c **** if (1u >= clockSel) + 923:Generated_Source\PSoC4/CyLFClk.c **** { + 924:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_WCO_CONFIG_REG = (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(~CY_SYS_CLK_WCO_S + 925:Generated_Source\PSoC4/CyLFClk.c **** (clockSel << CY_SYS_CLK_WCO_SELECT_PIN_OFFSET); + 926:Generated_Source\PSoC4/CyLFClk.c **** } + 927:Generated_Source\PSoC4/CyLFClk.c **** else + 928:Generated_Source\PSoC4/CyLFClk.c **** { + 929:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); + 930:Generated_Source\PSoC4/CyLFClk.c **** } + 931:Generated_Source\PSoC4/CyLFClk.c **** } + 932:Generated_Source\PSoC4/CyLFClk.c **** } + 933:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_WCO) */ + 934:Generated_Source\PSoC4/CyLFClk.c **** + 935:Generated_Source\PSoC4/CyLFClk.c **** + 936:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) + 937:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 938:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtLock + 939:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 940:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 941:Generated_Source\PSoC4/CyLFClk.c **** * Locks out configuration changes to the Watchdog timer registers and ILO + 942:Generated_Source\PSoC4/CyLFClk.c **** * configuration register. + 943:Generated_Source\PSoC4/CyLFClk.c **** * + 944:Generated_Source\PSoC4/CyLFClk.c **** * After this function is called, ILO clock can't be disabled until + 945:Generated_Source\PSoC4/CyLFClk.c **** * CySysWdtUnlock() is called. + 946:Generated_Source\PSoC4/CyLFClk.c **** * + 947:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 948:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtLock(void) + 949:Generated_Source\PSoC4/CyLFClk.c **** { + 518 .loc 1 949 0 + 519 .cfi_startproc + 520 @ args = 0, pretend = 0, frame = 8 + 521 @ frame_needed = 1, uses_anonymous_args = 0 + 522 0000 90B5 push {r4, r7, lr} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 27 + + + 523 .cfi_def_cfa_offset 12 + 524 .cfi_offset 4, -12 + 525 .cfi_offset 7, -8 + 526 .cfi_offset 14, -4 + 527 0002 83B0 sub sp, sp, #12 + 528 .cfi_def_cfa_offset 24 + 529 0004 00AF add r7, sp, #0 + 530 .cfi_def_cfa_register 7 + 950:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; + 951:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); + 531 .loc 1 951 0 + 532 0006 FC1D adds r4, r7, #7 + 533 0008 FFF7FEFF bl CyEnterCriticalSection + 534 000c 0300 movs r3, r0 + 535 000e 2370 strb r3, [r4] + 952:Generated_Source\PSoC4/CyLFClk.c **** + 953:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) + 536 .loc 1 953 0 + 537 0010 074B ldr r3, .L36 + 538 0012 074A ldr r2, .L36 + 539 0014 1268 ldr r2, [r2] + 540 0016 C021 movs r1, #192 + 541 0018 0902 lsls r1, r1, #8 + 542 001a 0A43 orrs r2, r1 + 543 001c 1A60 str r2, [r3] + 954:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CLK_LOCK_BITS_MASK; + 955:Generated_Source\PSoC4/CyLFClk.c **** + 956:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); + 544 .loc 1 956 0 + 545 001e FB1D adds r3, r7, #7 + 546 0020 1B78 ldrb r3, [r3] + 547 0022 1800 movs r0, r3 + 548 0024 FFF7FEFF bl CyExitCriticalSection + 957:Generated_Source\PSoC4/CyLFClk.c **** } + 549 .loc 1 957 0 + 550 0028 C046 nop + 551 002a BD46 mov sp, r7 + 552 002c 03B0 add sp, sp, #12 + 553 @ sp needed + 554 002e 90BD pop {r4, r7, pc} + 555 .L37: + 556 .align 2 + 557 .L36: + 558 0030 00010B40 .word 1074462976 + 559 .cfi_endproc + 560 .LFE6: + 561 .size CySysWdtLock, .-CySysWdtLock + 562 .section .text.CySysWdtLocked,"ax",%progbits + 563 .align 2 + 564 .code 16 + 565 .thumb_func + 566 .type CySysWdtLocked, %function + 567 CySysWdtLocked: + 568 .LFB7: + 958:Generated_Source\PSoC4/CyLFClk.c **** + 959:Generated_Source\PSoC4/CyLFClk.c **** + 960:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 28 + + + 961:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtLocked + 962:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 963:Generated_Source\PSoC4/CyLFClk.c **** * \internal + 964:Generated_Source\PSoC4/CyLFClk.c **** * Reports the WDT lock state. + 965:Generated_Source\PSoC4/CyLFClk.c **** * + 966:Generated_Source\PSoC4/CyLFClk.c **** * \return 1 - WDT is locked, and 0 - WDT is unlocked. + 967:Generated_Source\PSoC4/CyLFClk.c **** * \endinternal + 968:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 969:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysWdtLocked(void) + 970:Generated_Source\PSoC4/CyLFClk.c **** { + 569 .loc 1 970 0 + 570 .cfi_startproc + 571 @ args = 0, pretend = 0, frame = 0 + 572 @ frame_needed = 1, uses_anonymous_args = 0 + 573 0000 80B5 push {r7, lr} + 574 .cfi_def_cfa_offset 8 + 575 .cfi_offset 7, -8 + 576 .cfi_offset 14, -4 + 577 0002 00AF add r7, sp, #0 + 578 .cfi_def_cfa_register 7 + 971:Generated_Source\PSoC4/CyLFClk.c **** /* Prohibits writing to WDT registers and ILO/WCO registers when not equal 0 */ + 972:Generated_Source\PSoC4/CyLFClk.c **** return ((0u != (CY_SYS_CLK_SELECT_REG & (uint32)(CY_SYS_WDT_CLK_LOCK_BITS_MASK))) ? (uint32 + 579 .loc 1 972 0 + 580 0004 054B ldr r3, .L42 + 581 0006 1A68 ldr r2, [r3] + 582 0008 C023 movs r3, #192 + 583 000a 1B02 lsls r3, r3, #8 + 584 000c 1340 ands r3, r2 + 585 000e 01D0 beq .L39 + 586 .loc 1 972 0 is_stmt 0 discriminator 1 + 587 0010 0123 movs r3, #1 + 588 0012 00E0 b .L41 + 589 .L39: + 590 .loc 1 972 0 discriminator 2 + 591 0014 0023 movs r3, #0 + 592 .L41: + 973:Generated_Source\PSoC4/CyLFClk.c **** } + 593 .loc 1 973 0 is_stmt 1 discriminator 5 + 594 0016 1800 movs r0, r3 + 595 0018 BD46 mov sp, r7 + 596 @ sp needed + 597 001a 80BD pop {r7, pc} + 598 .L43: + 599 .align 2 + 600 .L42: + 601 001c 00010B40 .word 1074462976 + 602 .cfi_endproc + 603 .LFE7: + 604 .size CySysWdtLocked, .-CySysWdtLocked + 605 .section .text.CySysWdtUnlock,"ax",%progbits + 606 .align 2 + 607 .global CySysWdtUnlock + 608 .code 16 + 609 .thumb_func + 610 .type CySysWdtUnlock, %function + 611 CySysWdtUnlock: + 612 .LFB8: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 29 + + + 974:Generated_Source\PSoC4/CyLFClk.c **** + 975:Generated_Source\PSoC4/CyLFClk.c **** + 976:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + 977:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtUnlock + 978:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** + 979:Generated_Source\PSoC4/CyLFClk.c **** * \brief + 980:Generated_Source\PSoC4/CyLFClk.c **** * Unlocks the Watchdog Timer configuration register. + 981:Generated_Source\PSoC4/CyLFClk.c **** * + 982:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + 983:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtUnlock(void) + 984:Generated_Source\PSoC4/CyLFClk.c **** { + 613 .loc 1 984 0 + 614 .cfi_startproc + 615 @ args = 0, pretend = 0, frame = 8 + 616 @ frame_needed = 1, uses_anonymous_args = 0 + 617 0000 90B5 push {r4, r7, lr} + 618 .cfi_def_cfa_offset 12 + 619 .cfi_offset 4, -12 + 620 .cfi_offset 7, -8 + 621 .cfi_offset 14, -4 + 622 0002 83B0 sub sp, sp, #12 + 623 .cfi_def_cfa_offset 24 + 624 0004 00AF add r7, sp, #0 + 625 .cfi_def_cfa_register 7 + 985:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; + 986:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); + 626 .loc 1 986 0 + 627 0006 FC1D adds r4, r7, #7 + 628 0008 FFF7FEFF bl CyEnterCriticalSection + 629 000c 0300 movs r3, r0 + 630 000e 2370 strb r3, [r4] + 987:Generated_Source\PSoC4/CyLFClk.c **** + 988:Generated_Source\PSoC4/CyLFClk.c **** /* Removing WDT lock requires two writes */ + 989:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) + 631 .loc 1 989 0 + 632 0010 0D4B ldr r3, .L45 + 633 0012 0D4A ldr r2, .L45 + 634 0014 1268 ldr r2, [r2] + 635 0016 0D49 ldr r1, .L45+4 + 636 0018 0A40 ands r2, r1 + 637 001a 8021 movs r1, #128 + 638 001c C901 lsls r1, r1, #7 + 639 001e 0A43 orrs r2, r1 + 640 0020 1A60 str r2, [r3] + 990:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CLK_LOCK_BIT0); + 991:Generated_Source\PSoC4/CyLFClk.c **** + 992:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) + 641 .loc 1 992 0 + 642 0022 094B ldr r3, .L45 + 643 0024 084A ldr r2, .L45 + 644 0026 1268 ldr r2, [r2] + 645 0028 0849 ldr r1, .L45+4 + 646 002a 0A40 ands r2, r1 + 647 002c 8021 movs r1, #128 + 648 002e 0902 lsls r1, r1, #8 + 649 0030 0A43 orrs r2, r1 + 650 0032 1A60 str r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 30 + + + 993:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CLK_LOCK_BIT1); + 994:Generated_Source\PSoC4/CyLFClk.c **** + 995:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); + 651 .loc 1 995 0 + 652 0034 FB1D adds r3, r7, #7 + 653 0036 1B78 ldrb r3, [r3] + 654 0038 1800 movs r0, r3 + 655 003a FFF7FEFF bl CyExitCriticalSection + 996:Generated_Source\PSoC4/CyLFClk.c **** } + 656 .loc 1 996 0 + 657 003e C046 nop + 658 0040 BD46 mov sp, r7 + 659 0042 03B0 add sp, sp, #12 + 660 @ sp needed + 661 0044 90BD pop {r4, r7, pc} + 662 .L46: + 663 0046 C046 .align 2 + 664 .L45: + 665 0048 00010B40 .word 1074462976 + 666 004c FF3FFFFF .word -49153 + 667 .cfi_endproc + 668 .LFE8: + 669 .size CySysWdtUnlock, .-CySysWdtUnlock + 670 .section .text.CySysWdtGetEnabledStatus,"ax",%progbits + 671 .align 2 + 672 .global CySysWdtGetEnabledStatus + 673 .code 16 + 674 .thumb_func + 675 .type CySysWdtGetEnabledStatus, %function + 676 CySysWdtGetEnabledStatus: + 677 .LFB9: + 997:Generated_Source\PSoC4/CyLFClk.c **** + 998:Generated_Source\PSoC4/CyLFClk.c **** + 999:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1000:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetEnabledStatus +1001:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1002:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1003:Generated_Source\PSoC4/CyLFClk.c **** * Reads the enabled status of one of the three WDT counters. +1004:Generated_Source\PSoC4/CyLFClk.c **** * +1005:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum: Valid range [0-2]. The number of the WDT counter. +1006:Generated_Source\PSoC4/CyLFClk.c **** * +1007:Generated_Source\PSoC4/CyLFClk.c **** * \return The status of the WDT counter: +1008:Generated_Source\PSoC4/CyLFClk.c **** * \return 0 - If the counter is disabled. +1009:Generated_Source\PSoC4/CyLFClk.c **** * \return 1 - If the counter is enabled. +1010:Generated_Source\PSoC4/CyLFClk.c **** * +1011:Generated_Source\PSoC4/CyLFClk.c **** * \details +1012:Generated_Source\PSoC4/CyLFClk.c **** * This function returns an actual WDT counter status from the status register. It may +1013:Generated_Source\PSoC4/CyLFClk.c **** * take up to 3 LFCLK cycles for the WDT status register to contain actual data +1014:Generated_Source\PSoC4/CyLFClk.c **** * after the WDT counter is enabled. +1015:Generated_Source\PSoC4/CyLFClk.c **** * +1016:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1017:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetEnabledStatus(uint32 counterNum) +1018:Generated_Source\PSoC4/CyLFClk.c **** { + 678 .loc 1 1018 0 + 679 .cfi_startproc + 680 @ args = 0, pretend = 0, frame = 8 + 681 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 31 + + + 682 0000 80B5 push {r7, lr} + 683 .cfi_def_cfa_offset 8 + 684 .cfi_offset 7, -8 + 685 .cfi_offset 14, -4 + 686 0002 82B0 sub sp, sp, #8 + 687 .cfi_def_cfa_offset 16 + 688 0004 00AF add r7, sp, #0 + 689 .cfi_def_cfa_register 7 + 690 0006 7860 str r0, [r7, #4] +1019:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + 691 .loc 1 1019 0 + 692 0008 7B68 ldr r3, [r7, #4] + 693 000a 022B cmp r3, #2 + 694 000c 02D9 bls .L48 + 695 .loc 1 1019 0 is_stmt 0 discriminator 1 + 696 000e 0020 movs r0, #0 + 697 0010 FFF7FEFF bl CyHalt + 698 .L48: +1020:Generated_Source\PSoC4/CyLFClk.c **** return ((CY_SYS_WDT_CONTROL_REG >> ((CY_SYS_WDT_CNT_SHIFT * counterNum) + CY_SYS_WDT_CNT_ST + 699 .loc 1 1020 0 is_stmt 1 + 700 0014 064B ldr r3, .L50 + 701 0016 1A68 ldr r2, [r3] + 702 0018 7B68 ldr r3, [r7, #4] + 703 001a DB00 lsls r3, r3, #3 + 704 001c 0133 adds r3, r3, #1 + 705 001e DA40 lsrs r2, r2, r3 + 706 0020 1300 movs r3, r2 + 707 0022 0122 movs r2, #1 + 708 0024 1340 ands r3, r2 +1021:Generated_Source\PSoC4/CyLFClk.c **** } + 709 .loc 1 1021 0 + 710 0026 1800 movs r0, r3 + 711 0028 BD46 mov sp, r7 + 712 002a 02B0 add sp, sp, #8 + 713 @ sp needed + 714 002c 80BD pop {r7, pc} + 715 .L51: + 716 002e C046 .align 2 + 717 .L50: + 718 0030 10020B40 .word 1074463248 + 719 .cfi_endproc + 720 .LFE9: + 721 .size CySysWdtGetEnabledStatus, .-CySysWdtGetEnabledStatus + 722 .section .text.CySysWdtSetMode,"ax",%progbits + 723 .align 2 + 724 .global CySysWdtSetMode + 725 .code 16 + 726 .thumb_func + 727 .type CySysWdtSetMode, %function + 728 CySysWdtSetMode: + 729 .LFB10: +1022:Generated_Source\PSoC4/CyLFClk.c **** +1023:Generated_Source\PSoC4/CyLFClk.c **** +1024:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1025:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetMode +1026:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1027:Generated_Source\PSoC4/CyLFClk.c **** * \brief + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 32 + + +1028:Generated_Source\PSoC4/CyLFClk.c **** * Writes the mode of one of the three WDT counters. +1029:Generated_Source\PSoC4/CyLFClk.c **** * +1030:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum: Valid range [0-2]. The number of the WDT counter. +1031:Generated_Source\PSoC4/CyLFClk.c **** * +1032:Generated_Source\PSoC4/CyLFClk.c **** * \param mode +1033:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_MODE_NONE - Free running.
+1034:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_MODE_INT - The interrupt generated on match for counter 0 +1035:Generated_Source\PSoC4/CyLFClk.c **** * and 1, and on bit toggle for counter 2.
+1036:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_MODE_RESET - Reset on match (valid for counter 0 and 1 only).
+1037:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_MODE_INT_RESET - Generate an interrupt. Generate a reset on +1038:Generated_Source\PSoC4/CyLFClk.c **** * the 3rd non-handled interrupt (valid for counter 0 and counter 1 only). +1039:Generated_Source\PSoC4/CyLFClk.c **** * +1040:Generated_Source\PSoC4/CyLFClk.c **** * \details +1041:Generated_Source\PSoC4/CyLFClk.c **** * WDT counter counterNum should be disabled to set a mode. Otherwise, this +1042:Generated_Source\PSoC4/CyLFClk.c **** * function call has no effect. If the specified counter is enabled, +1043:Generated_Source\PSoC4/CyLFClk.c **** * call the CySysWdtDisable() function with the corresponding parameter to +1044:Generated_Source\PSoC4/CyLFClk.c **** * disable the specified counter and wait for it to stop. +1045:Generated_Source\PSoC4/CyLFClk.c **** * +1046:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1047:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtSetMode(uint32 counterNum, uint32 mode) +1048:Generated_Source\PSoC4/CyLFClk.c **** { + 730 .loc 1 1048 0 + 731 .cfi_startproc + 732 @ args = 0, pretend = 0, frame = 16 + 733 @ frame_needed = 1, uses_anonymous_args = 0 + 734 0000 80B5 push {r7, lr} + 735 .cfi_def_cfa_offset 8 + 736 .cfi_offset 7, -8 + 737 .cfi_offset 14, -4 + 738 0002 84B0 sub sp, sp, #16 + 739 .cfi_def_cfa_offset 24 + 740 0004 00AF add r7, sp, #0 + 741 .cfi_def_cfa_register 7 + 742 0006 7860 str r0, [r7, #4] + 743 0008 3960 str r1, [r7] +1049:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; +1050:Generated_Source\PSoC4/CyLFClk.c **** +1051:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + 744 .loc 1 1051 0 + 745 000a 7B68 ldr r3, [r7, #4] + 746 000c 022B cmp r3, #2 + 747 000e 02D9 bls .L53 + 748 .loc 1 1051 0 is_stmt 0 discriminator 1 + 749 0010 0020 movs r0, #0 + 750 0012 FFF7FEFF bl CyHalt + 751 .L53: +1052:Generated_Source\PSoC4/CyLFClk.c **** +1053:Generated_Source\PSoC4/CyLFClk.c **** if(0u == CySysWdtGetEnabledStatus(counterNum)) + 752 .loc 1 1053 0 is_stmt 1 + 753 0016 7B68 ldr r3, [r7, #4] + 754 0018 1800 movs r0, r3 + 755 001a FFF7FEFF bl CySysWdtGetEnabledStatus + 756 001e 031E subs r3, r0, #0 + 757 0020 16D1 bne .L55 +1054:Generated_Source\PSoC4/CyLFClk.c **** { +1055:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WDT_CONFIG_REG & + 758 .loc 1 1055 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 33 + + + 759 0022 0D4B ldr r3, .L56 + 760 0024 1B68 ldr r3, [r3] +1056:Generated_Source\PSoC4/CyLFClk.c **** (uint32)~((uint32)(CY_SYS_WDT_MODE_MASK << (counterNum * CY_SYS_WDT + 761 .loc 1 1056 0 + 762 0026 7A68 ldr r2, [r7, #4] + 763 0028 D200 lsls r2, r2, #3 + 764 002a 0321 movs r1, #3 + 765 002c 9140 lsls r1, r1, r2 + 766 002e 0A00 movs r2, r1 + 767 0030 D243 mvns r2, r2 +1055:Generated_Source\PSoC4/CyLFClk.c **** (uint32)~((uint32)(CY_SYS_WDT_MODE_MASK << (counterNum * CY_SYS_WDT + 768 .loc 1 1055 0 + 769 0032 1340 ands r3, r2 + 770 0034 FB60 str r3, [r7, #12] +1057:Generated_Source\PSoC4/CyLFClk.c **** configRegValue |= (uint32)((mode & CY_SYS_WDT_MODE_MASK) << (counterNum * CY_SYS_WDT_CN + 771 .loc 1 1057 0 + 772 0036 3B68 ldr r3, [r7] + 773 0038 0322 movs r2, #3 + 774 003a 1A40 ands r2, r3 + 775 003c 7B68 ldr r3, [r7, #4] + 776 003e DB00 lsls r3, r3, #3 + 777 0040 9A40 lsls r2, r2, r3 + 778 0042 1300 movs r3, r2 + 779 0044 FA68 ldr r2, [r7, #12] + 780 0046 1343 orrs r3, r2 + 781 0048 FB60 str r3, [r7, #12] +1058:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONFIG_REG = configRegValue; + 782 .loc 1 1058 0 + 783 004a 034B ldr r3, .L56 + 784 004c FA68 ldr r2, [r7, #12] + 785 004e 1A60 str r2, [r3] + 786 .L55: +1059:Generated_Source\PSoC4/CyLFClk.c **** } +1060:Generated_Source\PSoC4/CyLFClk.c **** } + 787 .loc 1 1060 0 + 788 0050 C046 nop + 789 0052 BD46 mov sp, r7 + 790 0054 04B0 add sp, sp, #16 + 791 @ sp needed + 792 0056 80BD pop {r7, pc} + 793 .L57: + 794 .align 2 + 795 .L56: + 796 0058 0C020B40 .word 1074463244 + 797 .cfi_endproc + 798 .LFE10: + 799 .size CySysWdtSetMode, .-CySysWdtSetMode + 800 .section .text.CySysWdtGetMode,"ax",%progbits + 801 .align 2 + 802 .global CySysWdtGetMode + 803 .code 16 + 804 .thumb_func + 805 .type CySysWdtGetMode, %function + 806 CySysWdtGetMode: + 807 .LFB11: +1061:Generated_Source\PSoC4/CyLFClk.c **** +1062:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 34 + + +1063:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1064:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetMode +1065:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1066:Generated_Source\PSoC4/CyLFClk.c **** * +1067:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the mode of one of the three WDT counters. +1068:Generated_Source\PSoC4/CyLFClk.c **** * +1069:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-2]. The number of the WDT counter. +1070:Generated_Source\PSoC4/CyLFClk.c **** * +1071:Generated_Source\PSoC4/CyLFClk.c **** * \return The mode of the counter. The same enumerated values as the mode +1072:Generated_Source\PSoC4/CyLFClk.c **** * parameter used in CySysWdtSetMode(). +1073:Generated_Source\PSoC4/CyLFClk.c **** * +1074:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1075:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetMode(uint32 counterNum) +1076:Generated_Source\PSoC4/CyLFClk.c **** { + 808 .loc 1 1076 0 + 809 .cfi_startproc + 810 @ args = 0, pretend = 0, frame = 8 + 811 @ frame_needed = 1, uses_anonymous_args = 0 + 812 0000 80B5 push {r7, lr} + 813 .cfi_def_cfa_offset 8 + 814 .cfi_offset 7, -8 + 815 .cfi_offset 14, -4 + 816 0002 82B0 sub sp, sp, #8 + 817 .cfi_def_cfa_offset 16 + 818 0004 00AF add r7, sp, #0 + 819 .cfi_def_cfa_register 7 + 820 0006 7860 str r0, [r7, #4] +1077:Generated_Source\PSoC4/CyLFClk.c **** return ((CY_SYS_WDT_CONFIG_REG >> (counterNum * CY_SYS_WDT_CNT_SHIFT)) & CY_SYS_WDT_MODE_MA + 821 .loc 1 1077 0 + 822 0008 054B ldr r3, .L60 + 823 000a 1A68 ldr r2, [r3] + 824 000c 7B68 ldr r3, [r7, #4] + 825 000e DB00 lsls r3, r3, #3 + 826 0010 DA40 lsrs r2, r2, r3 + 827 0012 1300 movs r3, r2 + 828 0014 0322 movs r2, #3 + 829 0016 1340 ands r3, r2 +1078:Generated_Source\PSoC4/CyLFClk.c **** } + 830 .loc 1 1078 0 + 831 0018 1800 movs r0, r3 + 832 001a BD46 mov sp, r7 + 833 001c 02B0 add sp, sp, #8 + 834 @ sp needed + 835 001e 80BD pop {r7, pc} + 836 .L61: + 837 .align 2 + 838 .L60: + 839 0020 0C020B40 .word 1074463244 + 840 .cfi_endproc + 841 .LFE11: + 842 .size CySysWdtGetMode, .-CySysWdtGetMode + 843 .section .text.CySysWdtSetClearOnMatch,"ax",%progbits + 844 .align 2 + 845 .global CySysWdtSetClearOnMatch + 846 .code 16 + 847 .thumb_func + 848 .type CySysWdtSetClearOnMatch, %function + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 35 + + + 849 CySysWdtSetClearOnMatch: + 850 .LFB12: +1079:Generated_Source\PSoC4/CyLFClk.c **** +1080:Generated_Source\PSoC4/CyLFClk.c **** +1081:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1082:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetClearOnMatch +1083:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1084:Generated_Source\PSoC4/CyLFClk.c **** * +1085:Generated_Source\PSoC4/CyLFClk.c **** * \brief Configures the WDT counter "clear on match" setting. +1086:Generated_Source\PSoC4/CyLFClk.c **** * +1087:Generated_Source\PSoC4/CyLFClk.c **** * If configured to "clear on match", the counter counts from 0 to MatchValue +1088:Generated_Source\PSoC4/CyLFClk.c **** * giving it a period of (MatchValue + 1). +1089:Generated_Source\PSoC4/CyLFClk.c **** * +1090:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum +1091:Generated_Source\PSoC4/CyLFClk.c **** * Valid range [0-1]. The number of the WDT counter. The match values are not +1092:Generated_Source\PSoC4/CyLFClk.c **** * supported by counter 2. +1093:Generated_Source\PSoC4/CyLFClk.c **** * +1094:Generated_Source\PSoC4/CyLFClk.c **** * \param enable 0 to disable appropriate counter
+1095:Generated_Source\PSoC4/CyLFClk.c **** * 1 to enable appropriate counter +1096:Generated_Source\PSoC4/CyLFClk.c **** * +1097:Generated_Source\PSoC4/CyLFClk.c **** * \details +1098:Generated_Source\PSoC4/CyLFClk.c **** * WDT counter counterNum should be disabled. Otherwise this function call +1099:Generated_Source\PSoC4/CyLFClk.c **** * has no effect. If the specified counter is enabled, call the CySysWdtDisable() +1100:Generated_Source\PSoC4/CyLFClk.c **** * function with the corresponding parameter to disable the specified counter and +1101:Generated_Source\PSoC4/CyLFClk.c **** * wait for it to stop. This may take up to three LFCLK cycles. +1102:Generated_Source\PSoC4/CyLFClk.c **** * +1103:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1104:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtSetClearOnMatch(uint32 counterNum, uint32 enable) +1105:Generated_Source\PSoC4/CyLFClk.c **** { + 851 .loc 1 1105 0 + 852 .cfi_startproc + 853 @ args = 0, pretend = 0, frame = 16 + 854 @ frame_needed = 1, uses_anonymous_args = 0 + 855 0000 80B5 push {r7, lr} + 856 .cfi_def_cfa_offset 8 + 857 .cfi_offset 7, -8 + 858 .cfi_offset 14, -4 + 859 0002 84B0 sub sp, sp, #16 + 860 .cfi_def_cfa_offset 24 + 861 0004 00AF add r7, sp, #0 + 862 .cfi_def_cfa_register 7 + 863 0006 7860 str r0, [r7, #4] + 864 0008 3960 str r1, [r7] +1106:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; +1107:Generated_Source\PSoC4/CyLFClk.c **** +1108:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + 865 .loc 1 1108 0 + 866 000a 7B68 ldr r3, [r7, #4] + 867 000c 002B cmp r3, #0 + 868 000e 02D0 beq .L63 + 869 .loc 1 1108 0 is_stmt 0 discriminator 2 + 870 0010 7B68 ldr r3, [r7, #4] + 871 0012 012B cmp r3, #1 + 872 0014 01D1 bne .L64 + 873 .L63: + 874 .loc 1 1108 0 discriminator 3 + 875 0016 0123 movs r3, #1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 36 + + + 876 0018 00E0 b .L65 + 877 .L64: + 878 .loc 1 1108 0 discriminator 4 + 879 001a 0023 movs r3, #0 + 880 .L65: + 881 .loc 1 1108 0 discriminator 6 + 882 001c 002B cmp r3, #0 + 883 001e 02D1 bne .L66 + 884 .loc 1 1108 0 discriminator 7 + 885 0020 0020 movs r0, #0 + 886 0022 FFF7FEFF bl CyHalt + 887 .L66: +1109:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_WDT_COUNTER1)); +1110:Generated_Source\PSoC4/CyLFClk.c **** +1111:Generated_Source\PSoC4/CyLFClk.c **** if(0u == CySysWdtGetEnabledStatus(counterNum)) + 888 .loc 1 1111 0 is_stmt 1 + 889 0026 7B68 ldr r3, [r7, #4] + 890 0028 1800 movs r0, r3 + 891 002a FFF7FEFF bl CySysWdtGetEnabledStatus + 892 002e 031E subs r3, r0, #0 + 893 0030 16D1 bne .L68 +1112:Generated_Source\PSoC4/CyLFClk.c **** { +1113:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << + 894 .loc 1 1113 0 + 895 0032 0D4B ldr r3, .L69 + 896 0034 1B68 ldr r3, [r3] +1114:Generated_Source\PSoC4/CyLFClk.c **** ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CL + 897 .loc 1 1114 0 + 898 0036 7A68 ldr r2, [r7, #4] + 899 0038 D200 lsls r2, r2, #3 + 900 003a 0232 adds r2, r2, #2 +1113:Generated_Source\PSoC4/CyLFClk.c **** ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CL + 901 .loc 1 1113 0 + 902 003c 0121 movs r1, #1 + 903 003e 9140 lsls r1, r1, r2 + 904 0040 0A00 movs r2, r1 + 905 0042 D243 mvns r2, r2 + 906 0044 1340 ands r3, r2 + 907 0046 FB60 str r3, [r7, #12] +1115:Generated_Source\PSoC4/CyLFClk.c **** +1116:Generated_Source\PSoC4/CyLFClk.c **** configRegValue +1117:Generated_Source\PSoC4/CyLFClk.c **** |= (uint32)(enable << ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_C + 908 .loc 1 1117 0 + 909 0048 7B68 ldr r3, [r7, #4] + 910 004a DB00 lsls r3, r3, #3 + 911 004c 0233 adds r3, r3, #2 + 912 004e 3A68 ldr r2, [r7] + 913 0050 9A40 lsls r2, r2, r3 + 914 0052 1300 movs r3, r2 + 915 0054 FA68 ldr r2, [r7, #12] + 916 0056 1343 orrs r3, r2 + 917 0058 FB60 str r3, [r7, #12] +1118:Generated_Source\PSoC4/CyLFClk.c **** +1119:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONFIG_REG = configRegValue; + 918 .loc 1 1119 0 + 919 005a 034B ldr r3, .L69 + 920 005c FA68 ldr r2, [r7, #12] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 37 + + + 921 005e 1A60 str r2, [r3] + 922 .L68: +1120:Generated_Source\PSoC4/CyLFClk.c **** } +1121:Generated_Source\PSoC4/CyLFClk.c **** } + 923 .loc 1 1121 0 + 924 0060 C046 nop + 925 0062 BD46 mov sp, r7 + 926 0064 04B0 add sp, sp, #16 + 927 @ sp needed + 928 0066 80BD pop {r7, pc} + 929 .L70: + 930 .align 2 + 931 .L69: + 932 0068 0C020B40 .word 1074463244 + 933 .cfi_endproc + 934 .LFE12: + 935 .size CySysWdtSetClearOnMatch, .-CySysWdtSetClearOnMatch + 936 .section .text.CySysWdtGetClearOnMatch,"ax",%progbits + 937 .align 2 + 938 .global CySysWdtGetClearOnMatch + 939 .code 16 + 940 .thumb_func + 941 .type CySysWdtGetClearOnMatch, %function + 942 CySysWdtGetClearOnMatch: + 943 .LFB13: +1122:Generated_Source\PSoC4/CyLFClk.c **** +1123:Generated_Source\PSoC4/CyLFClk.c **** +1124:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1125:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetClearOnMatch +1126:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1127:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1128:Generated_Source\PSoC4/CyLFClk.c **** * Reads the "clear on match" setting for the specified counter. +1129:Generated_Source\PSoC4/CyLFClk.c **** * +1130:Generated_Source\PSoC4/CyLFClk.c **** * \param +1131:Generated_Source\PSoC4/CyLFClk.c **** * counterNum Valid range [0-1]. The number of the WDT counter. The match values +1132:Generated_Source\PSoC4/CyLFClk.c **** * are not supported by counter 2. +1133:Generated_Source\PSoC4/CyLFClk.c **** * +1134:Generated_Source\PSoC4/CyLFClk.c **** * \return The "clear on match" status:
1 if enabled
0 if disabled +1135:Generated_Source\PSoC4/CyLFClk.c **** * +1136:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1137:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetClearOnMatch(uint32 counterNum) +1138:Generated_Source\PSoC4/CyLFClk.c **** { + 944 .loc 1 1138 0 + 945 .cfi_startproc + 946 @ args = 0, pretend = 0, frame = 8 + 947 @ frame_needed = 1, uses_anonymous_args = 0 + 948 0000 80B5 push {r7, lr} + 949 .cfi_def_cfa_offset 8 + 950 .cfi_offset 7, -8 + 951 .cfi_offset 14, -4 + 952 0002 82B0 sub sp, sp, #8 + 953 .cfi_def_cfa_offset 16 + 954 0004 00AF add r7, sp, #0 + 955 .cfi_def_cfa_register 7 + 956 0006 7860 str r0, [r7, #4] +1139:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + 957 .loc 1 1139 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 38 + + + 958 0008 7B68 ldr r3, [r7, #4] + 959 000a 002B cmp r3, #0 + 960 000c 02D0 beq .L72 + 961 .loc 1 1139 0 is_stmt 0 discriminator 2 + 962 000e 7B68 ldr r3, [r7, #4] + 963 0010 012B cmp r3, #1 + 964 0012 01D1 bne .L73 + 965 .L72: + 966 .loc 1 1139 0 discriminator 3 + 967 0014 0123 movs r3, #1 + 968 0016 00E0 b .L74 + 969 .L73: + 970 .loc 1 1139 0 discriminator 4 + 971 0018 0023 movs r3, #0 + 972 .L74: + 973 .loc 1 1139 0 discriminator 6 + 974 001a 002B cmp r3, #0 + 975 001c 02D1 bne .L75 + 976 .loc 1 1139 0 discriminator 7 + 977 001e 0020 movs r0, #0 + 978 0020 FFF7FEFF bl CyHalt + 979 .L75: +1140:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_WDT_COUNTER1)); +1141:Generated_Source\PSoC4/CyLFClk.c **** +1142:Generated_Source\PSoC4/CyLFClk.c **** return (uint32)((CY_SYS_WDT_CONFIG_REG >> + 980 .loc 1 1142 0 is_stmt 1 + 981 0024 064B ldr r3, .L77 + 982 0026 1A68 ldr r2, [r3] +1143:Generated_Source\PSoC4/CyLFClk.c **** ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)) & 0 + 983 .loc 1 1143 0 + 984 0028 7B68 ldr r3, [r7, #4] + 985 002a DB00 lsls r3, r3, #3 + 986 002c 0233 adds r3, r3, #2 +1142:Generated_Source\PSoC4/CyLFClk.c **** ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)) & 0 + 987 .loc 1 1142 0 + 988 002e DA40 lsrs r2, r2, r3 + 989 0030 1300 movs r3, r2 + 990 0032 0122 movs r2, #1 + 991 0034 1340 ands r3, r2 +1144:Generated_Source\PSoC4/CyLFClk.c **** } + 992 .loc 1 1144 0 + 993 0036 1800 movs r0, r3 + 994 0038 BD46 mov sp, r7 + 995 003a 02B0 add sp, sp, #8 + 996 @ sp needed + 997 003c 80BD pop {r7, pc} + 998 .L78: + 999 003e C046 .align 2 + 1000 .L77: + 1001 0040 0C020B40 .word 1074463244 + 1002 .cfi_endproc + 1003 .LFE13: + 1004 .size CySysWdtGetClearOnMatch, .-CySysWdtGetClearOnMatch + 1005 .section .text.CySysWdtEnable,"ax",%progbits + 1006 .align 2 + 1007 .global CySysWdtEnable + 1008 .code 16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 39 + + + 1009 .thumb_func + 1010 .type CySysWdtEnable, %function + 1011 CySysWdtEnable: + 1012 .LFB14: +1145:Generated_Source\PSoC4/CyLFClk.c **** +1146:Generated_Source\PSoC4/CyLFClk.c **** +1147:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1148:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtEnable +1149:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1150:Generated_Source\PSoC4/CyLFClk.c **** * +1151:Generated_Source\PSoC4/CyLFClk.c **** * \brief Enables the specified WDT counters. +1152:Generated_Source\PSoC4/CyLFClk.c **** * +1153:Generated_Source\PSoC4/CyLFClk.c **** * All the counters specified in the mask are enabled. +1154:Generated_Source\PSoC4/CyLFClk.c **** * +1155:Generated_Source\PSoC4/CyLFClk.c **** * \param counterMask +1156:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to enable.
+1157:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to enable.
+1158:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to enable. +1159:Generated_Source\PSoC4/CyLFClk.c **** * +1160:Generated_Source\PSoC4/CyLFClk.c **** * \details +1161:Generated_Source\PSoC4/CyLFClk.c **** * Enabling or disabling WDT requires 3 LFCLK cycles to come into effect. +1162:Generated_Source\PSoC4/CyLFClk.c **** * Therefore, the WDT enable state must not be changed more than once in +1163:Generated_Source\PSoC4/CyLFClk.c **** * that period. +1164:Generated_Source\PSoC4/CyLFClk.c **** * +1165:Generated_Source\PSoC4/CyLFClk.c **** * After WDT is enabled, it is illegal to write WDT configuration (WDT_CONFIG) +1166:Generated_Source\PSoC4/CyLFClk.c **** * and control (WDT_CONTROL) registers. This means that all WDT functions that +1167:Generated_Source\PSoC4/CyLFClk.c **** * contain 'write' in the name (with the exception of CySysWdtSetMatch() +1168:Generated_Source\PSoC4/CyLFClk.c **** * function) are illegal to call if WDT is enabled. +1169:Generated_Source\PSoC4/CyLFClk.c **** * +1170:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4100 / PSoC 4200: This function enables ILO. +1171:Generated_Source\PSoC4/CyLFClk.c **** * +1172:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4100 BLE / PSoC 4200 BLE / PSoC4200L / PSoC 4100M +1173:Generated_Source\PSoC4/CyLFClk.c **** * / PSoC 4200M: +1174:Generated_Source\PSoC4/CyLFClk.c **** * LFLCK should be configured before calling this function. The desired +1175:Generated_Source\PSoC4/CyLFClk.c **** * source should be enabled and configured to be the source for LFCLK. +1176:Generated_Source\PSoC4/CyLFClk.c **** * +1177:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1178:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtEnable(uint32 counterMask) +1179:Generated_Source\PSoC4/CyLFClk.c **** { + 1013 .loc 1 1179 0 + 1014 .cfi_startproc + 1015 @ args = 0, pretend = 0, frame = 8 + 1016 @ frame_needed = 1, uses_anonymous_args = 0 + 1017 0000 80B5 push {r7, lr} + 1018 .cfi_def_cfa_offset 8 + 1019 .cfi_offset 7, -8 + 1020 .cfi_offset 14, -4 + 1021 0002 82B0 sub sp, sp, #8 + 1022 .cfi_def_cfa_offset 16 + 1023 0004 00AF add r7, sp, #0 + 1024 .cfi_def_cfa_register 7 + 1025 0006 7860 str r0, [r7, #4] +1180:Generated_Source\PSoC4/CyLFClk.c **** #if (!CY_IP_WCO) +1181:Generated_Source\PSoC4/CyLFClk.c **** CySysClkIloStart(); + 1026 .loc 1 1181 0 + 1027 0008 FFF7FEFF bl CySysClkIloStart +1182:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (!CY_IP_WCO) */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 40 + + +1183:Generated_Source\PSoC4/CyLFClk.c **** +1184:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONTROL_REG |= counterMask; + 1028 .loc 1 1184 0 + 1029 000c 144B ldr r3, .L87 + 1030 000e 144A ldr r2, .L87 + 1031 0010 1168 ldr r1, [r2] + 1032 0012 7A68 ldr r2, [r7, #4] + 1033 0014 0A43 orrs r2, r1 + 1034 0016 1A60 str r2, [r3] +1185:Generated_Source\PSoC4/CyLFClk.c **** +1186:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + 1035 .loc 1 1186 0 + 1036 0018 7B68 ldr r3, [r7, #4] + 1037 001a 0122 movs r2, #1 + 1038 001c 1340 ands r3, r2 + 1039 001e 05D0 beq .L80 +1187:Generated_Source\PSoC4/CyLFClk.c **** { +1188:Generated_Source\PSoC4/CyLFClk.c **** while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + 1040 .loc 1 1188 0 + 1041 0020 C046 nop + 1042 .L81: + 1043 .loc 1 1188 0 is_stmt 0 discriminator 1 + 1044 0022 0020 movs r0, #0 + 1045 0024 FFF7FEFF bl CySysWdtGetEnabledStatus + 1046 0028 031E subs r3, r0, #0 + 1047 002a FAD0 beq .L81 + 1048 .L80: +1189:Generated_Source\PSoC4/CyLFClk.c **** { +1190:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +1191:Generated_Source\PSoC4/CyLFClk.c **** } +1192:Generated_Source\PSoC4/CyLFClk.c **** } +1193:Generated_Source\PSoC4/CyLFClk.c **** +1194:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + 1049 .loc 1 1194 0 is_stmt 1 + 1050 002c 7A68 ldr r2, [r7, #4] + 1051 002e 8023 movs r3, #128 + 1052 0030 5B00 lsls r3, r3, #1 + 1053 0032 1340 ands r3, r2 + 1054 0034 05D0 beq .L82 +1195:Generated_Source\PSoC4/CyLFClk.c **** { +1196:Generated_Source\PSoC4/CyLFClk.c **** while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + 1055 .loc 1 1196 0 + 1056 0036 C046 nop + 1057 .L83: + 1058 .loc 1 1196 0 is_stmt 0 discriminator 1 + 1059 0038 0120 movs r0, #1 + 1060 003a FFF7FEFF bl CySysWdtGetEnabledStatus + 1061 003e 031E subs r3, r0, #0 + 1062 0040 FAD0 beq .L83 + 1063 .L82: +1197:Generated_Source\PSoC4/CyLFClk.c **** { +1198:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +1199:Generated_Source\PSoC4/CyLFClk.c **** } +1200:Generated_Source\PSoC4/CyLFClk.c **** } +1201:Generated_Source\PSoC4/CyLFClk.c **** +1202:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + 1064 .loc 1 1202 0 is_stmt 1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 41 + + + 1065 0042 7A68 ldr r2, [r7, #4] + 1066 0044 8023 movs r3, #128 + 1067 0046 5B02 lsls r3, r3, #9 + 1068 0048 1340 ands r3, r2 + 1069 004a 05D0 beq .L86 +1203:Generated_Source\PSoC4/CyLFClk.c **** { +1204:Generated_Source\PSoC4/CyLFClk.c **** while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + 1070 .loc 1 1204 0 + 1071 004c C046 nop + 1072 .L85: + 1073 .loc 1 1204 0 is_stmt 0 discriminator 1 + 1074 004e 0220 movs r0, #2 + 1075 0050 FFF7FEFF bl CySysWdtGetEnabledStatus + 1076 0054 031E subs r3, r0, #0 + 1077 0056 FAD0 beq .L85 + 1078 .L86: +1205:Generated_Source\PSoC4/CyLFClk.c **** { +1206:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +1207:Generated_Source\PSoC4/CyLFClk.c **** } +1208:Generated_Source\PSoC4/CyLFClk.c **** } +1209:Generated_Source\PSoC4/CyLFClk.c **** } + 1079 .loc 1 1209 0 is_stmt 1 + 1080 0058 C046 nop + 1081 005a BD46 mov sp, r7 + 1082 005c 02B0 add sp, sp, #8 + 1083 @ sp needed + 1084 005e 80BD pop {r7, pc} + 1085 .L88: + 1086 .align 2 + 1087 .L87: + 1088 0060 10020B40 .word 1074463248 + 1089 .cfi_endproc + 1090 .LFE14: + 1091 .size CySysWdtEnable, .-CySysWdtEnable + 1092 .section .text.CySysWdtDisable,"ax",%progbits + 1093 .align 2 + 1094 .global CySysWdtDisable + 1095 .code 16 + 1096 .thumb_func + 1097 .type CySysWdtDisable, %function + 1098 CySysWdtDisable: + 1099 .LFB15: +1210:Generated_Source\PSoC4/CyLFClk.c **** +1211:Generated_Source\PSoC4/CyLFClk.c **** +1212:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1213:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtDisable +1214:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1215:Generated_Source\PSoC4/CyLFClk.c **** * +1216:Generated_Source\PSoC4/CyLFClk.c **** * \brief Disables the specified WDT counters. +1217:Generated_Source\PSoC4/CyLFClk.c **** * All the counters specified in the mask are disabled. The function waits for +1218:Generated_Source\PSoC4/CyLFClk.c **** * the changes to come into effect. +1219:Generated_Source\PSoC4/CyLFClk.c **** * +1220:Generated_Source\PSoC4/CyLFClk.c **** * \param counterMask +1221:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to disable.
+1222:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to disable.
+1223:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to disable. +1224:Generated_Source\PSoC4/CyLFClk.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 42 + + +1225:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1226:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtDisable(uint32 counterMask) +1227:Generated_Source\PSoC4/CyLFClk.c **** { + 1100 .loc 1 1227 0 + 1101 .cfi_startproc + 1102 @ args = 0, pretend = 0, frame = 8 + 1103 @ frame_needed = 1, uses_anonymous_args = 0 + 1104 0000 80B5 push {r7, lr} + 1105 .cfi_def_cfa_offset 8 + 1106 .cfi_offset 7, -8 + 1107 .cfi_offset 14, -4 + 1108 0002 82B0 sub sp, sp, #8 + 1109 .cfi_def_cfa_offset 16 + 1110 0004 00AF add r7, sp, #0 + 1111 .cfi_def_cfa_register 7 + 1112 0006 7860 str r0, [r7, #4] +1228:Generated_Source\PSoC4/CyLFClk.c **** if (0uL == CySysWdtLocked()) + 1113 .loc 1 1228 0 + 1114 0008 FFF7FEFF bl CySysWdtLocked + 1115 000c 031E subs r3, r0, #0 + 1116 000e 26D1 bne .L96 +1229:Generated_Source\PSoC4/CyLFClk.c **** { +1230:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONTROL_REG &= ~counterMask; + 1117 .loc 1 1230 0 + 1118 0010 154B ldr r3, .L97 + 1119 0012 154A ldr r2, .L97 + 1120 0014 1268 ldr r2, [r2] + 1121 0016 7968 ldr r1, [r7, #4] + 1122 0018 C943 mvns r1, r1 + 1123 001a 0A40 ands r2, r1 + 1124 001c 1A60 str r2, [r3] +1231:Generated_Source\PSoC4/CyLFClk.c **** +1232:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + 1125 .loc 1 1232 0 + 1126 001e 7B68 ldr r3, [r7, #4] + 1127 0020 0122 movs r2, #1 + 1128 0022 1340 ands r3, r2 + 1129 0024 05D0 beq .L91 +1233:Generated_Source\PSoC4/CyLFClk.c **** { +1234:Generated_Source\PSoC4/CyLFClk.c **** while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + 1130 .loc 1 1234 0 + 1131 0026 C046 nop + 1132 .L92: + 1133 .loc 1 1234 0 is_stmt 0 discriminator 1 + 1134 0028 0020 movs r0, #0 + 1135 002a FFF7FEFF bl CySysWdtGetEnabledStatus + 1136 002e 031E subs r3, r0, #0 + 1137 0030 FAD1 bne .L92 + 1138 .L91: +1235:Generated_Source\PSoC4/CyLFClk.c **** { +1236:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +1237:Generated_Source\PSoC4/CyLFClk.c **** } +1238:Generated_Source\PSoC4/CyLFClk.c **** } +1239:Generated_Source\PSoC4/CyLFClk.c **** +1240:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + 1139 .loc 1 1240 0 is_stmt 1 + 1140 0032 7A68 ldr r2, [r7, #4] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 43 + + + 1141 0034 8023 movs r3, #128 + 1142 0036 5B00 lsls r3, r3, #1 + 1143 0038 1340 ands r3, r2 + 1144 003a 05D0 beq .L93 +1241:Generated_Source\PSoC4/CyLFClk.c **** { +1242:Generated_Source\PSoC4/CyLFClk.c **** while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + 1145 .loc 1 1242 0 + 1146 003c C046 nop + 1147 .L94: + 1148 .loc 1 1242 0 is_stmt 0 discriminator 1 + 1149 003e 0120 movs r0, #1 + 1150 0040 FFF7FEFF bl CySysWdtGetEnabledStatus + 1151 0044 031E subs r3, r0, #0 + 1152 0046 FAD1 bne .L94 + 1153 .L93: +1243:Generated_Source\PSoC4/CyLFClk.c **** { +1244:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +1245:Generated_Source\PSoC4/CyLFClk.c **** } +1246:Generated_Source\PSoC4/CyLFClk.c **** } +1247:Generated_Source\PSoC4/CyLFClk.c **** +1248:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + 1154 .loc 1 1248 0 is_stmt 1 + 1155 0048 7A68 ldr r2, [r7, #4] + 1156 004a 8023 movs r3, #128 + 1157 004c 5B02 lsls r3, r3, #9 + 1158 004e 1340 ands r3, r2 + 1159 0050 05D0 beq .L96 +1249:Generated_Source\PSoC4/CyLFClk.c **** { +1250:Generated_Source\PSoC4/CyLFClk.c **** while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + 1160 .loc 1 1250 0 + 1161 0052 C046 nop + 1162 .L95: + 1163 .loc 1 1250 0 is_stmt 0 discriminator 1 + 1164 0054 0220 movs r0, #2 + 1165 0056 FFF7FEFF bl CySysWdtGetEnabledStatus + 1166 005a 031E subs r3, r0, #0 + 1167 005c FAD1 bne .L95 + 1168 .L96: +1251:Generated_Source\PSoC4/CyLFClk.c **** { +1252:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +1253:Generated_Source\PSoC4/CyLFClk.c **** } +1254:Generated_Source\PSoC4/CyLFClk.c **** } +1255:Generated_Source\PSoC4/CyLFClk.c **** } +1256:Generated_Source\PSoC4/CyLFClk.c **** } + 1169 .loc 1 1256 0 is_stmt 1 + 1170 005e C046 nop + 1171 0060 BD46 mov sp, r7 + 1172 0062 02B0 add sp, sp, #8 + 1173 @ sp needed + 1174 0064 80BD pop {r7, pc} + 1175 .L98: + 1176 0066 C046 .align 2 + 1177 .L97: + 1178 0068 10020B40 .word 1074463248 + 1179 .cfi_endproc + 1180 .LFE15: + 1181 .size CySysWdtDisable, .-CySysWdtDisable + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 44 + + + 1182 .section .text.CySysWdtSetCascade,"ax",%progbits + 1183 .align 2 + 1184 .global CySysWdtSetCascade + 1185 .code 16 + 1186 .thumb_func + 1187 .type CySysWdtSetCascade, %function + 1188 CySysWdtSetCascade: + 1189 .LFB16: +1257:Generated_Source\PSoC4/CyLFClk.c **** +1258:Generated_Source\PSoC4/CyLFClk.c **** +1259:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1260:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetCascade +1261:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1262:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1263:Generated_Source\PSoC4/CyLFClk.c **** * Writes the two WDT cascade values based on the combination of mask values +1264:Generated_Source\PSoC4/CyLFClk.c **** * specified. +1265:Generated_Source\PSoC4/CyLFClk.c **** * +1266:Generated_Source\PSoC4/CyLFClk.c **** * \param cascadeMask The mask value used to set or clear the cascade values: +1267:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_CASCADE_NONE - Neither
+1268:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_CASCADE_01 - Cascade 01
+1269:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_CASCADE_12 - Cascade 12 +1270:Generated_Source\PSoC4/CyLFClk.c **** * +1271:Generated_Source\PSoC4/CyLFClk.c **** * If only one cascade mask is specified, the second cascade is disabled. +1272:Generated_Source\PSoC4/CyLFClk.c **** * To set both cascade modes, two defines should be ORed: +1273:Generated_Source\PSoC4/CyLFClk.c **** * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). +1274:Generated_Source\PSoC4/CyLFClk.c **** * \note If CySysWdtSetCascade() was called with ORed defines it is necessary +1275:Generated_Source\PSoC4/CyLFClk.c **** * to call CySysWdtSetClearOnMatch(1,1). It is needed to make sure that +1276:Generated_Source\PSoC4/CyLFClk.c **** * Counter 2 will be updated in the expected way. +1277:Generated_Source\PSoC4/CyLFClk.c **** * +1278:Generated_Source\PSoC4/CyLFClk.c **** * WDT counters that are part of the specified cascade should be disabled. +1279:Generated_Source\PSoC4/CyLFClk.c **** * Otherwise this function call has no effect. If the specified +1280:Generated_Source\PSoC4/CyLFClk.c **** * counter is enabled, call CySysWdtDisable() function with the corresponding +1281:Generated_Source\PSoC4/CyLFClk.c **** * parameter to disable the specified counter and wait for it to stop. This may +1282:Generated_Source\PSoC4/CyLFClk.c **** * take up to 3 LFCLK cycles. +1283:Generated_Source\PSoC4/CyLFClk.c **** * +1284:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1285:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtSetCascade(uint32 cascadeMask) +1286:Generated_Source\PSoC4/CyLFClk.c **** { + 1190 .loc 1 1286 0 + 1191 .cfi_startproc + 1192 @ args = 0, pretend = 0, frame = 16 + 1193 @ frame_needed = 1, uses_anonymous_args = 0 + 1194 0000 90B5 push {r4, r7, lr} + 1195 .cfi_def_cfa_offset 12 + 1196 .cfi_offset 4, -12 + 1197 .cfi_offset 7, -8 + 1198 .cfi_offset 14, -4 + 1199 0002 85B0 sub sp, sp, #20 + 1200 .cfi_def_cfa_offset 32 + 1201 0004 00AF add r7, sp, #0 + 1202 .cfi_def_cfa_register 7 + 1203 0006 7860 str r0, [r7, #4] +1287:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; +1288:Generated_Source\PSoC4/CyLFClk.c **** uint32 countersEnableStatus; +1289:Generated_Source\PSoC4/CyLFClk.c **** +1290:Generated_Source\PSoC4/CyLFClk.c **** countersEnableStatus = CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0) | + 1204 .loc 1 1290 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 45 + + + 1205 0008 0020 movs r0, #0 + 1206 000a FFF7FEFF bl CySysWdtGetEnabledStatus + 1207 000e 0400 movs r4, r0 +1291:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1) | + 1208 .loc 1 1291 0 + 1209 0010 0120 movs r0, #1 + 1210 0012 FFF7FEFF bl CySysWdtGetEnabledStatus + 1211 0016 0300 movs r3, r0 +1290:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1) | + 1212 .loc 1 1290 0 + 1213 0018 1C43 orrs r4, r3 +1292:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2); + 1214 .loc 1 1292 0 + 1215 001a 0220 movs r0, #2 + 1216 001c FFF7FEFF bl CySysWdtGetEnabledStatus + 1217 0020 0300 movs r3, r0 +1290:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1) | + 1218 .loc 1 1290 0 + 1219 0022 2343 orrs r3, r4 + 1220 0024 FB60 str r3, [r7, #12] +1293:Generated_Source\PSoC4/CyLFClk.c **** +1294:Generated_Source\PSoC4/CyLFClk.c **** if (0u == countersEnableStatus) + 1221 .loc 1 1294 0 + 1222 0026 FB68 ldr r3, [r7, #12] + 1223 0028 002B cmp r3, #0 + 1224 002a 0DD1 bne .L101 +1295:Generated_Source\PSoC4/CyLFClk.c **** { +1296:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WDT_CONFIG_REG; + 1225 .loc 1 1296 0 + 1226 002c 084B ldr r3, .L102 + 1227 002e 1B68 ldr r3, [r3] + 1228 0030 BB60 str r3, [r7, #8] +1297:Generated_Source\PSoC4/CyLFClk.c **** configRegValue &= ((uint32)(~(CY_SYS_WDT_CASCADE_01|CY_SYS_WDT_CASCADE_12))); + 1229 .loc 1 1297 0 + 1230 0032 BB68 ldr r3, [r7, #8] + 1231 0034 074A ldr r2, .L102+4 + 1232 0036 1340 ands r3, r2 + 1233 0038 BB60 str r3, [r7, #8] +1298:Generated_Source\PSoC4/CyLFClk.c **** configRegValue |= cascadeMask; + 1234 .loc 1 1298 0 + 1235 003a BA68 ldr r2, [r7, #8] + 1236 003c 7B68 ldr r3, [r7, #4] + 1237 003e 1343 orrs r3, r2 + 1238 0040 BB60 str r3, [r7, #8] +1299:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONFIG_REG = configRegValue; + 1239 .loc 1 1299 0 + 1240 0042 034B ldr r3, .L102 + 1241 0044 BA68 ldr r2, [r7, #8] + 1242 0046 1A60 str r2, [r3] + 1243 .L101: +1300:Generated_Source\PSoC4/CyLFClk.c **** } +1301:Generated_Source\PSoC4/CyLFClk.c **** } + 1244 .loc 1 1301 0 + 1245 0048 C046 nop + 1246 004a BD46 mov sp, r7 + 1247 004c 05B0 add sp, sp, #20 + 1248 @ sp needed + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 46 + + + 1249 004e 90BD pop {r4, r7, pc} + 1250 .L103: + 1251 .align 2 + 1252 .L102: + 1253 0050 0C020B40 .word 1074463244 + 1254 0054 F7F7FFFF .word -2057 + 1255 .cfi_endproc + 1256 .LFE16: + 1257 .size CySysWdtSetCascade, .-CySysWdtSetCascade + 1258 .section .text.CySysWdtGetCascade,"ax",%progbits + 1259 .align 2 + 1260 .global CySysWdtGetCascade + 1261 .code 16 + 1262 .thumb_func + 1263 .type CySysWdtGetCascade, %function + 1264 CySysWdtGetCascade: + 1265 .LFB17: +1302:Generated_Source\PSoC4/CyLFClk.c **** +1303:Generated_Source\PSoC4/CyLFClk.c **** +1304:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1305:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetCascade +1306:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1307:Generated_Source\PSoC4/CyLFClk.c **** * +1308:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the two WDT cascade values returning a mask of the bits set. +1309:Generated_Source\PSoC4/CyLFClk.c **** * +1310:Generated_Source\PSoC4/CyLFClk.c **** * \return The mask of the cascade values set. +1311:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_WDT_CASCADE_NONE - Neither +1312:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_WDT_CASCADE_01 - Cascade 01 +1313:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_WDT_CASCADE_12 - Cascade 12 +1314:Generated_Source\PSoC4/CyLFClk.c **** * +1315:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1316:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetCascade(void) +1317:Generated_Source\PSoC4/CyLFClk.c **** { + 1266 .loc 1 1317 0 + 1267 .cfi_startproc + 1268 @ args = 0, pretend = 0, frame = 0 + 1269 @ frame_needed = 1, uses_anonymous_args = 0 + 1270 0000 80B5 push {r7, lr} + 1271 .cfi_def_cfa_offset 8 + 1272 .cfi_offset 7, -8 + 1273 .cfi_offset 14, -4 + 1274 0002 00AF add r7, sp, #0 + 1275 .cfi_def_cfa_register 7 +1318:Generated_Source\PSoC4/CyLFClk.c **** return (CY_SYS_WDT_CONFIG_REG & (CY_SYS_WDT_CASCADE_01 | CY_SYS_WDT_CASCADE_12)); + 1276 .loc 1 1318 0 + 1277 0004 034B ldr r3, .L106 + 1278 0006 1B68 ldr r3, [r3] + 1279 0008 034A ldr r2, .L106+4 + 1280 000a 1340 ands r3, r2 +1319:Generated_Source\PSoC4/CyLFClk.c **** } + 1281 .loc 1 1319 0 + 1282 000c 1800 movs r0, r3 + 1283 000e BD46 mov sp, r7 + 1284 @ sp needed + 1285 0010 80BD pop {r7, pc} + 1286 .L107: + 1287 0012 C046 .align 2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 47 + + + 1288 .L106: + 1289 0014 0C020B40 .word 1074463244 + 1290 0018 08080000 .word 2056 + 1291 .cfi_endproc + 1292 .LFE17: + 1293 .size CySysWdtGetCascade, .-CySysWdtGetCascade + 1294 .section .text.CySysWdtSetMatch,"ax",%progbits + 1295 .align 2 + 1296 .global CySysWdtSetMatch + 1297 .code 16 + 1298 .thumb_func + 1299 .type CySysWdtSetMatch, %function + 1300 CySysWdtSetMatch: + 1301 .LFB18: +1320:Generated_Source\PSoC4/CyLFClk.c **** +1321:Generated_Source\PSoC4/CyLFClk.c **** +1322:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1323:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetMatch +1324:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1325:Generated_Source\PSoC4/CyLFClk.c **** * +1326:Generated_Source\PSoC4/CyLFClk.c **** * \brief Configures the WDT counter match comparison value. +1327:Generated_Source\PSoC4/CyLFClk.c **** * +1328:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum +1329:Generated_Source\PSoC4/CyLFClk.c **** * Valid range [0-1]. The number of the WDT counter. The match values are not +1330:Generated_Source\PSoC4/CyLFClk.c **** * supported by counter 2. +1331:Generated_Source\PSoC4/CyLFClk.c **** * +1332:Generated_Source\PSoC4/CyLFClk.c **** * \param match +1333:Generated_Source\PSoC4/CyLFClk.c **** * Valid range [0-65535]. The value to be used to match against the counter. +1334:Generated_Source\PSoC4/CyLFClk.c **** * +1335:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1336:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtSetMatch(uint32 counterNum, uint32 match) +1337:Generated_Source\PSoC4/CyLFClk.c **** { + 1302 .loc 1 1337 0 + 1303 .cfi_startproc + 1304 @ args = 0, pretend = 0, frame = 16 + 1305 @ frame_needed = 1, uses_anonymous_args = 0 + 1306 0000 80B5 push {r7, lr} + 1307 .cfi_def_cfa_offset 8 + 1308 .cfi_offset 7, -8 + 1309 .cfi_offset 14, -4 + 1310 0002 84B0 sub sp, sp, #16 + 1311 .cfi_def_cfa_offset 24 + 1312 0004 00AF add r7, sp, #0 + 1313 .cfi_def_cfa_register 7 + 1314 0006 7860 str r0, [r7, #4] + 1315 0008 3960 str r1, [r7] +1338:Generated_Source\PSoC4/CyLFClk.c **** uint32 regValue; +1339:Generated_Source\PSoC4/CyLFClk.c **** +1340:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + 1316 .loc 1 1340 0 + 1317 000a 7B68 ldr r3, [r7, #4] + 1318 000c 002B cmp r3, #0 + 1319 000e 02D0 beq .L109 + 1320 .loc 1 1340 0 is_stmt 0 discriminator 2 + 1321 0010 7B68 ldr r3, [r7, #4] + 1322 0012 012B cmp r3, #1 + 1323 0014 01D1 bne .L110 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 48 + + + 1324 .L109: + 1325 .loc 1 1340 0 discriminator 3 + 1326 0016 0123 movs r3, #1 + 1327 0018 00E0 b .L111 + 1328 .L110: + 1329 .loc 1 1340 0 discriminator 4 + 1330 001a 0023 movs r3, #0 + 1331 .L111: + 1332 .loc 1 1340 0 discriminator 6 + 1333 001c 002B cmp r3, #0 + 1334 001e 02D1 bne .L112 + 1335 .loc 1 1340 0 discriminator 7 + 1336 0020 0020 movs r0, #0 + 1337 0022 FFF7FEFF bl CyHalt + 1338 .L112: +1341:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_WDT_COUNTER1)); +1342:Generated_Source\PSoC4/CyLFClk.c **** +1343:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for previous changes to come into effect */ +1344:Generated_Source\PSoC4/CyLFClk.c **** CyDelayUs(CY_SYS_WDT_3LFCLK_DELAY_US); + 1339 .loc 1 1344 0 is_stmt 1 + 1340 0026 C920 movs r0, #201 + 1341 0028 FFF7FEFF bl CyDelayUs +1345:Generated_Source\PSoC4/CyLFClk.c **** +1346:Generated_Source\PSoC4/CyLFClk.c **** regValue = CY_SYS_WDT_MATCH_REG; + 1342 .loc 1 1346 0 + 1343 002c 0D4B ldr r3, .L113 + 1344 002e 1B68 ldr r3, [r3] + 1345 0030 FB60 str r3, [r7, #12] +1347:Generated_Source\PSoC4/CyLFClk.c **** regValue &= (uint32)~((uint32)(CY_SYS_WDT_LOWER_16BITS_MASK << (counterNum * CY_SYS_WDT_CNT + 1346 .loc 1 1347 0 + 1347 0032 7B68 ldr r3, [r7, #4] + 1348 0034 1B01 lsls r3, r3, #4 + 1349 0036 0C4A ldr r2, .L113+4 + 1350 0038 9A40 lsls r2, r2, r3 + 1351 003a 1300 movs r3, r2 + 1352 003c DA43 mvns r2, r3 + 1353 003e FB68 ldr r3, [r7, #12] + 1354 0040 1340 ands r3, r2 + 1355 0042 FB60 str r3, [r7, #12] +1348:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT))); + 1356 .loc 1 1348 0 + 1357 0044 074B ldr r3, .L113 + 1358 0046 7A68 ldr r2, [r7, #4] + 1359 0048 1201 lsls r2, r2, #4 + 1360 004a 3968 ldr r1, [r7] + 1361 004c 9140 lsls r1, r1, r2 + 1362 004e FA68 ldr r2, [r7, #12] + 1363 0050 0A43 orrs r2, r1 + 1364 0052 1A60 str r2, [r3] +1349:Generated_Source\PSoC4/CyLFClk.c **** +1350:Generated_Source\PSoC4/CyLFClk.c **** /* Make sure match synchronization has started */ +1351:Generated_Source\PSoC4/CyLFClk.c **** CyDelayUs(CY_SYS_WDT_1LFCLK_DELAY_US); + 1365 .loc 1 1351 0 + 1366 0054 4320 movs r0, #67 + 1367 0056 FFF7FEFF bl CyDelayUs +1352:Generated_Source\PSoC4/CyLFClk.c **** } + 1368 .loc 1 1352 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 49 + + + 1369 005a C046 nop + 1370 005c BD46 mov sp, r7 + 1371 005e 04B0 add sp, sp, #16 + 1372 @ sp needed + 1373 0060 80BD pop {r7, pc} + 1374 .L114: + 1375 0062 C046 .align 2 + 1376 .L113: + 1377 0064 08020B40 .word 1074463240 + 1378 0068 FFFF0000 .word 65535 + 1379 .cfi_endproc + 1380 .LFE18: + 1381 .size CySysWdtSetMatch, .-CySysWdtSetMatch + 1382 .section .text.CySysWdtSetToggleBit,"ax",%progbits + 1383 .align 2 + 1384 .global CySysWdtSetToggleBit + 1385 .code 16 + 1386 .thumb_func + 1387 .type CySysWdtSetToggleBit, %function + 1388 CySysWdtSetToggleBit: + 1389 .LFB19: +1353:Generated_Source\PSoC4/CyLFClk.c **** +1354:Generated_Source\PSoC4/CyLFClk.c **** +1355:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1356:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetToggleBit +1357:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1358:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1359:Generated_Source\PSoC4/CyLFClk.c **** * Configures which bit in WDT counter 2 to monitor for a toggle. +1360:Generated_Source\PSoC4/CyLFClk.c **** * +1361:Generated_Source\PSoC4/CyLFClk.c **** * When that bit toggles, an interrupt is generated if the mode for counter 2 has +1362:Generated_Source\PSoC4/CyLFClk.c **** * enabled interrupts. +1363:Generated_Source\PSoC4/CyLFClk.c **** * +1364:Generated_Source\PSoC4/CyLFClk.c **** * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. +1365:Generated_Source\PSoC4/CyLFClk.c **** * +1366:Generated_Source\PSoC4/CyLFClk.c **** * \details +1367:Generated_Source\PSoC4/CyLFClk.c **** * WDT Counter 2 should be disabled. Otherwise this function call has no +1368:Generated_Source\PSoC4/CyLFClk.c **** * effect. +1369:Generated_Source\PSoC4/CyLFClk.c **** * +1370:Generated_Source\PSoC4/CyLFClk.c **** * If the specified counter is enabled, call the CySysWdtDisable() function with +1371:Generated_Source\PSoC4/CyLFClk.c **** * the corresponding parameter to disable the specified counter and wait for it to +1372:Generated_Source\PSoC4/CyLFClk.c **** * stop. This may take up to 3 LFCLK cycles. +1373:Generated_Source\PSoC4/CyLFClk.c **** * +1374:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1375:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtSetToggleBit(uint32 bits) +1376:Generated_Source\PSoC4/CyLFClk.c **** { + 1390 .loc 1 1376 0 + 1391 .cfi_startproc + 1392 @ args = 0, pretend = 0, frame = 16 + 1393 @ frame_needed = 1, uses_anonymous_args = 0 + 1394 0000 80B5 push {r7, lr} + 1395 .cfi_def_cfa_offset 8 + 1396 .cfi_offset 7, -8 + 1397 .cfi_offset 14, -4 + 1398 0002 84B0 sub sp, sp, #16 + 1399 .cfi_def_cfa_offset 24 + 1400 0004 00AF add r7, sp, #0 + 1401 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 50 + + + 1402 0006 7860 str r0, [r7, #4] +1377:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; +1378:Generated_Source\PSoC4/CyLFClk.c **** +1379:Generated_Source\PSoC4/CyLFClk.c **** if (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + 1403 .loc 1 1379 0 + 1404 0008 0220 movs r0, #2 + 1405 000a FFF7FEFF bl CySysWdtGetEnabledStatus + 1406 000e 031E subs r3, r0, #0 + 1407 0010 11D1 bne .L117 +1380:Generated_Source\PSoC4/CyLFClk.c **** { +1381:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WDT_CONFIG_REG; + 1408 .loc 1 1381 0 + 1409 0012 0B4B ldr r3, .L118 + 1410 0014 1B68 ldr r3, [r3] + 1411 0016 FB60 str r3, [r7, #12] +1382:Generated_Source\PSoC4/CyLFClk.c **** configRegValue &= (uint32)(~((uint32)(CY_SYS_WDT_CONFIG_BITS2_MASK << CY_SYS_WDT_CONFIG + 1412 .loc 1 1382 0 + 1413 0018 FB68 ldr r3, [r7, #12] + 1414 001a 0A4A ldr r2, .L118+4 + 1415 001c 1340 ands r3, r2 + 1416 001e FB60 str r3, [r7, #12] +1383:Generated_Source\PSoC4/CyLFClk.c **** configRegValue |= ((bits & CY_SYS_WDT_CONFIG_BITS2_MASK) << CY_SYS_WDT_CONFIG_BITS2_POS + 1417 .loc 1 1383 0 + 1418 0020 7B68 ldr r3, [r7, #4] + 1419 0022 1A06 lsls r2, r3, #24 + 1420 0024 F823 movs r3, #248 + 1421 0026 5B05 lsls r3, r3, #21 + 1422 0028 1340 ands r3, r2 + 1423 002a FA68 ldr r2, [r7, #12] + 1424 002c 1343 orrs r3, r2 + 1425 002e FB60 str r3, [r7, #12] +1384:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONFIG_REG = configRegValue; + 1426 .loc 1 1384 0 + 1427 0030 034B ldr r3, .L118 + 1428 0032 FA68 ldr r2, [r7, #12] + 1429 0034 1A60 str r2, [r3] + 1430 .L117: +1385:Generated_Source\PSoC4/CyLFClk.c **** } +1386:Generated_Source\PSoC4/CyLFClk.c **** } + 1431 .loc 1 1386 0 + 1432 0036 C046 nop + 1433 0038 BD46 mov sp, r7 + 1434 003a 04B0 add sp, sp, #16 + 1435 @ sp needed + 1436 003c 80BD pop {r7, pc} + 1437 .L119: + 1438 003e C046 .align 2 + 1439 .L118: + 1440 0040 0C020B40 .word 1074463244 + 1441 0044 FFFFFFE0 .word -520093697 + 1442 .cfi_endproc + 1443 .LFE19: + 1444 .size CySysWdtSetToggleBit, .-CySysWdtSetToggleBit + 1445 .section .text.CySysWdtGetToggleBit,"ax",%progbits + 1446 .align 2 + 1447 .global CySysWdtGetToggleBit + 1448 .code 16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 51 + + + 1449 .thumb_func + 1450 .type CySysWdtGetToggleBit, %function + 1451 CySysWdtGetToggleBit: + 1452 .LFB20: +1387:Generated_Source\PSoC4/CyLFClk.c **** +1388:Generated_Source\PSoC4/CyLFClk.c **** +1389:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1390:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetToggleBit +1391:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1392:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1393:Generated_Source\PSoC4/CyLFClk.c **** * Reads which bit in WDT counter 2 is monitored for a toggle. +1394:Generated_Source\PSoC4/CyLFClk.c **** * +1395:Generated_Source\PSoC4/CyLFClk.c **** * \return The bit that is monitored (range of 0 to 31) +1396:Generated_Source\PSoC4/CyLFClk.c **** * +1397:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1398:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetToggleBit(void) +1399:Generated_Source\PSoC4/CyLFClk.c **** { + 1453 .loc 1 1399 0 + 1454 .cfi_startproc + 1455 @ args = 0, pretend = 0, frame = 0 + 1456 @ frame_needed = 1, uses_anonymous_args = 0 + 1457 0000 80B5 push {r7, lr} + 1458 .cfi_def_cfa_offset 8 + 1459 .cfi_offset 7, -8 + 1460 .cfi_offset 14, -4 + 1461 0002 00AF add r7, sp, #0 + 1462 .cfi_def_cfa_register 7 +1400:Generated_Source\PSoC4/CyLFClk.c **** return ((CY_SYS_WDT_CONFIG_REG >> CY_SYS_WDT_CONFIG_BITS2_POS) & CY_SYS_WDT_CONFIG_BITS2_MA + 1463 .loc 1 1400 0 + 1464 0004 034B ldr r3, .L122 + 1465 0006 1B68 ldr r3, [r3] + 1466 0008 1B0E lsrs r3, r3, #24 + 1467 000a 1F22 movs r2, #31 + 1468 000c 1340 ands r3, r2 +1401:Generated_Source\PSoC4/CyLFClk.c **** } + 1469 .loc 1 1401 0 + 1470 000e 1800 movs r0, r3 + 1471 0010 BD46 mov sp, r7 + 1472 @ sp needed + 1473 0012 80BD pop {r7, pc} + 1474 .L123: + 1475 .align 2 + 1476 .L122: + 1477 0014 0C020B40 .word 1074463244 + 1478 .cfi_endproc + 1479 .LFE20: + 1480 .size CySysWdtGetToggleBit, .-CySysWdtGetToggleBit + 1481 .section .text.CySysWdtGetMatch,"ax",%progbits + 1482 .align 2 + 1483 .global CySysWdtGetMatch + 1484 .code 16 + 1485 .thumb_func + 1486 .type CySysWdtGetMatch, %function + 1487 CySysWdtGetMatch: + 1488 .LFB21: +1402:Generated_Source\PSoC4/CyLFClk.c **** +1403:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 52 + + +1404:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1405:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetMatch +1406:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1407:Generated_Source\PSoC4/CyLFClk.c **** * +1408:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the WDT counter match comparison value. +1409:Generated_Source\PSoC4/CyLFClk.c **** * +1410:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-1]. The number of the WDT counter. The match +1411:Generated_Source\PSoC4/CyLFClk.c **** * values are not supported by counter 2. +1412:Generated_Source\PSoC4/CyLFClk.c **** * +1413:Generated_Source\PSoC4/CyLFClk.c **** * \return A 16-bit match value. +1414:Generated_Source\PSoC4/CyLFClk.c **** * +1415:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1416:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetMatch(uint32 counterNum) +1417:Generated_Source\PSoC4/CyLFClk.c **** { + 1489 .loc 1 1417 0 + 1490 .cfi_startproc + 1491 @ args = 0, pretend = 0, frame = 8 + 1492 @ frame_needed = 1, uses_anonymous_args = 0 + 1493 0000 80B5 push {r7, lr} + 1494 .cfi_def_cfa_offset 8 + 1495 .cfi_offset 7, -8 + 1496 .cfi_offset 14, -4 + 1497 0002 82B0 sub sp, sp, #8 + 1498 .cfi_def_cfa_offset 16 + 1499 0004 00AF add r7, sp, #0 + 1500 .cfi_def_cfa_register 7 + 1501 0006 7860 str r0, [r7, #4] +1418:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + 1502 .loc 1 1418 0 + 1503 0008 7B68 ldr r3, [r7, #4] + 1504 000a 002B cmp r3, #0 + 1505 000c 02D0 beq .L125 + 1506 .loc 1 1418 0 is_stmt 0 discriminator 2 + 1507 000e 7B68 ldr r3, [r7, #4] + 1508 0010 012B cmp r3, #1 + 1509 0012 01D1 bne .L126 + 1510 .L125: + 1511 .loc 1 1418 0 discriminator 3 + 1512 0014 0123 movs r3, #1 + 1513 0016 00E0 b .L127 + 1514 .L126: + 1515 .loc 1 1418 0 discriminator 4 + 1516 0018 0023 movs r3, #0 + 1517 .L127: + 1518 .loc 1 1418 0 discriminator 6 + 1519 001a 002B cmp r3, #0 + 1520 001c 02D1 bne .L128 + 1521 .loc 1 1418 0 discriminator 7 + 1522 001e 0020 movs r0, #0 + 1523 0020 FFF7FEFF bl CyHalt + 1524 .L128: +1419:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_WDT_COUNTER1)); +1420:Generated_Source\PSoC4/CyLFClk.c **** +1421:Generated_Source\PSoC4/CyLFClk.c **** return ((uint32)(CY_SYS_WDT_MATCH_REG >> + 1525 .loc 1 1421 0 is_stmt 1 + 1526 0024 054B ldr r3, .L130 + 1527 0026 1A68 ldr r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 53 + + +1422:Generated_Source\PSoC4/CyLFClk.c **** (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT)) & CY_SYS_WDT + 1528 .loc 1 1422 0 + 1529 0028 7B68 ldr r3, [r7, #4] + 1530 002a 1B01 lsls r3, r3, #4 +1421:Generated_Source\PSoC4/CyLFClk.c **** (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT)) & CY_SYS_WDT + 1531 .loc 1 1421 0 + 1532 002c DA40 lsrs r2, r2, r3 + 1533 002e 1300 movs r3, r2 + 1534 0030 1B04 lsls r3, r3, #16 + 1535 0032 1B0C lsrs r3, r3, #16 +1423:Generated_Source\PSoC4/CyLFClk.c **** } + 1536 .loc 1 1423 0 + 1537 0034 1800 movs r0, r3 + 1538 0036 BD46 mov sp, r7 + 1539 0038 02B0 add sp, sp, #8 + 1540 @ sp needed + 1541 003a 80BD pop {r7, pc} + 1542 .L131: + 1543 .align 2 + 1544 .L130: + 1545 003c 08020B40 .word 1074463240 + 1546 .cfi_endproc + 1547 .LFE21: + 1548 .size CySysWdtGetMatch, .-CySysWdtGetMatch + 1549 .section .text.CySysWdtGetCount,"ax",%progbits + 1550 .align 2 + 1551 .global CySysWdtGetCount + 1552 .code 16 + 1553 .thumb_func + 1554 .type CySysWdtGetCount, %function + 1555 CySysWdtGetCount: + 1556 .LFB22: +1424:Generated_Source\PSoC4/CyLFClk.c **** +1425:Generated_Source\PSoC4/CyLFClk.c **** +1426:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1427:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetCount +1428:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1429:Generated_Source\PSoC4/CyLFClk.c **** * +1430:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the current WDT counter value. +1431:Generated_Source\PSoC4/CyLFClk.c **** * +1432:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum: Valid range [0-2]. The number of the WDT counter. +1433:Generated_Source\PSoC4/CyLFClk.c **** * +1434:Generated_Source\PSoC4/CyLFClk.c **** * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters +1435:Generated_Source\PSoC4/CyLFClk.c **** * and counter 2 is a 32 bit counter. +1436:Generated_Source\PSoC4/CyLFClk.c **** * +1437:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1438:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetCount(uint32 counterNum) +1439:Generated_Source\PSoC4/CyLFClk.c **** { + 1557 .loc 1 1439 0 + 1558 .cfi_startproc + 1559 @ args = 0, pretend = 0, frame = 16 + 1560 @ frame_needed = 1, uses_anonymous_args = 0 + 1561 0000 80B5 push {r7, lr} + 1562 .cfi_def_cfa_offset 8 + 1563 .cfi_offset 7, -8 + 1564 .cfi_offset 14, -4 + 1565 0002 84B0 sub sp, sp, #16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 54 + + + 1566 .cfi_def_cfa_offset 24 + 1567 0004 00AF add r7, sp, #0 + 1568 .cfi_def_cfa_register 7 + 1569 0006 7860 str r0, [r7, #4] +1440:Generated_Source\PSoC4/CyLFClk.c **** uint32 regValue = 0u; + 1570 .loc 1 1440 0 + 1571 0008 0023 movs r3, #0 + 1572 000a FB60 str r3, [r7, #12] +1441:Generated_Source\PSoC4/CyLFClk.c **** +1442:Generated_Source\PSoC4/CyLFClk.c **** switch(counterNum) + 1573 .loc 1 1442 0 + 1574 000c 7B68 ldr r3, [r7, #4] + 1575 000e 012B cmp r3, #1 + 1576 0010 09D0 beq .L134 + 1577 0012 02D3 bcc .L135 + 1578 0014 022B cmp r3, #2 + 1579 0016 0BD0 beq .L136 + 1580 0018 0EE0 b .L139 + 1581 .L135: +1443:Generated_Source\PSoC4/CyLFClk.c **** { +1444:Generated_Source\PSoC4/CyLFClk.c **** /* WDT Counter 0 */ +1445:Generated_Source\PSoC4/CyLFClk.c **** case 0u: +1446:Generated_Source\PSoC4/CyLFClk.c **** regValue = CY_SYS_WDT_CTRLOW_REG & CY_SYS_WDT_LOWER_16BITS_MASK; + 1582 .loc 1 1446 0 + 1583 001a 0C4B ldr r3, .L140 + 1584 001c 1B68 ldr r3, [r3] + 1585 001e 1B04 lsls r3, r3, #16 + 1586 0020 1B0C lsrs r3, r3, #16 + 1587 0022 FB60 str r3, [r7, #12] +1447:Generated_Source\PSoC4/CyLFClk.c **** break; + 1588 .loc 1 1447 0 + 1589 0024 0CE0 b .L137 + 1590 .L134: +1448:Generated_Source\PSoC4/CyLFClk.c **** +1449:Generated_Source\PSoC4/CyLFClk.c **** /* WDT Counter 1 */ +1450:Generated_Source\PSoC4/CyLFClk.c **** case 1u: +1451:Generated_Source\PSoC4/CyLFClk.c **** regValue = (CY_SYS_WDT_CTRLOW_REG >> CY_SYS_WDT_CNT_MATCH_SHIFT) & CY_SYS_WDT_LOWER + 1591 .loc 1 1451 0 + 1592 0026 094B ldr r3, .L140 + 1593 0028 1B68 ldr r3, [r3] + 1594 002a 1B0C lsrs r3, r3, #16 + 1595 002c FB60 str r3, [r7, #12] +1452:Generated_Source\PSoC4/CyLFClk.c **** break; + 1596 .loc 1 1452 0 + 1597 002e 07E0 b .L137 + 1598 .L136: +1453:Generated_Source\PSoC4/CyLFClk.c **** +1454:Generated_Source\PSoC4/CyLFClk.c **** /* WDT Counter 2 */ +1455:Generated_Source\PSoC4/CyLFClk.c **** case 2u: +1456:Generated_Source\PSoC4/CyLFClk.c **** regValue = CY_SYS_WDT_CTRHIGH_REG; + 1599 .loc 1 1456 0 + 1600 0030 074B ldr r3, .L140+4 + 1601 0032 1B68 ldr r3, [r3] + 1602 0034 FB60 str r3, [r7, #12] +1457:Generated_Source\PSoC4/CyLFClk.c **** break; + 1603 .loc 1 1457 0 + 1604 0036 03E0 b .L137 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 55 + + + 1605 .L139: +1458:Generated_Source\PSoC4/CyLFClk.c **** +1459:Generated_Source\PSoC4/CyLFClk.c **** default: +1460:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); + 1606 .loc 1 1460 0 + 1607 0038 0020 movs r0, #0 + 1608 003a FFF7FEFF bl CyHalt +1461:Generated_Source\PSoC4/CyLFClk.c **** break; + 1609 .loc 1 1461 0 + 1610 003e C046 nop + 1611 .L137: +1462:Generated_Source\PSoC4/CyLFClk.c **** } +1463:Generated_Source\PSoC4/CyLFClk.c **** +1464:Generated_Source\PSoC4/CyLFClk.c **** return (regValue); + 1612 .loc 1 1464 0 + 1613 0040 FB68 ldr r3, [r7, #12] +1465:Generated_Source\PSoC4/CyLFClk.c **** } + 1614 .loc 1 1465 0 + 1615 0042 1800 movs r0, r3 + 1616 0044 BD46 mov sp, r7 + 1617 0046 04B0 add sp, sp, #16 + 1618 @ sp needed + 1619 0048 80BD pop {r7, pc} + 1620 .L141: + 1621 004a C046 .align 2 + 1622 .L140: + 1623 004c 00020B40 .word 1074463232 + 1624 0050 04020B40 .word 1074463236 + 1625 .cfi_endproc + 1626 .LFE22: + 1627 .size CySysWdtGetCount, .-CySysWdtGetCount + 1628 .section .text.CySysWdtGetInterruptSource,"ax",%progbits + 1629 .align 2 + 1630 .global CySysWdtGetInterruptSource + 1631 .code 16 + 1632 .thumb_func + 1633 .type CySysWdtGetInterruptSource, %function + 1634 CySysWdtGetInterruptSource: + 1635 .LFB23: +1466:Generated_Source\PSoC4/CyLFClk.c **** +1467:Generated_Source\PSoC4/CyLFClk.c **** +1468:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1469:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetInterruptSource +1470:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1471:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1472:Generated_Source\PSoC4/CyLFClk.c **** * Reads a mask containing all the WDT counters interrupts that are currently +1473:Generated_Source\PSoC4/CyLFClk.c **** * set by the hardware, if a corresponding mode is selected. +1474:Generated_Source\PSoC4/CyLFClk.c **** * +1475:Generated_Source\PSoC4/CyLFClk.c **** * \return The mask of interrupts set +1476:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_WDT_COUNTER0_INT - Counter 0 +1477:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_WDT_COUNTER1_INT - Counter 1 +1478:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_WDT_COUNTER2_INT - Counter 2 +1479:Generated_Source\PSoC4/CyLFClk.c **** * +1480:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1481:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetInterruptSource(void) +1482:Generated_Source\PSoC4/CyLFClk.c **** { + 1636 .loc 1 1482 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 56 + + + 1637 .cfi_startproc + 1638 @ args = 0, pretend = 0, frame = 0 + 1639 @ frame_needed = 1, uses_anonymous_args = 0 + 1640 0000 80B5 push {r7, lr} + 1641 .cfi_def_cfa_offset 8 + 1642 .cfi_offset 7, -8 + 1643 .cfi_offset 14, -4 + 1644 0002 00AF add r7, sp, #0 + 1645 .cfi_def_cfa_register 7 +1483:Generated_Source\PSoC4/CyLFClk.c **** return (CY_SYS_WDT_CONTROL_REG & (CY_SYS_WDT_COUNTER0_INT | CY_SYS_WDT_COUNTER1_INT | CY_SY + 1646 .loc 1 1483 0 + 1647 0004 034B ldr r3, .L144 + 1648 0006 1B68 ldr r3, [r3] + 1649 0008 034A ldr r2, .L144+4 + 1650 000a 1340 ands r3, r2 +1484:Generated_Source\PSoC4/CyLFClk.c **** } + 1651 .loc 1 1484 0 + 1652 000c 1800 movs r0, r3 + 1653 000e BD46 mov sp, r7 + 1654 @ sp needed + 1655 0010 80BD pop {r7, pc} + 1656 .L145: + 1657 0012 C046 .align 2 + 1658 .L144: + 1659 0014 10020B40 .word 1074463248 + 1660 0018 04040400 .word 263172 + 1661 .cfi_endproc + 1662 .LFE23: + 1663 .size CySysWdtGetInterruptSource, .-CySysWdtGetInterruptSource + 1664 .section .text.CySysWdtClearInterrupt,"ax",%progbits + 1665 .align 2 + 1666 .global CySysWdtClearInterrupt + 1667 .code 16 + 1668 .thumb_func + 1669 .type CySysWdtClearInterrupt, %function + 1670 CySysWdtClearInterrupt: + 1671 .LFB24: +1485:Generated_Source\PSoC4/CyLFClk.c **** +1486:Generated_Source\PSoC4/CyLFClk.c **** +1487:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1488:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtClearInterrupt +1489:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1490:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1491:Generated_Source\PSoC4/CyLFClk.c **** * Clears all the WDT counter interrupts set in the mask. +1492:Generated_Source\PSoC4/CyLFClk.c **** * +1493:Generated_Source\PSoC4/CyLFClk.c **** * Calling this function also prevents from Reset when the counter mode is set +1494:Generated_Source\PSoC4/CyLFClk.c **** * to generate 3 interrupts and then the device resets. +1495:Generated_Source\PSoC4/CyLFClk.c **** * +1496:Generated_Source\PSoC4/CyLFClk.c **** * All the WDT interrupts are to be cleared by the firmware, otherwise +1497:Generated_Source\PSoC4/CyLFClk.c **** * interrupts are generated continuously. +1498:Generated_Source\PSoC4/CyLFClk.c **** * +1499:Generated_Source\PSoC4/CyLFClk.c **** * \param counterMask +1500:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER0_INT - Clears counter 0 interrupts
+1501:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER1_INT - Clears counter 1 interrupts
+1502:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER2_INT - Clears counter 2 interrupts +1503:Generated_Source\PSoC4/CyLFClk.c **** * +1504:Generated_Source\PSoC4/CyLFClk.c **** * \details + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 57 + + +1505:Generated_Source\PSoC4/CyLFClk.c **** * This function temporary removes the watchdog lock, if it was set, and +1506:Generated_Source\PSoC4/CyLFClk.c **** * restores the lock state after cleaning the WDT interrupts that are set in +1507:Generated_Source\PSoC4/CyLFClk.c **** * a mask. +1508:Generated_Source\PSoC4/CyLFClk.c **** * +1509:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1510:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtClearInterrupt(uint32 counterMask) +1511:Generated_Source\PSoC4/CyLFClk.c **** { + 1672 .loc 1 1511 0 + 1673 .cfi_startproc + 1674 @ args = 0, pretend = 0, frame = 16 + 1675 @ frame_needed = 1, uses_anonymous_args = 0 + 1676 0000 90B5 push {r4, r7, lr} + 1677 .cfi_def_cfa_offset 12 + 1678 .cfi_offset 4, -12 + 1679 .cfi_offset 7, -8 + 1680 .cfi_offset 14, -4 + 1681 0002 85B0 sub sp, sp, #20 + 1682 .cfi_def_cfa_offset 32 + 1683 0004 00AF add r7, sp, #0 + 1684 .cfi_def_cfa_register 7 + 1685 0006 7860 str r0, [r7, #4] +1512:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; +1513:Generated_Source\PSoC4/CyLFClk.c **** uint32 wdtLockState; +1514:Generated_Source\PSoC4/CyLFClk.c **** +1515:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); + 1686 .loc 1 1515 0 + 1687 0008 0B23 movs r3, #11 + 1688 000a FC18 adds r4, r7, r3 + 1689 000c FFF7FEFF bl CyEnterCriticalSection + 1690 0010 0300 movs r3, r0 + 1691 0012 2370 strb r3, [r4] +1516:Generated_Source\PSoC4/CyLFClk.c **** +1517:Generated_Source\PSoC4/CyLFClk.c **** if (0u != CySysWdtLocked()) + 1692 .loc 1 1517 0 + 1693 0014 FFF7FEFF bl CySysWdtLocked + 1694 0018 031E subs r3, r0, #0 + 1695 001a 04D0 beq .L147 +1518:Generated_Source\PSoC4/CyLFClk.c **** { +1519:Generated_Source\PSoC4/CyLFClk.c **** wdtLockState = 1u; + 1696 .loc 1 1519 0 + 1697 001c 0123 movs r3, #1 + 1698 001e FB60 str r3, [r7, #12] +1520:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtUnlock(); + 1699 .loc 1 1520 0 + 1700 0020 FFF7FEFF bl CySysWdtUnlock + 1701 0024 01E0 b .L148 + 1702 .L147: +1521:Generated_Source\PSoC4/CyLFClk.c **** } +1522:Generated_Source\PSoC4/CyLFClk.c **** else +1523:Generated_Source\PSoC4/CyLFClk.c **** { +1524:Generated_Source\PSoC4/CyLFClk.c **** wdtLockState = 0u; + 1703 .loc 1 1524 0 + 1704 0026 0023 movs r3, #0 + 1705 0028 FB60 str r3, [r7, #12] + 1706 .L148: +1525:Generated_Source\PSoC4/CyLFClk.c **** } +1526:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 58 + + +1527:Generated_Source\PSoC4/CyLFClk.c **** /* Set new WDT control register value */ +1528:Generated_Source\PSoC4/CyLFClk.c **** counterMask &= (CY_SYS_WDT_COUNTER0_INT | + 1707 .loc 1 1528 0 + 1708 002a 7B68 ldr r3, [r7, #4] + 1709 002c 0D4A ldr r2, .L150 + 1710 002e 1340 ands r3, r2 + 1711 0030 7B60 str r3, [r7, #4] +1529:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER1_INT | +1530:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER2_INT); +1531:Generated_Source\PSoC4/CyLFClk.c **** +1532:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONTROL_REG = counterMask | (CY_SYS_WDT_CONTROL_REG & ~(CY_SYS_WDT_COUNTER0_INT + 1712 .loc 1 1532 0 + 1713 0032 0D4B ldr r3, .L150+4 + 1714 0034 0C4A ldr r2, .L150+4 + 1715 0036 1268 ldr r2, [r2] + 1716 0038 0C49 ldr r1, .L150+8 + 1717 003a 1140 ands r1, r2 + 1718 003c 7A68 ldr r2, [r7, #4] + 1719 003e 0A43 orrs r2, r1 + 1720 0040 1A60 str r2, [r3] +1533:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER1_INT +1534:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_COUNTER2_INT) +1535:Generated_Source\PSoC4/CyLFClk.c **** +1536:Generated_Source\PSoC4/CyLFClk.c **** /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. +1537:Generated_Source\PSoC4/CyLFClk.c **** * Cypress ID #207093, #206231 +1538:Generated_Source\PSoC4/CyLFClk.c **** */ +1539:Generated_Source\PSoC4/CyLFClk.c **** (void)CY_SYS_WDT_CONTROL_REG; + 1721 .loc 1 1539 0 + 1722 0042 094B ldr r3, .L150+4 + 1723 0044 1B68 ldr r3, [r3] +1540:Generated_Source\PSoC4/CyLFClk.c **** +1541:Generated_Source\PSoC4/CyLFClk.c **** if (1u == wdtLockState) + 1724 .loc 1 1541 0 + 1725 0046 FB68 ldr r3, [r7, #12] + 1726 0048 012B cmp r3, #1 + 1727 004a 01D1 bne .L149 +1542:Generated_Source\PSoC4/CyLFClk.c **** { +1543:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtLock(); + 1728 .loc 1 1543 0 + 1729 004c FFF7FEFF bl CySysWdtLock + 1730 .L149: +1544:Generated_Source\PSoC4/CyLFClk.c **** } +1545:Generated_Source\PSoC4/CyLFClk.c **** +1546:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); + 1731 .loc 1 1546 0 + 1732 0050 0B23 movs r3, #11 + 1733 0052 FB18 adds r3, r7, r3 + 1734 0054 1B78 ldrb r3, [r3] + 1735 0056 1800 movs r0, r3 + 1736 0058 FFF7FEFF bl CyExitCriticalSection +1547:Generated_Source\PSoC4/CyLFClk.c **** } + 1737 .loc 1 1547 0 + 1738 005c C046 nop + 1739 005e BD46 mov sp, r7 + 1740 0060 05B0 add sp, sp, #20 + 1741 @ sp needed + 1742 0062 90BD pop {r4, r7, pc} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 59 + + + 1743 .L151: + 1744 .align 2 + 1745 .L150: + 1746 0064 04040400 .word 263172 + 1747 0068 10020B40 .word 1074463248 + 1748 006c FBFBFBFF .word -263173 + 1749 .cfi_endproc + 1750 .LFE24: + 1751 .size CySysWdtClearInterrupt, .-CySysWdtClearInterrupt + 1752 .section .text.CySysWdtResetCounters,"ax",%progbits + 1753 .align 2 + 1754 .global CySysWdtResetCounters + 1755 .code 16 + 1756 .thumb_func + 1757 .type CySysWdtResetCounters, %function + 1758 CySysWdtResetCounters: + 1759 .LFB25: +1548:Generated_Source\PSoC4/CyLFClk.c **** +1549:Generated_Source\PSoC4/CyLFClk.c **** +1550:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1551:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtResetCounters +1552:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1553:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1554:Generated_Source\PSoC4/CyLFClk.c **** * Resets all the WDT counters set in the mask. +1555:Generated_Source\PSoC4/CyLFClk.c **** * +1556:Generated_Source\PSoC4/CyLFClk.c **** * \param countersMask +1557:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER0_RESET - Reset counter 0
+1558:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER1_RESET - Reset counter 1
+1559:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER2_RESET - Reset counter 2 +1560:Generated_Source\PSoC4/CyLFClk.c **** * +1561:Generated_Source\PSoC4/CyLFClk.c **** * \details +1562:Generated_Source\PSoC4/CyLFClk.c **** * This function does not reset counter values if the Watchdog is locked. +1563:Generated_Source\PSoC4/CyLFClk.c **** * This function waits while corresponding counters will be reset. This may +1564:Generated_Source\PSoC4/CyLFClk.c **** * take up to 3 LFCLK cycles. +1565:Generated_Source\PSoC4/CyLFClk.c **** * The LFCLK source must be enabled. Otherwise, the function will never exit. +1566:Generated_Source\PSoC4/CyLFClk.c **** * +1567:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1568:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtResetCounters(uint32 countersMask) +1569:Generated_Source\PSoC4/CyLFClk.c **** { + 1760 .loc 1 1569 0 + 1761 .cfi_startproc + 1762 @ args = 0, pretend = 0, frame = 8 + 1763 @ frame_needed = 1, uses_anonymous_args = 0 + 1764 0000 80B5 push {r7, lr} + 1765 .cfi_def_cfa_offset 8 + 1766 .cfi_offset 7, -8 + 1767 .cfi_offset 14, -4 + 1768 0002 82B0 sub sp, sp, #8 + 1769 .cfi_def_cfa_offset 16 + 1770 0004 00AF add r7, sp, #0 + 1771 .cfi_def_cfa_register 7 + 1772 0006 7860 str r0, [r7, #4] +1570:Generated_Source\PSoC4/CyLFClk.c **** /* Set new WDT reset value */ +1571:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONTROL_REG |= (countersMask & CY_SYS_WDT_COUNTERS_RESET); + 1773 .loc 1 1571 0 + 1774 0008 084B ldr r3, .L154 + 1775 000a 084A ldr r2, .L154 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 60 + + + 1776 000c 1168 ldr r1, [r2] + 1777 000e 7A68 ldr r2, [r7, #4] + 1778 0010 0748 ldr r0, .L154+4 + 1779 0012 0240 ands r2, r0 + 1780 0014 0A43 orrs r2, r1 + 1781 0016 1A60 str r2, [r3] +1572:Generated_Source\PSoC4/CyLFClk.c **** +1573:Generated_Source\PSoC4/CyLFClk.c **** while (0uL != (CY_SYS_WDT_CONTROL_REG & CY_SYS_WDT_COUNTERS_RESET)) + 1782 .loc 1 1573 0 + 1783 0018 C046 nop + 1784 .L153: + 1785 .loc 1 1573 0 is_stmt 0 discriminator 1 + 1786 001a 044B ldr r3, .L154 + 1787 001c 1B68 ldr r3, [r3] + 1788 001e 044A ldr r2, .L154+4 + 1789 0020 1340 ands r3, r2 + 1790 0022 FAD1 bne .L153 +1574:Generated_Source\PSoC4/CyLFClk.c **** { +1575:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for reset to come into effect */ +1576:Generated_Source\PSoC4/CyLFClk.c **** } +1577:Generated_Source\PSoC4/CyLFClk.c **** } + 1791 .loc 1 1577 0 is_stmt 1 + 1792 0024 C046 nop + 1793 0026 BD46 mov sp, r7 + 1794 0028 02B0 add sp, sp, #8 + 1795 @ sp needed + 1796 002a 80BD pop {r7, pc} + 1797 .L155: + 1798 .align 2 + 1799 .L154: + 1800 002c 10020B40 .word 1074463248 + 1801 0030 08080800 .word 526344 + 1802 .cfi_endproc + 1803 .LFE25: + 1804 .size CySysWdtResetCounters, .-CySysWdtResetCounters + 1805 .section .text.CySysWdtSetInterruptCallback,"ax",%progbits + 1806 .align 2 + 1807 .global CySysWdtSetInterruptCallback + 1808 .code 16 + 1809 .thumb_func + 1810 .type CySysWdtSetInterruptCallback, %function + 1811 CySysWdtSetInterruptCallback: + 1812 .LFB26: +1578:Generated_Source\PSoC4/CyLFClk.c **** +1579:Generated_Source\PSoC4/CyLFClk.c **** +1580:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1581:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetInterruptCallback +1582:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1583:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1584:Generated_Source\PSoC4/CyLFClk.c **** * Sets the ISR callback function for the particular WDT counter. +1585:Generated_Source\PSoC4/CyLFClk.c **** * These functions are called on the WDT interrupt. +1586:Generated_Source\PSoC4/CyLFClk.c **** * +1587:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum The number of the WDT counter. +1588:Generated_Source\PSoC4/CyLFClk.c **** * \param function The pointer to the callback function. +1589:Generated_Source\PSoC4/CyLFClk.c **** * +1590:Generated_Source\PSoC4/CyLFClk.c **** * \return The pointer to the previous callback function. +1591:Generated_Source\PSoC4/CyLFClk.c **** * \return NULL is returned if the specified address is not set. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 61 + + +1592:Generated_Source\PSoC4/CyLFClk.c **** * +1593:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1594:Generated_Source\PSoC4/CyLFClk.c **** cyWdtCallback CySysWdtSetInterruptCallback(uint32 counterNum, cyWdtCallback function) +1595:Generated_Source\PSoC4/CyLFClk.c **** { + 1813 .loc 1 1595 0 + 1814 .cfi_startproc + 1815 @ args = 0, pretend = 0, frame = 16 + 1816 @ frame_needed = 1, uses_anonymous_args = 0 + 1817 0000 80B5 push {r7, lr} + 1818 .cfi_def_cfa_offset 8 + 1819 .cfi_offset 7, -8 + 1820 .cfi_offset 14, -4 + 1821 0002 84B0 sub sp, sp, #16 + 1822 .cfi_def_cfa_offset 24 + 1823 0004 00AF add r7, sp, #0 + 1824 .cfi_def_cfa_register 7 + 1825 0006 7860 str r0, [r7, #4] + 1826 0008 3960 str r1, [r7] +1596:Generated_Source\PSoC4/CyLFClk.c **** cyWdtCallback prevCallback = (void *)0; + 1827 .loc 1 1596 0 + 1828 000a 0023 movs r3, #0 + 1829 000c FB60 str r3, [r7, #12] +1597:Generated_Source\PSoC4/CyLFClk.c **** +1598:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum < CY_WDT_NUM_OF_WDT) + 1830 .loc 1 1598 0 + 1831 000e 7B68 ldr r3, [r7, #4] + 1832 0010 022B cmp r3, #2 + 1833 0012 0AD8 bhi .L157 +1599:Generated_Source\PSoC4/CyLFClk.c **** { +1600:Generated_Source\PSoC4/CyLFClk.c **** prevCallback = cySysWdtCallback[counterNum]; + 1834 .loc 1 1600 0 + 1835 0014 094B ldr r3, .L160 + 1836 0016 7A68 ldr r2, [r7, #4] + 1837 0018 9200 lsls r2, r2, #2 + 1838 001a D358 ldr r3, [r2, r3] + 1839 001c FB60 str r3, [r7, #12] +1601:Generated_Source\PSoC4/CyLFClk.c **** cySysWdtCallback[counterNum] = function; + 1840 .loc 1 1601 0 + 1841 001e 074B ldr r3, .L160 + 1842 0020 7A68 ldr r2, [r7, #4] + 1843 0022 9200 lsls r2, r2, #2 + 1844 0024 3968 ldr r1, [r7] + 1845 0026 D150 str r1, [r2, r3] + 1846 0028 02E0 b .L158 + 1847 .L157: +1602:Generated_Source\PSoC4/CyLFClk.c **** } +1603:Generated_Source\PSoC4/CyLFClk.c **** else +1604:Generated_Source\PSoC4/CyLFClk.c **** { +1605:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); + 1848 .loc 1 1605 0 discriminator 1 + 1849 002a 0020 movs r0, #0 + 1850 002c FFF7FEFF bl CyHalt + 1851 .L158: +1606:Generated_Source\PSoC4/CyLFClk.c **** } +1607:Generated_Source\PSoC4/CyLFClk.c **** +1608:Generated_Source\PSoC4/CyLFClk.c **** return((cyWdtCallback)prevCallback); + 1852 .loc 1 1608 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 62 + + + 1853 0030 FB68 ldr r3, [r7, #12] +1609:Generated_Source\PSoC4/CyLFClk.c **** } + 1854 .loc 1 1609 0 + 1855 0032 1800 movs r0, r3 + 1856 0034 BD46 mov sp, r7 + 1857 0036 04B0 add sp, sp, #16 + 1858 @ sp needed + 1859 0038 80BD pop {r7, pc} + 1860 .L161: + 1861 003a C046 .align 2 + 1862 .L160: + 1863 003c 0C000000 .word cySysWdtCallback + 1864 .cfi_endproc + 1865 .LFE26: + 1866 .size CySysWdtSetInterruptCallback, .-CySysWdtSetInterruptCallback + 1867 .section .text.CySysWdtGetInterruptCallback,"ax",%progbits + 1868 .align 2 + 1869 .global CySysWdtGetInterruptCallback + 1870 .code 16 + 1871 .thumb_func + 1872 .type CySysWdtGetInterruptCallback, %function + 1873 CySysWdtGetInterruptCallback: + 1874 .LFB27: +1610:Generated_Source\PSoC4/CyLFClk.c **** +1611:Generated_Source\PSoC4/CyLFClk.c **** +1612:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1613:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetInterruptCallback +1614:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1615:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1616:Generated_Source\PSoC4/CyLFClk.c **** * Gets the ISR callback function for the particular WDT counter. +1617:Generated_Source\PSoC4/CyLFClk.c **** * +1618:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum The number of the WDT counter. +1619:Generated_Source\PSoC4/CyLFClk.c **** * +1620:Generated_Source\PSoC4/CyLFClk.c **** * \return The pointer to the callback function registered for a particular WDT by +1621:Generated_Source\PSoC4/CyLFClk.c **** * a particular address that are passed through arguments. +1622:Generated_Source\PSoC4/CyLFClk.c **** * +1623:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1624:Generated_Source\PSoC4/CyLFClk.c **** cyWdtCallback CySysWdtGetInterruptCallback(uint32 counterNum) +1625:Generated_Source\PSoC4/CyLFClk.c **** { + 1875 .loc 1 1625 0 + 1876 .cfi_startproc + 1877 @ args = 0, pretend = 0, frame = 16 + 1878 @ frame_needed = 1, uses_anonymous_args = 0 + 1879 0000 80B5 push {r7, lr} + 1880 .cfi_def_cfa_offset 8 + 1881 .cfi_offset 7, -8 + 1882 .cfi_offset 14, -4 + 1883 0002 84B0 sub sp, sp, #16 + 1884 .cfi_def_cfa_offset 24 + 1885 0004 00AF add r7, sp, #0 + 1886 .cfi_def_cfa_register 7 + 1887 0006 7860 str r0, [r7, #4] +1626:Generated_Source\PSoC4/CyLFClk.c **** cyWdtCallback retCallback = (void *)0; + 1888 .loc 1 1626 0 + 1889 0008 0023 movs r3, #0 + 1890 000a FB60 str r3, [r7, #12] +1627:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 63 + + +1628:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum < CY_WDT_NUM_OF_WDT) + 1891 .loc 1 1628 0 + 1892 000c 7B68 ldr r3, [r7, #4] + 1893 000e 022B cmp r3, #2 + 1894 0010 05D8 bhi .L163 +1629:Generated_Source\PSoC4/CyLFClk.c **** { +1630:Generated_Source\PSoC4/CyLFClk.c **** retCallback = (cyWdtCallback)cySysWdtCallback[counterNum]; + 1895 .loc 1 1630 0 + 1896 0012 074B ldr r3, .L166 + 1897 0014 7A68 ldr r2, [r7, #4] + 1898 0016 9200 lsls r2, r2, #2 + 1899 0018 D358 ldr r3, [r2, r3] + 1900 001a FB60 str r3, [r7, #12] + 1901 001c 02E0 b .L164 + 1902 .L163: +1631:Generated_Source\PSoC4/CyLFClk.c **** } +1632:Generated_Source\PSoC4/CyLFClk.c **** else +1633:Generated_Source\PSoC4/CyLFClk.c **** { +1634:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); + 1903 .loc 1 1634 0 discriminator 1 + 1904 001e 0020 movs r0, #0 + 1905 0020 FFF7FEFF bl CyHalt + 1906 .L164: +1635:Generated_Source\PSoC4/CyLFClk.c **** } +1636:Generated_Source\PSoC4/CyLFClk.c **** +1637:Generated_Source\PSoC4/CyLFClk.c **** return(retCallback); + 1907 .loc 1 1637 0 + 1908 0024 FB68 ldr r3, [r7, #12] +1638:Generated_Source\PSoC4/CyLFClk.c **** } + 1909 .loc 1 1638 0 + 1910 0026 1800 movs r0, r3 + 1911 0028 BD46 mov sp, r7 + 1912 002a 04B0 add sp, sp, #16 + 1913 @ sp needed + 1914 002c 80BD pop {r7, pc} + 1915 .L167: + 1916 002e C046 .align 2 + 1917 .L166: + 1918 0030 0C000000 .word cySysWdtCallback + 1919 .cfi_endproc + 1920 .LFE27: + 1921 .size CySysWdtGetInterruptCallback, .-CySysWdtGetInterruptCallback + 1922 .section .text.CySysWdtEnableCounterIsr,"ax",%progbits + 1923 .align 2 + 1924 .global CySysWdtEnableCounterIsr + 1925 .code 16 + 1926 .thumb_func + 1927 .type CySysWdtEnableCounterIsr, %function + 1928 CySysWdtEnableCounterIsr: + 1929 .LFB28: +1639:Generated_Source\PSoC4/CyLFClk.c **** +1640:Generated_Source\PSoC4/CyLFClk.c **** +1641:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1642:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtEnableCounterIsr +1643:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1644:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1645:Generated_Source\PSoC4/CyLFClk.c **** * Enables the ISR callback servicing for the particular WDT counter + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 64 + + +1646:Generated_Source\PSoC4/CyLFClk.c **** * +1647:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-2]. The number of the WDT counter. +1648:Generated_Source\PSoC4/CyLFClk.c **** * +1649:Generated_Source\PSoC4/CyLFClk.c **** * Value corresponds to appropriate WDT counter. For example value 1 +1650:Generated_Source\PSoC4/CyLFClk.c **** * corresponds to second WDT counter. +1651:Generated_Source\PSoC4/CyLFClk.c **** * +1652:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1653:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtEnableCounterIsr(uint32 counterNum) +1654:Generated_Source\PSoC4/CyLFClk.c **** { + 1930 .loc 1 1654 0 + 1931 .cfi_startproc + 1932 @ args = 0, pretend = 0, frame = 8 + 1933 @ frame_needed = 1, uses_anonymous_args = 0 + 1934 0000 80B5 push {r7, lr} + 1935 .cfi_def_cfa_offset 8 + 1936 .cfi_offset 7, -8 + 1937 .cfi_offset 14, -4 + 1938 0002 82B0 sub sp, sp, #8 + 1939 .cfi_def_cfa_offset 16 + 1940 0004 00AF add r7, sp, #0 + 1941 .cfi_def_cfa_register 7 + 1942 0006 7860 str r0, [r7, #4] +1655:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum <= CY_SYS_WDT_COUNTER2) + 1943 .loc 1 1655 0 + 1944 0008 7B68 ldr r3, [r7, #4] + 1945 000a 022B cmp r3, #2 + 1946 000c 13D8 bhi .L169 +1656:Generated_Source\PSoC4/CyLFClk.c **** { +1657:Generated_Source\PSoC4/CyLFClk.c **** disableServicedIsr &= ~counterIntMaskTbl[counterNum]; + 1947 .loc 1 1657 0 + 1948 000e 0D4B ldr r3, .L172 + 1949 0010 7A68 ldr r2, [r7, #4] + 1950 0012 9200 lsls r2, r2, #2 + 1951 0014 D358 ldr r3, [r2, r3] + 1952 0016 DA43 mvns r2, r3 + 1953 0018 0B4B ldr r3, .L172+4 + 1954 001a 1B68 ldr r3, [r3] + 1955 001c 1A40 ands r2, r3 + 1956 001e 0A4B ldr r3, .L172+4 + 1957 0020 1A60 str r2, [r3] +1658:Generated_Source\PSoC4/CyLFClk.c **** wdtIsrMask |= counterIntMaskTbl[counterNum]; + 1958 .loc 1 1658 0 + 1959 0022 084B ldr r3, .L172 + 1960 0024 7A68 ldr r2, [r7, #4] + 1961 0026 9200 lsls r2, r2, #2 + 1962 0028 D258 ldr r2, [r2, r3] + 1963 002a 084B ldr r3, .L172+8 + 1964 002c 1B68 ldr r3, [r3] + 1965 002e 1A43 orrs r2, r3 + 1966 0030 064B ldr r3, .L172+8 + 1967 0032 1A60 str r2, [r3] +1659:Generated_Source\PSoC4/CyLFClk.c **** } +1660:Generated_Source\PSoC4/CyLFClk.c **** else +1661:Generated_Source\PSoC4/CyLFClk.c **** { +1662:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +1663:Generated_Source\PSoC4/CyLFClk.c **** } +1664:Generated_Source\PSoC4/CyLFClk.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 65 + + + 1968 .loc 1 1664 0 + 1969 0034 02E0 b .L171 + 1970 .L169: +1662:Generated_Source\PSoC4/CyLFClk.c **** } + 1971 .loc 1 1662 0 discriminator 1 + 1972 0036 0020 movs r0, #0 + 1973 0038 FFF7FEFF bl CyHalt + 1974 .L171: + 1975 .loc 1 1664 0 + 1976 003c C046 nop + 1977 003e BD46 mov sp, r7 + 1978 0040 02B0 add sp, sp, #8 + 1979 @ sp needed + 1980 0042 80BD pop {r7, pc} + 1981 .L173: + 1982 .align 2 + 1983 .L172: + 1984 0044 00000000 .word counterIntMaskTbl + 1985 0048 08000000 .word disableServicedIsr + 1986 004c 00000000 .word wdtIsrMask + 1987 .cfi_endproc + 1988 .LFE28: + 1989 .size CySysWdtEnableCounterIsr, .-CySysWdtEnableCounterIsr + 1990 .section .text.CySysWdtDisableCounterIsr,"ax",%progbits + 1991 .align 2 + 1992 .global CySysWdtDisableCounterIsr + 1993 .code 16 + 1994 .thumb_func + 1995 .type CySysWdtDisableCounterIsr, %function + 1996 CySysWdtDisableCounterIsr: + 1997 .LFB29: +1665:Generated_Source\PSoC4/CyLFClk.c **** +1666:Generated_Source\PSoC4/CyLFClk.c **** +1667:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1668:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtDisableCounterIsr +1669:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1670:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1671:Generated_Source\PSoC4/CyLFClk.c **** * Disables the ISR callback servicing for the particular WDT counter +1672:Generated_Source\PSoC4/CyLFClk.c **** * +1673:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-2]. The number of the WDT counter. +1674:Generated_Source\PSoC4/CyLFClk.c **** * +1675:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1676:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtDisableCounterIsr(uint32 counterNum) +1677:Generated_Source\PSoC4/CyLFClk.c **** { + 1998 .loc 1 1677 0 + 1999 .cfi_startproc + 2000 @ args = 0, pretend = 0, frame = 8 + 2001 @ frame_needed = 1, uses_anonymous_args = 0 + 2002 0000 80B5 push {r7, lr} + 2003 .cfi_def_cfa_offset 8 + 2004 .cfi_offset 7, -8 + 2005 .cfi_offset 14, -4 + 2006 0002 82B0 sub sp, sp, #8 + 2007 .cfi_def_cfa_offset 16 + 2008 0004 00AF add r7, sp, #0 + 2009 .cfi_def_cfa_register 7 + 2010 0006 7860 str r0, [r7, #4] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 66 + + +1678:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum <= CY_SYS_WDT_COUNTER2) + 2011 .loc 1 1678 0 + 2012 0008 7B68 ldr r3, [r7, #4] + 2013 000a 022B cmp r3, #2 + 2014 000c 0AD8 bhi .L175 +1679:Generated_Source\PSoC4/CyLFClk.c **** { +1680:Generated_Source\PSoC4/CyLFClk.c **** wdtIsrMask &= ~counterIntMaskTbl[counterNum]; + 2015 .loc 1 1680 0 + 2016 000e 094B ldr r3, .L178 + 2017 0010 7A68 ldr r2, [r7, #4] + 2018 0012 9200 lsls r2, r2, #2 + 2019 0014 D358 ldr r3, [r2, r3] + 2020 0016 DA43 mvns r2, r3 + 2021 0018 074B ldr r3, .L178+4 + 2022 001a 1B68 ldr r3, [r3] + 2023 001c 1A40 ands r2, r3 + 2024 001e 064B ldr r3, .L178+4 + 2025 0020 1A60 str r2, [r3] +1681:Generated_Source\PSoC4/CyLFClk.c **** } +1682:Generated_Source\PSoC4/CyLFClk.c **** else +1683:Generated_Source\PSoC4/CyLFClk.c **** { +1684:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +1685:Generated_Source\PSoC4/CyLFClk.c **** } +1686:Generated_Source\PSoC4/CyLFClk.c **** } + 2026 .loc 1 1686 0 + 2027 0022 02E0 b .L177 + 2028 .L175: +1684:Generated_Source\PSoC4/CyLFClk.c **** } + 2029 .loc 1 1684 0 discriminator 1 + 2030 0024 0020 movs r0, #0 + 2031 0026 FFF7FEFF bl CyHalt + 2032 .L177: + 2033 .loc 1 1686 0 + 2034 002a C046 nop + 2035 002c BD46 mov sp, r7 + 2036 002e 02B0 add sp, sp, #8 + 2037 @ sp needed + 2038 0030 80BD pop {r7, pc} + 2039 .L179: + 2040 0032 C046 .align 2 + 2041 .L178: + 2042 0034 00000000 .word counterIntMaskTbl + 2043 0038 00000000 .word wdtIsrMask + 2044 .cfi_endproc + 2045 .LFE29: + 2046 .size CySysWdtDisableCounterIsr, .-CySysWdtDisableCounterIsr + 2047 .section .text.CySysWdtIsr,"ax",%progbits + 2048 .align 2 + 2049 .global CySysWdtIsr + 2050 .code 16 + 2051 .thumb_func + 2052 .type CySysWdtIsr, %function + 2053 CySysWdtIsr: + 2054 .LFB30: +1687:Generated_Source\PSoC4/CyLFClk.c **** +1688:Generated_Source\PSoC4/CyLFClk.c **** +1689:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 67 + + +1690:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtIsr +1691:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1692:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1693:Generated_Source\PSoC4/CyLFClk.c **** * This is the handler of the WDT interrupt in CPU NVIC. +1694:Generated_Source\PSoC4/CyLFClk.c **** * +1695:Generated_Source\PSoC4/CyLFClk.c **** * The handler checks which WDT triggered in the interrupt and calls the +1696:Generated_Source\PSoC4/CyLFClk.c **** * respective callback functions configured by the user by using +1697:Generated_Source\PSoC4/CyLFClk.c **** * CySysWdtSetIsrCallback() API. +1698:Generated_Source\PSoC4/CyLFClk.c **** * +1699:Generated_Source\PSoC4/CyLFClk.c **** * The order of the callback execution is incremental. Callback-0 is +1700:Generated_Source\PSoC4/CyLFClk.c **** * run as the first one and callback-2 is called as the last one. +1701:Generated_Source\PSoC4/CyLFClk.c **** * +1702:Generated_Source\PSoC4/CyLFClk.c **** * \details +1703:Generated_Source\PSoC4/CyLFClk.c **** * This function clears the WDT interrupt every time when it is called. +1704:Generated_Source\PSoC4/CyLFClk.c **** * Reset after the 3rd interrupt does not happen if this function is registered +1705:Generated_Source\PSoC4/CyLFClk.c **** * as the interrupt handler even if the "Watchdog with Interrupt" mode is +1706:Generated_Source\PSoC4/CyLFClk.c **** * selected on the "Low Frequency Clocks" tab. +1707:Generated_Source\PSoC4/CyLFClk.c **** * +1708:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1709:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtIsr(void) +1710:Generated_Source\PSoC4/CyLFClk.c **** { + 2055 .loc 1 1710 0 + 2056 .cfi_startproc + 2057 @ args = 0, pretend = 0, frame = 0 + 2058 @ frame_needed = 1, uses_anonymous_args = 0 + 2059 0000 80B5 push {r7, lr} + 2060 .cfi_def_cfa_offset 8 + 2061 .cfi_offset 7, -8 + 2062 .cfi_offset 14, -4 + 2063 0002 00AF add r7, sp, #0 + 2064 .cfi_def_cfa_register 7 +1711:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_WDT_COUNTER0_INT & CY_SYS_WDT_CONTROL_REG)) + 2065 .loc 1 1711 0 + 2066 0004 344B ldr r3, .L188 + 2067 0006 1B68 ldr r3, [r3] + 2068 0008 0422 movs r2, #4 + 2069 000a 1340 ands r3, r2 + 2070 000c 1FD0 beq .L181 +1712:Generated_Source\PSoC4/CyLFClk.c **** { +1713:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_WDT_COUNTER0_INT & wdtIsrMask)) + 2071 .loc 1 1713 0 + 2072 000e 334B ldr r3, .L188+4 + 2073 0010 1B68 ldr r3, [r3] + 2074 0012 0422 movs r2, #4 + 2075 0014 1340 ands r3, r2 + 2076 0016 17D0 beq .L182 +1714:Generated_Source\PSoC4/CyLFClk.c **** { +1715:Generated_Source\PSoC4/CyLFClk.c **** wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER0_INT); + 2077 .loc 1 1715 0 + 2078 0018 314B ldr r3, .L188+8 + 2079 001a 1B68 ldr r3, [r3] + 2080 001c 0422 movs r2, #4 + 2081 001e 1340 ands r3, r2 + 2082 0020 DA43 mvns r2, r3 + 2083 0022 2E4B ldr r3, .L188+4 + 2084 0024 1B68 ldr r3, [r3] + 2085 0026 1A40 ands r2, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 68 + + + 2086 0028 2C4B ldr r3, .L188+4 + 2087 002a 1A60 str r2, [r3] +1716:Generated_Source\PSoC4/CyLFClk.c **** disableServicedIsr &= ~CY_SYS_WDT_COUNTER0_INT; + 2088 .loc 1 1716 0 + 2089 002c 2C4B ldr r3, .L188+8 + 2090 002e 1B68 ldr r3, [r3] + 2091 0030 0422 movs r2, #4 + 2092 0032 9343 bics r3, r2 + 2093 0034 1A00 movs r2, r3 + 2094 0036 2A4B ldr r3, .L188+8 + 2095 0038 1A60 str r2, [r3] +1717:Generated_Source\PSoC4/CyLFClk.c **** if(cySysWdtCallback[CY_SYS_WDT_COUNTER0] != (void *) 0) + 2096 .loc 1 1717 0 + 2097 003a 2A4B ldr r3, .L188+12 + 2098 003c 1B68 ldr r3, [r3] + 2099 003e 002B cmp r3, #0 + 2100 0040 02D0 beq .L182 +1718:Generated_Source\PSoC4/CyLFClk.c **** { +1719:Generated_Source\PSoC4/CyLFClk.c **** (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER0])(); + 2101 .loc 1 1719 0 + 2102 0042 284B ldr r3, .L188+12 + 2103 0044 1B68 ldr r3, [r3] + 2104 0046 9847 blx r3 + 2105 .L182: +1720:Generated_Source\PSoC4/CyLFClk.c **** } +1721:Generated_Source\PSoC4/CyLFClk.c **** } +1722:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + 2106 .loc 1 1722 0 + 2107 0048 0420 movs r0, #4 + 2108 004a FFF7FEFF bl CySysWdtClearInterrupt + 2109 .L181: +1723:Generated_Source\PSoC4/CyLFClk.c **** } +1724:Generated_Source\PSoC4/CyLFClk.c **** +1725:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_WDT_COUNTER1_INT & CY_SYS_WDT_CONTROL_REG)) + 2110 .loc 1 1725 0 + 2111 004e 224B ldr r3, .L188 + 2112 0050 1A68 ldr r2, [r3] + 2113 0052 8023 movs r3, #128 + 2114 0054 DB00 lsls r3, r3, #3 + 2115 0056 1340 ands r3, r2 + 2116 0058 22D0 beq .L183 +1726:Generated_Source\PSoC4/CyLFClk.c **** { +1727:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_WDT_COUNTER1_INT & wdtIsrMask)) + 2117 .loc 1 1727 0 + 2118 005a 204B ldr r3, .L188+4 + 2119 005c 1A68 ldr r2, [r3] + 2120 005e 8023 movs r3, #128 + 2121 0060 DB00 lsls r3, r3, #3 + 2122 0062 1340 ands r3, r2 + 2123 0064 17D0 beq .L184 +1728:Generated_Source\PSoC4/CyLFClk.c **** { +1729:Generated_Source\PSoC4/CyLFClk.c **** wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER1_INT); + 2124 .loc 1 1729 0 + 2125 0066 1E4B ldr r3, .L188+8 + 2126 0068 1A68 ldr r2, [r3] + 2127 006a 8023 movs r3, #128 + 2128 006c DB00 lsls r3, r3, #3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 69 + + + 2129 006e 1340 ands r3, r2 + 2130 0070 DA43 mvns r2, r3 + 2131 0072 1A4B ldr r3, .L188+4 + 2132 0074 1B68 ldr r3, [r3] + 2133 0076 1A40 ands r2, r3 + 2134 0078 184B ldr r3, .L188+4 + 2135 007a 1A60 str r2, [r3] +1730:Generated_Source\PSoC4/CyLFClk.c **** disableServicedIsr &= ~CY_SYS_WDT_COUNTER1_INT; + 2136 .loc 1 1730 0 + 2137 007c 184B ldr r3, .L188+8 + 2138 007e 1B68 ldr r3, [r3] + 2139 0080 194A ldr r2, .L188+16 + 2140 0082 1A40 ands r2, r3 + 2141 0084 164B ldr r3, .L188+8 + 2142 0086 1A60 str r2, [r3] +1731:Generated_Source\PSoC4/CyLFClk.c **** if(cySysWdtCallback[CY_SYS_WDT_COUNTER1] != (void *) 0) + 2143 .loc 1 1731 0 + 2144 0088 164B ldr r3, .L188+12 + 2145 008a 5B68 ldr r3, [r3, #4] + 2146 008c 002B cmp r3, #0 + 2147 008e 02D0 beq .L184 +1732:Generated_Source\PSoC4/CyLFClk.c **** { +1733:Generated_Source\PSoC4/CyLFClk.c **** (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER1])(); + 2148 .loc 1 1733 0 + 2149 0090 144B ldr r3, .L188+12 + 2150 0092 5B68 ldr r3, [r3, #4] + 2151 0094 9847 blx r3 + 2152 .L184: +1734:Generated_Source\PSoC4/CyLFClk.c **** } +1735:Generated_Source\PSoC4/CyLFClk.c **** } +1736:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + 2153 .loc 1 1736 0 + 2154 0096 8023 movs r3, #128 + 2155 0098 DB00 lsls r3, r3, #3 + 2156 009a 1800 movs r0, r3 + 2157 009c FFF7FEFF bl CySysWdtClearInterrupt + 2158 .L183: +1737:Generated_Source\PSoC4/CyLFClk.c **** } +1738:Generated_Source\PSoC4/CyLFClk.c **** +1739:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_WDT_COUNTER2_INT & CY_SYS_WDT_CONTROL_REG)) + 2159 .loc 1 1739 0 + 2160 00a0 0D4B ldr r3, .L188 + 2161 00a2 1A68 ldr r2, [r3] + 2162 00a4 8023 movs r3, #128 + 2163 00a6 DB02 lsls r3, r3, #11 + 2164 00a8 1340 ands r3, r2 + 2165 00aa 11D0 beq .L187 +1740:Generated_Source\PSoC4/CyLFClk.c **** { +1741:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_WDT_COUNTER2_INT & wdtIsrMask)) + 2166 .loc 1 1741 0 + 2167 00ac 0B4B ldr r3, .L188+4 + 2168 00ae 1A68 ldr r2, [r3] + 2169 00b0 8023 movs r3, #128 + 2170 00b2 DB02 lsls r3, r3, #11 + 2171 00b4 1340 ands r3, r2 + 2172 00b6 06D0 beq .L186 +1742:Generated_Source\PSoC4/CyLFClk.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 70 + + +1743:Generated_Source\PSoC4/CyLFClk.c **** if(cySysWdtCallback[CY_SYS_WDT_COUNTER2] != (void *) 0) + 2173 .loc 1 1743 0 + 2174 00b8 0A4B ldr r3, .L188+12 + 2175 00ba 9B68 ldr r3, [r3, #8] + 2176 00bc 002B cmp r3, #0 + 2177 00be 02D0 beq .L186 +1744:Generated_Source\PSoC4/CyLFClk.c **** { +1745:Generated_Source\PSoC4/CyLFClk.c **** (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER2])(); + 2178 .loc 1 1745 0 + 2179 00c0 084B ldr r3, .L188+12 + 2180 00c2 9B68 ldr r3, [r3, #8] + 2181 00c4 9847 blx r3 + 2182 .L186: +1746:Generated_Source\PSoC4/CyLFClk.c **** } +1747:Generated_Source\PSoC4/CyLFClk.c **** } +1748:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER2_INT); + 2183 .loc 1 1748 0 + 2184 00c6 8023 movs r3, #128 + 2185 00c8 DB02 lsls r3, r3, #11 + 2186 00ca 1800 movs r0, r3 + 2187 00cc FFF7FEFF bl CySysWdtClearInterrupt + 2188 .L187: +1749:Generated_Source\PSoC4/CyLFClk.c **** } +1750:Generated_Source\PSoC4/CyLFClk.c **** } + 2189 .loc 1 1750 0 + 2190 00d0 C046 nop + 2191 00d2 BD46 mov sp, r7 + 2192 @ sp needed + 2193 00d4 80BD pop {r7, pc} + 2194 .L189: + 2195 00d6 C046 .align 2 + 2196 .L188: + 2197 00d8 10020B40 .word 1074463248 + 2198 00dc 00000000 .word wdtIsrMask + 2199 00e0 08000000 .word disableServicedIsr + 2200 00e4 0C000000 .word cySysWdtCallback + 2201 00e8 FFFBFFFF .word -1025 + 2202 .cfi_endproc + 2203 .LFE30: + 2204 .size CySysWdtIsr, .-CySysWdtIsr + 2205 .section .text.CySysWatchdogFeed,"ax",%progbits + 2206 .align 2 + 2207 .global CySysWatchdogFeed + 2208 .code 16 + 2209 .thumb_func + 2210 .type CySysWatchdogFeed, %function + 2211 CySysWatchdogFeed: + 2212 .LFB31: +1751:Generated_Source\PSoC4/CyLFClk.c **** +1752:Generated_Source\PSoC4/CyLFClk.c **** +1753:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1754:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWatchdogFeed +1755:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1756:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1757:Generated_Source\PSoC4/CyLFClk.c **** * Feeds the corresponded Watchdog Counter before it causes the device reset. +1758:Generated_Source\PSoC4/CyLFClk.c **** * +1759:Generated_Source\PSoC4/CyLFClk.c **** * Supported only for first WDT0 and second WDT1 counters in the "Watchdog" or + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 71 + + +1760:Generated_Source\PSoC4/CyLFClk.c **** * "Watchdog w/ Interrupts" modes. +1761:Generated_Source\PSoC4/CyLFClk.c **** * +1762:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum +1763:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER0 - Feeds the Counter 0
+1764:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_WDT_COUNTER1 - Feeds the Counter 1 +1765:Generated_Source\PSoC4/CyLFClk.c **** * +1766:Generated_Source\PSoC4/CyLFClk.c **** * Value of counterNum corresponds to appropriate counter. For example value 1 +1767:Generated_Source\PSoC4/CyLFClk.c **** * corresponds to second WDT1 Counter. +1768:Generated_Source\PSoC4/CyLFClk.c **** * +1769:Generated_Source\PSoC4/CyLFClk.c **** * \details +1770:Generated_Source\PSoC4/CyLFClk.c **** * Clears the WDT counter in the "Watchdog" mode or clears the WDT interrupt in +1771:Generated_Source\PSoC4/CyLFClk.c **** * "Watchdog w/ Interrupts" mode. Does nothing in other modes. +1772:Generated_Source\PSoC4/CyLFClk.c **** * +1773:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1774:Generated_Source\PSoC4/CyLFClk.c **** void CySysWatchdogFeed(uint32 counterNum) +1775:Generated_Source\PSoC4/CyLFClk.c **** { + 2213 .loc 1 1775 0 + 2214 .cfi_startproc + 2215 @ args = 0, pretend = 0, frame = 8 + 2216 @ frame_needed = 1, uses_anonymous_args = 0 + 2217 0000 80B5 push {r7, lr} + 2218 .cfi_def_cfa_offset 8 + 2219 .cfi_offset 7, -8 + 2220 .cfi_offset 14, -4 + 2221 0002 82B0 sub sp, sp, #8 + 2222 .cfi_def_cfa_offset 16 + 2223 0004 00AF add r7, sp, #0 + 2224 .cfi_def_cfa_register 7 + 2225 0006 7860 str r0, [r7, #4] +1776:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum == CY_SYS_WDT_COUNTER0) + 2226 .loc 1 1776 0 + 2227 0008 7B68 ldr r3, [r7, #4] + 2228 000a 002B cmp r3, #0 + 2229 000c 18D1 bne .L191 +1777:Generated_Source\PSoC4/CyLFClk.c **** { +1778:Generated_Source\PSoC4/CyLFClk.c **** if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) + 2230 .loc 1 1778 0 + 2231 000e 7B68 ldr r3, [r7, #4] + 2232 0010 1800 movs r0, r3 + 2233 0012 FFF7FEFF bl CySysWdtGetMode + 2234 0016 0300 movs r3, r0 + 2235 0018 032B cmp r3, #3 + 2236 001a 03D1 bne .L192 +1779:Generated_Source\PSoC4/CyLFClk.c **** { +1780:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + 2237 .loc 1 1780 0 + 2238 001c 0420 movs r0, #4 + 2239 001e FFF7FEFF bl CySysWdtClearInterrupt +1781:Generated_Source\PSoC4/CyLFClk.c **** } +1782:Generated_Source\PSoC4/CyLFClk.c **** else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) +1783:Generated_Source\PSoC4/CyLFClk.c **** { +1784:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtResetCounters(CY_SYS_WDT_COUNTER0_RESET); +1785:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); +1786:Generated_Source\PSoC4/CyLFClk.c **** } +1787:Generated_Source\PSoC4/CyLFClk.c **** else +1788:Generated_Source\PSoC4/CyLFClk.c **** { +1789:Generated_Source\PSoC4/CyLFClk.c **** /* Do nothing. */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 72 + + +1790:Generated_Source\PSoC4/CyLFClk.c **** } +1791:Generated_Source\PSoC4/CyLFClk.c **** } +1792:Generated_Source\PSoC4/CyLFClk.c **** else if(counterNum == CY_SYS_WDT_COUNTER1) +1793:Generated_Source\PSoC4/CyLFClk.c **** { +1794:Generated_Source\PSoC4/CyLFClk.c **** if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) +1795:Generated_Source\PSoC4/CyLFClk.c **** { +1796:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); +1797:Generated_Source\PSoC4/CyLFClk.c **** } +1798:Generated_Source\PSoC4/CyLFClk.c **** else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) +1799:Generated_Source\PSoC4/CyLFClk.c **** { +1800:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtResetCounters(CY_SYS_WDT_COUNTER1_RESET); +1801:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); +1802:Generated_Source\PSoC4/CyLFClk.c **** } +1803:Generated_Source\PSoC4/CyLFClk.c **** else +1804:Generated_Source\PSoC4/CyLFClk.c **** { +1805:Generated_Source\PSoC4/CyLFClk.c **** /* Do nothing. */ +1806:Generated_Source\PSoC4/CyLFClk.c **** } +1807:Generated_Source\PSoC4/CyLFClk.c **** } +1808:Generated_Source\PSoC4/CyLFClk.c **** else +1809:Generated_Source\PSoC4/CyLFClk.c **** { +1810:Generated_Source\PSoC4/CyLFClk.c **** /* Do nothing. */ +1811:Generated_Source\PSoC4/CyLFClk.c **** } +1812:Generated_Source\PSoC4/CyLFClk.c **** } + 2240 .loc 1 1812 0 + 2241 0022 2EE0 b .L195 + 2242 .L192: +1782:Generated_Source\PSoC4/CyLFClk.c **** { + 2243 .loc 1 1782 0 + 2244 0024 7B68 ldr r3, [r7, #4] + 2245 0026 1800 movs r0, r3 + 2246 0028 FFF7FEFF bl CySysWdtGetMode + 2247 002c 0300 movs r3, r0 + 2248 002e 022B cmp r3, #2 + 2249 0030 27D1 bne .L195 +1784:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + 2250 .loc 1 1784 0 + 2251 0032 0820 movs r0, #8 + 2252 0034 FFF7FEFF bl CySysWdtResetCounters +1785:Generated_Source\PSoC4/CyLFClk.c **** } + 2253 .loc 1 1785 0 + 2254 0038 0420 movs r0, #4 + 2255 003a FFF7FEFF bl CySysWdtClearInterrupt + 2256 .loc 1 1812 0 + 2257 003e 20E0 b .L195 + 2258 .L191: +1792:Generated_Source\PSoC4/CyLFClk.c **** { + 2259 .loc 1 1792 0 + 2260 0040 7B68 ldr r3, [r7, #4] + 2261 0042 012B cmp r3, #1 + 2262 0044 1DD1 bne .L195 +1794:Generated_Source\PSoC4/CyLFClk.c **** { + 2263 .loc 1 1794 0 + 2264 0046 7B68 ldr r3, [r7, #4] + 2265 0048 1800 movs r0, r3 + 2266 004a FFF7FEFF bl CySysWdtGetMode + 2267 004e 0300 movs r3, r0 + 2268 0050 032B cmp r3, #3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 73 + + + 2269 0052 05D1 bne .L194 +1796:Generated_Source\PSoC4/CyLFClk.c **** } + 2270 .loc 1 1796 0 + 2271 0054 8023 movs r3, #128 + 2272 0056 DB00 lsls r3, r3, #3 + 2273 0058 1800 movs r0, r3 + 2274 005a FFF7FEFF bl CySysWdtClearInterrupt + 2275 .loc 1 1812 0 + 2276 005e 10E0 b .L195 + 2277 .L194: +1798:Generated_Source\PSoC4/CyLFClk.c **** { + 2278 .loc 1 1798 0 + 2279 0060 7B68 ldr r3, [r7, #4] + 2280 0062 1800 movs r0, r3 + 2281 0064 FFF7FEFF bl CySysWdtGetMode + 2282 0068 0300 movs r3, r0 + 2283 006a 022B cmp r3, #2 + 2284 006c 09D1 bne .L195 +1800:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + 2285 .loc 1 1800 0 + 2286 006e 8023 movs r3, #128 + 2287 0070 1B01 lsls r3, r3, #4 + 2288 0072 1800 movs r0, r3 + 2289 0074 FFF7FEFF bl CySysWdtResetCounters +1801:Generated_Source\PSoC4/CyLFClk.c **** } + 2290 .loc 1 1801 0 + 2291 0078 8023 movs r3, #128 + 2292 007a DB00 lsls r3, r3, #3 + 2293 007c 1800 movs r0, r3 + 2294 007e FFF7FEFF bl CySysWdtClearInterrupt + 2295 .L195: + 2296 .loc 1 1812 0 + 2297 0082 C046 nop + 2298 0084 BD46 mov sp, r7 + 2299 0086 02B0 add sp, sp, #8 + 2300 @ sp needed + 2301 0088 80BD pop {r7, pc} + 2302 .cfi_endproc + 2303 .LFE31: + 2304 .size CySysWatchdogFeed, .-CySysWatchdogFeed + 2305 008a C046 .section .text.CySysClkLfclkPosedgeCatch,"ax",%progbits + 2306 .align 2 + 2307 .code 16 + 2308 .thumb_func + 2309 .type CySysClkLfclkPosedgeCatch, %function + 2310 CySysClkLfclkPosedgeCatch: + 2311 .LFB32: +1813:Generated_Source\PSoC4/CyLFClk.c **** +1814:Generated_Source\PSoC4/CyLFClk.c **** +1815:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1816:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkLfclkPosedgeCatch +1817:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1818:Generated_Source\PSoC4/CyLFClk.c **** * \internal +1819:Generated_Source\PSoC4/CyLFClk.c **** * Returns once the LFCLK positive edge occurred. +1820:Generated_Source\PSoC4/CyLFClk.c **** * +1821:Generated_Source\PSoC4/CyLFClk.c **** * CySysClkLfclkPosedgeRestore() should be called after this function +1822:Generated_Source\PSoC4/CyLFClk.c **** * to restore the WDT configuration. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 74 + + +1823:Generated_Source\PSoC4/CyLFClk.c **** * +1824:Generated_Source\PSoC4/CyLFClk.c **** * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() +1825:Generated_Source\PSoC4/CyLFClk.c **** * functions is expected to be called inside a critical section. +1826:Generated_Source\PSoC4/CyLFClk.c **** * +1827:Generated_Source\PSoC4/CyLFClk.c **** * To ensure that the WDT counter value is read until it changes, the enabled +1828:Generated_Source\PSoC4/CyLFClk.c **** * WDT counter is used. If no counter is enabled, counter 0 is enabled. +1829:Generated_Source\PSoC4/CyLFClk.c **** * And after the LFCLK source is switched, the counter 0 configuration +1830:Generated_Source\PSoC4/CyLFClk.c **** * is restored. +1831:Generated_Source\PSoC4/CyLFClk.c **** * +1832:Generated_Source\PSoC4/CyLFClk.c **** * Not applicable for the PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog +1833:Generated_Source\PSoC4/CyLFClk.c **** * Coprocessor devices. +1834:Generated_Source\PSoC4/CyLFClk.c **** * +1835:Generated_Source\PSoC4/CyLFClk.c **** * \details +1836:Generated_Source\PSoC4/CyLFClk.c **** * This function has no effect if WDT is locked (CySysWdtLock() is +1837:Generated_Source\PSoC4/CyLFClk.c **** * called). Call CySysWdtUnlock() to unlock WDT. +1838:Generated_Source\PSoC4/CyLFClk.c **** * \endinternal +1839:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1840:Generated_Source\PSoC4/CyLFClk.c **** static void CySysClkLfclkPosedgeCatch(void) +1841:Generated_Source\PSoC4/CyLFClk.c **** { + 2312 .loc 1 1841 0 + 2313 .cfi_startproc + 2314 @ args = 0, pretend = 0, frame = 8 + 2315 @ frame_needed = 1, uses_anonymous_args = 0 + 2316 0000 80B5 push {r7, lr} + 2317 .cfi_def_cfa_offset 8 + 2318 .cfi_offset 7, -8 + 2319 .cfi_offset 14, -4 + 2320 0002 82B0 sub sp, sp, #8 + 2321 .cfi_def_cfa_offset 16 + 2322 0004 00AF add r7, sp, #0 + 2323 .cfi_def_cfa_register 7 +1842:Generated_Source\PSoC4/CyLFClk.c **** uint32 firstCount; +1843:Generated_Source\PSoC4/CyLFClk.c **** static uint32 lfclkPosedgeEnabledWdtCounter = 0u; +1844:Generated_Source\PSoC4/CyLFClk.c **** +1845:Generated_Source\PSoC4/CyLFClk.c **** if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + 2324 .loc 1 1845 0 + 2325 0006 0020 movs r0, #0 + 2326 0008 FFF7FEFF bl CySysWdtGetEnabledStatus + 2327 000c 031E subs r3, r0, #0 + 2328 000e 03D0 beq .L197 +1846:Generated_Source\PSoC4/CyLFClk.c **** { +1847:Generated_Source\PSoC4/CyLFClk.c **** lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + 2329 .loc 1 1847 0 + 2330 0010 1E4B ldr r3, .L202 + 2331 0012 0022 movs r2, #0 + 2332 0014 1A60 str r2, [r3] + 2333 0016 24E0 b .L198 + 2334 .L197: +1848:Generated_Source\PSoC4/CyLFClk.c **** } +1849:Generated_Source\PSoC4/CyLFClk.c **** else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + 2335 .loc 1 1849 0 + 2336 0018 0120 movs r0, #1 + 2337 001a FFF7FEFF bl CySysWdtGetEnabledStatus + 2338 001e 031E subs r3, r0, #0 + 2339 0020 03D0 beq .L199 +1850:Generated_Source\PSoC4/CyLFClk.c **** { +1851:Generated_Source\PSoC4/CyLFClk.c **** lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER1; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 75 + + + 2340 .loc 1 1851 0 + 2341 0022 1A4B ldr r3, .L202 + 2342 0024 0122 movs r2, #1 + 2343 0026 1A60 str r2, [r3] + 2344 0028 1BE0 b .L198 + 2345 .L199: +1852:Generated_Source\PSoC4/CyLFClk.c **** } +1853:Generated_Source\PSoC4/CyLFClk.c **** else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + 2346 .loc 1 1853 0 + 2347 002a 0220 movs r0, #2 + 2348 002c FFF7FEFF bl CySysWdtGetEnabledStatus + 2349 0030 031E subs r3, r0, #0 + 2350 0032 03D0 beq .L200 +1854:Generated_Source\PSoC4/CyLFClk.c **** { +1855:Generated_Source\PSoC4/CyLFClk.c **** lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER2; + 2351 .loc 1 1855 0 + 2352 0034 154B ldr r3, .L202 + 2353 0036 0222 movs r2, #2 + 2354 0038 1A60 str r2, [r3] + 2355 003a 12E0 b .L198 + 2356 .L200: +1856:Generated_Source\PSoC4/CyLFClk.c **** } +1857:Generated_Source\PSoC4/CyLFClk.c **** else /* All WDT counters are disabled */ +1858:Generated_Source\PSoC4/CyLFClk.c **** { +1859:Generated_Source\PSoC4/CyLFClk.c **** /* Configure WDT counter # 0 */ +1860:Generated_Source\PSoC4/CyLFClk.c **** lfclkPosedgeWdtCounter0Enabled = 1u; + 2357 .loc 1 1860 0 + 2358 003c 144B ldr r3, .L202+4 + 2359 003e 0122 movs r2, #1 + 2360 0040 1A60 str r2, [r3] +1861:Generated_Source\PSoC4/CyLFClk.c **** lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + 2361 .loc 1 1861 0 + 2362 0042 124B ldr r3, .L202 + 2363 0044 0022 movs r2, #0 + 2364 0046 1A60 str r2, [r3] +1862:Generated_Source\PSoC4/CyLFClk.c **** +1863:Generated_Source\PSoC4/CyLFClk.c **** lfclkPosedgeWdtCounter0Mode = CySysWdtGetMode(CY_SYS_WDT_COUNTER0); + 2365 .loc 1 1863 0 + 2366 0048 0020 movs r0, #0 + 2367 004a FFF7FEFF bl CySysWdtGetMode + 2368 004e 0200 movs r2, r0 + 2369 0050 104B ldr r3, .L202+8 + 2370 0052 1A60 str r2, [r3] +1864:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtSetMode(CY_SYS_WDT_COUNTER0, CY_SYS_WDT_MODE_NONE); + 2371 .loc 1 1864 0 + 2372 0054 0021 movs r1, #0 + 2373 0056 0020 movs r0, #0 + 2374 0058 FFF7FEFF bl CySysWdtSetMode +1865:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK); + 2375 .loc 1 1865 0 + 2376 005c 0120 movs r0, #1 + 2377 005e FFF7FEFF bl CySysWdtEnable + 2378 .L198: +1866:Generated_Source\PSoC4/CyLFClk.c **** } +1867:Generated_Source\PSoC4/CyLFClk.c **** +1868:Generated_Source\PSoC4/CyLFClk.c **** firstCount = CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter); + 2379 .loc 1 1868 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 76 + + + 2380 0062 0A4B ldr r3, .L202 + 2381 0064 1B68 ldr r3, [r3] + 2382 0066 1800 movs r0, r3 + 2383 0068 FFF7FEFF bl CySysWdtGetCount + 2384 006c 0300 movs r3, r0 + 2385 006e 7B60 str r3, [r7, #4] +1869:Generated_Source\PSoC4/CyLFClk.c **** while (CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter) == firstCount) + 2386 .loc 1 1869 0 + 2387 0070 C046 nop + 2388 .L201: + 2389 .loc 1 1869 0 is_stmt 0 discriminator 1 + 2390 0072 064B ldr r3, .L202 + 2391 0074 1B68 ldr r3, [r3] + 2392 0076 1800 movs r0, r3 + 2393 0078 FFF7FEFF bl CySysWdtGetCount + 2394 007c 0200 movs r2, r0 + 2395 007e 7B68 ldr r3, [r7, #4] + 2396 0080 9A42 cmp r2, r3 + 2397 0082 F6D0 beq .L201 +1870:Generated_Source\PSoC4/CyLFClk.c **** { +1871:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for counter to increment */ +1872:Generated_Source\PSoC4/CyLFClk.c **** } +1873:Generated_Source\PSoC4/CyLFClk.c **** } + 2398 .loc 1 1873 0 is_stmt 1 + 2399 0084 C046 nop + 2400 0086 BD46 mov sp, r7 + 2401 0088 02B0 add sp, sp, #8 + 2402 @ sp needed + 2403 008a 80BD pop {r7, pc} + 2404 .L203: + 2405 .align 2 + 2406 .L202: + 2407 008c 1C000000 .word lfclkPosedgeEnabledWdtCounter.4967 + 2408 0090 00000000 .word lfclkPosedgeWdtCounter0Enabled + 2409 0094 04000000 .word lfclkPosedgeWdtCounter0Mode + 2410 .cfi_endproc + 2411 .LFE32: + 2412 .size CySysClkLfclkPosedgeCatch, .-CySysClkLfclkPosedgeCatch + 2413 .section .text.CySysClkLfclkPosedgeRestore,"ax",%progbits + 2414 .align 2 + 2415 .code 16 + 2416 .thumb_func + 2417 .type CySysClkLfclkPosedgeRestore, %function + 2418 CySysClkLfclkPosedgeRestore: + 2419 .LFB33: +1874:Generated_Source\PSoC4/CyLFClk.c **** +1875:Generated_Source\PSoC4/CyLFClk.c **** +1876:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1877:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkLfclkPosedgeRestore +1878:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1879:Generated_Source\PSoC4/CyLFClk.c **** * \internal +1880:Generated_Source\PSoC4/CyLFClk.c **** * Restores the WDT configuration after a CySysClkLfclkPosedgeCatch() call. +1881:Generated_Source\PSoC4/CyLFClk.c **** * +1882:Generated_Source\PSoC4/CyLFClk.c **** * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() +1883:Generated_Source\PSoC4/CyLFClk.c **** * functions is expected to be called inside a critical section. +1884:Generated_Source\PSoC4/CyLFClk.c **** * +1885:Generated_Source\PSoC4/CyLFClk.c **** * Not applicable for the PSoC 4000/PSoC 4000S / PSoC 4100S / PSoC Analog + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 77 + + +1886:Generated_Source\PSoC4/CyLFClk.c **** * Coprocessor devices. +1887:Generated_Source\PSoC4/CyLFClk.c **** * +1888:Generated_Source\PSoC4/CyLFClk.c **** * \details +1889:Generated_Source\PSoC4/CyLFClk.c **** * This function has no effect if WDT is locked (CySysWdtLock() is +1890:Generated_Source\PSoC4/CyLFClk.c **** * called). Call CySysWdtUnlock() to unlock WDT. +1891:Generated_Source\PSoC4/CyLFClk.c **** * +1892:Generated_Source\PSoC4/CyLFClk.c **** * \endinternal +1893:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1894:Generated_Source\PSoC4/CyLFClk.c **** static void CySysClkLfclkPosedgeRestore(void) +1895:Generated_Source\PSoC4/CyLFClk.c **** { + 2420 .loc 1 1895 0 + 2421 .cfi_startproc + 2422 @ args = 0, pretend = 0, frame = 0 + 2423 @ frame_needed = 1, uses_anonymous_args = 0 + 2424 0000 80B5 push {r7, lr} + 2425 .cfi_def_cfa_offset 8 + 2426 .cfi_offset 7, -8 + 2427 .cfi_offset 14, -4 + 2428 0002 00AF add r7, sp, #0 + 2429 .cfi_def_cfa_register 7 +1896:Generated_Source\PSoC4/CyLFClk.c **** if (lfclkPosedgeWdtCounter0Enabled != 0u) + 2430 .loc 1 1896 0 + 2431 0004 0A4B ldr r3, .L207 + 2432 0006 1B68 ldr r3, [r3] + 2433 0008 002B cmp r3, #0 + 2434 000a 0ED0 beq .L206 +1897:Generated_Source\PSoC4/CyLFClk.c **** { +1898:Generated_Source\PSoC4/CyLFClk.c **** /* Restore counter # 0 configuration and force its shutdown */ +1899:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_CONTROL_REG &= (uint32)(~CY_SYS_WDT_COUNTER0_MASK); + 2435 .loc 1 1899 0 + 2436 000c 094B ldr r3, .L207+4 + 2437 000e 094A ldr r2, .L207+4 + 2438 0010 1268 ldr r2, [r2] + 2439 0012 0121 movs r1, #1 + 2440 0014 8A43 bics r2, r1 + 2441 0016 1A60 str r2, [r3] +1900:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtSetMode(CY_SYS_WDT_COUNTER0, lfclkPosedgeWdtCounter0Mode); + 2442 .loc 1 1900 0 + 2443 0018 074B ldr r3, .L207+8 + 2444 001a 1B68 ldr r3, [r3] + 2445 001c 1900 movs r1, r3 + 2446 001e 0020 movs r0, #0 + 2447 0020 FFF7FEFF bl CySysWdtSetMode +1901:Generated_Source\PSoC4/CyLFClk.c **** lfclkPosedgeWdtCounter0Enabled = 0u; + 2448 .loc 1 1901 0 + 2449 0024 024B ldr r3, .L207 + 2450 0026 0022 movs r2, #0 + 2451 0028 1A60 str r2, [r3] + 2452 .L206: +1902:Generated_Source\PSoC4/CyLFClk.c **** } +1903:Generated_Source\PSoC4/CyLFClk.c **** } + 2453 .loc 1 1903 0 + 2454 002a C046 nop + 2455 002c BD46 mov sp, r7 + 2456 @ sp needed + 2457 002e 80BD pop {r7, pc} + 2458 .L208: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 78 + + + 2459 .align 2 + 2460 .L207: + 2461 0030 00000000 .word lfclkPosedgeWdtCounter0Enabled + 2462 0034 10020B40 .word 1074463248 + 2463 0038 04000000 .word lfclkPosedgeWdtCounter0Mode + 2464 .cfi_endproc + 2465 .LFE33: + 2466 .size CySysClkLfclkPosedgeRestore, .-CySysClkLfclkPosedgeRestore + 2467 .section .text.CySysTimerDelay,"ax",%progbits + 2468 .align 2 + 2469 .global CySysTimerDelay + 2470 .code 16 + 2471 .thumb_func + 2472 .type CySysTimerDelay, %function + 2473 CySysTimerDelay: + 2474 .LFB34: +1904:Generated_Source\PSoC4/CyLFClk.c **** +1905:Generated_Source\PSoC4/CyLFClk.c **** #else +1906:Generated_Source\PSoC4/CyLFClk.c **** +1907:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1908:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetEnabledStatus +1909:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1910:Generated_Source\PSoC4/CyLFClk.c **** * +1911:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the enabled status of the WDT counter. +1912:Generated_Source\PSoC4/CyLFClk.c **** * +1913:Generated_Source\PSoC4/CyLFClk.c **** * \return The status of the WDT counter: +1914:Generated_Source\PSoC4/CyLFClk.c **** * \return 0 - Counter is disabled +1915:Generated_Source\PSoC4/CyLFClk.c **** * \return 1 - Counter is enabled +1916:Generated_Source\PSoC4/CyLFClk.c **** * +1917:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1918:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetEnabledStatus(void) +1919:Generated_Source\PSoC4/CyLFClk.c **** { +1920:Generated_Source\PSoC4/CyLFClk.c **** return ((CY_SYS_WDT_DISABLE_KEY_REG == CY_SYS_WDT_KEY) ? (uint32) 0u : (uint32) 1u); +1921:Generated_Source\PSoC4/CyLFClk.c **** } +1922:Generated_Source\PSoC4/CyLFClk.c **** +1923:Generated_Source\PSoC4/CyLFClk.c **** +1924:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1925:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtEnable +1926:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1927:Generated_Source\PSoC4/CyLFClk.c **** * +1928:Generated_Source\PSoC4/CyLFClk.c **** * \brief +1929:Generated_Source\PSoC4/CyLFClk.c **** * Enables watchdog timer reset generation. +1930:Generated_Source\PSoC4/CyLFClk.c **** * +1931:Generated_Source\PSoC4/CyLFClk.c **** * CySysWdtClearInterrupt() feeds the watchdog. Two unserviced interrupts lead +1932:Generated_Source\PSoC4/CyLFClk.c **** * to a system reset (i.e. at the third match). +1933:Generated_Source\PSoC4/CyLFClk.c **** * +1934:Generated_Source\PSoC4/CyLFClk.c **** * ILO is enabled by the hardware once WDT is started. +1935:Generated_Source\PSoC4/CyLFClk.c **** * +1936:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1937:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtEnable(void) +1938:Generated_Source\PSoC4/CyLFClk.c **** { +1939:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_DISABLE_KEY_REG = 0u; +1940:Generated_Source\PSoC4/CyLFClk.c **** } +1941:Generated_Source\PSoC4/CyLFClk.c **** +1942:Generated_Source\PSoC4/CyLFClk.c **** +1943:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1944:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtDisable + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 79 + + +1945:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1946:Generated_Source\PSoC4/CyLFClk.c **** * +1947:Generated_Source\PSoC4/CyLFClk.c **** * \brief Disables the WDT reset generation. +1948:Generated_Source\PSoC4/CyLFClk.c **** * +1949:Generated_Source\PSoC4/CyLFClk.c **** * This function unlocks the ENABLE bit in the CLK_ILO_CONFIG registers and +1950:Generated_Source\PSoC4/CyLFClk.c **** * enables the user to disable ILO. +1951:Generated_Source\PSoC4/CyLFClk.c **** * +1952:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1953:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtDisable(void) +1954:Generated_Source\PSoC4/CyLFClk.c **** { +1955:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_DISABLE_KEY_REG = CY_SYS_WDT_KEY; +1956:Generated_Source\PSoC4/CyLFClk.c **** } +1957:Generated_Source\PSoC4/CyLFClk.c **** +1958:Generated_Source\PSoC4/CyLFClk.c **** +1959:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1960:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetMatch +1961:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1962:Generated_Source\PSoC4/CyLFClk.c **** * +1963:Generated_Source\PSoC4/CyLFClk.c **** * \brief Configures the WDT counter match comparison value. +1964:Generated_Source\PSoC4/CyLFClk.c **** * +1965:Generated_Source\PSoC4/CyLFClk.c **** * \param match Valid range [0-65535]. The value to be used to match against +1966:Generated_Source\PSoC4/CyLFClk.c **** * the counter. +1967:Generated_Source\PSoC4/CyLFClk.c **** * +1968:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1969:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtSetMatch(uint32 match) +1970:Generated_Source\PSoC4/CyLFClk.c **** { +1971:Generated_Source\PSoC4/CyLFClk.c **** match &= CY_SYS_WDT_MATCH_MASK; +1972:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_MATCH_MASK)) | match; +1973:Generated_Source\PSoC4/CyLFClk.c **** } +1974:Generated_Source\PSoC4/CyLFClk.c **** +1975:Generated_Source\PSoC4/CyLFClk.c **** +1976:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1977:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetMatch +1978:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1979:Generated_Source\PSoC4/CyLFClk.c **** * +1980:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the WDT counter match comparison value. +1981:Generated_Source\PSoC4/CyLFClk.c **** * +1982:Generated_Source\PSoC4/CyLFClk.c **** * \return The counter match value. +1983:Generated_Source\PSoC4/CyLFClk.c **** * +1984:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +1985:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetMatch(void) +1986:Generated_Source\PSoC4/CyLFClk.c **** { +1987:Generated_Source\PSoC4/CyLFClk.c **** return (CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_MATCH_MASK); +1988:Generated_Source\PSoC4/CyLFClk.c **** } +1989:Generated_Source\PSoC4/CyLFClk.c **** +1990:Generated_Source\PSoC4/CyLFClk.c **** +1991:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +1992:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetCount +1993:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +1994:Generated_Source\PSoC4/CyLFClk.c **** * +1995:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the current WDT counter value. +1996:Generated_Source\PSoC4/CyLFClk.c **** * +1997:Generated_Source\PSoC4/CyLFClk.c **** * \return A live counter value. +1998:Generated_Source\PSoC4/CyLFClk.c **** * +1999:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2000:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetCount(void) +2001:Generated_Source\PSoC4/CyLFClk.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 80 + + +2002:Generated_Source\PSoC4/CyLFClk.c **** return ((uint32)CY_SYS_WDT_COUNTER_REG); +2003:Generated_Source\PSoC4/CyLFClk.c **** } +2004:Generated_Source\PSoC4/CyLFClk.c **** +2005:Generated_Source\PSoC4/CyLFClk.c **** +2006:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2007:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetIgnoreBits +2008:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2009:Generated_Source\PSoC4/CyLFClk.c **** * +2010:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2011:Generated_Source\PSoC4/CyLFClk.c **** * Configures the number of the MSB bits of the watchdog timer that are not +2012:Generated_Source\PSoC4/CyLFClk.c **** * checked against the match. +2013:Generated_Source\PSoC4/CyLFClk.c **** * +2014:Generated_Source\PSoC4/CyLFClk.c **** * \param bitsNum Valid range [0-15]. The number of the MSB bits. +2015:Generated_Source\PSoC4/CyLFClk.c **** * +2016:Generated_Source\PSoC4/CyLFClk.c **** * \details The value of bitsNum controls the time-to-reset of the watchdog +2017:Generated_Source\PSoC4/CyLFClk.c **** * (which happens after 3 successive matches). +2018:Generated_Source\PSoC4/CyLFClk.c **** * +2019:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2020:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtSetIgnoreBits(uint32 bitsNum) +2021:Generated_Source\PSoC4/CyLFClk.c **** { +2022:Generated_Source\PSoC4/CyLFClk.c **** bitsNum = ((uint32)(bitsNum << CY_SYS_WDT_IGNORE_BITS_SHIFT) & CY_SYS_WDT_IGNORE_BITS_MASK) +2023:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_IGNORE_BITS_MASK)) | bi +2024:Generated_Source\PSoC4/CyLFClk.c **** } +2025:Generated_Source\PSoC4/CyLFClk.c **** +2026:Generated_Source\PSoC4/CyLFClk.c **** +2027:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2028:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetIgnoreBits +2029:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2030:Generated_Source\PSoC4/CyLFClk.c **** * +2031:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2032:Generated_Source\PSoC4/CyLFClk.c **** * Reads the number of the MSB bits of the watchdog timer that are not +2033:Generated_Source\PSoC4/CyLFClk.c **** * checked against the match. +2034:Generated_Source\PSoC4/CyLFClk.c **** * +2035:Generated_Source\PSoC4/CyLFClk.c **** * \return The number of the MSB bits. +2036:Generated_Source\PSoC4/CyLFClk.c **** * +2037:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2038:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysWdtGetIgnoreBits(void) +2039:Generated_Source\PSoC4/CyLFClk.c **** { +2040:Generated_Source\PSoC4/CyLFClk.c **** return((uint32)((CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_IGNORE_BITS_MASK) >> CY_SYS_WDT_IGNORE_B +2041:Generated_Source\PSoC4/CyLFClk.c **** } +2042:Generated_Source\PSoC4/CyLFClk.c **** +2043:Generated_Source\PSoC4/CyLFClk.c **** +2044:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2045:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtClearInterrupt +2046:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2047:Generated_Source\PSoC4/CyLFClk.c **** * +2048:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2049:Generated_Source\PSoC4/CyLFClk.c **** * Feeds the watchdog. +2050:Generated_Source\PSoC4/CyLFClk.c **** * Cleans the WDT match flag which is set every time the WDT counter reaches a +2051:Generated_Source\PSoC4/CyLFClk.c **** * WDT match value. Two unserviced interrupts lead to a system reset +2052:Generated_Source\PSoC4/CyLFClk.c **** * (i.e. at the third match). +2053:Generated_Source\PSoC4/CyLFClk.c **** * +2054:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2055:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtClearInterrupt(void) +2056:Generated_Source\PSoC4/CyLFClk.c **** { +2057:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_SRSS_INTR_REG |= CY_SYS_WDT_LOWER_BIT_MASK; +2058:Generated_Source\PSoC4/CyLFClk.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 81 + + +2059:Generated_Source\PSoC4/CyLFClk.c **** +2060:Generated_Source\PSoC4/CyLFClk.c **** +2061:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2062:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtMaskInterrupt +2063:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2064:Generated_Source\PSoC4/CyLFClk.c **** * +2065:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2066:Generated_Source\PSoC4/CyLFClk.c **** * After masking interrupts from WDT, they are not passed to CPU. +2067:Generated_Source\PSoC4/CyLFClk.c **** * This function does not disable WDT reset generation. +2068:Generated_Source\PSoC4/CyLFClk.c **** * +2069:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2070:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtMaskInterrupt(void) +2071:Generated_Source\PSoC4/CyLFClk.c **** { +2072:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_SRSS_INTR_MASK_REG &= (uint32)(~ (uint32)CY_SYS_WDT_LOWER_BIT_MASK); +2073:Generated_Source\PSoC4/CyLFClk.c **** } +2074:Generated_Source\PSoC4/CyLFClk.c **** +2075:Generated_Source\PSoC4/CyLFClk.c **** +2076:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2077:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtUnmaskInterrupt +2078:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2079:Generated_Source\PSoC4/CyLFClk.c **** * +2080:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2081:Generated_Source\PSoC4/CyLFClk.c **** * After unmasking interrupts from WDT, they are passed to CPU. +2082:Generated_Source\PSoC4/CyLFClk.c **** * This function does not impact the reset generation. +2083:Generated_Source\PSoC4/CyLFClk.c **** * +2084:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2085:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtUnmaskInterrupt(void) +2086:Generated_Source\PSoC4/CyLFClk.c **** { +2087:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_SRSS_INTR_MASK_REG |= CY_SYS_WDT_LOWER_BIT_MASK; +2088:Generated_Source\PSoC4/CyLFClk.c **** } +2089:Generated_Source\PSoC4/CyLFClk.c **** +2090:Generated_Source\PSoC4/CyLFClk.c **** +2091:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2092:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtSetIsrCallback +2093:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2094:Generated_Source\PSoC4/CyLFClk.c **** * +2095:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2096:Generated_Source\PSoC4/CyLFClk.c **** * Sets the ISR callback function for the WDT counter +2097:Generated_Source\PSoC4/CyLFClk.c **** * +2098:Generated_Source\PSoC4/CyLFClk.c **** * \param function The pointer to the callback function. +2099:Generated_Source\PSoC4/CyLFClk.c **** * +2100:Generated_Source\PSoC4/CyLFClk.c **** * \return The pointer to a previous callback function. +2101:Generated_Source\PSoC4/CyLFClk.c **** * +2102:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2103:Generated_Source\PSoC4/CyLFClk.c **** cyWdtCallback CySysWdtSetInterruptCallback(cyWdtCallback function) +2104:Generated_Source\PSoC4/CyLFClk.c **** { +2105:Generated_Source\PSoC4/CyLFClk.c **** cyWdtCallback prevCallback = (void *)0; +2106:Generated_Source\PSoC4/CyLFClk.c **** +2107:Generated_Source\PSoC4/CyLFClk.c **** prevCallback = cySysWdtCallback; +2108:Generated_Source\PSoC4/CyLFClk.c **** cySysWdtCallback = function; +2109:Generated_Source\PSoC4/CyLFClk.c **** +2110:Generated_Source\PSoC4/CyLFClk.c **** return(prevCallback); +2111:Generated_Source\PSoC4/CyLFClk.c **** } +2112:Generated_Source\PSoC4/CyLFClk.c **** +2113:Generated_Source\PSoC4/CyLFClk.c **** +2114:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2115:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtGetIsrCallback + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 82 + + +2116:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2117:Generated_Source\PSoC4/CyLFClk.c **** * +2118:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2119:Generated_Source\PSoC4/CyLFClk.c **** * Gets the ISR callback function for the WDT counter +2120:Generated_Source\PSoC4/CyLFClk.c **** * +2121:Generated_Source\PSoC4/CyLFClk.c **** * \return The pointer to the callback function registered for WDT. +2122:Generated_Source\PSoC4/CyLFClk.c **** * +2123:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2124:Generated_Source\PSoC4/CyLFClk.c **** cyWdtCallback CySysWdtGetInterruptCallback(void) +2125:Generated_Source\PSoC4/CyLFClk.c **** { +2126:Generated_Source\PSoC4/CyLFClk.c **** return(cySysWdtCallback); +2127:Generated_Source\PSoC4/CyLFClk.c **** } +2128:Generated_Source\PSoC4/CyLFClk.c **** +2129:Generated_Source\PSoC4/CyLFClk.c **** +2130:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2131:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysWdtIsr +2132:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2133:Generated_Source\PSoC4/CyLFClk.c **** * +2134:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2135:Generated_Source\PSoC4/CyLFClk.c **** * This is the handler of the WDT interrupt in CPU NVIC. +2136:Generated_Source\PSoC4/CyLFClk.c **** * +2137:Generated_Source\PSoC4/CyLFClk.c **** * The handler calls the respective callback functions configured by the user +2138:Generated_Source\PSoC4/CyLFClk.c **** * by using CySysWdtSetIsrCallback() API. +2139:Generated_Source\PSoC4/CyLFClk.c **** * +2140:Generated_Source\PSoC4/CyLFClk.c **** * +2141:Generated_Source\PSoC4/CyLFClk.c **** * \details +2142:Generated_Source\PSoC4/CyLFClk.c **** * This function clears the WDT interrupt every time when it is called. +2143:Generated_Source\PSoC4/CyLFClk.c **** * Reset after the 3rd interrupt does not happen if this function is registered +2144:Generated_Source\PSoC4/CyLFClk.c **** * as the interrupt handler even if the "Watchdog with Interrupt" mode is +2145:Generated_Source\PSoC4/CyLFClk.c **** * selected on the "Low Frequency Clocks" tab. +2146:Generated_Source\PSoC4/CyLFClk.c **** * +2147:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2148:Generated_Source\PSoC4/CyLFClk.c **** void CySysWdtIsr(void) +2149:Generated_Source\PSoC4/CyLFClk.c **** { +2150:Generated_Source\PSoC4/CyLFClk.c **** if(cySysWdtCallback != (void *) 0) +2151:Generated_Source\PSoC4/CyLFClk.c **** { +2152:Generated_Source\PSoC4/CyLFClk.c **** (void)(cySysWdtCallback)(); +2153:Generated_Source\PSoC4/CyLFClk.c **** } +2154:Generated_Source\PSoC4/CyLFClk.c **** +2155:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtClearInterrupt(); +2156:Generated_Source\PSoC4/CyLFClk.c **** } +2157:Generated_Source\PSoC4/CyLFClk.c **** +2158:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ +2159:Generated_Source\PSoC4/CyLFClk.c **** +2160:Generated_Source\PSoC4/CyLFClk.c **** +2161:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) +2162:Generated_Source\PSoC4/CyLFClk.c **** +2163:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2164:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkGetTimerSource +2165:Generated_Source\PSoC4/CyLFClk.c **** ******************************************************************************** +2166:Generated_Source\PSoC4/CyLFClk.c **** * +2167:Generated_Source\PSoC4/CyLFClk.c **** * \brief Gets the clock source for the DeepSleep Timers. +2168:Generated_Source\PSoC4/CyLFClk.c **** * +2169:Generated_Source\PSoC4/CyLFClk.c **** * The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor. +2170:Generated_Source\PSoC4/CyLFClk.c **** * +2171:Generated_Source\PSoC4/CyLFClk.c **** * \return The DeepSleep Timer source +2172:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_TIMER_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 83 + + +2173:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_TIMER_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) +2174:Generated_Source\PSoC4/CyLFClk.c **** * +2175:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2176:Generated_Source\PSoC4/CyLFClk.c **** static uint32 CySysClkGetTimerSource(void) +2177:Generated_Source\PSoC4/CyLFClk.c **** { +2178:Generated_Source\PSoC4/CyLFClk.c **** uint32 timerSource; +2179:Generated_Source\PSoC4/CyLFClk.c **** timerSource = CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK; +2180:Generated_Source\PSoC4/CyLFClk.c **** return (timerSource); +2181:Generated_Source\PSoC4/CyLFClk.c **** } +2182:Generated_Source\PSoC4/CyLFClk.c **** +2183:Generated_Source\PSoC4/CyLFClk.c **** +2184:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2185:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysClkSetTimerSource +2186:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2187:Generated_Source\PSoC4/CyLFClk.c **** * +2188:Generated_Source\PSoC4/CyLFClk.c **** * \brief Sets the clock source for the DeepSleep Timers. +2189:Generated_Source\PSoC4/CyLFClk.c **** * +2190:Generated_Source\PSoC4/CyLFClk.c **** * The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor +2191:Generated_Source\PSoC4/CyLFClk.c **** * devices. +2192:Generated_Source\PSoC4/CyLFClk.c **** * +2193:Generated_Source\PSoC4/CyLFClk.c **** * \param source +2194:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_TIMER_SRC_ILO - Internal Low Frequency (32 kHz) Oscillator +2195:Generated_Source\PSoC4/CyLFClk.c **** * (ILO).
+2196:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_CLK_TIMER_SRC_WCO - Low Frequency Watch Crystal Oscillator +2197:Generated_Source\PSoC4/CyLFClk.c **** * (WCO). +2198:Generated_Source\PSoC4/CyLFClk.c **** * +2199:Generated_Source\PSoC4/CyLFClk.c **** * \details Both the current source and the new source must be running and stable +2200:Generated_Source\PSoC4/CyLFClk.c **** * before calling this function. +2201:Generated_Source\PSoC4/CyLFClk.c **** * +2202:Generated_Source\PSoC4/CyLFClk.c **** * \warning DeepSleep Timer reset is required if Timer source was switched while +2203:Generated_Source\PSoC4/CyLFClk.c **** * DeepSleep Timers were running. Call CySysTimerResetCounters() API after +2204:Generated_Source\PSoC4/CyLFClk.c **** * Timer source switching. +2205:Generated_Source\PSoC4/CyLFClk.c **** * It is highly recommended to disable DeepSleep Timers before Timer source +2206:Generated_Source\PSoC4/CyLFClk.c **** * switching. Changing the Timer source may change the functionality that uses +2207:Generated_Source\PSoC4/CyLFClk.c **** * this Timers as clock source. +2208:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2209:Generated_Source\PSoC4/CyLFClk.c **** void CySysClkSetTimerSource(uint32 source) +2210:Generated_Source\PSoC4/CyLFClk.c **** { +2211:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; +2212:Generated_Source\PSoC4/CyLFClk.c **** +2213:Generated_Source\PSoC4/CyLFClk.c **** if (CySysClkGetTimerSource() != source) +2214:Generated_Source\PSoC4/CyLFClk.c **** { +2215:Generated_Source\PSoC4/CyLFClk.c **** +2216:Generated_Source\PSoC4/CyLFClk.c **** /* Reset both _EN bits in WCO_WDT_CLKEN register */ +2217:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CLKEN_REG &= ~CY_SYS_WCO_WDT_CLKEN_RESET_MASK; +2218:Generated_Source\PSoC4/CyLFClk.c **** +2219:Generated_Source\PSoC4/CyLFClk.c **** /* Wait 4 new clock source-cycles for change to come into effect */ +2220:Generated_Source\PSoC4/CyLFClk.c **** CyDelayUs(CY_SYS_4TIMER_DELAY_US); +2221:Generated_Source\PSoC4/CyLFClk.c **** +2222:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); +2223:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONFIG_REG = (CY_SYS_WCO_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_TIMER_SEL +2224:Generated_Source\PSoC4/CyLFClk.c **** (source & CY_SYS_CLK_TIMER_SEL_MASK); +2225:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); +2226:Generated_Source\PSoC4/CyLFClk.c **** } +2227:Generated_Source\PSoC4/CyLFClk.c **** +2228:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CLKEN_REG = (CY_SYS_WCO_WDT_CLKEN_REG & (uint32)(~CY_SYS_WCO_WDT_CLKEN_RESET +2229:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_SET_CURRENT_TIMER_SOURCE_BIT; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 84 + + +2230:Generated_Source\PSoC4/CyLFClk.c **** } +2231:Generated_Source\PSoC4/CyLFClk.c **** +2232:Generated_Source\PSoC4/CyLFClk.c **** +2233:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2234:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetEnabledStatus +2235:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2236:Generated_Source\PSoC4/CyLFClk.c **** * +2237:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the enabled status of one of the three DeepSleep Timer +2238:Generated_Source\PSoC4/CyLFClk.c **** * counters. +2239:Generated_Source\PSoC4/CyLFClk.c **** * +2240:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer +2241:Generated_Source\PSoC4/CyLFClk.c **** * counter. +2242:Generated_Source\PSoC4/CyLFClk.c **** * +2243:Generated_Source\PSoC4/CyLFClk.c **** * \return The status of the Timers counter: +2244:Generated_Source\PSoC4/CyLFClk.c **** * \return 0 - If the Counter is disabled. +2245:Generated_Source\PSoC4/CyLFClk.c **** * \return 1 - If the Counter is enabled. +2246:Generated_Source\PSoC4/CyLFClk.c **** * +2247:Generated_Source\PSoC4/CyLFClk.c **** * \details +2248:Generated_Source\PSoC4/CyLFClk.c **** * This function returns an actual DeepSleep Timer counter status from the +2249:Generated_Source\PSoC4/CyLFClk.c **** * status register. It may take up to 3 LFCLK cycles for the Timer status +2250:Generated_Source\PSoC4/CyLFClk.c **** * register to contain actual data after the Timer counter is enabled. +2251:Generated_Source\PSoC4/CyLFClk.c **** * +2252:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2253:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetEnabledStatus(uint32 counterNum) +2254:Generated_Source\PSoC4/CyLFClk.c **** { +2255:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); +2256:Generated_Source\PSoC4/CyLFClk.c **** return ((CY_SYS_WCO_WDT_CONTROL_REG >> ((CY_SYS_TIMER_CNT_SHIFT * counterNum) + +2257:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER_CNT_STTS_SHIFT)) & 0x01u); +2258:Generated_Source\PSoC4/CyLFClk.c **** } +2259:Generated_Source\PSoC4/CyLFClk.c **** +2260:Generated_Source\PSoC4/CyLFClk.c **** +2261:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2262:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerSetMode +2263:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2264:Generated_Source\PSoC4/CyLFClk.c **** * +2265:Generated_Source\PSoC4/CyLFClk.c **** * \brief Writes the mode of one of the three DeepSleep Timer counters. +2266:Generated_Source\PSoC4/CyLFClk.c **** * +2267:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer +2268:Generated_Source\PSoC4/CyLFClk.c **** * counter. +2269:Generated_Source\PSoC4/CyLFClk.c **** * +2270:Generated_Source\PSoC4/CyLFClk.c **** * \param mode +2271:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_MODE_NONE - Free running.
+2272:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_MODE_INT - The interrupt generated on match for counter 0 +2273:Generated_Source\PSoC4/CyLFClk.c **** * and 1, and on bit toggle for counter 2. +2274:Generated_Source\PSoC4/CyLFClk.c **** * +2275:Generated_Source\PSoC4/CyLFClk.c **** * \details +2276:Generated_Source\PSoC4/CyLFClk.c **** * DeepSleep Timer counter counterNum should be disabled to set a mode. +2277:Generated_Source\PSoC4/CyLFClk.c **** * Otherwise, this function call has no effect. If the specified counter is +2278:Generated_Source\PSoC4/CyLFClk.c **** * enabled, call the CySysTimerDisable() function with the corresponding +2279:Generated_Source\PSoC4/CyLFClk.c **** * parameter to disable the specified counter and wait for it to stop. +2280:Generated_Source\PSoC4/CyLFClk.c **** * +2281:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2282:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerSetMode(uint32 counterNum, uint32 mode) +2283:Generated_Source\PSoC4/CyLFClk.c **** { +2284:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; +2285:Generated_Source\PSoC4/CyLFClk.c **** +2286:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 85 + + +2287:Generated_Source\PSoC4/CyLFClk.c **** +2288:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(mode <= CY_SYS_TIMER_MODE_MASK); +2289:Generated_Source\PSoC4/CyLFClk.c **** +2290:Generated_Source\PSoC4/CyLFClk.c **** if(0u == CySysTimerGetEnabledStatus(counterNum)) +2291:Generated_Source\PSoC4/CyLFClk.c **** { +2292:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & +2293:Generated_Source\PSoC4/CyLFClk.c **** (uint32)~((uint32)(CY_SYS_TIMER_MODE_MASK << (counterNum * CY_SYS_T +2294:Generated_Source\PSoC4/CyLFClk.c **** configRegValue |= (uint32)((mode & CY_SYS_TIMER_MODE_MASK) << (counterNum * CY_SYS_TIME +2295:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; +2296:Generated_Source\PSoC4/CyLFClk.c **** } +2297:Generated_Source\PSoC4/CyLFClk.c **** } +2298:Generated_Source\PSoC4/CyLFClk.c **** +2299:Generated_Source\PSoC4/CyLFClk.c **** +2300:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2301:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetMode +2302:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2303:Generated_Source\PSoC4/CyLFClk.c **** * +2304:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the mode of one of the three DeepSleep Timer counters. +2305:Generated_Source\PSoC4/CyLFClk.c **** * +2306:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-2]. The number of the Timer counter. +2307:Generated_Source\PSoC4/CyLFClk.c **** * +2308:Generated_Source\PSoC4/CyLFClk.c **** * \return The mode of the counter. The same enumerated values as the mode +2309:Generated_Source\PSoC4/CyLFClk.c **** * parameter used in CySysTimerSetMode(). +2310:Generated_Source\PSoC4/CyLFClk.c **** * +2311:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2312:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetMode(uint32 counterNum) +2313:Generated_Source\PSoC4/CyLFClk.c **** { +2314:Generated_Source\PSoC4/CyLFClk.c **** return ((CY_SYS_WCO_WDT_CONFIG_REG >> (counterNum * CY_SYS_TIMER_CNT_SHIFT)) & CY_SYS_TIMER +2315:Generated_Source\PSoC4/CyLFClk.c **** } +2316:Generated_Source\PSoC4/CyLFClk.c **** +2317:Generated_Source\PSoC4/CyLFClk.c **** +2318:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2319:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerSetClearOnMatch +2320:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2321:Generated_Source\PSoC4/CyLFClk.c **** * +2322:Generated_Source\PSoC4/CyLFClk.c **** * \brief Configures the DeepSleep Timer counter "clear on match" setting. +2323:Generated_Source\PSoC4/CyLFClk.c **** * +2324:Generated_Source\PSoC4/CyLFClk.c **** * If configured to "clear on match", the counter counts from 0 to MatchValue +2325:Generated_Source\PSoC4/CyLFClk.c **** * giving it a period of (MatchValue + 1). +2326:Generated_Source\PSoC4/CyLFClk.c **** * +2327:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum +2328:Generated_Source\PSoC4/CyLFClk.c **** * Valid range [0-1]. The number of the Timer counter. The match values are not +2329:Generated_Source\PSoC4/CyLFClk.c **** * supported by counter 2. +2330:Generated_Source\PSoC4/CyLFClk.c **** * \param enable 0 to disable appropriate counter
+2331:Generated_Source\PSoC4/CyLFClk.c **** * 1 to enable appropriate counter +2332:Generated_Source\PSoC4/CyLFClk.c **** * +2333:Generated_Source\PSoC4/CyLFClk.c **** * \details +2334:Generated_Source\PSoC4/CyLFClk.c **** * Timer counter counterNum should be disabled. Otherwise this function call +2335:Generated_Source\PSoC4/CyLFClk.c **** * has no effect. If the specified counter is enabled, call the CySysTimerDisable() +2336:Generated_Source\PSoC4/CyLFClk.c **** * function with the corresponding parameter to disable the specified counter and +2337:Generated_Source\PSoC4/CyLFClk.c **** * wait for it to stop. This may take up to three Timer source-cycles. +2338:Generated_Source\PSoC4/CyLFClk.c **** * +2339:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2340:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerSetClearOnMatch(uint32 counterNum, uint32 enable) +2341:Generated_Source\PSoC4/CyLFClk.c **** { +2342:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; +2343:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 86 + + +2344:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_TIMER0) || +2345:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_TIMER1)); +2346:Generated_Source\PSoC4/CyLFClk.c **** +2347:Generated_Source\PSoC4/CyLFClk.c **** if(0u == CySysTimerGetEnabledStatus(counterNum)) +2348:Generated_Source\PSoC4/CyLFClk.c **** { +2349:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << +2350:Generated_Source\PSoC4/CyLFClk.c **** ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT))); +2351:Generated_Source\PSoC4/CyLFClk.c **** +2352:Generated_Source\PSoC4/CyLFClk.c **** configRegValue +2353:Generated_Source\PSoC4/CyLFClk.c **** |= (uint32)(enable << ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MAT +2354:Generated_Source\PSoC4/CyLFClk.c **** +2355:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; +2356:Generated_Source\PSoC4/CyLFClk.c **** } +2357:Generated_Source\PSoC4/CyLFClk.c **** } +2358:Generated_Source\PSoC4/CyLFClk.c **** +2359:Generated_Source\PSoC4/CyLFClk.c **** +2360:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2361:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetClearOnMatch +2362:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2363:Generated_Source\PSoC4/CyLFClk.c **** * +2364:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the "clear on match" setting for the specified DeepSleep Timer +2365:Generated_Source\PSoC4/CyLFClk.c **** * counter. +2366:Generated_Source\PSoC4/CyLFClk.c **** * +2367:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-1]. The number of the Timer counter. The +2368:Generated_Source\PSoC4/CyLFClk.c **** * match values are not supported by counter 2. +2369:Generated_Source\PSoC4/CyLFClk.c **** * +2370:Generated_Source\PSoC4/CyLFClk.c **** * \return The "clear on match" status:
1 if enabled
0 if disabled +2371:Generated_Source\PSoC4/CyLFClk.c **** * +2372:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2373:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetClearOnMatch(uint32 counterNum) +2374:Generated_Source\PSoC4/CyLFClk.c **** { +2375:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_TIMER0) || +2376:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_TIMER1)); +2377:Generated_Source\PSoC4/CyLFClk.c **** +2378:Generated_Source\PSoC4/CyLFClk.c **** return (uint32)((CY_SYS_WCO_WDT_CONFIG_REG >> +2379:Generated_Source\PSoC4/CyLFClk.c **** ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT)) +2380:Generated_Source\PSoC4/CyLFClk.c **** } +2381:Generated_Source\PSoC4/CyLFClk.c **** +2382:Generated_Source\PSoC4/CyLFClk.c **** +2383:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2384:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerEnable +2385:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2386:Generated_Source\PSoC4/CyLFClk.c **** * +2387:Generated_Source\PSoC4/CyLFClk.c **** * \brief Enables the specified DeepSleep Timer counters. All the counters +2388:Generated_Source\PSoC4/CyLFClk.c **** * specified in the mask are enabled. +2389:Generated_Source\PSoC4/CyLFClk.c **** * +2390:Generated_Source\PSoC4/CyLFClk.c **** * \param counterMask CY_SYS_TIMER0_MASK - The mask for counter 0 to enable.
+2391:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER1_MASK - The mask for counter 1 to enable.
+2392:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER2_MASK - The mask for counter 2 to enable. +2393:Generated_Source\PSoC4/CyLFClk.c **** * +2394:Generated_Source\PSoC4/CyLFClk.c **** * \details +2395:Generated_Source\PSoC4/CyLFClk.c **** * Enabling or disabling Timer requires 3 Timer source-cycles to come into effect. +2396:Generated_Source\PSoC4/CyLFClk.c **** * Therefore, the Timer enable state must not be changed more than once in +2397:Generated_Source\PSoC4/CyLFClk.c **** * that period. +2398:Generated_Source\PSoC4/CyLFClk.c **** * +2399:Generated_Source\PSoC4/CyLFClk.c **** * After Timer is enabled, it is illegal to write Timer configuration +2400:Generated_Source\PSoC4/CyLFClk.c **** * (WCO_WDT_CONFIG) and control (WCO_WDT_CONTROL) registers. This means that all + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 87 + + +2401:Generated_Source\PSoC4/CyLFClk.c **** * Timer functions that contain 'write' in the name (with the exception of +2402:Generated_Source\PSoC4/CyLFClk.c **** * CySysTimerSetMatch() function) are illegal to call once Timer enabled. +2403:Generated_Source\PSoC4/CyLFClk.c **** * +2404:Generated_Source\PSoC4/CyLFClk.c **** * Timer current source must be running and stable before calling this +2405:Generated_Source\PSoC4/CyLFClk.c **** * function. +2406:Generated_Source\PSoC4/CyLFClk.c **** * +2407:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2408:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerEnable(uint32 counterMask) +2409:Generated_Source\PSoC4/CyLFClk.c **** { +2410:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONTROL_REG |= counterMask; +2411:Generated_Source\PSoC4/CyLFClk.c **** +2412:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_TIMER0_MASK)) +2413:Generated_Source\PSoC4/CyLFClk.c **** { +2414:Generated_Source\PSoC4/CyLFClk.c **** while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) +2415:Generated_Source\PSoC4/CyLFClk.c **** { +2416:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +2417:Generated_Source\PSoC4/CyLFClk.c **** } +2418:Generated_Source\PSoC4/CyLFClk.c **** } +2419:Generated_Source\PSoC4/CyLFClk.c **** +2420:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_TIMER1_MASK)) +2421:Generated_Source\PSoC4/CyLFClk.c **** { +2422:Generated_Source\PSoC4/CyLFClk.c **** while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) +2423:Generated_Source\PSoC4/CyLFClk.c **** { +2424:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +2425:Generated_Source\PSoC4/CyLFClk.c **** } +2426:Generated_Source\PSoC4/CyLFClk.c **** } +2427:Generated_Source\PSoC4/CyLFClk.c **** +2428:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_TIMER2_MASK)) +2429:Generated_Source\PSoC4/CyLFClk.c **** { +2430:Generated_Source\PSoC4/CyLFClk.c **** while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) +2431:Generated_Source\PSoC4/CyLFClk.c **** { +2432:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +2433:Generated_Source\PSoC4/CyLFClk.c **** } +2434:Generated_Source\PSoC4/CyLFClk.c **** } +2435:Generated_Source\PSoC4/CyLFClk.c **** } +2436:Generated_Source\PSoC4/CyLFClk.c **** +2437:Generated_Source\PSoC4/CyLFClk.c **** +2438:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2439:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerDisable +2440:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2441:Generated_Source\PSoC4/CyLFClk.c **** * +2442:Generated_Source\PSoC4/CyLFClk.c **** * \brief Disables the specified DeepSleep Timer counters. +2443:Generated_Source\PSoC4/CyLFClk.c **** * +2444:Generated_Source\PSoC4/CyLFClk.c **** * All the counters specified in the mask are disabled. The function waits for +2445:Generated_Source\PSoC4/CyLFClk.c **** * the changes to come into effect. +2446:Generated_Source\PSoC4/CyLFClk.c **** * +2447:Generated_Source\PSoC4/CyLFClk.c **** * \param counterMask +2448:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER0_MASK - The mask for Counter 0 to disable.
+2449:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER1_MASK - The mask for Counter 1 to disable.
+2450:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER2_MASK - The mask for Counter 2 to disable. +2451:Generated_Source\PSoC4/CyLFClk.c **** * +2452:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2453:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerDisable(uint32 counterMask) +2454:Generated_Source\PSoC4/CyLFClk.c **** { +2455:Generated_Source\PSoC4/CyLFClk.c **** +2456:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONTROL_REG &= ~counterMask; +2457:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 88 + + +2458:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_TIMER0_MASK)) +2459:Generated_Source\PSoC4/CyLFClk.c **** { +2460:Generated_Source\PSoC4/CyLFClk.c **** while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) +2461:Generated_Source\PSoC4/CyLFClk.c **** { +2462:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +2463:Generated_Source\PSoC4/CyLFClk.c **** } +2464:Generated_Source\PSoC4/CyLFClk.c **** } +2465:Generated_Source\PSoC4/CyLFClk.c **** +2466:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_TIMER1_MASK)) +2467:Generated_Source\PSoC4/CyLFClk.c **** { +2468:Generated_Source\PSoC4/CyLFClk.c **** while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) +2469:Generated_Source\PSoC4/CyLFClk.c **** { +2470:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +2471:Generated_Source\PSoC4/CyLFClk.c **** } +2472:Generated_Source\PSoC4/CyLFClk.c **** } +2473:Generated_Source\PSoC4/CyLFClk.c **** +2474:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (counterMask & CY_SYS_TIMER2_MASK)) +2475:Generated_Source\PSoC4/CyLFClk.c **** { +2476:Generated_Source\PSoC4/CyLFClk.c **** while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) +2477:Generated_Source\PSoC4/CyLFClk.c **** { +2478:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for changes to come into effect */ +2479:Generated_Source\PSoC4/CyLFClk.c **** } +2480:Generated_Source\PSoC4/CyLFClk.c **** } +2481:Generated_Source\PSoC4/CyLFClk.c **** +2482:Generated_Source\PSoC4/CyLFClk.c **** } +2483:Generated_Source\PSoC4/CyLFClk.c **** +2484:Generated_Source\PSoC4/CyLFClk.c **** +2485:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2486:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerSetCascade +2487:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2488:Generated_Source\PSoC4/CyLFClk.c **** * +2489:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2490:Generated_Source\PSoC4/CyLFClk.c **** * Writes the two DeepSleep Timers cascade values based on the combination of +2491:Generated_Source\PSoC4/CyLFClk.c **** * mask values specified. +2492:Generated_Source\PSoC4/CyLFClk.c **** * +2493:Generated_Source\PSoC4/CyLFClk.c **** * \param cascadeMask The mask value used to set or clear the cascade values: +2494:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_CASCADE_NONE - Neither
+2495:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_CASCADE_01 - Cascade 01
+2496:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_CASCADE_12 - Cascade 12 +2497:Generated_Source\PSoC4/CyLFClk.c **** * +2498:Generated_Source\PSoC4/CyLFClk.c **** * If only one cascade mask is specified, the second cascade is disabled. +2499:Generated_Source\PSoC4/CyLFClk.c **** * To set both cascade modes, two defines should be ORed: +2500:Generated_Source\PSoC4/CyLFClk.c **** * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). +2501:Generated_Source\PSoC4/CyLFClk.c **** * \note If CySysTimerSetCascade() was called with ORed defines it is necessary +2502:Generated_Source\PSoC4/CyLFClk.c **** * to call CySysTimeSetClearOnMatch(1,1). It is needed to make sure that +2503:Generated_Source\PSoC4/CyLFClk.c **** * Counter 2 will be updated in the expected way. +2504:Generated_Source\PSoC4/CyLFClk.c **** * +2505:Generated_Source\PSoC4/CyLFClk.c **** * Timer counters that are part of the specified cascade should be disabled. +2506:Generated_Source\PSoC4/CyLFClk.c **** * Otherwise this function call has no effect. If the specified +2507:Generated_Source\PSoC4/CyLFClk.c **** * counter is enabled, call CySysTimerDisable() function with the corresponding +2508:Generated_Source\PSoC4/CyLFClk.c **** * parameter to disable the specified counter and wait for it to stop. This may +2509:Generated_Source\PSoC4/CyLFClk.c **** * take up to 3 Timers source-cycles. +2510:Generated_Source\PSoC4/CyLFClk.c **** * +2511:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2512:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerSetCascade(uint32 cascadeMask) +2513:Generated_Source\PSoC4/CyLFClk.c **** { +2514:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 89 + + +2515:Generated_Source\PSoC4/CyLFClk.c **** uint32 countersEnableStatus; +2516:Generated_Source\PSoC4/CyLFClk.c **** +2517:Generated_Source\PSoC4/CyLFClk.c **** countersEnableStatus = CySysTimerGetEnabledStatus(CY_SYS_TIMER0) | +2518:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerGetEnabledStatus(CY_SYS_TIMER1) | +2519:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerGetEnabledStatus(CY_SYS_TIMER2); +2520:Generated_Source\PSoC4/CyLFClk.c **** +2521:Generated_Source\PSoC4/CyLFClk.c **** if (0u == countersEnableStatus) +2522:Generated_Source\PSoC4/CyLFClk.c **** { +2523:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; +2524:Generated_Source\PSoC4/CyLFClk.c **** configRegValue &= ((uint32)(~(CY_SYS_TIMER_CASCADE_01|CY_SYS_TIMER_CASCADE_12))); +2525:Generated_Source\PSoC4/CyLFClk.c **** configRegValue |= cascadeMask; +2526:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; +2527:Generated_Source\PSoC4/CyLFClk.c **** } +2528:Generated_Source\PSoC4/CyLFClk.c **** } +2529:Generated_Source\PSoC4/CyLFClk.c **** +2530:Generated_Source\PSoC4/CyLFClk.c **** +2531:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2532:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetCascade +2533:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2534:Generated_Source\PSoC4/CyLFClk.c **** * +2535:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the two DeepSleep Timer cascade values returning a mask of the +2536:Generated_Source\PSoC4/CyLFClk.c **** * bits set. +2537:Generated_Source\PSoC4/CyLFClk.c **** * +2538:Generated_Source\PSoC4/CyLFClk.c **** * \return The mask of the cascade values set. +2539:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_TIMER_CASCADE_NONE - Neither +2540:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_TIMER_CASCADE_01 - Cascade 01 +2541:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_TIMER_CASCADE_12 - Cascade 12 +2542:Generated_Source\PSoC4/CyLFClk.c **** * +2543:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2544:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetCascade(void) +2545:Generated_Source\PSoC4/CyLFClk.c **** { +2546:Generated_Source\PSoC4/CyLFClk.c **** return (CY_SYS_WCO_WDT_CONFIG_REG & (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12)); +2547:Generated_Source\PSoC4/CyLFClk.c **** } +2548:Generated_Source\PSoC4/CyLFClk.c **** +2549:Generated_Source\PSoC4/CyLFClk.c **** +2550:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2551:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerSetMatch +2552:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2553:Generated_Source\PSoC4/CyLFClk.c **** * +2554:Generated_Source\PSoC4/CyLFClk.c **** * \brief Configures the Timer counter match comparison value. +2555:Generated_Source\PSoC4/CyLFClk.c **** * +2556:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-1]. The number of the Timer counter. The +2557:Generated_Source\PSoC4/CyLFClk.c **** * match values are not supported by counter 2. +2558:Generated_Source\PSoC4/CyLFClk.c **** * +2559:Generated_Source\PSoC4/CyLFClk.c **** * \param match Valid range [0-65535]. The value to be used to match against +2560:Generated_Source\PSoC4/CyLFClk.c **** * the counter. +2561:Generated_Source\PSoC4/CyLFClk.c **** * +2562:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2563:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerSetMatch(uint32 counterNum, uint32 match) +2564:Generated_Source\PSoC4/CyLFClk.c **** { +2565:Generated_Source\PSoC4/CyLFClk.c **** uint32 regValue; +2566:Generated_Source\PSoC4/CyLFClk.c **** +2567:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_TIMER0) || +2568:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_TIMER1)); +2569:Generated_Source\PSoC4/CyLFClk.c **** +2570:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for previous changes to come into effect */ +2571:Generated_Source\PSoC4/CyLFClk.c **** CyDelayUs(CY_SYS_3TIMER_DELAY_US); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 90 + + +2572:Generated_Source\PSoC4/CyLFClk.c **** +2573:Generated_Source\PSoC4/CyLFClk.c **** regValue = CY_SYS_WCO_WDT_MATCH_REG; +2574:Generated_Source\PSoC4/CyLFClk.c **** regValue &= (uint32)~((uint32)(CY_SYS_TIMER_LOWER_16BITS_MASK << (counterNum * CY_SYS_TIMER +2575:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT +2576:Generated_Source\PSoC4/CyLFClk.c **** +2577:Generated_Source\PSoC4/CyLFClk.c **** /* Make sure match synchronization has started */ +2578:Generated_Source\PSoC4/CyLFClk.c **** CyDelayUs(CY_SYS_1TIMER_DELAY_US); +2579:Generated_Source\PSoC4/CyLFClk.c **** } +2580:Generated_Source\PSoC4/CyLFClk.c **** +2581:Generated_Source\PSoC4/CyLFClk.c **** +2582:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2583:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerSetToggleBit +2584:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2585:Generated_Source\PSoC4/CyLFClk.c **** * +2586:Generated_Source\PSoC4/CyLFClk.c **** * \brief Configures which bit in Timer counter 2 to monitor for a toggle. +2587:Generated_Source\PSoC4/CyLFClk.c **** * +2588:Generated_Source\PSoC4/CyLFClk.c **** * When that bit toggles, an interrupt is generated if mode for counter 2 has +2589:Generated_Source\PSoC4/CyLFClk.c **** * enabled interrupts. +2590:Generated_Source\PSoC4/CyLFClk.c **** * +2591:Generated_Source\PSoC4/CyLFClk.c **** * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. +2592:Generated_Source\PSoC4/CyLFClk.c **** * +2593:Generated_Source\PSoC4/CyLFClk.c **** * \details Timer counter 2 should be disabled. Otherwise this function call has +2594:Generated_Source\PSoC4/CyLFClk.c **** * no effect. +2595:Generated_Source\PSoC4/CyLFClk.c **** * +2596:Generated_Source\PSoC4/CyLFClk.c **** * If the specified counter is enabled, call the CySysTimerDisable() function with +2597:Generated_Source\PSoC4/CyLFClk.c **** * the corresponding parameter to disable the specified counter and wait for it to +2598:Generated_Source\PSoC4/CyLFClk.c **** * stop. This may take up to three Timer source-cycles. +2599:Generated_Source\PSoC4/CyLFClk.c **** * +2600:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2601:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerSetToggleBit(uint32 bits) +2602:Generated_Source\PSoC4/CyLFClk.c **** { +2603:Generated_Source\PSoC4/CyLFClk.c **** uint32 configRegValue; +2604:Generated_Source\PSoC4/CyLFClk.c **** +2605:Generated_Source\PSoC4/CyLFClk.c **** if (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) +2606:Generated_Source\PSoC4/CyLFClk.c **** { +2607:Generated_Source\PSoC4/CyLFClk.c **** configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; +2608:Generated_Source\PSoC4/CyLFClk.c **** configRegValue &= (uint32)(~((uint32)(CY_SYS_TIMER_CONFIG_BITS2_MASK << CY_SYS_TIMER_CO +2609:Generated_Source\PSoC4/CyLFClk.c **** configRegValue |= ((bits & CY_SYS_TIMER_CONFIG_BITS2_MASK) << CY_SYS_TIMER_CONFIG_BITS2 +2610:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; +2611:Generated_Source\PSoC4/CyLFClk.c **** } +2612:Generated_Source\PSoC4/CyLFClk.c **** } +2613:Generated_Source\PSoC4/CyLFClk.c **** +2614:Generated_Source\PSoC4/CyLFClk.c **** +2615:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2616:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetToggleBit +2617:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2618:Generated_Source\PSoC4/CyLFClk.c **** * +2619:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads which bit in Timer counter 2 is monitored for a toggle. +2620:Generated_Source\PSoC4/CyLFClk.c **** * +2621:Generated_Source\PSoC4/CyLFClk.c **** * \return The bit that is monitored (range of 0 to 31) +2622:Generated_Source\PSoC4/CyLFClk.c **** * +2623:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2624:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetToggleBit(void) +2625:Generated_Source\PSoC4/CyLFClk.c **** { +2626:Generated_Source\PSoC4/CyLFClk.c **** return ((CY_SYS_WCO_WDT_CONFIG_REG >> CY_SYS_TIMER_CONFIG_BITS2_POS) & CY_SYS_TIMER_CONFIG_ +2627:Generated_Source\PSoC4/CyLFClk.c **** } +2628:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 91 + + +2629:Generated_Source\PSoC4/CyLFClk.c **** +2630:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2631:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetMatch +2632:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2633:Generated_Source\PSoC4/CyLFClk.c **** * +2634:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the Timer counter match comparison value. +2635:Generated_Source\PSoC4/CyLFClk.c **** * +2636:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-1]. The number of the DeepSleep Timer +2637:Generated_Source\PSoC4/CyLFClk.c **** * counter. The match values are not supported by counter 2. +2638:Generated_Source\PSoC4/CyLFClk.c **** * +2639:Generated_Source\PSoC4/CyLFClk.c **** * \return A 16-bit match value. +2640:Generated_Source\PSoC4/CyLFClk.c **** * +2641:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2642:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetMatch(uint32 counterNum) +2643:Generated_Source\PSoC4/CyLFClk.c **** { +2644:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT((counterNum == CY_SYS_TIMER0) || +2645:Generated_Source\PSoC4/CyLFClk.c **** (counterNum == CY_SYS_TIMER1)); +2646:Generated_Source\PSoC4/CyLFClk.c **** +2647:Generated_Source\PSoC4/CyLFClk.c **** return ((uint32)(CY_SYS_WCO_WDT_MATCH_REG >> (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT)) & +2648:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER_LOWER_16BITS_MASK); +2649:Generated_Source\PSoC4/CyLFClk.c **** } +2650:Generated_Source\PSoC4/CyLFClk.c **** +2651:Generated_Source\PSoC4/CyLFClk.c **** +2652:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2653:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetCount +2654:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2655:Generated_Source\PSoC4/CyLFClk.c **** * +2656:Generated_Source\PSoC4/CyLFClk.c **** * \brief Reads the current DeepSleep Timer counter value. +2657:Generated_Source\PSoC4/CyLFClk.c **** * +2658:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-2]. The number of the Timer counter. +2659:Generated_Source\PSoC4/CyLFClk.c **** * +2660:Generated_Source\PSoC4/CyLFClk.c **** * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters +2661:Generated_Source\PSoC4/CyLFClk.c **** * and counter 2 is a 32 bit counter. +2662:Generated_Source\PSoC4/CyLFClk.c **** * +2663:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2664:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetCount(uint32 counterNum) +2665:Generated_Source\PSoC4/CyLFClk.c **** { +2666:Generated_Source\PSoC4/CyLFClk.c **** uint32 regValue = 0u; +2667:Generated_Source\PSoC4/CyLFClk.c **** +2668:Generated_Source\PSoC4/CyLFClk.c **** switch(counterNum) +2669:Generated_Source\PSoC4/CyLFClk.c **** { +2670:Generated_Source\PSoC4/CyLFClk.c **** /* Timer Counter 0 */ +2671:Generated_Source\PSoC4/CyLFClk.c **** case 0u: +2672:Generated_Source\PSoC4/CyLFClk.c **** regValue = CY_SYS_WCO_WDT_CTRLOW_REG & CY_SYS_TIMER_LOWER_16BITS_MASK; +2673:Generated_Source\PSoC4/CyLFClk.c **** break; +2674:Generated_Source\PSoC4/CyLFClk.c **** +2675:Generated_Source\PSoC4/CyLFClk.c **** /* Timer Counter 1 */ +2676:Generated_Source\PSoC4/CyLFClk.c **** case 1u: +2677:Generated_Source\PSoC4/CyLFClk.c **** regValue = (CY_SYS_WCO_WDT_CTRLOW_REG >> CY_SYS_TIMER_CNT_MATCH_SHIFT) & CY_SYS_TIM +2678:Generated_Source\PSoC4/CyLFClk.c **** break; +2679:Generated_Source\PSoC4/CyLFClk.c **** +2680:Generated_Source\PSoC4/CyLFClk.c **** /* Timer Counter 2 */ +2681:Generated_Source\PSoC4/CyLFClk.c **** case 2u: +2682:Generated_Source\PSoC4/CyLFClk.c **** regValue = CY_SYS_WCO_WDT_CTRHIGH_REG; +2683:Generated_Source\PSoC4/CyLFClk.c **** break; +2684:Generated_Source\PSoC4/CyLFClk.c **** +2685:Generated_Source\PSoC4/CyLFClk.c **** default: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 92 + + +2686:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +2687:Generated_Source\PSoC4/CyLFClk.c **** break; +2688:Generated_Source\PSoC4/CyLFClk.c **** } +2689:Generated_Source\PSoC4/CyLFClk.c **** +2690:Generated_Source\PSoC4/CyLFClk.c **** return (regValue); +2691:Generated_Source\PSoC4/CyLFClk.c **** } +2692:Generated_Source\PSoC4/CyLFClk.c **** +2693:Generated_Source\PSoC4/CyLFClk.c **** +2694:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2695:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetInterruptSource +2696:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2697:Generated_Source\PSoC4/CyLFClk.c **** * +2698:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2699:Generated_Source\PSoC4/CyLFClk.c **** * Reads a mask containing all the DeepSleep Timer counters interrupts that are +2700:Generated_Source\PSoC4/CyLFClk.c **** * currently set by the hardware, if a corresponding mode is selected. +2701:Generated_Source\PSoC4/CyLFClk.c **** * +2702:Generated_Source\PSoC4/CyLFClk.c **** * \return The mask of interrupts set +2703:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_TIMER0_INT - Set interrupt for Counter 0 +2704:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_TIMER1_INT - Set interrupt for Counter 1 +2705:Generated_Source\PSoC4/CyLFClk.c **** * \return CY_SYS_TIMER2_INT - Set interrupt for Counter 2 +2706:Generated_Source\PSoC4/CyLFClk.c **** * +2707:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2708:Generated_Source\PSoC4/CyLFClk.c **** uint32 CySysTimerGetInterruptSource(void) +2709:Generated_Source\PSoC4/CyLFClk.c **** { +2710:Generated_Source\PSoC4/CyLFClk.c **** return (CY_SYS_WCO_WDT_CONTROL_REG & (CY_SYS_TIMER0_INT | CY_SYS_TIMER1_INT | CY_SYS_TIMER2 +2711:Generated_Source\PSoC4/CyLFClk.c **** } +2712:Generated_Source\PSoC4/CyLFClk.c **** +2713:Generated_Source\PSoC4/CyLFClk.c **** +2714:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2715:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerClearInterrupt +2716:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2717:Generated_Source\PSoC4/CyLFClk.c **** * +2718:Generated_Source\PSoC4/CyLFClk.c **** * \brief Clears all the DeepSleep Timer counter interrupts set in the mask. +2719:Generated_Source\PSoC4/CyLFClk.c **** * +2720:Generated_Source\PSoC4/CyLFClk.c **** * All the Timer interrupts are to be cleared by the firmware, otherwise +2721:Generated_Source\PSoC4/CyLFClk.c **** * interrupts are generated continuously. +2722:Generated_Source\PSoC4/CyLFClk.c **** * +2723:Generated_Source\PSoC4/CyLFClk.c **** * \param counterMask +2724:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER0_INT - Clear counter 0
+2725:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER1_INT - Clear counter 1
+2726:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER2_INT - Clear counter 2 +2727:Generated_Source\PSoC4/CyLFClk.c **** * +2728:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2729:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerClearInterrupt(uint32 counterMask) +2730:Generated_Source\PSoC4/CyLFClk.c **** { +2731:Generated_Source\PSoC4/CyLFClk.c **** uint8 interruptState; +2732:Generated_Source\PSoC4/CyLFClk.c **** interruptState = CyEnterCriticalSection(); +2733:Generated_Source\PSoC4/CyLFClk.c **** +2734:Generated_Source\PSoC4/CyLFClk.c **** /* Set new WCO_TIMER control register value */ +2735:Generated_Source\PSoC4/CyLFClk.c **** counterMask &= (CY_SYS_TIMER0_INT | +2736:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER1_INT | +2737:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER2_INT); +2738:Generated_Source\PSoC4/CyLFClk.c **** +2739:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONTROL_REG = counterMask | (CY_SYS_WCO_WDT_CONTROL_REG & ~(CY_SYS_TIMER0_IN +2740:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER1_INT | +2741:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_TIMER2_INT)); +2742:Generated_Source\PSoC4/CyLFClk.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 93 + + +2743:Generated_Source\PSoC4/CyLFClk.c **** /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. +2744:Generated_Source\PSoC4/CyLFClk.c **** * Cypress ID #207093, #206231 +2745:Generated_Source\PSoC4/CyLFClk.c **** */ +2746:Generated_Source\PSoC4/CyLFClk.c **** (void)CY_SYS_WCO_WDT_CONTROL_REG; +2747:Generated_Source\PSoC4/CyLFClk.c **** +2748:Generated_Source\PSoC4/CyLFClk.c **** CyExitCriticalSection(interruptState); +2749:Generated_Source\PSoC4/CyLFClk.c **** } +2750:Generated_Source\PSoC4/CyLFClk.c **** +2751:Generated_Source\PSoC4/CyLFClk.c **** +2752:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2753:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerSetInterruptCallback +2754:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2755:Generated_Source\PSoC4/CyLFClk.c **** * +2756:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2757:Generated_Source\PSoC4/CyLFClk.c **** * Sets the ISR callback function for the particular DeepSleep Timer counter. +2758:Generated_Source\PSoC4/CyLFClk.c **** * +2759:Generated_Source\PSoC4/CyLFClk.c **** * These functions are called on the Timer interrupt. +2760:Generated_Source\PSoC4/CyLFClk.c **** * +2761:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum The number of the Timer counter. +2762:Generated_Source\PSoC4/CyLFClk.c **** * \param function The pointer to the callback function. +2763:Generated_Source\PSoC4/CyLFClk.c **** * +2764:Generated_Source\PSoC4/CyLFClk.c **** * \return The pointer to the previous callback function. +2765:Generated_Source\PSoC4/CyLFClk.c **** * \return NULL is returned if the specified address is not set. +2766:Generated_Source\PSoC4/CyLFClk.c **** * +2767:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2768:Generated_Source\PSoC4/CyLFClk.c **** cyTimerCallback CySysTimerSetInterruptCallback(uint32 counterNum, cyTimerCallback function) +2769:Generated_Source\PSoC4/CyLFClk.c **** { +2770:Generated_Source\PSoC4/CyLFClk.c **** cyTimerCallback prevCallback = (void *)0; +2771:Generated_Source\PSoC4/CyLFClk.c **** +2772:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum < CY_SYS_NUM_OF_TIMERS) +2773:Generated_Source\PSoC4/CyLFClk.c **** { +2774:Generated_Source\PSoC4/CyLFClk.c **** prevCallback = cySysTimerCallback[counterNum]; +2775:Generated_Source\PSoC4/CyLFClk.c **** cySysTimerCallback[counterNum] = function; +2776:Generated_Source\PSoC4/CyLFClk.c **** } +2777:Generated_Source\PSoC4/CyLFClk.c **** else +2778:Generated_Source\PSoC4/CyLFClk.c **** { +2779:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +2780:Generated_Source\PSoC4/CyLFClk.c **** } +2781:Generated_Source\PSoC4/CyLFClk.c **** +2782:Generated_Source\PSoC4/CyLFClk.c **** return((cyTimerCallback)prevCallback); +2783:Generated_Source\PSoC4/CyLFClk.c **** } +2784:Generated_Source\PSoC4/CyLFClk.c **** +2785:Generated_Source\PSoC4/CyLFClk.c **** +2786:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2787:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerGetInterruptCallback +2788:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2789:Generated_Source\PSoC4/CyLFClk.c **** * +2790:Generated_Source\PSoC4/CyLFClk.c **** * \brief Gets the ISR callback function for the particular DeepSleep Timer +2791:Generated_Source\PSoC4/CyLFClk.c **** * counter. +2792:Generated_Source\PSoC4/CyLFClk.c **** * +2793:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum The number of the Timer counter. +2794:Generated_Source\PSoC4/CyLFClk.c **** * +2795:Generated_Source\PSoC4/CyLFClk.c **** * \return +2796:Generated_Source\PSoC4/CyLFClk.c **** * The pointer to the callback function registered for a particular Timer by +2797:Generated_Source\PSoC4/CyLFClk.c **** * a particular address that are passed through arguments. +2798:Generated_Source\PSoC4/CyLFClk.c **** * +2799:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 94 + + +2800:Generated_Source\PSoC4/CyLFClk.c **** cyTimerCallback CySysTimerGetInterruptCallback(uint32 counterNum) +2801:Generated_Source\PSoC4/CyLFClk.c **** { +2802:Generated_Source\PSoC4/CyLFClk.c **** cyTimerCallback retCallback = (void *)0; +2803:Generated_Source\PSoC4/CyLFClk.c **** +2804:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum < CY_SYS_NUM_OF_TIMERS) +2805:Generated_Source\PSoC4/CyLFClk.c **** { +2806:Generated_Source\PSoC4/CyLFClk.c **** retCallback = (cyTimerCallback)cySysTimerCallback[counterNum]; +2807:Generated_Source\PSoC4/CyLFClk.c **** } +2808:Generated_Source\PSoC4/CyLFClk.c **** else +2809:Generated_Source\PSoC4/CyLFClk.c **** { +2810:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +2811:Generated_Source\PSoC4/CyLFClk.c **** } +2812:Generated_Source\PSoC4/CyLFClk.c **** +2813:Generated_Source\PSoC4/CyLFClk.c **** return(retCallback); +2814:Generated_Source\PSoC4/CyLFClk.c **** } +2815:Generated_Source\PSoC4/CyLFClk.c **** +2816:Generated_Source\PSoC4/CyLFClk.c **** +2817:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2818:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerEnableIsr +2819:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2820:Generated_Source\PSoC4/CyLFClk.c **** * +2821:Generated_Source\PSoC4/CyLFClk.c **** * \brief Enables the ISR callback servicing for the particular Timer counter +2822:Generated_Source\PSoC4/CyLFClk.c **** * +2823:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-2]. The number of the Timer counter. +2824:Generated_Source\PSoC4/CyLFClk.c **** * +2825:Generated_Source\PSoC4/CyLFClk.c **** * Value corresponds to appropriate Timer counter. For example value 1 +2826:Generated_Source\PSoC4/CyLFClk.c **** * corresponds to second Timer counter. +2827:Generated_Source\PSoC4/CyLFClk.c **** * +2828:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2829:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerEnableIsr(uint32 counterNum) +2830:Generated_Source\PSoC4/CyLFClk.c **** { +2831:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum <= CY_SYS_TIMER2) +2832:Generated_Source\PSoC4/CyLFClk.c **** { +2833:Generated_Source\PSoC4/CyLFClk.c **** disableTimerServicedIsr &= ~counterTimerIntMaskTbl[counterNum]; +2834:Generated_Source\PSoC4/CyLFClk.c **** timerIsrMask |= counterTimerIntMaskTbl[counterNum]; +2835:Generated_Source\PSoC4/CyLFClk.c **** } +2836:Generated_Source\PSoC4/CyLFClk.c **** else +2837:Generated_Source\PSoC4/CyLFClk.c **** { +2838:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +2839:Generated_Source\PSoC4/CyLFClk.c **** } +2840:Generated_Source\PSoC4/CyLFClk.c **** } +2841:Generated_Source\PSoC4/CyLFClk.c **** +2842:Generated_Source\PSoC4/CyLFClk.c **** +2843:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2844:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerDisableIsr +2845:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2846:Generated_Source\PSoC4/CyLFClk.c **** * +2847:Generated_Source\PSoC4/CyLFClk.c **** * \brief Disables the ISR callback servicing for the particular Timer counter +2848:Generated_Source\PSoC4/CyLFClk.c **** * +2849:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-2]. The number of the Timer counter. +2850:Generated_Source\PSoC4/CyLFClk.c **** * +2851:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2852:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerDisableIsr(uint32 counterNum) +2853:Generated_Source\PSoC4/CyLFClk.c **** { +2854:Generated_Source\PSoC4/CyLFClk.c **** if(counterNum <= CY_SYS_TIMER2) +2855:Generated_Source\PSoC4/CyLFClk.c **** { +2856:Generated_Source\PSoC4/CyLFClk.c **** timerIsrMask &= ~counterTimerIntMaskTbl[counterNum]; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 95 + + +2857:Generated_Source\PSoC4/CyLFClk.c **** } +2858:Generated_Source\PSoC4/CyLFClk.c **** else +2859:Generated_Source\PSoC4/CyLFClk.c **** { +2860:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +2861:Generated_Source\PSoC4/CyLFClk.c **** } +2862:Generated_Source\PSoC4/CyLFClk.c **** } +2863:Generated_Source\PSoC4/CyLFClk.c **** +2864:Generated_Source\PSoC4/CyLFClk.c **** +2865:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2866:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerIsr +2867:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2868:Generated_Source\PSoC4/CyLFClk.c **** * +2869:Generated_Source\PSoC4/CyLFClk.c **** * \brief This is the handler of the DeepSleep Timer interrupt in CPU NVIC. +2870:Generated_Source\PSoC4/CyLFClk.c **** * +2871:Generated_Source\PSoC4/CyLFClk.c **** * The handler checks which Timer triggered in the interrupt and calls the +2872:Generated_Source\PSoC4/CyLFClk.c **** * respective callback functions configured by the user by using +2873:Generated_Source\PSoC4/CyLFClk.c **** * CySysTimerSetIsrCallback() API. +2874:Generated_Source\PSoC4/CyLFClk.c **** * +2875:Generated_Source\PSoC4/CyLFClk.c **** * The order of the callback execution is incremental. Callback-0 is +2876:Generated_Source\PSoC4/CyLFClk.c **** * run as the first one and callback-2 is called as the last one. +2877:Generated_Source\PSoC4/CyLFClk.c **** * +2878:Generated_Source\PSoC4/CyLFClk.c **** * \details This function clears the DeepSleep Timer interrupt every time when +2879:Generated_Source\PSoC4/CyLFClk.c **** * it is called. +2880:Generated_Source\PSoC4/CyLFClk.c **** * +2881:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2882:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerIsr(void) +2883:Generated_Source\PSoC4/CyLFClk.c **** { +2884:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_TIMER0_INT & CY_SYS_WCO_WDT_CONTROL_REG)) +2885:Generated_Source\PSoC4/CyLFClk.c **** { +2886:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_TIMER0_INT & timerIsrMask)) +2887:Generated_Source\PSoC4/CyLFClk.c **** { +2888:Generated_Source\PSoC4/CyLFClk.c **** timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER0_INT); +2889:Generated_Source\PSoC4/CyLFClk.c **** disableTimerServicedIsr &= ~CY_SYS_TIMER0_INT; +2890:Generated_Source\PSoC4/CyLFClk.c **** if(cySysTimerCallback[CY_SYS_TIMER0] != (void *) 0) +2891:Generated_Source\PSoC4/CyLFClk.c **** { +2892:Generated_Source\PSoC4/CyLFClk.c **** (void)(cySysTimerCallback[CY_SYS_TIMER0])(); +2893:Generated_Source\PSoC4/CyLFClk.c **** } +2894:Generated_Source\PSoC4/CyLFClk.c **** } +2895:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerClearInterrupt(CY_SYS_TIMER0_INT); +2896:Generated_Source\PSoC4/CyLFClk.c **** } +2897:Generated_Source\PSoC4/CyLFClk.c **** +2898:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_TIMER1_INT & CY_SYS_WCO_WDT_CONTROL_REG)) +2899:Generated_Source\PSoC4/CyLFClk.c **** { +2900:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_TIMER1_INT & timerIsrMask)) +2901:Generated_Source\PSoC4/CyLFClk.c **** { +2902:Generated_Source\PSoC4/CyLFClk.c **** timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER1_INT); +2903:Generated_Source\PSoC4/CyLFClk.c **** disableTimerServicedIsr &= ~CY_SYS_TIMER1_INT; +2904:Generated_Source\PSoC4/CyLFClk.c **** if(cySysTimerCallback[CY_SYS_TIMER1] != (void *) 0) +2905:Generated_Source\PSoC4/CyLFClk.c **** { +2906:Generated_Source\PSoC4/CyLFClk.c **** (void)(cySysTimerCallback[CY_SYS_TIMER1])(); +2907:Generated_Source\PSoC4/CyLFClk.c **** } +2908:Generated_Source\PSoC4/CyLFClk.c **** } +2909:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerClearInterrupt(CY_SYS_TIMER1_INT); +2910:Generated_Source\PSoC4/CyLFClk.c **** } +2911:Generated_Source\PSoC4/CyLFClk.c **** +2912:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_TIMER2_INT & CY_SYS_WCO_WDT_CONTROL_REG)) +2913:Generated_Source\PSoC4/CyLFClk.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 96 + + +2914:Generated_Source\PSoC4/CyLFClk.c **** if(0u != (CY_SYS_TIMER2_INT & timerIsrMask)) +2915:Generated_Source\PSoC4/CyLFClk.c **** { +2916:Generated_Source\PSoC4/CyLFClk.c **** if(cySysTimerCallback[CY_SYS_TIMER2] != (void *) 0) +2917:Generated_Source\PSoC4/CyLFClk.c **** { +2918:Generated_Source\PSoC4/CyLFClk.c **** (void)(cySysTimerCallback[CY_SYS_TIMER2])(); +2919:Generated_Source\PSoC4/CyLFClk.c **** } +2920:Generated_Source\PSoC4/CyLFClk.c **** } +2921:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerClearInterrupt(CY_SYS_TIMER2_INT); +2922:Generated_Source\PSoC4/CyLFClk.c **** } +2923:Generated_Source\PSoC4/CyLFClk.c **** } +2924:Generated_Source\PSoC4/CyLFClk.c **** +2925:Generated_Source\PSoC4/CyLFClk.c **** +2926:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2927:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerResetCounters +2928:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2929:Generated_Source\PSoC4/CyLFClk.c **** * +2930:Generated_Source\PSoC4/CyLFClk.c **** * \brief Resets all the Timer counters set in the mask. +2931:Generated_Source\PSoC4/CyLFClk.c **** * +2932:Generated_Source\PSoC4/CyLFClk.c **** * \param countersMask +2933:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER0_RESET - Reset the Counter 0
+2934:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER1_RESET - Reset the Counter 1
+2935:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER2_RESET - Reset the Counter 2 +2936:Generated_Source\PSoC4/CyLFClk.c **** * +2937:Generated_Source\PSoC4/CyLFClk.c **** * \details +2938:Generated_Source\PSoC4/CyLFClk.c **** * This function waits while corresponding counters will be reset. This may +2939:Generated_Source\PSoC4/CyLFClk.c **** * take up to 3 DeepSleep Timer source-cycles. DeepSleep Timer source must be +2940:Generated_Source\PSoC4/CyLFClk.c **** * enabled. Otherwise, the function will never exit. +2941:Generated_Source\PSoC4/CyLFClk.c **** * +2942:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +2943:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerResetCounters(uint32 countersMask) +2944:Generated_Source\PSoC4/CyLFClk.c **** { +2945:Generated_Source\PSoC4/CyLFClk.c **** /* Set new Timer reset value */ +2946:Generated_Source\PSoC4/CyLFClk.c **** CY_SYS_WCO_WDT_CONTROL_REG |= (countersMask & CY_SYS_TIMER_RESET); +2947:Generated_Source\PSoC4/CyLFClk.c **** +2948:Generated_Source\PSoC4/CyLFClk.c **** while (0uL != (CY_SYS_WCO_WDT_CONTROL_REG & CY_SYS_TIMER_RESET)) +2949:Generated_Source\PSoC4/CyLFClk.c **** { +2950:Generated_Source\PSoC4/CyLFClk.c **** /* Wait for reset to come into effect */ +2951:Generated_Source\PSoC4/CyLFClk.c **** } +2952:Generated_Source\PSoC4/CyLFClk.c **** } +2953:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ +2954:Generated_Source\PSoC4/CyLFClk.c **** +2955:Generated_Source\PSoC4/CyLFClk.c **** +2956:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2 || (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT)) +2957:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +2958:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerDelay +2959:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +2960:Generated_Source\PSoC4/CyLFClk.c **** * +2961:Generated_Source\PSoC4/CyLFClk.c **** * \brief +2962:Generated_Source\PSoC4/CyLFClk.c **** * The function implements the delay specified in the LFCLK clock ticks. +2963:Generated_Source\PSoC4/CyLFClk.c **** * +2964:Generated_Source\PSoC4/CyLFClk.c **** * This API is applicable for PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / +2965:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4200 BLE / PRoC BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to +2966:Generated_Source\PSoC4/CyLFClk.c **** * use WDT. Also this API is available to use for PSoC4100S and / PSoC Analog +2967:Generated_Source\PSoC4/CyLFClk.c **** * Coprocessor devices to use DeepSleep Timers. +2968:Generated_Source\PSoC4/CyLFClk.c **** * +2969:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC +2970:Generated_Source\PSoC4/CyLFClk.c **** * 4200L / PSoC 4100M / PSoC 4200M devices: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 97 + + +2971:Generated_Source\PSoC4/CyLFClk.c **** * The specified WDT counter should be configured as described below and started. +2972:Generated_Source\PSoC4/CyLFClk.c **** * +2973:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC 4100S / PSoC Analog Coprocessor devices: +2974:Generated_Source\PSoC4/CyLFClk.c **** * The specified DeepSleep Timer counter should be configured as described below +2975:Generated_Source\PSoC4/CyLFClk.c **** * and started. +2976:Generated_Source\PSoC4/CyLFClk.c **** * +2977:Generated_Source\PSoC4/CyLFClk.c **** * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In +2978:Generated_Source\PSoC4/CyLFClk.c **** * the "WAIT" mode, the function waits for the specified number of ticks. In the +2979:Generated_Source\PSoC4/CyLFClk.c **** * "INTERRUPT" mode, the interrupt is generated after the specified number of +2980:Generated_Source\PSoC4/CyLFClk.c **** * ticks. +2981:Generated_Source\PSoC4/CyLFClk.c **** * +2982:Generated_Source\PSoC4/CyLFClk.c **** * For the correct function operation, the "Clear On Match" option should be +2983:Generated_Source\PSoC4/CyLFClk.c **** * disabled for the specified WDT or DeepSleep Timer counter. Use +2984:Generated_Source\PSoC4/CyLFClk.c **** * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep +2985:Generated_Source\PSoC4/CyLFClk.c **** * Timer function with the "enable" parameter equal to zero for the used WDT +2986:Generated_Source\PSoC4/CyLFClk.c **** * counter or DeepSleep Timer counter. +2987:Generated_Source\PSoC4/CyLFClk.c **** * +2988:Generated_Source\PSoC4/CyLFClk.c **** * The corresponding WDT counter should be configured to match the selected +2989:Generated_Source\PSoC4/CyLFClk.c **** * mode: "Free running Timer" for the "WAIT" mode, and +2990:Generated_Source\PSoC4/CyLFClk.c **** * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. +2991:Generated_Source\PSoC4/CyLFClk.c **** * +2992:Generated_Source\PSoC4/CyLFClk.c **** * Or the corresponding DeepSleep Timer counter should be configured to match the +2993:Generated_Source\PSoC4/CyLFClk.c **** * selected mode: "Free running Timer" for the "WAIT" mode, and +2994:Generated_Source\PSoC4/CyLFClk.c **** * "Periodic Timer" for the "INTERRUPT" mode. +2995:Generated_Source\PSoC4/CyLFClk.c **** * +2996:Generated_Source\PSoC4/CyLFClk.c **** * This can be configured in two ways: +2997:Generated_Source\PSoC4/CyLFClk.c **** * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." +2998:Generated_Source\PSoC4/CyLFClk.c **** * button, in the "Configure System Clocks" window click on the +2999:Generated_Source\PSoC4/CyLFClk.c **** * "Low Frequency Clocks" tab and choose the appropriate option for the used +3000:Generated_Source\PSoC4/CyLFClk.c **** * WDT or DeepSleep Timer counter. +3001:Generated_Source\PSoC4/CyLFClk.c **** * +3002:Generated_Source\PSoC4/CyLFClk.c **** * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep +3003:Generated_Source\PSoC4/CyLFClk.c **** * Timer function. Call it with the appropriate "mode" parameter for the +3004:Generated_Source\PSoC4/CyLFClk.c **** * used WDT or DeepSleep Timer counter. +3005:Generated_Source\PSoC4/CyLFClk.c **** * +3006:Generated_Source\PSoC4/CyLFClk.c **** * For the "INTERRUPT" mode, the recommended sequence is the following: +3007:Generated_Source\PSoC4/CyLFClk.c **** * - Call the CySysWdtDisableCounterIsr() for WDT or +3008:Generated_Source\PSoC4/CyLFClk.c **** * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing +3009:Generated_Source\PSoC4/CyLFClk.c **** * interrupts of the specified WDT or DeepSleep Timer counter. +3010:Generated_Source\PSoC4/CyLFClk.c **** * +3011:Generated_Source\PSoC4/CyLFClk.c **** * - Call the CySysWdtSetInterruptCallback() for WDT or +3012:Generated_Source\PSoC4/CyLFClk.c **** * CySysTimerSetIsrCallback() for DeepSleep Timer function to register +3013:Generated_Source\PSoC4/CyLFClk.c **** * the callback function for the corresponding WDT or DeepSleep Timer counter. +3014:Generated_Source\PSoC4/CyLFClk.c **** * +3015:Generated_Source\PSoC4/CyLFClk.c **** * - Call the CySysTimerDelay() function. +3016:Generated_Source\PSoC4/CyLFClk.c **** * +3017:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-1]. The number of the counter +3018:Generated_Source\PSoC4/CyLFClk.c **** * (Timer0 or Timer1). +3019:Generated_Source\PSoC4/CyLFClk.c **** * \param delayType +3020:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_WAIT - "WAIT" mode.
+3021:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. +3022:Generated_Source\PSoC4/CyLFClk.c **** * \param delay The delay value in the LFCLK ticks +3023:Generated_Source\PSoC4/CyLFClk.c **** * (allowable range - 16-bit value). +3024:Generated_Source\PSoC4/CyLFClk.c **** * +3025:Generated_Source\PSoC4/CyLFClk.c **** * \details +3026:Generated_Source\PSoC4/CyLFClk.c **** * In the "INTERRUPT" mode, this function enables ISR callback servicing +3027:Generated_Source\PSoC4/CyLFClk.c **** * from the corresponding WDT or DeepSleep Timer counter. Servicing of this ISR + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 98 + + +3028:Generated_Source\PSoC4/CyLFClk.c **** * callback will be disabled after the expiration of the delay time. +3029:Generated_Source\PSoC4/CyLFClk.c **** * +3030:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +3031:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay) +3032:Generated_Source\PSoC4/CyLFClk.c **** { + 2475 .loc 1 3032 0 + 2476 .cfi_startproc + 2477 @ args = 0, pretend = 0, frame = 24 + 2478 @ frame_needed = 1, uses_anonymous_args = 0 + 2479 0000 80B5 push {r7, lr} + 2480 .cfi_def_cfa_offset 8 + 2481 .cfi_offset 7, -8 + 2482 .cfi_offset 14, -4 + 2483 0002 86B0 sub sp, sp, #24 + 2484 .cfi_def_cfa_offset 32 + 2485 0004 00AF add r7, sp, #0 + 2486 .cfi_def_cfa_register 7 + 2487 0006 F860 str r0, [r7, #12] + 2488 0008 7A60 str r2, [r7, #4] + 2489 000a 0B23 movs r3, #11 + 2490 000c FB18 adds r3, r7, r3 + 2491 000e 0A1C adds r2, r1, #0 + 2492 0010 1A70 strb r2, [r3] +3033:Generated_Source\PSoC4/CyLFClk.c **** uint32 regValue; +3034:Generated_Source\PSoC4/CyLFClk.c **** uint32 matchValue; +3035:Generated_Source\PSoC4/CyLFClk.c **** +3036:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) +3037:Generated_Source\PSoC4/CyLFClk.c **** if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) & + 2493 .loc 1 3037 0 + 2494 0012 FB68 ldr r3, [r7, #12] + 2495 0014 012B cmp r3, #1 + 2496 0016 1ED8 bhi .L210 + 2497 .loc 1 3037 0 is_stmt 0 discriminator 1 + 2498 0018 FB68 ldr r3, [r7, #12] + 2499 001a 1800 movs r0, r3 + 2500 001c FFF7FEFF bl CySysWdtGetClearOnMatch + 2501 0020 031E subs r3, r0, #0 + 2502 0022 18D1 bne .L210 + 2503 .loc 1 3037 0 discriminator 2 + 2504 0024 7B68 ldr r3, [r7, #4] + 2505 0026 0F4A ldr r2, .L212 + 2506 0028 9342 cmp r3, r2 + 2507 002a 14D8 bhi .L210 +3038:Generated_Source\PSoC4/CyLFClk.c **** (delay <= CY_SYS_UINT16_MAX_VAL)) +3039:Generated_Source\PSoC4/CyLFClk.c **** { +3040:Generated_Source\PSoC4/CyLFClk.c **** regValue = CySysWdtGetCount(counterNum); + 2508 .loc 1 3040 0 is_stmt 1 + 2509 002c FB68 ldr r3, [r7, #12] + 2510 002e 1800 movs r0, r3 + 2511 0030 FFF7FEFF bl CySysWdtGetCount + 2512 0034 0300 movs r3, r0 + 2513 0036 7B61 str r3, [r7, #20] +3041:Generated_Source\PSoC4/CyLFClk.c **** matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; + 2514 .loc 1 3041 0 + 2515 0038 7A69 ldr r2, [r7, #20] + 2516 003a 7B68 ldr r3, [r7, #4] + 2517 003c D318 adds r3, r2, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 99 + + + 2518 003e 1B04 lsls r3, r3, #16 + 2519 0040 1B0C lsrs r3, r3, #16 + 2520 0042 3B61 str r3, [r7, #16] +3042:Generated_Source\PSoC4/CyLFClk.c **** +3043:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); + 2521 .loc 1 3043 0 + 2522 0044 3A69 ldr r2, [r7, #16] + 2523 0046 0B23 movs r3, #11 + 2524 0048 FB18 adds r3, r7, r3 + 2525 004a 1978 ldrb r1, [r3] + 2526 004c FB68 ldr r3, [r7, #12] + 2527 004e 1800 movs r0, r3 + 2528 0050 FFF7FEFF bl CySysTimerDelayUntilMatch + 2529 0054 02E0 b .L211 + 2530 .L210: +3044:Generated_Source\PSoC4/CyLFClk.c **** } +3045:Generated_Source\PSoC4/CyLFClk.c **** else +3046:Generated_Source\PSoC4/CyLFClk.c **** { +3047:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); + 2531 .loc 1 3047 0 discriminator 1 + 2532 0056 0020 movs r0, #0 + 2533 0058 FFF7FEFF bl CyHalt + 2534 .L211: +3048:Generated_Source\PSoC4/CyLFClk.c **** } +3049:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ +3050:Generated_Source\PSoC4/CyLFClk.c **** +3051:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) +3052:Generated_Source\PSoC4/CyLFClk.c **** if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && +3053:Generated_Source\PSoC4/CyLFClk.c **** (delay <= CY_SYS_UINT16_MAX_VAL)) +3054:Generated_Source\PSoC4/CyLFClk.c **** { +3055:Generated_Source\PSoC4/CyLFClk.c **** regValue = CySysTimerGetCount(counterNum); +3056:Generated_Source\PSoC4/CyLFClk.c **** matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; +3057:Generated_Source\PSoC4/CyLFClk.c **** +3058:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); +3059:Generated_Source\PSoC4/CyLFClk.c **** } +3060:Generated_Source\PSoC4/CyLFClk.c **** else +3061:Generated_Source\PSoC4/CyLFClk.c **** { +3062:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +3063:Generated_Source\PSoC4/CyLFClk.c **** } +3064:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_WCO_WDT_EN) */ +3065:Generated_Source\PSoC4/CyLFClk.c **** } + 2535 .loc 1 3065 0 + 2536 005c C046 nop + 2537 005e BD46 mov sp, r7 + 2538 0060 06B0 add sp, sp, #24 + 2539 @ sp needed + 2540 0062 80BD pop {r7, pc} + 2541 .L213: + 2542 .align 2 + 2543 .L212: + 2544 0064 FFFF0000 .word 65535 + 2545 .cfi_endproc + 2546 .LFE34: + 2547 .size CySysTimerDelay, .-CySysTimerDelay + 2548 .section .text.CySysTimerDelayUntilMatch,"ax",%progbits + 2549 .align 2 + 2550 .global CySysTimerDelayUntilMatch + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 100 + + + 2551 .code 16 + 2552 .thumb_func + 2553 .type CySysTimerDelayUntilMatch, %function + 2554 CySysTimerDelayUntilMatch: + 2555 .LFB35: +3066:Generated_Source\PSoC4/CyLFClk.c **** +3067:Generated_Source\PSoC4/CyLFClk.c **** +3068:Generated_Source\PSoC4/CyLFClk.c **** /******************************************************************************* +3069:Generated_Source\PSoC4/CyLFClk.c **** * Function Name: CySysTimerDelayUntilMatch +3070:Generated_Source\PSoC4/CyLFClk.c **** ****************************************************************************//** +3071:Generated_Source\PSoC4/CyLFClk.c **** * +3072:Generated_Source\PSoC4/CyLFClk.c **** * \brief +3073:Generated_Source\PSoC4/CyLFClk.c **** * The function implements the delay specified as the number of WDT or DeepSleep +3074:Generated_Source\PSoC4/CyLFClk.c **** * Timer clock source ticks between WDT or DeepSleep Timer current value and +3075:Generated_Source\PSoC4/CyLFClk.c **** * match" value. +3076:Generated_Source\PSoC4/CyLFClk.c **** * +3077:Generated_Source\PSoC4/CyLFClk.c **** * This API is applicable for PSoC 4100 / PSoC 4200 / PRoC BLE / PSoC 4100 BLE / +3078:Generated_Source\PSoC4/CyLFClk.c **** * PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to use WDT. +3079:Generated_Source\PSoC4/CyLFClk.c **** * Also this API is available to use for PSoC4100S / Analog Coprocessor devices +3080:Generated_Source\PSoC4/CyLFClk.c **** * to use DeepSleep Timers. +3081:Generated_Source\PSoC4/CyLFClk.c **** * +3082:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC +3083:Generated_Source\PSoC4/CyLFClk.c **** * 4200L / PSoC 4100M / PSoC 4200M devices: +3084:Generated_Source\PSoC4/CyLFClk.c **** * The function implements the delay specified as the number of LFCLK ticks +3085:Generated_Source\PSoC4/CyLFClk.c **** * between the specified WDT counter's current value and the "match" +3086:Generated_Source\PSoC4/CyLFClk.c **** * passed as the parameter to this function. The current WDT counter value can +3087:Generated_Source\PSoC4/CyLFClk.c **** * be obtained using the CySysWdtGetCount() function. +3088:Generated_Source\PSoC4/CyLFClk.c **** * +3089:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC4100 S and Analog Coprocessor devices: +3090:Generated_Source\PSoC4/CyLFClk.c **** * The function implements the delay specified as the number of DeepSleep Timer +3091:Generated_Source\PSoC4/CyLFClk.c **** * input clock ticks for Timer0/Timer1 counter's current value and the "match" +3092:Generated_Source\PSoC4/CyLFClk.c **** * passed as the parameter to this function. The current DeepSleep Timer counter +3093:Generated_Source\PSoC4/CyLFClk.c **** * value can be obtained using the CySysWdtGetCount() function. +3094:Generated_Source\PSoC4/CyLFClk.c **** * +3095:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC +3096:Generated_Source\PSoC4/CyLFClk.c **** * 4200L / PSoC 4100M / PSoC 4200M devices: +3097:Generated_Source\PSoC4/CyLFClk.c **** * The specified WDT counter should be configured as described below and started. +3098:Generated_Source\PSoC4/CyLFClk.c **** * +3099:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC PSoC 4100S / PSoC Analog Coprocessor devices: +3100:Generated_Source\PSoC4/CyLFClk.c **** * The specified DeepSleep Timer counter should be configured as described below +3101:Generated_Source\PSoC4/CyLFClk.c **** * and started. +3102:Generated_Source\PSoC4/CyLFClk.c **** * +3103:Generated_Source\PSoC4/CyLFClk.c **** * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In +3104:Generated_Source\PSoC4/CyLFClk.c **** * the "WAIT" mode, the function waits for the specified number of ticks. In the +3105:Generated_Source\PSoC4/CyLFClk.c **** * "INTERRUPT" mode, the interrupt is generated after the specified number of +3106:Generated_Source\PSoC4/CyLFClk.c **** * ticks. +3107:Generated_Source\PSoC4/CyLFClk.c **** * +3108:Generated_Source\PSoC4/CyLFClk.c **** * For the correct function operation, the "Clear On Match" option should be +3109:Generated_Source\PSoC4/CyLFClk.c **** * disabled for the specified WDT or DeepSleep Timer counter. Use +3110:Generated_Source\PSoC4/CyLFClk.c **** * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep +3111:Generated_Source\PSoC4/CyLFClk.c **** * Timer function with the "enable" parameter equal to zero for the used WDT +3112:Generated_Source\PSoC4/CyLFClk.c **** * or DeepSleep Timer counter. +3113:Generated_Source\PSoC4/CyLFClk.c **** * +3114:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC +3115:Generated_Source\PSoC4/CyLFClk.c **** * 4200L / PSoC 4100M/PSoC 4200M devices: +3116:Generated_Source\PSoC4/CyLFClk.c **** * The corresponding WDT counter should be configured to match the selected +3117:Generated_Source\PSoC4/CyLFClk.c **** * mode: "Free running Timer" for the "WAIT" mode, and + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 101 + + +3118:Generated_Source\PSoC4/CyLFClk.c **** * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. +3119:Generated_Source\PSoC4/CyLFClk.c **** * +3120:Generated_Source\PSoC4/CyLFClk.c **** * For PSoC 4100S / PSoC Analog Coprocessor devices: +3121:Generated_Source\PSoC4/CyLFClk.c **** * Corresponding DeepSleep Timer counter should be configured to match the +3122:Generated_Source\PSoC4/CyLFClk.c **** * selected mode: "Free running Timer" for the "WAIT" mode, and +3123:Generated_Source\PSoC4/CyLFClk.c **** * "Periodic Timer" for the "INTERRUPT" mode. +3124:Generated_Source\PSoC4/CyLFClk.c **** * +3125:Generated_Source\PSoC4/CyLFClk.c **** * This can be configured in two ways: +3126:Generated_Source\PSoC4/CyLFClk.c **** * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." +3127:Generated_Source\PSoC4/CyLFClk.c **** * button, in the "Configure System Clocks" window click on the +3128:Generated_Source\PSoC4/CyLFClk.c **** * "Low Frequency Clocks" tab and choose the appropriate option for the used +3129:Generated_Source\PSoC4/CyLFClk.c **** * WDT or DeepSleep Timer counter. +3130:Generated_Source\PSoC4/CyLFClk.c **** * +3131:Generated_Source\PSoC4/CyLFClk.c **** * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep +3132:Generated_Source\PSoC4/CyLFClk.c **** * Timer function. Call it with the appropriate "mode" parameter for the +3133:Generated_Source\PSoC4/CyLFClk.c **** * used WDT or DeepSleep Timer counter. +3134:Generated_Source\PSoC4/CyLFClk.c **** * +3135:Generated_Source\PSoC4/CyLFClk.c **** * For the "INTERRUPT" mode, the recommended sequence is the following: +3136:Generated_Source\PSoC4/CyLFClk.c **** * - Call the CySysWdtDisableCounterIsr() for WDT or +3137:Generated_Source\PSoC4/CyLFClk.c **** * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing +3138:Generated_Source\PSoC4/CyLFClk.c **** * interrupts of the specified WDT or DeepSleep Timer counter. +3139:Generated_Source\PSoC4/CyLFClk.c **** * +3140:Generated_Source\PSoC4/CyLFClk.c **** * - Call the CySysWdtSetInterruptCallback() for WDT or +3141:Generated_Source\PSoC4/CyLFClk.c **** * CySysTimerSetInterruptCallback() for DeepSleep Timer function to register +3142:Generated_Source\PSoC4/CyLFClk.c **** * the callback function for the corresponding WDT or DeepSleep Timer counter. +3143:Generated_Source\PSoC4/CyLFClk.c **** * +3144:Generated_Source\PSoC4/CyLFClk.c **** * - Call the CySysTimerDelay() function. +3145:Generated_Source\PSoC4/CyLFClk.c **** * +3146:Generated_Source\PSoC4/CyLFClk.c **** * \param counterNum Valid range [0-1]. The number of the WDT or DeepSleep +3147:Generated_Source\PSoC4/CyLFClk.c **** * Timer. +3148:Generated_Source\PSoC4/CyLFClk.c **** * counter (Timer0 or Timer1). +3149:Generated_Source\PSoC4/CyLFClk.c **** * \param delayType CY_SYS_TIMER_WAIT - "WAIT" mode.
+3150:Generated_Source\PSoC4/CyLFClk.c **** * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. +3151:Generated_Source\PSoC4/CyLFClk.c **** * \param delay The delay value in the LFCLK ticks +3152:Generated_Source\PSoC4/CyLFClk.c **** * (allowable range - 16-bit value). +3153:Generated_Source\PSoC4/CyLFClk.c **** * +3154:Generated_Source\PSoC4/CyLFClk.c **** * \details +3155:Generated_Source\PSoC4/CyLFClk.c **** * In the "INTERRUPT" mode, this function enables ISR callback servicing +3156:Generated_Source\PSoC4/CyLFClk.c **** * from the corresponding WDT counter. Servicing of this ISR callback will be +3157:Generated_Source\PSoC4/CyLFClk.c **** * disabled after the expiration of the delay time. +3158:Generated_Source\PSoC4/CyLFClk.c **** * +3159:Generated_Source\PSoC4/CyLFClk.c **** *******************************************************************************/ +3160:Generated_Source\PSoC4/CyLFClk.c **** void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 +3161:Generated_Source\PSoC4/CyLFClk.c **** { + 2556 .loc 1 3161 0 + 2557 .cfi_startproc + 2558 @ args = 0, pretend = 0, frame = 24 + 2559 @ frame_needed = 1, uses_anonymous_args = 0 + 2560 0000 80B5 push {r7, lr} + 2561 .cfi_def_cfa_offset 8 + 2562 .cfi_offset 7, -8 + 2563 .cfi_offset 14, -4 + 2564 0002 86B0 sub sp, sp, #24 + 2565 .cfi_def_cfa_offset 32 + 2566 0004 00AF add r7, sp, #0 + 2567 .cfi_def_cfa_register 7 + 2568 0006 F860 str r0, [r7, #12] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 102 + + + 2569 0008 7A60 str r2, [r7, #4] + 2570 000a 0B23 movs r3, #11 + 2571 000c FB18 adds r3, r7, r3 + 2572 000e 0A1C adds r2, r1, #0 + 2573 0010 1A70 strb r2, [r3] +3162:Generated_Source\PSoC4/CyLFClk.c **** uint32 tmpValue; +3163:Generated_Source\PSoC4/CyLFClk.c **** +3164:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_SRSSV2) +3165:Generated_Source\PSoC4/CyLFClk.c **** if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) & + 2574 .loc 1 3165 0 + 2575 0012 FB68 ldr r3, [r7, #12] + 2576 0014 012B cmp r3, #1 + 2577 0016 3BD8 bhi .L215 + 2578 .loc 1 3165 0 is_stmt 0 discriminator 1 + 2579 0018 FB68 ldr r3, [r7, #12] + 2580 001a 1800 movs r0, r3 + 2581 001c FFF7FEFF bl CySysWdtGetClearOnMatch + 2582 0020 031E subs r3, r0, #0 + 2583 0022 35D1 bne .L215 + 2584 .loc 1 3165 0 discriminator 2 + 2585 0024 7B68 ldr r3, [r7, #4] + 2586 0026 1E4A ldr r2, .L221 + 2587 0028 9342 cmp r3, r2 + 2588 002a 31D8 bhi .L215 +3166:Generated_Source\PSoC4/CyLFClk.c **** (match <= CY_SYS_UINT16_MAX_VAL)) +3167:Generated_Source\PSoC4/CyLFClk.c **** { +3168:Generated_Source\PSoC4/CyLFClk.c **** if(delayType == CY_SYS_TIMER_WAIT) + 2589 .loc 1 3168 0 is_stmt 1 + 2590 002c 0B23 movs r3, #11 + 2591 002e FB18 adds r3, r7, r3 + 2592 0030 1B78 ldrb r3, [r3] + 2593 0032 002B cmp r3, #0 + 2594 0034 14D1 bne .L216 + 2595 .L217: +3169:Generated_Source\PSoC4/CyLFClk.c **** { +3170:Generated_Source\PSoC4/CyLFClk.c **** do +3171:Generated_Source\PSoC4/CyLFClk.c **** { +3172:Generated_Source\PSoC4/CyLFClk.c **** tmpValue = CySysWdtGetCount(counterNum); + 2596 .loc 1 3172 0 discriminator 1 + 2597 0036 FB68 ldr r3, [r7, #12] + 2598 0038 1800 movs r0, r3 + 2599 003a FFF7FEFF bl CySysWdtGetCount + 2600 003e 0300 movs r3, r0 + 2601 0040 7B61 str r3, [r7, #20] +3173:Generated_Source\PSoC4/CyLFClk.c **** }while(tmpValue > match); + 2602 .loc 1 3173 0 discriminator 1 + 2603 0042 7A69 ldr r2, [r7, #20] + 2604 0044 7B68 ldr r3, [r7, #4] + 2605 0046 9A42 cmp r2, r3 + 2606 0048 F5D8 bhi .L217 + 2607 .L218: +3174:Generated_Source\PSoC4/CyLFClk.c **** +3175:Generated_Source\PSoC4/CyLFClk.c **** do +3176:Generated_Source\PSoC4/CyLFClk.c **** { +3177:Generated_Source\PSoC4/CyLFClk.c **** tmpValue = CySysWdtGetCount(counterNum); + 2608 .loc 1 3177 0 discriminator 1 + 2609 004a FB68 ldr r3, [r7, #12] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 103 + + + 2610 004c 1800 movs r0, r3 + 2611 004e FFF7FEFF bl CySysWdtGetCount + 2612 0052 0300 movs r3, r0 + 2613 0054 7B61 str r3, [r7, #20] +3178:Generated_Source\PSoC4/CyLFClk.c **** }while(tmpValue < match); + 2614 .loc 1 3178 0 discriminator 1 + 2615 0056 7A69 ldr r2, [r7, #20] + 2616 0058 7B68 ldr r3, [r7, #4] + 2617 005a 9A42 cmp r2, r3 + 2618 005c F5D3 bcc .L218 +3168:Generated_Source\PSoC4/CyLFClk.c **** { + 2619 .loc 1 3168 0 + 2620 005e 1AE0 b .L220 + 2621 .L216: +3179:Generated_Source\PSoC4/CyLFClk.c **** } +3180:Generated_Source\PSoC4/CyLFClk.c **** else +3181:Generated_Source\PSoC4/CyLFClk.c **** { +3182:Generated_Source\PSoC4/CyLFClk.c **** tmpValue = counterIntMaskTbl[counterNum]; + 2622 .loc 1 3182 0 + 2623 0060 104B ldr r3, .L221+4 + 2624 0062 FA68 ldr r2, [r7, #12] + 2625 0064 9200 lsls r2, r2, #2 + 2626 0066 D358 ldr r3, [r2, r3] + 2627 0068 7B61 str r3, [r7, #20] +3183:Generated_Source\PSoC4/CyLFClk.c **** CySysWdtSetMatch(counterNum, match); + 2628 .loc 1 3183 0 + 2629 006a 7A68 ldr r2, [r7, #4] + 2630 006c FB68 ldr r3, [r7, #12] + 2631 006e 1100 movs r1, r2 + 2632 0070 1800 movs r0, r3 + 2633 0072 FFF7FEFF bl CySysWdtSetMatch +3184:Generated_Source\PSoC4/CyLFClk.c **** +3185:Generated_Source\PSoC4/CyLFClk.c **** disableServicedIsr |= tmpValue; + 2634 .loc 1 3185 0 + 2635 0076 0C4B ldr r3, .L221+8 + 2636 0078 1A68 ldr r2, [r3] + 2637 007a 7B69 ldr r3, [r7, #20] + 2638 007c 1A43 orrs r2, r3 + 2639 007e 0A4B ldr r3, .L221+8 + 2640 0080 1A60 str r2, [r3] +3186:Generated_Source\PSoC4/CyLFClk.c **** wdtIsrMask |= tmpValue; + 2641 .loc 1 3186 0 + 2642 0082 0A4B ldr r3, .L221+12 + 2643 0084 1A68 ldr r2, [r3] + 2644 0086 7B69 ldr r3, [r7, #20] + 2645 0088 1A43 orrs r2, r3 + 2646 008a 084B ldr r3, .L221+12 + 2647 008c 1A60 str r2, [r3] +3168:Generated_Source\PSoC4/CyLFClk.c **** { + 2648 .loc 1 3168 0 + 2649 008e 02E0 b .L220 + 2650 .L215: +3187:Generated_Source\PSoC4/CyLFClk.c **** } +3188:Generated_Source\PSoC4/CyLFClk.c **** } +3189:Generated_Source\PSoC4/CyLFClk.c **** else +3190:Generated_Source\PSoC4/CyLFClk.c **** { +3191:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 104 + + + 2651 .loc 1 3191 0 discriminator 1 + 2652 0090 0020 movs r0, #0 + 2653 0092 FFF7FEFF bl CyHalt + 2654 .L220: +3192:Generated_Source\PSoC4/CyLFClk.c **** } +3193:Generated_Source\PSoC4/CyLFClk.c **** +3194:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_SRSSV2) */ +3195:Generated_Source\PSoC4/CyLFClk.c **** +3196:Generated_Source\PSoC4/CyLFClk.c **** #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) +3197:Generated_Source\PSoC4/CyLFClk.c **** if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && +3198:Generated_Source\PSoC4/CyLFClk.c **** (match <= CY_SYS_UINT16_MAX_VAL)) +3199:Generated_Source\PSoC4/CyLFClk.c **** { +3200:Generated_Source\PSoC4/CyLFClk.c **** if(delayType == CY_SYS_TIMER_WAIT) +3201:Generated_Source\PSoC4/CyLFClk.c **** { +3202:Generated_Source\PSoC4/CyLFClk.c **** do +3203:Generated_Source\PSoC4/CyLFClk.c **** { +3204:Generated_Source\PSoC4/CyLFClk.c **** tmpValue = CySysTimerGetCount(counterNum); +3205:Generated_Source\PSoC4/CyLFClk.c **** }while(tmpValue > match); +3206:Generated_Source\PSoC4/CyLFClk.c **** +3207:Generated_Source\PSoC4/CyLFClk.c **** do +3208:Generated_Source\PSoC4/CyLFClk.c **** { +3209:Generated_Source\PSoC4/CyLFClk.c **** tmpValue = CySysTimerGetCount(counterNum); +3210:Generated_Source\PSoC4/CyLFClk.c **** }while(tmpValue < match); +3211:Generated_Source\PSoC4/CyLFClk.c **** } +3212:Generated_Source\PSoC4/CyLFClk.c **** else +3213:Generated_Source\PSoC4/CyLFClk.c **** { +3214:Generated_Source\PSoC4/CyLFClk.c **** tmpValue = counterTimerIntMaskTbl[counterNum]; +3215:Generated_Source\PSoC4/CyLFClk.c **** CySysTimerSetMatch(counterNum, match); +3216:Generated_Source\PSoC4/CyLFClk.c **** +3217:Generated_Source\PSoC4/CyLFClk.c **** disableTimerServicedIsr |= tmpValue; +3218:Generated_Source\PSoC4/CyLFClk.c **** timerIsrMask |= tmpValue; +3219:Generated_Source\PSoC4/CyLFClk.c **** } +3220:Generated_Source\PSoC4/CyLFClk.c **** } +3221:Generated_Source\PSoC4/CyLFClk.c **** else +3222:Generated_Source\PSoC4/CyLFClk.c **** { +3223:Generated_Source\PSoC4/CyLFClk.c **** CYASSERT(0u != 0u); +3224:Generated_Source\PSoC4/CyLFClk.c **** } +3225:Generated_Source\PSoC4/CyLFClk.c **** #endif /* (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) */ +3226:Generated_Source\PSoC4/CyLFClk.c **** } + 2655 .loc 1 3226 0 + 2656 0096 C046 nop + 2657 0098 BD46 mov sp, r7 + 2658 009a 06B0 add sp, sp, #24 + 2659 @ sp needed + 2660 009c 80BD pop {r7, pc} + 2661 .L222: + 2662 009e C046 .align 2 + 2663 .L221: + 2664 00a0 FFFF0000 .word 65535 + 2665 00a4 00000000 .word counterIntMaskTbl + 2666 00a8 08000000 .word disableServicedIsr + 2667 00ac 00000000 .word wdtIsrMask + 2668 .cfi_endproc + 2669 .LFE35: + 2670 .size CySysTimerDelayUntilMatch, .-CySysTimerDelayUntilMatch + 2671 .bss + 2672 .align 2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 105 + + + 2673 compensateRunningStatus.4836: + 2674 0018 00000000 .space 4 + 2675 .align 2 + 2676 lfclkPosedgeEnabledWdtCounter.4967: + 2677 001c 00000000 .space 4 + 2678 .text + 2679 .Letext0: + 2680 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 2681 .file 3 "Generated_Source\\PSoC4\\CyLFClk.h" + 2682 .file 4 "Generated_Source\\PSoC4\\CyLib.h" + 2683 .section .debug_info,"",%progbits + 2684 .Ldebug_info0: + 2685 0000 1B080000 .4byte 0x81b + 2686 0004 0400 .2byte 0x4 + 2687 0006 00000000 .4byte .Ldebug_abbrev0 + 2688 000a 04 .byte 0x4 + 2689 000b 01 .uleb128 0x1 + 2690 000c B9030000 .4byte .LASF92 + 2691 0010 0C .byte 0xc + 2692 0011 C3050000 .4byte .LASF93 + 2693 0015 B7010000 .4byte .LASF94 + 2694 0019 00000000 .4byte .Ldebug_ranges0+0 + 2695 001d 00000000 .4byte 0 + 2696 0021 00000000 .4byte .Ldebug_line0 + 2697 0025 02 .uleb128 0x2 + 2698 0026 01 .byte 0x1 + 2699 0027 06 .byte 0x6 + 2700 0028 F3000000 .4byte .LASF0 + 2701 002c 02 .uleb128 0x2 + 2702 002d 01 .byte 0x1 + 2703 002e 08 .byte 0x8 + 2704 002f 27050000 .4byte .LASF1 + 2705 0033 02 .uleb128 0x2 + 2706 0034 02 .byte 0x2 + 2707 0035 05 .byte 0x5 + 2708 0036 71050000 .4byte .LASF2 + 2709 003a 02 .uleb128 0x2 + 2710 003b 02 .byte 0x2 + 2711 003c 07 .byte 0x7 + 2712 003d 3E030000 .4byte .LASF3 + 2713 0041 02 .uleb128 0x2 + 2714 0042 04 .byte 0x4 + 2715 0043 05 .byte 0x5 + 2716 0044 46010000 .4byte .LASF4 + 2717 0048 02 .uleb128 0x2 + 2718 0049 04 .byte 0x4 + 2719 004a 07 .byte 0x7 + 2720 004b EC020000 .4byte .LASF5 + 2721 004f 02 .uleb128 0x2 + 2722 0050 08 .byte 0x8 + 2723 0051 05 .byte 0x5 + 2724 0052 E5000000 .4byte .LASF6 + 2725 0056 02 .uleb128 0x2 + 2726 0057 08 .byte 0x8 + 2727 0058 07 .byte 0x7 + 2728 0059 CE000000 .4byte .LASF7 + 2729 005d 03 .uleb128 0x3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 106 + + + 2730 005e 04 .byte 0x4 + 2731 005f 05 .byte 0x5 + 2732 0060 696E7400 .ascii "int\000" + 2733 0064 02 .uleb128 0x2 + 2734 0065 04 .byte 0x4 + 2735 0066 07 .byte 0x7 + 2736 0067 BB020000 .4byte .LASF8 + 2737 006b 04 .uleb128 0x4 + 2738 006c 58010000 .4byte .LASF9 + 2739 0070 02 .byte 0x2 + 2740 0071 E401 .2byte 0x1e4 + 2741 0073 2C000000 .4byte 0x2c + 2742 0077 04 .uleb128 0x4 + 2743 0078 00000000 .4byte .LASF10 + 2744 007c 02 .byte 0x2 + 2745 007d E501 .2byte 0x1e5 + 2746 007f 3A000000 .4byte 0x3a + 2747 0083 04 .uleb128 0x4 + 2748 0084 B0010000 .4byte .LASF11 + 2749 0088 02 .byte 0x2 + 2750 0089 E601 .2byte 0x1e6 + 2751 008b 48000000 .4byte 0x48 + 2752 008f 02 .uleb128 0x2 + 2753 0090 04 .byte 0x4 + 2754 0091 04 .byte 0x4 + 2755 0092 E8040000 .4byte .LASF12 + 2756 0096 02 .uleb128 0x2 + 2757 0097 08 .byte 0x8 + 2758 0098 04 .byte 0x4 + 2759 0099 65010000 .4byte .LASF13 + 2760 009d 02 .uleb128 0x2 + 2761 009e 01 .byte 0x1 + 2762 009f 08 .byte 0x8 + 2763 00a0 FE050000 .4byte .LASF14 + 2764 00a4 04 .uleb128 0x4 + 2765 00a5 CD060000 .4byte .LASF15 + 2766 00a9 02 .byte 0x2 + 2767 00aa 8602 .2byte 0x286 + 2768 00ac 48000000 .4byte 0x48 + 2769 00b0 04 .uleb128 0x4 + 2770 00b1 47040000 .4byte .LASF16 + 2771 00b5 02 .byte 0x2 + 2772 00b6 9002 .2byte 0x290 + 2773 00b8 BC000000 .4byte 0xbc + 2774 00bc 05 .uleb128 0x5 + 2775 00bd 83000000 .4byte 0x83 + 2776 00c1 06 .uleb128 0x6 + 2777 00c2 04 .byte 0x4 + 2778 00c3 C7000000 .4byte 0xc7 + 2779 00c7 07 .uleb128 0x7 + 2780 00c8 08 .uleb128 0x8 + 2781 00c9 01 .byte 0x1 + 2782 00ca 2C000000 .4byte 0x2c + 2783 00ce 03 .byte 0x3 + 2784 00cf 1A .byte 0x1a + 2785 00d0 E1000000 .4byte 0xe1 + 2786 00d4 09 .uleb128 0x9 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 107 + + + 2787 00d5 8F040000 .4byte .LASF17 + 2788 00d9 00 .byte 0 + 2789 00da 09 .uleb128 0x9 + 2790 00db 01070000 .4byte .LASF18 + 2791 00df 01 .byte 0x1 + 2792 00e0 00 .byte 0 + 2793 00e1 0A .uleb128 0xa + 2794 00e2 25010000 .4byte .LASF19 + 2795 00e6 03 .byte 0x3 + 2796 00e7 1D .byte 0x1d + 2797 00e8 C8000000 .4byte 0xc8 + 2798 00ec 0A .uleb128 0xa + 2799 00ed 17010000 .4byte .LASF20 + 2800 00f1 03 .byte 0x3 + 2801 00f2 58 .byte 0x58 + 2802 00f3 C1000000 .4byte 0xc1 + 2803 00f7 02 .uleb128 0x2 + 2804 00f8 08 .byte 0x8 + 2805 00f9 04 .byte 0x4 + 2806 00fa 6C040000 .4byte .LASF21 + 2807 00fe 02 .uleb128 0x2 + 2808 00ff 04 .byte 0x4 + 2809 0100 07 .byte 0x7 + 2810 0101 63040000 .4byte .LASF22 + 2811 0105 0B .uleb128 0xb + 2812 0106 93030000 .4byte .LASF23 + 2813 010a 01 .byte 0x1 + 2814 010b 53 .byte 0x53 + 2815 010c 00000000 .4byte .LFB0 + 2816 0110 1C000000 .4byte .LFE0-.LFB0 + 2817 0114 01 .uleb128 0x1 + 2818 0115 9C .byte 0x9c + 2819 0116 0C .uleb128 0xc + 2820 0117 7E010000 .4byte .LASF34 + 2821 011b 01 .byte 0x1 + 2822 011c 6C .byte 0x6c + 2823 011d 00000000 .4byte .LFB1 + 2824 0121 4C000000 .4byte .LFE1-.LFB1 + 2825 0125 01 .uleb128 0x1 + 2826 0126 9C .byte 0x9c + 2827 0127 3A010000 .4byte 0x13a + 2828 012b 0D .uleb128 0xd + 2829 012c 08010000 .4byte .LASF28 + 2830 0130 01 .byte 0x1 + 2831 0131 6F .byte 0x6f + 2832 0132 6B000000 .4byte 0x6b + 2833 0136 02 .uleb128 0x2 + 2834 0137 91 .byte 0x91 + 2835 0138 6F .sleb128 -17 + 2836 0139 00 .byte 0 + 2837 013a 0B .uleb128 0xb + 2838 013b 93000000 .4byte .LASF24 + 2839 013f 01 .byte 0x1 + 2840 0140 A8 .byte 0xa8 + 2841 0141 00000000 .4byte .LFB2 + 2842 0145 40000000 .4byte .LFE2-.LFB2 + 2843 0149 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 108 + + + 2844 014a 9C .byte 0x9c + 2845 014b 0B .uleb128 0xb + 2846 014c 12020000 .4byte .LASF25 + 2847 0150 01 .byte 0x1 + 2848 0151 C9 .byte 0xc9 + 2849 0152 00000000 .4byte .LFB3 + 2850 0156 20000000 .4byte .LFE3-.LFB3 + 2851 015a 01 .uleb128 0x1 + 2852 015b 9C .byte 0x9c + 2853 015c 0E .uleb128 0xe + 2854 015d EB060000 .4byte .LASF39 + 2855 0161 01 .byte 0x1 + 2856 0162 0B01 .2byte 0x10b + 2857 0164 A4000000 .4byte 0xa4 + 2858 0168 00000000 .4byte .LFB4 + 2859 016c 58010000 .4byte .LFE4-.LFB4 + 2860 0170 01 .uleb128 0x1 + 2861 0171 9C .byte 0x9c + 2862 0172 E3010000 .4byte 0x1e3 + 2863 0176 0F .uleb128 0xf + 2864 0177 DF020000 .4byte .LASF26 + 2865 017b 01 .byte 0x1 + 2866 017c 0B01 .2byte 0x10b + 2867 017e 83000000 .4byte 0x83 + 2868 0182 02 .uleb128 0x2 + 2869 0183 91 .byte 0x91 + 2870 0184 5C .sleb128 -36 + 2871 0185 0F .uleb128 0xf + 2872 0186 6C010000 .4byte .LASF27 + 2873 018a 01 .byte 0x1 + 2874 018b 0B01 .2byte 0x10b + 2875 018d E3010000 .4byte 0x1e3 + 2876 0191 02 .uleb128 0x2 + 2877 0192 91 .byte 0x91 + 2878 0193 58 .sleb128 -40 + 2879 0194 10 .uleb128 0x10 + 2880 0195 8E010000 .4byte .LASF29 + 2881 0199 01 .byte 0x1 + 2882 019a 0D01 .2byte 0x10d + 2883 019c 83000000 .4byte 0x83 + 2884 01a0 02 .uleb128 0x2 + 2885 01a1 91 .byte 0x91 + 2886 01a2 6C .sleb128 -20 + 2887 01a3 10 .uleb128 0x10 + 2888 01a4 74060000 .4byte .LASF30 + 2889 01a8 01 .byte 0x1 + 2890 01a9 0E01 .2byte 0x10e + 2891 01ab 83000000 .4byte 0x83 + 2892 01af 02 .uleb128 0x2 + 2893 01b0 91 .byte 0x91 + 2894 01b1 60 .sleb128 -32 + 2895 01b2 10 .uleb128 0x10 + 2896 01b3 35050000 .4byte .LASF31 + 2897 01b7 01 .byte 0x1 + 2898 01b8 0F01 .2byte 0x10f + 2899 01ba 83000000 .4byte 0x83 + 2900 01be 05 .uleb128 0x5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 109 + + + 2901 01bf 03 .byte 0x3 + 2902 01c0 18000000 .4byte compensateRunningStatus.4836 + 2903 01c4 10 .uleb128 0x10 + 2904 01c5 A1040000 .4byte .LASF32 + 2905 01c9 01 .byte 0x1 + 2906 01ca 1001 .2byte 0x110 + 2907 01cc 83000000 .4byte 0x83 + 2908 01d0 02 .uleb128 0x2 + 2909 01d1 91 .byte 0x91 + 2910 01d2 64 .sleb128 -28 + 2911 01d3 10 .uleb128 0x10 + 2912 01d4 56040000 .4byte .LASF33 + 2913 01d8 01 .byte 0x1 + 2914 01d9 1101 .2byte 0x111 + 2915 01db A4000000 .4byte 0xa4 + 2916 01df 02 .uleb128 0x2 + 2917 01e0 91 .byte 0x91 + 2918 01e1 68 .sleb128 -24 + 2919 01e2 00 .byte 0 + 2920 01e3 06 .uleb128 0x6 + 2921 01e4 04 .byte 0x4 + 2922 01e5 83000000 .4byte 0x83 + 2923 01e9 11 .uleb128 0x11 + 2924 01ea 95050000 .4byte .LASF36 + 2925 01ee 01 .byte 0x1 + 2926 01ef 7201 .2byte 0x172 + 2927 01f1 83000000 .4byte 0x83 + 2928 01f5 00000000 .4byte .LFB5 + 2929 01f9 1C000000 .4byte .LFE5-.LFB5 + 2930 01fd 01 .uleb128 0x1 + 2931 01fe 9C .byte 0x9c + 2932 01ff 12 .uleb128 0x12 + 2933 0200 19060000 .4byte .LASF35 + 2934 0204 01 .byte 0x1 + 2935 0205 B403 .2byte 0x3b4 + 2936 0207 00000000 .4byte .LFB6 + 2937 020b 34000000 .4byte .LFE6-.LFB6 + 2938 020f 01 .uleb128 0x1 + 2939 0210 9C .byte 0x9c + 2940 0211 25020000 .4byte 0x225 + 2941 0215 10 .uleb128 0x10 + 2942 0216 08010000 .4byte .LASF28 + 2943 021a 01 .byte 0x1 + 2944 021b B603 .2byte 0x3b6 + 2945 021d 6B000000 .4byte 0x6b + 2946 0221 02 .uleb128 0x2 + 2947 0222 91 .byte 0x91 + 2948 0223 6F .sleb128 -17 + 2949 0224 00 .byte 0 + 2950 0225 11 .uleb128 0x11 + 2951 0226 18050000 .4byte .LASF37 + 2952 022a 01 .byte 0x1 + 2953 022b C903 .2byte 0x3c9 + 2954 022d 83000000 .4byte 0x83 + 2955 0231 00000000 .4byte .LFB7 + 2956 0235 20000000 .4byte .LFE7-.LFB7 + 2957 0239 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 110 + + + 2958 023a 9C .byte 0x9c + 2959 023b 12 .uleb128 0x12 + 2960 023c 3A000000 .4byte .LASF38 + 2961 0240 01 .byte 0x1 + 2962 0241 D703 .2byte 0x3d7 + 2963 0243 00000000 .4byte .LFB8 + 2964 0247 50000000 .4byte .LFE8-.LFB8 + 2965 024b 01 .uleb128 0x1 + 2966 024c 9C .byte 0x9c + 2967 024d 61020000 .4byte 0x261 + 2968 0251 10 .uleb128 0x10 + 2969 0252 08010000 .4byte .LASF28 + 2970 0256 01 .byte 0x1 + 2971 0257 D903 .2byte 0x3d9 + 2972 0259 6B000000 .4byte 0x6b + 2973 025d 02 .uleb128 0x2 + 2974 025e 91 .byte 0x91 + 2975 025f 6F .sleb128 -17 + 2976 0260 00 .byte 0 + 2977 0261 0E .uleb128 0xe + 2978 0262 51030000 .4byte .LASF40 + 2979 0266 01 .byte 0x1 + 2980 0267 F903 .2byte 0x3f9 + 2981 0269 83000000 .4byte 0x83 + 2982 026d 00000000 .4byte .LFB9 + 2983 0271 34000000 .4byte .LFE9-.LFB9 + 2984 0275 01 .uleb128 0x1 + 2985 0276 9C .byte 0x9c + 2986 0277 8B020000 .4byte 0x28b + 2987 027b 0F .uleb128 0xf + 2988 027c 5B000000 .4byte .LASF41 + 2989 0280 01 .byte 0x1 + 2990 0281 F903 .2byte 0x3f9 + 2991 0283 83000000 .4byte 0x83 + 2992 0287 02 .uleb128 0x2 + 2993 0288 91 .byte 0x91 + 2994 0289 74 .sleb128 -12 + 2995 028a 00 .byte 0 + 2996 028b 12 .uleb128 0x12 + 2997 028c 2A000000 .4byte .LASF42 + 2998 0290 01 .byte 0x1 + 2999 0291 1704 .2byte 0x417 + 3000 0293 00000000 .4byte .LFB10 + 3001 0297 5C000000 .4byte .LFE10-.LFB10 + 3002 029b 01 .uleb128 0x1 + 3003 029c 9C .byte 0x9c + 3004 029d CF020000 .4byte 0x2cf + 3005 02a1 0F .uleb128 0xf + 3006 02a2 5B000000 .4byte .LASF41 + 3007 02a6 01 .byte 0x1 + 3008 02a7 1704 .2byte 0x417 + 3009 02a9 83000000 .4byte 0x83 + 3010 02ad 02 .uleb128 0x2 + 3011 02ae 91 .byte 0x91 + 3012 02af 6C .sleb128 -20 + 3013 02b0 0F .uleb128 0xf + 3014 02b1 03060000 .4byte .LASF43 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 111 + + + 3015 02b5 01 .byte 0x1 + 3016 02b6 1704 .2byte 0x417 + 3017 02b8 83000000 .4byte 0x83 + 3018 02bc 02 .uleb128 0x2 + 3019 02bd 91 .byte 0x91 + 3020 02be 68 .sleb128 -24 + 3021 02bf 10 .uleb128 0x10 + 3022 02c0 89060000 .4byte .LASF44 + 3023 02c4 01 .byte 0x1 + 3024 02c5 1904 .2byte 0x419 + 3025 02c7 83000000 .4byte 0x83 + 3026 02cb 02 .uleb128 0x2 + 3027 02cc 91 .byte 0x91 + 3028 02cd 74 .sleb128 -12 + 3029 02ce 00 .byte 0 + 3030 02cf 13 .uleb128 0x13 + 3031 02d0 64060000 .4byte .LASF45 + 3032 02d4 01 .byte 0x1 + 3033 02d5 3304 .2byte 0x433 + 3034 02d7 83000000 .4byte 0x83 + 3035 02db 00000000 .4byte .LFB11 + 3036 02df 24000000 .4byte .LFE11-.LFB11 + 3037 02e3 01 .uleb128 0x1 + 3038 02e4 9C .byte 0x9c + 3039 02e5 F9020000 .4byte 0x2f9 + 3040 02e9 0F .uleb128 0xf + 3041 02ea 5B000000 .4byte .LASF41 + 3042 02ee 01 .byte 0x1 + 3043 02ef 3304 .2byte 0x433 + 3044 02f1 83000000 .4byte 0x83 + 3045 02f5 02 .uleb128 0x2 + 3046 02f6 91 .byte 0x91 + 3047 02f7 74 .sleb128 -12 + 3048 02f8 00 .byte 0 + 3049 02f9 12 .uleb128 0x12 + 3050 02fa 39060000 .4byte .LASF46 + 3051 02fe 01 .byte 0x1 + 3052 02ff 5004 .2byte 0x450 + 3053 0301 00000000 .4byte .LFB12 + 3054 0305 6C000000 .4byte .LFE12-.LFB12 + 3055 0309 01 .uleb128 0x1 + 3056 030a 9C .byte 0x9c + 3057 030b 3D030000 .4byte 0x33d + 3058 030f 0F .uleb128 0xf + 3059 0310 5B000000 .4byte .LASF41 + 3060 0314 01 .byte 0x1 + 3061 0315 5004 .2byte 0x450 + 3062 0317 83000000 .4byte 0x83 + 3063 031b 02 .uleb128 0x2 + 3064 031c 91 .byte 0x91 + 3065 031d 6C .sleb128 -20 + 3066 031e 0F .uleb128 0xf + 3067 031f 5E010000 .4byte .LASF47 + 3068 0323 01 .byte 0x1 + 3069 0324 5004 .2byte 0x450 + 3070 0326 83000000 .4byte 0x83 + 3071 032a 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 112 + + + 3072 032b 91 .byte 0x91 + 3073 032c 68 .sleb128 -24 + 3074 032d 10 .uleb128 0x10 + 3075 032e 89060000 .4byte .LASF44 + 3076 0332 01 .byte 0x1 + 3077 0333 5204 .2byte 0x452 + 3078 0335 83000000 .4byte 0x83 + 3079 0339 02 .uleb128 0x2 + 3080 033a 91 .byte 0x91 + 3081 033b 74 .sleb128 -12 + 3082 033c 00 .byte 0 + 3083 033d 0E .uleb128 0xe + 3084 033e A3020000 .4byte .LASF48 + 3085 0342 01 .byte 0x1 + 3086 0343 7104 .2byte 0x471 + 3087 0345 83000000 .4byte 0x83 + 3088 0349 00000000 .4byte .LFB13 + 3089 034d 44000000 .4byte .LFE13-.LFB13 + 3090 0351 01 .uleb128 0x1 + 3091 0352 9C .byte 0x9c + 3092 0353 67030000 .4byte 0x367 + 3093 0357 0F .uleb128 0xf + 3094 0358 5B000000 .4byte .LASF41 + 3095 035c 01 .byte 0x1 + 3096 035d 7104 .2byte 0x471 + 3097 035f 83000000 .4byte 0x83 + 3098 0363 02 .uleb128 0x2 + 3099 0364 91 .byte 0x91 + 3100 0365 74 .sleb128 -12 + 3101 0366 00 .byte 0 + 3102 0367 12 .uleb128 0x12 + 3103 0368 6B020000 .4byte .LASF49 + 3104 036c 01 .byte 0x1 + 3105 036d 9A04 .2byte 0x49a + 3106 036f 00000000 .4byte .LFB14 + 3107 0373 64000000 .4byte .LFE14-.LFB14 + 3108 0377 01 .uleb128 0x1 + 3109 0378 9C .byte 0x9c + 3110 0379 8D030000 .4byte 0x38d + 3111 037d 0F .uleb128 0xf + 3112 037e 97020000 .4byte .LASF50 + 3113 0382 01 .byte 0x1 + 3114 0383 9A04 .2byte 0x49a + 3115 0385 83000000 .4byte 0x83 + 3116 0389 02 .uleb128 0x2 + 3117 038a 91 .byte 0x91 + 3118 038b 74 .sleb128 -12 + 3119 038c 00 .byte 0 + 3120 038d 12 .uleb128 0x12 + 3121 038e 85050000 .4byte .LASF51 + 3122 0392 01 .byte 0x1 + 3123 0393 CA04 .2byte 0x4ca + 3124 0395 00000000 .4byte .LFB15 + 3125 0399 6C000000 .4byte .LFE15-.LFB15 + 3126 039d 01 .uleb128 0x1 + 3127 039e 9C .byte 0x9c + 3128 039f B3030000 .4byte 0x3b3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 113 + + + 3129 03a3 0F .uleb128 0xf + 3130 03a4 97020000 .4byte .LASF50 + 3131 03a8 01 .byte 0x1 + 3132 03a9 CA04 .2byte 0x4ca + 3133 03ab 83000000 .4byte 0x83 + 3134 03af 02 .uleb128 0x2 + 3135 03b0 91 .byte 0x91 + 3136 03b1 74 .sleb128 -12 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.sleb128 -20 + 3171 03f6 00 .byte 0 + 3172 03f7 14 .uleb128 0x14 + 3173 03f8 80000000 .4byte .LASF60 + 3174 03fc 01 .byte 0x1 + 3175 03fd 2405 .2byte 0x524 + 3176 03ff 83000000 .4byte 0x83 + 3177 0403 00000000 .4byte .LFB17 + 3178 0407 1C000000 .4byte .LFE17-.LFB17 + 3179 040b 01 .uleb128 0x1 + 3180 040c 9C .byte 0x9c + 3181 040d 12 .uleb128 0x12 + 3182 040e 3A020000 .4byte .LASF55 + 3183 0412 01 .byte 0x1 + 3184 0413 3805 .2byte 0x538 + 3185 0415 00000000 .4byte .LFB18 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 114 + + + 3186 0419 6C000000 .4byte .LFE18-.LFB18 + 3187 041d 01 .uleb128 0x1 + 3188 041e 9C .byte 0x9c + 3189 041f 51040000 .4byte 0x451 + 3190 0423 0F .uleb128 0xf + 3191 0424 5B000000 .4byte .LASF41 + 3192 0428 01 .byte 0x1 + 3193 0429 3805 .2byte 0x538 + 3194 042b 83000000 .4byte 0x83 + 3195 042f 02 .uleb128 0x2 + 3196 0430 91 .byte 0x91 + 3197 0431 6C .sleb128 -20 + 3198 0432 0F .uleb128 0xf + 3199 0433 89040000 .4byte .LASF56 + 3200 0437 01 .byte 0x1 + 3201 0438 3805 .2byte 0x538 + 3202 043a 83000000 .4byte 0x83 + 3203 043e 02 .uleb128 0x2 + 3204 043f 91 .byte 0x91 + 3205 0440 68 .sleb128 -24 + 3206 0441 10 .uleb128 0x10 + 3207 0442 4F010000 .4byte .LASF57 + 3208 0446 01 .byte 0x1 + 3209 0447 3A05 .2byte 0x53a + 3210 0449 83000000 .4byte 0x83 + 3211 044d 02 .uleb128 0x2 + 3212 044e 91 .byte 0x91 + 3213 044f 74 .sleb128 -12 + 3214 0450 00 .byte 0 + 3215 0451 12 .uleb128 0x12 + 3216 0452 A4030000 .4byte .LASF58 + 3217 0456 01 .byte 0x1 + 3218 0457 5F05 .2byte 0x55f + 3219 0459 00000000 .4byte .LFB19 + 3220 045d 48000000 .4byte .LFE19-.LFB19 + 3221 0461 01 .uleb128 0x1 + 3222 0462 9C .byte 0x9c + 3223 0463 86040000 .4byte 0x486 + 3224 0467 0F .uleb128 0xf + 3225 0468 41010000 .4byte .LASF59 + 3226 046c 01 .byte 0x1 + 3227 046d 5F05 .2byte 0x55f + 3228 046f 83000000 .4byte 0x83 + 3229 0473 02 .uleb128 0x2 + 3230 0474 91 .byte 0x91 + 3231 0475 6C .sleb128 -20 + 3232 0476 10 .uleb128 0x10 + 3233 0477 89060000 .4byte .LASF44 + 3234 047b 01 .byte 0x1 + 3235 047c 6105 .2byte 0x561 + 3236 047e 83000000 .4byte 0x83 + 3237 0482 02 .uleb128 0x2 + 3238 0483 91 .byte 0x91 + 3239 0484 74 .sleb128 -12 + 3240 0485 00 .byte 0 + 3241 0486 14 .uleb128 0x14 + 3242 0487 D6060000 .4byte .LASF61 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 115 + + + 3243 048b 01 .byte 0x1 + 3244 048c 7605 .2byte 0x576 + 3245 048e 83000000 .4byte 0x83 + 3246 0492 00000000 .4byte .LFB20 + 3247 0496 18000000 .4byte .LFE20-.LFB20 + 3248 049a 01 .uleb128 0x1 + 3249 049b 9C .byte 0x9c + 3250 049c 0E .uleb128 0xe + 3251 049d 78040000 .4byte .LASF62 + 3252 04a1 01 .byte 0x1 + 3253 04a2 8805 .2byte 0x588 + 3254 04a4 83000000 .4byte 0x83 + 3255 04a8 00000000 .4byte .LFB21 + 3256 04ac 40000000 .4byte .LFE21-.LFB21 + 3257 04b0 01 .uleb128 0x1 + 3258 04b1 9C .byte 0x9c + 3259 04b2 C6040000 .4byte 0x4c6 + 3260 04b6 0F .uleb128 0xf + 3261 04b7 5B000000 .4byte .LASF41 + 3262 04bb 01 .byte 0x1 + 3263 04bc 8805 .2byte 0x588 + 3264 04be 83000000 .4byte 0x83 + 3265 04c2 02 .uleb128 0x2 + 3266 04c3 91 .byte 0x91 + 3267 04c4 74 .sleb128 -12 + 3268 04c5 00 .byte 0 + 3269 04c6 0E .uleb128 0xe + 3270 04c7 08060000 .4byte .LASF63 + 3271 04cb 01 .byte 0x1 + 3272 04cc 9E05 .2byte 0x59e + 3273 04ce 83000000 .4byte 0x83 + 3274 04d2 00000000 .4byte .LFB22 + 3275 04d6 54000000 .4byte .LFE22-.LFB22 + 3276 04da 01 .uleb128 0x1 + 3277 04db 9C .byte 0x9c + 3278 04dc FF040000 .4byte 0x4ff + 3279 04e0 0F .uleb128 0xf + 3280 04e1 5B000000 .4byte .LASF41 + 3281 04e5 01 .byte 0x1 + 3282 04e6 9E05 .2byte 0x59e + 3283 04e8 83000000 .4byte 0x83 + 3284 04ec 02 .uleb128 0x2 + 3285 04ed 91 .byte 0x91 + 3286 04ee 6C .sleb128 -20 + 3287 04ef 10 .uleb128 0x10 + 3288 04f0 4F010000 .4byte .LASF57 + 3289 04f4 01 .byte 0x1 + 3290 04f5 A005 .2byte 0x5a0 + 3291 04f7 83000000 .4byte 0x83 + 3292 04fb 02 .uleb128 0x2 + 3293 04fc 91 .byte 0x91 + 3294 04fd 74 .sleb128 -12 + 3295 04fe 00 .byte 0 + 3296 04ff 14 .uleb128 0x14 + 3297 0500 A8050000 .4byte .LASF64 + 3298 0504 01 .byte 0x1 + 3299 0505 C905 .2byte 0x5c9 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 116 + + + 3300 0507 83000000 .4byte 0x83 + 3301 050b 00000000 .4byte .LFB23 + 3302 050f 1C000000 .4byte .LFE23-.LFB23 + 3303 0513 01 .uleb128 0x1 + 3304 0514 9C .byte 0x9c + 3305 0515 12 .uleb128 0x12 + 3306 0516 D1040000 .4byte .LASF65 + 3307 051a 01 .byte 0x1 + 3308 051b E605 .2byte 0x5e6 + 3309 051d 00000000 .4byte .LFB24 + 3310 0521 70000000 .4byte .LFE24-.LFB24 + 3311 0525 01 .uleb128 0x1 + 3312 0526 9C .byte 0x9c + 3313 0527 59050000 .4byte 0x559 + 3314 052b 0F .uleb128 0xf + 3315 052c 97020000 .4byte .LASF50 + 3316 0530 01 .byte 0x1 + 3317 0531 E605 .2byte 0x5e6 + 3318 0533 83000000 .4byte 0x83 + 3319 0537 02 .uleb128 0x2 + 3320 0538 91 .byte 0x91 + 3321 0539 64 .sleb128 -28 + 3322 053a 10 .uleb128 0x10 + 3323 053b 08010000 .4byte .LASF28 + 3324 053f 01 .byte 0x1 + 3325 0540 E805 .2byte 0x5e8 + 3326 0542 6B000000 .4byte 0x6b + 3327 0546 02 .uleb128 0x2 + 3328 0547 91 .byte 0x91 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3A06 .2byte 0x63a + 3361 0587 EC000000 .4byte 0xec + 3362 058b 00000000 .4byte .LFB26 + 3363 058f 40000000 .4byte .LFE26-.LFB26 + 3364 0593 01 .uleb128 0x1 + 3365 0594 9C .byte 0x9c + 3366 0595 C7050000 .4byte 0x5c7 + 3367 0599 0F .uleb128 0xf + 3368 059a 5B000000 .4byte .LASF41 + 3369 059e 01 .byte 0x1 + 3370 059f 3A06 .2byte 0x63a + 3371 05a1 83000000 .4byte 0x83 + 3372 05a5 02 .uleb128 0x2 + 3373 05a6 91 .byte 0x91 + 3374 05a7 6C .sleb128 -20 + 3375 05a8 0F .uleb128 0xf + 3376 05a9 FF000000 .4byte .LASF70 + 3377 05ad 01 .byte 0x1 + 3378 05ae 3A06 .2byte 0x63a + 3379 05b0 EC000000 .4byte 0xec + 3380 05b4 02 .uleb128 0x2 + 3381 05b5 91 .byte 0x91 + 3382 05b6 68 .sleb128 -24 + 3383 05b7 10 .uleb128 0x10 + 3384 05b8 2D020000 .4byte .LASF71 + 3385 05bc 01 .byte 0x1 + 3386 05bd 3C06 .2byte 0x63c + 3387 05bf EC000000 .4byte 0xec + 3388 05c3 02 .uleb128 0x2 + 3389 05c4 91 .byte 0x91 + 3390 05c5 74 .sleb128 -12 + 3391 05c6 00 .byte 0 + 3392 05c7 0E .uleb128 0xe + 3393 05c8 6A030000 .4byte .LASF72 + 3394 05cc 01 .byte 0x1 + 3395 05cd 5806 .2byte 0x658 + 3396 05cf EC000000 .4byte 0xec + 3397 05d3 00000000 .4byte .LFB27 + 3398 05d7 34000000 .4byte .LFE27-.LFB27 + 3399 05db 01 .uleb128 0x1 + 3400 05dc 9C .byte 0x9c + 3401 05dd 00060000 .4byte 0x600 + 3402 05e1 0F .uleb128 0xf + 3403 05e2 5B000000 .4byte .LASF41 + 3404 05e6 01 .byte 0x1 + 3405 05e7 5806 .2byte 0x658 + 3406 05e9 83000000 .4byte 0x83 + 3407 05ed 02 .uleb128 0x2 + 3408 05ee 91 .byte 0x91 + 3409 05ef 6C .sleb128 -20 + 3410 05f0 10 .uleb128 0x10 + 3411 05f1 D3020000 .4byte .LASF73 + 3412 05f5 01 .byte 0x1 + 3413 05f6 5A06 .2byte 0x65a + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 118 + + + 3414 05f8 EC000000 .4byte 0xec + 3415 05fc 02 .uleb128 0x2 + 3416 05fd 91 .byte 0x91 + 3417 05fe 74 .sleb128 -12 + 3418 05ff 00 .byte 0 + 3419 0600 12 .uleb128 0x12 + 3420 0601 25030000 .4byte .LASF74 + 3421 0605 01 .byte 0x1 + 3422 0606 7506 .2byte 0x675 + 3423 0608 00000000 .4byte .LFB28 + 3424 060c 50000000 .4byte .LFE28-.LFB28 + 3425 0610 01 .uleb128 0x1 + 3426 0611 9C .byte 0x9c + 3427 0612 26060000 .4byte 0x626 + 3428 0616 0F .uleb128 0xf + 3429 0617 5B000000 .4byte .LASF41 + 3430 061b 01 .byte 0x1 + 3431 061c 7506 .2byte 0x675 + 3432 061e 83000000 .4byte 0x83 + 3433 0622 02 .uleb128 0x2 + 3434 0623 91 .byte 0x91 + 3435 0624 74 .sleb128 -12 + 3436 0625 00 .byte 0 + 3437 0626 12 .uleb128 0x12 + 3438 0627 E4050000 .4byte .LASF75 + 3439 062b 01 .byte 0x1 + 3440 062c 8C06 .2byte 0x68c + 3441 062e 00000000 .4byte .LFB29 + 3442 0632 3C000000 .4byte .LFE29-.LFB29 + 3443 0636 01 .uleb128 0x1 + 3444 0637 9C .byte 0x9c + 3445 0638 4C060000 .4byte 0x64c + 3446 063c 0F .uleb128 0xf + 3447 063d 5B000000 .4byte .LASF41 + 3448 0641 01 .byte 0x1 + 3449 0642 8C06 .2byte 0x68c + 3450 0644 83000000 .4byte 0x83 + 3451 0648 02 .uleb128 0x2 + 3452 0649 91 .byte 0x91 + 3453 064a 74 .sleb128 -12 + 3454 064b 00 .byte 0 + 3455 064c 16 .uleb128 0x16 + 3456 064d 87030000 .4byte .LASF76 + 3457 0651 01 .byte 0x1 + 3458 0652 AD06 .2byte 0x6ad + 3459 0654 00000000 .4byte .LFB30 + 3460 0658 EC000000 .4byte .LFE30-.LFB30 + 3461 065c 01 .uleb128 0x1 + 3462 065d 9C .byte 0x9c + 3463 065e 12 .uleb128 0x12 + 3464 065f 49000000 .4byte .LASF77 + 3465 0663 01 .byte 0x1 + 3466 0664 EE06 .2byte 0x6ee + 3467 0666 00000000 .4byte .LFB31 + 3468 066a 8A000000 .4byte .LFE31-.LFB31 + 3469 066e 01 .uleb128 0x1 + 3470 066f 9C .byte 0x9c + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 119 + + + 3471 0670 84060000 .4byte 0x684 + 3472 0674 0F .uleb128 0xf + 3473 0675 5B000000 .4byte .LASF41 + 3474 0679 01 .byte 0x1 + 3475 067a EE06 .2byte 0x6ee + 3476 067c 83000000 .4byte 0x83 + 3477 0680 02 .uleb128 0x2 + 3478 0681 91 .byte 0x91 + 3479 0682 74 .sleb128 -12 + 3480 0683 00 .byte 0 + 3481 0684 17 .uleb128 0x17 + 3482 0685 66000000 .4byte .LASF95 + 3483 0689 01 .byte 0x1 + 3484 068a 3007 .2byte 0x730 + 3485 068c 00000000 .4byte .LFB32 + 3486 0690 98000000 .4byte .LFE32-.LFB32 + 3487 0694 01 .uleb128 0x1 + 3488 0695 9C .byte 0x9c + 3489 0696 BC060000 .4byte 0x6bc + 3490 069a 10 .uleb128 0x10 + 3491 069b C8020000 .4byte .LASF78 + 3492 069f 01 .byte 0x1 + 3493 06a0 3207 .2byte 0x732 + 3494 06a2 83000000 .4byte 0x83 + 3495 06a6 02 .uleb128 0x2 + 3496 06a7 91 .byte 0x91 + 3497 06a8 74 .sleb128 -12 + 3498 06a9 10 .uleb128 0x10 + 3499 06aa 4D050000 .4byte .LASF79 + 3500 06ae 01 .byte 0x1 + 3501 06af 3307 .2byte 0x733 + 3502 06b1 83000000 .4byte 0x83 + 3503 06b5 05 .uleb128 0x5 + 3504 06b6 03 .byte 0x3 + 3505 06b7 1C000000 .4byte lfclkPosedgeEnabledWdtCounter.4967 + 3506 06bb 00 .byte 0 + 3507 06bc 18 .uleb128 0x18 + 3508 06bd 09030000 .4byte .LASF96 + 3509 06c1 01 .byte 0x1 + 3510 06c2 6607 .2byte 0x766 + 3511 06c4 00000000 .4byte .LFB33 + 3512 06c8 3C000000 .4byte .LFE33-.LFB33 + 3513 06cc 01 .uleb128 0x1 + 3514 06cd 9C .byte 0x9c + 3515 06ce 12 .uleb128 0x12 + 3516 06cf 08050000 .4byte .LASF80 + 3517 06d3 01 .byte 0x1 + 3518 06d4 D70B .2byte 0xbd7 + 3519 06d6 00000000 .4byte .LFB34 + 3520 06da 68000000 .4byte .LFE34-.LFB34 + 3521 06de 01 .uleb128 0x1 + 3522 06df 9C .byte 0x9c + 3523 06e0 30070000 .4byte 0x730 + 3524 06e4 0F .uleb128 0xf + 3525 06e5 5B000000 .4byte .LASF41 + 3526 06e9 01 .byte 0x1 + 3527 06ea D70B .2byte 0xbd7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 120 + + + 3528 06ec 83000000 .4byte 0x83 + 3529 06f0 02 .uleb128 0x2 + 3530 06f1 91 .byte 0x91 + 3531 06f2 6C .sleb128 -20 + 3532 06f3 0F .uleb128 0xf + 3533 06f4 7B050000 .4byte .LASF81 + 3534 06f8 01 .byte 0x1 + 3535 06f9 D70B .2byte 0xbd7 + 3536 06fb E1000000 .4byte 0xe1 + 3537 06ff 02 .uleb128 0x2 + 3538 0700 91 .byte 0x91 + 3539 0701 6B .sleb128 -21 + 3540 0702 0F .uleb128 0xf + 3541 0703 6B050000 .4byte .LASF82 + 3542 0707 01 .byte 0x1 + 3543 0708 D70B .2byte 0xbd7 + 3544 070a 83000000 .4byte 0x83 + 3545 070e 02 .uleb128 0x2 + 3546 070f 91 .byte 0x91 + 3547 0710 64 .sleb128 -28 + 3548 0711 10 .uleb128 0x10 + 3549 0712 4F010000 .4byte .LASF57 + 3550 0716 01 .byte 0x1 + 3551 0717 D90B .2byte 0xbd9 + 3552 0719 83000000 .4byte 0x83 + 3553 071d 02 .uleb128 0x2 + 3554 071e 91 .byte 0x91 + 3555 071f 74 .sleb128 -12 + 3556 0720 10 .uleb128 0x10 + 3557 0721 FE020000 .4byte .LASF83 + 3558 0725 01 .byte 0x1 + 3559 0726 DA0B .2byte 0xbda + 3560 0728 83000000 .4byte 0x83 + 3561 072c 02 .uleb128 0x2 + 3562 072d 91 .byte 0x91 + 3563 072e 70 .sleb128 -16 + 3564 072f 00 .byte 0 + 3565 0730 12 .uleb128 0x12 + 3566 0731 EE040000 .4byte .LASF84 + 3567 0735 01 .byte 0x1 + 3568 0736 580C .2byte 0xc58 + 3569 0738 00000000 .4byte .LFB35 + 3570 073c B0000000 .4byte .LFE35-.LFB35 + 3571 0740 01 .uleb128 0x1 + 3572 0741 9C .byte 0x9c + 3573 0742 83070000 .4byte 0x783 + 3574 0746 0F .uleb128 0xf + 3575 0747 5B000000 .4byte .LASF41 + 3576 074b 01 .byte 0x1 + 3577 074c 580C .2byte 0xc58 + 3578 074e 83000000 .4byte 0x83 + 3579 0752 02 .uleb128 0x2 + 3580 0753 91 .byte 0x91 + 3581 0754 6C .sleb128 -20 + 3582 0755 0F .uleb128 0xf + 3583 0756 7B050000 .4byte .LASF81 + 3584 075a 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 121 + + + 3585 075b 580C .2byte 0xc58 + 3586 075d E1000000 .4byte 0xe1 + 3587 0761 02 .uleb128 0x2 + 3588 0762 91 .byte 0x91 + 3589 0763 6B .sleb128 -21 + 3590 0764 0F .uleb128 0xf + 3591 0765 89040000 .4byte .LASF56 + 3592 0769 01 .byte 0x1 + 3593 076a 580C .2byte 0xc58 + 3594 076c 83000000 .4byte 0x83 + 3595 0770 02 .uleb128 0x2 + 3596 0771 91 .byte 0x91 + 3597 0772 64 .sleb128 -28 + 3598 0773 10 .uleb128 0x10 + 3599 0774 4D040000 .4byte .LASF85 + 3600 0778 01 .byte 0x1 + 3601 0779 5A0C .2byte 0xc5a + 3602 077b 83000000 .4byte 0x83 + 3603 077f 02 .uleb128 0x2 + 3604 0780 91 .byte 0x91 + 3605 0781 74 .sleb128 -12 + 3606 0782 00 .byte 0 + 3607 0783 0D .uleb128 0xd + 3608 0784 AF000000 .4byte .LASF86 + 3609 0788 01 .byte 0x1 + 3610 0789 22 .byte 0x22 + 3611 078a 83000000 .4byte 0x83 + 3612 078e 05 .uleb128 0x5 + 3613 078f 03 .byte 0x3 + 3614 0790 00000000 .4byte lfclkPosedgeWdtCounter0Enabled + 3615 0794 0D .uleb128 0xd + 3616 0795 A5060000 .4byte .LASF87 + 3617 0799 01 .byte 0x1 + 3618 079a 23 .byte 0x23 + 3619 079b 83000000 .4byte 0x83 + 3620 079f 05 .uleb128 0x5 + 3621 07a0 03 .byte 0x3 + 3622 07a1 04000000 .4byte lfclkPosedgeWdtCounter0Mode + 3623 07a5 0D .uleb128 0xd + 3624 07a6 26060000 .4byte .LASF88 + 3625 07aa 01 .byte 0x1 + 3626 07ab 25 .byte 0x25 + 3627 07ac BC000000 .4byte 0xbc + 3628 07b0 05 .uleb128 0x5 + 3629 07b1 03 .byte 0x3 + 3630 07b2 08000000 .4byte disableServicedIsr + 3631 07b6 0D .uleb128 0xd + 3632 07b7 60020000 .4byte .LASF89 + 3633 07bb 01 .byte 0x1 + 3634 07bc 26 .byte 0x26 + 3635 07bd BC000000 .4byte 0xbc + 3636 07c1 05 .uleb128 0x5 + 3637 07c2 03 .byte 0x3 + 3638 07c3 00000000 .4byte wdtIsrMask + 3639 07c7 19 .uleb128 0x19 + 3640 07c8 D7070000 .4byte 0x7d7 + 3641 07cc D7070000 .4byte 0x7d7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 122 + + + 3642 07d0 1A .uleb128 0x1a + 3643 07d1 FE000000 .4byte 0xfe + 3644 07d5 02 .byte 0x2 + 3645 07d6 00 .byte 0 + 3646 07d7 1B .uleb128 0x1b + 3647 07d8 83000000 .4byte 0x83 + 3648 07dc 0D .uleb128 0xd + 3649 07dd 07000000 .4byte .LASF90 + 3650 07e1 01 .byte 0x1 + 3651 07e2 2A .byte 0x2a + 3652 07e3 ED070000 .4byte 0x7ed + 3653 07e7 05 .uleb128 0x5 + 3654 07e8 03 .byte 0x3 + 3655 07e9 00000000 .4byte counterIntMaskTbl + 3656 07ed 1B .uleb128 0x1b + 3657 07ee C7070000 .4byte 0x7c7 + 3658 07f2 19 .uleb128 0x19 + 3659 07f3 EC000000 .4byte 0xec + 3660 07f7 02080000 .4byte 0x802 + 3661 07fb 1A .uleb128 0x1a + 3662 07fc FE000000 .4byte 0xfe + 3663 0800 02 .byte 0x2 + 3664 0801 00 .byte 0 + 3665 0802 0D .uleb128 0xd + 3666 0803 19000000 .4byte .LASF91 + 3667 0807 01 .byte 0x1 + 3668 0808 44 .byte 0x44 + 3669 0809 F2070000 .4byte 0x7f2 + 3670 080d 05 .uleb128 0x5 + 3671 080e 03 .byte 0x3 + 3672 080f 0C000000 .4byte cySysWdtCallback + 3673 0813 1C .uleb128 0x1c + 3674 0814 AD040000 .4byte .LASF97 + 3675 0818 04 .byte 0x4 + 3676 0819 D4 .byte 0xd4 + 3677 081a 83000000 .4byte 0x83 + 3678 081e 00 .byte 0 + 3679 .section .debug_abbrev,"",%progbits + 3680 .Ldebug_abbrev0: + 3681 0000 01 .uleb128 0x1 + 3682 0001 11 .uleb128 0x11 + 3683 0002 01 .byte 0x1 + 3684 0003 25 .uleb128 0x25 + 3685 0004 0E .uleb128 0xe + 3686 0005 13 .uleb128 0x13 + 3687 0006 0B .uleb128 0xb + 3688 0007 03 .uleb128 0x3 + 3689 0008 0E .uleb128 0xe + 3690 0009 1B .uleb128 0x1b + 3691 000a 0E .uleb128 0xe + 3692 000b 55 .uleb128 0x55 + 3693 000c 17 .uleb128 0x17 + 3694 000d 11 .uleb128 0x11 + 3695 000e 01 .uleb128 0x1 + 3696 000f 10 .uleb128 0x10 + 3697 0010 17 .uleb128 0x17 + 3698 0011 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 123 + + + 3699 0012 00 .byte 0 + 3700 0013 02 .uleb128 0x2 + 3701 0014 24 .uleb128 0x24 + 3702 0015 00 .byte 0 + 3703 0016 0B .uleb128 0xb + 3704 0017 0B .uleb128 0xb + 3705 0018 3E .uleb128 0x3e + 3706 0019 0B .uleb128 0xb + 3707 001a 03 .uleb128 0x3 + 3708 001b 0E .uleb128 0xe + 3709 001c 00 .byte 0 + 3710 001d 00 .byte 0 + 3711 001e 03 .uleb128 0x3 + 3712 001f 24 .uleb128 0x24 + 3713 0020 00 .byte 0 + 3714 0021 0B .uleb128 0xb + 3715 0022 0B .uleb128 0xb + 3716 0023 3E .uleb128 0x3e + 3717 0024 0B .uleb128 0xb + 3718 0025 03 .uleb128 0x3 + 3719 0026 08 .uleb128 0x8 + 3720 0027 00 .byte 0 + 3721 0028 00 .byte 0 + 3722 0029 04 .uleb128 0x4 + 3723 002a 16 .uleb128 0x16 + 3724 002b 00 .byte 0 + 3725 002c 03 .uleb128 0x3 + 3726 002d 0E .uleb128 0xe + 3727 002e 3A .uleb128 0x3a + 3728 002f 0B .uleb128 0xb + 3729 0030 3B .uleb128 0x3b + 3730 0031 05 .uleb128 0x5 + 3731 0032 49 .uleb128 0x49 + 3732 0033 13 .uleb128 0x13 + 3733 0034 00 .byte 0 + 3734 0035 00 .byte 0 + 3735 0036 05 .uleb128 0x5 + 3736 0037 35 .uleb128 0x35 + 3737 0038 00 .byte 0 + 3738 0039 49 .uleb128 0x49 + 3739 003a 13 .uleb128 0x13 + 3740 003b 00 .byte 0 + 3741 003c 00 .byte 0 + 3742 003d 06 .uleb128 0x6 + 3743 003e 0F .uleb128 0xf + 3744 003f 00 .byte 0 + 3745 0040 0B .uleb128 0xb + 3746 0041 0B .uleb128 0xb + 3747 0042 49 .uleb128 0x49 + 3748 0043 13 .uleb128 0x13 + 3749 0044 00 .byte 0 + 3750 0045 00 .byte 0 + 3751 0046 07 .uleb128 0x7 + 3752 0047 15 .uleb128 0x15 + 3753 0048 00 .byte 0 + 3754 0049 27 .uleb128 0x27 + 3755 004a 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 124 + + + 3756 004b 00 .byte 0 + 3757 004c 00 .byte 0 + 3758 004d 08 .uleb128 0x8 + 3759 004e 04 .uleb128 0x4 + 3760 004f 01 .byte 0x1 + 3761 0050 0B .uleb128 0xb + 3762 0051 0B .uleb128 0xb + 3763 0052 49 .uleb128 0x49 + 3764 0053 13 .uleb128 0x13 + 3765 0054 3A .uleb128 0x3a + 3766 0055 0B .uleb128 0xb + 3767 0056 3B .uleb128 0x3b + 3768 0057 0B .uleb128 0xb + 3769 0058 01 .uleb128 0x1 + 3770 0059 13 .uleb128 0x13 + 3771 005a 00 .byte 0 + 3772 005b 00 .byte 0 + 3773 005c 09 .uleb128 0x9 + 3774 005d 28 .uleb128 0x28 + 3775 005e 00 .byte 0 + 3776 005f 03 .uleb128 0x3 + 3777 0060 0E .uleb128 0xe + 3778 0061 1C .uleb128 0x1c + 3779 0062 0B .uleb128 0xb + 3780 0063 00 .byte 0 + 3781 0064 00 .byte 0 + 3782 0065 0A .uleb128 0xa + 3783 0066 16 .uleb128 0x16 + 3784 0067 00 .byte 0 + 3785 0068 03 .uleb128 0x3 + 3786 0069 0E .uleb128 0xe + 3787 006a 3A .uleb128 0x3a + 3788 006b 0B .uleb128 0xb + 3789 006c 3B .uleb128 0x3b + 3790 006d 0B .uleb128 0xb + 3791 006e 49 .uleb128 0x49 + 3792 006f 13 .uleb128 0x13 + 3793 0070 00 .byte 0 + 3794 0071 00 .byte 0 + 3795 0072 0B .uleb128 0xb + 3796 0073 2E .uleb128 0x2e + 3797 0074 00 .byte 0 + 3798 0075 3F .uleb128 0x3f + 3799 0076 19 .uleb128 0x19 + 3800 0077 03 .uleb128 0x3 + 3801 0078 0E .uleb128 0xe + 3802 0079 3A .uleb128 0x3a + 3803 007a 0B .uleb128 0xb + 3804 007b 3B .uleb128 0x3b + 3805 007c 0B .uleb128 0xb + 3806 007d 27 .uleb128 0x27 + 3807 007e 19 .uleb128 0x19 + 3808 007f 11 .uleb128 0x11 + 3809 0080 01 .uleb128 0x1 + 3810 0081 12 .uleb128 0x12 + 3811 0082 06 .uleb128 0x6 + 3812 0083 40 .uleb128 0x40 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 125 + + + 3813 0084 18 .uleb128 0x18 + 3814 0085 9742 .uleb128 0x2117 + 3815 0087 19 .uleb128 0x19 + 3816 0088 00 .byte 0 + 3817 0089 00 .byte 0 + 3818 008a 0C .uleb128 0xc + 3819 008b 2E .uleb128 0x2e + 3820 008c 01 .byte 0x1 + 3821 008d 3F .uleb128 0x3f + 3822 008e 19 .uleb128 0x19 + 3823 008f 03 .uleb128 0x3 + 3824 0090 0E .uleb128 0xe + 3825 0091 3A .uleb128 0x3a + 3826 0092 0B .uleb128 0xb + 3827 0093 3B .uleb128 0x3b + 3828 0094 0B .uleb128 0xb + 3829 0095 27 .uleb128 0x27 + 3830 0096 19 .uleb128 0x19 + 3831 0097 11 .uleb128 0x11 + 3832 0098 01 .uleb128 0x1 + 3833 0099 12 .uleb128 0x12 + 3834 009a 06 .uleb128 0x6 + 3835 009b 40 .uleb128 0x40 + 3836 009c 18 .uleb128 0x18 + 3837 009d 9642 .uleb128 0x2116 + 3838 009f 19 .uleb128 0x19 + 3839 00a0 01 .uleb128 0x1 + 3840 00a1 13 .uleb128 0x13 + 3841 00a2 00 .byte 0 + 3842 00a3 00 .byte 0 + 3843 00a4 0D .uleb128 0xd + 3844 00a5 34 .uleb128 0x34 + 3845 00a6 00 .byte 0 + 3846 00a7 03 .uleb128 0x3 + 3847 00a8 0E .uleb128 0xe + 3848 00a9 3A .uleb128 0x3a + 3849 00aa 0B .uleb128 0xb + 3850 00ab 3B .uleb128 0x3b + 3851 00ac 0B .uleb128 0xb + 3852 00ad 49 .uleb128 0x49 + 3853 00ae 13 .uleb128 0x13 + 3854 00af 02 .uleb128 0x2 + 3855 00b0 18 .uleb128 0x18 + 3856 00b1 00 .byte 0 + 3857 00b2 00 .byte 0 + 3858 00b3 0E .uleb128 0xe + 3859 00b4 2E .uleb128 0x2e + 3860 00b5 01 .byte 0x1 + 3861 00b6 3F .uleb128 0x3f + 3862 00b7 19 .uleb128 0x19 + 3863 00b8 03 .uleb128 0x3 + 3864 00b9 0E .uleb128 0xe + 3865 00ba 3A .uleb128 0x3a + 3866 00bb 0B .uleb128 0xb + 3867 00bc 3B .uleb128 0x3b + 3868 00bd 05 .uleb128 0x5 + 3869 00be 27 .uleb128 0x27 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 126 + + + 3870 00bf 19 .uleb128 0x19 + 3871 00c0 49 .uleb128 0x49 + 3872 00c1 13 .uleb128 0x13 + 3873 00c2 11 .uleb128 0x11 + 3874 00c3 01 .uleb128 0x1 + 3875 00c4 12 .uleb128 0x12 + 3876 00c5 06 .uleb128 0x6 + 3877 00c6 40 .uleb128 0x40 + 3878 00c7 18 .uleb128 0x18 + 3879 00c8 9642 .uleb128 0x2116 + 3880 00ca 19 .uleb128 0x19 + 3881 00cb 01 .uleb128 0x1 + 3882 00cc 13 .uleb128 0x13 + 3883 00cd 00 .byte 0 + 3884 00ce 00 .byte 0 + 3885 00cf 0F .uleb128 0xf + 3886 00d0 05 .uleb128 0x5 + 3887 00d1 00 .byte 0 + 3888 00d2 03 .uleb128 0x3 + 3889 00d3 0E .uleb128 0xe + 3890 00d4 3A .uleb128 0x3a + 3891 00d5 0B .uleb128 0xb + 3892 00d6 3B .uleb128 0x3b + 3893 00d7 05 .uleb128 0x5 + 3894 00d8 49 .uleb128 0x49 + 3895 00d9 13 .uleb128 0x13 + 3896 00da 02 .uleb128 0x2 + 3897 00db 18 .uleb128 0x18 + 3898 00dc 00 .byte 0 + 3899 00dd 00 .byte 0 + 3900 00de 10 .uleb128 0x10 + 3901 00df 34 .uleb128 0x34 + 3902 00e0 00 .byte 0 + 3903 00e1 03 .uleb128 0x3 + 3904 00e2 0E .uleb128 0xe + 3905 00e3 3A .uleb128 0x3a + 3906 00e4 0B .uleb128 0xb + 3907 00e5 3B .uleb128 0x3b + 3908 00e6 05 .uleb128 0x5 + 3909 00e7 49 .uleb128 0x49 + 3910 00e8 13 .uleb128 0x13 + 3911 00e9 02 .uleb128 0x2 + 3912 00ea 18 .uleb128 0x18 + 3913 00eb 00 .byte 0 + 3914 00ec 00 .byte 0 + 3915 00ed 11 .uleb128 0x11 + 3916 00ee 2E .uleb128 0x2e + 3917 00ef 00 .byte 0 + 3918 00f0 03 .uleb128 0x3 + 3919 00f1 0E .uleb128 0xe + 3920 00f2 3A .uleb128 0x3a + 3921 00f3 0B .uleb128 0xb + 3922 00f4 3B .uleb128 0x3b + 3923 00f5 05 .uleb128 0x5 + 3924 00f6 27 .uleb128 0x27 + 3925 00f7 19 .uleb128 0x19 + 3926 00f8 49 .uleb128 0x49 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 127 + + + 3927 00f9 13 .uleb128 0x13 + 3928 00fa 11 .uleb128 0x11 + 3929 00fb 01 .uleb128 0x1 + 3930 00fc 12 .uleb128 0x12 + 3931 00fd 06 .uleb128 0x6 + 3932 00fe 40 .uleb128 0x40 + 3933 00ff 18 .uleb128 0x18 + 3934 0100 9742 .uleb128 0x2117 + 3935 0102 19 .uleb128 0x19 + 3936 0103 00 .byte 0 + 3937 0104 00 .byte 0 + 3938 0105 12 .uleb128 0x12 + 3939 0106 2E .uleb128 0x2e + 3940 0107 01 .byte 0x1 + 3941 0108 3F .uleb128 0x3f + 3942 0109 19 .uleb128 0x19 + 3943 010a 03 .uleb128 0x3 + 3944 010b 0E .uleb128 0xe + 3945 010c 3A .uleb128 0x3a + 3946 010d 0B .uleb128 0xb + 3947 010e 3B .uleb128 0x3b + 3948 010f 05 .uleb128 0x5 + 3949 0110 27 .uleb128 0x27 + 3950 0111 19 .uleb128 0x19 + 3951 0112 11 .uleb128 0x11 + 3952 0113 01 .uleb128 0x1 + 3953 0114 12 .uleb128 0x12 + 3954 0115 06 .uleb128 0x6 + 3955 0116 40 .uleb128 0x40 + 3956 0117 18 .uleb128 0x18 + 3957 0118 9642 .uleb128 0x2116 + 3958 011a 19 .uleb128 0x19 + 3959 011b 01 .uleb128 0x1 + 3960 011c 13 .uleb128 0x13 + 3961 011d 00 .byte 0 + 3962 011e 00 .byte 0 + 3963 011f 13 .uleb128 0x13 + 3964 0120 2E .uleb128 0x2e + 3965 0121 01 .byte 0x1 + 3966 0122 3F .uleb128 0x3f + 3967 0123 19 .uleb128 0x19 + 3968 0124 03 .uleb128 0x3 + 3969 0125 0E .uleb128 0xe + 3970 0126 3A .uleb128 0x3a + 3971 0127 0B .uleb128 0xb + 3972 0128 3B .uleb128 0x3b + 3973 0129 05 .uleb128 0x5 + 3974 012a 27 .uleb128 0x27 + 3975 012b 19 .uleb128 0x19 + 3976 012c 49 .uleb128 0x49 + 3977 012d 13 .uleb128 0x13 + 3978 012e 11 .uleb128 0x11 + 3979 012f 01 .uleb128 0x1 + 3980 0130 12 .uleb128 0x12 + 3981 0131 06 .uleb128 0x6 + 3982 0132 40 .uleb128 0x40 + 3983 0133 18 .uleb128 0x18 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 128 + + + 3984 0134 9742 .uleb128 0x2117 + 3985 0136 19 .uleb128 0x19 + 3986 0137 01 .uleb128 0x1 + 3987 0138 13 .uleb128 0x13 + 3988 0139 00 .byte 0 + 3989 013a 00 .byte 0 + 3990 013b 14 .uleb128 0x14 + 3991 013c 2E .uleb128 0x2e + 3992 013d 00 .byte 0 + 3993 013e 3F .uleb128 0x3f + 3994 013f 19 .uleb128 0x19 + 3995 0140 03 .uleb128 0x3 + 3996 0141 0E .uleb128 0xe + 3997 0142 3A .uleb128 0x3a + 3998 0143 0B .uleb128 0xb + 3999 0144 3B .uleb128 0x3b + 4000 0145 05 .uleb128 0x5 + 4001 0146 27 .uleb128 0x27 + 4002 0147 19 .uleb128 0x19 + 4003 0148 49 .uleb128 0x49 + 4004 0149 13 .uleb128 0x13 + 4005 014a 11 .uleb128 0x11 + 4006 014b 01 .uleb128 0x1 + 4007 014c 12 .uleb128 0x12 + 4008 014d 06 .uleb128 0x6 + 4009 014e 40 .uleb128 0x40 + 4010 014f 18 .uleb128 0x18 + 4011 0150 9742 .uleb128 0x2117 + 4012 0152 19 .uleb128 0x19 + 4013 0153 00 .byte 0 + 4014 0154 00 .byte 0 + 4015 0155 15 .uleb128 0x15 + 4016 0156 2E .uleb128 0x2e + 4017 0157 01 .byte 0x1 + 4018 0158 3F .uleb128 0x3f + 4019 0159 19 .uleb128 0x19 + 4020 015a 03 .uleb128 0x3 + 4021 015b 0E .uleb128 0xe + 4022 015c 3A .uleb128 0x3a + 4023 015d 0B .uleb128 0xb + 4024 015e 3B .uleb128 0x3b + 4025 015f 05 .uleb128 0x5 + 4026 0160 27 .uleb128 0x27 + 4027 0161 19 .uleb128 0x19 + 4028 0162 11 .uleb128 0x11 + 4029 0163 01 .uleb128 0x1 + 4030 0164 12 .uleb128 0x12 + 4031 0165 06 .uleb128 0x6 + 4032 0166 40 .uleb128 0x40 + 4033 0167 18 .uleb128 0x18 + 4034 0168 9742 .uleb128 0x2117 + 4035 016a 19 .uleb128 0x19 + 4036 016b 01 .uleb128 0x1 + 4037 016c 13 .uleb128 0x13 + 4038 016d 00 .byte 0 + 4039 016e 00 .byte 0 + 4040 016f 16 .uleb128 0x16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 129 + + + 4041 0170 2E .uleb128 0x2e + 4042 0171 00 .byte 0 + 4043 0172 3F .uleb128 0x3f + 4044 0173 19 .uleb128 0x19 + 4045 0174 03 .uleb128 0x3 + 4046 0175 0E .uleb128 0xe + 4047 0176 3A .uleb128 0x3a + 4048 0177 0B .uleb128 0xb + 4049 0178 3B .uleb128 0x3b + 4050 0179 05 .uleb128 0x5 + 4051 017a 27 .uleb128 0x27 + 4052 017b 19 .uleb128 0x19 + 4053 017c 11 .uleb128 0x11 + 4054 017d 01 .uleb128 0x1 + 4055 017e 12 .uleb128 0x12 + 4056 017f 06 .uleb128 0x6 + 4057 0180 40 .uleb128 0x40 + 4058 0181 18 .uleb128 0x18 + 4059 0182 9642 .uleb128 0x2116 + 4060 0184 19 .uleb128 0x19 + 4061 0185 00 .byte 0 + 4062 0186 00 .byte 0 + 4063 0187 17 .uleb128 0x17 + 4064 0188 2E .uleb128 0x2e + 4065 0189 01 .byte 0x1 + 4066 018a 03 .uleb128 0x3 + 4067 018b 0E .uleb128 0xe + 4068 018c 3A .uleb128 0x3a + 4069 018d 0B .uleb128 0xb + 4070 018e 3B .uleb128 0x3b + 4071 018f 05 .uleb128 0x5 + 4072 0190 27 .uleb128 0x27 + 4073 0191 19 .uleb128 0x19 + 4074 0192 11 .uleb128 0x11 + 4075 0193 01 .uleb128 0x1 + 4076 0194 12 .uleb128 0x12 + 4077 0195 06 .uleb128 0x6 + 4078 0196 40 .uleb128 0x40 + 4079 0197 18 .uleb128 0x18 + 4080 0198 9642 .uleb128 0x2116 + 4081 019a 19 .uleb128 0x19 + 4082 019b 01 .uleb128 0x1 + 4083 019c 13 .uleb128 0x13 + 4084 019d 00 .byte 0 + 4085 019e 00 .byte 0 + 4086 019f 18 .uleb128 0x18 + 4087 01a0 2E .uleb128 0x2e + 4088 01a1 00 .byte 0 + 4089 01a2 03 .uleb128 0x3 + 4090 01a3 0E .uleb128 0xe + 4091 01a4 3A .uleb128 0x3a + 4092 01a5 0B .uleb128 0xb + 4093 01a6 3B .uleb128 0x3b + 4094 01a7 05 .uleb128 0x5 + 4095 01a8 27 .uleb128 0x27 + 4096 01a9 19 .uleb128 0x19 + 4097 01aa 11 .uleb128 0x11 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 130 + + + 4098 01ab 01 .uleb128 0x1 + 4099 01ac 12 .uleb128 0x12 + 4100 01ad 06 .uleb128 0x6 + 4101 01ae 40 .uleb128 0x40 + 4102 01af 18 .uleb128 0x18 + 4103 01b0 9642 .uleb128 0x2116 + 4104 01b2 19 .uleb128 0x19 + 4105 01b3 00 .byte 0 + 4106 01b4 00 .byte 0 + 4107 01b5 19 .uleb128 0x19 + 4108 01b6 01 .uleb128 0x1 + 4109 01b7 01 .byte 0x1 + 4110 01b8 49 .uleb128 0x49 + 4111 01b9 13 .uleb128 0x13 + 4112 01ba 01 .uleb128 0x1 + 4113 01bb 13 .uleb128 0x13 + 4114 01bc 00 .byte 0 + 4115 01bd 00 .byte 0 + 4116 01be 1A .uleb128 0x1a + 4117 01bf 21 .uleb128 0x21 + 4118 01c0 00 .byte 0 + 4119 01c1 49 .uleb128 0x49 + 4120 01c2 13 .uleb128 0x13 + 4121 01c3 2F .uleb128 0x2f + 4122 01c4 0B .uleb128 0xb + 4123 01c5 00 .byte 0 + 4124 01c6 00 .byte 0 + 4125 01c7 1B .uleb128 0x1b + 4126 01c8 26 .uleb128 0x26 + 4127 01c9 00 .byte 0 + 4128 01ca 49 .uleb128 0x49 + 4129 01cb 13 .uleb128 0x13 + 4130 01cc 00 .byte 0 + 4131 01cd 00 .byte 0 + 4132 01ce 1C .uleb128 0x1c + 4133 01cf 34 .uleb128 0x34 + 4134 01d0 00 .byte 0 + 4135 01d1 03 .uleb128 0x3 + 4136 01d2 0E .uleb128 0xe + 4137 01d3 3A .uleb128 0x3a + 4138 01d4 0B .uleb128 0xb + 4139 01d5 3B .uleb128 0x3b + 4140 01d6 0B .uleb128 0xb + 4141 01d7 49 .uleb128 0x49 + 4142 01d8 13 .uleb128 0x13 + 4143 01d9 3F .uleb128 0x3f + 4144 01da 19 .uleb128 0x19 + 4145 01db 3C .uleb128 0x3c + 4146 01dc 19 .uleb128 0x19 + 4147 01dd 00 .byte 0 + 4148 01de 00 .byte 0 + 4149 01df 00 .byte 0 + 4150 .section .debug_aranges,"",%progbits + 4151 0000 34010000 .4byte 0x134 + 4152 0004 0200 .2byte 0x2 + 4153 0006 00000000 .4byte .Ldebug_info0 + 4154 000a 04 .byte 0x4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 131 + + + 4155 000b 00 .byte 0 + 4156 000c 0000 .2byte 0 + 4157 000e 0000 .2byte 0 + 4158 0010 00000000 .4byte .LFB0 + 4159 0014 1C000000 .4byte .LFE0-.LFB0 + 4160 0018 00000000 .4byte .LFB1 + 4161 001c 4C000000 .4byte .LFE1-.LFB1 + 4162 0020 00000000 .4byte .LFB2 + 4163 0024 40000000 .4byte .LFE2-.LFB2 + 4164 0028 00000000 .4byte .LFB3 + 4165 002c 20000000 .4byte .LFE3-.LFB3 + 4166 0030 00000000 .4byte .LFB4 + 4167 0034 58010000 .4byte .LFE4-.LFB4 + 4168 0038 00000000 .4byte .LFB5 + 4169 003c 1C000000 .4byte .LFE5-.LFB5 + 4170 0040 00000000 .4byte .LFB6 + 4171 0044 34000000 .4byte .LFE6-.LFB6 + 4172 0048 00000000 .4byte .LFB7 + 4173 004c 20000000 .4byte .LFE7-.LFB7 + 4174 0050 00000000 .4byte .LFB8 + 4175 0054 50000000 .4byte .LFE8-.LFB8 + 4176 0058 00000000 .4byte .LFB9 + 4177 005c 34000000 .4byte .LFE9-.LFB9 + 4178 0060 00000000 .4byte .LFB10 + 4179 0064 5C000000 .4byte .LFE10-.LFB10 + 4180 0068 00000000 .4byte .LFB11 + 4181 006c 24000000 .4byte .LFE11-.LFB11 + 4182 0070 00000000 .4byte .LFB12 + 4183 0074 6C000000 .4byte .LFE12-.LFB12 + 4184 0078 00000000 .4byte .LFB13 + 4185 007c 44000000 .4byte .LFE13-.LFB13 + 4186 0080 00000000 .4byte .LFB14 + 4187 0084 64000000 .4byte .LFE14-.LFB14 + 4188 0088 00000000 .4byte .LFB15 + 4189 008c 6C000000 .4byte .LFE15-.LFB15 + 4190 0090 00000000 .4byte .LFB16 + 4191 0094 58000000 .4byte .LFE16-.LFB16 + 4192 0098 00000000 .4byte .LFB17 + 4193 009c 1C000000 .4byte .LFE17-.LFB17 + 4194 00a0 00000000 .4byte .LFB18 + 4195 00a4 6C000000 .4byte .LFE18-.LFB18 + 4196 00a8 00000000 .4byte .LFB19 + 4197 00ac 48000000 .4byte .LFE19-.LFB19 + 4198 00b0 00000000 .4byte .LFB20 + 4199 00b4 18000000 .4byte .LFE20-.LFB20 + 4200 00b8 00000000 .4byte .LFB21 + 4201 00bc 40000000 .4byte .LFE21-.LFB21 + 4202 00c0 00000000 .4byte .LFB22 + 4203 00c4 54000000 .4byte .LFE22-.LFB22 + 4204 00c8 00000000 .4byte .LFB23 + 4205 00cc 1C000000 .4byte .LFE23-.LFB23 + 4206 00d0 00000000 .4byte .LFB24 + 4207 00d4 70000000 .4byte .LFE24-.LFB24 + 4208 00d8 00000000 .4byte .LFB25 + 4209 00dc 34000000 .4byte .LFE25-.LFB25 + 4210 00e0 00000000 .4byte .LFB26 + 4211 00e4 40000000 .4byte .LFE26-.LFB26 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 132 + + + 4212 00e8 00000000 .4byte .LFB27 + 4213 00ec 34000000 .4byte .LFE27-.LFB27 + 4214 00f0 00000000 .4byte .LFB28 + 4215 00f4 50000000 .4byte .LFE28-.LFB28 + 4216 00f8 00000000 .4byte .LFB29 + 4217 00fc 3C000000 .4byte .LFE29-.LFB29 + 4218 0100 00000000 .4byte .LFB30 + 4219 0104 EC000000 .4byte .LFE30-.LFB30 + 4220 0108 00000000 .4byte .LFB31 + 4221 010c 8A000000 .4byte .LFE31-.LFB31 + 4222 0110 00000000 .4byte .LFB32 + 4223 0114 98000000 .4byte .LFE32-.LFB32 + 4224 0118 00000000 .4byte .LFB33 + 4225 011c 3C000000 .4byte .LFE33-.LFB33 + 4226 0120 00000000 .4byte .LFB34 + 4227 0124 68000000 .4byte .LFE34-.LFB34 + 4228 0128 00000000 .4byte .LFB35 + 4229 012c B0000000 .4byte .LFE35-.LFB35 + 4230 0130 00000000 .4byte 0 + 4231 0134 00000000 .4byte 0 + 4232 .section .debug_ranges,"",%progbits + 4233 .Ldebug_ranges0: + 4234 0000 00000000 .4byte .LFB0 + 4235 0004 1C000000 .4byte .LFE0 + 4236 0008 00000000 .4byte .LFB1 + 4237 000c 4C000000 .4byte .LFE1 + 4238 0010 00000000 .4byte .LFB2 + 4239 0014 40000000 .4byte .LFE2 + 4240 0018 00000000 .4byte .LFB3 + 4241 001c 20000000 .4byte .LFE3 + 4242 0020 00000000 .4byte .LFB4 + 4243 0024 58010000 .4byte .LFE4 + 4244 0028 00000000 .4byte .LFB5 + 4245 002c 1C000000 .4byte .LFE5 + 4246 0030 00000000 .4byte .LFB6 + 4247 0034 34000000 .4byte .LFE6 + 4248 0038 00000000 .4byte .LFB7 + 4249 003c 20000000 .4byte .LFE7 + 4250 0040 00000000 .4byte .LFB8 + 4251 0044 50000000 .4byte .LFE8 + 4252 0048 00000000 .4byte .LFB9 + 4253 004c 34000000 .4byte .LFE9 + 4254 0050 00000000 .4byte .LFB10 + 4255 0054 5C000000 .4byte .LFE10 + 4256 0058 00000000 .4byte .LFB11 + 4257 005c 24000000 .4byte .LFE11 + 4258 0060 00000000 .4byte .LFB12 + 4259 0064 6C000000 .4byte .LFE12 + 4260 0068 00000000 .4byte .LFB13 + 4261 006c 44000000 .4byte .LFE13 + 4262 0070 00000000 .4byte .LFB14 + 4263 0074 64000000 .4byte .LFE14 + 4264 0078 00000000 .4byte .LFB15 + 4265 007c 6C000000 .4byte .LFE15 + 4266 0080 00000000 .4byte .LFB16 + 4267 0084 58000000 .4byte .LFE16 + 4268 0088 00000000 .4byte .LFB17 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 133 + + + 4269 008c 1C000000 .4byte .LFE17 + 4270 0090 00000000 .4byte .LFB18 + 4271 0094 6C000000 .4byte .LFE18 + 4272 0098 00000000 .4byte .LFB19 + 4273 009c 48000000 .4byte .LFE19 + 4274 00a0 00000000 .4byte .LFB20 + 4275 00a4 18000000 .4byte .LFE20 + 4276 00a8 00000000 .4byte .LFB21 + 4277 00ac 40000000 .4byte .LFE21 + 4278 00b0 00000000 .4byte .LFB22 + 4279 00b4 54000000 .4byte .LFE22 + 4280 00b8 00000000 .4byte .LFB23 + 4281 00bc 1C000000 .4byte .LFE23 + 4282 00c0 00000000 .4byte .LFB24 + 4283 00c4 70000000 .4byte .LFE24 + 4284 00c8 00000000 .4byte .LFB25 + 4285 00cc 34000000 .4byte .LFE25 + 4286 00d0 00000000 .4byte .LFB26 + 4287 00d4 40000000 .4byte .LFE26 + 4288 00d8 00000000 .4byte .LFB27 + 4289 00dc 34000000 .4byte .LFE27 + 4290 00e0 00000000 .4byte .LFB28 + 4291 00e4 50000000 .4byte .LFE28 + 4292 00e8 00000000 .4byte .LFB29 + 4293 00ec 3C000000 .4byte .LFE29 + 4294 00f0 00000000 .4byte .LFB30 + 4295 00f4 EC000000 .4byte .LFE30 + 4296 00f8 00000000 .4byte .LFB31 + 4297 00fc 8A000000 .4byte .LFE31 + 4298 0100 00000000 .4byte .LFB32 + 4299 0104 98000000 .4byte .LFE32 + 4300 0108 00000000 .4byte .LFB33 + 4301 010c 3C000000 .4byte .LFE33 + 4302 0110 00000000 .4byte .LFB34 + 4303 0114 68000000 .4byte .LFE34 + 4304 0118 00000000 .4byte .LFB35 + 4305 011c B0000000 .4byte .LFE35 + 4306 0120 00000000 .4byte 0 + 4307 0124 00000000 .4byte 0 + 4308 .section .debug_line,"",%progbits + 4309 .Ldebug_line0: + 4310 0000 00050000 .section .debug_str,"MS",%progbits,1 + 4310 02005C00 + 4310 00000201 + 4310 FB0E0D00 + 4310 01010101 + 4311 .LASF10: + 4312 0000 75696E74 .ascii "uint16\000" + 4312 313600 + 4313 .LASF90: + 4314 0007 636F756E .ascii "counterIntMaskTbl\000" + 4314 74657249 + 4314 6E744D61 + 4314 736B5462 + 4314 6C00 + 4315 .LASF91: + 4316 0019 63795379 .ascii "cySysWdtCallback\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 134 + + + 4316 73576474 + 4316 43616C6C + 4316 6261636B + 4316 00 + 4317 .LASF42: + 4318 002a 43795379 .ascii "CySysWdtSetMode\000" + 4318 73576474 + 4318 5365744D + 4318 6F646500 + 4319 .LASF38: + 4320 003a 43795379 .ascii "CySysWdtUnlock\000" + 4320 73576474 + 4320 556E6C6F + 4320 636B00 + 4321 .LASF77: + 4322 0049 43795379 .ascii "CySysWatchdogFeed\000" + 4322 73576174 + 4322 6368646F + 4322 67466565 + 4322 6400 + 4323 .LASF41: + 4324 005b 636F756E .ascii "counterNum\000" + 4324 7465724E + 4324 756D00 + 4325 .LASF95: + 4326 0066 43795379 .ascii "CySysClkLfclkPosedgeCatch\000" + 4326 73436C6B + 4326 4C66636C + 4326 6B506F73 + 4326 65646765 + 4327 .LASF60: + 4328 0080 43795379 .ascii "CySysWdtGetCascade\000" + 4328 73576474 + 4328 47657443 + 4328 61736361 + 4328 646500 + 4329 .LASF24: + 4330 0093 43795379 .ascii "CySysClkIloStartMeasurement\000" + 4330 73436C6B + 4330 496C6F53 + 4330 74617274 + 4330 4D656173 + 4331 .LASF86: + 4332 00af 6C66636C .ascii "lfclkPosedgeWdtCounter0Enabled\000" + 4332 6B506F73 + 4332 65646765 + 4332 57647443 + 4332 6F756E74 + 4333 .LASF7: + 4334 00ce 6C6F6E67 .ascii "long long unsigned int\000" + 4334 206C6F6E + 4334 6720756E + 4334 7369676E + 4334 65642069 + 4335 .LASF6: + 4336 00e5 6C6F6E67 .ascii "long long int\000" + 4336 206C6F6E + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 135 + + + 4336 6720696E + 4336 7400 + 4337 .LASF0: + 4338 00f3 7369676E .ascii "signed char\000" + 4338 65642063 + 4338 68617200 + 4339 .LASF70: + 4340 00ff 66756E63 .ascii "function\000" + 4340 74696F6E + 4340 00 + 4341 .LASF28: + 4342 0108 696E7465 .ascii "interruptState\000" + 4342 72727570 + 4342 74537461 + 4342 746500 + 4343 .LASF20: + 4344 0117 63795764 .ascii "cyWdtCallback\000" + 4344 7443616C + 4344 6C626163 + 4344 6B00 + 4345 .LASF19: + 4346 0125 63795F73 .ascii "cy_sys_timer_delaytype_enum\000" + 4346 79735F74 + 4346 696D6572 + 4346 5F64656C + 4346 61797479 + 4347 .LASF59: + 4348 0141 62697473 .ascii "bits\000" + 4348 00 + 4349 .LASF4: + 4350 0146 6C6F6E67 .ascii "long int\000" + 4350 20696E74 + 4350 00 + 4351 .LASF57: + 4352 014f 72656756 .ascii "regValue\000" + 4352 616C7565 + 4352 00 + 4353 .LASF9: + 4354 0158 75696E74 .ascii "uint8\000" + 4354 3800 + 4355 .LASF47: + 4356 015e 656E6162 .ascii "enable\000" + 4356 6C6500 + 4357 .LASF13: + 4358 0165 646F7562 .ascii "double\000" + 4358 6C6500 + 4359 .LASF27: + 4360 016c 636F6D70 .ascii "compensatedCycles\000" + 4360 656E7361 + 4360 74656443 + 4360 79636C65 + 4360 7300 + 4361 .LASF34: + 4362 017e 43795379 .ascii "CySysClkIloStop\000" + 4362 73436C6B + 4362 496C6F53 + 4362 746F7000 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 136 + + + 4363 .LASF29: + 4364 018e 696C6F43 .ascii "iloCompensatedCycles\000" + 4364 6F6D7065 + 4364 6E736174 + 4364 65644379 + 4364 636C6573 + 4365 .LASF68: + 4366 01a3 636F756E .ascii "countersMask\000" + 4366 74657273 + 4366 4D61736B + 4366 00 + 4367 .LASF11: + 4368 01b0 75696E74 .ascii "uint32\000" + 4368 333200 + 4369 .LASF94: + 4370 01b7 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 4370 73657273 + 4370 5C6A6167 + 4370 756D6965 + 4370 6C5C446F + 4371 01e5 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 4371 50536F43 + 4371 2D313031 + 4371 5C547261 + 4371 696E696E + 4372 .LASF25: + 4373 0212 43795379 .ascii "CySysClkIloStopMeasurement\000" + 4373 73436C6B + 4373 496C6F53 + 4373 746F704D + 4373 65617375 + 4374 .LASF71: + 4375 022d 70726576 .ascii "prevCallback\000" + 4375 43616C6C + 4375 6261636B + 4375 00 + 4376 .LASF55: + 4377 023a 43795379 .ascii "CySysWdtSetMatch\000" + 4377 73576474 + 4377 5365744D + 4377 61746368 + 4377 00 + 4378 .LASF54: + 4379 024b 636F756E .ascii "countersEnableStatus\000" + 4379 74657273 + 4379 456E6162 + 4379 6C655374 + 4379 61747573 + 4380 .LASF89: + 4381 0260 77647449 .ascii "wdtIsrMask\000" + 4381 73724D61 + 4381 736B00 + 4382 .LASF49: + 4383 026b 43795379 .ascii "CySysWdtEnable\000" + 4383 73576474 + 4383 456E6162 + 4383 6C6500 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 137 + + + 4384 .LASF69: + 4385 027a 43795379 .ascii "CySysWdtSetInterruptCallback\000" + 4385 73576474 + 4385 53657449 + 4385 6E746572 + 4385 72757074 + 4386 .LASF50: + 4387 0297 636F756E .ascii "counterMask\000" + 4387 7465724D + 4387 61736B00 + 4388 .LASF48: + 4389 02a3 43795379 .ascii "CySysWdtGetClearOnMatch\000" + 4389 73576474 + 4389 47657443 + 4389 6C656172 + 4389 4F6E4D61 + 4390 .LASF8: + 4391 02bb 756E7369 .ascii "unsigned int\000" + 4391 676E6564 + 4391 20696E74 + 4391 00 + 4392 .LASF78: + 4393 02c8 66697273 .ascii "firstCount\000" + 4393 74436F75 + 4393 6E7400 + 4394 .LASF73: + 4395 02d3 72657443 .ascii "retCallback\000" + 4395 616C6C62 + 4395 61636B00 + 4396 .LASF26: + 4397 02df 64657369 .ascii "desiredDelay\000" + 4397 72656444 + 4397 656C6179 + 4397 00 + 4398 .LASF5: + 4399 02ec 6C6F6E67 .ascii "long unsigned int\000" + 4399 20756E73 + 4399 69676E65 + 4399 6420696E + 4399 7400 + 4400 .LASF83: + 4401 02fe 6D617463 .ascii "matchValue\000" + 4401 6856616C + 4401 756500 + 4402 .LASF96: + 4403 0309 43795379 .ascii "CySysClkLfclkPosedgeRestore\000" + 4403 73436C6B + 4403 4C66636C + 4403 6B506F73 + 4403 65646765 + 4404 .LASF74: + 4405 0325 43795379 .ascii "CySysWdtEnableCounterIsr\000" + 4405 73576474 + 4405 456E6162 + 4405 6C65436F + 4405 756E7465 + 4406 .LASF3: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cccfkIBG.s page 138 + + + 4407 033e 73686F72 .ascii "short unsigned int\000" + 4407 7420756E + 4407 7369676E + 4407 65642069 + 4407 6E7400 + 4408 .LASF40: + 4409 0351 43795379 .ascii "CySysWdtGetEnabledStatus\000" + 4409 73576474 + 4409 47657445 + 4409 6E61626C + 4409 65645374 + 4410 .LASF72: + 4411 036a 43795379 .ascii "CySysWdtGetInterruptCallback\000" + 4411 73576474 + 4411 47657449 + 4411 6E746572 + 4411 72757074 + 4412 .LASF76: + 4413 0387 43795379 .ascii "CySysWdtIsr\000" + 4413 73576474 + 4413 49737200 + 4414 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zf-dl<96zN?#MsZ_&_`A2L(QR8dJom=H^$N|bviN`t4^Xa3QQhnrHOQPr3s~PwW$Gcpp|t z&@FgNb_j1~y9T7U#D+((n$!U7QKAlKTY?1aAYRG zeBj|b3_f>^jozPt&#gBBy`^ZQ-XeUA-cM0?>wO;bf@m|v$eRHsH{V;}!|jGs3||qL z++r}s<+88bC2znZ zkLNu#j%M;`Bg+A_#{+#~N5mtW?%lYYP8k#`XtndbYpN8bA`dGlQIcpr>^&VJRCrOp!2Bn$Pj z@V?odSN=8XnSu7!>t>DD{frFWrA@68^0tFZZO zM87F!9<3gED*L8?-7r@HkZ8Xz-i?1{MH?hr8$}7@wSI=BlyNL=zYVZw+nigfRA~w z)TQ@dJ@Q_JyiEH`8P==YzKh@sL5?YAzI;A*=RpE`&3=ld5CdzBY$H?o~ z^3Wv9))qJfG z^rMbx gTb=R=> CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT) + 216:Generated_Source\PSoC4/CyLib.c **** (uint32) CY_SYS_CLK_SELECT_HFCLK_DIV_MASK)); + 217:Generated_Source\PSoC4/CyLib.c **** #else + 218:Generated_Source\PSoC4/CyLib.c **** freq = ((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_ + 219:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_ + 220:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSLT) */ + 221:Generated_Source\PSoC4/CyLib.c **** + 222:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ + 223:Generated_Source\PSoC4/CyLib.c **** + 224:Generated_Source\PSoC4/CyLib.c **** /* For the WCO locking mode, the IMO gain needs to be CY_SYS_CLK_IMO_TRIM4_GAIN */ + 225:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) + 226:Generated_Source\PSoC4/CyLib.c **** if ((CY_SYS_CLK_IMO_TRIM4_REG & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) == 0u) + 227:Generated_Source\PSoC4/CyLib.c **** { + 228:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM4_REG = (CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_G + 229:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM4_WCO_GAIN; + 230:Generated_Source\PSoC4/CyLib.c **** } + 231:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ + 232:Generated_Source\PSoC4/CyLib.c **** + 233:Generated_Source\PSoC4/CyLib.c **** regTmp = CY_SYS_CLK_WCO_DPLL_REG & ~(CY_SYS_CLK_WCO_DPLL_MULT_MASK | + 234:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK | + 235:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK | + 236:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK); + 237:Generated_Source\PSoC4/CyLib.c **** + 238:Generated_Source\PSoC4/CyLib.c **** /* Set multiplier to determine IMO frequency in multiples of the WCO frequency */ + 239:Generated_Source\PSoC4/CyLib.c **** regTmp |= (CY_SYS_CLK_WCO_DPLL_MULT_VALUE(freq) & CY_SYS_CLK_WCO_DPLL_MULT_MASK); + 240:Generated_Source\PSoC4/CyLib.c **** + 241:Generated_Source\PSoC4/CyLib.c **** /* Set DPLL Loop Filter Integral and Proportional Gains Setting */ + 242:Generated_Source\PSoC4/CyLib.c **** regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN | CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN); + 243:Generated_Source\PSoC4/CyLib.c **** + 244:Generated_Source\PSoC4/CyLib.c **** /* Set maximum allowed IMO offset */ + 245:Generated_Source\PSoC4/CyLib.c **** if (freq < CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT) + 246:Generated_Source\PSoC4/CyLib.c **** { + 247:Generated_Source\PSoC4/CyLib.c **** regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX << CY_SYS_CLK_WCO_CONFIG_DPLL_LF + 248:Generated_Source\PSoC4/CyLib.c **** } + 249:Generated_Source\PSoC4/CyLib.c **** else + 250:Generated_Source\PSoC4/CyLib.c **** { + 251:Generated_Source\PSoC4/CyLib.c **** lfLimit = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + + 252:Generated_Source\PSoC4/CyLib.c **** cyImoFreqMhz2DpllOffset[freq - CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET]; + 253:Generated_Source\PSoC4/CyLib.c **** + 254:Generated_Source\PSoC4/CyLib.c **** lfLimit = (lfLimit > CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX) ? + 255:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX : lfLimit; + 256:Generated_Source\PSoC4/CyLib.c **** + 257:Generated_Source\PSoC4/CyLib.c **** regTmp |= (lfLimit << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 9 + + + 258:Generated_Source\PSoC4/CyLib.c **** } + 259:Generated_Source\PSoC4/CyLib.c **** + 260:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_WCO_DPLL_REG = regTmp; + 261:Generated_Source\PSoC4/CyLib.c **** + 262:Generated_Source\PSoC4/CyLib.c **** flashCtlReg = CY_FLASH_CTL_REG; + 263:Generated_Source\PSoC4/CyLib.c **** CySysFlashSetWaitCycles(CY_SYS_CLK_IMO_MAX_FREQ_MHZ); + 264:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + 265:Generated_Source\PSoC4/CyLib.c **** CyDelay(CY_SYS_CLK_WCO_IMO_TIMEOUT_MS); + 266:Generated_Source\PSoC4/CyLib.c **** CY_FLASH_CTL_REG = flashCtlReg; + 267:Generated_Source\PSoC4/CyLib.c **** + 268:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); + 269:Generated_Source\PSoC4/CyLib.c **** } + 270:Generated_Source\PSoC4/CyLib.c **** } + 271:Generated_Source\PSoC4/CyLib.c **** + 272:Generated_Source\PSoC4/CyLib.c **** + 273:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 274:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkImoDisableWcoLock + 275:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 276:Generated_Source\PSoC4/CyLib.c **** * + 277:Generated_Source\PSoC4/CyLib.c **** * Disables the IMO to WCO lock feature. + 278:Generated_Source\PSoC4/CyLib.c **** * + 279:Generated_Source\PSoC4/CyLib.c **** * For PSoC 4200L devices, note that the IMO can lock to either WCO or USB + 280:Generated_Source\PSoC4/CyLib.c **** * but not both. + 281:Generated_Source\PSoC4/CyLib.c **** * + 282:Generated_Source\PSoC4/CyLib.c **** * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + 283:Generated_Source\PSoC4/CyLib.c **** * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + 284:Generated_Source\PSoC4/CyLib.c **** * + 285:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 286:Generated_Source\PSoC4/CyLib.c **** void CySysClkImoDisableWcoLock(void) + 287:Generated_Source\PSoC4/CyLib.c **** { + 288:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + 289:Generated_Source\PSoC4/CyLib.c **** } + 290:Generated_Source\PSoC4/CyLib.c **** + 291:Generated_Source\PSoC4/CyLib.c **** + 292:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 293:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkImoGetWcoLock + 294:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 295:Generated_Source\PSoC4/CyLib.c **** * + 296:Generated_Source\PSoC4/CyLib.c **** * Reports the IMO to WCO lock enable state. + 297:Generated_Source\PSoC4/CyLib.c **** * + 298:Generated_Source\PSoC4/CyLib.c **** * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + 299:Generated_Source\PSoC4/CyLib.c **** * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + 300:Generated_Source\PSoC4/CyLib.c **** * + 301:Generated_Source\PSoC4/CyLib.c **** * \return 1 if IMO to WCO lock is enabled. + 302:Generated_Source\PSoC4/CyLib.c **** * \return 0 if IMO to WCO lock is disabled. + 303:Generated_Source\PSoC4/CyLib.c **** * + 304:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 305:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkImoGetWcoLock(void) + 306:Generated_Source\PSoC4/CyLib.c **** { + 307:Generated_Source\PSoC4/CyLib.c **** return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE)) ? + 308:Generated_Source\PSoC4/CyLib.c **** (uint32) 1u : + 309:Generated_Source\PSoC4/CyLib.c **** (uint32) 0u); + 310:Generated_Source\PSoC4/CyLib.c **** } + 311:Generated_Source\PSoC4/CyLib.c **** + 312:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + 313:Generated_Source\PSoC4/CyLib.c **** + 314:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 10 + + + 315:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) + 316:Generated_Source\PSoC4/CyLib.c **** + 317:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 318:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkImoEnableUsbLock + 319:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 320:Generated_Source\PSoC4/CyLib.c **** * + 321:Generated_Source\PSoC4/CyLib.c **** * Enables the IMO to USB lock feature. + 322:Generated_Source\PSoC4/CyLib.c **** * + 323:Generated_Source\PSoC4/CyLib.c **** * This function must be called before CySysClkWriteImoFreq(). + 324:Generated_Source\PSoC4/CyLib.c **** * + 325:Generated_Source\PSoC4/CyLib.c **** * This function is called from CySysClkImoStart() function if USB lock + 326:Generated_Source\PSoC4/CyLib.c **** * selected in the Design Wide Resources tab. + 327:Generated_Source\PSoC4/CyLib.c **** * + 328:Generated_Source\PSoC4/CyLib.c **** * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + 329:Generated_Source\PSoC4/CyLib.c **** * devices, the IMO can lock to either WCO or USB, but not both. + 330:Generated_Source\PSoC4/CyLib.c **** * + 331:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 332:Generated_Source\PSoC4/CyLib.c **** void CySysClkImoEnableUsbLock(void) + 333:Generated_Source\PSoC4/CyLib.c **** { + 334:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) + 335:Generated_Source\PSoC4/CyLib.c **** uint32 i; + 336:Generated_Source\PSoC4/CyLib.c **** + 337:Generated_Source\PSoC4/CyLib.c **** /* Check for new trim algorithm */ + 338:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_R + 339:Generated_Source\PSoC4/CyLib.c **** CY_SFLASH_S1_TESTPGM_RE + 340:Generated_Source\PSoC4/CyLib.c **** + 341:Generated_Source\PSoC4/CyLib.c **** /* Get current IMO frequency based on the register value */ + 342:Generated_Source\PSoC4/CyLib.c **** uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + 343:Generated_Source\PSoC4/CyLib.c **** + 344:Generated_Source\PSoC4/CyLib.c **** for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + 345:Generated_Source\PSoC4/CyLib.c **** { + 346:Generated_Source\PSoC4/CyLib.c **** if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreq + 347:Generated_Source\PSoC4/CyLib.c **** { + 348:Generated_Source\PSoC4/CyLib.c **** freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + 349:Generated_Source\PSoC4/CyLib.c **** break; + 350:Generated_Source\PSoC4/CyLib.c **** } + 351:Generated_Source\PSoC4/CyLib.c **** } + 352:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ + 353:Generated_Source\PSoC4/CyLib.c **** + 354:Generated_Source\PSoC4/CyLib.c **** /* Set oscillator interface control port to USB */ + 355:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + 356:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_OSCINTF_CTL_REG = (CY_SYS_CLK_OSCINTF_CTL_REG & (uint32) ~CY_SYS_CLK_OSCINTF + 357:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_USB; + 358:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + 359:Generated_Source\PSoC4/CyLib.c **** + 360:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) + 361:Generated_Source\PSoC4/CyLib.c **** + 362:Generated_Source\PSoC4/CyLib.c **** /* Save CY_SYS_CLK_IMO_TRIM4_REG and set IMO gain for USB lock */ + 363:Generated_Source\PSoC4/CyLib.c **** CySysClkImoTrim4 = CY_SYS_CLK_IMO_TRIM4_REG; + 364:Generated_Source\PSoC4/CyLib.c **** + 365:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkUsbCuSortTrim) + 366:Generated_Source\PSoC4/CyLib.c **** { + 367:Generated_Source\PSoC4/CyLib.c **** CySysClkImoTrim5 = CY_PWR_BG_TRIM5_REG; + 368:Generated_Source\PSoC4/CyLib.c **** + 369:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_ + 370:Generated_Source\PSoC4/CyLib.c **** CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG; + 371:Generated_Source\PSoC4/CyLib.c **** CY_PWR_BG_TRIM5_REG = CY_SFLASH_USBMODE_IMO_TEMPCO_REG; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 11 + + + 372:Generated_Source\PSoC4/CyLib.c **** + 373:Generated_Source\PSoC4/CyLib.c **** } + 374:Generated_Source\PSoC4/CyLib.c **** else + 375:Generated_Source\PSoC4/CyLib.c **** { + 376:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_ + 377:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM4_USB_GAIN; + 378:Generated_Source\PSoC4/CyLib.c **** + 379:Generated_Source\PSoC4/CyLib.c **** } + 380:Generated_Source\PSoC4/CyLib.c **** + 381:Generated_Source\PSoC4/CyLib.c **** if (48u == freq) + 382:Generated_Source\PSoC4/CyLib.c **** { + 383:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + 384:Generated_Source\PSoC4/CyLib.c **** (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_48_REG : + 385:Generated_Source\PSoC4/CyLib.c **** (uint32)CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + 386:Generated_Source\PSoC4/CyLib.c **** } + 387:Generated_Source\PSoC4/CyLib.c **** else if (24u == freq) + 388:Generated_Source\PSoC4/CyLib.c **** { + 389:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + 390:Generated_Source\PSoC4/CyLib.c **** (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_24_REG : + 391:Generated_Source\PSoC4/CyLib.c **** (uint32)CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + 392:Generated_Source\PSoC4/CyLib.c **** } + 393:Generated_Source\PSoC4/CyLib.c **** else + 394:Generated_Source\PSoC4/CyLib.c **** { + 395:Generated_Source\PSoC4/CyLib.c **** /* Do nothing */ + 396:Generated_Source\PSoC4/CyLib.c **** } + 397:Generated_Source\PSoC4/CyLib.c **** + 398:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ + 399:Generated_Source\PSoC4/CyLib.c **** + 400:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_USBDEVv2_CR1_REG |= CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + 401:Generated_Source\PSoC4/CyLib.c **** } + 402:Generated_Source\PSoC4/CyLib.c **** + 403:Generated_Source\PSoC4/CyLib.c **** + 404:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 405:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkImoDisableUsbLock + 406:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 407:Generated_Source\PSoC4/CyLib.c **** * + 408:Generated_Source\PSoC4/CyLib.c **** * Disables the IMO to USB lock feature. + 409:Generated_Source\PSoC4/CyLib.c **** * + 410:Generated_Source\PSoC4/CyLib.c **** * This function is called from CySysClkImoStop() function if USB lock selected + 411:Generated_Source\PSoC4/CyLib.c **** * in the Design Wide Resources tab. + 412:Generated_Source\PSoC4/CyLib.c **** * + 413:Generated_Source\PSoC4/CyLib.c **** * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + 414:Generated_Source\PSoC4/CyLib.c **** * devices, the IMO can lock to either WCO or USB, but not both. + 415:Generated_Source\PSoC4/CyLib.c **** * + 416:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 417:Generated_Source\PSoC4/CyLib.c **** void CySysClkImoDisableUsbLock(void) + 418:Generated_Source\PSoC4/CyLib.c **** { + 419:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) + 420:Generated_Source\PSoC4/CyLib.c **** uint32 i; + 421:Generated_Source\PSoC4/CyLib.c **** + 422:Generated_Source\PSoC4/CyLib.c **** /* Check for new trim algorithm */ + 423:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_R + 424:Generated_Source\PSoC4/CyLib.c **** CY_SFLASH_S1_TESTPGM_RE + 425:Generated_Source\PSoC4/CyLib.c **** + 426:Generated_Source\PSoC4/CyLib.c **** /* Get current IMO frequency based on the register value */ + 427:Generated_Source\PSoC4/CyLib.c **** uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ;; + 428:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 12 + + + 429:Generated_Source\PSoC4/CyLib.c **** for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + 430:Generated_Source\PSoC4/CyLib.c **** { + 431:Generated_Source\PSoC4/CyLib.c **** if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreq + 432:Generated_Source\PSoC4/CyLib.c **** { + 433:Generated_Source\PSoC4/CyLib.c **** freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + 434:Generated_Source\PSoC4/CyLib.c **** break; + 435:Generated_Source\PSoC4/CyLib.c **** } + 436:Generated_Source\PSoC4/CyLib.c **** } + 437:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ + 438:Generated_Source\PSoC4/CyLib.c **** + 439:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_USBDEVv2_CR1_REG &= (uint32) ~CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + 440:Generated_Source\PSoC4/CyLib.c **** + 441:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) + 442:Generated_Source\PSoC4/CyLib.c **** /* Restore CY_SYS_CLK_IMO_TRIM4_REG */ + 443:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM4_REG = ((CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_ + 444:Generated_Source\PSoC4/CyLib.c **** (CySysClkImoTrim4 & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK)); + 445:Generated_Source\PSoC4/CyLib.c **** + 446:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkUsbCuSortTrim) + 447:Generated_Source\PSoC4/CyLib.c **** { + 448:Generated_Source\PSoC4/CyLib.c **** CY_PWR_BG_TRIM5_REG = CySysClkImoTrim5; + 449:Generated_Source\PSoC4/CyLib.c **** } + 450:Generated_Source\PSoC4/CyLib.c **** + 451:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM1_REG = CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFS + 452:Generated_Source\PSoC4/CyLib.c **** + 453:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ + 454:Generated_Source\PSoC4/CyLib.c **** } + 455:Generated_Source\PSoC4/CyLib.c **** + 456:Generated_Source\PSoC4/CyLib.c **** + 457:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 458:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkImoGetUsbLock + 459:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 460:Generated_Source\PSoC4/CyLib.c **** * + 461:Generated_Source\PSoC4/CyLib.c **** * Reports the IMO to USB lock enable state. + 462:Generated_Source\PSoC4/CyLib.c **** * + 463:Generated_Source\PSoC4/CyLib.c **** * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + 464:Generated_Source\PSoC4/CyLib.c **** * devices, the IMO can lock to either WCO or USB, but not both. + 465:Generated_Source\PSoC4/CyLib.c **** * + 466:Generated_Source\PSoC4/CyLib.c **** * \return 1 if IMO to USB lock is enabled. + 467:Generated_Source\PSoC4/CyLib.c **** * \return 0 if IMO to USB lock is disabled. + 468:Generated_Source\PSoC4/CyLib.c **** * + 469:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 470:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkImoGetUsbLock(void) + 471:Generated_Source\PSoC4/CyLib.c **** { + 472:Generated_Source\PSoC4/CyLib.c **** return ((0u != (CY_SYS_CLK_USBDEVv2_CR1_REG & CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK)) ? + 473:Generated_Source\PSoC4/CyLib.c **** (uint32) 1u : + 474:Generated_Source\PSoC4/CyLib.c **** (uint32) 0u); + 475:Generated_Source\PSoC4/CyLib.c **** } + 476:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + 477:Generated_Source\PSoC4/CyLib.c **** + 478:Generated_Source\PSoC4/CyLib.c **** + 479:Generated_Source\PSoC4/CyLib.c **** + 480:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 481:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkWriteHfclkDirect + 482:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 483:Generated_Source\PSoC4/CyLib.c **** * + 484:Generated_Source\PSoC4/CyLib.c **** * Selects the direct source for the HFCLK. + 485:Generated_Source\PSoC4/CyLib.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 13 + + + 486:Generated_Source\PSoC4/CyLib.c **** * The new source must be running and stable before calling this function. + 487:Generated_Source\PSoC4/CyLib.c **** * + 488:Generated_Source\PSoC4/CyLib.c **** * PSoC 4000: + 489:Generated_Source\PSoC4/CyLib.c **** * The SYSCLK has a maximum speed of 16 MHz, so HFCLK and SYSCLK dividers should + 490:Generated_Source\PSoC4/CyLib.c **** * be selected in a way to not to exceed 16 MHz for the System clock. + 491:Generated_Source\PSoC4/CyLib.c **** * + 492:Generated_Source\PSoC4/CyLib.c **** * If the SYSCLK clock frequency increases during device operation, call + 493:Generated_Source\PSoC4/CyLib.c **** * CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number + 494:Generated_Source\PSoC4/CyLib.c **** * of clock cycles the cache will wait before sampling data comes back from + 495:Generated_Source\PSoC4/CyLib.c **** * Flash. If the SYSCLK clock frequency decreases, you can call + 496:Generated_Source\PSoC4/CyLib.c **** * CySysFlashSetWaitCycles() to improve the CPU performance. See + 497:Generated_Source\PSoC4/CyLib.c **** * CySysFlashSetWaitCycles() description for more information. + 498:Generated_Source\PSoC4/CyLib.c **** * + 499:Generated_Source\PSoC4/CyLib.c **** * Do not select PLL as the source for HFCLK if PLL output frequency exceeds + 500:Generated_Source\PSoC4/CyLib.c **** * maximum permissible value for HFCLK. + 501:Generated_Source\PSoC4/CyLib.c **** * + 502:Generated_Source\PSoC4/CyLib.c **** * \param clkSelect One of the available HFCLK direct sources. + 503:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_HFCLK_IMO IMO. + 504:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_HFCLK_EXTCLK External clock pin. + 505:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_HFCLK_ECO External crystal oscillator. Applicable for + 506:Generated_Source\PSoC4/CyLib.c **** * PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / + 507:Generated_Source\PSoC4/CyLib.c **** * 4100S with ECO. + 508:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_HFCLK_PLL0 PLL#0. Applicable for PSoC 4200L / + 509:Generated_Source\PSoC4/CyLib.c **** * 4100S with PLL. + 510:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_HFCLK_PLL1 PLL#1. Applicable for PSoC 4200L. + 511:Generated_Source\PSoC4/CyLib.c **** * + 512:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 513:Generated_Source\PSoC4/CyLib.c **** void CySysClkWriteHfclkDirect(uint32 clkSelect) + 514:Generated_Source\PSoC4/CyLib.c **** { + 196 .loc 1 514 0 + 197 .cfi_startproc + 198 @ args = 0, pretend = 0, frame = 16 + 199 @ frame_needed = 1, uses_anonymous_args = 0 + 200 0000 90B5 push {r4, r7, lr} + 201 .cfi_def_cfa_offset 12 + 202 .cfi_offset 4, -12 + 203 .cfi_offset 7, -8 + 204 .cfi_offset 14, -4 + 205 0002 85B0 sub sp, sp, #20 + 206 .cfi_def_cfa_offset 32 + 207 0004 00AF add r7, sp, #0 + 208 .cfi_def_cfa_register 7 + 209 0006 7860 str r0, [r7, #4] + 515:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; + 516:Generated_Source\PSoC4/CyLib.c **** uint32 tmpReg; + 517:Generated_Source\PSoC4/CyLib.c **** + 518:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_SRSSLT && CY_IP_PLL) + 519:Generated_Source\PSoC4/CyLib.c **** uint8 i = 0u; + 520:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + 521:Generated_Source\PSoC4/CyLib.c **** + 522:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); + 210 .loc 1 522 0 + 211 0008 0F23 movs r3, #15 + 212 000a FC18 adds r4, r7, r3 + 213 000c FFF7FEFF bl CyEnterCriticalSection + 214 0010 0300 movs r3, r0 + 215 0012 2370 strb r3, [r4] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 14 + + + 523:Generated_Source\PSoC4/CyLib.c **** + 524:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_SRSSLT && CY_IP_PLL) + 525:Generated_Source\PSoC4/CyLib.c **** if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_ECO == clkSelect)) + 526:Generated_Source\PSoC4/CyLib.c **** { + 527:Generated_Source\PSoC4/CyLib.c **** tmpReg = CY_SYS_CLK_SELECT_REG & ~CY_SYS_CLK_SELECT_DIRECT_SEL_MASK; + 528:Generated_Source\PSoC4/CyLib.c **** tmpReg |= CY_SYS_CLK_HFCLK_IMO; + 529:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_REG = tmpReg; + 530:Generated_Source\PSoC4/CyLib.c **** + 531:Generated_Source\PSoC4/CyLib.c **** /* SRSSLT block does not have registers to select PLL. It is part of EXCO */ + 532:Generated_Source\PSoC4/CyLib.c **** tmpReg = CY_SYS_ECO_CLK_SELECT_REG & ~CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK; + 533:Generated_Source\PSoC4/CyLib.c **** tmpReg |= ((clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_PLL_MASK) >> CY_SYS_CLK_SELECT_HFCLK_PL + 534:Generated_Source\PSoC4/CyLib.c **** CY_SYS_ECO_CLK_SELECT_REG = tmpReg; + 535:Generated_Source\PSoC4/CyLib.c **** + 536:Generated_Source\PSoC4/CyLib.c **** /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ + 537:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + 538:Generated_Source\PSoC4/CyLib.c **** + 539:Generated_Source\PSoC4/CyLib.c **** for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) + 540:Generated_Source\PSoC4/CyLib.c **** { + 541:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + 542:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + 543:Generated_Source\PSoC4/CyLib.c **** } + 544:Generated_Source\PSoC4/CyLib.c **** + 545:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + 546:Generated_Source\PSoC4/CyLib.c **** } + 547:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + 548:Generated_Source\PSoC4/CyLib.c **** + 549:Generated_Source\PSoC4/CyLib.c **** tmpReg = CY_SYS_CLK_SELECT_REG & ~(CY_SYS_CLK_SELECT_DIRECT_SEL_MASK | + 216 .loc 1 549 0 + 217 0014 0B4B ldr r3, .L8 + 218 0016 1B68 ldr r3, [r3] + 219 0018 0722 movs r2, #7 + 220 001a 9343 bics r3, r2 + 221 001c BB60 str r3, [r7, #8] + 550:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + 551:Generated_Source\PSoC4/CyLib.c **** + 552:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_SRSSV2 && CY_IP_PLL) + 553:Generated_Source\PSoC4/CyLib.c **** if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_PLL1 == clkSelect)) + 554:Generated_Source\PSoC4/CyLib.c **** { + 555:Generated_Source\PSoC4/CyLib.c **** tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + 556:Generated_Source\PSoC4/CyLib.c **** } + 557:Generated_Source\PSoC4/CyLib.c **** else + 558:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + 559:Generated_Source\PSoC4/CyLib.c **** { + 560:Generated_Source\PSoC4/CyLib.c **** tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + 222 .loc 1 560 0 + 223 001e 7B68 ldr r3, [r7, #4] + 224 0020 0722 movs r2, #7 + 225 0022 1340 ands r3, r2 + 226 0024 BA68 ldr r2, [r7, #8] + 227 0026 1343 orrs r3, r2 + 228 0028 BB60 str r3, [r7, #8] + 561:Generated_Source\PSoC4/CyLib.c **** } + 562:Generated_Source\PSoC4/CyLib.c **** + 563:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_REG = tmpReg; + 229 .loc 1 563 0 + 230 002a 064B ldr r3, .L8 + 231 002c BA68 ldr r2, [r7, #8] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 15 + + + 232 002e 1A60 str r2, [r3] + 564:Generated_Source\PSoC4/CyLib.c **** + 565:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); + 233 .loc 1 565 0 + 234 0030 0F23 movs r3, #15 + 235 0032 FB18 adds r3, r7, r3 + 236 0034 1B78 ldrb r3, [r3] + 237 0036 1800 movs r0, r3 + 238 0038 FFF7FEFF bl CyExitCriticalSection + 566:Generated_Source\PSoC4/CyLib.c **** } + 239 .loc 1 566 0 + 240 003c C046 nop + 241 003e BD46 mov sp, r7 + 242 0040 05B0 add sp, sp, #20 + 243 @ sp needed + 244 0042 90BD pop {r4, r7, pc} + 245 .L9: + 246 .align 2 + 247 .L8: + 248 0044 00010B40 .word 1074462976 + 249 .cfi_endproc + 250 .LFE2: + 251 .size CySysClkWriteHfclkDirect, .-CySysClkWriteHfclkDirect + 252 .section .text.CySysEnablePumpClock,"ax",%progbits + 253 .align 2 + 254 .global CySysEnablePumpClock + 255 .code 16 + 256 .thumb_func + 257 .type CySysEnablePumpClock, %function + 258 CySysEnablePumpClock: + 259 .LFB3: + 567:Generated_Source\PSoC4/CyLib.c **** + 568:Generated_Source\PSoC4/CyLib.c **** + 569:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 570:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysEnablePumpClock + 571:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 572:Generated_Source\PSoC4/CyLib.c **** * + 573:Generated_Source\PSoC4/CyLib.c **** * Enables / disables the pump clock. + 574:Generated_Source\PSoC4/CyLib.c **** * + 575:Generated_Source\PSoC4/CyLib.c **** * \param enable + 576:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_PUMP_DISABLE - Disables the pump clock + 577:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_PUMP_ENABLE - Enables and restores the operating source of + 578:Generated_Source\PSoC4/CyLib.c **** * the pump clock. + 579:Generated_Source\PSoC4/CyLib.c **** * + 580:Generated_Source\PSoC4/CyLib.c **** * \sideeffect + 581:Generated_Source\PSoC4/CyLib.c **** * Enabling/disabling the pump clock does not guarantee glitch free operation + 582:Generated_Source\PSoC4/CyLib.c **** * when changing the IMO parameters or clock divider settings. + 583:Generated_Source\PSoC4/CyLib.c **** * + 584:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 585:Generated_Source\PSoC4/CyLib.c **** void CySysEnablePumpClock(uint32 enable) + 586:Generated_Source\PSoC4/CyLib.c **** { + 260 .loc 1 586 0 + 261 .cfi_startproc + 262 @ args = 0, pretend = 0, frame = 8 + 263 @ frame_needed = 1, uses_anonymous_args = 0 + 264 0000 80B5 push {r7, lr} + 265 .cfi_def_cfa_offset 8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 16 + + + 266 .cfi_offset 7, -8 + 267 .cfi_offset 14, -4 + 268 0002 82B0 sub sp, sp, #8 + 269 .cfi_def_cfa_offset 16 + 270 0004 00AF add r7, sp, #0 + 271 .cfi_def_cfa_register 7 + 272 0006 7860 str r0, [r7, #4] + 587:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) + 588:Generated_Source\PSoC4/CyLib.c **** if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + 273 .loc 1 588 0 + 274 0008 7B68 ldr r3, [r7, #4] + 275 000a 0122 movs r2, #1 + 276 000c 1340 ands r3, r2 + 277 000e 08D0 beq .L11 + 589:Generated_Source\PSoC4/CyLib.c **** { + 590:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_CONFIG_REG |= (CySysClkPumpConfig << CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIF + 278 .loc 1 590 0 + 279 0010 0C4A ldr r2, .L14 + 280 0012 0C4B ldr r3, .L14 + 281 0014 1968 ldr r1, [r3] + 282 0016 0C4B ldr r3, .L14+4 + 283 0018 1B68 ldr r3, [r3] + 284 001a 5B06 lsls r3, r3, #25 + 285 001c 0B43 orrs r3, r1 + 286 001e 1360 str r3, [r2] + 591:Generated_Source\PSoC4/CyLib.c **** } + 592:Generated_Source\PSoC4/CyLib.c **** else + 593:Generated_Source\PSoC4/CyLib.c **** { + 594:Generated_Source\PSoC4/CyLib.c **** CySysClkPumpConfig = (CY_SYS_CLK_IMO_CONFIG_REG >> CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT + 595:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK; + 596:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_CONFIG_REG &= ~(CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK << CY_SYS_CLK_IMO_CO + 597:Generated_Source\PSoC4/CyLib.c **** } + 598:Generated_Source\PSoC4/CyLib.c **** #else /* CY_IP_SRSSLT */ + 599:Generated_Source\PSoC4/CyLib.c **** if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + 600:Generated_Source\PSoC4/CyLib.c **** { + 601:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_REG |= (CySysClkPumpConfig << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT); + 602:Generated_Source\PSoC4/CyLib.c **** } + 603:Generated_Source\PSoC4/CyLib.c **** else + 604:Generated_Source\PSoC4/CyLib.c **** { + 605:Generated_Source\PSoC4/CyLib.c **** CySysClkPumpConfig = (CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & + 606:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_PUMP_SEL_MASK; + 607:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_REG &= ~(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SE + 608:Generated_Source\PSoC4/CyLib.c **** } + 609:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ + 610:Generated_Source\PSoC4/CyLib.c **** } + 287 .loc 1 610 0 + 288 0020 0CE0 b .L13 + 289 .L11: + 594:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK; + 290 .loc 1 594 0 + 291 0022 084B ldr r3, .L14 + 292 0024 1B68 ldr r3, [r3] + 293 0026 5B0E lsrs r3, r3, #25 + 294 0028 0722 movs r2, #7 + 295 002a 1A40 ands r2, r3 + 296 002c 064B ldr r3, .L14+4 + 297 002e 1A60 str r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 17 + + + 596:Generated_Source\PSoC4/CyLib.c **** } + 298 .loc 1 596 0 + 299 0030 044B ldr r3, .L14 + 300 0032 044A ldr r2, .L14 + 301 0034 1268 ldr r2, [r2] + 302 0036 0549 ldr r1, .L14+8 + 303 0038 0A40 ands r2, r1 + 304 003a 1A60 str r2, [r3] + 305 .L13: + 306 .loc 1 610 0 + 307 003c C046 nop + 308 003e BD46 mov sp, r7 + 309 0040 02B0 add sp, sp, #8 + 310 @ sp needed + 311 0042 80BD pop {r7, pc} + 312 .L15: + 313 .align 2 + 314 .L14: + 315 0044 08010B40 .word 1074462984 + 316 0048 00000000 .word CySysClkPumpConfig + 317 004c FFFFFFF1 .word -234881025 + 318 .cfi_endproc + 319 .LFE3: + 320 .size CySysEnablePumpClock, .-CySysEnablePumpClock + 321 .section .text.CySysClkGetSysclkSource,"ax",%progbits + 322 .align 2 + 323 .global CySysClkGetSysclkSource + 324 .code 16 + 325 .thumb_func + 326 .type CySysClkGetSysclkSource, %function + 327 CySysClkGetSysclkSource: + 328 .LFB4: + 611:Generated_Source\PSoC4/CyLib.c **** + 612:Generated_Source\PSoC4/CyLib.c **** + 613:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 614:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkGetSysclkSource + 615:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 616:Generated_Source\PSoC4/CyLib.c **** * + 617:Generated_Source\PSoC4/CyLib.c **** * Returns the source of the System clock. + 618:Generated_Source\PSoC4/CyLib.c **** * + 619:Generated_Source\PSoC4/CyLib.c **** * \return The same as \ref CySysClkWriteHfclkDirect() function parameters. + 620:Generated_Source\PSoC4/CyLib.c **** * + 621:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 622:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkGetSysclkSource(void) + 623:Generated_Source\PSoC4/CyLib.c **** { + 329 .loc 1 623 0 + 330 .cfi_startproc + 331 @ args = 0, pretend = 0, frame = 8 + 332 @ frame_needed = 1, uses_anonymous_args = 0 + 333 0000 90B5 push {r4, r7, lr} + 334 .cfi_def_cfa_offset 12 + 335 .cfi_offset 4, -12 + 336 .cfi_offset 7, -8 + 337 .cfi_offset 14, -4 + 338 0002 83B0 sub sp, sp, #12 + 339 .cfi_def_cfa_offset 24 + 340 0004 00AF add r7, sp, #0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 18 + + + 341 .cfi_def_cfa_register 7 + 624:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; + 625:Generated_Source\PSoC4/CyLib.c **** uint32 sysclkSource; + 626:Generated_Source\PSoC4/CyLib.c **** + 627:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); + 342 .loc 1 627 0 + 343 0006 FC1D adds r4, r7, #7 + 344 0008 FFF7FEFF bl CyEnterCriticalSection + 345 000c 0300 movs r3, r0 + 346 000e 2370 strb r3, [r4] + 628:Generated_Source\PSoC4/CyLib.c **** + 629:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_SRSSV2 && CY_IP_PLL) + 630:Generated_Source\PSoC4/CyLib.c **** if ((CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK) != 0u) + 631:Generated_Source\PSoC4/CyLib.c **** { + 632:Generated_Source\PSoC4/CyLib.c **** sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + 633:Generated_Source\PSoC4/CyLib.c **** } + 634:Generated_Source\PSoC4/CyLib.c **** else + 635:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + 636:Generated_Source\PSoC4/CyLib.c **** { + 637:Generated_Source\PSoC4/CyLib.c **** sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + 347 .loc 1 637 0 + 348 0010 074B ldr r3, .L18 + 349 0012 1B68 ldr r3, [r3] + 350 0014 0722 movs r2, #7 + 351 0016 1340 ands r3, r2 + 352 0018 3B60 str r3, [r7] + 638:Generated_Source\PSoC4/CyLib.c **** + 639:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_SRSSLT && CY_IP_PLL) + 640:Generated_Source\PSoC4/CyLib.c **** sysclkSource |= (((uint32)(CY_SYS_ECO_CLK_SELECT_REG & CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK)) + 641:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT); + 642:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + 643:Generated_Source\PSoC4/CyLib.c **** + 644:Generated_Source\PSoC4/CyLib.c **** } + 645:Generated_Source\PSoC4/CyLib.c **** + 646:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); + 353 .loc 1 646 0 + 354 001a FB1D adds r3, r7, #7 + 355 001c 1B78 ldrb r3, [r3] + 356 001e 1800 movs r0, r3 + 357 0020 FFF7FEFF bl CyExitCriticalSection + 647:Generated_Source\PSoC4/CyLib.c **** + 648:Generated_Source\PSoC4/CyLib.c **** return (sysclkSource); + 358 .loc 1 648 0 + 359 0024 3B68 ldr r3, [r7] + 649:Generated_Source\PSoC4/CyLib.c **** } + 360 .loc 1 649 0 + 361 0026 1800 movs r0, r3 + 362 0028 BD46 mov sp, r7 + 363 002a 03B0 add sp, sp, #12 + 364 @ sp needed + 365 002c 90BD pop {r4, r7, pc} + 366 .L19: + 367 002e C046 .align 2 + 368 .L18: + 369 0030 00010B40 .word 1074462976 + 370 .cfi_endproc + 371 .LFE4: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 19 + + + 372 .size CySysClkGetSysclkSource, .-CySysClkGetSysclkSource + 373 .section .text.CySysClkWriteSysclkDiv,"ax",%progbits + 374 .align 2 + 375 .global CySysClkWriteSysclkDiv + 376 .code 16 + 377 .thumb_func + 378 .type CySysClkWriteSysclkDiv, %function + 379 CySysClkWriteSysclkDiv: + 380 .LFB5: + 650:Generated_Source\PSoC4/CyLib.c **** + 651:Generated_Source\PSoC4/CyLib.c **** + 652:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 653:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkWriteSysclkDiv + 654:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 655:Generated_Source\PSoC4/CyLib.c **** * + 656:Generated_Source\PSoC4/CyLib.c **** * Selects the prescaler divide amount for SYSCLK from HFCLK. + 657:Generated_Source\PSoC4/CyLib.c **** * + 658:Generated_Source\PSoC4/CyLib.c **** * PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers + 659:Generated_Source\PSoC4/CyLib.c **** * should be selected in a way, not to exceed 16 MHz for SYSCLK. + 660:Generated_Source\PSoC4/CyLib.c **** * + 661:Generated_Source\PSoC4/CyLib.c **** * PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, + 662:Generated_Source\PSoC4/CyLib.c **** * so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz + 663:Generated_Source\PSoC4/CyLib.c **** * for SYSCLK. + 664:Generated_Source\PSoC4/CyLib.c **** * + 665:Generated_Source\PSoC4/CyLib.c **** * If the SYSCLK clock frequency increases during the device operation, call + 666:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the + 667:Generated_Source\PSoC4/CyLib.c **** * number of clock cycles the cache will wait before sampling data comes back + 668:Generated_Source\PSoC4/CyLib.c **** * from Flash. If the SYSCLK clock frequency decreases, you can call + 669:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() to improve the CPU performance. See + 670:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() description for more information. + 671:Generated_Source\PSoC4/CyLib.c **** * + 672:Generated_Source\PSoC4/CyLib.c **** * \param divider Power of 2 prescaler selection + 673:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV1 SYSCLK = HFCLK / 1 + 674:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV2 SYSCLK = HFCLK / 2 + 675:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV4 SYSCLK = HFCLK / 4 + 676:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV8 SYSCLK = HFCLK / 8 + 677:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV16 SYSCLK = HFCLK / 16 (N/A for 4000 Family) + 678:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV32 SYSCLK = HFCLK / 32 (N/A for 4000 Family) + 679:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV64 SYSCLK = HFCLK / 64 (N/A for 4000 Family) + 680:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_CLK_SYSCLK_DIV128 SYSCLK = HFCLK / 128 (N/A for 4000 Family) + 681:Generated_Source\PSoC4/CyLib.c **** * + 682:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 683:Generated_Source\PSoC4/CyLib.c **** void CySysClkWriteSysclkDiv(uint32 divider) + 684:Generated_Source\PSoC4/CyLib.c **** { + 381 .loc 1 684 0 + 382 .cfi_startproc + 383 @ args = 0, pretend = 0, frame = 16 + 384 @ frame_needed = 1, uses_anonymous_args = 0 + 385 0000 90B5 push {r4, r7, lr} + 386 .cfi_def_cfa_offset 12 + 387 .cfi_offset 4, -12 + 388 .cfi_offset 7, -8 + 389 .cfi_offset 14, -4 + 390 0002 85B0 sub sp, sp, #20 + 391 .cfi_def_cfa_offset 32 + 392 0004 00AF add r7, sp, #0 + 393 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 20 + + + 394 0006 7860 str r0, [r7, #4] + 685:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; + 686:Generated_Source\PSoC4/CyLib.c **** + 687:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); + 395 .loc 1 687 0 + 396 0008 0F23 movs r3, #15 + 397 000a FC18 adds r4, r7, r3 + 398 000c FFF7FEFF bl CyEnterCriticalSection + 399 0010 0300 movs r3, r0 + 400 0012 2370 strb r3, [r4] + 688:Generated_Source\PSoC4/CyLib.c **** + 689:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_REG = ((uint32)(((uint32)divider & CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK) << + 401 .loc 1 689 0 + 402 0014 0A4B ldr r3, .L21 + 403 0016 7A68 ldr r2, [r7, #4] + 404 0018 D104 lsls r1, r2, #19 + 405 001a E022 movs r2, #224 + 406 001c 9203 lsls r2, r2, #14 + 407 001e 1140 ands r1, r2 + 690:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)) | + 691:Generated_Source\PSoC4/CyLib.c **** (CY_SYS_CLK_SELECT_REG & ((uint32)(~(uint32)(CY_SYS_CLK_SELECT_SYSCLK_D + 408 .loc 1 691 0 + 409 0020 074A ldr r2, .L21 + 410 0022 1268 ldr r2, [r2] + 411 0024 0748 ldr r0, .L21+4 + 412 0026 0240 ands r2, r0 + 690:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)) | + 413 .loc 1 690 0 + 414 0028 0A43 orrs r2, r1 + 689:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)) | + 415 .loc 1 689 0 + 416 002a 1A60 str r2, [r3] + 692:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)))); + 693:Generated_Source\PSoC4/CyLib.c **** + 694:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); + 417 .loc 1 694 0 + 418 002c 0F23 movs r3, #15 + 419 002e FB18 adds r3, r7, r3 + 420 0030 1B78 ldrb r3, [r3] + 421 0032 1800 movs r0, r3 + 422 0034 FFF7FEFF bl CyExitCriticalSection + 695:Generated_Source\PSoC4/CyLib.c **** } + 423 .loc 1 695 0 + 424 0038 C046 nop + 425 003a BD46 mov sp, r7 + 426 003c 05B0 add sp, sp, #20 + 427 @ sp needed + 428 003e 90BD pop {r4, r7, pc} + 429 .L22: + 430 .align 2 + 431 .L21: + 432 0040 00010B40 .word 1074462976 + 433 0044 FFFFC7FF .word -3670017 + 434 .cfi_endproc + 435 .LFE5: + 436 .size CySysClkWriteSysclkDiv, .-CySysClkWriteSysclkDiv + 437 .section .text.CySysClkWriteImoFreq,"ax",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 21 + + + 438 .align 2 + 439 .global CySysClkWriteImoFreq + 440 .code 16 + 441 .thumb_func + 442 .type CySysClkWriteImoFreq, %function + 443 CySysClkWriteImoFreq: + 444 .LFB6: + 696:Generated_Source\PSoC4/CyLib.c **** + 697:Generated_Source\PSoC4/CyLib.c **** + 698:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* + 699:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkWriteImoFreq + 700:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** + 701:Generated_Source\PSoC4/CyLib.c **** * + 702:Generated_Source\PSoC4/CyLib.c **** * Sets the frequency of the IMO. + 703:Generated_Source\PSoC4/CyLib.c **** * + 704:Generated_Source\PSoC4/CyLib.c **** * PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers + 705:Generated_Source\PSoC4/CyLib.c **** * should be selected in a way, not to exceed 16 MHz for SYSCLK. + 706:Generated_Source\PSoC4/CyLib.c **** * + 707:Generated_Source\PSoC4/CyLib.c **** * PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, + 708:Generated_Source\PSoC4/CyLib.c **** * so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz + 709:Generated_Source\PSoC4/CyLib.c **** * for SYSCLK. + 710:Generated_Source\PSoC4/CyLib.c **** * + 711:Generated_Source\PSoC4/CyLib.c **** * For PSoC 4200M and PSoC 4200L device families, if WCO lock feature is enabled + 712:Generated_Source\PSoC4/CyLib.c **** * then this API will disable the lock, write the new IMO frequency and then + 713:Generated_Source\PSoC4/CyLib.c **** * re-enable the lock. + 714:Generated_Source\PSoC4/CyLib.c **** * + 715:Generated_Source\PSoC4/CyLib.c **** * For PSoC 4200L device families, this function enables the USB lock when 24 or + 716:Generated_Source\PSoC4/CyLib.c **** * 48 MHz passed as a parameter if the USB lock option is enabled in Design Wide + 717:Generated_Source\PSoC4/CyLib.c **** * Resources tab or CySysClkImoEnableUsbLock() was called before. Note the USB + 718:Generated_Source\PSoC4/CyLib.c **** * lock is disabled during IMO frequency change. + 719:Generated_Source\PSoC4/CyLib.c **** * + 720:Generated_Source\PSoC4/CyLib.c **** * The CPU is halted if new frequency is invalid and project is compiled + 721:Generated_Source\PSoC4/CyLib.c **** * in debug mode. + 722:Generated_Source\PSoC4/CyLib.c **** * + 723:Generated_Source\PSoC4/CyLib.c **** * If the SYSCLK clock frequency increases during the device operation, call + 724:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the + 725:Generated_Source\PSoC4/CyLib.c **** * number of clock cycles the cache will wait before sampling data comes back + 726:Generated_Source\PSoC4/CyLib.c **** * from Flash. If the SYSCLK clock frequency decreases, you can call + 727:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() to improve the CPU performance. See + 728:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() description for more information. + 729:Generated_Source\PSoC4/CyLib.c **** * + 730:Generated_Source\PSoC4/CyLib.c **** * PSoC 4000: The System Clock (SYSCLK) has maximum speed of 16 MHz, so HFCLK + 731:Generated_Source\PSoC4/CyLib.c **** * and SYSCLK dividers should be selected in a way, to not to exceed 16 MHz for + 732:Generated_Source\PSoC4/CyLib.c **** * the System clock. + 733:Generated_Source\PSoC4/CyLib.c **** * + 734:Generated_Source\PSoC4/CyLib.c **** * \param freq All PSoC 4 families excluding the following: Valid range [3-48] + 735:Generated_Source\PSoC4/CyLib.c **** * with step size equals 1. PSoC 4000: Valid values are 24, 32, and 48. + 736:Generated_Source\PSoC4/CyLib.c **** * PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor: Valid range [24-48] with + 737:Generated_Source\PSoC4/CyLib.c **** * step size equals 4. + 738:Generated_Source\PSoC4/CyLib.c **** * + 739:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ + 740:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) + 741:Generated_Source\PSoC4/CyLib.c **** void CySysClkWriteImoFreq(uint32 freq) + 742:Generated_Source\PSoC4/CyLib.c **** { + 445 .loc 1 742 0 + 446 .cfi_startproc + 447 @ args = 0, pretend = 0, frame = 16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 22 + + + 448 @ frame_needed = 1, uses_anonymous_args = 0 + 449 0000 90B5 push {r4, r7, lr} + 450 .cfi_def_cfa_offset 12 + 451 .cfi_offset 4, -12 + 452 .cfi_offset 7, -8 + 453 .cfi_offset 14, -4 + 454 0002 85B0 sub sp, sp, #20 + 455 .cfi_def_cfa_offset 32 + 456 0004 00AF add r7, sp, #0 + 457 .cfi_def_cfa_register 7 + 458 0006 7860 str r0, [r7, #4] + 743:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_FMLT) + 744:Generated_Source\PSoC4/CyLib.c **** volatile uint32 parameters[2u]; + 745:Generated_Source\PSoC4/CyLib.c **** volatile uint32 regValues[4u]; + 746:Generated_Source\PSoC4/CyLib.c **** #else + 747:Generated_Source\PSoC4/CyLib.c **** uint8 bgTrim4; + 748:Generated_Source\PSoC4/CyLib.c **** uint8 bgTrim5; + 749:Generated_Source\PSoC4/CyLib.c **** uint8 newImoTrim2Value; + 750:Generated_Source\PSoC4/CyLib.c **** uint8 currentImoTrim2Value; + 751:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_FM) */ + 752:Generated_Source\PSoC4/CyLib.c **** + 753:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + 754:Generated_Source\PSoC4/CyLib.c **** uint32 wcoLock = 0u; + 755:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + 756:Generated_Source\PSoC4/CyLib.c **** + 757:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) + 758:Generated_Source\PSoC4/CyLib.c **** uint32 usbLock = 0u; + 759:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + 760:Generated_Source\PSoC4/CyLib.c **** + 761:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; + 762:Generated_Source\PSoC4/CyLib.c **** + 763:Generated_Source\PSoC4/CyLib.c **** + 764:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); + 459 .loc 1 764 0 + 460 0008 0C23 movs r3, #12 + 461 000a FC18 adds r4, r7, r3 + 462 000c FFF7FEFF bl CyEnterCriticalSection + 463 0010 0300 movs r3, r0 + 464 0012 2370 strb r3, [r4] + 765:Generated_Source\PSoC4/CyLib.c **** + 766:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + 767:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkImoGetWcoLock()) + 768:Generated_Source\PSoC4/CyLib.c **** { + 769:Generated_Source\PSoC4/CyLib.c **** wcoLock = 1u; + 770:Generated_Source\PSoC4/CyLib.c **** CySysClkImoDisableWcoLock(); + 771:Generated_Source\PSoC4/CyLib.c **** } + 772:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + 773:Generated_Source\PSoC4/CyLib.c **** + 774:Generated_Source\PSoC4/CyLib.c **** + 775:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) + 776:Generated_Source\PSoC4/CyLib.c **** + 777:Generated_Source\PSoC4/CyLib.c **** #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + 778:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkImoGetUsbLock()) + 779:Generated_Source\PSoC4/CyLib.c **** { + 780:Generated_Source\PSoC4/CyLib.c **** #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + 781:Generated_Source\PSoC4/CyLib.c **** + 782:Generated_Source\PSoC4/CyLib.c **** if ((24u == freq) || (48u == freq)) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 23 + + + 783:Generated_Source\PSoC4/CyLib.c **** { + 784:Generated_Source\PSoC4/CyLib.c **** usbLock = 1u; + 785:Generated_Source\PSoC4/CyLib.c **** CySysClkImoDisableUsbLock(); + 786:Generated_Source\PSoC4/CyLib.c **** } + 787:Generated_Source\PSoC4/CyLib.c **** + 788:Generated_Source\PSoC4/CyLib.c **** #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + 789:Generated_Source\PSoC4/CyLib.c **** } + 790:Generated_Source\PSoC4/CyLib.c **** #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + 791:Generated_Source\PSoC4/CyLib.c **** + 792:Generated_Source\PSoC4/CyLib.c **** #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + 793:Generated_Source\PSoC4/CyLib.c **** + 794:Generated_Source\PSoC4/CyLib.c **** + 795:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_FMLT) + 796:Generated_Source\PSoC4/CyLib.c **** + 797:Generated_Source\PSoC4/CyLib.c **** /* FM-Lite Clock Restore */ + 798:Generated_Source\PSoC4/CyLib.c **** regValues[0u] = CY_SYS_CLK_IMO_CONFIG_REG; + 799:Generated_Source\PSoC4/CyLib.c **** regValues[1u] = CY_SYS_CLK_SELECT_REG; + 800:Generated_Source\PSoC4/CyLib.c **** regValues[2u] = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + 801:Generated_Source\PSoC4/CyLib.c **** regValues[3u] = CY_FLASH_CTL_REG; + 802:Generated_Source\PSoC4/CyLib.c **** + 803:Generated_Source\PSoC4/CyLib.c **** parameters[0u] = + 804:Generated_Source\PSoC4/CyLib.c **** (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY + 805:Generated_Source\PSoC4/CyLib.c **** CY_FLASH_KEY_ONE); + 806:Generated_Source\PSoC4/CyLib.c **** parameters[1u] = (uint32) ®Values[0u]; + 807:Generated_Source\PSoC4/CyLib.c **** + 808:Generated_Source\PSoC4/CyLib.c **** CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + 809:Generated_Source\PSoC4/CyLib.c **** CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + 810:Generated_Source\PSoC4/CyLib.c **** (void) CY_FLASH_CPUSS_SYSARG_REG; + 811:Generated_Source\PSoC4/CyLib.c **** + 812:Generated_Source\PSoC4/CyLib.c **** #else /* (CY_IP_FM) */ + 813:Generated_Source\PSoC4/CyLib.c **** + 814:Generated_Source\PSoC4/CyLib.c **** if ((freq >= CY_SYS_CLK_IMO_MIN_FREQ_MHZ) && (freq <= CY_SYS_CLK_IMO_MAX_FREQ_MHZ)) + 465 .loc 1 814 0 + 466 0014 7B68 ldr r3, [r7, #4] + 467 0016 022B cmp r3, #2 + 468 0018 00D8 bhi .LCB302 + 469 001a AFE0 b .L24 @long jump + 470 .LCB302: + 471 .loc 1 814 0 is_stmt 0 discriminator 1 + 472 001c 7B68 ldr r3, [r7, #4] + 473 001e 302B cmp r3, #48 + 474 0020 00D9 bls .LCB305 + 475 0022 ABE0 b .L24 @long jump + 476 .LCB305: + 815:Generated_Source\PSoC4/CyLib.c **** { + 816:Generated_Source\PSoC4/CyLib.c **** if(freq <= CY_SFLASH_IMO_MAXF0_REG) + 477 .loc 1 816 0 is_stmt 1 + 478 0024 5C4B ldr r3, .L35 + 479 0026 1B78 ldrb r3, [r3] + 480 0028 DBB2 uxtb r3, r3 + 481 002a 1A00 movs r2, r3 + 482 002c 7B68 ldr r3, [r7, #4] + 483 002e 9A42 cmp r2, r3 + 484 0030 0AD3 bcc .L25 + 817:Generated_Source\PSoC4/CyLib.c **** { + 818:Generated_Source\PSoC4/CyLib.c **** bgTrim4 = CY_SFLASH_IMO_ABS0_REG; + 485 .loc 1 818 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 24 + + + 486 0032 5A4A ldr r2, .L35+4 + 487 0034 0F23 movs r3, #15 + 488 0036 FB18 adds r3, r7, r3 + 489 0038 1278 ldrb r2, [r2] + 490 003a 1A70 strb r2, [r3] + 819:Generated_Source\PSoC4/CyLib.c **** bgTrim5 = CY_SFLASH_IMO_TMPCO0_REG; + 491 .loc 1 819 0 + 492 003c 584A ldr r2, .L35+8 + 493 003e 0E23 movs r3, #14 + 494 0040 FB18 adds r3, r7, r3 + 495 0042 1278 ldrb r2, [r2] + 496 0044 1A70 strb r2, [r3] + 497 0046 3FE0 b .L26 + 498 .L25: + 820:Generated_Source\PSoC4/CyLib.c **** } + 821:Generated_Source\PSoC4/CyLib.c **** else if(freq <= CY_SFLASH_IMO_MAXF1_REG) + 499 .loc 1 821 0 + 500 0048 564B ldr r3, .L35+12 + 501 004a 1B78 ldrb r3, [r3] + 502 004c DBB2 uxtb r3, r3 + 503 004e 1A00 movs r2, r3 + 504 0050 7B68 ldr r3, [r7, #4] + 505 0052 9A42 cmp r2, r3 + 506 0054 0AD3 bcc .L27 + 822:Generated_Source\PSoC4/CyLib.c **** { + 823:Generated_Source\PSoC4/CyLib.c **** bgTrim4 = CY_SFLASH_IMO_ABS1_REG; + 507 .loc 1 823 0 + 508 0056 544A ldr r2, .L35+16 + 509 0058 0F23 movs r3, #15 + 510 005a FB18 adds r3, r7, r3 + 511 005c 1278 ldrb r2, [r2] + 512 005e 1A70 strb r2, [r3] + 824:Generated_Source\PSoC4/CyLib.c **** bgTrim5 = CY_SFLASH_IMO_TMPCO1_REG; + 513 .loc 1 824 0 + 514 0060 524A ldr r2, .L35+20 + 515 0062 0E23 movs r3, #14 + 516 0064 FB18 adds r3, r7, r3 + 517 0066 1278 ldrb r2, [r2] + 518 0068 1A70 strb r2, [r3] + 519 006a 2DE0 b .L26 + 520 .L27: + 825:Generated_Source\PSoC4/CyLib.c **** } + 826:Generated_Source\PSoC4/CyLib.c **** else if(freq <= CY_SFLASH_IMO_MAXF2_REG) + 521 .loc 1 826 0 + 522 006c 504B ldr r3, .L35+24 + 523 006e 1B78 ldrb r3, [r3] + 524 0070 DBB2 uxtb r3, r3 + 525 0072 1A00 movs r2, r3 + 526 0074 7B68 ldr r3, [r7, #4] + 527 0076 9A42 cmp r2, r3 + 528 0078 0AD3 bcc .L28 + 827:Generated_Source\PSoC4/CyLib.c **** { + 828:Generated_Source\PSoC4/CyLib.c **** bgTrim4 = CY_SFLASH_IMO_ABS2_REG; + 529 .loc 1 828 0 + 530 007a 4E4A ldr r2, .L35+28 + 531 007c 0F23 movs r3, #15 + 532 007e FB18 adds r3, r7, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 25 + + + 533 0080 1278 ldrb r2, [r2] + 534 0082 1A70 strb r2, [r3] + 829:Generated_Source\PSoC4/CyLib.c **** bgTrim5 = CY_SFLASH_IMO_TMPCO2_REG; + 535 .loc 1 829 0 + 536 0084 4C4A ldr r2, .L35+32 + 537 0086 0E23 movs r3, #14 + 538 0088 FB18 adds r3, r7, r3 + 539 008a 1278 ldrb r2, [r2] + 540 008c 1A70 strb r2, [r3] + 541 008e 1BE0 b .L26 + 542 .L28: + 830:Generated_Source\PSoC4/CyLib.c **** } + 831:Generated_Source\PSoC4/CyLib.c **** else if(freq <= CY_SFLASH_IMO_MAXF3_REG) + 543 .loc 1 831 0 + 544 0090 4A4B ldr r3, .L35+36 + 545 0092 1B78 ldrb r3, [r3] + 546 0094 DBB2 uxtb r3, r3 + 547 0096 1A00 movs r2, r3 + 548 0098 7B68 ldr r3, [r7, #4] + 549 009a 9A42 cmp r2, r3 + 550 009c 0AD3 bcc .L29 + 832:Generated_Source\PSoC4/CyLib.c **** { + 833:Generated_Source\PSoC4/CyLib.c **** bgTrim4 = CY_SFLASH_IMO_ABS3_REG; + 551 .loc 1 833 0 + 552 009e 484A ldr r2, .L35+40 + 553 00a0 0F23 movs r3, #15 + 554 00a2 FB18 adds r3, r7, r3 + 555 00a4 1278 ldrb r2, [r2] + 556 00a6 1A70 strb r2, [r3] + 834:Generated_Source\PSoC4/CyLib.c **** bgTrim5 = CY_SFLASH_IMO_TMPCO3_REG; + 557 .loc 1 834 0 + 558 00a8 464A ldr r2, .L35+44 + 559 00aa 0E23 movs r3, #14 + 560 00ac FB18 adds r3, r7, r3 + 561 00ae 1278 ldrb r2, [r2] + 562 00b0 1A70 strb r2, [r3] + 563 00b2 09E0 b .L26 + 564 .L29: + 835:Generated_Source\PSoC4/CyLib.c **** } + 836:Generated_Source\PSoC4/CyLib.c **** else + 837:Generated_Source\PSoC4/CyLib.c **** { + 838:Generated_Source\PSoC4/CyLib.c **** bgTrim4 = CY_SFLASH_IMO_ABS4_REG; + 565 .loc 1 838 0 + 566 00b4 444A ldr r2, .L35+48 + 567 00b6 0F23 movs r3, #15 + 568 00b8 FB18 adds r3, r7, r3 + 569 00ba 1278 ldrb r2, [r2] + 570 00bc 1A70 strb r2, [r3] + 839:Generated_Source\PSoC4/CyLib.c **** bgTrim5 = CY_SFLASH_IMO_TMPCO4_REG; + 571 .loc 1 839 0 + 572 00be 434A ldr r2, .L35+52 + 573 00c0 0E23 movs r3, #14 + 574 00c2 FB18 adds r3, r7, r3 + 575 00c4 1278 ldrb r2, [r2] + 576 00c6 1A70 strb r2, [r3] + 577 .L26: + 840:Generated_Source\PSoC4/CyLib.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 26 + + + 841:Generated_Source\PSoC4/CyLib.c **** + 842:Generated_Source\PSoC4/CyLib.c **** /* Get IMO_TRIM2 value for the new frequency */ + 843:Generated_Source\PSoC4/CyLib.c **** newImoTrim2Value = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + 578 .loc 1 843 0 + 579 00c8 7B68 ldr r3, [r7, #4] + 580 00ca DA1E subs r2, r3, #3 + 581 00cc 0B23 movs r3, #11 + 582 00ce FB18 adds r3, r7, r3 + 583 00d0 3F49 ldr r1, .L35+56 + 584 00d2 8A5C ldrb r2, [r1, r2] + 585 00d4 1A70 strb r2, [r3] + 844:Generated_Source\PSoC4/CyLib.c **** + 845:Generated_Source\PSoC4/CyLib.c **** + 846:Generated_Source\PSoC4/CyLib.c **** /**************************************************************************** + 847:Generated_Source\PSoC4/CyLib.c **** * The IMO can have a different trim per frequency. To avoid possible corner + 848:Generated_Source\PSoC4/CyLib.c **** * cases where a trim change can exceed the maximum frequency, the trim must + 849:Generated_Source\PSoC4/CyLib.c **** * be applied at a frequency that is low enough. + 850:Generated_Source\PSoC4/CyLib.c **** * + 851:Generated_Source\PSoC4/CyLib.c **** * Comparing IMO_TRIM2 values for the current and new frequencies, since + 852:Generated_Source\PSoC4/CyLib.c **** * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + 853:Generated_Source\PSoC4/CyLib.c **** * function and is time-invariant. + 854:Generated_Source\PSoC4/CyLib.c **** ***************************************************************************/ + 855:Generated_Source\PSoC4/CyLib.c **** if ((newImoTrim2Value >= CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2) && (freq >= CY_SYS_CLK_IMO + 586 .loc 1 855 0 + 587 00d6 0B23 movs r3, #11 + 588 00d8 FB18 adds r3, r7, r3 + 589 00da 1B78 ldrb r3, [r3] + 590 00dc 2F2B cmp r3, #47 + 591 00de 0DD9 bls .L30 + 592 .loc 1 855 0 is_stmt 0 discriminator 1 + 593 00e0 7B68 ldr r3, [r7, #4] + 594 00e2 2A2B cmp r3, #42 + 595 00e4 0AD9 bls .L30 + 856:Generated_Source\PSoC4/CyLib.c **** { + 857:Generated_Source\PSoC4/CyLib.c **** /* Set boundary IMO frequency: safe for IMO above 48 MHZ trimming */ + 858:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM2_REG = (uint32) cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_TEMP_FREQ_MHZ - + 596 .loc 1 858 0 is_stmt 1 + 597 00e6 3B4B ldr r3, .L35+60 + 598 00e8 1922 movs r2, #25 + 599 00ea 1A60 str r2, [r3] + 859:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_FREQ_TABLE_OFFS + 860:Generated_Source\PSoC4/CyLib.c **** + 861:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + 600 .loc 1 861 0 + 601 00ec 0520 movs r0, #5 + 602 00ee FFF7FEFF bl CyDelayCycles + 862:Generated_Source\PSoC4/CyLib.c **** + 863:Generated_Source\PSoC4/CyLib.c **** currentImoTrim2Value = CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2; + 603 .loc 1 863 0 + 604 00f2 0D23 movs r3, #13 + 605 00f4 FB18 adds r3, r7, r3 + 606 00f6 1922 movs r2, #25 + 607 00f8 1A70 strb r2, [r3] + 608 00fa 07E0 b .L31 + 609 .L30: + 864:Generated_Source\PSoC4/CyLib.c **** } + 865:Generated_Source\PSoC4/CyLib.c **** else + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 27 + + + 866:Generated_Source\PSoC4/CyLib.c **** { + 867:Generated_Source\PSoC4/CyLib.c **** currentImoTrim2Value = (uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS + 610 .loc 1 867 0 + 611 00fc 354B ldr r3, .L35+60 + 612 00fe 1B68 ldr r3, [r3] + 613 0100 DAB2 uxtb r2, r3 + 614 0102 0D23 movs r3, #13 + 615 0104 FB18 adds r3, r7, r3 + 616 0106 3F21 movs r1, #63 + 617 0108 0A40 ands r2, r1 + 618 010a 1A70 strb r2, [r3] + 619 .L31: + 868:Generated_Source\PSoC4/CyLib.c **** } + 869:Generated_Source\PSoC4/CyLib.c **** + 870:Generated_Source\PSoC4/CyLib.c **** + 871:Generated_Source\PSoC4/CyLib.c **** /*************************************************************************** + 872:Generated_Source\PSoC4/CyLib.c **** * A trim change needs to be allowed to settle (within 5us) before the Freq + 873:Generated_Source\PSoC4/CyLib.c **** * can be changed to a new frequency. + 874:Generated_Source\PSoC4/CyLib.c **** * + 875:Generated_Source\PSoC4/CyLib.c **** * Comparing IMO_TRIM2 values for the current and new frequencies, since + 876:Generated_Source\PSoC4/CyLib.c **** * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + 877:Generated_Source\PSoC4/CyLib.c **** * function and is time-invariant. + 878:Generated_Source\PSoC4/CyLib.c **** ***************************************************************************/ + 879:Generated_Source\PSoC4/CyLib.c **** if (newImoTrim2Value < currentImoTrim2Value) + 620 .loc 1 879 0 + 621 010c 0B23 movs r3, #11 + 622 010e FA18 adds r2, r7, r3 + 623 0110 0D23 movs r3, #13 + 624 0112 FB18 adds r3, r7, r3 + 625 0114 1278 ldrb r2, [r2] + 626 0116 1B78 ldrb r3, [r3] + 627 0118 9A42 cmp r2, r3 + 628 011a 08D2 bcs .L32 + 880:Generated_Source\PSoC4/CyLib.c **** { + 881:Generated_Source\PSoC4/CyLib.c **** /* Set new IMO frequency */ + 882:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET + 629 .loc 1 882 0 + 630 011c 2D4B ldr r3, .L35+60 + 631 011e 7A68 ldr r2, [r7, #4] + 632 0120 033A subs r2, r2, #3 + 633 0122 2B49 ldr r1, .L35+56 + 634 0124 8A5C ldrb r2, [r1, r2] + 635 0126 1A60 str r2, [r3] + 883:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + 636 .loc 1 883 0 + 637 0128 0520 movs r0, #5 + 638 012a FFF7FEFF bl CyDelayCycles + 639 .L32: + 884:Generated_Source\PSoC4/CyLib.c **** } + 885:Generated_Source\PSoC4/CyLib.c **** + 886:Generated_Source\PSoC4/CyLib.c **** /* Set trims for the new IMO frequency */ + 887:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM1_REG = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_T + 640 .loc 1 887 0 + 641 012e 2A4B ldr r3, .L35+64 + 642 0130 7A68 ldr r2, [r7, #4] + 643 0132 2649 ldr r1, .L35+52 + 644 0134 8C46 mov ip, r1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 28 + + + 645 0136 6244 add r2, r2, ip + 646 0138 1278 ldrb r2, [r2] + 647 013a D2B2 uxtb r2, r2 + 648 013c 1A60 str r2, [r3] + 888:Generated_Source\PSoC4/CyLib.c **** CY_PWR_BG_TRIM4_REG = bgTrim4; + 649 .loc 1 888 0 + 650 013e 274B ldr r3, .L35+68 + 651 0140 0F22 movs r2, #15 + 652 0142 BA18 adds r2, r7, r2 + 653 0144 1278 ldrb r2, [r2] + 654 0146 1A60 str r2, [r3] + 889:Generated_Source\PSoC4/CyLib.c **** CY_PWR_BG_TRIM5_REG = bgTrim5; + 655 .loc 1 889 0 + 656 0148 254B ldr r3, .L35+72 + 657 014a 0E22 movs r2, #14 + 658 014c BA18 adds r2, r7, r2 + 659 014e 1278 ldrb r2, [r2] + 660 0150 1A60 str r2, [r3] + 890:Generated_Source\PSoC4/CyLib.c **** CyDelayUs(CY_SYS_CLK_IMO_TRIM_TIMEOUT_US); + 661 .loc 1 890 0 + 662 0152 0520 movs r0, #5 + 663 0154 FFF7FEFF bl CyDelayUs + 891:Generated_Source\PSoC4/CyLib.c **** + 892:Generated_Source\PSoC4/CyLib.c **** if (newImoTrim2Value > currentImoTrim2Value) + 664 .loc 1 892 0 + 665 0158 0B23 movs r3, #11 + 666 015a FA18 adds r2, r7, r3 + 667 015c 0D23 movs r3, #13 + 668 015e FB18 adds r3, r7, r3 + 669 0160 1278 ldrb r2, [r2] + 670 0162 1B78 ldrb r3, [r3] + 671 0164 9A42 cmp r2, r3 + 672 0166 0CD9 bls .L34 + 893:Generated_Source\PSoC4/CyLib.c **** { + 894:Generated_Source\PSoC4/CyLib.c **** /* Set new IMO frequency */ + 895:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET + 673 .loc 1 895 0 + 674 0168 1A4B ldr r3, .L35+60 + 675 016a 7A68 ldr r2, [r7, #4] + 676 016c 033A subs r2, r2, #3 + 677 016e 1849 ldr r1, .L35+56 + 678 0170 8A5C ldrb r2, [r1, r2] + 679 0172 1A60 str r2, [r3] + 896:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + 680 .loc 1 896 0 + 681 0174 0520 movs r0, #5 + 682 0176 FFF7FEFF bl CyDelayCycles + 892:Generated_Source\PSoC4/CyLib.c **** { + 683 .loc 1 892 0 + 684 017a 02E0 b .L34 + 685 .L24: + 897:Generated_Source\PSoC4/CyLib.c **** } + 898:Generated_Source\PSoC4/CyLib.c **** } + 899:Generated_Source\PSoC4/CyLib.c **** else + 900:Generated_Source\PSoC4/CyLib.c **** { + 901:Generated_Source\PSoC4/CyLib.c **** /* Halt CPU in debug mode if new frequency is invalid */ + 902:Generated_Source\PSoC4/CyLib.c **** CYASSERT(0u != 0u); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 29 + + + 686 .loc 1 902 0 discriminator 1 + 687 017c 0020 movs r0, #0 + 688 017e FFF7FEFF bl CyHalt + 689 .L34: + 903:Generated_Source\PSoC4/CyLib.c **** } + 904:Generated_Source\PSoC4/CyLib.c **** + 905:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_FMLT) */ + 906:Generated_Source\PSoC4/CyLib.c **** + 907:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + 908:Generated_Source\PSoC4/CyLib.c **** if (1u == wcoLock) + 909:Generated_Source\PSoC4/CyLib.c **** { + 910:Generated_Source\PSoC4/CyLib.c **** CySysClkImoEnableWcoLock(); + 911:Generated_Source\PSoC4/CyLib.c **** } + 912:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + 913:Generated_Source\PSoC4/CyLib.c **** + 914:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) + 915:Generated_Source\PSoC4/CyLib.c **** if (1u == usbLock) + 916:Generated_Source\PSoC4/CyLib.c **** { + 917:Generated_Source\PSoC4/CyLib.c **** CySysClkImoEnableUsbLock(); + 918:Generated_Source\PSoC4/CyLib.c **** } + 919:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + 920:Generated_Source\PSoC4/CyLib.c **** + 921:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); + 690 .loc 1 921 0 + 691 0182 0C23 movs r3, #12 + 692 0184 FB18 adds r3, r7, r3 + 693 0186 1B78 ldrb r3, [r3] + 694 0188 1800 movs r0, r3 + 695 018a FFF7FEFF bl CyExitCriticalSection + 922:Generated_Source\PSoC4/CyLib.c **** } + 696 .loc 1 922 0 + 697 018e C046 nop + 698 0190 BD46 mov sp, r7 + 699 0192 05B0 add sp, sp, #20 + 700 @ sp needed + 701 0194 90BD pop {r4, r7, pc} + 702 .L36: + 703 0196 C046 .align 2 + 704 .L35: + 705 0198 C0F1FF0F .word 268431808 + 706 019c C1F1FF0F .word 268431809 + 707 01a0 C2F1FF0F .word 268431810 + 708 01a4 C3F1FF0F .word 268431811 + 709 01a8 C4F1FF0F .word 268431812 + 710 01ac C5F1FF0F .word 268431813 + 711 01b0 C6F1FF0F .word 268431814 + 712 01b4 C7F1FF0F .word 268431815 + 713 01b8 C8F1FF0F .word 268431816 + 714 01bc C9F1FF0F .word 268431817 + 715 01c0 CAF1FF0F .word 268431818 + 716 01c4 CBF1FF0F .word 268431819 + 717 01c8 CCF1FF0F .word 268431820 + 718 01cc CDF1FF0F .word 268431821 + 719 01d0 00000000 .word cyImoFreqMhz2Reg + 720 01d4 2CFF0B40 .word 1074528044 + 721 01d8 28FF0B40 .word 1074528040 + 722 01dc 1CFF0B40 .word 1074528028 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 30 + + + 723 01e0 20FF0B40 .word 1074528032 + 724 .cfi_endproc + 725 .LFE6: + 726 .size CySysClkWriteImoFreq, .-CySysClkWriteImoFreq + 727 .section .text.CySysLvdEnable,"ax",%progbits + 728 .align 2 + 729 .global CySysLvdEnable + 730 .code 16 + 731 .thumb_func + 732 .type CySysLvdEnable, %function + 733 CySysLvdEnable: + 734 .LFB7: + 923:Generated_Source\PSoC4/CyLib.c **** + 924:Generated_Source\PSoC4/CyLib.c **** #else + 925:Generated_Source\PSoC4/CyLib.c **** + 926:Generated_Source\PSoC4/CyLib.c **** void CySysClkWriteImoFreq(uint32 freq) + 927:Generated_Source\PSoC4/CyLib.c **** { + 928:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; + 929:Generated_Source\PSoC4/CyLib.c **** uint8 imoTrim1Value; + 930:Generated_Source\PSoC4/CyLib.c **** + 931:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + 932:Generated_Source\PSoC4/CyLib.c **** uint32 wcoLock = 0u; + 933:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + 934:Generated_Source\PSoC4/CyLib.c **** + 935:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) + 936:Generated_Source\PSoC4/CyLib.c **** uint32 usbLock = 0u; + 937:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + 938:Generated_Source\PSoC4/CyLib.c **** + 939:Generated_Source\PSoC4/CyLib.c **** #if (CY_PSOC4_4000) + 940:Generated_Source\PSoC4/CyLib.c **** if ((freq == 24u) || (freq == 32u) || (freq == 48u)) + 941:Generated_Source\PSoC4/CyLib.c **** #elif (CY_CCG3) + 942:Generated_Source\PSoC4/CyLib.c **** if ((freq == 24u) || (freq == 36u) || (freq == 48u)) + 943:Generated_Source\PSoC4/CyLib.c **** #else + 944:Generated_Source\PSoC4/CyLib.c **** if ((freq == 24u) || (freq == 28u) || (freq == 32u) || + 945:Generated_Source\PSoC4/CyLib.c **** (freq == 36u) || (freq == 40u) || (freq == 44u) || + 946:Generated_Source\PSoC4/CyLib.c **** (freq == 48u)) + 947:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_PSOC4_4000) */ + 948:Generated_Source\PSoC4/CyLib.c **** { + 949:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); + 950:Generated_Source\PSoC4/CyLib.c **** + 951:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + 952:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkImoGetWcoLock()) + 953:Generated_Source\PSoC4/CyLib.c **** { + 954:Generated_Source\PSoC4/CyLib.c **** wcoLock = 1u; + 955:Generated_Source\PSoC4/CyLib.c **** CySysClkImoDisableWcoLock(); + 956:Generated_Source\PSoC4/CyLib.c **** } + 957:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + 958:Generated_Source\PSoC4/CyLib.c **** + 959:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) + 960:Generated_Source\PSoC4/CyLib.c **** + 961:Generated_Source\PSoC4/CyLib.c **** #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + 962:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkImoGetUsbLock()) + 963:Generated_Source\PSoC4/CyLib.c **** { + 964:Generated_Source\PSoC4/CyLib.c **** #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + 965:Generated_Source\PSoC4/CyLib.c **** + 966:Generated_Source\PSoC4/CyLib.c **** if (48u == freq) + 967:Generated_Source\PSoC4/CyLib.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 31 + + + 968:Generated_Source\PSoC4/CyLib.c **** usbLock = 1u; + 969:Generated_Source\PSoC4/CyLib.c **** CySysClkImoDisableUsbLock(); + 970:Generated_Source\PSoC4/CyLib.c **** } + 971:Generated_Source\PSoC4/CyLib.c **** + 972:Generated_Source\PSoC4/CyLib.c **** #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + 973:Generated_Source\PSoC4/CyLib.c **** } + 974:Generated_Source\PSoC4/CyLib.c **** #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + 975:Generated_Source\PSoC4/CyLib.c **** + 976:Generated_Source\PSoC4/CyLib.c **** #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + 977:Generated_Source\PSoC4/CyLib.c **** + 978:Generated_Source\PSoC4/CyLib.c **** + 979:Generated_Source\PSoC4/CyLib.c **** /* Set IMO to 24 MHz - CLK_IMO_SELECT.FREQ = 0 */ + 980:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_SELECT_REG &= ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + 981:Generated_Source\PSoC4/CyLib.c **** + 982:Generated_Source\PSoC4/CyLib.c **** + 983:Generated_Source\PSoC4/CyLib.c **** /* Apply coarse trim */ + 984:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) + 985:Generated_Source\PSoC4/CyLib.c **** if ((1u == usbLock) && (48u == freq)) + 986:Generated_Source\PSoC4/CyLib.c **** { + 987:Generated_Source\PSoC4/CyLib.c **** imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + 988:Generated_Source\PSoC4/CyLib.c **** } + 989:Generated_Source\PSoC4/CyLib.c **** else if ((1u == usbLock) && (24u == freq)) + 990:Generated_Source\PSoC4/CyLib.c **** { + 991:Generated_Source\PSoC4/CyLib.c **** imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + 992:Generated_Source\PSoC4/CyLib.c **** } + 993:Generated_Source\PSoC4/CyLib.c **** else + 994:Generated_Source\PSoC4/CyLib.c **** { + 995:Generated_Source\PSoC4/CyLib.c **** imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_M + 996:Generated_Source\PSoC4/CyLib.c **** } + 997:Generated_Source\PSoC4/CyLib.c **** #else + 998:Generated_Source\PSoC4/CyLib.c **** imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + 999:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ +1000:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM1_REG = (uint32) imoTrim1Value; +1001:Generated_Source\PSoC4/CyLib.c **** +1002:Generated_Source\PSoC4/CyLib.c **** /* Zero out fine trim */ +1003:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM2_REG = CY_SYS_CLK_IMO_TRIM2_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM2_F +1004:Generated_Source\PSoC4/CyLib.c **** +1005:Generated_Source\PSoC4/CyLib.c **** /* Apply TC trim */ +1006:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_TRIM3_REG = (CY_SYS_CLK_IMO_TRIM3_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM3_ +1007:Generated_Source\PSoC4/CyLib.c **** (CY_SFLASH_IMO_TCTRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) & CY_SYS_CLK_IMO_TRIM +1008:Generated_Source\PSoC4/CyLib.c **** +1009:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); +1010:Generated_Source\PSoC4/CyLib.c **** +1011:Generated_Source\PSoC4/CyLib.c **** if (freq > CY_SYS_CLK_IMO_MIN_FREQ_MHZ) +1012:Generated_Source\PSoC4/CyLib.c **** { +1013:Generated_Source\PSoC4/CyLib.c **** /* Select nearby intermediate frequency */ +1014:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_ +1015:Generated_Source\PSoC4/CyLib.c **** (((freq - 4u - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ +1016:Generated_Source\PSoC4/CyLib.c **** +1017:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); +1018:Generated_Source\PSoC4/CyLib.c **** +1019:Generated_Source\PSoC4/CyLib.c **** /* Make small step to final frequency */ +1020:Generated_Source\PSoC4/CyLib.c **** /* Select nearby intermediate frequency */ +1021:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_ +1022:Generated_Source\PSoC4/CyLib.c **** (((freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ_MASK +1023:Generated_Source\PSoC4/CyLib.c **** } +1024:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 32 + + +1025:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_WCO) +1026:Generated_Source\PSoC4/CyLib.c **** if (1u == wcoLock) +1027:Generated_Source\PSoC4/CyLib.c **** { +1028:Generated_Source\PSoC4/CyLib.c **** CySysClkImoEnableWcoLock(); +1029:Generated_Source\PSoC4/CyLib.c **** } +1030:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ +1031:Generated_Source\PSoC4/CyLib.c **** +1032:Generated_Source\PSoC4/CyLib.c **** +1033:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_IMO_TRIMMABLE_BY_USB) +1034:Generated_Source\PSoC4/CyLib.c **** if (1u == usbLock) +1035:Generated_Source\PSoC4/CyLib.c **** { +1036:Generated_Source\PSoC4/CyLib.c **** CySysClkImoEnableUsbLock(); +1037:Generated_Source\PSoC4/CyLib.c **** } +1038:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ +1039:Generated_Source\PSoC4/CyLib.c **** +1040:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1041:Generated_Source\PSoC4/CyLib.c **** } +1042:Generated_Source\PSoC4/CyLib.c **** else +1043:Generated_Source\PSoC4/CyLib.c **** { +1044:Generated_Source\PSoC4/CyLib.c **** /* Halt CPU in debug mode if new frequency is invalid */ +1045:Generated_Source\PSoC4/CyLib.c **** CYASSERT(0u != 0u); +1046:Generated_Source\PSoC4/CyLib.c **** } +1047:Generated_Source\PSoC4/CyLib.c **** } +1048:Generated_Source\PSoC4/CyLib.c **** +1049:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ +1050:Generated_Source\PSoC4/CyLib.c **** +1051:Generated_Source\PSoC4/CyLib.c **** +1052:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSLT) +1053:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1054:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkWriteHfclkDiv +1055:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1056:Generated_Source\PSoC4/CyLib.c **** * +1057:Generated_Source\PSoC4/CyLib.c **** * Selects the pre-scaler divider value for HFCLK from IMO. +1058:Generated_Source\PSoC4/CyLib.c **** * +1059:Generated_Source\PSoC4/CyLib.c **** * The HFCLK predivider allows the device to divide the HFCLK selection mux +1060:Generated_Source\PSoC4/CyLib.c **** * input before use as HFCLK. The predivider is capable of dividing the HFCLK by +1061:Generated_Source\PSoC4/CyLib.c **** * powers of 2 between 1 and 8. +1062:Generated_Source\PSoC4/CyLib.c **** * +1063:Generated_Source\PSoC4/CyLib.c **** * PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers +1064:Generated_Source\PSoC4/CyLib.c **** * should be selected in a way, not to exceed 16 MHz for SYSCLK. +1065:Generated_Source\PSoC4/CyLib.c **** * +1066:Generated_Source\PSoC4/CyLib.c **** * If the SYSCLK clock frequency increases during the device operation, call +1067:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the +1068:Generated_Source\PSoC4/CyLib.c **** * number of clock cycles the cache will wait before sampling data comes back +1069:Generated_Source\PSoC4/CyLib.c **** * from Flash. If the SYSCLK clock frequency decreases, you can call +1070:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() to improve the CPU performance. See +1071:Generated_Source\PSoC4/CyLib.c **** * \ref CySysFlashSetWaitCycles() description for more information. +1072:Generated_Source\PSoC4/CyLib.c **** * +1073:Generated_Source\PSoC4/CyLib.c **** * \param \ref CY_SYS_CLK_HFCLK_DIV_NODIV Transparent mode (w/o dividing) +1074:Generated_Source\PSoC4/CyLib.c **** * \param \ref CY_SYS_CLK_HFCLK_DIV_2 Divide selected clock source by 2 +1075:Generated_Source\PSoC4/CyLib.c **** * \param \ref CY_SYS_CLK_HFCLK_DIV_4 Divide selected clock source by 4 +1076:Generated_Source\PSoC4/CyLib.c **** * \param \ref CY_SYS_CLK_HFCLK_DIV_8 Divide selected clock source by 8 +1077:Generated_Source\PSoC4/CyLib.c **** * +1078:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1079:Generated_Source\PSoC4/CyLib.c **** void CySysClkWriteHfclkDiv(uint32 divider) +1080:Generated_Source\PSoC4/CyLib.c **** { +1081:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 33 + + +1082:Generated_Source\PSoC4/CyLib.c **** +1083:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1084:Generated_Source\PSoC4/CyLib.c **** +1085:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & ((uint32) (~(CY_SYS_CLK_SELECT_HFCLK_DIV_ +1086:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT)))) | +1087:Generated_Source\PSoC4/CyLib.c **** ((uint32)((divider & CY_SYS_CLK_SELECT_HFCLK_DIV_MASK) << CY_SYS_CLK_SELECT_HFC +1088:Generated_Source\PSoC4/CyLib.c **** +1089:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1090:Generated_Source\PSoC4/CyLib.c **** } +1091:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSLT) */ +1092:Generated_Source\PSoC4/CyLib.c **** +1093:Generated_Source\PSoC4/CyLib.c **** +1094:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_ECO) +1095:Generated_Source\PSoC4/CyLib.c **** +1096:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1097:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkEcoStart +1098:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1099:Generated_Source\PSoC4/CyLib.c **** * +1100:Generated_Source\PSoC4/CyLib.c **** * Starts the External Crystal Oscillator (ECO). Refer to the device datasheet +1101:Generated_Source\PSoC4/CyLib.c **** * for the ECO startup time. +1102:Generated_Source\PSoC4/CyLib.c **** * +1103:Generated_Source\PSoC4/CyLib.c **** * The timeout interval is measured based on the system frequency defined by +1104:Generated_Source\PSoC4/CyLib.c **** * PSoC Creator at build time. If System clock frequency is changed in +1105:Generated_Source\PSoC4/CyLib.c **** * runtime, the \ref CyDelayFreq() with the appropriate parameter should be +1106:Generated_Source\PSoC4/CyLib.c **** * called. +1107:Generated_Source\PSoC4/CyLib.c **** * +1108:Generated_Source\PSoC4/CyLib.c **** * PSoC 4100 BLE / PSoC 4200 BLE: The WCO must be enabled prior to enabling ECO. +1109:Generated_Source\PSoC4/CyLib.c **** * +1110:Generated_Source\PSoC4/CyLib.c **** * \param timeoutUs Timeout in microseconds. +1111:Generated_Source\PSoC4/CyLib.c **** * +1112:Generated_Source\PSoC4/CyLib.c **** * If zero is specified, the function does not wait for timeout and returns +1113:Generated_Source\PSoC4/CyLib.c **** * CYRET_SUCCESS. If non-zero is specified, the function waits for the timeout. +1114:Generated_Source\PSoC4/CyLib.c **** * +1115:Generated_Source\PSoC4/CyLib.c **** * \return \ref CYRET_SUCCESS Completed successfully. The ECO is oscillating and +1116:Generated_Source\PSoC4/CyLib.c **** * amplitude reached 60% and it does not mean 24 MHz crystal is within 50 ppm. +1117:Generated_Source\PSoC4/CyLib.c **** * +1118:Generated_Source\PSoC4/CyLib.c **** * \return \ref CYRET_TIMEOUT Timeout occurred. If the crystal is not oscillating +1119:Generated_Source\PSoC4/CyLib.c **** * or amplitude didn't reach 60% after specified amount of time, CYRET_TIMEOUT +1120:Generated_Source\PSoC4/CyLib.c **** * is returned. +1121:Generated_Source\PSoC4/CyLib.c **** * +1122:Generated_Source\PSoC4/CyLib.c **** * \return \ref CYRET_BAD_PARAM One or more invalid parameters. +1123:Generated_Source\PSoC4/CyLib.c **** * +1124:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1125:Generated_Source\PSoC4/CyLib.c **** cystatus CySysClkEcoStart(uint32 timeoutUs) +1126:Generated_Source\PSoC4/CyLib.c **** { +1127:Generated_Source\PSoC4/CyLib.c **** cystatus returnStatus = CYRET_SUCCESS; +1128:Generated_Source\PSoC4/CyLib.c **** +1129:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_ECO_BLESS) +1130:Generated_Source\PSoC4/CyLib.c **** /* Enable the RF oscillator band gap */ +1131:Generated_Source\PSoC4/CyLib.c **** CY_SYS_XTAL_BLESS_RF_CONFIG_REG |= CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; +1132:Generated_Source\PSoC4/CyLib.c **** +1133:Generated_Source\PSoC4/CyLib.c **** /* Update trimming register */ +1134:Generated_Source\PSoC4/CyLib.c **** CY_SYS_XTAL_BLERD_BB_XO_REG = CY_SYS_XTAL_BLERD_BB_XO_TRIM; +1135:Generated_Source\PSoC4/CyLib.c **** +1136:Generated_Source\PSoC4/CyLib.c **** /* Enable the Crystal */ +1137:Generated_Source\PSoC4/CyLib.c **** CY_SYS_XTAL_BLERD_DBUS_REG |= CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; +1138:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 34 + + +1139:Generated_Source\PSoC4/CyLib.c **** #elif (CY_IP_ECO_BLESSV3) +1140:Generated_Source\PSoC4/CyLib.c **** uint32 regConfig; +1141:Generated_Source\PSoC4/CyLib.c **** uint32 intrRegMaskStore = 0u; +1142:Generated_Source\PSoC4/CyLib.c **** +1143:Generated_Source\PSoC4/CyLib.c **** if (0u != (CY_SYS_BLESS_MT_CFG_REG & (CY_SYS_BLESS_MT_CFG_ENABLE_BLERD << CYFLD_BLE_BL +1144:Generated_Source\PSoC4/CyLib.c **** { +1145:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_MT_CFG_REG |= (CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_D +1146:Generated_Source\PSoC4/CyLib.c **** } +1147:Generated_Source\PSoC4/CyLib.c **** else +1148:Generated_Source\PSoC4/CyLib.c **** { +1149:Generated_Source\PSoC4/CyLib.c **** /* Init BLE core */ +1150:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_MT_DELAY_CFG_REG = CY_SYS_BLESS_MT_DELAY_CFG_INIT; +1151:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_MT_DELAY_CFG2_REG = CY_SYS_BLESS_MT_DELAY_CFG2_INIT; +1152:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_MT_DELAY_CFG3_REG = CY_SYS_BLESS_MT_DELAY_CFG3_INIT; +1153:Generated_Source\PSoC4/CyLib.c **** +1154:Generated_Source\PSoC4/CyLib.c **** /* RCB init */ +1155:Generated_Source\PSoC4/CyLib.c **** regConfig = CY_SYS_RCB_CTRL_REG; +1156:Generated_Source\PSoC4/CyLib.c **** regConfig &= CY_SYS_RCB_CTRL_CLEAR; +1157:Generated_Source\PSoC4/CyLib.c **** regConfig |= CY_SYS_RCB_CTRL_INIT; +1158:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_CTRL_REG = regConfig; +1159:Generated_Source\PSoC4/CyLib.c **** +1160:Generated_Source\PSoC4/CyLib.c **** intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; +1161:Generated_Source\PSoC4/CyLib.c **** if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) +1162:Generated_Source\PSoC4/CyLib.c **** { +1163:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_INTR_MASK_REG &= ~CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; +1164:Generated_Source\PSoC4/CyLib.c **** } +1165:Generated_Source\PSoC4/CyLib.c **** +1166:Generated_Source\PSoC4/CyLib.c **** /* Enable BLE core */ +1167:Generated_Source\PSoC4/CyLib.c **** regConfig = CY_SYS_BLESS_MT_CFG_REG; +1168:Generated_Source\PSoC4/CyLib.c **** regConfig &= CY_SYS_BLESS_MT_CFG_CLEAR; +1169:Generated_Source\PSoC4/CyLib.c **** regConfig |= CY_SYS_BLESS_MT_CFG_INIT; +1170:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_MT_CFG_REG = regConfig; +1171:Generated_Source\PSoC4/CyLib.c **** +1172:Generated_Source\PSoC4/CyLib.c **** while(0u == ((CY_SYS_BLESS_BLERD_ACTIVE_INTR_STAT & CY_SYS_BLESS_INTR_STAT_REG))) +1173:Generated_Source\PSoC4/CyLib.c **** { +1174:Generated_Source\PSoC4/CyLib.c **** /* Wait until BLERD55 moves to active state */ +1175:Generated_Source\PSoC4/CyLib.c **** } +1176:Generated_Source\PSoC4/CyLib.c **** +1177:Generated_Source\PSoC4/CyLib.c **** if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) +1178:Generated_Source\PSoC4/CyLib.c **** { +1179:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_INTR_MASK_REG |= CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; +1180:Generated_Source\PSoC4/CyLib.c **** } +1181:Generated_Source\PSoC4/CyLib.c **** +1182:Generated_Source\PSoC4/CyLib.c **** /* Send write commands to RBUS */ +1183:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_NRST_SET; +1184:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_DIG_CLK_SET; +1185:Generated_Source\PSoC4/CyLib.c **** +1186:Generated_Source\PSoC4/CyLib.c **** #if (CY_SYS_BLE_CLK_ECO_FREQ_32MHZ == CYDEV_ECO_CLK_MHZ) +1187:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_DIV_SET; +1188:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | CY_SYS_RCB_RBUS_ +1189:Generated_Source\PSoC4/CyLib.c **** #else +1190:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_NODIV_SET; +1191:Generated_Source\PSoC4/CyLib.c **** #endif +1192:Generated_Source\PSoC4/CyLib.c **** +1193:Generated_Source\PSoC4/CyLib.c **** intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; +1194:Generated_Source\PSoC4/CyLib.c **** if(0u != (CY_SYS_RCB_INTR_RCB_DONE & intrRegMaskStore)) +1195:Generated_Source\PSoC4/CyLib.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 35 + + +1196:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_INTR_MASK_REG &= ~(CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_ +1197:Generated_Source\PSoC4/CyLib.c **** } +1198:Generated_Source\PSoC4/CyLib.c **** +1199:Generated_Source\PSoC4/CyLib.c **** /* Send read commands to RBUS */ +1200:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RD_CMD | +1201:Generated_Source\PSoC4/CyLib.c **** (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET & ~CY_SYS_RCB_RBUS_VAL +1202:Generated_Source\PSoC4/CyLib.c **** +1203:Generated_Source\PSoC4/CyLib.c **** while (0u == (CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY & CY_SYS_RCB_INTR_REG)) +1204:Generated_Source\PSoC4/CyLib.c **** { +1205:Generated_Source\PSoC4/CyLib.c **** /* Wait until RX_FIFO_NOT_EMPTY state */ +1206:Generated_Source\PSoC4/CyLib.c **** } +1207:Generated_Source\PSoC4/CyLib.c **** +1208:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_INTR_REG |= CY_SYS_RCB_INTR_RCB_DONE; +1209:Generated_Source\PSoC4/CyLib.c **** +1210:Generated_Source\PSoC4/CyLib.c **** regConfig = CY_SYS_RCB_RX_FIFO_RD_REG & CY_SYS_RCB_RBUS_TRIM_MASK; +1211:Generated_Source\PSoC4/CyLib.c **** +1212:Generated_Source\PSoC4/CyLib.c **** /* Send write commands to RBUS */ +1213:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | regConfig | CY_SYS_R +1214:Generated_Source\PSoC4/CyLib.c **** +1215:Generated_Source\PSoC4/CyLib.c **** while (0u == (CY_SYS_RCB_INTR_RCB_DONE & CY_SYS_RCB_INTR_REG)) +1216:Generated_Source\PSoC4/CyLib.c **** { +1217:Generated_Source\PSoC4/CyLib.c **** /* Wait until RCB_DONE state */ +1218:Generated_Source\PSoC4/CyLib.c **** } +1219:Generated_Source\PSoC4/CyLib.c **** +1220:Generated_Source\PSoC4/CyLib.c **** /* Clear Interrupt */ +1221:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RCB_INTR_REG = CY_SYS_RCB_INTR_CLEAR; +1222:Generated_Source\PSoC4/CyLib.c **** +1223:Generated_Source\PSoC4/CyLib.c **** if(0u != ((CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY) & intr +1224:Generated_Source\PSoC4/CyLib.c **** { +1225:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_INTR_MASK_REG |= intrRegMaskStore; +1226:Generated_Source\PSoC4/CyLib.c **** } +1227:Generated_Source\PSoC4/CyLib.c **** +1228:Generated_Source\PSoC4/CyLib.c **** } +1229:Generated_Source\PSoC4/CyLib.c **** #else /* CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT */ +1230:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_ENABLE; +1231:Generated_Source\PSoC4/CyLib.c **** CyDelayUs(CY_SYS_CLK_ECO_CONFIG_CLK_EN_TIMEOUT_US); +1232:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_CLK_EN; +1233:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_ECO_BLESS) */ +1234:Generated_Source\PSoC4/CyLib.c **** +1235:Generated_Source\PSoC4/CyLib.c **** if(timeoutUs > 0u) +1236:Generated_Source\PSoC4/CyLib.c **** { +1237:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_TIMEOUT; +1238:Generated_Source\PSoC4/CyLib.c **** +1239:Generated_Source\PSoC4/CyLib.c **** for( ; timeoutUs > 0u; timeoutUs--) +1240:Generated_Source\PSoC4/CyLib.c **** { +1241:Generated_Source\PSoC4/CyLib.c **** CyDelayUs(1u); +1242:Generated_Source\PSoC4/CyLib.c **** +1243:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkEcoReadStatus()) +1244:Generated_Source\PSoC4/CyLib.c **** { +1245:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_SUCCESS; +1246:Generated_Source\PSoC4/CyLib.c **** break; +1247:Generated_Source\PSoC4/CyLib.c **** } +1248:Generated_Source\PSoC4/CyLib.c **** } +1249:Generated_Source\PSoC4/CyLib.c **** +1250:Generated_Source\PSoC4/CyLib.c **** } +1251:Generated_Source\PSoC4/CyLib.c **** +1252:Generated_Source\PSoC4/CyLib.c **** return(returnStatus); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 36 + + +1253:Generated_Source\PSoC4/CyLib.c **** } +1254:Generated_Source\PSoC4/CyLib.c **** +1255:Generated_Source\PSoC4/CyLib.c **** +1256:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1257:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkEcoStop +1258:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1259:Generated_Source\PSoC4/CyLib.c **** * +1260:Generated_Source\PSoC4/CyLib.c **** * Stops the megahertz crystal. +1261:Generated_Source\PSoC4/CyLib.c **** * +1262:Generated_Source\PSoC4/CyLib.c **** * If ECO is disabled when it is sourcing HFCLK, the CPU will halt. In addition, +1263:Generated_Source\PSoC4/CyLib.c **** * for PSoC 4100 BLE / PSoC 4200 BLE devices, the BLE sub-system will stop +1264:Generated_Source\PSoC4/CyLib.c **** * functioning. +1265:Generated_Source\PSoC4/CyLib.c **** * +1266:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1267:Generated_Source\PSoC4/CyLib.c **** void CySysClkEcoStop(void) +1268:Generated_Source\PSoC4/CyLib.c **** { +1269:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_WCO_BLESS) +1270:Generated_Source\PSoC4/CyLib.c **** /* Disable the RF oscillator band gap */ +1271:Generated_Source\PSoC4/CyLib.c **** CY_SYS_XTAL_BLESS_RF_CONFIG_REG &= (uint32) ~CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; +1272:Generated_Source\PSoC4/CyLib.c **** +1273:Generated_Source\PSoC4/CyLib.c **** /* Disable the Crystal */ +1274:Generated_Source\PSoC4/CyLib.c **** CY_SYS_XTAL_BLERD_DBUS_REG &= (uint32) ~CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; +1275:Generated_Source\PSoC4/CyLib.c **** #elif (CY_IP_ECO_BLESSV3) +1276:Generated_Source\PSoC4/CyLib.c **** CY_SYS_BLESS_MT_CFG_REG &= ~(CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSL +1277:Generated_Source\PSoC4/CyLib.c **** #else +1278:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~(CY_SYS_CLK_ECO_CONFIG_ENABLE | CY_SYS_CLK_ECO_C +1279:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_WCO_BLESS) */ +1280:Generated_Source\PSoC4/CyLib.c **** } +1281:Generated_Source\PSoC4/CyLib.c **** +1282:Generated_Source\PSoC4/CyLib.c **** +1283:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1284:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkEcoReadStatus +1285:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1286:Generated_Source\PSoC4/CyLib.c **** * +1287:Generated_Source\PSoC4/CyLib.c **** * Reads the status bit for the megahertz crystal. +1288:Generated_Source\PSoC4/CyLib.c **** * +1289:Generated_Source\PSoC4/CyLib.c **** * For PSoC 4100 BLE / PSoC 4200 BLE devices, the status bit is the +1290:Generated_Source\PSoC4/CyLib.c **** * XO_AMP_DETECT bit in FSM register. +1291:Generated_Source\PSoC4/CyLib.c **** * +1292:Generated_Source\PSoC4/CyLib.c **** * For PSoC 4200L / 4100S with ECO devices, the error status bit is the +1293:Generated_Source\PSoC4/CyLib.c **** * WATCHDOG_ERROR bit in ECO_STATUS register. +1294:Generated_Source\PSoC4/CyLib.c **** * +1295:Generated_Source\PSoC4/CyLib.c **** * \return PSoC 4100 BLE/PSoC 4200 BLE: Non-zero indicates that ECO output +1296:Generated_Source\PSoC4/CyLib.c **** * reached 50 ppm and is oscillating in valid range. +1297:Generated_Source\PSoC4/CyLib.c **** * +1298:Generated_Source\PSoC4/CyLib.c **** * \return PSoC 4200L / 4100S with ECO: Non-zero indicates that ECO is running. +1299:Generated_Source\PSoC4/CyLib.c **** * +1300:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1301:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkEcoReadStatus(void) +1302:Generated_Source\PSoC4/CyLib.c **** { +1303:Generated_Source\PSoC4/CyLib.c **** uint32 returnValue; +1304:Generated_Source\PSoC4/CyLib.c **** +1305:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_WCO_BLESS) +1306:Generated_Source\PSoC4/CyLib.c **** returnValue = CY_SYS_XTAL_BLERD_FSM_REG & CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT; +1307:Generated_Source\PSoC4/CyLib.c **** #elif (CY_IP_ECO_BLESSV3) +1308:Generated_Source\PSoC4/CyLib.c **** returnValue = (CY_SYS_BLESS_MT_STATUS_REG & CY_SYS_BLESS_MT_STATUS_CURR_STATE_MASK) >> +1309:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 37 + + +1310:Generated_Source\PSoC4/CyLib.c **** returnValue = ((CY_SYS_BLESS_MT_STATUS_BLERD_IDLE == returnValue) || +1311:Generated_Source\PSoC4/CyLib.c **** (CY_SYS_BLESS_MT_STATUS_SWITCH_EN == returnValue) || +1312:Generated_Source\PSoC4/CyLib.c **** (CY_SYS_BLESS_MT_STATUS_ACTIVE == returnValue) || +1313:Generated_Source\PSoC4/CyLib.c **** (CY_SYS_BLESS_MT_STATUS_ISOLATE == returnValue)); +1314:Generated_Source\PSoC4/CyLib.c **** #else +1315:Generated_Source\PSoC4/CyLib.c **** returnValue = (0u != (CY_SYS_CLK_ECO_STATUS_REG & CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR) +1316:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_WCO_BLESS) */ +1317:Generated_Source\PSoC4/CyLib.c **** +1318:Generated_Source\PSoC4/CyLib.c **** return (returnValue); +1319:Generated_Source\PSoC4/CyLib.c **** } +1320:Generated_Source\PSoC4/CyLib.c **** +1321:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) +1322:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1323:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkWriteEcoDiv +1324:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1325:Generated_Source\PSoC4/CyLib.c **** * +1326:Generated_Source\PSoC4/CyLib.c **** * Selects value for the ECO divider. +1327:Generated_Source\PSoC4/CyLib.c **** * +1328:Generated_Source\PSoC4/CyLib.c **** * The ECO must not be the HFCLK clock source when this function is called. +1329:Generated_Source\PSoC4/CyLib.c **** * The HFCLK source can be changed to the other clock source by call to the +1330:Generated_Source\PSoC4/CyLib.c **** * CySysClkWriteHfclkDirect() function. If the ECO sources the HFCLK this +1331:Generated_Source\PSoC4/CyLib.c **** * function will not have any effect if compiler in release mode, and halt the +1332:Generated_Source\PSoC4/CyLib.c **** * CPU when compiler in debug mode. +1333:Generated_Source\PSoC4/CyLib.c **** * +1334:Generated_Source\PSoC4/CyLib.c **** * If the SYSCLK clock frequency increases during the device operation, call +1335:Generated_Source\PSoC4/CyLib.c **** * CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number +1336:Generated_Source\PSoC4/CyLib.c **** * of clock cycles the cache will wait before sampling data comes back from +1337:Generated_Source\PSoC4/CyLib.c **** * Flash. If the SYSCLK clock frequency decreases, you can call +1338:Generated_Source\PSoC4/CyLib.c **** * CySysFlashSetWaitCycles() to improve the CPU performance. See +1339:Generated_Source\PSoC4/CyLib.c **** * CySysFlashSetWaitCycles() description for more information. +1340:Generated_Source\PSoC4/CyLib.c **** * +1341:Generated_Source\PSoC4/CyLib.c **** * \param divider Power of 2 divider selection. +1342:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_DIV1 +1343:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_DIV2 +1344:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_DIV4 +1345:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_DIV8 +1346:Generated_Source\PSoC4/CyLib.c **** * +1347:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1348:Generated_Source\PSoC4/CyLib.c **** void CySysClkWriteEcoDiv(uint32 divider) +1349:Generated_Source\PSoC4/CyLib.c **** { +1350:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1351:Generated_Source\PSoC4/CyLib.c **** +1352:Generated_Source\PSoC4/CyLib.c **** if (CY_SYS_CLK_HFCLK_ECO != (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) +1353:Generated_Source\PSoC4/CyLib.c **** { +1354:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1355:Generated_Source\PSoC4/CyLib.c **** +1356:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG = (divider & CY_SYS_CLK_XTAL_CLK_DIV_MASK) | +1357:Generated_Source\PSoC4/CyLib.c **** (CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG & ((uint3 +1358:Generated_Source\PSoC4/CyLib.c **** +1359:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1360:Generated_Source\PSoC4/CyLib.c **** } +1361:Generated_Source\PSoC4/CyLib.c **** else +1362:Generated_Source\PSoC4/CyLib.c **** { +1363:Generated_Source\PSoC4/CyLib.c **** /* Halt CPU in debug mode if ECO sources HFCLK */ +1364:Generated_Source\PSoC4/CyLib.c **** CYASSERT(0u != 0u); +1365:Generated_Source\PSoC4/CyLib.c **** } +1366:Generated_Source\PSoC4/CyLib.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 38 + + +1367:Generated_Source\PSoC4/CyLib.c **** +1368:Generated_Source\PSoC4/CyLib.c **** #else +1369:Generated_Source\PSoC4/CyLib.c **** +1370:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1371:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkConfigureEcoTrim +1372:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1373:Generated_Source\PSoC4/CyLib.c **** * +1374:Generated_Source\PSoC4/CyLib.c **** * Selects trim setting values for ECO. This API is available only for PSoC +1375:Generated_Source\PSoC4/CyLib.c **** * 4200L / 4100S with ECO devices only. +1376:Generated_Source\PSoC4/CyLib.c **** * +1377:Generated_Source\PSoC4/CyLib.c **** * The following parameters can be trimmed for ECO. The affected registers are +1378:Generated_Source\PSoC4/CyLib.c **** * ECO_TRIM0 and ECO_TRIM1. +1379:Generated_Source\PSoC4/CyLib.c **** * +1380:Generated_Source\PSoC4/CyLib.c **** * Watchdog trim - This bit field sets the error threshold below the steady +1381:Generated_Source\PSoC4/CyLib.c **** * state amplitude level. +1382:Generated_Source\PSoC4/CyLib.c **** * +1383:Generated_Source\PSoC4/CyLib.c **** * Amplitude trim - This bit field is to set the crystal drive level when +1384:Generated_Source\PSoC4/CyLib.c **** * ECO_CONFIG.AGC_EN = 1. WARNING: use care when setting this field because +1385:Generated_Source\PSoC4/CyLib.c **** * driving a crystal beyond its rated limit can permanently damage the crystal. +1386:Generated_Source\PSoC4/CyLib.c **** * +1387:Generated_Source\PSoC4/CyLib.c **** * Filter frequency trim - This bit field sets LPF frequency trim and affects +1388:Generated_Source\PSoC4/CyLib.c **** * the 3rd harmonic content. +1389:Generated_Source\PSoC4/CyLib.c **** * +1390:Generated_Source\PSoC4/CyLib.c **** * Feedback resistor trim - This bit field sets the feedback resistor trim and +1391:Generated_Source\PSoC4/CyLib.c **** * impacts the oscillation amplitude. +1392:Generated_Source\PSoC4/CyLib.c **** * +1393:Generated_Source\PSoC4/CyLib.c **** * Amplifier gain trim - This bit field sets the amplifier gain trim and affects +1394:Generated_Source\PSoC4/CyLib.c **** * the startup time of the crystal. +1395:Generated_Source\PSoC4/CyLib.c **** * +1396:Generated_Source\PSoC4/CyLib.c **** * Use care when setting the amplitude trim field because driving a crystal +1397:Generated_Source\PSoC4/CyLib.c **** * beyond its rated limit can permanently damage the crystal. +1398:Generated_Source\PSoC4/CyLib.c **** * +1399:Generated_Source\PSoC4/CyLib.c **** * \param wDTrim: Watchdog trim +1400:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_WDTRIM0 Error threshold is 0.05 V +1401:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_WDTRIM1 Error threshold is 0.10 V +1402:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_WDTRIM2 Error threshold is 0.15 V +1403:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_WDTRIM3 Error threshold is 0.20 V +1404:Generated_Source\PSoC4/CyLib.c **** * +1405:Generated_Source\PSoC4/CyLib.c **** * \param aTrim: Amplitude trim +1406:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM0 Amplitude is 0.3 Vpp +1407:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM1 Amplitude is 0.4 Vpp +1408:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM2 Amplitude is 0.5 Vpp +1409:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM3 Amplitude is 0.6 Vpp +1410:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM4 Amplitude is 0.7 Vpp +1411:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM5 Amplitude is 0.8 Vpp +1412:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM6 Amplitude is 0.9 Vpp +1413:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_ATRIM7 Amplitude is 1.0 Vpp +1414:Generated_Source\PSoC4/CyLib.c **** * +1415:Generated_Source\PSoC4/CyLib.c **** * \param fTrim: Filter frequency trim +1416:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_FTRIM0 Crystal frequency > 30 MHz +1417:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_FTRIM1 24 MHz < Crystal frequency <= 30 MHz +1418:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_FTRIM2 17 MHz < Crystal frequency <= 24 MHz +1419:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_FTRIM3 Crystal frequency <= 17 MHz +1420:Generated_Source\PSoC4/CyLib.c **** * +1421:Generated_Source\PSoC4/CyLib.c **** * \param rTrim: Feedback resistor trim +1422:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_RTRIM0 Crystal frequency > 30 MHz +1423:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_RTRIM1 24 MHz < Crystal frequency <= 30 MHz + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 39 + + +1424:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_RTRIM2 17 MHz < Crystal frequency <= 24 MHz +1425:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_RTRIM3 Crystal frequency <= 17 MHz +1426:Generated_Source\PSoC4/CyLib.c **** * +1427:Generated_Source\PSoC4/CyLib.c **** * \param gTrim: Amplifier gain trim. Calculate the minimum required gm +1428:Generated_Source\PSoC4/CyLib.c **** * (trans-conductance value). Divide the calculated gm value by 4.5 to +1429:Generated_Source\PSoC4/CyLib.c **** * obtain an integer value 'result'. For more information please refer +1430:Generated_Source\PSoC4/CyLib.c **** * to the device TRM. +1431:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_GTRIM0 If result = 1 +1432:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_GTRIM1 If result = 0 +1433:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 2 +1434:Generated_Source\PSoC4/CyLib.c **** * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 3 +1435:Generated_Source\PSoC4/CyLib.c **** * +1436:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1437:Generated_Source\PSoC4/CyLib.c **** void CySysClkConfigureEcoTrim(uint32 wDTrim, uint32 aTrim, uint32 fTrim, uint32 rTrim, uint +1438:Generated_Source\PSoC4/CyLib.c **** { +1439:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1440:Generated_Source\PSoC4/CyLib.c **** uint32 regTmp; +1441:Generated_Source\PSoC4/CyLib.c **** +1442:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1443:Generated_Source\PSoC4/CyLib.c **** +1444:Generated_Source\PSoC4/CyLib.c **** regTmp = CY_SYS_CLK_ECO_TRIM0_REG & ~(CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK | CY_SYS_CLK_EC +1445:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((uint32) (wDTrim << CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM +1446:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((uint32) (aTrim << CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM0_ +1447:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_TRIM0_REG = regTmp; +1448:Generated_Source\PSoC4/CyLib.c **** +1449:Generated_Source\PSoC4/CyLib.c **** regTmp = CY_SYS_CLK_ECO_TRIM1_REG & ~(CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK | +1450:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK | +1451:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK); +1452:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((uint32) (fTrim << CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_ +1453:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((uint32) (rTrim << CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_ +1454:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((uint32) (gTrim << CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_ +1455:Generated_Source\PSoC4/CyLib.c **** +1456:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_TRIM1_REG = regTmp; +1457:Generated_Source\PSoC4/CyLib.c **** +1458:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1459:Generated_Source\PSoC4/CyLib.c **** } +1460:Generated_Source\PSoC4/CyLib.c **** +1461:Generated_Source\PSoC4/CyLib.c **** +1462:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1463:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkConfigureEcoDrive +1464:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1465:Generated_Source\PSoC4/CyLib.c **** * +1466:Generated_Source\PSoC4/CyLib.c **** * Selects trim setting values for ECO based on crystal parameters. Use care +1467:Generated_Source\PSoC4/CyLib.c **** * when setting the driveLevel parameter because driving a crystal beyond its +1468:Generated_Source\PSoC4/CyLib.c **** * rated limit can permanently damage the crystal. +1469:Generated_Source\PSoC4/CyLib.c **** * +1470:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with ECO devices only. +1471:Generated_Source\PSoC4/CyLib.c **** * +1472:Generated_Source\PSoC4/CyLib.c **** * \param freq Frequency of the crystal in kHz. +1473:Generated_Source\PSoC4/CyLib.c **** * \param cLoad Crystal load capacitance in pF. +1474:Generated_Source\PSoC4/CyLib.c **** * \param esr Equivalent series resistance of the crystal in ohm. +1475:Generated_Source\PSoC4/CyLib.c **** * maxAmplitude: maximum amplitude level in mV. Calculate as +1476:Generated_Source\PSoC4/CyLib.c **** * ((sqrt(driveLevel in uW / 2 / esr))/(3.14 * freq * cLoad)) * 10^9. +1477:Generated_Source\PSoC4/CyLib.c **** * +1478:Generated_Source\PSoC4/CyLib.c **** * The Automatic Gain Control (AGC) is disabled when the specified maximum +1479:Generated_Source\PSoC4/CyLib.c **** * amplitude level equals or above 2. In this case the amplitude is not +1480:Generated_Source\PSoC4/CyLib.c **** * explicitly controlled and will grow until it saturates to the supply rail + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 40 + + +1481:Generated_Source\PSoC4/CyLib.c **** * (1.8V nom). WARNING: use care when disabling AGC because driving a crystal +1482:Generated_Source\PSoC4/CyLib.c **** * beyond its rated limit can permanently damage the crystal. +1483:Generated_Source\PSoC4/CyLib.c **** * +1484:Generated_Source\PSoC4/CyLib.c **** * \return \ref CYRET_SUCCESS ECO configuration completed successfully. +1485:Generated_Source\PSoC4/CyLib.c **** * \return \ref CYRET_BAD_PARAM One or more invalid parameters. +1486:Generated_Source\PSoC4/CyLib.c **** * +1487:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1488:Generated_Source\PSoC4/CyLib.c **** cystatus CySysClkConfigureEcoDrive(uint32 freq, uint32 cLoad, uint32 esr, uint32 maxAmplitu +1489:Generated_Source\PSoC4/CyLib.c **** { +1490:Generated_Source\PSoC4/CyLib.c **** cystatus returnStatus = CYRET_SUCCESS; +1491:Generated_Source\PSoC4/CyLib.c **** +1492:Generated_Source\PSoC4/CyLib.c **** uint32 wDTrim; +1493:Generated_Source\PSoC4/CyLib.c **** uint32 aTrim; +1494:Generated_Source\PSoC4/CyLib.c **** uint32 fTrim; +1495:Generated_Source\PSoC4/CyLib.c **** uint32 rTrim; +1496:Generated_Source\PSoC4/CyLib.c **** uint32 gTrim; +1497:Generated_Source\PSoC4/CyLib.c **** +1498:Generated_Source\PSoC4/CyLib.c **** uint32 gmMin; +1499:Generated_Source\PSoC4/CyLib.c **** +1500:Generated_Source\PSoC4/CyLib.c **** +1501:Generated_Source\PSoC4/CyLib.c **** if ((maxAmplitude < CY_SYS_CLK_ECO_MAX_AMPL_MIN_mV) || +1502:Generated_Source\PSoC4/CyLib.c **** (freq < CY_SYS_CLK_ECO_FREQ_KHZ_MIN) || (freq > CY_SYS_CLK_ECO_FREQ_KHZ_MAX)) +1503:Generated_Source\PSoC4/CyLib.c **** { +1504:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_BAD_PARAM; +1505:Generated_Source\PSoC4/CyLib.c **** } +1506:Generated_Source\PSoC4/CyLib.c **** else +1507:Generated_Source\PSoC4/CyLib.c **** { +1508:Generated_Source\PSoC4/CyLib.c **** /* Calculate amplitude trim */ +1509:Generated_Source\PSoC4/CyLib.c **** aTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/100u) - 4u) +1510:Generated_Source\PSoC4/CyLib.c **** +1511:Generated_Source\PSoC4/CyLib.c **** if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM0) +1512:Generated_Source\PSoC4/CyLib.c **** { +1513:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM0; +1514:Generated_Source\PSoC4/CyLib.c **** } +1515:Generated_Source\PSoC4/CyLib.c **** else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM1) +1516:Generated_Source\PSoC4/CyLib.c **** { +1517:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM1; +1518:Generated_Source\PSoC4/CyLib.c **** } +1519:Generated_Source\PSoC4/CyLib.c **** else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM2) +1520:Generated_Source\PSoC4/CyLib.c **** { +1521:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM2; +1522:Generated_Source\PSoC4/CyLib.c **** } +1523:Generated_Source\PSoC4/CyLib.c **** else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM3) +1524:Generated_Source\PSoC4/CyLib.c **** { +1525:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM3; +1526:Generated_Source\PSoC4/CyLib.c **** } +1527:Generated_Source\PSoC4/CyLib.c **** else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM4) +1528:Generated_Source\PSoC4/CyLib.c **** { +1529:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM4; +1530:Generated_Source\PSoC4/CyLib.c **** } +1531:Generated_Source\PSoC4/CyLib.c **** else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM5) +1532:Generated_Source\PSoC4/CyLib.c **** { +1533:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM5; +1534:Generated_Source\PSoC4/CyLib.c **** } +1535:Generated_Source\PSoC4/CyLib.c **** else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM6) +1536:Generated_Source\PSoC4/CyLib.c **** { +1537:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM6; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 41 + + +1538:Generated_Source\PSoC4/CyLib.c **** } +1539:Generated_Source\PSoC4/CyLib.c **** else +1540:Generated_Source\PSoC4/CyLib.c **** { +1541:Generated_Source\PSoC4/CyLib.c **** aTrim = CY_SYS_CLK_ECO_ATRIM7; +1542:Generated_Source\PSoC4/CyLib.c **** } +1543:Generated_Source\PSoC4/CyLib.c **** +1544:Generated_Source\PSoC4/CyLib.c **** /* Calculate Watchdog trim. */ +1545:Generated_Source\PSoC4/CyLib.c **** wDTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/200u) - 2u) +1546:Generated_Source\PSoC4/CyLib.c **** +1547:Generated_Source\PSoC4/CyLib.c **** /* Calculate amplifier gain trim. */ +1548:Generated_Source\PSoC4/CyLib.c **** gmMin = (uint32) (((((CY_SYS_CLK_ECO_GMMIN_COEFFICIENT * freq * cLoad) / 1000) * (( +1549:Generated_Source\PSoC4/CyLib.c **** if (gmMin > 3u) +1550:Generated_Source\PSoC4/CyLib.c **** { +1551:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_BAD_PARAM; +1552:Generated_Source\PSoC4/CyLib.c **** gTrim = 0u; +1553:Generated_Source\PSoC4/CyLib.c **** } +1554:Generated_Source\PSoC4/CyLib.c **** else if (gmMin > 1u) +1555:Generated_Source\PSoC4/CyLib.c **** { +1556:Generated_Source\PSoC4/CyLib.c **** gTrim = gmMin; +1557:Generated_Source\PSoC4/CyLib.c **** } +1558:Generated_Source\PSoC4/CyLib.c **** else +1559:Generated_Source\PSoC4/CyLib.c **** { +1560:Generated_Source\PSoC4/CyLib.c **** gTrim = (gmMin == 1u) ? 0u : 1u; +1561:Generated_Source\PSoC4/CyLib.c **** } +1562:Generated_Source\PSoC4/CyLib.c **** +1563:Generated_Source\PSoC4/CyLib.c **** /* Calculate feedback resistor trim */ +1564:Generated_Source\PSoC4/CyLib.c **** if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM0) +1565:Generated_Source\PSoC4/CyLib.c **** { +1566:Generated_Source\PSoC4/CyLib.c **** rTrim = CY_SYS_CLK_ECO_FTRIM0; +1567:Generated_Source\PSoC4/CyLib.c **** } +1568:Generated_Source\PSoC4/CyLib.c **** else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM1) +1569:Generated_Source\PSoC4/CyLib.c **** { +1570:Generated_Source\PSoC4/CyLib.c **** rTrim = CY_SYS_CLK_ECO_FTRIM1; +1571:Generated_Source\PSoC4/CyLib.c **** } +1572:Generated_Source\PSoC4/CyLib.c **** else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM2) +1573:Generated_Source\PSoC4/CyLib.c **** { +1574:Generated_Source\PSoC4/CyLib.c **** rTrim = CY_SYS_CLK_ECO_FTRIM2; +1575:Generated_Source\PSoC4/CyLib.c **** } +1576:Generated_Source\PSoC4/CyLib.c **** else +1577:Generated_Source\PSoC4/CyLib.c **** { +1578:Generated_Source\PSoC4/CyLib.c **** rTrim = CY_SYS_CLK_ECO_FTRIM3; +1579:Generated_Source\PSoC4/CyLib.c **** } +1580:Generated_Source\PSoC4/CyLib.c **** +1581:Generated_Source\PSoC4/CyLib.c **** /* Calculate filter frequency trim */ +1582:Generated_Source\PSoC4/CyLib.c **** fTrim = rTrim; +1583:Generated_Source\PSoC4/CyLib.c **** +1584:Generated_Source\PSoC4/CyLib.c **** CySysClkConfigureEcoTrim(wDTrim, aTrim, fTrim, rTrim, gTrim); +1585:Generated_Source\PSoC4/CyLib.c **** +1586:Generated_Source\PSoC4/CyLib.c **** /* Automatic Gain Control (AGC) enable */ +1587:Generated_Source\PSoC4/CyLib.c **** if (maxAmplitude < 2u) +1588:Generated_Source\PSoC4/CyLib.c **** { +1589:Generated_Source\PSoC4/CyLib.c **** /* The oscillation amplitude is controlled to the level selected by amplitude t +1590:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_AGC_EN; +1591:Generated_Source\PSoC4/CyLib.c **** } +1592:Generated_Source\PSoC4/CyLib.c **** else +1593:Generated_Source\PSoC4/CyLib.c **** { +1594:Generated_Source\PSoC4/CyLib.c **** /* The amplitude is not explicitly controlled and will grow until it saturates + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 42 + + +1595:Generated_Source\PSoC4/CyLib.c **** * supply rail (1.8V nom). +1596:Generated_Source\PSoC4/CyLib.c **** */ +1597:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_ECO_CONFIG_AGC_EN; +1598:Generated_Source\PSoC4/CyLib.c **** } +1599:Generated_Source\PSoC4/CyLib.c **** } +1600:Generated_Source\PSoC4/CyLib.c **** +1601:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); +1602:Generated_Source\PSoC4/CyLib.c **** } +1603:Generated_Source\PSoC4/CyLib.c **** +1604:Generated_Source\PSoC4/CyLib.c **** #endif /* CY_IP_ECO_BLESS */ +1605:Generated_Source\PSoC4/CyLib.c **** +1606:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_ECO) */ +1607:Generated_Source\PSoC4/CyLib.c **** +1608:Generated_Source\PSoC4/CyLib.c **** +1609:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_PLL) +1610:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1611:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllStart +1612:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1613:Generated_Source\PSoC4/CyLib.c **** * +1614:Generated_Source\PSoC4/CyLib.c **** * Enables the PLL. Optionally waits for it to become stable. Waits at least +1615:Generated_Source\PSoC4/CyLib.c **** * 250 us or until it is detected that the PLL is stable. +1616:Generated_Source\PSoC4/CyLib.c **** * +1617:Generated_Source\PSoC4/CyLib.c **** * Clears the unlock occurred status bit by calling CySysClkPllGetUnlockStatus(), +1618:Generated_Source\PSoC4/CyLib.c **** * once the PLL is locked if the wait parameter is 1). +1619:Generated_Source\PSoC4/CyLib.c **** * +1620:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1621:Generated_Source\PSoC4/CyLib.c **** * +1622:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +1623:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1624:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1625:Generated_Source\PSoC4/CyLib.c **** * +1626:Generated_Source\PSoC4/CyLib.c **** * \param wait: +1627:Generated_Source\PSoC4/CyLib.c **** * 0 - Return immediately after configuration. +1628:Generated_Source\PSoC4/CyLib.c **** * 1 - Wait for PLL lock or timeout. This API shall use the CyDelayUs() to +1629:Generated_Source\PSoC4/CyLib.c **** * implement the timeout feature. +1630:Generated_Source\PSoC4/CyLib.c **** * +1631:Generated_Source\PSoC4/CyLib.c **** * \return CYRET_SUCCESS Completed successfully. +1632:Generated_Source\PSoC4/CyLib.c **** * \return CYRET_TIMEOUT The timeout occurred without detecting a stable clock. +1633:Generated_Source\PSoC4/CyLib.c **** * If the input source of the clock is jittery, then the lock indication may +1634:Generated_Source\PSoC4/CyLib.c **** * not occur. However, after the timeout has expired, the generated PLL clock can +1635:Generated_Source\PSoC4/CyLib.c **** * still be used. +1636:Generated_Source\PSoC4/CyLib.c **** * \return CYRET_BAD_PARAM - Either the PLL or wait parameter is invalid. +1637:Generated_Source\PSoC4/CyLib.c **** * +1638:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1639:Generated_Source\PSoC4/CyLib.c **** cystatus CySysClkPllStart(uint32 pll, uint32 wait) +1640:Generated_Source\PSoC4/CyLib.c **** { +1641:Generated_Source\PSoC4/CyLib.c **** uint32 counts = CY_SYS_CLK_PLL_MAX_STARTUP_US; +1642:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1643:Generated_Source\PSoC4/CyLib.c **** cystatus returnStatus = CYRET_SUCCESS; +1644:Generated_Source\PSoC4/CyLib.c **** +1645:Generated_Source\PSoC4/CyLib.c **** if((pll < CY_IP_PLL_NR) && (wait <= 1u)) +1646:Generated_Source\PSoC4/CyLib.c **** { +1647:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1648:Generated_Source\PSoC4/CyLib.c **** +1649:Generated_Source\PSoC4/CyLib.c **** /* Isolate PLL outputs */ +1650:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~CY_SYS_CLK_PLL_CONFIG_ISOLATE; +1651:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 43 + + +1652:Generated_Source\PSoC4/CyLib.c **** /* Enable PLL */ +1653:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ENABLE; +1654:Generated_Source\PSoC4/CyLib.c **** +1655:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1656:Generated_Source\PSoC4/CyLib.c **** +1657:Generated_Source\PSoC4/CyLib.c **** /* De-isolate >= CY_SYS_CLK_PLL_MIN_STARTUP_US after PLL enabled */ +1658:Generated_Source\PSoC4/CyLib.c **** CyDelayUs(CY_SYS_CLK_PLL_MIN_STARTUP_US); +1659:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1660:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ISOLATE; +1661:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1662:Generated_Source\PSoC4/CyLib.c **** +1663:Generated_Source\PSoC4/CyLib.c **** if(wait != 0u) +1664:Generated_Source\PSoC4/CyLib.c **** { +1665:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_TIMEOUT; +1666:Generated_Source\PSoC4/CyLib.c **** +1667:Generated_Source\PSoC4/CyLib.c **** while(0u != counts) +1668:Generated_Source\PSoC4/CyLib.c **** { +1669:Generated_Source\PSoC4/CyLib.c **** +1670:Generated_Source\PSoC4/CyLib.c **** if(0u != CySysClkPllGetLockStatus(pll)) +1671:Generated_Source\PSoC4/CyLib.c **** { +1672:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_SUCCESS; +1673:Generated_Source\PSoC4/CyLib.c **** (void) CySysClkPllGetUnlockStatus(pll); +1674:Generated_Source\PSoC4/CyLib.c **** break; +1675:Generated_Source\PSoC4/CyLib.c **** } +1676:Generated_Source\PSoC4/CyLib.c **** +1677:Generated_Source\PSoC4/CyLib.c **** CyDelayUs(1u); +1678:Generated_Source\PSoC4/CyLib.c **** counts--; +1679:Generated_Source\PSoC4/CyLib.c **** } +1680:Generated_Source\PSoC4/CyLib.c **** } +1681:Generated_Source\PSoC4/CyLib.c **** } +1682:Generated_Source\PSoC4/CyLib.c **** else +1683:Generated_Source\PSoC4/CyLib.c **** { +1684:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_BAD_PARAM; +1685:Generated_Source\PSoC4/CyLib.c **** } +1686:Generated_Source\PSoC4/CyLib.c **** +1687:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); +1688:Generated_Source\PSoC4/CyLib.c **** } +1689:Generated_Source\PSoC4/CyLib.c **** +1690:Generated_Source\PSoC4/CyLib.c **** +1691:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1692:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllGetLockStatus +1693:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1694:Generated_Source\PSoC4/CyLib.c **** * +1695:Generated_Source\PSoC4/CyLib.c **** * Returns non-zero if the output of the specified PLL output is locked. +1696:Generated_Source\PSoC4/CyLib.c **** * +1697:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1698:Generated_Source\PSoC4/CyLib.c **** * +1699:Generated_Source\PSoC4/CyLib.c **** * PLL: +1700:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1701:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1702:Generated_Source\PSoC4/CyLib.c **** * +1703:Generated_Source\PSoC4/CyLib.c **** * \return A non-zero value when the specified PLL is locked. +1704:Generated_Source\PSoC4/CyLib.c **** * +1705:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1706:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkPllGetLockStatus(uint32 pll) +1707:Generated_Source\PSoC4/CyLib.c **** { +1708:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 44 + + +1709:Generated_Source\PSoC4/CyLib.c **** uint32 returnStatus; +1710:Generated_Source\PSoC4/CyLib.c **** +1711:Generated_Source\PSoC4/CyLib.c **** CYASSERT(pll < CY_IP_PLL_NR); +1712:Generated_Source\PSoC4/CyLib.c **** +1713:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1714:Generated_Source\PSoC4/CyLib.c **** +1715:Generated_Source\PSoC4/CyLib.c **** /* PLL is locked if reported so for two consecutive read. */ +1716:Generated_Source\PSoC4/CyLib.c **** returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; +1717:Generated_Source\PSoC4/CyLib.c **** if(0u != returnStatus) +1718:Generated_Source\PSoC4/CyLib.c **** { +1719:Generated_Source\PSoC4/CyLib.c **** returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; +1720:Generated_Source\PSoC4/CyLib.c **** } +1721:Generated_Source\PSoC4/CyLib.c **** +1722:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1723:Generated_Source\PSoC4/CyLib.c **** +1724:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); +1725:Generated_Source\PSoC4/CyLib.c **** } +1726:Generated_Source\PSoC4/CyLib.c **** +1727:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1728:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllStop +1729:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1730:Generated_Source\PSoC4/CyLib.c **** * +1731:Generated_Source\PSoC4/CyLib.c **** * Disables the PLL. +1732:Generated_Source\PSoC4/CyLib.c **** * +1733:Generated_Source\PSoC4/CyLib.c **** * Ensures that either PLL is not the source of HFCLK before it is disabled, +1734:Generated_Source\PSoC4/CyLib.c **** * otherwise, the CPU will halt. +1735:Generated_Source\PSoC4/CyLib.c **** * +1736:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1737:Generated_Source\PSoC4/CyLib.c **** * +1738:Generated_Source\PSoC4/CyLib.c **** * PLL: +1739:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1740:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1741:Generated_Source\PSoC4/CyLib.c **** * +1742:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1743:Generated_Source\PSoC4/CyLib.c **** void CySysClkPllStop(uint32 pll) +1744:Generated_Source\PSoC4/CyLib.c **** { +1745:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1746:Generated_Source\PSoC4/CyLib.c **** +1747:Generated_Source\PSoC4/CyLib.c **** if (pll < CY_IP_PLL_NR) +1748:Generated_Source\PSoC4/CyLib.c **** { +1749:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1750:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~(CY_SYS_CLK_PLL_CONFIG_ISOLATE | CY_SY +1751:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1752:Generated_Source\PSoC4/CyLib.c **** } +1753:Generated_Source\PSoC4/CyLib.c **** } +1754:Generated_Source\PSoC4/CyLib.c **** +1755:Generated_Source\PSoC4/CyLib.c **** +1756:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1757:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllSetPQ +1758:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1759:Generated_Source\PSoC4/CyLib.c **** * +1760:Generated_Source\PSoC4/CyLib.c **** * Sets feedback (P) and reference the (Q) divider value. This API also sets the +1761:Generated_Source\PSoC4/CyLib.c **** * programmable charge pump current value. Note that the PLL has to be disabled +1762:Generated_Source\PSoC4/CyLib.c **** * before calling this API. If this function is called while any PLL is sourcing, +1763:Generated_Source\PSoC4/CyLib.c **** * the SYSCLK will return an error. +1764:Generated_Source\PSoC4/CyLib.c **** * +1765:Generated_Source\PSoC4/CyLib.c **** * The PLL must not be the system clock source when calling this function. The + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 45 + + +1766:Generated_Source\PSoC4/CyLib.c **** * PLL output will glitch during this function call. +1767:Generated_Source\PSoC4/CyLib.c **** * +1768:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1769:Generated_Source\PSoC4/CyLib.c **** * +1770:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +1771:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1772:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1773:Generated_Source\PSoC4/CyLib.c **** * +1774:Generated_Source\PSoC4/CyLib.c **** * \param feedback The P divider. Range 4 - 259. Control bits for the feedback +1775:Generated_Source\PSoC4/CyLib.c **** * divider. +1776:Generated_Source\PSoC4/CyLib.c **** * +1777:Generated_Source\PSoC4/CyLib.c **** * \param reference The Q divider. Range 1 - 64. Divide by the reference. +1778:Generated_Source\PSoC4/CyLib.c **** * +1779:Generated_Source\PSoC4/CyLib.c **** * \param current Charge the pump current in uA. The 2 uA for output frequencies +1780:Generated_Source\PSoC4/CyLib.c **** * of 67 MHz or less, and 3 uA for higher output frequencies. The default +1781:Generated_Source\PSoC4/CyLib.c **** * value is 2 uA. +1782:Generated_Source\PSoC4/CyLib.c **** * +1783:Generated_Source\PSoC4/CyLib.c **** * \return CYRET_SUCCESS Completed successfully. +1784:Generated_Source\PSoC4/CyLib.c **** * \return CYRET_BAD_PARAM The parameters are out of range or the specified PLL +1785:Generated_Source\PSoC4/CyLib.c **** * sources the system clock. +1786:Generated_Source\PSoC4/CyLib.c **** * +1787:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1788:Generated_Source\PSoC4/CyLib.c **** cystatus CySysClkPllSetPQ(uint32 pll, uint32 feedback, uint32 reference, uint32 current) +1789:Generated_Source\PSoC4/CyLib.c **** { +1790:Generated_Source\PSoC4/CyLib.c **** uint32 regTmp; +1791:Generated_Source\PSoC4/CyLib.c **** cystatus tmp; +1792:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1793:Generated_Source\PSoC4/CyLib.c **** cystatus returnStatus = CYRET_BAD_PARAM; +1794:Generated_Source\PSoC4/CyLib.c **** +1795:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1796:Generated_Source\PSoC4/CyLib.c **** +1797:Generated_Source\PSoC4/CyLib.c **** tmp = CySysClkPllConfigChangeAllowed(pll); +1798:Generated_Source\PSoC4/CyLib.c **** +1799:Generated_Source\PSoC4/CyLib.c **** if ((pll < CY_IP_PLL_NR) && +1800:Generated_Source\PSoC4/CyLib.c **** (feedback >= CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MIN) && (feedback <= CY_SYS_CLK_PLL_ +1801:Generated_Source\PSoC4/CyLib.c **** (reference >= CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MIN) && (reference <= CY_SYS_CLK_PLL_ +1802:Generated_Source\PSoC4/CyLib.c **** (current >= CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MIN ) && (current <= CY_SYS_CLK_PLL_ +1803:Generated_Source\PSoC4/CyLib.c **** (CYRET_SUCCESS == tmp)) +1804:Generated_Source\PSoC4/CyLib.c **** { +1805:Generated_Source\PSoC4/CyLib.c **** /* Set new feedback, reference and current values */ +1806:Generated_Source\PSoC4/CyLib.c **** regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_FEEDBA +1807:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_CONFIG_REFERE +1808:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_CONFIG_ICP_SE +1809:Generated_Source\PSoC4/CyLib.c **** +1810:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((feedback << CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT) & CY_SYS_CLK_PLL_CONF +1811:Generated_Source\PSoC4/CyLib.c **** regTmp |= (((reference - 1u) << CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT) & CY_SYS_CLK +1812:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((current << CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT) & CY_SYS_CLK_PLL_CONFIG_ICP +1813:Generated_Source\PSoC4/CyLib.c **** +1814:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; +1815:Generated_Source\PSoC4/CyLib.c **** +1816:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_SUCCESS; +1817:Generated_Source\PSoC4/CyLib.c **** } +1818:Generated_Source\PSoC4/CyLib.c **** +1819:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1820:Generated_Source\PSoC4/CyLib.c **** +1821:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); +1822:Generated_Source\PSoC4/CyLib.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 46 + + +1823:Generated_Source\PSoC4/CyLib.c **** +1824:Generated_Source\PSoC4/CyLib.c **** +1825:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1826:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllSetBypassMode +1827:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1828:Generated_Source\PSoC4/CyLib.c **** * +1829:Generated_Source\PSoC4/CyLib.c **** * Sets the bypass mode for the specified PLL. +1830:Generated_Source\PSoC4/CyLib.c **** * +1831:Generated_Source\PSoC4/CyLib.c **** * The PLL must not be the system clock source when calling this function. +1832:Generated_Source\PSoC4/CyLib.c **** * The PLL output will glitch during this function call. +1833:Generated_Source\PSoC4/CyLib.c **** * +1834:Generated_Source\PSoC4/CyLib.c **** * When the PLL's reference input is higher than HFCLK frequency the device may +1835:Generated_Source\PSoC4/CyLib.c **** * lock due to incorrect flash wait cycle configuration and bypass switches from +1836:Generated_Source\PSoC4/CyLib.c **** * PLL output to the reference input. See description of +1837:Generated_Source\PSoC4/CyLib.c **** * CySysFlashSetWaitCycles() for more information. +1838:Generated_Source\PSoC4/CyLib.c **** * +1839:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1840:Generated_Source\PSoC4/CyLib.c **** * +1841:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +1842:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1843:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1844:Generated_Source\PSoC4/CyLib.c **** * +1845:Generated_Source\PSoC4/CyLib.c **** * \param bypass: The bypass mode. +1846:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_BYPASS_AUTO - Automatic usage of the lock indicator. When unlocked, +1847:Generated_Source\PSoC4/CyLib.c **** * automatically selects PLL the reference input (bypass mode). When locked, +1848:Generated_Source\PSoC4/CyLib.c **** * automatically selects the PLL output. +1849:Generated_Source\PSoC4/CyLib.c **** * +1850:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_BYPASS_PLL_REF - Selects the PLL reference input (bypass mode). +1851:Generated_Source\PSoC4/CyLib.c **** * Ignores the lock indicator. +1852:Generated_Source\PSoC4/CyLib.c **** * +1853:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_BYPASS_PLL_OUT - Selects the PLL output. Ignores the lock indicator. +1854:Generated_Source\PSoC4/CyLib.c **** * +1855:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1856:Generated_Source\PSoC4/CyLib.c **** void CySysClkPllSetBypassMode(uint32 pll, uint32 bypass) +1857:Generated_Source\PSoC4/CyLib.c **** { +1858:Generated_Source\PSoC4/CyLib.c **** uint32 regTmp; +1859:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1860:Generated_Source\PSoC4/CyLib.c **** +1861:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1862:Generated_Source\PSoC4/CyLib.c **** +1863:Generated_Source\PSoC4/CyLib.c **** if ((pll < CY_IP_PLL_NR) && (bypass <= CY_SYS_PLL_BYPASS_PLL_OUT)) +1864:Generated_Source\PSoC4/CyLib.c **** { +1865:Generated_Source\PSoC4/CyLib.c **** regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~CY_SYS_CLK_PLL_CONFIG_BYPASS_ +1866:Generated_Source\PSoC4/CyLib.c **** regTmp |= (uint32)(bypass << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT); +1867:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; +1868:Generated_Source\PSoC4/CyLib.c **** } +1869:Generated_Source\PSoC4/CyLib.c **** +1870:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1871:Generated_Source\PSoC4/CyLib.c **** } +1872:Generated_Source\PSoC4/CyLib.c **** +1873:Generated_Source\PSoC4/CyLib.c **** +1874:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1875:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllGetBypassMode +1876:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1877:Generated_Source\PSoC4/CyLib.c **** * +1878:Generated_Source\PSoC4/CyLib.c **** * Gets the bypass mode for the specified PLL. +1879:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 47 + + +1880:Generated_Source\PSoC4/CyLib.c **** * +1881:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +1882:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1883:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1884:Generated_Source\PSoC4/CyLib.c **** * +1885:Generated_Source\PSoC4/CyLib.c **** * \param bypass: Bypass mode. +1886:Generated_Source\PSoC4/CyLib.c **** * The same as the parameter of the CySysClkPllSetBypassMode(). +1887:Generated_Source\PSoC4/CyLib.c **** * +1888:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1889:Generated_Source\PSoC4/CyLib.c **** static uint32 CySysClkPllGetBypassMode(uint32 pll) +1890:Generated_Source\PSoC4/CyLib.c **** { +1891:Generated_Source\PSoC4/CyLib.c **** uint32 returnValue; +1892:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1893:Generated_Source\PSoC4/CyLib.c **** +1894:Generated_Source\PSoC4/CyLib.c **** CYASSERT(pll < CY_IP_PLL_NR); +1895:Generated_Source\PSoC4/CyLib.c **** +1896:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1897:Generated_Source\PSoC4/CyLib.c **** +1898:Generated_Source\PSoC4/CyLib.c **** returnValue = CY_SYS_CLK_PLL_BASE.pll[pll].config & CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK; +1899:Generated_Source\PSoC4/CyLib.c **** returnValue = returnValue >> CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT; +1900:Generated_Source\PSoC4/CyLib.c **** +1901:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1902:Generated_Source\PSoC4/CyLib.c **** +1903:Generated_Source\PSoC4/CyLib.c **** return (returnValue); +1904:Generated_Source\PSoC4/CyLib.c **** } +1905:Generated_Source\PSoC4/CyLib.c **** +1906:Generated_Source\PSoC4/CyLib.c **** +1907:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1908:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllConfigChangeAllowed +1909:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1910:Generated_Source\PSoC4/CyLib.c **** * +1911:Generated_Source\PSoC4/CyLib.c **** * The function returns non-zero value if the specified PLL sources the System +1912:Generated_Source\PSoC4/CyLib.c **** * clock and the PLL is not in the bypass mode. +1913:Generated_Source\PSoC4/CyLib.c **** * +1914:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1915:Generated_Source\PSoC4/CyLib.c **** * +1916:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +1917:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1918:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1919:Generated_Source\PSoC4/CyLib.c **** * +1920:Generated_Source\PSoC4/CyLib.c **** * \return Non-zero value when the specified PLL sources the System clock and +1921:Generated_Source\PSoC4/CyLib.c **** * the PLL is not in the bypass mode. +1922:Generated_Source\PSoC4/CyLib.c **** * +1923:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1924:Generated_Source\PSoC4/CyLib.c **** static cystatus CySysClkPllConfigChangeAllowed(uint32 pll) +1925:Generated_Source\PSoC4/CyLib.c **** { +1926:Generated_Source\PSoC4/CyLib.c **** uint32 pllBypassMode; +1927:Generated_Source\PSoC4/CyLib.c **** uint32 sysclkSource; +1928:Generated_Source\PSoC4/CyLib.c **** cystatus returnValue = CYRET_INVALID_STATE; +1929:Generated_Source\PSoC4/CyLib.c **** +1930:Generated_Source\PSoC4/CyLib.c **** sysclkSource = CySysClkGetSysclkSource(); +1931:Generated_Source\PSoC4/CyLib.c **** pllBypassMode = CySysClkPllGetBypassMode(pll); +1932:Generated_Source\PSoC4/CyLib.c **** +1933:Generated_Source\PSoC4/CyLib.c **** if ((CY_SYS_PLL_BYPASS_PLL_REF == pllBypassMode) || +1934:Generated_Source\PSoC4/CyLib.c **** ((CY_SYS_CLK_HFCLK_PLL0 != sysclkSource) && (0u == pll)) +1935:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_SRSSV2) +1936:Generated_Source\PSoC4/CyLib.c **** || ((CY_SYS_CLK_HFCLK_PLL1 != sysclkSource) && (1u == pll)) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 48 + + +1937:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ +1938:Generated_Source\PSoC4/CyLib.c **** ) +1939:Generated_Source\PSoC4/CyLib.c **** { +1940:Generated_Source\PSoC4/CyLib.c **** returnValue = CYRET_SUCCESS; +1941:Generated_Source\PSoC4/CyLib.c **** } +1942:Generated_Source\PSoC4/CyLib.c **** +1943:Generated_Source\PSoC4/CyLib.c **** return (returnValue); +1944:Generated_Source\PSoC4/CyLib.c **** } +1945:Generated_Source\PSoC4/CyLib.c **** +1946:Generated_Source\PSoC4/CyLib.c **** +1947:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1948:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllGetUnlockStatus +1949:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1950:Generated_Source\PSoC4/CyLib.c **** * +1951:Generated_Source\PSoC4/CyLib.c **** * Returns a non-zero value if the specified PLL output was unlocked. +1952:Generated_Source\PSoC4/CyLib.c **** * The unlock status is an indicator that the PLL has lost a lock at least once +1953:Generated_Source\PSoC4/CyLib.c **** * during its operation. The unlock status is cleared once it is read using +1954:Generated_Source\PSoC4/CyLib.c **** * this API. +1955:Generated_Source\PSoC4/CyLib.c **** * +1956:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1957:Generated_Source\PSoC4/CyLib.c **** * +1958:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +1959:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1960:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1961:Generated_Source\PSoC4/CyLib.c **** * +1962:Generated_Source\PSoC4/CyLib.c **** * \return Non-zero value when the specified PLL was unlocked. +1963:Generated_Source\PSoC4/CyLib.c **** * +1964:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +1965:Generated_Source\PSoC4/CyLib.c **** uint32 CySysClkPllGetUnlockStatus(uint32 pll) +1966:Generated_Source\PSoC4/CyLib.c **** { +1967:Generated_Source\PSoC4/CyLib.c **** uint32 returnStatus = 0u; +1968:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +1969:Generated_Source\PSoC4/CyLib.c **** +1970:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +1971:Generated_Source\PSoC4/CyLib.c **** +1972:Generated_Source\PSoC4/CyLib.c **** returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].test & CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK +1973:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].test |= CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK; +1974:Generated_Source\PSoC4/CyLib.c **** +1975:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +1976:Generated_Source\PSoC4/CyLib.c **** +1977:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); +1978:Generated_Source\PSoC4/CyLib.c **** } +1979:Generated_Source\PSoC4/CyLib.c **** +1980:Generated_Source\PSoC4/CyLib.c **** +1981:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +1982:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllSetFrequency +1983:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +1984:Generated_Source\PSoC4/CyLib.c **** * +1985:Generated_Source\PSoC4/CyLib.c **** * Configures either PLL#0 or PLL#1 for the requested input/output frequencies. +1986:Generated_Source\PSoC4/CyLib.c **** * The input frequency is the frequency of the source to the PLL. The source is +1987:Generated_Source\PSoC4/CyLib.c **** * set using the CySysClkPllSetSource() function. +1988:Generated_Source\PSoC4/CyLib.c **** * +1989:Generated_Source\PSoC4/CyLib.c **** * The PLL must not be the system clock source when calling this function. The +1990:Generated_Source\PSoC4/CyLib.c **** * PLL output will glitch during this function call. +1991:Generated_Source\PSoC4/CyLib.c **** * +1992:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +1993:Generated_Source\PSoC4/CyLib.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 49 + + +1994:Generated_Source\PSoC4/CyLib.c **** * \param pll: +1995:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +1996:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +1997:Generated_Source\PSoC4/CyLib.c **** * +1998:Generated_Source\PSoC4/CyLib.c **** * \param inputFreq The reference frequency in KHz. The valid range is from 1000 to 49152 KHz. +1999:Generated_Source\PSoC4/CyLib.c **** * +2000:Generated_Source\PSoC4/CyLib.c **** * \param pllFreq The target frequency in KHz. The valid range is from 22500 to 49152 KHz. +2001:Generated_Source\PSoC4/CyLib.c **** * +2002:Generated_Source\PSoC4/CyLib.c **** * \param divider The output clock divider for the PLL: +2003:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIVPASS Pass Through +2004:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 +2005:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 +2006:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 +2007:Generated_Source\PSoC4/CyLib.c **** * +2008:Generated_Source\PSoC4/CyLib.c **** * \param freqTol The tolerance in ppm, 10 ppm is equal to 0.001%. +2009:Generated_Source\PSoC4/CyLib.c **** * +2010:Generated_Source\PSoC4/CyLib.c **** * \return CYRET_SUCCESS The PLL was successfully configured for the requested +2011:Generated_Source\PSoC4/CyLib.c **** * frequency. +2012:Generated_Source\PSoC4/CyLib.c **** * +2013:Generated_Source\PSoC4/CyLib.c **** * \return CYRET_BAD_PARAM The PLL was not able to successfully configure for the +2014:Generated_Source\PSoC4/CyLib.c **** * requested frequency. +2015:Generated_Source\PSoC4/CyLib.c **** * +2016:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2017:Generated_Source\PSoC4/CyLib.c **** cystatus CySysClkPllSetFrequency(uint32 pll, uint32 inputFreq, uint32 pllFreq, uint32 divider, +2018:Generated_Source\PSoC4/CyLib.c **** { +2019:Generated_Source\PSoC4/CyLib.c **** uint32 qMin; +2020:Generated_Source\PSoC4/CyLib.c **** uint32 qMax; +2021:Generated_Source\PSoC4/CyLib.c **** +2022:Generated_Source\PSoC4/CyLib.c **** uint32 qVal = CY_SYS_CLK_PLL_INVALID; +2023:Generated_Source\PSoC4/CyLib.c **** uint32 pVal = CY_SYS_CLK_PLL_INVALID; +2024:Generated_Source\PSoC4/CyLib.c **** +2025:Generated_Source\PSoC4/CyLib.c **** uint32 q; +2026:Generated_Source\PSoC4/CyLib.c **** uint32 p; +2027:Generated_Source\PSoC4/CyLib.c **** +2028:Generated_Source\PSoC4/CyLib.c **** uint32 fvco; +2029:Generated_Source\PSoC4/CyLib.c **** int32 ferr; +2030:Generated_Source\PSoC4/CyLib.c **** +2031:Generated_Source\PSoC4/CyLib.c **** cystatus tmp; +2032:Generated_Source\PSoC4/CyLib.c **** cystatus returnStatus = CYRET_BAD_PARAM; +2033:Generated_Source\PSoC4/CyLib.c **** +2034:Generated_Source\PSoC4/CyLib.c **** +2035:Generated_Source\PSoC4/CyLib.c **** tmp = CySysClkPllConfigChangeAllowed(pll); +2036:Generated_Source\PSoC4/CyLib.c **** +2037:Generated_Source\PSoC4/CyLib.c **** if ((pll < CY_IP_PLL_NR) && +2038:Generated_Source\PSoC4/CyLib.c **** (inputFreq >= CY_SYS_CLK_PLL_INPUT_FREQ_MIN ) && (inputFreq <= CY_SYS_CLK_PLL_INPUT_ +2039:Generated_Source\PSoC4/CyLib.c **** (pllFreq >= CY_SYS_CLK_PLL_OUTPUT_FREQ_MIN ) && (pllFreq <= CY_SYS_CLK_PLL_OUTPUT_FREQ_ +2040:Generated_Source\PSoC4/CyLib.c **** (divider <= CY_SYS_PLL_OUTPUT_DIV8) && +2041:Generated_Source\PSoC4/CyLib.c **** (CYRET_SUCCESS == tmp)) +2042:Generated_Source\PSoC4/CyLib.c **** { +2043:Generated_Source\PSoC4/CyLib.c **** +2044:Generated_Source\PSoC4/CyLib.c **** /* Minimum feed forward loop divisor */ +2045:Generated_Source\PSoC4/CyLib.c **** qMin = (inputFreq + (CY_SYS_CLK_PLL_FPFDMAX - 1u)) / CY_SYS_CLK_PLL_FPFDMAX; +2046:Generated_Source\PSoC4/CyLib.c **** qMin = (qMin < CY_SYS_CLK_PLL_QMINIP) ? CY_SYS_CLK_PLL_QMINIP : qMin; +2047:Generated_Source\PSoC4/CyLib.c **** +2048:Generated_Source\PSoC4/CyLib.c **** /* Maximum feed forward loop divisor */ +2049:Generated_Source\PSoC4/CyLib.c **** qMax = inputFreq / CY_SYS_CLK_PLL_FPFDMIN; +2050:Generated_Source\PSoC4/CyLib.c **** qMax = (qMax > CY_SYS_CLK_PLL_QMAXIP) ? CY_SYS_CLK_PLL_QMAXIP : qMax; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 50 + + +2051:Generated_Source\PSoC4/CyLib.c **** +2052:Generated_Source\PSoC4/CyLib.c **** if (qMin <= qMax) +2053:Generated_Source\PSoC4/CyLib.c **** { +2054:Generated_Source\PSoC4/CyLib.c **** for(q = qMin; q <= qMax; q++) +2055:Generated_Source\PSoC4/CyLib.c **** { +2056:Generated_Source\PSoC4/CyLib.c **** /* Solve for the feedback divisor value */ +2057:Generated_Source\PSoC4/CyLib.c **** +2058:Generated_Source\PSoC4/CyLib.c **** /* INT((pllFreq * q ) / inputFreq), where INT is normal rounding */ +2059:Generated_Source\PSoC4/CyLib.c **** p = ((pllFreq * q) + (inputFreq / 2u)) / inputFreq; +2060:Generated_Source\PSoC4/CyLib.c **** +2061:Generated_Source\PSoC4/CyLib.c **** /* Calculate the actual VCO frequency (FVCO) */ +2062:Generated_Source\PSoC4/CyLib.c **** fvco = ((inputFreq * p) / q); +2063:Generated_Source\PSoC4/CyLib.c **** +2064:Generated_Source\PSoC4/CyLib.c **** /* Calculate the frequency error (FERR) */ +2065:Generated_Source\PSoC4/CyLib.c **** ferr = ((1000000 * ((int32) fvco - (int32) pllFreq))/ (int32) pllFreq); +2066:Generated_Source\PSoC4/CyLib.c **** +2067:Generated_Source\PSoC4/CyLib.c **** /* Bound check the frequency error and decide next action */ +2068:Generated_Source\PSoC4/CyLib.c **** if ((( -1 * (int32) freqTol) <= ferr) && (ferr <= (int32) freqTol)) +2069:Generated_Source\PSoC4/CyLib.c **** { +2070:Generated_Source\PSoC4/CyLib.c **** qVal = q; +2071:Generated_Source\PSoC4/CyLib.c **** pVal = p; +2072:Generated_Source\PSoC4/CyLib.c **** break; +2073:Generated_Source\PSoC4/CyLib.c **** } +2074:Generated_Source\PSoC4/CyLib.c **** } +2075:Generated_Source\PSoC4/CyLib.c **** +2076:Generated_Source\PSoC4/CyLib.c **** +2077:Generated_Source\PSoC4/CyLib.c **** if ((pVal != CY_SYS_CLK_PLL_INVALID) && (qVal != CY_SYS_CLK_PLL_INVALID)) +2078:Generated_Source\PSoC4/CyLib.c **** { +2079:Generated_Source\PSoC4/CyLib.c **** if (CySysClkPllSetPQ(pll, pVal, qVal, CY_SYS_CLK_PLL_CURRENT_DEFAULT) == CYRET_ +2080:Generated_Source\PSoC4/CyLib.c **** { +2081:Generated_Source\PSoC4/CyLib.c **** returnStatus = CySysClkPllSetOutputDivider(pll, divider); +2082:Generated_Source\PSoC4/CyLib.c **** } +2083:Generated_Source\PSoC4/CyLib.c **** } +2084:Generated_Source\PSoC4/CyLib.c **** } +2085:Generated_Source\PSoC4/CyLib.c **** +2086:Generated_Source\PSoC4/CyLib.c **** } +2087:Generated_Source\PSoC4/CyLib.c **** +2088:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); +2089:Generated_Source\PSoC4/CyLib.c **** } +2090:Generated_Source\PSoC4/CyLib.c **** +2091:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2092:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllSetSource +2093:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2094:Generated_Source\PSoC4/CyLib.c **** * +2095:Generated_Source\PSoC4/CyLib.c **** * Sets the input clock source to the PLL. The PLL must be disabled before +2096:Generated_Source\PSoC4/CyLib.c **** * calling this function. +2097:Generated_Source\PSoC4/CyLib.c **** * +2098:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +2099:Generated_Source\PSoC4/CyLib.c **** * +2100:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +2101:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +2102:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +2103:Generated_Source\PSoC4/CyLib.c **** * +2104:Generated_Source\PSoC4/CyLib.c **** * \param source: +2105:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_SOURCE_IMO IMO +2106:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_SOURCE_EXTCLK External Clock (available only for PSoC 4200L) +2107:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_SOURCE_ECO ECO + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 51 + + +2108:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_SOURCE_DSI0 DSI_OUT[0] (available only for PSoC 4200L) +2109:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_SOURCE_DSI1 DSI_OUT[1] (available only for PSoC 4200L) +2110:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_SOURCE_DSI2 DSI_OUT[2] (available only for PSoC 4200L) +2111:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_SOURCE_DSI3 DSI_OUT[3] (available only for PSoC 4200L) +2112:Generated_Source\PSoC4/CyLib.c **** * +2113:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2114:Generated_Source\PSoC4/CyLib.c **** void CySysClkPllSetSource(uint32 pll, uint32 source) +2115:Generated_Source\PSoC4/CyLib.c **** { +2116:Generated_Source\PSoC4/CyLib.c **** uint32 regTmp; +2117:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +2118:Generated_Source\PSoC4/CyLib.c **** +2119:Generated_Source\PSoC4/CyLib.c **** #if (CY_IP_SRSSLT) +2120:Generated_Source\PSoC4/CyLib.c **** uint8 i = 0u; +2121:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSLT) */ +2122:Generated_Source\PSoC4/CyLib.c **** +2123:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +2124:Generated_Source\PSoC4/CyLib.c **** +2125:Generated_Source\PSoC4/CyLib.c **** if (pll < CY_IP_PLL_NR) +2126:Generated_Source\PSoC4/CyLib.c **** { +2127:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) +2128:Generated_Source\PSoC4/CyLib.c **** regTmp = CY_SYS_CLK_SELECT_REG & (uint32) ~CY_SYS_CLK_SELECT_PLL_MASK(pll); +2129:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((source << CY_SYS_CLK_SELECT_PLL_SHIFT(pll)) & CY_SYS_CLK_SELECT_PLL_MAS +2130:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_SELECT_REG = regTmp; +2131:Generated_Source\PSoC4/CyLib.c **** #else +2132:Generated_Source\PSoC4/CyLib.c **** regTmp = CY_SYS_ECO_CLK_SELECT_REG & (uint32) ~CY_SYS_ECO_CLK_SELECT_PLL0_MASK; +2133:Generated_Source\PSoC4/CyLib.c **** regTmp |= ((source << CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT) & CY_SYS_ECO_CLK_SELECT_PLL +2134:Generated_Source\PSoC4/CyLib.c **** CY_SYS_ECO_CLK_SELECT_REG = regTmp; +2135:Generated_Source\PSoC4/CyLib.c **** +2136:Generated_Source\PSoC4/CyLib.c **** /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ +2137:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; +2138:Generated_Source\PSoC4/CyLib.c **** +2139:Generated_Source\PSoC4/CyLib.c **** for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) +2140:Generated_Source\PSoC4/CyLib.c **** { +2141:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; +2142:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; +2143:Generated_Source\PSoC4/CyLib.c **** } +2144:Generated_Source\PSoC4/CyLib.c **** +2145:Generated_Source\PSoC4/CyLib.c **** CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; +2146:Generated_Source\PSoC4/CyLib.c **** +2147:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ +2148:Generated_Source\PSoC4/CyLib.c **** } +2149:Generated_Source\PSoC4/CyLib.c **** +2150:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +2151:Generated_Source\PSoC4/CyLib.c **** } +2152:Generated_Source\PSoC4/CyLib.c **** +2153:Generated_Source\PSoC4/CyLib.c **** +2154:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2155:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysClkPllSetOutputDivider +2156:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2157:Generated_Source\PSoC4/CyLib.c **** * +2158:Generated_Source\PSoC4/CyLib.c **** * Sets the output clock divider for the PLL. +2159:Generated_Source\PSoC4/CyLib.c **** * +2160:Generated_Source\PSoC4/CyLib.c **** * The PLL must not be the System Clock source when calling this function. The +2161:Generated_Source\PSoC4/CyLib.c **** * PLL output will glitch during this function call. +2162:Generated_Source\PSoC4/CyLib.c **** * +2163:Generated_Source\PSoC4/CyLib.c **** * This API is available only for PSoC 4200L / 4100S with PLL devices. +2164:Generated_Source\PSoC4/CyLib.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 52 + + +2165:Generated_Source\PSoC4/CyLib.c **** * \param PLL: +2166:Generated_Source\PSoC4/CyLib.c **** * 0 PLL#0 +2167:Generated_Source\PSoC4/CyLib.c **** * 1 PLL#1 (available only for PSoC 4200L) +2168:Generated_Source\PSoC4/CyLib.c **** * +2169:Generated_Source\PSoC4/CyLib.c **** * \param divider: +2170:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIVPASS Pass through +2171:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 +2172:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 +2173:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 +2174:Generated_Source\PSoC4/CyLib.c **** * +2175:Generated_Source\PSoC4/CyLib.c **** * \return \ref CYRET_SUCCESS Completed successfully. +2176:Generated_Source\PSoC4/CyLib.c **** * \return \ref CYRET_BAD_PARAM The parameters are out of range or the +2177:Generated_Source\PSoC4/CyLib.c **** * specified PLL sources the System clock. +2178:Generated_Source\PSoC4/CyLib.c **** * +2179:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2180:Generated_Source\PSoC4/CyLib.c **** cystatus CySysClkPllSetOutputDivider(uint32 pll, uint32 divider) +2181:Generated_Source\PSoC4/CyLib.c **** { +2182:Generated_Source\PSoC4/CyLib.c **** uint32 tmpReg; +2183:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +2184:Generated_Source\PSoC4/CyLib.c **** cystatus returnStatus = CYRET_BAD_PARAM; +2185:Generated_Source\PSoC4/CyLib.c **** cystatus tmp; +2186:Generated_Source\PSoC4/CyLib.c **** +2187:Generated_Source\PSoC4/CyLib.c **** +2188:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); +2189:Generated_Source\PSoC4/CyLib.c **** +2190:Generated_Source\PSoC4/CyLib.c **** tmp = CySysClkPllConfigChangeAllowed(pll); +2191:Generated_Source\PSoC4/CyLib.c **** +2192:Generated_Source\PSoC4/CyLib.c **** if ((pll < CY_IP_PLL_NR) && (CYRET_SUCCESS == tmp) && (divider <= CY_SYS_PLL_OUTPUT_DIV8)) +2193:Generated_Source\PSoC4/CyLib.c **** { +2194:Generated_Source\PSoC4/CyLib.c **** tmpReg = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_OUTPUT +2195:Generated_Source\PSoC4/CyLib.c **** tmpReg |= ((divider << CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_ +2196:Generated_Source\PSoC4/CyLib.c **** +2197:Generated_Source\PSoC4/CyLib.c **** CY_SYS_CLK_PLL_BASE.pll[pll].config = tmpReg; +2198:Generated_Source\PSoC4/CyLib.c **** +2199:Generated_Source\PSoC4/CyLib.c **** returnStatus = CYRET_SUCCESS; +2200:Generated_Source\PSoC4/CyLib.c **** } +2201:Generated_Source\PSoC4/CyLib.c **** +2202:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); +2203:Generated_Source\PSoC4/CyLib.c **** +2204:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); +2205:Generated_Source\PSoC4/CyLib.c **** } +2206:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_PLL) */ +2207:Generated_Source\PSoC4/CyLib.c **** +2208:Generated_Source\PSoC4/CyLib.c **** +2209:Generated_Source\PSoC4/CyLib.c **** #if(CY_IP_SRSSV2) +2210:Generated_Source\PSoC4/CyLib.c **** +2211:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2212:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysLvdEnable +2213:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2214:Generated_Source\PSoC4/CyLib.c **** * +2215:Generated_Source\PSoC4/CyLib.c **** * Enables the output of the low-voltage monitor when Vddd is at or below the +2216:Generated_Source\PSoC4/CyLib.c **** * trip point, configures the device to generate an interrupt, and sets the +2217:Generated_Source\PSoC4/CyLib.c **** * voltage trip level. +2218:Generated_Source\PSoC4/CyLib.c **** * +2219:Generated_Source\PSoC4/CyLib.c **** * \param threshold: Threshold selection for Low Voltage Detect circuit. +2220:Generated_Source\PSoC4/CyLib.c **** * Threshold variation is +/- 2.5% from these typical voltage choices. +2221:Generated_Source\PSoC4/CyLib.c **** * Define Voltage threshold + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 53 + + +2222:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_1_75_V 1.7500 V +2223:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_1_80_V 1.8000 V +2224:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_1_90_V 1.9000 V +2225:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_00_V 2.0000 V +2226:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_10_V 2.1000 V +2227:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_20_V 2.2000 V +2228:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_30_V 2.3000 V +2229:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_40_V 2.4000 V +2230:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_50_V 2.5000 V +2231:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_60_V 2.6000 V +2232:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_70_V 2.7000 V +2233:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_80_V 2.8000 V +2234:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_2_90_V 2.9000 V +2235:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_3_00_V 3.0000 V +2236:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_3_20_V 3.2000 V +2237:Generated_Source\PSoC4/CyLib.c **** * CY_LVD_THRESHOLD_4_50_V 4.5000 V +2238:Generated_Source\PSoC4/CyLib.c **** * +2239:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2240:Generated_Source\PSoC4/CyLib.c **** void CySysLvdEnable(uint32 threshold) +2241:Generated_Source\PSoC4/CyLib.c **** { + 735 .loc 1 2241 0 + 736 .cfi_startproc + 737 @ args = 0, pretend = 0, frame = 8 + 738 @ frame_needed = 1, uses_anonymous_args = 0 + 739 0000 80B5 push {r7, lr} + 740 .cfi_def_cfa_offset 8 + 741 .cfi_offset 7, -8 + 742 .cfi_offset 14, -4 + 743 0002 82B0 sub sp, sp, #8 + 744 .cfi_def_cfa_offset 16 + 745 0004 00AF add r7, sp, #0 + 746 .cfi_def_cfa_register 7 + 747 0006 7860 str r0, [r7, #4] +2242:Generated_Source\PSoC4/CyLib.c **** /* Prevent propagating a false interrupt */ +2243:Generated_Source\PSoC4/CyLib.c **** CY_LVD_PWR_INTR_MASK_REG &= (uint32) ~CY_LVD_PROPAGATE_INT_TO_CPU; + 748 .loc 1 2243 0 + 749 0008 144B ldr r3, .L38 + 750 000a 144A ldr r2, .L38 + 751 000c 1268 ldr r2, [r2] + 752 000e 0221 movs r1, #2 + 753 0010 8A43 bics r2, r1 + 754 0012 1A60 str r2, [r3] +2244:Generated_Source\PSoC4/CyLib.c **** +2245:Generated_Source\PSoC4/CyLib.c **** /* Set specified threshold */ +2246:Generated_Source\PSoC4/CyLib.c **** CY_LVD_PWR_VMON_CONFIG_REG = (CY_LVD_PWR_VMON_CONFIG_REG & ~CY_LVD_PWR_VMON_CONFIG_LVD_SEL_ + 755 .loc 1 2246 0 + 756 0014 124B ldr r3, .L38+4 + 757 0016 124A ldr r2, .L38+4 + 758 0018 1268 ldr r2, [r2] + 759 001a 1E21 movs r1, #30 + 760 001c 8A43 bics r2, r1 + 761 001e 1100 movs r1, r2 +2247:Generated_Source\PSoC4/CyLib.c **** ((threshold << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT) & CY_LVD_PWR_VMON_CONFIG_LVD_S + 762 .loc 1 2247 0 + 763 0020 7A68 ldr r2, [r7, #4] + 764 0022 5200 lsls r2, r2, #1 + 765 0024 1E20 movs r0, #30 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 54 + + + 766 0026 0240 ands r2, r0 +2246:Generated_Source\PSoC4/CyLib.c **** ((threshold << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT) & CY_LVD_PWR_VMON_CONFIG_LVD_S + 767 .loc 1 2246 0 + 768 0028 0A43 orrs r2, r1 + 769 002a 1A60 str r2, [r3] +2248:Generated_Source\PSoC4/CyLib.c **** +2249:Generated_Source\PSoC4/CyLib.c **** /* Enable the LVD. This may cause a false LVD event. */ +2250:Generated_Source\PSoC4/CyLib.c **** CY_LVD_PWR_VMON_CONFIG_REG |= CY_LVD_PWR_VMON_CONFIG_LVD_EN; + 770 .loc 1 2250 0 + 771 002c 0C4B ldr r3, .L38+4 + 772 002e 0C4A ldr r2, .L38+4 + 773 0030 1268 ldr r2, [r2] + 774 0032 0121 movs r1, #1 + 775 0034 0A43 orrs r2, r1 + 776 0036 1A60 str r2, [r3] +2251:Generated_Source\PSoC4/CyLib.c **** +2252:Generated_Source\PSoC4/CyLib.c **** /* Wait for the circuit to stabilize */ +2253:Generated_Source\PSoC4/CyLib.c **** CyDelayUs(CY_LVD_STABILIZE_TIMEOUT_US); + 777 .loc 1 2253 0 + 778 0038 FA23 movs r3, #250 + 779 003a 9B00 lsls r3, r3, #2 + 780 003c 1800 movs r0, r3 + 781 003e FFF7FEFF bl CyDelayUs +2254:Generated_Source\PSoC4/CyLib.c **** +2255:Generated_Source\PSoC4/CyLib.c **** /* Clear the false event */ +2256:Generated_Source\PSoC4/CyLib.c **** CySysLvdClearInterrupt(); + 782 .loc 1 2256 0 + 783 0042 FFF7FEFF bl CySysLvdClearInterrupt +2257:Generated_Source\PSoC4/CyLib.c **** +2258:Generated_Source\PSoC4/CyLib.c **** /* Unmask the interrupt */ +2259:Generated_Source\PSoC4/CyLib.c **** CY_LVD_PWR_INTR_MASK_REG |= CY_LVD_PROPAGATE_INT_TO_CPU; + 784 .loc 1 2259 0 + 785 0046 054B ldr r3, .L38 + 786 0048 044A ldr r2, .L38 + 787 004a 1268 ldr r2, [r2] + 788 004c 0221 movs r1, #2 + 789 004e 0A43 orrs r2, r1 + 790 0050 1A60 str r2, [r3] +2260:Generated_Source\PSoC4/CyLib.c **** } + 791 .loc 1 2260 0 + 792 0052 C046 nop + 793 0054 BD46 mov sp, r7 + 794 0056 02B0 add sp, sp, #8 + 795 @ sp needed + 796 0058 80BD pop {r7, pc} + 797 .L39: + 798 005a C046 .align 2 + 799 .L38: + 800 005c 08000B40 .word 1074462728 + 801 0060 18000B40 .word 1074462744 + 802 .cfi_endproc + 803 .LFE7: + 804 .size CySysLvdEnable, .-CySysLvdEnable + 805 .section .text.CySysLvdDisable,"ax",%progbits + 806 .align 2 + 807 .global CySysLvdDisable + 808 .code 16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 55 + + + 809 .thumb_func + 810 .type CySysLvdDisable, %function + 811 CySysLvdDisable: + 812 .LFB8: +2261:Generated_Source\PSoC4/CyLib.c **** +2262:Generated_Source\PSoC4/CyLib.c **** +2263:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2264:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysLvdDisable +2265:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2266:Generated_Source\PSoC4/CyLib.c **** * +2267:Generated_Source\PSoC4/CyLib.c **** * Disables the low voltage detection. A low voltage interrupt is disabled. +2268:Generated_Source\PSoC4/CyLib.c **** * +2269:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2270:Generated_Source\PSoC4/CyLib.c **** void CySysLvdDisable(void) +2271:Generated_Source\PSoC4/CyLib.c **** { + 813 .loc 1 2271 0 + 814 .cfi_startproc + 815 @ args = 0, pretend = 0, frame = 0 + 816 @ frame_needed = 1, uses_anonymous_args = 0 + 817 0000 80B5 push {r7, lr} + 818 .cfi_def_cfa_offset 8 + 819 .cfi_offset 7, -8 + 820 .cfi_offset 14, -4 + 821 0002 00AF add r7, sp, #0 + 822 .cfi_def_cfa_register 7 +2272:Generated_Source\PSoC4/CyLib.c **** CY_LVD_PWR_INTR_MASK_REG &= ~CY_LVD_PROPAGATE_INT_TO_CPU; + 823 .loc 1 2272 0 + 824 0004 074B ldr r3, .L41 + 825 0006 074A ldr r2, .L41 + 826 0008 1268 ldr r2, [r2] + 827 000a 0221 movs r1, #2 + 828 000c 8A43 bics r2, r1 + 829 000e 1A60 str r2, [r3] +2273:Generated_Source\PSoC4/CyLib.c **** CY_LVD_PWR_VMON_CONFIG_REG &= ~CY_LVD_PWR_VMON_CONFIG_LVD_EN; + 830 .loc 1 2273 0 + 831 0010 054B ldr r3, .L41+4 + 832 0012 054A ldr r2, .L41+4 + 833 0014 1268 ldr r2, [r2] + 834 0016 0121 movs r1, #1 + 835 0018 8A43 bics r2, r1 + 836 001a 1A60 str r2, [r3] +2274:Generated_Source\PSoC4/CyLib.c **** } + 837 .loc 1 2274 0 + 838 001c C046 nop + 839 001e BD46 mov sp, r7 + 840 @ sp needed + 841 0020 80BD pop {r7, pc} + 842 .L42: + 843 0022 C046 .align 2 + 844 .L41: + 845 0024 08000B40 .word 1074462728 + 846 0028 18000B40 .word 1074462744 + 847 .cfi_endproc + 848 .LFE8: + 849 .size CySysLvdDisable, .-CySysLvdDisable + 850 .section .text.CySysLvdGetInterruptSource,"ax",%progbits + 851 .align 2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 56 + + + 852 .global CySysLvdGetInterruptSource + 853 .code 16 + 854 .thumb_func + 855 .type CySysLvdGetInterruptSource, %function + 856 CySysLvdGetInterruptSource: + 857 .LFB9: +2275:Generated_Source\PSoC4/CyLib.c **** +2276:Generated_Source\PSoC4/CyLib.c **** +2277:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2278:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysLvdGetInterruptSource +2279:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2280:Generated_Source\PSoC4/CyLib.c **** * +2281:Generated_Source\PSoC4/CyLib.c **** * Gets the low voltage detection interrupt status (without clearing). +2282:Generated_Source\PSoC4/CyLib.c **** * +2283:Generated_Source\PSoC4/CyLib.c **** * \return +2284:Generated_Source\PSoC4/CyLib.c **** * Interrupt request value: +2285:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_LVD_INT - Indicates an Low Voltage Detect interrupt +2286:Generated_Source\PSoC4/CyLib.c **** * +2287:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2288:Generated_Source\PSoC4/CyLib.c **** uint32 CySysLvdGetInterruptSource(void) +2289:Generated_Source\PSoC4/CyLib.c **** { + 858 .loc 1 2289 0 + 859 .cfi_startproc + 860 @ args = 0, pretend = 0, frame = 0 + 861 @ frame_needed = 1, uses_anonymous_args = 0 + 862 0000 80B5 push {r7, lr} + 863 .cfi_def_cfa_offset 8 + 864 .cfi_offset 7, -8 + 865 .cfi_offset 14, -4 + 866 0002 00AF add r7, sp, #0 + 867 .cfi_def_cfa_register 7 +2290:Generated_Source\PSoC4/CyLib.c **** return (CY_LVD_PWR_INTR_REG & CY_SYS_LVD_INT); + 868 .loc 1 2290 0 + 869 0004 034B ldr r3, .L45 + 870 0006 1B68 ldr r3, [r3] + 871 0008 0222 movs r2, #2 + 872 000a 1340 ands r3, r2 +2291:Generated_Source\PSoC4/CyLib.c **** } + 873 .loc 1 2291 0 + 874 000c 1800 movs r0, r3 + 875 000e BD46 mov sp, r7 + 876 @ sp needed + 877 0010 80BD pop {r7, pc} + 878 .L46: + 879 0012 C046 .align 2 + 880 .L45: + 881 0014 04000B40 .word 1074462724 + 882 .cfi_endproc + 883 .LFE9: + 884 .size CySysLvdGetInterruptSource, .-CySysLvdGetInterruptSource + 885 .section .text.CySysLvdClearInterrupt,"ax",%progbits + 886 .align 2 + 887 .global CySysLvdClearInterrupt + 888 .code 16 + 889 .thumb_func + 890 .type CySysLvdClearInterrupt, %function + 891 CySysLvdClearInterrupt: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 57 + + + 892 .LFB10: +2292:Generated_Source\PSoC4/CyLib.c **** +2293:Generated_Source\PSoC4/CyLib.c **** +2294:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2295:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysLvdClearInterrupt +2296:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2297:Generated_Source\PSoC4/CyLib.c **** * +2298:Generated_Source\PSoC4/CyLib.c **** * Clears the low voltage detection interrupt status. +2299:Generated_Source\PSoC4/CyLib.c **** * +2300:Generated_Source\PSoC4/CyLib.c **** * \return +2301:Generated_Source\PSoC4/CyLib.c **** * None +2302:Generated_Source\PSoC4/CyLib.c **** * +2303:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2304:Generated_Source\PSoC4/CyLib.c **** void CySysLvdClearInterrupt(void) +2305:Generated_Source\PSoC4/CyLib.c **** { + 893 .loc 1 2305 0 + 894 .cfi_startproc + 895 @ args = 0, pretend = 0, frame = 0 + 896 @ frame_needed = 1, uses_anonymous_args = 0 + 897 0000 80B5 push {r7, lr} + 898 .cfi_def_cfa_offset 8 + 899 .cfi_offset 7, -8 + 900 .cfi_offset 14, -4 + 901 0002 00AF add r7, sp, #0 + 902 .cfi_def_cfa_register 7 +2306:Generated_Source\PSoC4/CyLib.c **** CY_LVD_PWR_INTR_REG = CY_SYS_LVD_INT; + 903 .loc 1 2306 0 + 904 0004 024B ldr r3, .L48 + 905 0006 0222 movs r2, #2 + 906 0008 1A60 str r2, [r3] +2307:Generated_Source\PSoC4/CyLib.c **** } + 907 .loc 1 2307 0 + 908 000a C046 nop + 909 000c BD46 mov sp, r7 + 910 @ sp needed + 911 000e 80BD pop {r7, pc} + 912 .L49: + 913 .align 2 + 914 .L48: + 915 0010 04000B40 .word 1074462724 + 916 .cfi_endproc + 917 .LFE10: + 918 .size CySysLvdClearInterrupt, .-CySysLvdClearInterrupt + 919 .section .text.CySysGetResetReason,"ax",%progbits + 920 .align 2 + 921 .global CySysGetResetReason + 922 .code 16 + 923 .thumb_func + 924 .type CySysGetResetReason, %function + 925 CySysGetResetReason: + 926 .LFB11: +2308:Generated_Source\PSoC4/CyLib.c **** +2309:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_IP_SRSSV2) */ +2310:Generated_Source\PSoC4/CyLib.c **** +2311:Generated_Source\PSoC4/CyLib.c **** +2312:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2313:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysGetResetReason + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 58 + + +2314:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2315:Generated_Source\PSoC4/CyLib.c **** * +2316:Generated_Source\PSoC4/CyLib.c **** * Reports the cause for the latest reset(s) that occurred in the system. All +2317:Generated_Source\PSoC4/CyLib.c **** * the bits in the RES_CAUSE register assert when the corresponding reset cause +2318:Generated_Source\PSoC4/CyLib.c **** * occurs and must be cleared by the firmware. These bits are cleared by the +2319:Generated_Source\PSoC4/CyLib.c **** * hardware only during XRES, POR, or a detected brown-out. +2320:Generated_Source\PSoC4/CyLib.c **** * +2321:Generated_Source\PSoC4/CyLib.c **** * \param reason: bits in the RES_CAUSE register to clear. +2322:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_RESET_WDT - WDT caused a reset +2323:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_RESET_PROTFAULT - Occured protection violation that requires reset +2324:Generated_Source\PSoC4/CyLib.c **** * CY_SYS_RESET_SW - Cortex-M0 requested a system reset. +2325:Generated_Source\PSoC4/CyLib.c **** * +2326:Generated_Source\PSoC4/CyLib.c **** * \return +2327:Generated_Source\PSoC4/CyLib.c **** * Status. Same enumerated bit values as used for the reason parameter. +2328:Generated_Source\PSoC4/CyLib.c **** * +2329:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2330:Generated_Source\PSoC4/CyLib.c **** uint32 CySysGetResetReason(uint32 reason) +2331:Generated_Source\PSoC4/CyLib.c **** { + 927 .loc 1 2331 0 + 928 .cfi_startproc + 929 @ args = 0, pretend = 0, frame = 16 + 930 @ frame_needed = 1, uses_anonymous_args = 0 + 931 0000 80B5 push {r7, lr} + 932 .cfi_def_cfa_offset 8 + 933 .cfi_offset 7, -8 + 934 .cfi_offset 14, -4 + 935 0002 84B0 sub sp, sp, #16 + 936 .cfi_def_cfa_offset 24 + 937 0004 00AF add r7, sp, #0 + 938 .cfi_def_cfa_register 7 + 939 0006 7860 str r0, [r7, #4] +2332:Generated_Source\PSoC4/CyLib.c **** uint32 returnStatus; +2333:Generated_Source\PSoC4/CyLib.c **** +2334:Generated_Source\PSoC4/CyLib.c **** reason &= (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); + 940 .loc 1 2334 0 + 941 0008 7B68 ldr r3, [r7, #4] + 942 000a 1922 movs r2, #25 + 943 000c 1340 ands r3, r2 + 944 000e 7B60 str r3, [r7, #4] +2335:Generated_Source\PSoC4/CyLib.c **** returnStatus = CY_SYS_RES_CAUSE_REG & + 945 .loc 1 2335 0 + 946 0010 064B ldr r3, .L52 + 947 0012 1B68 ldr r3, [r3] + 948 0014 1922 movs r2, #25 + 949 0016 1340 ands r3, r2 + 950 0018 FB60 str r3, [r7, #12] +2336:Generated_Source\PSoC4/CyLib.c **** (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); +2337:Generated_Source\PSoC4/CyLib.c **** CY_SYS_RES_CAUSE_REG = reason; + 951 .loc 1 2337 0 + 952 001a 044B ldr r3, .L52 + 953 001c 7A68 ldr r2, [r7, #4] + 954 001e 1A60 str r2, [r3] +2338:Generated_Source\PSoC4/CyLib.c **** +2339:Generated_Source\PSoC4/CyLib.c **** return (returnStatus); + 955 .loc 1 2339 0 + 956 0020 FB68 ldr r3, [r7, #12] +2340:Generated_Source\PSoC4/CyLib.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 59 + + + 957 .loc 1 2340 0 + 958 0022 1800 movs r0, r3 + 959 0024 BD46 mov sp, r7 + 960 0026 04B0 add sp, sp, #16 + 961 @ sp needed + 962 0028 80BD pop {r7, pc} + 963 .L53: + 964 002a C046 .align 2 + 965 .L52: + 966 002c 00030B40 .word 1074463488 + 967 .cfi_endproc + 968 .LFE11: + 969 .size CySysGetResetReason, .-CySysGetResetReason + 970 .section .text.CyDisableInts,"ax",%progbits + 971 .align 2 + 972 .global CyDisableInts + 973 .code 16 + 974 .thumb_func + 975 .type CyDisableInts, %function + 976 CyDisableInts: + 977 .LFB12: +2341:Generated_Source\PSoC4/CyLib.c **** +2342:Generated_Source\PSoC4/CyLib.c **** +2343:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2344:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyDisableInts +2345:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2346:Generated_Source\PSoC4/CyLib.c **** * +2347:Generated_Source\PSoC4/CyLib.c **** * Disables all interrupts. +2348:Generated_Source\PSoC4/CyLib.c **** * +2349:Generated_Source\PSoC4/CyLib.c **** * \return +2350:Generated_Source\PSoC4/CyLib.c **** * 32 bit mask of previously enabled interrupts. +2351:Generated_Source\PSoC4/CyLib.c **** * +2352:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2353:Generated_Source\PSoC4/CyLib.c **** uint32 CyDisableInts(void) +2354:Generated_Source\PSoC4/CyLib.c **** { + 978 .loc 1 2354 0 + 979 .cfi_startproc + 980 @ args = 0, pretend = 0, frame = 8 + 981 @ frame_needed = 1, uses_anonymous_args = 0 + 982 0000 80B5 push {r7, lr} + 983 .cfi_def_cfa_offset 8 + 984 .cfi_offset 7, -8 + 985 .cfi_offset 14, -4 + 986 0002 82B0 sub sp, sp, #8 + 987 .cfi_def_cfa_offset 16 + 988 0004 00AF add r7, sp, #0 + 989 .cfi_def_cfa_register 7 +2355:Generated_Source\PSoC4/CyLib.c **** uint32 intState; +2356:Generated_Source\PSoC4/CyLib.c **** +2357:Generated_Source\PSoC4/CyLib.c **** /* Get current interrupt state. */ +2358:Generated_Source\PSoC4/CyLib.c **** intState = CY_INT_CLEAR_REG; + 990 .loc 1 2358 0 + 991 0006 064B ldr r3, .L56 + 992 0008 1B68 ldr r3, [r3] + 993 000a 7B60 str r3, [r7, #4] +2359:Generated_Source\PSoC4/CyLib.c **** +2360:Generated_Source\PSoC4/CyLib.c **** /* Disable all interrupts. */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 60 + + +2361:Generated_Source\PSoC4/CyLib.c **** CY_INT_CLEAR_REG = CY_INT_CLEAR_DISABLE_ALL; + 994 .loc 1 2361 0 + 995 000c 044B ldr r3, .L56 + 996 000e 0122 movs r2, #1 + 997 0010 5242 rsbs r2, r2, #0 + 998 0012 1A60 str r2, [r3] +2362:Generated_Source\PSoC4/CyLib.c **** +2363:Generated_Source\PSoC4/CyLib.c **** return (intState); + 999 .loc 1 2363 0 + 1000 0014 7B68 ldr r3, [r7, #4] +2364:Generated_Source\PSoC4/CyLib.c **** } + 1001 .loc 1 2364 0 + 1002 0016 1800 movs r0, r3 + 1003 0018 BD46 mov sp, r7 + 1004 001a 02B0 add sp, sp, #8 + 1005 @ sp needed + 1006 001c 80BD pop {r7, pc} + 1007 .L57: + 1008 001e C046 .align 2 + 1009 .L56: + 1010 0020 80E100E0 .word -536813184 + 1011 .cfi_endproc + 1012 .LFE12: + 1013 .size CyDisableInts, .-CyDisableInts + 1014 .section .text.CyEnableInts,"ax",%progbits + 1015 .align 2 + 1016 .global CyEnableInts + 1017 .code 16 + 1018 .thumb_func + 1019 .type CyEnableInts, %function + 1020 CyEnableInts: + 1021 .LFB13: +2365:Generated_Source\PSoC4/CyLib.c **** +2366:Generated_Source\PSoC4/CyLib.c **** +2367:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2368:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyEnableInts +2369:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2370:Generated_Source\PSoC4/CyLib.c **** * +2371:Generated_Source\PSoC4/CyLib.c **** * Enables interrupts to a given state. +2372:Generated_Source\PSoC4/CyLib.c **** * +2373:Generated_Source\PSoC4/CyLib.c **** * \param mask The 32 bit mask of interrupts to enable. +2374:Generated_Source\PSoC4/CyLib.c **** * +2375:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2376:Generated_Source\PSoC4/CyLib.c **** void CyEnableInts(uint32 mask) +2377:Generated_Source\PSoC4/CyLib.c **** { + 1022 .loc 1 2377 0 + 1023 .cfi_startproc + 1024 @ args = 0, pretend = 0, frame = 8 + 1025 @ frame_needed = 1, uses_anonymous_args = 0 + 1026 0000 80B5 push {r7, lr} + 1027 .cfi_def_cfa_offset 8 + 1028 .cfi_offset 7, -8 + 1029 .cfi_offset 14, -4 + 1030 0002 82B0 sub sp, sp, #8 + 1031 .cfi_def_cfa_offset 16 + 1032 0004 00AF add r7, sp, #0 + 1033 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 61 + + + 1034 0006 7860 str r0, [r7, #4] +2378:Generated_Source\PSoC4/CyLib.c **** CY_INT_ENABLE_REG = mask; + 1035 .loc 1 2378 0 + 1036 0008 034B ldr r3, .L59 + 1037 000a 7A68 ldr r2, [r7, #4] + 1038 000c 1A60 str r2, [r3] +2379:Generated_Source\PSoC4/CyLib.c **** } + 1039 .loc 1 2379 0 + 1040 000e C046 nop + 1041 0010 BD46 mov sp, r7 + 1042 0012 02B0 add sp, sp, #8 + 1043 @ sp needed + 1044 0014 80BD pop {r7, pc} + 1045 .L60: + 1046 0016 C046 .align 2 + 1047 .L59: + 1048 0018 00E100E0 .word -536813312 + 1049 .cfi_endproc + 1050 .LFE13: + 1051 .size CyEnableInts, .-CyEnableInts + 1052 .section .text.CyIntSetSysVector,"ax",%progbits + 1053 .align 2 + 1054 .global CyIntSetSysVector + 1055 .code 16 + 1056 .thumb_func + 1057 .type CyIntSetSysVector, %function + 1058 CyIntSetSysVector: + 1059 .LFB14: +2380:Generated_Source\PSoC4/CyLib.c **** +2381:Generated_Source\PSoC4/CyLib.c **** +2382:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2383:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntSetSysVector +2384:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2385:Generated_Source\PSoC4/CyLib.c **** * +2386:Generated_Source\PSoC4/CyLib.c **** * Sets the interrupt vector of the specified system interrupt number. These +2387:Generated_Source\PSoC4/CyLib.c **** * interrupts are for SysTick, PendSV and others. +2388:Generated_Source\PSoC4/CyLib.c **** * +2389:Generated_Source\PSoC4/CyLib.c **** * \param number: System interrupt number: +2390:Generated_Source\PSoC4/CyLib.c **** * CY_INT_NMI_IRQN - Non Maskable Interrupt +2391:Generated_Source\PSoC4/CyLib.c **** * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +2392:Generated_Source\PSoC4/CyLib.c **** * CY_INT_SVCALL_IRQN - SV Call Interrupt +2393:Generated_Source\PSoC4/CyLib.c **** * CY_INT_PEND_SV_IRQN - Pend SV Interrupt +2394:Generated_Source\PSoC4/CyLib.c **** * CY_INT_SYSTICK_IRQN - System Tick Interrupt +2395:Generated_Source\PSoC4/CyLib.c **** * +2396:Generated_Source\PSoC4/CyLib.c **** * \param address Pointer to an interrupt service routine. +2397:Generated_Source\PSoC4/CyLib.c **** * +2398:Generated_Source\PSoC4/CyLib.c **** * \return The old ISR vector at this location. +2399:Generated_Source\PSoC4/CyLib.c **** * +2400:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2401:Generated_Source\PSoC4/CyLib.c **** cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) +2402:Generated_Source\PSoC4/CyLib.c **** { + 1060 .loc 1 2402 0 + 1061 .cfi_startproc + 1062 @ args = 0, pretend = 0, frame = 16 + 1063 @ frame_needed = 1, uses_anonymous_args = 0 + 1064 0000 80B5 push {r7, lr} + 1065 .cfi_def_cfa_offset 8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 62 + + + 1066 .cfi_offset 7, -8 + 1067 .cfi_offset 14, -4 + 1068 0002 84B0 sub sp, sp, #16 + 1069 .cfi_def_cfa_offset 24 + 1070 0004 00AF add r7, sp, #0 + 1071 .cfi_def_cfa_register 7 + 1072 0006 0200 movs r2, r0 + 1073 0008 3960 str r1, [r7] + 1074 000a FB1D adds r3, r7, #7 + 1075 000c 1A70 strb r2, [r3] +2403:Generated_Source\PSoC4/CyLib.c **** cyisraddress oldIsr; +2404:Generated_Source\PSoC4/CyLib.c **** cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + 1076 .loc 1 2404 0 + 1077 000e 8023 movs r3, #128 + 1078 0010 9B05 lsls r3, r3, #22 + 1079 0012 FB60 str r3, [r7, #12] +2405:Generated_Source\PSoC4/CyLib.c **** +2406:Generated_Source\PSoC4/CyLib.c **** CYASSERT(number < CY_INT_IRQ_BASE); + 1080 .loc 1 2406 0 + 1081 0014 FB1D adds r3, r7, #7 + 1082 0016 1B78 ldrb r3, [r3] + 1083 0018 0F2B cmp r3, #15 + 1084 001a 02D9 bls .L62 + 1085 .loc 1 2406 0 is_stmt 0 discriminator 1 + 1086 001c 0020 movs r0, #0 + 1087 001e FFF7FEFF bl CyHalt + 1088 .L62: +2407:Generated_Source\PSoC4/CyLib.c **** +2408:Generated_Source\PSoC4/CyLib.c **** /* Save old Interrupt service routine. */ +2409:Generated_Source\PSoC4/CyLib.c **** oldIsr = ramVectorTable[number]; + 1089 .loc 1 2409 0 is_stmt 1 + 1090 0022 FB1D adds r3, r7, #7 + 1091 0024 1B78 ldrb r3, [r3] + 1092 0026 9B00 lsls r3, r3, #2 + 1093 0028 FA68 ldr r2, [r7, #12] + 1094 002a D318 adds r3, r2, r3 + 1095 002c 1B68 ldr r3, [r3] + 1096 002e BB60 str r3, [r7, #8] +2410:Generated_Source\PSoC4/CyLib.c **** +2411:Generated_Source\PSoC4/CyLib.c **** /* Set new Interrupt service routine. */ +2412:Generated_Source\PSoC4/CyLib.c **** ramVectorTable[number] = address; + 1097 .loc 1 2412 0 + 1098 0030 FB1D adds r3, r7, #7 + 1099 0032 1B78 ldrb r3, [r3] + 1100 0034 9B00 lsls r3, r3, #2 + 1101 0036 FA68 ldr r2, [r7, #12] + 1102 0038 D318 adds r3, r2, r3 + 1103 003a 3A68 ldr r2, [r7] + 1104 003c 1A60 str r2, [r3] +2413:Generated_Source\PSoC4/CyLib.c **** +2414:Generated_Source\PSoC4/CyLib.c **** return(oldIsr); + 1105 .loc 1 2414 0 + 1106 003e BB68 ldr r3, [r7, #8] +2415:Generated_Source\PSoC4/CyLib.c **** } + 1107 .loc 1 2415 0 + 1108 0040 1800 movs r0, r3 + 1109 0042 BD46 mov sp, r7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 63 + + + 1110 0044 04B0 add sp, sp, #16 + 1111 @ sp needed + 1112 0046 80BD pop {r7, pc} + 1113 .cfi_endproc + 1114 .LFE14: + 1115 .size CyIntSetSysVector, .-CyIntSetSysVector + 1116 .section .text.CyIntGetSysVector,"ax",%progbits + 1117 .align 2 + 1118 .global CyIntGetSysVector + 1119 .code 16 + 1120 .thumb_func + 1121 .type CyIntGetSysVector, %function + 1122 CyIntGetSysVector: + 1123 .LFB15: +2416:Generated_Source\PSoC4/CyLib.c **** +2417:Generated_Source\PSoC4/CyLib.c **** +2418:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2419:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntGetSysVector +2420:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2421:Generated_Source\PSoC4/CyLib.c **** * +2422:Generated_Source\PSoC4/CyLib.c **** * Gets the interrupt vector of the specified system interrupt number. These +2423:Generated_Source\PSoC4/CyLib.c **** * interrupts are for SysTick, PendSV and others. +2424:Generated_Source\PSoC4/CyLib.c **** * +2425:Generated_Source\PSoC4/CyLib.c **** * \param number: System interrupt number: +2426:Generated_Source\PSoC4/CyLib.c **** * CY_INT_NMI_IRQN - Non Maskable Interrupt +2427:Generated_Source\PSoC4/CyLib.c **** * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +2428:Generated_Source\PSoC4/CyLib.c **** * CY_INT_SVCALL_IRQN - SV Call Interrupt +2429:Generated_Source\PSoC4/CyLib.c **** * CY_INT_PEND_SV_IRQN - Pend SV Interrupt +2430:Generated_Source\PSoC4/CyLib.c **** * CY_INT_SYSTICK_IRQN - System Tick Interrupt +2431:Generated_Source\PSoC4/CyLib.c **** * +2432:Generated_Source\PSoC4/CyLib.c **** * \return Address of the ISR in the interrupt vector table. +2433:Generated_Source\PSoC4/CyLib.c **** * +2434:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2435:Generated_Source\PSoC4/CyLib.c **** cyisraddress CyIntGetSysVector(uint8 number) +2436:Generated_Source\PSoC4/CyLib.c **** { + 1124 .loc 1 2436 0 + 1125 .cfi_startproc + 1126 @ args = 0, pretend = 0, frame = 16 + 1127 @ frame_needed = 1, uses_anonymous_args = 0 + 1128 0000 80B5 push {r7, lr} + 1129 .cfi_def_cfa_offset 8 + 1130 .cfi_offset 7, -8 + 1131 .cfi_offset 14, -4 + 1132 0002 84B0 sub sp, sp, #16 + 1133 .cfi_def_cfa_offset 24 + 1134 0004 00AF add r7, sp, #0 + 1135 .cfi_def_cfa_register 7 + 1136 0006 0200 movs r2, r0 + 1137 0008 FB1D adds r3, r7, #7 + 1138 000a 1A70 strb r2, [r3] +2437:Generated_Source\PSoC4/CyLib.c **** cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + 1139 .loc 1 2437 0 + 1140 000c 8023 movs r3, #128 + 1141 000e 9B05 lsls r3, r3, #22 + 1142 0010 FB60 str r3, [r7, #12] +2438:Generated_Source\PSoC4/CyLib.c **** +2439:Generated_Source\PSoC4/CyLib.c **** CYASSERT(number < CY_INT_IRQ_BASE); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 64 + + + 1143 .loc 1 2439 0 + 1144 0012 FB1D adds r3, r7, #7 + 1145 0014 1B78 ldrb r3, [r3] + 1146 0016 0F2B cmp r3, #15 + 1147 0018 02D9 bls .L65 + 1148 .loc 1 2439 0 is_stmt 0 discriminator 1 + 1149 001a 0020 movs r0, #0 + 1150 001c FFF7FEFF bl CyHalt + 1151 .L65: +2440:Generated_Source\PSoC4/CyLib.c **** +2441:Generated_Source\PSoC4/CyLib.c **** return(ramVectorTable[number]); + 1152 .loc 1 2441 0 is_stmt 1 + 1153 0020 FB1D adds r3, r7, #7 + 1154 0022 1B78 ldrb r3, [r3] + 1155 0024 9B00 lsls r3, r3, #2 + 1156 0026 FA68 ldr r2, [r7, #12] + 1157 0028 D318 adds r3, r2, r3 + 1158 002a 1B68 ldr r3, [r3] +2442:Generated_Source\PSoC4/CyLib.c **** } + 1159 .loc 1 2442 0 + 1160 002c 1800 movs r0, r3 + 1161 002e BD46 mov sp, r7 + 1162 0030 04B0 add sp, sp, #16 + 1163 @ sp needed + 1164 0032 80BD pop {r7, pc} + 1165 .cfi_endproc + 1166 .LFE15: + 1167 .size CyIntGetSysVector, .-CyIntGetSysVector + 1168 .section .text.CyIntSetVector,"ax",%progbits + 1169 .align 2 + 1170 .global CyIntSetVector + 1171 .code 16 + 1172 .thumb_func + 1173 .type CyIntSetVector, %function + 1174 CyIntSetVector: + 1175 .LFB16: +2443:Generated_Source\PSoC4/CyLib.c **** +2444:Generated_Source\PSoC4/CyLib.c **** +2445:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2446:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntSetVector +2447:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2448:Generated_Source\PSoC4/CyLib.c **** * +2449:Generated_Source\PSoC4/CyLib.c **** * Sets the interrupt vector of the specified interrupt number. +2450:Generated_Source\PSoC4/CyLib.c **** * +2451:Generated_Source\PSoC4/CyLib.c **** * \param number Valid range [0-31]. Interrupt number +2452:Generated_Source\PSoC4/CyLib.c **** * \param address Pointer to an interrupt service routine +2453:Generated_Source\PSoC4/CyLib.c **** * +2454:Generated_Source\PSoC4/CyLib.c **** * \return Previous interrupt vector value. +2455:Generated_Source\PSoC4/CyLib.c **** * +2456:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2457:Generated_Source\PSoC4/CyLib.c **** cyisraddress CyIntSetVector(uint8 number, cyisraddress address) +2458:Generated_Source\PSoC4/CyLib.c **** { + 1176 .loc 1 2458 0 + 1177 .cfi_startproc + 1178 @ args = 0, pretend = 0, frame = 16 + 1179 @ frame_needed = 1, uses_anonymous_args = 0 + 1180 0000 80B5 push {r7, lr} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 65 + + + 1181 .cfi_def_cfa_offset 8 + 1182 .cfi_offset 7, -8 + 1183 .cfi_offset 14, -4 + 1184 0002 84B0 sub sp, sp, #16 + 1185 .cfi_def_cfa_offset 24 + 1186 0004 00AF add r7, sp, #0 + 1187 .cfi_def_cfa_register 7 + 1188 0006 0200 movs r2, r0 + 1189 0008 3960 str r1, [r7] + 1190 000a FB1D adds r3, r7, #7 + 1191 000c 1A70 strb r2, [r3] +2459:Generated_Source\PSoC4/CyLib.c **** cyisraddress oldIsr; +2460:Generated_Source\PSoC4/CyLib.c **** cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + 1192 .loc 1 2460 0 + 1193 000e 8023 movs r3, #128 + 1194 0010 9B05 lsls r3, r3, #22 + 1195 0012 FB60 str r3, [r7, #12] +2461:Generated_Source\PSoC4/CyLib.c **** +2462:Generated_Source\PSoC4/CyLib.c **** CYASSERT(number < CY_NUM_INTERRUPTS); + 1196 .loc 1 2462 0 + 1197 0014 FB1D adds r3, r7, #7 + 1198 0016 1B78 ldrb r3, [r3] + 1199 0018 1F2B cmp r3, #31 + 1200 001a 02D9 bls .L68 + 1201 .loc 1 2462 0 is_stmt 0 discriminator 1 + 1202 001c 0020 movs r0, #0 + 1203 001e FFF7FEFF bl CyHalt + 1204 .L68: +2463:Generated_Source\PSoC4/CyLib.c **** +2464:Generated_Source\PSoC4/CyLib.c **** /* Save old Interrupt service routine. */ +2465:Generated_Source\PSoC4/CyLib.c **** oldIsr = ramVectorTable[CY_INT_IRQ_BASE + number]; + 1205 .loc 1 2465 0 is_stmt 1 + 1206 0022 FB1D adds r3, r7, #7 + 1207 0024 1B78 ldrb r3, [r3] + 1208 0026 1033 adds r3, r3, #16 + 1209 0028 9B00 lsls r3, r3, #2 + 1210 002a FA68 ldr r2, [r7, #12] + 1211 002c D318 adds r3, r2, r3 + 1212 002e 1B68 ldr r3, [r3] + 1213 0030 BB60 str r3, [r7, #8] +2466:Generated_Source\PSoC4/CyLib.c **** +2467:Generated_Source\PSoC4/CyLib.c **** /* Set new Interrupt service routine. */ +2468:Generated_Source\PSoC4/CyLib.c **** ramVectorTable[CY_INT_IRQ_BASE + number] = address; + 1214 .loc 1 2468 0 + 1215 0032 FB1D adds r3, r7, #7 + 1216 0034 1B78 ldrb r3, [r3] + 1217 0036 1033 adds r3, r3, #16 + 1218 0038 9B00 lsls r3, r3, #2 + 1219 003a FA68 ldr r2, [r7, #12] + 1220 003c D318 adds r3, r2, r3 + 1221 003e 3A68 ldr r2, [r7] + 1222 0040 1A60 str r2, [r3] +2469:Generated_Source\PSoC4/CyLib.c **** +2470:Generated_Source\PSoC4/CyLib.c **** return(oldIsr); + 1223 .loc 1 2470 0 + 1224 0042 BB68 ldr r3, [r7, #8] +2471:Generated_Source\PSoC4/CyLib.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 66 + + + 1225 .loc 1 2471 0 + 1226 0044 1800 movs r0, r3 + 1227 0046 BD46 mov sp, r7 + 1228 0048 04B0 add sp, sp, #16 + 1229 @ sp needed + 1230 004a 80BD pop {r7, pc} + 1231 .cfi_endproc + 1232 .LFE16: + 1233 .size CyIntSetVector, .-CyIntSetVector + 1234 .section .text.CyIntGetVector,"ax",%progbits + 1235 .align 2 + 1236 .global CyIntGetVector + 1237 .code 16 + 1238 .thumb_func + 1239 .type CyIntGetVector, %function + 1240 CyIntGetVector: + 1241 .LFB17: +2472:Generated_Source\PSoC4/CyLib.c **** +2473:Generated_Source\PSoC4/CyLib.c **** +2474:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2475:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntGetVector +2476:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2477:Generated_Source\PSoC4/CyLib.c **** * +2478:Generated_Source\PSoC4/CyLib.c **** * Gets the interrupt vector of the specified interrupt number. +2479:Generated_Source\PSoC4/CyLib.c **** * +2480:Generated_Source\PSoC4/CyLib.c **** * \param number: Valid range [0-31]. Interrupt number +2481:Generated_Source\PSoC4/CyLib.c **** * +2482:Generated_Source\PSoC4/CyLib.c **** * \return Address of the ISR in the interrupt vector table. +2483:Generated_Source\PSoC4/CyLib.c **** * +2484:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2485:Generated_Source\PSoC4/CyLib.c **** cyisraddress CyIntGetVector(uint8 number) +2486:Generated_Source\PSoC4/CyLib.c **** { + 1242 .loc 1 2486 0 + 1243 .cfi_startproc + 1244 @ args = 0, pretend = 0, frame = 16 + 1245 @ frame_needed = 1, uses_anonymous_args = 0 + 1246 0000 80B5 push {r7, lr} + 1247 .cfi_def_cfa_offset 8 + 1248 .cfi_offset 7, -8 + 1249 .cfi_offset 14, -4 + 1250 0002 84B0 sub sp, sp, #16 + 1251 .cfi_def_cfa_offset 24 + 1252 0004 00AF add r7, sp, #0 + 1253 .cfi_def_cfa_register 7 + 1254 0006 0200 movs r2, r0 + 1255 0008 FB1D adds r3, r7, #7 + 1256 000a 1A70 strb r2, [r3] +2487:Generated_Source\PSoC4/CyLib.c **** cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + 1257 .loc 1 2487 0 + 1258 000c 8023 movs r3, #128 + 1259 000e 9B05 lsls r3, r3, #22 + 1260 0010 FB60 str r3, [r7, #12] +2488:Generated_Source\PSoC4/CyLib.c **** +2489:Generated_Source\PSoC4/CyLib.c **** CYASSERT(number < CY_NUM_INTERRUPTS); + 1261 .loc 1 2489 0 + 1262 0012 FB1D adds r3, r7, #7 + 1263 0014 1B78 ldrb r3, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 67 + + + 1264 0016 1F2B cmp r3, #31 + 1265 0018 02D9 bls .L71 + 1266 .loc 1 2489 0 is_stmt 0 discriminator 1 + 1267 001a 0020 movs r0, #0 + 1268 001c FFF7FEFF bl CyHalt + 1269 .L71: +2490:Generated_Source\PSoC4/CyLib.c **** +2491:Generated_Source\PSoC4/CyLib.c **** return (ramVectorTable[CY_INT_IRQ_BASE + number]); + 1270 .loc 1 2491 0 is_stmt 1 + 1271 0020 FB1D adds r3, r7, #7 + 1272 0022 1B78 ldrb r3, [r3] + 1273 0024 1033 adds r3, r3, #16 + 1274 0026 9B00 lsls r3, r3, #2 + 1275 0028 FA68 ldr r2, [r7, #12] + 1276 002a D318 adds r3, r2, r3 + 1277 002c 1B68 ldr r3, [r3] +2492:Generated_Source\PSoC4/CyLib.c **** } + 1278 .loc 1 2492 0 + 1279 002e 1800 movs r0, r3 + 1280 0030 BD46 mov sp, r7 + 1281 0032 04B0 add sp, sp, #16 + 1282 @ sp needed + 1283 0034 80BD pop {r7, pc} + 1284 .cfi_endproc + 1285 .LFE17: + 1286 .size CyIntGetVector, .-CyIntGetVector + 1287 0036 C046 .section .text.CyIntSetPriority,"ax",%progbits + 1288 .align 2 + 1289 .global CyIntSetPriority + 1290 .code 16 + 1291 .thumb_func + 1292 .type CyIntSetPriority, %function + 1293 CyIntSetPriority: + 1294 .LFB18: +2493:Generated_Source\PSoC4/CyLib.c **** +2494:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2495:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntSetPriority +2496:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2497:Generated_Source\PSoC4/CyLib.c **** * +2498:Generated_Source\PSoC4/CyLib.c **** * Sets the priority of the interrupt. +2499:Generated_Source\PSoC4/CyLib.c **** * +2500:Generated_Source\PSoC4/CyLib.c **** * \param priority: Priority of the interrupt. 0 - 3, 0 being the highest. +2501:Generated_Source\PSoC4/CyLib.c **** * \param number: The number of the interrupt, 0 - 31. +2502:Generated_Source\PSoC4/CyLib.c **** * +2503:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2504:Generated_Source\PSoC4/CyLib.c **** void CyIntSetPriority(uint8 number, uint8 priority) +2505:Generated_Source\PSoC4/CyLib.c **** { + 1295 .loc 1 2505 0 + 1296 .cfi_startproc + 1297 @ args = 0, pretend = 0, frame = 24 + 1298 @ frame_needed = 1, uses_anonymous_args = 0 + 1299 0000 90B5 push {r4, r7, lr} + 1300 .cfi_def_cfa_offset 12 + 1301 .cfi_offset 4, -12 + 1302 .cfi_offset 7, -8 + 1303 .cfi_offset 14, -4 + 1304 0002 87B0 sub sp, sp, #28 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 68 + + + 1305 .cfi_def_cfa_offset 40 + 1306 0004 00AF add r7, sp, #0 + 1307 .cfi_def_cfa_register 7 + 1308 0006 0200 movs r2, r0 + 1309 0008 FB1D adds r3, r7, #7 + 1310 000a 1A70 strb r2, [r3] + 1311 000c BB1D adds r3, r7, #6 + 1312 000e 0A1C adds r2, r1, #0 + 1313 0010 1A70 strb r2, [r3] +2506:Generated_Source\PSoC4/CyLib.c **** uint8 interruptState; +2507:Generated_Source\PSoC4/CyLib.c **** uint32 shift; +2508:Generated_Source\PSoC4/CyLib.c **** uint32 value; +2509:Generated_Source\PSoC4/CyLib.c **** +2510:Generated_Source\PSoC4/CyLib.c **** CYASSERT(priority <= CY_MIN_PRIORITY); + 1314 .loc 1 2510 0 + 1315 0012 BB1D adds r3, r7, #6 + 1316 0014 1B78 ldrb r3, [r3] + 1317 0016 032B cmp r3, #3 + 1318 0018 02D9 bls .L74 + 1319 .loc 1 2510 0 is_stmt 0 discriminator 1 + 1320 001a 0020 movs r0, #0 + 1321 001c FFF7FEFF bl CyHalt + 1322 .L74: +2511:Generated_Source\PSoC4/CyLib.c **** CYASSERT(number < CY_NUM_INTERRUPTS); + 1323 .loc 1 2511 0 is_stmt 1 + 1324 0020 FB1D adds r3, r7, #7 + 1325 0022 1B78 ldrb r3, [r3] + 1326 0024 1F2B cmp r3, #31 + 1327 0026 02D9 bls .L75 + 1328 .loc 1 2511 0 is_stmt 0 discriminator 1 + 1329 0028 0020 movs r0, #0 + 1330 002a FFF7FEFF bl CyHalt + 1331 .L75: +2512:Generated_Source\PSoC4/CyLib.c **** +2513:Generated_Source\PSoC4/CyLib.c **** shift = CY_INT_PRIORITY_SHIFT(number); + 1332 .loc 1 2513 0 is_stmt 1 + 1333 002e FB1D adds r3, r7, #7 + 1334 0030 1B78 ldrb r3, [r3] + 1335 0032 0322 movs r2, #3 + 1336 0034 1340 ands r3, r2 + 1337 0036 DB00 lsls r3, r3, #3 + 1338 0038 0633 adds r3, r3, #6 + 1339 003a 7B61 str r3, [r7, #20] +2514:Generated_Source\PSoC4/CyLib.c **** +2515:Generated_Source\PSoC4/CyLib.c **** interruptState = CyEnterCriticalSection(); + 1340 .loc 1 2515 0 + 1341 003c 1323 movs r3, #19 + 1342 003e FC18 adds r4, r7, r3 + 1343 0040 FFF7FEFF bl CyEnterCriticalSection + 1344 0044 0300 movs r3, r0 + 1345 0046 2370 strb r3, [r4] +2516:Generated_Source\PSoC4/CyLib.c **** +2517:Generated_Source\PSoC4/CyLib.c **** value = CY_INT_PRIORITY_REG(number); + 1346 .loc 1 2517 0 + 1347 0048 FB1D adds r3, r7, #7 + 1348 004a 1B78 ldrb r3, [r3] + 1349 004c 9B08 lsrs r3, r3, #2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 69 + + + 1350 004e DBB2 uxtb r3, r3 + 1351 0050 9B00 lsls r3, r3, #2 + 1352 0052 144A ldr r2, .L76 + 1353 0054 9446 mov ip, r2 + 1354 0056 6344 add r3, r3, ip + 1355 0058 1B68 ldr r3, [r3] + 1356 005a FB60 str r3, [r7, #12] +2518:Generated_Source\PSoC4/CyLib.c **** value &= (uint32)(~((uint32)(CY_INT_PRIORITY_MASK << shift))); + 1357 .loc 1 2518 0 + 1358 005c 0322 movs r2, #3 + 1359 005e 7B69 ldr r3, [r7, #20] + 1360 0060 9A40 lsls r2, r2, r3 + 1361 0062 1300 movs r3, r2 + 1362 0064 DA43 mvns r2, r3 + 1363 0066 FB68 ldr r3, [r7, #12] + 1364 0068 1340 ands r3, r2 + 1365 006a FB60 str r3, [r7, #12] +2519:Generated_Source\PSoC4/CyLib.c **** value |= ((uint32)priority << shift); + 1366 .loc 1 2519 0 + 1367 006c BB1D adds r3, r7, #6 + 1368 006e 1A78 ldrb r2, [r3] + 1369 0070 7B69 ldr r3, [r7, #20] + 1370 0072 9A40 lsls r2, r2, r3 + 1371 0074 1300 movs r3, r2 + 1372 0076 FA68 ldr r2, [r7, #12] + 1373 0078 1343 orrs r3, r2 + 1374 007a FB60 str r3, [r7, #12] +2520:Generated_Source\PSoC4/CyLib.c **** CY_INT_PRIORITY_REG(number) = value; + 1375 .loc 1 2520 0 + 1376 007c FB1D adds r3, r7, #7 + 1377 007e 1B78 ldrb r3, [r3] + 1378 0080 9B08 lsrs r3, r3, #2 + 1379 0082 DBB2 uxtb r3, r3 + 1380 0084 9B00 lsls r3, r3, #2 + 1381 0086 074A ldr r2, .L76 + 1382 0088 9446 mov ip, r2 + 1383 008a 6344 add r3, r3, ip + 1384 008c FA68 ldr r2, [r7, #12] + 1385 008e 1A60 str r2, [r3] +2521:Generated_Source\PSoC4/CyLib.c **** +2522:Generated_Source\PSoC4/CyLib.c **** CyExitCriticalSection(interruptState); + 1386 .loc 1 2522 0 + 1387 0090 1323 movs r3, #19 + 1388 0092 FB18 adds r3, r7, r3 + 1389 0094 1B78 ldrb r3, [r3] + 1390 0096 1800 movs r0, r3 + 1391 0098 FFF7FEFF bl CyExitCriticalSection +2523:Generated_Source\PSoC4/CyLib.c **** } + 1392 .loc 1 2523 0 + 1393 009c C046 nop + 1394 009e BD46 mov sp, r7 + 1395 00a0 07B0 add sp, sp, #28 + 1396 @ sp needed + 1397 00a2 90BD pop {r4, r7, pc} + 1398 .L77: + 1399 .align 2 + 1400 .L76: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 70 + + + 1401 00a4 00E400E0 .word -536812544 + 1402 .cfi_endproc + 1403 .LFE18: + 1404 .size CyIntSetPriority, .-CyIntSetPriority + 1405 .section .text.CyIntGetPriority,"ax",%progbits + 1406 .align 2 + 1407 .global CyIntGetPriority + 1408 .code 16 + 1409 .thumb_func + 1410 .type CyIntGetPriority, %function + 1411 CyIntGetPriority: + 1412 .LFB19: +2524:Generated_Source\PSoC4/CyLib.c **** +2525:Generated_Source\PSoC4/CyLib.c **** +2526:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2527:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntGetPriority +2528:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2529:Generated_Source\PSoC4/CyLib.c **** * +2530:Generated_Source\PSoC4/CyLib.c **** * Gets the priority of the interrupt. +2531:Generated_Source\PSoC4/CyLib.c **** * +2532:Generated_Source\PSoC4/CyLib.c **** * \param number: The number of the interrupt, 0 - 31. +2533:Generated_Source\PSoC4/CyLib.c **** * +2534:Generated_Source\PSoC4/CyLib.c **** * \return +2535:Generated_Source\PSoC4/CyLib.c **** * Priority of the interrupt. 0 - 3, 0 being the highest. +2536:Generated_Source\PSoC4/CyLib.c **** * +2537:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2538:Generated_Source\PSoC4/CyLib.c **** uint8 CyIntGetPriority(uint8 number) +2539:Generated_Source\PSoC4/CyLib.c **** { + 1413 .loc 1 2539 0 + 1414 .cfi_startproc + 1415 @ args = 0, pretend = 0, frame = 16 + 1416 @ frame_needed = 1, uses_anonymous_args = 0 + 1417 0000 80B5 push {r7, lr} + 1418 .cfi_def_cfa_offset 8 + 1419 .cfi_offset 7, -8 + 1420 .cfi_offset 14, -4 + 1421 0002 84B0 sub sp, sp, #16 + 1422 .cfi_def_cfa_offset 24 + 1423 0004 00AF add r7, sp, #0 + 1424 .cfi_def_cfa_register 7 + 1425 0006 0200 movs r2, r0 + 1426 0008 FB1D adds r3, r7, #7 + 1427 000a 1A70 strb r2, [r3] +2540:Generated_Source\PSoC4/CyLib.c **** uint8 priority; +2541:Generated_Source\PSoC4/CyLib.c **** +2542:Generated_Source\PSoC4/CyLib.c **** CYASSERT(number < CY_NUM_INTERRUPTS); + 1428 .loc 1 2542 0 + 1429 000c FB1D adds r3, r7, #7 + 1430 000e 1B78 ldrb r3, [r3] + 1431 0010 1F2B cmp r3, #31 + 1432 0012 02D9 bls .L79 + 1433 .loc 1 2542 0 is_stmt 0 discriminator 1 + 1434 0014 0020 movs r0, #0 + 1435 0016 FFF7FEFF bl CyHalt + 1436 .L79: +2543:Generated_Source\PSoC4/CyLib.c **** +2544:Generated_Source\PSoC4/CyLib.c **** priority = (uint8) (CY_INT_PRIORITY_REG(number) >> CY_INT_PRIORITY_SHIFT(number)); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 71 + + + 1437 .loc 1 2544 0 is_stmt 1 + 1438 001a FB1D adds r3, r7, #7 + 1439 001c 1B78 ldrb r3, [r3] + 1440 001e 9B08 lsrs r3, r3, #2 + 1441 0020 DBB2 uxtb r3, r3 + 1442 0022 9B00 lsls r3, r3, #2 + 1443 0024 0B4A ldr r2, .L81 + 1444 0026 9446 mov ip, r2 + 1445 0028 6344 add r3, r3, ip + 1446 002a 1A68 ldr r2, [r3] + 1447 002c FB1D adds r3, r7, #7 + 1448 002e 1B78 ldrb r3, [r3] + 1449 0030 0321 movs r1, #3 + 1450 0032 0B40 ands r3, r1 + 1451 0034 DB00 lsls r3, r3, #3 + 1452 0036 0633 adds r3, r3, #6 + 1453 0038 DA40 lsrs r2, r2, r3 + 1454 003a 0F23 movs r3, #15 + 1455 003c FB18 adds r3, r7, r3 + 1456 003e 1A70 strb r2, [r3] +2545:Generated_Source\PSoC4/CyLib.c **** +2546:Generated_Source\PSoC4/CyLib.c **** return (priority & (uint8) CY_INT_PRIORITY_MASK); + 1457 .loc 1 2546 0 + 1458 0040 0F23 movs r3, #15 + 1459 0042 FB18 adds r3, r7, r3 + 1460 0044 1B78 ldrb r3, [r3] + 1461 0046 0322 movs r2, #3 + 1462 0048 1340 ands r3, r2 + 1463 004a DBB2 uxtb r3, r3 +2547:Generated_Source\PSoC4/CyLib.c **** } + 1464 .loc 1 2547 0 + 1465 004c 1800 movs r0, r3 + 1466 004e BD46 mov sp, r7 + 1467 0050 04B0 add sp, sp, #16 + 1468 @ sp needed + 1469 0052 80BD pop {r7, pc} + 1470 .L82: + 1471 .align 2 + 1472 .L81: + 1473 0054 00E400E0 .word -536812544 + 1474 .cfi_endproc + 1475 .LFE19: + 1476 .size CyIntGetPriority, .-CyIntGetPriority + 1477 .section .text.CyIntEnable,"ax",%progbits + 1478 .align 2 + 1479 .global CyIntEnable + 1480 .code 16 + 1481 .thumb_func + 1482 .type CyIntEnable, %function + 1483 CyIntEnable: + 1484 .LFB20: +2548:Generated_Source\PSoC4/CyLib.c **** +2549:Generated_Source\PSoC4/CyLib.c **** +2550:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2551:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntEnable +2552:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2553:Generated_Source\PSoC4/CyLib.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 72 + + +2554:Generated_Source\PSoC4/CyLib.c **** * Enables the specified interrupt number. +2555:Generated_Source\PSoC4/CyLib.c **** * +2556:Generated_Source\PSoC4/CyLib.c **** * \param number: Valid range [0-31]. Interrupt number +2557:Generated_Source\PSoC4/CyLib.c **** * +2558:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2559:Generated_Source\PSoC4/CyLib.c **** void CyIntEnable(uint8 number) +2560:Generated_Source\PSoC4/CyLib.c **** { + 1485 .loc 1 2560 0 + 1486 .cfi_startproc + 1487 @ args = 0, pretend = 0, frame = 8 + 1488 @ frame_needed = 1, uses_anonymous_args = 0 + 1489 0000 80B5 push {r7, lr} + 1490 .cfi_def_cfa_offset 8 + 1491 .cfi_offset 7, -8 + 1492 .cfi_offset 14, -4 + 1493 0002 82B0 sub sp, sp, #8 + 1494 .cfi_def_cfa_offset 16 + 1495 0004 00AF add r7, sp, #0 + 1496 .cfi_def_cfa_register 7 + 1497 0006 0200 movs r2, r0 + 1498 0008 FB1D adds r3, r7, #7 + 1499 000a 1A70 strb r2, [r3] +2561:Generated_Source\PSoC4/CyLib.c **** CY_INT_ENABLE_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); + 1500 .loc 1 2561 0 + 1501 000c 064B ldr r3, .L84 + 1502 000e FA1D adds r2, r7, #7 + 1503 0010 1278 ldrb r2, [r2] + 1504 0012 1F21 movs r1, #31 + 1505 0014 0A40 ands r2, r1 + 1506 0016 0121 movs r1, #1 + 1507 0018 9140 lsls r1, r1, r2 + 1508 001a 0A00 movs r2, r1 + 1509 001c 1A60 str r2, [r3] +2562:Generated_Source\PSoC4/CyLib.c **** } + 1510 .loc 1 2562 0 + 1511 001e C046 nop + 1512 0020 BD46 mov sp, r7 + 1513 0022 02B0 add sp, sp, #8 + 1514 @ sp needed + 1515 0024 80BD pop {r7, pc} + 1516 .L85: + 1517 0026 C046 .align 2 + 1518 .L84: + 1519 0028 00E100E0 .word -536813312 + 1520 .cfi_endproc + 1521 .LFE20: + 1522 .size CyIntEnable, .-CyIntEnable + 1523 .section .text.CyIntGetState,"ax",%progbits + 1524 .align 2 + 1525 .global CyIntGetState + 1526 .code 16 + 1527 .thumb_func + 1528 .type CyIntGetState, %function + 1529 CyIntGetState: + 1530 .LFB21: +2563:Generated_Source\PSoC4/CyLib.c **** +2564:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 73 + + +2565:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2566:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntGetState +2567:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2568:Generated_Source\PSoC4/CyLib.c **** * +2569:Generated_Source\PSoC4/CyLib.c **** * Gets the enable state of the specified interrupt number. +2570:Generated_Source\PSoC4/CyLib.c **** * +2571:Generated_Source\PSoC4/CyLib.c **** * \param number: Valid range [0-31]. Interrupt number. +2572:Generated_Source\PSoC4/CyLib.c **** * +2573:Generated_Source\PSoC4/CyLib.c **** * \return +2574:Generated_Source\PSoC4/CyLib.c **** * Enable status: 1 if enabled, 0 if disabled +2575:Generated_Source\PSoC4/CyLib.c **** * +2576:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2577:Generated_Source\PSoC4/CyLib.c **** uint8 CyIntGetState(uint8 number) +2578:Generated_Source\PSoC4/CyLib.c **** { + 1531 .loc 1 2578 0 + 1532 .cfi_startproc + 1533 @ args = 0, pretend = 0, frame = 8 + 1534 @ frame_needed = 1, uses_anonymous_args = 0 + 1535 0000 80B5 push {r7, lr} + 1536 .cfi_def_cfa_offset 8 + 1537 .cfi_offset 7, -8 + 1538 .cfi_offset 14, -4 + 1539 0002 82B0 sub sp, sp, #8 + 1540 .cfi_def_cfa_offset 16 + 1541 0004 00AF add r7, sp, #0 + 1542 .cfi_def_cfa_register 7 + 1543 0006 0200 movs r2, r0 + 1544 0008 FB1D adds r3, r7, #7 + 1545 000a 1A70 strb r2, [r3] +2579:Generated_Source\PSoC4/CyLib.c **** /* Get state of interrupt. */ +2580:Generated_Source\PSoC4/CyLib.c **** return ((0u != (CY_INT_ENABLE_REG & ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)))) ? + 1546 .loc 1 2580 0 + 1547 000c 074B ldr r3, .L88 + 1548 000e 1A68 ldr r2, [r3] + 1549 0010 FB1D adds r3, r7, #7 + 1550 0012 1B78 ldrb r3, [r3] + 1551 0014 1F21 movs r1, #31 + 1552 0016 0B40 ands r3, r1 + 1553 0018 DA40 lsrs r2, r2, r3 + 1554 001a 1300 movs r3, r2 + 1555 001c DBB2 uxtb r3, r3 + 1556 001e 0122 movs r2, #1 + 1557 0020 1340 ands r3, r2 + 1558 0022 DBB2 uxtb r3, r3 +2581:Generated_Source\PSoC4/CyLib.c **** } + 1559 .loc 1 2581 0 + 1560 0024 1800 movs r0, r3 + 1561 0026 BD46 mov sp, r7 + 1562 0028 02B0 add sp, sp, #8 + 1563 @ sp needed + 1564 002a 80BD pop {r7, pc} + 1565 .L89: + 1566 .align 2 + 1567 .L88: + 1568 002c 00E100E0 .word -536813312 + 1569 .cfi_endproc + 1570 .LFE21: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 74 + + + 1571 .size CyIntGetState, .-CyIntGetState + 1572 .section .text.CyIntDisable,"ax",%progbits + 1573 .align 2 + 1574 .global CyIntDisable + 1575 .code 16 + 1576 .thumb_func + 1577 .type CyIntDisable, %function + 1578 CyIntDisable: + 1579 .LFB22: +2582:Generated_Source\PSoC4/CyLib.c **** +2583:Generated_Source\PSoC4/CyLib.c **** +2584:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2585:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntDisable +2586:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2587:Generated_Source\PSoC4/CyLib.c **** * +2588:Generated_Source\PSoC4/CyLib.c **** * Disables the specified interrupt number. +2589:Generated_Source\PSoC4/CyLib.c **** * +2590:Generated_Source\PSoC4/CyLib.c **** * \param number: Valid range [0-31]. Interrupt number. +2591:Generated_Source\PSoC4/CyLib.c **** * +2592:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2593:Generated_Source\PSoC4/CyLib.c **** void CyIntDisable(uint8 number) +2594:Generated_Source\PSoC4/CyLib.c **** { + 1580 .loc 1 2594 0 + 1581 .cfi_startproc + 1582 @ args = 0, pretend = 0, frame = 8 + 1583 @ frame_needed = 1, uses_anonymous_args = 0 + 1584 0000 80B5 push {r7, lr} + 1585 .cfi_def_cfa_offset 8 + 1586 .cfi_offset 7, -8 + 1587 .cfi_offset 14, -4 + 1588 0002 82B0 sub sp, sp, #8 + 1589 .cfi_def_cfa_offset 16 + 1590 0004 00AF add r7, sp, #0 + 1591 .cfi_def_cfa_register 7 + 1592 0006 0200 movs r2, r0 + 1593 0008 FB1D adds r3, r7, #7 + 1594 000a 1A70 strb r2, [r3] +2595:Generated_Source\PSoC4/CyLib.c **** CY_INT_CLEAR_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); + 1595 .loc 1 2595 0 + 1596 000c 064B ldr r3, .L91 + 1597 000e FA1D adds r2, r7, #7 + 1598 0010 1278 ldrb r2, [r2] + 1599 0012 1F21 movs r1, #31 + 1600 0014 0A40 ands r2, r1 + 1601 0016 0121 movs r1, #1 + 1602 0018 9140 lsls r1, r1, r2 + 1603 001a 0A00 movs r2, r1 + 1604 001c 1A60 str r2, [r3] +2596:Generated_Source\PSoC4/CyLib.c **** } + 1605 .loc 1 2596 0 + 1606 001e C046 nop + 1607 0020 BD46 mov sp, r7 + 1608 0022 02B0 add sp, sp, #8 + 1609 @ sp needed + 1610 0024 80BD pop {r7, pc} + 1611 .L92: + 1612 0026 C046 .align 2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 75 + + + 1613 .L91: + 1614 0028 80E100E0 .word -536813184 + 1615 .cfi_endproc + 1616 .LFE22: + 1617 .size CyIntDisable, .-CyIntDisable + 1618 .section .text.CyIntSetPending,"ax",%progbits + 1619 .align 2 + 1620 .global CyIntSetPending + 1621 .code 16 + 1622 .thumb_func + 1623 .type CyIntSetPending, %function + 1624 CyIntSetPending: + 1625 .LFB23: +2597:Generated_Source\PSoC4/CyLib.c **** +2598:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2599:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntSetPending +2600:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2601:Generated_Source\PSoC4/CyLib.c **** * +2602:Generated_Source\PSoC4/CyLib.c **** * Forces the specified interrupt number to be pending. +2603:Generated_Source\PSoC4/CyLib.c **** * +2604:Generated_Source\PSoC4/CyLib.c **** * \param number: Valid range [0-31]. Interrupt number. +2605:Generated_Source\PSoC4/CyLib.c **** * +2606:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2607:Generated_Source\PSoC4/CyLib.c **** void CyIntSetPending(uint8 number) +2608:Generated_Source\PSoC4/CyLib.c **** { + 1626 .loc 1 2608 0 + 1627 .cfi_startproc + 1628 @ args = 0, pretend = 0, frame = 8 + 1629 @ frame_needed = 1, uses_anonymous_args = 0 + 1630 0000 80B5 push {r7, lr} + 1631 .cfi_def_cfa_offset 8 + 1632 .cfi_offset 7, -8 + 1633 .cfi_offset 14, -4 + 1634 0002 82B0 sub sp, sp, #8 + 1635 .cfi_def_cfa_offset 16 + 1636 0004 00AF add r7, sp, #0 + 1637 .cfi_def_cfa_register 7 + 1638 0006 0200 movs r2, r0 + 1639 0008 FB1D adds r3, r7, #7 + 1640 000a 1A70 strb r2, [r3] +2609:Generated_Source\PSoC4/CyLib.c **** CY_INT_SET_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); + 1641 .loc 1 2609 0 + 1642 000c 064B ldr r3, .L94 + 1643 000e FA1D adds r2, r7, #7 + 1644 0010 1278 ldrb r2, [r2] + 1645 0012 1F21 movs r1, #31 + 1646 0014 0A40 ands r2, r1 + 1647 0016 0121 movs r1, #1 + 1648 0018 9140 lsls r1, r1, r2 + 1649 001a 0A00 movs r2, r1 + 1650 001c 1A60 str r2, [r3] +2610:Generated_Source\PSoC4/CyLib.c **** } + 1651 .loc 1 2610 0 + 1652 001e C046 nop + 1653 0020 BD46 mov sp, r7 + 1654 0022 02B0 add sp, sp, #8 + 1655 @ sp needed + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 76 + + + 1656 0024 80BD pop {r7, pc} + 1657 .L95: + 1658 0026 C046 .align 2 + 1659 .L94: + 1660 0028 00E200E0 .word -536813056 + 1661 .cfi_endproc + 1662 .LFE23: + 1663 .size CyIntSetPending, .-CyIntSetPending + 1664 .section .text.CyIntClearPending,"ax",%progbits + 1665 .align 2 + 1666 .global CyIntClearPending + 1667 .code 16 + 1668 .thumb_func + 1669 .type CyIntClearPending, %function + 1670 CyIntClearPending: + 1671 .LFB24: +2611:Generated_Source\PSoC4/CyLib.c **** +2612:Generated_Source\PSoC4/CyLib.c **** +2613:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2614:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyIntClearPending +2615:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2616:Generated_Source\PSoC4/CyLib.c **** * +2617:Generated_Source\PSoC4/CyLib.c **** * Clears any pending interrupt for the specified interrupt number. +2618:Generated_Source\PSoC4/CyLib.c **** * +2619:Generated_Source\PSoC4/CyLib.c **** * \param number: Valid range [0-31]. Interrupt number. +2620:Generated_Source\PSoC4/CyLib.c **** * +2621:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2622:Generated_Source\PSoC4/CyLib.c **** void CyIntClearPending(uint8 number) +2623:Generated_Source\PSoC4/CyLib.c **** { + 1672 .loc 1 2623 0 + 1673 .cfi_startproc + 1674 @ args = 0, pretend = 0, frame = 8 + 1675 @ frame_needed = 1, uses_anonymous_args = 0 + 1676 0000 80B5 push {r7, lr} + 1677 .cfi_def_cfa_offset 8 + 1678 .cfi_offset 7, -8 + 1679 .cfi_offset 14, -4 + 1680 0002 82B0 sub sp, sp, #8 + 1681 .cfi_def_cfa_offset 16 + 1682 0004 00AF add r7, sp, #0 + 1683 .cfi_def_cfa_register 7 + 1684 0006 0200 movs r2, r0 + 1685 0008 FB1D adds r3, r7, #7 + 1686 000a 1A70 strb r2, [r3] +2624:Generated_Source\PSoC4/CyLib.c **** CY_INT_CLR_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); + 1687 .loc 1 2624 0 + 1688 000c 064B ldr r3, .L97 + 1689 000e FA1D adds r2, r7, #7 + 1690 0010 1278 ldrb r2, [r2] + 1691 0012 1F21 movs r1, #31 + 1692 0014 0A40 ands r2, r1 + 1693 0016 0121 movs r1, #1 + 1694 0018 9140 lsls r1, r1, r2 + 1695 001a 0A00 movs r2, r1 + 1696 001c 1A60 str r2, [r3] +2625:Generated_Source\PSoC4/CyLib.c **** } + 1697 .loc 1 2625 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 77 + + + 1698 001e C046 nop + 1699 0020 BD46 mov sp, r7 + 1700 0022 02B0 add sp, sp, #8 + 1701 @ sp needed + 1702 0024 80BD pop {r7, pc} + 1703 .L98: + 1704 0026 C046 .align 2 + 1705 .L97: + 1706 0028 80E200E0 .word -536812928 + 1707 .cfi_endproc + 1708 .LFE24: + 1709 .size CyIntClearPending, .-CyIntClearPending + 1710 .section .text.CyHalt,"ax",%progbits + 1711 .align 2 + 1712 .global CyHalt + 1713 .code 16 + 1714 .thumb_func + 1715 .type CyHalt, %function + 1716 CyHalt: + 1717 .LFB25: +2626:Generated_Source\PSoC4/CyLib.c **** +2627:Generated_Source\PSoC4/CyLib.c **** +2628:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2629:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyHalt +2630:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2631:Generated_Source\PSoC4/CyLib.c **** * +2632:Generated_Source\PSoC4/CyLib.c **** * Halts the CPU. +2633:Generated_Source\PSoC4/CyLib.c **** * +2634:Generated_Source\PSoC4/CyLib.c **** * \param reason: Value to be used during debugging. +2635:Generated_Source\PSoC4/CyLib.c **** * +2636:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2637:Generated_Source\PSoC4/CyLib.c **** void CyHalt(uint8 reason) +2638:Generated_Source\PSoC4/CyLib.c **** { + 1718 .loc 1 2638 0 + 1719 .cfi_startproc + 1720 @ args = 0, pretend = 0, frame = 8 + 1721 @ frame_needed = 1, uses_anonymous_args = 0 + 1722 0000 80B5 push {r7, lr} + 1723 .cfi_def_cfa_offset 8 + 1724 .cfi_offset 7, -8 + 1725 .cfi_offset 14, -4 + 1726 0002 82B0 sub sp, sp, #8 + 1727 .cfi_def_cfa_offset 16 + 1728 0004 00AF add r7, sp, #0 + 1729 .cfi_def_cfa_register 7 + 1730 0006 0200 movs r2, r0 + 1731 0008 FB1D adds r3, r7, #7 + 1732 000a 1A70 strb r2, [r3] +2639:Generated_Source\PSoC4/CyLib.c **** if(0u != reason) +2640:Generated_Source\PSoC4/CyLib.c **** { +2641:Generated_Source\PSoC4/CyLib.c **** /* To remove unreferenced local variable warning */ +2642:Generated_Source\PSoC4/CyLib.c **** } +2643:Generated_Source\PSoC4/CyLib.c **** +2644:Generated_Source\PSoC4/CyLib.c **** #if defined (__ARMCC_VERSION) +2645:Generated_Source\PSoC4/CyLib.c **** __breakpoint(0x0); +2646:Generated_Source\PSoC4/CyLib.c **** #elif defined(__GNUC__) || defined (__ICCARM__) +2647:Generated_Source\PSoC4/CyLib.c **** __asm(" bkpt 1"); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 78 + + + 1733 .loc 1 2647 0 + 1734 .syntax divided + 1735 @ 2647 "Generated_Source\PSoC4\CyLib.c" 1 + 1736 000c 01BE bkpt 1 + 1737 @ 0 "" 2 +2648:Generated_Source\PSoC4/CyLib.c **** #elif defined(__C51__) +2649:Generated_Source\PSoC4/CyLib.c **** CYDEV_HALT_CPU; +2650:Generated_Source\PSoC4/CyLib.c **** #endif /* (__ARMCC_VERSION) */ +2651:Generated_Source\PSoC4/CyLib.c **** } + 1738 .loc 1 2651 0 + 1739 .thumb + 1740 .syntax unified + 1741 000e C046 nop + 1742 0010 BD46 mov sp, r7 + 1743 0012 02B0 add sp, sp, #8 + 1744 @ sp needed + 1745 0014 80BD pop {r7, pc} + 1746 .cfi_endproc + 1747 .LFE25: + 1748 .size CyHalt, .-CyHalt + 1749 0016 C046 .section .text.CySoftwareReset,"ax",%progbits + 1750 .align 2 + 1751 .global CySoftwareReset + 1752 .code 16 + 1753 .thumb_func + 1754 .type CySoftwareReset, %function + 1755 CySoftwareReset: + 1756 .LFB26: +2652:Generated_Source\PSoC4/CyLib.c **** +2653:Generated_Source\PSoC4/CyLib.c **** +2654:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2655:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySoftwareReset +2656:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2657:Generated_Source\PSoC4/CyLib.c **** * +2658:Generated_Source\PSoC4/CyLib.c **** * Forces a software reset of the device. +2659:Generated_Source\PSoC4/CyLib.c **** * +2660:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2661:Generated_Source\PSoC4/CyLib.c **** void CySoftwareReset(void) +2662:Generated_Source\PSoC4/CyLib.c **** { + 1757 .loc 1 2662 0 + 1758 .cfi_startproc + 1759 @ args = 0, pretend = 0, frame = 0 + 1760 @ frame_needed = 1, uses_anonymous_args = 0 + 1761 0000 80B5 push {r7, lr} + 1762 .cfi_def_cfa_offset 8 + 1763 .cfi_offset 7, -8 + 1764 .cfi_offset 14, -4 + 1765 0002 00AF add r7, sp, #0 + 1766 .cfi_def_cfa_register 7 +2663:Generated_Source\PSoC4/CyLib.c **** /*************************************************************************** +2664:Generated_Source\PSoC4/CyLib.c **** * Setting the system reset request bit. The vector key value must be written +2665:Generated_Source\PSoC4/CyLib.c **** * to the register, otherwise the register write is unpredictable. +2666:Generated_Source\PSoC4/CyLib.c **** ***************************************************************************/ +2667:Generated_Source\PSoC4/CyLib.c **** CY_SYS_AIRCR_REG = (CY_SYS_AIRCR_REG & (uint32)(~CY_SYS_AIRCR_VECTKEY_MASK)) | + 1767 .loc 1 2667 0 + 1768 0004 054B ldr r3, .L101 + 1769 0006 054A ldr r2, .L101 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 79 + + + 1770 0008 1268 ldr r2, [r2] + 1771 000a 1204 lsls r2, r2, #16 + 1772 000c 120C lsrs r2, r2, #16 +2668:Generated_Source\PSoC4/CyLib.c **** CY_SYS_AIRCR_VECTKEY | CY_SYS_AIRCR_SYSRESETREQ; + 1773 .loc 1 2668 0 + 1774 000e 0449 ldr r1, .L101+4 + 1775 0010 0A43 orrs r2, r1 +2667:Generated_Source\PSoC4/CyLib.c **** CY_SYS_AIRCR_VECTKEY | CY_SYS_AIRCR_SYSRESETREQ; + 1776 .loc 1 2667 0 + 1777 0012 1A60 str r2, [r3] +2669:Generated_Source\PSoC4/CyLib.c **** } + 1778 .loc 1 2669 0 + 1779 0014 C046 nop + 1780 0016 BD46 mov sp, r7 + 1781 @ sp needed + 1782 0018 80BD pop {r7, pc} + 1783 .L102: + 1784 001a C046 .align 2 + 1785 .L101: + 1786 001c 0CED00E0 .word -536810228 + 1787 0020 0400FA05 .word 100270084 + 1788 .cfi_endproc + 1789 .LFE26: + 1790 .size CySoftwareReset, .-CySoftwareReset + 1791 .section .text.CyDelay,"ax",%progbits + 1792 .align 2 + 1793 .global CyDelay + 1794 .code 16 + 1795 .thumb_func + 1796 .type CyDelay, %function + 1797 CyDelay: + 1798 .LFB27: +2670:Generated_Source\PSoC4/CyLib.c **** +2671:Generated_Source\PSoC4/CyLib.c **** +2672:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2673:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyDelay +2674:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2675:Generated_Source\PSoC4/CyLib.c **** * +2676:Generated_Source\PSoC4/CyLib.c **** * Blocks for milliseconds. +2677:Generated_Source\PSoC4/CyLib.c **** * +2678:Generated_Source\PSoC4/CyLib.c **** * \param milliseconds: number of milliseconds to delay. +2679:Generated_Source\PSoC4/CyLib.c **** * +2680:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2681:Generated_Source\PSoC4/CyLib.c **** void CyDelay(uint32 milliseconds) +2682:Generated_Source\PSoC4/CyLib.c **** { + 1799 .loc 1 2682 0 + 1800 .cfi_startproc + 1801 @ args = 0, pretend = 0, frame = 8 + 1802 @ frame_needed = 1, uses_anonymous_args = 0 + 1803 0000 80B5 push {r7, lr} + 1804 .cfi_def_cfa_offset 8 + 1805 .cfi_offset 7, -8 + 1806 .cfi_offset 14, -4 + 1807 0002 82B0 sub sp, sp, #8 + 1808 .cfi_def_cfa_offset 16 + 1809 0004 00AF add r7, sp, #0 + 1810 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 80 + + + 1811 0006 7860 str r0, [r7, #4] +2683:Generated_Source\PSoC4/CyLib.c **** while (milliseconds > CY_DELAY_MS_OVERFLOW) + 1812 .loc 1 2683 0 + 1813 0008 09E0 b .L104 + 1814 .L105: +2684:Generated_Source\PSoC4/CyLib.c **** { +2685:Generated_Source\PSoC4/CyLib.c **** /* This loop prevents overflow. +2686:Generated_Source\PSoC4/CyLib.c **** * At 100MHz, milliseconds * cydelayFreqKhz overflows at about 42 seconds +2687:Generated_Source\PSoC4/CyLib.c **** */ +2688:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles(cydelay32kMs); + 1815 .loc 1 2688 0 + 1816 000a 0D4B ldr r3, .L106 + 1817 000c 1B68 ldr r3, [r3] + 1818 000e 1800 movs r0, r3 + 1819 0010 FFF7FEFF bl CyDelayCycles +2689:Generated_Source\PSoC4/CyLib.c **** milliseconds -= CY_DELAY_MS_OVERFLOW; + 1820 .loc 1 2689 0 + 1821 0014 7B68 ldr r3, [r7, #4] + 1822 0016 0B4A ldr r2, .L106+4 + 1823 0018 9446 mov ip, r2 + 1824 001a 6344 add r3, r3, ip + 1825 001c 7B60 str r3, [r7, #4] + 1826 .L104: +2683:Generated_Source\PSoC4/CyLib.c **** while (milliseconds > CY_DELAY_MS_OVERFLOW) + 1827 .loc 1 2683 0 + 1828 001e 7A68 ldr r2, [r7, #4] + 1829 0020 8023 movs r3, #128 + 1830 0022 1B02 lsls r3, r3, #8 + 1831 0024 9A42 cmp r2, r3 + 1832 0026 F0D8 bhi .L105 +2690:Generated_Source\PSoC4/CyLib.c **** } +2691:Generated_Source\PSoC4/CyLib.c **** +2692:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles(milliseconds * cydelayFreqKhz); + 1833 .loc 1 2692 0 + 1834 0028 074B ldr r3, .L106+8 + 1835 002a 1B68 ldr r3, [r3] + 1836 002c 7A68 ldr r2, [r7, #4] + 1837 002e 5343 muls r3, r2 + 1838 0030 1800 movs r0, r3 + 1839 0032 FFF7FEFF bl CyDelayCycles +2693:Generated_Source\PSoC4/CyLib.c **** } + 1840 .loc 1 2693 0 + 1841 0036 C046 nop + 1842 0038 BD46 mov sp, r7 + 1843 003a 02B0 add sp, sp, #8 + 1844 @ sp needed + 1845 003c 80BD pop {r7, pc} + 1846 .L107: + 1847 003e C046 .align 2 + 1848 .L106: + 1849 0040 00000000 .word cydelay32kMs + 1850 0044 0080FFFF .word -32768 + 1851 0048 00000000 .word cydelayFreqKhz + 1852 .cfi_endproc + 1853 .LFE27: + 1854 .size CyDelay, .-CyDelay + 1855 .section .text.CyDelayUs,"ax",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 81 + + + 1856 .align 2 + 1857 .global CyDelayUs + 1858 .code 16 + 1859 .thumb_func + 1860 .type CyDelayUs, %function + 1861 CyDelayUs: + 1862 .LFB28: +2694:Generated_Source\PSoC4/CyLib.c **** +2695:Generated_Source\PSoC4/CyLib.c **** +2696:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2697:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyDelayUs +2698:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2699:Generated_Source\PSoC4/CyLib.c **** * Blocks for microseconds. +2700:Generated_Source\PSoC4/CyLib.c **** * +2701:Generated_Source\PSoC4/CyLib.c **** * \param microseconds: number of microseconds to delay. +2702:Generated_Source\PSoC4/CyLib.c **** * +2703:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2704:Generated_Source\PSoC4/CyLib.c **** void CyDelayUs(uint16 microseconds) +2705:Generated_Source\PSoC4/CyLib.c **** { + 1863 .loc 1 2705 0 + 1864 .cfi_startproc + 1865 @ args = 0, pretend = 0, frame = 8 + 1866 @ frame_needed = 1, uses_anonymous_args = 0 + 1867 0000 80B5 push {r7, lr} + 1868 .cfi_def_cfa_offset 8 + 1869 .cfi_offset 7, -8 + 1870 .cfi_offset 14, -4 + 1871 0002 82B0 sub sp, sp, #8 + 1872 .cfi_def_cfa_offset 16 + 1873 0004 00AF add r7, sp, #0 + 1874 .cfi_def_cfa_register 7 + 1875 0006 0200 movs r2, r0 + 1876 0008 BB1D adds r3, r7, #6 + 1877 000a 1A80 strh r2, [r3] +2706:Generated_Source\PSoC4/CyLib.c **** CyDelayCycles((uint32)microseconds * cydelayFreqMhz); + 1878 .loc 1 2706 0 + 1879 000c BB1D adds r3, r7, #6 + 1880 000e 1B88 ldrh r3, [r3] + 1881 0010 044A ldr r2, .L109 + 1882 0012 1278 ldrb r2, [r2] + 1883 0014 5343 muls r3, r2 + 1884 0016 1800 movs r0, r3 + 1885 0018 FFF7FEFF bl CyDelayCycles +2707:Generated_Source\PSoC4/CyLib.c **** } + 1886 .loc 1 2707 0 + 1887 001c C046 nop + 1888 001e BD46 mov sp, r7 + 1889 0020 02B0 add sp, sp, #8 + 1890 @ sp needed + 1891 0022 80BD pop {r7, pc} + 1892 .L110: + 1893 .align 2 + 1894 .L109: + 1895 0024 00000000 .word cydelayFreqMhz + 1896 .cfi_endproc + 1897 .LFE28: + 1898 .size CyDelayUs, .-CyDelayUs + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 82 + + + 1899 .global __aeabi_uidiv + 1900 .section .text.CyDelayFreq,"ax",%progbits + 1901 .align 2 + 1902 .global CyDelayFreq + 1903 .code 16 + 1904 .thumb_func + 1905 .type CyDelayFreq, %function + 1906 CyDelayFreq: + 1907 .LFB29: +2708:Generated_Source\PSoC4/CyLib.c **** +2709:Generated_Source\PSoC4/CyLib.c **** +2710:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2711:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyDelayFreq +2712:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2713:Generated_Source\PSoC4/CyLib.c **** * Sets clock frequency for CyDelay. +2714:Generated_Source\PSoC4/CyLib.c **** * +2715:Generated_Source\PSoC4/CyLib.c **** * \param freq: Frequency of bus clock in Hertz. +2716:Generated_Source\PSoC4/CyLib.c **** * +2717:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2718:Generated_Source\PSoC4/CyLib.c **** void CyDelayFreq(uint32 freq) +2719:Generated_Source\PSoC4/CyLib.c **** { + 1908 .loc 1 2719 0 + 1909 .cfi_startproc + 1910 @ args = 0, pretend = 0, frame = 8 + 1911 @ frame_needed = 1, uses_anonymous_args = 0 + 1912 0000 80B5 push {r7, lr} + 1913 .cfi_def_cfa_offset 8 + 1914 .cfi_offset 7, -8 + 1915 .cfi_offset 14, -4 + 1916 0002 82B0 sub sp, sp, #8 + 1917 .cfi_def_cfa_offset 16 + 1918 0004 00AF add r7, sp, #0 + 1919 .cfi_def_cfa_register 7 + 1920 0006 7860 str r0, [r7, #4] +2720:Generated_Source\PSoC4/CyLib.c **** if (freq != 0u) + 1921 .loc 1 2720 0 + 1922 0008 7B68 ldr r3, [r7, #4] + 1923 000a 002B cmp r3, #0 + 1924 000c 03D0 beq .L112 +2721:Generated_Source\PSoC4/CyLib.c **** { +2722:Generated_Source\PSoC4/CyLib.c **** cydelayFreqHz = freq; + 1925 .loc 1 2722 0 + 1926 000e 154B ldr r3, .L114 + 1927 0010 7A68 ldr r2, [r7, #4] + 1928 0012 1A60 str r2, [r3] + 1929 0014 02E0 b .L113 + 1930 .L112: +2723:Generated_Source\PSoC4/CyLib.c **** } +2724:Generated_Source\PSoC4/CyLib.c **** else +2725:Generated_Source\PSoC4/CyLib.c **** { +2726:Generated_Source\PSoC4/CyLib.c **** cydelayFreqHz = CYDEV_BCLK__SYSCLK__HZ; + 1931 .loc 1 2726 0 + 1932 0016 134B ldr r3, .L114 + 1933 0018 134A ldr r2, .L114+4 + 1934 001a 1A60 str r2, [r3] + 1935 .L113: +2727:Generated_Source\PSoC4/CyLib.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 83 + + +2728:Generated_Source\PSoC4/CyLib.c **** +2729:Generated_Source\PSoC4/CyLib.c **** cydelayFreqMhz = (uint8)((cydelayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOL + 1936 .loc 1 2729 0 + 1937 001c 114B ldr r3, .L114 + 1938 001e 1B68 ldr r3, [r3] + 1939 0020 124A ldr r2, .L114+8 + 1940 0022 9446 mov ip, r2 + 1941 0024 6344 add r3, r3, ip + 1942 0026 1249 ldr r1, .L114+12 + 1943 0028 1800 movs r0, r3 + 1944 002a FFF7FEFF bl __aeabi_uidiv + 1945 002e 0300 movs r3, r0 + 1946 0030 DAB2 uxtb r2, r3 + 1947 0032 104B ldr r3, .L114+16 + 1948 0034 1A70 strb r2, [r3] +2730:Generated_Source\PSoC4/CyLib.c **** cydelayFreqKhz = (cydelayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + 1949 .loc 1 2730 0 + 1950 0036 0B4B ldr r3, .L114 + 1951 0038 1B68 ldr r3, [r3] + 1952 003a 0F4A ldr r2, .L114+20 + 1953 003c 9A18 adds r2, r3, r2 + 1954 003e FA23 movs r3, #250 + 1955 0040 9900 lsls r1, r3, #2 + 1956 0042 1000 movs r0, r2 + 1957 0044 FFF7FEFF bl __aeabi_uidiv + 1958 0048 0300 movs r3, r0 + 1959 004a 1A00 movs r2, r3 + 1960 004c 0B4B ldr r3, .L114+24 + 1961 004e 1A60 str r2, [r3] +2731:Generated_Source\PSoC4/CyLib.c **** cydelay32kMs = CY_DELAY_MS_OVERFLOW * cydelayFreqKhz; + 1962 .loc 1 2731 0 + 1963 0050 0A4B ldr r3, .L114+24 + 1964 0052 1B68 ldr r3, [r3] + 1965 0054 DA03 lsls r2, r3, #15 + 1966 0056 0A4B ldr r3, .L114+28 + 1967 0058 1A60 str r2, [r3] +2732:Generated_Source\PSoC4/CyLib.c **** } + 1968 .loc 1 2732 0 + 1969 005a C046 nop + 1970 005c BD46 mov sp, r7 + 1971 005e 02B0 add sp, sp, #8 + 1972 @ sp needed + 1973 0060 80BD pop {r7, pc} + 1974 .L115: + 1975 0062 C046 .align 2 + 1976 .L114: + 1977 0064 00000000 .word cydelayFreqHz + 1978 0068 00366E01 .word 24000000 + 1979 006c 3F420F00 .word 999999 + 1980 0070 40420F00 .word 1000000 + 1981 0074 00000000 .word cydelayFreqMhz + 1982 0078 E7030000 .word 999 + 1983 007c 00000000 .word cydelayFreqKhz + 1984 0080 00000000 .word cydelay32kMs + 1985 .cfi_endproc + 1986 .LFE29: + 1987 .size CyDelayFreq, .-CyDelayFreq + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 84 + + + 1988 .section .text.CySysTickStart,"ax",%progbits + 1989 .align 2 + 1990 .global CySysTickStart + 1991 .code 16 + 1992 .thumb_func + 1993 .type CySysTickStart, %function + 1994 CySysTickStart: + 1995 .LFB30: +2733:Generated_Source\PSoC4/CyLib.c **** +2734:Generated_Source\PSoC4/CyLib.c **** +2735:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2736:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysTick_Start +2737:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2738:Generated_Source\PSoC4/CyLib.c **** * +2739:Generated_Source\PSoC4/CyLib.c **** * Starts the system timer (SysTick): configures SysTick to generate interrupt +2740:Generated_Source\PSoC4/CyLib.c **** * every 1 ms and enables the interrupt. +2741:Generated_Source\PSoC4/CyLib.c **** * +2742:Generated_Source\PSoC4/CyLib.c **** * There are components (LIN, CapSense Gesture) that relies on the default +2743:Generated_Source\PSoC4/CyLib.c **** * interval (1 ms). And that changing the interval will negatively impact +2744:Generated_Source\PSoC4/CyLib.c **** * their functionality. +2745:Generated_Source\PSoC4/CyLib.c **** * +2746:Generated_Source\PSoC4/CyLib.c **** * \sideeffect +2747:Generated_Source\PSoC4/CyLib.c **** * Clears SysTick count flag if it was set. +2748:Generated_Source\PSoC4/CyLib.c **** * +2749:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2750:Generated_Source\PSoC4/CyLib.c **** void CySysTickStart(void) +2751:Generated_Source\PSoC4/CyLib.c **** { + 1996 .loc 1 2751 0 + 1997 .cfi_startproc + 1998 @ args = 0, pretend = 0, frame = 0 + 1999 @ frame_needed = 1, uses_anonymous_args = 0 + 2000 0000 80B5 push {r7, lr} + 2001 .cfi_def_cfa_offset 8 + 2002 .cfi_offset 7, -8 + 2003 .cfi_offset 14, -4 + 2004 0002 00AF add r7, sp, #0 + 2005 .cfi_def_cfa_register 7 +2752:Generated_Source\PSoC4/CyLib.c **** if (0u == CySysTickInitVar) + 2006 .loc 1 2752 0 + 2007 0004 064B ldr r3, .L118 + 2008 0006 1B68 ldr r3, [r3] + 2009 0008 002B cmp r3, #0 + 2010 000a 04D1 bne .L117 +2753:Generated_Source\PSoC4/CyLib.c **** { +2754:Generated_Source\PSoC4/CyLib.c **** CySysTickInit(); + 2011 .loc 1 2754 0 + 2012 000c FFF7FEFF bl CySysTickInit +2755:Generated_Source\PSoC4/CyLib.c **** CySysTickInitVar = 1u; + 2013 .loc 1 2755 0 + 2014 0010 034B ldr r3, .L118 + 2015 0012 0122 movs r2, #1 + 2016 0014 1A60 str r2, [r3] + 2017 .L117: +2756:Generated_Source\PSoC4/CyLib.c **** } +2757:Generated_Source\PSoC4/CyLib.c **** +2758:Generated_Source\PSoC4/CyLib.c **** CySysTickEnable(); + 2018 .loc 1 2758 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 85 + + + 2019 0016 FFF7FEFF bl CySysTickEnable +2759:Generated_Source\PSoC4/CyLib.c **** } + 2020 .loc 1 2759 0 + 2021 001a C046 nop + 2022 001c BD46 mov sp, r7 + 2023 @ sp needed + 2024 001e 80BD pop {r7, pc} + 2025 .L119: + 2026 .align 2 + 2027 .L118: + 2028 0020 00000000 .word CySysTickInitVar + 2029 .cfi_endproc + 2030 .LFE30: + 2031 .size CySysTickStart, .-CySysTickStart + 2032 .section .text.CySysTickInit,"ax",%progbits + 2033 .align 2 + 2034 .global CySysTickInit + 2035 .code 16 + 2036 .thumb_func + 2037 .type CySysTickInit, %function + 2038 CySysTickInit: + 2039 .LFB31: +2760:Generated_Source\PSoC4/CyLib.c **** +2761:Generated_Source\PSoC4/CyLib.c **** +2762:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2763:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysTickInit +2764:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2765:Generated_Source\PSoC4/CyLib.c **** * +2766:Generated_Source\PSoC4/CyLib.c **** * Initializes the callback addresses with pointers to NULL, associates the +2767:Generated_Source\PSoC4/CyLib.c **** * SysTick system vector with the function that is responsible for calling +2768:Generated_Source\PSoC4/CyLib.c **** * registered callback functions, configures SysTick timer to generate interrupt +2769:Generated_Source\PSoC4/CyLib.c **** * every 1 ms. +2770:Generated_Source\PSoC4/CyLib.c **** * +2771:Generated_Source\PSoC4/CyLib.c **** * The 1 ms interrupt interval is configured based on the frequency determined +2772:Generated_Source\PSoC4/CyLib.c **** * by PSoC Creator at build time. If System clock frequency is changed in +2773:Generated_Source\PSoC4/CyLib.c **** * runtime, the CyDelayFreq() with the appropriate parameter should be called. +2774:Generated_Source\PSoC4/CyLib.c **** * +2775:Generated_Source\PSoC4/CyLib.c **** * \sideeffect +2776:Generated_Source\PSoC4/CyLib.c **** * Clears SysTick count flag if it was set. +2777:Generated_Source\PSoC4/CyLib.c **** * +2778:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2779:Generated_Source\PSoC4/CyLib.c **** void CySysTickInit(void) +2780:Generated_Source\PSoC4/CyLib.c **** { + 2040 .loc 1 2780 0 + 2041 .cfi_startproc + 2042 @ args = 0, pretend = 0, frame = 8 + 2043 @ frame_needed = 1, uses_anonymous_args = 0 + 2044 0000 80B5 push {r7, lr} + 2045 .cfi_def_cfa_offset 8 + 2046 .cfi_offset 7, -8 + 2047 .cfi_offset 14, -4 + 2048 0002 82B0 sub sp, sp, #8 + 2049 .cfi_def_cfa_offset 16 + 2050 0004 00AF add r7, sp, #0 + 2051 .cfi_def_cfa_register 7 +2781:Generated_Source\PSoC4/CyLib.c **** uint32 i; +2782:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 86 + + +2783:Generated_Source\PSoC4/CyLib.c **** for (i = 0u; i> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC +2967:Generated_Source\PSoC4/CyLib.c **** } +2968:Generated_Source\PSoC4/CyLib.c **** +2969:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_SYSTICK_LFCLK_SOURCE) */ +2970:Generated_Source\PSoC4/CyLib.c **** +2971:Generated_Source\PSoC4/CyLib.c **** +2972:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2973:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysTickGetCountFlag + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 95 + + +2974:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2975:Generated_Source\PSoC4/CyLib.c **** * +2976:Generated_Source\PSoC4/CyLib.c **** * The count flag is set once SysTick counter reaches zero. +2977:Generated_Source\PSoC4/CyLib.c **** * The flag cleared on read. +2978:Generated_Source\PSoC4/CyLib.c **** * +2979:Generated_Source\PSoC4/CyLib.c **** * \return +2980:Generated_Source\PSoC4/CyLib.c **** * Returns non-zero value if flag is set, otherwise zero is returned. +2981:Generated_Source\PSoC4/CyLib.c **** * +2982:Generated_Source\PSoC4/CyLib.c **** * +2983:Generated_Source\PSoC4/CyLib.c **** * \sideeffect +2984:Generated_Source\PSoC4/CyLib.c **** * Clears SysTick count flag if it was set. +2985:Generated_Source\PSoC4/CyLib.c **** * +2986:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +2987:Generated_Source\PSoC4/CyLib.c **** uint32 CySysTickGetCountFlag(void) +2988:Generated_Source\PSoC4/CyLib.c **** { + 2372 .loc 1 2988 0 + 2373 .cfi_startproc + 2374 @ args = 0, pretend = 0, frame = 0 + 2375 @ frame_needed = 1, uses_anonymous_args = 0 + 2376 0000 80B5 push {r7, lr} + 2377 .cfi_def_cfa_offset 8 + 2378 .cfi_offset 7, -8 + 2379 .cfi_offset 14, -4 + 2380 0002 00AF add r7, sp, #0 + 2381 .cfi_def_cfa_register 7 +2989:Generated_Source\PSoC4/CyLib.c **** return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); + 2382 .loc 1 2989 0 + 2383 0004 034B ldr r3, .L150 + 2384 0006 1B68 ldr r3, [r3] + 2385 0008 1B0C lsrs r3, r3, #16 + 2386 000a 0122 movs r2, #1 + 2387 000c 1340 ands r3, r2 +2990:Generated_Source\PSoC4/CyLib.c **** } + 2388 .loc 1 2990 0 + 2389 000e 1800 movs r0, r3 + 2390 0010 BD46 mov sp, r7 + 2391 @ sp needed + 2392 0012 80BD pop {r7, pc} + 2393 .L151: + 2394 .align 2 + 2395 .L150: + 2396 0014 10E000E0 .word -536813552 + 2397 .cfi_endproc + 2398 .LFE39: + 2399 .size CySysTickGetCountFlag, .-CySysTickGetCountFlag + 2400 .section .text.CySysTickClear,"ax",%progbits + 2401 .align 2 + 2402 .global CySysTickClear + 2403 .code 16 + 2404 .thumb_func + 2405 .type CySysTickClear, %function + 2406 CySysTickClear: + 2407 .LFB40: +2991:Generated_Source\PSoC4/CyLib.c **** +2992:Generated_Source\PSoC4/CyLib.c **** +2993:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +2994:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysTickClear + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 96 + + +2995:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +2996:Generated_Source\PSoC4/CyLib.c **** * +2997:Generated_Source\PSoC4/CyLib.c **** * Clears the SysTick counter for well-defined startup. +2998:Generated_Source\PSoC4/CyLib.c **** * +2999:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +3000:Generated_Source\PSoC4/CyLib.c **** void CySysTickClear(void) +3001:Generated_Source\PSoC4/CyLib.c **** { + 2408 .loc 1 3001 0 + 2409 .cfi_startproc + 2410 @ args = 0, pretend = 0, frame = 0 + 2411 @ frame_needed = 1, uses_anonymous_args = 0 + 2412 0000 80B5 push {r7, lr} + 2413 .cfi_def_cfa_offset 8 + 2414 .cfi_offset 7, -8 + 2415 .cfi_offset 14, -4 + 2416 0002 00AF add r7, sp, #0 + 2417 .cfi_def_cfa_register 7 +3002:Generated_Source\PSoC4/CyLib.c **** CY_SYS_SYST_CVR_REG = 0u; + 2418 .loc 1 3002 0 + 2419 0004 024B ldr r3, .L153 + 2420 0006 0022 movs r2, #0 + 2421 0008 1A60 str r2, [r3] +3003:Generated_Source\PSoC4/CyLib.c **** } + 2422 .loc 1 3003 0 + 2423 000a C046 nop + 2424 000c BD46 mov sp, r7 + 2425 @ sp needed + 2426 000e 80BD pop {r7, pc} + 2427 .L154: + 2428 .align 2 + 2429 .L153: + 2430 0010 18E000E0 .word -536813544 + 2431 .cfi_endproc + 2432 .LFE40: + 2433 .size CySysTickClear, .-CySysTickClear + 2434 .section .text.CySysTickSetCallback,"ax",%progbits + 2435 .align 2 + 2436 .global CySysTickSetCallback + 2437 .code 16 + 2438 .thumb_func + 2439 .type CySysTickSetCallback, %function + 2440 CySysTickSetCallback: + 2441 .LFB41: +3004:Generated_Source\PSoC4/CyLib.c **** +3005:Generated_Source\PSoC4/CyLib.c **** +3006:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +3007:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysTickSetCallback +3008:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +3009:Generated_Source\PSoC4/CyLib.c **** * +3010:Generated_Source\PSoC4/CyLib.c **** * This function allows up to five user-defined interrupt service routine +3011:Generated_Source\PSoC4/CyLib.c **** * functions to be associated with the SysTick interrupt. These are specified +3012:Generated_Source\PSoC4/CyLib.c **** * through the use of pointers to the function. +3013:Generated_Source\PSoC4/CyLib.c **** * +3014:Generated_Source\PSoC4/CyLib.c **** * To set a custom callback function without the overhead of the system provided +3015:Generated_Source\PSoC4/CyLib.c **** * one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress

), +3016:Generated_Source\PSoC4/CyLib.c **** * where
is address of the custom defined interrupt service routine. +3017:Generated_Source\PSoC4/CyLib.c **** * Note: a custom callback function overrides the system defined callback + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 97 + + +3018:Generated_Source\PSoC4/CyLib.c **** * functions. +3019:Generated_Source\PSoC4/CyLib.c **** * +3020:Generated_Source\PSoC4/CyLib.c **** * \param number: The number of the callback function addresses to be set. The valid +3021:Generated_Source\PSoC4/CyLib.c **** * range is from 0 to 4. +3022:Generated_Source\PSoC4/CyLib.c **** * +3023:Generated_Source\PSoC4/CyLib.c **** * void(*CallbackFunction(void): A pointer to the function that will be +3024:Generated_Source\PSoC4/CyLib.c **** * associated with the SysTick ISR for the +3025:Generated_Source\PSoC4/CyLib.c **** * specified number. +3026:Generated_Source\PSoC4/CyLib.c **** * +3027:Generated_Source\PSoC4/CyLib.c **** * \return +3028:Generated_Source\PSoC4/CyLib.c **** * Returns the address of the previous callback function. +3029:Generated_Source\PSoC4/CyLib.c **** * The NULL is returned if the specified address in not set. +3030:Generated_Source\PSoC4/CyLib.c **** * +3031:Generated_Source\PSoC4/CyLib.c **** * \sideeffect +3032:Generated_Source\PSoC4/CyLib.c **** * The registered callback functions will be executed in the interrupt. +3033:Generated_Source\PSoC4/CyLib.c **** * +3034:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +3035:Generated_Source\PSoC4/CyLib.c **** cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) +3036:Generated_Source\PSoC4/CyLib.c **** { + 2442 .loc 1 3036 0 + 2443 .cfi_startproc + 2444 @ args = 0, pretend = 0, frame = 16 + 2445 @ frame_needed = 1, uses_anonymous_args = 0 + 2446 0000 80B5 push {r7, lr} + 2447 .cfi_def_cfa_offset 8 + 2448 .cfi_offset 7, -8 + 2449 .cfi_offset 14, -4 + 2450 0002 84B0 sub sp, sp, #16 + 2451 .cfi_def_cfa_offset 24 + 2452 0004 00AF add r7, sp, #0 + 2453 .cfi_def_cfa_register 7 + 2454 0006 7860 str r0, [r7, #4] + 2455 0008 3960 str r1, [r7] +3037:Generated_Source\PSoC4/CyLib.c **** cySysTickCallback retVal; +3038:Generated_Source\PSoC4/CyLib.c **** +3039:Generated_Source\PSoC4/CyLib.c **** retVal = CySysTickCallbacks[number]; + 2456 .loc 1 3039 0 + 2457 000a 074B ldr r3, .L157 + 2458 000c 7A68 ldr r2, [r7, #4] + 2459 000e 9200 lsls r2, r2, #2 + 2460 0010 D358 ldr r3, [r2, r3] + 2461 0012 FB60 str r3, [r7, #12] +3040:Generated_Source\PSoC4/CyLib.c **** CySysTickCallbacks[number] = function; + 2462 .loc 1 3040 0 + 2463 0014 044B ldr r3, .L157 + 2464 0016 7A68 ldr r2, [r7, #4] + 2465 0018 9200 lsls r2, r2, #2 + 2466 001a 3968 ldr r1, [r7] + 2467 001c D150 str r1, [r2, r3] +3041:Generated_Source\PSoC4/CyLib.c **** return (retVal); + 2468 .loc 1 3041 0 + 2469 001e FB68 ldr r3, [r7, #12] +3042:Generated_Source\PSoC4/CyLib.c **** } + 2470 .loc 1 3042 0 + 2471 0020 1800 movs r0, r3 + 2472 0022 BD46 mov sp, r7 + 2473 0024 04B0 add sp, sp, #16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 98 + + + 2474 @ sp needed + 2475 0026 80BD pop {r7, pc} + 2476 .L158: + 2477 .align 2 + 2478 .L157: + 2479 0028 00000000 .word CySysTickCallbacks + 2480 .cfi_endproc + 2481 .LFE41: + 2482 .size CySysTickSetCallback, .-CySysTickSetCallback + 2483 .section .text.CySysTickGetCallback,"ax",%progbits + 2484 .align 2 + 2485 .global CySysTickGetCallback + 2486 .code 16 + 2487 .thumb_func + 2488 .type CySysTickGetCallback, %function + 2489 CySysTickGetCallback: + 2490 .LFB42: +3043:Generated_Source\PSoC4/CyLib.c **** +3044:Generated_Source\PSoC4/CyLib.c **** +3045:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +3046:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysTickGetCallback +3047:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +3048:Generated_Source\PSoC4/CyLib.c **** * +3049:Generated_Source\PSoC4/CyLib.c **** * The function get the specified callback pointer. +3050:Generated_Source\PSoC4/CyLib.c **** * +3051:Generated_Source\PSoC4/CyLib.c **** * \param number: The number of callback function address to get. The valid +3052:Generated_Source\PSoC4/CyLib.c **** * range is from 0 to 4. +3053:Generated_Source\PSoC4/CyLib.c **** * +3054:Generated_Source\PSoC4/CyLib.c **** * \return +3055:Generated_Source\PSoC4/CyLib.c **** * Returns the address of the specified callback function. +3056:Generated_Source\PSoC4/CyLib.c **** * The NULL is returned if the specified address in not initialized. +3057:Generated_Source\PSoC4/CyLib.c **** * +3058:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +3059:Generated_Source\PSoC4/CyLib.c **** cySysTickCallback CySysTickGetCallback(uint32 number) +3060:Generated_Source\PSoC4/CyLib.c **** { + 2491 .loc 1 3060 0 + 2492 .cfi_startproc + 2493 @ args = 0, pretend = 0, frame = 8 + 2494 @ frame_needed = 1, uses_anonymous_args = 0 + 2495 0000 80B5 push {r7, lr} + 2496 .cfi_def_cfa_offset 8 + 2497 .cfi_offset 7, -8 + 2498 .cfi_offset 14, -4 + 2499 0002 82B0 sub sp, sp, #8 + 2500 .cfi_def_cfa_offset 16 + 2501 0004 00AF add r7, sp, #0 + 2502 .cfi_def_cfa_register 7 + 2503 0006 7860 str r0, [r7, #4] +3061:Generated_Source\PSoC4/CyLib.c **** return ((cySysTickCallback) CySysTickCallbacks[number]); + 2504 .loc 1 3061 0 + 2505 0008 034B ldr r3, .L161 + 2506 000a 7A68 ldr r2, [r7, #4] + 2507 000c 9200 lsls r2, r2, #2 + 2508 000e D358 ldr r3, [r2, r3] +3062:Generated_Source\PSoC4/CyLib.c **** } + 2509 .loc 1 3062 0 + 2510 0010 1800 movs r0, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 99 + + + 2511 0012 BD46 mov sp, r7 + 2512 0014 02B0 add sp, sp, #8 + 2513 @ sp needed + 2514 0016 80BD pop {r7, pc} + 2515 .L162: + 2516 .align 2 + 2517 .L161: + 2518 0018 00000000 .word CySysTickCallbacks + 2519 .cfi_endproc + 2520 .LFE42: + 2521 .size CySysTickGetCallback, .-CySysTickGetCallback + 2522 .section .text.CySysTickServiceCallbacks,"ax",%progbits + 2523 .align 2 + 2524 .code 16 + 2525 .thumb_func + 2526 .type CySysTickServiceCallbacks, %function + 2527 CySysTickServiceCallbacks: + 2528 .LFB43: +3063:Generated_Source\PSoC4/CyLib.c **** +3064:Generated_Source\PSoC4/CyLib.c **** +3065:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +3066:Generated_Source\PSoC4/CyLib.c **** * Function Name: CySysTickServiceCallbacks +3067:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +3068:Generated_Source\PSoC4/CyLib.c **** * +3069:Generated_Source\PSoC4/CyLib.c **** * System Tick timer interrupt routine +3070:Generated_Source\PSoC4/CyLib.c **** * +3071:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +3072:Generated_Source\PSoC4/CyLib.c **** static void CySysTickServiceCallbacks(void) +3073:Generated_Source\PSoC4/CyLib.c **** { + 2529 .loc 1 3073 0 + 2530 .cfi_startproc + 2531 @ args = 0, pretend = 0, frame = 8 + 2532 @ frame_needed = 1, uses_anonymous_args = 0 + 2533 0000 80B5 push {r7, lr} + 2534 .cfi_def_cfa_offset 8 + 2535 .cfi_offset 7, -8 + 2536 .cfi_offset 14, -4 + 2537 0002 82B0 sub sp, sp, #8 + 2538 .cfi_def_cfa_offset 16 + 2539 0004 00AF add r7, sp, #0 + 2540 .cfi_def_cfa_register 7 +3074:Generated_Source\PSoC4/CyLib.c **** uint32 i; +3075:Generated_Source\PSoC4/CyLib.c **** +3076:Generated_Source\PSoC4/CyLib.c **** /* Verify that tick timer flag was set */ +3077:Generated_Source\PSoC4/CyLib.c **** if (1u == CySysTickGetCountFlag()) + 2541 .loc 1 3077 0 + 2542 0006 FFF7FEFF bl CySysTickGetCountFlag + 2543 000a 0300 movs r3, r0 + 2544 000c 012B cmp r3, #1 + 2545 000e 13D1 bne .L168 +3078:Generated_Source\PSoC4/CyLib.c **** { +3079:Generated_Source\PSoC4/CyLib.c **** for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + 2546 .loc 1 3079 0 + 2547 0010 0023 movs r3, #0 + 2548 0012 7B60 str r3, [r7, #4] + 2549 0014 0DE0 b .L165 + 2550 .L167: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 100 + + +3080:Generated_Source\PSoC4/CyLib.c **** { +3081:Generated_Source\PSoC4/CyLib.c **** if (CySysTickCallbacks[i] != (void *) 0) + 2551 .loc 1 3081 0 + 2552 0016 0A4B ldr r3, .L169 + 2553 0018 7A68 ldr r2, [r7, #4] + 2554 001a 9200 lsls r2, r2, #2 + 2555 001c D358 ldr r3, [r2, r3] + 2556 001e 002B cmp r3, #0 + 2557 0020 04D0 beq .L166 +3082:Generated_Source\PSoC4/CyLib.c **** { +3083:Generated_Source\PSoC4/CyLib.c **** (void)(CySysTickCallbacks[i])(); + 2558 .loc 1 3083 0 + 2559 0022 074B ldr r3, .L169 + 2560 0024 7A68 ldr r2, [r7, #4] + 2561 0026 9200 lsls r2, r2, #2 + 2562 0028 D358 ldr r3, [r2, r3] + 2563 002a 9847 blx r3 + 2564 .L166: +3079:Generated_Source\PSoC4/CyLib.c **** { + 2565 .loc 1 3079 0 discriminator 2 + 2566 002c 7B68 ldr r3, [r7, #4] + 2567 002e 0133 adds r3, r3, #1 + 2568 0030 7B60 str r3, [r7, #4] + 2569 .L165: +3079:Generated_Source\PSoC4/CyLib.c **** { + 2570 .loc 1 3079 0 is_stmt 0 discriminator 1 + 2571 0032 7B68 ldr r3, [r7, #4] + 2572 0034 042B cmp r3, #4 + 2573 0036 EED9 bls .L167 + 2574 .L168: +3084:Generated_Source\PSoC4/CyLib.c **** } +3085:Generated_Source\PSoC4/CyLib.c **** } +3086:Generated_Source\PSoC4/CyLib.c **** } +3087:Generated_Source\PSoC4/CyLib.c **** } + 2575 .loc 1 3087 0 is_stmt 1 + 2576 0038 C046 nop + 2577 003a BD46 mov sp, r7 + 2578 003c 02B0 add sp, sp, #8 + 2579 @ sp needed + 2580 003e 80BD pop {r7, pc} + 2581 .L170: + 2582 .align 2 + 2583 .L169: + 2584 0040 00000000 .word CySysTickCallbacks + 2585 .cfi_endproc + 2586 .LFE43: + 2587 .size CySysTickServiceCallbacks, .-CySysTickServiceCallbacks + 2588 .section .text.CyGetUniqueId,"ax",%progbits + 2589 .align 2 + 2590 .global CyGetUniqueId + 2591 .code 16 + 2592 .thumb_func + 2593 .type CyGetUniqueId, %function + 2594 CyGetUniqueId: + 2595 .LFB44: +3088:Generated_Source\PSoC4/CyLib.c **** +3089:Generated_Source\PSoC4/CyLib.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 101 + + +3090:Generated_Source\PSoC4/CyLib.c **** /******************************************************************************* +3091:Generated_Source\PSoC4/CyLib.c **** * Function Name: CyGetUniqueId +3092:Generated_Source\PSoC4/CyLib.c **** ****************************************************************************//** +3093:Generated_Source\PSoC4/CyLib.c **** * +3094:Generated_Source\PSoC4/CyLib.c **** * Returns the 64-bit unique ID of the device. The uniqueness of the number is +3095:Generated_Source\PSoC4/CyLib.c **** * guaranteed for 10 years due to the die lot number having a cycle life of 10 +3096:Generated_Source\PSoC4/CyLib.c **** * years and even after 10 years, the probability of getting two identical +3097:Generated_Source\PSoC4/CyLib.c **** * numbers is very small. +3098:Generated_Source\PSoC4/CyLib.c **** * +3099:Generated_Source\PSoC4/CyLib.c **** * \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns +3100:Generated_Source\PSoC4/CyLib.c **** * the 64-bit unique ID of the device by loading them into the integer array +3101:Generated_Source\PSoC4/CyLib.c **** * pointed to by uniqueId. +3102:Generated_Source\PSoC4/CyLib.c **** * +3103:Generated_Source\PSoC4/CyLib.c **** *******************************************************************************/ +3104:Generated_Source\PSoC4/CyLib.c **** void CyGetUniqueId(uint32* uniqueId) +3105:Generated_Source\PSoC4/CyLib.c **** { + 2596 .loc 1 3105 0 + 2597 .cfi_startproc + 2598 @ args = 0, pretend = 0, frame = 8 + 2599 @ frame_needed = 1, uses_anonymous_args = 0 + 2600 0000 80B5 push {r7, lr} + 2601 .cfi_def_cfa_offset 8 + 2602 .cfi_offset 7, -8 + 2603 .cfi_offset 14, -4 + 2604 0002 82B0 sub sp, sp, #8 + 2605 .cfi_def_cfa_offset 16 + 2606 0004 00AF add r7, sp, #0 + 2607 .cfi_def_cfa_register 7 + 2608 0006 7860 str r0, [r7, #4] +3106:Generated_Source\PSoC4/CyLib.c **** #if(CY_PSOC4) +3107:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 ); + 2609 .loc 1 3107 0 + 2610 0008 254B ldr r3, .L172 + 2611 000a 1B78 ldrb r3, [r3] + 2612 000c DBB2 uxtb r3, r3 + 2613 000e 1A00 movs r2, r3 + 2614 0010 7B68 ldr r3, [r7, #4] + 2615 0012 1A60 str r2, [r3] +3108:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u); + 2616 .loc 1 3108 0 + 2617 0014 234B ldr r3, .L172+4 + 2618 0016 1B78 ldrb r3, [r3] + 2619 0018 DBB2 uxtb r3, r3 + 2620 001a 1A02 lsls r2, r3, #8 + 2621 001c 7B68 ldr r3, [r7, #4] + 2622 001e 1B68 ldr r3, [r3] + 2623 0020 1A43 orrs r2, r3 + 2624 0022 7B68 ldr r3, [r7, #4] + 2625 0024 1A60 str r2, [r3] +3109:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u); + 2626 .loc 1 3109 0 + 2627 0026 204B ldr r3, .L172+8 + 2628 0028 1B78 ldrb r3, [r3] + 2629 002a DBB2 uxtb r3, r3 + 2630 002c 1A04 lsls r2, r3, #16 + 2631 002e 7B68 ldr r3, [r7, #4] + 2632 0030 1B68 ldr r3, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 102 + + + 2633 0032 1A43 orrs r2, r3 + 2634 0034 7B68 ldr r3, [r7, #4] + 2635 0036 1A60 str r2, [r3] +3110:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u); + 2636 .loc 1 3110 0 + 2637 0038 1C4B ldr r3, .L172+12 + 2638 003a 1B78 ldrb r3, [r3] + 2639 003c DBB2 uxtb r3, r3 + 2640 003e 1A06 lsls r2, r3, #24 + 2641 0040 7B68 ldr r3, [r7, #4] + 2642 0042 1B68 ldr r3, [r3] + 2643 0044 1A43 orrs r2, r3 + 2644 0046 7B68 ldr r3, [r7, #4] + 2645 0048 1A60 str r2, [r3] +3111:Generated_Source\PSoC4/CyLib.c **** +3112:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X ); + 2646 .loc 1 3112 0 + 2647 004a 7B68 ldr r3, [r7, #4] + 2648 004c 0433 adds r3, r3, #4 + 2649 004e 184A ldr r2, .L172+16 + 2650 0050 1278 ldrb r2, [r2] + 2651 0052 D2B2 uxtb r2, r2 + 2652 0054 1A60 str r2, [r3] +3113:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u); + 2653 .loc 1 3113 0 + 2654 0056 174B ldr r3, .L172+20 + 2655 0058 1B78 ldrb r3, [r3] + 2656 005a DBB2 uxtb r3, r3 + 2657 005c 1902 lsls r1, r3, #8 + 2658 005e 7B68 ldr r3, [r7, #4] + 2659 0060 0433 adds r3, r3, #4 + 2660 0062 7A68 ldr r2, [r7, #4] + 2661 0064 0432 adds r2, r2, #4 + 2662 0066 1268 ldr r2, [r2] + 2663 0068 0A43 orrs r2, r1 + 2664 006a 1A60 str r2, [r3] +3114:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u); + 2665 .loc 1 3114 0 + 2666 006c 124B ldr r3, .L172+24 + 2667 006e 1B78 ldrb r3, [r3] + 2668 0070 DBB2 uxtb r3, r3 + 2669 0072 1904 lsls r1, r3, #16 + 2670 0074 7B68 ldr r3, [r7, #4] + 2671 0076 0433 adds r3, r3, #4 + 2672 0078 7A68 ldr r2, [r7, #4] + 2673 007a 0432 adds r2, r2, #4 + 2674 007c 1268 ldr r2, [r2] + 2675 007e 0A43 orrs r2, r1 + 2676 0080 1A60 str r2, [r3] +3115:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u); + 2677 .loc 1 3115 0 + 2678 0082 0E4B ldr r3, .L172+28 + 2679 0084 1B78 ldrb r3, [r3] + 2680 0086 DBB2 uxtb r3, r3 + 2681 0088 1906 lsls r1, r3, #24 + 2682 008a 7B68 ldr r3, [r7, #4] + 2683 008c 0433 adds r3, r3, #4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 103 + + + 2684 008e 7A68 ldr r2, [r7, #4] + 2685 0090 0432 adds r2, r2, #4 + 2686 0092 1268 ldr r2, [r2] + 2687 0094 0A43 orrs r2, r1 + 2688 0096 1A60 str r2, [r3] +3116:Generated_Source\PSoC4/CyLib.c **** #else +3117:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB ) +3118:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB ) +3119:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID ) +3120:Generated_Source\PSoC4/CyLib.c **** uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM ) +3121:Generated_Source\PSoC4/CyLib.c **** +3122:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC ) +3123:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC ) +3124:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK ) +3125:Generated_Source\PSoC4/CyLib.c **** uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR ) +3126:Generated_Source\PSoC4/CyLib.c **** #endif /* (CY_PSOC4) */ +3127:Generated_Source\PSoC4/CyLib.c **** } + 2689 .loc 1 3127 0 + 2690 0098 C046 nop + 2691 009a BD46 mov sp, r7 + 2692 009c 02B0 add sp, sp, #8 + 2693 @ sp needed + 2694 009e 80BD pop {r7, pc} + 2695 .L173: + 2696 .align 2 + 2697 .L172: + 2698 00a0 78F1FF0F .word 268431736 + 2699 00a4 79F1FF0F .word 268431737 + 2700 00a8 7AF1FF0F .word 268431738 + 2701 00ac 7BF1FF0F .word 268431739 + 2702 00b0 7CF1FF0F .word 268431740 + 2703 00b4 7DF1FF0F .word 268431741 + 2704 00b8 7EF1FF0F .word 268431742 + 2705 00bc 7FF1FF0F .word 268431743 + 2706 .cfi_endproc + 2707 .LFE44: + 2708 .size CyGetUniqueId, .-CyGetUniqueId + 2709 .text + 2710 .Letext0: + 2711 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 2712 .file 3 "Generated_Source\\PSoC4\\CyLib.h" + 2713 .section .debug_info,"",%progbits + 2714 .Ldebug_info0: + 2715 0000 DC080000 .4byte 0x8dc + 2716 0004 0400 .2byte 0x4 + 2717 0006 00000000 .4byte .Ldebug_abbrev0 + 2718 000a 04 .byte 0x4 + 2719 000b 01 .uleb128 0x1 + 2720 000c 41030000 .4byte .LASF101 + 2721 0010 0C .byte 0xc + 2722 0011 34060000 .4byte .LASF102 + 2723 0015 AF010000 .4byte .LASF103 + 2724 0019 00000000 .4byte .Ldebug_ranges0+0 + 2725 001d 00000000 .4byte 0 + 2726 0021 00000000 .4byte .Ldebug_line0 + 2727 0025 02 .uleb128 0x2 + 2728 0026 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 104 + + + 2729 0027 06 .byte 0x6 + 2730 0028 FE000000 .4byte .LASF0 + 2731 002c 02 .uleb128 0x2 + 2732 002d 01 .byte 0x1 + 2733 002e 08 .byte 0x8 + 2734 002f 00050000 .4byte .LASF1 + 2735 0033 02 .uleb128 0x2 + 2736 0034 02 .byte 0x2 + 2737 0035 05 .byte 0x5 + 2738 0036 0E050000 .4byte .LASF2 + 2739 003a 02 .uleb128 0x2 + 2740 003b 02 .byte 0x2 + 2741 003c 07 .byte 0x7 + 2742 003d FA020000 .4byte .LASF3 + 2743 0041 02 .uleb128 0x2 + 2744 0042 04 .byte 0x4 + 2745 0043 05 .byte 0x5 + 2746 0044 3D010000 .4byte .LASF4 + 2747 0048 02 .uleb128 0x2 + 2748 0049 04 .byte 0x4 + 2749 004a 07 .byte 0x7 + 2750 004b 99020000 .4byte .LASF5 + 2751 004f 02 .uleb128 0x2 + 2752 0050 08 .byte 0x8 + 2753 0051 05 .byte 0x5 + 2754 0052 F0000000 .4byte .LASF6 + 2755 0056 02 .uleb128 0x2 + 2756 0057 08 .byte 0x8 + 2757 0058 07 .byte 0x7 + 2758 0059 84000000 .4byte .LASF7 + 2759 005d 03 .uleb128 0x3 + 2760 005e 04 .byte 0x4 + 2761 005f 05 .byte 0x5 + 2762 0060 696E7400 .ascii "int\000" + 2763 0064 02 .uleb128 0x2 + 2764 0065 04 .byte 0x4 + 2765 0066 07 .byte 0x7 + 2766 0067 7D020000 .4byte .LASF8 + 2767 006b 04 .uleb128 0x4 + 2768 006c 68010000 .4byte .LASF9 + 2769 0070 02 .byte 0x2 + 2770 0071 E401 .2byte 0x1e4 + 2771 0073 2C000000 .4byte 0x2c + 2772 0077 04 .uleb128 0x4 + 2773 0078 17000000 .4byte .LASF10 + 2774 007c 02 .byte 0x2 + 2775 007d E501 .2byte 0x1e5 + 2776 007f 3A000000 .4byte 0x3a + 2777 0083 04 .uleb128 0x4 + 2778 0084 A8010000 .4byte .LASF11 + 2779 0088 02 .byte 0x2 + 2780 0089 E601 .2byte 0x1e6 + 2781 008b 48000000 .4byte 0x48 + 2782 008f 02 .uleb128 0x2 + 2783 0090 04 .byte 0x4 + 2784 0091 04 .byte 0x4 + 2785 0092 A7040000 .4byte .LASF12 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 105 + + + 2786 0096 02 .uleb128 0x2 + 2787 0097 08 .byte 0x8 + 2788 0098 04 .byte 0x4 + 2789 0099 84010000 .4byte .LASF13 + 2790 009d 02 .uleb128 0x2 + 2791 009e 01 .byte 0x1 + 2792 009f 08 .byte 0x8 + 2793 00a0 51050000 .4byte .LASF14 + 2794 00a4 04 .uleb128 0x4 + 2795 00a5 EA040000 .4byte .LASF15 + 2796 00a9 02 .byte 0x2 + 2797 00aa 8E02 .2byte 0x28e + 2798 00ac B0000000 .4byte 0xb0 + 2799 00b0 05 .uleb128 0x5 + 2800 00b1 6B000000 .4byte 0x6b + 2801 00b5 04 .uleb128 0x4 + 2802 00b6 F6030000 .4byte .LASF16 + 2803 00ba 02 .byte 0x2 + 2804 00bb 9002 .2byte 0x290 + 2805 00bd C1000000 .4byte 0xc1 + 2806 00c1 05 .uleb128 0x5 + 2807 00c2 83000000 .4byte 0x83 + 2808 00c6 04 .uleb128 0x4 + 2809 00c7 56050000 .4byte .LASF17 + 2810 00cb 02 .byte 0x2 + 2811 00cc A002 .2byte 0x2a0 + 2812 00ce D2000000 .4byte 0xd2 + 2813 00d2 06 .uleb128 0x6 + 2814 00d3 04 .byte 0x4 + 2815 00d4 D8000000 .4byte 0xd8 + 2816 00d8 07 .uleb128 0x7 + 2817 00d9 02 .uleb128 0x2 + 2818 00da 08 .byte 0x8 + 2819 00db 04 .byte 0x4 + 2820 00dc 33040000 .4byte .LASF18 + 2821 00e0 02 .uleb128 0x2 + 2822 00e1 04 .byte 0x4 + 2823 00e2 07 .byte 0x7 + 2824 00e3 18040000 .4byte .LASF19 + 2825 00e7 08 .uleb128 0x8 + 2826 00e8 BC040000 .4byte .LASF20 + 2827 00ec 03 .byte 0x3 + 2828 00ed F5 .byte 0xf5 + 2829 00ee D2000000 .4byte 0xd2 + 2830 00f2 09 .uleb128 0x9 + 2831 00f3 12060000 .4byte .LASF21 + 2832 00f7 01 .byte 0x1 + 2833 00f8 6C .byte 0x6c + 2834 00f9 00000000 .4byte .LFB0 + 2835 00fd 1C000000 .4byte .LFE0-.LFB0 + 2836 0101 01 .uleb128 0x1 + 2837 0102 9C .byte 0x9c + 2838 0103 09 .uleb128 0x9 + 2839 0104 C6020000 .4byte .LASF22 + 2840 0108 01 .byte 0x1 + 2841 0109 8C .byte 0x8c + 2842 010a 00000000 .4byte .LFB1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 106 + + + 2843 010e 1C000000 .4byte .LFE1-.LFB1 + 2844 0112 01 .uleb128 0x1 + 2845 0113 9C .byte 0x9c + 2846 0114 0A .uleb128 0xa + 2847 0115 27000000 .4byte .LASF25 + 2848 0119 01 .byte 0x1 + 2849 011a 0102 .2byte 0x201 + 2850 011c 00000000 .4byte .LFB2 + 2851 0120 48000000 .4byte .LFE2-.LFB2 + 2852 0124 01 .uleb128 0x1 + 2853 0125 9C .byte 0x9c + 2854 0126 58010000 .4byte 0x158 + 2855 012a 0B .uleb128 0xb + 2856 012b 36050000 .4byte .LASF27 + 2857 012f 01 .byte 0x1 + 2858 0130 0102 .2byte 0x201 + 2859 0132 83000000 .4byte 0x83 + 2860 0136 02 .uleb128 0x2 + 2861 0137 91 .byte 0x91 + 2862 0138 64 .sleb128 -28 + 2863 0139 0C .uleb128 0xc + 2864 013a 1B010000 .4byte .LASF23 + 2865 013e 01 .byte 0x1 + 2866 013f 0302 .2byte 0x203 + 2867 0141 6B000000 .4byte 0x6b + 2868 0145 02 .uleb128 0x2 + 2869 0146 91 .byte 0x91 + 2870 0147 6F .sleb128 -17 + 2871 0148 0C .uleb128 0xc + 2872 0149 60060000 .4byte .LASF24 + 2873 014d 01 .byte 0x1 + 2874 014e 0402 .2byte 0x204 + 2875 0150 83000000 .4byte 0x83 + 2876 0154 02 .uleb128 0x2 + 2877 0155 91 .byte 0x91 + 2878 0156 68 .sleb128 -24 + 2879 0157 00 .byte 0 + 2880 0158 0D .uleb128 0xd + 2881 0159 E1030000 .4byte .LASF26 + 2882 015d 01 .byte 0x1 + 2883 015e 4902 .2byte 0x249 + 2884 0160 00000000 .4byte .LFB3 + 2885 0164 50000000 .4byte .LFE3-.LFB3 + 2886 0168 01 .uleb128 0x1 + 2887 0169 9C .byte 0x9c + 2888 016a 7E010000 .4byte 0x17e + 2889 016e 0B .uleb128 0xb + 2890 016f 7D010000 .4byte .LASF28 + 2891 0173 01 .byte 0x1 + 2892 0174 4902 .2byte 0x249 + 2893 0176 83000000 .4byte 0x83 + 2894 017a 02 .uleb128 0x2 + 2895 017b 91 .byte 0x91 + 2896 017c 74 .sleb128 -12 + 2897 017d 00 .byte 0 + 2898 017e 0E .uleb128 0xe + 2899 017f 0F020000 .4byte .LASF42 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 107 + + + 2900 0183 01 .byte 0x1 + 2901 0184 6E02 .2byte 0x26e + 2902 0186 83000000 .4byte 0x83 + 2903 018a 00000000 .4byte .LFB4 + 2904 018e 34000000 .4byte .LFE4-.LFB4 + 2905 0192 01 .uleb128 0x1 + 2906 0193 9C .byte 0x9c + 2907 0194 B7010000 .4byte 0x1b7 + 2908 0198 0C .uleb128 0xc + 2909 0199 1B010000 .4byte .LASF23 + 2910 019d 01 .byte 0x1 + 2911 019e 7002 .2byte 0x270 + 2912 01a0 6B000000 .4byte 0x6b + 2913 01a4 02 .uleb128 0x2 + 2914 01a5 91 .byte 0x91 + 2915 01a6 6F .sleb128 -17 + 2916 01a7 0C .uleb128 0xc + 2917 01a8 4F040000 .4byte .LASF29 + 2918 01ac 01 .byte 0x1 + 2919 01ad 7102 .2byte 0x271 + 2920 01af 83000000 .4byte 0x83 + 2921 01b3 02 .uleb128 0x2 + 2922 01b4 91 .byte 0x91 + 2923 01b5 68 .sleb128 -24 + 2924 01b6 00 .byte 0 + 2925 01b7 0A .uleb128 0xa + 2926 01b8 73050000 .4byte .LASF30 + 2927 01bc 01 .byte 0x1 + 2928 01bd AB02 .2byte 0x2ab + 2929 01bf 00000000 .4byte .LFB5 + 2930 01c3 48000000 .4byte .LFE5-.LFB5 + 2931 01c7 01 .uleb128 0x1 + 2932 01c8 9C .byte 0x9c + 2933 01c9 EC010000 .4byte 0x1ec + 2934 01cd 0B .uleb128 0xb + 2935 01ce 0A060000 .4byte .LASF31 + 2936 01d2 01 .byte 0x1 + 2937 01d3 AB02 .2byte 0x2ab + 2938 01d5 83000000 .4byte 0x83 + 2939 01d9 02 .uleb128 0x2 + 2940 01da 91 .byte 0x91 + 2941 01db 64 .sleb128 -28 + 2942 01dc 0C .uleb128 0xc + 2943 01dd 1B010000 .4byte .LASF23 + 2944 01e1 01 .byte 0x1 + 2945 01e2 AD02 .2byte 0x2ad + 2946 01e4 6B000000 .4byte 0x6b + 2947 01e8 02 .uleb128 0x2 + 2948 01e9 91 .byte 0x91 + 2949 01ea 6F .sleb128 -17 + 2950 01eb 00 .byte 0 + 2951 01ec 0A .uleb128 0xa + 2952 01ed 2C030000 .4byte .LASF32 + 2953 01f1 01 .byte 0x1 + 2954 01f2 E502 .2byte 0x2e5 + 2955 01f4 00000000 .4byte .LFB6 + 2956 01f8 E4010000 .4byte .LFE6-.LFB6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 108 + + + 2957 01fc 01 .uleb128 0x1 + 2958 01fd 9C .byte 0x9c + 2959 01fe 5D020000 .4byte 0x25d + 2960 0202 0B .uleb128 0xb + 2961 0203 0A010000 .4byte .LASF33 + 2962 0207 01 .byte 0x1 + 2963 0208 E502 .2byte 0x2e5 + 2964 020a 83000000 .4byte 0x83 + 2965 020e 02 .uleb128 0x2 + 2966 020f 91 .byte 0x91 + 2967 0210 64 .sleb128 -28 + 2968 0211 0C .uleb128 0xc + 2969 0212 0F000000 .4byte .LASF34 + 2970 0216 01 .byte 0x1 + 2971 0217 EB02 .2byte 0x2eb + 2972 0219 6B000000 .4byte 0x6b + 2973 021d 02 .uleb128 0x2 + 2974 021e 91 .byte 0x91 + 2975 021f 6F .sleb128 -17 + 2976 0220 0C .uleb128 0xc + 2977 0221 47040000 .4byte .LASF35 + 2978 0225 01 .byte 0x1 + 2979 0226 EC02 .2byte 0x2ec + 2980 0228 6B000000 .4byte 0x6b + 2981 022c 02 .uleb128 0x2 + 2982 022d 91 .byte 0x91 + 2983 022e 6E .sleb128 -18 + 2984 022f 0C .uleb128 0xc + 2985 0230 23060000 .4byte .LASF36 + 2986 0234 01 .byte 0x1 + 2987 0235 ED02 .2byte 0x2ed + 2988 0237 6B000000 .4byte 0x6b + 2989 023b 02 .uleb128 0x2 + 2990 023c 91 .byte 0x91 + 2991 023d 6B .sleb128 -21 + 2992 023e 0C .uleb128 0xc + 2993 023f 6F000000 .4byte .LASF37 + 2994 0243 01 .byte 0x1 + 2995 0244 EE02 .2byte 0x2ee + 2996 0246 6B000000 .4byte 0x6b + 2997 024a 02 .uleb128 0x2 + 2998 024b 91 .byte 0x91 + 2999 024c 6D .sleb128 -19 + 3000 024d 0C .uleb128 0xc + 3001 024e 1B010000 .4byte .LASF23 + 3002 0252 01 .byte 0x1 + 3003 0253 F902 .2byte 0x2f9 + 3004 0255 6B000000 .4byte 0x6b + 3005 0259 02 .uleb128 0x2 + 3006 025a 91 .byte 0x91 + 3007 025b 6C .sleb128 -20 + 3008 025c 00 .byte 0 + 3009 025d 0A .uleb128 0xa + 3010 025e AD040000 .4byte .LASF38 + 3011 0262 01 .byte 0x1 + 3012 0263 C008 .2byte 0x8c0 + 3013 0265 00000000 .4byte .LFB7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 109 + + + 3014 0269 64000000 .4byte .LFE7-.LFB7 + 3015 026d 01 .uleb128 0x1 + 3016 026e 9C .byte 0x9c + 3017 026f 83020000 .4byte 0x283 + 3018 0273 0B .uleb128 0xb + 3019 0274 EF040000 .4byte .LASF39 + 3020 0278 01 .byte 0x1 + 3021 0279 C008 .2byte 0x8c0 + 3022 027b 83000000 .4byte 0x83 + 3023 027f 02 .uleb128 0x2 + 3024 0280 91 .byte 0x91 + 3025 0281 74 .sleb128 -12 + 3026 0282 00 .byte 0 + 3027 0283 0F .uleb128 0xf + 3028 0284 DD050000 .4byte .LASF40 + 3029 0288 01 .byte 0x1 + 3030 0289 DE08 .2byte 0x8de + 3031 028b 00000000 .4byte .LFB8 + 3032 028f 2C000000 .4byte .LFE8-.LFB8 + 3033 0293 01 .uleb128 0x1 + 3034 0294 9C .byte 0x9c + 3035 0295 10 .uleb128 0x10 + 3036 0296 AB020000 .4byte .LASF82 + 3037 029a 01 .byte 0x1 + 3038 029b F008 .2byte 0x8f0 + 3039 029d 83000000 .4byte 0x83 + 3040 02a1 00000000 .4byte .LFB9 + 3041 02a5 18000000 .4byte .LFE9-.LFB9 + 3042 02a9 01 .uleb128 0x1 + 3043 02aa 9C .byte 0x9c + 3044 02ab 0F .uleb128 0xf + 3045 02ac 91010000 .4byte .LASF41 + 3046 02b0 01 .byte 0x1 + 3047 02b1 0009 .2byte 0x900 + 3048 02b3 00000000 .4byte .LFB10 + 3049 02b7 14000000 .4byte .LFE10-.LFB10 + 3050 02bb 01 .uleb128 0x1 + 3051 02bc 9C .byte 0x9c + 3052 02bd 11 .uleb128 0x11 + 3053 02be E6020000 .4byte .LASF43 + 3054 02c2 01 .byte 0x1 + 3055 02c3 1A09 .2byte 0x91a + 3056 02c5 83000000 .4byte 0x83 + 3057 02c9 00000000 .4byte .LFB11 + 3058 02cd 30000000 .4byte .LFE11-.LFB11 + 3059 02d1 01 .uleb128 0x1 + 3060 02d2 9C .byte 0x9c + 3061 02d3 F6020000 .4byte 0x2f6 + 3062 02d7 0B .uleb128 0xb + 3063 02d8 4A050000 .4byte .LASF44 + 3064 02dc 01 .byte 0x1 + 3065 02dd 1A09 .2byte 0x91a + 3066 02df 83000000 .4byte 0x83 + 3067 02e3 02 .uleb128 0x2 + 3068 02e4 91 .byte 0x91 + 3069 02e5 6C .sleb128 -20 + 3070 02e6 0C .uleb128 0xc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 110 + + + 3071 02e7 0B040000 .4byte .LASF45 + 3072 02eb 01 .byte 0x1 + 3073 02ec 1C09 .2byte 0x91c + 3074 02ee 83000000 .4byte 0x83 + 3075 02f2 02 .uleb128 0x2 + 3076 02f3 91 .byte 0x91 + 3077 02f4 74 .sleb128 -12 + 3078 02f5 00 .byte 0 + 3079 02f6 11 .uleb128 0x11 + 3080 02f7 61000000 .4byte .LASF46 + 3081 02fb 01 .byte 0x1 + 3082 02fc 3109 .2byte 0x931 + 3083 02fe 83000000 .4byte 0x83 + 3084 0302 00000000 .4byte .LFB12 + 3085 0306 24000000 .4byte .LFE12-.LFB12 + 3086 030a 01 .uleb128 0x1 + 3087 030b 9C .byte 0x9c + 3088 030c 20030000 .4byte 0x320 + 3089 0310 0C .uleb128 0xc + 3090 0311 1E000000 .4byte .LASF47 + 3091 0315 01 .byte 0x1 + 3092 0316 3309 .2byte 0x933 + 3093 0318 83000000 .4byte 0x83 + 3094 031c 02 .uleb128 0x2 + 3095 031d 91 .byte 0x91 + 3096 031e 74 .sleb128 -12 + 3097 031f 00 .byte 0 + 3098 0320 0D .uleb128 0xd + 3099 0321 AC000000 .4byte .LASF48 + 3100 0325 01 .byte 0x1 + 3101 0326 4809 .2byte 0x948 + 3102 0328 00000000 .4byte .LFB13 + 3103 032c 1C000000 .4byte .LFE13-.LFB13 + 3104 0330 01 .uleb128 0x1 + 3105 0331 9C .byte 0x9c + 3106 0332 46030000 .4byte 0x346 + 3107 0336 0B .uleb128 0xb + 3108 0337 0A020000 .4byte .LASF49 + 3109 033b 01 .byte 0x1 + 3110 033c 4809 .2byte 0x948 + 3111 033e 83000000 .4byte 0x83 + 3112 0342 02 .uleb128 0x2 + 3113 0343 91 .byte 0x91 + 3114 0344 74 .sleb128 -12 + 3115 0345 00 .byte 0 + 3116 0346 0E .uleb128 0xe + 3117 0347 CF030000 .4byte .LASF50 + 3118 034b 01 .byte 0x1 + 3119 034c 6109 .2byte 0x961 + 3120 034e C6000000 .4byte 0xc6 + 3121 0352 00000000 .4byte .LFB14 + 3122 0356 48000000 .4byte .LFE14-.LFB14 + 3123 035a 01 .uleb128 0x1 + 3124 035b 9C .byte 0x9c + 3125 035c 9D030000 .4byte 0x39d + 3126 0360 0B .uleb128 0xb + 3127 0361 1C030000 .4byte .LASF51 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 111 + + + 3128 0365 01 .byte 0x1 + 3129 0366 6109 .2byte 0x961 + 3130 0368 6B000000 .4byte 0x6b + 3131 036c 02 .uleb128 0x2 + 3132 036d 91 .byte 0x91 + 3133 036e 6F .sleb128 -17 + 3134 036f 0B .uleb128 0xb + 3135 0370 3F040000 .4byte .LASF52 + 3136 0374 01 .byte 0x1 + 3137 0375 6109 .2byte 0x961 + 3138 0377 C6000000 .4byte 0xc6 + 3139 037b 02 .uleb128 0x2 + 3140 037c 91 .byte 0x91 + 3141 037d 68 .sleb128 -24 + 3142 037e 0C .uleb128 0xc + 3143 037f 53000000 .4byte .LASF53 + 3144 0383 01 .byte 0x1 + 3145 0384 6309 .2byte 0x963 + 3146 0386 C6000000 .4byte 0xc6 + 3147 038a 02 .uleb128 0x2 + 3148 038b 91 .byte 0x91 + 3149 038c 70 .sleb128 -16 + 3150 038d 0C .uleb128 0xc + 3151 038e 00000000 .4byte .LASF54 + 3152 0392 01 .byte 0x1 + 3153 0393 6409 .2byte 0x964 + 3154 0395 9D030000 .4byte 0x39d + 3155 0399 02 .uleb128 0x2 + 3156 039a 91 .byte 0x91 + 3157 039b 74 .sleb128 -12 + 3158 039c 00 .byte 0 + 3159 039d 06 .uleb128 0x6 + 3160 039e 04 .byte 0x4 + 3161 039f C6000000 .4byte 0xc6 + 3162 03a3 0E .uleb128 0xe + 3163 03a4 24050000 .4byte .LASF55 + 3164 03a8 01 .byte 0x1 + 3165 03a9 8309 .2byte 0x983 + 3166 03ab C6000000 .4byte 0xc6 + 3167 03af 00000000 .4byte .LFB15 + 3168 03b3 34000000 .4byte .LFE15-.LFB15 + 3169 03b7 01 .uleb128 0x1 + 3170 03b8 9C .byte 0x9c + 3171 03b9 DC030000 .4byte 0x3dc + 3172 03bd 0B .uleb128 0xb + 3173 03be 1C030000 .4byte .LASF51 + 3174 03c2 01 .byte 0x1 + 3175 03c3 8309 .2byte 0x983 + 3176 03c5 6B000000 .4byte 0x6b + 3177 03c9 02 .uleb128 0x2 + 3178 03ca 91 .byte 0x91 + 3179 03cb 6F .sleb128 -17 + 3180 03cc 0C .uleb128 0xc + 3181 03cd 00000000 .4byte .LASF54 + 3182 03d1 01 .byte 0x1 + 3183 03d2 8509 .2byte 0x985 + 3184 03d4 9D030000 .4byte 0x39d + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 112 + + + 3185 03d8 02 .uleb128 0x2 + 3186 03d9 91 .byte 0x91 + 3187 03da 74 .sleb128 -12 + 3188 03db 00 .byte 0 + 3189 03dc 0E .uleb128 0xe + 3190 03dd 0D030000 .4byte .LASF56 + 3191 03e1 01 .byte 0x1 + 3192 03e2 9909 .2byte 0x999 + 3193 03e4 C6000000 .4byte 0xc6 + 3194 03e8 00000000 .4byte .LFB16 + 3195 03ec 4C000000 .4byte .LFE16-.LFB16 + 3196 03f0 01 .uleb128 0x1 + 3197 03f1 9C .byte 0x9c + 3198 03f2 33040000 .4byte 0x433 + 3199 03f6 0B .uleb128 0xb + 3200 03f7 1C030000 .4byte .LASF51 + 3201 03fb 01 .byte 0x1 + 3202 03fc 9909 .2byte 0x999 + 3203 03fe 6B000000 .4byte 0x6b + 3204 0402 02 .uleb128 0x2 + 3205 0403 91 .byte 0x91 + 3206 0404 6F .sleb128 -17 + 3207 0405 0B .uleb128 0xb + 3208 0406 3F040000 .4byte .LASF52 + 3209 040a 01 .byte 0x1 + 3210 040b 9909 .2byte 0x999 + 3211 040d C6000000 .4byte 0xc6 + 3212 0411 02 .uleb128 0x2 + 3213 0412 91 .byte 0x91 + 3214 0413 68 .sleb128 -24 + 3215 0414 0C .uleb128 0xc + 3216 0415 53000000 .4byte .LASF53 + 3217 0419 01 .byte 0x1 + 3218 041a 9B09 .2byte 0x99b + 3219 041c C6000000 .4byte 0xc6 + 3220 0420 02 .uleb128 0x2 + 3221 0421 91 .byte 0x91 + 3222 0422 70 .sleb128 -16 + 3223 0423 0C .uleb128 0xc + 3224 0424 00000000 .4byte .LASF54 + 3225 0428 01 .byte 0x1 + 3226 0429 9C09 .2byte 0x99c + 3227 042b 9D030000 .4byte 0x39d + 3228 042f 02 .uleb128 0x2 + 3229 0430 91 .byte 0x91 + 3230 0431 74 .sleb128 -12 + 3231 0432 00 .byte 0 + 3232 0433 0E .uleb128 0xe + 3233 0434 CE040000 .4byte .LASF57 + 3234 0438 01 .byte 0x1 + 3235 0439 B509 .2byte 0x9b5 + 3236 043b C6000000 .4byte 0xc6 + 3237 043f 00000000 .4byte .LFB17 + 3238 0443 36000000 .4byte .LFE17-.LFB17 + 3239 0447 01 .uleb128 0x1 + 3240 0448 9C .byte 0x9c + 3241 0449 6C040000 .4byte 0x46c + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 113 + + + 3242 044d 0B .uleb128 0xb + 3243 044e 1C030000 .4byte .LASF51 + 3244 0452 01 .byte 0x1 + 3245 0453 B509 .2byte 0x9b5 + 3246 0455 6B000000 .4byte 0x6b + 3247 0459 02 .uleb128 0x2 + 3248 045a 91 .byte 0x91 + 3249 045b 6F .sleb128 -17 + 3250 045c 0C .uleb128 0xc + 3251 045d 00000000 .4byte .LASF54 + 3252 0461 01 .byte 0x1 + 3253 0462 B709 .2byte 0x9b7 + 3254 0464 9D030000 .4byte 0x39d + 3255 0468 02 .uleb128 0x2 + 3256 0469 91 .byte 0x91 + 3257 046a 74 .sleb128 -12 + 3258 046b 00 .byte 0 + 3259 046c 0A .uleb128 0xa + 3260 046d 96040000 .4byte .LASF58 + 3261 0471 01 .byte 0x1 + 3262 0472 C809 .2byte 0x9c8 + 3263 0474 00000000 .4byte .LFB18 + 3264 0478 A8000000 .4byte .LFE18-.LFB18 + 3265 047c 01 .uleb128 0x1 + 3266 047d 9C .byte 0x9c + 3267 047e CE040000 .4byte 0x4ce + 3268 0482 0B .uleb128 0xb + 3269 0483 1C030000 .4byte .LASF51 + 3270 0487 01 .byte 0x1 + 3271 0488 C809 .2byte 0x9c8 + 3272 048a 6B000000 .4byte 0x6b + 3273 048e 02 .uleb128 0x2 + 3274 048f 91 .byte 0x91 + 3275 0490 5F .sleb128 -33 + 3276 0491 0B .uleb128 0xb + 3277 0492 23030000 .4byte .LASF59 + 3278 0496 01 .byte 0x1 + 3279 0497 C809 .2byte 0x9c8 + 3280 0499 6B000000 .4byte 0x6b + 3281 049d 02 .uleb128 0x2 + 3282 049e 91 .byte 0x91 + 3283 049f 5E .sleb128 -34 + 3284 04a0 0C .uleb128 0xc + 3285 04a1 1B010000 .4byte .LASF23 + 3286 04a5 01 .byte 0x1 + 3287 04a6 CA09 .2byte 0x9ca + 3288 04a8 6B000000 .4byte 0x6b + 3289 04ac 02 .uleb128 0x2 + 3290 04ad 91 .byte 0x91 + 3291 04ae 6B .sleb128 -21 + 3292 04af 0C .uleb128 0xc + 3293 04b0 8B010000 .4byte .LASF60 + 3294 04b4 01 .byte 0x1 + 3295 04b5 CB09 .2byte 0x9cb + 3296 04b7 83000000 .4byte 0x83 + 3297 04bb 02 .uleb128 0x2 + 3298 04bc 91 .byte 0x91 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 114 + + + 3299 04bd 6C .sleb128 -20 + 3300 04be 0C .uleb128 0xc + 3301 04bf 53020000 .4byte .LASF61 + 3302 04c3 01 .byte 0x1 + 3303 04c4 CC09 .2byte 0x9cc + 3304 04c6 83000000 .4byte 0x83 + 3305 04ca 02 .uleb128 0x2 + 3306 04cb 91 .byte 0x91 + 3307 04cc 64 .sleb128 -28 + 3308 04cd 00 .byte 0 + 3309 04ce 0E .uleb128 0xe + 3310 04cf 27020000 .4byte .LASF62 + 3311 04d3 01 .byte 0x1 + 3312 04d4 EA09 .2byte 0x9ea + 3313 04d6 6B000000 .4byte 0x6b + 3314 04da 00000000 .4byte .LFB19 + 3315 04de 58000000 .4byte .LFE19-.LFB19 + 3316 04e2 01 .uleb128 0x1 + 3317 04e3 9C .byte 0x9c + 3318 04e4 07050000 .4byte 0x507 + 3319 04e8 0B .uleb128 0xb + 3320 04e9 1C030000 .4byte .LASF51 + 3321 04ed 01 .byte 0x1 + 3322 04ee EA09 .2byte 0x9ea + 3323 04f0 6B000000 .4byte 0x6b + 3324 04f4 02 .uleb128 0x2 + 3325 04f5 91 .byte 0x91 + 3326 04f6 6F .sleb128 -17 + 3327 04f7 0C .uleb128 0xc + 3328 04f8 23030000 .4byte .LASF59 + 3329 04fc 01 .byte 0x1 + 3330 04fd EC09 .2byte 0x9ec + 3331 04ff 6B000000 .4byte 0x6b + 3332 0503 02 .uleb128 0x2 + 3333 0504 91 .byte 0x91 + 3334 0505 77 .sleb128 -9 + 3335 0506 00 .byte 0 + 3336 0507 0D .uleb128 0xd + 3337 0508 18050000 .4byte .LASF63 + 3338 050c 01 .byte 0x1 + 3339 050d FF09 .2byte 0x9ff + 3340 050f 00000000 .4byte .LFB20 + 3341 0513 2C000000 .4byte .LFE20-.LFB20 + 3342 0517 01 .uleb128 0x1 + 3343 0518 9C .byte 0x9c + 3344 0519 2D050000 .4byte 0x52d + 3345 051d 0B .uleb128 0xb + 3346 051e 1C030000 .4byte .LASF51 + 3347 0522 01 .byte 0x1 + 3348 0523 FF09 .2byte 0x9ff + 3349 0525 6B000000 .4byte 0x6b + 3350 0529 02 .uleb128 0x2 + 3351 052a 91 .byte 0x91 + 3352 052b 77 .sleb128 -9 + 3353 052c 00 .byte 0 + 3354 052d 11 .uleb128 0x11 + 3355 052e E2000000 .4byte .LASF64 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 115 + + + 3356 0532 01 .byte 0x1 + 3357 0533 110A .2byte 0xa11 + 3358 0535 6B000000 .4byte 0x6b + 3359 0539 00000000 .4byte .LFB21 + 3360 053d 30000000 .4byte .LFE21-.LFB21 + 3361 0541 01 .uleb128 0x1 + 3362 0542 9C .byte 0x9c + 3363 0543 57050000 .4byte 0x557 + 3364 0547 0B .uleb128 0xb + 3365 0548 1C030000 .4byte .LASF51 + 3366 054c 01 .byte 0x1 + 3367 054d 110A .2byte 0xa11 + 3368 054f 6B000000 .4byte 0x6b + 3369 0553 02 .uleb128 0x2 + 3370 0554 91 .byte 0x91 + 3371 0555 77 .sleb128 -9 + 3372 0556 00 .byte 0 + 3373 0557 0D .uleb128 0xd + 3374 0558 46010000 .4byte .LASF65 + 3375 055c 01 .byte 0x1 + 3376 055d 210A .2byte 0xa21 + 3377 055f 00000000 .4byte .LFB22 + 3378 0563 2C000000 .4byte .LFE22-.LFB22 + 3379 0567 01 .uleb128 0x1 + 3380 0568 9C .byte 0x9c + 3381 0569 7D050000 .4byte 0x57d + 3382 056d 0B .uleb128 0xb + 3383 056e 1C030000 .4byte .LASF51 + 3384 0572 01 .byte 0x1 + 3385 0573 210A .2byte 0xa21 + 3386 0575 6B000000 .4byte 0x6b + 3387 0579 02 .uleb128 0x2 + 3388 057a 91 .byte 0x91 + 3389 057b 77 .sleb128 -9 + 3390 057c 00 .byte 0 + 3391 057d 0D .uleb128 0xd + 3392 057e D6020000 .4byte .LASF66 + 3393 0582 01 .byte 0x1 + 3394 0583 2F0A .2byte 0xa2f + 3395 0585 00000000 .4byte .LFB23 + 3396 0589 2C000000 .4byte .LFE23-.LFB23 + 3397 058d 01 .uleb128 0x1 + 3398 058e 9C .byte 0x9c + 3399 058f A3050000 .4byte 0x5a3 + 3400 0593 0B .uleb128 0xb + 3401 0594 1C030000 .4byte .LASF51 + 3402 0598 01 .byte 0x1 + 3403 0599 2F0A .2byte 0xa2f + 3404 059b 6B000000 .4byte 0x6b + 3405 059f 02 .uleb128 0x2 + 3406 05a0 91 .byte 0x91 + 3407 05a1 77 .sleb128 -9 + 3408 05a2 00 .byte 0 + 3409 05a3 0D .uleb128 0xd + 3410 05a4 21040000 .4byte .LASF67 + 3411 05a8 01 .byte 0x1 + 3412 05a9 3E0A .2byte 0xa3e + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 116 + + + 3413 05ab 00000000 .4byte .LFB24 + 3414 05af 2C000000 .4byte .LFE24-.LFB24 + 3415 05b3 01 .uleb128 0x1 + 3416 05b4 9C .byte 0x9c + 3417 05b5 C9050000 .4byte 0x5c9 + 3418 05b9 0B .uleb128 0xb + 3419 05ba 1C030000 .4byte .LASF51 + 3420 05be 01 .byte 0x1 + 3421 05bf 3E0A .2byte 0xa3e + 3422 05c1 6B000000 .4byte 0x6b + 3423 05c5 02 .uleb128 0x2 + 3424 05c6 91 .byte 0x91 + 3425 05c7 77 .sleb128 -9 + 3426 05c8 00 .byte 0 + 3427 05c9 0D .uleb128 0xd + 3428 05ca F9040000 .4byte .LASF68 + 3429 05ce 01 .byte 0x1 + 3430 05cf 4D0A .2byte 0xa4d + 3431 05d1 00000000 .4byte .LFB25 + 3432 05d5 16000000 .4byte .LFE25-.LFB25 + 3433 05d9 01 .uleb128 0x1 + 3434 05da 9C .byte 0x9c + 3435 05db EF050000 .4byte 0x5ef + 3436 05df 0B .uleb128 0xb + 3437 05e0 4A050000 .4byte .LASF44 + 3438 05e4 01 .byte 0x1 + 3439 05e5 4D0A .2byte 0xa4d + 3440 05e7 6B000000 .4byte 0x6b + 3441 05eb 02 .uleb128 0x2 + 3442 05ec 91 .byte 0x91 + 3443 05ed 77 .sleb128 -9 + 3444 05ee 00 .byte 0 + 3445 05ef 0F .uleb128 0xf + 3446 05f0 B9000000 .4byte .LASF69 + 3447 05f4 01 .byte 0x1 + 3448 05f5 650A .2byte 0xa65 + 3449 05f7 00000000 .4byte .LFB26 + 3450 05fb 24000000 .4byte .LFE26-.LFB26 + 3451 05ff 01 .uleb128 0x1 + 3452 0600 9C .byte 0x9c + 3453 0601 0A .uleb128 0xa + 3454 0602 BB050000 .4byte .LASF70 + 3455 0606 01 .byte 0x1 + 3456 0607 790A .2byte 0xa79 + 3457 0609 00000000 .4byte .LFB27 + 3458 060d 4C000000 .4byte .LFE27-.LFB27 + 3459 0611 01 .uleb128 0x1 + 3460 0612 9C .byte 0x9c + 3461 0613 27060000 .4byte 0x627 + 3462 0617 0B .uleb128 0xb + 3463 0618 DD040000 .4byte .LASF71 + 3464 061c 01 .byte 0x1 + 3465 061d 790A .2byte 0xa79 + 3466 061f 83000000 .4byte 0x83 + 3467 0623 02 .uleb128 0x2 + 3468 0624 91 .byte 0x91 + 3469 0625 74 .sleb128 -12 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 117 + + + 3470 0626 00 .byte 0 + 3471 0627 0A .uleb128 0xa + 3472 0628 40050000 .4byte .LASF72 + 3473 062c 01 .byte 0x1 + 3474 062d 900A .2byte 0xa90 + 3475 062f 00000000 .4byte .LFB28 + 3476 0633 28000000 .4byte .LFE28-.LFB28 + 3477 0637 01 .uleb128 0x1 + 3478 0638 9C .byte 0x9c + 3479 0639 4D060000 .4byte 0x64d + 3480 063d 0B .uleb128 0xb + 3481 063e 53060000 .4byte .LASF73 + 3482 0642 01 .byte 0x1 + 3483 0643 900A .2byte 0xa90 + 3484 0645 77000000 .4byte 0x77 + 3485 0649 02 .uleb128 0x2 + 3486 064a 91 .byte 0x91 + 3487 064b 76 .sleb128 -10 + 3488 064c 00 .byte 0 + 3489 064d 0A .uleb128 0xa + 3490 064e 0F010000 .4byte .LASF74 + 3491 0652 01 .byte 0x1 + 3492 0653 9E0A .2byte 0xa9e + 3493 0655 00000000 .4byte .LFB29 + 3494 0659 84000000 .4byte .LFE29-.LFB29 + 3495 065d 01 .uleb128 0x1 + 3496 065e 9C .byte 0x9c + 3497 065f 73060000 .4byte 0x673 + 3498 0663 0B .uleb128 0xb + 3499 0664 0A010000 .4byte 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.byte 0x91 + 3531 06a7 74 .sleb128 -12 + 3532 06a8 00 .byte 0 + 3533 06a9 12 .uleb128 0x12 + 3534 06aa 63050000 .4byte .LASF77 + 3535 06ae 01 .byte 0x1 + 3536 06af F90A .2byte 0xaf9 + 3537 06b1 00000000 .4byte .LFB32 + 3538 06b5 20000000 .4byte .LFE32-.LFB32 + 3539 06b9 01 .uleb128 0x1 + 3540 06ba 9C .byte 0x9c + 3541 06bb 0F .uleb128 0xf + 3542 06bc FC050000 .4byte .LASF78 + 3543 06c0 01 .byte 0x1 + 3544 06c1 0A0B .2byte 0xb0a + 3545 06c3 00000000 .4byte .LFB33 + 3546 06c7 1C000000 .4byte .LFE33-.LFB33 + 3547 06cb 01 .uleb128 0x1 + 3548 06cc 9C .byte 0x9c + 3549 06cd 0F .uleb128 0xf + 3550 06ce C9000000 .4byte .LASF79 + 3551 06d2 01 .byte 0x1 + 3552 06d3 1A0B .2byte 0xb1a + 3553 06d5 00000000 .4byte .LFB34 + 3554 06d9 1C000000 .4byte .LFE34-.LFB34 + 3555 06dd 01 .uleb128 0x1 + 3556 06de 9C .byte 0x9c + 3557 06df 0F .uleb128 0xf + 3558 06e0 C3050000 .4byte .LASF80 + 3559 06e4 01 .byte 0x1 + 3560 06e5 2A0B .2byte 0xb2a + 3561 06e7 00000000 .4byte .LFB35 + 3562 06eb 1C000000 .4byte .LFE35-.LFB35 + 3563 06ef 01 .uleb128 0x1 + 3564 06f0 9C .byte 0x9c + 3565 06f1 0D .uleb128 0xd + 3566 06f2 67060000 .4byte .LASF81 + 3567 06f6 01 .byte 0x1 + 3568 06f7 3B0B .2byte 0xb3b + 3569 06f9 00000000 .4byte .LFB36 + 3570 06fd 20000000 .4byte .LFE36-.LFB36 + 3571 0701 01 .uleb128 0x1 + 3572 0702 9C .byte 0x9c + 3573 0703 17070000 .4byte 0x717 + 3574 0707 0B .uleb128 0xb + 3575 0708 53020000 .4byte .LASF61 + 3576 070c 01 .byte 0x1 + 3577 070d 3B0B .2byte 0xb3b + 3578 070f 83000000 .4byte 0x83 + 3579 0713 02 .uleb128 0x2 + 3580 0714 91 .byte 0x91 + 3581 0715 74 .sleb128 -12 + 3582 0716 00 .byte 0 + 3583 0717 10 .uleb128 0x10 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 119 + + + 3584 0718 2A010000 .4byte .LASF83 + 3585 071c 01 .byte 0x1 + 3586 071d 4B0B .2byte 0xb4b + 3587 071f 83000000 .4byte 0x83 + 3588 0723 00000000 .4byte .LFB37 + 3589 0727 18000000 .4byte .LFE37-.LFB37 + 3590 072b 01 .uleb128 0x1 + 3591 072c 9C .byte 0x9c + 3592 072d 10 .uleb128 0x10 + 3593 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.LFE41-.LFB41 + 3625 077f 01 .uleb128 0x1 + 3626 0780 9C .byte 0x9c + 3627 0781 B3070000 .4byte 0x7b3 + 3628 0785 0B .uleb128 0xb + 3629 0786 1C030000 .4byte .LASF51 + 3630 078a 01 .byte 0x1 + 3631 078b DB0B .2byte 0xbdb + 3632 078d 83000000 .4byte 0x83 + 3633 0791 02 .uleb128 0x2 + 3634 0792 91 .byte 0x91 + 3635 0793 6C .sleb128 -20 + 3636 0794 0B .uleb128 0xb + 3637 0795 5C040000 .4byte .LASF88 + 3638 0799 01 .byte 0x1 + 3639 079a DB0B .2byte 0xbdb + 3640 079c E7000000 .4byte 0xe7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 120 + + + 3641 07a0 02 .uleb128 0x2 + 3642 07a1 91 .byte 0x91 + 3643 07a2 68 .sleb128 -24 + 3644 07a3 0C .uleb128 0xc + 3645 07a4 5A000000 .4byte .LASF89 + 3646 07a8 01 .byte 0x1 + 3647 07a9 DD0B .2byte 0xbdd + 3648 07ab E7000000 .4byte 0xe7 + 3649 07af 02 .uleb128 0x2 + 3650 07b0 91 .byte 0x91 + 3651 07b1 74 .sleb128 -12 + 3652 07b2 00 .byte 0 + 3653 07b3 11 .uleb128 0x11 + 3654 07b4 53010000 .4byte .LASF90 + 3655 07b8 01 .byte 0x1 + 3656 07b9 F30B .2byte 0xbf3 + 3657 07bb E7000000 .4byte 0xe7 + 3658 07bf 00000000 .4byte .LFB42 + 3659 07c3 1C000000 .4byte .LFE42-.LFB42 + 3660 07c7 01 .uleb128 0x1 + 3661 07c8 9C .byte 0x9c + 3662 07c9 DD070000 .4byte 0x7dd + 3663 07cd 0B .uleb128 0xb + 3664 07ce 1C030000 .4byte .LASF51 + 3665 07d2 01 .byte 0x1 + 3666 07d3 F30B .2byte 0xbf3 + 3667 07d5 83000000 .4byte 0x83 + 3668 07d9 02 .uleb128 0x2 + 3669 07da 91 .byte 0x91 + 3670 07db 74 .sleb128 -12 + 3671 07dc 00 .byte 0 + 3672 07dd 14 .uleb128 0x14 + 3673 07de 7A060000 .4byte .LASF104 + 3674 07e2 01 .byte 0x1 + 3675 07e3 000C .2byte 0xc00 + 3676 07e5 00000000 .4byte .LFB43 + 3677 07e9 44000000 .4byte .LFE43-.LFB43 + 3678 07ed 01 .uleb128 0x1 + 3679 07ee 9C .byte 0x9c + 3680 07ef 01080000 .4byte 0x801 + 3681 07f3 13 .uleb128 0x13 + 3682 07f4 6900 .ascii "i\000" + 3683 07f6 01 .byte 0x1 + 3684 07f7 020C .2byte 0xc02 + 3685 07f9 83000000 .4byte 0x83 + 3686 07fd 02 .uleb128 0x2 + 3687 07fe 91 .byte 0x91 + 3688 07ff 74 .sleb128 -12 + 3689 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.byte 0x1 + 3721 0843 22 .byte 0x22 + 3722 0844 2D080000 .4byte 0x82d + 3723 0848 05 .uleb128 0x5 + 3724 0849 03 .byte 0x3 + 3725 084a 00000000 .4byte CySysTickCallbacks + 3726 084e 18 .uleb128 0x18 + 3727 084f 88040000 .4byte .LASF94 + 3728 0853 01 .byte 0x1 + 3729 0854 1B .byte 0x1b + 3730 0855 83000000 .4byte 0x83 + 3731 0859 05 .uleb128 0x5 + 3732 085a 03 .byte 0x3 + 3733 085b 00000000 .4byte cydelayFreqHz + 3734 085f 18 .uleb128 0x18 + 3735 0860 6E010000 .4byte .LASF95 + 3736 0864 01 .byte 0x1 + 3737 0865 1C .byte 0x1c + 3738 0866 83000000 .4byte 0x83 + 3739 086a 05 .uleb128 0x5 + 3740 086b 03 .byte 0x3 + 3741 086c 00000000 .4byte cydelayFreqKhz + 3742 0870 18 .uleb128 0x18 + 3743 0871 ED050000 .4byte .LASF96 + 3744 0875 01 .byte 0x1 + 3745 0876 1D .byte 0x1d + 3746 0877 6B000000 .4byte 0x6b + 3747 087b 05 .uleb128 0x5 + 3748 087c 03 .byte 0x3 + 3749 087d 00000000 .4byte cydelayFreqMhz + 3750 0881 18 .uleb128 0x18 + 3751 0882 38020000 .4byte .LASF97 + 3752 0886 01 .byte 0x1 + 3753 0887 1E .byte 0x1e + 3754 0888 83000000 .4byte 0x83 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 122 + + + 3755 088c 05 .uleb128 0x5 + 3756 088d 03 .byte 0x3 + 3757 088e 00000000 .4byte cydelay32kMs + 3758 0892 18 .uleb128 0x18 + 3759 0893 9B000000 .4byte .LASF98 + 3760 0897 01 .byte 0x1 + 3761 0898 36 .byte 0x36 + 3762 0899 83000000 .4byte 0x83 + 3763 089d 05 .uleb128 0x5 + 3764 089e 03 .byte 0x3 + 3765 089f 00000000 .4byte CySysTickInitVar + 3766 08a3 15 .uleb128 0x15 + 3767 08a4 B3080000 .4byte 0x8b3 + 3768 08a8 B3080000 .4byte 0x8b3 + 3769 08ac 16 .uleb128 0x16 + 3770 08ad E0000000 .4byte 0xe0 + 3771 08b1 2D .byte 0x2d + 3772 08b2 00 .byte 0 + 3773 08b3 19 .uleb128 0x19 + 3774 08b4 6B000000 .4byte 0x6b + 3775 08b8 18 .uleb128 0x18 + 3776 08b9 65040000 .4byte .LASF99 + 3777 08bd 01 .byte 0x1 + 3778 08be 3B .byte 0x3b + 3779 08bf C9080000 .4byte 0x8c9 + 3780 08c3 05 .uleb128 0x5 + 3781 08c4 03 .byte 0x3 + 3782 08c5 00000000 .4byte cyImoFreqMhz2Reg + 3783 08c9 19 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3956 00a2 3B .uleb128 0x3b + 3957 00a3 05 .uleb128 0x5 + 3958 00a4 49 .uleb128 0x49 + 3959 00a5 13 .uleb128 0x13 + 3960 00a6 02 .uleb128 0x2 + 3961 00a7 18 .uleb128 0x18 + 3962 00a8 00 .byte 0 + 3963 00a9 00 .byte 0 + 3964 00aa 0D .uleb128 0xd + 3965 00ab 2E .uleb128 0x2e + 3966 00ac 01 .byte 0x1 + 3967 00ad 3F .uleb128 0x3f + 3968 00ae 19 .uleb128 0x19 + 3969 00af 03 .uleb128 0x3 + 3970 00b0 0E .uleb128 0xe + 3971 00b1 3A .uleb128 0x3a + 3972 00b2 0B .uleb128 0xb + 3973 00b3 3B .uleb128 0x3b + 3974 00b4 05 .uleb128 0x5 + 3975 00b5 27 .uleb128 0x27 + 3976 00b6 19 .uleb128 0x19 + 3977 00b7 11 .uleb128 0x11 + 3978 00b8 01 .uleb128 0x1 + 3979 00b9 12 .uleb128 0x12 + 3980 00ba 06 .uleb128 0x6 + 3981 00bb 40 .uleb128 0x40 + 3982 00bc 18 .uleb128 0x18 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 126 + + + 3983 00bd 9742 .uleb128 0x2117 + 3984 00bf 19 .uleb128 0x19 + 3985 00c0 01 .uleb128 0x1 + 3986 00c1 13 .uleb128 0x13 + 3987 00c2 00 .byte 0 + 3988 00c3 00 .byte 0 + 3989 00c4 0E .uleb128 0xe + 3990 00c5 2E .uleb128 0x2e + 3991 00c6 01 .byte 0x1 + 3992 00c7 3F .uleb128 0x3f + 3993 00c8 19 .uleb128 0x19 + 3994 00c9 03 .uleb128 0x3 + 3995 00ca 0E .uleb128 0xe + 3996 00cb 3A .uleb128 0x3a + 3997 00cc 0B .uleb128 0xb + 3998 00cd 3B .uleb128 0x3b + 3999 00ce 05 .uleb128 0x5 + 4000 00cf 27 .uleb128 0x27 + 4001 00d0 19 .uleb128 0x19 + 4002 00d1 49 .uleb128 0x49 + 4003 00d2 13 .uleb128 0x13 + 4004 00d3 11 .uleb128 0x11 + 4005 00d4 01 .uleb128 0x1 + 4006 00d5 12 .uleb128 0x12 + 4007 00d6 06 .uleb128 0x6 + 4008 00d7 40 .uleb128 0x40 + 4009 00d8 18 .uleb128 0x18 + 4010 00d9 9642 .uleb128 0x2116 + 4011 00db 19 .uleb128 0x19 + 4012 00dc 01 .uleb128 0x1 + 4013 00dd 13 .uleb128 0x13 + 4014 00de 00 .byte 0 + 4015 00df 00 .byte 0 + 4016 00e0 0F .uleb128 0xf + 4017 00e1 2E .uleb128 0x2e + 4018 00e2 00 .byte 0 + 4019 00e3 3F .uleb128 0x3f + 4020 00e4 19 .uleb128 0x19 + 4021 00e5 03 .uleb128 0x3 + 4022 00e6 0E .uleb128 0xe + 4023 00e7 3A .uleb128 0x3a + 4024 00e8 0B .uleb128 0xb + 4025 00e9 3B .uleb128 0x3b + 4026 00ea 05 .uleb128 0x5 + 4027 00eb 27 .uleb128 0x27 + 4028 00ec 19 .uleb128 0x19 + 4029 00ed 11 .uleb128 0x11 + 4030 00ee 01 .uleb128 0x1 + 4031 00ef 12 .uleb128 0x12 + 4032 00f0 06 .uleb128 0x6 + 4033 00f1 40 .uleb128 0x40 + 4034 00f2 18 .uleb128 0x18 + 4035 00f3 9742 .uleb128 0x2117 + 4036 00f5 19 .uleb128 0x19 + 4037 00f6 00 .byte 0 + 4038 00f7 00 .byte 0 + 4039 00f8 10 .uleb128 0x10 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 127 + + + 4040 00f9 2E .uleb128 0x2e + 4041 00fa 00 .byte 0 + 4042 00fb 3F .uleb128 0x3f + 4043 00fc 19 .uleb128 0x19 + 4044 00fd 03 .uleb128 0x3 + 4045 00fe 0E .uleb128 0xe + 4046 00ff 3A .uleb128 0x3a + 4047 0100 0B .uleb128 0xb + 4048 0101 3B .uleb128 0x3b + 4049 0102 05 .uleb128 0x5 + 4050 0103 27 .uleb128 0x27 + 4051 0104 19 .uleb128 0x19 + 4052 0105 49 .uleb128 0x49 + 4053 0106 13 .uleb128 0x13 + 4054 0107 11 .uleb128 0x11 + 4055 0108 01 .uleb128 0x1 + 4056 0109 12 .uleb128 0x12 + 4057 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.uleb128 0x2e + 4093 0130 00 .byte 0 + 4094 0131 3F .uleb128 0x3f + 4095 0132 19 .uleb128 0x19 + 4096 0133 03 .uleb128 0x3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 128 + + + 4097 0134 0E .uleb128 0xe + 4098 0135 3A .uleb128 0x3a + 4099 0136 0B .uleb128 0xb + 4100 0137 3B .uleb128 0x3b + 4101 0138 05 .uleb128 0x5 + 4102 0139 27 .uleb128 0x27 + 4103 013a 19 .uleb128 0x19 + 4104 013b 11 .uleb128 0x11 + 4105 013c 01 .uleb128 0x1 + 4106 013d 12 .uleb128 0x12 + 4107 013e 06 .uleb128 0x6 + 4108 013f 40 .uleb128 0x40 + 4109 0140 18 .uleb128 0x18 + 4110 0141 9642 .uleb128 0x2116 + 4111 0143 19 .uleb128 0x19 + 4112 0144 00 .byte 0 + 4113 0145 00 .byte 0 + 4114 0146 13 .uleb128 0x13 + 4115 0147 34 .uleb128 0x34 + 4116 0148 00 .byte 0 + 4117 0149 03 .uleb128 0x3 + 4118 014a 08 .uleb128 0x8 + 4119 014b 3A .uleb128 0x3a + 4120 014c 0B .uleb128 0xb + 4121 014d 3B .uleb128 0x3b + 4122 014e 05 .uleb128 0x5 + 4123 014f 49 .uleb128 0x49 + 4124 0150 13 .uleb128 0x13 + 4125 0151 02 .uleb128 0x2 + 4126 0152 18 .uleb128 0x18 + 4127 0153 00 .byte 0 + 4128 0154 00 .byte 0 + 4129 0155 14 .uleb128 0x14 + 4130 0156 2E .uleb128 0x2e + 4131 0157 01 .byte 0x1 + 4132 0158 03 .uleb128 0x3 + 4133 0159 0E .uleb128 0xe + 4134 015a 3A .uleb128 0x3a + 4135 015b 0B .uleb128 0xb + 4136 015c 3B .uleb128 0x3b + 4137 015d 05 .uleb128 0x5 + 4138 015e 27 .uleb128 0x27 + 4139 015f 19 .uleb128 0x19 + 4140 0160 11 .uleb128 0x11 + 4141 0161 01 .uleb128 0x1 + 4142 0162 12 .uleb128 0x12 + 4143 0163 06 .uleb128 0x6 + 4144 0164 40 .uleb128 0x40 + 4145 0165 18 .uleb128 0x18 + 4146 0166 9642 .uleb128 0x2116 + 4147 0168 19 .uleb128 0x19 + 4148 0169 01 .uleb128 0x1 + 4149 016a 13 .uleb128 0x13 + 4150 016b 00 .byte 0 + 4151 016c 00 .byte 0 + 4152 016d 15 .uleb128 0x15 + 4153 016e 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 129 + + + 4154 016f 01 .byte 0x1 + 4155 0170 49 .uleb128 0x49 + 4156 0171 13 .uleb128 0x13 + 4157 0172 01 .uleb128 0x1 + 4158 0173 13 .uleb128 0x13 + 4159 0174 00 .byte 0 + 4160 0175 00 .byte 0 + 4161 0176 16 .uleb128 0x16 + 4162 0177 21 .uleb128 0x21 + 4163 0178 00 .byte 0 + 4164 0179 49 .uleb128 0x49 + 4165 017a 13 .uleb128 0x13 + 4166 017b 2F .uleb128 0x2f + 4167 017c 0B .uleb128 0xb + 4168 017d 00 .byte 0 + 4169 017e 00 .byte 0 + 4170 017f 17 .uleb128 0x17 + 4171 0180 34 .uleb128 0x34 + 4172 0181 00 .byte 0 + 4173 0182 03 .uleb128 0x3 + 4174 0183 0E .uleb128 0xe + 4175 0184 3A .uleb128 0x3a + 4176 0185 0B .uleb128 0xb + 4177 0186 3B .uleb128 0x3b + 4178 0187 0B .uleb128 0xb + 4179 0188 49 .uleb128 0x49 + 4180 0189 13 .uleb128 0x13 + 4181 018a 02 .uleb128 0x2 + 4182 018b 18 .uleb128 0x18 + 4183 018c 00 .byte 0 + 4184 018d 00 .byte 0 + 4185 018e 18 .uleb128 0x18 + 4186 018f 34 .uleb128 0x34 + 4187 0190 00 .byte 0 + 4188 0191 03 .uleb128 0x3 + 4189 0192 0E .uleb128 0xe + 4190 0193 3A .uleb128 0x3a + 4191 0194 0B .uleb128 0xb + 4192 0195 3B .uleb128 0x3b + 4193 0196 0B .uleb128 0xb + 4194 0197 49 .uleb128 0x49 + 4195 0198 13 .uleb128 0x13 + 4196 0199 3F .uleb128 0x3f + 4197 019a 19 .uleb128 0x19 + 4198 019b 02 .uleb128 0x2 + 4199 019c 18 .uleb128 0x18 + 4200 019d 00 .byte 0 + 4201 019e 00 .byte 0 + 4202 019f 19 .uleb128 0x19 + 4203 01a0 26 .uleb128 0x26 + 4204 01a1 00 .byte 0 + 4205 01a2 49 .uleb128 0x49 + 4206 01a3 13 .uleb128 0x13 + 4207 01a4 00 .byte 0 + 4208 01a5 00 .byte 0 + 4209 01a6 00 .byte 0 + 4210 .section .debug_aranges,"",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 130 + + + 4211 0000 7C010000 .4byte 0x17c + 4212 0004 0200 .2byte 0x2 + 4213 0006 00000000 .4byte .Ldebug_info0 + 4214 000a 04 .byte 0x4 + 4215 000b 00 .byte 0 + 4216 000c 0000 .2byte 0 + 4217 000e 0000 .2byte 0 + 4218 0010 00000000 .4byte .LFB0 + 4219 0014 1C000000 .4byte .LFE0-.LFB0 + 4220 0018 00000000 .4byte .LFB1 + 4221 001c 1C000000 .4byte .LFE1-.LFB1 + 4222 0020 00000000 .4byte .LFB2 + 4223 0024 48000000 .4byte .LFE2-.LFB2 + 4224 0028 00000000 .4byte .LFB3 + 4225 002c 50000000 .4byte .LFE3-.LFB3 + 4226 0030 00000000 .4byte .LFB4 + 4227 0034 34000000 .4byte .LFE4-.LFB4 + 4228 0038 00000000 .4byte .LFB5 + 4229 003c 48000000 .4byte .LFE5-.LFB5 + 4230 0040 00000000 .4byte .LFB6 + 4231 0044 E4010000 .4byte .LFE6-.LFB6 + 4232 0048 00000000 .4byte .LFB7 + 4233 004c 64000000 .4byte .LFE7-.LFB7 + 4234 0050 00000000 .4byte .LFB8 + 4235 0054 2C000000 .4byte .LFE8-.LFB8 + 4236 0058 00000000 .4byte .LFB9 + 4237 005c 18000000 .4byte .LFE9-.LFB9 + 4238 0060 00000000 .4byte .LFB10 + 4239 0064 14000000 .4byte .LFE10-.LFB10 + 4240 0068 00000000 .4byte .LFB11 + 4241 006c 30000000 .4byte .LFE11-.LFB11 + 4242 0070 00000000 .4byte .LFB12 + 4243 0074 24000000 .4byte .LFE12-.LFB12 + 4244 0078 00000000 .4byte .LFB13 + 4245 007c 1C000000 .4byte .LFE13-.LFB13 + 4246 0080 00000000 .4byte .LFB14 + 4247 0084 48000000 .4byte .LFE14-.LFB14 + 4248 0088 00000000 .4byte .LFB15 + 4249 008c 34000000 .4byte .LFE15-.LFB15 + 4250 0090 00000000 .4byte .LFB16 + 4251 0094 4C000000 .4byte .LFE16-.LFB16 + 4252 0098 00000000 .4byte .LFB17 + 4253 009c 36000000 .4byte .LFE17-.LFB17 + 4254 00a0 00000000 .4byte .LFB18 + 4255 00a4 A8000000 .4byte .LFE18-.LFB18 + 4256 00a8 00000000 .4byte .LFB19 + 4257 00ac 58000000 .4byte .LFE19-.LFB19 + 4258 00b0 00000000 .4byte .LFB20 + 4259 00b4 2C000000 .4byte .LFE20-.LFB20 + 4260 00b8 00000000 .4byte .LFB21 + 4261 00bc 30000000 .4byte .LFE21-.LFB21 + 4262 00c0 00000000 .4byte .LFB22 + 4263 00c4 2C000000 .4byte .LFE22-.LFB22 + 4264 00c8 00000000 .4byte .LFB23 + 4265 00cc 2C000000 .4byte .LFE23-.LFB23 + 4266 00d0 00000000 .4byte .LFB24 + 4267 00d4 2C000000 .4byte .LFE24-.LFB24 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 131 + + + 4268 00d8 00000000 .4byte .LFB25 + 4269 00dc 16000000 .4byte .LFE25-.LFB25 + 4270 00e0 00000000 .4byte .LFB26 + 4271 00e4 24000000 .4byte .LFE26-.LFB26 + 4272 00e8 00000000 .4byte .LFB27 + 4273 00ec 4C000000 .4byte .LFE27-.LFB27 + 4274 00f0 00000000 .4byte .LFB28 + 4275 00f4 28000000 .4byte .LFE28-.LFB28 + 4276 00f8 00000000 .4byte .LFB29 + 4277 00fc 84000000 .4byte .LFE29-.LFB29 + 4278 0100 00000000 .4byte .LFB30 + 4279 0104 24000000 .4byte .LFE30-.LFB30 + 4280 0108 00000000 .4byte .LFB31 + 4281 010c 5C000000 .4byte .LFE31-.LFB31 + 4282 0110 00000000 .4byte .LFB32 + 4283 0114 20000000 .4byte .LFE32-.LFB32 + 4284 0118 00000000 .4byte .LFB33 + 4285 011c 1C000000 .4byte .LFE33-.LFB33 + 4286 0120 00000000 .4byte .LFB34 + 4287 0124 1C000000 .4byte .LFE34-.LFB34 + 4288 0128 00000000 .4byte .LFB35 + 4289 012c 1C000000 .4byte .LFE35-.LFB35 + 4290 0130 00000000 .4byte .LFB36 + 4291 0134 20000000 .4byte .LFE36-.LFB36 + 4292 0138 00000000 .4byte .LFB37 + 4293 013c 18000000 .4byte .LFE37-.LFB37 + 4294 0140 00000000 .4byte .LFB38 + 4295 0144 18000000 .4byte .LFE38-.LFB38 + 4296 0148 00000000 .4byte .LFB39 + 4297 014c 18000000 .4byte .LFE39-.LFB39 + 4298 0150 00000000 .4byte .LFB40 + 4299 0154 14000000 .4byte .LFE40-.LFB40 + 4300 0158 00000000 .4byte .LFB41 + 4301 015c 2C000000 .4byte .LFE41-.LFB41 + 4302 0160 00000000 .4byte .LFB42 + 4303 0164 1C000000 .4byte .LFE42-.LFB42 + 4304 0168 00000000 .4byte .LFB43 + 4305 016c 44000000 .4byte .LFE43-.LFB43 + 4306 0170 00000000 .4byte .LFB44 + 4307 0174 C0000000 .4byte .LFE44-.LFB44 + 4308 0178 00000000 .4byte 0 + 4309 017c 00000000 .4byte 0 + 4310 .section .debug_ranges,"",%progbits + 4311 .Ldebug_ranges0: + 4312 0000 00000000 .4byte .LFB0 + 4313 0004 1C000000 .4byte .LFE0 + 4314 0008 00000000 .4byte .LFB1 + 4315 000c 1C000000 .4byte .LFE1 + 4316 0010 00000000 .4byte .LFB2 + 4317 0014 48000000 .4byte .LFE2 + 4318 0018 00000000 .4byte .LFB3 + 4319 001c 50000000 .4byte .LFE3 + 4320 0020 00000000 .4byte .LFB4 + 4321 0024 34000000 .4byte .LFE4 + 4322 0028 00000000 .4byte .LFB5 + 4323 002c 48000000 .4byte .LFE5 + 4324 0030 00000000 .4byte .LFB6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 132 + + + 4325 0034 E4010000 .4byte .LFE6 + 4326 0038 00000000 .4byte .LFB7 + 4327 003c 64000000 .4byte .LFE7 + 4328 0040 00000000 .4byte .LFB8 + 4329 0044 2C000000 .4byte .LFE8 + 4330 0048 00000000 .4byte .LFB9 + 4331 004c 18000000 .4byte .LFE9 + 4332 0050 00000000 .4byte .LFB10 + 4333 0054 14000000 .4byte .LFE10 + 4334 0058 00000000 .4byte .LFB11 + 4335 005c 30000000 .4byte .LFE11 + 4336 0060 00000000 .4byte .LFB12 + 4337 0064 24000000 .4byte .LFE12 + 4338 0068 00000000 .4byte .LFB13 + 4339 006c 1C000000 .4byte .LFE13 + 4340 0070 00000000 .4byte .LFB14 + 4341 0074 48000000 .4byte .LFE14 + 4342 0078 00000000 .4byte .LFB15 + 4343 007c 34000000 .4byte .LFE15 + 4344 0080 00000000 .4byte .LFB16 + 4345 0084 4C000000 .4byte .LFE16 + 4346 0088 00000000 .4byte .LFB17 + 4347 008c 36000000 .4byte .LFE17 + 4348 0090 00000000 .4byte .LFB18 + 4349 0094 A8000000 .4byte .LFE18 + 4350 0098 00000000 .4byte .LFB19 + 4351 009c 58000000 .4byte .LFE19 + 4352 00a0 00000000 .4byte .LFB20 + 4353 00a4 2C000000 .4byte .LFE20 + 4354 00a8 00000000 .4byte .LFB21 + 4355 00ac 30000000 .4byte .LFE21 + 4356 00b0 00000000 .4byte .LFB22 + 4357 00b4 2C000000 .4byte .LFE22 + 4358 00b8 00000000 .4byte .LFB23 + 4359 00bc 2C000000 .4byte .LFE23 + 4360 00c0 00000000 .4byte .LFB24 + 4361 00c4 2C000000 .4byte .LFE24 + 4362 00c8 00000000 .4byte .LFB25 + 4363 00cc 16000000 .4byte .LFE25 + 4364 00d0 00000000 .4byte .LFB26 + 4365 00d4 24000000 .4byte .LFE26 + 4366 00d8 00000000 .4byte .LFB27 + 4367 00dc 4C000000 .4byte .LFE27 + 4368 00e0 00000000 .4byte .LFB28 + 4369 00e4 28000000 .4byte .LFE28 + 4370 00e8 00000000 .4byte .LFB29 + 4371 00ec 84000000 .4byte .LFE29 + 4372 00f0 00000000 .4byte .LFB30 + 4373 00f4 24000000 .4byte .LFE30 + 4374 00f8 00000000 .4byte .LFB31 + 4375 00fc 5C000000 .4byte .LFE31 + 4376 0100 00000000 .4byte .LFB32 + 4377 0104 20000000 .4byte .LFE32 + 4378 0108 00000000 .4byte .LFB33 + 4379 010c 1C000000 .4byte .LFE33 + 4380 0110 00000000 .4byte .LFB34 + 4381 0114 1C000000 .4byte .LFE34 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 133 + + + 4382 0118 00000000 .4byte .LFB35 + 4383 011c 1C000000 .4byte .LFE35 + 4384 0120 00000000 .4byte .LFB36 + 4385 0124 20000000 .4byte .LFE36 + 4386 0128 00000000 .4byte .LFB37 + 4387 012c 18000000 .4byte .LFE37 + 4388 0130 00000000 .4byte .LFB38 + 4389 0134 18000000 .4byte .LFE38 + 4390 0138 00000000 .4byte .LFB39 + 4391 013c 18000000 .4byte .LFE39 + 4392 0140 00000000 .4byte .LFB40 + 4393 0144 14000000 .4byte .LFE40 + 4394 0148 00000000 .4byte .LFB41 + 4395 014c 2C000000 .4byte .LFE41 + 4396 0150 00000000 .4byte .LFB42 + 4397 0154 1C000000 .4byte .LFE42 + 4398 0158 00000000 .4byte .LFB43 + 4399 015c 44000000 .4byte .LFE43 + 4400 0160 00000000 .4byte .LFB44 + 4401 0164 C0000000 .4byte .LFE44 + 4402 0168 00000000 .4byte 0 + 4403 016c 00000000 .4byte 0 + 4404 .section .debug_line,"",%progbits + 4405 .Ldebug_line0: + 4406 0000 77040000 .section .debug_str,"MS",%progbits,1 + 4406 02004D00 + 4406 00000201 + 4406 FB0E0D00 + 4406 01010101 + 4407 .LASF54: + 4408 0000 72616D56 .ascii "ramVectorTable\000" + 4408 6563746F + 4408 72546162 + 4408 6C6500 + 4409 .LASF34: + 4410 000f 62675472 .ascii "bgTrim4\000" + 4410 696D3400 + 4411 .LASF10: + 4412 0017 75696E74 .ascii "uint16\000" + 4412 313600 + 4413 .LASF47: + 4414 001e 696E7453 .ascii "intState\000" + 4414 74617465 + 4414 00 + 4415 .LASF25: + 4416 0027 43795379 .ascii "CySysClkWriteHfclkDirect\000" + 4416 73436C6B + 4416 57726974 + 4416 65486663 + 4416 6C6B4469 + 4417 .LASF100: + 4418 0040 43795379 .ascii "CySysClkPumpConfig\000" + 4418 73436C6B + 4418 50756D70 + 4418 436F6E66 + 4418 696700 + 4419 .LASF53: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 134 + + + 4420 0053 6F6C6449 .ascii "oldIsr\000" + 4420 737200 + 4421 .LASF89: + 4422 005a 72657456 .ascii "retVal\000" + 4422 616C00 + 4423 .LASF46: + 4424 0061 43794469 .ascii "CyDisableInts\000" + 4424 7361626C + 4424 65496E74 + 4424 7300 + 4425 .LASF37: + 4426 006f 63757272 .ascii "currentImoTrim2Value\000" + 4426 656E7449 + 4426 6D6F5472 + 4426 696D3256 + 4426 616C7565 + 4427 .LASF7: + 4428 0084 6C6F6E67 .ascii "long long unsigned int\000" + 4428 206C6F6E + 4428 6720756E + 4428 7369676E + 4428 65642069 + 4429 .LASF98: + 4430 009b 43795379 .ascii "CySysTickInitVar\000" + 4430 73546963 + 4430 6B496E69 + 4430 74566172 + 4430 00 + 4431 .LASF48: + 4432 00ac 4379456E .ascii "CyEnableInts\000" + 4432 61626C65 + 4432 496E7473 + 4432 00 + 4433 .LASF69: + 4434 00b9 4379536F .ascii "CySoftwareReset\000" + 4434 66747761 + 4434 72655265 + 4434 73657400 + 4435 .LASF79: + 4436 00c9 43795379 .ascii "CySysTickEnableInterrupt\000" + 4436 73546963 + 4436 6B456E61 + 4436 626C6549 + 4436 6E746572 + 4437 .LASF64: + 4438 00e2 4379496E .ascii "CyIntGetState\000" + 4438 74476574 + 4438 53746174 + 4438 6500 + 4439 .LASF6: + 4440 00f0 6C6F6E67 .ascii "long long int\000" + 4440 206C6F6E + 4440 6720696E + 4440 7400 + 4441 .LASF0: + 4442 00fe 7369676E .ascii "signed char\000" + 4442 65642063 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 135 + + + 4442 68617200 + 4443 .LASF33: + 4444 010a 66726571 .ascii "freq\000" + 4444 00 + 4445 .LASF74: + 4446 010f 43794465 .ascii "CyDelayFreq\000" + 4446 6C617946 + 4446 72657100 + 4447 .LASF23: + 4448 011b 696E7465 .ascii "interruptState\000" + 4448 72727570 + 4448 74537461 + 4448 746500 + 4449 .LASF83: + 4450 012a 43795379 .ascii "CySysTickGetReload\000" + 4450 73546963 + 4450 6B476574 + 4450 52656C6F + 4450 616400 + 4451 .LASF4: + 4452 013d 6C6F6E67 .ascii "long int\000" + 4452 20696E74 + 4452 00 + 4453 .LASF65: + 4454 0146 4379496E .ascii "CyIntDisable\000" + 4454 74446973 + 4454 61626C65 + 4454 00 + 4455 .LASF90: + 4456 0153 43795379 .ascii "CySysTickGetCallback\000" + 4456 73546963 + 4456 6B476574 + 4456 43616C6C + 4456 6261636B + 4457 .LASF9: + 4458 0168 75696E74 .ascii "uint8\000" + 4458 3800 + 4459 .LASF95: + 4460 016e 63796465 .ascii "cydelayFreqKhz\000" + 4460 6C617946 + 4460 7265714B + 4460 687A00 + 4461 .LASF28: + 4462 017d 656E6162 .ascii "enable\000" + 4462 6C6500 + 4463 .LASF13: + 4464 0184 646F7562 .ascii "double\000" + 4464 6C6500 + 4465 .LASF60: + 4466 018b 73686966 .ascii "shift\000" + 4466 7400 + 4467 .LASF41: + 4468 0191 43795379 .ascii "CySysLvdClearInterrupt\000" + 4468 734C7664 + 4468 436C6561 + 4468 72496E74 + 4468 65727275 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 136 + + + 4469 .LASF11: + 4470 01a8 75696E74 .ascii "uint32\000" + 4470 333200 + 4471 .LASF103: + 4472 01af 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 4472 73657273 + 4472 5C6A6167 + 4472 756D6965 + 4472 6C5C446F + 4473 01dd 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 4473 50536F43 + 4473 2D313031 + 4473 5C547261 + 4473 696E696E + 4474 .LASF49: + 4475 020a 6D61736B .ascii "mask\000" + 4475 00 + 4476 .LASF42: + 4477 020f 43795379 .ascii "CySysClkGetSysclkSource\000" + 4477 73436C6B + 4477 47657453 + 4477 7973636C + 4477 6B536F75 + 4478 .LASF62: + 4479 0227 4379496E .ascii "CyIntGetPriority\000" + 4479 74476574 + 4479 5072696F + 4479 72697479 + 4479 00 + 4480 .LASF97: + 4481 0238 63796465 .ascii "cydelay32kMs\000" + 4481 6C617933 + 4481 326B4D73 + 4481 00 + 4482 .LASF76: + 4483 0245 43795379 .ascii "CySysTickInit\000" + 4483 73546963 + 4483 6B496E69 + 4483 7400 + 4484 .LASF61: + 4485 0253 76616C75 .ascii "value\000" + 4485 6500 + 4486 .LASF91: + 4487 0259 43794765 .ascii "CyGetUniqueId\000" + 4487 74556E69 + 4487 71756549 + 4487 6400 + 4488 .LASF85: + 4489 0267 43795379 .ascii "CySysTickGetCountFlag\000" + 4489 73546963 + 4489 6B476574 + 4489 436F756E + 4489 74466C61 + 4490 .LASF8: + 4491 027d 756E7369 .ascii "unsigned int\000" + 4491 676E6564 + 4491 20696E74 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 137 + + + 4491 00 + 4492 .LASF86: + 4493 028a 43795379 .ascii "CySysTickClear\000" + 4493 73546963 + 4493 6B436C65 + 4493 617200 + 4494 .LASF5: + 4495 0299 6C6F6E67 .ascii "long unsigned int\000" + 4495 20756E73 + 4495 69676E65 + 4495 6420696E + 4495 7400 + 4496 .LASF82: + 4497 02ab 43795379 .ascii "CySysLvdGetInterruptSource\000" + 4497 734C7664 + 4497 47657449 + 4497 6E746572 + 4497 72757074 + 4498 .LASF22: + 4499 02c6 43795379 .ascii "CySysClkImoStop\000" + 4499 73436C6B + 4499 496D6F53 + 4499 746F7000 + 4500 .LASF66: + 4501 02d6 4379496E .ascii "CyIntSetPending\000" + 4501 74536574 + 4501 50656E64 + 4501 696E6700 + 4502 .LASF43: + 4503 02e6 43795379 .ascii "CySysGetResetReason\000" + 4503 73476574 + 4503 52657365 + 4503 74526561 + 4503 736F6E00 + 4504 .LASF3: + 4505 02fa 73686F72 .ascii "short unsigned int\000" + 4505 7420756E + 4505 7369676E + 4505 65642069 + 4505 6E7400 + 4506 .LASF56: + 4507 030d 4379496E .ascii "CyIntSetVector\000" + 4507 74536574 + 4507 56656374 + 4507 6F7200 + 4508 .LASF51: + 4509 031c 6E756D62 .ascii "number\000" + 4509 657200 + 4510 .LASF59: + 4511 0323 7072696F .ascii "priority\000" + 4511 72697479 + 4511 00 + 4512 .LASF32: + 4513 032c 43795379 .ascii "CySysClkWriteImoFreq\000" + 4513 73436C6B + 4513 57726974 + 4513 65496D6F + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 138 + + + 4513 46726571 + 4514 .LASF101: + 4515 0341 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 4515 43313120 + 4515 352E342E + 4515 31203230 + 4515 31363036 + 4516 0374 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 4516 20726576 + 4516 6973696F + 4516 6E203233 + 4516 37373135 + 4517 03a7 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 4517 66756E63 + 4517 74696F6E + 4517 2D736563 + 4517 74696F6E + 4518 .LASF50: + 4519 03cf 4379496E .ascii "CyIntSetSysVector\000" + 4519 74536574 + 4519 53797356 + 4519 6563746F + 4519 7200 + 4520 .LASF26: + 4521 03e1 43795379 .ascii "CySysEnablePumpClock\000" + 4521 73456E61 + 4521 626C6550 + 4521 756D7043 + 4521 6C6F636B + 4522 .LASF16: + 4523 03f6 72656733 .ascii "reg32\000" + 4523 3200 + 4524 .LASF75: + 4525 03fc 43795379 .ascii "CySysTickStart\000" + 4525 73546963 + 4525 6B537461 + 4525 727400 + 4526 .LASF45: + 4527 040b 72657475 .ascii "returnStatus\000" + 4527 726E5374 + 4527 61747573 + 4527 00 + 4528 .LASF19: + 4529 0418 73697A65 .ascii "sizetype\000" + 4529 74797065 + 4529 00 + 4530 .LASF67: + 4531 0421 4379496E .ascii "CyIntClearPending\000" + 4531 74436C65 + 4531 61725065 + 4531 6E64696E + 4531 6700 + 4532 .LASF18: + 4533 0433 6C6F6E67 .ascii "long double\000" + 4533 20646F75 + 4533 626C6500 + 4534 .LASF52: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 139 + + + 4535 043f 61646472 .ascii "address\000" + 4535 65737300 + 4536 .LASF35: + 4537 0447 62675472 .ascii "bgTrim5\000" + 4537 696D3500 + 4538 .LASF29: + 4539 044f 73797363 .ascii "sysclkSource\000" + 4539 6C6B536F + 4539 75726365 + 4539 00 + 4540 .LASF88: + 4541 045c 66756E63 .ascii "function\000" + 4541 74696F6E + 4541 00 + 4542 .LASF99: + 4543 0465 6379496D .ascii "cyImoFreqMhz2Reg\000" + 4543 6F467265 + 4543 714D687A + 4543 32526567 + 4543 00 + 4544 .LASF84: + 4545 0476 43795379 .ascii "CySysTickGetValue\000" + 4545 73546963 + 4545 6B476574 + 4545 56616C75 + 4545 6500 + 4546 .LASF94: + 4547 0488 63796465 .ascii "cydelayFreqHz\000" + 4547 6C617946 + 4547 72657148 + 4547 7A00 + 4548 .LASF58: + 4549 0496 4379496E .ascii "CyIntSetPriority\000" + 4549 74536574 + 4549 5072696F + 4549 72697479 + 4549 00 + 4550 .LASF12: + 4551 04a7 666C6F61 .ascii "float\000" + 4551 7400 + 4552 .LASF38: + 4553 04ad 43795379 .ascii "CySysLvdEnable\000" + 4553 734C7664 + 4553 456E6162 + 4553 6C6500 + 4554 .LASF20: + 4555 04bc 63795379 .ascii "cySysTickCallback\000" + 4555 73546963 + 4555 6B43616C + 4555 6C626163 + 4555 6B00 + 4556 .LASF57: + 4557 04ce 4379496E .ascii "CyIntGetVector\000" + 4557 74476574 + 4557 56656374 + 4557 6F7200 + 4558 .LASF71: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 140 + + + 4559 04dd 6D696C6C .ascii "milliseconds\000" + 4559 69736563 + 4559 6F6E6473 + 4559 00 + 4560 .LASF15: + 4561 04ea 72656738 .ascii "reg8\000" + 4561 00 + 4562 .LASF39: + 4563 04ef 74687265 .ascii "threshold\000" + 4563 73686F6C + 4563 6400 + 4564 .LASF68: + 4565 04f9 43794861 .ascii "CyHalt\000" + 4565 6C7400 + 4566 .LASF1: + 4567 0500 756E7369 .ascii "unsigned char\000" + 4567 676E6564 + 4567 20636861 + 4567 7200 + 4568 .LASF2: + 4569 050e 73686F72 .ascii "short int\000" + 4569 7420696E + 4569 7400 + 4570 .LASF63: + 4571 0518 4379496E .ascii "CyIntEnable\000" + 4571 74456E61 + 4571 626C6500 + 4572 .LASF55: + 4573 0524 4379496E .ascii "CyIntGetSysVector\000" + 4573 74476574 + 4573 53797356 + 4573 6563746F + 4573 7200 + 4574 .LASF27: + 4575 0536 636C6B53 .ascii "clkSelect\000" + 4575 656C6563 + 4575 7400 + 4576 .LASF72: + 4577 0540 43794465 .ascii "CyDelayUs\000" + 4577 6C617955 + 4577 7300 + 4578 .LASF44: + 4579 054a 72656173 .ascii "reason\000" + 4579 6F6E00 + 4580 .LASF14: + 4581 0551 63686172 .ascii "char\000" + 4581 00 + 4582 .LASF17: + 4583 0556 63796973 .ascii "cyisraddress\000" + 4583 72616464 + 4583 72657373 + 4583 00 + 4584 .LASF77: + 4585 0563 43795379 .ascii "CySysTickEnable\000" + 4585 73546963 + 4585 6B456E61 + 4585 626C6500 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 141 + + + 4586 .LASF30: + 4587 0573 43795379 .ascii "CySysClkWriteSysclkDiv\000" + 4587 73436C6B + 4587 57726974 + 4587 65537973 + 4587 636C6B44 + 4588 .LASF87: + 4589 058a 43795379 .ascii "CySysTickSetCallback\000" + 4589 73546963 + 4589 6B536574 + 4589 43616C6C + 4589 6261636B + 4590 .LASF93: + 4591 059f 43795379 .ascii "CySysTickCallbacks\000" + 4591 73546963 + 4591 6B43616C + 4591 6C626163 + 4591 6B7300 + 4592 .LASF92: + 4593 05b2 756E6971 .ascii "uniqueId\000" + 4593 75654964 + 4593 00 + 4594 .LASF70: + 4595 05bb 43794465 .ascii "CyDelay\000" + 4595 6C617900 + 4596 .LASF80: + 4597 05c3 43795379 .ascii "CySysTickDisableInterrupt\000" + 4597 73546963 + 4597 6B446973 + 4597 61626C65 + 4597 496E7465 + 4598 .LASF40: + 4599 05dd 43795379 .ascii "CySysLvdDisable\000" + 4599 734C7664 + 4599 44697361 + 4599 626C6500 + 4600 .LASF96: + 4601 05ed 63796465 .ascii "cydelayFreqMhz\000" + 4601 6C617946 + 4601 7265714D + 4601 687A00 + 4602 .LASF78: + 4603 05fc 43795379 .ascii "CySysTickStop\000" + 4603 73546963 + 4603 6B53746F + 4603 7000 + 4604 .LASF31: + 4605 060a 64697669 .ascii "divider\000" + 4605 64657200 + 4606 .LASF21: + 4607 0612 43795379 .ascii "CySysClkImoStart\000" + 4607 73436C6B + 4607 496D6F53 + 4607 74617274 + 4607 00 + 4608 .LASF36: + 4609 0623 6E657749 .ascii "newImoTrim2Value\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccDAMPja.s page 142 + + + 4609 6D6F5472 + 4609 696D3256 + 4609 616C7565 + 4609 00 + 4610 .LASF102: + 4611 0634 47656E65 .ascii "Generated_Source\\PSoC4\\CyLib.c\000" + 4611 72617465 + 4611 645F536F + 4611 75726365 + 4611 5C50536F + 4612 .LASF73: + 4613 0653 6D696372 .ascii "microseconds\000" + 4613 6F736563 + 4613 6F6E6473 + 4613 00 + 4614 .LASF24: + 4615 0660 746D7052 .ascii "tmpReg\000" + 4615 656700 + 4616 .LASF81: + 4617 0667 43795379 .ascii "CySysTickSetReload\000" + 4617 73546963 + 4617 6B536574 + 4617 52656C6F + 4617 616400 + 4618 .LASF104: + 4619 067a 43795379 .ascii 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17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.Input_1_SetDriveMode,"ax",%progbits + 20 .align 2 + 21 .global Input_1_SetDriveMode + 22 .code 16 + 23 .thumb_func + 24 .type Input_1_SetDriveMode, %function + 25 Input_1_SetDriveMode: + 26 .LFB0: + 27 .file 1 "Generated_Source\\PSoC4\\Input_1.c" + 1:Generated_Source\PSoC4/Input_1.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/Input_1.c **** * File Name: Input_1.c + 3:Generated_Source\PSoC4/Input_1.c **** * Version 2.20 + 4:Generated_Source\PSoC4/Input_1.c **** * + 5:Generated_Source\PSoC4/Input_1.c **** * Description: + 6:Generated_Source\PSoC4/Input_1.c **** * This file contains API to enable firmware control of a Pins component. + 7:Generated_Source\PSoC4/Input_1.c **** * + 8:Generated_Source\PSoC4/Input_1.c **** ******************************************************************************** + 9:Generated_Source\PSoC4/Input_1.c **** * Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. + 10:Generated_Source\PSoC4/Input_1.c **** * You may use this file only in accordance with the license, terms, conditions, + 11:Generated_Source\PSoC4/Input_1.c **** * disclaimers, and limitations in the end user license agreement accompanying + 12:Generated_Source\PSoC4/Input_1.c **** * the software package with which this file was provided. + 13:Generated_Source\PSoC4/Input_1.c **** *******************************************************************************/ + 14:Generated_Source\PSoC4/Input_1.c **** + 15:Generated_Source\PSoC4/Input_1.c **** #include "cytypes.h" + 16:Generated_Source\PSoC4/Input_1.c **** #include "Input_1.h" + 17:Generated_Source\PSoC4/Input_1.c **** + 18:Generated_Source\PSoC4/Input_1.c **** + 19:Generated_Source\PSoC4/Input_1.c **** #if defined(Input_1__PC) + 20:Generated_Source\PSoC4/Input_1.c **** #define Input_1_SetP4PinDriveMode(shift, mode) \ + 21:Generated_Source\PSoC4/Input_1.c **** do { \ + 22:Generated_Source\PSoC4/Input_1.c **** Input_1_PC = (Input_1_PC & \ + 23:Generated_Source\PSoC4/Input_1.c **** (uint32)(~(uint32)(Input_1_DRIVE_MODE_IND_MASK << \ + 24:Generated_Source\PSoC4/Input_1.c **** (Input_1_DRIVE_MODE_BITS * (shift))))) | \ + 25:Generated_Source\PSoC4/Input_1.c **** (uint32)((uint32)(mode) << \ + 26:Generated_Source\PSoC4/Input_1.c **** (Input_1_DRIVE_MODE_BITS * (shift))); \ + 27:Generated_Source\PSoC4/Input_1.c **** } while (0) + 28:Generated_Source\PSoC4/Input_1.c **** #else + 29:Generated_Source\PSoC4/Input_1.c **** #if (CY_PSOC4_4200L) + 30:Generated_Source\PSoC4/Input_1.c **** #define Input_1_SetP4PinDriveMode(shift, mode) \ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 2 + + + 31:Generated_Source\PSoC4/Input_1.c **** do { \ + 32:Generated_Source\PSoC4/Input_1.c **** Input_1_USBIO_CTRL_REG = (Input_1_USBIO_CTRL_REG & \ + 33:Generated_Source\PSoC4/Input_1.c **** (uint32)(~(uint32)(Input_1_DRIVE_MODE_IND_MASK << \ + 34:Generated_Source\PSoC4/Input_1.c **** (Input_1_DRIVE_MODE_BITS * (shift))))) | \ + 35:Generated_Source\PSoC4/Input_1.c **** (uint32)((uint32)(mode) << \ + 36:Generated_Source\PSoC4/Input_1.c **** (Input_1_DRIVE_MODE_BITS * (shift))); \ + 37:Generated_Source\PSoC4/Input_1.c **** } while (0) + 38:Generated_Source\PSoC4/Input_1.c **** #endif + 39:Generated_Source\PSoC4/Input_1.c **** #endif + 40:Generated_Source\PSoC4/Input_1.c **** + 41:Generated_Source\PSoC4/Input_1.c **** + 42:Generated_Source\PSoC4/Input_1.c **** #if defined(Input_1__PC) || (CY_PSOC4_4200L) + 43:Generated_Source\PSoC4/Input_1.c **** /******************************************************************************* + 44:Generated_Source\PSoC4/Input_1.c **** * Function Name: Input_1_SetDriveMode + 45:Generated_Source\PSoC4/Input_1.c **** ****************************************************************************//** + 46:Generated_Source\PSoC4/Input_1.c **** * + 47:Generated_Source\PSoC4/Input_1.c **** * \brief Sets the drive mode for each of the Pins component's pins. + 48:Generated_Source\PSoC4/Input_1.c **** * + 49:Generated_Source\PSoC4/Input_1.c **** * Note This affects all pins in the Pins component instance. Use the + 50:Generated_Source\PSoC4/Input_1.c **** * Per-Pin APIs if you wish to control individual pin's drive modes. + 51:Generated_Source\PSoC4/Input_1.c **** * + 52:Generated_Source\PSoC4/Input_1.c **** * Note USBIOs have limited drive functionality. Refer to the Drive Mode + 53:Generated_Source\PSoC4/Input_1.c **** * parameter for more information. + 54:Generated_Source\PSoC4/Input_1.c **** * + 55:Generated_Source\PSoC4/Input_1.c **** * \param mode + 56:Generated_Source\PSoC4/Input_1.c **** * Mode for the selected signals. Valid options are documented in + 57:Generated_Source\PSoC4/Input_1.c **** * \ref driveMode. + 58:Generated_Source\PSoC4/Input_1.c **** * + 59:Generated_Source\PSoC4/Input_1.c **** * \return + 60:Generated_Source\PSoC4/Input_1.c **** * None + 61:Generated_Source\PSoC4/Input_1.c **** * + 62:Generated_Source\PSoC4/Input_1.c **** * \sideeffect + 63:Generated_Source\PSoC4/Input_1.c **** * If you use read-modify-write operations that are not atomic, the ISR can + 64:Generated_Source\PSoC4/Input_1.c **** * cause corruption of this function. An ISR that interrupts this function + 65:Generated_Source\PSoC4/Input_1.c **** * and performs writes to the Pins component Drive Mode registers can cause + 66:Generated_Source\PSoC4/Input_1.c **** * corrupted port data. To avoid this issue, you should either use the Per-Pin + 67:Generated_Source\PSoC4/Input_1.c **** * APIs (primary method) or disable interrupts around this function. + 68:Generated_Source\PSoC4/Input_1.c **** * + 69:Generated_Source\PSoC4/Input_1.c **** * \funcusage + 70:Generated_Source\PSoC4/Input_1.c **** * \snippet Input_1_SUT.c usage_Input_1_SetDriveMode + 71:Generated_Source\PSoC4/Input_1.c **** *******************************************************************************/ + 72:Generated_Source\PSoC4/Input_1.c **** void Input_1_SetDriveMode(uint8 mode) + 73:Generated_Source\PSoC4/Input_1.c **** { + 28 .loc 1 73 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 82B0 sub sp, sp, #8 + 37 .cfi_def_cfa_offset 16 + 38 0004 00AF add r7, sp, #0 + 39 .cfi_def_cfa_register 7 + 40 0006 0200 movs r2, r0 + 41 0008 FB1D adds r3, r7, #7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 3 + + + 42 000a 1A70 strb r2, [r3] + 74:Generated_Source\PSoC4/Input_1.c **** Input_1_SetP4PinDriveMode(Input_1__0__SHIFT, mode); + 43 .loc 1 74 0 + 44 000c 064B ldr r3, .L2 + 45 000e 064A ldr r2, .L2 + 46 0010 1268 ldr r2, [r2] + 47 0012 0649 ldr r1, .L2+4 + 48 0014 1140 ands r1, r2 + 49 0016 FA1D adds r2, r7, #7 + 50 0018 1278 ldrb r2, [r2] + 51 001a 5202 lsls r2, r2, #9 + 52 001c 0A43 orrs r2, r1 + 53 001e 1A60 str r2, [r3] + 75:Generated_Source\PSoC4/Input_1.c **** } + 54 .loc 1 75 0 + 55 0020 C046 nop + 56 0022 BD46 mov sp, r7 + 57 0024 02B0 add sp, sp, #8 + 58 @ sp needed + 59 0026 80BD pop {r7, pc} + 60 .L3: + 61 .align 2 + 62 .L2: + 63 0028 08020440 .word 1074004488 + 64 002c FFF1FFFF .word -3585 + 65 .cfi_endproc + 66 .LFE0: + 67 .size Input_1_SetDriveMode, .-Input_1_SetDriveMode + 68 .section .text.Input_1_Write,"ax",%progbits + 69 .align 2 + 70 .global Input_1_Write + 71 .code 16 + 72 .thumb_func + 73 .type Input_1_Write, %function + 74 Input_1_Write: + 75 .LFB1: + 76:Generated_Source\PSoC4/Input_1.c **** #endif + 77:Generated_Source\PSoC4/Input_1.c **** + 78:Generated_Source\PSoC4/Input_1.c **** + 79:Generated_Source\PSoC4/Input_1.c **** /******************************************************************************* + 80:Generated_Source\PSoC4/Input_1.c **** * Function Name: Input_1_Write + 81:Generated_Source\PSoC4/Input_1.c **** ****************************************************************************//** + 82:Generated_Source\PSoC4/Input_1.c **** * + 83:Generated_Source\PSoC4/Input_1.c **** * \brief Writes the value to the physical port (data output register), masking + 84:Generated_Source\PSoC4/Input_1.c **** * and shifting the bits appropriately. + 85:Generated_Source\PSoC4/Input_1.c **** * + 86:Generated_Source\PSoC4/Input_1.c **** * The data output register controls the signal applied to the physical pin in + 87:Generated_Source\PSoC4/Input_1.c **** * conjunction with the drive mode parameter. This function avoids changing + 88:Generated_Source\PSoC4/Input_1.c **** * other bits in the port by using the appropriate method (read-modify-write or + 89:Generated_Source\PSoC4/Input_1.c **** * bit banding). + 90:Generated_Source\PSoC4/Input_1.c **** * + 91:Generated_Source\PSoC4/Input_1.c **** * Note This function should not be used on a hardware digital output pin + 92:Generated_Source\PSoC4/Input_1.c **** * as it is driven by the hardware signal attached to it. + 93:Generated_Source\PSoC4/Input_1.c **** * + 94:Generated_Source\PSoC4/Input_1.c **** * \param value + 95:Generated_Source\PSoC4/Input_1.c **** * Value to write to the component instance. + 96:Generated_Source\PSoC4/Input_1.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 4 + + + 97:Generated_Source\PSoC4/Input_1.c **** * \return + 98:Generated_Source\PSoC4/Input_1.c **** * None + 99:Generated_Source\PSoC4/Input_1.c **** * + 100:Generated_Source\PSoC4/Input_1.c **** * \sideeffect + 101:Generated_Source\PSoC4/Input_1.c **** * If you use read-modify-write operations that are not atomic; the Interrupt + 102:Generated_Source\PSoC4/Input_1.c **** * Service Routines (ISR) can cause corruption of this function. An ISR that + 103:Generated_Source\PSoC4/Input_1.c **** * interrupts this function and performs writes to the Pins component data + 104:Generated_Source\PSoC4/Input_1.c **** * register can cause corrupted port data. To avoid this issue, you should + 105:Generated_Source\PSoC4/Input_1.c **** * either use the Per-Pin APIs (primary method) or disable interrupts around + 106:Generated_Source\PSoC4/Input_1.c **** * this function. + 107:Generated_Source\PSoC4/Input_1.c **** * + 108:Generated_Source\PSoC4/Input_1.c **** * \funcusage + 109:Generated_Source\PSoC4/Input_1.c **** * \snippet Input_1_SUT.c usage_Input_1_Write + 110:Generated_Source\PSoC4/Input_1.c **** *******************************************************************************/ + 111:Generated_Source\PSoC4/Input_1.c **** void Input_1_Write(uint8 value) + 112:Generated_Source\PSoC4/Input_1.c **** { + 76 .loc 1 112 0 + 77 .cfi_startproc + 78 @ args = 0, pretend = 0, frame = 16 + 79 @ frame_needed = 1, uses_anonymous_args = 0 + 80 0000 80B5 push {r7, lr} + 81 .cfi_def_cfa_offset 8 + 82 .cfi_offset 7, -8 + 83 .cfi_offset 14, -4 + 84 0002 84B0 sub sp, sp, #16 + 85 .cfi_def_cfa_offset 24 + 86 0004 00AF add r7, sp, #0 + 87 .cfi_def_cfa_register 7 + 88 0006 0200 movs r2, r0 + 89 0008 FB1D adds r3, r7, #7 + 90 000a 1A70 strb r2, [r3] + 113:Generated_Source\PSoC4/Input_1.c **** uint8 drVal = (uint8)(Input_1_DR & (uint8)(~Input_1_MASK)); + 91 .loc 1 113 0 + 92 000c 0F4B ldr r3, .L5 + 93 000e 1B68 ldr r3, [r3] + 94 0010 DAB2 uxtb r2, r3 + 95 0012 0F23 movs r3, #15 + 96 0014 FB18 adds r3, r7, r3 + 97 0016 0821 movs r1, #8 + 98 0018 8A43 bics r2, r1 + 99 001a 1A70 strb r2, [r3] + 114:Generated_Source\PSoC4/Input_1.c **** drVal = (drVal | ((uint8)(value << Input_1_SHIFT) & Input_1_MASK)); + 100 .loc 1 114 0 + 101 001c FB1D adds r3, r7, #7 + 102 001e 1B78 ldrb r3, [r3] + 103 0020 DB00 lsls r3, r3, #3 + 104 0022 DBB2 uxtb r3, r3 + 105 0024 0822 movs r2, #8 + 106 0026 1340 ands r3, r2 + 107 0028 D9B2 uxtb r1, r3 + 108 002a 0F23 movs r3, #15 + 109 002c FB18 adds r3, r7, r3 + 110 002e 0F22 movs r2, #15 + 111 0030 BA18 adds r2, r7, r2 + 112 0032 1278 ldrb r2, [r2] + 113 0034 0A43 orrs r2, r1 + 114 0036 1A70 strb r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 5 + + + 115:Generated_Source\PSoC4/Input_1.c **** Input_1_DR = (uint32)drVal; + 115 .loc 1 115 0 + 116 0038 044B ldr r3, .L5 + 117 003a 0F22 movs r2, #15 + 118 003c BA18 adds r2, r7, r2 + 119 003e 1278 ldrb r2, [r2] + 120 0040 1A60 str r2, [r3] + 116:Generated_Source\PSoC4/Input_1.c **** } + 121 .loc 1 116 0 + 122 0042 C046 nop + 123 0044 BD46 mov sp, r7 + 124 0046 04B0 add sp, sp, #16 + 125 @ sp needed + 126 0048 80BD pop {r7, pc} + 127 .L6: + 128 004a C046 .align 2 + 129 .L5: + 130 004c 00020440 .word 1074004480 + 131 .cfi_endproc + 132 .LFE1: + 133 .size Input_1_Write, .-Input_1_Write + 134 .section .text.Input_1_Read,"ax",%progbits + 135 .align 2 + 136 .global Input_1_Read + 137 .code 16 + 138 .thumb_func + 139 .type Input_1_Read, %function + 140 Input_1_Read: + 141 .LFB2: + 117:Generated_Source\PSoC4/Input_1.c **** + 118:Generated_Source\PSoC4/Input_1.c **** + 119:Generated_Source\PSoC4/Input_1.c **** /******************************************************************************* + 120:Generated_Source\PSoC4/Input_1.c **** * Function Name: Input_1_Read + 121:Generated_Source\PSoC4/Input_1.c **** ****************************************************************************//** + 122:Generated_Source\PSoC4/Input_1.c **** * + 123:Generated_Source\PSoC4/Input_1.c **** * \brief Reads the associated physical port (pin status register) and masks + 124:Generated_Source\PSoC4/Input_1.c **** * the required bits according to the width and bit position of the component + 125:Generated_Source\PSoC4/Input_1.c **** * instance. + 126:Generated_Source\PSoC4/Input_1.c **** * + 127:Generated_Source\PSoC4/Input_1.c **** * The pin's status register returns the current logic level present on the + 128:Generated_Source\PSoC4/Input_1.c **** * physical pin. + 129:Generated_Source\PSoC4/Input_1.c **** * + 130:Generated_Source\PSoC4/Input_1.c **** * \return + 131:Generated_Source\PSoC4/Input_1.c **** * The current value for the pins in the component as a right justified number. + 132:Generated_Source\PSoC4/Input_1.c **** * + 133:Generated_Source\PSoC4/Input_1.c **** * \funcusage + 134:Generated_Source\PSoC4/Input_1.c **** * \snippet Input_1_SUT.c usage_Input_1_Read + 135:Generated_Source\PSoC4/Input_1.c **** *******************************************************************************/ + 136:Generated_Source\PSoC4/Input_1.c **** uint8 Input_1_Read(void) + 137:Generated_Source\PSoC4/Input_1.c **** { + 142 .loc 1 137 0 + 143 .cfi_startproc + 144 @ args = 0, pretend = 0, frame = 0 + 145 @ frame_needed = 1, uses_anonymous_args = 0 + 146 0000 80B5 push {r7, lr} + 147 .cfi_def_cfa_offset 8 + 148 .cfi_offset 7, -8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 6 + + + 149 .cfi_offset 14, -4 + 150 0002 00AF add r7, sp, #0 + 151 .cfi_def_cfa_register 7 + 138:Generated_Source\PSoC4/Input_1.c **** return (uint8)((Input_1_PS & Input_1_MASK) >> Input_1_SHIFT); + 152 .loc 1 138 0 + 153 0004 044B ldr r3, .L9 + 154 0006 1B68 ldr r3, [r3] + 155 0008 0822 movs r2, #8 + 156 000a 1340 ands r3, r2 + 157 000c DB08 lsrs r3, r3, #3 + 158 000e DBB2 uxtb r3, r3 + 139:Generated_Source\PSoC4/Input_1.c **** } + 159 .loc 1 139 0 + 160 0010 1800 movs r0, r3 + 161 0012 BD46 mov sp, r7 + 162 @ sp needed + 163 0014 80BD pop {r7, pc} + 164 .L10: + 165 0016 C046 .align 2 + 166 .L9: + 167 0018 04020440 .word 1074004484 + 168 .cfi_endproc + 169 .LFE2: + 170 .size Input_1_Read, .-Input_1_Read + 171 .section .text.Input_1_ReadDataReg,"ax",%progbits + 172 .align 2 + 173 .global Input_1_ReadDataReg + 174 .code 16 + 175 .thumb_func + 176 .type Input_1_ReadDataReg, %function + 177 Input_1_ReadDataReg: + 178 .LFB3: + 140:Generated_Source\PSoC4/Input_1.c **** + 141:Generated_Source\PSoC4/Input_1.c **** + 142:Generated_Source\PSoC4/Input_1.c **** /******************************************************************************* + 143:Generated_Source\PSoC4/Input_1.c **** * Function Name: Input_1_ReadDataReg + 144:Generated_Source\PSoC4/Input_1.c **** ****************************************************************************//** + 145:Generated_Source\PSoC4/Input_1.c **** * + 146:Generated_Source\PSoC4/Input_1.c **** * \brief Reads the associated physical port's data output register and masks + 147:Generated_Source\PSoC4/Input_1.c **** * the correct bits according to the width and bit position of the component + 148:Generated_Source\PSoC4/Input_1.c **** * instance. + 149:Generated_Source\PSoC4/Input_1.c **** * + 150:Generated_Source\PSoC4/Input_1.c **** * The data output register controls the signal applied to the physical pin in + 151:Generated_Source\PSoC4/Input_1.c **** * conjunction with the drive mode parameter. This is not the same as the + 152:Generated_Source\PSoC4/Input_1.c **** * preferred Input_1_Read() API because the + 153:Generated_Source\PSoC4/Input_1.c **** * Input_1_ReadDataReg() reads the data register instead of the status + 154:Generated_Source\PSoC4/Input_1.c **** * register. For output pins this is a useful function to determine the value + 155:Generated_Source\PSoC4/Input_1.c **** * just written to the pin. + 156:Generated_Source\PSoC4/Input_1.c **** * + 157:Generated_Source\PSoC4/Input_1.c **** * \return + 158:Generated_Source\PSoC4/Input_1.c **** * The current value of the data register masked and shifted into a right + 159:Generated_Source\PSoC4/Input_1.c **** * justified number for the component instance. + 160:Generated_Source\PSoC4/Input_1.c **** * + 161:Generated_Source\PSoC4/Input_1.c **** * \funcusage + 162:Generated_Source\PSoC4/Input_1.c **** * \snippet Input_1_SUT.c usage_Input_1_ReadDataReg + 163:Generated_Source\PSoC4/Input_1.c **** *******************************************************************************/ + 164:Generated_Source\PSoC4/Input_1.c **** uint8 Input_1_ReadDataReg(void) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 7 + + + 165:Generated_Source\PSoC4/Input_1.c **** { + 179 .loc 1 165 0 + 180 .cfi_startproc + 181 @ args = 0, pretend = 0, frame = 0 + 182 @ frame_needed = 1, uses_anonymous_args = 0 + 183 0000 80B5 push {r7, lr} + 184 .cfi_def_cfa_offset 8 + 185 .cfi_offset 7, -8 + 186 .cfi_offset 14, -4 + 187 0002 00AF add r7, sp, #0 + 188 .cfi_def_cfa_register 7 + 166:Generated_Source\PSoC4/Input_1.c **** return (uint8)((Input_1_DR & Input_1_MASK) >> Input_1_SHIFT); + 189 .loc 1 166 0 + 190 0004 044B ldr r3, .L13 + 191 0006 1B68 ldr r3, [r3] + 192 0008 0822 movs r2, #8 + 193 000a 1340 ands r3, r2 + 194 000c DB08 lsrs r3, r3, #3 + 195 000e DBB2 uxtb r3, r3 + 167:Generated_Source\PSoC4/Input_1.c **** } + 196 .loc 1 167 0 + 197 0010 1800 movs r0, r3 + 198 0012 BD46 mov sp, r7 + 199 @ sp needed + 200 0014 80BD pop {r7, pc} + 201 .L14: + 202 0016 C046 .align 2 + 203 .L13: + 204 0018 00020440 .word 1074004480 + 205 .cfi_endproc + 206 .LFE3: + 207 .size Input_1_ReadDataReg, .-Input_1_ReadDataReg + 208 .section .text.Input_1_SetInterruptMode,"ax",%progbits + 209 .align 2 + 210 .global Input_1_SetInterruptMode + 211 .code 16 + 212 .thumb_func + 213 .type Input_1_SetInterruptMode, %function + 214 Input_1_SetInterruptMode: + 215 .LFB4: + 168:Generated_Source\PSoC4/Input_1.c **** + 169:Generated_Source\PSoC4/Input_1.c **** + 170:Generated_Source\PSoC4/Input_1.c **** /******************************************************************************* + 171:Generated_Source\PSoC4/Input_1.c **** * Function Name: Input_1_SetInterruptMode + 172:Generated_Source\PSoC4/Input_1.c **** ****************************************************************************//** + 173:Generated_Source\PSoC4/Input_1.c **** * + 174:Generated_Source\PSoC4/Input_1.c **** * \brief Configures the interrupt mode for each of the Pins component's + 175:Generated_Source\PSoC4/Input_1.c **** * pins. Alternatively you may set the interrupt mode for all the pins + 176:Generated_Source\PSoC4/Input_1.c **** * specified in the Pins component. + 177:Generated_Source\PSoC4/Input_1.c **** * + 178:Generated_Source\PSoC4/Input_1.c **** * Note The interrupt is port-wide and therefore any enabled pin + 179:Generated_Source\PSoC4/Input_1.c **** * interrupt may trigger it. + 180:Generated_Source\PSoC4/Input_1.c **** * + 181:Generated_Source\PSoC4/Input_1.c **** * \param position + 182:Generated_Source\PSoC4/Input_1.c **** * The pin position as listed in the Pins component. You may OR these to be + 183:Generated_Source\PSoC4/Input_1.c **** * able to configure the interrupt mode of multiple pins within a Pins + 184:Generated_Source\PSoC4/Input_1.c **** * component. Or you may use Input_1_INTR_ALL to configure the + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 8 + + + 185:Generated_Source\PSoC4/Input_1.c **** * interrupt mode of all the pins in the Pins component. + 186:Generated_Source\PSoC4/Input_1.c **** * - Input_1_0_INTR (First pin in the list) + 187:Generated_Source\PSoC4/Input_1.c **** * - Input_1_1_INTR (Second pin in the list) + 188:Generated_Source\PSoC4/Input_1.c **** * - ... + 189:Generated_Source\PSoC4/Input_1.c **** * - Input_1_INTR_ALL (All pins in Pins component) + 190:Generated_Source\PSoC4/Input_1.c **** * + 191:Generated_Source\PSoC4/Input_1.c **** * \param mode + 192:Generated_Source\PSoC4/Input_1.c **** * Interrupt mode for the selected pins. Valid options are documented in + 193:Generated_Source\PSoC4/Input_1.c **** * \ref intrMode. + 194:Generated_Source\PSoC4/Input_1.c **** * + 195:Generated_Source\PSoC4/Input_1.c **** * \return + 196:Generated_Source\PSoC4/Input_1.c **** * None + 197:Generated_Source\PSoC4/Input_1.c **** * + 198:Generated_Source\PSoC4/Input_1.c **** * \sideeffect + 199:Generated_Source\PSoC4/Input_1.c **** * It is recommended that the interrupt be disabled before calling this + 200:Generated_Source\PSoC4/Input_1.c **** * function to avoid unintended interrupt requests. Note that the interrupt + 201:Generated_Source\PSoC4/Input_1.c **** * type is port wide, and therefore will trigger for any enabled pin on the + 202:Generated_Source\PSoC4/Input_1.c **** * port. + 203:Generated_Source\PSoC4/Input_1.c **** * + 204:Generated_Source\PSoC4/Input_1.c **** * \funcusage + 205:Generated_Source\PSoC4/Input_1.c **** * \snippet Input_1_SUT.c usage_Input_1_SetInterruptMode + 206:Generated_Source\PSoC4/Input_1.c **** *******************************************************************************/ + 207:Generated_Source\PSoC4/Input_1.c **** void Input_1_SetInterruptMode(uint16 position, uint16 mode) + 208:Generated_Source\PSoC4/Input_1.c **** { + 216 .loc 1 208 0 + 217 .cfi_startproc + 218 @ args = 0, pretend = 0, frame = 16 + 219 @ frame_needed = 1, uses_anonymous_args = 0 + 220 0000 80B5 push {r7, lr} + 221 .cfi_def_cfa_offset 8 + 222 .cfi_offset 7, -8 + 223 .cfi_offset 14, -4 + 224 0002 84B0 sub sp, sp, #16 + 225 .cfi_def_cfa_offset 24 + 226 0004 00AF add r7, sp, #0 + 227 .cfi_def_cfa_register 7 + 228 0006 0200 movs r2, r0 + 229 0008 BB1D adds r3, r7, #6 + 230 000a 1A80 strh r2, [r3] + 231 000c 3B1D adds r3, r7, #4 + 232 000e 0A1C adds r2, r1, #0 + 233 0010 1A80 strh r2, [r3] + 209:Generated_Source\PSoC4/Input_1.c **** uint32 intrCfg; + 210:Generated_Source\PSoC4/Input_1.c **** + 211:Generated_Source\PSoC4/Input_1.c **** intrCfg = Input_1_INTCFG & (uint32)(~(uint32)position); + 234 .loc 1 211 0 + 235 0012 0B4B ldr r3, .L16 + 236 0014 1B68 ldr r3, [r3] + 237 0016 BA1D adds r2, r7, #6 + 238 0018 1288 ldrh r2, [r2] + 239 001a D243 mvns r2, r2 + 240 001c 1340 ands r3, r2 + 241 001e FB60 str r3, [r7, #12] + 212:Generated_Source\PSoC4/Input_1.c **** Input_1_INTCFG = intrCfg | ((uint32)position & (uint32)mode); + 242 .loc 1 212 0 + 243 0020 074B ldr r3, .L16 + 244 0022 BA1D adds r2, r7, #6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 9 + + + 245 0024 391D adds r1, r7, #4 + 246 0026 1288 ldrh r2, [r2] + 247 0028 0988 ldrh r1, [r1] + 248 002a 0A40 ands r2, r1 + 249 002c 92B2 uxth r2, r2 + 250 002e 1100 movs r1, r2 + 251 0030 FA68 ldr r2, [r7, #12] + 252 0032 0A43 orrs r2, r1 + 253 0034 1A60 str r2, [r3] + 213:Generated_Source\PSoC4/Input_1.c **** } + 254 .loc 1 213 0 + 255 0036 C046 nop + 256 0038 BD46 mov sp, r7 + 257 003a 04B0 add sp, sp, #16 + 258 @ sp needed + 259 003c 80BD pop {r7, pc} + 260 .L17: + 261 003e C046 .align 2 + 262 .L16: + 263 0040 0C020440 .word 1074004492 + 264 .cfi_endproc + 265 .LFE4: + 266 .size Input_1_SetInterruptMode, .-Input_1_SetInterruptMode + 267 .section .text.Input_1_ClearInterrupt,"ax",%progbits + 268 .align 2 + 269 .global Input_1_ClearInterrupt + 270 .code 16 + 271 .thumb_func + 272 .type Input_1_ClearInterrupt, %function + 273 Input_1_ClearInterrupt: + 274 .LFB5: + 214:Generated_Source\PSoC4/Input_1.c **** + 215:Generated_Source\PSoC4/Input_1.c **** + 216:Generated_Source\PSoC4/Input_1.c **** /******************************************************************************* + 217:Generated_Source\PSoC4/Input_1.c **** * Function Name: Input_1_ClearInterrupt + 218:Generated_Source\PSoC4/Input_1.c **** ****************************************************************************//** + 219:Generated_Source\PSoC4/Input_1.c **** * + 220:Generated_Source\PSoC4/Input_1.c **** * \brief Clears any active interrupts attached with the component and returns + 221:Generated_Source\PSoC4/Input_1.c **** * the value of the interrupt status register allowing determination of which + 222:Generated_Source\PSoC4/Input_1.c **** * pins generated an interrupt event. + 223:Generated_Source\PSoC4/Input_1.c **** * + 224:Generated_Source\PSoC4/Input_1.c **** * \return + 225:Generated_Source\PSoC4/Input_1.c **** * The right-shifted current value of the interrupt status register. Each pin + 226:Generated_Source\PSoC4/Input_1.c **** * has one bit set if it generated an interrupt event. For example, bit 0 is + 227:Generated_Source\PSoC4/Input_1.c **** * for pin 0 and bit 1 is for pin 1 of the Pins component. + 228:Generated_Source\PSoC4/Input_1.c **** * + 229:Generated_Source\PSoC4/Input_1.c **** * \sideeffect + 230:Generated_Source\PSoC4/Input_1.c **** * Clears all bits of the physical port's interrupt status register, not just + 231:Generated_Source\PSoC4/Input_1.c **** * those associated with the Pins component. + 232:Generated_Source\PSoC4/Input_1.c **** * + 233:Generated_Source\PSoC4/Input_1.c **** * \funcusage + 234:Generated_Source\PSoC4/Input_1.c **** * \snippet Input_1_SUT.c usage_Input_1_ClearInterrupt + 235:Generated_Source\PSoC4/Input_1.c **** *******************************************************************************/ + 236:Generated_Source\PSoC4/Input_1.c **** uint8 Input_1_ClearInterrupt(void) + 237:Generated_Source\PSoC4/Input_1.c **** { + 275 .loc 1 237 0 + 276 .cfi_startproc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 10 + + + 277 @ args = 0, pretend = 0, frame = 8 + 278 @ frame_needed = 1, uses_anonymous_args = 0 + 279 0000 80B5 push {r7, lr} + 280 .cfi_def_cfa_offset 8 + 281 .cfi_offset 7, -8 + 282 .cfi_offset 14, -4 + 283 0002 82B0 sub sp, sp, #8 + 284 .cfi_def_cfa_offset 16 + 285 0004 00AF add r7, sp, #0 + 286 .cfi_def_cfa_register 7 + 238:Generated_Source\PSoC4/Input_1.c **** uint8 maskedStatus = (uint8)(Input_1_INTSTAT & Input_1_MASK); + 287 .loc 1 238 0 + 288 0006 094B ldr r3, .L20 + 289 0008 1B68 ldr r3, [r3] + 290 000a DAB2 uxtb r2, r3 + 291 000c FB1D adds r3, r7, #7 + 292 000e 0821 movs r1, #8 + 293 0010 0A40 ands r2, r1 + 294 0012 1A70 strb r2, [r3] + 239:Generated_Source\PSoC4/Input_1.c **** Input_1_INTSTAT = maskedStatus; + 295 .loc 1 239 0 + 296 0014 054B ldr r3, .L20 + 297 0016 FA1D adds r2, r7, #7 + 298 0018 1278 ldrb r2, [r2] + 299 001a 1A60 str r2, [r3] + 240:Generated_Source\PSoC4/Input_1.c **** return maskedStatus >> Input_1_SHIFT; + 300 .loc 1 240 0 + 301 001c FB1D adds r3, r7, #7 + 302 001e 1B78 ldrb r3, [r3] + 303 0020 DB08 lsrs r3, r3, #3 + 304 0022 DBB2 uxtb r3, r3 + 241:Generated_Source\PSoC4/Input_1.c **** } + 305 .loc 1 241 0 + 306 0024 1800 movs r0, r3 + 307 0026 BD46 mov sp, r7 + 308 0028 02B0 add sp, sp, #8 + 309 @ sp needed + 310 002a 80BD pop {r7, pc} + 311 .L21: + 312 .align 2 + 313 .L20: + 314 002c 10020440 .word 1074004496 + 315 .cfi_endproc + 316 .LFE5: + 317 .size Input_1_ClearInterrupt, .-Input_1_ClearInterrupt + 318 .text + 319 .Letext0: + 320 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 321 .section .debug_info,"",%progbits + 322 .Ldebug_info0: + 323 0000 96010000 .4byte 0x196 + 324 0004 0400 .2byte 0x4 + 325 0006 00000000 .4byte .Ldebug_abbrev0 + 326 000a 04 .byte 0x4 + 327 000b 01 .uleb128 0x1 + 328 000c 0D010000 .4byte .LASF28 + 329 0010 0C .byte 0xc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 11 + + + 330 0011 0A020000 .4byte .LASF29 + 331 0015 51000000 .4byte .LASF30 + 332 0019 00000000 .4byte .Ldebug_ranges0+0 + 333 001d 00000000 .4byte 0 + 334 0021 00000000 .4byte .Ldebug_line0 + 335 0025 02 .uleb128 0x2 + 336 0026 01 .byte 0x1 + 337 0027 06 .byte 0x6 + 338 0028 44020000 .4byte .LASF0 + 339 002c 02 .uleb128 0x2 + 340 002d 01 .byte 0x1 + 341 002e 08 .byte 0x8 + 342 002f D4000000 .4byte .LASF1 + 343 0033 02 .uleb128 0x2 + 344 0034 02 .byte 0x2 + 345 0035 05 .byte 0x5 + 346 0036 2B020000 .4byte .LASF2 + 347 003a 02 .uleb128 0x2 + 348 003b 02 .byte 0x2 + 349 003c 07 .byte 0x7 + 350 003d FA000000 .4byte .LASF3 + 351 0041 02 .uleb128 0x2 + 352 0042 04 .byte 0x4 + 353 0043 05 .byte 0x5 + 354 0044 3B020000 .4byte .LASF4 + 355 0048 02 .uleb128 0x2 + 356 0049 04 .byte 0x4 + 357 004a 07 .byte 0x7 + 358 004b E8000000 .4byte .LASF5 + 359 004f 02 .uleb128 0x2 + 360 0050 08 .byte 0x8 + 361 0051 05 .byte 0x5 + 362 0052 EA010000 .4byte .LASF6 + 363 0056 02 .uleb128 0x2 + 364 0057 08 .byte 0x8 + 365 0058 07 .byte 0x7 + 366 0059 CE010000 .4byte .LASF7 + 367 005d 03 .uleb128 0x3 + 368 005e 04 .byte 0x4 + 369 005f 05 .byte 0x5 + 370 0060 696E7400 .ascii "int\000" + 371 0064 02 .uleb128 0x2 + 372 0065 04 .byte 0x4 + 373 0066 07 .byte 0x7 + 374 0067 C1010000 .4byte .LASF8 + 375 006b 04 .uleb128 0x4 + 376 006c 35020000 .4byte .LASF9 + 377 0070 02 .byte 0x2 + 378 0071 E401 .2byte 0x1e4 + 379 0073 2C000000 .4byte 0x2c + 380 0077 04 .uleb128 0x4 + 381 0078 A2010000 .4byte .LASF10 + 382 007c 02 .byte 0x2 + 383 007d E501 .2byte 0x1e5 + 384 007f 3A000000 .4byte 0x3a + 385 0083 04 .uleb128 0x4 + 386 0084 B2010000 .4byte .LASF11 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 12 + + + 387 0088 02 .byte 0x2 + 388 0089 E601 .2byte 0x1e6 + 389 008b 48000000 .4byte 0x48 + 390 008f 02 .uleb128 0x2 + 391 0090 04 .byte 0x4 + 392 0091 04 .byte 0x4 + 393 0092 AC000000 .4byte .LASF12 + 394 0096 02 .uleb128 0x2 + 395 0097 08 .byte 0x8 + 396 0098 04 .byte 0x4 + 397 0099 9B010000 .4byte .LASF13 + 398 009d 02 .uleb128 0x2 + 399 009e 01 .byte 0x1 + 400 009f 08 .byte 0x8 + 401 00a0 05020000 .4byte .LASF14 + 402 00a4 04 .uleb128 0x4 + 403 00a5 00000000 .4byte .LASF15 + 404 00a9 02 .byte 0x2 + 405 00aa 9002 .2byte 0x290 + 406 00ac B0000000 .4byte 0xb0 + 407 00b0 05 .uleb128 0x5 + 408 00b1 83000000 .4byte 0x83 + 409 00b5 06 .uleb128 0x6 + 410 00b6 25000000 .4byte .LASF16 + 411 00ba 01 .byte 0x1 + 412 00bb 48 .byte 0x48 + 413 00bc 00000000 .4byte .LFB0 + 414 00c0 30000000 .4byte .LFE0-.LFB0 + 415 00c4 01 .uleb128 0x1 + 416 00c5 9C .byte 0x9c + 417 00c6 D9000000 .4byte 0xd9 + 418 00ca 07 .uleb128 0x7 + 419 00cb E5010000 .4byte .LASF18 + 420 00cf 01 .byte 0x1 + 421 00d0 48 .byte 0x48 + 422 00d1 6B000000 .4byte 0x6b + 423 00d5 02 .uleb128 0x2 + 424 00d6 91 .byte 0x91 + 425 00d7 77 .sleb128 -9 + 426 00d8 00 .byte 0 + 427 00d9 06 .uleb128 0x6 + 428 00da B2000000 .4byte .LASF17 + 429 00de 01 .byte 0x1 + 430 00df 6F .byte 0x6f + 431 00e0 00000000 .4byte .LFB1 + 432 00e4 50000000 .4byte .LFE1-.LFB1 + 433 00e8 01 .uleb128 0x1 + 434 00e9 9C .byte 0x9c + 435 00ea 0B010000 .4byte 0x10b + 436 00ee 07 .uleb128 0x7 + 437 00ef 1F000000 .4byte .LASF19 + 438 00f3 01 .byte 0x1 + 439 00f4 6F .byte 0x6f + 440 00f5 6B000000 .4byte 0x6b + 441 00f9 02 .uleb128 0x2 + 442 00fa 91 .byte 0x91 + 443 00fb 6F .sleb128 -17 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 13 + + + 444 00fc 08 .uleb128 0x8 + 445 00fd E2000000 .4byte .LASF24 + 446 0101 01 .byte 0x1 + 447 0102 71 .byte 0x71 + 448 0103 6B000000 .4byte 0x6b + 449 0107 02 .uleb128 0x2 + 450 0108 91 .byte 0x91 + 451 0109 77 .sleb128 -9 + 452 010a 00 .byte 0 + 453 010b 09 .uleb128 0x9 + 454 010c 50020000 .4byte .LASF20 + 455 0110 01 .byte 0x1 + 456 0111 88 .byte 0x88 + 457 0112 6B000000 .4byte 0x6b + 458 0116 00000000 .4byte .LFB2 + 459 011a 1C000000 .4byte .LFE2-.LFB2 + 460 011e 01 .uleb128 0x1 + 461 011f 9C .byte 0x9c + 462 0120 09 .uleb128 0x9 + 463 0121 C0000000 .4byte .LASF21 + 464 0125 01 .byte 0x1 + 465 0126 A4 .byte 0xa4 + 466 0127 6B000000 .4byte 0x6b + 467 012b 00000000 .4byte .LFB3 + 468 012f 1C000000 .4byte .LFE3-.LFB3 + 469 0133 01 .uleb128 0x1 + 470 0134 9C .byte 0x9c + 471 0135 06 .uleb128 0x6 + 472 0136 06000000 .4byte .LASF22 + 473 013a 01 .byte 0x1 + 474 013b CF .byte 0xcf + 475 013c 00000000 .4byte .LFB4 + 476 0140 44000000 .4byte .LFE4-.LFB4 + 477 0144 01 .uleb128 0x1 + 478 0145 9C .byte 0x9c + 479 0146 75010000 .4byte 0x175 + 480 014a 07 .uleb128 0x7 + 481 014b A9010000 .4byte .LASF23 + 482 014f 01 .byte 0x1 + 483 0150 CF .byte 0xcf + 484 0151 77000000 .4byte 0x77 + 485 0155 02 .uleb128 0x2 + 486 0156 91 .byte 0x91 + 487 0157 6E .sleb128 -18 + 488 0158 07 .uleb128 0x7 + 489 0159 E5010000 .4byte .LASF18 + 490 015d 01 .byte 0x1 + 491 015e CF .byte 0xcf + 492 015f 77000000 .4byte 0x77 + 493 0163 02 .uleb128 0x2 + 494 0164 91 .byte 0x91 + 495 0165 6C .sleb128 -20 + 496 0166 08 .uleb128 0x8 + 497 0167 B9010000 .4byte .LASF25 + 498 016b 01 .byte 0x1 + 499 016c D1 .byte 0xd1 + 500 016d 83000000 .4byte 0x83 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 14 + + + 501 0171 02 .uleb128 0x2 + 502 0172 91 .byte 0x91 + 503 0173 74 .sleb128 -12 + 504 0174 00 .byte 0 + 505 0175 0A .uleb128 0xa + 506 0176 3A000000 .4byte .LASF26 + 507 017a 01 .byte 0x1 + 508 017b EC .byte 0xec + 509 017c 6B000000 .4byte 0x6b + 510 0180 00000000 .4byte .LFB5 + 511 0184 30000000 .4byte .LFE5-.LFB5 + 512 0188 01 .uleb128 0x1 + 513 0189 9C .byte 0x9c + 514 018a 08 .uleb128 0x8 + 515 018b F8010000 .4byte .LASF27 + 516 018f 01 .byte 0x1 + 517 0190 EE .byte 0xee + 518 0191 6B000000 .4byte 0x6b + 519 0195 02 .uleb128 0x2 + 520 0196 91 .byte 0x91 + 521 0197 77 .sleb128 -9 + 522 0198 00 .byte 0 + 523 0199 00 .byte 0 + 524 .section .debug_abbrev,"",%progbits + 525 .Ldebug_abbrev0: + 526 0000 01 .uleb128 0x1 + 527 0001 11 .uleb128 0x11 + 528 0002 01 .byte 0x1 + 529 0003 25 .uleb128 0x25 + 530 0004 0E .uleb128 0xe + 531 0005 13 .uleb128 0x13 + 532 0006 0B .uleb128 0xb + 533 0007 03 .uleb128 0x3 + 534 0008 0E .uleb128 0xe + 535 0009 1B .uleb128 0x1b + 536 000a 0E .uleb128 0xe + 537 000b 55 .uleb128 0x55 + 538 000c 17 .uleb128 0x17 + 539 000d 11 .uleb128 0x11 + 540 000e 01 .uleb128 0x1 + 541 000f 10 .uleb128 0x10 + 542 0010 17 .uleb128 0x17 + 543 0011 00 .byte 0 + 544 0012 00 .byte 0 + 545 0013 02 .uleb128 0x2 + 546 0014 24 .uleb128 0x24 + 547 0015 00 .byte 0 + 548 0016 0B .uleb128 0xb + 549 0017 0B .uleb128 0xb + 550 0018 3E .uleb128 0x3e + 551 0019 0B .uleb128 0xb + 552 001a 03 .uleb128 0x3 + 553 001b 0E .uleb128 0xe + 554 001c 00 .byte 0 + 555 001d 00 .byte 0 + 556 001e 03 .uleb128 0x3 + 557 001f 24 .uleb128 0x24 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 15 + + + 558 0020 00 .byte 0 + 559 0021 0B .uleb128 0xb + 560 0022 0B .uleb128 0xb + 561 0023 3E .uleb128 0x3e + 562 0024 0B .uleb128 0xb + 563 0025 03 .uleb128 0x3 + 564 0026 08 .uleb128 0x8 + 565 0027 00 .byte 0 + 566 0028 00 .byte 0 + 567 0029 04 .uleb128 0x4 + 568 002a 16 .uleb128 0x16 + 569 002b 00 .byte 0 + 570 002c 03 .uleb128 0x3 + 571 002d 0E .uleb128 0xe + 572 002e 3A .uleb128 0x3a + 573 002f 0B .uleb128 0xb + 574 0030 3B .uleb128 0x3b + 575 0031 05 .uleb128 0x5 + 576 0032 49 .uleb128 0x49 + 577 0033 13 .uleb128 0x13 + 578 0034 00 .byte 0 + 579 0035 00 .byte 0 + 580 0036 05 .uleb128 0x5 + 581 0037 35 .uleb128 0x35 + 582 0038 00 .byte 0 + 583 0039 49 .uleb128 0x49 + 584 003a 13 .uleb128 0x13 + 585 003b 00 .byte 0 + 586 003c 00 .byte 0 + 587 003d 06 .uleb128 0x6 + 588 003e 2E .uleb128 0x2e + 589 003f 01 .byte 0x1 + 590 0040 3F .uleb128 0x3f + 591 0041 19 .uleb128 0x19 + 592 0042 03 .uleb128 0x3 + 593 0043 0E .uleb128 0xe + 594 0044 3A .uleb128 0x3a + 595 0045 0B .uleb128 0xb + 596 0046 3B .uleb128 0x3b + 597 0047 0B .uleb128 0xb + 598 0048 27 .uleb128 0x27 + 599 0049 19 .uleb128 0x19 + 600 004a 11 .uleb128 0x11 + 601 004b 01 .uleb128 0x1 + 602 004c 12 .uleb128 0x12 + 603 004d 06 .uleb128 0x6 + 604 004e 40 .uleb128 0x40 + 605 004f 18 .uleb128 0x18 + 606 0050 9742 .uleb128 0x2117 + 607 0052 19 .uleb128 0x19 + 608 0053 01 .uleb128 0x1 + 609 0054 13 .uleb128 0x13 + 610 0055 00 .byte 0 + 611 0056 00 .byte 0 + 612 0057 07 .uleb128 0x7 + 613 0058 05 .uleb128 0x5 + 614 0059 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 16 + + + 615 005a 03 .uleb128 0x3 + 616 005b 0E .uleb128 0xe + 617 005c 3A .uleb128 0x3a + 618 005d 0B .uleb128 0xb + 619 005e 3B .uleb128 0x3b + 620 005f 0B .uleb128 0xb + 621 0060 49 .uleb128 0x49 + 622 0061 13 .uleb128 0x13 + 623 0062 02 .uleb128 0x2 + 624 0063 18 .uleb128 0x18 + 625 0064 00 .byte 0 + 626 0065 00 .byte 0 + 627 0066 08 .uleb128 0x8 + 628 0067 34 .uleb128 0x34 + 629 0068 00 .byte 0 + 630 0069 03 .uleb128 0x3 + 631 006a 0E .uleb128 0xe + 632 006b 3A .uleb128 0x3a + 633 006c 0B .uleb128 0xb + 634 006d 3B .uleb128 0x3b + 635 006e 0B .uleb128 0xb + 636 006f 49 .uleb128 0x49 + 637 0070 13 .uleb128 0x13 + 638 0071 02 .uleb128 0x2 + 639 0072 18 .uleb128 0x18 + 640 0073 00 .byte 0 + 641 0074 00 .byte 0 + 642 0075 09 .uleb128 0x9 + 643 0076 2E .uleb128 0x2e + 644 0077 00 .byte 0 + 645 0078 3F .uleb128 0x3f + 646 0079 19 .uleb128 0x19 + 647 007a 03 .uleb128 0x3 + 648 007b 0E .uleb128 0xe + 649 007c 3A .uleb128 0x3a + 650 007d 0B .uleb128 0xb + 651 007e 3B .uleb128 0x3b + 652 007f 0B .uleb128 0xb + 653 0080 27 .uleb128 0x27 + 654 0081 19 .uleb128 0x19 + 655 0082 49 .uleb128 0x49 + 656 0083 13 .uleb128 0x13 + 657 0084 11 .uleb128 0x11 + 658 0085 01 .uleb128 0x1 + 659 0086 12 .uleb128 0x12 + 660 0087 06 .uleb128 0x6 + 661 0088 40 .uleb128 0x40 + 662 0089 18 .uleb128 0x18 + 663 008a 9742 .uleb128 0x2117 + 664 008c 19 .uleb128 0x19 + 665 008d 00 .byte 0 + 666 008e 00 .byte 0 + 667 008f 0A .uleb128 0xa + 668 0090 2E .uleb128 0x2e + 669 0091 01 .byte 0x1 + 670 0092 3F .uleb128 0x3f + 671 0093 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 17 + + + 672 0094 03 .uleb128 0x3 + 673 0095 0E .uleb128 0xe + 674 0096 3A .uleb128 0x3a + 675 0097 0B .uleb128 0xb + 676 0098 3B .uleb128 0x3b + 677 0099 0B .uleb128 0xb + 678 009a 27 .uleb128 0x27 + 679 009b 19 .uleb128 0x19 + 680 009c 49 .uleb128 0x49 + 681 009d 13 .uleb128 0x13 + 682 009e 11 .uleb128 0x11 + 683 009f 01 .uleb128 0x1 + 684 00a0 12 .uleb128 0x12 + 685 00a1 06 .uleb128 0x6 + 686 00a2 40 .uleb128 0x40 + 687 00a3 18 .uleb128 0x18 + 688 00a4 9742 .uleb128 0x2117 + 689 00a6 19 .uleb128 0x19 + 690 00a7 00 .byte 0 + 691 00a8 00 .byte 0 + 692 00a9 00 .byte 0 + 693 .section .debug_aranges,"",%progbits + 694 0000 44000000 .4byte 0x44 + 695 0004 0200 .2byte 0x2 + 696 0006 00000000 .4byte .Ldebug_info0 + 697 000a 04 .byte 0x4 + 698 000b 00 .byte 0 + 699 000c 0000 .2byte 0 + 700 000e 0000 .2byte 0 + 701 0010 00000000 .4byte .LFB0 + 702 0014 30000000 .4byte .LFE0-.LFB0 + 703 0018 00000000 .4byte .LFB1 + 704 001c 50000000 .4byte .LFE1-.LFB1 + 705 0020 00000000 .4byte .LFB2 + 706 0024 1C000000 .4byte .LFE2-.LFB2 + 707 0028 00000000 .4byte .LFB3 + 708 002c 1C000000 .4byte .LFE3-.LFB3 + 709 0030 00000000 .4byte .LFB4 + 710 0034 44000000 .4byte .LFE4-.LFB4 + 711 0038 00000000 .4byte .LFB5 + 712 003c 30000000 .4byte .LFE5-.LFB5 + 713 0040 00000000 .4byte 0 + 714 0044 00000000 .4byte 0 + 715 .section .debug_ranges,"",%progbits + 716 .Ldebug_ranges0: + 717 0000 00000000 .4byte .LFB0 + 718 0004 30000000 .4byte .LFE0 + 719 0008 00000000 .4byte .LFB1 + 720 000c 50000000 .4byte .LFE1 + 721 0010 00000000 .4byte .LFB2 + 722 0014 1C000000 .4byte .LFE2 + 723 0018 00000000 .4byte .LFB3 + 724 001c 1C000000 .4byte .LFE3 + 725 0020 00000000 .4byte .LFB4 + 726 0024 44000000 .4byte .LFE4 + 727 0028 00000000 .4byte .LFB5 + 728 002c 30000000 .4byte .LFE5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 18 + + + 729 0030 00000000 .4byte 0 + 730 0034 00000000 .4byte 0 + 731 .section .debug_line,"",%progbits + 732 .Ldebug_line0: + 733 0000 BB000000 .section .debug_str,"MS",%progbits,1 + 733 02004400 + 733 00000201 + 733 FB0E0D00 + 733 01010101 + 734 .LASF15: + 735 0000 72656733 .ascii "reg32\000" + 735 3200 + 736 .LASF22: + 737 0006 496E7075 .ascii "Input_1_SetInterruptMode\000" + 737 745F315F + 737 53657449 + 737 6E746572 + 737 72757074 + 738 .LASF19: + 739 001f 76616C75 .ascii "value\000" + 739 6500 + 740 .LASF16: + 741 0025 496E7075 .ascii "Input_1_SetDriveMode\000" + 741 745F315F + 741 53657444 + 741 72697665 + 741 4D6F6465 + 742 .LASF26: + 743 003a 496E7075 .ascii "Input_1_ClearInterrupt\000" + 743 745F315F + 743 436C6561 + 743 72496E74 + 743 65727275 + 744 .LASF30: + 745 0051 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 745 73657273 + 745 5C6A6167 + 745 756D6965 + 745 6C5C446F + 746 007f 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 746 50536F43 + 746 2D313031 + 746 5C547261 + 746 696E696E + 747 .LASF12: + 748 00ac 666C6F61 .ascii "float\000" + 748 7400 + 749 .LASF17: + 750 00b2 496E7075 .ascii "Input_1_Write\000" + 750 745F315F + 750 57726974 + 750 6500 + 751 .LASF21: + 752 00c0 496E7075 .ascii "Input_1_ReadDataReg\000" + 752 745F315F + 752 52656164 + 752 44617461 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 19 + + + 752 52656700 + 753 .LASF1: + 754 00d4 756E7369 .ascii "unsigned char\000" + 754 676E6564 + 754 20636861 + 754 7200 + 755 .LASF24: + 756 00e2 64725661 .ascii "drVal\000" + 756 6C00 + 757 .LASF5: + 758 00e8 6C6F6E67 .ascii "long unsigned int\000" + 758 20756E73 + 758 69676E65 + 758 6420696E + 758 7400 + 759 .LASF3: + 760 00fa 73686F72 .ascii "short unsigned int\000" + 760 7420756E + 760 7369676E + 760 65642069 + 760 6E7400 + 761 .LASF28: + 762 010d 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 762 43313120 + 762 352E342E + 762 31203230 + 762 31363036 + 763 0140 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 763 20726576 + 763 6973696F + 763 6E203233 + 763 37373135 + 764 0173 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 764 66756E63 + 764 74696F6E + 764 2D736563 + 764 74696F6E + 765 .LASF13: + 766 019b 646F7562 .ascii "double\000" + 766 6C6500 + 767 .LASF10: + 768 01a2 75696E74 .ascii "uint16\000" + 768 313600 + 769 .LASF23: + 770 01a9 706F7369 .ascii "position\000" + 770 74696F6E + 770 00 + 771 .LASF11: + 772 01b2 75696E74 .ascii "uint32\000" + 772 333200 + 773 .LASF25: + 774 01b9 696E7472 .ascii "intrCfg\000" + 774 43666700 + 775 .LASF8: + 776 01c1 756E7369 .ascii "unsigned int\000" + 776 676E6564 + 776 20696E74 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc4fFtMk.s page 20 + + + 776 00 + 777 .LASF7: + 778 01ce 6C6F6E67 .ascii "long long unsigned int\000" + 778 206C6F6E + 778 6720756E + 778 7369676E + 778 65642069 + 779 .LASF18: + 780 01e5 6D6F6465 .ascii "mode\000" + 780 00 + 781 .LASF6: + 782 01ea 6C6F6E67 .ascii "long long int\000" + 782 206C6F6E + 782 6720696E + 782 7400 + 783 .LASF27: + 784 01f8 6D61736B .ascii "maskedStatus\000" + 784 65645374 + 784 61747573 + 784 00 + 785 .LASF14: + 786 0205 63686172 .ascii "char\000" + 786 00 + 787 .LASF29: + 788 020a 47656E65 .ascii "Generated_Source\\PSoC4\\Input_1.c\000" + 788 72617465 + 788 645F536F + 788 75726365 + 788 5C50536F + 789 .LASF2: + 790 022b 73686F72 .ascii "short int\000" + 790 7420696E + 790 7400 + 791 .LASF9: + 792 0235 75696E74 .ascii "uint8\000" + 792 3800 + 793 .LASF4: + 794 023b 6C6F6E67 .ascii "long int\000" + 794 20696E74 + 794 00 + 795 .LASF0: + 796 0244 7369676E .ascii "signed char\000" + 796 65642063 + 796 68617200 + 797 .LASF20: + 798 0250 496E7075 .ascii "Input_1_Read\000" + 798 745F315F + 798 52656164 + 798 00 + 799 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/Input_1.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/Input_1.o new file mode 100644 index 0000000000000000000000000000000000000000..3c3e15a934be8ccdfaa364be20d6dd05efa25e62 GIT binary patch literal 5016 zcmbtXZHQb~89w*U=YA%;n>L$Gwoc;KrnEEJO_Q`ujLtgSBU?76%IKqzy3TfIUtAdw zw-$9Z!PvbrKWp!jRjiICw{~Yo>aiKtJ~A(BQS)K_>*4aB ze$nsI>uqB%`4#f-7>8uG=tY?(`Vy5!GKLsAKl26i5-hQ2@e{unKhj@}lRN(geiLsa z!Z`FaSo7R7BECY4gC8+V?tBl-i4RC+;Nv9UqV!oE(KU;)jI$I;Tksg?yRH!~v@7Fr zDzD>5Op!a^VD2As{Oiv^VV)^9}YnCR*G2vlgTVv}gk-6GPzw`X5$dIV~*p(5jxapy0q!8WVjBOU#1GEkltR!-*iNxNM z*iDi~_Kl?d0;whcFLAFT*bHW2toHW_oEK;%j|tcXa8`*OoVi24P!^ijE6KA z)@ZI9#@8D^ZVS6<82cMDGcwS%OAqbTGdgwD_NQyU?YfP+f5a);;51`)7IVzC z%C&N>H0wG~*#-DdPUX_aC+Ci33TKL5O)OL#%WqER({9;sO>NG$ic^+v&DkZj?x(DZs5rG!s%hZC;4M0?->y3NiQ}o<#6)U$W>;n+wR3!8&-kA4M^oEf z8#Q|N{i!D==Z@^Kt9iRvw2SH8>AY*z3X3V%K3(?8PA#?bp@$!y*!^TGT`klb`wJMr zUP@QTA^VGsYCe@NrP7~-xUkTu6?{abJroM`sI&ZZ#dp$9URE!PP9tBjMFW$a*dywW zSEi?w@yeiea|@wjS(B`CZK+kh%9f3uRm*$YE*|wQzu^hlr#r9KldZ)XG>pNV(j!4a zis5eSRl)Zm#KBx{Z)!W+ddzVuUTVQ{Q)pr8G1bBpUUk9tJjeC!|G&GA`vY6&Hpmd> z=lXm5n){twihF&sKbifKnf;nE*}s0WFVSY_o)6iFX~z-OB%U2Ddtc)HZ2FvGFwdG+ zT))g4w%=)9lT=!^l`jk9LttaMU?m+H7xCW2kuGB}y1}^1*ccf$HW?$vJ-iV*iHDG; zsCe(T=82KEuNca~395Y}(1a<1v$ZFzfQ)MZUqhN&XD>Ao5$o`eN&myz9riFqM7+a4 zF8y0QZm%#R5*_}D4*x_rJ?4|_@J~wrY|{%jS%@N{tHZxb`t#!E$cudPsGIpcf`sMC)&(tUWa6#kkhu>uX}=m2VZYx(zLVeC4!@g_r|@Xf`F;RJINvygJJs=;^3(D2@cT9c z6>0WYka+`UmHqV4benCc& zwk5!X^F4=r>@)M>C~4-~sPgG|@F(PZQZHioF(0389e&w_5DxU3wBHWpr}dZM$9JiT zb&z;hgy;84s9xTex?bKPXjxqb;b#dib3zM1j!R-q@N3croS%oa5n9a>L*Note This function is available in PSoC 4 only. + 32:Generated_Source\PSoC4/Input_1_PM.c **** * + 33:Generated_Source\PSoC4/Input_1_PM.c **** * \return + 34:Generated_Source\PSoC4/Input_1_PM.c **** * None + 35:Generated_Source\PSoC4/Input_1_PM.c **** * + 36:Generated_Source\PSoC4/Input_1_PM.c **** * \sideeffect + 37:Generated_Source\PSoC4/Input_1_PM.c **** * For SIO pins, this function configures the pin input threshold to CMOS and + 38:Generated_Source\PSoC4/Input_1_PM.c **** * drive level to Vddio. This is needed for SIO pins when in device + 39:Generated_Source\PSoC4/Input_1_PM.c **** * deep-sleep/hibernate modes. + 40:Generated_Source\PSoC4/Input_1_PM.c **** * + 41:Generated_Source\PSoC4/Input_1_PM.c **** * \funcusage + 42:Generated_Source\PSoC4/Input_1_PM.c **** * \snippet Input_1_SUT.c usage_Input_1_Sleep_Wakeup + 43:Generated_Source\PSoC4/Input_1_PM.c **** *******************************************************************************/ + 44:Generated_Source\PSoC4/Input_1_PM.c **** void Input_1_Sleep(void) + 45:Generated_Source\PSoC4/Input_1_PM.c **** { + 32 .loc 1 45 0 + 33 .cfi_startproc + 34 @ args = 0, pretend = 0, frame = 0 + 35 @ frame_needed = 1, uses_anonymous_args = 0 + 36 0000 80B5 push {r7, lr} + 37 .cfi_def_cfa_offset 8 + 38 .cfi_offset 7, -8 + 39 .cfi_offset 14, -4 + 40 0002 00AF add r7, sp, #0 + 41 .cfi_def_cfa_register 7 + 46:Generated_Source\PSoC4/Input_1_PM.c **** #if defined(Input_1__PC) + 47:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_backup.pcState = Input_1_PC; + 42 .loc 1 47 0 + 43 0004 034B ldr r3, .L2 + 44 0006 1A68 ldr r2, [r3] + 45 0008 034B ldr r3, .L2+4 + 46 000a 1A60 str r2, [r3] + 48:Generated_Source\PSoC4/Input_1_PM.c **** #else + 49:Generated_Source\PSoC4/Input_1_PM.c **** #if (CY_PSOC4_4200L) + 50:Generated_Source\PSoC4/Input_1_PM.c **** /* Save the regulator state and put the PHY into suspend mode */ + 51:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_backup.usbState = Input_1_CR1_REG; + 52:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_USB_POWER_REG |= Input_1_USBIO_ENTER_SLEEP; + 53:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_CR1_REG &= Input_1_USBIO_CR1_OFF; + 54:Generated_Source\PSoC4/Input_1_PM.c **** #endif + 55:Generated_Source\PSoC4/Input_1_PM.c **** #endif + 56:Generated_Source\PSoC4/Input_1_PM.c **** #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(Input_1__SIO) + 57:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_backup.sioState = Input_1_SIO_REG; + 58:Generated_Source\PSoC4/Input_1_PM.c **** /* SIO requires unregulated output buffer and single ended input buffer */ + 59:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_SIO_REG &= (uint32)(~Input_1_SIO_LPM_MASK); + 60:Generated_Source\PSoC4/Input_1_PM.c **** #endif + 61:Generated_Source\PSoC4/Input_1_PM.c **** } + 47 .loc 1 61 0 + 48 000c C046 nop + 49 000e BD46 mov sp, r7 + 50 @ sp needed + 51 0010 80BD pop {r7, pc} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 3 + + + 52 .L3: + 53 0012 C046 .align 2 + 54 .L2: + 55 0014 08020440 .word 1074004488 + 56 0018 00000000 .word Input_1_backup + 57 .cfi_endproc + 58 .LFE0: + 59 .size Input_1_Sleep, .-Input_1_Sleep + 60 .section .text.Input_1_Wakeup,"ax",%progbits + 61 .align 2 + 62 .global Input_1_Wakeup + 63 .code 16 + 64 .thumb_func + 65 .type Input_1_Wakeup, %function + 66 Input_1_Wakeup: + 67 .LFB1: + 62:Generated_Source\PSoC4/Input_1_PM.c **** + 63:Generated_Source\PSoC4/Input_1_PM.c **** + 64:Generated_Source\PSoC4/Input_1_PM.c **** /******************************************************************************* + 65:Generated_Source\PSoC4/Input_1_PM.c **** * Function Name: Input_1_Wakeup + 66:Generated_Source\PSoC4/Input_1_PM.c **** ****************************************************************************//** + 67:Generated_Source\PSoC4/Input_1_PM.c **** * + 68:Generated_Source\PSoC4/Input_1_PM.c **** * \brief Restores the pin configuration that was saved during Pin_Sleep(). This + 69:Generated_Source\PSoC4/Input_1_PM.c **** * function applies only to SIO and USBIO pins. It should not be called for + 70:Generated_Source\PSoC4/Input_1_PM.c **** * GPIO or GPIO_OVT pins. + 71:Generated_Source\PSoC4/Input_1_PM.c **** * + 72:Generated_Source\PSoC4/Input_1_PM.c **** * For USBIO pins, the wakeup is only triggered for falling edge interrupts. + 73:Generated_Source\PSoC4/Input_1_PM.c **** * + 74:Generated_Source\PSoC4/Input_1_PM.c **** * Note This function is available in PSoC 4 only. + 75:Generated_Source\PSoC4/Input_1_PM.c **** * + 76:Generated_Source\PSoC4/Input_1_PM.c **** * \return + 77:Generated_Source\PSoC4/Input_1_PM.c **** * None + 78:Generated_Source\PSoC4/Input_1_PM.c **** * + 79:Generated_Source\PSoC4/Input_1_PM.c **** * \funcusage + 80:Generated_Source\PSoC4/Input_1_PM.c **** * Refer to Input_1_Sleep() for an example usage. + 81:Generated_Source\PSoC4/Input_1_PM.c **** *******************************************************************************/ + 82:Generated_Source\PSoC4/Input_1_PM.c **** void Input_1_Wakeup(void) + 83:Generated_Source\PSoC4/Input_1_PM.c **** { + 68 .loc 1 83 0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 1, uses_anonymous_args = 0 + 72 0000 80B5 push {r7, lr} + 73 .cfi_def_cfa_offset 8 + 74 .cfi_offset 7, -8 + 75 .cfi_offset 14, -4 + 76 0002 00AF add r7, sp, #0 + 77 .cfi_def_cfa_register 7 + 84:Generated_Source\PSoC4/Input_1_PM.c **** #if defined(Input_1__PC) + 85:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_PC = Input_1_backup.pcState; + 78 .loc 1 85 0 + 79 0004 034A ldr r2, .L5 + 80 0006 044B ldr r3, .L5+4 + 81 0008 1B68 ldr r3, [r3] + 82 000a 1360 str r3, [r2] + 86:Generated_Source\PSoC4/Input_1_PM.c **** #else + 87:Generated_Source\PSoC4/Input_1_PM.c **** #if (CY_PSOC4_4200L) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 4 + + + 88:Generated_Source\PSoC4/Input_1_PM.c **** /* Restore the regulator state and come out of suspend mode */ + 89:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_USB_POWER_REG &= Input_1_USBIO_EXIT_SLEEP_PH1; + 90:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_CR1_REG = Input_1_backup.usbState; + 91:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_USB_POWER_REG &= Input_1_USBIO_EXIT_SLEEP_PH2; + 92:Generated_Source\PSoC4/Input_1_PM.c **** #endif + 93:Generated_Source\PSoC4/Input_1_PM.c **** #endif + 94:Generated_Source\PSoC4/Input_1_PM.c **** #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(Input_1__SIO) + 95:Generated_Source\PSoC4/Input_1_PM.c **** Input_1_SIO_REG = Input_1_backup.sioState; + 96:Generated_Source\PSoC4/Input_1_PM.c **** #endif + 97:Generated_Source\PSoC4/Input_1_PM.c **** } + 83 .loc 1 97 0 + 84 000c C046 nop + 85 000e BD46 mov sp, r7 + 86 @ sp needed + 87 0010 80BD pop {r7, pc} + 88 .L6: + 89 0012 C046 .align 2 + 90 .L5: + 91 0014 08020440 .word 1074004488 + 92 0018 00000000 .word Input_1_backup + 93 .cfi_endproc + 94 .LFE1: + 95 .size Input_1_Wakeup, .-Input_1_Wakeup + 96 .text + 97 .Letext0: + 98 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 99 .file 3 "Generated_Source\\PSoC4\\Input_1.h" + 100 .section .debug_info,"",%progbits + 101 .Ldebug_info0: + 102 0000 05010000 .4byte 0x105 + 103 0004 0400 .2byte 0x4 + 104 0006 00000000 .4byte .Ldebug_abbrev0 + 105 000a 04 .byte 0x4 + 106 000b 01 .uleb128 0x1 + 107 000c A3000000 .4byte .LASF20 + 108 0010 0C .byte 0xc + 109 0011 98010000 .4byte .LASF21 + 110 0015 0F000000 .4byte .LASF22 + 111 0019 00000000 .4byte .Ldebug_ranges0+0 + 112 001d 00000000 .4byte 0 + 113 0021 00000000 .4byte .Ldebug_line0 + 114 0025 02 .uleb128 0x2 + 115 0026 01 .byte 0x1 + 116 0027 06 .byte 0x6 + 117 0028 EA010000 .4byte .LASF0 + 118 002c 02 .uleb128 0x2 + 119 002d 01 .byte 0x1 + 120 002e 08 .byte 0x8 + 121 002f 70000000 .4byte .LASF1 + 122 0033 02 .uleb128 0x2 + 123 0034 02 .byte 0x2 + 124 0035 05 .byte 0x5 + 125 0036 C1010000 .4byte .LASF2 + 126 003a 02 .uleb128 0x2 + 127 003b 02 .byte 0x2 + 128 003c 07 .byte 0x7 + 129 003d 90000000 .4byte .LASF3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 5 + + + 130 0041 02 .uleb128 0x2 + 131 0042 04 .byte 0x4 + 132 0043 05 .byte 0x5 + 133 0044 E1010000 .4byte .LASF4 + 134 0048 02 .uleb128 0x2 + 135 0049 04 .byte 0x4 + 136 004a 07 .byte 0x7 + 137 004b 7E000000 .4byte .LASF5 + 138 004f 02 .uleb128 0x2 + 139 0050 08 .byte 0x8 + 140 0051 05 .byte 0x5 + 141 0052 8A010000 .4byte .LASF6 + 142 0056 02 .uleb128 0x2 + 143 0057 08 .byte 0x8 + 144 0058 07 .byte 0x7 + 145 0059 6A010000 .4byte .LASF7 + 146 005d 03 .uleb128 0x3 + 147 005e 04 .byte 0x4 + 148 005f 05 .byte 0x5 + 149 0060 696E7400 .ascii "int\000" + 150 0064 02 .uleb128 0x2 + 151 0065 04 .byte 0x4 + 152 0066 07 .byte 0x7 + 153 0067 5D010000 .4byte .LASF8 + 154 006b 04 .uleb128 0x4 + 155 006c 47010000 .4byte .LASF12 + 156 0070 02 .byte 0x2 + 157 0071 E601 .2byte 0x1e6 + 158 0073 48000000 .4byte 0x48 + 159 0077 02 .uleb128 0x2 + 160 0078 04 .byte 0x4 + 161 0079 04 .byte 0x4 + 162 007a 6A000000 .4byte .LASF9 + 163 007e 02 .uleb128 0x2 + 164 007f 08 .byte 0x8 + 165 0080 04 .byte 0x4 + 166 0081 40010000 .4byte .LASF10 + 167 0085 02 .uleb128 0x2 + 168 0086 01 .byte 0x1 + 169 0087 08 .byte 0x8 + 170 0088 BC010000 .4byte .LASF11 + 171 008c 04 .uleb128 0x4 + 172 008d 00000000 .4byte .LASF13 + 173 0091 02 .byte 0x2 + 174 0092 9002 .2byte 0x290 + 175 0094 98000000 .4byte 0x98 + 176 0098 05 .uleb128 0x5 + 177 0099 6B000000 .4byte 0x6b + 178 009d 06 .uleb128 0x6 + 179 009e 0C .byte 0xc + 180 009f 03 .byte 0x3 + 181 00a0 21 .byte 0x21 + 182 00a1 CA000000 .4byte 0xca + 183 00a5 07 .uleb128 0x7 + 184 00a6 D9010000 .4byte .LASF14 + 185 00aa 03 .byte 0x3 + 186 00ab 23 .byte 0x23 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 6 + + + 187 00ac 6B000000 .4byte 0x6b + 188 00b0 00 .byte 0 + 189 00b1 07 .uleb128 0x7 + 190 00b2 81010000 .4byte .LASF15 + 191 00b6 03 .byte 0x3 + 192 00b7 24 .byte 0x24 + 193 00b8 6B000000 .4byte 0x6b + 194 00bc 04 .byte 0x4 + 195 00bd 07 .uleb128 0x7 + 196 00be 06000000 .4byte .LASF16 + 197 00c2 03 .byte 0x3 + 198 00c3 25 .byte 0x25 + 199 00c4 6B000000 .4byte 0x6b + 200 00c8 08 .byte 0x8 + 201 00c9 00 .byte 0 + 202 00ca 08 .uleb128 0x8 + 203 00cb F6010000 .4byte .LASF17 + 204 00cf 03 .byte 0x3 + 205 00d0 26 .byte 0x26 + 206 00d1 9D000000 .4byte 0x9d + 207 00d5 09 .uleb128 0x9 + 208 00d6 CB010000 .4byte .LASF18 + 209 00da 01 .byte 0x1 + 210 00db 2C .byte 0x2c + 211 00dc 00000000 .4byte .LFB0 + 212 00e0 1C000000 .4byte .LFE0-.LFB0 + 213 00e4 01 .uleb128 0x1 + 214 00e5 9C .byte 0x9c + 215 00e6 09 .uleb128 0x9 + 216 00e7 4E010000 .4byte .LASF19 + 217 00eb 01 .byte 0x1 + 218 00ec 52 .byte 0x52 + 219 00ed 00000000 .4byte .LFB1 + 220 00f1 1C000000 .4byte .LFE1-.LFB1 + 221 00f5 01 .uleb128 0x1 + 222 00f6 9C .byte 0x9c + 223 00f7 0A .uleb128 0xa + 224 00f8 31010000 .4byte .LASF23 + 225 00fc 01 .byte 0x1 + 226 00fd 14 .byte 0x14 + 227 00fe CA000000 .4byte 0xca + 228 0102 05 .uleb128 0x5 + 229 0103 03 .byte 0x3 + 230 0104 00000000 .4byte Input_1_backup + 231 0108 00 .byte 0 + 232 .section .debug_abbrev,"",%progbits + 233 .Ldebug_abbrev0: + 234 0000 01 .uleb128 0x1 + 235 0001 11 .uleb128 0x11 + 236 0002 01 .byte 0x1 + 237 0003 25 .uleb128 0x25 + 238 0004 0E .uleb128 0xe + 239 0005 13 .uleb128 0x13 + 240 0006 0B .uleb128 0xb + 241 0007 03 .uleb128 0x3 + 242 0008 0E .uleb128 0xe + 243 0009 1B .uleb128 0x1b + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 7 + + + 244 000a 0E .uleb128 0xe + 245 000b 55 .uleb128 0x55 + 246 000c 17 .uleb128 0x17 + 247 000d 11 .uleb128 0x11 + 248 000e 01 .uleb128 0x1 + 249 000f 10 .uleb128 0x10 + 250 0010 17 .uleb128 0x17 + 251 0011 00 .byte 0 + 252 0012 00 .byte 0 + 253 0013 02 .uleb128 0x2 + 254 0014 24 .uleb128 0x24 + 255 0015 00 .byte 0 + 256 0016 0B .uleb128 0xb + 257 0017 0B .uleb128 0xb + 258 0018 3E .uleb128 0x3e + 259 0019 0B .uleb128 0xb + 260 001a 03 .uleb128 0x3 + 261 001b 0E .uleb128 0xe + 262 001c 00 .byte 0 + 263 001d 00 .byte 0 + 264 001e 03 .uleb128 0x3 + 265 001f 24 .uleb128 0x24 + 266 0020 00 .byte 0 + 267 0021 0B .uleb128 0xb + 268 0022 0B .uleb128 0xb + 269 0023 3E .uleb128 0x3e + 270 0024 0B .uleb128 0xb + 271 0025 03 .uleb128 0x3 + 272 0026 08 .uleb128 0x8 + 273 0027 00 .byte 0 + 274 0028 00 .byte 0 + 275 0029 04 .uleb128 0x4 + 276 002a 16 .uleb128 0x16 + 277 002b 00 .byte 0 + 278 002c 03 .uleb128 0x3 + 279 002d 0E .uleb128 0xe + 280 002e 3A .uleb128 0x3a + 281 002f 0B .uleb128 0xb + 282 0030 3B .uleb128 0x3b + 283 0031 05 .uleb128 0x5 + 284 0032 49 .uleb128 0x49 + 285 0033 13 .uleb128 0x13 + 286 0034 00 .byte 0 + 287 0035 00 .byte 0 + 288 0036 05 .uleb128 0x5 + 289 0037 35 .uleb128 0x35 + 290 0038 00 .byte 0 + 291 0039 49 .uleb128 0x49 + 292 003a 13 .uleb128 0x13 + 293 003b 00 .byte 0 + 294 003c 00 .byte 0 + 295 003d 06 .uleb128 0x6 + 296 003e 13 .uleb128 0x13 + 297 003f 01 .byte 0x1 + 298 0040 0B .uleb128 0xb + 299 0041 0B .uleb128 0xb + 300 0042 3A .uleb128 0x3a + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 8 + + + 301 0043 0B .uleb128 0xb + 302 0044 3B .uleb128 0x3b + 303 0045 0B .uleb128 0xb + 304 0046 01 .uleb128 0x1 + 305 0047 13 .uleb128 0x13 + 306 0048 00 .byte 0 + 307 0049 00 .byte 0 + 308 004a 07 .uleb128 0x7 + 309 004b 0D .uleb128 0xd + 310 004c 00 .byte 0 + 311 004d 03 .uleb128 0x3 + 312 004e 0E .uleb128 0xe + 313 004f 3A .uleb128 0x3a + 314 0050 0B .uleb128 0xb + 315 0051 3B .uleb128 0x3b + 316 0052 0B .uleb128 0xb + 317 0053 49 .uleb128 0x49 + 318 0054 13 .uleb128 0x13 + 319 0055 38 .uleb128 0x38 + 320 0056 0B .uleb128 0xb + 321 0057 00 .byte 0 + 322 0058 00 .byte 0 + 323 0059 08 .uleb128 0x8 + 324 005a 16 .uleb128 0x16 + 325 005b 00 .byte 0 + 326 005c 03 .uleb128 0x3 + 327 005d 0E .uleb128 0xe + 328 005e 3A .uleb128 0x3a + 329 005f 0B .uleb128 0xb + 330 0060 3B .uleb128 0x3b + 331 0061 0B .uleb128 0xb + 332 0062 49 .uleb128 0x49 + 333 0063 13 .uleb128 0x13 + 334 0064 00 .byte 0 + 335 0065 00 .byte 0 + 336 0066 09 .uleb128 0x9 + 337 0067 2E .uleb128 0x2e + 338 0068 00 .byte 0 + 339 0069 3F .uleb128 0x3f + 340 006a 19 .uleb128 0x19 + 341 006b 03 .uleb128 0x3 + 342 006c 0E .uleb128 0xe + 343 006d 3A .uleb128 0x3a + 344 006e 0B .uleb128 0xb + 345 006f 3B .uleb128 0x3b + 346 0070 0B .uleb128 0xb + 347 0071 27 .uleb128 0x27 + 348 0072 19 .uleb128 0x19 + 349 0073 11 .uleb128 0x11 + 350 0074 01 .uleb128 0x1 + 351 0075 12 .uleb128 0x12 + 352 0076 06 .uleb128 0x6 + 353 0077 40 .uleb128 0x40 + 354 0078 18 .uleb128 0x18 + 355 0079 9742 .uleb128 0x2117 + 356 007b 19 .uleb128 0x19 + 357 007c 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 9 + + + 358 007d 00 .byte 0 + 359 007e 0A .uleb128 0xa + 360 007f 34 .uleb128 0x34 + 361 0080 00 .byte 0 + 362 0081 03 .uleb128 0x3 + 363 0082 0E .uleb128 0xe + 364 0083 3A .uleb128 0x3a + 365 0084 0B .uleb128 0xb + 366 0085 3B .uleb128 0x3b + 367 0086 0B .uleb128 0xb + 368 0087 49 .uleb128 0x49 + 369 0088 13 .uleb128 0x13 + 370 0089 02 .uleb128 0x2 + 371 008a 18 .uleb128 0x18 + 372 008b 00 .byte 0 + 373 008c 00 .byte 0 + 374 008d 00 .byte 0 + 375 .section .debug_aranges,"",%progbits + 376 0000 24000000 .4byte 0x24 + 377 0004 0200 .2byte 0x2 + 378 0006 00000000 .4byte .Ldebug_info0 + 379 000a 04 .byte 0x4 + 380 000b 00 .byte 0 + 381 000c 0000 .2byte 0 + 382 000e 0000 .2byte 0 + 383 0010 00000000 .4byte .LFB0 + 384 0014 1C000000 .4byte .LFE0-.LFB0 + 385 0018 00000000 .4byte .LFB1 + 386 001c 1C000000 .4byte .LFE1-.LFB1 + 387 0020 00000000 .4byte 0 + 388 0024 00000000 .4byte 0 + 389 .section .debug_ranges,"",%progbits + 390 .Ldebug_ranges0: + 391 0000 00000000 .4byte .LFB0 + 392 0004 1C000000 .4byte .LFE0 + 393 0008 00000000 .4byte .LFB1 + 394 000c 1C000000 .4byte .LFE1 + 395 0010 00000000 .4byte 0 + 396 0014 00000000 .4byte 0 + 397 .section .debug_line,"",%progbits + 398 .Ldebug_line0: + 399 0000 81000000 .section .debug_str,"MS",%progbits,1 + 399 02005400 + 399 00000201 + 399 FB0E0D00 + 399 01010101 + 400 .LASF13: + 401 0000 72656733 .ascii "reg32\000" + 401 3200 + 402 .LASF16: + 403 0006 75736253 .ascii "usbState\000" + 403 74617465 + 403 00 + 404 .LASF22: + 405 000f 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 405 73657273 + 405 5C6A6167 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 10 + + + 405 756D6965 + 405 6C5C446F + 406 003d 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 406 50536F43 + 406 2D313031 + 406 5C547261 + 406 696E696E + 407 .LASF9: + 408 006a 666C6F61 .ascii "float\000" + 408 7400 + 409 .LASF1: + 410 0070 756E7369 .ascii "unsigned char\000" + 410 676E6564 + 410 20636861 + 410 7200 + 411 .LASF5: + 412 007e 6C6F6E67 .ascii "long unsigned int\000" + 412 20756E73 + 412 69676E65 + 412 6420696E + 412 7400 + 413 .LASF3: + 414 0090 73686F72 .ascii "short unsigned int\000" + 414 7420756E + 414 7369676E + 414 65642069 + 414 6E7400 + 415 .LASF20: + 416 00a3 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 416 43313120 + 416 352E342E + 416 31203230 + 416 31363036 + 417 00d6 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 417 20726576 + 417 6973696F + 417 6E203233 + 417 37373135 + 418 0109 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 418 66756E63 + 418 74696F6E + 418 2D736563 + 418 74696F6E + 419 .LASF23: + 420 0131 496E7075 .ascii "Input_1_backup\000" + 420 745F315F + 420 6261636B + 420 757000 + 421 .LASF10: + 422 0140 646F7562 .ascii "double\000" + 422 6C6500 + 423 .LASF12: + 424 0147 75696E74 .ascii "uint32\000" + 424 333200 + 425 .LASF19: + 426 014e 496E7075 .ascii "Input_1_Wakeup\000" + 426 745F315F + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 11 + + + 426 57616B65 + 426 757000 + 427 .LASF8: + 428 015d 756E7369 .ascii "unsigned int\000" + 428 676E6564 + 428 20696E74 + 428 00 + 429 .LASF7: + 430 016a 6C6F6E67 .ascii "long long unsigned int\000" + 430 206C6F6E + 430 6720756E + 430 7369676E + 430 65642069 + 431 .LASF15: + 432 0181 73696F53 .ascii "sioState\000" + 432 74617465 + 432 00 + 433 .LASF6: + 434 018a 6C6F6E67 .ascii "long long int\000" + 434 206C6F6E + 434 6720696E + 434 7400 + 435 .LASF21: + 436 0198 47656E65 .ascii "Generated_Source\\PSoC4\\Input_1_PM.c\000" + 436 72617465 + 436 645F536F + 436 75726365 + 436 5C50536F + 437 .LASF11: + 438 01bc 63686172 .ascii "char\000" + 438 00 + 439 .LASF2: + 440 01c1 73686F72 .ascii "short int\000" + 440 7420696E + 440 7400 + 441 .LASF18: + 442 01cb 496E7075 .ascii "Input_1_Sleep\000" + 442 745F315F + 442 536C6565 + 442 7000 + 443 .LASF14: + 444 01d9 70635374 .ascii "pcState\000" + 444 61746500 + 445 .LASF4: + 446 01e1 6C6F6E67 .ascii "long int\000" + 446 20696E74 + 446 00 + 447 .LASF0: + 448 01ea 7369676E .ascii "signed char\000" + 448 65642063 + 448 68617200 + 449 .LASF17: + 450 01f6 496E7075 .ascii "Input_1_BACKUP_STRUCT\000" + 450 745F315F + 450 4241434B + 450 55505F53 + 450 54525543 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cch2KHT2.s page 12 + + + 451 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/Input_1_PM.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/Input_1_PM.o new file mode 100644 index 0000000000000000000000000000000000000000..eaae32827b8713a3343e8880d8022b509e449882 GIT binary patch literal 3528 zcmbtWUuauZ7(e&kq)C@HcJ2Ok6S-sE*5Q&RTf6CGnwqZNRy#}oAYwy$MM0*F=bp?uh0>#=#*E)WKTG!%DD0MyhIVC-|LMamc ziBcr?BBglrRZ8*L62OQ=s|}yFbC4qAwEUu-3T8!?0{2LcN-h2=9iS2VihczUJ zm$CaxVC;KXjXhL}*d_7<Na5{k0&0Ap6*ZTy!mLq5SxZp=jc0-%>ahZ zwB+TG<5oxt+tQjG)?b2A7qk3oeleU2UCfmyaA4Ew3=+ zV?8l?e16WeU2lHLD!1xYyEZ@S6kBz>;d?<2X5O_e-*E#WmCa<=m|54VHmZ&Cl;9m#hPRJqSf%K<%V4{ixtZiHK$QFS5>S-uj07=de!*ZIWwQl zn#1X#bk;na$sWxd%{*uhx^~UBJo|w8)X4PYA-i6%OC`IM8cr2lt5K|&uKi5at2zzy z@R4K3vcu=hRK3`2ohV`f``J`I1KF>%>IE}ZHdBv7TwH85iautfJZu2yQD^z7n(w5X zLa-}!$_oXnc)ryXC8t%W*`kHqagOSKp0Li_Fs|EKu-Ch6xazcze$CEvxO)Z6s|A7r z2#&CQV4R|CGd0_8ie@nsHaOYPxhvO4NAeSMQwuY*({p(g;&?uP+#KY2&pJ-cGZ!7# z#MzoB<=L9J+oJ7xj_V!x-`9aYhHAeJ(uDp(va4J0Q7Pg>8A---FYCF>+DLco-)tip zI9s+=s0wW#*l50e#giFyr`Tkt)*IQPZPm6LJG6dnr*i{Z9UJ`D@5n%>4U-`@g+*k8 zmKP#JbcZBnyZ*<8yJ3Dkt6u1mAu_~9xi@5GyscsnG(1J#YcKYjT_+=dRgytv50qAA z`OXG5*0=JPPmT4Vei7in;m@ZUGO}SMu$#QnO2w8ZcTUUcIbcN#!eug& zlz_YLrB4p?zN;?Yl$vN4x%y!R2$gpTp> zELY>b3tr6uEAoi<5*bO#b`^3s-VMa-fsXOmomGAxg6EtJ2I&Ukbzvx?jpGxE%I|9g zaFmm@(eH-jm1#8Et_>w~UD6jA;rzY}?U%m>D!*^Qqn4Y1fL=p9_I^cNlf?e4YM$~f l#QT|yB;`j8ZBJZBycH4CWS&H-);&L8nN?`v)_C&nEx? literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/LED.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/LED.lst new file mode 100644 index 0000000..59edbc1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/LED.lst @@ -0,0 +1,1190 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "LED.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.LED_SetDriveMode,"ax",%progbits + 20 .align 2 + 21 .global LED_SetDriveMode + 22 .code 16 + 23 .thumb_func + 24 .type LED_SetDriveMode, %function + 25 LED_SetDriveMode: + 26 .LFB0: + 27 .file 1 "Generated_Source\\PSoC4\\LED.c" + 1:Generated_Source\PSoC4/LED.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/LED.c **** * File Name: LED.c + 3:Generated_Source\PSoC4/LED.c **** * Version 2.20 + 4:Generated_Source\PSoC4/LED.c **** * + 5:Generated_Source\PSoC4/LED.c **** * Description: + 6:Generated_Source\PSoC4/LED.c **** * This file contains API to enable firmware control of a Pins component. + 7:Generated_Source\PSoC4/LED.c **** * + 8:Generated_Source\PSoC4/LED.c **** ******************************************************************************** + 9:Generated_Source\PSoC4/LED.c **** * Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. + 10:Generated_Source\PSoC4/LED.c **** * You may use this file only in accordance with the license, terms, conditions, + 11:Generated_Source\PSoC4/LED.c **** * disclaimers, and limitations in the end user license agreement accompanying + 12:Generated_Source\PSoC4/LED.c **** * the software package with which this file was provided. + 13:Generated_Source\PSoC4/LED.c **** *******************************************************************************/ + 14:Generated_Source\PSoC4/LED.c **** + 15:Generated_Source\PSoC4/LED.c **** #include "cytypes.h" + 16:Generated_Source\PSoC4/LED.c **** #include "LED.h" + 17:Generated_Source\PSoC4/LED.c **** + 18:Generated_Source\PSoC4/LED.c **** + 19:Generated_Source\PSoC4/LED.c **** #if defined(LED__PC) + 20:Generated_Source\PSoC4/LED.c **** #define LED_SetP4PinDriveMode(shift, mode) \ + 21:Generated_Source\PSoC4/LED.c **** do { \ + 22:Generated_Source\PSoC4/LED.c **** LED_PC = (LED_PC & \ + 23:Generated_Source\PSoC4/LED.c **** (uint32)(~(uint32)(LED_DRIVE_MODE_IND_MASK << \ + 24:Generated_Source\PSoC4/LED.c **** (LED_DRIVE_MODE_BITS * (shift))))) | \ + 25:Generated_Source\PSoC4/LED.c **** (uint32)((uint32)(mode) << \ + 26:Generated_Source\PSoC4/LED.c **** (LED_DRIVE_MODE_BITS * (shift))); \ + 27:Generated_Source\PSoC4/LED.c **** } while (0) + 28:Generated_Source\PSoC4/LED.c **** #else + 29:Generated_Source\PSoC4/LED.c **** #if (CY_PSOC4_4200L) + 30:Generated_Source\PSoC4/LED.c **** #define LED_SetP4PinDriveMode(shift, mode) \ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 2 + + + 31:Generated_Source\PSoC4/LED.c **** do { \ + 32:Generated_Source\PSoC4/LED.c **** LED_USBIO_CTRL_REG = (LED_USBIO_CTRL_REG & \ + 33:Generated_Source\PSoC4/LED.c **** (uint32)(~(uint32)(LED_DRIVE_MODE_IND_MASK << \ + 34:Generated_Source\PSoC4/LED.c **** (LED_DRIVE_MODE_BITS * (shift))))) | \ + 35:Generated_Source\PSoC4/LED.c **** (uint32)((uint32)(mode) << \ + 36:Generated_Source\PSoC4/LED.c **** (LED_DRIVE_MODE_BITS * (shift))); \ + 37:Generated_Source\PSoC4/LED.c **** } while (0) + 38:Generated_Source\PSoC4/LED.c **** #endif + 39:Generated_Source\PSoC4/LED.c **** #endif + 40:Generated_Source\PSoC4/LED.c **** + 41:Generated_Source\PSoC4/LED.c **** + 42:Generated_Source\PSoC4/LED.c **** #if defined(LED__PC) || (CY_PSOC4_4200L) + 43:Generated_Source\PSoC4/LED.c **** /******************************************************************************* + 44:Generated_Source\PSoC4/LED.c **** * Function Name: LED_SetDriveMode + 45:Generated_Source\PSoC4/LED.c **** ****************************************************************************//** + 46:Generated_Source\PSoC4/LED.c **** * + 47:Generated_Source\PSoC4/LED.c **** * \brief Sets the drive mode for each of the Pins component's pins. + 48:Generated_Source\PSoC4/LED.c **** * + 49:Generated_Source\PSoC4/LED.c **** * Note This affects all pins in the Pins component instance. Use the + 50:Generated_Source\PSoC4/LED.c **** * Per-Pin APIs if you wish to control individual pin's drive modes. + 51:Generated_Source\PSoC4/LED.c **** * + 52:Generated_Source\PSoC4/LED.c **** * Note USBIOs have limited drive functionality. Refer to the Drive Mode + 53:Generated_Source\PSoC4/LED.c **** * parameter for more information. + 54:Generated_Source\PSoC4/LED.c **** * + 55:Generated_Source\PSoC4/LED.c **** * \param mode + 56:Generated_Source\PSoC4/LED.c **** * Mode for the selected signals. Valid options are documented in + 57:Generated_Source\PSoC4/LED.c **** * \ref driveMode. + 58:Generated_Source\PSoC4/LED.c **** * + 59:Generated_Source\PSoC4/LED.c **** * \return + 60:Generated_Source\PSoC4/LED.c **** * None + 61:Generated_Source\PSoC4/LED.c **** * + 62:Generated_Source\PSoC4/LED.c **** * \sideeffect + 63:Generated_Source\PSoC4/LED.c **** * If you use read-modify-write operations that are not atomic, the ISR can + 64:Generated_Source\PSoC4/LED.c **** * cause corruption of this function. An ISR that interrupts this function + 65:Generated_Source\PSoC4/LED.c **** * and performs writes to the Pins component Drive Mode registers can cause + 66:Generated_Source\PSoC4/LED.c **** * corrupted port data. To avoid this issue, you should either use the Per-Pin + 67:Generated_Source\PSoC4/LED.c **** * APIs (primary method) or disable interrupts around this function. + 68:Generated_Source\PSoC4/LED.c **** * + 69:Generated_Source\PSoC4/LED.c **** * \funcusage + 70:Generated_Source\PSoC4/LED.c **** * \snippet LED_SUT.c usage_LED_SetDriveMode + 71:Generated_Source\PSoC4/LED.c **** *******************************************************************************/ + 72:Generated_Source\PSoC4/LED.c **** void LED_SetDriveMode(uint8 mode) + 73:Generated_Source\PSoC4/LED.c **** { + 28 .loc 1 73 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 82B0 sub sp, sp, #8 + 37 .cfi_def_cfa_offset 16 + 38 0004 00AF add r7, sp, #0 + 39 .cfi_def_cfa_register 7 + 40 0006 0200 movs r2, r0 + 41 0008 FB1D adds r3, r7, #7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 3 + + + 42 000a 1A70 strb r2, [r3] + 74:Generated_Source\PSoC4/LED.c **** LED_SetP4PinDriveMode(LED__0__SHIFT, mode); + 43 .loc 1 74 0 + 44 000c 064B ldr r3, .L2 + 45 000e 064A ldr r2, .L2 + 46 0010 1268 ldr r2, [r2] + 47 0012 0649 ldr r1, .L2+4 + 48 0014 1140 ands r1, r2 + 49 0016 FA1D adds r2, r7, #7 + 50 0018 1278 ldrb r2, [r2] + 51 001a 9204 lsls r2, r2, #18 + 52 001c 0A43 orrs r2, r1 + 53 001e 1A60 str r2, [r3] + 75:Generated_Source\PSoC4/LED.c **** } + 54 .loc 1 75 0 + 55 0020 C046 nop + 56 0022 BD46 mov sp, r7 + 57 0024 02B0 add sp, sp, #8 + 58 @ sp needed + 59 0026 80BD pop {r7, pc} + 60 .L3: + 61 .align 2 + 62 .L2: + 63 0028 08010440 .word 1074004232 + 64 002c FFFFE3FF .word -1835009 + 65 .cfi_endproc + 66 .LFE0: + 67 .size LED_SetDriveMode, .-LED_SetDriveMode + 68 .section .text.LED_Write,"ax",%progbits + 69 .align 2 + 70 .global LED_Write + 71 .code 16 + 72 .thumb_func + 73 .type LED_Write, %function + 74 LED_Write: + 75 .LFB1: + 76:Generated_Source\PSoC4/LED.c **** #endif + 77:Generated_Source\PSoC4/LED.c **** + 78:Generated_Source\PSoC4/LED.c **** + 79:Generated_Source\PSoC4/LED.c **** /******************************************************************************* + 80:Generated_Source\PSoC4/LED.c **** * Function Name: LED_Write + 81:Generated_Source\PSoC4/LED.c **** ****************************************************************************//** + 82:Generated_Source\PSoC4/LED.c **** * + 83:Generated_Source\PSoC4/LED.c **** * \brief Writes the value to the physical port (data output register), masking + 84:Generated_Source\PSoC4/LED.c **** * and shifting the bits appropriately. + 85:Generated_Source\PSoC4/LED.c **** * + 86:Generated_Source\PSoC4/LED.c **** * The data output register controls the signal applied to the physical pin in + 87:Generated_Source\PSoC4/LED.c **** * conjunction with the drive mode parameter. This function avoids changing + 88:Generated_Source\PSoC4/LED.c **** * other bits in the port by using the appropriate method (read-modify-write or + 89:Generated_Source\PSoC4/LED.c **** * bit banding). + 90:Generated_Source\PSoC4/LED.c **** * + 91:Generated_Source\PSoC4/LED.c **** * Note This function should not be used on a hardware digital output pin + 92:Generated_Source\PSoC4/LED.c **** * as it is driven by the hardware signal attached to it. + 93:Generated_Source\PSoC4/LED.c **** * + 94:Generated_Source\PSoC4/LED.c **** * \param value + 95:Generated_Source\PSoC4/LED.c **** * Value to write to the component instance. + 96:Generated_Source\PSoC4/LED.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 4 + + + 97:Generated_Source\PSoC4/LED.c **** * \return + 98:Generated_Source\PSoC4/LED.c **** * None + 99:Generated_Source\PSoC4/LED.c **** * + 100:Generated_Source\PSoC4/LED.c **** * \sideeffect + 101:Generated_Source\PSoC4/LED.c **** * If you use read-modify-write operations that are not atomic; the Interrupt + 102:Generated_Source\PSoC4/LED.c **** * Service Routines (ISR) can cause corruption of this function. An ISR that + 103:Generated_Source\PSoC4/LED.c **** * interrupts this function and performs writes to the Pins component data + 104:Generated_Source\PSoC4/LED.c **** * register can cause corrupted port data. To avoid this issue, you should + 105:Generated_Source\PSoC4/LED.c **** * either use the Per-Pin APIs (primary method) or disable interrupts around + 106:Generated_Source\PSoC4/LED.c **** * this function. + 107:Generated_Source\PSoC4/LED.c **** * + 108:Generated_Source\PSoC4/LED.c **** * \funcusage + 109:Generated_Source\PSoC4/LED.c **** * \snippet LED_SUT.c usage_LED_Write + 110:Generated_Source\PSoC4/LED.c **** *******************************************************************************/ + 111:Generated_Source\PSoC4/LED.c **** void LED_Write(uint8 value) + 112:Generated_Source\PSoC4/LED.c **** { + 76 .loc 1 112 0 + 77 .cfi_startproc + 78 @ args = 0, pretend = 0, frame = 16 + 79 @ frame_needed = 1, uses_anonymous_args = 0 + 80 0000 80B5 push {r7, lr} + 81 .cfi_def_cfa_offset 8 + 82 .cfi_offset 7, -8 + 83 .cfi_offset 14, -4 + 84 0002 84B0 sub sp, sp, #16 + 85 .cfi_def_cfa_offset 24 + 86 0004 00AF add r7, sp, #0 + 87 .cfi_def_cfa_register 7 + 88 0006 0200 movs r2, r0 + 89 0008 FB1D adds r3, r7, #7 + 90 000a 1A70 strb r2, [r3] + 113:Generated_Source\PSoC4/LED.c **** uint8 drVal = (uint8)(LED_DR & (uint8)(~LED_MASK)); + 91 .loc 1 113 0 + 92 000c 0F4B ldr r3, .L5 + 93 000e 1B68 ldr r3, [r3] + 94 0010 DAB2 uxtb r2, r3 + 95 0012 0F23 movs r3, #15 + 96 0014 FB18 adds r3, r7, r3 + 97 0016 4021 movs r1, #64 + 98 0018 8A43 bics r2, r1 + 99 001a 1A70 strb r2, [r3] + 114:Generated_Source\PSoC4/LED.c **** drVal = (drVal | ((uint8)(value << LED_SHIFT) & LED_MASK)); + 100 .loc 1 114 0 + 101 001c FB1D adds r3, r7, #7 + 102 001e 1B78 ldrb r3, [r3] + 103 0020 9B01 lsls r3, r3, #6 + 104 0022 DBB2 uxtb r3, r3 + 105 0024 4022 movs r2, #64 + 106 0026 1340 ands r3, r2 + 107 0028 D9B2 uxtb r1, r3 + 108 002a 0F23 movs r3, #15 + 109 002c FB18 adds r3, r7, r3 + 110 002e 0F22 movs r2, #15 + 111 0030 BA18 adds r2, r7, r2 + 112 0032 1278 ldrb r2, [r2] + 113 0034 0A43 orrs r2, r1 + 114 0036 1A70 strb r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 5 + + + 115:Generated_Source\PSoC4/LED.c **** LED_DR = (uint32)drVal; + 115 .loc 1 115 0 + 116 0038 044B ldr r3, .L5 + 117 003a 0F22 movs r2, #15 + 118 003c BA18 adds r2, r7, r2 + 119 003e 1278 ldrb r2, [r2] + 120 0040 1A60 str r2, [r3] + 116:Generated_Source\PSoC4/LED.c **** } + 121 .loc 1 116 0 + 122 0042 C046 nop + 123 0044 BD46 mov sp, r7 + 124 0046 04B0 add sp, sp, #16 + 125 @ sp needed + 126 0048 80BD pop {r7, pc} + 127 .L6: + 128 004a C046 .align 2 + 129 .L5: + 130 004c 00010440 .word 1074004224 + 131 .cfi_endproc + 132 .LFE1: + 133 .size LED_Write, .-LED_Write + 134 .section .text.LED_Read,"ax",%progbits + 135 .align 2 + 136 .global LED_Read + 137 .code 16 + 138 .thumb_func + 139 .type LED_Read, %function + 140 LED_Read: + 141 .LFB2: + 117:Generated_Source\PSoC4/LED.c **** + 118:Generated_Source\PSoC4/LED.c **** + 119:Generated_Source\PSoC4/LED.c **** /******************************************************************************* + 120:Generated_Source\PSoC4/LED.c **** * Function Name: LED_Read + 121:Generated_Source\PSoC4/LED.c **** ****************************************************************************//** + 122:Generated_Source\PSoC4/LED.c **** * + 123:Generated_Source\PSoC4/LED.c **** * \brief Reads the associated physical port (pin status register) and masks + 124:Generated_Source\PSoC4/LED.c **** * the required bits according to the width and bit position of the component + 125:Generated_Source\PSoC4/LED.c **** * instance. + 126:Generated_Source\PSoC4/LED.c **** * + 127:Generated_Source\PSoC4/LED.c **** * The pin's status register returns the current logic level present on the + 128:Generated_Source\PSoC4/LED.c **** * physical pin. + 129:Generated_Source\PSoC4/LED.c **** * + 130:Generated_Source\PSoC4/LED.c **** * \return + 131:Generated_Source\PSoC4/LED.c **** * The current value for the pins in the component as a right justified number. + 132:Generated_Source\PSoC4/LED.c **** * + 133:Generated_Source\PSoC4/LED.c **** * \funcusage + 134:Generated_Source\PSoC4/LED.c **** * \snippet LED_SUT.c usage_LED_Read + 135:Generated_Source\PSoC4/LED.c **** *******************************************************************************/ + 136:Generated_Source\PSoC4/LED.c **** uint8 LED_Read(void) + 137:Generated_Source\PSoC4/LED.c **** { + 142 .loc 1 137 0 + 143 .cfi_startproc + 144 @ args = 0, pretend = 0, frame = 0 + 145 @ frame_needed = 1, uses_anonymous_args = 0 + 146 0000 80B5 push {r7, lr} + 147 .cfi_def_cfa_offset 8 + 148 .cfi_offset 7, -8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 6 + + + 149 .cfi_offset 14, -4 + 150 0002 00AF add r7, sp, #0 + 151 .cfi_def_cfa_register 7 + 138:Generated_Source\PSoC4/LED.c **** return (uint8)((LED_PS & LED_MASK) >> LED_SHIFT); + 152 .loc 1 138 0 + 153 0004 044B ldr r3, .L9 + 154 0006 1B68 ldr r3, [r3] + 155 0008 4022 movs r2, #64 + 156 000a 1340 ands r3, r2 + 157 000c 9B09 lsrs r3, r3, #6 + 158 000e DBB2 uxtb r3, r3 + 139:Generated_Source\PSoC4/LED.c **** } + 159 .loc 1 139 0 + 160 0010 1800 movs r0, r3 + 161 0012 BD46 mov sp, r7 + 162 @ sp needed + 163 0014 80BD pop {r7, pc} + 164 .L10: + 165 0016 C046 .align 2 + 166 .L9: + 167 0018 04010440 .word 1074004228 + 168 .cfi_endproc + 169 .LFE2: + 170 .size LED_Read, .-LED_Read + 171 .section .text.LED_ReadDataReg,"ax",%progbits + 172 .align 2 + 173 .global LED_ReadDataReg + 174 .code 16 + 175 .thumb_func + 176 .type LED_ReadDataReg, %function + 177 LED_ReadDataReg: + 178 .LFB3: + 140:Generated_Source\PSoC4/LED.c **** + 141:Generated_Source\PSoC4/LED.c **** + 142:Generated_Source\PSoC4/LED.c **** /******************************************************************************* + 143:Generated_Source\PSoC4/LED.c **** * Function Name: LED_ReadDataReg + 144:Generated_Source\PSoC4/LED.c **** ****************************************************************************//** + 145:Generated_Source\PSoC4/LED.c **** * + 146:Generated_Source\PSoC4/LED.c **** * \brief Reads the associated physical port's data output register and masks + 147:Generated_Source\PSoC4/LED.c **** * the correct bits according to the width and bit position of the component + 148:Generated_Source\PSoC4/LED.c **** * instance. + 149:Generated_Source\PSoC4/LED.c **** * + 150:Generated_Source\PSoC4/LED.c **** * The data output register controls the signal applied to the physical pin in + 151:Generated_Source\PSoC4/LED.c **** * conjunction with the drive mode parameter. This is not the same as the + 152:Generated_Source\PSoC4/LED.c **** * preferred LED_Read() API because the + 153:Generated_Source\PSoC4/LED.c **** * LED_ReadDataReg() reads the data register instead of the status + 154:Generated_Source\PSoC4/LED.c **** * register. For output pins this is a useful function to determine the value + 155:Generated_Source\PSoC4/LED.c **** * just written to the pin. + 156:Generated_Source\PSoC4/LED.c **** * + 157:Generated_Source\PSoC4/LED.c **** * \return + 158:Generated_Source\PSoC4/LED.c **** * The current value of the data register masked and shifted into a right + 159:Generated_Source\PSoC4/LED.c **** * justified number for the component instance. + 160:Generated_Source\PSoC4/LED.c **** * + 161:Generated_Source\PSoC4/LED.c **** * \funcusage + 162:Generated_Source\PSoC4/LED.c **** * \snippet LED_SUT.c usage_LED_ReadDataReg + 163:Generated_Source\PSoC4/LED.c **** *******************************************************************************/ + 164:Generated_Source\PSoC4/LED.c **** uint8 LED_ReadDataReg(void) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 7 + + + 165:Generated_Source\PSoC4/LED.c **** { + 179 .loc 1 165 0 + 180 .cfi_startproc + 181 @ args = 0, pretend = 0, frame = 0 + 182 @ frame_needed = 1, uses_anonymous_args = 0 + 183 0000 80B5 push {r7, lr} + 184 .cfi_def_cfa_offset 8 + 185 .cfi_offset 7, -8 + 186 .cfi_offset 14, -4 + 187 0002 00AF add r7, sp, #0 + 188 .cfi_def_cfa_register 7 + 166:Generated_Source\PSoC4/LED.c **** return (uint8)((LED_DR & LED_MASK) >> LED_SHIFT); + 189 .loc 1 166 0 + 190 0004 044B ldr r3, .L13 + 191 0006 1B68 ldr r3, [r3] + 192 0008 4022 movs r2, #64 + 193 000a 1340 ands r3, r2 + 194 000c 9B09 lsrs r3, r3, #6 + 195 000e DBB2 uxtb r3, r3 + 167:Generated_Source\PSoC4/LED.c **** } + 196 .loc 1 167 0 + 197 0010 1800 movs r0, r3 + 198 0012 BD46 mov sp, r7 + 199 @ sp needed + 200 0014 80BD pop {r7, pc} + 201 .L14: + 202 0016 C046 .align 2 + 203 .L13: + 204 0018 00010440 .word 1074004224 + 205 .cfi_endproc + 206 .LFE3: + 207 .size LED_ReadDataReg, .-LED_ReadDataReg + 208 .section .text.LED_SetInterruptMode,"ax",%progbits + 209 .align 2 + 210 .global LED_SetInterruptMode + 211 .code 16 + 212 .thumb_func + 213 .type LED_SetInterruptMode, %function + 214 LED_SetInterruptMode: + 215 .LFB4: + 168:Generated_Source\PSoC4/LED.c **** + 169:Generated_Source\PSoC4/LED.c **** + 170:Generated_Source\PSoC4/LED.c **** /******************************************************************************* + 171:Generated_Source\PSoC4/LED.c **** * Function Name: LED_SetInterruptMode + 172:Generated_Source\PSoC4/LED.c **** ****************************************************************************//** + 173:Generated_Source\PSoC4/LED.c **** * + 174:Generated_Source\PSoC4/LED.c **** * \brief Configures the interrupt mode for each of the Pins component's + 175:Generated_Source\PSoC4/LED.c **** * pins. Alternatively you may set the interrupt mode for all the pins + 176:Generated_Source\PSoC4/LED.c **** * specified in the Pins component. + 177:Generated_Source\PSoC4/LED.c **** * + 178:Generated_Source\PSoC4/LED.c **** * Note The interrupt is port-wide and therefore any enabled pin + 179:Generated_Source\PSoC4/LED.c **** * interrupt may trigger it. + 180:Generated_Source\PSoC4/LED.c **** * + 181:Generated_Source\PSoC4/LED.c **** * \param position + 182:Generated_Source\PSoC4/LED.c **** * The pin position as listed in the Pins component. You may OR these to be + 183:Generated_Source\PSoC4/LED.c **** * able to configure the interrupt mode of multiple pins within a Pins + 184:Generated_Source\PSoC4/LED.c **** * component. Or you may use LED_INTR_ALL to configure the + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 8 + + + 185:Generated_Source\PSoC4/LED.c **** * interrupt mode of all the pins in the Pins component. + 186:Generated_Source\PSoC4/LED.c **** * - LED_0_INTR (First pin in the list) + 187:Generated_Source\PSoC4/LED.c **** * - LED_1_INTR (Second pin in the list) + 188:Generated_Source\PSoC4/LED.c **** * - ... + 189:Generated_Source\PSoC4/LED.c **** * - LED_INTR_ALL (All pins in Pins component) + 190:Generated_Source\PSoC4/LED.c **** * + 191:Generated_Source\PSoC4/LED.c **** * \param mode + 192:Generated_Source\PSoC4/LED.c **** * Interrupt mode for the selected pins. Valid options are documented in + 193:Generated_Source\PSoC4/LED.c **** * \ref intrMode. + 194:Generated_Source\PSoC4/LED.c **** * + 195:Generated_Source\PSoC4/LED.c **** * \return + 196:Generated_Source\PSoC4/LED.c **** * None + 197:Generated_Source\PSoC4/LED.c **** * + 198:Generated_Source\PSoC4/LED.c **** * \sideeffect + 199:Generated_Source\PSoC4/LED.c **** * It is recommended that the interrupt be disabled before calling this + 200:Generated_Source\PSoC4/LED.c **** * function to avoid unintended interrupt requests. Note that the interrupt + 201:Generated_Source\PSoC4/LED.c **** * type is port wide, and therefore will trigger for any enabled pin on the + 202:Generated_Source\PSoC4/LED.c **** * port. + 203:Generated_Source\PSoC4/LED.c **** * + 204:Generated_Source\PSoC4/LED.c **** * \funcusage + 205:Generated_Source\PSoC4/LED.c **** * \snippet LED_SUT.c usage_LED_SetInterruptMode + 206:Generated_Source\PSoC4/LED.c **** *******************************************************************************/ + 207:Generated_Source\PSoC4/LED.c **** void LED_SetInterruptMode(uint16 position, uint16 mode) + 208:Generated_Source\PSoC4/LED.c **** { + 216 .loc 1 208 0 + 217 .cfi_startproc + 218 @ args = 0, pretend = 0, frame = 16 + 219 @ frame_needed = 1, uses_anonymous_args = 0 + 220 0000 80B5 push {r7, lr} + 221 .cfi_def_cfa_offset 8 + 222 .cfi_offset 7, -8 + 223 .cfi_offset 14, -4 + 224 0002 84B0 sub sp, sp, #16 + 225 .cfi_def_cfa_offset 24 + 226 0004 00AF add r7, sp, #0 + 227 .cfi_def_cfa_register 7 + 228 0006 0200 movs r2, r0 + 229 0008 BB1D adds r3, r7, #6 + 230 000a 1A80 strh r2, [r3] + 231 000c 3B1D adds r3, r7, #4 + 232 000e 0A1C adds r2, r1, #0 + 233 0010 1A80 strh r2, [r3] + 209:Generated_Source\PSoC4/LED.c **** uint32 intrCfg; + 210:Generated_Source\PSoC4/LED.c **** + 211:Generated_Source\PSoC4/LED.c **** intrCfg = LED_INTCFG & (uint32)(~(uint32)position); + 234 .loc 1 211 0 + 235 0012 0B4B ldr r3, .L16 + 236 0014 1B68 ldr r3, [r3] + 237 0016 BA1D adds r2, r7, #6 + 238 0018 1288 ldrh r2, [r2] + 239 001a D243 mvns r2, r2 + 240 001c 1340 ands r3, r2 + 241 001e FB60 str r3, [r7, #12] + 212:Generated_Source\PSoC4/LED.c **** LED_INTCFG = intrCfg | ((uint32)position & (uint32)mode); + 242 .loc 1 212 0 + 243 0020 074B ldr r3, .L16 + 244 0022 BA1D adds r2, r7, #6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 9 + + + 245 0024 391D adds r1, r7, #4 + 246 0026 1288 ldrh r2, [r2] + 247 0028 0988 ldrh r1, [r1] + 248 002a 0A40 ands r2, r1 + 249 002c 92B2 uxth r2, r2 + 250 002e 1100 movs r1, r2 + 251 0030 FA68 ldr r2, [r7, #12] + 252 0032 0A43 orrs r2, r1 + 253 0034 1A60 str r2, [r3] + 213:Generated_Source\PSoC4/LED.c **** } + 254 .loc 1 213 0 + 255 0036 C046 nop + 256 0038 BD46 mov sp, r7 + 257 003a 04B0 add sp, sp, #16 + 258 @ sp needed + 259 003c 80BD pop {r7, pc} + 260 .L17: + 261 003e C046 .align 2 + 262 .L16: + 263 0040 0C010440 .word 1074004236 + 264 .cfi_endproc + 265 .LFE4: + 266 .size LED_SetInterruptMode, .-LED_SetInterruptMode + 267 .section .text.LED_ClearInterrupt,"ax",%progbits + 268 .align 2 + 269 .global LED_ClearInterrupt + 270 .code 16 + 271 .thumb_func + 272 .type LED_ClearInterrupt, %function + 273 LED_ClearInterrupt: + 274 .LFB5: + 214:Generated_Source\PSoC4/LED.c **** + 215:Generated_Source\PSoC4/LED.c **** + 216:Generated_Source\PSoC4/LED.c **** /******************************************************************************* + 217:Generated_Source\PSoC4/LED.c **** * Function Name: LED_ClearInterrupt + 218:Generated_Source\PSoC4/LED.c **** ****************************************************************************//** + 219:Generated_Source\PSoC4/LED.c **** * + 220:Generated_Source\PSoC4/LED.c **** * \brief Clears any active interrupts attached with the component and returns + 221:Generated_Source\PSoC4/LED.c **** * the value of the interrupt status register allowing determination of which + 222:Generated_Source\PSoC4/LED.c **** * pins generated an interrupt event. + 223:Generated_Source\PSoC4/LED.c **** * + 224:Generated_Source\PSoC4/LED.c **** * \return + 225:Generated_Source\PSoC4/LED.c **** * The right-shifted current value of the interrupt status register. Each pin + 226:Generated_Source\PSoC4/LED.c **** * has one bit set if it generated an interrupt event. For example, bit 0 is + 227:Generated_Source\PSoC4/LED.c **** * for pin 0 and bit 1 is for pin 1 of the Pins component. + 228:Generated_Source\PSoC4/LED.c **** * + 229:Generated_Source\PSoC4/LED.c **** * \sideeffect + 230:Generated_Source\PSoC4/LED.c **** * Clears all bits of the physical port's interrupt status register, not just + 231:Generated_Source\PSoC4/LED.c **** * those associated with the Pins component. + 232:Generated_Source\PSoC4/LED.c **** * + 233:Generated_Source\PSoC4/LED.c **** * \funcusage + 234:Generated_Source\PSoC4/LED.c **** * \snippet LED_SUT.c usage_LED_ClearInterrupt + 235:Generated_Source\PSoC4/LED.c **** *******************************************************************************/ + 236:Generated_Source\PSoC4/LED.c **** uint8 LED_ClearInterrupt(void) + 237:Generated_Source\PSoC4/LED.c **** { + 275 .loc 1 237 0 + 276 .cfi_startproc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 10 + + + 277 @ args = 0, pretend = 0, frame = 8 + 278 @ frame_needed = 1, uses_anonymous_args = 0 + 279 0000 80B5 push {r7, lr} + 280 .cfi_def_cfa_offset 8 + 281 .cfi_offset 7, -8 + 282 .cfi_offset 14, -4 + 283 0002 82B0 sub sp, sp, #8 + 284 .cfi_def_cfa_offset 16 + 285 0004 00AF add r7, sp, #0 + 286 .cfi_def_cfa_register 7 + 238:Generated_Source\PSoC4/LED.c **** uint8 maskedStatus = (uint8)(LED_INTSTAT & LED_MASK); + 287 .loc 1 238 0 + 288 0006 094B ldr r3, .L20 + 289 0008 1B68 ldr r3, [r3] + 290 000a DAB2 uxtb r2, r3 + 291 000c FB1D adds r3, r7, #7 + 292 000e 4021 movs r1, #64 + 293 0010 0A40 ands r2, r1 + 294 0012 1A70 strb r2, [r3] + 239:Generated_Source\PSoC4/LED.c **** LED_INTSTAT = maskedStatus; + 295 .loc 1 239 0 + 296 0014 054B ldr r3, .L20 + 297 0016 FA1D adds r2, r7, #7 + 298 0018 1278 ldrb r2, [r2] + 299 001a 1A60 str r2, [r3] + 240:Generated_Source\PSoC4/LED.c **** return maskedStatus >> LED_SHIFT; + 300 .loc 1 240 0 + 301 001c FB1D adds r3, r7, #7 + 302 001e 1B78 ldrb r3, [r3] + 303 0020 9B09 lsrs r3, r3, #6 + 304 0022 DBB2 uxtb r3, r3 + 241:Generated_Source\PSoC4/LED.c **** } + 305 .loc 1 241 0 + 306 0024 1800 movs r0, r3 + 307 0026 BD46 mov sp, r7 + 308 0028 02B0 add sp, sp, #8 + 309 @ sp needed + 310 002a 80BD pop {r7, pc} + 311 .L21: + 312 .align 2 + 313 .L20: + 314 002c 10010440 .word 1074004240 + 315 .cfi_endproc + 316 .LFE5: + 317 .size LED_ClearInterrupt, .-LED_ClearInterrupt + 318 .text + 319 .Letext0: + 320 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 321 .section .debug_info,"",%progbits + 322 .Ldebug_info0: + 323 0000 96010000 .4byte 0x196 + 324 0004 0400 .2byte 0x4 + 325 0006 00000000 .4byte .Ldebug_abbrev0 + 326 000a 04 .byte 0x4 + 327 000b 01 .uleb128 0x1 + 328 000c F2000000 .4byte .LASF28 + 329 0010 0C .byte 0xc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 11 + + + 330 0011 24020000 .4byte .LASF29 + 331 0015 3C000000 .4byte .LASF30 + 332 0019 00000000 .4byte .Ldebug_ranges0+0 + 333 001d 00000000 .4byte 0 + 334 0021 00000000 .4byte .Ldebug_line0 + 335 0025 02 .uleb128 0x2 + 336 0026 01 .byte 0x1 + 337 0027 06 .byte 0x6 + 338 0028 18020000 .4byte .LASF0 + 339 002c 02 .uleb128 0x2 + 340 002d 01 .byte 0x1 + 341 002e 08 .byte 0x8 + 342 002f 9D000000 .4byte .LASF1 + 343 0033 02 .uleb128 0x2 + 344 0034 02 .byte 0x2 + 345 0035 05 .byte 0x5 + 346 0036 FF010000 .4byte .LASF2 + 347 003a 02 .uleb128 0x2 + 348 003b 02 .byte 0x2 + 349 003c 07 .byte 0x7 + 350 003d D6000000 .4byte .LASF3 + 351 0041 02 .uleb128 0x2 + 352 0042 04 .byte 0x4 + 353 0043 05 .byte 0x5 + 354 0044 0F020000 .4byte .LASF4 + 355 0048 02 .uleb128 0x2 + 356 0049 04 .byte 0x4 + 357 004a 07 .byte 0x7 + 358 004b C4000000 .4byte .LASF5 + 359 004f 02 .uleb128 0x2 + 360 0050 08 .byte 0x8 + 361 0051 05 .byte 0x5 + 362 0052 DF010000 .4byte .LASF6 + 363 0056 02 .uleb128 0x2 + 364 0057 08 .byte 0x8 + 365 0058 07 .byte 0x7 + 366 0059 C3010000 .4byte .LASF7 + 367 005d 03 .uleb128 0x3 + 368 005e 04 .byte 0x4 + 369 005f 05 .byte 0x5 + 370 0060 696E7400 .ascii "int\000" + 371 0064 02 .uleb128 0x2 + 372 0065 04 .byte 0x4 + 373 0066 07 .byte 0x7 + 374 0067 B6010000 .4byte .LASF8 + 375 006b 04 .uleb128 0x4 + 376 006c 09020000 .4byte .LASF9 + 377 0070 02 .byte 0x2 + 378 0071 E401 .2byte 0x1e4 + 379 0073 2C000000 .4byte 0x2c + 380 0077 04 .uleb128 0x4 + 381 0078 97010000 .4byte .LASF10 + 382 007c 02 .byte 0x2 + 383 007d E501 .2byte 0x1e5 + 384 007f 3A000000 .4byte 0x3a + 385 0083 04 .uleb128 0x4 + 386 0084 A7010000 .4byte .LASF11 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 12 + + + 387 0088 02 .byte 0x2 + 388 0089 E601 .2byte 0x1e6 + 389 008b 48000000 .4byte 0x48 + 390 008f 02 .uleb128 0x2 + 391 0090 04 .byte 0x4 + 392 0091 04 .byte 0x4 + 393 0092 97000000 .4byte .LASF12 + 394 0096 02 .uleb128 0x2 + 395 0097 08 .byte 0x8 + 396 0098 04 .byte 0x4 + 397 0099 90010000 .4byte .LASF13 + 398 009d 02 .uleb128 0x2 + 399 009e 01 .byte 0x1 + 400 009f 08 .byte 0x8 + 401 00a0 FA010000 .4byte .LASF14 + 402 00a4 04 .uleb128 0x4 + 403 00a5 00000000 .4byte .LASF15 + 404 00a9 02 .byte 0x2 + 405 00aa 9002 .2byte 0x290 + 406 00ac B0000000 .4byte 0xb0 + 407 00b0 05 .uleb128 0x5 + 408 00b1 83000000 .4byte 0x83 + 409 00b5 06 .uleb128 0x6 + 410 00b6 06000000 .4byte .LASF16 + 411 00ba 01 .byte 0x1 + 412 00bb 48 .byte 0x48 + 413 00bc 00000000 .4byte .LFB0 + 414 00c0 30000000 .4byte .LFE0-.LFB0 + 415 00c4 01 .uleb128 0x1 + 416 00c5 9C .byte 0x9c + 417 00c6 D9000000 .4byte 0xd9 + 418 00ca 07 .uleb128 0x7 + 419 00cb DA010000 .4byte .LASF18 + 420 00cf 01 .byte 0x1 + 421 00d0 48 .byte 0x48 + 422 00d1 6B000000 .4byte 0x6b + 423 00d5 02 .uleb128 0x2 + 424 00d6 91 .byte 0x91 + 425 00d7 77 .sleb128 -9 + 426 00d8 00 .byte 0 + 427 00d9 06 .uleb128 0x6 + 428 00da 17000000 .4byte .LASF17 + 429 00de 01 .byte 0x1 + 430 00df 6F .byte 0x6f + 431 00e0 00000000 .4byte .LFB1 + 432 00e4 50000000 .4byte .LFE1-.LFB1 + 433 00e8 01 .uleb128 0x1 + 434 00e9 9C .byte 0x9c + 435 00ea 0B010000 .4byte 0x10b + 436 00ee 07 .uleb128 0x7 + 437 00ef 21000000 .4byte .LASF19 + 438 00f3 01 .byte 0x1 + 439 00f4 6F .byte 0x6f + 440 00f5 6B000000 .4byte 0x6b + 441 00f9 02 .uleb128 0x2 + 442 00fa 91 .byte 0x91 + 443 00fb 6F .sleb128 -17 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 13 + + + 444 00fc 08 .uleb128 0x8 + 445 00fd AB000000 .4byte .LASF24 + 446 0101 01 .byte 0x1 + 447 0102 71 .byte 0x71 + 448 0103 6B000000 .4byte 0x6b + 449 0107 02 .uleb128 0x2 + 450 0108 91 .byte 0x91 + 451 0109 77 .sleb128 -9 + 452 010a 00 .byte 0 + 453 010b 09 .uleb128 0x9 + 454 010c E9000000 .4byte .LASF20 + 455 0110 01 .byte 0x1 + 456 0111 88 .byte 0x88 + 457 0112 6B000000 .4byte 0x6b + 458 0116 00000000 .4byte .LFB2 + 459 011a 1C000000 .4byte .LFE2-.LFB2 + 460 011e 01 .uleb128 0x1 + 461 011f 9C .byte 0x9c + 462 0120 09 .uleb128 0x9 + 463 0121 80010000 .4byte .LASF21 + 464 0125 01 .byte 0x1 + 465 0126 A4 .byte 0xa4 + 466 0127 6B000000 .4byte 0x6b + 467 012b 00000000 .4byte .LFB3 + 468 012f 1C000000 .4byte .LFE3-.LFB3 + 469 0133 01 .uleb128 0x1 + 470 0134 9C .byte 0x9c + 471 0135 06 .uleb128 0x6 + 472 0136 27000000 .4byte .LASF22 + 473 013a 01 .byte 0x1 + 474 013b CF .byte 0xcf + 475 013c 00000000 .4byte .LFB4 + 476 0140 44000000 .4byte .LFE4-.LFB4 + 477 0144 01 .uleb128 0x1 + 478 0145 9C .byte 0x9c + 479 0146 75010000 .4byte 0x175 + 480 014a 07 .uleb128 0x7 + 481 014b 9E010000 .4byte .LASF23 + 482 014f 01 .byte 0x1 + 483 0150 CF .byte 0xcf + 484 0151 77000000 .4byte 0x77 + 485 0155 02 .uleb128 0x2 + 486 0156 91 .byte 0x91 + 487 0157 6E .sleb128 -18 + 488 0158 07 .uleb128 0x7 + 489 0159 DA010000 .4byte .LASF18 + 490 015d 01 .byte 0x1 + 491 015e CF .byte 0xcf + 492 015f 77000000 .4byte 0x77 + 493 0163 02 .uleb128 0x2 + 494 0164 91 .byte 0x91 + 495 0165 6C .sleb128 -20 + 496 0166 08 .uleb128 0x8 + 497 0167 AE010000 .4byte .LASF25 + 498 016b 01 .byte 0x1 + 499 016c D1 .byte 0xd1 + 500 016d 83000000 .4byte 0x83 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 14 + + + 501 0171 02 .uleb128 0x2 + 502 0172 91 .byte 0x91 + 503 0173 74 .sleb128 -12 + 504 0174 00 .byte 0 + 505 0175 0A .uleb128 0xa + 506 0176 B1000000 .4byte .LASF26 + 507 017a 01 .byte 0x1 + 508 017b EC .byte 0xec + 509 017c 6B000000 .4byte 0x6b + 510 0180 00000000 .4byte .LFB5 + 511 0184 30000000 .4byte .LFE5-.LFB5 + 512 0188 01 .uleb128 0x1 + 513 0189 9C .byte 0x9c + 514 018a 08 .uleb128 0x8 + 515 018b ED010000 .4byte .LASF27 + 516 018f 01 .byte 0x1 + 517 0190 EE .byte 0xee + 518 0191 6B000000 .4byte 0x6b + 519 0195 02 .uleb128 0x2 + 520 0196 91 .byte 0x91 + 521 0197 77 .sleb128 -9 + 522 0198 00 .byte 0 + 523 0199 00 .byte 0 + 524 .section .debug_abbrev,"",%progbits + 525 .Ldebug_abbrev0: + 526 0000 01 .uleb128 0x1 + 527 0001 11 .uleb128 0x11 + 528 0002 01 .byte 0x1 + 529 0003 25 .uleb128 0x25 + 530 0004 0E .uleb128 0xe + 531 0005 13 .uleb128 0x13 + 532 0006 0B .uleb128 0xb + 533 0007 03 .uleb128 0x3 + 534 0008 0E .uleb128 0xe + 535 0009 1B .uleb128 0x1b + 536 000a 0E .uleb128 0xe + 537 000b 55 .uleb128 0x55 + 538 000c 17 .uleb128 0x17 + 539 000d 11 .uleb128 0x11 + 540 000e 01 .uleb128 0x1 + 541 000f 10 .uleb128 0x10 + 542 0010 17 .uleb128 0x17 + 543 0011 00 .byte 0 + 544 0012 00 .byte 0 + 545 0013 02 .uleb128 0x2 + 546 0014 24 .uleb128 0x24 + 547 0015 00 .byte 0 + 548 0016 0B .uleb128 0xb + 549 0017 0B .uleb128 0xb + 550 0018 3E .uleb128 0x3e + 551 0019 0B .uleb128 0xb + 552 001a 03 .uleb128 0x3 + 553 001b 0E .uleb128 0xe + 554 001c 00 .byte 0 + 555 001d 00 .byte 0 + 556 001e 03 .uleb128 0x3 + 557 001f 24 .uleb128 0x24 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 15 + + + 558 0020 00 .byte 0 + 559 0021 0B .uleb128 0xb + 560 0022 0B .uleb128 0xb + 561 0023 3E .uleb128 0x3e + 562 0024 0B .uleb128 0xb + 563 0025 03 .uleb128 0x3 + 564 0026 08 .uleb128 0x8 + 565 0027 00 .byte 0 + 566 0028 00 .byte 0 + 567 0029 04 .uleb128 0x4 + 568 002a 16 .uleb128 0x16 + 569 002b 00 .byte 0 + 570 002c 03 .uleb128 0x3 + 571 002d 0E .uleb128 0xe + 572 002e 3A .uleb128 0x3a + 573 002f 0B .uleb128 0xb + 574 0030 3B .uleb128 0x3b + 575 0031 05 .uleb128 0x5 + 576 0032 49 .uleb128 0x49 + 577 0033 13 .uleb128 0x13 + 578 0034 00 .byte 0 + 579 0035 00 .byte 0 + 580 0036 05 .uleb128 0x5 + 581 0037 35 .uleb128 0x35 + 582 0038 00 .byte 0 + 583 0039 49 .uleb128 0x49 + 584 003a 13 .uleb128 0x13 + 585 003b 00 .byte 0 + 586 003c 00 .byte 0 + 587 003d 06 .uleb128 0x6 + 588 003e 2E .uleb128 0x2e + 589 003f 01 .byte 0x1 + 590 0040 3F .uleb128 0x3f + 591 0041 19 .uleb128 0x19 + 592 0042 03 .uleb128 0x3 + 593 0043 0E .uleb128 0xe + 594 0044 3A .uleb128 0x3a + 595 0045 0B .uleb128 0xb + 596 0046 3B .uleb128 0x3b + 597 0047 0B .uleb128 0xb + 598 0048 27 .uleb128 0x27 + 599 0049 19 .uleb128 0x19 + 600 004a 11 .uleb128 0x11 + 601 004b 01 .uleb128 0x1 + 602 004c 12 .uleb128 0x12 + 603 004d 06 .uleb128 0x6 + 604 004e 40 .uleb128 0x40 + 605 004f 18 .uleb128 0x18 + 606 0050 9742 .uleb128 0x2117 + 607 0052 19 .uleb128 0x19 + 608 0053 01 .uleb128 0x1 + 609 0054 13 .uleb128 0x13 + 610 0055 00 .byte 0 + 611 0056 00 .byte 0 + 612 0057 07 .uleb128 0x7 + 613 0058 05 .uleb128 0x5 + 614 0059 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 16 + + + 615 005a 03 .uleb128 0x3 + 616 005b 0E .uleb128 0xe + 617 005c 3A .uleb128 0x3a + 618 005d 0B .uleb128 0xb + 619 005e 3B .uleb128 0x3b + 620 005f 0B .uleb128 0xb + 621 0060 49 .uleb128 0x49 + 622 0061 13 .uleb128 0x13 + 623 0062 02 .uleb128 0x2 + 624 0063 18 .uleb128 0x18 + 625 0064 00 .byte 0 + 626 0065 00 .byte 0 + 627 0066 08 .uleb128 0x8 + 628 0067 34 .uleb128 0x34 + 629 0068 00 .byte 0 + 630 0069 03 .uleb128 0x3 + 631 006a 0E .uleb128 0xe + 632 006b 3A .uleb128 0x3a + 633 006c 0B .uleb128 0xb + 634 006d 3B .uleb128 0x3b + 635 006e 0B .uleb128 0xb + 636 006f 49 .uleb128 0x49 + 637 0070 13 .uleb128 0x13 + 638 0071 02 .uleb128 0x2 + 639 0072 18 .uleb128 0x18 + 640 0073 00 .byte 0 + 641 0074 00 .byte 0 + 642 0075 09 .uleb128 0x9 + 643 0076 2E .uleb128 0x2e + 644 0077 00 .byte 0 + 645 0078 3F .uleb128 0x3f + 646 0079 19 .uleb128 0x19 + 647 007a 03 .uleb128 0x3 + 648 007b 0E .uleb128 0xe + 649 007c 3A .uleb128 0x3a + 650 007d 0B .uleb128 0xb + 651 007e 3B .uleb128 0x3b + 652 007f 0B .uleb128 0xb + 653 0080 27 .uleb128 0x27 + 654 0081 19 .uleb128 0x19 + 655 0082 49 .uleb128 0x49 + 656 0083 13 .uleb128 0x13 + 657 0084 11 .uleb128 0x11 + 658 0085 01 .uleb128 0x1 + 659 0086 12 .uleb128 0x12 + 660 0087 06 .uleb128 0x6 + 661 0088 40 .uleb128 0x40 + 662 0089 18 .uleb128 0x18 + 663 008a 9742 .uleb128 0x2117 + 664 008c 19 .uleb128 0x19 + 665 008d 00 .byte 0 + 666 008e 00 .byte 0 + 667 008f 0A .uleb128 0xa + 668 0090 2E .uleb128 0x2e + 669 0091 01 .byte 0x1 + 670 0092 3F .uleb128 0x3f + 671 0093 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 17 + + + 672 0094 03 .uleb128 0x3 + 673 0095 0E .uleb128 0xe + 674 0096 3A .uleb128 0x3a + 675 0097 0B .uleb128 0xb + 676 0098 3B .uleb128 0x3b + 677 0099 0B .uleb128 0xb + 678 009a 27 .uleb128 0x27 + 679 009b 19 .uleb128 0x19 + 680 009c 49 .uleb128 0x49 + 681 009d 13 .uleb128 0x13 + 682 009e 11 .uleb128 0x11 + 683 009f 01 .uleb128 0x1 + 684 00a0 12 .uleb128 0x12 + 685 00a1 06 .uleb128 0x6 + 686 00a2 40 .uleb128 0x40 + 687 00a3 18 .uleb128 0x18 + 688 00a4 9742 .uleb128 0x2117 + 689 00a6 19 .uleb128 0x19 + 690 00a7 00 .byte 0 + 691 00a8 00 .byte 0 + 692 00a9 00 .byte 0 + 693 .section .debug_aranges,"",%progbits + 694 0000 44000000 .4byte 0x44 + 695 0004 0200 .2byte 0x2 + 696 0006 00000000 .4byte .Ldebug_info0 + 697 000a 04 .byte 0x4 + 698 000b 00 .byte 0 + 699 000c 0000 .2byte 0 + 700 000e 0000 .2byte 0 + 701 0010 00000000 .4byte .LFB0 + 702 0014 30000000 .4byte .LFE0-.LFB0 + 703 0018 00000000 .4byte .LFB1 + 704 001c 50000000 .4byte .LFE1-.LFB1 + 705 0020 00000000 .4byte .LFB2 + 706 0024 1C000000 .4byte .LFE2-.LFB2 + 707 0028 00000000 .4byte .LFB3 + 708 002c 1C000000 .4byte .LFE3-.LFB3 + 709 0030 00000000 .4byte .LFB4 + 710 0034 44000000 .4byte .LFE4-.LFB4 + 711 0038 00000000 .4byte .LFB5 + 712 003c 30000000 .4byte .LFE5-.LFB5 + 713 0040 00000000 .4byte 0 + 714 0044 00000000 .4byte 0 + 715 .section .debug_ranges,"",%progbits + 716 .Ldebug_ranges0: + 717 0000 00000000 .4byte .LFB0 + 718 0004 30000000 .4byte .LFE0 + 719 0008 00000000 .4byte .LFB1 + 720 000c 50000000 .4byte .LFE1 + 721 0010 00000000 .4byte .LFB2 + 722 0014 1C000000 .4byte .LFE2 + 723 0018 00000000 .4byte .LFB3 + 724 001c 1C000000 .4byte .LFE3 + 725 0020 00000000 .4byte .LFB4 + 726 0024 44000000 .4byte .LFE4 + 727 0028 00000000 .4byte .LFB5 + 728 002c 30000000 .4byte .LFE5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 18 + + + 729 0030 00000000 .4byte 0 + 730 0034 00000000 .4byte 0 + 731 .section .debug_line,"",%progbits + 732 .Ldebug_line0: + 733 0000 B7000000 .section .debug_str,"MS",%progbits,1 + 733 02004000 + 733 00000201 + 733 FB0E0D00 + 733 01010101 + 734 .LASF15: + 735 0000 72656733 .ascii "reg32\000" + 735 3200 + 736 .LASF16: + 737 0006 4C45445F .ascii "LED_SetDriveMode\000" + 737 53657444 + 737 72697665 + 737 4D6F6465 + 737 00 + 738 .LASF17: + 739 0017 4C45445F .ascii "LED_Write\000" + 739 57726974 + 739 6500 + 740 .LASF19: + 741 0021 76616C75 .ascii "value\000" + 741 6500 + 742 .LASF22: + 743 0027 4C45445F .ascii "LED_SetInterruptMode\000" + 743 53657449 + 743 6E746572 + 743 72757074 + 743 4D6F6465 + 744 .LASF30: + 745 003c 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 745 73657273 + 745 5C6A6167 + 745 756D6965 + 745 6C5C446F + 746 006a 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 746 50536F43 + 746 2D313031 + 746 5C547261 + 746 696E696E + 747 .LASF12: + 748 0097 666C6F61 .ascii "float\000" + 748 7400 + 749 .LASF1: + 750 009d 756E7369 .ascii "unsigned char\000" + 750 676E6564 + 750 20636861 + 750 7200 + 751 .LASF24: + 752 00ab 64725661 .ascii "drVal\000" + 752 6C00 + 753 .LASF26: + 754 00b1 4C45445F .ascii "LED_ClearInterrupt\000" + 754 436C6561 + 754 72496E74 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 19 + + + 754 65727275 + 754 707400 + 755 .LASF5: + 756 00c4 6C6F6E67 .ascii "long unsigned int\000" + 756 20756E73 + 756 69676E65 + 756 6420696E + 756 7400 + 757 .LASF3: + 758 00d6 73686F72 .ascii "short unsigned int\000" + 758 7420756E + 758 7369676E + 758 65642069 + 758 6E7400 + 759 .LASF20: + 760 00e9 4C45445F .ascii "LED_Read\000" + 760 52656164 + 760 00 + 761 .LASF28: + 762 00f2 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 762 43313120 + 762 352E342E + 762 31203230 + 762 31363036 + 763 0125 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 763 20726576 + 763 6973696F + 763 6E203233 + 763 37373135 + 764 0158 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 764 66756E63 + 764 74696F6E + 764 2D736563 + 764 74696F6E + 765 .LASF21: + 766 0180 4C45445F .ascii "LED_ReadDataReg\000" + 766 52656164 + 766 44617461 + 766 52656700 + 767 .LASF13: + 768 0190 646F7562 .ascii "double\000" + 768 6C6500 + 769 .LASF10: + 770 0197 75696E74 .ascii "uint16\000" + 770 313600 + 771 .LASF23: + 772 019e 706F7369 .ascii "position\000" + 772 74696F6E + 772 00 + 773 .LASF11: + 774 01a7 75696E74 .ascii "uint32\000" + 774 333200 + 775 .LASF25: + 776 01ae 696E7472 .ascii "intrCfg\000" + 776 43666700 + 777 .LASF8: + 778 01b6 756E7369 .ascii "unsigned int\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cczPsvlX.s page 20 + + + 778 676E6564 + 778 20696E74 + 778 00 + 779 .LASF7: + 780 01c3 6C6F6E67 .ascii "long long unsigned int\000" + 780 206C6F6E + 780 6720756E + 780 7369676E + 780 65642069 + 781 .LASF18: + 782 01da 6D6F6465 .ascii "mode\000" + 782 00 + 783 .LASF6: + 784 01df 6C6F6E67 .ascii "long long int\000" + 784 206C6F6E + 784 6720696E + 784 7400 + 785 .LASF27: + 786 01ed 6D61736B .ascii "maskedStatus\000" + 786 65645374 + 786 61747573 + 786 00 + 787 .LASF14: + 788 01fa 63686172 .ascii "char\000" + 788 00 + 789 .LASF2: + 790 01ff 73686F72 .ascii "short int\000" + 790 7420696E + 790 7400 + 791 .LASF9: + 792 0209 75696E74 .ascii "uint8\000" + 792 3800 + 793 .LASF4: + 794 020f 6C6F6E67 .ascii "long int\000" + 794 20696E74 + 794 00 + 795 .LASF0: + 796 0218 7369676E .ascii "signed char\000" + 796 65642063 + 796 68617200 + 797 .LASF29: + 798 0224 47656E65 .ascii "Generated_Source\\PSoC4\\LED.c\000" + 798 72617465 + 798 645F536F + 798 75726365 + 798 5C50536F + 799 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/LED.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/LED.o new file mode 100644 index 0000000000000000000000000000000000000000..9245b15f977193cfa56f3945b62648389f2c344a GIT binary patch literal 4932 zcmbtWTWlOx89p<6w;d<8+s1L~YEleI1-r4+ByH0M)~s{G2}HS+Mg+yPyW{n?yF1Iw zZ0blzShR?URwzj&BH9#q2twjk6OkgNjZ_I9Dv${905laUh>Ji9RKQydGT(RRoZayz z6cE2O^Zoa8{&WA-uKl|W!w{Mbu}O3!A^KKJOJb{pO=7(m77Ld@y(nHX#nR|VGdZ37 z(BNEh-$4H6=-~Xhcu!$u=C$2dcbkg~SJOs3zr6h0<%P>nxBXX7ub;bqY4y97hVvUf zR~Tt7jjo@6!Fcmh{@$Vd8&bde-Ydg{^T^YTPltS%F^-I{?H0(na9O+*M;^w!ka_dc zu(-OLw)i{P!nm*>uZ)f?JUrTS_sBvovRoM*JpHr6P=0A9HGO6DAxN3iJ^6E&2E@%d zT}{|_pUltNGqQ@M(fo#<{75q~&Duw1WG$*ctbYyszktDv%dv|ae*^Z7nL<1w6`h}H zB!{6kjr5C9nr31dQKp&tIi+}FHEr?K4=AM*Z_$=ceIF2uC#sErwwKvVhJL>@-Uq+< zd3ycc*g^hl7@f3c^B!1FgjFY?Y2L7q*a5eTm z0oFYGq)4u%#l=q?BzK_~=F|qM41L`6Hz<8VM`Zp)@iax!-S~_PnFVIOxKf$iNZU1f zO-Zj7bAO4R*PevJJlhC+qoi8;+qC_ZeK*erqUSq|x}lSXHKhMcpTFqd2xGu_cmGgt ztbcv~(X|7{8q{NsiQeA#LxrJLY#PIJmx%T6=zTb`ZwTYFO%Ref;{)rYws+&Y0b?+k zA3p!Vbp|Y{MCjeSZ^#@LBE5Bmn8}Gw+`gf9q!2yPj4Ld13^28za3zsrO(c#ziK9u< z$Z;cSzfkJP|4ZEW5NwJ(|He}PDuMF?L&;;p*yA)D&kmgOiNkKoD>=sx9(D^jEB5c2 z%9ZF*Iu)F1I(}|0JXI31j@awMsC?N>Ba={?x1o9J7st$0M0eUSHdoAKM04>L%{9Y# zuJx@IVK)q8XKQ*|26|5A{w?gyiNj7X_4QtE&4?Hlj?c-LqUTU^>me7(jpRJEW4(3|*qLr;! z*^fY+oozKr0V1+KN(B1U*+I4zxLLO->z3uPTT^ymA95<9?6!(EN3>AI#CFki{VF4+ zjCq3AE6i3p1H)ov`L~Wio%7hS(X(#*PdMenfgQAbA;&ZvDB9TKgP}jg=)m884IdAe zu-H>5?65X*RFAlB&9`P<&%y{=yVM9;nB$V;`>yBT_kRyM?gwnFWso7vPxkk%YVT*L z-m0Drvo{rduX~z-NCY}u)`>NDC+4MQWV4fwNxPF;8YUddf zvCDo+zCB>PeaGR9#14&zQ^ZEV`X-!kb59+YU?^@D^)R(=<-iU|NU+MM4Jo!lU@Ev>E9XS zl@-R|y|O>4F8`I*m`Hc|r=@?s-3#1Q5sHaSmw!h3^KlSTMl%v)(%MnQ zmfhWE?Xy)g`ZS|_%e6se*9nexIs1GM zaDSWVAV-VHQ6R1(jtH@VxISE$)NfYy?Fx4)WKFbBD?Fs|n8J#}n!~gZCCOmL=3{Tl8-5@ zC_JfffrzE?jFROz;;F`U#eQ*ru^$!@?QuV|9nLZHKS)$di~ii@MD7;G$@u`ve2Awj z^T@o&gHmKZi->$<3S~QR=6+)S14QIKK}0^Eh&-PmBF}ju;=fLWzibB!TDF6@t<*!7 z{YCr{B|k<)o~DumBJw?}3Y5mJf}UqTUi6?JXOlW9r%-IlN7BWvAGxoTxTtU35+IcCm;@iHKNj zJXI>%)}#a4i{|1DvA%5zDd=$yMK z>6>T+lvuXyo2c85Hqu6XnDYPV$F;_oXuIQ(HF0f|3izUaWyl9*BI@@O$hY&G@AA6=c?zEF2Ot z_QJ?Bm3KVb<@mmePse~2H!)G%kD9dY$53dVwu^X5?A1;Y+YiA<+gP4(Note This function is available in PSoC 4 only. + 32:Generated_Source\PSoC4/LED_PM.c **** * + 33:Generated_Source\PSoC4/LED_PM.c **** * \return + 34:Generated_Source\PSoC4/LED_PM.c **** * None + 35:Generated_Source\PSoC4/LED_PM.c **** * + 36:Generated_Source\PSoC4/LED_PM.c **** * \sideeffect + 37:Generated_Source\PSoC4/LED_PM.c **** * For SIO pins, this function configures the pin input threshold to CMOS and + 38:Generated_Source\PSoC4/LED_PM.c **** * drive level to Vddio. This is needed for SIO pins when in device + 39:Generated_Source\PSoC4/LED_PM.c **** * deep-sleep/hibernate modes. + 40:Generated_Source\PSoC4/LED_PM.c **** * + 41:Generated_Source\PSoC4/LED_PM.c **** * \funcusage + 42:Generated_Source\PSoC4/LED_PM.c **** * \snippet LED_SUT.c usage_LED_Sleep_Wakeup + 43:Generated_Source\PSoC4/LED_PM.c **** *******************************************************************************/ + 44:Generated_Source\PSoC4/LED_PM.c **** void LED_Sleep(void) + 45:Generated_Source\PSoC4/LED_PM.c **** { + 32 .loc 1 45 0 + 33 .cfi_startproc + 34 @ args = 0, pretend = 0, frame = 0 + 35 @ frame_needed = 1, uses_anonymous_args = 0 + 36 0000 80B5 push {r7, lr} + 37 .cfi_def_cfa_offset 8 + 38 .cfi_offset 7, -8 + 39 .cfi_offset 14, -4 + 40 0002 00AF add r7, sp, #0 + 41 .cfi_def_cfa_register 7 + 46:Generated_Source\PSoC4/LED_PM.c **** #if defined(LED__PC) + 47:Generated_Source\PSoC4/LED_PM.c **** LED_backup.pcState = LED_PC; + 42 .loc 1 47 0 + 43 0004 034B ldr r3, .L2 + 44 0006 1A68 ldr r2, [r3] + 45 0008 034B ldr r3, .L2+4 + 46 000a 1A60 str r2, [r3] + 48:Generated_Source\PSoC4/LED_PM.c **** #else + 49:Generated_Source\PSoC4/LED_PM.c **** #if (CY_PSOC4_4200L) + 50:Generated_Source\PSoC4/LED_PM.c **** /* Save the regulator state and put the PHY into suspend mode */ + 51:Generated_Source\PSoC4/LED_PM.c **** LED_backup.usbState = LED_CR1_REG; + 52:Generated_Source\PSoC4/LED_PM.c **** LED_USB_POWER_REG |= LED_USBIO_ENTER_SLEEP; + 53:Generated_Source\PSoC4/LED_PM.c **** LED_CR1_REG &= LED_USBIO_CR1_OFF; + 54:Generated_Source\PSoC4/LED_PM.c **** #endif + 55:Generated_Source\PSoC4/LED_PM.c **** #endif + 56:Generated_Source\PSoC4/LED_PM.c **** #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(LED__SIO) + 57:Generated_Source\PSoC4/LED_PM.c **** LED_backup.sioState = LED_SIO_REG; + 58:Generated_Source\PSoC4/LED_PM.c **** /* SIO requires unregulated output buffer and single ended input buffer */ + 59:Generated_Source\PSoC4/LED_PM.c **** LED_SIO_REG &= (uint32)(~LED_SIO_LPM_MASK); + 60:Generated_Source\PSoC4/LED_PM.c **** #endif + 61:Generated_Source\PSoC4/LED_PM.c **** } + 47 .loc 1 61 0 + 48 000c C046 nop + 49 000e BD46 mov sp, r7 + 50 @ sp needed + 51 0010 80BD pop {r7, pc} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 3 + + + 52 .L3: + 53 0012 C046 .align 2 + 54 .L2: + 55 0014 08010440 .word 1074004232 + 56 0018 00000000 .word LED_backup + 57 .cfi_endproc + 58 .LFE0: + 59 .size LED_Sleep, .-LED_Sleep + 60 .section .text.LED_Wakeup,"ax",%progbits + 61 .align 2 + 62 .global LED_Wakeup + 63 .code 16 + 64 .thumb_func + 65 .type LED_Wakeup, %function + 66 LED_Wakeup: + 67 .LFB1: + 62:Generated_Source\PSoC4/LED_PM.c **** + 63:Generated_Source\PSoC4/LED_PM.c **** + 64:Generated_Source\PSoC4/LED_PM.c **** /******************************************************************************* + 65:Generated_Source\PSoC4/LED_PM.c **** * Function Name: LED_Wakeup + 66:Generated_Source\PSoC4/LED_PM.c **** ****************************************************************************//** + 67:Generated_Source\PSoC4/LED_PM.c **** * + 68:Generated_Source\PSoC4/LED_PM.c **** * \brief Restores the pin configuration that was saved during Pin_Sleep(). This + 69:Generated_Source\PSoC4/LED_PM.c **** * function applies only to SIO and USBIO pins. It should not be called for + 70:Generated_Source\PSoC4/LED_PM.c **** * GPIO or GPIO_OVT pins. + 71:Generated_Source\PSoC4/LED_PM.c **** * + 72:Generated_Source\PSoC4/LED_PM.c **** * For USBIO pins, the wakeup is only triggered for falling edge interrupts. + 73:Generated_Source\PSoC4/LED_PM.c **** * + 74:Generated_Source\PSoC4/LED_PM.c **** * Note This function is available in PSoC 4 only. + 75:Generated_Source\PSoC4/LED_PM.c **** * + 76:Generated_Source\PSoC4/LED_PM.c **** * \return + 77:Generated_Source\PSoC4/LED_PM.c **** * None + 78:Generated_Source\PSoC4/LED_PM.c **** * + 79:Generated_Source\PSoC4/LED_PM.c **** * \funcusage + 80:Generated_Source\PSoC4/LED_PM.c **** * Refer to LED_Sleep() for an example usage. + 81:Generated_Source\PSoC4/LED_PM.c **** *******************************************************************************/ + 82:Generated_Source\PSoC4/LED_PM.c **** void LED_Wakeup(void) + 83:Generated_Source\PSoC4/LED_PM.c **** { + 68 .loc 1 83 0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 1, uses_anonymous_args = 0 + 72 0000 80B5 push {r7, lr} + 73 .cfi_def_cfa_offset 8 + 74 .cfi_offset 7, -8 + 75 .cfi_offset 14, -4 + 76 0002 00AF add r7, sp, #0 + 77 .cfi_def_cfa_register 7 + 84:Generated_Source\PSoC4/LED_PM.c **** #if defined(LED__PC) + 85:Generated_Source\PSoC4/LED_PM.c **** LED_PC = LED_backup.pcState; + 78 .loc 1 85 0 + 79 0004 034A ldr r2, .L5 + 80 0006 044B ldr r3, .L5+4 + 81 0008 1B68 ldr r3, [r3] + 82 000a 1360 str r3, [r2] + 86:Generated_Source\PSoC4/LED_PM.c **** #else + 87:Generated_Source\PSoC4/LED_PM.c **** #if (CY_PSOC4_4200L) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 4 + + + 88:Generated_Source\PSoC4/LED_PM.c **** /* Restore the regulator state and come out of suspend mode */ + 89:Generated_Source\PSoC4/LED_PM.c **** LED_USB_POWER_REG &= LED_USBIO_EXIT_SLEEP_PH1; + 90:Generated_Source\PSoC4/LED_PM.c **** LED_CR1_REG = LED_backup.usbState; + 91:Generated_Source\PSoC4/LED_PM.c **** LED_USB_POWER_REG &= LED_USBIO_EXIT_SLEEP_PH2; + 92:Generated_Source\PSoC4/LED_PM.c **** #endif + 93:Generated_Source\PSoC4/LED_PM.c **** #endif + 94:Generated_Source\PSoC4/LED_PM.c **** #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(LED__SIO) + 95:Generated_Source\PSoC4/LED_PM.c **** LED_SIO_REG = LED_backup.sioState; + 96:Generated_Source\PSoC4/LED_PM.c **** #endif + 97:Generated_Source\PSoC4/LED_PM.c **** } + 83 .loc 1 97 0 + 84 000c C046 nop + 85 000e BD46 mov sp, r7 + 86 @ sp needed + 87 0010 80BD pop {r7, pc} + 88 .L6: + 89 0012 C046 .align 2 + 90 .L5: + 91 0014 08010440 .word 1074004232 + 92 0018 00000000 .word LED_backup + 93 .cfi_endproc + 94 .LFE1: + 95 .size LED_Wakeup, .-LED_Wakeup + 96 .text + 97 .Letext0: + 98 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 99 .file 3 "Generated_Source\\PSoC4\\LED.h" + 100 .section .debug_info,"",%progbits + 101 .Ldebug_info0: + 102 0000 05010000 .4byte 0x105 + 103 0004 0400 .2byte 0x4 + 104 0006 00000000 .4byte .Ldebug_abbrev0 + 105 000a 04 .byte 0x4 + 106 000b 01 .uleb128 0x1 + 107 000c C0000000 .4byte .LASF20 + 108 0010 0C .byte 0xc + 109 0011 5F010000 .4byte .LASF21 + 110 0015 2C000000 .4byte .LASF22 + 111 0019 00000000 .4byte .Ldebug_ranges0+0 + 112 001d 00000000 .4byte 0 + 113 0021 00000000 .4byte .Ldebug_line0 + 114 0025 02 .uleb128 0x2 + 115 0026 01 .byte 0x1 + 116 0027 06 .byte 0x6 + 117 0028 EC010000 .4byte .LASF0 + 118 002c 02 .uleb128 0x2 + 119 002d 01 .byte 0x1 + 120 002e 08 .byte 0x8 + 121 002f 8D000000 .4byte .LASF1 + 122 0033 02 .uleb128 0x2 + 123 0034 02 .byte 0x2 + 124 0035 05 .byte 0x5 + 125 0036 D1010000 .4byte .LASF2 + 126 003a 02 .uleb128 0x2 + 127 003b 02 .byte 0x2 + 128 003c 07 .byte 0x7 + 129 003d AD000000 .4byte .LASF3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 5 + + + 130 0041 02 .uleb128 0x2 + 131 0042 04 .byte 0x4 + 132 0043 05 .byte 0x5 + 133 0044 E3010000 .4byte .LASF4 + 134 0048 02 .uleb128 0x2 + 135 0049 04 .byte 0x4 + 136 004a 07 .byte 0x7 + 137 004b 9B000000 .4byte .LASF5 + 138 004f 02 .uleb128 0x2 + 139 0050 08 .byte 0x8 + 140 0051 05 .byte 0x5 + 141 0052 BE010000 .4byte .LASF6 + 142 0056 02 .uleb128 0x2 + 143 0057 08 .byte 0x8 + 144 0058 07 .byte 0x7 + 145 0059 93010000 .4byte .LASF7 + 146 005d 03 .uleb128 0x3 + 147 005e 04 .byte 0x4 + 148 005f 05 .byte 0x5 + 149 0060 696E7400 .ascii "int\000" + 150 0064 02 .uleb128 0x2 + 151 0065 04 .byte 0x4 + 152 0066 07 .byte 0x7 + 153 0067 86010000 .4byte .LASF8 + 154 006b 04 .uleb128 0x4 + 155 006c 7F010000 .4byte .LASF12 + 156 0070 02 .byte 0x2 + 157 0071 E601 .2byte 0x1e6 + 158 0073 48000000 .4byte 0x48 + 159 0077 02 .uleb128 0x2 + 160 0078 04 .byte 0x4 + 161 0079 04 .byte 0x4 + 162 007a 87000000 .4byte .LASF9 + 163 007e 02 .uleb128 0x2 + 164 007f 08 .byte 0x8 + 165 0080 04 .byte 0x4 + 166 0081 4E010000 .4byte .LASF10 + 167 0085 02 .uleb128 0x2 + 168 0086 01 .byte 0x1 + 169 0087 08 .byte 0x8 + 170 0088 CC010000 .4byte .LASF11 + 171 008c 04 .uleb128 0x4 + 172 008d 00000000 .4byte .LASF13 + 173 0091 02 .byte 0x2 + 174 0092 9002 .2byte 0x290 + 175 0094 98000000 .4byte 0x98 + 176 0098 05 .uleb128 0x5 + 177 0099 6B000000 .4byte 0x6b + 178 009d 06 .uleb128 0x6 + 179 009e 0C .byte 0xc + 180 009f 03 .byte 0x3 + 181 00a0 21 .byte 0x21 + 182 00a1 CA000000 .4byte 0xca + 183 00a5 07 .uleb128 0x7 + 184 00a6 DB010000 .4byte .LASF14 + 185 00aa 03 .byte 0x3 + 186 00ab 23 .byte 0x23 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 6 + + + 187 00ac 6B000000 .4byte 0x6b + 188 00b0 00 .byte 0 + 189 00b1 07 .uleb128 0x7 + 190 00b2 B5010000 .4byte .LASF15 + 191 00b6 03 .byte 0x3 + 192 00b7 24 .byte 0x24 + 193 00b8 6B000000 .4byte 0x6b + 194 00bc 04 .byte 0x4 + 195 00bd 07 .uleb128 0x7 + 196 00be 06000000 .4byte .LASF16 + 197 00c2 03 .byte 0x3 + 198 00c3 25 .byte 0x25 + 199 00c4 6B000000 .4byte 0x6b + 200 00c8 08 .byte 0x8 + 201 00c9 00 .byte 0 + 202 00ca 08 .uleb128 0x8 + 203 00cb 1A000000 .4byte .LASF17 + 204 00cf 03 .byte 0x3 + 205 00d0 26 .byte 0x26 + 206 00d1 9D000000 .4byte 0x9d + 207 00d5 09 .uleb128 0x9 + 208 00d6 55010000 .4byte .LASF18 + 209 00da 01 .byte 0x1 + 210 00db 2C .byte 0x2c + 211 00dc 00000000 .4byte .LFB0 + 212 00e0 1C000000 .4byte .LFE0-.LFB0 + 213 00e4 01 .uleb128 0x1 + 214 00e5 9C .byte 0x9c + 215 00e6 09 .uleb128 0x9 + 216 00e7 0F000000 .4byte .LASF19 + 217 00eb 01 .byte 0x1 + 218 00ec 52 .byte 0x52 + 219 00ed 00000000 .4byte .LFB1 + 220 00f1 1C000000 .4byte .LFE1-.LFB1 + 221 00f5 01 .uleb128 0x1 + 222 00f6 9C .byte 0x9c + 223 00f7 0A .uleb128 0xa + 224 00f8 AA010000 .4byte .LASF23 + 225 00fc 01 .byte 0x1 + 226 00fd 14 .byte 0x14 + 227 00fe CA000000 .4byte 0xca + 228 0102 05 .uleb128 0x5 + 229 0103 03 .byte 0x3 + 230 0104 00000000 .4byte LED_backup + 231 0108 00 .byte 0 + 232 .section .debug_abbrev,"",%progbits + 233 .Ldebug_abbrev0: + 234 0000 01 .uleb128 0x1 + 235 0001 11 .uleb128 0x11 + 236 0002 01 .byte 0x1 + 237 0003 25 .uleb128 0x25 + 238 0004 0E .uleb128 0xe + 239 0005 13 .uleb128 0x13 + 240 0006 0B .uleb128 0xb + 241 0007 03 .uleb128 0x3 + 242 0008 0E .uleb128 0xe + 243 0009 1B .uleb128 0x1b + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 7 + + + 244 000a 0E .uleb128 0xe + 245 000b 55 .uleb128 0x55 + 246 000c 17 .uleb128 0x17 + 247 000d 11 .uleb128 0x11 + 248 000e 01 .uleb128 0x1 + 249 000f 10 .uleb128 0x10 + 250 0010 17 .uleb128 0x17 + 251 0011 00 .byte 0 + 252 0012 00 .byte 0 + 253 0013 02 .uleb128 0x2 + 254 0014 24 .uleb128 0x24 + 255 0015 00 .byte 0 + 256 0016 0B .uleb128 0xb + 257 0017 0B .uleb128 0xb + 258 0018 3E .uleb128 0x3e + 259 0019 0B .uleb128 0xb + 260 001a 03 .uleb128 0x3 + 261 001b 0E .uleb128 0xe + 262 001c 00 .byte 0 + 263 001d 00 .byte 0 + 264 001e 03 .uleb128 0x3 + 265 001f 24 .uleb128 0x24 + 266 0020 00 .byte 0 + 267 0021 0B .uleb128 0xb + 268 0022 0B .uleb128 0xb + 269 0023 3E .uleb128 0x3e + 270 0024 0B .uleb128 0xb + 271 0025 03 .uleb128 0x3 + 272 0026 08 .uleb128 0x8 + 273 0027 00 .byte 0 + 274 0028 00 .byte 0 + 275 0029 04 .uleb128 0x4 + 276 002a 16 .uleb128 0x16 + 277 002b 00 .byte 0 + 278 002c 03 .uleb128 0x3 + 279 002d 0E .uleb128 0xe + 280 002e 3A .uleb128 0x3a + 281 002f 0B .uleb128 0xb + 282 0030 3B .uleb128 0x3b + 283 0031 05 .uleb128 0x5 + 284 0032 49 .uleb128 0x49 + 285 0033 13 .uleb128 0x13 + 286 0034 00 .byte 0 + 287 0035 00 .byte 0 + 288 0036 05 .uleb128 0x5 + 289 0037 35 .uleb128 0x35 + 290 0038 00 .byte 0 + 291 0039 49 .uleb128 0x49 + 292 003a 13 .uleb128 0x13 + 293 003b 00 .byte 0 + 294 003c 00 .byte 0 + 295 003d 06 .uleb128 0x6 + 296 003e 13 .uleb128 0x13 + 297 003f 01 .byte 0x1 + 298 0040 0B .uleb128 0xb + 299 0041 0B .uleb128 0xb + 300 0042 3A .uleb128 0x3a + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 8 + + + 301 0043 0B .uleb128 0xb + 302 0044 3B .uleb128 0x3b + 303 0045 0B .uleb128 0xb + 304 0046 01 .uleb128 0x1 + 305 0047 13 .uleb128 0x13 + 306 0048 00 .byte 0 + 307 0049 00 .byte 0 + 308 004a 07 .uleb128 0x7 + 309 004b 0D .uleb128 0xd + 310 004c 00 .byte 0 + 311 004d 03 .uleb128 0x3 + 312 004e 0E .uleb128 0xe + 313 004f 3A .uleb128 0x3a + 314 0050 0B .uleb128 0xb + 315 0051 3B .uleb128 0x3b + 316 0052 0B .uleb128 0xb + 317 0053 49 .uleb128 0x49 + 318 0054 13 .uleb128 0x13 + 319 0055 38 .uleb128 0x38 + 320 0056 0B .uleb128 0xb + 321 0057 00 .byte 0 + 322 0058 00 .byte 0 + 323 0059 08 .uleb128 0x8 + 324 005a 16 .uleb128 0x16 + 325 005b 00 .byte 0 + 326 005c 03 .uleb128 0x3 + 327 005d 0E .uleb128 0xe + 328 005e 3A .uleb128 0x3a + 329 005f 0B .uleb128 0xb + 330 0060 3B .uleb128 0x3b + 331 0061 0B .uleb128 0xb + 332 0062 49 .uleb128 0x49 + 333 0063 13 .uleb128 0x13 + 334 0064 00 .byte 0 + 335 0065 00 .byte 0 + 336 0066 09 .uleb128 0x9 + 337 0067 2E .uleb128 0x2e + 338 0068 00 .byte 0 + 339 0069 3F .uleb128 0x3f + 340 006a 19 .uleb128 0x19 + 341 006b 03 .uleb128 0x3 + 342 006c 0E .uleb128 0xe + 343 006d 3A .uleb128 0x3a + 344 006e 0B .uleb128 0xb + 345 006f 3B .uleb128 0x3b + 346 0070 0B .uleb128 0xb + 347 0071 27 .uleb128 0x27 + 348 0072 19 .uleb128 0x19 + 349 0073 11 .uleb128 0x11 + 350 0074 01 .uleb128 0x1 + 351 0075 12 .uleb128 0x12 + 352 0076 06 .uleb128 0x6 + 353 0077 40 .uleb128 0x40 + 354 0078 18 .uleb128 0x18 + 355 0079 9742 .uleb128 0x2117 + 356 007b 19 .uleb128 0x19 + 357 007c 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 9 + + + 358 007d 00 .byte 0 + 359 007e 0A .uleb128 0xa + 360 007f 34 .uleb128 0x34 + 361 0080 00 .byte 0 + 362 0081 03 .uleb128 0x3 + 363 0082 0E .uleb128 0xe + 364 0083 3A .uleb128 0x3a + 365 0084 0B .uleb128 0xb + 366 0085 3B .uleb128 0x3b + 367 0086 0B .uleb128 0xb + 368 0087 49 .uleb128 0x49 + 369 0088 13 .uleb128 0x13 + 370 0089 02 .uleb128 0x2 + 371 008a 18 .uleb128 0x18 + 372 008b 00 .byte 0 + 373 008c 00 .byte 0 + 374 008d 00 .byte 0 + 375 .section .debug_aranges,"",%progbits + 376 0000 24000000 .4byte 0x24 + 377 0004 0200 .2byte 0x2 + 378 0006 00000000 .4byte .Ldebug_info0 + 379 000a 04 .byte 0x4 + 380 000b 00 .byte 0 + 381 000c 0000 .2byte 0 + 382 000e 0000 .2byte 0 + 383 0010 00000000 .4byte .LFB0 + 384 0014 1C000000 .4byte .LFE0-.LFB0 + 385 0018 00000000 .4byte .LFB1 + 386 001c 1C000000 .4byte .LFE1-.LFB1 + 387 0020 00000000 .4byte 0 + 388 0024 00000000 .4byte 0 + 389 .section .debug_ranges,"",%progbits + 390 .Ldebug_ranges0: + 391 0000 00000000 .4byte .LFB0 + 392 0004 1C000000 .4byte .LFE0 + 393 0008 00000000 .4byte .LFB1 + 394 000c 1C000000 .4byte .LFE1 + 395 0010 00000000 .4byte 0 + 396 0014 00000000 .4byte 0 + 397 .section .debug_line,"",%progbits + 398 .Ldebug_line0: + 399 0000 79000000 .section .debug_str,"MS",%progbits,1 + 399 02004C00 + 399 00000201 + 399 FB0E0D00 + 399 01010101 + 400 .LASF13: + 401 0000 72656733 .ascii "reg32\000" + 401 3200 + 402 .LASF16: + 403 0006 75736253 .ascii "usbState\000" + 403 74617465 + 403 00 + 404 .LASF19: + 405 000f 4C45445F .ascii "LED_Wakeup\000" + 405 57616B65 + 405 757000 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 10 + + + 406 .LASF17: + 407 001a 4C45445F .ascii "LED_BACKUP_STRUCT\000" + 407 4241434B + 407 55505F53 + 407 54525543 + 407 5400 + 408 .LASF22: + 409 002c 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 409 73657273 + 409 5C6A6167 + 409 756D6965 + 409 6C5C446F + 410 005a 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 410 50536F43 + 410 2D313031 + 410 5C547261 + 410 696E696E + 411 .LASF9: + 412 0087 666C6F61 .ascii "float\000" + 412 7400 + 413 .LASF1: + 414 008d 756E7369 .ascii "unsigned char\000" + 414 676E6564 + 414 20636861 + 414 7200 + 415 .LASF5: + 416 009b 6C6F6E67 .ascii "long unsigned int\000" + 416 20756E73 + 416 69676E65 + 416 6420696E + 416 7400 + 417 .LASF3: + 418 00ad 73686F72 .ascii "short unsigned int\000" + 418 7420756E + 418 7369676E + 418 65642069 + 418 6E7400 + 419 .LASF20: + 420 00c0 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 420 43313120 + 420 352E342E + 420 31203230 + 420 31363036 + 421 00f3 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 421 20726576 + 421 6973696F + 421 6E203233 + 421 37373135 + 422 0126 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 422 66756E63 + 422 74696F6E + 422 2D736563 + 422 74696F6E + 423 .LASF10: + 424 014e 646F7562 .ascii "double\000" + 424 6C6500 + 425 .LASF18: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccSMXqDJ.s page 11 + + + 426 0155 4C45445F .ascii "LED_Sleep\000" + 426 536C6565 + 426 7000 + 427 .LASF21: + 428 015f 47656E65 .ascii "Generated_Source\\PSoC4\\LED_PM.c\000" + 428 72617465 + 428 645F536F + 428 75726365 + 428 5C50536F + 429 .LASF12: + 430 017f 75696E74 .ascii "uint32\000" + 430 333200 + 431 .LASF8: + 432 0186 756E7369 .ascii "unsigned int\000" + 432 676E6564 + 432 20696E74 + 432 00 + 433 .LASF7: + 434 0193 6C6F6E67 .ascii "long long unsigned int\000" + 434 206C6F6E + 434 6720756E + 434 7369676E + 434 65642069 + 435 .LASF23: + 436 01aa 4C45445F .ascii "LED_backup\000" + 436 6261636B + 436 757000 + 437 .LASF15: + 438 01b5 73696F53 .ascii "sioState\000" + 438 74617465 + 438 00 + 439 .LASF6: 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), +* where
is address of the custom defined interrupt service routine. +* Note: a custom callback function overrides the system defined callback +* functions. +* +* \param number: The number of the callback function addresses to be set. The valid +* range is from 0 to 4. +* +* void(*CallbackFunction(void): A pointer to the function that will be +* associated with the SysTick ISR for the +* specified number. +* +* \return +* Returns the address of the previous callback function. +* The NULL is returned if the specified address in not set. +* +* \sideeffect +* The registered callback functions will be executed in the interrupt. +* +*******************************************************************************/ +cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) +{ + cySysTickCallback retVal; + + retVal = CySysTickCallbacks[number]; + CySysTickCallbacks[number] = function; + return (retVal); +} + + +/******************************************************************************* +* Function Name: CySysTickGetCallback +****************************************************************************//** +* +* The function get the specified callback pointer. +* +* \param number: The number of callback function address to get. The valid +* range is from 0 to 4. +* +* \return +* Returns the address of the specified callback function. +* The NULL is returned if the specified address in not initialized. +* +*******************************************************************************/ +cySysTickCallback CySysTickGetCallback(uint32 number) +{ + return ((cySysTickCallback) CySysTickCallbacks[number]); +} + + +/******************************************************************************* +* Function Name: CySysTickServiceCallbacks +****************************************************************************//** +* +* System Tick timer interrupt routine +* +*******************************************************************************/ +static void CySysTickServiceCallbacks(void) +{ + uint32 i; + + /* Verify that tick timer flag was set */ + if (1u == CySysTickGetCountFlag()) + { + for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + { + if (CySysTickCallbacks[i] != (void *) 0) + { + (void)(CySysTickCallbacks[i])(); + } + } + } +} + + +/******************************************************************************* +* Function Name: CyGetUniqueId +****************************************************************************//** +* +* Returns the 64-bit unique ID of the device. The uniqueness of the number is +* guaranteed for 10 years due to the die lot number having a cycle life of 10 +* years and even after 10 years, the probability of getting two identical +* numbers is very small. +* +* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns +* the 64-bit unique ID of the device by loading them into the integer array +* pointed to by uniqueId. +* +*******************************************************************************/ +void CyGetUniqueId(uint32* uniqueId) +{ +#if(CY_PSOC4) + uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 ); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u); + + uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X ); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u); +#else + uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB )); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u); + + uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC )); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u); +#endif /* (CY_PSOC4) */ +} + + +#if (CY_IP_DMAC_PRESENT) + /******************************************************************************* + * Function Name: CySysSetRamAccessArbPriority + ****************************************************************************//** + * + * Sets RAM access priority between CPU and DMA. The RAM_CTL register is + * configured to set the priority. Please refer to the device TRM for more + * details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetRamAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_RAM_CTL_REG & ~CY_SYS_CPUSS_RAM_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT) & CY_SYS_CPUSS_RAM_CTL_ARB_MASK); + CY_SYS_CPUSS_RAM_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetFlashAccessArbPriority + ****************************************************************************//** + * + * Sets flash access priority between CPU and DMA. The FLASH_CTL register is + * configured to set the priority. Please refer to the device TRM for more + * details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetFlashAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_FLASH_CTL_REG & ~CY_SYS_CPUSS_FLASH_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT) & CY_SYS_CPUSS_FLASH_CTL_ARB_MASK); + CY_SYS_CPUSS_FLASH_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetDmacAccessArbPriority + ****************************************************************************//** + * + * Sets DMAC slave interface access priority between CPU and DMA. The DMAC_CTL + * register is configured to set the priority. Please refer to the device TRM + * for more details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetDmacAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_DMAC_CTL_REG & ~CY_SYS_CPUSS_DMAC_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT) & CY_SYS_CPUSS_DMAC_CTL_ARB_MASK); + CY_SYS_CPUSS_DMAC_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetPeripheralAccessArbPriority + ****************************************************************************//** + * + * Sets slave peripheral interface access priority between CPU and DMA. + * The SL_CTL register is configured to set the priority. Please refer to the + * device TRM for more details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param interfaceNumber: the slave interface number. Please refer to the + * device TRM for more details. + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetPeripheralAccessArbPriority(uint32 interfaceNumber, uint32 source) + { + uint32 regTmp; + + if (interfaceNumber == 0u) + { + regTmp = CY_SYS_CPUSS_SL_CTL0_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL0_REG = regTmp; + } else + #if (CY_IP_SL_NR >= 2) + if (interfaceNumber == 1u) + { + regTmp = CY_SYS_CPUSS_SL_CTL1_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL1_REG = regTmp; + } else + #endif /* (CY_IP_SL_NR >= 1) */ + #if (CY_IP_SL_NR >= 3) + if (interfaceNumber == 2u) + { + regTmp = CY_SYS_CPUSS_SL_CTL2_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL2_REG = regTmp; + } else + #endif /* (CY_IP_SL_NR >= 1) */ + { + /* Halt CPU in debug mode if interface is invalid */ + CYASSERT(0u != 0u); + } + } + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +#if (CY_IP_PASS) + /******************************************************************************* + * Function Name: CySysPrbSetGlobalVrefSource + ****************************************************************************//** + * + * Selects the source of the global voltage reference. + * + * \note The global voltage reference uses one of the available programmable + * voltage reference lines. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * This API affects the voltage values available in + * \ref CySysPrbSetGlobalVrefVoltage(). + * + * This API is applicable for PSoC 4200M, PSoC 4200L and PSoC Analog + * Coprocessor devices only. + * + * \param source: + * CY_SYS_VREF_SOURCE_BG Sets bandgap as the source of the global voltage + * reference. + * CY_SYS_VREF_SOURCE_VDDA Sets VDDA as the source of the global voltage + * reference. + * + *******************************************************************************/ + #ifdef CyDesignWideVoltageReference_PRB_REF + void CySysPrbSetGlobalVrefSource(uint32 source) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_REF, CYFLD_PASS_VREF_SUP_SEL, source); + } + #endif + + /******************************************************************************* + * Function Name: CySysPrbSetBgGain + ****************************************************************************//** + * + * Selects the gain of bandgap reference buffer. Note that this API is effective + * only when the bandgap is set as the source of global voltage reference. + * + * \note This API affects the voltage values available in \ref + * CySysPrbSetGlobalVrefVoltage() API. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * \param gain: + * CY_SYS_VREF_BG_GAINx1 Gain is 1. + * CY_SYS_VREF_BG_GAINx2 Gain is 2. + * + *******************************************************************************/ + void CySysPrbSetBgGain(uint32 gain) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VBGR_BUF_GAIN, gain); + } + + + /******************************************************************************* + * Function Name: CySysPrbSetGlobalVrefVoltage + ****************************************************************************//** + * + * Selects the value of global voltage reference. Set the source of the global + * voltage reference and bandgap buffer gain (if applicable) before calling this + * API. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * \param voltageTap The range is from 1 to 16 that corresponds to: + * Source is bandgap (x1): 0.08 V to 1.20 V in steps of 0.07 V approximately. + * Source is bandgap (x2): 0.16 V to 2.40 V in steps of 0.14 V approximately. + * Source is Vdda: 0.21 V to 3.30 in steps of 0.21 V approximately. The Vdda + * is equal to 3.3 V. Voltage value will change according to value of Vdda. + * + * voltageTap | If bandgap (x1), V| If bandgap (x2), V| If Vdda + * ------------|-------------------|-------------------|------------------- + * 1 | 0.08 | 0.16 | 0.21 + * 2 | 0.15 | 0.30 | 0.41 + * 3 | 0.23 | 0.46 | 0.62 + * 4 | 0.30 | 0.60 | 0.83 + * 5 | 0.38 | 0.76 | 1.03 + * 6 | 0.45 | 0.90 | 1.24 + * 7 | 0.53 | 1.06 | 1.44 + * 8 | 0.60 | 1.20 | 1.65 + * 9 | 0.68 | 1.36 | 1.86 + * 10 | 0.75 | 1.50 | 2.06 + * 11 | 0.83 | 1.66 | 2.27 + * 12 | 0.90 | 1.80 | 2.48 + * 13 | 0.98 | 1.96 | 2.68 + * 14 | 1.05 | 2.10 | 2.89 + * 15 | 1.13 | 2.26 | 3.09 + * 16 | 1.20 | 2.40 | 3.30 + * + *******************************************************************************/ + #ifdef CyDesignWideVoltageReference_PRB_REF + void CySysPrbSetGlobalVrefVoltage(uint32 voltageTap) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_REF, CYFLD_PASS_VREF_SEL, voltageTap); + } + #endif + + + /******************************************************************************* + * Function Name: CySysPrbEnableDeepsleepVddaRef + ****************************************************************************//** + * + * Enables the Vdda reference in deep sleep mode. The Vdda reference is by + * default disabled when entering deep sleep mode. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbEnableDeepsleepVddaRef(void) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_DEEPSLEEP_ON, 1u); + } + + + /******************************************************************************* + * Function Name: CySysPrbDisableDeepsleepVddaRef + ****************************************************************************//** + * + * Disables the Vdda reference in deep sleep mode. The Vdda reference is by + * default disabled when entering deep sleep mode. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbDisableDeepsleepVddaRef(void) + { + CY_CLEAR_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_DEEPSLEEP_ON); + } + + + /******************************************************************************* + * Function Name: CySysPrbEnableVddaRef + ****************************************************************************//** + * + * Enables the Vdda reference. The Vdda reference is by default not enabled. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbEnableVddaRef(void) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VDDA_ENABLE, 1u); + } + + + /******************************************************************************* + * Function Name: CySysPrbDisableVddaRef + ****************************************************************************//** + * + * Disables the Vdda reference. The Vdda reference is by default not enabled. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbDisableVddaRef(void) + { + CY_CLEAR_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VDDA_ENABLE); + } + + + /******************************************************************************* + * Function Name: CySysPrbSetBgBufferTrim + ****************************************************************************//** + * + * Sets the trim for the bandgap reference buffer. + * + * \note Affects all bandgap sourced references. + * + * \param bgTrim The trim value from -32 to 31. Step size is approximately 1 mV. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbSetBgBufferTrim(int32 bgTrim) + { + uint8 tmp = 0u; + + if (bgTrim >= 0) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM, (uint32) bgTrim); + } + else + { + tmp = (uint8)((int32) bgTrim * (int8) (-1)); /* Make positive */ + tmp = (uint8) ~tmp + 1u; /* Two's complement */ + tmp |= (uint8) CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT; + + CY_SET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM, tmp); + } + } + + + /******************************************************************************* + * Function Name: CySysPrbGetBgBufferTrim + ****************************************************************************//** + * + * Returns the current trim of the bandgap reference buffer. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + int32 CySysPrbGetBgBufferTrim(void) + { + uint8 tmp; + int32 returnValue; + + tmp = (uint8) CY_GET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM); + if ((tmp & CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT) != 0u) + { + tmp = ((uint8) ~tmp) + 1u; /* Make positive */ + returnValue = (int32) tmp * (-1); /* Make negative */ + } + else + { + returnValue = (int32) tmp; + } + + return (returnValue); + } + + +#endif /* (CY_IP_PASS) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.h new file mode 100644 index 0000000..c818cc1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.h @@ -0,0 +1,1576 @@ +/***************************************************************************//** +* \file CyLib.h +* \version 5.70 +* +* \brief Provides a system API for the clocking, and interrupts. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include "cytypes.h" +#include "cydevice_trm.h" +#include "CyLFClk.h" + +#include +#include +#include + + +/** +* \addtogroup group_clocking + +PSoC devices supported by PSoC Creator have flexible clocking capabilities. These clocking capabilities are +controlled in PSoC Creator by selections within the Design-Wide Resources settings, connectivity of clocking signals on +the design schematic, and API calls that can modify the clocking at runtime. The clocking API is provided in the CyLib.c +and CyLib.h files. + +This section describes how PSoC Creator maps clocks onto the device and provides guidance on clocking methodologies that +are optimized for the PSoC architecture. + + +\section section_clocking_modes Power Modes +The IMO is available in Active and Sleep modes. It is automatically disabled/enabled for the proper Deep Sleep and +Hibernate mode entry/exit. The IMO is disabled during Deep Sleep and Hibernate modes. + +The EXTCLK is available in Active and Sleep modes. The system will enter/exit Deep Sleep and Hibernate using external +clock. The device will re-enable the IMO if it was enabled before entering Deep Sleep or Hibernate, but it does not wait +for the IMO before starting the CPU. After entering Active mode, the IMO may take an additional 2 us to begin toggling. +The IMO will startup cleanly without glitches, but any dependency should account for this extra startup time. If +desired, firmware may increase wakeup hold-off using \ref CySysPmSetWakeupHoldoff() function to include this 2 us and +ensure the IMO is toggling by the time Active mode is reached. + +The ILO is available in all modes except Hibernate and Stop. + + + +\section section_clocking_connectivity Clock Connectivity +The PSoC architecture includes flexible clock generation logic. Refer to the Technical Reference Manual for a detailed +description of all the clocking sources available in a particular device. The usage of these various clocking sources +can be categorized by how those clocks are connected to elements of a design. + +\section section_clocking_runtime_changing Changing Clocks in Run-time + +\subsection section_clocking_runtime_changing_impact Impact on Components Operation +The components with internal clocks are directly impacted by the change of the system clock frequencies or sources. The +components clock frequencies obtained using design-time dividers. The run-time change of components clock source will +correspondingly change the internal component clock. Refer to the component datasheet for the details. + +\subsection section_clocking_runtime_adjust CyDelay APIs +The CyDelay APIs implement simple software-based delay loops. The loops compensate for system clock frequency. The +\ref CyDelayFreq() function must be called in order to adjust \ref CyDelay(), \ref CyDelayUs() and \ref CyDelayCycles() +functions to the new system clock value. + +\subsection section_clocking_runtime_cache Cache Configuration +If the CPU clock frequency increases during device operation, the number of clock cycles cache will wait before sampling +data coming back from Flash should be adjusted. If the CPU clock frequency decreases, the number of clock cycles can be +also adjusted to improve CPU performance. See “CySysFlashSetWaitCycles()” for PSoC 4 for more information. + +*/ + + +/** +* \addtogroup group_clocking_hfclk High-Frequency Clocking API +* \ingroup group_clocking +* @{ +*/ +void CySysClkImoStart(void); +void CySysClkImoStop(void); +void CySysClkWriteHfclkDirect(uint32 clkSelect); + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + void CySysClkImoEnableWcoLock(void); + void CySysClkImoDisableWcoLock(void); + uint32 CySysClkImoGetWcoLock(void); +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_USB) + void CySysClkImoEnableUsbLock(void); + void CySysClkImoDisableUsbLock(void); + uint32 CySysClkImoGetUsbLock(void); +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#if (CY_IP_SRSSLT) + void CySysClkWriteHfclkDiv(uint32 divider); +#endif /* (CY_IP_SRSSLT) */ + +void CySysClkWriteSysclkDiv(uint32 divider); +void CySysClkWriteImoFreq(uint32 freq); +uint32 CySysClkGetSysclkSource(void); +void CySysEnablePumpClock(uint32 enable); + +/** @} group_clocking_hfclk */ + + +/** +* \addtogroup group_clocking_lfclk Low-Frequency Clocking API +* \ingroup group_clocking +* \detailed For PSoC 4 devices, the CyLFClk (low-frequency clock) APIs are located in separate files +* (CyLFClk.h/CyLFClk.c). See the CyLFClk Component Datasheet available from the System Reference Guides item of the +* PSoC Creator Help menu. +* @{ +*/ +/** @} group_clocking_lfclk */ + + +/** +* \addtogroup group_clocking_eco External Crystal Oscillator (ECO) API +* \ingroup group_clocking +* @{ +*/ +#if (CY_IP_ECO) + cystatus CySysClkEcoStart(uint32 timeoutUs); + void CySysClkEcoStop(void); + uint32 CySysClkEcoReadStatus(void); + + #if (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) + void CySysClkWriteEcoDiv(uint32 divider); + #endif /* (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) */ + + #if (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) + void CySysClkConfigureEcoTrim(uint32 wDTrim, uint32 aTrim, uint32 fTrim, uint32 rTrim, uint32 gTrim); + cystatus CySysClkConfigureEcoDrive(uint32 freq, uint32 cLoad, uint32 esr, uint32 maxAmplitude); + #endif /* (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) */ +#endif /* (CY_IP_ECO) */ +/** @} group_clocking_eco */ + + +/** +* \addtogroup group_clocking_pll Phase-Locked Loop (PLL) API +* \ingroup group_clocking +* @{ +*/ +#if (CY_IP_PLL) + cystatus CySysClkPllStart(uint32 pll, uint32 wait); + void CySysClkPllStop(uint32 pll); + cystatus CySysClkPllSetPQ(uint32 pll, uint32 feedback, uint32 reference, uint32 current); + cystatus CySysClkPllSetFrequency(uint32 pll, uint32 inputFreq, uint32 pllFreq, uint32 divider, uint32 freqTol); + void CySysClkPllSetSource(uint32 pll, uint32 source); + cystatus CySysClkPllSetOutputDivider(uint32 pll, uint32 divider); + void CySysClkPllSetBypassMode(uint32 pll, uint32 bypass); + uint32 CySysClkPllGetUnlockStatus(uint32 pll); + uint32 CySysClkPllGetLockStatus(uint32 pll); +#endif /* (CY_IP_PLL) */ +/** @} group_clocking_pll */ + + +/** +* \addtogroup group_api_lvd_functions Low Voltage Detection API +* @{ +*/ +#if(CY_IP_SRSSV2) + void CySysLvdEnable(uint32 threshold); + void CySysLvdDisable(void); + uint32 CySysLvdGetInterruptSource(void); + void CySysLvdClearInterrupt(void); +#endif /* (CY_IP_SRSSV2) */ +/** @} group_api_lvd_functions */ + + +/** +* \addtogroup group_interrupts Interrupt API +* \brief The APIs in this chapter apply to all architectures except as noted. The Interrupts API is provided in the +* CyLib.c and CyLib.h files. Refer also to the Interrupt component datasheet for more information about interrupts. +* @{ +*/ +cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address); +cyisraddress CyIntGetSysVector(uint8 number); + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address); +cyisraddress CyIntGetVector(uint8 number); + +void CyIntSetPriority(uint8 number, uint8 priority); +uint8 CyIntGetPriority(uint8 number); + +void CyIntEnable(uint8 number); +uint8 CyIntGetState(uint8 number); +void CyIntDisable(uint8 number); + +void CyIntSetPending(uint8 number); +void CyIntClearPending(uint8 number); + +uint32 CyDisableInts(void); +void CyEnableInts(uint32 mask); +/** @} group_interrupts */ + + +/** +* \addtogroup group_api_delay_functions Delay API +* @{ +*/ +/* Do not use these definitions directly in your application */ +extern uint32 cydelayFreqHz; +extern uint32 cydelayFreqKhz; +extern uint8 cydelayFreqMhz; +extern uint32 cydelay32kMs; + +void CyDelay(uint32 milliseconds); +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq); +void CyDelayCycles(uint32 cycles); +/** @} group_api_delay_functions */ + + +/** +* \addtogroup group_api_system_functions System API +* @{ +*/ +void CySoftwareReset(void); +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason); +uint32 CySysGetResetReason(uint32 reason); +void CyGetUniqueId(uint32* uniqueId); + +/* Default interrupt handler */ +CY_ISR_PROTO(IntDefaultHandler); +/** @} group_api_system_functions */ + + +/** +* \addtogroup group_api_systick_functions System Timer (SysTick) API +* @{ +*/ + +typedef void (*cySysTickCallback)(void); + +void CySysTickStart(void); +void CySysTickInit(void); +void CySysTickEnable(void); +void CySysTickStop(void); +void CySysTickEnableInterrupt(void); +void CySysTickDisableInterrupt(void); +void CySysTickSetReload(uint32 value); +uint32 CySysTickGetReload(void); +uint32 CySysTickGetValue(void); +cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function); +cySysTickCallback CySysTickGetCallback(uint32 number); + +#if(CY_SYSTICK_LFCLK_SOURCE) + void CySysTickSetClockSource(uint32 clockSource); + uint32 CySysTickGetClockSource(void); +#endif /* (CY_SYSTICK_LFCLK_SOURCE) */ + +uint32 CySysTickGetCountFlag(void); +void CySysTickClear(void); +extern uint32 CySysTickInitVar; +/** @} group_api_systick_functions */ + + +#if (CY_IP_DMAC_PRESENT) + void CySysSetRamAccessArbPriority(uint32 source); + void CySysSetFlashAccessArbPriority(uint32 source); + void CySysSetDmacAccessArbPriority(uint32 source); + void CySysSetPeripheralAccessArbPriority(uint32 interfaceNumber, uint32 source); +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/** +* \addtogroup group_api_pvb_functions Programmable Voltage Block (PVB) API +* @{ +*/ +#if (CY_IP_PASS) + void CySysPrbSetGlobalVrefSource(uint32 source); + void CySysPrbSetBgGain(uint32 gain); + void CySysPrbSetGlobalVrefVoltage(uint32 voltageTap); + void CySysPrbEnableDeepsleepVddaRef(void); + void CySysPrbDisableDeepsleepVddaRef(void); + void CySysPrbEnableVddaRef(void); + void CySysPrbDisableVddaRef(void); + void CySysPrbSetBgBufferTrim(int32 bgTrim); + int32 CySysPrbGetBgBufferTrim(void); +#endif /* (CY_IP_PASS) */ +/** @} group_api_pvb_functions */ + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* Clock API Constants +*******************************************************************************/ + +/* CySysClkWriteHfclkDirect() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x07u) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (( uint32 ) 0x07u) + + #define CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT (( uint32 ) 16u) + + #if (CY_IP_PLL) + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 3u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT) + #else + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 0u ) + #endif /* (CY_IP_PLL) */ + +#else + #if (CY_IP_PLL && CY_IP_SRSSLT) + #define CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK (( uint32 ) 0x01u ) + #define CY_SYS_CLK_SELECT_HFCLK_SEL_PLL_MASK (( uint32 ) 0x04u ) + #define CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT (( uint32 ) 2u) + + #define CY_SYS_EXCO_PGM_CLK_ENABLE_MASK (( uint32 ) 0x80000000u) + #define CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK (( uint32 ) 0x2u) + #define CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR (( uint8 ) 0x5u) + #endif /* (CY_IP_PLL && CY_IP_SRSSLT) */ + + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 0u ) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x03u) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkWriteHfclkDirect() - parameter definitions */ +#define CY_SYS_CLK_HFCLK_IMO (0u) +#define CY_SYS_CLK_HFCLK_EXTCLK (1u) +#if (CY_IP_ECO) + #define CY_SYS_CLK_HFCLK_ECO (2u) +#endif /* (CY_IP_ECO) */ + +#if (CY_IP_PLL) + #if (CY_IP_SRSSV2) + #define CY_SYS_CLK_HFCLK_PLL0 ((uint32) ((uint32) 2u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT)) + #define CY_SYS_CLK_HFCLK_PLL1 ((uint32) ((uint32) 1u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT)) + #else + #define CY_SYS_CLK_HFCLK_PLL0 (6u) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkWriteSysclkDiv() - parameter definitions */ +#define CY_SYS_CLK_SYSCLK_DIV1 (0u) +#define CY_SYS_CLK_SYSCLK_DIV2 (1u) +#define CY_SYS_CLK_SYSCLK_DIV4 (2u) +#define CY_SYS_CLK_SYSCLK_DIV8 (3u) +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SYSCLK_DIV16 (4u) + #define CY_SYS_CLK_SYSCLK_DIV32 (5u) + #define CY_SYS_CLK_SYSCLK_DIV64 (6u) + #define CY_SYS_CLK_SYSCLK_DIV128 (7u) +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkWriteSysclkDiv() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (19u) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x07u) +#else + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (6u) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x03u) +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkPllSetSource() - implementation definitions */ +#if (CY_IP_PLL) + #if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_PLL_SHIFT(x) (3u + (3u * (x))) + #define CY_SYS_CLK_SELECT_PLL_MASK(x) ((uint32) ((uint32) 0x07u << CY_SYS_CLK_SELECT_PLL_SHIFT((x)))) + #else + #define CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT (1u) + #define CY_SYS_ECO_CLK_SELECT_PLL0_MASK ((uint32) ((uint32) 0x01u << CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT)) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkPllSetSource() - parameter definitions */ +#if (CY_IP_PLL) + #if(CY_IP_SRSSV2) + #define CY_SYS_PLL_SOURCE_IMO (0u) + #define CY_SYS_PLL_SOURCE_EXTCLK (1u) + #define CY_SYS_PLL_SOURCE_ECO (2u) + #define CY_SYS_PLL_SOURCE_DSI0 (4u) + #define CY_SYS_PLL_SOURCE_DSI1 (5u) + #define CY_SYS_PLL_SOURCE_DSI2 (6u) + #define CY_SYS_PLL_SOURCE_DSI3 (7u) + #else + #define CY_SYS_PLL_SOURCE_ECO (0u) + #define CY_SYS_PLL_SOURCE_IMO (1u) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkPllSetBypassMode() - parameter definitions */ +#if(CY_IP_SRSSV2 || CY_IP_SRSSLT) + #if (CY_IP_PLL) + #define CY_SYS_PLL_BYPASS_AUTO (0u) + #define CY_SYS_PLL_BYPASS_PLL_REF (2u) + #define CY_SYS_PLL_BYPASS_PLL_OUT (3u) + #endif /* (CY_IP_PLL) */ +#endif /* (CY_IP_SRSSV2 || CY_IP_SRSSLT)) */ + +/* CySysClkPllSetOutputDivider()/CySysClkPllSetFrequency() - parameters */ +#if(CY_IP_SRSSV2 || CY_IP_SRSSLT) + #if (CY_IP_PLL) + #define CY_SYS_PLL_OUTPUT_DIVPASS (0u) + #define CY_SYS_PLL_OUTPUT_DIV2 (1u) + #define CY_SYS_PLL_OUTPUT_DIV4 (2u) + #define CY_SYS_PLL_OUTPUT_DIV8 (3u) + #endif /* (CY_IP_PLL) */ +#endif /* (CY_IP_SRSSV2 || CY_IP_SRSSLT) */ + +/* CySysPumpClock() */ +#define CY_SYS_CLK_PUMP_DISABLE ((uint32) 0u) +#define CY_SYS_CLK_PUMP_ENABLE ((uint32) 1u) + +#if (CY_IP_PLL) + + /* Set of the PLL registers */ + typedef struct + { + uint32 config; + uint32 status; + uint32 test; + } cy_sys_clk_pll_regs_struct; + + /* Array of the PLL registers */ + typedef struct + { + cy_sys_clk_pll_regs_struct pll[2u]; + } cy_sys_clk_pll_struct; + + + /* CySysClkPllSetPQ() - implementation definitions */ + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT (0u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT (8u) + #define CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT (14u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT (16u) + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT (20u) + + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK ((uint32) ((uint32) 0xFFu << CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK ((uint32) ((uint32) 0x3Fu << CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK ((uint32) ((uint32) 0x03u << CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK ((uint32) ((uint32) 0x07u << CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK ((uint32) ((uint32) 0x03u << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT)) + + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_PLL_REF ((uint32) ((uint32) 2u << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT)) + + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MIN (4u) + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MAX (259u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MIN (2u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MAX (3u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MIN (1u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MAX (64u) + + /* CySysClkPllGetUnlockStatus() - implementation definitions */ + #define CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_SHIFT (4u) + #define CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK (( uint32 )(( uint32 )0x01u << CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_SHIFT)) + + /* CySysClkPllSetFrequency() - implementation definitions */ + #define CY_SYS_CLK_PLL_QMINIP (1u) + #define CY_SYS_CLK_PLL_FPFDMAX (3000u) + + #define CY_SYS_CLK_PLL_QMAXIP (64u) + #define CY_SYS_CLK_PLL_FPFDMIN (1000u) + + #define CY_SYS_CLK_PLL_INVALID (0u) + #define CY_SYS_CLK_PLL_CURRENT_DEFAULT (2u) + + #define CY_SYS_CLK_PLL_INPUT_FREQ_MIN (1000u) + #define CY_SYS_CLK_PLL_INPUT_FREQ_MAX (49152u) + + #define CY_SYS_CLK_PLL_OUTPUT_FREQ_MIN (22500u) + #define CY_SYS_CLK_PLL_OUTPUT_FREQ_MAX (49152u) + + /* CySysClkPllStart() / CySysClkPllStop() - implementation definitions */ + #define CY_SYS_CLK_PLL_STATUS_LOCKED (1u) + #define CY_SYS_CLK_PLL_MIN_STARTUP_US (5u) + #define CY_SYS_CLK_PLL_MAX_STARTUP_US (255u) + + #define CY_SYS_CLK_PLL_CONFIG_ENABLE ((uint32) ((uint32) 1u << 31u)) + #define CY_SYS_CLK_PLL_CONFIG_ISOLATE ((uint32) ((uint32) 1u << 30u)) + +#endif /* (CY_IP_PLL) */ + +/* CySysClkWriteImoFreq() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u) + #define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (3u) + + #define CY_SYS_CLK_IMO_TEMP_FREQ_MHZ (24u) + #define CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2 (0x19u) /* Corresponds to 24 MHz */ + + #define CY_SYS_CLK_IMO_BOUNDARY_FREQ_MHZ (43u) + #define CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2 (0x30u) /* Corresponds to 43 MHz */ + + #define CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES (5u) + #define CY_SYS_CLK_IMO_TRIM_TIMEOUT_US (5u) + #define CY_SYS_CLK_IMO_FREQ_TABLE_SIZE (46u) + #define CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET (3u) + #define CY_SYS_CLK_IMO_FREQ_BITS_MASK (( uint32 )0x3Fu) + #define CY_SYS_CLK_IMO_FREQ_CLEAR (( uint32 )(CY_SYS_CLK_IMO_FREQ_BITS_MASK << 8u)) + #define CY_SYS_CLK_IMO_TRIM4_GAIN_MASK (( uint32 )0x1Fu) + #define CY_SYS_CLK_IMO_TRIM4_WCO_GAIN (( uint32 ) 12u) + #define CY_SYS_CLK_IMO_TRIM4_USB_GAIN (( uint32 ) 8u) + + #if(CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK (( uint32 )0x02u) + #define CY_SFLASH_S1_TESTPGM_REV_MASK (( uint32 )0x3Fu) + #define CY_SFLASH_S1_TESTPGM_OLD_REV (( uint32 )4u) + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#else + #define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (24u) + #define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u) + #define CY_SYS_CLK_IMO_STEP_SIZE_MASK (0x03u) + #define CY_SYS_CLK_IMO_TRIM1_OFFSET_MASK (( uint32 )(0xFFu)) + #define CY_SYS_CLK_IMO_TRIM2_FSOFFSET_MASK (( uint32 )(0x07u)) + #define CY_SYS_CLK_IMO_TRIM3_VALUES_MASK (( uint32 )(0x7Fu)) + #define CY_SYS_CLK_IMO_SELECT_FREQ_MASK (( uint32 )(0x07u)) + #define CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT (( uint32 )(0x02u)) + #define CY_SYS_CLK_IMO_SELECT_24MHZ (( uint32 )(0x00u)) + + #define CY_SYS_CLK_IMO_TRIM_DELAY_US (( uint32 )(50u)) + #define CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES (( uint32 )(50u)) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkImoEnableUsbLock(void) - - implementation definitions */ +#if(CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK (( uint32 )0x02u) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK (( uint32 )0x01u) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_USB (( uint32 )0x00u) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_WCO (( uint32 )0x01u) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +#if(CY_IP_SRSSV2) + /* Conversion between CySysClkWriteImoFreq() parameter and register's value */ + extern const uint8 cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_FREQ_TABLE_SIZE]; +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkImoStart()/CySysClkImoStop() - implementation definitions */ +#define CY_SYS_CLK_IMO_CONFIG_ENABLE (( uint32 )(( uint32 )0x01u << 31u)) + + +#if(CY_IP_SRSSLT) + /* CySysClkWriteHfclkDiv() - parameter definitions */ + #define CY_SYS_CLK_HFCLK_DIV_NODIV (0u) + #define CY_SYS_CLK_HFCLK_DIV_2 (1u) + #define CY_SYS_CLK_HFCLK_DIV_4 (2u) + #define CY_SYS_CLK_HFCLK_DIV_8 (3u) + + /* CySysClkWriteHfclkDiv() - implementation definitions */ + #define CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT (2u) + #define CY_SYS_CLK_SELECT_HFCLK_DIV_MASK (( uint32 )0x03u) +#endif /* (CY_IP_SRSSLT) */ + + +/* Operating source for Pump clock */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT (25u) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK ((uint32) 0x07u) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_IMO (1u) + + #define CY_SYS_CLK_IMO_CONFIG_PUMP_OSC (( uint32 )(( uint32 )0x01u << 22u)) +#else /* CY_IP_SRSSLT */ + #define CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT (4u) + #define CY_SYS_CLK_SELECT_PUMP_SEL_MASK ((uint32) 0x03u) + #define CY_SYS_CLK_SELECT_PUMP_SEL_IMO (1u) +#endif /* (CY_IP_SRSSLT) */ + + +#if (CY_IP_ECO_BLESS) + /* Radio configuration register */ + #define CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE (( uint32 )0x01u) + + /* RFCTRL mode transition control */ + #define CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE (( uint32 )(( uint32 )0x01u << 15u)) + + /* XO is oscillating status */ + #define CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT (( uint32 )0x01u) + + /* BB bump configuration 2 */ + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_MASK (( uint32 )(( uint32 )0x7Fu << 8u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_MASK (( uint32 )(( uint32 )0x7Fu << 0u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_ADD_CAP (( uint32 )(( uint32 )0x01u << 15u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_ADD_CAP (( uint32 )(( uint32 )0x01u << 7u)) + + /* BB bump configuration 1 */ + #define CY_SYS_XTAL_BLERD_BB_XO_TRIM ((uint32) 0x2002u) + + + /** + * \addtogroup group_api_eco + * @{ + */ + #define CY_SYS_CLK_ECO_DIV1 ((uint32) 0x00) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_DIV2 ((uint32) 0x01) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 2 */ + #define CY_SYS_CLK_ECO_DIV4 ((uint32) 0x02) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 4 */ + #define CY_SYS_CLK_ECO_DIV8 ((uint32) 0x03) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 8 */ + /** @} group_api_eco */ + + /* CySysClkWriteEcoDiv() - implementation definitions */ + #define CY_SYS_CLK_XTAL_CLK_DIV_MASK ((uint32) 0x03) +#endif /* (CY_IP_ECO_BLESS) */ + +#if (CY_IP_ECO_BLESSV3) + #define CY_SYS_CLK_ECO_DIV1 ((uint32) 0x00) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_DIV2 ((uint32) 0x01) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 2 */ + #define CY_SYS_CLK_ECO_DIV4 ((uint32) 0x02) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 4 */ + #define CY_SYS_CLK_ECO_DIV8 ((uint32) 0x03) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 8 */ + /** @} group_api_eco */ + + #define CY_SYS_BLESS_HVLDO_STARTUP_DELAY ((uint32) 2u) + #define CY_SYS_BLESS_ISOLATE_DEASSERT_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_ACT_TO_SWITCH_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_HVLDO_DISABLE_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_OSC_STARTUP_DELAY_LF ((uint32) 80u) + #define CY_SYS_BLESS_DSM_OFFSET_TO_WAKEUP_INST_LF ((uint32) 4u) + #define CY_SYS_BLESS_ACT_STARTUP_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_DIG_LDO_STARTUP_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_XTAL_DISABLE_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_DIG_LDO_DISABLE_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_MT_CFG_ACT_LDO ((uint32) 1u) + #define CY_SYS_BLESS_MT_CFG_ENABLE_BLERD ((uint32) 1u) + #define CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON ((uint32) 1u) + + #define CY_SYS_BLESS_MT_STATUS_BLERD_IDLE ((uint32) 4u) + #define CY_SYS_BLESS_MT_STATUS_SWITCH_EN ((uint32) 5u) + #define CY_SYS_BLESS_MT_STATUS_ACTIVE ((uint32) 6u) + #define CY_SYS_BLESS_MT_STATUS_ISOLATE ((uint32) 7u) + + #define CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK ((uint32) 0x20u) + #define CY_SYS_BLESS_BLERD_ACTIVE_INTR_STAT ((uint32) 0x8u) + + #define CY_SYS_BLESS_MT_STATUS_CURR_STATE_MASK ((uint32) 0x1Eu) + + #define CY_SYS_RCB_CTRL_ENABLED ((uint32) 1u) + #define CY_SYS_RCB_CTRL_DIV_ENABLED ((uint32) 1u) + #define CY_SYS_RCB_CTRL_DIV ((uint32) 2u) + #define CY_SYS_RCB_CTRL_LEAD ((uint32) 3u) + #define CY_SYS_RCB_CTRL_LAG ((uint32) 3u) + + #define CY_SYS_RCB_INTR_RCB_DONE ((uint32) 1u) + #define CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY ((uint32) ((uint32)0x1u << 17u)) + #define CY_SYS_RCB_INTR_CLEAR ((uint32) 0xFFFFFFFFu) + #define CY_SYS_RCB_RBUS_RD_CMD ((uint32) ((uint32)0x1u << 31u)) + #define CY_SYS_RCB_RBUS_DIG_CLK_SET ((uint32) 0x1e030400u) + #define CY_SYS_RCB_RBUS_FREQ_NRST_SET ((uint32) 0x1e021800u) + #define CY_SYS_RCB_RBUS_FREQ_XTAL_DIV_SET ((uint32) 0x1e090040u) + #define CY_SYS_RCB_RBUS_FREQ_XTAL_NODIV_SET ((uint32) 0x1e090000u) + #define CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET ((uint32) 0x1e080000u) + #define CY_SYS_RCB_RBUS_IB_VAL ((uint32) ((uint32)0x1u << 9u)) + #define CY_SYS_RCB_RBUS_IB_MASK ((uint32) ((uint32)0x3u << 9u)) + #define CY_SYS_RCB_RBUS_TRIM_VAL ((uint32) (CYDEV_RCB_RBUS_RF_DCXO_CAP_TRIM << 1u)) + #define CY_SYS_RCB_RBUS_TRIM_MASK ((uint32) ((uint32)0xFFu << 1u)) + #define CY_SYS_RCB_RBUS_VAL_MASK ((uint32) 0xFFFFu) + + #define CY_SYS_RCBLL_CPU_ACCESS ((uint32) 0u) + #define CY_SYS_RCBLL_BLELL_ACCESS ((uint32) 1u) + + #define CY_SYS_BLELL_CMD_ENTER_DSM ((uint32) 0x50u) + + #define CY_SYS_BLESS_MT_DELAY_CFG_INIT \ + ((CY_SYS_BLESS_HVLDO_STARTUP_DELAY << CYFLD_BLE_BLESS_HVLDO_STARTUP_DELAY__OFFSET) | \ + (CY_SYS_BLESS_ISOLATE_DEASSERT_DELAY << CYFLD_BLE_BLESS_ISOLATE_DEASSERT_DELAY__OFFSET) | \ + (CY_SYS_BLESS_ACT_TO_SWITCH_DELAY << CYFLD_BLE_BLESS_ACT_TO_SWITCH_DELAY__OFFSET) | \ + (CY_SYS_BLESS_HVLDO_DISABLE_DELAY << CYFLD_BLE_BLESS_HVLDO_DISABLE_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_DELAY_CFG2_INIT \ + ((CY_SYS_BLESS_OSC_STARTUP_DELAY_LF << CYFLD_BLE_BLESS_OSC_STARTUP_DELAY_LF__OFFSET) | \ + (CY_SYS_BLESS_DSM_OFFSET_TO_WAKEUP_INST_LF << CYFLD_BLE_BLESS_DSM_OFFSET_TO_WAKEUP_INSTANT_LF__OFFSET) | \ + (CY_SYS_BLESS_ACT_STARTUP_DELAY << CYFLD_BLE_BLESS_ACT_STARTUP_DELAY__OFFSET) | \ + (CY_SYS_BLESS_DIG_LDO_STARTUP_DELAY << CYFLD_BLE_BLESS_DIG_LDO_STARTUP_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_DELAY_CFG3_INIT \ + ((CY_SYS_BLESS_XTAL_DISABLE_DELAY << CYFLD_BLE_BLESS_XTAL_DISABLE_DELAY__OFFSET) | \ + (CY_SYS_BLESS_DIG_LDO_DISABLE_DELAY << CYFLD_BLE_BLESS_DIG_LDO_DISABLE_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_CFG_CLEAR \ + ~(CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_ENABLE_BLERD) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_DPSLP_ECO_ON) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_ACT_LDO_NOT_BUCK)) + + #define CY_SYS_BLESS_MT_CFG_INIT \ + ((CY_SYS_BLESS_MT_CFG_ENABLE_BLERD << CYFLD_BLE_BLESS_ENABLE_BLERD__OFFSET) | \ + (CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET) | \ + (CY_SYS_BLESS_MT_CFG_ACT_LDO << CYFLD_BLE_BLESS_ACT_LDO_NOT_BUCK__OFFSET)) + + #define CY_SYS_RCB_CTRL_CLEAR \ + ~(CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_ENABLED) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_DIV_ENABLED) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_DIV) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_LEAD) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_LAG)) + + #define CY_SYS_RCB_CTRL_INIT \ + ((CY_SYS_RCB_CTRL_ENABLED << CYFLD_BLE_RCB_ENABLED__OFFSET) | \ + (CY_SYS_RCB_CTRL_DIV_ENABLED << CYFLD_BLE_RCB_DIV_ENABLED__OFFSET) | \ + (CY_SYS_RCB_CTRL_DIV << CYFLD_BLE_RCB_DIV__OFFSET) | \ + (CY_SYS_RCB_CTRL_LEAD << CYFLD_BLE_RCB_LEAD__OFFSET) | \ + (CY_SYS_RCB_CTRL_LAG << CYFLD_BLE_RCB_LAG__OFFSET)) + + /* CySysClkWriteEcoDiv() - implementation definitions */ + #define CY_SYS_CLK_XTAL_CLK_DIV_MASK ((uint32) 0x03) + + #define CY_SYS_BLE_CLK_ECO_FREQ_32MHZ (32) + +#endif /* (CY_IP_ECO_BLESSV3) */ + + +/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() constants */ +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* Fimo = DPLL_MULT * Fwco */ + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE (( uint32 )(( uint32 )0x01u << 30u)) + + /* Rounding integer division: DPLL_MULT = (Fimo_in_khz + Fwco_in_khz / 2) / Fwco_in_khz */ + #define CY_SYS_CLK_WCO_DPLL_MULT_VALUE(frequencyMhz) ((uint32) (((((frequencyMhz) * 1000000u) + 16384u) / 32768u) - 1u)) + #define CY_SYS_CLK_WCO_DPLL_MULT_MASK ((uint32) 0x7FFu) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT (16u) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT (19u) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT (22u) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK (( uint32 )(( uint32 )0xFFu << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT)) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN (( uint32 )(( uint32 ) 4u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN (( uint32 )(( uint32 ) 2u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT)) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX ((uint32) 0xFFu) + #define CY_SYS_CLK_WCO_IMO_TIMEOUT_MS ((uint32) 20u) + + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT (26u) + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE (23u) + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET (26u) + +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +/******************************************************************************* +* System API Constants +*******************************************************************************/ + +/* CySysGetResetReason() */ +#define CY_SYS_RESET_WDT_SHIFT (0u) +#define CY_SYS_RESET_PROTFAULT_SHIFT (3u) +#define CY_SYS_RESET_SW_SHIFT (4u) + +#define CY_SYS_RESET_WDT ((uint32)1u << CY_SYS_RESET_WDT_SHIFT ) +#define CY_SYS_RESET_PROTFAULT ((uint32)1u << CY_SYS_RESET_PROTFAULT_SHIFT) +#define CY_SYS_RESET_SW ((uint32)1u << CY_SYS_RESET_SW_SHIFT ) + + +/* CySoftwareReset() - implementation definitions */ + +/* Vector Key */ +#define CY_SYS_AIRCR_VECTKEY_SHIFT (16u) +#define CY_SYS_AIRCR_VECTKEY ((uint32)((uint32)0x05FAu << CY_SYS_AIRCR_VECTKEY_SHIFT)) +#define CY_SYS_AIRCR_VECTKEY_MASK ((uint32)((uint32)0xFFFFu << CY_SYS_AIRCR_VECTKEY_SHIFT)) + +/* System Reset Request */ +#define CY_SYS_AIRCR_SYSRESETREQ_SHIFT (2u) +#define CY_SYS_AIRCR_SYSRESETREQ ((uint32)((uint32)1u << CY_SYS_AIRCR_SYSRESETREQ_SHIFT)) + + +#if defined(__ARMCC_VERSION) + + #define CyGlobalIntEnable do \ + { \ + __enable_irq(); \ + } while ( 0 ) + + #define CyGlobalIntDisable do \ + { \ + __disable_irq(); \ + } while ( 0 ) + +#elif defined(__GNUC__) || defined (__ICCARM__) + + #define CyGlobalIntEnable do \ + { \ + __asm("CPSIE i"); \ + } while ( 0 ) + + #define CyGlobalIntDisable do \ + { \ + __asm("CPSID i"); \ + } while ( 0 ) + +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + +/* System tick timer */ +#define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u)) +#define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u)) +#define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT (0x02u) +#define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT (16u) +#define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u)) +#define CY_SYS_SYST_CSR_CLK_SRC_LFCLK (0u) +#define CY_SYS_SYST_RVR_CNT_MASK (0x00FFFFFFu) +#define CY_SYS_SYST_CVR_CNT_MASK (0x00FFFFFFu) +#define CY_SYS_SYST_NUM_OF_CALLBACKS (5u) + + +/******************************************************************************* +* Macro Name: CyAssert +******************************************************************************** +* Summary: +* Macro that evaluates the expression and, if it is false (evaluates to 0), +* the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* If NDEBUG is defined, then no code is generated for this macro. +* NDEBUG is defined by default for a Release build setting and not defined for +* a Debug build setting. +* +* Parameters: +* expr: Logical expression. Asserts if false. +* +* Return: +* None +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) do \ + { \ + if(0u == (uint32)(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } while ( 0u ) +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/******************************************************************************* +* Interrupt API Constants +*******************************************************************************/ +#define CY_NUM_INTERRUPTS (CY_IP_INT_NR) + +#define CY_MIN_PRIORITY (3u) + +#define CY_INT_IRQ_BASE (16u) +#define CY_INT_CLEAR_DISABLE_ALL (0xFFFFFFFFu) +#define CY_INT_ENABLE_RANGE_MASK (0x1Fu) + +/* Register n contains priorities for interrupts N=4n .. 4n+3 */ +#define CY_INT_PRIORITY_SHIFT(number) (( uint32 )6u + (8u * (( uint32 )(number) % 4u))) + +/* Mask to get valid range of system priority 0-3 */ +#define CY_INT_PRIORITY_MASK (( uint32 ) 0x03u) + +/* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */ +#define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */ +#define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */ +#define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */ +#define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */ +#define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */ + + +#if(CY_IP_SRSSV2) + + + /******************************************************************************* + * Low Voltage Detection API Constants + *******************************************************************************/ + + /* CySysLvdEnable() - parameter definitions */ + #define CY_LVD_THRESHOLD_1_75_V (( uint32 ) 0u) + #define CY_LVD_THRESHOLD_1_80_V (( uint32 ) 1u) + #define CY_LVD_THRESHOLD_1_90_V (( uint32 ) 2u) + #define CY_LVD_THRESHOLD_2_00_V (( uint32 ) 3u) + #define CY_LVD_THRESHOLD_2_10_V (( uint32 ) 4u) + #define CY_LVD_THRESHOLD_2_20_V (( uint32 ) 5u) + #define CY_LVD_THRESHOLD_2_30_V (( uint32 ) 6u) + #define CY_LVD_THRESHOLD_2_40_V (( uint32 ) 7u) + #define CY_LVD_THRESHOLD_2_50_V (( uint32 ) 8u) + #define CY_LVD_THRESHOLD_2_60_V (( uint32 ) 9u) + #define CY_LVD_THRESHOLD_2_70_V (( uint32 ) 10u) + #define CY_LVD_THRESHOLD_2_80_V (( uint32 ) 11u) + #define CY_LVD_THRESHOLD_2_90_V (( uint32 ) 12u) + #define CY_LVD_THRESHOLD_3_00_V (( uint32 ) 13u) + #define CY_LVD_THRESHOLD_3_20_V (( uint32 ) 14u) + #define CY_LVD_THRESHOLD_4_50_V (( uint32 ) 15u) + + /* CySysLvdEnable() - implementation definitions */ + #define CY_LVD_PWR_VMON_CONFIG_LVD_EN (( uint32 ) 0x01u) + #define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT (1u) + #define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK (( uint32 ) (0x0F << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT)) + #define CY_LVD_PROPAGATE_INT_TO_CPU (( uint32 ) 0x02u) + #define CY_LVD_STABILIZE_TIMEOUT_US (1000u) + + /* CySysLvdGetInterruptSource()/ CySysLvdClearInterrupt() - parameter definitions */ + #define CY_SYS_LVD_INT (( uint32 ) 0x02u) +#endif /* (CY_IP_SRSSV2) */ + +/* CyDelay()/CyDelayFreq() - implementation definitions */ +#define CY_DELAY_MS_OVERFLOW (0x8000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (999999u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (999u) + + +/******************************************************************************* +* ECO +*******************************************************************************/ +#if (CY_IP_ECO) + #if (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) + + /* CySysClkEcoStart() - implementation definitions */ + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN_SHIFT (0u) + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_CLK_EN_SHIFT)) + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN_TIMEOUT_US (10u) + + #define CY_SYS_CLK_ECO_CONFIG_ENABLE_SHIFT (31u) + #define CY_SYS_CLK_ECO_CONFIG_ENABLE ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_ENABLE_SHIFT)) + + #define CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR_SHIFT (0u) + #define CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR_SHIFT)) + + #define CY_SYS_CLK_ECO_CONFIG_AGC_EN_SHIFT (1u) + #define CY_SYS_CLK_ECO_CONFIG_AGC_EN ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_AGC_EN_SHIFT)) + + + /** + * \addtogroup group_api_eco + * @{ + */ + #define CY_SYS_CLK_ECO_WDTRIM0 (0u) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_WDTRIM1 (1u) + #define CY_SYS_CLK_ECO_WDTRIM2 (2u) + #define CY_SYS_CLK_ECO_WDTRIM3 (3u) + + #define CY_SYS_CLK_ECO_ATRIM0 (0u) + #define CY_SYS_CLK_ECO_ATRIM1 (1u) + #define CY_SYS_CLK_ECO_ATRIM2 (2u) + #define CY_SYS_CLK_ECO_ATRIM3 (3u) + #define CY_SYS_CLK_ECO_ATRIM4 (4u) + #define CY_SYS_CLK_ECO_ATRIM5 (5u) + #define CY_SYS_CLK_ECO_ATRIM6 (6u) + #define CY_SYS_CLK_ECO_ATRIM7 (7u) + + #define CY_SYS_CLK_ECO_FTRIM0 (0u) + #define CY_SYS_CLK_ECO_FTRIM1 (1u) + #define CY_SYS_CLK_ECO_FTRIM2 (2u) + #define CY_SYS_CLK_ECO_FTRIM3 (3u) + + #define CY_SYS_CLK_ECO_RTRIM0 (0u) + #define CY_SYS_CLK_ECO_RTRIM1 (1u) + #define CY_SYS_CLK_ECO_RTRIM2 (2u) + #define CY_SYS_CLK_ECO_RTRIM3 (3u) + + #define CY_SYS_CLK_ECO_GTRIM0 (0u) + #define CY_SYS_CLK_ECO_GTRIM1 (1u) + #define CY_SYS_CLK_ECO_GTRIM2 (2u) + #define CY_SYS_CLK_ECO_GTRIM3 (3u) + /** @} group_api_eco */ + + + /* CySysClkConfigureEcoTrim() - implementation definitions */ + #define CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT (0u) + #define CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT (2u) + #define CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK ((uint32) ((uint32) 7u << CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT (0u) + #define CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT (2u) + #define CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT (4u) + #define CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT)) + + + /* CySysClkConfigureEcoDrive() - implementation definitions */ + #define CY_SYS_CLK_ECO_FREQ_KHZ_MIN (4000u) + #define CY_SYS_CLK_ECO_FREQ_KHZ_MAX (33333u) + + #define CY_SYS_CLK_ECO_MAX_AMPL_MIN_mV (500u) + #define CY_SYS_CLK_ECO_TRIM_BOUNDARY (1200u) + + /* Constant coefficient: 5u * 4u * CY_M_PI * CY_M_PI * 4 / 10 */ + #define CY_SYS_CLK_ECO_GMMIN_COEFFICIENT (79u) + + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM0 (30000u) + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM1 (24000u) + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM2 (17000u) + + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM0 (600u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM1 (700u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM2 (800u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM3 (900u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM4 (1025u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM5 (1150u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM6 (1275u) + + #endif /* (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) */ +#endif /* (CY_IP_ECO) */ + + +/******************************************************************************* +* Access Arbitration API Constants +*******************************************************************************/ +#if (CY_IP_DMAC_PRESENT) + #define CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_RAM_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_FLASH_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_DMAC_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_SL_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_SL_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT)) + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +#if (CY_IP_DMAC_PRESENT) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_CPU (0u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_DMA (1u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_ROUND (2u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_ROUND_STICKY (3u) +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/******************************************************************************* +* Programmable Voltage Reference API +*******************************************************************************/ +#if (CY_IP_PASS) + + #define CYFLD_PASS_VREF_ENABLE__OFFSET (CYFLD_PASS_VREF0_ENABLE__OFFSET ) + #define CYFLD_PASS_VREF_ENABLE__SIZE (CYFLD_PASS_VREF0_ENABLE__SIZE ) + #define CYFLD_PASS_VREF_SUP_SEL__OFFSET (CYFLD_PASS_VREF0_SUP_SEL__OFFSET) + #define CYFLD_PASS_VREF_SUP_SEL__SIZE (CYFLD_PASS_VREF0_SUP_SEL__SIZE ) + #define CYFLD_PASS_VREF_SEL__OFFSET (CYFLD_PASS_VREF0_SEL__OFFSET ) + #define CYFLD_PASS_VREF_SEL__SIZE (CYFLD_PASS_VREF0_SEL__SIZE ) + + /* CySysSetGlobalVrefSource() */ + #define CY_SYS_VREF_SOURCE_BG (0u) + #define CY_SYS_VREF_SOURCE_VDDA (1u) + + /* CySysSetGlobalVrefBgGain() */ + #define CY_SYS_VREF_BG_GAINx1 (1u) + #define CY_SYS_VREF_BG_GAINx2 (2u) + + #ifdef CyDesignWideVoltageReference_PRB_REF + #define CYREG_PASS_PRB_REF (CyDesignWideVoltageReference_PRB_REF) + #endif + + #define CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT (0x20u) + +#endif /* (CY_IP_PASS) */ + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* Clocks API Registers +*******************************************************************************/ +#define CY_SYS_CLK_IMO_TRIM1_REG (*(reg32 *) CYREG_CLK_IMO_TRIM1) +#define CY_SYS_CLK_IMO_TRIM1_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM1) + +#define CY_SYS_CLK_IMO_TRIM2_REG (*(reg32 *) CYREG_CLK_IMO_TRIM2) +#define CY_SYS_CLK_IMO_TRIM2_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM2) + +#define CY_SYS_CLK_IMO_TRIM3_REG (*(reg32 *) CYREG_CLK_IMO_TRIM3) +#define CY_SYS_CLK_IMO_TRIM3_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM3) + +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_TRIM4_REG (*(reg32 *) CYREG_CLK_IMO_TRIM4) + #define CY_SYS_CLK_IMO_TRIM4_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM4) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_CLK_IMO_CONFIG_REG (*(reg32 *) CYREG_CLK_IMO_CONFIG) +#define CY_SYS_CLK_IMO_CONFIG_PTR ( (reg32 *) CYREG_CLK_IMO_CONFIG) + + +#define CY_SYS_CLK_SELECT_REG (*(reg32 *) CYREG_CLK_SELECT) +#define CY_SYS_CLK_SELECT_PTR ( (reg32 *) CYREG_CLK_SELECT) + +#if(CY_IP_SRSSV2) + + #if(CY_IP_HOBTO_DEVICE) + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number]) + #else + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number]) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG (*(reg8 *) CYREG_SFLASH_USBMODE_IMO_GAIN_TRIM) + #define CY_SFLASH_USBMODE_IMO_GAIN_TRIM_PTR ( (reg8 *) CYREG_SFLASH_USBMODE_IMO_GAIN_TRIM) + + #define CY_SFLASH_USBMODE_IMO_TEMPCO_REG (*(reg8 *) CYREG_SFLASH_USBMODE_IMO_TEMPCO) + #define CY_SFLASH_USBMODE_IMO_TEMPCO_PTR ( (reg8 *) CYREG_SFLASH_USBMODE_IMO_TEMPCO) + + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_48) + + #define CY_SFLASH_S1_TESTPGM_REV_REG (*(reg8 *) CYSFLASH_S1_testpgm_rev) + #define CY_SFLASH_S1_TESTPGM_REV_PTR ( (reg8 *) CYSFLASH_S1_testpgm_rev) + + #define CY_SFLASH_IMO_MAXF0_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF0) + #define CY_SFLASH_IMO_MAXF0_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF0) + + #define CY_SFLASH_IMO_ABS0_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS0) + #define CY_SFLASH_IMO_ABS0_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS0) + + #define CY_SFLASH_IMO_TMPCO0_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO0) + #define CY_SFLASH_IMO_TMPCO0_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO0) + + #define CY_SFLASH_IMO_MAXF1_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF1) + #define CY_SFLASH_IMO_MAXF1_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF1) + + #define CY_SFLASH_IMO_ABS1_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS1) + #define CY_SFLASH_IMO_ABS1_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS1) + + #define CY_SFLASH_IMO_TMPCO1_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO1) + #define CY_SFLASH_IMO_TMPCO1_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO1) + + #define CY_SFLASH_IMO_MAXF2_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF2) + #define CY_SFLASH_IMO_MAXF2_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF2) + + #define CY_SFLASH_IMO_ABS2_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS2) + #define CY_SFLASH_IMO_ABS2_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS2) + + #define CY_SFLASH_IMO_TMPCO2_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO2) + #define CY_SFLASH_IMO_TMPCO2_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO2) + + #define CY_SFLASH_IMO_MAXF3_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF3) + #define CY_SFLASH_IMO_MAXF3_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF3) + + #define CY_SFLASH_IMO_ABS3_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS3) + #define CY_SFLASH_IMO_ABS3_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS3) + + #define CY_SFLASH_IMO_TMPCO3_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO3) + #define CY_SFLASH_IMO_TMPCO3_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO3) + + #define CY_SFLASH_IMO_ABS4_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS4) + #define CY_SFLASH_IMO_ABS4_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS4) + + #define CY_SFLASH_IMO_TMPCO4_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO4) + #define CY_SFLASH_IMO_TMPCO4_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO4) + + #define CY_PWR_BG_TRIM4_REG (*(reg32 *) CYREG_PWR_BG_TRIM4) + #define CY_PWR_BG_TRIM4_PTR ( (reg32 *) CYREG_PWR_BG_TRIM4) + + #define CY_PWR_BG_TRIM5_REG (*(reg32 *) CYREG_PWR_BG_TRIM5) + #define CY_PWR_BG_TRIM5_PTR ( (reg32 *) CYREG_PWR_BG_TRIM5) + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #define CY_SFLASH_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#else + + #define CY_SYS_CLK_IMO_SELECT_REG (*(reg32 *) CYREG_CLK_IMO_SELECT) + #define CY_SYS_CLK_IMO_SELECT_PTR ( (reg32 *) CYREG_CLK_IMO_SELECT) + + #define CY_SFLASH_IMO_TCTRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number]) + #define CY_SFLASH_IMO_TCTRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number]) + + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number]) + + #if (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSLT) + + #define CY_SFLASH_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSLT) */ + +#endif /* (CY_IP_SRSSV2) */ + +#if(CY_IP_IMO_TRIMMABLE_BY_USB) + /* USB control 0 Register */ + #define CY_SYS_CLK_USBDEVv2_CR1_REG (*(reg32 *) CYREG_USBDEVv2_CR1) + #define CY_SYS_CLK_USBDEVv2_CR1_PTR ( (reg32 *) CYREG_USBDEVv2_CR1) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +/******************************************************************************* +* ECO +*******************************************************************************/ +#if (CY_IP_ECO) + #if (CY_IP_ECO_BLESS) + + /* Radio configuration register */ + #define CY_SYS_XTAL_BLESS_RF_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_RF_CONFIG) + #define CY_SYS_XTAL_BLESS_RF_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_RF_CONFIG) + + /* RFCTRL mode transition control */ + #define CY_SYS_XTAL_BLERD_DBUS_REG (*(reg32 *) CYREG_BLE_BLERD_DBUS) + #define CY_SYS_XTAL_BLERD_DBUS_PTR ( (reg32 *) CYREG_BLE_BLERD_DBUS) + + /* RFCTRL state information */ + #define CY_SYS_XTAL_BLERD_FSM_REG (*(reg32 *) CYREG_BLE_BLERD_FSM) + #define CY_SYS_XTAL_BLERD_FSM_PTR ( (reg32 *) CYREG_BLE_BLERD_FSM) + + /* BB bump configuration 1 */ + #define CY_SYS_XTAL_BLERD_BB_XO_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO) + #define CY_SYS_XTAL_BLERD_BB_XO_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO) + + /* BB bump configuration 2 */ + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM) + + /* Crystal clock divider configuration register */ + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + + #elif (CY_IP_ECO_BLESSV3) + /* Crystal clock divider configuration register */ + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + + /* RCB registers */ + #define CY_SYS_RCB_CTRL_REG (*(reg32 *) CYREG_BLE_RCB_CTRL) + #define CY_SYS_RCB_CTRL_PTR ( (reg32 *) CYREG_BLE_RCB_CTRL) + #define CY_SYS_RCB_TX_FIFO_WR_REG (*(reg32 *) CYREG_BLE_RCB_TX_FIFO_WR) + #define CY_SYS_RCB_TX_FIFO_WR_PTR ( (reg32 *) CYREG_BLE_RCB_TX_FIFO_WR) + #define CY_SYS_RCB_RX_FIFO_RD_REG (*(reg32 *) CYREG_BLE_RCB_RX_FIFO_RD) + #define CY_SYS_RCB_RX_FIFO_RD_PTR ( (reg32 *) CYREG_BLE_RCB_RX_FIFO_RD) + #define CY_SYS_RCB_INTR_REG (*(reg32 *) CYREG_BLE_RCB_INTR) + #define CY_SYS_RCB_INTR_PTR ( (reg32 *) CYREG_BLE_RCB_INTR) + #define CY_SYS_RCB_INTR_MASK_REG (*(reg32 *) CYREG_BLE_RCB_INTR_MASK) + #define CY_SYS_RCB_INTR_MASK_PTR ( (reg32 *) CYREG_BLE_RCB_INTR_MASK) + + + /* BLESS registers */ + #define CY_SYS_BLESS_MT_CFG_REG (*(reg32 *) CYREG_BLE_BLESS_MT_CFG) + #define CY_SYS_BLESS_MT_CFG_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_CFG) + #define CY_SYS_BLESS_MT_STATUS_REG (*(reg32 *) CYREG_BLE_BLESS_MT_STATUS) + #define CY_SYS_BLESS_MT_STATUS_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_STATUS) + #define CY_SYS_BLESS_INTR_STAT_REG (*(reg32 *) CYREG_BLE_BLESS_INTR_STAT) + #define CY_SYS_BLESS_INTR_STAT_PTR ( (reg32 *) CYREG_BLE_BLESS_INTR_STAT) + #define CY_SYS_BLESS_INTR_MASK_REG (*(reg32 *) CYREG_BLE_BLESS_INTR_MASK) + #define CY_SYS_BLESS_INTR_MASK_PTR ( (reg32 *) CYREG_BLE_BLESS_INTR_MASK) + #define CY_SYS_BLESS_MT_DELAY_CFG_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG) + #define CY_SYS_BLESS_MT_DELAY_CFG_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG) + #define CY_SYS_BLESS_MT_DELAY_CFG2_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG2) + #define CY_SYS_BLESS_MT_DELAY_CFG2_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG2) + #define CY_SYS_BLESS_MT_DELAY_CFG3_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG3) + #define CY_SYS_BLESS_MT_DELAY_CFG3_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG3) + + /* BLELL registers */ + #define CY_SYS_BLELL_COMMAND_REG (*(reg32 *) CYREG_BLE_BLELL_COMMAND_REGISTER) + #define CY_SYS_BLELL_COMMAND_PTR ( (reg32 *) CYREG_BLE_BLELL_COMMAND_REGISTER) + + #elif (CY_IP_ECO_SRSSLT) + + /* ECO Clock Select Register */ + #define CY_SYS_ECO_CLK_SELECT_REG (*(reg32 *) CYREG_EXCO_CLK_SELECT) + #define CY_SYS_ECO_CLK_SELECT_PTR ( (reg32 *) CYREG_EXCO_CLK_SELECT) + + /* ECO Configuration Register */ + #define CY_SYS_CLK_ECO_CONFIG_REG (*(reg32 *) CYREG_EXCO_ECO_CONFIG) + #define CY_SYS_CLK_ECO_CONFIG_PTR ( (reg32 *) CYREG_EXCO_ECO_CONFIG) + + /* ECO Status Register */ + #define CY_SYS_CLK_ECO_STATUS_REG (*(reg32 *) CYREG_EXCO_ECO_STATUS) + #define CY_SYS_CLK_ECO_STATUS_PTR ( (reg32 *) CYREG_EXCO_ECO_STATUS) + + /* PLL Configuration Register */ + #define CY_SYS_CLK_PLL0_CONFIG_REG (*(reg32 *) CYREG_EXCO_PLL_CONFIG) + #define CY_SYS_CLK_PLL0_CONFIG_PTR ( (reg32 *) CYREG_EXCO_PLL_CONFIG) + + /* PLL Status Register */ + #define CY_SYS_CLK_PLL_STATUS_REG (*(reg32 *) CYREG_EXCO_PLL_STATUS) + #define CY_SYS_CLK_PLL_STATUS_PTR ( (reg32 *) CYREG_EXCO_PLL_STATUS) + + #define CY_SYS_CLK_PLL_BASE (*(volatile cy_sys_clk_pll_struct *) CYREG_EXCO_PLL_CONFIG) + + /* ECO Trim0 Register */ + #define CY_SYS_CLK_ECO_TRIM0_REG (*(reg32 *) CYREG_EXCO_ECO_TRIM0) + #define CY_SYS_CLK_ECO_TRIM0_PTR ( (reg32 *) CYREG_EXCO_ECO_TRIM0) + + /* ECO Trim1 Register */ + #define CY_SYS_CLK_ECO_TRIM1_REG (*(reg32 *) CYREG_EXCO_ECO_TRIM1) + #define CY_SYS_CLK_ECO_TRIM1_PTR ( (reg32 *) CYREG_EXCO_ECO_TRIM1) + + /* PLL Trim Register */ + #define CY_SYS_CLK_PLL_TRIM_REG (*(reg32 *) CYREG_EXCO_PLL_TRIM) + #define CY_SYS_CLK_PLL_TRIM_PTR ( (reg32 *) CYREG_EXCO_PLL_TRIM) + + #define CY_SYS_EXCO_PGM_CLK_REG (*(reg32 *) CYREG_EXCO_EXCO_PGM_CLK) + #define CY_SYS_EXCO_PGM_CLK_PTR ( (reg32 *) CYREG_EXCO_EXCO_PGM_CLK) + + #else + /* ECO Configuration Register */ + #define CY_SYS_CLK_ECO_CONFIG_REG (*(reg32 *) CYREG_CLK_ECO_CONFIG) + #define CY_SYS_CLK_ECO_CONFIG_PTR ( (reg32 *) CYREG_CLK_ECO_CONFIG) + + /* ECO Status Register */ + #define CY_SYS_CLK_ECO_STATUS_REG (*(reg32 *) CYREG_CLK_ECO_STATUS) + #define CY_SYS_CLK_ECO_STATUS_PTR ( (reg32 *) CYREG_CLK_ECO_STATUS) + + /* ECO Trim0 Register */ + #define CY_SYS_CLK_ECO_TRIM0_REG (*(reg32 *) CYREG_CLK_ECO_TRIM0) + #define CY_SYS_CLK_ECO_TRIM0_PTR ( (reg32 *) CYREG_CLK_ECO_TRIM0) + + /* ECO Trim1 Register */ + #define CY_SYS_CLK_ECO_TRIM1_REG (*(reg32 *) CYREG_CLK_ECO_TRIM1) + #define CY_SYS_CLK_ECO_TRIM1_PTR ( (reg32 *) CYREG_CLK_ECO_TRIM1) + #endif /* (CY_IP_ECO_BLESS) */ +#endif /* (CY_IP_ECO) */ + + +/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() registers */ +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* WCO DPLL Register */ + #define CY_SYS_CLK_WCO_DPLL_REG (*(reg32 *) CYREG_WCO_DPLL) + #define CY_SYS_CLK_WCO_DPLL_PTR ( (reg32 *) CYREG_WCO_DPLL) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + /* Oscillator Interface Control */ + #define CY_SYS_CLK_OSCINTF_CTL_REG (*(reg32 *) CYREG_CLK_OSCINTF_CTL) + #define CY_SYS_CLK_OSCINTF_CTL_PTR ( (reg32 *) CYREG_CLK_OSCINTF_CTL) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +/******************************************************************************* +* PLL +*******************************************************************************/ +#if (CY_IP_SRSSV2 && CY_IP_PLL) + + /* PLL #0 Configuration Register */ + #define CY_SYS_CLK_PLL0_CONFIG_REG (*(reg32 *) CYREG_CLK_PLL0_CONFIG) + #define CY_SYS_CLK_PLL0_CONFIG_PTR ( (reg32 *) CYREG_CLK_PLL0_CONFIG) + + /* PLL #0 Status Register */ + #define CY_SYS_CLK_PLL0_STATUS_REG (*(reg32 *) CYREG_CLK_PLL0_STATUS) + #define CY_SYS_CLK_PLL0_STATUS_PTR ( (reg32 *) CYREG_CLK_PLL0_STATUS) + + + /* PLL #1 Configuration Register */ + #define CY_SYS_CLK_PLL1_CONFIG_REG (*(reg32 *) CYREG_CLK_PLL1_CONFIG) + #define CY_SYS_CLK_PLL1_CONFIG_PTR ( (reg32 *) CYREG_CLK_PLL1_CONFIG) + + /* PLL #1 Status Register */ + #define CY_SYS_CLK_PLL1_STATUS_REG (*(reg32 *) CYREG_CLK_PLL1_STATUS) + #define CY_SYS_CLK_PLL1_STATUS_PTR ( (reg32 *) CYREG_CLK_PLL1_STATUS) + + #define CY_SYS_CLK_PLL_BASE (*(volatile cy_sys_clk_pll_struct *) CYREG_CLK_PLL0_CONFIG) + +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + + +/******************************************************************************* +* System API Registers +*******************************************************************************/ +#if (CY_IP_CPUSS_CM0) + #define CY_SYS_AIRCR_REG (*(reg32 *) CYREG_CM0_AIRCR) + #define CY_SYS_AIRCR_PTR ( (reg32 *) CYREG_CM0_AIRCR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_SYS_AIRCR_REG (*(reg32 *) CYREG_CM0P_AIRCR) + #define CY_SYS_AIRCR_PTR ( (reg32 *) CYREG_CM0P_AIRCR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/* Reset Cause Observation Register */ +#define CY_SYS_RES_CAUSE_REG (*(reg32 *) CYREG_RES_CAUSE) +#define CY_SYS_RES_CAUSE_PTR ( (reg32 *) CYREG_RES_CAUSE) + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Low Voltage Detection + *******************************************************************************/ + + /* Voltage Monitoring Trim and Configuration */ + #define CY_LVD_PWR_VMON_CONFIG_REG (*(reg32 *) CYREG_PWR_VMON_CONFIG) + #define CY_LVD_PWR_VMON_CONFIG_PTR ( (reg32 *) CYREG_PWR_VMON_CONFIG) + + /* Power System Interrupt Mask Register */ + #define CY_LVD_PWR_INTR_MASK_REG (*(reg32 *) CYREG_PWR_INTR_MASK) + #define CY_LVD_PWR_INTR_MASK_PTR ( (reg32 *) CYREG_PWR_INTR_MASK) + + /* Power System Interrupt Register */ + #define CY_LVD_PWR_INTR_REG (*(reg32 *) CYREG_PWR_INTR) + #define CY_LVD_PWR_INTR_PTR ( (reg32 *) CYREG_PWR_INTR) + +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Interrupt API Registers +*******************************************************************************/ +#define CY_INT_VECT_TABLE ( (cyisraddress **) CYDEV_SRAM_BASE) + +#if (CY_IP_CPUSS_CM0) + #define CY_INT_PRIORITY_REG(number) ( ((reg32 *) CYREG_CM0_IPR0)[(number)/4u]) + #define CY_INT_PRIORITY_PTR(number) (&((reg32 *) CYREG_CM0_IPR0)[(number)/4u]) + + #define CY_INT_ENABLE_REG (*(reg32 *) CYREG_CM0_ISER) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_CM0_ISER) + + #define CY_INT_CLEAR_REG (*(reg32 *) CYREG_CM0_ICER) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_CM0_ICER) + + #define CY_INT_SET_PEND_REG (*(reg32 *) CYREG_CM0_ISPR) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_CM0_ISPR) + + #define CY_INT_CLR_PEND_REG (*(reg32 *) CYREG_CM0_ICPR) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_CM0_ICPR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_INT_PRIORITY_REG(number) ( ((reg32 *) CYREG_CM0P_IPR0)[(number)/4u]) + #define CY_INT_PRIORITY_PTR(number) (&((reg32 *) CYREG_CM0P_IPR0)[(number)/4u]) + + #define CY_INT_ENABLE_REG (*(reg32 *) CYREG_CM0P_ISER) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_CM0P_ISER) + + #define CY_INT_CLEAR_REG (*(reg32 *) CYREG_CM0P_ICER) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_CM0P_ICER) + + #define CY_INT_SET_PEND_REG (*(reg32 *) CYREG_CM0P_ISPR) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_CM0P_ISPR) + + #define CY_INT_CLR_PEND_REG (*(reg32 *) CYREG_CM0P_ICPR) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_CM0P_ICPR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/******************************************************************************* +* System tick API Registers +*******************************************************************************/ +#if (CY_IP_CPUSS_CM0) + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_CM0_SYST_CSR) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_CM0_SYST_CSR) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_CM0_SYST_RVR) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_CM0_SYST_RVR) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_CM0_SYST_CVR) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_CM0_SYST_CVR) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_CM0_SYST_CALIB) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_CM0_SYST_CALIB) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_CM0P_SYST_CSR) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_CM0P_SYST_CSR) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_CM0P_SYST_RVR) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_CM0P_SYST_RVR) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_CM0P_SYST_CVR) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_CM0P_SYST_CVR) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_CM0P_SYST_CALIB) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_CM0P_SYST_CALIB) +#endif /* (CY_IP_CPUSS_CM0) */ + + +/******************************************************************************* +* Access Arbitration API Registers +*******************************************************************************/ +#if (CY_IP_DMAC_PRESENT) + /* RAM control register */ + #define CY_SYS_CPUSS_RAM_CTL_REG (*(reg32 *) CYREG_CPUSS_RAM_CTL) + #define CY_SYS_CPUSS_RAM_CTL_PTR ( (reg32 *) CYREG_CPUSS_RAM_CTL) + + /* FLASH control register */ + #define CY_SYS_CPUSS_FLASH_CTL_REG (*(reg32 *) CYREG_CPUSS_FLASH_CTL) + #define CY_SYS_CPUSS_FLASH_CTL_PTR ( (reg32 *) CYREG_CPUSS_FLASH_CTL) + + /* DMAC control register */ + #define CY_SYS_CPUSS_DMAC_CTL_REG (*(reg32 *) CYREG_CPUSS_DMAC_CTL) + #define CY_SYS_CPUSS_DMAC_CTL_PTR ( (reg32 *) CYREG_CPUSS_DMAC_CTL) + + #if (CY_IP_SL_NR >= 1) + /* Slave control register # 0 */ + #if (CY_IP_SL_NR == 1) + #define CY_SYS_CPUSS_SL_CTL0_REG (*(reg32 *) CYREG_CPUSS_SL_CTL) + #define CY_SYS_CPUSS_SL_CTL0_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL) + #else + #define CY_SYS_CPUSS_SL_CTL0_REG (*(reg32 *) CYREG_CPUSS_SL_CTL0) + #define CY_SYS_CPUSS_SL_CTL0_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL0) + #endif /* (CY_IP_SL_NR == 1) */ + #endif /* (CY_IP_SL_NR > 0) */ + + #if (CY_IP_SL_NR >= 2) + /* Slave control register # 1 */ + #define CY_SYS_CPUSS_SL_CTL1_REG (*(reg32 *) CYREG_CPUSS_SL_CTL1) + #define CY_SYS_CPUSS_SL_CTL1_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL1) + #endif /* (CY_IP_SL_NR >= 1) */ + + #if (CY_IP_SL_NR >= 3) + /* Slave control register # 2 */ + #define CY_SYS_CPUSS_SL_CTL2_REG (*(reg32 *) CYREG_CPUSS_SL_CTL2) + #define CY_SYS_CPUSS_SL_CTL2_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL2) + #endif /* (CY_IP_SL_NR >= 2) */ + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions are intended for use in the application, +* use the following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) +#define CY_SYS_CLK_IMO_TRIM4_GAIN (CY_SYS_CLK_IMO_TRIM4_USB_GAIN) + +/* SFLASH0 block has been renamed to SFLASH */ +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + #if !defined(CYREG_SFLASH_IMO_TRIM21) + #define CYREG_SFLASH_IMO_TRIM21 (CYREG_SFLASH0_IMO_TRIM21) + #endif /* !defined(CYREG_SFLASH_IMO_TRIM21) */ +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + +#if (CY_IP_CPUSS_CM0) + + #define CY_SYS_CM0_AIRCR_REG (CY_SYS_AIRCR_REG) + #define CY_SYS_CM0_AIRCR_PTR (CY_SYS_AIRCR_PTR) + + #define CY_SYS_CM0_AIRCR_VECTKEY_SHIFT (CY_SYS_AIRCR_VECTKEY_SHIFT ) + #define CY_SYS_CM0_AIRCR_VECTKEY (CY_SYS_AIRCR_VECTKEY ) + #define CY_SYS_CM0_AIRCR_VECTKEY_MASK (CY_SYS_AIRCR_VECTKEY_MASK ) + #define CY_SYS_CM0_AIRCR_SYSRESETREQ_SHIFT (CY_SYS_AIRCR_SYSRESETREQ_SHIFT) + #define CY_SYS_CM0_AIRCR_SYSRESETREQ (CY_SYS_AIRCR_SYSRESETREQ ) + +#endif /* (CY_IP_CPUSS_CM0) */ + +#endif /* CY_BOOT_CYLIB_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1.c new file mode 100644 index 0000000..9bee24a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: Input_1.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "Input_1.h" + + +#if defined(Input_1__PC) + #define Input_1_SetP4PinDriveMode(shift, mode) \ + do { \ + Input_1_PC = (Input_1_PC & \ + (uint32)(~(uint32)(Input_1_DRIVE_MODE_IND_MASK << \ + (Input_1_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (Input_1_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define Input_1_SetP4PinDriveMode(shift, mode) \ + do { \ + Input_1_USBIO_CTRL_REG = (Input_1_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(Input_1_DRIVE_MODE_IND_MASK << \ + (Input_1_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (Input_1_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(Input_1__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: Input_1_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet Input_1_SUT.c usage_Input_1_SetDriveMode + *******************************************************************************/ + void Input_1_SetDriveMode(uint8 mode) + { + Input_1_SetP4PinDriveMode(Input_1__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: Input_1_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_Write +*******************************************************************************/ +void Input_1_Write(uint8 value) +{ + uint8 drVal = (uint8)(Input_1_DR & (uint8)(~Input_1_MASK)); + drVal = (drVal | ((uint8)(value << Input_1_SHIFT) & Input_1_MASK)); + Input_1_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: Input_1_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_Read +*******************************************************************************/ +uint8 Input_1_Read(void) +{ + return (uint8)((Input_1_PS & Input_1_MASK) >> Input_1_SHIFT); +} + + +/******************************************************************************* +* Function Name: Input_1_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred Input_1_Read() API because the +* Input_1_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_ReadDataReg +*******************************************************************************/ +uint8 Input_1_ReadDataReg(void) +{ + return (uint8)((Input_1_DR & Input_1_MASK) >> Input_1_SHIFT); +} + + +/******************************************************************************* +* Function Name: Input_1_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use Input_1_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - Input_1_0_INTR (First pin in the list) +* - Input_1_1_INTR (Second pin in the list) +* - ... +* - Input_1_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_SetInterruptMode +*******************************************************************************/ +void Input_1_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = Input_1_INTCFG & (uint32)(~(uint32)position); + Input_1_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: Input_1_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_ClearInterrupt +*******************************************************************************/ +uint8 Input_1_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(Input_1_INTSTAT & Input_1_MASK); + Input_1_INTSTAT = maskedStatus; + return maskedStatus >> Input_1_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1.h new file mode 100644 index 0000000..a02adc3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: Input_1.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_Input_1_H) /* Pins Input_1_H */ +#define CY_PINS_Input_1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "Input_1_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} Input_1_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 Input_1_Read(void); +void Input_1_Write(uint8 value); +uint8 Input_1_ReadDataReg(void); +#if defined(Input_1__PC) || (CY_PSOC4_4200L) + void Input_1_SetDriveMode(uint8 mode); +#endif +void Input_1_SetInterruptMode(uint16 position, uint16 mode); +uint8 Input_1_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void Input_1_Sleep(void); +void Input_1_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(Input_1__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define Input_1_DRIVE_MODE_BITS (3) + #define Input_1_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - Input_1_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the Input_1_SetDriveMode() function. + * @{ + */ + #define Input_1_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define Input_1_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define Input_1_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define Input_1_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define Input_1_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define Input_1_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define Input_1_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define Input_1_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define Input_1_MASK Input_1__MASK +#define Input_1_SHIFT Input_1__SHIFT +#define Input_1_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in Input_1_SetInterruptMode() function. + * @{ + */ + #define Input_1_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define Input_1_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define Input_1_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define Input_1_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(Input_1__SIO) + #define Input_1_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(Input_1__PC) && (CY_PSOC4_4200L) + #define Input_1_USBIO_ENABLE ((uint32)0x80000000u) + #define Input_1_USBIO_DISABLE ((uint32)(~Input_1_USBIO_ENABLE)) + #define Input_1_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define Input_1_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define Input_1_USBIO_ENTER_SLEEP ((uint32)((1u << Input_1_USBIO_SUSPEND_SHIFT) \ + | (1u << Input_1_USBIO_SUSPEND_DEL_SHIFT))) + #define Input_1_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << Input_1_USBIO_SUSPEND_SHIFT))) + #define Input_1_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << Input_1_USBIO_SUSPEND_DEL_SHIFT))) + #define Input_1_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(Input_1__PC) + /* Port Configuration */ + #define Input_1_PC (* (reg32 *) Input_1__PC) +#endif +/* Pin State */ +#define Input_1_PS (* (reg32 *) Input_1__PS) +/* Data Register */ +#define Input_1_DR (* (reg32 *) Input_1__DR) +/* Input Buffer Disable Override */ +#define Input_1_INP_DIS (* (reg32 *) Input_1__PC2) + +/* Interrupt configuration Registers */ +#define Input_1_INTCFG (* (reg32 *) Input_1__INTCFG) +#define Input_1_INTSTAT (* (reg32 *) Input_1__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define Input_1_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(Input_1__SIO) + #define Input_1_SIO_REG (* (reg32 *) Input_1__SIO) +#endif /* (Input_1__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(Input_1__PC) && (CY_PSOC4_4200L) + #define Input_1_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define Input_1_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define Input_1_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define Input_1_DRIVE_MODE_SHIFT (0x00u) +#define Input_1_DRIVE_MODE_MASK (0x07u << Input_1_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins Input_1_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1_PM.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1_PM.c new file mode 100644 index 0000000..de3c500 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: Input_1.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "Input_1.h" + +static Input_1_BACKUP_STRUCT Input_1_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: Input_1_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_Sleep_Wakeup +*******************************************************************************/ +void Input_1_Sleep(void) +{ + #if defined(Input_1__PC) + Input_1_backup.pcState = Input_1_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + Input_1_backup.usbState = Input_1_CR1_REG; + Input_1_USB_POWER_REG |= Input_1_USBIO_ENTER_SLEEP; + Input_1_CR1_REG &= Input_1_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(Input_1__SIO) + Input_1_backup.sioState = Input_1_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + Input_1_SIO_REG &= (uint32)(~Input_1_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: Input_1_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to Input_1_Sleep() for an example usage. +*******************************************************************************/ +void Input_1_Wakeup(void) +{ + #if defined(Input_1__PC) + Input_1_PC = Input_1_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + Input_1_USB_POWER_REG &= Input_1_USBIO_EXIT_SLEEP_PH1; + Input_1_CR1_REG = Input_1_backup.usbState; + Input_1_USB_POWER_REG &= Input_1_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(Input_1__SIO) + Input_1_SIO_REG = Input_1_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1_aliases.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1_aliases.h new file mode 100644 index 0000000..ad275f1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Input_1_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: Input_1.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_Input_1_ALIASES_H) /* Pins Input_1_ALIASES_H */ +#define CY_PINS_Input_1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define Input_1_0 (Input_1__0__PC) +#define Input_1_0_PS (Input_1__0__PS) +#define Input_1_0_PC (Input_1__0__PC) +#define Input_1_0_DR (Input_1__0__DR) +#define Input_1_0_SHIFT (Input_1__0__SHIFT) +#define Input_1_0_INTR ((uint16)((uint16)0x0003u << (Input_1__0__SHIFT*2u))) + +#define Input_1_INTR_ALL ((uint16)(Input_1_0_INTR)) + + +#endif /* End Pins Input_1_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED.c new file mode 100644 index 0000000..f6a2fdf --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: LED.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED.h" + + +#if defined(LED__PC) + #define LED_SetP4PinDriveMode(shift, mode) \ + do { \ + LED_PC = (LED_PC & \ + (uint32)(~(uint32)(LED_DRIVE_MODE_IND_MASK << \ + (LED_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (LED_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define LED_SetP4PinDriveMode(shift, mode) \ + do { \ + LED_USBIO_CTRL_REG = (LED_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(LED_DRIVE_MODE_IND_MASK << \ + (LED_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (LED_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(LED__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: LED_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet LED_SUT.c usage_LED_SetDriveMode + *******************************************************************************/ + void LED_SetDriveMode(uint8 mode) + { + LED_SetP4PinDriveMode(LED__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: LED_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Write +*******************************************************************************/ +void LED_Write(uint8 value) +{ + uint8 drVal = (uint8)(LED_DR & (uint8)(~LED_MASK)); + drVal = (drVal | ((uint8)(value << LED_SHIFT) & LED_MASK)); + LED_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: LED_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Read +*******************************************************************************/ +uint8 LED_Read(void) +{ + return (uint8)((LED_PS & LED_MASK) >> LED_SHIFT); +} + + +/******************************************************************************* +* Function Name: LED_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED_Read() API because the +* LED_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_ReadDataReg +*******************************************************************************/ +uint8 LED_ReadDataReg(void) +{ + return (uint8)((LED_DR & LED_MASK) >> LED_SHIFT); +} + + +/******************************************************************************* +* Function Name: LED_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use LED_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - LED_0_INTR (First pin in the list) +* - LED_1_INTR (Second pin in the list) +* - ... +* - LED_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_SetInterruptMode +*******************************************************************************/ +void LED_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = LED_INTCFG & (uint32)(~(uint32)position); + LED_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: LED_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_ClearInterrupt +*******************************************************************************/ +uint8 LED_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(LED_INTSTAT & LED_MASK); + LED_INTSTAT = maskedStatus; + return maskedStatus >> LED_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED.h new file mode 100644 index 0000000..900f52f --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: LED.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_H) /* Pins LED_H */ +#define CY_PINS_LED_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "LED_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} LED_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 LED_Read(void); +void LED_Write(uint8 value); +uint8 LED_ReadDataReg(void); +#if defined(LED__PC) || (CY_PSOC4_4200L) + void LED_SetDriveMode(uint8 mode); +#endif +void LED_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void LED_Sleep(void); +void LED_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(LED__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define LED_DRIVE_MODE_BITS (3) + #define LED_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - LED_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED_SetDriveMode() function. + * @{ + */ + #define LED_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define LED_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define LED_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define LED_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define LED_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define LED_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define LED_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define LED_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define LED_MASK LED__MASK +#define LED_SHIFT LED__SHIFT +#define LED_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED_SetInterruptMode() function. + * @{ + */ + #define LED_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define LED_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define LED_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define LED_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(LED__SIO) + #define LED_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(LED__PC) && (CY_PSOC4_4200L) + #define LED_USBIO_ENABLE ((uint32)0x80000000u) + #define LED_USBIO_DISABLE ((uint32)(~LED_USBIO_ENABLE)) + #define LED_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define LED_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define LED_USBIO_ENTER_SLEEP ((uint32)((1u << LED_USBIO_SUSPEND_SHIFT) \ + | (1u << LED_USBIO_SUSPEND_DEL_SHIFT))) + #define LED_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << LED_USBIO_SUSPEND_SHIFT))) + #define LED_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << LED_USBIO_SUSPEND_DEL_SHIFT))) + #define LED_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(LED__PC) + /* Port Configuration */ + #define LED_PC (* (reg32 *) LED__PC) +#endif +/* Pin State */ +#define LED_PS (* (reg32 *) LED__PS) +/* Data Register */ +#define LED_DR (* (reg32 *) LED__DR) +/* Input Buffer Disable Override */ +#define LED_INP_DIS (* (reg32 *) LED__PC2) + +/* Interrupt configuration Registers */ +#define LED_INTCFG (* (reg32 *) LED__INTCFG) +#define LED_INTSTAT (* (reg32 *) LED__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define LED_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(LED__SIO) + #define LED_SIO_REG (* (reg32 *) LED__SIO) +#endif /* (LED__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(LED__PC) && (CY_PSOC4_4200L) + #define LED_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define LED_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define LED_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define LED_DRIVE_MODE_SHIFT (0x00u) +#define LED_DRIVE_MODE_MASK (0x07u << LED_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins LED_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED_PM.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED_PM.c new file mode 100644 index 0000000..7d143dd --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: LED.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED.h" + +static LED_BACKUP_STRUCT LED_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: LED_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Sleep_Wakeup +*******************************************************************************/ +void LED_Sleep(void) +{ + #if defined(LED__PC) + LED_backup.pcState = LED_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + LED_backup.usbState = LED_CR1_REG; + LED_USB_POWER_REG |= LED_USBIO_ENTER_SLEEP; + LED_CR1_REG &= LED_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(LED__SIO) + LED_backup.sioState = LED_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + LED_SIO_REG &= (uint32)(~LED_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: LED_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to LED_Sleep() for an example usage. +*******************************************************************************/ +void LED_Wakeup(void) +{ + #if defined(LED__PC) + LED_PC = LED_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + LED_USB_POWER_REG &= LED_USBIO_EXIT_SLEEP_PH1; + LED_CR1_REG = LED_backup.usbState; + LED_USB_POWER_REG &= LED_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(LED__SIO) + LED_SIO_REG = LED_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED_aliases.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED_aliases.h new file mode 100644 index 0000000..056ce76 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/LED_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: LED.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_ALIASES_H) /* Pins LED_ALIASES_H */ +#define CY_PINS_LED_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define LED_0 (LED__0__PC) +#define LED_0_PS (LED__0__PS) +#define LED_0_PC (LED__0__PC) +#define LED_0_DR (LED__0__DR) +#define LED_0_SHIFT (LED__0__SHIFT) +#define LED_0_INTR ((uint16)((uint16)0x0003u << (LED__0__SHIFT*2u))) + +#define LED_INTR_ALL ((uint16)(LED_0_INTR)) + + +#endif /* End Pins LED_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART.c new file mode 100644 index 0000000..7e83645 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART.c @@ -0,0 +1,818 @@ +/***************************************************************************//** +* \file UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" + +#if (UART_SCB_MODE_I2C_INC) + #include "UART_I2C_PVT.h" +#endif /* (UART_SCB_MODE_I2C_INC) */ + +#if (UART_SCB_MODE_EZI2C_INC) + #include "UART_EZI2C_PVT.h" +#endif /* (UART_SCB_MODE_EZI2C_INC) */ + +#if (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) + #include "UART_SPI_UART_PVT.h" +#endif /* (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) */ + + +/*************************************** +* Run Time Configuration Vars +***************************************/ + +/* Stores internal component configuration for Unconfigured mode */ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + uint8 UART_scbMode = UART_SCB_MODE_UNCONFIG; + uint8 UART_scbEnableWake; + uint8 UART_scbEnableIntr; + + /* I2C configuration variables */ + uint8 UART_mode; + uint8 UART_acceptAddr; + + /* SPI/UART configuration variables */ + volatile uint8 * UART_rxBuffer; + uint8 UART_rxDataBits; + uint32 UART_rxBufferSize; + + volatile uint8 * UART_txBuffer; + uint8 UART_txDataBits; + uint32 UART_txBufferSize; + + /* EZI2C configuration variables */ + uint8 UART_numberOfAddr; + uint8 UART_subAddrSize; +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Common SCB Vars +***************************************/ +/** +* \addtogroup group_general +* \{ +*/ + +/** UART_initVar indicates whether the UART +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the UART_Start() routine. +* +* If re-initialization of the component is required, then the +* UART_Init() function can be called before the +* UART_Start() or UART_Enable() function. +*/ +uint8 UART_initVar = 0u; + + +#if (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) + /** This global variable stores TX interrupt sources after + * UART_Stop() is called. Only these TX interrupt sources + * will be restored on a subsequent UART_Enable() call. + */ + uint16 UART_IntrTxMask = 0u; +#endif /* (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) */ +/** \} globals */ + +#if (UART_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + void (*UART_customIntrHandler)(void) = NULL; +#endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +static void UART_ScbEnableIntr(void); +static void UART_ScbModeStop(void); +static void UART_ScbModePostEnable(void); + + +/******************************************************************************* +* Function Name: UART_Init +****************************************************************************//** +* +* Initializes the UART component to operate in one of the selected +* configurations: I2C, SPI, UART or EZI2C. +* When the configuration is set to "Unconfigured SCB", this function does +* not do any initialization. Use mode-specific initialization APIs instead: +* UART_I2CInit, UART_SpiInit, +* UART_UartInit or UART_EzI2CInit. +* +*******************************************************************************/ +void UART_Init(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + if (UART_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + UART_initVar = 0u; + } + else + { + /* Initialization was done before this function call */ + } + +#elif (UART_SCB_MODE_I2C_CONST_CFG) + UART_I2CInit(); + +#elif (UART_SCB_MODE_SPI_CONST_CFG) + UART_SpiInit(); + +#elif (UART_SCB_MODE_UART_CONST_CFG) + UART_UartInit(); + +#elif (UART_SCB_MODE_EZI2C_CONST_CFG) + UART_EzI2CInit(); + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_Enable +****************************************************************************//** +* +* Enables UART component operation: activates the hardware and +* internal interrupt. It also restores TX interrupt sources disabled after the +* UART_Stop() function was called (note that level-triggered TX +* interrupt sources remain disabled to not cause code lock-up). +* For I2C and EZI2C modes the interrupt is internal and mandatory for +* operation. For SPI and UART modes the interrupt can be configured as none, +* internal or external. +* The UART configuration should be not changed when the component +* is enabled. Any configuration changes should be made after disabling the +* component. +* When configuration is set to “Unconfigured UART”, the component +* must first be initialized to operate in one of the following configurations: +* I2C, SPI, UART or EZ I2C, using the mode-specific initialization API. +* Otherwise this function does not enable the component. +* +*******************************************************************************/ +void UART_Enable(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Enable SCB block, only if it is already configured */ + if (!UART_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + UART_CTRL_REG |= UART_CTRL_ENABLED; + + UART_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + UART_ScbModePostEnable(); + } +#else + UART_CTRL_REG |= UART_CTRL_ENABLED; + + UART_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + UART_ScbModePostEnable(); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_Start +****************************************************************************//** +* +* Invokes UART_Init() and UART_Enable(). +* After this function call, the component is enabled and ready for operation. +* When configuration is set to "Unconfigured SCB", the component must first be +* initialized to operate in one of the following configurations: I2C, SPI, UART +* or EZI2C. Otherwise this function does not enable the component. +* +* \globalvars +* UART_initVar - used to check initial configuration, modified +* on first function call. +* +*******************************************************************************/ +void UART_Start(void) +{ + if (0u == UART_initVar) + { + UART_Init(); + UART_initVar = 1u; /* Component was initialized */ + } + + UART_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_Stop +****************************************************************************//** +* +* Disables the UART component: disable the hardware and internal +* interrupt. It also disables all TX interrupt sources so as not to cause an +* unexpected interrupt trigger because after the component is enabled, the +* TX FIFO is empty. +* Refer to the function UART_Enable() for the interrupt +* configuration details. +* This function disables the SCB component without checking to see if +* communication is in progress. Before calling this function it may be +* necessary to check the status of communication to make sure communication +* is complete. If this is not done then communication could be stopped mid +* byte and corrupted data could result. +* +*******************************************************************************/ +void UART_Stop(void) +{ +#if (UART_SCB_IRQ_INTERNAL) + UART_DisableInt(); +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + /* Call Stop function specific to current operation mode */ + UART_ScbModeStop(); + + /* Disable SCB IP */ + UART_CTRL_REG &= (uint32) ~UART_CTRL_ENABLED; + + /* Disable all TX interrupt sources so as not to cause an unexpected + * interrupt trigger after the component will be enabled because the + * TX FIFO is empty. + * For SCB IP v0, it is critical as it does not mask-out interrupt + * sources when it is disabled. This can cause a code lock-up in the + * interrupt handler because TX FIFO cannot be loaded after the block + * is disabled. + */ + UART_SetTxInterruptMode(UART_NO_INTR_SOURCES); + +#if (UART_SCB_IRQ_INTERNAL) + UART_ClearPendingInt(); +#endif /* (UART_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: UART_SetRxFifoLevel +****************************************************************************//** +* +* Sets level in the RX FIFO to generate a RX level interrupt. +* When the RX FIFO has more entries than the RX FIFO level an RX level +* interrupt request is generated. +* +* \param level: Level in the RX FIFO to generate RX level interrupt. +* The range of valid level values is between 0 and RX FIFO depth - 1. +* +*******************************************************************************/ +void UART_SetRxFifoLevel(uint32 level) +{ + uint32 rxFifoCtrl; + + rxFifoCtrl = UART_RX_FIFO_CTRL_REG; + + rxFifoCtrl &= ((uint32) ~UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + rxFifoCtrl |= ((uint32) (UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_RX_FIFO_CTRL_REG = rxFifoCtrl; +} + + +/******************************************************************************* +* Function Name: UART_SetTxFifoLevel +****************************************************************************//** +* +* Sets level in the TX FIFO to generate a TX level interrupt. +* When the TX FIFO has less entries than the TX FIFO level an TX level +* interrupt request is generated. +* +* \param level: Level in the TX FIFO to generate TX level interrupt. +* The range of valid level values is between 0 and TX FIFO depth - 1. +* +*******************************************************************************/ +void UART_SetTxFifoLevel(uint32 level) +{ + uint32 txFifoCtrl; + + txFifoCtrl = UART_TX_FIFO_CTRL_REG; + + txFifoCtrl &= ((uint32) ~UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + txFifoCtrl |= ((uint32) (UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_TX_FIFO_CTRL_REG = txFifoCtrl; +} + + +#if (UART_SCB_IRQ_INTERNAL) + /******************************************************************************* + * Function Name: UART_SetCustomInterruptHandler + ****************************************************************************//** + * + * Registers a function to be called by the internal interrupt handler. + * First the function that is registered is called, then the internal interrupt + * handler performs any operation such as software buffer management functions + * before the interrupt returns. It is the user's responsibility not to break + * the software buffer operations. Only one custom handler is supported, which + * is the function provided by the most recent call. + * At the initialization time no custom handler is registered. + * + * \param func: Pointer to the function to register. + * The value NULL indicates to remove the current custom interrupt + * handler. + * + *******************************************************************************/ + void UART_SetCustomInterruptHandler(void (*func)(void)) + { + #if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + UART_customIntrHandler = func; /* Register interrupt handler */ + #else + if (NULL != func) + { + /* Suppress compiler warning */ + } + #endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ + } +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + +/******************************************************************************* +* Function Name: UART_ScbModeEnableIntr +****************************************************************************//** +* +* Enables an interrupt for a specific mode. +* +*******************************************************************************/ +static void UART_ScbEnableIntr(void) +{ +#if (UART_SCB_IRQ_INTERNAL) + /* Enable interrupt in NVIC */ + #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + if (0u != UART_scbEnableIntr) + { + UART_EnableInt(); + } + + #else + UART_EnableInt(); + + #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +#endif /* (UART_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: UART_ScbModePostEnable +****************************************************************************//** +* +* Calls the PostEnable function for a specific operation mode. +* +*******************************************************************************/ +static void UART_ScbModePostEnable(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) +#if (!UART_CY_SCBIP_V1) + if (UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiPostEnable(); + } + else if (UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartPostEnable(); + } + else + { + /* Unknown mode: do nothing */ + } +#endif /* (!UART_CY_SCBIP_V1) */ + +#elif (UART_SCB_MODE_SPI_CONST_CFG) + UART_SpiPostEnable(); + +#elif (UART_SCB_MODE_UART_CONST_CFG) + UART_UartPostEnable(); + +#else + /* Unknown mode: do nothing */ +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_ScbModeStop +****************************************************************************//** +* +* Calls the Stop function for a specific operation mode. +* +*******************************************************************************/ +static void UART_ScbModeStop(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + if (UART_SCB_MODE_I2C_RUNTM_CFG) + { + UART_I2CStop(); + } + else if (UART_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_EzI2CStop(); + } +#if (!UART_CY_SCBIP_V1) + else if (UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiStop(); + } + else if (UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartStop(); + } +#endif /* (!UART_CY_SCBIP_V1) */ + else + { + /* Unknown mode: do nothing */ + } +#elif (UART_SCB_MODE_I2C_CONST_CFG) + UART_I2CStop(); + +#elif (UART_SCB_MODE_EZI2C_CONST_CFG) + UART_EzI2CStop(); + +#elif (UART_SCB_MODE_SPI_CONST_CFG) + UART_SpiStop(); + +#elif (UART_SCB_MODE_UART_CONST_CFG) + UART_UartStop(); + +#else + /* Unknown mode: do nothing */ +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: UART_SetPins + ****************************************************************************//** + * + * Sets the pins settings accordingly to the selected operation mode. + * Only available in the Unconfigured operation mode. The mode specific + * initialization function calls it. + * Pins configuration is set by PSoC Creator when a specific mode of operation + * is selected in design time. + * + * \param mode: Mode of SCB operation. + * \param subMode: Sub-mode of SCB operation. It is only required for SPI and UART + * modes. + * \param uartEnableMask: enables TX or RX direction and RTS and CTS signals. + * + *******************************************************************************/ + void UART_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask) + { + uint32 pinsDm[UART_SCB_PINS_NUMBER]; + uint32 i; + + #if (!UART_CY_SCBIP_V1) + uint32 pinsInBuf = 0u; + #endif /* (!UART_CY_SCBIP_V1) */ + + uint32 hsiomSel[UART_SCB_PINS_NUMBER] = + { + UART_RX_SCL_MOSI_HSIOM_SEL_GPIO, + UART_TX_SDA_MISO_HSIOM_SEL_GPIO, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + + #if (UART_CY_SCBIP_V1) + /* Supress compiler warning. */ + if ((0u == subMode) || (0u == uartEnableMask)) + { + } + #endif /* (UART_CY_SCBIP_V1) */ + + /* Set default HSIOM to GPIO and Drive Mode to Analog Hi-Z */ + for (i = 0u; i < UART_SCB_PINS_NUMBER; i++) + { + pinsDm[i] = UART_PIN_DM_ALG_HIZ; + } + + if ((UART_SCB_MODE_I2C == mode) || + (UART_SCB_MODE_EZI2C == mode)) + { + #if (UART_RX_SCL_MOSI_PIN) + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_I2C; + pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + #if (!UART_CY_SCBIP_V1) + else if (UART_SCB_MODE_SPI == mode) + { + #if (UART_RX_SCL_MOSI_PIN) + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_SPI; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_SPI; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_SPI; + #endif /* (UART_TX_SDA_MISO_PIN) */ + + #if (UART_SCLK_PIN) + hsiomSel[UART_SCLK_PIN_INDEX] = UART_SCLK_HSIOM_SEL_SPI; + #endif /* (UART_SCLK_PIN) */ + + if (UART_SPI_SLAVE == subMode) + { + /* Slave */ + pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + + #if (UART_SS0_PIN) + /* Only SS0 is valid choice for Slave */ + hsiomSel[UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_SPI; + pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #endif /* (UART_SS0_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + /* Disable input buffer */ + pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + else + { + /* (Master) */ + pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_STRONG; + + #if (UART_SS0_PIN) + hsiomSel [UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_SPI; + pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS0_PIN_MASK; + #endif /* (UART_SS0_PIN) */ + + #if (UART_SS1_PIN) + hsiomSel [UART_SS1_PIN_INDEX] = UART_SS1_HSIOM_SEL_SPI; + pinsDm [UART_SS1_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS1_PIN_MASK; + #endif /* (UART_SS1_PIN) */ + + #if (UART_SS2_PIN) + hsiomSel [UART_SS2_PIN_INDEX] = UART_SS2_HSIOM_SEL_SPI; + pinsDm [UART_SS2_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS2_PIN_MASK; + #endif /* (UART_SS2_PIN) */ + + #if (UART_SS3_PIN) + hsiomSel [UART_SS3_PIN_INDEX] = UART_SS3_HSIOM_SEL_SPI; + pinsDm [UART_SS3_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS3_PIN_MASK; + #endif /* (UART_SS3_PIN) */ + + /* Disable input buffers */ + #if (UART_RX_SCL_MOSI_PIN) + pinsInBuf |= UART_RX_SCL_MOSI_PIN_MASK; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + pinsInBuf |= UART_RX_WAKE_SCL_MOSI_PIN_MASK; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_SCLK_PIN) + pinsInBuf |= UART_SCLK_PIN_MASK; + #endif /* (UART_SCLK_PIN) */ + } + } + else /* UART */ + { + if (UART_UART_MODE_SMARTCARD == subMode) + { + /* SmartCard */ + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + else /* Standard or IrDA */ + { + if (0u != (UART_UART_RX_PIN_ENABLE & uartEnableMask)) + { + #if (UART_RX_SCL_MOSI_PIN) + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + } + + if (0u != (UART_UART_TX_PIN_ENABLE & uartEnableMask)) + { + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + if (UART_UART_MODE_STD == subMode) + { + if (0u != (UART_UART_CTS_PIN_ENABLE & uartEnableMask)) + { + /* CTS input is multiplexed with SCLK */ + #if (UART_SCLK_PIN) + hsiomSel[UART_SCLK_PIN_INDEX] = UART_SCLK_HSIOM_SEL_UART; + pinsDm [UART_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #endif /* (UART_SCLK_PIN) */ + } + + if (0u != (UART_UART_RTS_PIN_ENABLE & uartEnableMask)) + { + /* RTS output is multiplexed with SS0 */ + #if (UART_SS0_PIN) + hsiomSel[UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_UART; + pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= UART_SS0_PIN_MASK; + #endif /* (UART_SS0_PIN) */ + } + } + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + } + } + #endif /* (!UART_CY_SCBIP_V1) */ + + /* Configure pins: set HSIOM, DM and InputBufEnable */ + /* Note: the DR register settings do not effect the pin output if HSIOM is other than GPIO */ + + #if (UART_RX_SCL_MOSI_PIN) + UART_SET_HSIOM_SEL(UART_RX_SCL_MOSI_HSIOM_REG, + UART_RX_SCL_MOSI_HSIOM_MASK, + UART_RX_SCL_MOSI_HSIOM_POS, + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX]); + + UART_uart_rx_i2c_scl_spi_mosi_SetDriveMode((uint8) pinsDm[UART_RX_SCL_MOSI_PIN_INDEX]); + + #if (!UART_CY_SCBIP_V1) + UART_SET_INP_DIS(UART_uart_rx_i2c_scl_spi_mosi_INP_DIS, + UART_uart_rx_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & UART_RX_SCL_MOSI_PIN_MASK))); + #endif /* (!UART_CY_SCBIP_V1) */ + + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + UART_SET_HSIOM_SEL(UART_RX_WAKE_SCL_MOSI_HSIOM_REG, + UART_RX_WAKE_SCL_MOSI_HSIOM_MASK, + UART_RX_WAKE_SCL_MOSI_HSIOM_POS, + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + UART_uart_rx_wake_i2c_scl_spi_mosi_SetDriveMode((uint8) + pinsDm[UART_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + UART_SET_INP_DIS(UART_uart_rx_wake_i2c_scl_spi_mosi_INP_DIS, + UART_uart_rx_wake_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & UART_RX_WAKE_SCL_MOSI_PIN_MASK))); + + /* Set interrupt on falling edge */ + UART_SET_INCFG_TYPE(UART_RX_WAKE_SCL_MOSI_INTCFG_REG, + UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_MASK, + UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_POS, + UART_INTCFG_TYPE_FALLING_EDGE); + #else + #endif /* (UART_RX_WAKE_SCL_MOSI_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, + UART_TX_SDA_MISO_HSIOM_MASK, + UART_TX_SDA_MISO_HSIOM_POS, + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX]); + + UART_uart_tx_i2c_sda_spi_miso_SetDriveMode((uint8) pinsDm[UART_TX_SDA_MISO_PIN_INDEX]); + + #if (!UART_CY_SCBIP_V1) + UART_SET_INP_DIS(UART_uart_tx_i2c_sda_spi_miso_INP_DIS, + UART_uart_tx_i2c_sda_spi_miso_MASK, + (0u != (pinsInBuf & UART_TX_SDA_MISO_PIN_MASK))); + #endif /* (!UART_CY_SCBIP_V1) */ + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_SCLK_PIN) + UART_SET_HSIOM_SEL(UART_SCLK_HSIOM_REG, + UART_SCLK_HSIOM_MASK, + UART_SCLK_HSIOM_POS, + hsiomSel[UART_SCLK_PIN_INDEX]); + + UART_spi_sclk_SetDriveMode((uint8) pinsDm[UART_SCLK_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_sclk_INP_DIS, + UART_spi_sclk_MASK, + (0u != (pinsInBuf & UART_SCLK_PIN_MASK))); + #endif /* (UART_SCLK_PIN) */ + + #if (UART_SS0_PIN) + UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, + UART_SS0_HSIOM_MASK, + UART_SS0_HSIOM_POS, + hsiomSel[UART_SS0_PIN_INDEX]); + + UART_spi_ss0_SetDriveMode((uint8) pinsDm[UART_SS0_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss0_INP_DIS, + UART_spi_ss0_MASK, + (0u != (pinsInBuf & UART_SS0_PIN_MASK))); + #endif /* (UART_SS0_PIN) */ + + #if (UART_SS1_PIN) + UART_SET_HSIOM_SEL(UART_SS1_HSIOM_REG, + UART_SS1_HSIOM_MASK, + UART_SS1_HSIOM_POS, + hsiomSel[UART_SS1_PIN_INDEX]); + + UART_spi_ss1_SetDriveMode((uint8) pinsDm[UART_SS1_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss1_INP_DIS, + UART_spi_ss1_MASK, + (0u != (pinsInBuf & UART_SS1_PIN_MASK))); + #endif /* (UART_SS1_PIN) */ + + #if (UART_SS2_PIN) + UART_SET_HSIOM_SEL(UART_SS2_HSIOM_REG, + UART_SS2_HSIOM_MASK, + UART_SS2_HSIOM_POS, + hsiomSel[UART_SS2_PIN_INDEX]); + + UART_spi_ss2_SetDriveMode((uint8) pinsDm[UART_SS2_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss2_INP_DIS, + UART_spi_ss2_MASK, + (0u != (pinsInBuf & UART_SS2_PIN_MASK))); + #endif /* (UART_SS2_PIN) */ + + #if (UART_SS3_PIN) + UART_SET_HSIOM_SEL(UART_SS3_HSIOM_REG, + UART_SS3_HSIOM_MASK, + UART_SS3_HSIOM_POS, + hsiomSel[UART_SS3_PIN_INDEX]); + + UART_spi_ss3_SetDriveMode((uint8) pinsDm[UART_SS3_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss3_INP_DIS, + UART_spi_ss3_MASK, + (0u != (pinsInBuf & UART_SS3_PIN_MASK))); + #endif /* (UART_SS3_PIN) */ + } + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UART_I2CSlaveNackGeneration + ****************************************************************************//** + * + * Sets command to generate NACK to the address or data. + * + *******************************************************************************/ + void UART_I2CSlaveNackGeneration(void) + { + /* Check for EC_AM toggle condition: EC_AM and clock stretching for address are enabled */ + if ((0u != (UART_CTRL_REG & UART_CTRL_EC_AM_MODE)) && + (0u == (UART_I2C_CTRL_REG & UART_I2C_CTRL_S_NOT_READY_ADDR_NACK))) + { + /* Toggle EC_AM before NACK generation */ + UART_CTRL_REG &= ~UART_CTRL_EC_AM_MODE; + UART_CTRL_REG |= UART_CTRL_EC_AM_MODE; + } + + UART_I2C_SLAVE_CMD_REG = UART_I2C_SLAVE_CMD_S_NACK; + } +#endif /* (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART.h new file mode 100644 index 0000000..ae88815 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART.h @@ -0,0 +1,2126 @@ +/***************************************************************************//** +* \file UART.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_UART_H) +#define CY_SCB_UART_H + +#include +#include +#include +#include + +/* SCB IP block v0 is available in PSoC 4100/PSoC 4200 */ +#define UART_CY_SCBIP_V0 (CYIPBLOCK_m0s8scb_VERSION == 0u) +/* SCB IP block v1 is available in PSoC 4000 */ +#define UART_CY_SCBIP_V1 (CYIPBLOCK_m0s8scb_VERSION == 1u) +/* SCB IP block v2 is available in all other devices */ +#define UART_CY_SCBIP_V2 (CYIPBLOCK_m0s8scb_VERSION >= 2u) + +/** Component version major.minor */ +#define UART_COMP_VERSION_MAJOR (4) +#define UART_COMP_VERSION_MINOR (0) + +#define UART_SCB_MODE (4u) + +/* SCB modes enum */ +#define UART_SCB_MODE_I2C (0x01u) +#define UART_SCB_MODE_SPI (0x02u) +#define UART_SCB_MODE_UART (0x04u) +#define UART_SCB_MODE_EZI2C (0x08u) +#define UART_SCB_MODE_UNCONFIG (0xFFu) + +/* Condition compilation depends on operation mode: Unconfigured implies apply to all modes */ +#define UART_SCB_MODE_I2C_CONST_CFG (UART_SCB_MODE_I2C == UART_SCB_MODE) +#define UART_SCB_MODE_SPI_CONST_CFG (UART_SCB_MODE_SPI == UART_SCB_MODE) +#define UART_SCB_MODE_UART_CONST_CFG (UART_SCB_MODE_UART == UART_SCB_MODE) +#define UART_SCB_MODE_EZI2C_CONST_CFG (UART_SCB_MODE_EZI2C == UART_SCB_MODE) +#define UART_SCB_MODE_UNCONFIG_CONST_CFG (UART_SCB_MODE_UNCONFIG == UART_SCB_MODE) + +/* Condition compilation for includes */ +#define UART_SCB_MODE_I2C_INC (0u !=(UART_SCB_MODE_I2C & UART_SCB_MODE)) +#define UART_SCB_MODE_EZI2C_INC (0u !=(UART_SCB_MODE_EZI2C & UART_SCB_MODE)) +#if (!UART_CY_SCBIP_V1) + #define UART_SCB_MODE_SPI_INC (0u !=(UART_SCB_MODE_SPI & UART_SCB_MODE)) + #define UART_SCB_MODE_UART_INC (0u !=(UART_SCB_MODE_UART & UART_SCB_MODE)) +#else + #define UART_SCB_MODE_SPI_INC (0u) + #define UART_SCB_MODE_UART_INC (0u) +#endif /* (!UART_CY_SCBIP_V1) */ + +/* Interrupts remove options */ +#define UART_REMOVE_SCB_IRQ (1u) +#define UART_SCB_IRQ_INTERNAL (0u == UART_REMOVE_SCB_IRQ) + +#define UART_REMOVE_UART_RX_WAKEUP_IRQ (1u) +#define UART_UART_RX_WAKEUP_IRQ (0u == UART_REMOVE_UART_RX_WAKEUP_IRQ) + +/* SCB interrupt enum */ +#define UART_SCB_INTR_MODE_NONE (0u) +#define UART_SCB_INTR_MODE_INTERNAL (1u) +#define UART_SCB_INTR_MODE_EXTERNAL (2u) + +/* Internal clock remove option */ +#define UART_REMOVE_SCB_CLK (0u) +#define UART_SCB_CLK_INTERNAL (0u == UART_REMOVE_SCB_CLK) + + +/*************************************** +* Includes +****************************************/ + +#include "UART_PINS.h" + +#if (UART_SCB_CLK_INTERNAL) + #include "UART_SCBCLK.h" +#endif /* (UART_SCB_CLK_INTERNAL) */ + + +/*************************************** +* Type Definitions +***************************************/ + +typedef struct +{ + uint8 enableState; +} UART_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ + +/* Start and Stop APIs */ +void UART_Init(void); +void UART_Enable(void); +void UART_Start(void); +void UART_Stop(void); + +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +/* Sleep and Wakeup APis */ +void UART_Sleep(void); +void UART_Wakeup(void); +/** @} power */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +#if (UART_SCB_IRQ_INTERNAL) + /* Custom interrupt handler */ + void UART_SetCustomInterruptHandler(void (*func)(void)); +#endif /* (UART_SCB_IRQ_INTERNAL) */ +/** @} interrupt */ + +/* Interface to internal interrupt component */ +#if (UART_SCB_IRQ_INTERNAL) + /** + * \addtogroup group_interrupt + * @{ + */ + /******************************************************************************* + * Function Name: UART_EnableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this enables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to enable the interrupt. + * + *******************************************************************************/ + #define UART_EnableInt() CyIntEnable(UART_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_DisableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this disables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to disable the interrupt. + * + *******************************************************************************/ + #define UART_DisableInt() CyIntDisable(UART_ISR_NUMBER) + /** @} interrupt */ + + /******************************************************************************* + * Function Name: UART_ClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt pending status in the NVIC. + * + *******************************************************************************/ + #define UART_ClearPendingInt() CyIntClearPending(UART_ISR_NUMBER) +#endif /* (UART_SCB_IRQ_INTERNAL) */ + +#if (UART_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: UART_RxWakeEnableInt + ****************************************************************************//** + * + * This function enables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_RxWakeEnableInt() CyIntEnable(UART_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_RxWakeDisableInt + ****************************************************************************//** + * + * This function disables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_RxWakeDisableInt() CyIntDisable(UART_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_RxWakeClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_RxWakeClearPendingInt() CyIntClearPending(UART_RX_WAKE_ISR_NUMBER) +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +/* Get interrupt cause */ +/******************************************************************************* +* Function Name: UART_GetInterruptCause +****************************************************************************//** +* +* Returns a mask of bits showing the source of the current triggered interrupt. +* This is useful for modes of operation where an interrupt can be generated by +* conditions in multiple interrupt source registers. +* +* \return +* Mask with the OR of the following conditions that have been triggered. +* - UART_INTR_CAUSE_MASTER - Interrupt from Master +* - UART_INTR_CAUSE_SLAVE - Interrupt from Slave +* - UART_INTR_CAUSE_TX - Interrupt from TX +* - UART_INTR_CAUSE_RX - Interrupt from RX +* +*******************************************************************************/ +#define UART_GetInterruptCause() (UART_INTR_CAUSE_REG) + + +/* APIs to service INTR_RX register */ +/******************************************************************************* +* Function Name: UART_GetRxInterruptSource +****************************************************************************//** +* +* Returns RX interrupt request register. This register contains current status +* of RX interrupt sources. +* +* \return +* Current status of RX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_RX_FIFO_LEVEL - The number of data elements in the + RX FIFO is greater than the value of RX FIFO level. +* - UART_INTR_RX_NOT_EMPTY - Receiver FIFO is not empty. +* - UART_INTR_RX_FULL - Receiver FIFO is full. +* - UART_INTR_RX_OVERFLOW - Attempt to write to a full +* receiver FIFO. +* - UART_INTR_RX_UNDERFLOW - Attempt to read from an empty +* receiver FIFO. +* - UART_INTR_RX_FRAME_ERROR - UART framing error detected. +* - UART_INTR_RX_PARITY_ERROR - UART parity error detected. +* +*******************************************************************************/ +#define UART_GetRxInterruptSource() (UART_INTR_RX_REG) + + +/******************************************************************************* +* Function Name: UART_SetRxInterruptMode +****************************************************************************//** +* +* Writes RX interrupt mask register. This register configures which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: RX interrupt sources to be enabled (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_SetRxInterruptMode(interruptMask) UART_WRITE_INTR_RX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: UART_GetRxInterruptMode +****************************************************************************//** +* +* Returns RX interrupt mask register This register specifies which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \return +* RX interrupt sources to be enabled (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_GetRxInterruptMode() (UART_INTR_RX_MASK_REG) + + +/******************************************************************************* +* Function Name: UART_GetRxInterruptSourceMasked +****************************************************************************//** +* +* Returns RX interrupt masked request register. This register contains logical +* AND of corresponding bits from RX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled RX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled RX interrupt sources (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_GetRxInterruptSourceMasked() (UART_INTR_RX_MASKED_REG) + + +/******************************************************************************* +* Function Name: UART_ClearRxInterruptSource +****************************************************************************//** +* +* Clears RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to be cleared (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +* \sideeffects +* The side effects are listed in the table below for each +* affected interrupt source. Refer to section RX FIFO interrupt sources for +* detailed description. +* - UART_INTR_RX_FIFO_LEVEL Interrupt source is not cleared when +* the receiver FIFO has more entries than level. +* - UART_INTR_RX_NOT_EMPTY Interrupt source is not cleared when +* receiver FIFO is not empty. +* - UART_INTR_RX_FULL Interrupt source is not cleared when +* receiver FIFO is full. +* +*******************************************************************************/ +#define UART_ClearRxInterruptSource(interruptMask) UART_CLEAR_INTR_RX(interruptMask) + + +/******************************************************************************* +* Function Name: UART_SetRxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to UART_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define UART_SetRxInterrupt(interruptMask) UART_SET_INTR_RX(interruptMask) + +void UART_SetRxFifoLevel(uint32 level); + + +/* APIs to service INTR_TX register */ +/******************************************************************************* +* Function Name: UART_GetTxInterruptSource +****************************************************************************//** +* +* Returns TX interrupt request register. This register contains current status +* of TX interrupt sources. +* +* \return +* Current status of TX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_TX_FIFO_LEVEL - The number of data elements in the +* TX FIFO is less than the value of TX FIFO level. +* - UART_INTR_TX_NOT_FULL - Transmitter FIFO is not full. +* - UART_INTR_TX_EMPTY - Transmitter FIFO is empty. +* - UART_INTR_TX_OVERFLOW - Attempt to write to a full +* transmitter FIFO. +* - UART_INTR_TX_UNDERFLOW - Attempt to read from an empty +* transmitter FIFO. +* - UART_INTR_TX_UART_NACK - UART received a NACK in SmartCard +* mode. +* - UART_INTR_TX_UART_DONE - UART transfer is complete. +* All data elements from the TX FIFO are sent. +* - UART_INTR_TX_UART_ARB_LOST - Value on the TX line of the UART +* does not match the value on the RX line. +* +*******************************************************************************/ +#define UART_GetTxInterruptSource() (UART_INTR_TX_REG) + + +/******************************************************************************* +* Function Name: UART_SetTxInterruptMode +****************************************************************************//** +* +* Writes TX interrupt mask register. This register configures which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: TX interrupt sources to be enabled (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_SetTxInterruptMode(interruptMask) UART_WRITE_INTR_TX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: UART_GetTxInterruptMode +****************************************************************************//** +* +* Returns TX interrupt mask register This register specifies which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \return +* Enabled TX interrupt sources (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_GetTxInterruptMode() (UART_INTR_TX_MASK_REG) + + +/******************************************************************************* +* Function Name: UART_GetTxInterruptSourceMasked +****************************************************************************//** +* +* Returns TX interrupt masked request register. This register contains logical +* AND of corresponding bits from TX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to identify +* which of enabled TX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled TX interrupt sources (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_GetTxInterruptSourceMasked() (UART_INTR_TX_MASKED_REG) + + +/******************************************************************************* +* Function Name: UART_ClearTxInterruptSource +****************************************************************************//** +* +* Clears TX interrupt sources in the interrupt request register. +* +* \param interruptMask: TX interrupt sources to be cleared (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +* \sideeffects +* The side effects are listed in the table below for each affected interrupt +* source. Refer to section TX FIFO interrupt sources for detailed description. +* - UART_INTR_TX_FIFO_LEVEL - Interrupt source is not cleared when +* transmitter FIFO has less entries than level. +* - UART_INTR_TX_NOT_FULL - Interrupt source is not cleared when +* transmitter FIFO has empty entries. +* - UART_INTR_TX_EMPTY - Interrupt source is not cleared when +* transmitter FIFO is empty. +* - UART_INTR_TX_UNDERFLOW - Interrupt source is not cleared when +* transmitter FIFO is empty and I2C mode with clock stretching is selected. +* Put data into the transmitter FIFO before clearing it. This behavior only +* applicable for PSoC 4100/PSoC 4200 devices. +* +*******************************************************************************/ +#define UART_ClearTxInterruptSource(interruptMask) UART_CLEAR_INTR_TX(interruptMask) + + +/******************************************************************************* +* Function Name: UART_SetTxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to UART_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define UART_SetTxInterrupt(interruptMask) UART_SET_INTR_TX(interruptMask) + +void UART_SetTxFifoLevel(uint32 level); + + +/* APIs to service INTR_MASTER register */ +/******************************************************************************* +* Function Name: UART_GetMasterInterruptSource +****************************************************************************//** +* +* Returns Master interrupt request register. This register contains current +* status of Master interrupt sources. +* +* \return +* Current status of Master interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_MASTER_SPI_DONE - SPI master transfer is complete. +* Refer to Interrupt sources section for detailed description. +* - UART_INTR_MASTER_I2C_ARB_LOST - I2C master lost arbitration. +* - UART_INTR_MASTER_I2C_NACK - I2C master received negative +* acknowledgement (NAK). +* - UART_INTR_MASTER_I2C_ACK - I2C master received acknowledgement. +* - UART_INTR_MASTER_I2C_STOP - I2C master generated STOP. +* - UART_INTR_MASTER_I2C_BUS_ERROR - I2C master bus error +* (detection of unexpected START or STOP condition). +* +*******************************************************************************/ +#define UART_GetMasterInterruptSource() (UART_INTR_MASTER_REG) + +/******************************************************************************* +* Function Name: UART_SetMasterInterruptMode +****************************************************************************//** +* +* Writes Master interrupt mask register. This register configures which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \param interruptMask: Master interrupt sources to be enabled (refer to +* UART_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_SetMasterInterruptMode(interruptMask) UART_WRITE_INTR_MASTER_MASK(interruptMask) + +/******************************************************************************* +* Function Name: UART_GetMasterInterruptMode +****************************************************************************//** +* +* Returns Master interrupt mask register This register specifies which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \return +* Enabled Master interrupt sources (refer to +* UART_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_GetMasterInterruptMode() (UART_INTR_MASTER_MASK_REG) + +/******************************************************************************* +* Function Name: UART_GetMasterInterruptSourceMasked +****************************************************************************//** +* +* Returns Master interrupt masked request register. This register contains +* logical AND of corresponding bits from Master interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Master interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Master interrupt sources (refer to +* UART_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_GetMasterInterruptSourceMasked() (UART_INTR_MASTER_MASKED_REG) + +/******************************************************************************* +* Function Name: UART_ClearMasterInterruptSource +****************************************************************************//** +* +* Clears Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to be cleared (refer to +* UART_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_ClearMasterInterruptSource(interruptMask) UART_CLEAR_INTR_MASTER(interruptMask) + +/******************************************************************************* +* Function Name: UART_SetMasterInterrupt +****************************************************************************//** +* +* Sets Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to set in the Master interrupt +* request register (refer to UART_GetMasterInterruptSource() +* function for bit field values). +* +*******************************************************************************/ +#define UART_SetMasterInterrupt(interruptMask) UART_SET_INTR_MASTER(interruptMask) + + +/* APIs to service INTR_SLAVE register */ +/******************************************************************************* +* Function Name: UART_GetSlaveInterruptSource +****************************************************************************//** +* +* Returns Slave interrupt request register. This register contains current +* status of Slave interrupt sources. +* +* \return +* Current status of Slave interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_SLAVE_I2C_ARB_LOST - I2C slave lost arbitration: +* the value driven on the SDA line is not the same as the value observed +* on the SDA line. +* - UART_INTR_SLAVE_I2C_NACK - I2C slave received negative +* acknowledgement (NAK). +* - UART_INTR_SLAVE_I2C_ACK - I2C slave received +* acknowledgement (ACK). +* - UART_INTR_SLAVE_I2C_WRITE_STOP - Stop or Repeated Start +* event for write transfer intended for this slave (address matching +* is performed). +* - UART_INTR_SLAVE_I2C_STOP - Stop or Repeated Start event +* for (read or write) transfer intended for this slave (address matching +* is performed). +* - UART_INTR_SLAVE_I2C_START - I2C slave received Start +* condition. +* - UART_INTR_SLAVE_I2C_ADDR_MATCH - I2C slave received matching +* address. +* - UART_INTR_SLAVE_I2C_GENERAL - I2C Slave received general +* call address. +* - UART_INTR_SLAVE_I2C_BUS_ERROR - I2C slave bus error (detection +* of unexpected Start or Stop condition). +* - UART_INTR_SLAVE_SPI_BUS_ERROR - SPI slave select line is +* deselected at an expected time while the SPI transfer. +* +*******************************************************************************/ +#define UART_GetSlaveInterruptSource() (UART_INTR_SLAVE_REG) + +/******************************************************************************* +* Function Name: UART_SetSlaveInterruptMode +****************************************************************************//** +* +* Writes Slave interrupt mask register. +* This register configures which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \param interruptMask: Slave interrupt sources to be enabled (refer to +* UART_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_SetSlaveInterruptMode(interruptMask) UART_WRITE_INTR_SLAVE_MASK(interruptMask) + +/******************************************************************************* +* Function Name: UART_GetSlaveInterruptMode +****************************************************************************//** +* +* Returns Slave interrupt mask register. +* This register specifies which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \return +* Enabled Slave interrupt sources(refer to +* UART_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_GetSlaveInterruptMode() (UART_INTR_SLAVE_MASK_REG) + +/******************************************************************************* +* Function Name: UART_GetSlaveInterruptSourceMasked +****************************************************************************//** +* +* Returns Slave interrupt masked request register. This register contains +* logical AND of corresponding bits from Slave interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Slave interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Slave interrupt sources (refer to +* UART_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_GetSlaveInterruptSourceMasked() (UART_INTR_SLAVE_MASKED_REG) + +/******************************************************************************* +* Function Name: UART_ClearSlaveInterruptSource +****************************************************************************//** +* +* Clears Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to be cleared (refer to +* UART_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_ClearSlaveInterruptSource(interruptMask) UART_CLEAR_INTR_SLAVE(interruptMask) + +/******************************************************************************* +* Function Name: UART_SetSlaveInterrupt +****************************************************************************//** +* +* Sets Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to set in the Slave interrupt +* request register (refer to UART_GetSlaveInterruptSource() +* function for return values). +* +*******************************************************************************/ +#define UART_SetSlaveInterrupt(interruptMask) UART_SET_INTR_SLAVE(interruptMask) + +/** @} interrupt */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +/** +* \addtogroup group_globals +* @{ +*/ + +/** UART_initVar indicates whether the UART +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the UART_Start() routine. +* +* If re-initialization of the component is required, then the +* UART_Init() function can be called before the +* UART_Start() or UART_Enable() function. +*/ +extern uint8 UART_initVar; +/** @} globals */ + +/*************************************** +* Registers +***************************************/ + +#define UART_CTRL_REG (*(reg32 *) UART_SCB__CTRL) +#define UART_CTRL_PTR ( (reg32 *) UART_SCB__CTRL) + +#define UART_STATUS_REG (*(reg32 *) UART_SCB__STATUS) +#define UART_STATUS_PTR ( (reg32 *) UART_SCB__STATUS) + +#if (!UART_CY_SCBIP_V1) + #define UART_SPI_CTRL_REG (*(reg32 *) UART_SCB__SPI_CTRL) + #define UART_SPI_CTRL_PTR ( (reg32 *) UART_SCB__SPI_CTRL) + + #define UART_SPI_STATUS_REG (*(reg32 *) UART_SCB__SPI_STATUS) + #define UART_SPI_STATUS_PTR ( (reg32 *) UART_SCB__SPI_STATUS) + + #define UART_UART_CTRL_REG (*(reg32 *) UART_SCB__UART_CTRL) + #define UART_UART_CTRL_PTR ( (reg32 *) UART_SCB__UART_CTRL) + + #define UART_UART_TX_CTRL_REG (*(reg32 *) UART_SCB__UART_TX_CTRL) + #define UART_UART_TX_CTRL_PTR ( (reg32 *) UART_SCB__UART_TX_CTRL) + + #define UART_UART_RX_CTRL_REG (*(reg32 *) UART_SCB__UART_RX_CTRL) + #define UART_UART_RX_CTRL_PTR ( (reg32 *) UART_SCB__UART_RX_CTRL) + + #define UART_UART_RX_STATUS_REG (*(reg32 *) UART_SCB__UART_RX_STATUS) + #define UART_UART_RX_STATUS_PTR ( (reg32 *) UART_SCB__UART_RX_STATUS) +#endif /* (!UART_CY_SCBIP_V1) */ + +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_UART_FLOW_CTRL_REG (*(reg32 *) UART_SCB__UART_FLOW_CTRL) + #define UART_UART_FLOW_CTRL_PTR ( (reg32 *) UART_SCB__UART_FLOW_CTRL) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#define UART_I2C_CTRL_REG (*(reg32 *) UART_SCB__I2C_CTRL) +#define UART_I2C_CTRL_PTR ( (reg32 *) UART_SCB__I2C_CTRL) + +#define UART_I2C_STATUS_REG (*(reg32 *) UART_SCB__I2C_STATUS) +#define UART_I2C_STATUS_PTR ( (reg32 *) UART_SCB__I2C_STATUS) + +#define UART_I2C_MASTER_CMD_REG (*(reg32 *) UART_SCB__I2C_M_CMD) +#define UART_I2C_MASTER_CMD_PTR ( (reg32 *) UART_SCB__I2C_M_CMD) + +#define UART_I2C_SLAVE_CMD_REG (*(reg32 *) UART_SCB__I2C_S_CMD) +#define UART_I2C_SLAVE_CMD_PTR ( (reg32 *) UART_SCB__I2C_S_CMD) + +#define UART_I2C_CFG_REG (*(reg32 *) UART_SCB__I2C_CFG) +#define UART_I2C_CFG_PTR ( (reg32 *) UART_SCB__I2C_CFG) + +#define UART_TX_CTRL_REG (*(reg32 *) UART_SCB__TX_CTRL) +#define UART_TX_CTRL_PTR ( (reg32 *) UART_SCB__TX_CTRL) + +#define UART_TX_FIFO_CTRL_REG (*(reg32 *) UART_SCB__TX_FIFO_CTRL) +#define UART_TX_FIFO_CTRL_PTR ( (reg32 *) UART_SCB__TX_FIFO_CTRL) + +#define UART_TX_FIFO_STATUS_REG (*(reg32 *) UART_SCB__TX_FIFO_STATUS) +#define UART_TX_FIFO_STATUS_PTR ( (reg32 *) UART_SCB__TX_FIFO_STATUS) + +#define UART_TX_FIFO_WR_REG (*(reg32 *) UART_SCB__TX_FIFO_WR) +#define UART_TX_FIFO_WR_PTR ( (reg32 *) UART_SCB__TX_FIFO_WR) + +#define UART_RX_CTRL_REG (*(reg32 *) UART_SCB__RX_CTRL) +#define UART_RX_CTRL_PTR ( (reg32 *) UART_SCB__RX_CTRL) + +#define UART_RX_FIFO_CTRL_REG (*(reg32 *) UART_SCB__RX_FIFO_CTRL) +#define UART_RX_FIFO_CTRL_PTR ( (reg32 *) UART_SCB__RX_FIFO_CTRL) + +#define UART_RX_FIFO_STATUS_REG (*(reg32 *) UART_SCB__RX_FIFO_STATUS) +#define UART_RX_FIFO_STATUS_PTR ( (reg32 *) UART_SCB__RX_FIFO_STATUS) + +#define UART_RX_MATCH_REG (*(reg32 *) UART_SCB__RX_MATCH) +#define UART_RX_MATCH_PTR ( (reg32 *) UART_SCB__RX_MATCH) + +#define UART_RX_FIFO_RD_REG (*(reg32 *) UART_SCB__RX_FIFO_RD) +#define UART_RX_FIFO_RD_PTR ( (reg32 *) UART_SCB__RX_FIFO_RD) + +#define UART_RX_FIFO_RD_SILENT_REG (*(reg32 *) UART_SCB__RX_FIFO_RD_SILENT) +#define UART_RX_FIFO_RD_SILENT_PTR ( (reg32 *) UART_SCB__RX_FIFO_RD_SILENT) + +#ifdef UART_SCB__EZ_DATA0 + #define UART_EZBUF_DATA0_REG (*(reg32 *) UART_SCB__EZ_DATA0) + #define UART_EZBUF_DATA0_PTR ( (reg32 *) UART_SCB__EZ_DATA0) +#else + #define UART_EZBUF_DATA0_REG (*(reg32 *) UART_SCB__EZ_DATA00) + #define UART_EZBUF_DATA0_PTR ( (reg32 *) UART_SCB__EZ_DATA00) +#endif /* UART_SCB__EZ_DATA00 */ + +#define UART_INTR_CAUSE_REG (*(reg32 *) UART_SCB__INTR_CAUSE) +#define UART_INTR_CAUSE_PTR ( (reg32 *) UART_SCB__INTR_CAUSE) + +#define UART_INTR_I2C_EC_REG (*(reg32 *) UART_SCB__INTR_I2C_EC) +#define UART_INTR_I2C_EC_PTR ( (reg32 *) UART_SCB__INTR_I2C_EC) + +#define UART_INTR_I2C_EC_MASK_REG (*(reg32 *) UART_SCB__INTR_I2C_EC_MASK) +#define UART_INTR_I2C_EC_MASK_PTR ( (reg32 *) UART_SCB__INTR_I2C_EC_MASK) + +#define UART_INTR_I2C_EC_MASKED_REG (*(reg32 *) UART_SCB__INTR_I2C_EC_MASKED) +#define UART_INTR_I2C_EC_MASKED_PTR ( (reg32 *) UART_SCB__INTR_I2C_EC_MASKED) + +#if (!UART_CY_SCBIP_V1) + #define UART_INTR_SPI_EC_REG (*(reg32 *) UART_SCB__INTR_SPI_EC) + #define UART_INTR_SPI_EC_PTR ( (reg32 *) UART_SCB__INTR_SPI_EC) + + #define UART_INTR_SPI_EC_MASK_REG (*(reg32 *) UART_SCB__INTR_SPI_EC_MASK) + #define UART_INTR_SPI_EC_MASK_PTR ( (reg32 *) UART_SCB__INTR_SPI_EC_MASK) + + #define UART_INTR_SPI_EC_MASKED_REG (*(reg32 *) UART_SCB__INTR_SPI_EC_MASKED) + #define UART_INTR_SPI_EC_MASKED_PTR ( (reg32 *) UART_SCB__INTR_SPI_EC_MASKED) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_INTR_MASTER_REG (*(reg32 *) UART_SCB__INTR_M) +#define UART_INTR_MASTER_PTR ( (reg32 *) UART_SCB__INTR_M) + +#define UART_INTR_MASTER_SET_REG (*(reg32 *) UART_SCB__INTR_M_SET) +#define UART_INTR_MASTER_SET_PTR ( (reg32 *) UART_SCB__INTR_M_SET) + +#define UART_INTR_MASTER_MASK_REG (*(reg32 *) UART_SCB__INTR_M_MASK) +#define UART_INTR_MASTER_MASK_PTR ( (reg32 *) UART_SCB__INTR_M_MASK) + +#define UART_INTR_MASTER_MASKED_REG (*(reg32 *) UART_SCB__INTR_M_MASKED) +#define UART_INTR_MASTER_MASKED_PTR ( (reg32 *) UART_SCB__INTR_M_MASKED) + +#define UART_INTR_SLAVE_REG (*(reg32 *) UART_SCB__INTR_S) +#define UART_INTR_SLAVE_PTR ( (reg32 *) UART_SCB__INTR_S) + +#define UART_INTR_SLAVE_SET_REG (*(reg32 *) UART_SCB__INTR_S_SET) +#define UART_INTR_SLAVE_SET_PTR ( (reg32 *) UART_SCB__INTR_S_SET) + +#define UART_INTR_SLAVE_MASK_REG (*(reg32 *) UART_SCB__INTR_S_MASK) +#define UART_INTR_SLAVE_MASK_PTR ( (reg32 *) UART_SCB__INTR_S_MASK) + +#define UART_INTR_SLAVE_MASKED_REG (*(reg32 *) UART_SCB__INTR_S_MASKED) +#define UART_INTR_SLAVE_MASKED_PTR ( (reg32 *) UART_SCB__INTR_S_MASKED) + +#define UART_INTR_TX_REG (*(reg32 *) UART_SCB__INTR_TX) +#define UART_INTR_TX_PTR ( (reg32 *) UART_SCB__INTR_TX) + +#define UART_INTR_TX_SET_REG (*(reg32 *) UART_SCB__INTR_TX_SET) +#define UART_INTR_TX_SET_PTR ( (reg32 *) UART_SCB__INTR_TX_SET) + +#define UART_INTR_TX_MASK_REG (*(reg32 *) UART_SCB__INTR_TX_MASK) +#define UART_INTR_TX_MASK_PTR ( (reg32 *) UART_SCB__INTR_TX_MASK) + +#define UART_INTR_TX_MASKED_REG (*(reg32 *) UART_SCB__INTR_TX_MASKED) +#define UART_INTR_TX_MASKED_PTR ( (reg32 *) UART_SCB__INTR_TX_MASKED) + +#define UART_INTR_RX_REG (*(reg32 *) UART_SCB__INTR_RX) +#define UART_INTR_RX_PTR ( (reg32 *) UART_SCB__INTR_RX) + +#define UART_INTR_RX_SET_REG (*(reg32 *) UART_SCB__INTR_RX_SET) +#define UART_INTR_RX_SET_PTR ( (reg32 *) UART_SCB__INTR_RX_SET) + +#define UART_INTR_RX_MASK_REG (*(reg32 *) UART_SCB__INTR_RX_MASK) +#define UART_INTR_RX_MASK_PTR ( (reg32 *) UART_SCB__INTR_RX_MASK) + +#define UART_INTR_RX_MASKED_REG (*(reg32 *) UART_SCB__INTR_RX_MASKED) +#define UART_INTR_RX_MASKED_PTR ( (reg32 *) UART_SCB__INTR_RX_MASKED) + +/* Defines get from SCB IP parameters. */ +#define UART_FIFO_SIZE (8u) /* TX or RX FIFO size. */ +#define UART_EZ_DATA_NR (32u) /* Number of words in EZ memory. */ +#define UART_ONE_BYTE_WIDTH (8u) /* Number of bits in one byte. */ +#define UART_FF_DATA_NR_LOG2_MASK (0x07u) /* Number of bits to represent a FIFO address. */ +#define UART_FF_DATA_NR_LOG2_PLUS1_MASK (0x0Fu) /* Number of bits to represent #bytes in FIFO. */ + + +/*************************************** +* Registers Constants +***************************************/ + +#if (UART_SCB_IRQ_INTERNAL) + #define UART_ISR_NUMBER ((uint8) UART_SCB_IRQ__INTC_NUMBER) + #define UART_ISR_PRIORITY ((uint8) UART_SCB_IRQ__INTC_PRIOR_NUM) +#endif /* (UART_SCB_IRQ_INTERNAL) */ + +#if (UART_UART_RX_WAKEUP_IRQ) + #define UART_RX_WAKE_ISR_NUMBER ((uint8) UART_RX_WAKEUP_IRQ__INTC_NUMBER) + #define UART_RX_WAKE_ISR_PRIORITY ((uint8) UART_RX_WAKEUP_IRQ__INTC_PRIOR_NUM) +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + +/* UART_CTRL_REG */ +#define UART_CTRL_OVS_POS (0u) /* [3:0] Oversampling factor */ +#define UART_CTRL_EC_AM_MODE_POS (8u) /* [8] Externally clocked address match */ +#define UART_CTRL_EC_OP_MODE_POS (9u) /* [9] Externally clocked operation mode */ +#define UART_CTRL_EZBUF_MODE_POS (10u) /* [10] EZ buffer is enabled */ +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_CTRL_BYTE_MODE_POS (11u) /* [11] Determines the number of bits per FIFO data element */ +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#define UART_CTRL_ADDR_ACCEPT_POS (16u) /* [16] Put matched address in RX FIFO */ +#define UART_CTRL_BLOCK_POS (17u) /* [17] Ext and Int logic to resolve collide */ +#define UART_CTRL_MODE_POS (24u) /* [25:24] Operation mode */ +#define UART_CTRL_ENABLED_POS (31u) /* [31] Enable SCB block */ +#define UART_CTRL_OVS_MASK ((uint32) 0x0Fu) +#define UART_CTRL_EC_AM_MODE ((uint32) 0x01u << UART_CTRL_EC_AM_MODE_POS) +#define UART_CTRL_EC_OP_MODE ((uint32) 0x01u << UART_CTRL_EC_OP_MODE_POS) +#define UART_CTRL_EZBUF_MODE ((uint32) 0x01u << UART_CTRL_EZBUF_MODE_POS) +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_CTRL_BYTE_MODE ((uint32) 0x01u << UART_CTRL_BYTE_MODE_POS) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#define UART_CTRL_ADDR_ACCEPT ((uint32) 0x01u << UART_CTRL_ADDR_ACCEPT_POS) +#define UART_CTRL_BLOCK ((uint32) 0x01u << UART_CTRL_BLOCK_POS) +#define UART_CTRL_MODE_MASK ((uint32) 0x03u << UART_CTRL_MODE_POS) +#define UART_CTRL_MODE_I2C ((uint32) 0x00u) +#define UART_CTRL_MODE_SPI ((uint32) 0x01u << UART_CTRL_MODE_POS) +#define UART_CTRL_MODE_UART ((uint32) 0x02u << UART_CTRL_MODE_POS) +#define UART_CTRL_ENABLED ((uint32) 0x01u << UART_CTRL_ENABLED_POS) + +/* UART_STATUS_REG */ +#define UART_STATUS_EC_BUSY_POS (0u) /* [0] Bus busy. Externally clocked logic access to EZ memory */ +#define UART_STATUS_EC_BUSY ((uint32) 0x0Fu) + +/* UART_SPI_CTRL_REG */ +#define UART_SPI_CTRL_CONTINUOUS_POS (0u) /* [0] Continuous or Separated SPI data transfers */ +#define UART_SPI_CTRL_SELECT_PRECEDE_POS (1u) /* [1] Precedes or coincides start of data frame */ +#define UART_SPI_CTRL_CPHA_POS (2u) /* [2] SCLK phase */ +#define UART_SPI_CTRL_CPOL_POS (3u) /* [3] SCLK polarity */ +#define UART_SPI_CTRL_LATE_MISO_SAMPLE_POS (4u) /* [4] Late MISO sample enabled */ +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_SPI_CTRL_SCLK_CONTINUOUS_POS (5u) /* [5] Enable continuous SCLK generation */ + #define UART_SPI_CTRL_SSEL0_POLARITY_POS (8u) /* [8] SS0 polarity */ + #define UART_SPI_CTRL_SSEL1_POLARITY_POS (9u) /* [9] SS1 polarity */ + #define UART_SPI_CTRL_SSEL2_POLARITY_POS (10u) /* [10] SS2 polarity */ + #define UART_SPI_CTRL_SSEL3_POLARITY_POS (11u) /* [11] SS3 polarity */ +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#define UART_SPI_CTRL_LOOPBACK_POS (16u) /* [16] Local loop-back control enabled */ +#define UART_SPI_CTRL_MODE_POS (24u) /* [25:24] Submode of SPI operation */ +#define UART_SPI_CTRL_SLAVE_SELECT_POS (26u) /* [27:26] Selects SPI SS signal */ +#define UART_SPI_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define UART_SPI_CTRL_CONTINUOUS ((uint32) 0x01u) +#define UART_SPI_CTRL_SELECT_PRECEDE ((uint32) 0x01u << UART_SPI_CTRL_SELECT_PRECEDE_POS) +#define UART_SPI_CTRL_SCLK_MODE_MASK ((uint32) 0x03u << UART_SPI_CTRL_CPHA_POS) +#define UART_SPI_CTRL_CPHA ((uint32) 0x01u << UART_SPI_CTRL_CPHA_POS) +#define UART_SPI_CTRL_CPOL ((uint32) 0x01u << UART_SPI_CTRL_CPOL_POS) +#define UART_SPI_CTRL_LATE_MISO_SAMPLE ((uint32) 0x01u << \ + UART_SPI_CTRL_LATE_MISO_SAMPLE_POS) +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_SPI_CTRL_SCLK_CONTINUOUS ((uint32) 0x01u << UART_SPI_CTRL_SCLK_CONTINUOUS_POS) + #define UART_SPI_CTRL_SSEL0_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL0_POLARITY_POS) + #define UART_SPI_CTRL_SSEL1_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL1_POLARITY_POS) + #define UART_SPI_CTRL_SSEL2_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL2_POLARITY_POS) + #define UART_SPI_CTRL_SSEL3_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL3_POLARITY_POS) + #define UART_SPI_CTRL_SSEL_POLARITY_MASK ((uint32)0x0Fu << UART_SPI_CTRL_SSEL0_POLARITY_POS) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#define UART_SPI_CTRL_LOOPBACK ((uint32) 0x01u << UART_SPI_CTRL_LOOPBACK_POS) +#define UART_SPI_CTRL_MODE_MASK ((uint32) 0x03u << UART_SPI_CTRL_MODE_POS) +#define UART_SPI_CTRL_MODE_MOTOROLA ((uint32) 0x00u) +#define UART_SPI_CTRL_MODE_TI ((uint32) 0x01u << UART_CTRL_MODE_POS) +#define UART_SPI_CTRL_MODE_NS ((uint32) 0x02u << UART_CTRL_MODE_POS) +#define UART_SPI_CTRL_SLAVE_SELECT_MASK ((uint32) 0x03u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_SLAVE_SELECT0 ((uint32) 0x00u) +#define UART_SPI_CTRL_SLAVE_SELECT1 ((uint32) 0x01u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_SLAVE_SELECT2 ((uint32) 0x02u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_SLAVE_SELECT3 ((uint32) 0x03u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_MASTER ((uint32) 0x01u << UART_SPI_CTRL_MASTER_MODE_POS) +#define UART_SPI_CTRL_SLAVE ((uint32) 0x00u) + +/* UART_SPI_STATUS_REG */ +#define UART_SPI_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy - slave selected */ +#define UART_SPI_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EzAddress */ +#define UART_SPI_STATUS_BUS_BUSY ((uint32) 0x01u) +#define UART_SPI_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << UART_I2C_STATUS_EZBUF_ADDR_POS) + +/* UART_UART_CTRL */ +#define UART_UART_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define UART_UART_CTRL_MODE_POS (24u) /* [24] UART subMode */ +#define UART_UART_CTRL_LOOPBACK ((uint32) 0x01u << UART_UART_CTRL_LOOPBACK_POS) +#define UART_UART_CTRL_MODE_UART_STD ((uint32) 0x00u) +#define UART_UART_CTRL_MODE_UART_SMARTCARD ((uint32) 0x01u << UART_UART_CTRL_MODE_POS) +#define UART_UART_CTRL_MODE_UART_IRDA ((uint32) 0x02u << UART_UART_CTRL_MODE_POS) +#define UART_UART_CTRL_MODE_MASK ((uint32) 0x03u << UART_UART_CTRL_MODE_POS) + +/* UART_UART_TX_CTRL */ +#define UART_UART_TX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period */ +#define UART_UART_TX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define UART_UART_TX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define UART_UART_TX_CTRL_RETRY_ON_NACK_POS (8u) /* [8] Smart Card: re-send frame on NACK */ +#define UART_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define UART_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define UART_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define UART_UART_TX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define UART_UART_TX_CTRL_PARITY ((uint32) 0x01u << \ + UART_UART_TX_CTRL_PARITY_POS) +#define UART_UART_TX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + UART_UART_TX_CTRL_PARITY_ENABLED_POS) +#define UART_UART_TX_CTRL_RETRY_ON_NACK ((uint32) 0x01u << \ + UART_UART_TX_CTRL_RETRY_ON_NACK_POS) + +/* UART_UART_RX_CTRL */ +#define UART_UART_RX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period*/ +#define UART_UART_RX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define UART_UART_RX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define UART_UART_RX_CTRL_POLARITY_POS (6u) /* [6] IrDA: inverts polarity of RX signal */ +#define UART_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS (8u) /* [8] Drop and lost RX FIFO on parity error */ +#define UART_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS (9u) /* [9] Drop and lost RX FIFO on frame error */ +#define UART_UART_RX_CTRL_MP_MODE_POS (10u) /* [10] Multi-processor mode */ +#define UART_UART_RX_CTRL_LIN_MODE_POS (12u) /* [12] Lin mode: applicable for UART Standard */ +#define UART_UART_RX_CTRL_SKIP_START_POS (13u) /* [13] Skip start not: only for UART Standard */ +#define UART_UART_RX_CTRL_BREAK_WIDTH_POS (16u) /* [19:16] Break width: (Break width + 1) */ +#define UART_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define UART_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define UART_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define UART_UART_RX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define UART_UART_RX_CTRL_PARITY ((uint32) 0x01u << \ + UART_UART_RX_CTRL_PARITY_POS) +#define UART_UART_RX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + UART_UART_RX_CTRL_PARITY_ENABLED_POS) +#define UART_UART_RX_CTRL_POLARITY ((uint32) 0x01u << \ + UART_UART_RX_CTRL_POLARITY_POS) +#define UART_UART_RX_CTRL_DROP_ON_PARITY_ERR ((uint32) 0x01u << \ + UART_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS) +#define UART_UART_RX_CTRL_DROP_ON_FRAME_ERR ((uint32) 0x01u << \ + UART_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS) +#define UART_UART_RX_CTRL_MP_MODE ((uint32) 0x01u << \ + UART_UART_RX_CTRL_MP_MODE_POS) +#define UART_UART_RX_CTRL_LIN_MODE ((uint32) 0x01u << \ + UART_UART_RX_CTRL_LIN_MODE_POS) +#define UART_UART_RX_CTRL_SKIP_START ((uint32) 0x01u << \ + UART_UART_RX_CTRL_SKIP_START_POS) +#define UART_UART_RX_CTRL_BREAK_WIDTH_MASK ((uint32) 0x0Fu << \ + UART_UART_RX_CTRL_BREAK_WIDTH_POS) +/* UART_UART_RX_STATUS_REG */ +#define UART_UART_RX_STATUS_BR_COUNTER_POS (0u) /* [11:0] Baud Rate counter */ +#define UART_UART_RX_STATUS_BR_COUNTER_MASK ((uint32) 0xFFFu) + +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* UART_UART_FLOW_CTRL_REG */ + #define UART_UART_FLOW_CTRL_TRIGGER_LEVEL_POS (0u) /* [7:0] RTS RX FIFO trigger level */ + #define UART_UART_FLOW_CTRL_RTS_POLARITY_POS (16u) /* [16] Polarity of the RTS output signal */ + #define UART_UART_FLOW_CTRL_CTS_POLARITY_POS (24u) /* [24] Polarity of the CTS input signal */ + #define UART_UART_FLOW_CTRL_CTS_ENABLED_POS (25u) /* [25] Enable CTS signal */ + #define UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK) + #define UART_UART_FLOW_CTRL_RTS_POLARITY ((uint32) 0x01u << \ + UART_UART_FLOW_CTRL_RTS_POLARITY_POS) + #define UART_UART_FLOW_CTRL_CTS_POLARITY ((uint32) 0x01u << \ + UART_UART_FLOW_CTRL_CTS_POLARITY_POS) + #define UART_UART_FLOW_CTRL_CTS_ENABLE ((uint32) 0x01u << \ + UART_UART_FLOW_CTRL_CTS_ENABLED_POS) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +/* UART_I2C_CTRL */ +#define UART_I2C_CTRL_HIGH_PHASE_OVS_POS (0u) /* [3:0] Oversampling factor high: master only */ +#define UART_I2C_CTRL_LOW_PHASE_OVS_POS (4u) /* [7:4] Oversampling factor low: master only */ +#define UART_I2C_CTRL_M_READY_DATA_ACK_POS (8u) /* [8] Master ACKs data while RX FIFO != FULL*/ +#define UART_I2C_CTRL_M_NOT_READY_DATA_NACK_POS (9u) /* [9] Master NACKs data if RX FIFO == FULL */ +#define UART_I2C_CTRL_S_GENERAL_IGNORE_POS (11u) /* [11] Slave ignores General call */ +#define UART_I2C_CTRL_S_READY_ADDR_ACK_POS (12u) /* [12] Slave ACKs Address if RX FIFO != FULL */ +#define UART_I2C_CTRL_S_READY_DATA_ACK_POS (13u) /* [13] Slave ACKs data while RX FIFO == FULL */ +#define UART_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS (14u) /* [14] Slave NACKs address if RX FIFO == FULL*/ +#define UART_I2C_CTRL_S_NOT_READY_DATA_NACK_POS (15u) /* [15] Slave NACKs data if RX FIFO is FULL */ +#define UART_I2C_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define UART_I2C_CTRL_SLAVE_MODE_POS (30u) /* [30] Slave mode enabled */ +#define UART_I2C_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define UART_I2C_CTRL_HIGH_PHASE_OVS_MASK ((uint32) 0x0Fu) +#define UART_I2C_CTRL_LOW_PHASE_OVS_MASK ((uint32) 0x0Fu << \ + UART_I2C_CTRL_LOW_PHASE_OVS_POS) +#define UART_I2C_CTRL_M_READY_DATA_ACK ((uint32) 0x01u << \ + UART_I2C_CTRL_M_READY_DATA_ACK_POS) +#define UART_I2C_CTRL_M_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + UART_I2C_CTRL_M_NOT_READY_DATA_NACK_POS) +#define UART_I2C_CTRL_S_GENERAL_IGNORE ((uint32) 0x01u << \ + UART_I2C_CTRL_S_GENERAL_IGNORE_POS) +#define UART_I2C_CTRL_S_READY_ADDR_ACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_READY_ADDR_ACK_POS) +#define UART_I2C_CTRL_S_READY_DATA_ACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_READY_DATA_ACK_POS) +#define UART_I2C_CTRL_S_NOT_READY_ADDR_NACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS) +#define UART_I2C_CTRL_S_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK_POS) +#define UART_I2C_CTRL_LOOPBACK ((uint32) 0x01u << \ + UART_I2C_CTRL_LOOPBACK_POS) +#define UART_I2C_CTRL_SLAVE_MODE ((uint32) 0x01u << \ + UART_I2C_CTRL_SLAVE_MODE_POS) +#define UART_I2C_CTRL_MASTER_MODE ((uint32) 0x01u << \ + UART_I2C_CTRL_MASTER_MODE_POS) +#define UART_I2C_CTRL_SLAVE_MASTER_MODE_MASK ((uint32) 0x03u << \ + UART_I2C_CTRL_SLAVE_MODE_POS) + +/* UART_I2C_STATUS_REG */ +#define UART_I2C_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy: internally clocked */ +#define UART_I2C_STATUS_S_READ_POS (4u) /* [4] Slave is read by master */ +#define UART_I2C_STATUS_M_READ_POS (5u) /* [5] Master reads Slave */ +#define UART_I2C_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EZAddress */ +#define UART_I2C_STATUS_BUS_BUSY ((uint32) 0x01u) +#define UART_I2C_STATUS_S_READ ((uint32) 0x01u << UART_I2C_STATUS_S_READ_POS) +#define UART_I2C_STATUS_M_READ ((uint32) 0x01u << UART_I2C_STATUS_M_READ_POS) +#define UART_I2C_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << UART_I2C_STATUS_EZBUF_ADDR_POS) + +/* UART_I2C_MASTER_CMD_REG */ +#define UART_I2C_MASTER_CMD_M_START_POS (0u) /* [0] Master generate Start */ +#define UART_I2C_MASTER_CMD_M_START_ON_IDLE_POS (1u) /* [1] Master generate Start if bus is free */ +#define UART_I2C_MASTER_CMD_M_ACK_POS (2u) /* [2] Master generate ACK */ +#define UART_I2C_MASTER_CMD_M_NACK_POS (3u) /* [3] Master generate NACK */ +#define UART_I2C_MASTER_CMD_M_STOP_POS (4u) /* [4] Master generate Stop */ +#define UART_I2C_MASTER_CMD_M_START ((uint32) 0x01u) +#define UART_I2C_MASTER_CMD_M_START_ON_IDLE ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_START_ON_IDLE_POS) +#define UART_I2C_MASTER_CMD_M_ACK ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_ACK_POS) +#define UART_I2C_MASTER_CMD_M_NACK ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_NACK_POS) +#define UART_I2C_MASTER_CMD_M_STOP ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_STOP_POS) + +/* UART_I2C_SLAVE_CMD_REG */ +#define UART_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define UART_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define UART_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define UART_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << UART_I2C_SLAVE_CMD_S_NACK_POS) + +#define UART_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define UART_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define UART_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define UART_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << UART_I2C_SLAVE_CMD_S_NACK_POS) + +/* UART_I2C_CFG_REG */ +#if (UART_CY_SCBIP_V0) +#define UART_I2C_CFG_SDA_FILT_HYS_POS (0u) /* [1:0] Trim bits for the I2C SDA filter */ +#define UART_I2C_CFG_SDA_FILT_TRIM_POS (2u) /* [3:2] Trim bits for the I2C SDA filter */ +#define UART_I2C_CFG_SCL_FILT_HYS_POS (4u) /* [5:4] Trim bits for the I2C SCL filter */ +#define UART_I2C_CFG_SCL_FILT_TRIM_POS (6u) /* [7:6] Trim bits for the I2C SCL filter */ +#define UART_I2C_CFG_SDA_FILT_OUT_HYS_POS (8u) /* [9:8] Trim bits for I2C SDA filter output path */ +#define UART_I2C_CFG_SDA_FILT_OUT_TRIM_POS (10u) /* [11:10] Trim bits for I2C SDA filter output path */ +#define UART_I2C_CFG_SDA_FILT_HS_POS (16u) /* [16] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_I2C_CFG_SDA_FILT_ENABLED_POS (17u) /* [17] I2C SDA filter enabled */ +#define UART_I2C_CFG_SCL_FILT_HS_POS (24u) /* [24] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_I2C_CFG_SCL_FILT_ENABLED_POS (25u) /* [25] I2C SCL filter enabled */ +#define UART_I2C_CFG_SDA_FILT_OUT_HS_POS (26u) /* [26] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_I2C_CFG_SDA_FILT_OUT_ENABLED_POS (27u) /* [27] I2C SDA output delay filter enabled */ +#define UART_I2C_CFG_SDA_FILT_HYS_MASK ((uint32) 0x03u) +#define UART_I2C_CFG_SDA_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_FILT_TRIM_POS) +#define UART_I2C_CFG_SCL_FILT_HYS_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SCL_FILT_HYS_POS) +#define UART_I2C_CFG_SCL_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SCL_FILT_TRIM_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_HYS_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_FILT_OUT_HYS_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_FILT_OUT_TRIM_POS) +#define UART_I2C_CFG_SDA_FILT_HS ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_HS_POS) +#define UART_I2C_CFG_SDA_FILT_ENABLED ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_ENABLED_POS) +#define UART_I2C_CFG_SCL_FILT_HS ((uint32) 0x01u << \ + UART_I2C_CFG_SCL_FILT_HS_POS) +#define UART_I2C_CFG_SCL_FILT_ENABLED ((uint32) 0x01u << \ + UART_I2C_CFG_SCL_FILT_ENABLED_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_HS ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_OUT_HS_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_ENABLED ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_OUT_ENABLED_POS) +#else +#define UART_I2C_CFG_SDA_IN_FILT_TRIM_POS (0u) /* [1:0] Trim bits for "i2c_sda_in" 50 ns filter */ +#define UART_I2C_CFG_SDA_IN_FILT_SEL_POS (4u) /* [4] "i2c_sda_in" filter delay: 0 ns and 50 ns */ +#define UART_I2C_CFG_SCL_IN_FILT_TRIM_POS (8u) /* [9:8] Trim bits for "i2c_scl_in" 50 ns filter */ +#define UART_I2C_CFG_SCL_IN_FILT_SEL_POS (12u) /* [12] "i2c_scl_in" filter delay: 0 ns and 50 ns */ +#define UART_I2C_CFG_SDA_OUT_FILT0_TRIM_POS (16u) /* [17:16] Trim bits for "i2c_sda_out" 50 ns filter 0 */ +#define UART_I2C_CFG_SDA_OUT_FILT1_TRIM_POS (18u) /* [19:18] Trim bits for "i2c_sda_out" 50 ns filter 1 */ +#define UART_I2C_CFG_SDA_OUT_FILT2_TRIM_POS (20u) /* [21:20] Trim bits for "i2c_sda_out" 50 ns filter 2 */ +#define UART_I2C_CFG_SDA_OUT_FILT_SEL_POS (28u) /* [29:28] Cumulative "i2c_sda_out" filter delay: */ + +#define UART_I2C_CFG_SDA_IN_FILT_TRIM_MASK ((uint32) 0x03u) +#define UART_I2C_CFG_SDA_IN_FILT_SEL ((uint32) 0x01u << UART_I2C_CFG_SDA_IN_FILT_SEL_POS) +#define UART_I2C_CFG_SCL_IN_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SCL_IN_FILT_TRIM_POS) +#define UART_I2C_CFG_SCL_IN_FILT_SEL ((uint32) 0x01u << UART_I2C_CFG_SCL_IN_FILT_SEL_POS) +#define UART_I2C_CFG_SDA_OUT_FILT0_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT0_TRIM_POS) +#define UART_I2C_CFG_SDA_OUT_FILT1_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT1_TRIM_POS) +#define UART_I2C_CFG_SDA_OUT_FILT2_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT2_TRIM_POS) +#define UART_I2C_CFG_SDA_OUT_FILT_SEL_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT_SEL_POS) +#endif /* (UART_CY_SCBIP_V0) */ + + +/* UART_TX_CTRL_REG */ +#define UART_TX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define UART_TX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define UART_TX_CTRL_ENABLED_POS (31u) /* [31] Transmitter enabled */ +#define UART_TX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define UART_TX_CTRL_MSB_FIRST ((uint32) 0x01u << UART_TX_CTRL_MSB_FIRST_POS) +#define UART_TX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define UART_TX_CTRL_ENABLED ((uint32) 0x01u << UART_TX_CTRL_ENABLED_POS) + +/* UART_TX_CTRL_FIFO_REG */ +#define UART_TX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define UART_TX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear TX FIFO: cleared after set */ +#define UART_TX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze TX FIFO: HW do not inc read pointer */ +#define UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK) +#define UART_TX_FIFO_CTRL_CLEAR ((uint32) 0x01u << UART_TX_FIFO_CTRL_CLEAR_POS) +#define UART_TX_FIFO_CTRL_FREEZE ((uint32) 0x01u << UART_TX_FIFO_CTRL_FREEZE_POS) + +/* UART_TX_FIFO_STATUS_REG */ +#define UART_TX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in TX FIFO */ +#define UART_TX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of TX FIFO */ +#define UART_TX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] TX FIFO read pointer */ +#define UART_TX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] TX FIFO write pointer */ +#define UART_TX_FIFO_STATUS_USED_MASK ((uint32) UART_FF_DATA_NR_LOG2_PLUS1_MASK) +#define UART_TX_FIFO_SR_VALID ((uint32) 0x01u << UART_TX_FIFO_SR_VALID_POS) +#define UART_TX_FIFO_STATUS_RD_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_TX_FIFO_STATUS_RD_PTR_POS) +#define UART_TX_FIFO_STATUS_WR_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_TX_FIFO_STATUS_WR_PTR_POS) + +/* UART_TX_FIFO_WR_REG */ +#define UART_TX_FIFO_WR_POS (0u) /* [15:0] Data written into TX FIFO */ +#define UART_TX_FIFO_WR_MASK ((uint32) 0xFFu) + +/* UART_RX_CTRL_REG */ +#define UART_RX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define UART_RX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define UART_RX_CTRL_MEDIAN_POS (9u) /* [9] Median filter */ +#define UART_RX_CTRL_ENABLED_POS (31u) /* [31] Receiver enabled */ +#define UART_RX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define UART_RX_CTRL_MSB_FIRST ((uint32) 0x01u << UART_RX_CTRL_MSB_FIRST_POS) +#define UART_RX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define UART_RX_CTRL_MEDIAN ((uint32) 0x01u << UART_RX_CTRL_MEDIAN_POS) +#define UART_RX_CTRL_ENABLED ((uint32) 0x01u << UART_RX_CTRL_ENABLED_POS) + + +/* UART_RX_FIFO_CTRL_REG */ +#define UART_RX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define UART_RX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear RX FIFO: clear after set */ +#define UART_RX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze RX FIFO: HW writes has not effect */ +#define UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK) +#define UART_RX_FIFO_CTRL_CLEAR ((uint32) 0x01u << UART_RX_FIFO_CTRL_CLEAR_POS) +#define UART_RX_FIFO_CTRL_FREEZE ((uint32) 0x01u << UART_RX_FIFO_CTRL_FREEZE_POS) + +/* UART_RX_FIFO_STATUS_REG */ +#define UART_RX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in RX FIFO */ +#define UART_RX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of RX FIFO */ +#define UART_RX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] RX FIFO read pointer */ +#define UART_RX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] RX FIFO write pointer */ +#define UART_RX_FIFO_STATUS_USED_MASK ((uint32) UART_FF_DATA_NR_LOG2_PLUS1_MASK) +#define UART_RX_FIFO_SR_VALID ((uint32) 0x01u << UART_RX_FIFO_SR_VALID_POS) +#define UART_RX_FIFO_STATUS_RD_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_RX_FIFO_STATUS_RD_PTR_POS) +#define UART_RX_FIFO_STATUS_WR_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_RX_FIFO_STATUS_WR_PTR_POS) + +/* UART_RX_MATCH_REG */ +#define UART_RX_MATCH_ADDR_POS (0u) /* [7:0] Slave address */ +#define UART_RX_MATCH_MASK_POS (16u) /* [23:16] Slave address mask: 0 - doesn't care */ +#define UART_RX_MATCH_ADDR_MASK ((uint32) 0xFFu) +#define UART_RX_MATCH_MASK_MASK ((uint32) 0xFFu << UART_RX_MATCH_MASK_POS) + +/* UART_RX_FIFO_WR_REG */ +#define UART_RX_FIFO_RD_POS (0u) /* [15:0] Data read from RX FIFO */ +#define UART_RX_FIFO_RD_MASK ((uint32) 0xFFu) + +/* UART_RX_FIFO_RD_SILENT_REG */ +#define UART_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define UART_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* UART_RX_FIFO_RD_SILENT_REG */ +#define UART_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define UART_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* UART_EZBUF_DATA_REG */ +#define UART_EZBUF_DATA_POS (0u) /* [7:0] Data from EZ Memory */ +#define UART_EZBUF_DATA_MASK ((uint32) 0xFFu) + +/* UART_INTR_CAUSE_REG */ +#define UART_INTR_CAUSE_MASTER_POS (0u) /* [0] Master interrupt active */ +#define UART_INTR_CAUSE_SLAVE_POS (1u) /* [1] Slave interrupt active */ +#define UART_INTR_CAUSE_TX_POS (2u) /* [2] Transmitter interrupt active */ +#define UART_INTR_CAUSE_RX_POS (3u) /* [3] Receiver interrupt active */ +#define UART_INTR_CAUSE_I2C_EC_POS (4u) /* [4] Externally clock I2C interrupt active */ +#define UART_INTR_CAUSE_SPI_EC_POS (5u) /* [5] Externally clocked SPI interrupt active */ +#define UART_INTR_CAUSE_MASTER ((uint32) 0x01u) +#define UART_INTR_CAUSE_SLAVE ((uint32) 0x01u << UART_INTR_CAUSE_SLAVE_POS) +#define UART_INTR_CAUSE_TX ((uint32) 0x01u << UART_INTR_CAUSE_TX_POS) +#define UART_INTR_CAUSE_RX ((uint32) 0x01u << UART_INTR_CAUSE_RX_POS) +#define UART_INTR_CAUSE_I2C_EC ((uint32) 0x01u << UART_INTR_CAUSE_I2C_EC_POS) +#define UART_INTR_CAUSE_SPI_EC ((uint32) 0x01u << UART_INTR_CAUSE_SPI_EC_POS) + +/* UART_INTR_SPI_EC_REG, UART_INTR_SPI_EC_MASK_REG, UART_INTR_SPI_EC_MASKED_REG */ +#define UART_INTR_SPI_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define UART_INTR_SPI_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define UART_INTR_SPI_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define UART_INTR_SPI_EC_WAKE_UP ((uint32) 0x01u) +#define UART_INTR_SPI_EC_EZBUF_STOP ((uint32) 0x01u << \ + UART_INTR_SPI_EC_EZBUF_STOP_POS) +#define UART_INTR_SPI_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_SPI_EC_EZBUF_WRITE_STOP_POS) + +/* UART_INTR_I2C_EC, UART_INTR_I2C_EC_MASK, UART_INTR_I2C_EC_MASKED */ +#define UART_INTR_I2C_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define UART_INTR_I2C_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define UART_INTR_I2C_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define UART_INTR_I2C_EC_WAKE_UP ((uint32) 0x01u) +#define UART_INTR_I2C_EC_EZBUF_STOP ((uint32) 0x01u << \ + UART_INTR_I2C_EC_EZBUF_STOP_POS) +#define UART_INTR_I2C_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_I2C_EC_EZBUF_WRITE_STOP_POS) + +/* UART_INTR_MASTER, UART_INTR_MASTER_SET, + UART_INTR_MASTER_MASK, UART_INTR_MASTER_MASKED */ +#define UART_INTR_MASTER_I2C_ARB_LOST_POS (0u) /* [0] Master lost arbitration */ +#define UART_INTR_MASTER_I2C_NACK_POS (1u) /* [1] Master receives NACK: address or write to slave */ +#define UART_INTR_MASTER_I2C_ACK_POS (2u) /* [2] Master receives NACK: address or write to slave */ +#define UART_INTR_MASTER_I2C_STOP_POS (4u) /* [4] Master detects the Stop: only self generated Stop*/ +#define UART_INTR_MASTER_I2C_BUS_ERROR_POS (8u) /* [8] Master detects bus error: misplaced Start or Stop*/ +#define UART_INTR_MASTER_SPI_DONE_POS (9u) /* [9] Master complete transfer: Only for SPI */ +#define UART_INTR_MASTER_I2C_ARB_LOST ((uint32) 0x01u) +#define UART_INTR_MASTER_I2C_NACK ((uint32) 0x01u << UART_INTR_MASTER_I2C_NACK_POS) +#define UART_INTR_MASTER_I2C_ACK ((uint32) 0x01u << UART_INTR_MASTER_I2C_ACK_POS) +#define UART_INTR_MASTER_I2C_STOP ((uint32) 0x01u << UART_INTR_MASTER_I2C_STOP_POS) +#define UART_INTR_MASTER_I2C_BUS_ERROR ((uint32) 0x01u << \ + UART_INTR_MASTER_I2C_BUS_ERROR_POS) +#define UART_INTR_MASTER_SPI_DONE ((uint32) 0x01u << UART_INTR_MASTER_SPI_DONE_POS) + +/* +* UART_INTR_SLAVE, UART_INTR_SLAVE_SET, +* UART_INTR_SLAVE_MASK, UART_INTR_SLAVE_MASKED +*/ +#define UART_INTR_SLAVE_I2C_ARB_LOST_POS (0u) /* [0] Slave lost arbitration */ +#define UART_INTR_SLAVE_I2C_NACK_POS (1u) /* [1] Slave receives NACK: master reads data */ +#define UART_INTR_SLAVE_I2C_ACK_POS (2u) /* [2] Slave receives ACK: master reads data */ +#define UART_INTR_SLAVE_I2C_WRITE_STOP_POS (3u) /* [3] Slave detects end of write transaction */ +#define UART_INTR_SLAVE_I2C_STOP_POS (4u) /* [4] Slave detects end of transaction intended */ +#define UART_INTR_SLAVE_I2C_START_POS (5u) /* [5] Slave detects Start */ +#define UART_INTR_SLAVE_I2C_ADDR_MATCH_POS (6u) /* [6] Slave address matches */ +#define UART_INTR_SLAVE_I2C_GENERAL_POS (7u) /* [7] General call received */ +#define UART_INTR_SLAVE_I2C_BUS_ERROR_POS (8u) /* [8] Slave detects bus error */ +#define UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS (9u) /* [9] Slave write complete: Only for SPI */ +#define UART_INTR_SLAVE_SPI_EZBUF_STOP_POS (10u) /* [10] Slave end of transaction: Only for SPI */ +#define UART_INTR_SLAVE_SPI_BUS_ERROR_POS (11u) /* [11] Slave detects bus error: Only for SPI */ +#define UART_INTR_SLAVE_I2C_ARB_LOST ((uint32) 0x01u) +#define UART_INTR_SLAVE_I2C_NACK ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_NACK_POS) +#define UART_INTR_SLAVE_I2C_ACK ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_ACK_POS) +#define UART_INTR_SLAVE_I2C_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_WRITE_STOP_POS) +#define UART_INTR_SLAVE_I2C_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_STOP_POS) +#define UART_INTR_SLAVE_I2C_START ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_START_POS) +#define UART_INTR_SLAVE_I2C_ADDR_MATCH ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_ADDR_MATCH_POS) +#define UART_INTR_SLAVE_I2C_GENERAL ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_GENERAL_POS) +#define UART_INTR_SLAVE_I2C_BUS_ERROR ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_BUS_ERROR_POS) +#define UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS) +#define UART_INTR_SLAVE_SPI_EZBUF_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_SPI_EZBUF_STOP_POS) +#define UART_INTR_SLAVE_SPI_BUS_ERROR ((uint32) 0x01u << \ + UART_INTR_SLAVE_SPI_BUS_ERROR_POS) + +/* +* UART_INTR_TX, UART_INTR_TX_SET, +* UART_INTR_TX_MASK, UART_INTR_TX_MASKED +*/ +#define UART_INTR_TX_TRIGGER_POS (0u) /* [0] Trigger on TX FIFO entires */ +#define UART_INTR_TX_NOT_FULL_POS (1u) /* [1] TX FIFO is not full */ +#define UART_INTR_TX_EMPTY_POS (4u) /* [4] TX FIFO is empty */ +#define UART_INTR_TX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full TX FIFO */ +#define UART_INTR_TX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty TX FIFO */ +#define UART_INTR_TX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define UART_INTR_TX_UART_NACK_POS (8u) /* [8] UART transmitter received a NACK: SmartCard mode */ +#define UART_INTR_TX_UART_DONE_POS (9u) /* [9] UART transmitter done even */ +#define UART_INTR_TX_UART_ARB_LOST_POS (10u) /* [10] UART lost arbitration: LIN or SmartCard */ +#define UART_INTR_TX_TRIGGER ((uint32) 0x01u) +#define UART_INTR_TX_FIFO_LEVEL (UART_INTR_TX_TRIGGER) +#define UART_INTR_TX_NOT_FULL ((uint32) 0x01u << UART_INTR_TX_NOT_FULL_POS) +#define UART_INTR_TX_EMPTY ((uint32) 0x01u << UART_INTR_TX_EMPTY_POS) +#define UART_INTR_TX_OVERFLOW ((uint32) 0x01u << UART_INTR_TX_OVERFLOW_POS) +#define UART_INTR_TX_UNDERFLOW ((uint32) 0x01u << UART_INTR_TX_UNDERFLOW_POS) +#define UART_INTR_TX_BLOCKED ((uint32) 0x01u << UART_INTR_TX_BLOCKED_POS) +#define UART_INTR_TX_UART_NACK ((uint32) 0x01u << UART_INTR_TX_UART_NACK_POS) +#define UART_INTR_TX_UART_DONE ((uint32) 0x01u << UART_INTR_TX_UART_DONE_POS) +#define UART_INTR_TX_UART_ARB_LOST ((uint32) 0x01u << UART_INTR_TX_UART_ARB_LOST_POS) + +/* +* UART_INTR_RX, UART_INTR_RX_SET, +* UART_INTR_RX_MASK, UART_INTR_RX_MASKED +*/ +#define UART_INTR_RX_TRIGGER_POS (0u) /* [0] Trigger on RX FIFO entires */ +#define UART_INTR_RX_NOT_EMPTY_POS (2u) /* [2] RX FIFO is not empty */ +#define UART_INTR_RX_FULL_POS (3u) /* [3] RX FIFO is full */ +#define UART_INTR_RX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full RX FIFO */ +#define UART_INTR_RX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty RX FIFO */ +#define UART_INTR_RX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define UART_INTR_RX_FRAME_ERROR_POS (8u) /* [8] Frame error in received data frame */ +#define UART_INTR_RX_PARITY_ERROR_POS (9u) /* [9] Parity error in received data frame */ +#define UART_INTR_RX_BAUD_DETECT_POS (10u) /* [10] LIN baud rate detection is completed */ +#define UART_INTR_RX_BREAK_DETECT_POS (11u) /* [11] Break detection is successful */ +#define UART_INTR_RX_TRIGGER ((uint32) 0x01u) +#define UART_INTR_RX_FIFO_LEVEL (UART_INTR_RX_TRIGGER) +#define UART_INTR_RX_NOT_EMPTY ((uint32) 0x01u << UART_INTR_RX_NOT_EMPTY_POS) +#define UART_INTR_RX_FULL ((uint32) 0x01u << UART_INTR_RX_FULL_POS) +#define UART_INTR_RX_OVERFLOW ((uint32) 0x01u << UART_INTR_RX_OVERFLOW_POS) +#define UART_INTR_RX_UNDERFLOW ((uint32) 0x01u << UART_INTR_RX_UNDERFLOW_POS) +#define UART_INTR_RX_BLOCKED ((uint32) 0x01u << UART_INTR_RX_BLOCKED_POS) +#define UART_INTR_RX_FRAME_ERROR ((uint32) 0x01u << UART_INTR_RX_FRAME_ERROR_POS) +#define UART_INTR_RX_PARITY_ERROR ((uint32) 0x01u << UART_INTR_RX_PARITY_ERROR_POS) +#define UART_INTR_RX_BAUD_DETECT ((uint32) 0x01u << UART_INTR_RX_BAUD_DETECT_POS) +#define UART_INTR_RX_BREAK_DETECT ((uint32) 0x01u << UART_INTR_RX_BREAK_DETECT_POS) + +/* Define all interrupt sources */ +#define UART_INTR_I2C_EC_ALL (UART_INTR_I2C_EC_WAKE_UP | \ + UART_INTR_I2C_EC_EZBUF_STOP | \ + UART_INTR_I2C_EC_EZBUF_WRITE_STOP) + +#define UART_INTR_SPI_EC_ALL (UART_INTR_SPI_EC_WAKE_UP | \ + UART_INTR_SPI_EC_EZBUF_STOP | \ + UART_INTR_SPI_EC_EZBUF_WRITE_STOP) + +#define UART_INTR_MASTER_ALL (UART_INTR_MASTER_I2C_ARB_LOST | \ + UART_INTR_MASTER_I2C_NACK | \ + UART_INTR_MASTER_I2C_ACK | \ + UART_INTR_MASTER_I2C_STOP | \ + UART_INTR_MASTER_I2C_BUS_ERROR | \ + UART_INTR_MASTER_SPI_DONE) + +#define UART_INTR_SLAVE_ALL (UART_INTR_SLAVE_I2C_ARB_LOST | \ + UART_INTR_SLAVE_I2C_NACK | \ + UART_INTR_SLAVE_I2C_ACK | \ + UART_INTR_SLAVE_I2C_WRITE_STOP | \ + UART_INTR_SLAVE_I2C_STOP | \ + UART_INTR_SLAVE_I2C_START | \ + UART_INTR_SLAVE_I2C_ADDR_MATCH | \ + UART_INTR_SLAVE_I2C_GENERAL | \ + UART_INTR_SLAVE_I2C_BUS_ERROR | \ + UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP | \ + UART_INTR_SLAVE_SPI_EZBUF_STOP | \ + UART_INTR_SLAVE_SPI_BUS_ERROR) + +#define UART_INTR_TX_ALL (UART_INTR_TX_TRIGGER | \ + UART_INTR_TX_NOT_FULL | \ + UART_INTR_TX_EMPTY | \ + UART_INTR_TX_OVERFLOW | \ + UART_INTR_TX_UNDERFLOW | \ + UART_INTR_TX_BLOCKED | \ + UART_INTR_TX_UART_NACK | \ + UART_INTR_TX_UART_DONE | \ + UART_INTR_TX_UART_ARB_LOST) + +#define UART_INTR_RX_ALL (UART_INTR_RX_TRIGGER | \ + UART_INTR_RX_NOT_EMPTY | \ + UART_INTR_RX_FULL | \ + UART_INTR_RX_OVERFLOW | \ + UART_INTR_RX_UNDERFLOW | \ + UART_INTR_RX_BLOCKED | \ + UART_INTR_RX_FRAME_ERROR | \ + UART_INTR_RX_PARITY_ERROR | \ + UART_INTR_RX_BAUD_DETECT | \ + UART_INTR_RX_BREAK_DETECT) + +/* I2C and EZI2C slave address defines */ +#define UART_I2C_SLAVE_ADDR_POS (0x01u) /* 7-bit address shift */ +#define UART_I2C_SLAVE_ADDR_MASK (0xFEu) /* 8-bit address mask */ + +/* OVS constants for IrDA Low Power operation */ +#define UART_CTRL_OVS_IRDA_LP_OVS16 (0x00u) +#define UART_CTRL_OVS_IRDA_LP_OVS32 (0x01u) +#define UART_CTRL_OVS_IRDA_LP_OVS48 (0x02u) +#define UART_CTRL_OVS_IRDA_LP_OVS96 (0x03u) +#define UART_CTRL_OVS_IRDA_LP_OVS192 (0x04u) +#define UART_CTRL_OVS_IRDA_LP_OVS768 (0x05u) +#define UART_CTRL_OVS_IRDA_LP_OVS1536 (0x06u) + +/* OVS constant for IrDA */ +#define UART_CTRL_OVS_IRDA_OVS16 (UART_UART_IRDA_LP_OVS16) + + +/*************************************** +* Common Macro Definitions +***************************************/ + +/* Re-enables the SCB IP. A clear enable bit has a different effect +* on the scb IP depending on the version: +* CY_SCBIP_V0: resets state, status, TX and RX FIFOs. +* CY_SCBIP_V1 or later: resets state, status, TX and RX FIFOs and interrupt sources. +* Clear I2C command registers are because they are not impacted by re-enable. +*/ +#define UART_SCB_SW_RESET UART_I2CFwBlockReset() + +/* TX FIFO macro */ +#define UART_CLEAR_TX_FIFO \ + do{ \ + UART_TX_FIFO_CTRL_REG |= ((uint32) UART_TX_FIFO_CTRL_CLEAR); \ + UART_TX_FIFO_CTRL_REG &= ((uint32) ~UART_TX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define UART_GET_TX_FIFO_ENTRIES (UART_TX_FIFO_STATUS_REG & \ + UART_TX_FIFO_STATUS_USED_MASK) + +#define UART_GET_TX_FIFO_SR_VALID ((0u != (UART_TX_FIFO_STATUS_REG & \ + UART_TX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* RX FIFO macro */ +#define UART_CLEAR_RX_FIFO \ + do{ \ + UART_RX_FIFO_CTRL_REG |= ((uint32) UART_RX_FIFO_CTRL_CLEAR); \ + UART_RX_FIFO_CTRL_REG &= ((uint32) ~UART_RX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define UART_GET_RX_FIFO_ENTRIES (UART_RX_FIFO_STATUS_REG & \ + UART_RX_FIFO_STATUS_USED_MASK) + +#define UART_GET_RX_FIFO_SR_VALID ((0u != (UART_RX_FIFO_STATUS_REG & \ + UART_RX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* Write interrupt source: set sourceMask bits in UART_INTR_X_MASK_REG */ +#define UART_WRITE_INTR_I2C_EC_MASK(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!UART_CY_SCBIP_V1) + #define UART_WRITE_INTR_SPI_EC_MASK(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_WRITE_INTR_MASTER_MASK(sourceMask) \ + do{ \ + UART_INTR_MASTER_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_WRITE_INTR_SLAVE_MASK(sourceMask) \ + do{ \ + UART_INTR_SLAVE_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_WRITE_INTR_TX_MASK(sourceMask) \ + do{ \ + UART_INTR_TX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_WRITE_INTR_RX_MASK(sourceMask) \ + do{ \ + UART_INTR_RX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +/* Enable interrupt source: set sourceMask bits in UART_INTR_X_MASK_REG */ +#define UART_ENABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#if (!UART_CY_SCBIP_V1) + #define UART_ENABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_ENABLE_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_ENABLE_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_ENABLE_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_ENABLE_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +/* Disable interrupt source: clear sourceMask bits in UART_INTR_X_MASK_REG */ +#define UART_DISABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#if (!UART_CY_SCBIP_V1) + #define UART_DISABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_DISABLE_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_DISABLE_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_DISABLE_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_DISABLE_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +/* Set interrupt sources: write sourceMask bits in UART_INTR_X_SET_REG */ +#define UART_SET_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_SET_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_SET_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_SET_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +/* Clear interrupt sources: write sourceMask bits in UART_INTR_X_REG */ +#define UART_CLEAR_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!UART_CY_SCBIP_V1) + #define UART_CLEAR_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_CLEAR_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_CLEAR_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_CLEAR_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_CLEAR_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_REG = (uint32) (sourceMask); \ + }while(0) + +/* Return true if sourceMask is set in UART_INTR_CAUSE_REG */ +#define UART_CHECK_CAUSE_INTR(sourceMask) (0u != (UART_INTR_CAUSE_REG & (sourceMask))) + +/* Return true if sourceMask is set in INTR_X_MASKED_REG */ +#define UART_CHECK_INTR_I2C_EC(sourceMask) (0u != (UART_INTR_I2C_EC_REG & (sourceMask))) +#if (!UART_CY_SCBIP_V1) + #define UART_CHECK_INTR_SPI_EC(sourceMask) (0u != (UART_INTR_SPI_EC_REG & (sourceMask))) +#endif /* (!UART_CY_SCBIP_V1) */ +#define UART_CHECK_INTR_MASTER(sourceMask) (0u != (UART_INTR_MASTER_REG & (sourceMask))) +#define UART_CHECK_INTR_SLAVE(sourceMask) (0u != (UART_INTR_SLAVE_REG & (sourceMask))) +#define UART_CHECK_INTR_TX(sourceMask) (0u != (UART_INTR_TX_REG & (sourceMask))) +#define UART_CHECK_INTR_RX(sourceMask) (0u != (UART_INTR_RX_REG & (sourceMask))) + +/* Return true if sourceMask is set in UART_INTR_X_MASKED_REG */ +#define UART_CHECK_INTR_I2C_EC_MASKED(sourceMask) (0u != (UART_INTR_I2C_EC_MASKED_REG & \ + (sourceMask))) +#if (!UART_CY_SCBIP_V1) + #define UART_CHECK_INTR_SPI_EC_MASKED(sourceMask) (0u != (UART_INTR_SPI_EC_MASKED_REG & \ + (sourceMask))) +#endif /* (!UART_CY_SCBIP_V1) */ +#define UART_CHECK_INTR_MASTER_MASKED(sourceMask) (0u != (UART_INTR_MASTER_MASKED_REG & \ + (sourceMask))) +#define UART_CHECK_INTR_SLAVE_MASKED(sourceMask) (0u != (UART_INTR_SLAVE_MASKED_REG & \ + (sourceMask))) +#define UART_CHECK_INTR_TX_MASKED(sourceMask) (0u != (UART_INTR_TX_MASKED_REG & \ + (sourceMask))) +#define UART_CHECK_INTR_RX_MASKED(sourceMask) (0u != (UART_INTR_RX_MASKED_REG & \ + (sourceMask))) + +/* Return true if sourceMask is set in UART_CTRL_REG: generally is used to check enable bit */ +#define UART_GET_CTRL_ENABLED (0u != (UART_CTRL_REG & UART_CTRL_ENABLED)) + +#define UART_CHECK_SLAVE_AUTO_ADDR_NACK (0u != (UART_I2C_CTRL_REG & \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK)) + + +/*************************************** +* I2C Macro Definitions +***************************************/ + +/* Enable auto ACK/NACK */ +#define UART_ENABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_ENABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define UART_ENABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_ENABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define UART_ENABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Disable auto ACK/NACK */ +#define UART_DISABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_DISABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define UART_DISABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_DISABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define UART_DISABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Enable Slave autoACK/NACK Data */ +#define UART_ENABLE_SLAVE_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG |= (UART_I2C_CTRL_S_READY_DATA_ACK | \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK); \ + }while(0) + +/* Disable Slave autoACK/NACK Data */ +#define UART_DISABLE_SLAVE_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG &= ((uint32) \ + ~(UART_I2C_CTRL_S_READY_DATA_ACK | \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Disable Master autoACK/NACK Data */ +#define UART_DISABLE_MASTER_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG &= ((uint32) \ + ~(UART_I2C_CTRL_M_READY_DATA_ACK | \ + UART_I2C_CTRL_M_NOT_READY_DATA_NACK)); \ + }while(0) +/* Disables auto data ACK/NACK bits */ +#define UART_DISABLE_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG &= ((uint32) ~(UART_I2C_CTRL_M_READY_DATA_ACK | \ + UART_I2C_CTRL_M_NOT_READY_DATA_NACK | \ + UART_I2C_CTRL_S_READY_DATA_ACK | \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Master commands */ +#define UART_I2C_MASTER_GENERATE_START \ + do{ \ + UART_I2C_MASTER_CMD_REG = UART_I2C_MASTER_CMD_M_START_ON_IDLE; \ + }while(0) + +#define UART_I2C_MASTER_CLEAR_START \ + do{ \ + UART_I2C_MASTER_CMD_REG = ((uint32) 0u); \ + }while(0) + +#define UART_I2C_MASTER_GENERATE_RESTART UART_I2CReStartGeneration() + +#define UART_I2C_MASTER_GENERATE_STOP \ + do{ \ + UART_I2C_MASTER_CMD_REG = \ + (UART_I2C_MASTER_CMD_M_STOP | \ + (UART_CHECK_I2C_STATUS(UART_I2C_STATUS_M_READ) ? \ + (UART_I2C_MASTER_CMD_M_NACK) : (0u))); \ + }while(0) + +#define UART_I2C_MASTER_GENERATE_ACK \ + do{ \ + UART_I2C_MASTER_CMD_REG = UART_I2C_MASTER_CMD_M_ACK; \ + }while(0) + +#define UART_I2C_MASTER_GENERATE_NACK \ + do{ \ + UART_I2C_MASTER_CMD_REG = UART_I2C_MASTER_CMD_M_NACK; \ + }while(0) + +/* Slave commands */ +#define UART_I2C_SLAVE_GENERATE_ACK \ + do{ \ + UART_I2C_SLAVE_CMD_REG = UART_I2C_SLAVE_CMD_S_ACK; \ + }while(0) + +#if (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* Slave NACK generation for EC_AM logic on address phase. Ticket ID #183902 */ + void UART_I2CSlaveNackGeneration(void); + #define UART_I2C_SLAVE_GENERATE_NACK UART_I2CSlaveNackGeneration() + +#else + #define UART_I2C_SLAVE_GENERATE_NACK \ + do{ \ + UART_I2C_SLAVE_CMD_REG = UART_I2C_SLAVE_CMD_S_NACK; \ + }while(0) +#endif /* (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#define UART_I2C_SLAVE_CLEAR_NACK \ + do{ \ + UART_I2C_SLAVE_CMD_REG = 0u; \ + }while(0) + +/* Return 8-bit address. The input address should be 7-bits */ +#define UART_GET_I2C_8BIT_ADDRESS(addr) (((uint32) ((uint32) (addr) << \ + UART_I2C_SLAVE_ADDR_POS)) & \ + UART_I2C_SLAVE_ADDR_MASK) + +#define UART_GET_I2C_7BIT_ADDRESS(addr) ((uint32) (addr) >> UART_I2C_SLAVE_ADDR_POS) + +/* Adjust SDA filter Trim settings */ +#define UART_DEFAULT_I2C_CFG_SDA_FILT_TRIM (0x02u) +#define UART_EC_AM_I2C_CFG_SDA_FILT_TRIM (0x03u) + +#if (UART_CY_SCBIP_V0) + #define UART_SET_I2C_CFG_SDA_FILT_TRIM(sdaTrim) \ + do{ \ + UART_I2C_CFG_REG = \ + ((UART_I2C_CFG_REG & (uint32) ~UART_I2C_CFG_SDA_FILT_TRIM_MASK) | \ + ((uint32) ((uint32) (sdaTrim) <> \ + (UART_DM_SIZE * (pos)) ) + +#if (UART_TX_SDA_MISO_PIN) + #define UART_CHECK_TX_SDA_MISO_PIN_USED \ + (UART_PIN_DM_ALG_HIZ != \ + UART_GET_P4_PIN_DM(UART_uart_tx_i2c_sda_spi_miso_PC, \ + UART_uart_tx_i2c_sda_spi_miso_SHIFT)) +#endif /* (UART_TX_SDA_MISO_PIN) */ + +#if (UART_SS0_PIN) + #define UART_CHECK_SS0_PIN_USED \ + (UART_PIN_DM_ALG_HIZ != \ + UART_GET_P4_PIN_DM(UART_spi_ss0_PC, \ + UART_spi_ss0_SHIFT)) +#endif /* (UART_SS0_PIN) */ + +/* Set bits-mask in register */ +#define UART_SET_REGISTER_BITS(reg, mask, pos, mode) \ + do \ + { \ + (reg) = (((reg) & ((uint32) ~(uint32) (mask))) | ((uint32) ((uint32) (mode) << (pos)))); \ + }while(0) + +/* Set bit in the register */ +#define UART_SET_REGISTER_BIT(reg, mask, val) \ + ((val) ? ((reg) |= (mask)) : ((reg) &= ((uint32) ~((uint32) (mask))))) + +#define UART_SET_HSIOM_SEL(reg, mask, pos, sel) UART_SET_REGISTER_BITS(reg, mask, pos, sel) +#define UART_SET_INCFG_TYPE(reg, mask, pos, intType) \ + UART_SET_REGISTER_BITS(reg, mask, pos, intType) +#define UART_SET_INP_DIS(reg, mask, val) UART_SET_REGISTER_BIT(reg, mask, val) + +/* UART_SET_I2C_SCL_DR(val) - Sets I2C SCL DR register. +* UART_SET_I2C_SCL_HSIOM_SEL(sel) - Sets I2C SCL HSIOM settings. +*/ +/* SCB I2C: scl signal */ +#if (UART_CY_SCBIP_V0) +#if (UART_I2C_PINS) + #define UART_SET_I2C_SCL_DR(val) UART_scl_Write(val) + + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_SET_HSIOM_SEL(UART_SCL_HSIOM_REG, \ + UART_SCL_HSIOM_MASK, \ + UART_SCL_HSIOM_POS, \ + (sel)) + #define UART_WAIT_SCL_SET_HIGH (0u == UART_scl_Read()) + +/* Unconfigured SCB: scl signal */ +#elif (UART_RX_WAKE_SCL_MOSI_PIN) + #define UART_SET_I2C_SCL_DR(val) \ + UART_uart_rx_wake_i2c_scl_spi_mosi_Write(val) + + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_SET_HSIOM_SEL(UART_RX_WAKE_SCL_MOSI_HSIOM_REG, \ + UART_RX_WAKE_SCL_MOSI_HSIOM_MASK, \ + UART_RX_WAKE_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define UART_WAIT_SCL_SET_HIGH (0u == UART_uart_rx_wake_i2c_scl_spi_mosi_Read()) + +#elif (UART_RX_SCL_MOSI_PIN) + #define UART_SET_I2C_SCL_DR(val) \ + UART_uart_rx_i2c_scl_spi_mosi_Write(val) + + + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_SET_HSIOM_SEL(UART_RX_SCL_MOSI_HSIOM_REG, \ + UART_RX_SCL_MOSI_HSIOM_MASK, \ + UART_RX_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define UART_WAIT_SCL_SET_HIGH (0u == UART_uart_rx_i2c_scl_spi_mosi_Read()) + +#else + #define UART_SET_I2C_SCL_DR(val) do{ /* Does nothing */ }while(0) + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) do{ /* Does nothing */ }while(0) + + #define UART_WAIT_SCL_SET_HIGH (0u) +#endif /* (UART_I2C_PINS) */ + +/* SCB I2C: sda signal */ +#if (UART_I2C_PINS) + #define UART_WAIT_SDA_SET_HIGH (0u == UART_sda_Read()) +/* Unconfigured SCB: sda signal */ +#elif (UART_TX_SDA_MISO_PIN) + #define UART_WAIT_SDA_SET_HIGH (0u == UART_uart_tx_i2c_sda_spi_miso_Read()) +#else + #define UART_WAIT_SDA_SET_HIGH (0u) +#endif /* (UART_MOSI_SCL_RX_PIN) */ +#endif /* (UART_CY_SCBIP_V0) */ + +/* Clear UART wakeup source */ +#if (UART_RX_SCL_MOSI_PIN) + #define UART_CLEAR_UART_RX_WAKE_INTR do{ /* Does nothing */ }while(0) + +#elif (UART_RX_WAKE_SCL_MOSI_PIN) + #define UART_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) UART_uart_rx_wake_i2c_scl_spi_mosi_ClearInterrupt(); \ + }while(0) + +#elif(UART_UART_RX_WAKE_PIN) + #define UART_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) UART_rx_wake_ClearInterrupt(); \ + }while(0) +#else +#endif /* (UART_RX_SCL_MOSI_PIN) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Unconfigured pins */ +#define UART_REMOVE_MOSI_SCL_RX_WAKE_PIN UART_REMOVE_RX_WAKE_SCL_MOSI_PIN +#define UART_REMOVE_MOSI_SCL_RX_PIN UART_REMOVE_RX_SCL_MOSI_PIN +#define UART_REMOVE_MISO_SDA_TX_PIN UART_REMOVE_TX_SDA_MISO_PIN +#ifndef UART_REMOVE_SCLK_PIN +#define UART_REMOVE_SCLK_PIN UART_REMOVE_SCLK_PIN +#endif /* UART_REMOVE_SCLK_PIN */ +#ifndef UART_REMOVE_SS0_PIN +#define UART_REMOVE_SS0_PIN UART_REMOVE_SS0_PIN +#endif /* UART_REMOVE_SS0_PIN */ + +/* Unconfigured pins */ +#define UART_MOSI_SCL_RX_WAKE_PIN UART_RX_WAKE_SCL_MOSI_PIN +#define UART_MOSI_SCL_RX_PIN UART_RX_SCL_MOSI_PIN +#define UART_MISO_SDA_TX_PIN UART_TX_SDA_MISO_PIN +#ifndef UART_SCLK_PIN +#define UART_SCLK_PIN UART_SCLK_PIN +#endif /* UART_SCLK_PIN */ +#ifndef UART_SS0_PIN +#define UART_SS0_PIN UART_SS0_PIN +#endif /* UART_SS0_PIN */ + +#if (UART_MOSI_SCL_RX_WAKE_PIN) + #define UART_MOSI_SCL_RX_WAKE_HSIOM_REG UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_HSIOM_PTR UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_HSIOM_MASK UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_HSIOM_POS UART_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define UART_MOSI_SCL_RX_WAKE_INTCFG_REG UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_INTCFG_PTR UART_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define UART_MOSI_SCL_RX_WAKE_INTCFG_TYPE_POS UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_INTCFG_TYPE_MASK UART_RX_WAKE_SCL_MOSI_HSIOM_REG +#endif /* (UART_RX_WAKE_SCL_MOSI_PIN) */ + +#if (UART_MOSI_SCL_RX_PIN) + #define UART_MOSI_SCL_RX_HSIOM_REG UART_RX_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_HSIOM_PTR UART_RX_SCL_MOSI_HSIOM_PTR + #define UART_MOSI_SCL_RX_HSIOM_MASK UART_RX_SCL_MOSI_HSIOM_MASK + #define UART_MOSI_SCL_RX_HSIOM_POS UART_RX_SCL_MOSI_HSIOM_POS +#endif /* (UART_MOSI_SCL_RX_PIN) */ + +#if (UART_MISO_SDA_TX_PIN) + #define UART_MISO_SDA_TX_HSIOM_REG UART_TX_SDA_MISO_HSIOM_REG + #define UART_MISO_SDA_TX_HSIOM_PTR UART_TX_SDA_MISO_HSIOM_REG + #define UART_MISO_SDA_TX_HSIOM_MASK UART_TX_SDA_MISO_HSIOM_REG + #define UART_MISO_SDA_TX_HSIOM_POS UART_TX_SDA_MISO_HSIOM_REG +#endif /* (UART_MISO_SDA_TX_PIN_PIN) */ + +#if (UART_SCLK_PIN) + #ifndef UART_SCLK_HSIOM_REG + #define UART_SCLK_HSIOM_REG UART_SCLK_HSIOM_REG + #define UART_SCLK_HSIOM_PTR UART_SCLK_HSIOM_PTR + #define UART_SCLK_HSIOM_MASK UART_SCLK_HSIOM_MASK + #define UART_SCLK_HSIOM_POS UART_SCLK_HSIOM_POS + #endif /* UART_SCLK_HSIOM_REG */ +#endif /* (UART_SCLK_PIN) */ + +#if (UART_SS0_PIN) + #ifndef UART_SS0_HSIOM_REG + #define UART_SS0_HSIOM_REG UART_SS0_HSIOM_REG + #define UART_SS0_HSIOM_PTR UART_SS0_HSIOM_PTR + #define UART_SS0_HSIOM_MASK UART_SS0_HSIOM_MASK + #define UART_SS0_HSIOM_POS UART_SS0_HSIOM_POS + #endif /* UART_SS0_HSIOM_REG */ +#endif /* (UART_SS0_PIN) */ + +#define UART_MOSI_SCL_RX_WAKE_PIN_INDEX UART_RX_WAKE_SCL_MOSI_PIN_INDEX +#define UART_MOSI_SCL_RX_PIN_INDEX UART_RX_SCL_MOSI_PIN_INDEX +#define UART_MISO_SDA_TX_PIN_INDEX UART_TX_SDA_MISO_PIN_INDEX +#ifndef UART_SCLK_PIN_INDEX +#define UART_SCLK_PIN_INDEX UART_SCLK_PIN_INDEX +#endif /* UART_SCLK_PIN_INDEX */ +#ifndef UART_SS0_PIN_INDEX +#define UART_SS0_PIN_INDEX UART_SS0_PIN_INDEX +#endif /* UART_SS0_PIN_INDEX */ + +#define UART_MOSI_SCL_RX_WAKE_PIN_MASK UART_RX_WAKE_SCL_MOSI_PIN_MASK +#define UART_MOSI_SCL_RX_PIN_MASK UART_RX_SCL_MOSI_PIN_MASK +#define UART_MISO_SDA_TX_PIN_MASK UART_TX_SDA_MISO_PIN_MASK +#ifndef UART_SCLK_PIN_MASK +#define UART_SCLK_PIN_MASK UART_SCLK_PIN_MASK +#endif /* UART_SCLK_PIN_MASK */ +#ifndef UART_SS0_PIN_MASK +#define UART_SS0_PIN_MASK UART_SS0_PIN_MASK +#endif /* UART_SS0_PIN_MASK */ + +#endif /* (CY_SCB_PINS_UART_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PM.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PM.c new file mode 100644 index 0000000..000a1be --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PM.c @@ -0,0 +1,223 @@ +/***************************************************************************//** +* \file UART_PM.c +* \version 4.0 +* +* \brief +* This file provides the source code to the Power Management support for +* the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART.h" +#include "UART_PVT.h" + +#if(UART_SCB_MODE_I2C_INC) + #include "UART_I2C_PVT.h" +#endif /* (UART_SCB_MODE_I2C_INC) */ + +#if(UART_SCB_MODE_EZI2C_INC) + #include "UART_EZI2C_PVT.h" +#endif /* (UART_SCB_MODE_EZI2C_INC) */ + +#if(UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) + #include "UART_SPI_UART_PVT.h" +#endif /* (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) */ + + +/*************************************** +* Backup Structure declaration +***************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG || \ + (UART_SCB_MODE_I2C_CONST_CFG && (!UART_I2C_WAKE_ENABLE_CONST)) || \ + (UART_SCB_MODE_EZI2C_CONST_CFG && (!UART_EZI2C_WAKE_ENABLE_CONST)) || \ + (UART_SCB_MODE_SPI_CONST_CFG && (!UART_SPI_WAKE_ENABLE_CONST)) || \ + (UART_SCB_MODE_UART_CONST_CFG && (!UART_UART_WAKE_ENABLE_CONST))) + + UART_BACKUP_STRUCT UART_backup = + { + 0u, /* enableState */ + }; +#endif + + +/******************************************************************************* +* Function Name: UART_Sleep +****************************************************************************//** +* +* Prepares the UART component to enter Deep Sleep. +* The “Enable wakeup from Deep Sleep Mode” selection has an influence on this +* function implementation: +* - Checked: configures the component to be wakeup source from Deep Sleep. +* - Unchecked: stores the current component state (enabled or disabled) and +* disables the component. See SCB_Stop() function for details about component +* disabling. +* +* Call the UART_Sleep() function before calling the +* CyPmSysDeepSleep() function. +* Refer to the PSoC Creator System Reference Guide for more information about +* power management functions and Low power section of this document for the +* selected mode. +* +* This function should not be called before entering Sleep. +* +*******************************************************************************/ +void UART_Sleep(void) +{ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + if(UART_SCB_WAKE_ENABLE_CHECK) + { + if(UART_SCB_MODE_I2C_RUNTM_CFG) + { + UART_I2CSaveConfig(); + } + else if(UART_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_EzI2CSaveConfig(); + } + #if(!UART_CY_SCBIP_V1) + else if(UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiSaveConfig(); + } + else if(UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartSaveConfig(); + } + #endif /* (!UART_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + UART_backup.enableState = (uint8) UART_GET_CTRL_ENABLED; + + if(0u != UART_backup.enableState) + { + UART_Stop(); + } + } + +#else + + #if (UART_SCB_MODE_I2C_CONST_CFG && UART_I2C_WAKE_ENABLE_CONST) + UART_I2CSaveConfig(); + + #elif (UART_SCB_MODE_EZI2C_CONST_CFG && UART_EZI2C_WAKE_ENABLE_CONST) + UART_EzI2CSaveConfig(); + + #elif (UART_SCB_MODE_SPI_CONST_CFG && UART_SPI_WAKE_ENABLE_CONST) + UART_SpiSaveConfig(); + + #elif (UART_SCB_MODE_UART_CONST_CFG && UART_UART_WAKE_ENABLE_CONST) + UART_UartSaveConfig(); + + #else + + UART_backup.enableState = (uint8) UART_GET_CTRL_ENABLED; + + if(0u != UART_backup.enableState) + { + UART_Stop(); + } + + #endif /* defined (UART_SCB_MODE_I2C_CONST_CFG) && (UART_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_Wakeup +****************************************************************************//** +* +* Prepares the UART component for Active mode operation after +* Deep Sleep. +* The “Enable wakeup from Deep Sleep Mode” selection has influence on this +* function implementation: +* - Checked: restores the component Active mode configuration. +* - Unchecked: enables the component if it was enabled before enter Deep Sleep. +* +* This function should not be called after exiting Sleep. +* +* \sideeffect +* Calling the UART_Wakeup() function without first calling the +* UART_Sleep() function may produce unexpected behavior. +* +*******************************************************************************/ +void UART_Wakeup(void) +{ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + if(UART_SCB_WAKE_ENABLE_CHECK) + { + if(UART_SCB_MODE_I2C_RUNTM_CFG) + { + UART_I2CRestoreConfig(); + } + else if(UART_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_EzI2CRestoreConfig(); + } + #if(!UART_CY_SCBIP_V1) + else if(UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiRestoreConfig(); + } + else if(UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartRestoreConfig(); + } + #endif /* (!UART_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + if(0u != UART_backup.enableState) + { + UART_Enable(); + } + } + +#else + + #if (UART_SCB_MODE_I2C_CONST_CFG && UART_I2C_WAKE_ENABLE_CONST) + UART_I2CRestoreConfig(); + + #elif (UART_SCB_MODE_EZI2C_CONST_CFG && UART_EZI2C_WAKE_ENABLE_CONST) + UART_EzI2CRestoreConfig(); + + #elif (UART_SCB_MODE_SPI_CONST_CFG && UART_SPI_WAKE_ENABLE_CONST) + UART_SpiRestoreConfig(); + + #elif (UART_SCB_MODE_UART_CONST_CFG && UART_UART_WAKE_ENABLE_CONST) + UART_UartRestoreConfig(); + + #else + + if(0u != UART_backup.enableState) + { + UART_Enable(); + } + + #endif /* (UART_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PVT.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PVT.h new file mode 100644 index 0000000..aa1d516 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_PVT.h @@ -0,0 +1,123 @@ +/***************************************************************************//** +* \file .h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_PVT_UART_H) +#define CY_SCB_PVT_UART_H + +#include "UART.h" + + +/*************************************** +* Private Function Prototypes +***************************************/ + +/* APIs to service INTR_I2C_EC register */ +#define UART_SetI2CExtClkInterruptMode(interruptMask) UART_WRITE_INTR_I2C_EC_MASK(interruptMask) +#define UART_ClearI2CExtClkInterruptSource(interruptMask) UART_CLEAR_INTR_I2C_EC(interruptMask) +#define UART_GetI2CExtClkInterruptSource() (UART_INTR_I2C_EC_REG) +#define UART_GetI2CExtClkInterruptMode() (UART_INTR_I2C_EC_MASK_REG) +#define UART_GetI2CExtClkInterruptSourceMasked() (UART_INTR_I2C_EC_MASKED_REG) + +#if (!UART_CY_SCBIP_V1) + /* APIs to service INTR_SPI_EC register */ + #define UART_SetSpiExtClkInterruptMode(interruptMask) \ + UART_WRITE_INTR_SPI_EC_MASK(interruptMask) + #define UART_ClearSpiExtClkInterruptSource(interruptMask) \ + UART_CLEAR_INTR_SPI_EC(interruptMask) + #define UART_GetExtSpiClkInterruptSource() (UART_INTR_SPI_EC_REG) + #define UART_GetExtSpiClkInterruptMode() (UART_INTR_SPI_EC_MASK_REG) + #define UART_GetExtSpiClkInterruptSourceMasked() (UART_INTR_SPI_EC_MASKED_REG) +#endif /* (!UART_CY_SCBIP_V1) */ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + extern void UART_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if (UART_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + extern cyisraddress UART_customIntrHandler; +#endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ +#endif /* (UART_SCB_IRQ_INTERNAL) */ + +extern UART_BACKUP_STRUCT UART_backup; + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + extern uint8 UART_scbMode; + extern uint8 UART_scbEnableWake; + extern uint8 UART_scbEnableIntr; + + /* I2C configuration variables */ + extern uint8 UART_mode; + extern uint8 UART_acceptAddr; + + /* SPI/UART configuration variables */ + extern volatile uint8 * UART_rxBuffer; + extern uint8 UART_rxDataBits; + extern uint32 UART_rxBufferSize; + + extern volatile uint8 * UART_txBuffer; + extern uint8 UART_txDataBits; + extern uint32 UART_txBufferSize; + + /* EZI2C configuration variables */ + extern uint8 UART_numberOfAddr; + extern uint8 UART_subAddrSize; +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) + extern uint16 UART_IntrTxMask; +#endif /* (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) */ + + +/*************************************** +* Conditional Macro +****************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Defines run time operation mode */ + #define UART_SCB_MODE_I2C_RUNTM_CFG (UART_SCB_MODE_I2C == UART_scbMode) + #define UART_SCB_MODE_SPI_RUNTM_CFG (UART_SCB_MODE_SPI == UART_scbMode) + #define UART_SCB_MODE_UART_RUNTM_CFG (UART_SCB_MODE_UART == UART_scbMode) + #define UART_SCB_MODE_EZI2C_RUNTM_CFG (UART_SCB_MODE_EZI2C == UART_scbMode) + #define UART_SCB_MODE_UNCONFIG_RUNTM_CFG \ + (UART_SCB_MODE_UNCONFIG == UART_scbMode) + + /* Defines wakeup enable */ + #define UART_SCB_WAKE_ENABLE_CHECK (0u != UART_scbEnableWake) +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +/* Defines maximum number of SCB pins */ +#if (!UART_CY_SCBIP_V1) + #define UART_SCB_PINS_NUMBER (7u) +#else + #define UART_SCB_PINS_NUMBER (2u) +#endif /* (!UART_CY_SCBIP_V1) */ + +#endif /* (CY_SCB_PVT_UART_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SCBCLK.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SCBCLK.c new file mode 100644 index 0000000..4205404 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SCBCLK.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: UART_SCBCLK.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "UART_SCBCLK.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: UART_SCBCLK_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void UART_SCBCLK_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((UART_SCBCLK_CMD_REG & UART_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + UART_SCBCLK_CMD_REG = + ((uint32)UART_SCBCLK__DIV_ID << UART_SCBCLK_CMD_DIV_SHIFT)| + (alignClkDiv << UART_SCBCLK_CMD_PA_DIV_SHIFT) | + (uint32)UART_SCBCLK_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: UART_SCBCLK_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void UART_SCBCLK_Start(void) +{ + /* Set the bit to enable the clock. */ + UART_SCBCLK_ENABLE_REG |= UART_SCBCLK__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: UART_SCBCLK_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void UART_SCBCLK_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((UART_SCBCLK_CMD_REG & UART_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + UART_SCBCLK_CMD_REG = + ((uint32)UART_SCBCLK__DIV_ID << UART_SCBCLK_CMD_DIV_SHIFT)| + ((uint32)UART_SCBCLK_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + UART_SCBCLK_ENABLE_REG &= (uint32)(~UART_SCBCLK__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: UART_SCBCLK_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void UART_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (UART_SCBCLK__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = UART_SCBCLK_DIV_REG & + (uint32)(~(uint32)(UART_SCBCLK_DIV_INT_MASK | UART_SCBCLK_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << UART_SCBCLK_DIV_INT_SHIFT) & UART_SCBCLK_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << UART_SCBCLK_DIV_FRAC_SHIFT) & UART_SCBCLK_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = UART_SCBCLK_DIV_REG & (uint32)(~(uint32)UART_SCBCLK__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* UART_SCBCLK__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + UART_SCBCLK_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: UART_SCBCLK_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 UART_SCBCLK_GetDividerRegister(void) +{ + return (uint16)((UART_SCBCLK_DIV_REG & UART_SCBCLK_DIV_INT_MASK) + >> UART_SCBCLK_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_SCBCLK_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 UART_SCBCLK_GetFractionalDividerRegister(void) +{ +#if defined (UART_SCBCLK__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((UART_SCBCLK_DIV_REG & UART_SCBCLK_DIV_FRAC_MASK) + >> UART_SCBCLK_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* UART_SCBCLK__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SCBCLK.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SCBCLK.h new file mode 100644 index 0000000..65b74d1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SCBCLK.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* File Name: UART_SCBCLK.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_UART_SCBCLK_H) +#define CY_CLOCK_UART_SCBCLK_H + +#include +#include + + +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void UART_SCBCLK_StartEx(uint32 alignClkDiv); +#define UART_SCBCLK_Start() \ + UART_SCBCLK_StartEx(UART_SCBCLK__PA_DIV_ID) + +#else + +void UART_SCBCLK_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void UART_SCBCLK_Stop(void); + +void UART_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 UART_SCBCLK_GetDividerRegister(void); +uint8 UART_SCBCLK_GetFractionalDividerRegister(void); + +#define UART_SCBCLK_Enable() UART_SCBCLK_Start() +#define UART_SCBCLK_Disable() UART_SCBCLK_Stop() +#define UART_SCBCLK_SetDividerRegister(clkDivider, reset) \ + UART_SCBCLK_SetFractionalDividerRegister((clkDivider), 0u) +#define UART_SCBCLK_SetDivider(clkDivider) UART_SCBCLK_SetDividerRegister((clkDivider), 1u) +#define UART_SCBCLK_SetDividerValue(clkDivider) UART_SCBCLK_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define UART_SCBCLK_DIV_ID UART_SCBCLK__DIV_ID + +#define UART_SCBCLK_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define UART_SCBCLK_CTRL_REG (*(reg32 *)UART_SCBCLK__CTRL_REGISTER) +#define UART_SCBCLK_DIV_REG (*(reg32 *)UART_SCBCLK__DIV_REGISTER) + +#define UART_SCBCLK_CMD_DIV_SHIFT (0u) +#define UART_SCBCLK_CMD_PA_DIV_SHIFT (8u) +#define UART_SCBCLK_CMD_DISABLE_SHIFT (30u) +#define UART_SCBCLK_CMD_ENABLE_SHIFT (31u) + +#define UART_SCBCLK_CMD_DISABLE_MASK ((uint32)((uint32)1u << UART_SCBCLK_CMD_DISABLE_SHIFT)) +#define UART_SCBCLK_CMD_ENABLE_MASK ((uint32)((uint32)1u << UART_SCBCLK_CMD_ENABLE_SHIFT)) + +#define UART_SCBCLK_DIV_FRAC_MASK (0x000000F8u) +#define UART_SCBCLK_DIV_FRAC_SHIFT (3u) +#define UART_SCBCLK_DIV_INT_MASK (0xFFFFFF00u) +#define UART_SCBCLK_DIV_INT_SHIFT (8u) + +#else + +#define UART_SCBCLK_DIV_REG (*(reg32 *)UART_SCBCLK__REGISTER) +#define UART_SCBCLK_ENABLE_REG UART_SCBCLK_DIV_REG +#define UART_SCBCLK_DIV_FRAC_MASK UART_SCBCLK__FRAC_MASK +#define UART_SCBCLK_DIV_FRAC_SHIFT (16u) +#define UART_SCBCLK_DIV_INT_MASK UART_SCBCLK__DIVIDER_MASK +#define UART_SCBCLK_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_UART_SCBCLK_H) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART.c new file mode 100644 index 0000000..4db5689 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART.c @@ -0,0 +1,603 @@ +/***************************************************************************//** +* \file UART_SPI_UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" +#include "UART_SPI_UART_PVT.h" + +/*************************************** +* SPI/UART Private Vars +***************************************/ + +#if(UART_INTERNAL_RX_SW_BUFFER_CONST) + /* Start index to put data into the software receive buffer.*/ + volatile uint32 UART_rxBufferHead; + /* Start index to get data from the software receive buffer.*/ + volatile uint32 UART_rxBufferTail; + /** + * \addtogroup group_globals + * \{ + */ + /** Sets when internal software receive buffer overflow + * was occurred. + */ + volatile uint8 UART_rxBufferOverflow; + /** \} globals */ +#endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if(UART_INTERNAL_TX_SW_BUFFER_CONST) + /* Start index to put data into the software transmit buffer.*/ + volatile uint32 UART_txBufferHead; + /* Start index to get data from the software transmit buffer.*/ + volatile uint32 UART_txBufferTail; +#endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if(UART_INTERNAL_RX_SW_BUFFER) + /* Add one element to the buffer to receive full packet. One byte in receive buffer is always empty */ + volatile uint8 UART_rxBufferInternal[UART_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_RX_SW_BUFFER) */ + +#if(UART_INTERNAL_TX_SW_BUFFER) + volatile uint8 UART_txBufferInternal[UART_TX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_TX_SW_BUFFER) */ + + +#if(UART_RX_DIRECTION) + /******************************************************************************* + * Function Name: UART_SpiUartReadRxData + ****************************************************************************//** + * + * Retrieves the next data element from the receive buffer. + * - RX software buffer is disabled: Returns data element retrieved from + * RX FIFO. Undefined data will be returned if the RX FIFO is empty. + * - RX software buffer is enabled: Returns data element from the software + * receive buffer. Zero value is returned if the software receive buffer + * is empty. + * + * \return + * Next data element from the receive buffer. + * The amount of data bits to be received depends on RX data bits selection + * (the data bit counting starts from LSB of return value). + * + * \globalvars + * UART_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 UART_SpiUartReadRxData(void) + { + uint32 rxData = 0u; + + #if (UART_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_RX_SW_BUFFER) + { + if (UART_rxBufferHead != UART_rxBufferTail) + { + /* There is data in RX software buffer */ + + /* Calculate index to read from */ + locTail = (UART_rxBufferTail + 1u); + + if (UART_INTERNAL_RX_BUFFER_SIZE == locTail) + { + locTail = 0u; + } + + /* Get data from RX software buffer */ + rxData = UART_GetWordFromRxBuffer(locTail); + + /* Change index in the buffer */ + UART_rxBufferTail = locTail; + + #if (UART_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Check if RX Not Empty is disabled in the interrupt */ + if (0u == (UART_INTR_RX_MASK_REG & UART_INTR_RX_NOT_EMPTY)) + { + /* Enable RX Not Empty interrupt source to continue + * receiving data into software buffer. + */ + UART_INTR_RX_MASK_REG |= UART_INTR_RX_NOT_EMPTY; + } + } + #endif + + } + } + #else + { + /* Read data from RX FIFO */ + rxData = UART_RX_FIFO_RD_REG; + } + #endif + + return (rxData); + } + + + /******************************************************************************* + * Function Name: UART_SpiUartGetRxBufferSize + ****************************************************************************//** + * + * Returns the number of received data elements in the receive buffer. + * - RX software buffer disabled: returns the number of used entries in + * RX FIFO. + * - RX software buffer enabled: returns the number of elements which were + * placed in the receive buffer. This does not include the hardware RX FIFO. + * + * \return + * Number of received data elements. + * + * \globalvars + * UART_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 UART_SpiUartGetRxBufferSize(void) + { + uint32 size; + #if (UART_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_RX_SW_BUFFER) + { + locHead = UART_rxBufferHead; + + if(locHead >= UART_rxBufferTail) + { + size = (locHead - UART_rxBufferTail); + } + else + { + size = (locHead + (UART_INTERNAL_RX_BUFFER_SIZE - UART_rxBufferTail)); + } + } + #else + { + size = UART_GET_RX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: UART_SpiUartClearRxBuffer + ****************************************************************************//** + * + * Clears the receive buffer and RX FIFO. + * + * \globalvars + * UART_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + void UART_SpiUartClearRxBuffer(void) + { + #if (UART_CHECK_RX_SW_BUFFER) + { + /* Lock from component interruption */ + UART_DisableInt(); + + /* Flush RX software buffer */ + UART_rxBufferHead = UART_rxBufferTail; + UART_rxBufferOverflow = 0u; + + UART_CLEAR_RX_FIFO; + UART_ClearRxInterruptSource(UART_INTR_RX_ALL); + + #if (UART_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Enable RX Not Empty interrupt source to continue receiving + * data into software buffer. + */ + UART_INTR_RX_MASK_REG |= UART_INTR_RX_NOT_EMPTY; + } + #endif + + /* Release lock */ + UART_EnableInt(); + } + #else + { + UART_CLEAR_RX_FIFO; + } + #endif + } + +#endif /* (UART_RX_DIRECTION) */ + + +#if(UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_SpiUartWriteTxData + ****************************************************************************//** + * + * Places a data entry into the transmit buffer to be sent at the next available + * bus time. + * This function is blocking and waits until there is space available to put the + * requested data in the transmit buffer. + * + * \param txDataByte: the data to be transmitted. + * The amount of data bits to be transmitted depends on TX data bits selection + * (the data bit counting starts from LSB of txDataByte). + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_SpiUartWriteTxData(uint32 txData) + { + #if (UART_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_TX_SW_BUFFER) + { + /* Put data directly into the TX FIFO */ + if ((UART_txBufferHead == UART_txBufferTail) && + (UART_SPI_UART_FIFO_SIZE != UART_GET_TX_FIFO_ENTRIES)) + { + /* TX software buffer is empty: put data directly in TX FIFO */ + UART_TX_FIFO_WR_REG = txData; + } + /* Put data into TX software buffer */ + else + { + /* Head index to put data */ + locHead = (UART_txBufferHead + 1u); + + /* Adjust TX software buffer index */ + if (UART_TX_BUFFER_SIZE == locHead) + { + locHead = 0u; + } + + /* Wait for space in TX software buffer */ + while (locHead == UART_txBufferTail) + { + } + + /* TX software buffer has at least one room */ + + /* Clear old status of INTR_TX_NOT_FULL. It sets at the end of transfer when TX FIFO is empty. */ + UART_ClearTxInterruptSource(UART_INTR_TX_NOT_FULL); + + UART_PutWordInTxBuffer(locHead, txData); + + UART_txBufferHead = locHead; + + /* Check if TX Not Full is disabled in interrupt */ + if (0u == (UART_INTR_TX_MASK_REG & UART_INTR_TX_NOT_FULL)) + { + /* Enable TX Not Full interrupt source to transmit from software buffer */ + UART_INTR_TX_MASK_REG |= (uint32) UART_INTR_TX_NOT_FULL; + } + } + } + #else + { + /* Wait until TX FIFO has space to put data element */ + while (UART_SPI_UART_FIFO_SIZE == UART_GET_TX_FIFO_ENTRIES) + { + } + + UART_TX_FIFO_WR_REG = txData; + } + #endif + } + + + /******************************************************************************* + * Function Name: UART_SpiUartPutArray + ****************************************************************************//** + * + * Places an array of data into the transmit buffer to be sent. + * This function is blocking and waits until there is a space available to put + * all the requested data in the transmit buffer. The array size can be greater + * than transmit buffer size. + * + * \param wrBuf: pointer to an array of data to be placed in transmit buffer. + * The width of the data to be transmitted depends on TX data width selection + * (the data bit counting starts from LSB for each array element). + * \param count: number of data elements to be placed in the transmit buffer. + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_SpiUartPutArray(const uint8 wrBuf[], uint32 count) + { + uint32 i; + + for (i=0u; i < count; i++) + { + UART_SpiUartWriteTxData((uint32) wrBuf[i]); + } + } + + + /******************************************************************************* + * Function Name: UART_SpiUartGetTxBufferSize + ****************************************************************************//** + * + * Returns the number of elements currently in the transmit buffer. + * - TX software buffer is disabled: returns the number of used entries in + * TX FIFO. + * - TX software buffer is enabled: returns the number of elements currently + * used in the transmit buffer. This number does not include used entries in + * the TX FIFO. The transmit buffer size is zero until the TX FIFO is + * not full. + * + * \return + * Number of data elements ready to transmit. + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + uint32 UART_SpiUartGetTxBufferSize(void) + { + uint32 size; + #if (UART_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_TX_SW_BUFFER) + { + /* Get current Tail index */ + locTail = UART_txBufferTail; + + if (UART_txBufferHead >= locTail) + { + size = (UART_txBufferHead - locTail); + } + else + { + size = (UART_txBufferHead + (UART_TX_BUFFER_SIZE - locTail)); + } + } + #else + { + size = UART_GET_TX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: UART_SpiUartClearTxBuffer + ****************************************************************************//** + * + * Clears the transmit buffer and TX FIFO. + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_SpiUartClearTxBuffer(void) + { + #if (UART_CHECK_TX_SW_BUFFER) + { + /* Lock from component interruption */ + UART_DisableInt(); + + /* Flush TX software buffer */ + UART_txBufferHead = UART_txBufferTail; + + UART_INTR_TX_MASK_REG &= (uint32) ~UART_INTR_TX_NOT_FULL; + UART_CLEAR_TX_FIFO; + UART_ClearTxInterruptSource(UART_INTR_TX_ALL); + + /* Release lock */ + UART_EnableInt(); + } + #else + { + UART_CLEAR_TX_FIFO; + } + #endif + } + +#endif /* (UART_TX_DIRECTION) */ + + +/******************************************************************************* +* Function Name: UART_SpiUartDisableIntRx +****************************************************************************//** +* +* Disables the RX interrupt sources. +* +* \return +* Returns the RX interrupt sources enabled before the function call. +* +*******************************************************************************/ +uint32 UART_SpiUartDisableIntRx(void) +{ + uint32 intSource; + + intSource = UART_GetRxInterruptMode(); + + UART_SetRxInterruptMode(UART_NO_INTR_SOURCES); + + return (intSource); +} + + +/******************************************************************************* +* Function Name: UART_SpiUartDisableIntTx +****************************************************************************//** +* +* Disables TX interrupt sources. +* +* \return +* Returns TX interrupt sources enabled before function call. +* +*******************************************************************************/ +uint32 UART_SpiUartDisableIntTx(void) +{ + uint32 intSourceMask; + + intSourceMask = UART_GetTxInterruptMode(); + + UART_SetTxInterruptMode(UART_NO_INTR_SOURCES); + + return (intSourceMask); +} + + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: UART_PutWordInRxBuffer + ****************************************************************************//** + * + * Stores a byte/word into the RX buffer. + * Only available in the Unconfigured operation mode. + * + * \param index: index to store data byte/word in the RX buffer. + * \param rxDataByte: byte/word to store. + * + *******************************************************************************/ + void UART_PutWordInRxBuffer(uint32 idx, uint32 rxDataByte) + { + /* Put data in buffer */ + if (UART_ONE_BYTE_WIDTH == UART_rxDataBits) + { + UART_rxBuffer[idx] = ((uint8) rxDataByte); + } + else + { + UART_rxBuffer[(uint32)(idx << 1u)] = LO8(LO16(rxDataByte)); + UART_rxBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(rxDataByte)); + } + } + + + /******************************************************************************* + * Function Name: UART_GetWordFromRxBuffer + ****************************************************************************//** + * + * Reads byte/word from RX buffer. + * Only available in the Unconfigured operation mode. + * + * \return + * Returns byte/word read from RX buffer. + * + *******************************************************************************/ + uint32 UART_GetWordFromRxBuffer(uint32 idx) + { + uint32 value; + + if (UART_ONE_BYTE_WIDTH == UART_rxDataBits) + { + value = UART_rxBuffer[idx]; + } + else + { + value = (uint32) UART_rxBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32)UART_rxBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + + + /******************************************************************************* + * Function Name: UART_PutWordInTxBuffer + ****************************************************************************//** + * + * Stores byte/word into the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to store data byte/word in the TX buffer. + * \param txDataByte: byte/word to store. + * + *******************************************************************************/ + void UART_PutWordInTxBuffer(uint32 idx, uint32 txDataByte) + { + /* Put data in buffer */ + if (UART_ONE_BYTE_WIDTH == UART_txDataBits) + { + UART_txBuffer[idx] = ((uint8) txDataByte); + } + else + { + UART_txBuffer[(uint32)(idx << 1u)] = LO8(LO16(txDataByte)); + UART_txBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(txDataByte)); + } + } + + + /******************************************************************************* + * Function Name: UART_GetWordFromTxBuffer + ****************************************************************************//** + * + * Reads byte/word from the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to get data byte/word from the TX buffer. + * + * \return + * Returns byte/word read from the TX buffer. + * + *******************************************************************************/ + uint32 UART_GetWordFromTxBuffer(uint32 idx) + { + uint32 value; + + if (UART_ONE_BYTE_WIDTH == UART_txDataBits) + { + value = (uint32) UART_txBuffer[idx]; + } + else + { + value = (uint32) UART_txBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32) UART_txBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART.h new file mode 100644 index 0000000..3e2b602 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART.h @@ -0,0 +1,1231 @@ +/***************************************************************************//** +* \file UART_SPI_UART.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_SPI_UART_UART_H) +#define CY_SCB_SPI_UART_UART_H + +#include "UART.h" + + +/*************************************** +* SPI Initial Parameter Constants +****************************************/ + +#define UART_SPI_MODE (0u) +#define UART_SPI_SUB_MODE (0u) +#define UART_SPI_CLOCK_MODE (0u) +#define UART_SPI_OVS_FACTOR (16u) +#define UART_SPI_MEDIAN_FILTER_ENABLE (0u) +#define UART_SPI_LATE_MISO_SAMPLE_ENABLE (0u) +#define UART_SPI_RX_DATA_BITS_NUM (8u) +#define UART_SPI_TX_DATA_BITS_NUM (8u) +#define UART_SPI_WAKE_ENABLE (0u) +#define UART_SPI_BITS_ORDER (1u) +#define UART_SPI_TRANSFER_SEPARATION (1u) +#define UART_SPI_NUMBER_OF_SS_LINES (1u) +#define UART_SPI_RX_BUFFER_SIZE (8u) +#define UART_SPI_TX_BUFFER_SIZE (8u) + +#define UART_SPI_INTERRUPT_MODE (1u) + +#define UART_SPI_INTR_RX_MASK (0x0u) +#define UART_SPI_INTR_TX_MASK (0x0u) + +#define UART_SPI_RX_TRIGGER_LEVEL (7u) +#define UART_SPI_TX_TRIGGER_LEVEL (0u) + +#define UART_SPI_BYTE_MODE_ENABLE (0u) +#define UART_SPI_FREE_RUN_SCLK_ENABLE (0u) +#define UART_SPI_SS0_POLARITY (0u) +#define UART_SPI_SS1_POLARITY (0u) +#define UART_SPI_SS2_POLARITY (0u) +#define UART_SPI_SS3_POLARITY (0u) + + +/*************************************** +* UART Initial Parameter Constants +****************************************/ + +#define UART_UART_SUB_MODE (0u) +#define UART_UART_DIRECTION (2u) +#define UART_UART_DATA_BITS_NUM (8u) +#define UART_UART_PARITY_TYPE (2u) +#define UART_UART_STOP_BITS_NUM (2u) +#define UART_UART_OVS_FACTOR (8u) +#define UART_UART_IRDA_LOW_POWER (0u) +#define UART_UART_MEDIAN_FILTER_ENABLE (0u) +#define UART_UART_RETRY_ON_NACK (0u) +#define UART_UART_IRDA_POLARITY (0u) +#define UART_UART_DROP_ON_FRAME_ERR (0u) +#define UART_UART_DROP_ON_PARITY_ERR (0u) +#define UART_UART_WAKE_ENABLE (0u) +#define UART_UART_RX_BUFFER_SIZE (8u) +#define UART_UART_TX_BUFFER_SIZE (8u) +#define UART_UART_MP_MODE_ENABLE (0u) +#define UART_UART_MP_ACCEPT_ADDRESS (0u) +#define UART_UART_MP_RX_ADDRESS (0x2u) +#define UART_UART_MP_RX_ADDRESS_MASK (0xFFu) + +#define UART_UART_INTERRUPT_MODE (0u) + +#define UART_UART_INTR_RX_MASK (0x0u) +#define UART_UART_INTR_TX_MASK (0x0u) + +#define UART_UART_RX_TRIGGER_LEVEL (7u) +#define UART_UART_TX_TRIGGER_LEVEL (0u) + +#define UART_UART_BYTE_MODE_ENABLE (0u) +#define UART_UART_CTS_ENABLE (0u) +#define UART_UART_CTS_POLARITY (0u) +#define UART_UART_RTS_ENABLE (0u) +#define UART_UART_RTS_POLARITY (0u) +#define UART_UART_RTS_FIFO_LEVEL (4u) + +#define UART_UART_RX_BREAK_WIDTH (11u) + +/* SPI mode enum */ +#define UART_SPI_SLAVE (0u) +#define UART_SPI_MASTER (1u) + +/* UART direction enum */ +#define UART_UART_RX (1u) +#define UART_UART_TX (2u) +#define UART_UART_TX_RX (3u) + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + /* Mode */ + #define UART_SPI_SLAVE_CONST (1u) + #define UART_SPI_MASTER_CONST (1u) + + /* Direction */ + #define UART_RX_DIRECTION (1u) + #define UART_TX_DIRECTION (1u) + #define UART_UART_RX_DIRECTION (1u) + #define UART_UART_TX_DIRECTION (1u) + + /* Only external RX and TX buffer for Uncofigured mode */ + #define UART_INTERNAL_RX_SW_BUFFER (0u) + #define UART_INTERNAL_TX_SW_BUFFER (0u) + + /* Get RX and TX buffer size */ + #define UART_INTERNAL_RX_BUFFER_SIZE (UART_rxBufferSize + 1u) + #define UART_RX_BUFFER_SIZE (UART_rxBufferSize) + #define UART_TX_BUFFER_SIZE (UART_txBufferSize) + + /* Return true if buffer is provided */ + #define UART_CHECK_RX_SW_BUFFER (NULL != UART_rxBuffer) + #define UART_CHECK_TX_SW_BUFFER (NULL != UART_txBuffer) + + /* Always provide global variables to support RX and TX buffers */ + #define UART_INTERNAL_RX_SW_BUFFER_CONST (1u) + #define UART_INTERNAL_TX_SW_BUFFER_CONST (1u) + + /* Get wakeup enable option */ + #define UART_SPI_WAKE_ENABLE_CONST (1u) + #define UART_UART_WAKE_ENABLE_CONST (1u) + #define UART_CHECK_SPI_WAKE_ENABLE ((0u != UART_scbEnableWake) && UART_SCB_MODE_SPI_RUNTM_CFG) + #define UART_CHECK_UART_WAKE_ENABLE ((0u != UART_scbEnableWake) && UART_SCB_MODE_UART_RUNTM_CFG) + + /* SPI/UART: TX or RX FIFO size */ + #if (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_SPI_UART_FIFO_SIZE (UART_FIFO_SIZE) + #define UART_CHECK_UART_RTS_CONTROL_FLOW (0u) + #else + #define UART_SPI_UART_FIFO_SIZE (UART_GET_FIFO_SIZE(UART_CTRL_REG & \ + UART_CTRL_BYTE_MODE)) + + #define UART_CHECK_UART_RTS_CONTROL_FLOW \ + ((UART_SCB_MODE_UART_RUNTM_CFG) && \ + (0u != UART_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(UART_UART_FLOW_CTRL_REG))) + #endif /* (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#else + + /* Internal RX and TX buffer: for SPI or UART */ + #if (UART_SCB_MODE_SPI_CONST_CFG) + + /* SPI Direction */ + #define UART_SPI_RX_DIRECTION (1u) + #define UART_SPI_TX_DIRECTION (1u) + + /* Get FIFO size */ + #define UART_SPI_UART_FIFO_SIZE UART_GET_FIFO_SIZE(UART_SPI_BYTE_MODE_ENABLE) + + /* SPI internal RX and TX buffers */ + #define UART_INTERNAL_SPI_RX_SW_BUFFER (UART_SPI_RX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + #define UART_INTERNAL_SPI_TX_SW_BUFFER (UART_SPI_TX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + + /* Internal SPI RX and TX buffer */ + #define UART_INTERNAL_RX_SW_BUFFER (UART_INTERNAL_SPI_RX_SW_BUFFER) + #define UART_INTERNAL_TX_SW_BUFFER (UART_INTERNAL_SPI_TX_SW_BUFFER) + + /* Internal SPI RX and TX buffer size */ + #define UART_INTERNAL_RX_BUFFER_SIZE (UART_SPI_RX_BUFFER_SIZE + 1u) + #define UART_RX_BUFFER_SIZE (UART_SPI_RX_BUFFER_SIZE) + #define UART_TX_BUFFER_SIZE (UART_SPI_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define UART_SPI_WAKE_ENABLE_CONST (0u != UART_SPI_WAKE_ENABLE) + #define UART_UART_WAKE_ENABLE_CONST (0u) + + #else + + /* UART Direction */ + #define UART_UART_RX_DIRECTION (0u != (UART_UART_DIRECTION & UART_UART_RX)) + #define UART_UART_TX_DIRECTION (0u != (UART_UART_DIRECTION & UART_UART_TX)) + + /* Get FIFO size */ + #define UART_SPI_UART_FIFO_SIZE UART_GET_FIFO_SIZE(UART_UART_BYTE_MODE_ENABLE) + + /* UART internal RX and TX buffers */ + #define UART_INTERNAL_UART_RX_SW_BUFFER (UART_UART_RX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + #define UART_INTERNAL_UART_TX_SW_BUFFER (UART_UART_TX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + + /* Internal UART RX and TX buffer */ + #define UART_INTERNAL_RX_SW_BUFFER (UART_INTERNAL_UART_RX_SW_BUFFER) + #define UART_INTERNAL_TX_SW_BUFFER (UART_INTERNAL_UART_TX_SW_BUFFER) + + /* Internal UART RX and TX buffer size */ + #define UART_INTERNAL_RX_BUFFER_SIZE (UART_UART_RX_BUFFER_SIZE + 1u) + #define UART_RX_BUFFER_SIZE (UART_UART_RX_BUFFER_SIZE) + #define UART_TX_BUFFER_SIZE (UART_UART_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define UART_SPI_WAKE_ENABLE_CONST (0u) + #define UART_UART_WAKE_ENABLE_CONST (0u != UART_UART_WAKE_ENABLE) + + #endif /* (UART_SCB_MODE_SPI_CONST_CFG) */ + + /* Mode */ + #define UART_SPI_SLAVE_CONST (UART_SPI_MODE == UART_SPI_SLAVE) + #define UART_SPI_MASTER_CONST (UART_SPI_MODE == UART_SPI_MASTER) + + /* Direction */ + #define UART_RX_DIRECTION ((UART_SCB_MODE_SPI_CONST_CFG) ? \ + (UART_SPI_RX_DIRECTION) : (UART_UART_RX_DIRECTION)) + + #define UART_TX_DIRECTION ((UART_SCB_MODE_SPI_CONST_CFG) ? \ + (UART_SPI_TX_DIRECTION) : (UART_UART_TX_DIRECTION)) + + /* Internal RX and TX buffer: for SPI or UART. Used in conditional compilation check */ + #define UART_CHECK_RX_SW_BUFFER (UART_INTERNAL_RX_SW_BUFFER) + #define UART_CHECK_TX_SW_BUFFER (UART_INTERNAL_TX_SW_BUFFER) + + /* Provide global variables to support RX and TX buffers */ + #define UART_INTERNAL_RX_SW_BUFFER_CONST (UART_INTERNAL_RX_SW_BUFFER) + #define UART_INTERNAL_TX_SW_BUFFER_CONST (UART_INTERNAL_TX_SW_BUFFER) + + /* Wake up enable */ + #define UART_CHECK_SPI_WAKE_ENABLE (UART_SPI_WAKE_ENABLE_CONST) + #define UART_CHECK_UART_WAKE_ENABLE (UART_UART_WAKE_ENABLE_CONST) + + /* UART flow control: not applicable for CY_SCBIP_V0 || CY_SCBIP_V1 */ + #define UART_CHECK_UART_RTS_CONTROL_FLOW (UART_SCB_MODE_UART_CONST_CFG && \ + UART_UART_RTS_ENABLE) + +#endif /* End (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* UART_SPI_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for SPI. The following defines are available choices: + * - UART_SPI_SLAVE + * - UART_SPI_MASTE + */ + uint32 mode; + + /** Submode of operation for SPI. The following defines are available + * choices: + * - UART_SPI_MODE_MOTOROLA + * - UART_SPI_MODE_TI_COINCIDES + * - UART_SPI_MODE_TI_PRECEDES + * - UART_SPI_MODE_NATIONAL + */ + uint32 submode; + + /** Determines the sclk relationship for Motorola submode. Ignored + * for other submodes. The following defines are available choices: + * - UART_SPI_SCLK_CPHA0_CPOL0 + * - UART_SPI_SCLK_CPHA0_CPOL1 + * - UART_SPI_SCLK_CPHA1_CPOL0 + * - UART_SPI_SCLK_CPHA1_CPOL1 + */ + uint32 sclkMode; + + /** Oversampling factor for the SPI clock. Ignored for Slave mode operation. + */ + uint32 oversample; + + /** Applies median filter on the input lines: 0 – not applied, 1 – applied. + */ + uint32 enableMedianFilter; + + /** Applies late sampling of MISO line: 0 – not applied, 1 – applied. + * Ignored for slave mode. + */ + uint32 enableLateSampling; + + /** Enables wakeup from low power mode: 0 – disable, 1 – enable. + * Ignored for master mode. + */ + uint32 enableWake; + + /** Number of data bits for RX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 rxDataBits; + + /** Number of data bits for TX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 txDataBits; + + /** Determines the bit ordering. The following defines are available + * choices: + * - UART_BITS_ORDER_LSB_FIRST + * - UART_BITS_ORDER_MSB_FIRST + */ + uint32 bitOrder; + + /** Determines whether transfers are back to back or have SS disabled + * between words. Ignored for slave mode. The following defines are + * available choices: + * - UART_SPI_TRANSFER_CONTINUOUS + * - UART_SPI_TRANSFER_SEPARATED + */ + uint32 transferSeperation; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The UART_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables component interrupt: 0 – disable, 1 – enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of enabled interrupt sources for the RX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_RX_FIFO_LEVEL + * - UART_INTR_RX_NOT_EMPTY + * - UART_INTR_RX_FULL + * - UART_INTR_RX_OVERFLOW + * - UART_INTR_RX_UNDERFLOW + * - UART_INTR_SLAVE_SPI_BUS_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of enabled interrupt sources for the TX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_TX_FIFO_LEVEL + * - UART_INTR_TX_NOT_FULL + * - UART_INTR_TX_EMPTY + * - UART_INTR_TX_OVERFLOW + * - UART_INTR_TX_UNDERFLOW + * - UART_INTR_MASTER_SPI_DONE + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 – disable, 1 – enable. This implies that number of + * TX and RX data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables continuous SCLK generation by the SPI master: 0 – disable, + * 1 – enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableFreeRunSclk; + + /** Active polarity of slave select lines 0-3. This is bit mask where bit + * UART_SPI_SLAVE_SELECT0 corresponds to slave select 0 + * polarity, bit UART_SPI_SLAVE_SELECT1 – slave select 1 + * polarity and so on. Polarity constants are: + * - UART_SPI_SS_ACTIVE_LOW + * - UART_SPI_SS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 polaritySs; +} UART_SPI_INIT_STRUCT; + + +/* UART_UART_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for the UART. The following defines are available + * choices: + * - UART_UART_MODE_STD + * - UART_UART_MODE_SMARTCARD + * - UART_UART_MODE_IRDA + */ + uint32 mode; + + /** Direction of operation for the UART. The following defines are available + * choices: + * - UART_UART_TX_RX + * - UART_UART_RX + * - UART_UART_TX + */ + uint32 direction; + + /** Number of data bits. + */ + uint32 dataBits; + + /** Determines the parity. The following defines are available choices: + * - UART_UART_PARITY_EVEN + * - UART_UART_PARITY_ODD + * - UART_UART_PARITY_NONE + */ + uint32 parity; + + /** Determines the number of stop bits. The following defines are available + * choices: + * - UART_UART_STOP_BITS_1 + * - UART_UART_STOP_BITS_1_5 + * - UART_UART_STOP_BITS_2 + */ + uint32 stopBits; + + /** Oversampling factor for the UART. + * + * Note The oversampling factor values are changed when enableIrdaLowPower + * is enabled: + * - UART_UART_IRDA_LP_OVS16 + * - UART_UART_IRDA_LP_OVS32 + * - UART_UART_IRDA_LP_OVS48 + * - UART_UART_IRDA_LP_OVS96 + * - UART_UART_IRDA_LP_OVS192 + * - UART_UART_IRDA_LP_OVS768 + * - UART_UART_IRDA_LP_OVS1536 + */ + uint32 oversample; + + /** Enables IrDA low power RX mode operation: 0 – disable, 1 – enable. + * The TX functionality does not work when enabled. + */ + uint32 enableIrdaLowPower; + + /** Applies median filter on the input lines: 0 – not applied, 1 – applied. + */ + uint32 enableMedianFilter; + + /** Enables retry when NACK response was received: 0 – disable, 1 – enable. + * Only current content of TX FIFO is re-sent. + * Ignored for modes other than SmartCard. + */ + uint32 enableRetryNack; + + /** Inverts polarity of RX line: 0 – non-inverting, 1 – inverting. + * Ignored for modes other than IrDA. + */ + uint32 enableInvertedRx; + + /** Drop data from RX FIFO if parity error is detected: 0 – disable, + * 1 – enable. + */ + uint32 dropOnParityErr; + + /** Drop data from RX FIFO if a frame error is detected: 0 – disable, + * 1 – enable. + */ + uint32 dropOnFrameErr; + + /** Enables wakeup from low power mode: 0 – disable, 1 – enable. + * Ignored for modes other than standard UART. The RX functionality + * has to be enabled. + */ + uint32 enableWake; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The UART_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables multiprocessor mode: 0 – disable, 1 – enable. + */ + uint32 enableMultiproc; + + /** Enables matched address to be accepted: 0 – disable, 1 – enable. + */ + uint32 multiprocAcceptAddr; + + /** 8 bit address to match in Multiprocessor mode. Ignored for other modes. + */ + uint32 multiprocAddr; + + /** 8 bit mask of address bits that are compared for a Multiprocessor + * address match. Ignored for other modes. + * - Bit value 0 – excludes bit from address comparison. + * - Bit value 1 – the bit needs to match with the corresponding bit + * of the device address. + */ + uint32 multiprocAddrMask; + + /** Enables component interrupt: 0 – disable, 1 – enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of interrupt sources to enable in the RX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_RX_FIFO_LEVEL + * - UART_INTR_RX_NOT_EMPTY + * - UART_INTR_RX_FULL + * - UART_INTR_RX_OVERFLOW + * - UART_INTR_RX_UNDERFLOW + * - UART_INTR_RX_FRAME_ERROR + * - UART_INTR_RX_PARITY_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of interrupt sources to enable in the TX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_TX_FIFO_LEVEL + * - UART_INTR_TX_NOT_FULL + * - UART_INTR_TX_EMPTY + * - UART_INTR_TX_OVERFLOW + * - UART_INTR_TX_UNDERFLOW + * - UART_INTR_TX_UART_DONE + * - UART_INTR_TX_UART_NACK + * - UART_INTR_TX_UART_ARB_LOST + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 – disable, 1 – enable. This implies that number of + * Data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables usage of CTS input signal by the UART transmitter : 0 – disable, + * 1 – enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableCts; + + /** Sets active polarity of CTS input signal: + * - UART_UART_CTS_ACTIVE_LOW + * - UART_UART_CTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 ctsPolarity; + + /** RX FIFO level for RTS signal activation. While the RX FIFO has fewer + * entries than the RTS FIFO level value the RTS signal remains active, + * otherwise the RTS signal becomes inactive. By setting this field to 0, + * RTS signal activation is disabled. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsRxFifoLevel; + + /** Sets active polarity of RTS output signal: + * - UART_UART_RTS_ ACTIVE_LOW + * - UART_UART_RTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsPolarity; + + /** Configures the width of a break signal in that triggers the break + * detection interrupt source. A Break is a low level on the RX line. + * Valid range is 1-16 UART bits times. + */ + uint8 breakWidth; +} UART_UART_INIT_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_spi +* @{ +*/ +/* SPI specific functions */ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + void UART_SpiInit(const UART_SPI_INIT_STRUCT *config); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if(UART_SCB_MODE_SPI_INC) + /******************************************************************************* + * Function Name: UART_SpiIsBusBusy + ****************************************************************************//** + * + * Returns the current status on the bus. The bus status is determined using + * the slave select signal. + * - Motorola and National Semiconductor sub-modes: The bus is busy after + * the slave select line is activated and lasts until the slave select line + * is deactivated. + * - Texas Instrument sub-modes: The bus is busy at the moment of the initial + * pulse on the slave select line and lasts until the transfer is complete. + * If SPI Master is configured to use "Separated transfers" + * (see Continuous versus Separated Transfer Separation), the bus is busy + * during each element transfer and is free between each element transfer. + * The Master does not activate SS line immediately after data has been + * written into the TX FIFO. + * + * \return slaveSelect: Current status on the bus. + * If the returned value is nonzero, the bus is busy. + * If zero is returned, the bus is free. The bus status is determined using + * the slave select signal. + * + *******************************************************************************/ + #define UART_SpiIsBusBusy() ((uint32) (0u != (UART_SPI_STATUS_REG & \ + UART_SPI_STATUS_BUS_BUSY))) + + #if (UART_SPI_MASTER_CONST) + void UART_SpiSetActiveSlaveSelect(uint32 slaveSelect); + #endif /*(UART_SPI_MASTER_CONST) */ + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + void UART_SpiSetSlaveSelectPolarity(uint32 slaveSelect, uint32 polarity); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#endif /* (UART_SCB_MODE_SPI_INC) */ +/** @} spi */ + +/** +* \addtogroup group_uart +* @{ +*/ +/* UART specific functions */ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + void UART_UartInit(const UART_UART_INIT_STRUCT *config); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if(UART_SCB_MODE_UART_INC) + void UART_UartSetRxAddress(uint32 address); + void UART_UartSetRxAddressMask(uint32 addressMask); + + + /* UART RX direction APIs */ + #if(UART_UART_RX_DIRECTION) + uint32 UART_UartGetChar(void); + uint32 UART_UartGetByte(void); + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void UART_UartSetRtsPolarity(uint32 polarity); + void UART_UartSetRtsFifoLevel(uint32 level); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + #endif /* (UART_UART_RX_DIRECTION) */ + + /* UART TX direction APIs */ + #if(UART_UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_UartPutChar + ****************************************************************************//** + * + * Places a byte of data in the transmit buffer to be sent at the next available + * bus time. This function is blocking and waits until there is a space + * available to put requested data in the transmit buffer. + * For UART Multi Processor mode this function can send 9-bits data as well. + * Use UART_UART_MP_MARK to add a mark to create an address byte. + * + * \param txDataByte: the data to be transmitted. + * + *******************************************************************************/ + #define UART_UartPutChar(ch) UART_SpiUartWriteTxData((uint32)(ch)) + + void UART_UartPutString(const char8 string[]); + void UART_UartPutCRLF(uint32 txDataByte); + void UART_UartSendBreakBlocking(uint32 breakWidth); + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void UART_UartEnableCts(void); + void UART_UartDisableCts(void); + void UART_UartSetCtsPolarity(uint32 polarity); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + #endif /* (UART_UART_TX_DIRECTION) */ +#endif /* (UART_SCB_MODE_UART_INC) */ +/** @} uart */ + +/** +* \addtogroup group_spi_uart +* @{ +*/ +#if(UART_RX_DIRECTION) + uint32 UART_SpiUartReadRxData(void); + uint32 UART_SpiUartGetRxBufferSize(void); + void UART_SpiUartClearRxBuffer(void); +#endif /* (UART_RX_DIRECTION) */ + +/* Common APIs TX direction */ +#if(UART_TX_DIRECTION) + void UART_SpiUartWriteTxData(uint32 txData); + void UART_SpiUartPutArray(const uint8 wrBuf[], uint32 count); + uint32 UART_SpiUartGetTxBufferSize(void); + void UART_SpiUartClearTxBuffer(void); +#endif /* (UART_TX_DIRECTION) */ +/** @} spi_uart */ + +CY_ISR_PROTO(UART_SPI_UART_ISR); + +#if(UART_UART_RX_WAKEUP_IRQ) + CY_ISR_PROTO(UART_UART_WAKEUP_ISR); +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Buffer Access Macro Definitions +***************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* RX direction */ + void UART_PutWordInRxBuffer (uint32 idx, uint32 rxDataByte); + uint32 UART_GetWordFromRxBuffer(uint32 idx); + + /* TX direction */ + void UART_PutWordInTxBuffer (uint32 idx, uint32 txDataByte); + uint32 UART_GetWordFromTxBuffer(uint32 idx); + +#else + /* RX direction */ + #if(UART_INTERNAL_RX_SW_BUFFER_CONST) + #define UART_PutWordInRxBuffer(idx, rxDataByte) \ + do{ \ + UART_rxBufferInternal[(idx)] = ((uint8) (rxDataByte)); \ + }while(0) + + #define UART_GetWordFromRxBuffer(idx) UART_rxBufferInternal[(idx)] + + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + /* TX direction */ + #if(UART_INTERNAL_TX_SW_BUFFER_CONST) + #define UART_PutWordInTxBuffer(idx, txDataByte) \ + do{ \ + UART_txBufferInternal[(idx)] = ((uint8) (txDataByte)); \ + }while(0) + + #define UART_GetWordFromTxBuffer(idx) UART_txBufferInternal[(idx)] + + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#endif /* (UART_TX_SW_BUFFER_ENABLE) */ + + +/*************************************** +* SPI API Constants +***************************************/ + +/* SPI sub mode enum */ +#define UART_SPI_MODE_MOTOROLA (0x00u) +#define UART_SPI_MODE_TI_COINCIDES (0x01u) +#define UART_SPI_MODE_TI_PRECEDES (0x11u) +#define UART_SPI_MODE_NATIONAL (0x02u) +#define UART_SPI_MODE_MASK (0x03u) +#define UART_SPI_MODE_TI_PRECEDES_MASK (0x10u) +#define UART_SPI_MODE_NS_MICROWIRE (UART_SPI_MODE_NATIONAL) + +/* SPI phase and polarity mode enum */ +#define UART_SPI_SCLK_CPHA0_CPOL0 (0x00u) +#define UART_SPI_SCLK_CPHA0_CPOL1 (0x02u) +#define UART_SPI_SCLK_CPHA1_CPOL0 (0x01u) +#define UART_SPI_SCLK_CPHA1_CPOL1 (0x03u) + +/* SPI bits order enum */ +#define UART_BITS_ORDER_LSB_FIRST (0u) +#define UART_BITS_ORDER_MSB_FIRST (1u) + +/* SPI transfer separation enum */ +#define UART_SPI_TRANSFER_SEPARATED (0u) +#define UART_SPI_TRANSFER_CONTINUOUS (1u) + +/* SPI slave select constants */ +#define UART_SPI_SLAVE_SELECT0 (UART_SCB__SS0_POSISTION) +#define UART_SPI_SLAVE_SELECT1 (UART_SCB__SS1_POSISTION) +#define UART_SPI_SLAVE_SELECT2 (UART_SCB__SS2_POSISTION) +#define UART_SPI_SLAVE_SELECT3 (UART_SCB__SS3_POSISTION) + +/* SPI slave select polarity settings */ +#define UART_SPI_SS_ACTIVE_LOW (0u) +#define UART_SPI_SS_ACTIVE_HIGH (1u) + +#define UART_INTR_SPIM_TX_RESTORE (UART_INTR_TX_OVERFLOW) + +#define UART_INTR_SPIS_TX_RESTORE (UART_INTR_TX_OVERFLOW | \ + UART_INTR_TX_UNDERFLOW) + +/*************************************** +* UART API Constants +***************************************/ + +/* UART sub-modes enum */ +#define UART_UART_MODE_STD (0u) +#define UART_UART_MODE_SMARTCARD (1u) +#define UART_UART_MODE_IRDA (2u) + +/* UART direction enum */ +#define UART_UART_RX (1u) +#define UART_UART_TX (2u) +#define UART_UART_TX_RX (3u) + +/* UART parity enum */ +#define UART_UART_PARITY_EVEN (0u) +#define UART_UART_PARITY_ODD (1u) +#define UART_UART_PARITY_NONE (2u) + +/* UART stop bits enum */ +#define UART_UART_STOP_BITS_1 (2u) +#define UART_UART_STOP_BITS_1_5 (3u) +#define UART_UART_STOP_BITS_2 (4u) + +/* UART IrDA low power OVS enum */ +#define UART_UART_IRDA_LP_OVS16 (16u) +#define UART_UART_IRDA_LP_OVS32 (32u) +#define UART_UART_IRDA_LP_OVS48 (48u) +#define UART_UART_IRDA_LP_OVS96 (96u) +#define UART_UART_IRDA_LP_OVS192 (192u) +#define UART_UART_IRDA_LP_OVS768 (768u) +#define UART_UART_IRDA_LP_OVS1536 (1536u) + +/* Uart MP: mark (address) and space (data) bit definitions */ +#define UART_UART_MP_MARK (0x100u) +#define UART_UART_MP_SPACE (0x000u) + +/* UART CTS/RTS polarity settings */ +#define UART_UART_CTS_ACTIVE_LOW (0u) +#define UART_UART_CTS_ACTIVE_HIGH (1u) +#define UART_UART_RTS_ACTIVE_LOW (0u) +#define UART_UART_RTS_ACTIVE_HIGH (1u) + +/* Sources of RX errors */ +#define UART_INTR_RX_ERR (UART_INTR_RX_OVERFLOW | \ + UART_INTR_RX_UNDERFLOW | \ + UART_INTR_RX_FRAME_ERROR | \ + UART_INTR_RX_PARITY_ERROR) + +/* Shifted INTR_RX_ERR defines ONLY for UART_UartGetByte() */ +#define UART_UART_RX_OVERFLOW (UART_INTR_RX_OVERFLOW << 8u) +#define UART_UART_RX_UNDERFLOW (UART_INTR_RX_UNDERFLOW << 8u) +#define UART_UART_RX_FRAME_ERROR (UART_INTR_RX_FRAME_ERROR << 8u) +#define UART_UART_RX_PARITY_ERROR (UART_INTR_RX_PARITY_ERROR << 8u) +#define UART_UART_RX_ERROR_MASK (UART_UART_RX_OVERFLOW | \ + UART_UART_RX_UNDERFLOW | \ + UART_UART_RX_FRAME_ERROR | \ + UART_UART_RX_PARITY_ERROR) + +#define UART_INTR_UART_TX_RESTORE (UART_INTR_TX_OVERFLOW | \ + UART_INTR_TX_UART_NACK | \ + UART_INTR_TX_UART_DONE | \ + UART_INTR_TX_UART_ARB_LOST) + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + extern const UART_SPI_INIT_STRUCT UART_configSpi; + extern const UART_UART_INIT_STRUCT UART_configUart; +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) + extern uint8 UART_skipStart; +#endif /* (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Specific SPI Macro Definitions +***************************************/ + +#define UART_GET_SPI_INTR_SLAVE_MASK(sourceMask) ((sourceMask) & UART_INTR_SLAVE_SPI_BUS_ERROR) +#define UART_GET_SPI_INTR_MASTER_MASK(sourceMask) ((sourceMask) & UART_INTR_MASTER_SPI_DONE) +#define UART_GET_SPI_INTR_RX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~UART_INTR_SLAVE_SPI_BUS_ERROR) + +#define UART_GET_SPI_INTR_TX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~UART_INTR_MASTER_SPI_DONE) + + +/*************************************** +* Specific UART Macro Definitions +***************************************/ + +#define UART_UART_GET_CTRL_OVS_IRDA_LP(oversample) \ + ((UART_UART_IRDA_LP_OVS16 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS16 : \ + ((UART_UART_IRDA_LP_OVS32 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS32 : \ + ((UART_UART_IRDA_LP_OVS48 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS48 : \ + ((UART_UART_IRDA_LP_OVS96 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS96 : \ + ((UART_UART_IRDA_LP_OVS192 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS192 : \ + ((UART_UART_IRDA_LP_OVS768 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS768 : \ + ((UART_UART_IRDA_LP_OVS1536 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS1536 : \ + UART_CTRL_OVS_IRDA_LP_OVS16))))))) + +#define UART_GET_UART_RX_CTRL_ENABLED(direction) ((0u != (UART_UART_RX & (direction))) ? \ + (UART_RX_CTRL_ENABLED) : (0u)) + +#define UART_GET_UART_TX_CTRL_ENABLED(direction) ((0u != (UART_UART_TX & (direction))) ? \ + (UART_TX_CTRL_ENABLED) : (0u)) + + +/*************************************** +* SPI Register Settings +***************************************/ + +#define UART_CTRL_SPI (UART_CTRL_MODE_SPI) +#define UART_SPI_RX_CTRL (UART_RX_CTRL_ENABLED) +#define UART_SPI_TX_CTRL (UART_TX_CTRL_ENABLED) + + +/*************************************** +* SPI Init Register Settings +***************************************/ + +#define UART_SPI_SS_POLARITY \ + (((uint32) UART_SPI_SS0_POLARITY << UART_SPI_SLAVE_SELECT0) | \ + ((uint32) UART_SPI_SS1_POLARITY << UART_SPI_SLAVE_SELECT1) | \ + ((uint32) UART_SPI_SS2_POLARITY << UART_SPI_SLAVE_SELECT2) | \ + ((uint32) UART_SPI_SS3_POLARITY << UART_SPI_SLAVE_SELECT3)) + +#if(UART_SCB_MODE_SPI_CONST_CFG) + + /* SPI Configuration */ + #define UART_SPI_DEFAULT_CTRL \ + (UART_GET_CTRL_OVS(UART_SPI_OVS_FACTOR) | \ + UART_GET_CTRL_BYTE_MODE (UART_SPI_BYTE_MODE_ENABLE) | \ + UART_GET_CTRL_EC_AM_MODE(UART_SPI_WAKE_ENABLE) | \ + UART_CTRL_SPI) + + #define UART_SPI_DEFAULT_SPI_CTRL \ + (UART_GET_SPI_CTRL_CONTINUOUS (UART_SPI_TRANSFER_SEPARATION) | \ + UART_GET_SPI_CTRL_SELECT_PRECEDE(UART_SPI_SUB_MODE & \ + UART_SPI_MODE_TI_PRECEDES_MASK) | \ + UART_GET_SPI_CTRL_SCLK_MODE (UART_SPI_CLOCK_MODE) | \ + UART_GET_SPI_CTRL_LATE_MISO_SAMPLE(UART_SPI_LATE_MISO_SAMPLE_ENABLE) | \ + UART_GET_SPI_CTRL_SCLK_CONTINUOUS(UART_SPI_FREE_RUN_SCLK_ENABLE) | \ + UART_GET_SPI_CTRL_SSEL_POLARITY (UART_SPI_SS_POLARITY) | \ + UART_GET_SPI_CTRL_SUB_MODE (UART_SPI_SUB_MODE) | \ + UART_GET_SPI_CTRL_MASTER_MODE (UART_SPI_MODE)) + + /* RX direction */ + #define UART_SPI_DEFAULT_RX_CTRL \ + (UART_GET_RX_CTRL_DATA_WIDTH(UART_SPI_RX_DATA_BITS_NUM) | \ + UART_GET_RX_CTRL_BIT_ORDER (UART_SPI_BITS_ORDER) | \ + UART_GET_RX_CTRL_MEDIAN (UART_SPI_MEDIAN_FILTER_ENABLE) | \ + UART_SPI_RX_CTRL) + + #define UART_SPI_DEFAULT_RX_FIFO_CTRL \ + UART_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(UART_SPI_RX_TRIGGER_LEVEL) + + /* TX direction */ + #define UART_SPI_DEFAULT_TX_CTRL \ + (UART_GET_TX_CTRL_DATA_WIDTH(UART_SPI_TX_DATA_BITS_NUM) | \ + UART_GET_TX_CTRL_BIT_ORDER (UART_SPI_BITS_ORDER) | \ + UART_SPI_TX_CTRL) + + #define UART_SPI_DEFAULT_TX_FIFO_CTRL \ + UART_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(UART_SPI_TX_TRIGGER_LEVEL) + + /* Interrupt sources */ + #define UART_SPI_DEFAULT_INTR_SPI_EC_MASK (UART_NO_INTR_SOURCES) + + #define UART_SPI_DEFAULT_INTR_I2C_EC_MASK (UART_NO_INTR_SOURCES) + #define UART_SPI_DEFAULT_INTR_SLAVE_MASK \ + (UART_SPI_INTR_RX_MASK & UART_INTR_SLAVE_SPI_BUS_ERROR) + + #define UART_SPI_DEFAULT_INTR_MASTER_MASK \ + (UART_SPI_INTR_TX_MASK & UART_INTR_MASTER_SPI_DONE) + + #define UART_SPI_DEFAULT_INTR_RX_MASK \ + (UART_SPI_INTR_RX_MASK & (uint32) ~UART_INTR_SLAVE_SPI_BUS_ERROR) + + #define UART_SPI_DEFAULT_INTR_TX_MASK \ + (UART_SPI_INTR_TX_MASK & (uint32) ~UART_INTR_MASTER_SPI_DONE) + +#endif /* (UART_SCB_MODE_SPI_CONST_CFG) */ + + +/*************************************** +* UART Register Settings +***************************************/ + +#define UART_CTRL_UART (UART_CTRL_MODE_UART) +#define UART_UART_RX_CTRL (UART_RX_CTRL_LSB_FIRST) /* LSB for UART goes first */ +#define UART_UART_TX_CTRL (UART_TX_CTRL_LSB_FIRST) /* LSB for UART goes first */ + + +/*************************************** +* UART Init Register Settings +***************************************/ + +#if(UART_SCB_MODE_UART_CONST_CFG) + + /* UART configuration */ + #if(UART_UART_MODE_IRDA == UART_UART_SUB_MODE) + + #define UART_DEFAULT_CTRL_OVS ((0u != UART_UART_IRDA_LOW_POWER) ? \ + (UART_UART_GET_CTRL_OVS_IRDA_LP(UART_UART_OVS_FACTOR)) : \ + (UART_CTRL_OVS_IRDA_OVS16)) + + #else + + #define UART_DEFAULT_CTRL_OVS UART_GET_CTRL_OVS(UART_UART_OVS_FACTOR) + + #endif /* (UART_UART_MODE_IRDA == UART_UART_SUB_MODE) */ + + #define UART_UART_DEFAULT_CTRL \ + (UART_GET_CTRL_BYTE_MODE (UART_UART_BYTE_MODE_ENABLE) | \ + UART_GET_CTRL_ADDR_ACCEPT(UART_UART_MP_ACCEPT_ADDRESS) | \ + UART_DEFAULT_CTRL_OVS | \ + UART_CTRL_UART) + + #define UART_UART_DEFAULT_UART_CTRL \ + (UART_GET_UART_CTRL_MODE(UART_UART_SUB_MODE)) + + /* RX direction */ + #define UART_UART_DEFAULT_RX_CTRL_PARITY \ + ((UART_UART_PARITY_NONE != UART_UART_PARITY_TYPE) ? \ + (UART_GET_UART_RX_CTRL_PARITY(UART_UART_PARITY_TYPE) | \ + UART_UART_RX_CTRL_PARITY_ENABLED) : (0u)) + + #define UART_UART_DEFAULT_UART_RX_CTRL \ + (UART_GET_UART_RX_CTRL_MODE(UART_UART_STOP_BITS_NUM) | \ + UART_GET_UART_RX_CTRL_POLARITY(UART_UART_IRDA_POLARITY) | \ + UART_GET_UART_RX_CTRL_MP_MODE(UART_UART_MP_MODE_ENABLE) | \ + UART_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(UART_UART_DROP_ON_PARITY_ERR) | \ + UART_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(UART_UART_DROP_ON_FRAME_ERR) | \ + UART_GET_UART_RX_CTRL_BREAK_WIDTH(UART_UART_RX_BREAK_WIDTH) | \ + UART_UART_DEFAULT_RX_CTRL_PARITY) + + + #define UART_UART_DEFAULT_RX_CTRL \ + (UART_GET_RX_CTRL_DATA_WIDTH(UART_UART_DATA_BITS_NUM) | \ + UART_GET_RX_CTRL_MEDIAN (UART_UART_MEDIAN_FILTER_ENABLE) | \ + UART_GET_UART_RX_CTRL_ENABLED(UART_UART_DIRECTION)) + + #define UART_UART_DEFAULT_RX_FIFO_CTRL \ + UART_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(UART_UART_RX_TRIGGER_LEVEL) + + #define UART_UART_DEFAULT_RX_MATCH_REG ((0u != UART_UART_MP_MODE_ENABLE) ? \ + (UART_GET_RX_MATCH_ADDR(UART_UART_MP_RX_ADDRESS) | \ + UART_GET_RX_MATCH_MASK(UART_UART_MP_RX_ADDRESS_MASK)) : (0u)) + + /* TX direction */ + #define UART_UART_DEFAULT_TX_CTRL_PARITY (UART_UART_DEFAULT_RX_CTRL_PARITY) + + #define UART_UART_DEFAULT_UART_TX_CTRL \ + (UART_GET_UART_TX_CTRL_MODE(UART_UART_STOP_BITS_NUM) | \ + UART_GET_UART_TX_CTRL_RETRY_NACK(UART_UART_RETRY_ON_NACK) | \ + UART_UART_DEFAULT_TX_CTRL_PARITY) + + #define UART_UART_DEFAULT_TX_CTRL \ + (UART_GET_TX_CTRL_DATA_WIDTH(UART_UART_DATA_BITS_NUM) | \ + UART_GET_UART_TX_CTRL_ENABLED(UART_UART_DIRECTION)) + + #define UART_UART_DEFAULT_TX_FIFO_CTRL \ + UART_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(UART_UART_TX_TRIGGER_LEVEL) + + #define UART_UART_DEFAULT_FLOW_CTRL \ + (UART_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(UART_UART_RTS_FIFO_LEVEL) | \ + UART_GET_UART_FLOW_CTRL_RTS_POLARITY (UART_UART_RTS_POLARITY) | \ + UART_GET_UART_FLOW_CTRL_CTS_POLARITY (UART_UART_CTS_POLARITY) | \ + UART_GET_UART_FLOW_CTRL_CTS_ENABLE (UART_UART_CTS_ENABLE)) + + /* Interrupt sources */ + #define UART_UART_DEFAULT_INTR_I2C_EC_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_SPI_EC_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_SLAVE_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_MASTER_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_RX_MASK (UART_UART_INTR_RX_MASK) + #define UART_UART_DEFAULT_INTR_TX_MASK (UART_UART_INTR_TX_MASK) + +#endif /* (UART_SCB_MODE_UART_CONST_CFG) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +#define UART_SPIM_ACTIVE_SS0 (UART_SPI_SLAVE_SELECT0) +#define UART_SPIM_ACTIVE_SS1 (UART_SPI_SLAVE_SELECT1) +#define UART_SPIM_ACTIVE_SS2 (UART_SPI_SLAVE_SELECT2) +#define UART_SPIM_ACTIVE_SS3 (UART_SPI_SLAVE_SELECT3) + +#endif /* CY_SCB_SPI_UART_UART_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART_INT.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART_INT.c new file mode 100644 index 0000000..c7809b2 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART_INT.c @@ -0,0 +1,158 @@ +/***************************************************************************//** +* \file UART_SPI_UART_INT.c +* \version 4.0 +* +* \brief +* This file provides the source code to the Interrupt Service Routine for +* the SCB Component in SPI and UART modes. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" +#include "UART_SPI_UART_PVT.h" +#include "cyapicallbacks.h" + +#if (UART_SCB_IRQ_INTERNAL) +/******************************************************************************* +* Function Name: UART_SPI_UART_ISR +****************************************************************************//** +* +* Handles the Interrupt Service Routine for the SCB SPI or UART modes. +* +*******************************************************************************/ +CY_ISR(UART_SPI_UART_ISR) +{ +#if (UART_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locHead; +#endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if (UART_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locTail; +#endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#ifdef UART_SPI_UART_ISR_ENTRY_CALLBACK + UART_SPI_UART_ISR_EntryCallback(); +#endif /* UART_SPI_UART_ISR_ENTRY_CALLBACK */ + + if (NULL != UART_customIntrHandler) + { + UART_customIntrHandler(); + } + + #if(UART_CHECK_SPI_WAKE_ENABLE) + { + /* Clear SPI wakeup source */ + UART_ClearSpiExtClkInterruptSource(UART_INTR_SPI_EC_WAKE_UP); + } + #endif + + #if (UART_CHECK_RX_SW_BUFFER) + { + if (UART_CHECK_INTR_RX_MASKED(UART_INTR_RX_NOT_EMPTY)) + { + do + { + /* Move local head index */ + locHead = (UART_rxBufferHead + 1u); + + /* Adjust local head index */ + if (UART_INTERNAL_RX_BUFFER_SIZE == locHead) + { + locHead = 0u; + } + + if (locHead == UART_rxBufferTail) + { + #if (UART_CHECK_UART_RTS_CONTROL_FLOW) + { + /* There is no space in the software buffer - disable the + * RX Not Empty interrupt source. The data elements are + * still being received into the RX FIFO until the RTS signal + * stops the transmitter. After the data element is read from the + * buffer, the RX Not Empty interrupt source is enabled to + * move the next data element in the software buffer. + */ + UART_INTR_RX_MASK_REG &= ~UART_INTR_RX_NOT_EMPTY; + break; + } + #else + { + /* Overflow: through away received data element */ + (void) UART_RX_FIFO_RD_REG; + UART_rxBufferOverflow = (uint8) UART_INTR_RX_OVERFLOW; + } + #endif + } + else + { + /* Store received data */ + UART_PutWordInRxBuffer(locHead, UART_RX_FIFO_RD_REG); + + /* Move head index */ + UART_rxBufferHead = locHead; + } + } + while(0u != UART_GET_RX_FIFO_ENTRIES); + + UART_ClearRxInterruptSource(UART_INTR_RX_NOT_EMPTY); + } + } + #endif + + + #if (UART_CHECK_TX_SW_BUFFER) + { + if (UART_CHECK_INTR_TX_MASKED(UART_INTR_TX_NOT_FULL)) + { + do + { + /* Check for room in TX software buffer */ + if (UART_txBufferHead != UART_txBufferTail) + { + /* Move local tail index */ + locTail = (UART_txBufferTail + 1u); + + /* Adjust local tail index */ + if (UART_TX_BUFFER_SIZE == locTail) + { + locTail = 0u; + } + + /* Put data into TX FIFO */ + UART_TX_FIFO_WR_REG = UART_GetWordFromTxBuffer(locTail); + + /* Move tail index */ + UART_txBufferTail = locTail; + } + else + { + /* TX software buffer is empty: complete transfer */ + UART_DISABLE_INTR_TX(UART_INTR_TX_NOT_FULL); + break; + } + } + while (UART_SPI_UART_FIFO_SIZE != UART_GET_TX_FIFO_ENTRIES); + + UART_ClearTxInterruptSource(UART_INTR_TX_NOT_FULL); + } + } + #endif + +#ifdef UART_SPI_UART_ISR_EXIT_CALLBACK + UART_SPI_UART_ISR_ExitCallback(); +#endif /* UART_SPI_UART_ISR_EXIT_CALLBACK */ + +} + +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART_PVT.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART_PVT.h new file mode 100644 index 0000000..5d656ee --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_SPI_UART_PVT.h @@ -0,0 +1,117 @@ +/***************************************************************************//** +* \file UART_SPI_UART_PVT.h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component in SPI and UART modes. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_SPI_UART_PVT_UART_H) +#define CY_SCB_SPI_UART_PVT_UART_H + +#include "UART_SPI_UART.h" + + +/*************************************** +* Internal Global Vars +***************************************/ + +#if (UART_INTERNAL_RX_SW_BUFFER_CONST) + extern volatile uint32 UART_rxBufferHead; + extern volatile uint32 UART_rxBufferTail; + + /** + * \addtogroup group_globals + * @{ + */ + + /** Sets when internal software receive buffer overflow + * was occurred. + */ + extern volatile uint8 UART_rxBufferOverflow; + /** @} globals */ +#endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if (UART_INTERNAL_TX_SW_BUFFER_CONST) + extern volatile uint32 UART_txBufferHead; + extern volatile uint32 UART_txBufferTail; +#endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if (UART_INTERNAL_RX_SW_BUFFER) + extern volatile uint8 UART_rxBufferInternal[UART_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_RX_SW_BUFFER) */ + +#if (UART_INTERNAL_TX_SW_BUFFER) + extern volatile uint8 UART_txBufferInternal[UART_TX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_TX_SW_BUFFER) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +void UART_SpiPostEnable(void); +void UART_SpiStop(void); + +#if (UART_SCB_MODE_SPI_CONST_CFG) + void UART_SpiInit(void); +#endif /* (UART_SCB_MODE_SPI_CONST_CFG) */ + +#if (UART_SPI_WAKE_ENABLE_CONST) + void UART_SpiSaveConfig(void); + void UART_SpiRestoreConfig(void); +#endif /* (UART_SPI_WAKE_ENABLE_CONST) */ + +void UART_UartPostEnable(void); +void UART_UartStop(void); + +#if (UART_SCB_MODE_UART_CONST_CFG) + void UART_UartInit(void); +#endif /* (UART_SCB_MODE_UART_CONST_CFG) */ + +#if (UART_UART_WAKE_ENABLE_CONST) + void UART_UartSaveConfig(void); + void UART_UartRestoreConfig(void); +#endif /* (UART_UART_WAKE_ENABLE_CONST) */ + + +/*************************************** +* UART API Constants +***************************************/ + +/* UART RX and TX position to be used in UART_SetPins() */ +#define UART_UART_RX_PIN_ENABLE (UART_UART_RX) +#define UART_UART_TX_PIN_ENABLE (UART_UART_TX) + +/* UART RTS and CTS position to be used in UART_SetPins() */ +#define UART_UART_RTS_PIN_ENABLE (0x10u) +#define UART_UART_CTS_PIN_ENABLE (0x20u) + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Interrupt processing */ +#define UART_SpiUartEnableIntRx(intSourceMask) UART_SetRxInterruptMode(intSourceMask) +#define UART_SpiUartEnableIntTx(intSourceMask) UART_SetTxInterruptMode(intSourceMask) +uint32 UART_SpiUartDisableIntRx(void); +uint32 UART_SpiUartDisableIntTx(void); + + +#endif /* (CY_SCB_SPI_UART_PVT_UART_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_UART.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_UART.c new file mode 100644 index 0000000..0b7318e --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_UART.c @@ -0,0 +1,905 @@ +/***************************************************************************//** +* \file UART_UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* UART mode. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" +#include "UART_SPI_UART_PVT.h" +#include "cyapicallbacks.h" + +#if (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) + /** + * \addtogroup group_globals + * \{ + */ + /** This global variable determines whether to enable Skip Start + * functionality when UART_Sleep() function is called: + * 0 – disable, other values – enable. Default value is 1. + * It is only available when Enable wakeup from Deep Sleep Mode is enabled. + */ + uint8 UART_skipStart = 1u; + /** \} globals */ +#endif /* (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) */ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + /*************************************** + * Configuration Structure Initialization + ***************************************/ + + const UART_UART_INIT_STRUCT UART_configUart = + { + UART_UART_SUB_MODE, + UART_UART_DIRECTION, + UART_UART_DATA_BITS_NUM, + UART_UART_PARITY_TYPE, + UART_UART_STOP_BITS_NUM, + UART_UART_OVS_FACTOR, + UART_UART_IRDA_LOW_POWER, + UART_UART_MEDIAN_FILTER_ENABLE, + UART_UART_RETRY_ON_NACK, + UART_UART_IRDA_POLARITY, + UART_UART_DROP_ON_PARITY_ERR, + UART_UART_DROP_ON_FRAME_ERR, + UART_UART_WAKE_ENABLE, + 0u, + NULL, + 0u, + NULL, + UART_UART_MP_MODE_ENABLE, + UART_UART_MP_ACCEPT_ADDRESS, + UART_UART_MP_RX_ADDRESS, + UART_UART_MP_RX_ADDRESS_MASK, + (uint32) UART_SCB_IRQ_INTERNAL, + UART_UART_INTR_RX_MASK, + UART_UART_RX_TRIGGER_LEVEL, + UART_UART_INTR_TX_MASK, + UART_UART_TX_TRIGGER_LEVEL, + (uint8) UART_UART_BYTE_MODE_ENABLE, + (uint8) UART_UART_CTS_ENABLE, + (uint8) UART_UART_CTS_POLARITY, + (uint8) UART_UART_RTS_POLARITY, + (uint8) UART_UART_RTS_FIFO_LEVEL, + (uint8) UART_UART_RX_BREAK_WIDTH + }; + + + /******************************************************************************* + * Function Name: UART_UartInit + ****************************************************************************//** + * + * Configures the UART for UART operation. + * + * This function is intended specifically to be used when the UART + * configuration is set to “Unconfigured UART” in the customizer. + * After initializing the UART in UART mode using this function, + * the component can be enabled using the UART_Start() or + * UART_Enable() function. + * This function uses a pointer to a structure that provides the configuration + * settings. This structure contains the same information that would otherwise + * be provided by the customizer settings. + * + * \param config: pointer to a structure that contains the following list of + * fields. These fields match the selections available in the customizer. + * Refer to the customizer for further description of the settings. + * + *******************************************************************************/ + void UART_UartInit(const UART_UART_INIT_STRUCT *config) + { + uint32 pinsConfig; + + if (NULL == config) + { + CYASSERT(0u != 0u); /* Halt execution due to bad function parameter */ + } + else + { + /* Get direction to configure UART pins: TX, RX or TX+RX */ + pinsConfig = config->direction; + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* Add RTS and CTS pins to configure */ + pinsConfig |= (0u != config->rtsRxFifoLevel) ? (UART_UART_RTS_PIN_ENABLE) : (0u); + pinsConfig |= (0u != config->enableCts) ? (UART_UART_CTS_PIN_ENABLE) : (0u); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + /* Configure pins */ + UART_SetPins(UART_SCB_MODE_UART, config->mode, pinsConfig); + + /* Store internal configuration */ + UART_scbMode = (uint8) UART_SCB_MODE_UART; + UART_scbEnableWake = (uint8) config->enableWake; + UART_scbEnableIntr = (uint8) config->enableInterrupt; + + /* Set RX direction internal variables */ + UART_rxBuffer = config->rxBuffer; + UART_rxDataBits = (uint8) config->dataBits; + UART_rxBufferSize = config->rxBufferSize; + + /* Set TX direction internal variables */ + UART_txBuffer = config->txBuffer; + UART_txDataBits = (uint8) config->dataBits; + UART_txBufferSize = config->txBufferSize; + + /* Configure UART interface */ + if(UART_UART_MODE_IRDA == config->mode) + { + /* OVS settings: IrDA */ + UART_CTRL_REG = ((0u != config->enableIrdaLowPower) ? + (UART_UART_GET_CTRL_OVS_IRDA_LP(config->oversample)) : + (UART_CTRL_OVS_IRDA_OVS16)); + } + else + { + /* OVS settings: UART and SmartCard */ + UART_CTRL_REG = UART_GET_CTRL_OVS(config->oversample); + } + + UART_CTRL_REG |= UART_GET_CTRL_BYTE_MODE (config->enableByteMode) | + UART_GET_CTRL_ADDR_ACCEPT(config->multiprocAcceptAddr) | + UART_CTRL_UART; + + /* Configure sub-mode: UART, SmartCard or IrDA */ + UART_UART_CTRL_REG = UART_GET_UART_CTRL_MODE(config->mode); + + /* Configure RX direction */ + UART_UART_RX_CTRL_REG = UART_GET_UART_RX_CTRL_MODE(config->stopBits) | + UART_GET_UART_RX_CTRL_POLARITY(config->enableInvertedRx) | + UART_GET_UART_RX_CTRL_MP_MODE(config->enableMultiproc) | + UART_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(config->dropOnParityErr) | + UART_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(config->dropOnFrameErr) | + UART_GET_UART_RX_CTRL_BREAK_WIDTH(config->breakWidth); + + if(UART_UART_PARITY_NONE != config->parity) + { + UART_UART_RX_CTRL_REG |= UART_GET_UART_RX_CTRL_PARITY(config->parity) | + UART_UART_RX_CTRL_PARITY_ENABLED; + } + + UART_RX_CTRL_REG = UART_GET_RX_CTRL_DATA_WIDTH(config->dataBits) | + UART_GET_RX_CTRL_MEDIAN(config->enableMedianFilter) | + UART_GET_UART_RX_CTRL_ENABLED(config->direction); + + UART_RX_FIFO_CTRL_REG = UART_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(config->rxTriggerLevel); + + /* Configure MP address */ + UART_RX_MATCH_REG = UART_GET_RX_MATCH_ADDR(config->multiprocAddr) | + UART_GET_RX_MATCH_MASK(config->multiprocAddrMask); + + /* Configure RX direction */ + UART_UART_TX_CTRL_REG = UART_GET_UART_TX_CTRL_MODE(config->stopBits) | + UART_GET_UART_TX_CTRL_RETRY_NACK(config->enableRetryNack); + + if(UART_UART_PARITY_NONE != config->parity) + { + UART_UART_TX_CTRL_REG |= UART_GET_UART_TX_CTRL_PARITY(config->parity) | + UART_UART_TX_CTRL_PARITY_ENABLED; + } + + UART_TX_CTRL_REG = UART_GET_TX_CTRL_DATA_WIDTH(config->dataBits) | + UART_GET_UART_TX_CTRL_ENABLED(config->direction); + + UART_TX_FIFO_CTRL_REG = UART_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(config->txTriggerLevel); + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + UART_UART_FLOW_CTRL_REG = UART_GET_UART_FLOW_CTRL_CTS_ENABLE(config->enableCts) | \ + UART_GET_UART_FLOW_CTRL_CTS_POLARITY (config->ctsPolarity) | \ + UART_GET_UART_FLOW_CTRL_RTS_POLARITY (config->rtsPolarity) | \ + UART_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(config->rtsRxFifoLevel); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + /* Configure interrupt with UART handler but do not enable it */ + CyIntDisable (UART_ISR_NUMBER); + CyIntSetPriority(UART_ISR_NUMBER, UART_ISR_PRIORITY); + (void) CyIntSetVector(UART_ISR_NUMBER, &UART_SPI_UART_ISR); + + /* Configure WAKE interrupt */ + #if(UART_UART_RX_WAKEUP_IRQ) + CyIntDisable (UART_RX_WAKE_ISR_NUMBER); + CyIntSetPriority(UART_RX_WAKE_ISR_NUMBER, UART_RX_WAKE_ISR_PRIORITY); + (void) CyIntSetVector(UART_RX_WAKE_ISR_NUMBER, &UART_UART_WAKEUP_ISR); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + /* Configure interrupt sources */ + UART_INTR_I2C_EC_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_SPI_EC_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_SLAVE_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_MASTER_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_RX_MASK_REG = config->rxInterruptMask; + UART_INTR_TX_MASK_REG = config->txInterruptMask; + + /* Configure TX interrupt sources to restore. */ + UART_IntrTxMask = LO16(UART_INTR_TX_MASK_REG); + + /* Clear RX buffer indexes */ + UART_rxBufferHead = 0u; + UART_rxBufferTail = 0u; + UART_rxBufferOverflow = 0u; + + /* Clear TX buffer indexes */ + UART_txBufferHead = 0u; + UART_txBufferTail = 0u; + } + } + +#else + + /******************************************************************************* + * Function Name: UART_UartInit + ****************************************************************************//** + * + * Configures the SCB for the UART operation. + * + *******************************************************************************/ + void UART_UartInit(void) + { + /* Configure UART interface */ + UART_CTRL_REG = UART_UART_DEFAULT_CTRL; + + /* Configure sub-mode: UART, SmartCard or IrDA */ + UART_UART_CTRL_REG = UART_UART_DEFAULT_UART_CTRL; + + /* Configure RX direction */ + UART_UART_RX_CTRL_REG = UART_UART_DEFAULT_UART_RX_CTRL; + UART_RX_CTRL_REG = UART_UART_DEFAULT_RX_CTRL; + UART_RX_FIFO_CTRL_REG = UART_UART_DEFAULT_RX_FIFO_CTRL; + UART_RX_MATCH_REG = UART_UART_DEFAULT_RX_MATCH_REG; + + /* Configure TX direction */ + UART_UART_TX_CTRL_REG = UART_UART_DEFAULT_UART_TX_CTRL; + UART_TX_CTRL_REG = UART_UART_DEFAULT_TX_CTRL; + UART_TX_FIFO_CTRL_REG = UART_UART_DEFAULT_TX_FIFO_CTRL; + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + UART_UART_FLOW_CTRL_REG = UART_UART_DEFAULT_FLOW_CTRL; + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + /* Configure interrupt with UART handler but do not enable it */ + #if(UART_SCB_IRQ_INTERNAL) + CyIntDisable (UART_ISR_NUMBER); + CyIntSetPriority(UART_ISR_NUMBER, UART_ISR_PRIORITY); + (void) CyIntSetVector(UART_ISR_NUMBER, &UART_SPI_UART_ISR); + #endif /* (UART_SCB_IRQ_INTERNAL) */ + + /* Configure WAKE interrupt */ + #if(UART_UART_RX_WAKEUP_IRQ) + CyIntDisable (UART_RX_WAKE_ISR_NUMBER); + CyIntSetPriority(UART_RX_WAKE_ISR_NUMBER, UART_RX_WAKE_ISR_PRIORITY); + (void) CyIntSetVector(UART_RX_WAKE_ISR_NUMBER, &UART_UART_WAKEUP_ISR); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + /* Configure interrupt sources */ + UART_INTR_I2C_EC_MASK_REG = UART_UART_DEFAULT_INTR_I2C_EC_MASK; + UART_INTR_SPI_EC_MASK_REG = UART_UART_DEFAULT_INTR_SPI_EC_MASK; + UART_INTR_SLAVE_MASK_REG = UART_UART_DEFAULT_INTR_SLAVE_MASK; + UART_INTR_MASTER_MASK_REG = UART_UART_DEFAULT_INTR_MASTER_MASK; + UART_INTR_RX_MASK_REG = UART_UART_DEFAULT_INTR_RX_MASK; + UART_INTR_TX_MASK_REG = UART_UART_DEFAULT_INTR_TX_MASK; + + /* Configure TX interrupt sources to restore. */ + UART_IntrTxMask = LO16(UART_INTR_TX_MASK_REG); + + #if(UART_INTERNAL_RX_SW_BUFFER_CONST) + UART_rxBufferHead = 0u; + UART_rxBufferTail = 0u; + UART_rxBufferOverflow = 0u; + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if(UART_INTERNAL_TX_SW_BUFFER_CONST) + UART_txBufferHead = 0u; + UART_txBufferTail = 0u; + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + } +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/******************************************************************************* +* Function Name: UART_UartPostEnable +****************************************************************************//** +* +* Restores HSIOM settings for the UART output pins (TX and/or RTS) to be +* controlled by the SCB UART. +* +*******************************************************************************/ +void UART_UartPostEnable(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + #if (UART_TX_SDA_MISO_PIN) + if (UART_CHECK_TX_SDA_MISO_PIN_USED) + { + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, UART_TX_SDA_MISO_HSIOM_MASK, + UART_TX_SDA_MISO_HSIOM_POS, UART_TX_SDA_MISO_HSIOM_SEL_UART); + } + #endif /* (UART_TX_SDA_MISO_PIN_PIN) */ + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #if (UART_SS0_PIN) + if (UART_CHECK_SS0_PIN_USED) + { + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, UART_SS0_HSIOM_MASK, + UART_SS0_HSIOM_POS, UART_SS0_HSIOM_SEL_UART); + } + #endif /* (UART_SS0_PIN) */ + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#else + #if (UART_UART_TX_PIN) + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_TX_HSIOM_REG, UART_TX_HSIOM_MASK, + UART_TX_HSIOM_POS, UART_TX_HSIOM_SEL_UART); + #endif /* (UART_UART_TX_PIN) */ + + #if (UART_UART_RTS_PIN) + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_RTS_HSIOM_REG, UART_RTS_HSIOM_MASK, + UART_RTS_HSIOM_POS, UART_RTS_HSIOM_SEL_UART); + #endif /* (UART_UART_RTS_PIN) */ +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + /* Restore TX interrupt sources. */ + UART_SetTxInterruptMode(UART_IntrTxMask); +} + + +/******************************************************************************* +* Function Name: UART_UartStop +****************************************************************************//** +* +* Changes the HSIOM settings for the UART output pins (TX and/or RTS) to keep +* them inactive after the block is disabled. The output pins are controlled by +* the GPIO data register. Also, the function disables the skip start feature +* to not cause it to trigger after the component is enabled. +* +*******************************************************************************/ +void UART_UartStop(void) +{ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + #if (UART_TX_SDA_MISO_PIN) + if (UART_CHECK_TX_SDA_MISO_PIN_USED) + { + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, UART_TX_SDA_MISO_HSIOM_MASK, + UART_TX_SDA_MISO_HSIOM_POS, UART_TX_SDA_MISO_HSIOM_SEL_GPIO); + } + #endif /* (UART_TX_SDA_MISO_PIN_PIN) */ + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #if (UART_SS0_PIN) + if (UART_CHECK_SS0_PIN_USED) + { + /* Set output pin state after block is disabled */ + UART_spi_ss0_Write(UART_GET_UART_RTS_INACTIVE); + + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, UART_SS0_HSIOM_MASK, + UART_SS0_HSIOM_POS, UART_SS0_HSIOM_SEL_GPIO); + } + #endif /* (UART_SS0_PIN) */ + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#else + #if (UART_UART_TX_PIN) + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_TX_HSIOM_REG, UART_TX_HSIOM_MASK, + UART_TX_HSIOM_POS, UART_TX_HSIOM_SEL_GPIO); + #endif /* (UART_UART_TX_PIN) */ + + #if (UART_UART_RTS_PIN) + /* Set output pin state after block is disabled */ + UART_rts_Write(UART_GET_UART_RTS_INACTIVE); + + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_RTS_HSIOM_REG, UART_RTS_HSIOM_MASK, + UART_RTS_HSIOM_POS, UART_RTS_HSIOM_SEL_GPIO); + #endif /* (UART_UART_RTS_PIN) */ + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (UART_UART_WAKE_ENABLE_CONST) + /* Disable skip start feature used for wakeup */ + UART_UART_RX_CTRL_REG &= (uint32) ~UART_UART_RX_CTRL_SKIP_START; +#endif /* (UART_UART_WAKE_ENABLE_CONST) */ + + /* Store TX interrupt sources (exclude level triggered). */ + UART_IntrTxMask = LO16(UART_GetTxInterruptMode() & UART_INTR_UART_TX_RESTORE); +} + + +/******************************************************************************* +* Function Name: UART_UartSetRxAddress +****************************************************************************//** +* +* Sets the hardware detectable receiver address for the UART in the +* Multiprocessor mode. +* +* \param address: Address for hardware address detection. +* +*******************************************************************************/ +void UART_UartSetRxAddress(uint32 address) +{ + uint32 matchReg; + + matchReg = UART_RX_MATCH_REG; + + matchReg &= ((uint32) ~UART_RX_MATCH_ADDR_MASK); /* Clear address bits */ + matchReg |= ((uint32) (address & UART_RX_MATCH_ADDR_MASK)); /* Set address */ + + UART_RX_MATCH_REG = matchReg; +} + + +/******************************************************************************* +* Function Name: UART_UartSetRxAddressMask +****************************************************************************//** +* +* Sets the hardware address mask for the UART in the Multiprocessor mode. +* +* \param addressMask: Address mask. +* - Bit value 0 – excludes bit from address comparison. +* - Bit value 1 – the bit needs to match with the corresponding bit +* of the address. +* +*******************************************************************************/ +void UART_UartSetRxAddressMask(uint32 addressMask) +{ + uint32 matchReg; + + matchReg = UART_RX_MATCH_REG; + + matchReg &= ((uint32) ~UART_RX_MATCH_MASK_MASK); /* Clear address mask bits */ + matchReg |= ((uint32) (addressMask << UART_RX_MATCH_MASK_POS)); + + UART_RX_MATCH_REG = matchReg; +} + + +#if(UART_UART_RX_DIRECTION) + /******************************************************************************* + * Function Name: UART_UartGetChar + ****************************************************************************//** + * + * Retrieves next data element from receive buffer. + * This function is designed for ASCII characters and returns a char where + * 1 to 255 are valid characters and 0 indicates an error occurred or no data + * is present. + * - RX software buffer is disabled: Returns data element retrieved from RX + * FIFO. + * - RX software buffer is enabled: Returns data element from the software + * receive buffer. + * + * \return + * Next data element from the receive buffer. ASCII character values from + * 1 to 255 are valid. A returned zero signifies an error condition or no + * data available. + * + * \sideeffect + * The errors bits may not correspond with reading characters due to + * RX FIFO and software buffer usage. + * RX software buffer is enabled: The internal software buffer overflow + * is not treated as an error condition. + * Check UART_rxBufferOverflow to capture that error condition. + * + *******************************************************************************/ + uint32 UART_UartGetChar(void) + { + uint32 rxData = 0u; + + /* Reads data only if there is data to read */ + if (0u != UART_SpiUartGetRxBufferSize()) + { + rxData = UART_SpiUartReadRxData(); + } + + if (UART_CHECK_INTR_RX(UART_INTR_RX_ERR)) + { + rxData = 0u; /* Error occurred: returns zero */ + UART_ClearRxInterruptSource(UART_INTR_RX_ERR); + } + + return (rxData); + } + + + /******************************************************************************* + * Function Name: UART_UartGetByte + ****************************************************************************//** + * + * Retrieves the next data element from the receive buffer, returns the + * received byte and error condition. + * - The RX software buffer is disabled: returns the data element retrieved + * from the RX FIFO. Undefined data will be returned if the RX FIFO is + * empty. + * - The RX software buffer is enabled: returns data element from the + * software receive buffer. + * + * \return + * Bits 7-0 contain the next data element from the receive buffer and + * other bits contain the error condition. + * - UART_UART_RX_OVERFLOW - Attempt to write to a full + * receiver FIFO. + * - UART_UART_RX_UNDERFLOW Attempt to read from an empty + * receiver FIFO. + * - UART_UART_RX_FRAME_ERROR - UART framing error detected. + * - UART_UART_RX_PARITY_ERROR - UART parity error detected. + * + * \sideeffect + * The errors bits may not correspond with reading characters due to + * RX FIFO and software buffer usage. + * RX software buffer is enabled: The internal software buffer overflow + * is not treated as an error condition. + * Check UART_rxBufferOverflow to capture that error condition. + * + *******************************************************************************/ + uint32 UART_UartGetByte(void) + { + uint32 rxData; + uint32 tmpStatus; + + #if (UART_CHECK_RX_SW_BUFFER) + { + UART_DisableInt(); + } + #endif + + if (0u != UART_SpiUartGetRxBufferSize()) + { + /* Enables interrupt to receive more bytes: at least one byte is in + * buffer. + */ + #if (UART_CHECK_RX_SW_BUFFER) + { + UART_EnableInt(); + } + #endif + + /* Get received byte */ + rxData = UART_SpiUartReadRxData(); + } + else + { + /* Reads a byte directly from RX FIFO: underflow is raised in the + * case of empty. Otherwise the first received byte will be read. + */ + rxData = UART_RX_FIFO_RD_REG; + + + /* Enables interrupt to receive more bytes. */ + #if (UART_CHECK_RX_SW_BUFFER) + { + + /* The byte has been read from RX FIFO. Clear RX interrupt to + * not involve interrupt handler when RX FIFO is empty. + */ + UART_ClearRxInterruptSource(UART_INTR_RX_NOT_EMPTY); + + UART_EnableInt(); + } + #endif + } + + /* Get and clear RX error mask */ + tmpStatus = (UART_GetRxInterruptSource() & UART_INTR_RX_ERR); + UART_ClearRxInterruptSource(UART_INTR_RX_ERR); + + /* Puts together data and error status: + * MP mode and accept address: 9th bit is set to notify mark. + */ + rxData |= ((uint32) (tmpStatus << 8u)); + + return (rxData); + } + + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UART_UartSetRtsPolarity + ****************************************************************************//** + * + * Sets active polarity of RTS output signal. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param polarity: Active polarity of RTS output signal. + * - UART_UART_RTS_ACTIVE_LOW - RTS signal is active low. + * - UART_UART_RTS_ACTIVE_HIGH - RTS signal is active high. + * + *******************************************************************************/ + void UART_UartSetRtsPolarity(uint32 polarity) + { + if(0u != polarity) + { + UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_RTS_POLARITY; + } + else + { + UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_RTS_POLARITY; + } + } + + + /******************************************************************************* + * Function Name: UART_UartSetRtsFifoLevel + ****************************************************************************//** + * + * Sets level in the RX FIFO for RTS signal activation. + * While the RX FIFO has fewer entries than the RX FIFO level the RTS signal + * remains active, otherwise the RTS signal becomes inactive. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param level: Level in the RX FIFO for RTS signal activation. + * The range of valid level values is between 0 and RX FIFO depth - 1. + * Setting level value to 0 disables RTS signal activation. + * + *******************************************************************************/ + void UART_UartSetRtsFifoLevel(uint32 level) + { + uint32 uartFlowCtrl; + + uartFlowCtrl = UART_UART_FLOW_CTRL_REG; + + uartFlowCtrl &= ((uint32) ~UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + uartFlowCtrl |= ((uint32) (UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_UART_FLOW_CTRL_REG = uartFlowCtrl; + } + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#endif /* (UART_UART_RX_DIRECTION) */ + + +#if(UART_UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_UartPutString + ****************************************************************************//** + * + * Places a NULL terminated string in the transmit buffer to be sent at the + * next available bus time. + * This function is blocking and waits until there is a space available to put + * requested data in transmit buffer. + * + * \param string: pointer to the null terminated string array to be placed in the + * transmit buffer. + * + *******************************************************************************/ + void UART_UartPutString(const char8 string[]) + { + uint32 bufIndex; + + bufIndex = 0u; + + /* Blocks the control flow until all data has been sent */ + while(string[bufIndex] != ((char8) 0)) + { + UART_UartPutChar((uint32) string[bufIndex]); + bufIndex++; + } + } + + + /******************************************************************************* + * Function Name: UART_UartPutCRLF + ****************************************************************************//** + * + * Places byte of data followed by a carriage return (0x0D) and line feed + * (0x0A) in the transmit buffer. + * This function is blocking and waits until there is a space available to put + * all requested data in transmit buffer. + * + * \param txDataByte: the data to be transmitted. + * + *******************************************************************************/ + void UART_UartPutCRLF(uint32 txDataByte) + { + UART_UartPutChar(txDataByte); /* Blocks control flow until all data has been sent */ + UART_UartPutChar(0x0Du); /* Blocks control flow until all data has been sent */ + UART_UartPutChar(0x0Au); /* Blocks control flow until all data has been sent */ + } + + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UARTSCB_UartEnableCts + ****************************************************************************//** + * + * Enables usage of CTS input signal by the UART transmitter. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + *******************************************************************************/ + void UART_UartEnableCts(void) + { + UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_CTS_ENABLE; + } + + + /******************************************************************************* + * Function Name: UART_UartDisableCts + ****************************************************************************//** + * + * Disables usage of CTS input signal by the UART transmitter. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + *******************************************************************************/ + void UART_UartDisableCts(void) + { + UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_CTS_ENABLE; + } + + + /******************************************************************************* + * Function Name: UART_UartSetCtsPolarity + ****************************************************************************//** + * + * Sets active polarity of CTS input signal. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param + * polarity: Active polarity of CTS output signal. + * - UART_UART_CTS_ACTIVE_LOW - CTS signal is active low. + * - UART_UART_CTS_ACTIVE_HIGH - CTS signal is active high. + * + *******************************************************************************/ + void UART_UartSetCtsPolarity(uint32 polarity) + { + if (0u != polarity) + { + UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_CTS_POLARITY; + } + else + { + UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_CTS_POLARITY; + } + } + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + + /******************************************************************************* + * Function Name: UART_UartSendBreakBlocking + ****************************************************************************//** + * + * Sends a break condition (logic low) of specified width on UART TX line. + * Blocks until break is completed. Only call this function when UART TX FIFO + * and shifter are empty. + * + * \param breakWidth + * Width of break condition. Valid range is 4 to 16 bits. + * + * \note + * Before sending break all UART TX interrupt sources are disabled. The state + * of UART TX interrupt sources is restored before function returns. + * + * \sideeffect + * If this function is called while there is data in the TX FIFO or shifter that + * data will be shifted out in packets the size of breakWidth. + * + *******************************************************************************/ + void UART_UartSendBreakBlocking(uint32 breakWidth) + { + uint32 txCtrlReg; + uint32 txIntrReg; + + /* Disable all UART TX interrupt source and clear UART TX Done history */ + txIntrReg = UART_GetTxInterruptMode(); + UART_SetTxInterruptMode(0u); + UART_ClearTxInterruptSource(UART_INTR_TX_UART_DONE); + + /* Store TX CTRL configuration */ + txCtrlReg = UART_TX_CTRL_REG; + + /* Set break width */ + UART_TX_CTRL_REG = (UART_TX_CTRL_REG & (uint32) ~UART_TX_CTRL_DATA_WIDTH_MASK) | + UART_GET_TX_CTRL_DATA_WIDTH(breakWidth); + + /* Generate break */ + UART_TX_FIFO_WR_REG = 0u; + + /* Wait for break completion */ + while (0u == (UART_GetTxInterruptSource() & UART_INTR_TX_UART_DONE)) + { + } + + /* Clear all UART TX interrupt sources to */ + UART_ClearTxInterruptSource(UART_INTR_TX_ALL); + + /* Restore TX interrupt sources and data width */ + UART_TX_CTRL_REG = txCtrlReg; + UART_SetTxInterruptMode(txIntrReg); + } +#endif /* (UART_UART_TX_DIRECTION) */ + + +#if (UART_UART_WAKE_ENABLE_CONST) + /******************************************************************************* + * Function Name: UART_UartSaveConfig + ****************************************************************************//** + * + * Clears and enables an interrupt on a falling edge of the Rx input. The GPIO + * interrupt does not track in the active mode, therefore requires to be + * cleared by this API. + * + *******************************************************************************/ + void UART_UartSaveConfig(void) + { + #if (UART_UART_RX_WAKEUP_IRQ) + /* Set SKIP_START if requested (set by default). */ + if (0u != UART_skipStart) + { + UART_UART_RX_CTRL_REG |= (uint32) UART_UART_RX_CTRL_SKIP_START; + } + else + { + UART_UART_RX_CTRL_REG &= (uint32) ~UART_UART_RX_CTRL_SKIP_START; + } + + /* Clear RX GPIO interrupt status and pending interrupt in NVIC because + * falling edge on RX line occurs while UART communication in active mode. + * Enable interrupt: next interrupt trigger should wakeup device. + */ + UART_CLEAR_UART_RX_WAKE_INTR; + UART_RxWakeClearPendingInt(); + UART_RxWakeEnableInt(); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + } + + + /******************************************************************************* + * Function Name: UART_UartRestoreConfig + ****************************************************************************//** + * + * Disables the RX GPIO interrupt. Until this function is called the interrupt + * remains active and triggers on every falling edge of the UART RX line. + * + *******************************************************************************/ + void UART_UartRestoreConfig(void) + { + #if (UART_UART_RX_WAKEUP_IRQ) + /* Disable interrupt: no more triggers in active mode */ + UART_RxWakeDisableInt(); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + } + + + #if (UART_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: UART_UART_WAKEUP_ISR + ****************************************************************************//** + * + * Handles the Interrupt Service Routine for the SCB UART mode GPIO wakeup + * event. This event is configured to trigger on a falling edge of the RX line. + * + *******************************************************************************/ + CY_ISR(UART_UART_WAKEUP_ISR) + { + #ifdef UART_UART_WAKEUP_ISR_ENTRY_CALLBACK + UART_UART_WAKEUP_ISR_EntryCallback(); + #endif /* UART_UART_WAKEUP_ISR_ENTRY_CALLBACK */ + + UART_CLEAR_UART_RX_WAKE_INTR; + + #ifdef UART_UART_WAKEUP_ISR_EXIT_CALLBACK + UART_UART_WAKEUP_ISR_ExitCallback(); + #endif /* UART_UART_WAKEUP_ISR_EXIT_CALLBACK */ + } + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_UART_BOOT.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_UART_BOOT.c new file mode 100644 index 0000000..cd16e78 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_UART_BOOT.c @@ -0,0 +1,189 @@ +/***************************************************************************//** +* \file UART_UART_BOOT.c +* \version 4.0 +* +* \brief +* This file provides the source code of the bootloader communication APIs +* for the SCB Component UART mode. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_BOOT.h" +#include "UART_SPI_UART.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && (UART_UART_BTLDR_COMM_ENABLED) + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommStart +****************************************************************************//** +* +* Starts the UART component. +* +*******************************************************************************/ +void UART_UartCyBtldrCommStart(void) +{ + UART_Start(); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommStop +****************************************************************************//** +* +* Disables the UART component. +* +*******************************************************************************/ +void UART_UartCyBtldrCommStop(void) +{ + UART_Stop(); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommReset +****************************************************************************//** +* +* Resets the receive and transmit communication buffers. +* +*******************************************************************************/ +void UART_UartCyBtldrCommReset(void) +{ + /* Clear RX and TX buffers */ + UART_SpiUartClearRxBuffer(); + UART_SpiUartClearTxBuffer(); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommRead +****************************************************************************//** +* +* Allows the caller to read data from the bootloader host (the host writes the +* data). The function handles polling to allow a block of data to be completely +* received from the host device. +* +* \param pData: Pointer to storage for the block of data to be read from the +* bootloader host +* \param size: Number of bytes to be read. +* \param count: Pointer to the variable to write the number of bytes actually +* read. +* \param timeOut Number of units in 10 ms to wait before returning +* because of a timeout. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus UART_UartCyBtldrCommRead(uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + uint32 byteCount; + uint32 timeoutMs; + uint32 i; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + status = CYRET_TIMEOUT; + timeoutMs = ((uint32) 10u * timeOut); /* Convert from 10mS check to 1mS checks */ + + /* Wait with timeout 1mS for packet end */ + byteCount = 0u; + do + { + /* Check packet start */ + if (0u != UART_SpiUartGetRxBufferSize()) + { + /* Wait for end of packet */ + do + { + byteCount = UART_SpiUartGetRxBufferSize(); + CyDelayUs(UART_UART_BYTE_TO_BYTE); + } + while (byteCount != UART_SpiUartGetRxBufferSize()); + + byteCount = UART_BYTES_TO_COPY(byteCount, size); + *count = (uint16) byteCount; + status = CYRET_SUCCESS; + + break; + } + + CyDelay(UART_WAIT_1_MS); + --timeoutMs; + } + while (0u != timeoutMs); + + /* Get data from RX buffer into bootloader buffer */ + for (i = 0u; i < byteCount; ++i) + { + pData[i] = (uint8) UART_SpiUartReadRxData(); + } + } + + return (status); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommWrite +****************************************************************************//** +* +* Allows the caller to write data to the bootloader host (the host reads the +* data). The function does not use timeout and returns after data has been +* copied into the transmit buffer. The data transmission starts immediately +* after the first data element is written into the buffer and lasts until all +* data elements from the buffer are sent. +* +* \param pData: Pointer to the block of data to be written to the bootloader +* host. +* \param size: Number of bytes to be written. +* \param count: Pointer to the variable to write the number of bytes actually +* written. +* \param timeOut: The timeout is not used by this function. +* The function returns as soon as data is copied into the transmit buffer. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus UART_UartCyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + /* Transmit data. This function does not wait until data is sent. */ + UART_SpiUartPutArray(pData, (uint32) size); + + *count = size; + status = CYRET_SUCCESS; + + if (0u != timeOut) + { + /* Suppress compiler warning */ + } + } + + return (status); +} + +#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (UART_UART_BTLDR_COMM_ENABLED) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx.c new file mode 100644 index 0000000..2a025d1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: UART_tx.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_tx.h" + + +#if defined(UART_tx__PC) + #define UART_tx_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_tx_PC = (UART_tx_PC & \ + (uint32)(~(uint32)(UART_tx_DRIVE_MODE_IND_MASK << \ + (UART_tx_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_tx_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define UART_tx_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_tx_USBIO_CTRL_REG = (UART_tx_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(UART_tx_DRIVE_MODE_IND_MASK << \ + (UART_tx_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_tx_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(UART_tx__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: UART_tx_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet UART_tx_SUT.c usage_UART_tx_SetDriveMode + *******************************************************************************/ + void UART_tx_SetDriveMode(uint8 mode) + { + UART_tx_SetP4PinDriveMode(UART_tx__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: UART_tx_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_Write +*******************************************************************************/ +void UART_tx_Write(uint8 value) +{ + uint8 drVal = (uint8)(UART_tx_DR & (uint8)(~UART_tx_MASK)); + drVal = (drVal | ((uint8)(value << UART_tx_SHIFT) & UART_tx_MASK)); + UART_tx_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: UART_tx_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_Read +*******************************************************************************/ +uint8 UART_tx_Read(void) +{ + return (uint8)((UART_tx_PS & UART_tx_MASK) >> UART_tx_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_tx_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred UART_tx_Read() API because the +* UART_tx_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_ReadDataReg +*******************************************************************************/ +uint8 UART_tx_ReadDataReg(void) +{ + return (uint8)((UART_tx_DR & UART_tx_MASK) >> UART_tx_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_tx_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use UART_tx_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - UART_tx_0_INTR (First pin in the list) +* - UART_tx_1_INTR (Second pin in the list) +* - ... +* - UART_tx_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_SetInterruptMode +*******************************************************************************/ +void UART_tx_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = UART_tx_INTCFG & (uint32)(~(uint32)position); + UART_tx_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: UART_tx_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_ClearInterrupt +*******************************************************************************/ +uint8 UART_tx_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(UART_tx_INTSTAT & UART_tx_MASK); + UART_tx_INTSTAT = maskedStatus; + return maskedStatus >> UART_tx_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx.h new file mode 100644 index 0000000..bdcfe1c --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: UART_tx.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_tx_H) /* Pins UART_tx_H */ +#define CY_PINS_UART_tx_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "UART_tx_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} UART_tx_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 UART_tx_Read(void); +void UART_tx_Write(uint8 value); +uint8 UART_tx_ReadDataReg(void); +#if defined(UART_tx__PC) || (CY_PSOC4_4200L) + void UART_tx_SetDriveMode(uint8 mode); +#endif +void UART_tx_SetInterruptMode(uint16 position, uint16 mode); +uint8 UART_tx_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void UART_tx_Sleep(void); +void UART_tx_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(UART_tx__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define UART_tx_DRIVE_MODE_BITS (3) + #define UART_tx_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - UART_tx_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the UART_tx_SetDriveMode() function. + * @{ + */ + #define UART_tx_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define UART_tx_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define UART_tx_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define UART_tx_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define UART_tx_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define UART_tx_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define UART_tx_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define UART_tx_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define UART_tx_MASK UART_tx__MASK +#define UART_tx_SHIFT UART_tx__SHIFT +#define UART_tx_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in UART_tx_SetInterruptMode() function. + * @{ + */ + #define UART_tx_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define UART_tx_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define UART_tx_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define UART_tx_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(UART_tx__SIO) + #define UART_tx_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(UART_tx__PC) && (CY_PSOC4_4200L) + #define UART_tx_USBIO_ENABLE ((uint32)0x80000000u) + #define UART_tx_USBIO_DISABLE ((uint32)(~UART_tx_USBIO_ENABLE)) + #define UART_tx_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define UART_tx_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define UART_tx_USBIO_ENTER_SLEEP ((uint32)((1u << UART_tx_USBIO_SUSPEND_SHIFT) \ + | (1u << UART_tx_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_tx_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << UART_tx_USBIO_SUSPEND_SHIFT))) + #define UART_tx_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << UART_tx_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_tx_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(UART_tx__PC) + /* Port Configuration */ + #define UART_tx_PC (* (reg32 *) UART_tx__PC) +#endif +/* Pin State */ +#define UART_tx_PS (* (reg32 *) UART_tx__PS) +/* Data Register */ +#define UART_tx_DR (* (reg32 *) UART_tx__DR) +/* Input Buffer Disable Override */ +#define UART_tx_INP_DIS (* (reg32 *) UART_tx__PC2) + +/* Interrupt configuration Registers */ +#define UART_tx_INTCFG (* (reg32 *) UART_tx__INTCFG) +#define UART_tx_INTSTAT (* (reg32 *) UART_tx__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define UART_tx_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(UART_tx__SIO) + #define UART_tx_SIO_REG (* (reg32 *) UART_tx__SIO) +#endif /* (UART_tx__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(UART_tx__PC) && (CY_PSOC4_4200L) + #define UART_tx_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define UART_tx_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define UART_tx_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define UART_tx_DRIVE_MODE_SHIFT (0x00u) +#define UART_tx_DRIVE_MODE_MASK (0x07u << UART_tx_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins UART_tx_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx_PM.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx_PM.c new file mode 100644 index 0000000..d72f2ee --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: UART_tx.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_tx.h" + +static UART_tx_BACKUP_STRUCT UART_tx_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: UART_tx_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_Sleep_Wakeup +*******************************************************************************/ +void UART_tx_Sleep(void) +{ + #if defined(UART_tx__PC) + UART_tx_backup.pcState = UART_tx_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + UART_tx_backup.usbState = UART_tx_CR1_REG; + UART_tx_USB_POWER_REG |= UART_tx_USBIO_ENTER_SLEEP; + UART_tx_CR1_REG &= UART_tx_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_tx__SIO) + UART_tx_backup.sioState = UART_tx_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + UART_tx_SIO_REG &= (uint32)(~UART_tx_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: UART_tx_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to UART_tx_Sleep() for an example usage. +*******************************************************************************/ +void UART_tx_Wakeup(void) +{ + #if defined(UART_tx__PC) + UART_tx_PC = UART_tx_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + UART_tx_USB_POWER_REG &= UART_tx_USBIO_EXIT_SLEEP_PH1; + UART_tx_CR1_REG = UART_tx_backup.usbState; + UART_tx_USB_POWER_REG &= UART_tx_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_tx__SIO) + UART_tx_SIO_REG = UART_tx_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx_aliases.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx_aliases.h new file mode 100644 index 0000000..14254ae --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/UART_tx_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: UART_tx.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_tx_ALIASES_H) /* Pins UART_tx_ALIASES_H */ +#define CY_PINS_UART_tx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define UART_tx_0 (UART_tx__0__PC) +#define UART_tx_0_PS (UART_tx__0__PS) +#define UART_tx_0_PC (UART_tx__0__PC) +#define UART_tx_0_DR (UART_tx__0__DR) +#define UART_tx_0_SHIFT (UART_tx__0__SHIFT) +#define UART_tx_0_INTR ((uint16)((uint16)0x0003u << (UART_tx__0__SHIFT*2u))) + +#define UART_tx_INTR_ALL ((uint16)(UART_tx_0_INTR)) + + +#endif /* End Pins UART_tx_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cm0gcc.ld b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cm0gcc.ld new file mode 100644 index 0000000..b2b139d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cm0gcc.ld @@ -0,0 +1,475 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(Reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + + +/* Code sharing support */ +INCLUDE cycodeshareexport.ld +INCLUDE cycodeshareimport.ld + + +MEMORY +{ + rom (rx) : ORIGIN = 0x0, LENGTH = 32768 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4096 +} + + +CY_APPL_ORIGIN = 0; +CY_FLASH_ROW_SIZE = 128; +CY_APPL_NUM = 1; +CY_APPL_MAX = 1; +CY_METADATA_SIZE = 64; +CY_APPL_LOADABLE = 0; +CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(0, CY_FLASH_ROW_SIZE); +CY_APP_FOR_STACK_AND_COPIER = 0; + + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(Reset) + +/* Bring in the interrupt routines & vector */ +EXTERN(main) + +/* Bring in the romvector */ +EXTERN(RomVectors) + +/* Bring in the ramvector */ +EXTERN(CyRamVectors) + +/* Bring in the meta data */ +EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) +EXTERN(cy_meta_flashprotect cy_metadata cy_meta_chipprotect) +EXTERN(cy_heap) + +/* Provide fall-back values */ +PROVIDE(__cy_heap_start = _end); +PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); + +/* Set stack top to end of RAM, and stack limit move down by + * size of .stack section. + */ +PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); + +PROVIDE(__cy_heap_end = __cy_stack - 0x0400); + + +SECTIONS +{ + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + + + cy_project_type_bootloader = (appl_start == 0) ? 1 : 0; + cy_project_type_app_for_stack_and_copier = (CY_APP_FOR_STACK_AND_COPIER == 1) ? 1 : 0; + + + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); + + KEEP(*(.romvectors)) + + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + + PROVIDE(__cy_reset = Reset); + + *(.text.Reset) + + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); + + *(.psocinit) + + /* The first 0x100 Flash bytes become unavailable right after remapping of the vector table to RAM. */ + . = MAX(., 0x100); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + + __exidx_end = .; + + + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + + /*************************************************************************** + * Checksum Exclude Section for non-bootloadable projects. See below. + ***************************************************************************/ + .cy_checksum_exclude : { KEEP(*(.cy_checksum_exclude)) } >rom + + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + + + + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x0100; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x0400) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x0400; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + + /*************************************************************************** + * Checksum Exclude Section + *************************************************************************** + * + * For the normal and bootloader projects this section is placed at any + * place. For the Bootloadable applications, it is placed at the specific + * address. + * + * Case # 1. Bootloadable application + * + * _______________________________ + * | Metadata (BTLDBL) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | | + * | | + * | BTLDBL | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDR | + * |_______________________________| + * + * + * Case # 2. Bootloadable application for Dual-Application Bootloader + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 2 | + * |_______________________________|____BTLDBL # 2 Start address___ + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + * + * + * Case # 3. OTA updatable stack + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * | | + * |-------------------------------| + * |_______________________________|____Temporary location for BTLDBL # 1 update(Former BTLDBL # 2 start)___ + * | | + * | BTLDBL # 2 | + * | | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + */ + + + + /* Bootloadable applications only: verify that size of the data in the section is within the specified limit. */ + cy_checksum_exclude_size = (CY_APPL_LOADABLE == 1) ? SIZEOF(.cy_checksum_exclude) : 0; + ASSERT(cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE, "CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.") + + + /*************************************************************************** + * Bootloader Metadata Section + *************************************************************************** + * + * Case # 1. Bootloader project + * + * _______________________________ + * | BTLDR Metadata | + * |-------------------------------| + * | | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | Bootloader (BTLDR) | + * |_______________________________| + * + * + * Case # 2. Code sharing + * + * _______________________________ + * | SP/L Metadata | CY_APPL_METADATA_SLOT_NUM == 0 + * |-------------------------------| + * | App for SP+L Metadata | CY_APPL_METADATA_SLOT_NUM == 1 + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | App for SP+L | ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + * | | + * |-------------------------------| + * | | + * | Stack Project (SP) | (CYDEV_IS_EXPORTING_CODE == 1) + * | | + * |-------------------------------| + * | | + * | Launcher (L) | + * |_______________________________| + * + * Notes: + * - App for SP+L start just after the SP + * - SP treated as a single bootloadable application + * - App for SP+L treats SP+L as a bootloader + */ + + /* For the bootloader project, place bootloader metadata at the last flash row, otherwise place beyond map */ + cyloadermeta_start = (cy_project_type_bootloader || cy_project_type_app_for_stack_and_copier) ? + (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000; + .cyloadermeta (cyloadermeta_start) : + { + KEEP(*(.cyloadermeta)) + } : NONE + + + cyloadablemeta_start = (cy_project_type_app_for_stack_and_copier) ? + (LENGTH(rom) - CY_FLASH_ROW_SIZE - CY_METADATA_SIZE) : (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE); + .cyloadablemeta (cyloadablemeta_start) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + .cychipprotect 0x90600000 : { KEEP(*(.cychipprotect)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_armcc.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_armcc.h new file mode 100644 index 0000000..234ea5e --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_armcc.h @@ -0,0 +1,791 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 27. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_compiler.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_compiler.h new file mode 100644 index 0000000..658bd96 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_compiler.h @@ -0,0 +1,210 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V5.00 + * @date 09. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include + + #ifndef __NO_RETURN + #define __NO_RETURN __noreturn + #endif + #ifndef __USED + #define __USED __root + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + __packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_gcc.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_gcc.h new file mode 100644 index 0000000..1b85b91 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cmsis_gcc.h @@ -0,0 +1,1894 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 28. October 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef _WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1U)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1U)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cm0.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cm0.h new file mode 100644 index 0000000..41b07f5 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cm0.h @@ -0,0 +1,820 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.00 + * @date 13. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cm0_psoc4.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cm0_psoc4.h new file mode 100644 index 0000000..51de779 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cm0_psoc4.h @@ -0,0 +1,43 @@ +/******************************************************************************* +* \file core_cm0_psoc4.h +* \version 5.70 +* +* \brief Provides important type information for the PSOC4 device family. +* This includes types necessary for core_cm0.h. +* +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_BOOT_CORE_CM0_PSOC4_H) +#define CY_BOOT_CORE_CM0_PSOC4_H + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M0 System Tick Interrupt */ +/****** PSOC4 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#define __CHECK_DEVICE_DEFINES + +#define __CM0_REV 0x0000 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +#include + +#endif /* CY_BOOT_CORE_CM0_PSOC4_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cmFunc.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cmFunc.h new file mode 100644 index 0000000..652a48a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cmInstr.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cmInstr.h new file mode 100644 index 0000000..f474b0e --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyPm.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyPm.c new file mode 100644 index 0000000..3181e33 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyPm.c @@ -0,0 +1,435 @@ +/***************************************************************************//** +* \file cyPm.c +* \version 5.70 +* +* \brief Provides an API for the power management. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2011-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" +#include "CyLib.h" +#include "CyFlash.h" + + +/******************************************************************************* +* Function Name: CySysPmSleep +****************************************************************************//** +* +* Puts the part into the Sleep state. This is a CPU-centric power mode. +* It means that the CPU has indicated that it is in the sleep mode and +* its main clock can be removed. It is identical to Active from a peripheral +* point of view. Any enabled interrupts can cause wakeup from the Sleep mode. +* +*******************************************************************************/ +void CySysPmSleep(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* CPU enters Sleep mode upon execution of WFI */ + CY_PM_CPU_SCR_REG &= (uint32) (~CY_PM_CPU_SCR_SLEEPDEEP); + + /* Sleep and wait for interrupt */ + CY_PM_WFI; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysPmDeepSleep +****************************************************************************//** +* +* Puts the part into the Deep Sleep state. If the firmware attempts to enter +* this mode before the system is ready (that is, when +* PWR_CONTROL.LPM_READY = 0), then the device will go into the Sleep mode +* instead and automatically enter the originally intended mode when the +* holdoff expires. +* +* The wakeup occurs when an interrupt is received from a DeepSleep or +* Hibernate peripheral. For more details, see a corresponding +* peripheral's datasheet. +* +*******************************************************************************/ +void CySysPmDeepSleep(void) +{ + uint8 interruptState; + #if(CY_IP_SRSSV2) + volatile uint32 clkSelectReg; + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_ECO_SRSSLT) + volatile uint32 pllResoreFlag = 0u; + #endif /* (CY_IP_ECO_SRSSLT) */ + + interruptState = CyEnterCriticalSection(); + + #if(CY_IP_ECO_SRSSLT) + if(0u != (CY_SYS_ECO_CLK_SELECT_REG & CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK)) + { + pllResoreFlag = 1u; + + /* Set default state = IMO for HFCLK_SEL bit mask */ + CY_SYS_CLK_SELECT_REG &= (uint32)(~CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + } + #endif /* (CY_IP_ECO_SRSSLT) */ + + #if(CY_IP_SRSSV2) + /* Device enters DeepSleep mode when CPU asserts SLEEPDEEP signal */ + CY_PM_PWR_CONTROL_REG &= (uint32) (~CY_PM_PWR_CONTROL_HIBERNATE); + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_CPUSS && CY_IP_SRSSV2) + CY_PM_CPUSS_CONFIG_REG |= CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS; + #endif /* (CY_IP_CPUSS && CY_IP_SRSSV2) */ + + /* Adjust delay to wait for references to settle on wakeup from Deep Sleep */ + CY_PM_PWR_KEY_DELAY_REG = CY_SFLASH_DPSLP_KEY_DELAY_REG; + + /* CPU enters DeepSleep/Hibernate mode upon execution of WFI */ + CY_PM_CPU_SCR_REG |= CY_PM_CPU_SCR_SLEEPDEEP; + + #if(CY_IP_SRSSV2) + /* Preserve system clock configuration and + * reduce sysclk to <=12 MHz (Cypress ID #158710, #179888). + */ + clkSelectReg = CY_SYS_CLK_SELECT_REG; + CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV4); + #endif /* (CY_IP_SRSSV2) */ + + /* Sleep and wait for interrupt */ + CY_PM_WFI; + + #if(CY_IP_SRSSV2) + /* Restore system clock configuration */ + CY_SYS_CLK_SELECT_REG = clkSelectReg; + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_CPUSS && CY_IP_SRSSV2) + CY_PM_CPUSS_CONFIG_REG &= (uint32) (~CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS); + #endif /* (CY_IP_CPUSS && CY_IP_SRSSV2) */ + + #if(CY_IP_ECO_SRSSLT) + if(0u != pllResoreFlag) + { + CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_PLL0); + } + #endif /* (CY_IP_ECO_SRSSLT) */ + + CyExitCriticalSection(interruptState); +} + + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Function Name: CySysPmHibernate + ****************************************************************************//** + * + * Puts the part into the Hibernate state. Only SRAM and UDBs are retained; + * most internal supplies are off. Wakeup is possible from a pin or a hibernate + * comparator only. + * + * It is expected that the firmware has already frozen the IO-Cells using + * CySysPmFreezeIo() function before the call to this function. If this is + * omitted, the IO-cells will be frozen in the same way as they are + * in the Active to Deep Sleep transition, but will lose their state on wake up + * (because of the reset occurring at that time). + * + * Because all the CPU state is lost, the CPU will start up at the reset vector. + * To save the firmware state through the Hibernate low power mode, a + * corresponding variable should be defined with CY_NOINIT attribute. It + * prevents data from being initialized to zero on startup. The interrupt + * cause of the hibernate peripheral is retained, such that it can be either + * read by the firmware or cause an interrupt after the firmware has booted and + * enabled the corresponding interrupt. To distinguish the wakeup from + * the Hibernate mode and the general Reset event, the + * \ref CySysPmGetResetReason() function could be used. + * + *******************************************************************************/ + void CySysPmHibernate(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_HOBTO_DEVICE) + /* Disable input buffers for all ports */ + CySysPmHibPinsDisableInputBuf(); + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Device enters Hibernate mode when CPU asserts SLEEPDEEP signal */ + CY_PM_PWR_CONTROL_REG |= CY_PM_PWR_CONTROL_HIBERNATE; + + /* Adjust delay to wait for references to settle on wakeup from hibernate */ + CY_PM_PWR_KEY_DELAY_REG = CY_SFLASH_HIB_KEY_DELAY_REG; + + /* CPU enters DeepSleep/Hibernate mode upon execution of WFI */ + CY_PM_CPU_SCR_REG |= CY_PM_CPU_SCR_SLEEPDEEP; + + /* Save token that will retain through a STOP/WAKEUP sequence + * thus could be used by CySysPmGetResetReason() to differentiate + * WAKEUP from a general RESET event. + */ + CY_PM_PWR_STOP_REG = (CY_PM_PWR_STOP_REG & (uint32)(~CY_PM_PWR_STOP_TOKEN_MASK)) | CY_PM_PWR_STOP_TOKEN_HIB; + + /* Sleep and wait for interrupt. Wakeup from Hibernate is performed + * through RESET state, causing a normal Boot procedure to occur. + * The WFI instruction doesn't put the core to sleep if its wake condition + * is true when the instruction is executed. + */ + CY_PM_WFI; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmStop + ****************************************************************************//** + * + * Puts the part into the Stop state. All internal supplies are off; + * no state is retained. + * + * Wakeup from Stop is performed by toggling the wakeup pin, causing + * a normal boot procedure to occur. To configure the wakeup pin, + * the Digital Input Pin component should be placed on the schematic, + * assigned to the wakeup pin, and resistively pulled up or down to the inverse + * state of the wakeup polarity. To distinguish the wakeup from the Stop mode + * and the general Reset event, \ref CySysPmGetResetReason() function could be + * used. The wakeup pin is active low by default. The wakeup pin polarity + * could be changed with the \ref CySysPmSetWakeupPolarity() function. + * + * This function freezes IO cells implicitly. It is not possible to enter + * the STOP mode before freezing the IO cells. The IO cells remain frozen after + * awake from the Stop mode until the firmware unfreezes them after booting + * explicitly with \ref CySysPmUnfreezeIo() function call. + * + *******************************************************************************/ + void CySysPmStop(void) + { + (void) CyEnterCriticalSection(); + + /* Update token to indicate Stop mode transition. Preserve only polarity. */ + CY_PM_PWR_STOP_REG = (CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_POLARITY) | CY_PM_PWR_STOP_TOKEN_STOP; + + /* Freeze IO-Cells to save IO-Cell state */ + CySysPmFreezeIo(); + + /* Initiates transition to Stop state */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_REG | CY_PM_PWR_STOP_STOP; + + /* Depending on the clock frequency and internal timing delays, + * the final AHB transaction may or may not complete. To guard against + * accidentally executing an unintended instruction, it is recommended + * to add 2 NOP cycles after the final write to the STOP register. + */ + CY_NOP; + CY_NOP; + + /* Should never get to this WFI instruction */ + CY_PM_WFI; + + /* Wakeup from Stop is performed by toggling of Wakeup pin, + * causing a normal Boot procedure to occur. No need to exit + * from the critical section. + */ + } + + + /******************************************************************************* + * Function Name: CySysPmSetWakeupPolarity + ****************************************************************************//** + * + * Wake up from the stop mode is performed by toggling the wakeup pin, + * causing a normal boot procedure to occur. This function assigns + * the wakeup pin active level. Setting the wakeup pin to this level will cause + * the wakeup from stop mode. The wakeup pin is active low by default. + * + * \param polarity + * - \ref CY_PM_STOP_WAKEUP_ACTIVE_LOW Logical zero will wakeup the chip + * - \ref CY_PM_STOP_WAKEUP_ACTIVE_HIGH Logical one will wakeup the chip + * + *******************************************************************************/ + void CySysPmSetWakeupPolarity(uint32 polarity) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_PM_PWR_STOP_REG = (CY_PM_STOP_WAKEUP_ACTIVE_LOW != polarity) ? + (CY_PM_PWR_STOP_REG | CY_PM_PWR_STOP_POLARITY) : + (CY_PM_PWR_STOP_REG & (uint32) (~CY_PM_PWR_STOP_POLARITY)); + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmGetResetReason + ****************************************************************************//** + * + * Retrieves the last reset reason - transition from OFF/XRES/STOP/HIBERNATE to + * the RESET state. Note that waking up from STOP using XRES will be perceived + * as a general RESET. + * + * \return CY_PM_RESET_REASON_UNKN Unknown reset reason. + * \return CY_PM_RESET_REASON_XRES Transition from OFF/XRES to RESET + * \return CY_PM_RESET_REASON_WAKEUP_HIB Transition/wakeup from HIBERNATE to RESET + * \return CY_PM_RESET_REASON_WAKEUP_STOP Transition/wakeup from STOP to RESET + * + *******************************************************************************/ + uint32 CySysPmGetResetReason(void) + { + uint32 reason = CY_PM_RESET_REASON_UNKN; + + switch(CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_TOKEN_MASK) + { + /* Power up, XRES */ + case CY_PM_PWR_STOP_TOKEN_XRES: + reason = CY_PM_RESET_REASON_XRES; + break; + + /* Wakeup from Hibernate */ + case CY_PM_PWR_STOP_TOKEN_HIB: + reason = CY_PM_RESET_REASON_WAKEUP_HIB; + break; + + /* Wakeup from Stop (through WAKEUP pin assert) */ + case CY_PM_PWR_STOP_TOKEN_STOP: + reason = CY_PM_RESET_REASON_WAKEUP_STOP; + break; + + /* Unknown reason */ + default: + break; + } + + return (reason); + } + + + /******************************************************************************* + * Function Name: CySysPmFreezeIo + ****************************************************************************//** + * + * Freezes IO-Cells directly to save the IO-Cell state on wake up from the + * Hibernate or Stop state. It is not required to call this function before + * entering the Stop mode, since \ref CySysPmStop() function freezes IO-Cells + * implicitly. + * + * This API is not available for PSoC 4000 family of devices. + * + *******************************************************************************/ + void CySysPmFreezeIo(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Check FREEZE state to avoid recurrent IO-Cells freeze attempt, + * since the second call to this function will cause accidental switch + * to the STOP mode (the system will enter STOP mode immediately after + * writing to STOP bit since both UNLOCK and FREEZE have been set correctly + * in a previous call to this function). + */ + if (0u == (CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_FREEZE)) + { + /* Preserve last reset reason and disable overrides the next freeze command by peripherals */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_STOP | CY_PM_PWR_STOP_FREEZE | CY_PM_PWR_STOP_UNLOCK | + (CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY)); + + /* If reading after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) CY_PM_PWR_STOP_REG; + (void) CY_PM_PWR_STOP_REG; + + /* Second write causes the freeze of IO-Cells to save IO-Cell state */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_REG; + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmUnfreezeIo + ****************************************************************************//** + * + * The IO-Cells remain frozen after awake from Hibernate or Stop mode until + * the firmware unfreezes them after booting. The call of this function + * unfreezes IO-Cells explicitly. + * + * If the firmware intent is to retain the data value on the port, then the + * value must be read and re-written to the data register before calling this + * API. Furthermore, the drive mode must be re-programmed. If this is not done, + * the pin state will change to default state the moment the freeze is removed. + * + * This API is not available for PSoC 4000 family of devices. + * + *******************************************************************************/ + void CySysPmUnfreezeIo(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Preserve last reset reason and wakeup polarity. Then, unfreeze I/O: + * write PWR_STOP.FREEZE=0, .UNLOCK=0x3A, .STOP=0, .TOKEN + */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_UNLOCK | + (CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY)); + + /* If reading after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) CY_PM_PWR_STOP_REG; + (void) CY_PM_PWR_STOP_REG; + + /* Lock STOP mode: write PWR_STOP.FREEZE=0, UNLOCK=0x00, STOP=0, .TOKEN */ + CY_PM_PWR_STOP_REG &= (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY); + + CyExitCriticalSection(interruptState); + } + +#else + + /******************************************************************************* + * Function Name: CySysPmSetWakeupHoldoff + ****************************************************************************//** + * + * Sets the Deep Sleep wakeup time by scaling the hold-off to the HFCLK + * frequency. + * + * This function must be called before increasing HFCLK clock frequency. It can + * optionally be called after lowering HFCLK clock frequency in order to improve + * Deep Sleep wakeup time. + * + * It is functionally acceptable to leave the default hold-off setting, but + * Deep Sleep wakeup time may exceed the specification. + * + * This function is applicable only for the 4000 device family. + * + * \param hfclkFrequencyMhz The HFCLK frequency in MHz. + * + *******************************************************************************/ + void CySysPmSetWakeupHoldoff(uint32 hfclkFrequencyMhz) + { + CY_PM_PWR_KEY_DELAY_REG = ((((uint32)(CY_PM_PWR_KEY_DELAY_REG_DEFAULT << 16u) / + CY_PM_PWR_KEY_DELAY_FREQ_DEFAULT) * hfclkFrequencyMhz) >> 16u) + 1u; + } + +#endif /* (CY_IP_SRSSV2) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyPm.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyPm.h new file mode 100644 index 0000000..7b0641a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyPm.h @@ -0,0 +1,302 @@ +/***************************************************************************//** +* \file cyPm.h +* \version 5.70 +* +* \brief Provides the function definitions for the power management API. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2011-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" +#include "cypins.h" + + +/** +* \addtogroup group_power_management Power Management API +* @{ + +\brief PSoC 4 devices support the following power modes (in order of high to low power consumption): Active, Sleep, +Deep Sleep, Hibernate, and Stop. Active, Sleep and Deep-Sleep are standard ARM defined power modes, supported by the +ARM CPUs. Hibernate/Stop are even lower power modes that are entered from firmware just like Deep-Sleep, but on wakeup +the CPU (and all peripherals) goes through a full reset. + +There is a full range of power modes supported by PSoC devices to control power consumption and the amount of available +resources. See the following table for the supported power modes. + +Mode | PSoC 4000 | Rest Devices | +----------- | ---------------------- | ---------------------- | +Active | Y | Y | +Sleep | Y | Y | +Deep Sleep | Y | Y | +Hibernate | Y | Y | +Stop | | Y | + +For the ARM-based devices (PSoC 4), an interrupt is required for the CPU to wake up. The Power Management implementation +assumes that wakeup time is configured with a separate component (component-based wakeup time configuration) for an +interrupt to be issued on terminal count. + +All pending interrupts should be cleared before the device is put into low power mode, even if they are masked. + +The Power Management API is provided in the CyPm.c and CyPm.h files. + + +\section group_power_management_implementation Implementation +For PSoC 4100, PSoC 4000U and PSoC 4200 devices, the software should set EXT_VCCD bit in the PWR_CONTROL register when +Vccd is shorted to Vddd on the board. This impacts the chip internal state transitions where it is necessary to know +whether Vccd is connected or floating to achieve minimum current in low power modes. Note Setting this bit turns off +the active regulator and will lead to a system reset unless both Vddd and Vccd pins are supplied externally. Refer to +the device TRM for more information. + +It is safe to call PM APIs from the ISR. The wakeup conditions for Sleep and DeepSleep low power modes are illustrated +in the following table. + +Interrupts State | Condition | Wakeup | ISR Execution | +------------------|---------------------------------|-----------|------------------ | +Unmasked | IRQ priority > current level | Yes | Yes | +Unmasked | IRQ priority ≤ current level | No | No | +Masked | IRQ priority > current level | Yes | No | +Masked | IRQ priority ≤ current level | No | No | + + +\section group_power_management_clocks Clock Configuration +For PSoC 4100 BLE and PSoC 4200 BLE devices, the HFCLK source should be set to IMO before switching the device into low +power mode. The IMO should be enabled (by calling CySysClkImoStart(), if it is not) and HFCLK source should be changed +to IMO by calling CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO). + +If the System clock frequency is increased by switching to the IMO, the CySysFlashSetWaitCycles() function with an +appropriate parameter should be called beforehand. Also, it can optionally be called after lowering the System clock +frequency in order to improve CPU performance. See CySysFlashSetWaitCycles() description for the details. + + + + + +*/ +void CySysPmSleep(void); +void CySysPmDeepSleep(void); + +#if(CY_IP_SRSSV2) + void CySysPmHibernate(void); + void CySysPmFreezeIo(void); + void CySysPmUnfreezeIo(void); + uint32 CySysPmGetResetReason(void); + void CySysPmStop(void); + void CySysPmSetWakeupPolarity(uint32 polarity); +#else + void CySysPmSetWakeupHoldoff(uint32 hfclkFrequencyMhz); +#endif /* (CY_IP_SRSSV2) */ + +/** @} group_power_management */ + + +/******************************************************************************* +* The ARM compilers have the __wfi() intrinsic that inserts a WFI instruction +* into the instruction stream generated by the compiler. The GCC compiler has to +* execute assembly language instruction. +*******************************************************************************/ +#if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() +#else /* ASM for GCC & IAR */ + #define CY_PM_WFI __asm volatile ("WFI \n") +#endif /* __ARMCC_VERSION */ + +#if(CY_IP_SRSSV2) + + /* CySysPmSetWakeupPolarity() */ + #define CY_PM_STOP_WAKEUP_ACTIVE_LOW ((uint32)(0x0u)) /**< Logical zero will wakeup the chip */ + #define CY_PM_STOP_WAKEUP_ACTIVE_HIGH ((uint32)(0x1u)) /**< Logical one will wakeup the chip */ + #define CY_PM_STOP_WAKEUP_POLARITY (CY_PM_STOP_WAKEUP_ACTIVE_LOW) + + /* CySysPmGetResetReason() */ + #define CY_PM_RESET_REASON_UNKN (0u) /**< Unknown reset reason. */ + #define CY_PM_RESET_REASON_XRES (1u) /**< Transition from OFF/XRES to RESET */ + #define CY_PM_RESET_REASON_WAKEUP_HIB (2u) /**< Transition/wakeup from HIBERNATE to RESET */ + #define CY_PM_RESET_REASON_WAKEUP_STOP (3u) /**< Transition/wakeup from STOP to RESET */ + +#endif /* (CY_IP_SRSSV2) */ + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Control */ +#define CY_PM_PWR_CONTROL_REG (*(reg32 *) CYREG_PWR_CONTROL) +#define CY_PM_PWR_CONTROL_PTR ( (reg32 *) CYREG_PWR_CONTROL) + +/* CPU System Control Register */ +#if (CY_IP_CPUSS_CM0) + #define CY_PM_CPU_SCR_REG (*(reg32 *) CYREG_CM0_SCR) + #define CY_PM_CPU_SCR_PTR ( (reg32 *) CYREG_CM0_SCR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_PM_CPU_SCR_REG (*(reg32 *) CYREG_CM0P_SCR) + #define CY_PM_CPU_SCR_PTR ( (reg32 *) CYREG_CM0P_SCR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/* Power System Key & Delay Register */ +#define CY_PM_PWR_KEY_DELAY_REG (*(reg32 *) CYREG_PWR_KEY_DELAY) +#define CY_PM_PWR_KEY_DELAY_PTR ( (reg32 *) CYREG_PWR_KEY_DELAY) + + +#if(CY_IP_SRSSV2) + /* Hibernate wakeup value for PWR_KEY_DELAY */ + #define CY_SFLASH_HIB_KEY_DELAY_REG (*(reg16 *) CYREG_SFLASH_HIB_KEY_DELAY) + #define CY_SFLASH_HIB_KEY_DELAY_PTR ( (reg16 *) CYREG_SFLASH_HIB_KEY_DELAY) +#endif /* (CY_IP_SRSSV2) */ + +/* Deep Sleep wakeup value for PWR_KEY_DELAY */ +#define CY_SFLASH_DPSLP_KEY_DELAY_REG (*(reg16 *) CYREG_SFLASH_DPSLP_KEY_DELAY) +#define CY_SFLASH_DPSLP_KEY_DELAY_PTR ( (reg16 *) CYREG_SFLASH_DPSLP_KEY_DELAY) + +/* Power Stop Mode Register */ +#if(CY_IP_SRSSV2) + #define CY_PM_PWR_STOP_REG (*(reg32 *) CYREG_PWR_STOP) + #define CY_PM_PWR_STOP_PTR ( (reg32 *) CYREG_PWR_STOP) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + /* CPU Subsystem Configuration */ + #define CY_PM_CPUSS_CONFIG_REG (*(reg32 *) CYREG_CPUSS_CONFIG) + #define CY_PM_CPUSS_CONFIG_PTR ( (reg32 *) CYREG_CPUSS_CONFIG) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* CM0 System Control Register Constants */ +#define CY_PM_CPU_SCR_SLEEPDEEP ((uint32)(0x04u)) + +#if(CY_IP_SRSSV2) + /* Power Mode Control Constants */ + #define CY_PM_PWR_CONTROL_HIBERNATE (0x80000000u) + + /* Power Mode Stop Constants */ + #define CY_PM_PWR_STOP_POLARITY_SHIFT (16u) + #define CY_PM_PWR_STOP_POLARITY ((uint32)((uint32)1u << CY_PM_PWR_STOP_POLARITY_SHIFT)) + #define CY_PM_PWR_STOP_FREEZE_SHIFT (17u) + #define CY_PM_PWR_STOP_FREEZE ((uint32)((uint32)1u << CY_PM_PWR_STOP_FREEZE_SHIFT)) + #define CY_PM_PWR_STOP_UNLOCK_SHIFT (8u) + #define CY_PM_PWR_STOP_UNLOCK_MASK ((uint32)((uint32)0xFFu << CY_PM_PWR_STOP_UNLOCK_SHIFT)) + #define CY_PM_PWR_STOP_UNLOCK ((uint32)((uint32)0x3Au << CY_PM_PWR_STOP_UNLOCK_SHIFT)) + #define CY_PM_PWR_STOP_STOP_SHIFT (31u) + #define CY_PM_PWR_STOP_STOP ((uint32)((uint32)1u << CY_PM_PWR_STOP_STOP_SHIFT)) + #define CY_PM_PWR_STOP_TOKEN_MASK ((uint32)(0xFFu)) + #define CY_PM_PWR_STOP_TOKEN_XRES ((uint32)(0x00u)) + #define CY_PM_PWR_STOP_TOKEN_HIB ((uint32)(0xF1u)) + #define CY_PM_PWR_STOP_TOKEN_STOP ((uint32)(0xF2u)) +#else + #define CY_PM_PWR_KEY_DELAY_REG_DEFAULT ((uint32) 248u) + #define CY_PM_PWR_KEY_DELAY_FREQ_DEFAULT (48u) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + /* 0 - normal operation, 1 - Flash Accelerator in bypass mode */ + #define CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS ((uint32) 0x02u) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + + +#if (CY_IP_SRSSV2) + #if (CY_IP_HOBTO_DEVICE) + /******************************************************************************* + * Function Name: CySysPmHibPinsDisableInputBuf + ****************************************************************************//** + * + * Disable the input buffer for all the port. This is required before Hibernate + * mode entry as the operation of the input buffer is not guaranteed if VCCD + * drops down to 1.0 V. + * + *******************************************************************************/ + static CY_INLINE void CySysPmHibPinsDisableInputBuf(void) + { + #ifdef CYREG_GPIO_PRT0_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT0_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT0_PC */ + + #ifdef CYREG_GPIO_PRT1_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT1_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT1_PC */ + + #ifdef CYREG_GPIO_PRT2_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT2_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT2_PC */ + + #ifdef CYREG_GPIO_PRT3_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT3_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT3_PC */ + + #ifdef CYREG_GPIO_PRT4_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT4_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT4_PC */ + + #ifdef CYREG_GPIO_PRT5_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT5_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT5_PC */ + + #ifdef CYREG_GPIO_PRT6_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT6_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT6_PC */ + + #ifdef CYREG_GPIO_PRT7_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT7_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT7_PC */ + + #ifdef CYREG_GPIO_PRT8_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT8_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT8_PC */ + + #ifdef CYREG_GPIO_PRT9_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT9_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT9_PC */ + + #ifdef CYREG_GPIO_PRT10_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT10_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT10_PC */ + + #ifdef CYREG_GPIO_PRT11_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT11_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT11_PC */ + + #ifdef CYREG_GPIO_PRT12_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT12_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT12_PC */ + + #ifdef CYREG_GPIO_PRT13_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT13_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT13_PC */ + + #ifdef CYREG_GPIO_PRT14_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT14_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT14_PC */ + + #ifdef CYREG_GPIO_PRT15_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT15_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT15_PC */ + } + #endif /* (CY_IP_HOBTO_DEVICE) */ +#endif /* (CY_IP_SRSSV2) */ + + +#if (CY_IP_CPUSS_CM0) + #define CY_PM_CM0_SCR_REG (CY_PM_CPU_SCR_REG) + #define CY_PM_CM0_SCR_PTR (CY_PM_CPU_SCR_PTR) + #define CY_PM_CM0_SCR_SLEEPDEEP (CY_PM_CPU_SCR_SLEEPDEEP) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#endif /* CY_BOOT_CYPM_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cy_em_eeprom.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cy_em_eeprom.c new file mode 100644 index 0000000..ce94d9c --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cy_em_eeprom.c @@ -0,0 +1,1416 @@ +/***************************************************************************//** +* \file cy_em_eeprom.c +* \version 2.0 +* +* \brief +* This file provides source code of the API for the Emulated EEPROM library. +* The Emulated EEPROM API allows creating of an emulated EEPROM in flash that +* has the ability to do wear leveling and restore corrupted data from a +* redundant copy. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "cytypes.h" +#include + +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include "em_eeprom/cy_em_eeprom.h" +#else + #include "cy_em_eeprom.h" +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Private Function Prototypes +***************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context); +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context); +static uint8 CalcChecksum(uint8 rowData[], uint32 len); +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config); +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context); +static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint32 addr, uint32 len); +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context); + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Init +****************************************************************************//** +* +* Initializes the Emulated EEPROM library by filling the context structure. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \param context +* The pointer to the EEPROM context structure to be filled by the function. +* \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* The context structure should not be modified by the user after it is filled +* with this function. Modification of context structure may cause the +* unexpected behavior of the Cy_Em_EEPROM API functions which rely on it. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* If the "Redundant Copy" option is used, the function performs a number of +* write operations to the EEPROM to initialize flash rows checksums. Therefore, +* Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(), +* will return a non-zero value that identifies the number of writes performed +* by Cy_Em_EEPROM_Init(). +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) && + (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSize != 0u)) + { + ret = CheckRanges(config); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Copy the user config structure fields into context */ + context->eepromSize = config->eepromSize; + context->wearLevelingFactor = config->wearLevelingFactor; + context->redundantCopy = config->redundantCopy; + context->blockingWrite = config->blockingWrite; + context->userFlashStartAddr = config->userFlashStartAddr; + /* Store frequently used data for internal use */ + context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize); + context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->wearLevelingFactor) + + config->userFlashStartAddr); + /* Find last written EEPROM row and store it for quick access */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + + if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundantCopy)) + { + /* Call the function only after device reprogramming in case + * if redundant copy is enabled. + */ + ret = FillChecksum(context); + + /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Read +****************************************************************************//** +* +* This function takes the logical EEPROM address, converts it to the actual +* physical address where the data is stored and returns the data to the user. +* +* \param addr +* The logical start address in EEPROM to start reading data from. +* +* \param eepromData +* The pointer to a user array to write data to. +* +* \param size +* The amount of data to read. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \note +* In case if redundant copy option is enabled the function may perform writes +* to EEPROM. This is done in case if the data in the EEPPROM is corrupted and +* the data in redundant copy is valid based on CRC-8 data integrity check. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 numBytesToRead; + uint32 curEepromBaseAddr; + uint32 curRowOffset; + uint32 startRowAddr; + uint32 actEepromRowNum; + uint32 curRdEepromRowNum = 0u; + uint32 dataStartEepromRowNum = 0u; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Validate input parameters */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 rdAddr = addr; + uint32 rdSize = size; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr); + uint32 updateAddrFlag = 0u; + + /* Calculate the number of the row read operations. Currently this only concerns + * the reads from the EEPROM data locations. + */ + uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) - + (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + + /* Get the address of the first row of the currently active EEPROM sector. If + * no wear leveling is used - the EEPROM has only one sector, so use the base + * addr stored in "context->userFlashStartAddr". + */ + curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) / + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) + + context->userFlashStartAddr; + + /* Find the number of the row that contains the start address of the data */ + for(i = 0u; i < context->numberOfRows; i++) + { + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i)) + { + dataStartEepromRowNum = i; + curRdEepromRowNum = dataStartEepromRowNum; + break; + } + } + + /* Find the row number of the last written row */ + actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + /* Check if wear leveling is used */ + if(context->wearLevelingFactor > 1u) + { + uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u); + + /* Check if the future validation of the read address is required. */ + updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u : + ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u); + } + + /* Copy data from the EEPROM data locations to the user buffer */ + for(i = 0u; i < numRowReads; i++) + { + startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Check if there are more reads pending and update the number of the + * remaining bytes to read respectively. + */ + if((i + 1u) < numRowReads) + { + numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + } + else + { + numBytesToRead = rdSize; + } + + /* Check if the read address needs to be updated to point to the correct + * EEPROM sector. + */ + if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum)) + { + startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if(startRowAddr < context->userFlashStartAddr) + { + startRowAddr = context->wlEndAddr - + ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + + if(0u != context->redundantCopy) + { + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + * the corresponding row in redundant copy, otherwise return failure. + */ + ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + /* Copy the data to the user buffer */ + (void)memcpy((void *)(eeData), + (void *)(startRowAddr + curRowOffset), + numBytesToRead); + + /* Indicate success to be able to execute next code block */ + ret = CY_EM_EEPROM_SUCCESS; + } + + /* Update variables anticipated in the read operation */ + rdAddr += numBytesToRead; + rdSize -= numBytesToRead; + eeData += numBytesToRead; + curRdEepromRowNum++; + } + + /* This code block will copy the latest data from the EEPROM headers into the + * user buffer. The data previously copied into the user buffer may be updated + * as the EEPROM headers contain more recent data. + * The code block is executed when two following conditions are true: + * 1) The reads from "historic" data locations were successful; + * 2) The user performed at least one write operation to Em_EEPROM (0u != + * seqNum). + */ + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum)) + { + numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum); + numRowReads--; + + for(i = (seqNum - numRowReads); i <= seqNum; i++) + { + startRowAddr = GetRowAddrBySeqNum(i, context); + + if (0u != startRowAddr) + { + /* The following variables are introduced to increase code readability. */ + uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET); + uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + + /* Check if the current row EEPROM header contains the data requested for read */ + if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + size)) + { + uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr); + uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u); + rdAddr = (startAddr > addr) ? (startAddr) : (addr); + + srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET; + + /* Calculate the number of bytes to be read from the current row's EEPROM header */ + numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rdAddr; + + /* Calculate the offset in the user buffer from which the data will be updated. */ + eeData = ((uint32)eepromData) + dstOffset; + + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in the + * corresponding row in redundant copy, otherwise return failure. Copy the data + * from the recent EEPROM headers to the user buffer. This will overwrite the + * data copied form EEPROM data locations as the data in EEPROM headers is newer. + */ + if(0u != context->redundantCopy) + { + ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numBytesToRead); + } + } + } + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Write +****************************************************************************//** +* +* This function takes the logical EEPROM address and converts it to the actual +* physical address and writes data there. If wear leveling is implemented, the +* writing process will use the wear leveling techniques. This is a blocking +* function and it does not return until the write operation is completed. The +* user firmware should not enter Hibernate mode until write is completed. The +* write operation is allowed in Sleep and Deep-Sleep modes. During the flash +* operation, the device should not be reset, including the XRES pin, a software +* reset, and watchdog reset sources. Also, low-voltage detect circuits should +* be configured to generate an interrupt instead of a reset. Otherwise, portions +* of flash may undergo unexpected changes. +* +* \param addr +* The logical start address in EEPROM to start writing data from. +* +* \param eepromData +* Data to write to EEPROM. +* +* \param size +* The amount of data to write to EEPROM. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform write +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM write is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 wrCnt; + uint32 actEmEepromRowNum; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 startAddr = 0u; + uint32 endAddr = 0u; + uint32 tmpRowAddr; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + void * tmpData; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Check if the EEPROM data does not exceed the EEPROM capacity */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u; + uint32 eeHeaderDataOffset = 0u; + + for(wrCnt = 0u; wrCnt < numWrites; wrCnt++) + { + uint32 skipOperation = 0u; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* Get the address of the row to be written. The "emEepromRowAddr" may be + * updated with the proper address (if wear leveling is used). The + * "emEepromRowRdAddr" will point to the row address from which the historic + * data will be read into the RAM buffer. + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + + /* Clear the RAM buffer so to not put junk into flash */ + (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Fill the EM_EEPROM header info for the row in the RAM buffer */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr; + tmpData = (void *) eeData; + + /* Check if this is the last row to write */ + if(wrCnt == (numWrites - 1u)) + { + /* Fill in the remaining size value to the EEPROM header. */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size; + } + else + { + /* This is not the last row to write in the current EEPROM write operation. + * Write the maximum possible data size to the EEPROM header. Update the + * size, eeData and addr respectively. + */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN; + size -= CY_EM_EEPROM_HEADER_DATA_LEN; + addr += CY_EM_EEPROM_HEADER_DATA_LEN; + eeData += CY_EM_EEPROM_HEADER_DATA_LEN; + } + + /* Write the data to the EEPROM header */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32], + tmpData, + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]); + + if(emEepromRowRdAddr != 0UL) + { + /* Copy the EEPROM historic data for this row from flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + /* Check if there is data for this location in other EEPROM headers: + * find out the row with the lowest possible sequence number which + * may contain the data for the current row. + */ + i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u; + + for(; i <= seqNum; i++) + { + if(i == seqNum) + { + /* The code reached the row that is about to be written. Analyze the recently + * created EEPROM header (stored in the RAM buffer currently): if it contains + * the data for EEPROM data locations in the row that is about to be written. + */ + tmpRowAddr = (uint32) writeRamBuffer; + } + else + { + /* Retrieve the address of the previously written row by its sequence number. + * The pointer will be used to get data from the respective EEPROM header. + */ + tmpRowAddr = GetRowAddrBySeqNum(i, context); + } + + actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr, + context->numberOfRows, + context->userFlashStartAddr); + if(0UL != tmpRowAddr) + { + /* Calculate the required addressed for the later EEPROM historic data update */ + skipOperation = GetAddresses( + &startAddr, + &endAddr, + &eeHeaderDataOffset, + actEmEepromRowNum, + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET), + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + } + else + { + /* Skip writes to the RAM buffer */ + skipOperation++; + } + + /* Write data to the RAM buffer */ + if(0u == skipOperation) + { + uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr; + + /* Update the address to point to the EEPROM header data and not to + * the start of the row. + */ + tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset; + (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr); + } + + /* Calculate the checksum if redundant copy is enabled */ + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + } + + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, writeRamBuffer, context); + tmpRowAddr = emEepromRowAddr; + + /* Check if redundant copy is used */ + if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret)) + { + /* Update the row address to point to the row in the redundant EEPROM's copy */ + tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Store last written row address only when EEPROM and redundant + * copy writes were successful. + */ + context->lastWrRowAddr = emEepromRowAddr; + } + else + { + break; + } + } + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Erase +****************************************************************************//** +* +* This function erases the entire contents of the EEPROM. Erased values are all +* zeros. This is a blocking function and it does not return until the write +* operation is completed. The user firmware should not enter Hibernate mode until +* erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage +* detect circuits should be configured to generate an interrupt instead of a +* reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* For all non PSoC 6 devices the erase operation is performed by clearing +* the EEPROM data using flash write. This affects the flash durability. +* So it is recommended to use this function in utmost case to prolongate +* flash life. +* +* \note +* This function uses a buffer of the flash row size to perform erase +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM erase is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 seqNum; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u}; +#if (CY_PSOC6) + uint32 emEepromStoredRowAddr = context->lastWrRowAddr; + uint32 storedSeqNum; +#endif /* (!CY_PSOC6) */ + + /* Get the sequence number of the last written row */ + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* If there were no writes to EEPROM - nothing to erase */ + if(0u != seqNum) + { + /* Calculate the number of row erase operations required */ + uint32 numWrites = context->numberOfRows * context->wearLevelingFactor; + + #if (CY_PSOC6) + GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context); + storedSeqNum = seqNum + 1u; + #endif /* (CY_PSOC6) */ + + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + for(i = 0u; i < numWrites; i++) + { + #if (CY_PSOC6) + /* For PSoC 6 the erase operation moves backwards. From last written row + * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr" + * is zero this means that the row identified by "seqNum" was previously + * erased. + */ + if(0u != emEepromRowAddr) + { + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + } + + seqNum--; + + if(0u == seqNum) + { + /* Exit the loop as there is no more row is EEPROM to be erased */ + break; + } + emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context); + #else + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + /* Get the address of the row to be erased. "emEepromRowAddr" may be updated + * with the proper address (if wear leveling is used). + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + seqNum++; + writeRamBuffer[0u] = seqNum; + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + #endif /* (CY_PSOC6) */ + } + + #if (CY_PSOC6) + if(CY_EM_EEPROM_SUCCESS == ret) + { + writeRamBuffer[0u] = storedSeqNum; + + /* Write the previously stored sequence number to the flash row which would be + * written next if the erase wouldn't happen. In this case the write to + * redundant copy can be skipped as it does not add any value. + */ + ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = emEepromStoredRowAddr; + } + } + #endif /* (CY_PSOC6) */ + + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_NumWrites +****************************************************************************//** +* +* Returns the number of the EEPROM writes completed so far. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* The number of writes performed to the EEPROM. +* +*******************************************************************************/ +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context) +{ + return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)); +} + +/** \} */ + +/** \cond INTERNAL */ + + +/******************************************************************************* +* Function Name: FindLastWrittenRow +****************************************************************************//** +* +* Performs a search of the last written row address of the EEPROM associated +* with the context structure. If there were no writes to the EEPROM the +* function returns the start address of the EEPROM. The row address is returned +* in the input parameter. +* +* \param lastWrRowPtr +* The pointer to a memory where the last written row will be returned. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context) +{ + uint32 seqNum = 0u; + uint32 prevSeqNum = 0u; + uint32 numRows; + uint32 emEepromAddr = context->userFlashStartAddr; + + *lastWrRowPtr = emEepromAddr; + + for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++) + { + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr); + if((0u != seqNum) && (seqNum > prevSeqNum)) + { + /* Some record in EEPROM was found. Store found sequence + * number and row address. + */ + prevSeqNum = seqNum; + *lastWrRowPtr = emEepromAddr; + } + + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } +} + + +/******************************************************************************* +* Function Name: GetRowAddrBySeqNum +****************************************************************************//** +* +* Returns the address of the row in EEPROM using its sequence number. +* +* \param seqNum +* The sequence number of the row. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* The address of the row or zero if the row with the sequence number was not +* found. +* +*******************************************************************************/ +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context) +{ + uint32 emEepromAddr = context->userFlashStartAddr; + + while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum) + { + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if (CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + { + emEepromAddr = 0u; + /* Exit the loop as we reached the end of EEPROM */ + break; + } + } + + return (emEepromAddr); +} + + +/******************************************************************************* +* Function Name: GetNextRowToWrite +****************************************************************************//** +* +* Performs a range check of the row that should be written and updates the +* address to the row respectively. The similar actions are done for the read +* address. +* +* \param seqNum +* The sequence number of the last written row. +* +* \param rowToWrPtr +* The address of the last written row (input). The address of the row to be +* written (output). +* +* \param rowToRdPtr +* The address of the row from which the data should be read into the RAM buffer +* in a later write operation. Out parameter. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context) +{ + /* Switch to the next row to be written if the current sequence number is + * not zero. + */ + if(0u != seqNum) + { + *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + + /* If the resulting row address is out of EEPROM, then switch to the base + * EEPROM address (Row#0). + */ + if(CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + { + *rowToWrPtr = context->userFlashStartAddr; + } + + *rowToRdPtr = 0u; + + /* Check if the sequence number is larger than the number of rows in the EEPROM. + * If not, do not update the row read address because there is no historic + * data to be read. + */ + if(context->numberOfRows <= seqNum) + { + /* Check if wear leveling is used in EEPROM */ + if(context->wearLevelingFactor > 1u) + { + /* The read row address should be taken from an EEPROM copy that became + * inactive recently. This condition check handles that. + */ + if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) < + context->userFlashStartAddr) + { + *rowToRdPtr = context->userFlashStartAddr + + (context->numberOfRows * (context->wearLevelingFactor - 1u) * + CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr); + } + else + { + *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + else + { + /* If no wear leveling, always read from the same flash row that + * should be written. + */ + *rowToRdPtr = *rowToWrPtr; + } + } +} + + +/******************************************************************************* +* Function Name: CalcChecksum +****************************************************************************//** +* +* Implements CRC-8 that is used in checksum calculation for the redundant copy +* algorithm. +* +* \param rowData +* The row data to be used to calculate the checksum. +* +* \param len +* The length of rowData. +* +* \return +* The calculated value of CRC-8. +* +*******************************************************************************/ +static uint8 CalcChecksum(uint8 rowData[], uint32 len) +{ + uint8 crc = CY_EM_EEPROM_CRC8_SEED; + uint8 i; + uint16 cnt = 0u; + + while(cnt != len) + { + crc ^= rowData[cnt]; + for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + { + crc = CY_EM_EEPROM_CALCULATE_CRC8(crc); + } + cnt++; + } + + return (crc); +} + + +/******************************************************************************* +* Function Name: CheckRanges +****************************************************************************//** +* +* Checks if the EEPROM of the requested size can be placed in flash. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA; + uint32 startAddr = config->userFlashStartAddr; + uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize, + config->wearLevelingFactor, config->redundantCopy); + + /* Range check if there is enough flash for EEPROM */ + if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + return (ret); +} + + +/******************************************************************************* +* Function Name: WriteRow +****************************************************************************//** +* +* Writes one flash row starting from the specified row address. +* +* \param rowAdd +* The address of the flash row. +* +* \param rowData +* The pointer to the data to be written to the row. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, + uint32 *rowData, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (!CY_PSOC6) + cystatus rc; + uint32 rowId; + #if ((CY_PSOC3) || (CY_PSOC5)) + uint32 arrayId; + #endif /* (CY_PSOC3) */ + + #if (CY_PSOC3) + rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK; + context = context; /* To avoid compiler warning generation */ + #else + (void)context; /* To avoid compiler warning generation */ + #endif /* ((CY_PSOC3) */ + + /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */ + rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY; + + /* Write the flash row */ + #if (CY_PSOC4) + rc = CySysFlashWriteRow(rowId, (uint8 *)rowData); + #else + + #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT + (void)CySetTemp(); + #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */ + + arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY; + rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData); + + #if (CY_PSOC5) + CyFlushCache(); + #endif /* (CY_PSOC5) */ + #endif /* (CY_PSOC4) */ + + if(CYRET_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } +#else /* PSoC 6 */ + if(0u != context->blockingWrite) + { + /* Do blocking write */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate write */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } +#endif /* (CY_PSOC6) */ + + return (ret); +} + + +/******************************************************************************* +* Function Name: EraseRow +****************************************************************************//** +* +* Erases one flash row starting from the specified row address. If the redundant +* copy option is enabled the corresponding row in the redundant copy will also +* be erased. +* +* \param rowAdd +* The address of the flash row. +* +* \param ramBuffAddr +* The address of the RAM buffer that contains zeroed data (used only for +* non-PSoC 6 devices). +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, + uint32 ramBuffAddr, + cy_stc_eeprom_context_t * context) +{ + uint32 emEepromRowAddr = rowAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (CY_PSOC6) + uint32 i = 1u; + + (void)ramBuffAddr; /* To avoid compiler warning */ + + if(0u != context->redundantCopy) + { + i++; + } + + do + { + if(0u != context->blockingWrite) + { + /* Erase the flash row */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate erase */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + } + else + { + break; + } + i--; + } while (0u != i); +#else + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy)) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = rowAddr; + } +#endif /* (CY_PSOC6) */ + + return(ret); +} + + +/******************************************************************************* +* Function Name: CheckCrcAndCopy +****************************************************************************//** +* +* Checks the checksum of the specific row in EEPROM. If the CRC matches - copies +* the data to the "datAddr" from EEPROM. f the CRC does not match checks the +* CRC of the corresponding row in the EEPROM's redundant copy. If the CRC +* matches - copies the data to the "datAddr" from EEPROM redundant copy. If the +* CRC of the redundant copy does not match - returns bad checksum. +* +* \param startAddr +* The address that points to the start of the specified row. +* +* \param datAddr +* The start address of where the row data will be copied if the CRC check +* will succeed. +* +* \param rowOffset +* The offset in the row from which the data should be copied. +* +* \param numBytes +* The number of bytes to be copied. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + + /* Calculate the row address in the EEPROM's redundant copy */ + uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Check the row data CRC in the EEPROM */ + if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes); + + ret = CY_EM_EEPROM_SUCCESS; + } + /* Check the row data CRC in the EEPROM's redundant copy */ + else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW) + * flash exception. The RWW occurs while trying to write and read the data from + * same flash macro. + */ + (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Restore bad row data from the RAM buffer */ + ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes); + } + } + else + { + ret = CY_EM_EEPROM_BAD_CHECKSUM; + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: GetAddresses +****************************************************************************//** +* +* Calculates the start and end address of the row's EEPROM data to be updated. +* The start and end are not absolute addresses but a relative addresses in a +* flash row. +* +* \param startAddr +* The pointer the address where the EEPROM data start address will be returned. +* +* \param endAddr +* The pointer the address where the EEPROM data end address will be returned. +* +* \param offset +* The pointer the address where the calculated offset of the EEPROM header data +* will be returned. +* +* \param rowNum +* The row number that is about to be written. +* +* \param addr +* The address of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \param len +* The length of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \return +* Zero indicates that the currently analyzed row has the data to be written to +* the active EEPROM row data locations. Non zero value indicates that there is +* no data to be written +* +*******************************************************************************/ +static uint32 GetAddresses(uint32 *startAddr, + uint32 *endAddr, + uint32 *offset, + uint32 rowNum, + uint32 addr, + uint32 len) +{ + uint32 skip = 0u; + + *offset =0u; + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *endAddr = *startAddr + len; + } + else + { + *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } + } + else + { + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN; + *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN)); + *offset = len - (*endAddr - *startAddr); + } + else + { + skip++; + } + } + + return (skip); +} + + +/******************************************************************************* +* Function Name: FillChecksum +****************************************************************************//** +* +* Performs calculation of the checksum on each row in the Em_EEPROM and fills +* the Em_EEPROM headers checksum field with the calculated checksums. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \theory +* In case if redundant copy option is used the Em_EEPROM would return bad +* checksum while trying to read the EEPROM rows which were not yet written by +* the user. E.g. any read after device reprogramming without previous Write() +* operation to the EEPROM would fail. This would happen because the Em_EEPROM +* headers checksum field values (which is zero at the moment) would not be +* equal to the actual data checksum. This function allows to avoid read failure +* after device reprogramming. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 rdAddr; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 wrAddr = context->lastWrRowAddr; + uint32 tmpRowAddr; + /* Get the sequence number (number of writes) */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr); + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++) + { + /* Copy the EEPROM row from Flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Increment the sequence number */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + + /* Calculate and fill the checksum to the Em_EEPROM header */ + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Write the data to the specified flash row */ + ret = WriteRow(wrAddr, writeRamBuffer, context); + + /* Update the row address to point to the relevant row in the redundant + * EEPROM's copy. + */ + tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + + /* Get the address of the next row to be written. + * "rdAddr" is not used in this function but provided to prevent NULL + * pointer exception in GetNextRowToWrite(). + */ + GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context); + } + + return(ret); +} + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cy_em_eeprom.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cy_em_eeprom.h new file mode 100644 index 0000000..4aef67b --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cy_em_eeprom.h @@ -0,0 +1,556 @@ +/******************************************************************************* +* \file cy_em_eeprom.h +* \version 2.0 +* +* \brief +* This file provides the function prototypes and constants for the Emulated +* EEPROM middleware library. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** + * \mainpage Cypress Em_EEPROM Middleware Library + * + * The Emulated EEPROM provides an API that allows creating an emulated + * EEPROM in flash that has the ability to do wear leveling and restore + * corrupted data from a redundant copy. The Emulated EEPROM library is designed + * to be used with the Em_EEPROM component. + * + * The Cy_Em_EEPROM API is described in the following sections: + * - \ref group_em_eeprom_macros + * - \ref group_em_eeprom_data_structures + * - \ref group_em_eeprom_enums + * - \ref group_em_eeprom_functions + * + * Features: + * * EEPROM-Like Non-Volatile Storage + * * Easy to use Read and Write API + * * Optional Wear Leveling + * * Optional Redundant Data storage + * + * \section group_em_eeprom_configuration Configuration Considerations + * + * The Em_EEPROM operates on the top of the flash driver. The flash driver has + * some prerequisites for proper operation. Refer to the "Flash System + * Routine (Flash)" section of the PDL API Reference Manual. + * + * Initializing Emulated EEPROM in User flash + * + * To initialize an Emulated EEPROM in the User flash, the EEPROM storage should + * be declared by the user. For the proper operation, the EEPROM storage should + * be aligned to the size of the flash row. An example of the EEPROM storage + * declaration is below (applicable for GCC and MDK compilers): + * + * CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * Note that the name "emEeprom" is shown for reference. Any other name can be + * used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is + * generated by the PSoC Creator Em_EEPROM component and so it is instance name + * dependent and its prefix should be changed when the name of the component + * changes. If the The Cy_Em_EEPROM middleware library is used without the + * Em_EEPROM component, the user has to provide a proper size for the EEPROM + * storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage + * can be calculated using the following equation: + * + * Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy) + * + * where, + * "EEPROM data size" - the size of data the user wants to store in the + * EEPROM. The data size must divide evenly to the half of the flash row size. + * "wear leveling" - the wear leveling factor (1-10). + * "redundant copy" - "zero" if a redundant copy is not used, and "one" + * otherwise. + * + * The start address of the storage should be filled to the Emulated EEPROM + * configuration structure and then passed to the Cy_Em_EEPROM_Init(). + * If the Em_EEPROM component is used, the config (Em_EEPROM_config) and + * context structures (Em_EEPROM_context) are defined by the component, so the + * user may just use that structures otherwise both of the structures need to + * be provided by the user. Note that if the "Config Data in Flash" + * option is selected in the component, then the configuration structure should + * be copied to RAM to allow EEPROM storage start address update. The following + * code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context" + * Em_EEPROM component structures for Cy_Em_EEPROM middleware library + * initialization: + * + * cy_en_em_eeprom_status_t retValue; + * cy_stc_eeprom_config_t config; + * + * memcpy((void *)&config, + (void *)&Em_EEPROM_config, + sizeof(cy_stc_eeprom_config_t)); + * config.userFlashStartAddr = (uint32)emEeprom; + * retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context); + * + * Initializing EEPROM in Emulated EEPROM flash area + * + * Initializing of the EEPROM storage in the Emulated EEPROM flash area is + * identical to initializing of the EEPROM storage in the User flash with one + * difference. The location of the Emulated EEPROM storage should be specified + * somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is + * utilized in the project, then the respective storage + * (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component + * if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to + * fill the start address of the storage to the config structure. If the + * Em_EEPROM component is not used, the user needs to declare the storage + * in the Emulated EEPROM flash area. An example of such declaration is + * following (applicable for GCC and MDK compilers): + * + * CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma location = ".cy_em_eeprom" + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * where, + * Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM + * component when the component is utilized in the project or it should be + * provided by the user. The equation for the calculation of the constant is + * shown above. + * + * Note that the size of the Emulated EEPROM flash area is limited. Refer to the + * specific device datasheet for the value of the available EEPROM Emulation + * area. + * + * \section group_em_eeprom_more_information More Information + * See the Em_EEPROM Component datasheet. + * + * + * \section group_em_eeprom_MISRA MISRA-C Compliance + * + * The Cy_Em_EEPROM library has the following specific deviations: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AThe cast should not be performed between a pointer to the object type + * and a different pointer to the object type.The cast from the object type and a different pointer to the object + * was used intentionally because of the performance reasons.
14.2RAll non-null statements shall either have at least one side-effect, + * however executed, or cause control flow to change.To maintain common codebase, some variables, unused for a specific + * device, are casted to void to prevent generation of an unused variable + * compiler warning.
16.7AThe object addressed by the pointer parameter is not modified and so + * the pointer could be of type 'pointer to const'.The warning is generated because of the pointer dereferencing to + * address which makes the MISRA checker think the data is not + * modified.
17.4RThe array indexing shall be the only allowed form of pointer + * arithmetic.The pointer arithmetic used in several places on the Cy_Em_EEPROM + * implementation is safe and preferred because it increases the code + * flexibility.
19.7AA function shall be used in preference to a function-like macro.Macro is used because of performance reasons.
+ * + * \section group_em_eeprom_changelog Changelog + * + * + * + * + * + * + * + *
VersionChangesReason for Change
1.0Initial Version
+ * + * \defgroup group_em_eeprom_macros Macros + * \brief + * This section describes the Emulated EEPROM Macros. + * + * \defgroup group_em_eeprom_functions Functions + * \brief + * This section describes the Emulated EEPROM Function Prototypes. + * + * \defgroup group_em_eeprom_data_structures Data Structures + * \brief + * Describes the data structures defined by the Emulated EEPROM. + * + * \defgroup group_em_eeprom_enums Enumerated types + * \brief + * Describes the enumeration types defined by the Emulated EEPROM. + * + */ + + +#if !defined(CY_EM_EEPROM_H) +#define CY_EM_EEPROM_H + +#include "cytypes.h" +#include +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include + #include "syslib/cy_syslib.h" + #include "flash/cy_flash.h" +#else + #include "CyFlash.h" + #include +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + +/* The C binding of definitions if building with the C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + + +/*************************************** +* Data Structure definitions +***************************************/ +/** +* \addtogroup group_em_eeprom_data_structures +* \{ +*/ + +/** EEPROM configuration structure */ +typedef struct +{ + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_config_t; + +/** \} group_em_eeprom_data_structures */ + +/** The EEPROM context data structure. It is used to store the specific +* EEPROM context data. +*/ +typedef struct +{ + /** The pointer to the end address of EEPROM including wear leveling overhead + * and excluding redundant copy overhead. + */ + uint32 wlEndAddr; + + /** The number of flash rows allocated for the EEPROM excluding the number of + * rows allocated for wear leveling and redundant copy overhead. + */ + uint32 numberOfRows; + + /** The address of the last written EEPROM row */ + uint32 lastWrRowAddr; + + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_context_t; + +#if (CY_PSOC6) + + #define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */ + /** + * \addtogroup group_em_eeprom_enums + * \{ + * Specifies return values meaning. + */ + /** A prefix for EEPROM function error return-values */ + #define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR) + +#else + + /** A prefix for EEPROM function status codes. For non-PSoC6 devices, + * prefix is zero. + */ + #define CY_EM_EEPROM_ID_ERROR (0uL) + +#endif /* (CY_PSOC6) */ + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/** EEPROM return enumeration type */ +typedef enum +{ + CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */ + CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */ + CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */ + CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */ + CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */ +} cy_en_em_eeprom_status_t; + +/** \} group_em_eeprom_enums */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context); +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context); +/** \} group_em_eeprom_functions */ + + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ +/** Library major version */ +#define CY_EM_EEPROM_VERSION_MAJOR (2) + +/** Library minor version */ +#define CY_EM_EEPROM_VERSION_MINOR (0) + +/** Defines the maximum data length that can be stored in one flash row */ +#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) + +/** \} group_em_eeprom_macros */ + + +/*************************************** +* Macro definitions +***************************************/ +/** \cond INTERNAL */ + +/* Defines the size of flash row */ +#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW) + +/* Device specific flash constants */ +#if (!CY_PSOC6) + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE) + #define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW) + #if (CY_PSOC3) + #define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL) + #define CY_EM_EEPROM_CODE_ADDR_END \ + (CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u)) + #define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu) + /* Checks if the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \ + ((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END)) + #else + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) + #endif /* (CY_PSOC3) */ +#else + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE) + #define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE) + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \ + (((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \ + ((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR)))) +#endif /* (!CY_PSOC6) */ + +#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE) + +/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */ +#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u) + +#define CY_EM_EEPROM_ADDR_IN_RANGE (1u) + +/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of +* EEPROM. The wear leveling overhead is included in the range but redundant copy +* is excluded. +*/ +#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \ + (((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE)) + +/* Check to see if the specified address is present in the EEPROM */ +#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \ + (((addr) > (startEepromAddr)) ? \ + (((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u)) + +/* Check if the EEPROM address locations from startAddr1 to endAddr1 +* are crossed with EEPROM address locations from startAddr2 to endAddr2. +*/ +#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \ + (((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \ + (((startAddr2) >= (endAddr1)) ? (0u) : (1u))) + +/* Return the pointer to the start of the redundant copy of the EEPROM */ +#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \ + ((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr)) + +/* Return the number of the row in EM_EEPROM which contains an address defined by +* rowAddr. + */ +#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \ + ((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows)) + + +/** Returns the size allocated for the EEPROM excluding wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) + +/* Check if the given address belongs to the EEPROM address of the row +* specified by rowNum. +*/ +#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \ + (((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \ + (((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \ + (0u) : (1u))) + +/* CRC-8 constants */ +#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u)) +#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u) +#define CY_EM_EEPROM_CRC8_SEED (0xFFu) +#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u)) + +#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \ + ((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \ + ((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u))) + +#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr)) + +/** \endcond */ + +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ + +/** Calculate the number of flash rows required to create an Em_EEPROM of +* dataSize. +*/ +#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \ + (((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \ + ((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U)) + +/** Returns the size of flash allocated for EEPROM including wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \ + (((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \ + CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \ + (wearLeveling)) * (1uL + (redundantCopy))) + +/** \} group_em_eeprom_macros */ + + +/****************************************************************************** +* Local definitions +*******************************************************************************/ +/** \cond INTERNAL */ + +/* Offsets for 32-bit RAM buffer addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u) +#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u) + +/* The same offsets as above used for direct memory addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u) + +#define CY_EM_EEPROM_U32_DIV (4u) + +/* Maximum wear leveling value */ +#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u) + +/* Maximum allowed flash row write/erase operation duration */ +#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u) + +/** \endcond */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* CY_EM_EEPROM_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cycodeshareexport.ld b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cycodeshareexport.ld new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cycodeshareimport.ld b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cycodeshareimport.ld new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cycodeshareimport.scat b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cycodeshareimport.scat new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevice_trm.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevice_trm.h new file mode 100644 index 0000000..47bacde --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevice_trm.h @@ -0,0 +1,6497 @@ +/******************************************************************************* +* File Name: cydevice_trm.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00008000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00008000u +#define CYDEV_SFLASH_BASE 0x0ffff000u +#define CYDEV_SFLASH_SIZE 0x00000200u +#define CYREG_SFLASH_PROT_ROW00 0x0ffff000u +#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000u +#define CYFLD_SFLASH_DATA8__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_ROW01 0x0ffff001u +#define CYREG_SFLASH_PROT_ROW02 0x0ffff002u +#define CYREG_SFLASH_PROT_ROW03 0x0ffff003u +#define CYREG_SFLASH_PROT_ROW04 0x0ffff004u +#define CYREG_SFLASH_PROT_ROW05 0x0ffff005u +#define CYREG_SFLASH_PROT_ROW06 0x0ffff006u +#define CYREG_SFLASH_PROT_ROW07 0x0ffff007u +#define CYREG_SFLASH_PROT_ROW08 0x0ffff008u +#define CYREG_SFLASH_PROT_ROW09 0x0ffff009u +#define CYREG_SFLASH_PROT_ROW10 0x0ffff00au +#define CYREG_SFLASH_PROT_ROW11 0x0ffff00bu +#define CYREG_SFLASH_PROT_ROW12 0x0ffff00cu +#define CYREG_SFLASH_PROT_ROW13 0x0ffff00du +#define CYREG_SFLASH_PROT_ROW14 0x0ffff00eu +#define CYREG_SFLASH_PROT_ROW15 0x0ffff00fu +#define CYREG_SFLASH_PROT_ROW16 0x0ffff010u +#define CYREG_SFLASH_PROT_ROW17 0x0ffff011u +#define CYREG_SFLASH_PROT_ROW18 0x0ffff012u +#define CYREG_SFLASH_PROT_ROW19 0x0ffff013u +#define CYREG_SFLASH_PROT_ROW20 0x0ffff014u +#define CYREG_SFLASH_PROT_ROW21 0x0ffff015u +#define CYREG_SFLASH_PROT_ROW22 0x0ffff016u +#define CYREG_SFLASH_PROT_ROW23 0x0ffff017u +#define CYREG_SFLASH_PROT_ROW24 0x0ffff018u +#define CYREG_SFLASH_PROT_ROW25 0x0ffff019u +#define CYREG_SFLASH_PROT_ROW26 0x0ffff01au +#define CYREG_SFLASH_PROT_ROW27 0x0ffff01bu +#define CYREG_SFLASH_PROT_ROW28 0x0ffff01cu +#define CYREG_SFLASH_PROT_ROW29 0x0ffff01du +#define CYREG_SFLASH_PROT_ROW30 0x0ffff01eu +#define CYREG_SFLASH_PROT_ROW31 0x0ffff01fu +#define CYREG_SFLASH_PROT_ROW32 0x0ffff020u +#define CYREG_SFLASH_PROT_ROW33 0x0ffff021u +#define CYREG_SFLASH_PROT_ROW34 0x0ffff022u +#define CYREG_SFLASH_PROT_ROW35 0x0ffff023u +#define CYREG_SFLASH_PROT_ROW36 0x0ffff024u +#define CYREG_SFLASH_PROT_ROW37 0x0ffff025u +#define CYREG_SFLASH_PROT_ROW38 0x0ffff026u +#define CYREG_SFLASH_PROT_ROW39 0x0ffff027u +#define CYREG_SFLASH_PROT_ROW40 0x0ffff028u +#define CYREG_SFLASH_PROT_ROW41 0x0ffff029u +#define CYREG_SFLASH_PROT_ROW42 0x0ffff02au +#define CYREG_SFLASH_PROT_ROW43 0x0ffff02bu +#define CYREG_SFLASH_PROT_ROW44 0x0ffff02cu +#define CYREG_SFLASH_PROT_ROW45 0x0ffff02du +#define CYREG_SFLASH_PROT_ROW46 0x0ffff02eu +#define CYREG_SFLASH_PROT_ROW47 0x0ffff02fu +#define CYREG_SFLASH_PROT_ROW48 0x0ffff030u +#define CYREG_SFLASH_PROT_ROW49 0x0ffff031u +#define CYREG_SFLASH_PROT_ROW50 0x0ffff032u +#define CYREG_SFLASH_PROT_ROW51 0x0ffff033u +#define CYREG_SFLASH_PROT_ROW52 0x0ffff034u +#define CYREG_SFLASH_PROT_ROW53 0x0ffff035u +#define CYREG_SFLASH_PROT_ROW54 0x0ffff036u +#define CYREG_SFLASH_PROT_ROW55 0x0ffff037u +#define CYREG_SFLASH_PROT_ROW56 0x0ffff038u +#define CYREG_SFLASH_PROT_ROW57 0x0ffff039u +#define CYREG_SFLASH_PROT_ROW58 0x0ffff03au +#define CYREG_SFLASH_PROT_ROW59 0x0ffff03bu +#define CYREG_SFLASH_PROT_ROW60 0x0ffff03cu +#define CYREG_SFLASH_PROT_ROW61 0x0ffff03du +#define CYREG_SFLASH_PROT_ROW62 0x0ffff03eu +#define CYREG_SFLASH_PROT_ROW63 0x0ffff03fu +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07fu +#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000u +#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002u +#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001u +#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000u +#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002u +#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003u +#define CYREG_SFLASH_AV_PAIRS_8B000 0x0ffff080u +#define CYREG_SFLASH_AV_PAIRS_8B001 0x0ffff081u +#define CYREG_SFLASH_AV_PAIRS_8B002 0x0ffff082u +#define CYREG_SFLASH_AV_PAIRS_8B003 0x0ffff083u +#define CYREG_SFLASH_AV_PAIRS_8B004 0x0ffff084u +#define CYREG_SFLASH_AV_PAIRS_8B005 0x0ffff085u +#define CYREG_SFLASH_AV_PAIRS_8B006 0x0ffff086u +#define CYREG_SFLASH_AV_PAIRS_8B007 0x0ffff087u +#define CYREG_SFLASH_AV_PAIRS_8B008 0x0ffff088u +#define CYREG_SFLASH_AV_PAIRS_8B009 0x0ffff089u +#define CYREG_SFLASH_AV_PAIRS_8B010 0x0ffff08au +#define CYREG_SFLASH_AV_PAIRS_8B011 0x0ffff08bu +#define CYREG_SFLASH_AV_PAIRS_8B012 0x0ffff08cu +#define CYREG_SFLASH_AV_PAIRS_8B013 0x0ffff08du +#define CYREG_SFLASH_AV_PAIRS_8B014 0x0ffff08eu +#define CYREG_SFLASH_AV_PAIRS_8B015 0x0ffff08fu +#define CYREG_SFLASH_AV_PAIRS_8B016 0x0ffff090u +#define CYREG_SFLASH_AV_PAIRS_8B017 0x0ffff091u +#define CYREG_SFLASH_AV_PAIRS_8B018 0x0ffff092u +#define CYREG_SFLASH_AV_PAIRS_8B019 0x0ffff093u +#define CYREG_SFLASH_AV_PAIRS_8B020 0x0ffff094u +#define CYREG_SFLASH_AV_PAIRS_8B021 0x0ffff095u +#define CYREG_SFLASH_AV_PAIRS_8B022 0x0ffff096u +#define CYREG_SFLASH_AV_PAIRS_8B023 0x0ffff097u +#define CYREG_SFLASH_AV_PAIRS_8B024 0x0ffff098u +#define CYREG_SFLASH_AV_PAIRS_8B025 0x0ffff099u +#define CYREG_SFLASH_AV_PAIRS_8B026 0x0ffff09au +#define CYREG_SFLASH_AV_PAIRS_8B027 0x0ffff09bu +#define CYREG_SFLASH_AV_PAIRS_8B028 0x0ffff09cu +#define CYREG_SFLASH_AV_PAIRS_8B029 0x0ffff09du +#define CYREG_SFLASH_AV_PAIRS_8B030 0x0ffff09eu +#define CYREG_SFLASH_AV_PAIRS_8B031 0x0ffff09fu +#define CYREG_SFLASH_AV_PAIRS_8B032 0x0ffff0a0u +#define CYREG_SFLASH_AV_PAIRS_8B033 0x0ffff0a1u +#define CYREG_SFLASH_AV_PAIRS_8B034 0x0ffff0a2u +#define CYREG_SFLASH_AV_PAIRS_8B035 0x0ffff0a3u +#define CYREG_SFLASH_AV_PAIRS_8B036 0x0ffff0a4u +#define CYREG_SFLASH_AV_PAIRS_8B037 0x0ffff0a5u +#define CYREG_SFLASH_AV_PAIRS_8B038 0x0ffff0a6u +#define CYREG_SFLASH_AV_PAIRS_8B039 0x0ffff0a7u +#define CYREG_SFLASH_AV_PAIRS_8B040 0x0ffff0a8u +#define CYREG_SFLASH_AV_PAIRS_8B041 0x0ffff0a9u +#define CYREG_SFLASH_AV_PAIRS_8B042 0x0ffff0aau +#define CYREG_SFLASH_AV_PAIRS_8B043 0x0ffff0abu +#define CYREG_SFLASH_AV_PAIRS_8B044 0x0ffff0acu +#define CYREG_SFLASH_AV_PAIRS_8B045 0x0ffff0adu +#define CYREG_SFLASH_AV_PAIRS_8B046 0x0ffff0aeu +#define CYREG_SFLASH_AV_PAIRS_8B047 0x0ffff0afu +#define CYREG_SFLASH_AV_PAIRS_8B048 0x0ffff0b0u +#define CYREG_SFLASH_AV_PAIRS_8B049 0x0ffff0b1u +#define CYREG_SFLASH_AV_PAIRS_8B050 0x0ffff0b2u +#define CYREG_SFLASH_AV_PAIRS_8B051 0x0ffff0b3u +#define CYREG_SFLASH_AV_PAIRS_8B052 0x0ffff0b4u +#define CYREG_SFLASH_AV_PAIRS_8B053 0x0ffff0b5u +#define CYREG_SFLASH_AV_PAIRS_8B054 0x0ffff0b6u +#define CYREG_SFLASH_AV_PAIRS_8B055 0x0ffff0b7u +#define CYREG_SFLASH_AV_PAIRS_8B056 0x0ffff0b8u +#define CYREG_SFLASH_AV_PAIRS_8B057 0x0ffff0b9u +#define CYREG_SFLASH_AV_PAIRS_8B058 0x0ffff0bau +#define CYREG_SFLASH_AV_PAIRS_8B059 0x0ffff0bbu +#define CYREG_SFLASH_AV_PAIRS_8B060 0x0ffff0bcu +#define CYREG_SFLASH_AV_PAIRS_8B061 0x0ffff0bdu +#define CYREG_SFLASH_AV_PAIRS_8B062 0x0ffff0beu +#define CYREG_SFLASH_AV_PAIRS_8B063 0x0ffff0bfu +#define CYREG_SFLASH_AV_PAIRS_8B064 0x0ffff0c0u +#define CYREG_SFLASH_AV_PAIRS_8B065 0x0ffff0c1u +#define CYREG_SFLASH_AV_PAIRS_8B066 0x0ffff0c2u +#define CYREG_SFLASH_AV_PAIRS_8B067 0x0ffff0c3u +#define CYREG_SFLASH_AV_PAIRS_8B068 0x0ffff0c4u +#define CYREG_SFLASH_AV_PAIRS_8B069 0x0ffff0c5u +#define CYREG_SFLASH_AV_PAIRS_8B070 0x0ffff0c6u +#define CYREG_SFLASH_AV_PAIRS_8B071 0x0ffff0c7u +#define CYREG_SFLASH_AV_PAIRS_8B072 0x0ffff0c8u +#define CYREG_SFLASH_AV_PAIRS_8B073 0x0ffff0c9u +#define CYREG_SFLASH_AV_PAIRS_8B074 0x0ffff0cau +#define CYREG_SFLASH_AV_PAIRS_8B075 0x0ffff0cbu +#define CYREG_SFLASH_AV_PAIRS_8B076 0x0ffff0ccu +#define CYREG_SFLASH_AV_PAIRS_8B077 0x0ffff0cdu +#define CYREG_SFLASH_AV_PAIRS_8B078 0x0ffff0ceu +#define CYREG_SFLASH_AV_PAIRS_8B079 0x0ffff0cfu +#define CYREG_SFLASH_AV_PAIRS_8B080 0x0ffff0d0u +#define CYREG_SFLASH_AV_PAIRS_8B081 0x0ffff0d1u +#define CYREG_SFLASH_AV_PAIRS_8B082 0x0ffff0d2u +#define CYREG_SFLASH_AV_PAIRS_8B083 0x0ffff0d3u +#define CYREG_SFLASH_AV_PAIRS_8B084 0x0ffff0d4u +#define CYREG_SFLASH_AV_PAIRS_8B085 0x0ffff0d5u +#define CYREG_SFLASH_AV_PAIRS_8B086 0x0ffff0d6u +#define CYREG_SFLASH_AV_PAIRS_8B087 0x0ffff0d7u +#define CYREG_SFLASH_AV_PAIRS_8B088 0x0ffff0d8u +#define CYREG_SFLASH_AV_PAIRS_8B089 0x0ffff0d9u +#define CYREG_SFLASH_AV_PAIRS_8B090 0x0ffff0dau +#define CYREG_SFLASH_AV_PAIRS_8B091 0x0ffff0dbu +#define CYREG_SFLASH_AV_PAIRS_8B092 0x0ffff0dcu +#define CYREG_SFLASH_AV_PAIRS_8B093 0x0ffff0ddu +#define CYREG_SFLASH_AV_PAIRS_8B094 0x0ffff0deu +#define CYREG_SFLASH_AV_PAIRS_8B095 0x0ffff0dfu +#define CYREG_SFLASH_AV_PAIRS_8B096 0x0ffff0e0u +#define CYREG_SFLASH_AV_PAIRS_8B097 0x0ffff0e1u +#define CYREG_SFLASH_AV_PAIRS_8B098 0x0ffff0e2u +#define CYREG_SFLASH_AV_PAIRS_8B099 0x0ffff0e3u +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4u +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5u +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6u +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7u +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8u +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9u +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0eau +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0ebu +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ecu +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0edu +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0eeu +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0efu +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0u +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1u +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2u +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3u +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4u +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5u +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6u +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7u +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8u +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9u +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fau +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fbu +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fcu +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fdu +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0feu +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ffu +#define CYREG_SFLASH_AV_PAIRS_32B00 0x0ffff100u +#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000u +#define CYFLD_SFLASH_DATA32__SIZE 0x00000020u +#define CYREG_SFLASH_AV_PAIRS_32B01 0x0ffff104u +#define CYREG_SFLASH_AV_PAIRS_32B02 0x0ffff108u +#define CYREG_SFLASH_AV_PAIRS_32B03 0x0ffff10cu +#define CYREG_SFLASH_AV_PAIRS_32B04 0x0ffff110u +#define CYREG_SFLASH_AV_PAIRS_32B05 0x0ffff114u +#define CYREG_SFLASH_AV_PAIRS_32B06 0x0ffff118u +#define CYREG_SFLASH_AV_PAIRS_32B07 0x0ffff11cu +#define CYREG_SFLASH_AV_PAIRS_32B08 0x0ffff120u +#define CYREG_SFLASH_AV_PAIRS_32B09 0x0ffff124u +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128u +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12cu +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130u +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134u +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138u +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13cu +#define CYREG_SFLASH_CPUSS_WOUNDING 0x0ffff140u +#define CYREG_SFLASH_SILICON_ID 0x0ffff144u +#define CYFLD_SFLASH_ID__OFFSET 0x00000000u +#define CYFLD_SFLASH_ID__SIZE 0x00000010u +#define CYREG_SFLASH_CPUSS_PRIV_RAM 0x0ffff148u +#define CYREG_SFLASH_CPUSS_PRIV_FLASH 0x0ffff14cu +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150u +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152u +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154u +#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u +#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158u +#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u +#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u +#define CYREG_SFLASH_FLASH_START 0x0ffff15cu +#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u +#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u +#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160u +#define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000u +#define CYFLD_SFLASH_TRIM8__SIZE 0x00000008u +#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161u +#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162u +#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163u +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164u +#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000u +#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010u +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166u +#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000u +#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010u +#define CYREG_SFLASH_SKIP_CHECKSUM 0x0ffff169u +#define CYFLD_SFLASH_SKIP__OFFSET 0x00000000u +#define CYFLD_SFLASH_SKIP__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170u +#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000u +#define CYFLD_SFLASH_KEY8__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171u +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172u +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173u +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174u +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175u +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176u +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177u +#define CYREG_SFLASH_DIE_LOT0 0x0ffff178u +#define CYFLD_SFLASH_LOT__OFFSET 0x00000000u +#define CYFLD_SFLASH_LOT__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_LOT1 0x0ffff179u +#define CYREG_SFLASH_DIE_LOT2 0x0ffff17au +#define CYREG_SFLASH_DIE_WAFER 0x0ffff17bu +#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u +#define CYFLD_SFLASH_WAFER__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_X 0x0ffff17cu +#define CYFLD_SFLASH_X__OFFSET 0x00000000u +#define CYFLD_SFLASH_X__SIZE 0x00000006u +#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000006u +#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000002u +#define CYREG_SFLASH_DIE_Y 0x0ffff17du +#define CYFLD_SFLASH_Y__OFFSET 0x00000000u +#define CYFLD_SFLASH_Y__SIZE 0x00000006u +#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000006u +#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000002u +#define CYREG_SFLASH_DIE_SORT 0x0ffff17eu +#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u +#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000002u +#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000002u +#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000002u +#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000004u +#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000002u +#define CYREG_SFLASH_DIE_MINOR 0x0ffff17fu +#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u +#define CYFLD_SFLASH_MINOR__SIZE 0x00000008u +#define CYREG_SFLASH_PE_TE_DATA00 0x0ffff180u +#define CYREG_SFLASH_PE_TE_DATA01 0x0ffff181u +#define CYREG_SFLASH_PE_TE_DATA02 0x0ffff182u +#define CYREG_SFLASH_PE_TE_DATA03 0x0ffff183u +#define CYREG_SFLASH_PE_TE_DATA04 0x0ffff184u +#define CYREG_SFLASH_PE_TE_DATA05 0x0ffff185u +#define CYREG_SFLASH_PE_TE_DATA06 0x0ffff186u +#define CYREG_SFLASH_PE_TE_DATA07 0x0ffff187u +#define CYREG_SFLASH_PE_TE_DATA08 0x0ffff188u +#define CYREG_SFLASH_PE_TE_DATA09 0x0ffff189u +#define CYREG_SFLASH_PE_TE_DATA10 0x0ffff18au +#define CYREG_SFLASH_PE_TE_DATA11 0x0ffff18bu +#define CYREG_SFLASH_PE_TE_DATA12 0x0ffff18cu +#define CYREG_SFLASH_PE_TE_DATA13 0x0ffff18du +#define CYREG_SFLASH_PE_TE_DATA14 0x0ffff18eu +#define CYREG_SFLASH_PE_TE_DATA15 0x0ffff18fu +#define CYREG_SFLASH_PE_TE_DATA16 0x0ffff190u +#define CYREG_SFLASH_PE_TE_DATA17 0x0ffff191u +#define CYREG_SFLASH_PE_TE_DATA18 0x0ffff192u +#define CYREG_SFLASH_PE_TE_DATA19 0x0ffff193u +#define CYREG_SFLASH_PE_TE_DATA20 0x0ffff194u +#define CYREG_SFLASH_PE_TE_DATA21 0x0ffff195u +#define CYREG_SFLASH_PE_TE_DATA22 0x0ffff196u +#define CYREG_SFLASH_PE_TE_DATA23 0x0ffff197u +#define CYREG_SFLASH_PE_TE_DATA24 0x0ffff198u +#define CYREG_SFLASH_PE_TE_DATA25 0x0ffff199u +#define CYREG_SFLASH_PE_TE_DATA26 0x0ffff19au +#define CYREG_SFLASH_PE_TE_DATA27 0x0ffff19bu +#define CYREG_SFLASH_PE_TE_DATA28 0x0ffff19cu +#define CYREG_SFLASH_PE_TE_DATA29 0x0ffff19du +#define CYREG_SFLASH_PE_TE_DATA30 0x0ffff19eu +#define CYREG_SFLASH_PE_TE_DATA31 0x0ffff19fu +#define CYREG_SFLASH_PP 0x0ffff1a0u +#define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000u +#define CYFLD_SFLASH_PERIOD__SIZE 0x00000018u +#define CYFLD_SFLASH_PDAC__OFFSET 0x00000018u +#define CYFLD_SFLASH_PDAC__SIZE 0x00000004u +#define CYFLD_SFLASH_NDAC__OFFSET 0x0000001cu +#define CYFLD_SFLASH_NDAC__SIZE 0x00000004u +#define CYREG_SFLASH_E 0x0ffff1a4u +#define CYREG_SFLASH_P 0x0ffff1a8u +#define CYREG_SFLASH_EA_E 0x0ffff1acu +#define CYREG_SFLASH_EA_P 0x0ffff1b0u +#define CYREG_SFLASH_ES_E 0x0ffff1b4u +#define CYREG_SFLASH_ES_P_EO 0x0ffff1b8u +#define CYREG_SFLASH_E_VCTAT 0x0ffff1bcu +#define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000u +#define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004u +#define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004u +#define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002u +#define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006u +#define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001u +#define CYREG_SFLASH_P_VCTAT 0x0ffff1bdu +#define CYREG_SFLASH_MARGIN 0x0ffff1beu +#define CYFLD_SFLASH_MDAC__OFFSET 0x00000000u +#define CYFLD_SFLASH_MDAC__SIZE 0x00000008u +#define CYREG_SFLASH_SPCIF_TRIM1 0x0ffff1bfu +#define CYFLD_SFLASH_BDAC__OFFSET 0x00000000u +#define CYFLD_SFLASH_BDAC__SIZE 0x00000004u +#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0u +#define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000u +#define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006u +#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1u +#define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006u +#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2u +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006u +#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3u +#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4u +#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5u +#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6u +#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7u +#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8u +#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9u +#define CYREG_SFLASH_IMO_ABS3 0x0ffff1cau +#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cbu +#define CYREG_SFLASH_IMO_ABS4 0x0ffff1ccu +#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cdu +#define CYREG_SFLASH_IMO_TRIM00 0x0ffff1d0u +#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u +#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u +#define CYREG_SFLASH_IMO_TRIM01 0x0ffff1d1u +#define CYREG_SFLASH_IMO_TRIM02 0x0ffff1d2u +#define CYREG_SFLASH_IMO_TRIM03 0x0ffff1d3u +#define CYREG_SFLASH_IMO_TRIM04 0x0ffff1d4u +#define CYREG_SFLASH_IMO_TRIM05 0x0ffff1d5u +#define CYREG_SFLASH_IMO_TRIM06 0x0ffff1d6u +#define CYREG_SFLASH_IMO_TRIM07 0x0ffff1d7u +#define CYREG_SFLASH_IMO_TRIM08 0x0ffff1d8u +#define CYREG_SFLASH_IMO_TRIM09 0x0ffff1d9u +#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1dau +#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1dbu +#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dcu +#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1ddu +#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1deu +#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1dfu +#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0u +#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1u +#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2u +#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3u +#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4u +#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5u +#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6u +#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7u +#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8u +#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9u +#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1eau +#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1ebu +#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ecu +#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1edu +#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1eeu +#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1efu +#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0u +#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1u +#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2u +#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3u +#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4u +#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5u +#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6u +#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7u +#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8u +#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9u +#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fau +#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fbu +#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fcu +#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fdu +#define CYREG_SFLASH_CHECKSUM 0x0ffff1feu +#define CYFLD_SFLASH_CHECKSUM__OFFSET 0x00000000u +#define CYFLD_SFLASH_CHECKSUM__SIZE 0x00000010u +#define CYDEV_SROM_BASE 0x10000000u +#define CYDEV_SROM_SIZE 0x00001000u +#define CYREG_SROM_DATA_MBASE 0x10000000u +#define CYREG_SROM_DATA_MSIZE 0x00001000u +#define CYDEV_SRAM_BASE 0x20000000u +#define CYDEV_SRAM_SIZE 0x00001000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00001000u +#define CYDEV_CPUSS_BASE 0x40000000u +#define CYDEV_CPUSS_SIZE 0x00010000u +#define CYREG_CPUSS_CONFIG 0x40000000u +#define CYFLD_CPUSS_VECS_IN_RAM__OFFSET 0x00000000u +#define CYFLD_CPUSS_VECS_IN_RAM__SIZE 0x00000001u +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET 0x00000001u +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE 0x00000001u +#define CYREG_CPUSS_SYSREQ 0x40000004u +#define CYFLD_CPUSS_COMMAND__OFFSET 0x00000000u +#define CYFLD_CPUSS_COMMAND__SIZE 0x00000010u +#define CYFLD_CPUSS_NO_RST_OVR__OFFSET 0x0000001bu +#define CYFLD_CPUSS_NO_RST_OVR__SIZE 0x00000001u +#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001cu +#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001u +#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001du +#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001u +#define CYFLD_CPUSS_HMASTER__OFFSET 0x0000001eu +#define CYFLD_CPUSS_HMASTER__SIZE 0x00000001u +#define CYFLD_CPUSS_SYSREQ__OFFSET 0x0000001fu +#define CYFLD_CPUSS_SYSREQ__SIZE 0x00000001u +#define CYREG_CPUSS_SYSARG 0x40000008u +#define CYFLD_CPUSS_ARG32__OFFSET 0x00000000u +#define CYFLD_CPUSS_ARG32__SIZE 0x00000020u +#define CYREG_CPUSS_PROTECTION 0x4000000cu +#define CYFLD_CPUSS_PROT__OFFSET 0x00000000u +#define CYFLD_CPUSS_PROT__SIZE 0x00000004u +#define CYVAL_CPUSS_PROT_VIRGIN 0x00000000u +#define CYVAL_CPUSS_PROT_OPEN 0x00000001u +#define CYVAL_CPUSS_PROT_PROTECTED 0x00000002u +#define CYVAL_CPUSS_PROT_KILL 0x00000004u +#define CYVAL_CPUSS_PROT_BOOT 0x00000008u +#define CYFLD_CPUSS_PROT_LOCK__OFFSET 0x0000001fu +#define CYFLD_CPUSS_PROT_LOCK__SIZE 0x00000001u +#define CYREG_CPUSS_PRIV_ROM 0x40000010u +#define CYFLD_CPUSS_ROM_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_ROM_LIMIT__SIZE 0x00000008u +#define CYREG_CPUSS_PRIV_RAM 0x40000014u +#define CYFLD_CPUSS_RAM_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_RAM_LIMIT__SIZE 0x00000009u +#define CYREG_CPUSS_PRIV_FLASH 0x40000018u +#define CYFLD_CPUSS_FLASH_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_FLASH_LIMIT__SIZE 0x0000000bu +#define CYREG_CPUSS_WOUNDING 0x4000001cu +#define CYFLD_CPUSS_RAM_SIZE__OFFSET 0x00000000u +#define CYFLD_CPUSS_RAM_SIZE__SIZE 0x00000009u +#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010u +#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003u +#define CYVAL_CPUSS_RAM_WOUND_FULL 0x00000000u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 0x00000001u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 0x00000002u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 0x00000003u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 0x00000004u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 0x00000005u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 0x00000006u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 0x00000007u +#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014u +#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003u +#define CYVAL_CPUSS_FLASH_WOUND_FULL 0x00000000u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 0x00000001u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 0x00000002u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 0x00000003u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 0x00000004u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 0x00000005u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 0x00000006u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 0x00000007u +#define CYREG_CPUSS_INTR_SELECT 0x40000020u +#define CYFLD_CPUSS_SELECT32__OFFSET 0x00000000u +#define CYFLD_CPUSS_SELECT32__SIZE 0x00000020u +#define CYDEV_HSIOM_BASE 0x40010000u +#define CYDEV_HSIOM_SIZE 0x00001000u +#define CYREG_HSIOM_PORT_SEL0 0x40010000u +#define CYFLD_HSIOM_SEL0__OFFSET 0x00000000u +#define CYFLD_HSIOM_SEL0__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL0_GPIO 0x00000000u +#define CYVAL_HSIOM_SEL0_GPIO_DSI 0x00000001u +#define CYVAL_HSIOM_SEL0_DSI_DSI 0x00000002u +#define CYVAL_HSIOM_SEL0_DSI_GPIO 0x00000003u +#define CYVAL_HSIOM_SEL0_CSD_SENSE 0x00000004u +#define CYVAL_HSIOM_SEL0_CSD_SHIELD 0x00000005u +#define CYVAL_HSIOM_SEL0_AMUXA 0x00000006u +#define CYVAL_HSIOM_SEL0_AMUXB 0x00000007u +#define CYVAL_HSIOM_SEL0_ACT_0 0x00000008u +#define CYVAL_HSIOM_SEL0_ACT_1 0x00000009u +#define CYVAL_HSIOM_SEL0_ACT_2 0x0000000au +#define CYVAL_HSIOM_SEL0_ACT_3 0x0000000bu +#define CYVAL_HSIOM_SEL0_LCD_COM 0x0000000cu +#define CYVAL_HSIOM_SEL0_LCD_SEG 0x0000000du +#define CYVAL_HSIOM_SEL0_DPSLP_0 0x0000000eu +#define CYVAL_HSIOM_SEL0_DPSLP_1 0x0000000fu +#define CYVAL_HSIOM_SEL0_COMP1_INP 0x00000000u +#define CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 0x0000000fu +#define CYFLD_HSIOM_SEL1__OFFSET 0x00000004u +#define CYFLD_HSIOM_SEL1__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL1_COMP1_INN 0x00000000u +#define CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 0x0000000fu +#define CYFLD_HSIOM_SEL2__OFFSET 0x00000008u +#define CYFLD_HSIOM_SEL2__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL2_COMP2_INP 0x00000000u +#define CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 0x0000000fu +#define CYFLD_HSIOM_SEL3__OFFSET 0x0000000cu +#define CYFLD_HSIOM_SEL3__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL3_COMP2_INN 0x00000000u +#define CYFLD_HSIOM_SEL4__OFFSET 0x00000010u +#define CYFLD_HSIOM_SEL4__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL4_SCB1_UART_RX 0x00000009u +#define CYVAL_HSIOM_SEL4_SCB1_I2C_SCL 0x0000000eu +#define CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI 0x0000000fu +#define CYFLD_HSIOM_SEL5__OFFSET 0x00000014u +#define CYFLD_HSIOM_SEL5__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL5_SCB1_UART_TX 0x00000009u +#define CYVAL_HSIOM_SEL5_SCB1_I2C_SDA 0x0000000eu +#define CYVAL_HSIOM_SEL5_SCB1_SPI_MISO 0x0000000fu +#define CYFLD_HSIOM_SEL6__OFFSET 0x00000018u +#define CYFLD_HSIOM_SEL6__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL6_EXT_CLK 0x00000008u +#define CYVAL_HSIOM_SEL6_SCB1_SPI_CLK 0x0000000fu +#define CYFLD_HSIOM_SEL7__OFFSET 0x0000001cu +#define CYFLD_HSIOM_SEL7__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL7_WAKEUP 0x0000000eu +#define CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 0x0000000fu +#define CYREG_HSIOM_PORT_SEL1 0x40010004u +#define CYREG_HSIOM_PORT_SEL2 0x40010008u +#define CYREG_HSIOM_PORT_SEL3 0x4001000cu +#define CYREG_HSIOM_PORT_SEL4 0x40010010u +#define CYDEV_CLK_BASE 0x40020000u +#define CYDEV_CLK_SIZE 0x00010000u +#define CYREG_CLK_DIVIDER_A00 0x40020000u +#define CYFLD_CLK_DIVIDER_A__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_A__SIZE 0x00000010u +#define CYFLD_CLK_ENABLE_A__OFFSET 0x0000001fu +#define CYFLD_CLK_ENABLE_A__SIZE 0x00000001u +#define CYREG_CLK_DIVIDER_A01 0x40020004u +#define CYREG_CLK_DIVIDER_A02 0x40020008u +#define CYREG_CLK_DIVIDER_B00 0x40020040u +#define CYFLD_CLK_DIVIDER_B__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_B__SIZE 0x00000010u +#define CYFLD_CLK_CASCADE_A_B__OFFSET 0x0000001eu +#define CYFLD_CLK_CASCADE_A_B__SIZE 0x00000001u +#define CYFLD_CLK_ENABLE_B__OFFSET 0x0000001fu +#define CYFLD_CLK_ENABLE_B__SIZE 0x00000001u +#define CYREG_CLK_DIVIDER_B01 0x40020044u +#define CYREG_CLK_DIVIDER_B02 0x40020048u +#define CYREG_CLK_DIVIDER_C00 0x40020080u +#define CYFLD_CLK_DIVIDER_C__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_C__SIZE 0x00000010u +#define CYFLD_CLK_CASCADE_B_C__OFFSET 0x0000001eu +#define CYFLD_CLK_CASCADE_B_C__SIZE 0x00000001u +#define CYFLD_CLK_ENABLE_C__OFFSET 0x0000001fu +#define CYFLD_CLK_ENABLE_C__SIZE 0x00000001u +#define CYREG_CLK_DIVIDER_C01 0x40020084u +#define CYREG_CLK_DIVIDER_C02 0x40020088u +#define CYREG_CLK_DIVIDER_FRAC_A00 0x40020100u +#define CYFLD_CLK_FRAC_A__OFFSET 0x00000010u +#define CYFLD_CLK_FRAC_A__SIZE 0x00000005u +#define CYREG_CLK_DIVIDER_FRAC_B00 0x40020140u +#define CYFLD_CLK_FRAC_B__OFFSET 0x00000010u +#define CYFLD_CLK_FRAC_B__SIZE 0x00000005u +#define CYREG_CLK_DIVIDER_FRAC_C00 0x40020180u +#define CYFLD_CLK_FRAC_C__OFFSET 0x00000010u +#define CYFLD_CLK_FRAC_C__SIZE 0x00000005u +#define CYREG_CLK_SELECT00 0x40020200u +#define CYFLD_CLK_DIVIDER_N__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_N__SIZE 0x00000004u +#define CYFLD_CLK_DIVIDER_ABC__OFFSET 0x00000004u +#define CYFLD_CLK_DIVIDER_ABC__SIZE 0x00000002u +#define CYVAL_CLK_DIVIDER_ABC_OFF 0x00000000u +#define CYVAL_CLK_DIVIDER_ABC_A 0x00000001u +#define CYVAL_CLK_DIVIDER_ABC_B 0x00000002u +#define CYVAL_CLK_DIVIDER_ABC_C 0x00000003u +#define CYREG_CLK_SELECT01 0x40020204u +#define CYREG_CLK_SELECT02 0x40020208u +#define CYREG_CLK_SELECT03 0x4002020cu +#define CYREG_CLK_SELECT04 0x40020210u +#define CYREG_CLK_SELECT05 0x40020214u +#define CYREG_CLK_SELECT06 0x40020218u +#define CYREG_CLK_SELECT07 0x4002021cu +#define CYREG_CLK_SELECT08 0x40020220u +#define CYREG_CLK_SELECT09 0x40020224u +#define CYREG_CLK_SELECT10 0x40020228u +#define CYREG_CLK_SELECT11 0x4002022cu +#define CYREG_CLK_SELECT12 0x40020230u +#define CYREG_CLK_SELECT13 0x40020234u +#define CYREG_CLK_SELECT14 0x40020238u +#define CYREG_CLK_SELECT15 0x4002023cu +#define CYDEV_TST_BASE 0x40030000u +#define CYDEV_TST_SIZE 0x00010000u +#define CYREG_TST_CTRL 0x40030000u +#define CYFLD_TST_DAP_NO_ACCESS__OFFSET 0x00000000u +#define CYFLD_TST_DAP_NO_ACCESS__SIZE 0x00000001u +#define CYFLD_TST_DAP_NO_DEBUG__OFFSET 0x00000001u +#define CYFLD_TST_DAP_NO_DEBUG__SIZE 0x00000001u +#define CYFLD_TST_SWD_CONNECTED__OFFSET 0x00000002u +#define CYFLD_TST_SWD_CONNECTED__SIZE 0x00000001u +#define CYFLD_TST_TEST_RESET_EN_N__OFFSET 0x00000008u +#define CYFLD_TST_TEST_RESET_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_SET_EN_N__OFFSET 0x00000009u +#define CYFLD_TST_TEST_SET_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_ICG_EN_N__OFFSET 0x0000000au +#define CYFLD_TST_TEST_ICG_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET 0x0000000bu +#define CYFLD_TST_TEST_OCC0_1_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET 0x0000000cu +#define CYFLD_TST_TEST_OCC0_2_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET 0x0000000du +#define CYFLD_TST_TEST_SLPISOLATE_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET 0x0000000eu +#define CYFLD_TST_TEST_SYSISOLATE_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET 0x0000000fu +#define CYFLD_TST_TEST_SLPRETAIN_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET 0x00000010u +#define CYFLD_TST_TEST_SYSRETAIN_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SPARE1_EN__OFFSET 0x00000011u +#define CYFLD_TST_TEST_SPARE1_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SPARE2_EN__OFFSET 0x00000012u +#define CYFLD_TST_TEST_SPARE2_EN__SIZE 0x00000001u +#define CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET 0x00000018u +#define CYFLD_TST_SCAN_OCC_OBSERVE__SIZE 0x00000001u +#define CYFLD_TST_SCAN_TRF1__OFFSET 0x00000019u +#define CYFLD_TST_SCAN_TRF1__SIZE 0x00000001u +#define CYFLD_TST_SCAN_TRF__OFFSET 0x0000001au +#define CYFLD_TST_SCAN_TRF__SIZE 0x00000001u +#define CYFLD_TST_SCAN_IDDQ__OFFSET 0x0000001bu +#define CYFLD_TST_SCAN_IDDQ__SIZE 0x00000001u +#define CYFLD_TST_SCAN_COMPRESS__OFFSET 0x0000001cu +#define CYFLD_TST_SCAN_COMPRESS__SIZE 0x00000001u +#define CYFLD_TST_SCAN_MODE__OFFSET 0x0000001du +#define CYFLD_TST_SCAN_MODE__SIZE 0x00000001u +#define CYFLD_TST_PTM_MODE_EN__OFFSET 0x0000001eu +#define CYFLD_TST_PTM_MODE_EN__SIZE 0x00000001u +#define CYREG_TST_ADFT_CTRL 0x40030004u +#define CYFLD_TST_ENABLE__OFFSET 0x0000001fu +#define CYFLD_TST_ENABLE__SIZE 0x00000001u +#define CYREG_TST_DDFT_CTRL 0x40030008u +#define CYFLD_TST_DFT_SEL1__OFFSET 0x00000000u +#define CYFLD_TST_DFT_SEL1__SIZE 0x00000006u +#define CYVAL_TST_DFT_SEL1_VSS 0x00000000u +#define CYVAL_TST_DFT_SEL1_CLK1 0x00000001u +#define CYVAL_TST_DFT_SEL1_CLK2 0x00000002u +#define CYVAL_TST_DFT_SEL1_PWR1 0x00000003u +#define CYVAL_TST_DFT_SEL1_PWR2 0x00000004u +#define CYVAL_TST_DFT_SEL1_VMON 0x00000005u +#define CYVAL_TST_DFT_SEL1_TSS_VDDA_OK 0x00000006u +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP1 0x00000007u +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP2 0x00000008u +#define CYVAL_TST_DFT_SEL1_TSS1 0x00000009u +#define CYVAL_TST_DFT_SEL1_TSS2 0x0000000au +#define CYVAL_TST_DFT_SEL1_TSS3 0x0000000bu +#define CYVAL_TST_DFT_SEL1_TSS4 0x0000000cu +#define CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS 0x0000000du +#define CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI 0x0000000eu +#define CYFLD_TST_DFT_SEL2__OFFSET 0x00000008u +#define CYFLD_TST_DFT_SEL2__SIZE 0x00000006u +#define CYVAL_TST_DFT_SEL2_VSS 0x00000000u +#define CYVAL_TST_DFT_SEL2_CLK1 0x00000001u +#define CYVAL_TST_DFT_SEL2_CLK2 0x00000002u +#define CYVAL_TST_DFT_SEL2_PWR1 0x00000003u +#define CYVAL_TST_DFT_SEL2_PWR2 0x00000004u +#define CYVAL_TST_DFT_SEL2_VMON 0x00000005u +#define CYVAL_TST_DFT_SEL2_TSS_VDDA_OK 0x00000006u +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP1 0x00000007u +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP2 0x00000008u +#define CYVAL_TST_DFT_SEL2_TSS1 0x00000009u +#define CYVAL_TST_DFT_SEL2_TSS2 0x0000000au +#define CYVAL_TST_DFT_SEL2_TSS3 0x0000000bu +#define CYVAL_TST_DFT_SEL2_TSS4 0x0000000cu +#define CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS 0x0000000du +#define CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI 0x0000000eu +#define CYFLD_TST_EDGE__OFFSET 0x0000001cu +#define CYFLD_TST_EDGE__SIZE 0x00000001u +#define CYVAL_TST_EDGE_POSEDGE 0x00000000u +#define CYVAL_TST_EDGE_NEGEDGE 0x00000001u +#define CYFLD_TST_DIVIDE__OFFSET 0x0000001du +#define CYFLD_TST_DIVIDE__SIZE 0x00000002u +#define CYVAL_TST_DIVIDE_DIRECT 0x00000000u +#define CYVAL_TST_DIVIDE_DIV_BY_2 0x00000001u +#define CYVAL_TST_DIVIDE_DIV_BY_4 0x00000002u +#define CYVAL_TST_DIVIDE_DIV_BY_8 0x00000003u +#define CYREG_TST_MODE 0x40030014u +#define CYFLD_TST_TEST_MODE__OFFSET 0x0000001fu +#define CYFLD_TST_TEST_MODE__SIZE 0x00000001u +#define CYREG_TST_TRIM_CNTR1 0x40030018u +#define CYFLD_TST_COUNTER__OFFSET 0x00000000u +#define CYFLD_TST_COUNTER__SIZE 0x00000010u +#define CYFLD_TST_COUNTER_DONE__OFFSET 0x0000001fu +#define CYFLD_TST_COUNTER_DONE__SIZE 0x00000001u +#define CYREG_TST_TRIM_CNTR2 0x4003001cu +#define CYDEV_PRT0_BASE 0x40040000u +#define CYDEV_PRT0_SIZE 0x00000100u +#define CYREG_PRT0_DR 0x40040000u +#define CYFLD_PRT_DATAREG__OFFSET 0x00000000u +#define CYFLD_PRT_DATAREG__SIZE 0x00000008u +#define CYREG_PRT0_PS 0x40040004u +#define CYFLD_PRT_PINSTATE__OFFSET 0x00000000u +#define CYFLD_PRT_PINSTATE__SIZE 0x00000008u +#define CYFLD_PRT_PINSTATE_FLT__OFFSET 0x00000008u +#define CYFLD_PRT_PINSTATE_FLT__SIZE 0x00000001u +#define CYREG_PRT0_PC 0x40040008u +#define CYFLD_PRT_DM__OFFSET 0x00000000u +#define CYFLD_PRT_DM__SIZE 0x00000018u +#define CYVAL_PRT_DM_OFF 0x00000000u +#define CYVAL_PRT_DM_INPUT 0x00000001u +#define CYVAL_PRT_DM_0_PU 0x00000002u +#define CYVAL_PRT_DM_PD_1 0x00000003u +#define CYVAL_PRT_DM_0_Z 0x00000004u +#define CYVAL_PRT_DM_Z_1 0x00000005u +#define CYVAL_PRT_DM_0_1 0x00000006u +#define CYVAL_PRT_DM_PD_PU 0x00000007u +#define CYFLD_PRT_VTRIP_SEL__OFFSET 0x00000018u +#define CYFLD_PRT_VTRIP_SEL__SIZE 0x00000001u +#define CYFLD_PRT_SLOW__OFFSET 0x00000019u +#define CYFLD_PRT_SLOW__SIZE 0x00000001u +#define CYREG_PRT0_INTCFG 0x4004000cu +#define CYFLD_PRT_INTTYPE__OFFSET 0x00000000u +#define CYFLD_PRT_INTTYPE__SIZE 0x00000010u +#define CYVAL_PRT_INTTYPE_DISABLE 0x00000000u +#define CYVAL_PRT_INTTYPE_RISING 0x00000001u +#define CYVAL_PRT_INTTYPE_FALLING 0x00000002u +#define CYVAL_PRT_INTTYPE_BOTH 0x00000003u +#define CYFLD_PRT_INTTYPE_FLT__OFFSET 0x00000010u +#define CYFLD_PRT_INTTYPE_FLT__SIZE 0x00000002u +#define CYVAL_PRT_INTTYPE_FLT_DISABLE 0x00000000u +#define CYVAL_PRT_INTTYPE_FLT_RISING 0x00000001u +#define CYVAL_PRT_INTTYPE_FLT_FALLING 0x00000002u +#define CYVAL_PRT_INTTYPE_FLT_BOTH 0x00000003u +#define CYFLD_PRT_FLT_SELECT__OFFSET 0x00000012u +#define CYFLD_PRT_FLT_SELECT__SIZE 0x00000003u +#define CYREG_PRT0_INTSTAT 0x40040010u +#define CYFLD_PRT_INTSTAT__OFFSET 0x00000000u +#define CYFLD_PRT_INTSTAT__SIZE 0x00000008u +#define CYFLD_PRT_INTSTAT_FLT__OFFSET 0x00000008u +#define CYFLD_PRT_INTSTAT_FLT__SIZE 0x00000001u +#define CYFLD_PRT_PS__OFFSET 0x00000010u +#define CYFLD_PRT_PS__SIZE 0x00000008u +#define CYFLD_PRT_PS_FLT__OFFSET 0x00000018u +#define CYFLD_PRT_PS_FLT__SIZE 0x00000001u +#define CYREG_PRT0_PC2 0x40040018u +#define CYFLD_PRT_INP_DIS__OFFSET 0x00000000u +#define CYFLD_PRT_INP_DIS__SIZE 0x00000008u +#define CYDEV_PRT1_BASE 0x40040100u +#define CYDEV_PRT1_SIZE 0x00000100u +#define CYREG_PRT1_DR 0x40040100u +#define CYREG_PRT1_PS 0x40040104u +#define CYREG_PRT1_PC 0x40040108u +#define CYREG_PRT1_INTCFG 0x4004010cu +#define CYREG_PRT1_INTSTAT 0x40040110u +#define CYREG_PRT1_PC2 0x40040118u +#define CYDEV_PRT2_BASE 0x40040200u +#define CYDEV_PRT2_SIZE 0x00000100u +#define CYREG_PRT2_DR 0x40040200u +#define CYREG_PRT2_PS 0x40040204u +#define CYREG_PRT2_PC 0x40040208u +#define CYREG_PRT2_INTCFG 0x4004020cu +#define CYREG_PRT2_INTSTAT 0x40040210u +#define CYREG_PRT2_PC2 0x40040218u +#define CYDEV_PRT3_BASE 0x40040300u +#define CYDEV_PRT3_SIZE 0x00000100u +#define CYREG_PRT3_DR 0x40040300u +#define CYREG_PRT3_PS 0x40040304u +#define CYREG_PRT3_PC 0x40040308u +#define CYREG_PRT3_INTCFG 0x4004030cu +#define CYREG_PRT3_INTSTAT 0x40040310u +#define CYREG_PRT3_PC2 0x40040318u +#define CYDEV_PRT4_BASE 0x40040400u +#define CYDEV_PRT4_SIZE 0x00000100u +#define CYREG_PRT4_DR 0x40040400u +#define CYREG_PRT4_PS 0x40040404u +#define CYREG_PRT4_PC 0x40040408u +#define CYREG_PRT4_INTCFG 0x4004040cu +#define CYREG_PRT4_INTSTAT 0x40040410u +#define CYREG_PRT4_PC2 0x40040418u +#define CYDEV_TCPWM_BASE 0x40050000u +#define CYDEV_TCPWM_SIZE 0x00001000u +#define CYREG_TCPWM_CTRL 0x40050000u +#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008u +#define CYREG_TCPWM_CMD 0x40050008u +#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008u +#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010u +#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018u +#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008u +#define CYREG_TCPWM_INTR_CAUSE 0x4005000cu +#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008u +#define CYDEV_TCPWM_CNT0_BASE 0x40050100u +#define CYDEV_TCPWM_CNT0_SIZE 0x00000040u +#define CYREG_TCPWM_CNT0_CTRL 0x40050100u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003u +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007u +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010u +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003u +#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012u +#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014u +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002u +#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018u +#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003u +#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000u +#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002u +#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003u +#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004u +#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005u +#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006u +#define CYREG_TCPWM_CNT0_STATUS 0x40050104u +#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001fu +#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001u +#define CYREG_TCPWM_CNT0_COUNTER 0x40050108u +#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_CC 0x4005010cu +#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_CC_BUFF 0x40050110u +#define CYREG_TCPWM_CNT0_PERIOD 0x40050114u +#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40050118u +#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40050120u +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000cu +#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010u +#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004u +#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40050124u +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006u +#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003u +#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40050128u +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003u +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003u +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003u +#define CYREG_TCPWM_CNT0_INTR 0x40050130u +#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001u +#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001u +#define CYREG_TCPWM_CNT0_INTR_SET 0x40050134u +#define CYREG_TCPWM_CNT0_INTR_MASK 0x40050138u +#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4005013cu +#define CYDEV_TCPWM_CNT1_BASE 0x40050140u +#define CYDEV_TCPWM_CNT1_SIZE 0x00000040u +#define CYREG_TCPWM_CNT1_CTRL 0x40050140u +#define CYREG_TCPWM_CNT1_STATUS 0x40050144u +#define CYREG_TCPWM_CNT1_COUNTER 0x40050148u +#define CYREG_TCPWM_CNT1_CC 0x4005014cu +#define CYREG_TCPWM_CNT1_CC_BUFF 0x40050150u +#define CYREG_TCPWM_CNT1_PERIOD 0x40050154u +#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40050158u +#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40050160u +#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40050164u +#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40050168u +#define CYREG_TCPWM_CNT1_INTR 0x40050170u +#define CYREG_TCPWM_CNT1_INTR_SET 0x40050174u +#define CYREG_TCPWM_CNT1_INTR_MASK 0x40050178u +#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4005017cu +#define CYDEV_TCPWM_CNT2_BASE 0x40050180u +#define CYDEV_TCPWM_CNT2_SIZE 0x00000040u +#define CYREG_TCPWM_CNT2_CTRL 0x40050180u +#define CYREG_TCPWM_CNT2_STATUS 0x40050184u +#define CYREG_TCPWM_CNT2_COUNTER 0x40050188u +#define CYREG_TCPWM_CNT2_CC 0x4005018cu +#define CYREG_TCPWM_CNT2_CC_BUFF 0x40050190u +#define CYREG_TCPWM_CNT2_PERIOD 0x40050194u +#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40050198u +#define CYREG_TCPWM_CNT2_TR_CTRL0 0x400501a0u +#define CYREG_TCPWM_CNT2_TR_CTRL1 0x400501a4u +#define CYREG_TCPWM_CNT2_TR_CTRL2 0x400501a8u +#define CYREG_TCPWM_CNT2_INTR 0x400501b0u +#define CYREG_TCPWM_CNT2_INTR_SET 0x400501b4u +#define CYREG_TCPWM_CNT2_INTR_MASK 0x400501b8u +#define CYREG_TCPWM_CNT2_INTR_MASKED 0x400501bcu +#define CYDEV_TCPWM_CNT3_BASE 0x400501c0u +#define CYDEV_TCPWM_CNT3_SIZE 0x00000040u +#define CYREG_TCPWM_CNT3_CTRL 0x400501c0u +#define CYREG_TCPWM_CNT3_STATUS 0x400501c4u +#define CYREG_TCPWM_CNT3_COUNTER 0x400501c8u +#define CYREG_TCPWM_CNT3_CC 0x400501ccu +#define CYREG_TCPWM_CNT3_CC_BUFF 0x400501d0u +#define CYREG_TCPWM_CNT3_PERIOD 0x400501d4u +#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x400501d8u +#define CYREG_TCPWM_CNT3_TR_CTRL0 0x400501e0u +#define CYREG_TCPWM_CNT3_TR_CTRL1 0x400501e4u +#define CYREG_TCPWM_CNT3_TR_CTRL2 0x400501e8u +#define CYREG_TCPWM_CNT3_INTR 0x400501f0u +#define CYREG_TCPWM_CNT3_INTR_SET 0x400501f4u +#define CYREG_TCPWM_CNT3_INTR_MASK 0x400501f8u +#define CYREG_TCPWM_CNT3_INTR_MASKED 0x400501fcu +#define CYDEV_SCB0_BASE 0x40060000u +#define CYDEV_SCB0_SIZE 0x00010000u +#define CYREG_SCB0_CTRL 0x40060000u +#define CYFLD_SCB_OVS__OFFSET 0x00000000u +#define CYFLD_SCB_OVS__SIZE 0x00000004u +#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008u +#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001u +#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009u +#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001u +#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000au +#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001u +#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010u +#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001u +#define CYFLD_SCB_BLOCK__OFFSET 0x00000011u +#define CYFLD_SCB_BLOCK__SIZE 0x00000001u +#define CYFLD_SCB_MODE__OFFSET 0x00000018u +#define CYFLD_SCB_MODE__SIZE 0x00000002u +#define CYVAL_SCB_MODE_I2C 0x00000000u +#define CYVAL_SCB_MODE_SPI 0x00000001u +#define CYVAL_SCB_MODE_UART 0x00000002u +#define CYFLD_SCB_ENABLED__OFFSET 0x0000001fu +#define CYFLD_SCB_ENABLED__SIZE 0x00000001u +#define CYREG_SCB0_STATUS 0x40060004u +#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000u +#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001u +#define CYREG_SCB0_SPI_CTRL 0x40060020u +#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000u +#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001u +#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001u +#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001u +#define CYFLD_SCB_CPHA__OFFSET 0x00000002u +#define CYFLD_SCB_CPHA__SIZE 0x00000001u +#define CYFLD_SCB_CPOL__OFFSET 0x00000003u +#define CYFLD_SCB_CPOL__SIZE 0x00000001u +#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004u +#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001u +#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010u +#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001u +#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001au +#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002u +#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001fu +#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001u +#define CYREG_SCB0_SPI_STATUS 0x40060024u +#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000u +#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001u +#define CYFLD_SCB_EZ_ADDR__OFFSET 0x00000008u +#define CYFLD_SCB_EZ_ADDR__SIZE 0x00000008u +#define CYREG_SCB0_UART_CTRL 0x40060040u +#define CYREG_SCB0_UART_TX_CTRL 0x40060044u +#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000u +#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003u +#define CYFLD_SCB_PARITY__OFFSET 0x00000004u +#define CYFLD_SCB_PARITY__SIZE 0x00000001u +#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005u +#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001u +#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008u +#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001u +#define CYREG_SCB0_UART_RX_CTRL 0x40060048u +#define CYFLD_SCB_POLARITY__OFFSET 0x00000006u +#define CYFLD_SCB_POLARITY__SIZE 0x00000001u +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009u +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000au +#define CYFLD_SCB_MP_MODE__SIZE 0x00000001u +#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000cu +#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001u +#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000du +#define CYFLD_SCB_SKIP_START__SIZE 0x00000001u +#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010u +#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004u +#define CYREG_SCB0_UART_RX_STATUS 0x4006004cu +#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000u +#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000cu +#define CYREG_SCB0_I2C_CTRL 0x40060060u +#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000u +#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004u +#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004u +#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004u +#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008u +#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001u +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009u +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001u +#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000bu +#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001u +#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000cu +#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000du +#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000eu +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000fu +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001u +#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001eu +#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001u +#define CYREG_SCB0_I2C_STATUS 0x40060064u +#define CYFLD_SCB_S_READ__OFFSET 0x00000004u +#define CYFLD_SCB_S_READ__SIZE 0x00000001u +#define CYFLD_SCB_M_READ__OFFSET 0x00000005u +#define CYFLD_SCB_M_READ__SIZE 0x00000001u +#define CYREG_SCB0_I2C_M_CMD 0x40060068u +#define CYFLD_SCB_M_START__OFFSET 0x00000000u +#define CYFLD_SCB_M_START__SIZE 0x00000001u +#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001u +#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001u +#define CYFLD_SCB_M_ACK__OFFSET 0x00000002u +#define CYFLD_SCB_M_ACK__SIZE 0x00000001u +#define CYFLD_SCB_M_NACK__OFFSET 0x00000003u +#define CYFLD_SCB_M_NACK__SIZE 0x00000001u +#define CYFLD_SCB_M_STOP__OFFSET 0x00000004u +#define CYFLD_SCB_M_STOP__SIZE 0x00000001u +#define CYREG_SCB0_I2C_S_CMD 0x4006006cu +#define CYFLD_SCB_S_ACK__OFFSET 0x00000000u +#define CYFLD_SCB_S_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NACK__OFFSET 0x00000001u +#define CYFLD_SCB_S_NACK__SIZE 0x00000001u +#define CYREG_SCB0_I2C_CFG 0x40060070u +#define CYFLD_SCB_SDA_FILT_HYS__OFFSET 0x00000000u +#define CYFLD_SCB_SDA_FILT_HYS__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_TRIM__OFFSET 0x00000002u +#define CYFLD_SCB_SDA_FILT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SCL_FILT_HYS__OFFSET 0x00000004u +#define CYFLD_SCB_SCL_FILT_HYS__SIZE 0x00000002u +#define CYFLD_SCB_SCL_FILT_TRIM__OFFSET 0x00000006u +#define CYFLD_SCB_SCL_FILT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET 0x00000008u +#define CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET 0x0000000au +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_HS__OFFSET 0x00000010u +#define CYFLD_SCB_SDA_FILT_HS__SIZE 0x00000001u +#define CYFLD_SCB_SDA_FILT_ENABLED__OFFSET 0x00000011u +#define CYFLD_SCB_SDA_FILT_ENABLED__SIZE 0x00000001u +#define CYFLD_SCB_SCL_FILT_HS__OFFSET 0x00000018u +#define CYFLD_SCB_SCL_FILT_HS__SIZE 0x00000001u +#define CYFLD_SCB_SCL_FILT_ENABLED__OFFSET 0x00000019u +#define CYFLD_SCB_SCL_FILT_ENABLED__SIZE 0x00000001u +#define CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET 0x0000001au +#define CYFLD_SCB_SDA_FILT_OUT_HS__SIZE 0x00000001u +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET 0x0000001bu +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE 0x00000001u +#define CYREG_SCB0_BIST_CONTROL 0x40060100u +#define CYFLD_SCB_RAM_ADDR__OFFSET 0x00000000u +#define CYFLD_SCB_RAM_ADDR__SIZE 0x00000005u +#define CYFLD_SCB_RAM_OP1__OFFSET 0x00000010u +#define CYFLD_SCB_RAM_OP1__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OP2__OFFSET 0x00000012u +#define CYFLD_SCB_RAM_OP2__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OP3__OFFSET 0x00000014u +#define CYFLD_SCB_RAM_OP3__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OP4__OFFSET 0x00000016u +#define CYFLD_SCB_RAM_OP4__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OPCNT__OFFSET 0x00000018u +#define CYFLD_SCB_RAM_OPCNT__SIZE 0x00000002u +#define CYFLD_SCB_RAM_PREADR__OFFSET 0x0000001au +#define CYFLD_SCB_RAM_PREADR__SIZE 0x00000001u +#define CYFLD_SCB_RAM_WORD__OFFSET 0x0000001bu +#define CYFLD_SCB_RAM_WORD__SIZE 0x00000001u +#define CYFLD_SCB_RAM_FAIL__OFFSET 0x0000001cu +#define CYFLD_SCB_RAM_FAIL__SIZE 0x00000001u +#define CYFLD_SCB_RAM_GO__OFFSET 0x0000001du +#define CYFLD_SCB_RAM_GO__SIZE 0x00000001u +#define CYREG_SCB0_BIST_DATA 0x40060104u +#define CYFLD_SCB_RAM_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_RAM_DATA__SIZE 0x00000010u +#define CYREG_SCB0_TX_CTRL 0x40060200u +#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000u +#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004u +#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008u +#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001u +#define CYREG_SCB0_TX_FIFO_CTRL 0x40060204u +#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000u +#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000003u +#define CYFLD_SCB_CLEAR__OFFSET 0x00000010u +#define CYFLD_SCB_CLEAR__SIZE 0x00000001u +#define CYFLD_SCB_FREEZE__OFFSET 0x00000011u +#define CYFLD_SCB_FREEZE__SIZE 0x00000001u +#define CYREG_SCB0_TX_FIFO_STATUS 0x40060208u +#define CYFLD_SCB_USED__OFFSET 0x00000000u +#define CYFLD_SCB_USED__SIZE 0x00000004u +#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000fu +#define CYFLD_SCB_SR_VALID__SIZE 0x00000001u +#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010u +#define CYFLD_SCB_RD_PTR__SIZE 0x00000003u +#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018u +#define CYFLD_SCB_WR_PTR__SIZE 0x00000003u +#define CYREG_SCB0_TX_FIFO_WR 0x40060240u +#define CYFLD_SCB_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_DATA__SIZE 0x00000010u +#define CYREG_SCB0_RX_CTRL 0x40060300u +#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009u +#define CYFLD_SCB_MEDIAN__SIZE 0x00000001u +#define CYREG_SCB0_RX_FIFO_CTRL 0x40060304u +#define CYREG_SCB0_RX_FIFO_STATUS 0x40060308u +#define CYREG_SCB0_RX_MATCH 0x40060310u +#define CYFLD_SCB_ADDR__OFFSET 0x00000000u +#define CYFLD_SCB_ADDR__SIZE 0x00000008u +#define CYFLD_SCB_MASK__OFFSET 0x00000010u +#define CYFLD_SCB_MASK__SIZE 0x00000008u +#define CYREG_SCB0_RX_FIFO_RD 0x40060340u +#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40060344u +#define CYREG_SCB0_EZ_DATA00 0x40060400u +#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008u +#define CYREG_SCB0_EZ_DATA01 0x40060404u +#define CYREG_SCB0_EZ_DATA02 0x40060408u +#define CYREG_SCB0_EZ_DATA03 0x4006040cu +#define CYREG_SCB0_EZ_DATA04 0x40060410u +#define CYREG_SCB0_EZ_DATA05 0x40060414u +#define CYREG_SCB0_EZ_DATA06 0x40060418u +#define CYREG_SCB0_EZ_DATA07 0x4006041cu +#define CYREG_SCB0_EZ_DATA08 0x40060420u +#define CYREG_SCB0_EZ_DATA09 0x40060424u +#define CYREG_SCB0_EZ_DATA10 0x40060428u +#define CYREG_SCB0_EZ_DATA11 0x4006042cu +#define CYREG_SCB0_EZ_DATA12 0x40060430u +#define CYREG_SCB0_EZ_DATA13 0x40060434u +#define CYREG_SCB0_EZ_DATA14 0x40060438u +#define CYREG_SCB0_EZ_DATA15 0x4006043cu +#define CYREG_SCB0_EZ_DATA16 0x40060440u +#define CYREG_SCB0_EZ_DATA17 0x40060444u +#define CYREG_SCB0_EZ_DATA18 0x40060448u +#define CYREG_SCB0_EZ_DATA19 0x4006044cu +#define CYREG_SCB0_EZ_DATA20 0x40060450u +#define CYREG_SCB0_EZ_DATA21 0x40060454u +#define CYREG_SCB0_EZ_DATA22 0x40060458u +#define CYREG_SCB0_EZ_DATA23 0x4006045cu +#define CYREG_SCB0_EZ_DATA24 0x40060460u +#define CYREG_SCB0_EZ_DATA25 0x40060464u +#define CYREG_SCB0_EZ_DATA26 0x40060468u +#define CYREG_SCB0_EZ_DATA27 0x4006046cu +#define CYREG_SCB0_EZ_DATA28 0x40060470u +#define CYREG_SCB0_EZ_DATA29 0x40060474u +#define CYREG_SCB0_EZ_DATA30 0x40060478u +#define CYREG_SCB0_EZ_DATA31 0x4006047cu +#define CYREG_SCB0_INTR_CAUSE 0x40060e00u +#define CYFLD_SCB_M__OFFSET 0x00000000u +#define CYFLD_SCB_M__SIZE 0x00000001u +#define CYFLD_SCB_S__OFFSET 0x00000001u +#define CYFLD_SCB_S__SIZE 0x00000001u +#define CYFLD_SCB_TX__OFFSET 0x00000002u +#define CYFLD_SCB_TX__SIZE 0x00000001u +#define CYFLD_SCB_RX__OFFSET 0x00000003u +#define CYFLD_SCB_RX__SIZE 0x00000001u +#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004u +#define CYFLD_SCB_I2C_EC__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005u +#define CYFLD_SCB_SPI_EC__SIZE 0x00000001u +#define CYREG_SCB0_INTR_I2C_EC 0x40060e80u +#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000u +#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001u +#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001u +#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001u +#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002u +#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001u +#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40060e88u +#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40060e8cu +#define CYREG_SCB0_INTR_SPI_EC 0x40060ec0u +#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40060ec8u +#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40060eccu +#define CYREG_SCB0_INTR_M 0x40060f00u +#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000u +#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001u +#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001u +#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001u +#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002u +#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001u +#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004u +#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001u +#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009u +#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001u +#define CYREG_SCB0_INTR_M_SET 0x40060f04u +#define CYREG_SCB0_INTR_M_MASK 0x40060f08u +#define CYREG_SCB0_INTR_M_MASKED 0x40060f0cu +#define CYREG_SCB0_INTR_S 0x40060f40u +#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003u +#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001u +#define CYFLD_SCB_I2C_START__OFFSET 0x00000005u +#define CYFLD_SCB_I2C_START__SIZE 0x00000001u +#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006u +#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001u +#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007u +#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009u +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000au +#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001u +#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000bu +#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001u +#define CYREG_SCB0_INTR_S_SET 0x40060f44u +#define CYREG_SCB0_INTR_S_MASK 0x40060f48u +#define CYREG_SCB0_INTR_S_MASKED 0x40060f4cu +#define CYREG_SCB0_INTR_TX 0x40060f80u +#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000u +#define CYFLD_SCB_TRIGGER__SIZE 0x00000001u +#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001u +#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001u +#define CYFLD_SCB_EMPTY__OFFSET 0x00000004u +#define CYFLD_SCB_EMPTY__SIZE 0x00000001u +#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005u +#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001u +#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006u +#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001u +#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007u +#define CYFLD_SCB_BLOCKED__SIZE 0x00000001u +#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008u +#define CYFLD_SCB_UART_NACK__SIZE 0x00000001u +#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009u +#define CYFLD_SCB_UART_DONE__SIZE 0x00000001u +#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000au +#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001u +#define CYREG_SCB0_INTR_TX_SET 0x40060f84u +#define CYREG_SCB0_INTR_TX_MASK 0x40060f88u +#define CYREG_SCB0_INTR_TX_MASKED 0x40060f8cu +#define CYREG_SCB0_INTR_RX 0x40060fc0u +#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002u +#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001u +#define CYFLD_SCB_FULL__OFFSET 0x00000003u +#define CYFLD_SCB_FULL__SIZE 0x00000001u +#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009u +#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000au +#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001u +#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000bu +#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001u +#define CYREG_SCB0_INTR_RX_SET 0x40060fc4u +#define CYREG_SCB0_INTR_RX_MASK 0x40060fc8u +#define CYREG_SCB0_INTR_RX_MASKED 0x40060fccu +#define CYDEV_SCB1_BASE 0x40070000u +#define CYDEV_SCB1_SIZE 0x00010000u +#define CYREG_SCB1_CTRL 0x40070000u +#define CYREG_SCB1_STATUS 0x40070004u +#define CYREG_SCB1_SPI_CTRL 0x40070020u +#define CYREG_SCB1_SPI_STATUS 0x40070024u +#define CYREG_SCB1_UART_CTRL 0x40070040u +#define CYREG_SCB1_UART_TX_CTRL 0x40070044u +#define CYREG_SCB1_UART_RX_CTRL 0x40070048u +#define CYREG_SCB1_UART_RX_STATUS 0x4007004cu +#define CYREG_SCB1_I2C_CTRL 0x40070060u +#define CYREG_SCB1_I2C_STATUS 0x40070064u +#define CYREG_SCB1_I2C_M_CMD 0x40070068u +#define CYREG_SCB1_I2C_S_CMD 0x4007006cu +#define CYREG_SCB1_I2C_CFG 0x40070070u +#define CYREG_SCB1_BIST_CONTROL 0x40070100u +#define CYREG_SCB1_BIST_DATA 0x40070104u +#define CYREG_SCB1_TX_CTRL 0x40070200u +#define CYREG_SCB1_TX_FIFO_CTRL 0x40070204u +#define CYREG_SCB1_TX_FIFO_STATUS 0x40070208u +#define CYREG_SCB1_TX_FIFO_WR 0x40070240u +#define CYREG_SCB1_RX_CTRL 0x40070300u +#define CYREG_SCB1_RX_FIFO_CTRL 0x40070304u +#define CYREG_SCB1_RX_FIFO_STATUS 0x40070308u +#define CYREG_SCB1_RX_MATCH 0x40070310u +#define CYREG_SCB1_RX_FIFO_RD 0x40070340u +#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40070344u +#define CYREG_SCB1_EZ_DATA00 0x40070400u +#define CYREG_SCB1_EZ_DATA01 0x40070404u +#define CYREG_SCB1_EZ_DATA02 0x40070408u +#define CYREG_SCB1_EZ_DATA03 0x4007040cu +#define CYREG_SCB1_EZ_DATA04 0x40070410u +#define CYREG_SCB1_EZ_DATA05 0x40070414u +#define CYREG_SCB1_EZ_DATA06 0x40070418u +#define CYREG_SCB1_EZ_DATA07 0x4007041cu +#define CYREG_SCB1_EZ_DATA08 0x40070420u +#define CYREG_SCB1_EZ_DATA09 0x40070424u +#define CYREG_SCB1_EZ_DATA10 0x40070428u +#define CYREG_SCB1_EZ_DATA11 0x4007042cu +#define CYREG_SCB1_EZ_DATA12 0x40070430u +#define CYREG_SCB1_EZ_DATA13 0x40070434u +#define CYREG_SCB1_EZ_DATA14 0x40070438u +#define CYREG_SCB1_EZ_DATA15 0x4007043cu +#define CYREG_SCB1_EZ_DATA16 0x40070440u +#define CYREG_SCB1_EZ_DATA17 0x40070444u +#define CYREG_SCB1_EZ_DATA18 0x40070448u +#define CYREG_SCB1_EZ_DATA19 0x4007044cu +#define CYREG_SCB1_EZ_DATA20 0x40070450u +#define CYREG_SCB1_EZ_DATA21 0x40070454u +#define CYREG_SCB1_EZ_DATA22 0x40070458u +#define CYREG_SCB1_EZ_DATA23 0x4007045cu +#define CYREG_SCB1_EZ_DATA24 0x40070460u +#define CYREG_SCB1_EZ_DATA25 0x40070464u +#define CYREG_SCB1_EZ_DATA26 0x40070468u +#define CYREG_SCB1_EZ_DATA27 0x4007046cu +#define CYREG_SCB1_EZ_DATA28 0x40070470u +#define CYREG_SCB1_EZ_DATA29 0x40070474u +#define CYREG_SCB1_EZ_DATA30 0x40070478u +#define CYREG_SCB1_EZ_DATA31 0x4007047cu +#define CYREG_SCB1_INTR_CAUSE 0x40070e00u +#define CYREG_SCB1_INTR_I2C_EC 0x40070e80u +#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40070e88u +#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40070e8cu +#define CYREG_SCB1_INTR_SPI_EC 0x40070ec0u +#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40070ec8u +#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40070eccu +#define CYREG_SCB1_INTR_M 0x40070f00u +#define CYREG_SCB1_INTR_M_SET 0x40070f04u +#define CYREG_SCB1_INTR_M_MASK 0x40070f08u +#define CYREG_SCB1_INTR_M_MASKED 0x40070f0cu +#define CYREG_SCB1_INTR_S 0x40070f40u +#define CYREG_SCB1_INTR_S_SET 0x40070f44u +#define CYREG_SCB1_INTR_S_MASK 0x40070f48u +#define CYREG_SCB1_INTR_S_MASKED 0x40070f4cu +#define CYREG_SCB1_INTR_TX 0x40070f80u +#define CYREG_SCB1_INTR_TX_SET 0x40070f84u +#define CYREG_SCB1_INTR_TX_MASK 0x40070f88u +#define CYREG_SCB1_INTR_TX_MASKED 0x40070f8cu +#define CYREG_SCB1_INTR_RX 0x40070fc0u +#define CYREG_SCB1_INTR_RX_SET 0x40070fc4u +#define CYREG_SCB1_INTR_RX_MASK 0x40070fc8u +#define CYREG_SCB1_INTR_RX_MASKED 0x40070fccu +#define CYDEV_CSD_BASE 0x40080000u +#define CYDEV_CSD_SIZE 0x00010000u +#define CYREG_CSD_ID 0x40080000u +#define CYFLD_CSD_ID__OFFSET 0x00000000u +#define CYFLD_CSD_ID__SIZE 0x00000010u +#define CYFLD_CSD_REVISION__OFFSET 0x00000010u +#define CYFLD_CSD_REVISION__SIZE 0x00000010u +#define CYREG_CSD_CONFIG 0x40080004u +#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000000u +#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001u +#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x00000001u +#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001u +#define CYFLD_CSD_PRS_CLEAR__OFFSET 0x00000005u +#define CYFLD_CSD_PRS_CLEAR__SIZE 0x00000001u +#define CYFLD_CSD_PRS_SELECT__OFFSET 0x00000006u +#define CYFLD_CSD_PRS_SELECT__SIZE 0x00000001u +#define CYVAL_CSD_PRS_SELECT_DIV2 0x00000000u +#define CYVAL_CSD_PRS_SELECT_PRS 0x00000001u +#define CYFLD_CSD_PRS_12_8__OFFSET 0x00000007u +#define CYFLD_CSD_PRS_12_8__SIZE 0x00000001u +#define CYVAL_CSD_PRS_12_8_8B 0x00000000u +#define CYVAL_CSD_PRS_12_8_12B 0x00000001u +#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x00000008u +#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001u +#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000009u +#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002u +#define CYFLD_CSD_SENSE_COMP_BW__OFFSET 0x0000000bu +#define CYFLD_CSD_SENSE_COMP_BW__SIZE 0x00000001u +#define CYVAL_CSD_SENSE_COMP_BW_LOW 0x00000000u +#define CYVAL_CSD_SENSE_COMP_BW_HIGH 0x00000001u +#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000cu +#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001u +#define CYFLD_CSD_REFBUF_EN__OFFSET 0x0000000du +#define CYFLD_CSD_REFBUF_EN__SIZE 0x00000001u +#define CYFLD_CSD_COMP_MODE__OFFSET 0x0000000eu +#define CYFLD_CSD_COMP_MODE__SIZE 0x00000001u +#define CYVAL_CSD_COMP_MODE_CHARGE_BUF 0x00000000u +#define CYVAL_CSD_COMP_MODE_CHARGE_IO 0x00000001u +#define CYFLD_CSD_COMP_PIN__OFFSET 0x0000000fu +#define CYFLD_CSD_COMP_PIN__SIZE 0x00000001u +#define CYVAL_CSD_COMP_PIN_CHANNEL1 0x00000000u +#define CYVAL_CSD_COMP_PIN_CHANNEL2 0x00000001u +#define CYFLD_CSD_POLARITY__OFFSET 0x00000010u +#define CYFLD_CSD_POLARITY__SIZE 0x00000001u +#define CYVAL_CSD_POLARITY_VSSIO 0x00000000u +#define CYVAL_CSD_POLARITY_VDDIO 0x00000001u +#define CYFLD_CSD_POLARITY2__OFFSET 0x00000011u +#define CYFLD_CSD_POLARITY2__SIZE 0x00000001u +#define CYVAL_CSD_POLARITY2_VSSIO 0x00000000u +#define CYVAL_CSD_POLARITY2_VDDIO 0x00000001u +#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012u +#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001u +#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000u +#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001u +#define CYFLD_CSD_SENSE_COMP_EN__OFFSET 0x00000013u +#define CYFLD_CSD_SENSE_COMP_EN__SIZE 0x00000001u +#define CYFLD_CSD_REBUF_OUTSEL__OFFSET 0x00000015u +#define CYFLD_CSD_REBUF_OUTSEL__SIZE 0x00000001u +#define CYVAL_CSD_REBUF_OUTSEL_AMUXA 0x00000000u +#define CYVAL_CSD_REBUF_OUTSEL_AMUXB 0x00000001u +#define CYFLD_CSD_SENSE_INSEL__OFFSET 0x00000016u +#define CYFLD_CSD_SENSE_INSEL__SIZE 0x00000001u +#define CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 0x00000000u +#define CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA 0x00000001u +#define CYFLD_CSD_REFBUF_DRV__OFFSET 0x00000017u +#define CYFLD_CSD_REFBUF_DRV__SIZE 0x00000002u +#define CYVAL_CSD_REFBUF_DRV_OFF 0x00000000u +#define CYVAL_CSD_REFBUF_DRV_DRV_1 0x00000001u +#define CYVAL_CSD_REFBUF_DRV_DRV_2 0x00000002u +#define CYVAL_CSD_REFBUF_DRV_DRV_3 0x00000003u +#define CYFLD_CSD_DDFTSEL__OFFSET 0x0000001au +#define CYFLD_CSD_DDFTSEL__SIZE 0x00000003u +#define CYVAL_CSD_DDFTSEL_NORMAL 0x00000000u +#define CYVAL_CSD_DDFTSEL_CSD_SENSE 0x00000001u +#define CYVAL_CSD_DDFTSEL_CSD_SHIELD 0x00000002u +#define CYVAL_CSD_DDFTSEL_CLK_SAMPLE 0x00000003u +#define CYVAL_CSD_DDFTSEL_COMP_OUT 0x00000004u +#define CYFLD_CSD_ADFTEN__OFFSET 0x0000001du +#define CYFLD_CSD_ADFTEN__SIZE 0x00000001u +#define CYFLD_CSD_DDFTCOMP__OFFSET 0x0000001eu +#define CYFLD_CSD_DDFTCOMP__SIZE 0x00000001u +#define CYVAL_CSD_DDFTCOMP_REFBUFCOMP 0x00000000u +#define CYVAL_CSD_DDFTCOMP_SENSECOMP 0x00000001u +#define CYFLD_CSD_ENABLE__OFFSET 0x0000001fu +#define CYFLD_CSD_ENABLE__SIZE 0x00000001u +#define CYREG_CSD_IDAC 0x40080008u +#define CYFLD_CSD_IDAC1__OFFSET 0x00000000u +#define CYFLD_CSD_IDAC1__SIZE 0x00000008u +#define CYFLD_CSD_IDAC1_MODE__OFFSET 0x00000008u +#define CYFLD_CSD_IDAC1_MODE__SIZE 0x00000002u +#define CYVAL_CSD_IDAC1_MODE_OFF 0x00000000u +#define CYVAL_CSD_IDAC1_MODE_FIXED 0x00000001u +#define CYVAL_CSD_IDAC1_MODE_VARIABLE 0x00000002u +#define CYVAL_CSD_IDAC1_MODE_DSI 0x00000003u +#define CYFLD_CSD_IDAC1_RANGE__OFFSET 0x0000000au +#define CYFLD_CSD_IDAC1_RANGE__SIZE 0x00000001u +#define CYVAL_CSD_IDAC1_RANGE_4X 0x00000000u +#define CYVAL_CSD_IDAC1_RANGE_8X 0x00000001u +#define CYFLD_CSD_IDAC2__OFFSET 0x00000010u +#define CYFLD_CSD_IDAC2__SIZE 0x00000007u +#define CYFLD_CSD_IDAC2_MODE__OFFSET 0x00000018u +#define CYFLD_CSD_IDAC2_MODE__SIZE 0x00000002u +#define CYVAL_CSD_IDAC2_MODE_OFF 0x00000000u +#define CYVAL_CSD_IDAC2_MODE_FIXED 0x00000001u +#define CYVAL_CSD_IDAC2_MODE_VARIABLE 0x00000002u +#define CYVAL_CSD_IDAC2_MODE_DSI 0x00000003u +#define CYFLD_CSD_IDAC2_RANGE__OFFSET 0x0000001au +#define CYFLD_CSD_IDAC2_RANGE__SIZE 0x00000001u +#define CYVAL_CSD_IDAC2_RANGE_4X 0x00000000u +#define CYVAL_CSD_IDAC2_RANGE_8X 0x00000001u +#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001eu +#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001u +#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000u +#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001u +#define CYREG_CSD_COUNTER 0x4008000cu +#define CYFLD_CSD_COUNTER__OFFSET 0x00000000u +#define CYFLD_CSD_COUNTER__SIZE 0x00000010u +#define CYFLD_CSD_PERIOD__OFFSET 0x00000010u +#define CYFLD_CSD_PERIOD__SIZE 0x00000010u +#define CYREG_CSD_STATUS 0x40080010u +#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000u +#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001u +#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001u +#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001u +#define CYFLD_CSD_COMP_OUT__OFFSET 0x00000002u +#define CYFLD_CSD_COMP_OUT__SIZE 0x00000001u +#define CYVAL_CSD_COMP_OUT_C_LT_VREF 0x00000000u +#define CYVAL_CSD_COMP_OUT_C_GT_VREF 0x00000001u +#define CYFLD_CSD_SAMPLE__OFFSET 0x00000003u +#define CYFLD_CSD_SAMPLE__SIZE 0x00000001u +#define CYREG_CSD_INTR 0x40080014u +#define CYFLD_CSD_CSD__OFFSET 0x00000000u +#define CYFLD_CSD_CSD__SIZE 0x00000001u +#define CYREG_CSD_INTR_SET 0x40080018u +#define CYREG_CSD_TRIM1 0x4008ff00u +#define CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET 0x00000000u +#define CYFLD_CSD_IDAC1_SRC_TRIM__SIZE 0x00000004u +#define CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET 0x00000004u +#define CYFLD_CSD_IDAC2_SRC_TRIM__SIZE 0x00000004u +#define CYREG_CSD_TRIM2 0x4008ff04u +#define CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET 0x00000000u +#define CYFLD_CSD_IDAC1_SNK_TRIM__SIZE 0x00000004u +#define CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET 0x00000004u +#define CYFLD_CSD_IDAC2_SNK_TRIM__SIZE 0x00000004u +#define CYDEV_LCD_BASE 0x40090000u +#define CYDEV_LCD_SIZE 0x00010000u +#define CYREG_LCD_ID 0x40090000u +#define CYFLD_LCD_ID__OFFSET 0x00000000u +#define CYFLD_LCD_ID__SIZE 0x00000010u +#define CYFLD_LCD_REVISION__OFFSET 0x00000010u +#define CYFLD_LCD_REVISION__SIZE 0x00000010u +#define CYREG_LCD_DIVIDER 0x40090004u +#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000u +#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010u +#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010u +#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010u +#define CYREG_LCD_CONTROL 0x40090008u +#define CYFLD_LCD_LS_EN__OFFSET 0x00000000u +#define CYFLD_LCD_LS_EN__SIZE 0x00000001u +#define CYFLD_LCD_HS_EN__OFFSET 0x00000001u +#define CYFLD_LCD_HS_EN__SIZE 0x00000001u +#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002u +#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001u +#define CYVAL_LCD_LCD_MODE_LS 0x00000000u +#define CYVAL_LCD_LCD_MODE_HS 0x00000001u +#define CYFLD_LCD_TYPE__OFFSET 0x00000003u +#define CYFLD_LCD_TYPE__SIZE 0x00000001u +#define CYVAL_LCD_TYPE_A 0x00000000u +#define CYVAL_LCD_TYPE_B 0x00000001u +#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004u +#define CYFLD_LCD_OP_MODE__SIZE 0x00000001u +#define CYVAL_LCD_OP_MODE_PWM 0x00000000u +#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001u +#define CYFLD_LCD_BIAS__OFFSET 0x00000005u +#define CYFLD_LCD_BIAS__SIZE 0x00000002u +#define CYVAL_LCD_BIAS_HALF 0x00000000u +#define CYVAL_LCD_BIAS_THIRD 0x00000001u +#define CYVAL_LCD_BIAS_FOURTH 0x00000002u +#define CYVAL_LCD_BIAS_FIFTH 0x00000003u +#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008u +#define CYFLD_LCD_COM_NUM__SIZE 0x00000004u +#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001fu +#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001u +#define CYREG_LCD_DATA00 0x40090100u +#define CYFLD_LCD_DATA__OFFSET 0x00000000u +#define CYFLD_LCD_DATA__SIZE 0x00000020u +#define CYREG_LCD_DATA01 0x40090104u +#define CYREG_LCD_DATA02 0x40090108u +#define CYREG_LCD_DATA03 0x4009010cu +#define CYREG_LCD_DATA04 0x40090110u +#define CYDEV_LPCOMP_BASE 0x400a0000u +#define CYDEV_LPCOMP_SIZE 0x00010000u +#define CYREG_LPCOMP_ID 0x400a0000u +#define CYFLD_LPCOMP_ID__OFFSET 0x00000000u +#define CYFLD_LPCOMP_ID__SIZE 0x00000010u +#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010u +#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010u +#define CYREG_LPCOMP_CONFIG 0x400a0004u +#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000u +#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002u +#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000u +#define CYVAL_LPCOMP_MODE1_FAST 0x00000001u +#define CYVAL_LPCOMP_MODE1_ULP 0x00000002u +#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002u +#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001u +#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003u +#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001u +#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004u +#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002u +#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000u +#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001u +#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002u +#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003u +#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006u +#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001u +#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007u +#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001u +#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008u +#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002u +#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000u +#define CYVAL_LPCOMP_MODE2_FAST 0x00000001u +#define CYVAL_LPCOMP_MODE2_ULP 0x00000002u +#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000au +#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001u +#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000bu +#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001u +#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000cu +#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002u +#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000u +#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001u +#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002u +#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003u +#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000eu +#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001u +#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000fu +#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001u +#define CYREG_LPCOMP_DFT 0x400a0008u +#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000u +#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001u +#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001u +#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001u +#define CYREG_LPCOMP_INTR 0x400a000cu +#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001u +#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001u +#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001u +#define CYREG_LPCOMP_INTR_SET 0x400a0010u +#define CYREG_LPCOMP_TRIM1 0x400aff00u +#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM2 0x400aff04u +#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM3 0x400aff08u +#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM4 0x400aff0cu +#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005u +#define CYREG_PWR_CONTROL 0x400b0000u +#define CYFLD__POWER_MODE__OFFSET 0x00000000u +#define CYFLD__POWER_MODE__SIZE 0x00000004u +#define CYVAL__POWER_MODE_RESET 0x00000000u +#define CYVAL__POWER_MODE_ACTIVE 0x00000001u +#define CYVAL__POWER_MODE_SLEEP 0x00000002u +#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003u +#define CYVAL__POWER_MODE_HIBERNATE 0x00000004u +#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004u +#define CYFLD__DEBUG_SESSION__SIZE 0x00000001u +#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000u +#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001u +#define CYFLD__LPM_READY__OFFSET 0x00000005u +#define CYFLD__LPM_READY__SIZE 0x00000001u +#define CYFLD__EXT_VCCD__OFFSET 0x00000017u +#define CYFLD__EXT_VCCD__SIZE 0x00000001u +#define CYFLD__HVMON_ENABLE__OFFSET 0x00000018u +#define CYFLD__HVMON_ENABLE__SIZE 0x00000001u +#define CYFLD__HVMON_RELOAD__OFFSET 0x00000019u +#define CYFLD__HVMON_RELOAD__SIZE 0x00000001u +#define CYFLD__FIMO_DISABLE__OFFSET 0x0000001bu +#define CYFLD__FIMO_DISABLE__SIZE 0x00000001u +#define CYFLD__HIBERNATE_DISABLE__OFFSET 0x0000001cu +#define CYFLD__HIBERNATE_DISABLE__SIZE 0x00000001u +#define CYFLD__LFCLK_SHORT__OFFSET 0x0000001du +#define CYFLD__LFCLK_SHORT__SIZE 0x00000001u +#define CYFLD__HIBERNATE__OFFSET 0x0000001fu +#define CYFLD__HIBERNATE__SIZE 0x00000001u +#define CYVAL__HIBERNATE_DEEP_SLEEP 0x00000000u +#define CYVAL__HIBERNATE_HIBERNATE 0x00000001u +#define CYREG_PWR_INTR 0x400b0004u +#define CYFLD__LVD__OFFSET 0x00000001u +#define CYFLD__LVD__SIZE 0x00000001u +#define CYREG_PWR_INTR_MASK 0x400b0008u +#define CYREG_PWR_KEY_DELAY 0x400b000cu +#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000u +#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000au +#define CYREG_PWR_PWRSYS_CONFIG 0x400b0010u +#define CYFLD__HIB_TEST_EN__OFFSET 0x00000008u +#define CYFLD__HIB_TEST_EN__SIZE 0x00000001u +#define CYFLD__HIB_TEST_REP__OFFSET 0x00000009u +#define CYFLD__HIB_TEST_REP__SIZE 0x00000001u +#define CYREG_PWR_BG_CONFIG 0x400b0014u +#define CYFLD__BG_DFT_EN__OFFSET 0x00000000u +#define CYFLD__BG_DFT_EN__SIZE 0x00000001u +#define CYFLD__BG_DFT_VREF_SEL__OFFSET 0x00000001u +#define CYFLD__BG_DFT_VREF_SEL__SIZE 0x00000004u +#define CYFLD__BG_DFT_CORE_SEL__OFFSET 0x00000005u +#define CYFLD__BG_DFT_CORE_SEL__SIZE 0x00000001u +#define CYFLD__BG_DFT_ICORE_SEL__OFFSET 0x00000006u +#define CYFLD__BG_DFT_ICORE_SEL__SIZE 0x00000002u +#define CYFLD__BG_DFT_VCORE_SEL__OFFSET 0x00000008u +#define CYFLD__BG_DFT_VCORE_SEL__SIZE 0x00000001u +#define CYFLD__VREF_EN__OFFSET 0x00000010u +#define CYFLD__VREF_EN__SIZE 0x00000003u +#define CYREG_PWR_VMON_CONFIG 0x400b0018u +#define CYFLD__LVD_EN__OFFSET 0x00000000u +#define CYFLD__LVD_EN__SIZE 0x00000001u +#define CYFLD__LVD_SEL__OFFSET 0x00000001u +#define CYFLD__LVD_SEL__SIZE 0x00000004u +#define CYFLD__VMON_DDFT_SEL__OFFSET 0x00000005u +#define CYFLD__VMON_DDFT_SEL__SIZE 0x00000003u +#define CYFLD__VMON_ADFT_SEL__OFFSET 0x00000008u +#define CYFLD__VMON_ADFT_SEL__SIZE 0x00000002u +#define CYREG_PWR_DFT_SELECT 0x400b001cu +#define CYFLD__TVMON1_SEL__OFFSET 0x00000000u +#define CYFLD__TVMON1_SEL__SIZE 0x00000003u +#define CYFLD__TVMON2_SEL__OFFSET 0x00000003u +#define CYFLD__TVMON2_SEL__SIZE 0x00000003u +#define CYFLD__BYPASS__OFFSET 0x00000006u +#define CYFLD__BYPASS__SIZE 0x00000001u +#define CYFLD__ACTIVE_EN__OFFSET 0x00000007u +#define CYFLD__ACTIVE_EN__SIZE 0x00000001u +#define CYFLD__ACTIVE_INRUSH_DIS__OFFSET 0x00000008u +#define CYFLD__ACTIVE_INRUSH_DIS__SIZE 0x00000001u +#define CYFLD__LPCOMP_DIS__OFFSET 0x00000009u +#define CYFLD__LPCOMP_DIS__SIZE 0x00000001u +#define CYFLD__BLEED_EN__OFFSET 0x0000000au +#define CYFLD__BLEED_EN__SIZE 0x00000001u +#define CYFLD__IPOR_EN__OFFSET 0x0000000bu +#define CYFLD__IPOR_EN__SIZE 0x00000001u +#define CYFLD__POWER_UP_RAW_BYP__OFFSET 0x0000000cu +#define CYFLD__POWER_UP_RAW_BYP__SIZE 0x00000001u +#define CYFLD__POWER_UP_RAW_CTL__OFFSET 0x0000000du +#define CYFLD__POWER_UP_RAW_CTL__SIZE 0x00000001u +#define CYFLD__DEEPSLEEP_EN__OFFSET 0x0000000eu +#define CYFLD__DEEPSLEEP_EN__SIZE 0x00000001u +#define CYFLD__RSVD_BYPASS__OFFSET 0x0000000fu +#define CYFLD__RSVD_BYPASS__SIZE 0x00000001u +#define CYFLD__NWELL_OPEN__OFFSET 0x00000010u +#define CYFLD__NWELL_OPEN__SIZE 0x00000001u +#define CYFLD__HIBERNATE_OPEN__OFFSET 0x00000011u +#define CYFLD__HIBERNATE_OPEN__SIZE 0x00000001u +#define CYFLD__DEEPSLEEP_OPEN__OFFSET 0x00000012u +#define CYFLD__DEEPSLEEP_OPEN__SIZE 0x00000001u +#define CYFLD__QUIET_OPEN__OFFSET 0x00000013u +#define CYFLD__QUIET_OPEN__SIZE 0x00000001u +#define CYFLD__LFCLK_OPEN__OFFSET 0x00000014u +#define CYFLD__LFCLK_OPEN__SIZE 0x00000001u +#define CYFLD__QUIET_EN__OFFSET 0x00000016u +#define CYFLD__QUIET_EN__SIZE 0x00000001u +#define CYFLD__BREF_EN__OFFSET 0x00000017u +#define CYFLD__BREF_EN__SIZE 0x00000001u +#define CYFLD__BREF_OUTEN__OFFSET 0x00000018u +#define CYFLD__BREF_OUTEN__SIZE 0x00000001u +#define CYFLD__BREF_REFSW__OFFSET 0x00000019u +#define CYFLD__BREF_REFSW__SIZE 0x00000001u +#define CYFLD__BREF_TESTMODE__OFFSET 0x0000001au +#define CYFLD__BREF_TESTMODE__SIZE 0x00000001u +#define CYFLD__NWELL_DIS__OFFSET 0x0000001bu +#define CYFLD__NWELL_DIS__SIZE 0x00000001u +#define CYFLD__HVMON_DFT_OVR__OFFSET 0x0000001cu +#define CYFLD__HVMON_DFT_OVR__SIZE 0x00000001u +#define CYFLD__IMO_REFGEN_DIS__OFFSET 0x0000001du +#define CYFLD__IMO_REFGEN_DIS__SIZE 0x00000001u +#define CYFLD__POWER_UP_ACTIVE__OFFSET 0x0000001eu +#define CYFLD__POWER_UP_ACTIVE__SIZE 0x00000001u +#define CYFLD__POWER_UP_HIBDPSLP__OFFSET 0x0000001fu +#define CYFLD__POWER_UP_HIBDPSLP__SIZE 0x00000001u +#define CYREG_PWR_DDFT_SELECT 0x400b0020u +#define CYFLD__DDFT1_SEL__OFFSET 0x00000000u +#define CYFLD__DDFT1_SEL__SIZE 0x00000004u +#define CYFLD__DDFT2_SEL__OFFSET 0x00000004u +#define CYFLD__DDFT2_SEL__SIZE 0x00000004u +#define CYREG_PWR_DFT_KEY 0x400b0024u +#define CYFLD__KEY16__OFFSET 0x00000000u +#define CYFLD__KEY16__SIZE 0x00000010u +#define CYFLD__HBOD_OFF_AWAKE__OFFSET 0x00000010u +#define CYFLD__HBOD_OFF_AWAKE__SIZE 0x00000001u +#define CYFLD__BODS_OFF__OFFSET 0x00000011u +#define CYFLD__BODS_OFF__SIZE 0x00000001u +#define CYFLD__DFT_MODE__OFFSET 0x00000012u +#define CYFLD__DFT_MODE__SIZE 0x00000001u +#define CYFLD__IO_DISABLE_BYPASS__OFFSET 0x00000013u +#define CYFLD__IO_DISABLE_BYPASS__SIZE 0x00000001u +#define CYFLD__VMON_PD__OFFSET 0x00000014u +#define CYFLD__VMON_PD__SIZE 0x00000001u +#define CYREG_PWR_BOD_KEY 0x400b0028u +#define CYREG_PWR_STOP 0x400b002cu +#define CYFLD__TOKEN__OFFSET 0x00000000u +#define CYFLD__TOKEN__SIZE 0x00000008u +#define CYFLD__UNLOCK__OFFSET 0x00000008u +#define CYFLD__UNLOCK__SIZE 0x00000008u +#define CYFLD__POLARITY__OFFSET 0x00000010u +#define CYFLD__POLARITY__SIZE 0x00000001u +#define CYFLD__FREEZE__OFFSET 0x00000011u +#define CYFLD__FREEZE__SIZE 0x00000001u +#define CYFLD__STOP__OFFSET 0x0000001fu +#define CYFLD__STOP__SIZE 0x00000001u +#define CYREG_CLK_SELECT 0x400b0100u +#define CYFLD__DIRECT_SEL__OFFSET 0x00000000u +#define CYFLD__DIRECT_SEL__SIZE 0x00000003u +#define CYVAL__DIRECT_SEL_IMO 0x00000000u +#define CYVAL__DIRECT_SEL_EXTCLK 0x00000001u +#define CYVAL__DIRECT_SEL_ECO 0x00000002u +#define CYVAL__DIRECT_SEL_DSI0 0x00000004u +#define CYVAL__DIRECT_SEL_DSI1 0x00000005u +#define CYVAL__DIRECT_SEL_DSI2 0x00000006u +#define CYVAL__DIRECT_SEL_DSI3 0x00000007u +#define CYFLD__DBL_SEL__OFFSET 0x00000003u +#define CYFLD__DBL_SEL__SIZE 0x00000003u +#define CYVAL__DBL_SEL_IMO 0x00000000u +#define CYVAL__DBL_SEL_EXTCLK 0x00000001u +#define CYVAL__DBL_SEL_ECO 0x00000002u +#define CYVAL__DBL_SEL_DSI0 0x00000004u +#define CYVAL__DBL_SEL_DSI1 0x00000005u +#define CYVAL__DBL_SEL_DSI2 0x00000006u +#define CYVAL__DBL_SEL_DSI3 0x00000007u +#define CYFLD__PLL_SEL__OFFSET 0x00000006u +#define CYFLD__PLL_SEL__SIZE 0x00000003u +#define CYVAL__PLL_SEL_IMO 0x00000000u +#define CYVAL__PLL_SEL_EXTCLK 0x00000001u +#define CYVAL__PLL_SEL_ECO 0x00000002u +#define CYVAL__PLL_SEL_DPLL 0x00000003u +#define CYVAL__PLL_SEL_DSI0 0x00000004u +#define CYVAL__PLL_SEL_DSI1 0x00000005u +#define CYVAL__PLL_SEL_DSI2 0x00000006u +#define CYVAL__PLL_SEL_DSI3 0x00000007u +#define CYFLD__DPLLIN_SEL__OFFSET 0x00000009u +#define CYFLD__DPLLIN_SEL__SIZE 0x00000003u +#define CYVAL__DPLLIN_SEL_IMO 0x00000000u +#define CYVAL__DPLLIN_SEL_EXTCLK 0x00000001u +#define CYVAL__DPLLIN_SEL_ECO 0x00000002u +#define CYVAL__DPLLIN_SEL_DSI0 0x00000004u +#define CYVAL__DPLLIN_SEL_DSI1 0x00000005u +#define CYVAL__DPLLIN_SEL_DSI2 0x00000006u +#define CYVAL__DPLLIN_SEL_DSI3 0x00000007u +#define CYFLD__DPLLREF_SEL__OFFSET 0x0000000cu +#define CYFLD__DPLLREF_SEL__SIZE 0x00000002u +#define CYVAL__DPLLREF_SEL_DSI0 0x00000000u +#define CYVAL__DPLLREF_SEL_DSI1 0x00000001u +#define CYVAL__DPLLREF_SEL_DSI2 0x00000002u +#define CYVAL__DPLLREF_SEL_DSI3 0x00000003u +#define CYFLD__WDT_LOCK__OFFSET 0x0000000eu +#define CYFLD__WDT_LOCK__SIZE 0x00000002u +#define CYVAL__WDT_LOCK_NO_CHG 0x00000000u +#define CYVAL__WDT_LOCK_CLR0 0x00000001u +#define CYVAL__WDT_LOCK_CLR1 0x00000002u +#define CYVAL__WDT_LOCK_SET01 0x00000003u +#define CYFLD__HFCLK_SEL__OFFSET 0x00000010u +#define CYFLD__HFCLK_SEL__SIZE 0x00000002u +#define CYVAL__HFCLK_SEL_DIRECT_SEL 0x00000000u +#define CYVAL__HFCLK_SEL_DBL 0x00000001u +#define CYVAL__HFCLK_SEL_PLL 0x00000002u +#define CYFLD__HALF_EN__OFFSET 0x00000012u +#define CYFLD__HALF_EN__SIZE 0x00000001u +#define CYFLD__SYSCLK_DIV__OFFSET 0x00000013u +#define CYFLD__SYSCLK_DIV__SIZE 0x00000003u +#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000u +#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001u +#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002u +#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003u +#define CYVAL__SYSCLK_DIV_DIV_BY_16 0x00000004u +#define CYVAL__SYSCLK_DIV_DIV_BY_32 0x00000005u +#define CYVAL__SYSCLK_DIV_DIV_BY_64 0x00000006u +#define CYVAL__SYSCLK_DIV_DIV_BY_128 0x00000007u +#define CYREG_CLK_ILO_CONFIG 0x400b0104u +#define CYFLD__PD_MODE__OFFSET 0x00000000u +#define CYFLD__PD_MODE__SIZE 0x00000001u +#define CYVAL__PD_MODE_SLEEP 0x00000000u +#define CYVAL__PD_MODE_COMA 0x00000001u +#define CYFLD__TURBO__OFFSET 0x00000001u +#define CYFLD__TURBO__SIZE 0x00000001u +#define CYFLD__SATBIAS__OFFSET 0x00000002u +#define CYFLD__SATBIAS__SIZE 0x00000001u +#define CYVAL__SATBIAS_SATURATED 0x00000000u +#define CYVAL__SATBIAS_SUBTHRESHOLD 0x00000001u +#define CYFLD__ENABLE__OFFSET 0x0000001fu +#define CYFLD__ENABLE__SIZE 0x00000001u +#define CYREG_CLK_IMO_CONFIG 0x400b0108u +#define CYFLD__FLASHPUMP_SEL__OFFSET 0x00000016u +#define CYFLD__FLASHPUMP_SEL__SIZE 0x00000001u +#define CYVAL__FLASHPUMP_SEL_GND 0x00000000u +#define CYVAL__FLASHPUMP_SEL_CLK36 0x00000001u +#define CYFLD__EN_FASTBIAS__OFFSET 0x00000017u +#define CYFLD__EN_FASTBIAS__SIZE 0x00000001u +#define CYFLD__TEST_FASTBIAS__OFFSET 0x00000018u +#define CYFLD__TEST_FASTBIAS__SIZE 0x00000001u +#define CYFLD__PUMP_SEL__OFFSET 0x00000019u +#define CYFLD__PUMP_SEL__SIZE 0x00000003u +#define CYVAL__PUMP_SEL_GND 0x00000000u +#define CYVAL__PUMP_SEL_IMO 0x00000001u +#define CYVAL__PUMP_SEL_DBL 0x00000002u +#define CYVAL__PUMP_SEL_CLK36 0x00000003u +#define CYVAL__PUMP_SEL_FF1 0x00000004u +#define CYFLD__TEST_USB_MODE__OFFSET 0x0000001cu +#define CYFLD__TEST_USB_MODE__SIZE 0x00000001u +#define CYFLD__EN_CLK36__OFFSET 0x0000001du +#define CYFLD__EN_CLK36__SIZE 0x00000001u +#define CYFLD__EN_CLK2X__OFFSET 0x0000001eu +#define CYFLD__EN_CLK2X__SIZE 0x00000001u +#define CYREG_CLK_IMO_SPREAD 0x400b010cu +#define CYFLD__SS_VALUE__OFFSET 0x00000000u +#define CYFLD__SS_VALUE__SIZE 0x00000005u +#define CYFLD__SS_MAX__OFFSET 0x00000008u +#define CYFLD__SS_MAX__SIZE 0x00000005u +#define CYFLD__SS_RANGE__OFFSET 0x0000001cu +#define CYFLD__SS_RANGE__SIZE 0x00000002u +#define CYVAL__SS_RANGE_M1 0x00000000u +#define CYVAL__SS_RANGE_M2 0x00000001u +#define CYVAL__SS_RANGE_M4 0x00000002u +#define CYFLD__SS_MODE__OFFSET 0x0000001eu +#define CYFLD__SS_MODE__SIZE 0x00000002u +#define CYVAL__SS_MODE_OFF 0x00000000u +#define CYVAL__SS_MODE_TRIANGLE 0x00000001u +#define CYVAL__SS_MODE_LFSR 0x00000002u +#define CYVAL__SS_MODE_DSI 0x00000003u +#define CYREG_CLK_DFT_SELECT 0x400b0110u +#define CYFLD__DFT_SEL1__OFFSET 0x00000000u +#define CYFLD__DFT_SEL1__SIZE 0x00000004u +#define CYVAL__DFT_SEL1_NC 0x00000000u +#define CYVAL__DFT_SEL1_ILO 0x00000001u +#define CYVAL__DFT_SEL1_WCO 0x00000002u +#define CYVAL__DFT_SEL1_IMO 0x00000003u +#define CYVAL__DFT_SEL1_ECO 0x00000004u +#define CYVAL__DFT_SEL1_PLL 0x00000005u +#define CYVAL__DFT_SEL1_DPLL_OUT 0x00000006u +#define CYVAL__DFT_SEL1_DPLL_REF 0x00000007u +#define CYVAL__DFT_SEL1_DBL 0x00000008u +#define CYVAL__DFT_SEL1_IMO2X 0x00000009u +#define CYVAL__DFT_SEL1_IMO36 0x0000000au +#define CYVAL__DFT_SEL1_HFCLK 0x0000000bu +#define CYVAL__DFT_SEL1_LFCLK 0x0000000cu +#define CYVAL__DFT_SEL1_SYSCLK 0x0000000du +#define CYVAL__DFT_SEL1_EXTCLK 0x0000000eu +#define CYVAL__DFT_SEL1_HALFSYSCLK 0x0000000fu +#define CYFLD__DFT_DIV1__OFFSET 0x00000004u +#define CYFLD__DFT_DIV1__SIZE 0x00000002u +#define CYVAL__DFT_DIV1_NO_DIV 0x00000000u +#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001u +#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002u +#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003u +#define CYFLD__DFT_SEL2__OFFSET 0x00000008u +#define CYFLD__DFT_SEL2__SIZE 0x00000004u +#define CYVAL__DFT_SEL2_NC 0x00000000u +#define CYVAL__DFT_SEL2_ILO 0x00000001u +#define CYVAL__DFT_SEL2_WCO 0x00000002u +#define CYVAL__DFT_SEL2_IMO 0x00000003u +#define CYVAL__DFT_SEL2_ECO 0x00000004u +#define CYVAL__DFT_SEL2_PLL 0x00000005u +#define CYVAL__DFT_SEL2_DPLL_OUT 0x00000006u +#define CYVAL__DFT_SEL2_DPLL_REF 0x00000007u +#define CYVAL__DFT_SEL2_DBL 0x00000008u +#define CYVAL__DFT_SEL2_IMO2X 0x00000009u +#define CYVAL__DFT_SEL2_IMO36 0x0000000au +#define CYVAL__DFT_SEL2_HFCLK 0x0000000bu +#define CYVAL__DFT_SEL2_LFCLK 0x0000000cu +#define CYVAL__DFT_SEL2_SYSCLK 0x0000000du +#define CYVAL__DFT_SEL2_EXTCLK 0x0000000eu +#define CYVAL__DFT_SEL2_HALFSYSCLK 0x0000000fu +#define CYFLD__DFT_DIV2__OFFSET 0x0000000cu +#define CYFLD__DFT_DIV2__SIZE 0x00000002u +#define CYVAL__DFT_DIV2_NO_DIV 0x00000000u +#define CYVAL__DFT_DIV2_DIV_BY_2 0x00000001u +#define CYVAL__DFT_DIV2_DIV_BY_4 0x00000002u +#define CYVAL__DFT_DIV2_DIV_BY_8 0x00000003u +#define CYREG_WDT_CTRLOW 0x400b0200u +#define CYFLD__WDT_CTR0__OFFSET 0x00000000u +#define CYFLD__WDT_CTR0__SIZE 0x00000010u +#define CYFLD__WDT_CTR1__OFFSET 0x00000010u +#define CYFLD__WDT_CTR1__SIZE 0x00000010u +#define CYREG_WDT_CTRHIGH 0x400b0204u +#define CYFLD__WDT_CTR2__OFFSET 0x00000000u +#define CYFLD__WDT_CTR2__SIZE 0x00000020u +#define CYREG_WDT_MATCH 0x400b0208u +#define CYFLD__WDT_MATCH0__OFFSET 0x00000000u +#define CYFLD__WDT_MATCH0__SIZE 0x00000010u +#define CYFLD__WDT_MATCH1__OFFSET 0x00000010u +#define CYFLD__WDT_MATCH1__SIZE 0x00000010u +#define CYREG_WDT_CONFIG 0x400b020cu +#define CYFLD__WDT_MODE0__OFFSET 0x00000000u +#define CYFLD__WDT_MODE0__SIZE 0x00000002u +#define CYVAL__WDT_MODE0_NOTHING 0x00000000u +#define CYVAL__WDT_MODE0_INT 0x00000001u +#define CYVAL__WDT_MODE0_RESET 0x00000002u +#define CYVAL__WDT_MODE0_INT_THEN_RESET 0x00000003u +#define CYFLD__WDT_CLEAR0__OFFSET 0x00000002u +#define CYFLD__WDT_CLEAR0__SIZE 0x00000001u +#define CYFLD__WDT_CASCADE0_1__OFFSET 0x00000003u +#define CYFLD__WDT_CASCADE0_1__SIZE 0x00000001u +#define CYFLD__WDT_MODE1__OFFSET 0x00000008u +#define CYFLD__WDT_MODE1__SIZE 0x00000002u +#define CYVAL__WDT_MODE1_NOTHING 0x00000000u +#define CYVAL__WDT_MODE1_INT 0x00000001u +#define CYVAL__WDT_MODE1_RESET 0x00000002u +#define CYVAL__WDT_MODE1_INT_THEN_RESET 0x00000003u +#define CYFLD__WDT_CLEAR1__OFFSET 0x0000000au +#define CYFLD__WDT_CLEAR1__SIZE 0x00000001u +#define CYFLD__WDT_CASCADE1_2__OFFSET 0x0000000bu +#define CYFLD__WDT_CASCADE1_2__SIZE 0x00000001u +#define CYFLD__WDT_MODE2__OFFSET 0x00000010u +#define CYFLD__WDT_MODE2__SIZE 0x00000001u +#define CYVAL__WDT_MODE2_NOTHING 0x00000000u +#define CYVAL__WDT_MODE2_INT 0x00000001u +#define CYFLD__WDT_BITS2__OFFSET 0x00000018u +#define CYFLD__WDT_BITS2__SIZE 0x00000005u +#define CYFLD__LFCLK_SEL__OFFSET 0x0000001eu +#define CYFLD__LFCLK_SEL__SIZE 0x00000002u +#define CYREG_WDT_CONTROL 0x400b0210u +#define CYFLD__WDT_ENABLE0__OFFSET 0x00000000u +#define CYFLD__WDT_ENABLE0__SIZE 0x00000001u +#define CYFLD__WDT_ENABLED0__OFFSET 0x00000001u +#define CYFLD__WDT_ENABLED0__SIZE 0x00000001u +#define CYFLD__WDT_INT0__OFFSET 0x00000002u +#define CYFLD__WDT_INT0__SIZE 0x00000001u +#define CYFLD__WDT_RESET0__OFFSET 0x00000003u +#define CYFLD__WDT_RESET0__SIZE 0x00000001u +#define CYFLD__WDT_ENABLE1__OFFSET 0x00000008u +#define CYFLD__WDT_ENABLE1__SIZE 0x00000001u +#define CYFLD__WDT_ENABLED1__OFFSET 0x00000009u +#define CYFLD__WDT_ENABLED1__SIZE 0x00000001u +#define CYFLD__WDT_INT1__OFFSET 0x0000000au +#define CYFLD__WDT_INT1__SIZE 0x00000001u +#define CYFLD__WDT_RESET1__OFFSET 0x0000000bu +#define CYFLD__WDT_RESET1__SIZE 0x00000001u +#define CYFLD__WDT_ENABLE2__OFFSET 0x00000010u +#define CYFLD__WDT_ENABLE2__SIZE 0x00000001u +#define CYFLD__WDT_ENABLED2__OFFSET 0x00000011u +#define CYFLD__WDT_ENABLED2__SIZE 0x00000001u +#define CYFLD__WDT_INT2__OFFSET 0x00000012u +#define CYFLD__WDT_INT2__SIZE 0x00000001u +#define CYFLD__WDT_RESET2__OFFSET 0x00000013u +#define CYFLD__WDT_RESET2__SIZE 0x00000001u +#define CYREG_RES_CAUSE 0x400b0300u +#define CYFLD__RESET_WDT__OFFSET 0x00000000u +#define CYFLD__RESET_WDT__SIZE 0x00000001u +#define CYFLD__RESET_DSBOD__OFFSET 0x00000001u +#define CYFLD__RESET_DSBOD__SIZE 0x00000001u +#define CYFLD__RESET_LOCKUP__OFFSET 0x00000002u +#define CYFLD__RESET_LOCKUP__SIZE 0x00000001u +#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003u +#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001u +#define CYFLD__RESET_SOFT__OFFSET 0x00000004u +#define CYFLD__RESET_SOFT__SIZE 0x00000001u +#define CYFLD__RESET_HVBOD__OFFSET 0x00000005u +#define CYFLD__RESET_HVBOD__SIZE 0x00000001u +#define CYFLD__RESET_PBOD__OFFSET 0x00000006u +#define CYFLD__RESET_PBOD__SIZE 0x00000001u +#define CYFLD__RESET_XRES__OFFSET 0x00000007u +#define CYFLD__RESET_XRES__SIZE 0x00000001u +#define CYREG_PWR_PWRSYS_TRIM1 0x400bff00u +#define CYFLD__HIB_BIAS_TRIM__OFFSET 0x00000000u +#define CYFLD__HIB_BIAS_TRIM__SIZE 0x00000003u +#define CYFLD__BOD_TURBO_THRESH__OFFSET 0x00000003u +#define CYFLD__BOD_TURBO_THRESH__SIZE 0x00000001u +#define CYFLD__BOD_TRIM_TRIP__OFFSET 0x00000004u +#define CYFLD__BOD_TRIM_TRIP__SIZE 0x00000004u +#define CYREG_PWR_PWRSYS_TRIM2 0x400bff04u +#define CYFLD__LFCLK_TRIM_LOAD__OFFSET 0x00000000u +#define CYFLD__LFCLK_TRIM_LOAD__SIZE 0x00000002u +#define CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET 0x00000002u +#define CYFLD__LFCLK_TRIM_VOLTAGE__SIZE 0x00000002u +#define CYFLD__DPSLP_TRIM_LOAD__OFFSET 0x00000004u +#define CYFLD__DPSLP_TRIM_LOAD__SIZE 0x00000002u +#define CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET 0x00000006u +#define CYFLD__DPSLP_TRIM_LEAKAGE__SIZE 0x00000001u +#define CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET 0x00000007u +#define CYFLD__DPSLP_TRIM_VOLTAGE__SIZE 0x00000001u +#define CYREG_PWR_PWRSYS_TRIM3 0x400bff08u +#define CYFLD__NWELL_TRIM__OFFSET 0x00000000u +#define CYFLD__NWELL_TRIM__SIZE 0x00000003u +#define CYFLD__QUIET_TRIM__OFFSET 0x00000003u +#define CYFLD__QUIET_TRIM__SIZE 0x00000005u +#define CYREG_PWR_PWRSYS_TRIM4 0x400bff0cu +#define CYFLD__HIB_TRIM_NWELL__OFFSET 0x00000000u +#define CYFLD__HIB_TRIM_NWELL__SIZE 0x00000002u +#define CYFLD__HIB_TRIM_LEAKAGE__OFFSET 0x00000002u +#define CYFLD__HIB_TRIM_LEAKAGE__SIZE 0x00000001u +#define CYFLD__HIB_TRIM_VOLTAGE__OFFSET 0x00000003u +#define CYFLD__HIB_TRIM_VOLTAGE__SIZE 0x00000001u +#define CYFLD__HIB_TRIM_REFERENCE__OFFSET 0x00000004u +#define CYFLD__HIB_TRIM_REFERENCE__SIZE 0x00000002u +#define CYREG_PWR_BG_TRIM1 0x400bff10u +#define CYFLD__INL_TRIM_MAIN__OFFSET 0x00000000u +#define CYFLD__INL_TRIM_MAIN__SIZE 0x00000003u +#define CYFLD__INL_CROSS_MAIN__OFFSET 0x00000003u +#define CYFLD__INL_CROSS_MAIN__SIZE 0x00000004u +#define CYREG_PWR_BG_TRIM2 0x400bff14u +#define CYFLD__VCTAT_SLOPE__OFFSET 0x00000000u +#define CYFLD__VCTAT_SLOPE__SIZE 0x00000004u +#define CYFLD__VCTAT_VOLTAGE__OFFSET 0x00000004u +#define CYFLD__VCTAT_VOLTAGE__SIZE 0x00000002u +#define CYFLD__VCTAT_ENABLE__OFFSET 0x00000006u +#define CYFLD__VCTAT_ENABLE__SIZE 0x00000001u +#define CYFLD__VCTAT_VOLTAGE_MSB__OFFSET 0x00000007u +#define CYFLD__VCTAT_VOLTAGE_MSB__SIZE 0x00000001u +#define CYREG_PWR_BG_TRIM3 0x400bff18u +#define CYFLD__INL_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD__INL_TRIM_IMO__SIZE 0x00000003u +#define CYFLD__INL_CROSS_IMO__OFFSET 0x00000003u +#define CYFLD__INL_CROSS_IMO__SIZE 0x00000004u +#define CYREG_PWR_BG_TRIM4 0x400bff1cu +#define CYFLD__ABS_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD__ABS_TRIM_IMO__SIZE 0x00000006u +#define CYREG_PWR_BG_TRIM5 0x400bff20u +#define CYFLD__TMPCO_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD__TMPCO_TRIM_IMO__SIZE 0x00000006u +#define CYREG_CLK_ILO_TRIM 0x400bff24u +#define CYFLD__TRIM__OFFSET 0x00000000u +#define CYFLD__TRIM__SIZE 0x00000004u +#define CYFLD__COARSE_TRIM__OFFSET 0x00000004u +#define CYFLD__COARSE_TRIM__SIZE 0x00000004u +#define CYREG_CLK_IMO_TRIM1 0x400bff28u +#define CYFLD__OFFSET__OFFSET 0x00000000u +#define CYFLD__OFFSET__SIZE 0x00000008u +#define CYREG_CLK_IMO_TRIM2 0x400bff2cu +#define CYFLD__FREQ__OFFSET 0x00000000u +#define CYFLD__FREQ__SIZE 0x00000006u +#define CYREG_CLK_IMO_TRIM3 0x400bff30u +#define CYFLD__TRIM_CLK36__OFFSET 0x00000000u +#define CYFLD__TRIM_CLK36__SIZE 0x00000004u +#define CYREG_CLK_IMO_TRIM4 0x400bff34u +#define CYFLD__GAIN__OFFSET 0x00000000u +#define CYFLD__GAIN__SIZE 0x00000005u +#define CYFLD__FSOFFSET__OFFSET 0x00000005u +#define CYFLD__FSOFFSET__SIZE 0x00000003u +#define CYREG_PWR_RSVD_TRIM 0x400bff38u +#define CYFLD__RSVD_TRIM__OFFSET 0x00000000u +#define CYFLD__RSVD_TRIM__SIZE 0x00000004u +#define CYDEV_SPCIF_BASE 0x400e0000u +#define CYDEV_SPCIF_SIZE 0x00010000u +#define CYREG_SPCIF_GEOMETRY 0x400e0000u +#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000u +#define CYFLD_SPCIF_FLASH__SIZE 0x00000010u +#define CYFLD_SPCIF_SFLASH__OFFSET 0x00000010u +#define CYFLD_SPCIF_SFLASH__SIZE 0x00000004u +#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014u +#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002u +#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016u +#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002u +#define CYFLD_SPCIF_NVL__OFFSET 0x00000018u +#define CYFLD_SPCIF_NVL__SIZE 0x00000007u +#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001fu +#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001u +#define CYREG_SPCIF_NVL_WR_DATA 0x400e001cu +#define CYFLD_SPCIF_DATA__OFFSET 0x00000000u +#define CYFLD_SPCIF_DATA__SIZE 0x00000008u +#define CYDEV_UDB_BASE 0x400f0000u +#define CYDEV_UDB_SIZE 0x00010000u +#define CYDEV_UDB_W8_BASE 0x400f0000u +#define CYDEV_UDB_W8_SIZE 0x00001000u +#define CYREG_UDB_W8_A0_00 0x400f0000u +#define CYFLD_UDB_W8_A0__OFFSET 0x00000000u +#define CYFLD_UDB_W8_A0__SIZE 0x00000008u +#define CYREG_UDB_W8_A0_01 0x400f0001u +#define CYREG_UDB_W8_A0_02 0x400f0002u +#define CYREG_UDB_W8_A0_03 0x400f0003u +#define CYREG_UDB_W8_A1_00 0x400f0010u +#define CYFLD_UDB_W8_A1__OFFSET 0x00000000u +#define CYFLD_UDB_W8_A1__SIZE 0x00000008u +#define CYREG_UDB_W8_A1_01 0x400f0011u +#define CYREG_UDB_W8_A1_02 0x400f0012u +#define CYREG_UDB_W8_A1_03 0x400f0013u +#define CYREG_UDB_W8_D0_00 0x400f0020u +#define CYFLD_UDB_W8_D0__OFFSET 0x00000000u +#define CYFLD_UDB_W8_D0__SIZE 0x00000008u +#define CYREG_UDB_W8_D0_01 0x400f0021u +#define CYREG_UDB_W8_D0_02 0x400f0022u +#define CYREG_UDB_W8_D0_03 0x400f0023u +#define CYREG_UDB_W8_D1_00 0x400f0030u +#define CYFLD_UDB_W8_D1__OFFSET 0x00000000u +#define CYFLD_UDB_W8_D1__SIZE 0x00000008u +#define CYREG_UDB_W8_D1_01 0x400f0031u +#define CYREG_UDB_W8_D1_02 0x400f0032u +#define CYREG_UDB_W8_D1_03 0x400f0033u +#define CYREG_UDB_W8_F0_00 0x400f0040u +#define CYFLD_UDB_W8_F0__OFFSET 0x00000000u +#define CYFLD_UDB_W8_F0__SIZE 0x00000008u +#define CYREG_UDB_W8_F0_01 0x400f0041u +#define CYREG_UDB_W8_F0_02 0x400f0042u +#define CYREG_UDB_W8_F0_03 0x400f0043u +#define CYREG_UDB_W8_F1_00 0x400f0050u +#define CYFLD_UDB_W8_F1__OFFSET 0x00000000u +#define CYFLD_UDB_W8_F1__SIZE 0x00000008u +#define CYREG_UDB_W8_F1_01 0x400f0051u +#define CYREG_UDB_W8_F1_02 0x400f0052u +#define CYREG_UDB_W8_F1_03 0x400f0053u +#define CYREG_UDB_W8_ST_00 0x400f0060u +#define CYFLD_UDB_W8_ST__OFFSET 0x00000000u +#define CYFLD_UDB_W8_ST__SIZE 0x00000008u +#define CYREG_UDB_W8_ST_01 0x400f0061u +#define CYREG_UDB_W8_ST_02 0x400f0062u +#define CYREG_UDB_W8_ST_03 0x400f0063u +#define CYREG_UDB_W8_CTL_00 0x400f0070u +#define CYFLD_UDB_W8_CTL__OFFSET 0x00000000u +#define CYFLD_UDB_W8_CTL__SIZE 0x00000008u +#define CYREG_UDB_W8_CTL_01 0x400f0071u +#define CYREG_UDB_W8_CTL_02 0x400f0072u +#define CYREG_UDB_W8_CTL_03 0x400f0073u +#define CYREG_UDB_W8_MSK_00 0x400f0080u +#define CYFLD_UDB_W8_MSK__OFFSET 0x00000000u +#define CYFLD_UDB_W8_MSK__SIZE 0x00000007u +#define CYREG_UDB_W8_MSK_01 0x400f0081u +#define CYREG_UDB_W8_MSK_02 0x400f0082u +#define CYREG_UDB_W8_MSK_03 0x400f0083u +#define CYREG_UDB_W8_ACTL_00 0x400f0090u +#define CYFLD_UDB_W8_FIFO0_CLR__OFFSET 0x00000000u +#define CYFLD_UDB_W8_FIFO0_CLR__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO0_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO0_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_W8_FIFO1_CLR__OFFSET 0x00000001u +#define CYFLD_UDB_W8_FIFO1_CLR__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO1_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO1_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_W8_FIFO0_LVL__OFFSET 0x00000002u +#define CYFLD_UDB_W8_FIFO0_LVL__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO0_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO0_LVL_MID 0x00000001u +#define CYFLD_UDB_W8_FIFO1_LVL__OFFSET 0x00000003u +#define CYFLD_UDB_W8_FIFO1_LVL__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO1_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO1_LVL_MID 0x00000001u +#define CYFLD_UDB_W8_INT_EN__OFFSET 0x00000004u +#define CYFLD_UDB_W8_INT_EN__SIZE 0x00000001u +#define CYVAL_UDB_W8_INT_EN_DISABLE 0x00000000u +#define CYVAL_UDB_W8_INT_EN_ENABLE 0x00000001u +#define CYFLD_UDB_W8_CNT_START__OFFSET 0x00000005u +#define CYFLD_UDB_W8_CNT_START__SIZE 0x00000001u +#define CYVAL_UDB_W8_CNT_START_DISABLE 0x00000000u +#define CYVAL_UDB_W8_CNT_START_ENABLE 0x00000001u +#define CYREG_UDB_W8_ACTL_01 0x400f0091u +#define CYREG_UDB_W8_ACTL_02 0x400f0092u +#define CYREG_UDB_W8_ACTL_03 0x400f0093u +#define CYREG_UDB_W8_MC_00 0x400f00a0u +#define CYFLD_UDB_W8_PLD0_MC__OFFSET 0x00000000u +#define CYFLD_UDB_W8_PLD0_MC__SIZE 0x00000004u +#define CYFLD_UDB_W8_PLD1_MC__OFFSET 0x00000004u +#define CYFLD_UDB_W8_PLD1_MC__SIZE 0x00000004u +#define CYREG_UDB_W8_MC_01 0x400f00a1u +#define CYREG_UDB_W8_MC_02 0x400f00a2u +#define CYREG_UDB_W8_MC_03 0x400f00a3u +#define CYDEV_UDB_CAT16_BASE 0x400f1000u +#define CYDEV_UDB_CAT16_SIZE 0x00001000u +#define CYREG_UDB_CAT16_A_00 0x400f1000u +#define CYFLD_UDB_CAT16_A0__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_A0__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_A1__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_A1__SIZE 0x00000008u +#define CYREG_UDB_CAT16_A_01 0x400f1002u +#define CYREG_UDB_CAT16_A_02 0x400f1004u +#define CYREG_UDB_CAT16_A_03 0x400f1006u +#define CYREG_UDB_CAT16_D_00 0x400f1040u +#define CYFLD_UDB_CAT16_D0__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_D0__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_D1__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_D1__SIZE 0x00000008u +#define CYREG_UDB_CAT16_D_01 0x400f1042u +#define CYREG_UDB_CAT16_D_02 0x400f1044u +#define CYREG_UDB_CAT16_D_03 0x400f1046u +#define CYREG_UDB_CAT16_F_00 0x400f1080u +#define CYFLD_UDB_CAT16_F0__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_F0__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_F1__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_F1__SIZE 0x00000008u +#define CYREG_UDB_CAT16_F_01 0x400f1082u +#define CYREG_UDB_CAT16_F_02 0x400f1084u +#define CYREG_UDB_CAT16_F_03 0x400f1086u +#define CYREG_UDB_CAT16_CTL_ST_00 0x400f10c0u +#define CYFLD_UDB_CAT16_ST__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_ST__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_CTL__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_CTL__SIZE 0x00000008u +#define CYREG_UDB_CAT16_CTL_ST_01 0x400f10c2u +#define CYREG_UDB_CAT16_CTL_ST_02 0x400f10c4u +#define CYREG_UDB_CAT16_CTL_ST_03 0x400f10c6u +#define CYREG_UDB_CAT16_ACTL_MSK_00 0x400f1100u +#define CYFLD_UDB_CAT16_MSK__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_MSK__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_FIFO0_CLR__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET 0x00000009u +#define CYFLD_UDB_CAT16_FIFO1_CLR__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET 0x0000000au +#define CYFLD_UDB_CAT16_FIFO0_LVL__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO0_LVL_MID 0x00000001u +#define CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET 0x0000000bu +#define CYFLD_UDB_CAT16_FIFO1_LVL__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO1_LVL_MID 0x00000001u +#define CYFLD_UDB_CAT16_INT_EN__OFFSET 0x0000000cu +#define CYFLD_UDB_CAT16_INT_EN__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_INT_EN_DISABLE 0x00000000u +#define CYVAL_UDB_CAT16_INT_EN_ENABLE 0x00000001u +#define CYFLD_UDB_CAT16_CNT_START__OFFSET 0x0000000du +#define CYFLD_UDB_CAT16_CNT_START__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_CNT_START_DISABLE 0x00000000u +#define CYVAL_UDB_CAT16_CNT_START_ENABLE 0x00000001u +#define CYREG_UDB_CAT16_ACTL_MSK_01 0x400f1102u +#define CYREG_UDB_CAT16_ACTL_MSK_02 0x400f1104u +#define CYREG_UDB_CAT16_ACTL_MSK_03 0x400f1106u +#define CYREG_UDB_CAT16_MC_00 0x400f1140u +#define CYFLD_UDB_CAT16_PLD0_MC__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_PLD0_MC__SIZE 0x00000004u +#define CYFLD_UDB_CAT16_PLD1_MC__OFFSET 0x00000004u +#define CYFLD_UDB_CAT16_PLD1_MC__SIZE 0x00000004u +#define CYREG_UDB_CAT16_MC_01 0x400f1142u +#define CYREG_UDB_CAT16_MC_02 0x400f1144u +#define CYREG_UDB_CAT16_MC_03 0x400f1146u +#define CYDEV_UDB_W16_BASE 0x400f1000u +#define CYDEV_UDB_W16_SIZE 0x00001000u +#define CYREG_UDB_W16_A0_00 0x400f1000u +#define CYFLD_UDB_W16_A0_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_A0_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_A0_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_A0_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_A0_01 0x400f1002u +#define CYREG_UDB_W16_A0_02 0x400f1004u +#define CYREG_UDB_W16_A1_00 0x400f1020u +#define CYFLD_UDB_W16_A1_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_A1_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_A1_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_A1_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_A1_01 0x400f1022u +#define CYREG_UDB_W16_A1_02 0x400f1024u +#define CYREG_UDB_W16_D0_00 0x400f1040u +#define CYFLD_UDB_W16_D0_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_D0_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_D0_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_D0_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_D0_01 0x400f1042u +#define CYREG_UDB_W16_D0_02 0x400f1044u +#define CYREG_UDB_W16_D1_00 0x400f1060u +#define CYFLD_UDB_W16_D1_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_D1_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_D1_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_D1_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_D1_01 0x400f1062u +#define CYREG_UDB_W16_D1_02 0x400f1064u +#define CYREG_UDB_W16_F0_00 0x400f1080u +#define CYFLD_UDB_W16_F0_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_F0_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_F0_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_F0_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_F0_01 0x400f1082u +#define CYREG_UDB_W16_F0_02 0x400f1084u +#define CYREG_UDB_W16_F1_00 0x400f10a0u +#define CYFLD_UDB_W16_F1_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_F1_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_F1_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_F1_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_F1_01 0x400f10a2u +#define CYREG_UDB_W16_F1_02 0x400f10a4u +#define CYREG_UDB_W16_ST_00 0x400f10c0u +#define CYFLD_UDB_W16_ST_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_ST_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_ST_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_ST_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_ST_01 0x400f10c2u +#define CYREG_UDB_W16_ST_02 0x400f10c4u +#define CYREG_UDB_W16_CTL_00 0x400f10e0u +#define CYFLD_UDB_W16_CTL_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_CTL_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_CTL_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_CTL_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_CTL_01 0x400f10e2u +#define CYREG_UDB_W16_CTL_02 0x400f10e4u +#define CYREG_UDB_W16_MSK_00 0x400f1100u +#define CYFLD_UDB_W16_MSK_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_MSK_LS__SIZE 0x00000007u +#define CYFLD_UDB_W16_MSK_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_MSK_MS__SIZE 0x00000007u +#define CYREG_UDB_W16_MSK_01 0x400f1102u +#define CYREG_UDB_W16_MSK_02 0x400f1104u +#define CYREG_UDB_W16_ACTL_00 0x400f1120u +#define CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET 0x00000001u +#define CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET 0x00000002u +#define CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_LVL_LS_MID 0x00000001u +#define CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET 0x00000003u +#define CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_LVL_LS_MID 0x00000001u +#define CYFLD_UDB_W16_INT_EN_LS__OFFSET 0x00000004u +#define CYFLD_UDB_W16_INT_EN_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_INT_EN_LS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_INT_EN_LS_ENABLE 0x00000001u +#define CYFLD_UDB_W16_CNT_START_LS__OFFSET 0x00000005u +#define CYFLD_UDB_W16_CNT_START_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_CNT_START_LS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_CNT_START_LS_ENABLE 0x00000001u +#define CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET 0x00000009u +#define CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET 0x0000000au +#define CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_LVL_MS_MID 0x00000001u +#define CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET 0x0000000bu +#define CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_LVL_MS_MID 0x00000001u +#define CYFLD_UDB_W16_INT_EN_MS__OFFSET 0x0000000cu +#define CYFLD_UDB_W16_INT_EN_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_INT_EN_MS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_INT_EN_MS_ENABLE 0x00000001u +#define CYFLD_UDB_W16_CNT_START_MS__OFFSET 0x0000000du +#define CYFLD_UDB_W16_CNT_START_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_CNT_START_MS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_CNT_START_MS_ENABLE 0x00000001u +#define CYREG_UDB_W16_ACTL_01 0x400f1122u +#define CYREG_UDB_W16_ACTL_02 0x400f1124u +#define CYREG_UDB_W16_MC_00 0x400f1140u +#define CYFLD_UDB_W16_PLD0_MC_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_PLD0_MC_LS__SIZE 0x00000004u +#define CYFLD_UDB_W16_PLD1_MC_LS__OFFSET 0x00000004u +#define CYFLD_UDB_W16_PLD1_MC_LS__SIZE 0x00000004u +#define CYFLD_UDB_W16_PLD0_MC_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_PLD0_MC_MS__SIZE 0x00000004u +#define CYFLD_UDB_W16_PLD1_MC_MS__OFFSET 0x0000000cu +#define CYFLD_UDB_W16_PLD1_MC_MS__SIZE 0x00000004u +#define CYREG_UDB_W16_MC_01 0x400f1142u +#define CYREG_UDB_W16_MC_02 0x400f1144u +#define CYDEV_UDB_W32_BASE 0x400f2000u +#define CYDEV_UDB_W32_SIZE 0x00001000u +#define CYREG_UDB_W32_A0_00 0x400f2000u +#define CYFLD_UDB_W32_A0_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_A0_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_A0_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_A0_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_A0_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_A0_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_A0_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_A0_3__SIZE 0x00000008u +#define CYREG_UDB_W32_A1_00 0x400f2040u +#define CYFLD_UDB_W32_A1_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_A1_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_A1_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_A1_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_A1_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_A1_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_A1_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_A1_3__SIZE 0x00000008u +#define CYREG_UDB_W32_D0_00 0x400f2080u +#define CYFLD_UDB_W32_D0_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_D0_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_D0_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_D0_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_D0_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_D0_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_D0_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_D0_3__SIZE 0x00000008u +#define CYREG_UDB_W32_D1_00 0x400f20c0u +#define CYFLD_UDB_W32_D1_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_D1_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_D1_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_D1_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_D1_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_D1_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_D1_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_D1_3__SIZE 0x00000008u +#define CYREG_UDB_W32_F0_00 0x400f2100u +#define CYFLD_UDB_W32_F0_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_F0_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_F0_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_F0_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_F0_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_F0_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_F0_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_F0_3__SIZE 0x00000008u +#define CYREG_UDB_W32_F1_00 0x400f2140u +#define CYFLD_UDB_W32_F1_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_F1_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_F1_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_F1_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_F1_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_F1_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_F1_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_F1_3__SIZE 0x00000008u +#define CYREG_UDB_W32_ST_00 0x400f2180u +#define CYFLD_UDB_W32_ST_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_ST_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_ST_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_ST_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_ST_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_ST_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_ST_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_ST_3__SIZE 0x00000008u +#define CYREG_UDB_W32_CTL_00 0x400f21c0u +#define CYFLD_UDB_W32_CTL_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_CTL_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_CTL_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_CTL_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_CTL_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_CTL_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_CTL_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_CTL_3__SIZE 0x00000008u +#define CYREG_UDB_W32_MSK_00 0x400f2200u +#define CYFLD_UDB_W32_MSK_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_MSK_0__SIZE 0x00000007u +#define CYFLD_UDB_W32_MSK_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_MSK_1__SIZE 0x00000007u +#define CYFLD_UDB_W32_MSK_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_MSK_2__SIZE 0x00000007u +#define CYFLD_UDB_W32_MSK_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_MSK_3__SIZE 0x00000007u +#define CYREG_UDB_W32_ACTL_00 0x400f2240u +#define CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_FIFO0_CLR_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET 0x00000002u +#define CYFLD_UDB_W32_FIFO0_LVL_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_0_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET 0x00000003u +#define CYFLD_UDB_W32_FIFO1_LVL_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_0_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_0__OFFSET 0x00000004u +#define CYFLD_UDB_W32_INT_EN_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_0_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_0_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_0__OFFSET 0x00000005u +#define CYFLD_UDB_W32_CNT_START_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_0_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_0_ENABLE 0x00000001u +#define CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_FIFO0_CLR_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET 0x00000009u +#define CYFLD_UDB_W32_FIFO1_CLR_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET 0x0000000au +#define CYFLD_UDB_W32_FIFO0_LVL_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_1_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET 0x0000000bu +#define CYFLD_UDB_W32_FIFO1_LVL_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_1_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_1__OFFSET 0x0000000cu +#define CYFLD_UDB_W32_INT_EN_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_1_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_1_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_1__OFFSET 0x0000000du +#define CYFLD_UDB_W32_CNT_START_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_1_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_1_ENABLE 0x00000001u +#define CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_FIFO0_CLR_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET 0x00000011u +#define CYFLD_UDB_W32_FIFO1_CLR_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET 0x00000012u +#define CYFLD_UDB_W32_FIFO0_LVL_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_2_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET 0x00000013u +#define CYFLD_UDB_W32_FIFO1_LVL_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_2_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_2__OFFSET 0x00000014u +#define CYFLD_UDB_W32_INT_EN_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_2_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_2_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_2__OFFSET 0x00000015u +#define CYFLD_UDB_W32_CNT_START_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_2_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_2_ENABLE 0x00000001u +#define CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_FIFO0_CLR_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET 0x00000019u +#define CYFLD_UDB_W32_FIFO1_CLR_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET 0x0000001au +#define CYFLD_UDB_W32_FIFO0_LVL_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_3_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET 0x0000001bu +#define CYFLD_UDB_W32_FIFO1_LVL_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_3_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_3__OFFSET 0x0000001cu +#define CYFLD_UDB_W32_INT_EN_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_3_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_3_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_3__OFFSET 0x0000001du +#define CYFLD_UDB_W32_CNT_START_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_3_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_3_ENABLE 0x00000001u +#define CYREG_UDB_W32_MC_00 0x400f2280u +#define CYFLD_UDB_W32_PLD0_MC_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_PLD0_MC_0__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_0__OFFSET 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_0__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD0_MC_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_PLD0_MC_1__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_1__OFFSET 0x0000000cu +#define CYFLD_UDB_W32_PLD1_MC_1__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD0_MC_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_PLD0_MC_2__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_2__OFFSET 0x00000014u +#define CYFLD_UDB_W32_PLD1_MC_2__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD0_MC_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_PLD0_MC_3__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_3__OFFSET 0x0000001cu +#define CYFLD_UDB_W32_PLD1_MC_3__SIZE 0x00000004u +#define CYDEV_UDB_P0_BASE 0x400f3000u +#define CYDEV_UDB_P0_SIZE 0x00000200u +#define CYDEV_UDB_P0_U0_BASE 0x400f3000u +#define CYDEV_UDB_P0_U0_SIZE 0x00000080u +#define CYREG_UDB_P0_U0_PLD_IT0 0x400f3000u +#define CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET 0x00000010u +#define CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET 0x00000011u +#define CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET 0x00000012u +#define CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET 0x00000013u +#define CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET 0x00000014u +#define CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET 0x00000015u +#define CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET 0x00000016u +#define CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET 0x00000017u +#define CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET 0x00000018u +#define CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET 0x00000019u +#define CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET 0x0000001au +#define CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET 0x0000001bu +#define CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET 0x0000001cu +#define CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET 0x0000001du +#define CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET 0x0000001eu +#define CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET 0x0000001fu +#define CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_PLD_IT1 0x400f3004u +#define CYREG_UDB_P0_U0_PLD_IT2 0x400f3008u +#define CYREG_UDB_P0_U0_PLD_IT3 0x400f300cu +#define CYREG_UDB_P0_U0_PLD_IT4 0x400f3010u +#define CYREG_UDB_P0_U0_PLD_IT5 0x400f3014u +#define CYREG_UDB_P0_U0_PLD_IT6 0x400f3018u +#define CYREG_UDB_P0_U0_PLD_IT7 0x400f301cu +#define CYREG_UDB_P0_U0_PLD_IT8 0x400f3020u +#define CYREG_UDB_P0_U0_PLD_IT9 0x400f3024u +#define CYREG_UDB_P0_U0_PLD_IT10 0x400f3028u +#define CYREG_UDB_P0_U0_PLD_IT11 0x400f302cu +#define CYREG_UDB_P0_U0_PLD_ORT0 0x400f3030u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_PLD_ORT1 0x400f3032u +#define CYREG_UDB_P0_U0_PLD_ORT2 0x400f3034u +#define CYREG_UDB_P0_U0_PLD_ORT3 0x400f3036u +#define CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST 0x400f3038u +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED 0x00000001u +#define CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB 0x400f303au +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L 0x00000003u +#define CYREG_UDB_P0_U0_PLD_MC_SET_RESET 0x400f303cu +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS 0x400f303eu +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_NC1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC3__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_NC3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC5__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_NC5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC7__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_NC7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC9__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_NC9__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC11__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_NC11__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC13__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_NC13__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC15__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_NC15__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG0 0x400f3040u +#define CYFLD_UDB_P_U_RAD0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RAD0__SIZE 0x00000003u +#define CYVAL_UDB_P_U_RAD0_OFF 0x00000000u +#define CYVAL_UDB_P_U_RAD0_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_RAD0_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_RAD0_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_RAD0_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_RAD0_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_RAD0_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_RAD0_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_RAD1__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_RAD1__SIZE 0x00000003u +#define CYVAL_UDB_P_U_RAD1_OFF 0x00000000u +#define CYVAL_UDB_P_U_RAD1_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_RAD1_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_RAD1_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_RAD1_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_RAD1_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_RAD1_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_RAD1_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG1 0x400f3041u +#define CYFLD_UDB_P_U_RAD2__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RAD2__SIZE 0x00000003u +#define CYVAL_UDB_P_U_RAD2_OFF 0x00000000u +#define CYVAL_UDB_P_U_RAD2_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_RAD2_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_RAD2_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_RAD2_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_RAD2_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_RAD2_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_RAD2_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS 0x00000001u +#define CYREG_UDB_P0_U0_CFG2 0x400f3042u +#define CYFLD_UDB_P_U_F0_LD__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_F0_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_F0_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_F0_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_F0_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_F0_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_F0_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_F0_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_F0_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_F0_LD_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_F1_LD__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_F1_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_F1_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_F1_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_F1_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_F1_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_F1_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_F1_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_F1_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_F1_LD_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG3 0x400f3043u +#define CYFLD_UDB_P_U_D0_LD__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_D0_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_D0_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_D0_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_D0_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_D0_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_D0_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_D0_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_D0_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_D0_LD_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_D1_LD__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_D1_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_D1_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_D1_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_D1_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_D1_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_D1_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_D1_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_D1_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_D1_LD_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG4 0x400f3044u +#define CYFLD_UDB_P_U_SI_MUX__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_SI_MUX__SIZE 0x00000003u +#define CYVAL_UDB_P_U_SI_MUX_OFF 0x00000000u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_SI_MUX_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_CI_MUX__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_CI_MUX__SIZE 0x00000003u +#define CYVAL_UDB_P_U_CI_MUX_OFF 0x00000000u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_CI_MUX_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG5 0x400f3045u +#define CYFLD_UDB_P_U_OUT0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT0__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT0_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT0_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT0_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT0_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT0_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT0_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT0_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT0_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT0_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT0_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT0_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT0_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT0_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT0_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT0_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT0_F1_BUS_STAT 0x0000000fu +#define CYFLD_UDB_P_U_OUT1__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_OUT1__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT1_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT1_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT1_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT1_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT1_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT1_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT1_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT1_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT1_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT1_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT1_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT1_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT1_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT1_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT1_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT1_F1_BUS_STAT 0x0000000fu +#define CYREG_UDB_P0_U0_CFG6 0x400f3046u +#define CYFLD_UDB_P_U_OUT2__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT2__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT2_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT2_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT2_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT2_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT2_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT2_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT2_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT2_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT2_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT2_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT2_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT2_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT2_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT2_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT2_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT2_F1_BUS_STAT 0x0000000fu +#define CYFLD_UDB_P_U_OUT3__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_OUT3__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT3_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT3_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT3_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT3_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT3_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT3_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT3_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT3_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT3_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT3_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT3_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT3_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT3_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT3_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT3_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT3_F1_BUS_STAT 0x0000000fu +#define CYREG_UDB_P0_U0_CFG7 0x400f3047u +#define CYFLD_UDB_P_U_OUT4__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT4__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT4_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT4_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT4_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT4_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT4_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT4_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT4_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT4_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT4_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT4_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT4_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT4_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT4_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT4_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT4_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT4_F1_BUS_STAT 0x0000000fu +#define CYFLD_UDB_P_U_OUT5__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_OUT5__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT5_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT5_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT5_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT5_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT5_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT5_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT5_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT5_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT5_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT5_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT5_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT5_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT5_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT5_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT5_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT5_F1_BUS_STAT 0x0000000fu +#define CYREG_UDB_P0_U0_CFG8 0x400f3048u +#define CYFLD_UDB_P_U_OUT_SYNC__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT_SYNC__SIZE 0x00000006u +#define CYVAL_UDB_P_U_OUT_SYNC_REGISTERED 0x00000000u +#define CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC6__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_NC6__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG9 0x400f3049u +#define CYFLD_UDB_P_U_AMASK__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_AMASK__SIZE 0x00000008u +#define CYREG_UDB_P0_U0_CFG10 0x400f304au +#define CYFLD_UDB_P_U_CMASK0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CMASK0__SIZE 0x00000008u +#define CYREG_UDB_P0_U0_CFG11 0x400f304bu +#define CYREG_UDB_P0_U0_CFG12 0x400f304cu +#define CYFLD_UDB_P_U_SI_SELA__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_SI_SELA__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELA_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_SI_SELA_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_SI_SELA_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELA_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_SI_SELB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_SI_SELB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELB_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_SI_SELB_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_SI_SELB_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELB_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_DEF_SI__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_DEF_SI__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 0x00000000u +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 0x00000001u +#define CYFLD_UDB_P_U_AMASK_EN__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_AMASK_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_AMASK_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_AMASK_EN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CMASK0_EN__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_CMASK0_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CMASK0_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CMASK0_EN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CMASK1_EN__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_CMASK1_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CMASK1_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CMASK1_EN_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_CFG13 0x400f304du +#define CYFLD_UDB_P_U_CI_SELA__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CI_SELA__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELA_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_CI_SELA_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_CI_SELA_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELA_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_CI_SELB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CI_SELB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELB_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_CI_SELB_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_CI_SELB_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELB_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_CMP_SELA__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_CMP_SELA__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELA_A1_D1 0x00000000u +#define CYVAL_UDB_P_U_CMP_SELA_A1_A0 0x00000001u +#define CYVAL_UDB_P_U_CMP_SELA_A0_D1 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELA_A0_A0 0x00000003u +#define CYFLD_UDB_P_U_CMP_SELB__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_CMP_SELB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELB_A1_D1 0x00000000u +#define CYVAL_UDB_P_U_CMP_SELB_A1_A0 0x00000001u +#define CYVAL_UDB_P_U_CMP_SELB_A0_D1 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELB_A0_A0 0x00000003u +#define CYREG_UDB_P0_U0_CFG14 0x400f304eu +#define CYFLD_UDB_P_U_CHAIN0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CHAIN0__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN0_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN0_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CHAIN1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_CHAIN1__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN1_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN1_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CHAIN_FB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CHAIN_FB__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN_FB_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN_FB_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_CHAIN_CMSB__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_MSB_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_MSB_SEL__SIZE 0x00000003u +#define CYVAL_UDB_P_U_MSB_SEL_BIT0 0x00000000u +#define CYVAL_UDB_P_U_MSB_SEL_BIT1 0x00000001u +#define CYVAL_UDB_P_U_MSB_SEL_BIT2 0x00000002u +#define CYVAL_UDB_P_U_MSB_SEL_BIT3 0x00000003u +#define CYVAL_UDB_P_U_MSB_SEL_BIT4 0x00000004u +#define CYVAL_UDB_P_U_MSB_SEL_BIT5 0x00000005u +#define CYVAL_UDB_P_U_MSB_SEL_BIT6 0x00000006u +#define CYVAL_UDB_P_U_MSB_SEL_BIT7 0x00000007u +#define CYFLD_UDB_P_U_MSB_EN__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_MSB_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_MSB_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_MSB_EN_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_CFG15 0x400f304fu +#define CYFLD_UDB_P_U_F0_INSEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_F0_INSEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_F0_INSEL_INPUT 0x00000000u +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 0x00000001u +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 0x00000002u +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU 0x00000003u +#define CYFLD_UDB_P_U_F1_INSEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_F1_INSEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_F1_INSEL_INPUT 0x00000000u +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 0x00000001u +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 0x00000002u +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU 0x00000003u +#define CYFLD_UDB_P_U_MSB_SI__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_MSB_SI__SIZE 0x00000001u +#define CYVAL_UDB_P_U_MSB_SI_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_MSB_SI_MSB 0x00000001u +#define CYFLD_UDB_P_U_PI_DYN__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PI_DYN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PI_DYN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PI_DYN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_SHIFT_SEL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_SHIFT_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB 0x00000000u +#define CYVAL_UDB_P_U_SHIFT_SEL_SOR 0x00000001u +#define CYFLD_UDB_P_U_PI_SEL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PI_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PI_SEL_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_PI_SEL_PARALLEL 0x00000001u +#define CYREG_UDB_P0_U0_CFG16 0x400f3050u +#define CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_WRK16_CONCAT__SIZE 0x00000001u +#define CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE 0x00000001u +#define CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_EXT_CRCPRS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL 0x00000000u +#define CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL 0x00000001u +#define CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_FIFO_ASYNC__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_EDGE__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_FIFO_EDGE__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_EDGE_LEVEL 0x00000000u +#define CYVAL_UDB_P_U_FIFO_EDGE_EDGE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_CAP__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_FIFO_CAP__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_CAP_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_CAP_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_FAST__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_FIFO_FAST__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_FAST_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_FAST_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_F0_CK_INV__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_F0_CK_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F0_CK_INV_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_F0_CK_INV_INVERT 0x00000001u +#define CYFLD_UDB_P_U_F1_CK_INV__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_F1_CK_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F1_CK_INV_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_F1_CK_INV_INVERT 0x00000001u +#define CYREG_UDB_P0_U0_CFG17 0x400f3051u +#define CYFLD_UDB_P_U_F0_DYN__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_F0_DYN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F0_DYN_STATIC 0x00000000u +#define CYVAL_UDB_P_U_F0_DYN_DYNAMIC 0x00000001u +#define CYFLD_UDB_P_U_F1_DYN__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_F1_DYN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F1_DYN_STATIC 0x00000000u +#define CYVAL_UDB_P_U_F1_DYN_DYNAMIC 0x00000001u +#define CYFLD_UDB_P_U_NC2__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_NC2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_CFG18 0x400f3052u +#define CYFLD_UDB_P_U_CTL_MD0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CTL_MD0__SIZE 0x00000008u +#define CYVAL_UDB_P_U_CTL_MD0_DIRECT 0x00000000u +#define CYVAL_UDB_P_U_CTL_MD0_SYNC 0x00000001u +#define CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC 0x00000002u +#define CYVAL_UDB_P_U_CTL_MD0_PULSE 0x00000003u +#define CYREG_UDB_P0_U0_CFG19 0x400f3053u +#define CYFLD_UDB_P_U_CTL_MD1__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CTL_MD1__SIZE 0x00000008u +#define CYVAL_UDB_P_U_CTL_MD1_DIRECT 0x00000000u +#define CYVAL_UDB_P_U_CTL_MD1_SYNC 0x00000001u +#define CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC 0x00000002u +#define CYVAL_UDB_P_U_CTL_MD1_PULSE 0x00000003u +#define CYREG_UDB_P0_U0_CFG20 0x400f3054u +#define CYFLD_UDB_P_U_STAT_MD__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_STAT_MD__SIZE 0x00000008u +#define CYREG_UDB_P0_U0_CFG21 0x400f3055u +#define CYFLD_UDB_P_U_NC0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_NC0__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG22 0x400f3056u +#define CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_SC_OUT_CTL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL 0x00000000u +#define CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL 0x00000001u +#define CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER 0x00000002u +#define CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED 0x00000003u +#define CYFLD_UDB_P_U_SC_INT_MD__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_SC_INT_MD__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_INT_MD_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_SC_INT_MD_INT_MODE 0x00000001u +#define CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_SC_SYNC_MD__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE 0x00000001u +#define CYFLD_UDB_P_U_SC_EXT_RES__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_SC_EXT_RES__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_EXT_RES_DISABLED 0x00000000u +#define CYVAL_UDB_P_U_SC_EXT_RES_ENABLED 0x00000001u +#define CYREG_UDB_P0_U0_CFG23 0x400f3057u +#define CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CNT_LD_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 0x00000000u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 0x00000001u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 0x00000002u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 0x00000003u +#define CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CNT_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 0x00000000u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 0x00000001u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 0x00000002u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO 0x00000003u +#define CYFLD_UDB_P_U_ROUTE_LD__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_ROUTE_LD__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ROUTE_LD_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_ROUTE_LD_ROUTED 0x00000001u +#define CYFLD_UDB_P_U_ROUTE_EN__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_ROUTE_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ROUTE_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_ROUTE_EN_ROUTED 0x00000001u +#define CYFLD_UDB_P_U_ALT_CNT__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_ALT_CNT__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE 0x00000000u +#define CYVAL_UDB_P_U_ALT_CNT_ALT_MODE 0x00000001u +#define CYREG_UDB_P0_U0_CFG24 0x400f3058u +#define CYFLD_UDB_P_U_RC_EN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RC_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 0x00000000u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 0x00000001u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 0x00000003u +#define CYFLD_UDB_P_U_RC_EN_MODE__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_RC_EN_MODE__SIZE 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_MODE_OFF 0x00000000u +#define CYVAL_UDB_P_U_RC_EN_MODE_ON 0x00000001u +#define CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_MODE_LEVEL 0x00000003u +#define CYFLD_UDB_P_U_RC_EN_INV__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_RC_EN_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_RC_EN_INV_NOINV 0x00000000u +#define CYVAL_UDB_P_U_RC_EN_INV_INVERT 0x00000001u +#define CYFLD_UDB_P_U_RC_INV__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_RC_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_RC_INV_NOINV 0x00000000u +#define CYVAL_UDB_P_U_RC_INV_INVERT 0x00000001u +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE 0x00000001u +#define CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_RC_RES_SEL1__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG25 0x400f3059u +#define CYREG_UDB_P0_U0_CFG26 0x400f305au +#define CYREG_UDB_P0_U0_CFG27 0x400f305bu +#define CYREG_UDB_P0_U0_CFG28 0x400f305cu +#define CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK 0x00000009u +#define CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK 0x00000009u +#define CYREG_UDB_P0_U0_CFG29 0x400f305du +#define CYFLD_UDB_P_U_DP_CK_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_DP_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK 0x00000009u +#define CYFLD_UDB_P_U_SC_CK_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_SC_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK 0x00000009u +#define CYREG_UDB_P0_U0_CFG30 0x400f305eu +#define CYFLD_UDB_P_U_RES_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RES_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN0 0x00000000u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN1 0x00000001u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN2 0x00000002u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN3 0x00000003u +#define CYFLD_UDB_P_U_RES_POL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_RES_POL_NEGATED 0x00000000u +#define CYVAL_UDB_P_U_RES_POL_ASSERTED 0x00000001u +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_GUDB_WR__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_GUDB_WR__SIZE 0x00000001u +#define CYVAL_UDB_P_U_GUDB_WR_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_GUDB_WR_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_DP_RES_POL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_DP_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_DP_RES_POL_INVERT 0x00000001u +#define CYFLD_UDB_P_U_SC_RES_POL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_SC_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_SC_RES_POL_INVERT 0x00000001u +#define CYREG_UDB_P0_U0_CFG31 0x400f305fu +#define CYFLD_UDB_P_U_ALT_RES__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_ALT_RES__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ALT_RES_COMPATIBLE 0x00000000u +#define CYVAL_UDB_P_U_ALT_RES_ALTERNATE 0x00000001u +#define CYFLD_UDB_P_U_EXT_SYNC__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_EXT_SYNC__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EXT_SYNC_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_EXT_SYNC_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_EN_RES_STAT__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_EN_RES_STAT__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EN_RES_STAT_NEGATED 0x00000000u +#define CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED 0x00000001u +#define CYFLD_UDB_P_U_EN_RES_DP__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_EN_RES_DP__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EN_RES_DP_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_EN_RES_DP_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_EXT_CK_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 0x00000000u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 0x00000001u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 0x00000002u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 0x00000003u +#define CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_RES_POL_INVERT 0x00000001u +#define CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD1_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_RES_POL_INVERT 0x00000001u +#define CYREG_UDB_P0_U0_DCFG0 0x400f3060u +#define CYFLD_UDB_P_U_CMP_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CMP_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CMP_SEL_CFG_A 0x00000000u +#define CYVAL_UDB_P_U_CMP_SEL_CFG_B 0x00000001u +#define CYFLD_UDB_P_U_SI_SEL__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_SI_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SI_SEL_CFG_A 0x00000000u +#define CYVAL_UDB_P_U_SI_SEL_CFG_B 0x00000001u +#define CYFLD_UDB_P_U_CI_SEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CI_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CI_SEL_CFG_A 0x00000000u +#define CYVAL_UDB_P_U_CI_SEL_CFG_B 0x00000001u +#define CYFLD_UDB_P_U_CFB_EN__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_CFB_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CFB_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CFB_EN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_A1_WR_SRC__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_A1_WR_SRC__SIZE 0x00000002u +#define CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE 0x00000000u +#define CYVAL_UDB_P_U_A1_WR_SRC_ALU 0x00000001u +#define CYVAL_UDB_P_U_A1_WR_SRC_D1 0x00000002u +#define CYVAL_UDB_P_U_A1_WR_SRC_F1 0x00000003u +#define CYFLD_UDB_P_U_A0_WR_SRC__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_A0_WR_SRC__SIZE 0x00000002u +#define CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE 0x00000000u +#define CYVAL_UDB_P_U_A0_WR_SRC_ALU 0x00000001u +#define CYVAL_UDB_P_U_A0_WR_SRC_D0 0x00000002u +#define CYVAL_UDB_P_U_A0_WR_SRC_F0 0x00000003u +#define CYFLD_UDB_P_U_SHIFT__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_SHIFT__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SHIFT_NOSHIFT 0x00000000u +#define CYVAL_UDB_P_U_SHIFT_LEFT 0x00000001u +#define CYVAL_UDB_P_U_SHIFT_RIGHT 0x00000002u +#define CYVAL_UDB_P_U_SHIFT_SWAP 0x00000003u +#define CYFLD_UDB_P_U_SRC_B__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_SRC_B__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SRC_B_D0 0x00000000u +#define CYVAL_UDB_P_U_SRC_B_D1 0x00000001u +#define CYVAL_UDB_P_U_SRC_B_A0 0x00000002u +#define CYVAL_UDB_P_U_SRC_B_A1 0x00000003u +#define CYFLD_UDB_P_U_SRC_A__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_SRC_A__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SRC_A_A0 0x00000000u +#define CYVAL_UDB_P_U_SRC_A_A1 0x00000001u +#define CYFLD_UDB_P_U_FUNC__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_FUNC__SIZE 0x00000003u +#define CYVAL_UDB_P_U_FUNC_PASS 0x00000000u +#define CYVAL_UDB_P_U_FUNC_INC_A 0x00000001u +#define CYVAL_UDB_P_U_FUNC_DEC_A 0x00000002u +#define CYVAL_UDB_P_U_FUNC_ADD 0x00000003u +#define CYVAL_UDB_P_U_FUNC_SUB 0x00000004u +#define CYVAL_UDB_P_U_FUNC_XOR 0x00000005u +#define CYVAL_UDB_P_U_FUNC_AND 0x00000006u +#define CYVAL_UDB_P_U_FUNC_OR 0x00000007u +#define CYREG_UDB_P0_U0_DCFG1 0x400f3062u +#define CYREG_UDB_P0_U0_DCFG2 0x400f3064u +#define CYREG_UDB_P0_U0_DCFG3 0x400f3066u +#define CYREG_UDB_P0_U0_DCFG4 0x400f3068u +#define CYREG_UDB_P0_U0_DCFG5 0x400f306au +#define CYREG_UDB_P0_U0_DCFG6 0x400f306cu +#define CYREG_UDB_P0_U0_DCFG7 0x400f306eu +#define CYDEV_UDB_P0_U1_BASE 0x400f3080u +#define CYDEV_UDB_P0_U1_SIZE 0x00000080u +#define CYREG_UDB_P0_U1_PLD_IT0 0x400f3080u +#define CYREG_UDB_P0_U1_PLD_IT1 0x400f3084u +#define CYREG_UDB_P0_U1_PLD_IT2 0x400f3088u +#define CYREG_UDB_P0_U1_PLD_IT3 0x400f308cu +#define CYREG_UDB_P0_U1_PLD_IT4 0x400f3090u +#define CYREG_UDB_P0_U1_PLD_IT5 0x400f3094u +#define CYREG_UDB_P0_U1_PLD_IT6 0x400f3098u +#define CYREG_UDB_P0_U1_PLD_IT7 0x400f309cu +#define CYREG_UDB_P0_U1_PLD_IT8 0x400f30a0u +#define CYREG_UDB_P0_U1_PLD_IT9 0x400f30a4u +#define CYREG_UDB_P0_U1_PLD_IT10 0x400f30a8u +#define CYREG_UDB_P0_U1_PLD_IT11 0x400f30acu +#define CYREG_UDB_P0_U1_PLD_ORT0 0x400f30b0u +#define CYREG_UDB_P0_U1_PLD_ORT1 0x400f30b2u +#define CYREG_UDB_P0_U1_PLD_ORT2 0x400f30b4u +#define CYREG_UDB_P0_U1_PLD_ORT3 0x400f30b6u +#define CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST 0x400f30b8u +#define CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB 0x400f30bau +#define CYREG_UDB_P0_U1_PLD_MC_SET_RESET 0x400f30bcu +#define CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS 0x400f30beu +#define CYREG_UDB_P0_U1_CFG0 0x400f30c0u +#define CYREG_UDB_P0_U1_CFG1 0x400f30c1u +#define CYREG_UDB_P0_U1_CFG2 0x400f30c2u +#define CYREG_UDB_P0_U1_CFG3 0x400f30c3u +#define CYREG_UDB_P0_U1_CFG4 0x400f30c4u +#define CYREG_UDB_P0_U1_CFG5 0x400f30c5u +#define CYREG_UDB_P0_U1_CFG6 0x400f30c6u +#define CYREG_UDB_P0_U1_CFG7 0x400f30c7u +#define CYREG_UDB_P0_U1_CFG8 0x400f30c8u +#define CYREG_UDB_P0_U1_CFG9 0x400f30c9u +#define CYREG_UDB_P0_U1_CFG10 0x400f30cau +#define CYREG_UDB_P0_U1_CFG11 0x400f30cbu +#define CYREG_UDB_P0_U1_CFG12 0x400f30ccu +#define CYREG_UDB_P0_U1_CFG13 0x400f30cdu +#define CYREG_UDB_P0_U1_CFG14 0x400f30ceu +#define CYREG_UDB_P0_U1_CFG15 0x400f30cfu +#define CYREG_UDB_P0_U1_CFG16 0x400f30d0u +#define CYREG_UDB_P0_U1_CFG17 0x400f30d1u +#define CYREG_UDB_P0_U1_CFG18 0x400f30d2u +#define CYREG_UDB_P0_U1_CFG19 0x400f30d3u +#define CYREG_UDB_P0_U1_CFG20 0x400f30d4u +#define CYREG_UDB_P0_U1_CFG21 0x400f30d5u +#define CYREG_UDB_P0_U1_CFG22 0x400f30d6u +#define CYREG_UDB_P0_U1_CFG23 0x400f30d7u +#define CYREG_UDB_P0_U1_CFG24 0x400f30d8u +#define CYREG_UDB_P0_U1_CFG25 0x400f30d9u +#define CYREG_UDB_P0_U1_CFG26 0x400f30dau +#define CYREG_UDB_P0_U1_CFG27 0x400f30dbu +#define CYREG_UDB_P0_U1_CFG28 0x400f30dcu +#define CYREG_UDB_P0_U1_CFG29 0x400f30ddu +#define CYREG_UDB_P0_U1_CFG30 0x400f30deu +#define CYREG_UDB_P0_U1_CFG31 0x400f30dfu +#define CYREG_UDB_P0_U1_DCFG0 0x400f30e0u +#define CYREG_UDB_P0_U1_DCFG1 0x400f30e2u +#define CYREG_UDB_P0_U1_DCFG2 0x400f30e4u +#define CYREG_UDB_P0_U1_DCFG3 0x400f30e6u +#define CYREG_UDB_P0_U1_DCFG4 0x400f30e8u +#define CYREG_UDB_P0_U1_DCFG5 0x400f30eau +#define CYREG_UDB_P0_U1_DCFG6 0x400f30ecu +#define CYREG_UDB_P0_U1_DCFG7 0x400f30eeu +#define CYDEV_UDB_P0_ROUTE_BASE 0x400f3100u +#define CYDEV_UDB_P0_ROUTE_SIZE 0x00000100u +#define CYREG_UDB_P0_ROUTE_HC0 0x400f3100u +#define CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE 0x00000008u +#define CYREG_UDB_P0_ROUTE_HC1 0x400f3101u +#define CYREG_UDB_P0_ROUTE_HC2 0x400f3102u +#define CYREG_UDB_P0_ROUTE_HC3 0x400f3103u +#define CYREG_UDB_P0_ROUTE_HC4 0x400f3104u +#define CYREG_UDB_P0_ROUTE_HC5 0x400f3105u +#define CYREG_UDB_P0_ROUTE_HC6 0x400f3106u +#define CYREG_UDB_P0_ROUTE_HC7 0x400f3107u +#define CYREG_UDB_P0_ROUTE_HC8 0x400f3108u +#define CYREG_UDB_P0_ROUTE_HC9 0x400f3109u +#define CYREG_UDB_P0_ROUTE_HC10 0x400f310au +#define CYREG_UDB_P0_ROUTE_HC11 0x400f310bu +#define CYREG_UDB_P0_ROUTE_HC12 0x400f310cu +#define CYREG_UDB_P0_ROUTE_HC13 0x400f310du +#define CYREG_UDB_P0_ROUTE_HC14 0x400f310eu +#define CYREG_UDB_P0_ROUTE_HC15 0x400f310fu +#define CYREG_UDB_P0_ROUTE_HC16 0x400f3110u +#define CYREG_UDB_P0_ROUTE_HC17 0x400f3111u +#define CYREG_UDB_P0_ROUTE_HC18 0x400f3112u +#define CYREG_UDB_P0_ROUTE_HC19 0x400f3113u +#define CYREG_UDB_P0_ROUTE_HC20 0x400f3114u +#define CYREG_UDB_P0_ROUTE_HC21 0x400f3115u +#define CYREG_UDB_P0_ROUTE_HC22 0x400f3116u +#define CYREG_UDB_P0_ROUTE_HC23 0x400f3117u +#define CYREG_UDB_P0_ROUTE_HC24 0x400f3118u +#define CYREG_UDB_P0_ROUTE_HC25 0x400f3119u +#define CYREG_UDB_P0_ROUTE_HC26 0x400f311au +#define CYREG_UDB_P0_ROUTE_HC27 0x400f311bu +#define CYREG_UDB_P0_ROUTE_HC28 0x400f311cu +#define CYREG_UDB_P0_ROUTE_HC29 0x400f311du +#define CYREG_UDB_P0_ROUTE_HC30 0x400f311eu +#define CYREG_UDB_P0_ROUTE_HC31 0x400f311fu +#define CYREG_UDB_P0_ROUTE_HC32 0x400f3120u +#define CYREG_UDB_P0_ROUTE_HC33 0x400f3121u +#define CYREG_UDB_P0_ROUTE_HC34 0x400f3122u +#define CYREG_UDB_P0_ROUTE_HC35 0x400f3123u +#define CYREG_UDB_P0_ROUTE_HC36 0x400f3124u +#define CYREG_UDB_P0_ROUTE_HC37 0x400f3125u +#define CYREG_UDB_P0_ROUTE_HC38 0x400f3126u +#define CYREG_UDB_P0_ROUTE_HC39 0x400f3127u +#define CYREG_UDB_P0_ROUTE_HC40 0x400f3128u +#define CYREG_UDB_P0_ROUTE_HC41 0x400f3129u +#define CYREG_UDB_P0_ROUTE_HC42 0x400f312au +#define CYREG_UDB_P0_ROUTE_HC43 0x400f312bu +#define CYREG_UDB_P0_ROUTE_HC44 0x400f312cu +#define CYREG_UDB_P0_ROUTE_HC45 0x400f312du +#define CYREG_UDB_P0_ROUTE_HC46 0x400f312eu +#define CYREG_UDB_P0_ROUTE_HC47 0x400f312fu +#define CYREG_UDB_P0_ROUTE_HC48 0x400f3130u +#define CYREG_UDB_P0_ROUTE_HC49 0x400f3131u +#define CYREG_UDB_P0_ROUTE_HC50 0x400f3132u +#define CYREG_UDB_P0_ROUTE_HC51 0x400f3133u +#define CYREG_UDB_P0_ROUTE_HC52 0x400f3134u +#define CYREG_UDB_P0_ROUTE_HC53 0x400f3135u +#define CYREG_UDB_P0_ROUTE_HC54 0x400f3136u +#define CYREG_UDB_P0_ROUTE_HC55 0x400f3137u +#define CYREG_UDB_P0_ROUTE_HC56 0x400f3138u +#define CYREG_UDB_P0_ROUTE_HC57 0x400f3139u +#define CYREG_UDB_P0_ROUTE_HC58 0x400f313au +#define CYREG_UDB_P0_ROUTE_HC59 0x400f313bu +#define CYREG_UDB_P0_ROUTE_HC60 0x400f313cu +#define CYREG_UDB_P0_ROUTE_HC61 0x400f313du +#define CYREG_UDB_P0_ROUTE_HC62 0x400f313eu +#define CYREG_UDB_P0_ROUTE_HC63 0x400f313fu +#define CYREG_UDB_P0_ROUTE_HC64 0x400f3140u +#define CYREG_UDB_P0_ROUTE_HC65 0x400f3141u +#define CYREG_UDB_P0_ROUTE_HC66 0x400f3142u +#define CYREG_UDB_P0_ROUTE_HC67 0x400f3143u +#define CYREG_UDB_P0_ROUTE_HC68 0x400f3144u +#define CYREG_UDB_P0_ROUTE_HC69 0x400f3145u +#define CYREG_UDB_P0_ROUTE_HC70 0x400f3146u +#define CYREG_UDB_P0_ROUTE_HC71 0x400f3147u +#define CYREG_UDB_P0_ROUTE_HC72 0x400f3148u +#define CYREG_UDB_P0_ROUTE_HC73 0x400f3149u +#define CYREG_UDB_P0_ROUTE_HC74 0x400f314au +#define CYREG_UDB_P0_ROUTE_HC75 0x400f314bu +#define CYREG_UDB_P0_ROUTE_HC76 0x400f314cu +#define CYREG_UDB_P0_ROUTE_HC77 0x400f314du +#define CYREG_UDB_P0_ROUTE_HC78 0x400f314eu +#define CYREG_UDB_P0_ROUTE_HC79 0x400f314fu +#define CYREG_UDB_P0_ROUTE_HC80 0x400f3150u +#define CYREG_UDB_P0_ROUTE_HC81 0x400f3151u +#define CYREG_UDB_P0_ROUTE_HC82 0x400f3152u +#define CYREG_UDB_P0_ROUTE_HC83 0x400f3153u +#define CYREG_UDB_P0_ROUTE_HC84 0x400f3154u +#define CYREG_UDB_P0_ROUTE_HC85 0x400f3155u +#define CYREG_UDB_P0_ROUTE_HC86 0x400f3156u +#define CYREG_UDB_P0_ROUTE_HC87 0x400f3157u +#define CYREG_UDB_P0_ROUTE_HC88 0x400f3158u +#define CYREG_UDB_P0_ROUTE_HC89 0x400f3159u +#define CYREG_UDB_P0_ROUTE_HC90 0x400f315au +#define CYREG_UDB_P0_ROUTE_HC91 0x400f315bu +#define CYREG_UDB_P0_ROUTE_HC92 0x400f315cu +#define CYREG_UDB_P0_ROUTE_HC93 0x400f315du +#define CYREG_UDB_P0_ROUTE_HC94 0x400f315eu +#define CYREG_UDB_P0_ROUTE_HC95 0x400f315fu +#define CYREG_UDB_P0_ROUTE_HC96 0x400f3160u +#define CYREG_UDB_P0_ROUTE_HC97 0x400f3161u +#define CYREG_UDB_P0_ROUTE_HC98 0x400f3162u +#define CYREG_UDB_P0_ROUTE_HC99 0x400f3163u +#define CYREG_UDB_P0_ROUTE_HC100 0x400f3164u +#define CYREG_UDB_P0_ROUTE_HC101 0x400f3165u +#define CYREG_UDB_P0_ROUTE_HC102 0x400f3166u +#define CYREG_UDB_P0_ROUTE_HC103 0x400f3167u +#define CYREG_UDB_P0_ROUTE_HC104 0x400f3168u +#define CYREG_UDB_P0_ROUTE_HC105 0x400f3169u +#define CYREG_UDB_P0_ROUTE_HC106 0x400f316au +#define CYREG_UDB_P0_ROUTE_HC107 0x400f316bu +#define CYREG_UDB_P0_ROUTE_HC108 0x400f316cu +#define CYREG_UDB_P0_ROUTE_HC109 0x400f316du +#define CYREG_UDB_P0_ROUTE_HC110 0x400f316eu +#define CYREG_UDB_P0_ROUTE_HC111 0x400f316fu +#define CYREG_UDB_P0_ROUTE_HC112 0x400f3170u +#define CYREG_UDB_P0_ROUTE_HC113 0x400f3171u +#define CYREG_UDB_P0_ROUTE_HC114 0x400f3172u +#define CYREG_UDB_P0_ROUTE_HC115 0x400f3173u +#define CYREG_UDB_P0_ROUTE_HC116 0x400f3174u +#define CYREG_UDB_P0_ROUTE_HC117 0x400f3175u +#define CYREG_UDB_P0_ROUTE_HC118 0x400f3176u +#define CYREG_UDB_P0_ROUTE_HC119 0x400f3177u +#define CYREG_UDB_P0_ROUTE_HC120 0x400f3178u +#define CYREG_UDB_P0_ROUTE_HC121 0x400f3179u +#define CYREG_UDB_P0_ROUTE_HC122 0x400f317au +#define CYREG_UDB_P0_ROUTE_HC123 0x400f317bu +#define CYREG_UDB_P0_ROUTE_HC124 0x400f317cu +#define CYREG_UDB_P0_ROUTE_HC125 0x400f317du +#define CYREG_UDB_P0_ROUTE_HC126 0x400f317eu +#define CYREG_UDB_P0_ROUTE_HC127 0x400f317fu +#define CYREG_UDB_P0_ROUTE_HV_L0 0x400f3180u +#define CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE 0x00000008u +#define CYREG_UDB_P0_ROUTE_HV_L1 0x400f3181u +#define CYREG_UDB_P0_ROUTE_HV_L2 0x400f3182u +#define CYREG_UDB_P0_ROUTE_HV_L3 0x400f3183u +#define CYREG_UDB_P0_ROUTE_HV_L4 0x400f3184u +#define CYREG_UDB_P0_ROUTE_HV_L5 0x400f3185u +#define CYREG_UDB_P0_ROUTE_HV_L6 0x400f3186u +#define CYREG_UDB_P0_ROUTE_HV_L7 0x400f3187u +#define CYREG_UDB_P0_ROUTE_HV_L8 0x400f3188u +#define CYREG_UDB_P0_ROUTE_HV_L9 0x400f3189u +#define CYREG_UDB_P0_ROUTE_HV_L10 0x400f318au +#define CYREG_UDB_P0_ROUTE_HV_L11 0x400f318bu +#define CYREG_UDB_P0_ROUTE_HV_L12 0x400f318cu +#define CYREG_UDB_P0_ROUTE_HV_L13 0x400f318du +#define CYREG_UDB_P0_ROUTE_HV_L14 0x400f318eu +#define CYREG_UDB_P0_ROUTE_HV_L15 0x400f318fu +#define CYREG_UDB_P0_ROUTE_HS0 0x400f3190u +#define CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE 0x00000008u +#define CYREG_UDB_P0_ROUTE_HS1 0x400f3191u +#define CYREG_UDB_P0_ROUTE_HS2 0x400f3192u +#define CYREG_UDB_P0_ROUTE_HS3 0x400f3193u +#define CYREG_UDB_P0_ROUTE_HS4 0x400f3194u +#define CYREG_UDB_P0_ROUTE_HS5 0x400f3195u +#define CYREG_UDB_P0_ROUTE_HS6 0x400f3196u +#define CYREG_UDB_P0_ROUTE_HS7 0x400f3197u +#define CYREG_UDB_P0_ROUTE_HS8 0x400f3198u +#define CYREG_UDB_P0_ROUTE_HS9 0x400f3199u +#define CYREG_UDB_P0_ROUTE_HS10 0x400f319au +#define CYREG_UDB_P0_ROUTE_HS11 0x400f319bu +#define CYREG_UDB_P0_ROUTE_HS12 0x400f319cu +#define CYREG_UDB_P0_ROUTE_HS13 0x400f319du +#define CYREG_UDB_P0_ROUTE_HS14 0x400f319eu +#define CYREG_UDB_P0_ROUTE_HS15 0x400f319fu +#define CYREG_UDB_P0_ROUTE_HS16 0x400f31a0u +#define CYREG_UDB_P0_ROUTE_HS17 0x400f31a1u +#define CYREG_UDB_P0_ROUTE_HS18 0x400f31a2u +#define CYREG_UDB_P0_ROUTE_HS19 0x400f31a3u +#define CYREG_UDB_P0_ROUTE_HS20 0x400f31a4u +#define CYREG_UDB_P0_ROUTE_HS21 0x400f31a5u +#define CYREG_UDB_P0_ROUTE_HS22 0x400f31a6u +#define CYREG_UDB_P0_ROUTE_HS23 0x400f31a7u +#define CYREG_UDB_P0_ROUTE_HV_R0 0x400f31a8u +#define CYREG_UDB_P0_ROUTE_HV_R1 0x400f31a9u +#define CYREG_UDB_P0_ROUTE_HV_R2 0x400f31aau +#define CYREG_UDB_P0_ROUTE_HV_R3 0x400f31abu +#define CYREG_UDB_P0_ROUTE_HV_R4 0x400f31acu +#define CYREG_UDB_P0_ROUTE_HV_R5 0x400f31adu +#define CYREG_UDB_P0_ROUTE_HV_R6 0x400f31aeu +#define CYREG_UDB_P0_ROUTE_HV_R7 0x400f31afu +#define CYREG_UDB_P0_ROUTE_HV_R8 0x400f31b0u +#define CYREG_UDB_P0_ROUTE_HV_R9 0x400f31b1u +#define CYREG_UDB_P0_ROUTE_HV_R10 0x400f31b2u +#define CYREG_UDB_P0_ROUTE_HV_R11 0x400f31b3u +#define CYREG_UDB_P0_ROUTE_HV_R12 0x400f31b4u +#define CYREG_UDB_P0_ROUTE_HV_R13 0x400f31b5u +#define CYREG_UDB_P0_ROUTE_HV_R14 0x400f31b6u +#define CYREG_UDB_P0_ROUTE_HV_R15 0x400f31b7u +#define CYREG_UDB_P0_ROUTE_PLD0IN0 0x400f31c0u +#define CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_PI_TOP__SIZE 0x00000004u +#define CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_P_ROUTE_PI_BOT__SIZE 0x00000004u +#define CYREG_UDB_P0_ROUTE_PLD0IN1 0x400f31c2u +#define CYREG_UDB_P0_ROUTE_PLD0IN2 0x400f31c4u +#define CYREG_UDB_P0_ROUTE_PLD1IN0 0x400f31cau +#define CYREG_UDB_P0_ROUTE_PLD1IN1 0x400f31ccu +#define CYREG_UDB_P0_ROUTE_PLD1IN2 0x400f31ceu +#define CYREG_UDB_P0_ROUTE_DPIN0 0x400f31d0u +#define CYREG_UDB_P0_ROUTE_DPIN1 0x400f31d2u +#define CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET 0x00000002u +#define CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE 0x00000002u +#define CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET 0x00000004u +#define CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE 0x00000002u +#define CYREG_UDB_P0_ROUTE_SCIN 0x400f31d6u +#define CYREG_UDB_P0_ROUTE_SCIOIN 0x400f31d8u +#define CYREG_UDB_P0_ROUTE_RCIN 0x400f31deu +#define CYREG_UDB_P0_ROUTE_VS0 0x400f31e0u +#define CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_VS_TOP__SIZE 0x00000004u +#define CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_P_ROUTE_VS_BOT__SIZE 0x00000004u +#define CYREG_UDB_P0_ROUTE_VS1 0x400f31e2u +#define CYREG_UDB_P0_ROUTE_VS2 0x400f31e4u +#define CYREG_UDB_P0_ROUTE_VS3 0x400f31e6u +#define CYREG_UDB_P0_ROUTE_VS4 0x400f31e8u +#define CYREG_UDB_P0_ROUTE_VS5 0x400f31eau +#define CYREG_UDB_P0_ROUTE_VS6 0x400f31ecu +#define CYREG_UDB_P0_ROUTE_VS7 0x400f31eeu +#define CYDEV_UDB_P1_BASE 0x400f3200u +#define CYDEV_UDB_P1_SIZE 0x00000200u +#define CYDEV_UDB_P1_U0_BASE 0x400f3200u +#define CYDEV_UDB_P1_U0_SIZE 0x00000080u +#define CYREG_UDB_P1_U0_PLD_IT0 0x400f3200u +#define CYREG_UDB_P1_U0_PLD_IT1 0x400f3204u +#define CYREG_UDB_P1_U0_PLD_IT2 0x400f3208u +#define CYREG_UDB_P1_U0_PLD_IT3 0x400f320cu +#define CYREG_UDB_P1_U0_PLD_IT4 0x400f3210u +#define CYREG_UDB_P1_U0_PLD_IT5 0x400f3214u +#define CYREG_UDB_P1_U0_PLD_IT6 0x400f3218u +#define CYREG_UDB_P1_U0_PLD_IT7 0x400f321cu +#define CYREG_UDB_P1_U0_PLD_IT8 0x400f3220u +#define CYREG_UDB_P1_U0_PLD_IT9 0x400f3224u +#define CYREG_UDB_P1_U0_PLD_IT10 0x400f3228u +#define CYREG_UDB_P1_U0_PLD_IT11 0x400f322cu +#define CYREG_UDB_P1_U0_PLD_ORT0 0x400f3230u +#define CYREG_UDB_P1_U0_PLD_ORT1 0x400f3232u +#define CYREG_UDB_P1_U0_PLD_ORT2 0x400f3234u +#define CYREG_UDB_P1_U0_PLD_ORT3 0x400f3236u +#define CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST 0x400f3238u +#define CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB 0x400f323au +#define CYREG_UDB_P1_U0_PLD_MC_SET_RESET 0x400f323cu +#define CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS 0x400f323eu +#define CYREG_UDB_P1_U0_CFG0 0x400f3240u +#define CYREG_UDB_P1_U0_CFG1 0x400f3241u +#define CYREG_UDB_P1_U0_CFG2 0x400f3242u +#define CYREG_UDB_P1_U0_CFG3 0x400f3243u +#define CYREG_UDB_P1_U0_CFG4 0x400f3244u +#define CYREG_UDB_P1_U0_CFG5 0x400f3245u +#define CYREG_UDB_P1_U0_CFG6 0x400f3246u +#define CYREG_UDB_P1_U0_CFG7 0x400f3247u +#define CYREG_UDB_P1_U0_CFG8 0x400f3248u +#define CYREG_UDB_P1_U0_CFG9 0x400f3249u +#define CYREG_UDB_P1_U0_CFG10 0x400f324au +#define CYREG_UDB_P1_U0_CFG11 0x400f324bu +#define CYREG_UDB_P1_U0_CFG12 0x400f324cu +#define CYREG_UDB_P1_U0_CFG13 0x400f324du +#define CYREG_UDB_P1_U0_CFG14 0x400f324eu +#define CYREG_UDB_P1_U0_CFG15 0x400f324fu +#define CYREG_UDB_P1_U0_CFG16 0x400f3250u +#define CYREG_UDB_P1_U0_CFG17 0x400f3251u +#define CYREG_UDB_P1_U0_CFG18 0x400f3252u +#define CYREG_UDB_P1_U0_CFG19 0x400f3253u +#define CYREG_UDB_P1_U0_CFG20 0x400f3254u +#define CYREG_UDB_P1_U0_CFG21 0x400f3255u +#define CYREG_UDB_P1_U0_CFG22 0x400f3256u +#define CYREG_UDB_P1_U0_CFG23 0x400f3257u +#define CYREG_UDB_P1_U0_CFG24 0x400f3258u +#define CYREG_UDB_P1_U0_CFG25 0x400f3259u +#define CYREG_UDB_P1_U0_CFG26 0x400f325au +#define CYREG_UDB_P1_U0_CFG27 0x400f325bu +#define CYREG_UDB_P1_U0_CFG28 0x400f325cu +#define CYREG_UDB_P1_U0_CFG29 0x400f325du +#define CYREG_UDB_P1_U0_CFG30 0x400f325eu +#define CYREG_UDB_P1_U0_CFG31 0x400f325fu +#define CYREG_UDB_P1_U0_DCFG0 0x400f3260u +#define CYREG_UDB_P1_U0_DCFG1 0x400f3262u +#define CYREG_UDB_P1_U0_DCFG2 0x400f3264u +#define CYREG_UDB_P1_U0_DCFG3 0x400f3266u +#define CYREG_UDB_P1_U0_DCFG4 0x400f3268u +#define CYREG_UDB_P1_U0_DCFG5 0x400f326au +#define CYREG_UDB_P1_U0_DCFG6 0x400f326cu +#define CYREG_UDB_P1_U0_DCFG7 0x400f326eu +#define CYDEV_UDB_P1_U1_BASE 0x400f3280u +#define CYDEV_UDB_P1_U1_SIZE 0x00000080u +#define CYREG_UDB_P1_U1_PLD_IT0 0x400f3280u +#define CYREG_UDB_P1_U1_PLD_IT1 0x400f3284u +#define CYREG_UDB_P1_U1_PLD_IT2 0x400f3288u +#define CYREG_UDB_P1_U1_PLD_IT3 0x400f328cu +#define CYREG_UDB_P1_U1_PLD_IT4 0x400f3290u +#define CYREG_UDB_P1_U1_PLD_IT5 0x400f3294u +#define CYREG_UDB_P1_U1_PLD_IT6 0x400f3298u +#define CYREG_UDB_P1_U1_PLD_IT7 0x400f329cu +#define CYREG_UDB_P1_U1_PLD_IT8 0x400f32a0u +#define CYREG_UDB_P1_U1_PLD_IT9 0x400f32a4u +#define CYREG_UDB_P1_U1_PLD_IT10 0x400f32a8u +#define CYREG_UDB_P1_U1_PLD_IT11 0x400f32acu +#define CYREG_UDB_P1_U1_PLD_ORT0 0x400f32b0u +#define CYREG_UDB_P1_U1_PLD_ORT1 0x400f32b2u +#define CYREG_UDB_P1_U1_PLD_ORT2 0x400f32b4u +#define CYREG_UDB_P1_U1_PLD_ORT3 0x400f32b6u +#define CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST 0x400f32b8u +#define CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB 0x400f32bau +#define CYREG_UDB_P1_U1_PLD_MC_SET_RESET 0x400f32bcu +#define CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS 0x400f32beu +#define CYREG_UDB_P1_U1_CFG0 0x400f32c0u +#define CYREG_UDB_P1_U1_CFG1 0x400f32c1u +#define CYREG_UDB_P1_U1_CFG2 0x400f32c2u +#define CYREG_UDB_P1_U1_CFG3 0x400f32c3u +#define CYREG_UDB_P1_U1_CFG4 0x400f32c4u +#define CYREG_UDB_P1_U1_CFG5 0x400f32c5u +#define CYREG_UDB_P1_U1_CFG6 0x400f32c6u +#define CYREG_UDB_P1_U1_CFG7 0x400f32c7u +#define CYREG_UDB_P1_U1_CFG8 0x400f32c8u +#define CYREG_UDB_P1_U1_CFG9 0x400f32c9u +#define CYREG_UDB_P1_U1_CFG10 0x400f32cau +#define CYREG_UDB_P1_U1_CFG11 0x400f32cbu +#define CYREG_UDB_P1_U1_CFG12 0x400f32ccu +#define CYREG_UDB_P1_U1_CFG13 0x400f32cdu +#define CYREG_UDB_P1_U1_CFG14 0x400f32ceu +#define CYREG_UDB_P1_U1_CFG15 0x400f32cfu +#define CYREG_UDB_P1_U1_CFG16 0x400f32d0u +#define CYREG_UDB_P1_U1_CFG17 0x400f32d1u +#define CYREG_UDB_P1_U1_CFG18 0x400f32d2u +#define CYREG_UDB_P1_U1_CFG19 0x400f32d3u +#define CYREG_UDB_P1_U1_CFG20 0x400f32d4u +#define CYREG_UDB_P1_U1_CFG21 0x400f32d5u +#define CYREG_UDB_P1_U1_CFG22 0x400f32d6u +#define CYREG_UDB_P1_U1_CFG23 0x400f32d7u +#define CYREG_UDB_P1_U1_CFG24 0x400f32d8u +#define CYREG_UDB_P1_U1_CFG25 0x400f32d9u +#define CYREG_UDB_P1_U1_CFG26 0x400f32dau +#define CYREG_UDB_P1_U1_CFG27 0x400f32dbu +#define CYREG_UDB_P1_U1_CFG28 0x400f32dcu +#define CYREG_UDB_P1_U1_CFG29 0x400f32ddu +#define CYREG_UDB_P1_U1_CFG30 0x400f32deu +#define CYREG_UDB_P1_U1_CFG31 0x400f32dfu +#define CYREG_UDB_P1_U1_DCFG0 0x400f32e0u +#define CYREG_UDB_P1_U1_DCFG1 0x400f32e2u +#define CYREG_UDB_P1_U1_DCFG2 0x400f32e4u +#define CYREG_UDB_P1_U1_DCFG3 0x400f32e6u +#define CYREG_UDB_P1_U1_DCFG4 0x400f32e8u +#define CYREG_UDB_P1_U1_DCFG5 0x400f32eau +#define CYREG_UDB_P1_U1_DCFG6 0x400f32ecu +#define CYREG_UDB_P1_U1_DCFG7 0x400f32eeu +#define CYDEV_UDB_P1_ROUTE_BASE 0x400f3300u +#define CYDEV_UDB_P1_ROUTE_SIZE 0x00000100u +#define CYREG_UDB_P1_ROUTE_HC0 0x400f3300u +#define CYREG_UDB_P1_ROUTE_HC1 0x400f3301u +#define CYREG_UDB_P1_ROUTE_HC2 0x400f3302u +#define CYREG_UDB_P1_ROUTE_HC3 0x400f3303u +#define CYREG_UDB_P1_ROUTE_HC4 0x400f3304u +#define CYREG_UDB_P1_ROUTE_HC5 0x400f3305u +#define CYREG_UDB_P1_ROUTE_HC6 0x400f3306u +#define CYREG_UDB_P1_ROUTE_HC7 0x400f3307u +#define CYREG_UDB_P1_ROUTE_HC8 0x400f3308u +#define CYREG_UDB_P1_ROUTE_HC9 0x400f3309u +#define CYREG_UDB_P1_ROUTE_HC10 0x400f330au +#define CYREG_UDB_P1_ROUTE_HC11 0x400f330bu +#define CYREG_UDB_P1_ROUTE_HC12 0x400f330cu +#define CYREG_UDB_P1_ROUTE_HC13 0x400f330du +#define CYREG_UDB_P1_ROUTE_HC14 0x400f330eu +#define CYREG_UDB_P1_ROUTE_HC15 0x400f330fu +#define CYREG_UDB_P1_ROUTE_HC16 0x400f3310u +#define CYREG_UDB_P1_ROUTE_HC17 0x400f3311u +#define CYREG_UDB_P1_ROUTE_HC18 0x400f3312u +#define CYREG_UDB_P1_ROUTE_HC19 0x400f3313u +#define CYREG_UDB_P1_ROUTE_HC20 0x400f3314u +#define CYREG_UDB_P1_ROUTE_HC21 0x400f3315u +#define CYREG_UDB_P1_ROUTE_HC22 0x400f3316u +#define CYREG_UDB_P1_ROUTE_HC23 0x400f3317u +#define CYREG_UDB_P1_ROUTE_HC24 0x400f3318u +#define CYREG_UDB_P1_ROUTE_HC25 0x400f3319u +#define CYREG_UDB_P1_ROUTE_HC26 0x400f331au +#define CYREG_UDB_P1_ROUTE_HC27 0x400f331bu +#define CYREG_UDB_P1_ROUTE_HC28 0x400f331cu +#define CYREG_UDB_P1_ROUTE_HC29 0x400f331du +#define CYREG_UDB_P1_ROUTE_HC30 0x400f331eu +#define CYREG_UDB_P1_ROUTE_HC31 0x400f331fu +#define CYREG_UDB_P1_ROUTE_HC32 0x400f3320u +#define CYREG_UDB_P1_ROUTE_HC33 0x400f3321u +#define CYREG_UDB_P1_ROUTE_HC34 0x400f3322u +#define CYREG_UDB_P1_ROUTE_HC35 0x400f3323u +#define CYREG_UDB_P1_ROUTE_HC36 0x400f3324u +#define CYREG_UDB_P1_ROUTE_HC37 0x400f3325u +#define CYREG_UDB_P1_ROUTE_HC38 0x400f3326u +#define CYREG_UDB_P1_ROUTE_HC39 0x400f3327u +#define CYREG_UDB_P1_ROUTE_HC40 0x400f3328u +#define CYREG_UDB_P1_ROUTE_HC41 0x400f3329u +#define CYREG_UDB_P1_ROUTE_HC42 0x400f332au +#define CYREG_UDB_P1_ROUTE_HC43 0x400f332bu +#define CYREG_UDB_P1_ROUTE_HC44 0x400f332cu +#define CYREG_UDB_P1_ROUTE_HC45 0x400f332du +#define CYREG_UDB_P1_ROUTE_HC46 0x400f332eu +#define CYREG_UDB_P1_ROUTE_HC47 0x400f332fu +#define CYREG_UDB_P1_ROUTE_HC48 0x400f3330u +#define CYREG_UDB_P1_ROUTE_HC49 0x400f3331u +#define CYREG_UDB_P1_ROUTE_HC50 0x400f3332u +#define CYREG_UDB_P1_ROUTE_HC51 0x400f3333u +#define CYREG_UDB_P1_ROUTE_HC52 0x400f3334u +#define CYREG_UDB_P1_ROUTE_HC53 0x400f3335u +#define CYREG_UDB_P1_ROUTE_HC54 0x400f3336u +#define CYREG_UDB_P1_ROUTE_HC55 0x400f3337u +#define CYREG_UDB_P1_ROUTE_HC56 0x400f3338u +#define CYREG_UDB_P1_ROUTE_HC57 0x400f3339u +#define CYREG_UDB_P1_ROUTE_HC58 0x400f333au +#define CYREG_UDB_P1_ROUTE_HC59 0x400f333bu +#define CYREG_UDB_P1_ROUTE_HC60 0x400f333cu +#define CYREG_UDB_P1_ROUTE_HC61 0x400f333du +#define CYREG_UDB_P1_ROUTE_HC62 0x400f333eu +#define CYREG_UDB_P1_ROUTE_HC63 0x400f333fu +#define CYREG_UDB_P1_ROUTE_HC64 0x400f3340u +#define CYREG_UDB_P1_ROUTE_HC65 0x400f3341u +#define CYREG_UDB_P1_ROUTE_HC66 0x400f3342u +#define CYREG_UDB_P1_ROUTE_HC67 0x400f3343u +#define CYREG_UDB_P1_ROUTE_HC68 0x400f3344u +#define CYREG_UDB_P1_ROUTE_HC69 0x400f3345u +#define CYREG_UDB_P1_ROUTE_HC70 0x400f3346u +#define CYREG_UDB_P1_ROUTE_HC71 0x400f3347u +#define CYREG_UDB_P1_ROUTE_HC72 0x400f3348u +#define CYREG_UDB_P1_ROUTE_HC73 0x400f3349u +#define CYREG_UDB_P1_ROUTE_HC74 0x400f334au +#define CYREG_UDB_P1_ROUTE_HC75 0x400f334bu +#define CYREG_UDB_P1_ROUTE_HC76 0x400f334cu +#define CYREG_UDB_P1_ROUTE_HC77 0x400f334du +#define CYREG_UDB_P1_ROUTE_HC78 0x400f334eu +#define CYREG_UDB_P1_ROUTE_HC79 0x400f334fu +#define CYREG_UDB_P1_ROUTE_HC80 0x400f3350u +#define CYREG_UDB_P1_ROUTE_HC81 0x400f3351u +#define CYREG_UDB_P1_ROUTE_HC82 0x400f3352u +#define CYREG_UDB_P1_ROUTE_HC83 0x400f3353u +#define CYREG_UDB_P1_ROUTE_HC84 0x400f3354u +#define CYREG_UDB_P1_ROUTE_HC85 0x400f3355u +#define CYREG_UDB_P1_ROUTE_HC86 0x400f3356u +#define CYREG_UDB_P1_ROUTE_HC87 0x400f3357u +#define CYREG_UDB_P1_ROUTE_HC88 0x400f3358u +#define CYREG_UDB_P1_ROUTE_HC89 0x400f3359u +#define CYREG_UDB_P1_ROUTE_HC90 0x400f335au +#define CYREG_UDB_P1_ROUTE_HC91 0x400f335bu +#define CYREG_UDB_P1_ROUTE_HC92 0x400f335cu +#define CYREG_UDB_P1_ROUTE_HC93 0x400f335du +#define CYREG_UDB_P1_ROUTE_HC94 0x400f335eu +#define CYREG_UDB_P1_ROUTE_HC95 0x400f335fu +#define CYREG_UDB_P1_ROUTE_HC96 0x400f3360u +#define CYREG_UDB_P1_ROUTE_HC97 0x400f3361u +#define CYREG_UDB_P1_ROUTE_HC98 0x400f3362u +#define CYREG_UDB_P1_ROUTE_HC99 0x400f3363u +#define CYREG_UDB_P1_ROUTE_HC100 0x400f3364u +#define CYREG_UDB_P1_ROUTE_HC101 0x400f3365u +#define CYREG_UDB_P1_ROUTE_HC102 0x400f3366u +#define CYREG_UDB_P1_ROUTE_HC103 0x400f3367u +#define CYREG_UDB_P1_ROUTE_HC104 0x400f3368u +#define CYREG_UDB_P1_ROUTE_HC105 0x400f3369u +#define CYREG_UDB_P1_ROUTE_HC106 0x400f336au +#define CYREG_UDB_P1_ROUTE_HC107 0x400f336bu +#define CYREG_UDB_P1_ROUTE_HC108 0x400f336cu +#define CYREG_UDB_P1_ROUTE_HC109 0x400f336du +#define CYREG_UDB_P1_ROUTE_HC110 0x400f336eu +#define CYREG_UDB_P1_ROUTE_HC111 0x400f336fu +#define CYREG_UDB_P1_ROUTE_HC112 0x400f3370u +#define CYREG_UDB_P1_ROUTE_HC113 0x400f3371u +#define CYREG_UDB_P1_ROUTE_HC114 0x400f3372u +#define CYREG_UDB_P1_ROUTE_HC115 0x400f3373u +#define CYREG_UDB_P1_ROUTE_HC116 0x400f3374u +#define CYREG_UDB_P1_ROUTE_HC117 0x400f3375u +#define CYREG_UDB_P1_ROUTE_HC118 0x400f3376u +#define CYREG_UDB_P1_ROUTE_HC119 0x400f3377u +#define CYREG_UDB_P1_ROUTE_HC120 0x400f3378u +#define CYREG_UDB_P1_ROUTE_HC121 0x400f3379u +#define CYREG_UDB_P1_ROUTE_HC122 0x400f337au +#define CYREG_UDB_P1_ROUTE_HC123 0x400f337bu +#define CYREG_UDB_P1_ROUTE_HC124 0x400f337cu +#define CYREG_UDB_P1_ROUTE_HC125 0x400f337du +#define CYREG_UDB_P1_ROUTE_HC126 0x400f337eu +#define CYREG_UDB_P1_ROUTE_HC127 0x400f337fu +#define CYREG_UDB_P1_ROUTE_HV_L0 0x400f3380u +#define CYREG_UDB_P1_ROUTE_HV_L1 0x400f3381u +#define CYREG_UDB_P1_ROUTE_HV_L2 0x400f3382u +#define CYREG_UDB_P1_ROUTE_HV_L3 0x400f3383u +#define CYREG_UDB_P1_ROUTE_HV_L4 0x400f3384u +#define CYREG_UDB_P1_ROUTE_HV_L5 0x400f3385u +#define CYREG_UDB_P1_ROUTE_HV_L6 0x400f3386u +#define CYREG_UDB_P1_ROUTE_HV_L7 0x400f3387u +#define CYREG_UDB_P1_ROUTE_HV_L8 0x400f3388u +#define CYREG_UDB_P1_ROUTE_HV_L9 0x400f3389u +#define CYREG_UDB_P1_ROUTE_HV_L10 0x400f338au +#define CYREG_UDB_P1_ROUTE_HV_L11 0x400f338bu +#define CYREG_UDB_P1_ROUTE_HV_L12 0x400f338cu +#define CYREG_UDB_P1_ROUTE_HV_L13 0x400f338du +#define CYREG_UDB_P1_ROUTE_HV_L14 0x400f338eu +#define CYREG_UDB_P1_ROUTE_HV_L15 0x400f338fu +#define CYREG_UDB_P1_ROUTE_HS0 0x400f3390u +#define CYREG_UDB_P1_ROUTE_HS1 0x400f3391u +#define CYREG_UDB_P1_ROUTE_HS2 0x400f3392u +#define CYREG_UDB_P1_ROUTE_HS3 0x400f3393u +#define CYREG_UDB_P1_ROUTE_HS4 0x400f3394u +#define CYREG_UDB_P1_ROUTE_HS5 0x400f3395u +#define CYREG_UDB_P1_ROUTE_HS6 0x400f3396u +#define CYREG_UDB_P1_ROUTE_HS7 0x400f3397u +#define CYREG_UDB_P1_ROUTE_HS8 0x400f3398u +#define CYREG_UDB_P1_ROUTE_HS9 0x400f3399u +#define CYREG_UDB_P1_ROUTE_HS10 0x400f339au +#define CYREG_UDB_P1_ROUTE_HS11 0x400f339bu +#define CYREG_UDB_P1_ROUTE_HS12 0x400f339cu +#define CYREG_UDB_P1_ROUTE_HS13 0x400f339du +#define CYREG_UDB_P1_ROUTE_HS14 0x400f339eu +#define CYREG_UDB_P1_ROUTE_HS15 0x400f339fu +#define CYREG_UDB_P1_ROUTE_HS16 0x400f33a0u +#define CYREG_UDB_P1_ROUTE_HS17 0x400f33a1u +#define CYREG_UDB_P1_ROUTE_HS18 0x400f33a2u +#define CYREG_UDB_P1_ROUTE_HS19 0x400f33a3u +#define CYREG_UDB_P1_ROUTE_HS20 0x400f33a4u +#define CYREG_UDB_P1_ROUTE_HS21 0x400f33a5u +#define CYREG_UDB_P1_ROUTE_HS22 0x400f33a6u +#define CYREG_UDB_P1_ROUTE_HS23 0x400f33a7u +#define CYREG_UDB_P1_ROUTE_HV_R0 0x400f33a8u +#define CYREG_UDB_P1_ROUTE_HV_R1 0x400f33a9u +#define CYREG_UDB_P1_ROUTE_HV_R2 0x400f33aau +#define CYREG_UDB_P1_ROUTE_HV_R3 0x400f33abu +#define CYREG_UDB_P1_ROUTE_HV_R4 0x400f33acu +#define CYREG_UDB_P1_ROUTE_HV_R5 0x400f33adu +#define CYREG_UDB_P1_ROUTE_HV_R6 0x400f33aeu +#define CYREG_UDB_P1_ROUTE_HV_R7 0x400f33afu +#define CYREG_UDB_P1_ROUTE_HV_R8 0x400f33b0u +#define CYREG_UDB_P1_ROUTE_HV_R9 0x400f33b1u +#define CYREG_UDB_P1_ROUTE_HV_R10 0x400f33b2u +#define CYREG_UDB_P1_ROUTE_HV_R11 0x400f33b3u +#define CYREG_UDB_P1_ROUTE_HV_R12 0x400f33b4u +#define CYREG_UDB_P1_ROUTE_HV_R13 0x400f33b5u +#define CYREG_UDB_P1_ROUTE_HV_R14 0x400f33b6u +#define CYREG_UDB_P1_ROUTE_HV_R15 0x400f33b7u +#define CYREG_UDB_P1_ROUTE_PLD0IN0 0x400f33c0u +#define CYREG_UDB_P1_ROUTE_PLD0IN1 0x400f33c2u +#define CYREG_UDB_P1_ROUTE_PLD0IN2 0x400f33c4u +#define CYREG_UDB_P1_ROUTE_PLD1IN0 0x400f33cau +#define CYREG_UDB_P1_ROUTE_PLD1IN1 0x400f33ccu +#define CYREG_UDB_P1_ROUTE_PLD1IN2 0x400f33ceu +#define CYREG_UDB_P1_ROUTE_DPIN0 0x400f33d0u +#define CYREG_UDB_P1_ROUTE_DPIN1 0x400f33d2u +#define CYREG_UDB_P1_ROUTE_SCIN 0x400f33d6u +#define CYREG_UDB_P1_ROUTE_SCIOIN 0x400f33d8u +#define CYREG_UDB_P1_ROUTE_RCIN 0x400f33deu +#define CYREG_UDB_P1_ROUTE_VS0 0x400f33e0u +#define CYREG_UDB_P1_ROUTE_VS1 0x400f33e2u +#define CYREG_UDB_P1_ROUTE_VS2 0x400f33e4u +#define CYREG_UDB_P1_ROUTE_VS3 0x400f33e6u +#define CYREG_UDB_P1_ROUTE_VS4 0x400f33e8u +#define CYREG_UDB_P1_ROUTE_VS5 0x400f33eau +#define CYREG_UDB_P1_ROUTE_VS6 0x400f33ecu +#define CYREG_UDB_P1_ROUTE_VS7 0x400f33eeu +#define CYDEV_UDB_DSI0_BASE 0x400f4000u +#define CYDEV_UDB_DSI0_SIZE 0x00000100u +#define CYREG_UDB_DSI0_HC0 0x400f4000u +#define CYFLD_UDB_DSI_HC_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_HC_BYTE__SIZE 0x00000008u +#define CYREG_UDB_DSI0_HC1 0x400f4001u +#define CYREG_UDB_DSI0_HC2 0x400f4002u +#define CYREG_UDB_DSI0_HC3 0x400f4003u +#define CYREG_UDB_DSI0_HC4 0x400f4004u +#define CYREG_UDB_DSI0_HC5 0x400f4005u +#define CYREG_UDB_DSI0_HC6 0x400f4006u +#define CYREG_UDB_DSI0_HC7 0x400f4007u +#define CYREG_UDB_DSI0_HC8 0x400f4008u +#define CYREG_UDB_DSI0_HC9 0x400f4009u +#define CYREG_UDB_DSI0_HC10 0x400f400au +#define CYREG_UDB_DSI0_HC11 0x400f400bu +#define CYREG_UDB_DSI0_HC12 0x400f400cu +#define CYREG_UDB_DSI0_HC13 0x400f400du +#define CYREG_UDB_DSI0_HC14 0x400f400eu +#define CYREG_UDB_DSI0_HC15 0x400f400fu +#define CYREG_UDB_DSI0_HC16 0x400f4010u +#define CYREG_UDB_DSI0_HC17 0x400f4011u +#define CYREG_UDB_DSI0_HC18 0x400f4012u +#define CYREG_UDB_DSI0_HC19 0x400f4013u +#define CYREG_UDB_DSI0_HC20 0x400f4014u +#define CYREG_UDB_DSI0_HC21 0x400f4015u +#define CYREG_UDB_DSI0_HC22 0x400f4016u +#define CYREG_UDB_DSI0_HC23 0x400f4017u +#define CYREG_UDB_DSI0_HC24 0x400f4018u +#define CYREG_UDB_DSI0_HC25 0x400f4019u +#define CYREG_UDB_DSI0_HC26 0x400f401au +#define CYREG_UDB_DSI0_HC27 0x400f401bu +#define CYREG_UDB_DSI0_HC28 0x400f401cu +#define CYREG_UDB_DSI0_HC29 0x400f401du +#define CYREG_UDB_DSI0_HC30 0x400f401eu +#define CYREG_UDB_DSI0_HC31 0x400f401fu +#define CYREG_UDB_DSI0_HC32 0x400f4020u +#define CYREG_UDB_DSI0_HC33 0x400f4021u +#define CYREG_UDB_DSI0_HC34 0x400f4022u +#define CYREG_UDB_DSI0_HC35 0x400f4023u +#define CYREG_UDB_DSI0_HC36 0x400f4024u +#define CYREG_UDB_DSI0_HC37 0x400f4025u +#define CYREG_UDB_DSI0_HC38 0x400f4026u +#define CYREG_UDB_DSI0_HC39 0x400f4027u +#define CYREG_UDB_DSI0_HC40 0x400f4028u +#define CYREG_UDB_DSI0_HC41 0x400f4029u +#define CYREG_UDB_DSI0_HC42 0x400f402au +#define CYREG_UDB_DSI0_HC43 0x400f402bu +#define CYREG_UDB_DSI0_HC44 0x400f402cu +#define CYREG_UDB_DSI0_HC45 0x400f402du +#define CYREG_UDB_DSI0_HC46 0x400f402eu +#define CYREG_UDB_DSI0_HC47 0x400f402fu +#define CYREG_UDB_DSI0_HC48 0x400f4030u +#define CYREG_UDB_DSI0_HC49 0x400f4031u +#define CYREG_UDB_DSI0_HC50 0x400f4032u +#define CYREG_UDB_DSI0_HC51 0x400f4033u +#define CYREG_UDB_DSI0_HC52 0x400f4034u +#define CYREG_UDB_DSI0_HC53 0x400f4035u +#define CYREG_UDB_DSI0_HC54 0x400f4036u +#define CYREG_UDB_DSI0_HC55 0x400f4037u +#define CYREG_UDB_DSI0_HC56 0x400f4038u +#define CYREG_UDB_DSI0_HC57 0x400f4039u +#define CYREG_UDB_DSI0_HC58 0x400f403au +#define CYREG_UDB_DSI0_HC59 0x400f403bu +#define CYREG_UDB_DSI0_HC60 0x400f403cu +#define CYREG_UDB_DSI0_HC61 0x400f403du +#define CYREG_UDB_DSI0_HC62 0x400f403eu +#define CYREG_UDB_DSI0_HC63 0x400f403fu +#define CYREG_UDB_DSI0_HC64 0x400f4040u +#define CYREG_UDB_DSI0_HC65 0x400f4041u +#define CYREG_UDB_DSI0_HC66 0x400f4042u +#define CYREG_UDB_DSI0_HC67 0x400f4043u +#define CYREG_UDB_DSI0_HC68 0x400f4044u +#define CYREG_UDB_DSI0_HC69 0x400f4045u +#define CYREG_UDB_DSI0_HC70 0x400f4046u +#define CYREG_UDB_DSI0_HC71 0x400f4047u +#define CYREG_UDB_DSI0_HC72 0x400f4048u +#define CYREG_UDB_DSI0_HC73 0x400f4049u +#define CYREG_UDB_DSI0_HC74 0x400f404au +#define CYREG_UDB_DSI0_HC75 0x400f404bu +#define CYREG_UDB_DSI0_HC76 0x400f404cu +#define CYREG_UDB_DSI0_HC77 0x400f404du +#define CYREG_UDB_DSI0_HC78 0x400f404eu +#define CYREG_UDB_DSI0_HC79 0x400f404fu +#define CYREG_UDB_DSI0_HC80 0x400f4050u +#define CYREG_UDB_DSI0_HC81 0x400f4051u +#define CYREG_UDB_DSI0_HC82 0x400f4052u +#define CYREG_UDB_DSI0_HC83 0x400f4053u +#define CYREG_UDB_DSI0_HC84 0x400f4054u +#define CYREG_UDB_DSI0_HC85 0x400f4055u +#define CYREG_UDB_DSI0_HC86 0x400f4056u +#define CYREG_UDB_DSI0_HC87 0x400f4057u +#define CYREG_UDB_DSI0_HC88 0x400f4058u +#define CYREG_UDB_DSI0_HC89 0x400f4059u +#define CYREG_UDB_DSI0_HC90 0x400f405au +#define CYREG_UDB_DSI0_HC91 0x400f405bu +#define CYREG_UDB_DSI0_HC92 0x400f405cu +#define CYREG_UDB_DSI0_HC93 0x400f405du +#define CYREG_UDB_DSI0_HC94 0x400f405eu +#define CYREG_UDB_DSI0_HC95 0x400f405fu +#define CYREG_UDB_DSI0_HC96 0x400f4060u +#define CYREG_UDB_DSI0_HC97 0x400f4061u +#define CYREG_UDB_DSI0_HC98 0x400f4062u +#define CYREG_UDB_DSI0_HC99 0x400f4063u +#define CYREG_UDB_DSI0_HC100 0x400f4064u +#define CYREG_UDB_DSI0_HC101 0x400f4065u +#define CYREG_UDB_DSI0_HC102 0x400f4066u +#define CYREG_UDB_DSI0_HC103 0x400f4067u +#define CYREG_UDB_DSI0_HC104 0x400f4068u +#define CYREG_UDB_DSI0_HC105 0x400f4069u +#define CYREG_UDB_DSI0_HC106 0x400f406au +#define CYREG_UDB_DSI0_HC107 0x400f406bu +#define CYREG_UDB_DSI0_HC108 0x400f406cu +#define CYREG_UDB_DSI0_HC109 0x400f406du +#define CYREG_UDB_DSI0_HC110 0x400f406eu +#define CYREG_UDB_DSI0_HC111 0x400f406fu +#define CYREG_UDB_DSI0_HC112 0x400f4070u +#define CYREG_UDB_DSI0_HC113 0x400f4071u +#define CYREG_UDB_DSI0_HC114 0x400f4072u +#define CYREG_UDB_DSI0_HC115 0x400f4073u +#define CYREG_UDB_DSI0_HC116 0x400f4074u +#define CYREG_UDB_DSI0_HC117 0x400f4075u +#define CYREG_UDB_DSI0_HC118 0x400f4076u +#define CYREG_UDB_DSI0_HC119 0x400f4077u +#define CYREG_UDB_DSI0_HC120 0x400f4078u +#define CYREG_UDB_DSI0_HC121 0x400f4079u +#define CYREG_UDB_DSI0_HC122 0x400f407au +#define CYREG_UDB_DSI0_HC123 0x400f407bu +#define CYREG_UDB_DSI0_HC124 0x400f407cu +#define CYREG_UDB_DSI0_HC125 0x400f407du +#define CYREG_UDB_DSI0_HC126 0x400f407eu +#define CYREG_UDB_DSI0_HC127 0x400f407fu +#define CYREG_UDB_DSI0_HV_L0 0x400f4080u +#define CYFLD_UDB_DSI_HV_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_HV_BYTE__SIZE 0x00000008u +#define CYREG_UDB_DSI0_HV_L1 0x400f4081u +#define CYREG_UDB_DSI0_HV_L2 0x400f4082u +#define CYREG_UDB_DSI0_HV_L3 0x400f4083u +#define CYREG_UDB_DSI0_HV_L4 0x400f4084u +#define CYREG_UDB_DSI0_HV_L5 0x400f4085u +#define CYREG_UDB_DSI0_HV_L6 0x400f4086u +#define CYREG_UDB_DSI0_HV_L7 0x400f4087u +#define CYREG_UDB_DSI0_HV_L8 0x400f4088u +#define CYREG_UDB_DSI0_HV_L9 0x400f4089u +#define CYREG_UDB_DSI0_HV_L10 0x400f408au +#define CYREG_UDB_DSI0_HV_L11 0x400f408bu +#define CYREG_UDB_DSI0_HV_L12 0x400f408cu +#define CYREG_UDB_DSI0_HV_L13 0x400f408du +#define CYREG_UDB_DSI0_HV_L14 0x400f408eu +#define CYREG_UDB_DSI0_HV_L15 0x400f408fu +#define CYREG_UDB_DSI0_HS0 0x400f4090u +#define CYFLD_UDB_DSI_HS_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_HS_BYTE__SIZE 0x00000008u +#define CYREG_UDB_DSI0_HS1 0x400f4091u +#define CYREG_UDB_DSI0_HS2 0x400f4092u +#define CYREG_UDB_DSI0_HS3 0x400f4093u +#define CYREG_UDB_DSI0_HS4 0x400f4094u +#define CYREG_UDB_DSI0_HS5 0x400f4095u +#define CYREG_UDB_DSI0_HS6 0x400f4096u +#define CYREG_UDB_DSI0_HS7 0x400f4097u +#define CYREG_UDB_DSI0_HS8 0x400f4098u +#define CYREG_UDB_DSI0_HS9 0x400f4099u +#define CYREG_UDB_DSI0_HS10 0x400f409au +#define CYREG_UDB_DSI0_HS11 0x400f409bu +#define CYREG_UDB_DSI0_HS12 0x400f409cu +#define CYREG_UDB_DSI0_HS13 0x400f409du +#define CYREG_UDB_DSI0_HS14 0x400f409eu +#define CYREG_UDB_DSI0_HS15 0x400f409fu +#define CYREG_UDB_DSI0_HS16 0x400f40a0u +#define CYREG_UDB_DSI0_HS17 0x400f40a1u +#define CYREG_UDB_DSI0_HS18 0x400f40a2u +#define CYREG_UDB_DSI0_HS19 0x400f40a3u +#define CYREG_UDB_DSI0_HS20 0x400f40a4u +#define CYREG_UDB_DSI0_HS21 0x400f40a5u +#define CYREG_UDB_DSI0_HS22 0x400f40a6u +#define CYREG_UDB_DSI0_HS23 0x400f40a7u +#define CYREG_UDB_DSI0_HV_R0 0x400f40a8u +#define CYREG_UDB_DSI0_HV_R1 0x400f40a9u +#define CYREG_UDB_DSI0_HV_R2 0x400f40aau +#define CYREG_UDB_DSI0_HV_R3 0x400f40abu +#define CYREG_UDB_DSI0_HV_R4 0x400f40acu +#define CYREG_UDB_DSI0_HV_R5 0x400f40adu +#define CYREG_UDB_DSI0_HV_R6 0x400f40aeu +#define CYREG_UDB_DSI0_HV_R7 0x400f40afu +#define CYREG_UDB_DSI0_HV_R8 0x400f40b0u +#define CYREG_UDB_DSI0_HV_R9 0x400f40b1u +#define CYREG_UDB_DSI0_HV_R10 0x400f40b2u +#define CYREG_UDB_DSI0_HV_R11 0x400f40b3u +#define CYREG_UDB_DSI0_HV_R12 0x400f40b4u +#define CYREG_UDB_DSI0_HV_R13 0x400f40b5u +#define CYREG_UDB_DSI0_HV_R14 0x400f40b6u +#define CYREG_UDB_DSI0_HV_R15 0x400f40b7u +#define CYREG_UDB_DSI0_DSIINP0 0x400f40c0u +#define CYFLD_UDB_DSI_PI_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_PI_TOP__SIZE 0x00000004u +#define CYFLD_UDB_DSI_PI_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_DSI_PI_BOT__SIZE 0x00000004u +#define CYREG_UDB_DSI0_DSIINP1 0x400f40c2u +#define CYREG_UDB_DSI0_DSIINP2 0x400f40c4u +#define CYREG_UDB_DSI0_DSIINP3 0x400f40c6u +#define CYREG_UDB_DSI0_DSIINP4 0x400f40c8u +#define CYREG_UDB_DSI0_DSIINP5 0x400f40cau +#define CYREG_UDB_DSI0_DSIOUTP0 0x400f40ccu +#define CYREG_UDB_DSI0_DSIOUTP1 0x400f40ceu +#define CYREG_UDB_DSI0_DSIOUTP2 0x400f40d0u +#define CYREG_UDB_DSI0_DSIOUTP3 0x400f40d2u +#define CYREG_UDB_DSI0_DSIOUTT0 0x400f40d4u +#define CYREG_UDB_DSI0_DSIOUTT1 0x400f40d6u +#define CYREG_UDB_DSI0_DSIOUTT2 0x400f40d8u +#define CYREG_UDB_DSI0_DSIOUTT3 0x400f40dau +#define CYREG_UDB_DSI0_DSIOUTT4 0x400f40dcu +#define CYREG_UDB_DSI0_DSIOUTT5 0x400f40deu +#define CYREG_UDB_DSI0_VS0 0x400f40e0u +#define CYFLD_UDB_DSI_VS_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_VS_TOP__SIZE 0x00000004u +#define CYFLD_UDB_DSI_VS_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_DSI_VS_BOT__SIZE 0x00000004u +#define CYREG_UDB_DSI0_VS1 0x400f40e2u +#define CYREG_UDB_DSI0_VS2 0x400f40e4u +#define CYREG_UDB_DSI0_VS3 0x400f40e6u +#define CYREG_UDB_DSI0_VS4 0x400f40e8u +#define CYREG_UDB_DSI0_VS5 0x400f40eau +#define CYREG_UDB_DSI0_VS6 0x400f40ecu +#define CYREG_UDB_DSI0_VS7 0x400f40eeu +#define CYDEV_UDB_DSI1_BASE 0x400f4100u +#define CYDEV_UDB_DSI1_SIZE 0x00000100u +#define CYREG_UDB_DSI1_HC0 0x400f4100u +#define CYREG_UDB_DSI1_HC1 0x400f4101u +#define CYREG_UDB_DSI1_HC2 0x400f4102u +#define CYREG_UDB_DSI1_HC3 0x400f4103u +#define CYREG_UDB_DSI1_HC4 0x400f4104u +#define CYREG_UDB_DSI1_HC5 0x400f4105u +#define CYREG_UDB_DSI1_HC6 0x400f4106u +#define CYREG_UDB_DSI1_HC7 0x400f4107u +#define CYREG_UDB_DSI1_HC8 0x400f4108u +#define CYREG_UDB_DSI1_HC9 0x400f4109u +#define CYREG_UDB_DSI1_HC10 0x400f410au +#define CYREG_UDB_DSI1_HC11 0x400f410bu +#define CYREG_UDB_DSI1_HC12 0x400f410cu +#define CYREG_UDB_DSI1_HC13 0x400f410du +#define CYREG_UDB_DSI1_HC14 0x400f410eu +#define CYREG_UDB_DSI1_HC15 0x400f410fu +#define CYREG_UDB_DSI1_HC16 0x400f4110u +#define CYREG_UDB_DSI1_HC17 0x400f4111u +#define CYREG_UDB_DSI1_HC18 0x400f4112u +#define CYREG_UDB_DSI1_HC19 0x400f4113u +#define CYREG_UDB_DSI1_HC20 0x400f4114u +#define CYREG_UDB_DSI1_HC21 0x400f4115u +#define CYREG_UDB_DSI1_HC22 0x400f4116u +#define CYREG_UDB_DSI1_HC23 0x400f4117u +#define CYREG_UDB_DSI1_HC24 0x400f4118u +#define CYREG_UDB_DSI1_HC25 0x400f4119u +#define CYREG_UDB_DSI1_HC26 0x400f411au +#define CYREG_UDB_DSI1_HC27 0x400f411bu +#define CYREG_UDB_DSI1_HC28 0x400f411cu +#define CYREG_UDB_DSI1_HC29 0x400f411du +#define CYREG_UDB_DSI1_HC30 0x400f411eu +#define CYREG_UDB_DSI1_HC31 0x400f411fu +#define CYREG_UDB_DSI1_HC32 0x400f4120u +#define CYREG_UDB_DSI1_HC33 0x400f4121u +#define CYREG_UDB_DSI1_HC34 0x400f4122u +#define CYREG_UDB_DSI1_HC35 0x400f4123u +#define CYREG_UDB_DSI1_HC36 0x400f4124u +#define CYREG_UDB_DSI1_HC37 0x400f4125u +#define CYREG_UDB_DSI1_HC38 0x400f4126u +#define CYREG_UDB_DSI1_HC39 0x400f4127u +#define CYREG_UDB_DSI1_HC40 0x400f4128u +#define CYREG_UDB_DSI1_HC41 0x400f4129u +#define CYREG_UDB_DSI1_HC42 0x400f412au +#define CYREG_UDB_DSI1_HC43 0x400f412bu +#define CYREG_UDB_DSI1_HC44 0x400f412cu +#define CYREG_UDB_DSI1_HC45 0x400f412du +#define CYREG_UDB_DSI1_HC46 0x400f412eu +#define CYREG_UDB_DSI1_HC47 0x400f412fu +#define CYREG_UDB_DSI1_HC48 0x400f4130u +#define CYREG_UDB_DSI1_HC49 0x400f4131u +#define CYREG_UDB_DSI1_HC50 0x400f4132u +#define CYREG_UDB_DSI1_HC51 0x400f4133u +#define CYREG_UDB_DSI1_HC52 0x400f4134u +#define CYREG_UDB_DSI1_HC53 0x400f4135u +#define CYREG_UDB_DSI1_HC54 0x400f4136u +#define CYREG_UDB_DSI1_HC55 0x400f4137u +#define CYREG_UDB_DSI1_HC56 0x400f4138u +#define CYREG_UDB_DSI1_HC57 0x400f4139u +#define CYREG_UDB_DSI1_HC58 0x400f413au +#define CYREG_UDB_DSI1_HC59 0x400f413bu +#define CYREG_UDB_DSI1_HC60 0x400f413cu +#define CYREG_UDB_DSI1_HC61 0x400f413du +#define CYREG_UDB_DSI1_HC62 0x400f413eu +#define CYREG_UDB_DSI1_HC63 0x400f413fu +#define CYREG_UDB_DSI1_HC64 0x400f4140u +#define CYREG_UDB_DSI1_HC65 0x400f4141u +#define CYREG_UDB_DSI1_HC66 0x400f4142u +#define CYREG_UDB_DSI1_HC67 0x400f4143u +#define CYREG_UDB_DSI1_HC68 0x400f4144u +#define CYREG_UDB_DSI1_HC69 0x400f4145u +#define CYREG_UDB_DSI1_HC70 0x400f4146u +#define CYREG_UDB_DSI1_HC71 0x400f4147u +#define CYREG_UDB_DSI1_HC72 0x400f4148u +#define CYREG_UDB_DSI1_HC73 0x400f4149u +#define CYREG_UDB_DSI1_HC74 0x400f414au +#define CYREG_UDB_DSI1_HC75 0x400f414bu +#define CYREG_UDB_DSI1_HC76 0x400f414cu +#define CYREG_UDB_DSI1_HC77 0x400f414du +#define CYREG_UDB_DSI1_HC78 0x400f414eu +#define CYREG_UDB_DSI1_HC79 0x400f414fu +#define CYREG_UDB_DSI1_HC80 0x400f4150u +#define CYREG_UDB_DSI1_HC81 0x400f4151u +#define CYREG_UDB_DSI1_HC82 0x400f4152u +#define CYREG_UDB_DSI1_HC83 0x400f4153u +#define CYREG_UDB_DSI1_HC84 0x400f4154u +#define CYREG_UDB_DSI1_HC85 0x400f4155u +#define CYREG_UDB_DSI1_HC86 0x400f4156u +#define CYREG_UDB_DSI1_HC87 0x400f4157u +#define CYREG_UDB_DSI1_HC88 0x400f4158u +#define CYREG_UDB_DSI1_HC89 0x400f4159u +#define CYREG_UDB_DSI1_HC90 0x400f415au +#define CYREG_UDB_DSI1_HC91 0x400f415bu +#define CYREG_UDB_DSI1_HC92 0x400f415cu +#define CYREG_UDB_DSI1_HC93 0x400f415du +#define CYREG_UDB_DSI1_HC94 0x400f415eu +#define CYREG_UDB_DSI1_HC95 0x400f415fu +#define CYREG_UDB_DSI1_HC96 0x400f4160u +#define CYREG_UDB_DSI1_HC97 0x400f4161u +#define CYREG_UDB_DSI1_HC98 0x400f4162u +#define CYREG_UDB_DSI1_HC99 0x400f4163u +#define CYREG_UDB_DSI1_HC100 0x400f4164u +#define CYREG_UDB_DSI1_HC101 0x400f4165u +#define CYREG_UDB_DSI1_HC102 0x400f4166u +#define CYREG_UDB_DSI1_HC103 0x400f4167u +#define CYREG_UDB_DSI1_HC104 0x400f4168u +#define CYREG_UDB_DSI1_HC105 0x400f4169u +#define CYREG_UDB_DSI1_HC106 0x400f416au +#define CYREG_UDB_DSI1_HC107 0x400f416bu +#define CYREG_UDB_DSI1_HC108 0x400f416cu +#define CYREG_UDB_DSI1_HC109 0x400f416du +#define CYREG_UDB_DSI1_HC110 0x400f416eu +#define CYREG_UDB_DSI1_HC111 0x400f416fu +#define CYREG_UDB_DSI1_HC112 0x400f4170u +#define CYREG_UDB_DSI1_HC113 0x400f4171u +#define CYREG_UDB_DSI1_HC114 0x400f4172u +#define CYREG_UDB_DSI1_HC115 0x400f4173u +#define CYREG_UDB_DSI1_HC116 0x400f4174u +#define CYREG_UDB_DSI1_HC117 0x400f4175u +#define CYREG_UDB_DSI1_HC118 0x400f4176u +#define CYREG_UDB_DSI1_HC119 0x400f4177u +#define CYREG_UDB_DSI1_HC120 0x400f4178u +#define CYREG_UDB_DSI1_HC121 0x400f4179u +#define CYREG_UDB_DSI1_HC122 0x400f417au +#define CYREG_UDB_DSI1_HC123 0x400f417bu +#define CYREG_UDB_DSI1_HC124 0x400f417cu +#define CYREG_UDB_DSI1_HC125 0x400f417du +#define CYREG_UDB_DSI1_HC126 0x400f417eu +#define CYREG_UDB_DSI1_HC127 0x400f417fu +#define CYREG_UDB_DSI1_HV_L0 0x400f4180u +#define CYREG_UDB_DSI1_HV_L1 0x400f4181u +#define CYREG_UDB_DSI1_HV_L2 0x400f4182u +#define CYREG_UDB_DSI1_HV_L3 0x400f4183u +#define CYREG_UDB_DSI1_HV_L4 0x400f4184u +#define CYREG_UDB_DSI1_HV_L5 0x400f4185u +#define CYREG_UDB_DSI1_HV_L6 0x400f4186u +#define CYREG_UDB_DSI1_HV_L7 0x400f4187u +#define CYREG_UDB_DSI1_HV_L8 0x400f4188u +#define CYREG_UDB_DSI1_HV_L9 0x400f4189u +#define CYREG_UDB_DSI1_HV_L10 0x400f418au +#define CYREG_UDB_DSI1_HV_L11 0x400f418bu +#define CYREG_UDB_DSI1_HV_L12 0x400f418cu +#define CYREG_UDB_DSI1_HV_L13 0x400f418du +#define CYREG_UDB_DSI1_HV_L14 0x400f418eu +#define CYREG_UDB_DSI1_HV_L15 0x400f418fu +#define CYREG_UDB_DSI1_HS0 0x400f4190u +#define CYREG_UDB_DSI1_HS1 0x400f4191u +#define CYREG_UDB_DSI1_HS2 0x400f4192u +#define CYREG_UDB_DSI1_HS3 0x400f4193u +#define CYREG_UDB_DSI1_HS4 0x400f4194u +#define CYREG_UDB_DSI1_HS5 0x400f4195u +#define CYREG_UDB_DSI1_HS6 0x400f4196u +#define CYREG_UDB_DSI1_HS7 0x400f4197u +#define CYREG_UDB_DSI1_HS8 0x400f4198u +#define CYREG_UDB_DSI1_HS9 0x400f4199u +#define CYREG_UDB_DSI1_HS10 0x400f419au +#define CYREG_UDB_DSI1_HS11 0x400f419bu +#define CYREG_UDB_DSI1_HS12 0x400f419cu +#define CYREG_UDB_DSI1_HS13 0x400f419du +#define CYREG_UDB_DSI1_HS14 0x400f419eu +#define CYREG_UDB_DSI1_HS15 0x400f419fu +#define CYREG_UDB_DSI1_HS16 0x400f41a0u +#define CYREG_UDB_DSI1_HS17 0x400f41a1u +#define CYREG_UDB_DSI1_HS18 0x400f41a2u +#define CYREG_UDB_DSI1_HS19 0x400f41a3u +#define CYREG_UDB_DSI1_HS20 0x400f41a4u +#define CYREG_UDB_DSI1_HS21 0x400f41a5u +#define CYREG_UDB_DSI1_HS22 0x400f41a6u +#define CYREG_UDB_DSI1_HS23 0x400f41a7u +#define CYREG_UDB_DSI1_HV_R0 0x400f41a8u +#define CYREG_UDB_DSI1_HV_R1 0x400f41a9u +#define CYREG_UDB_DSI1_HV_R2 0x400f41aau +#define CYREG_UDB_DSI1_HV_R3 0x400f41abu +#define CYREG_UDB_DSI1_HV_R4 0x400f41acu +#define CYREG_UDB_DSI1_HV_R5 0x400f41adu +#define CYREG_UDB_DSI1_HV_R6 0x400f41aeu +#define CYREG_UDB_DSI1_HV_R7 0x400f41afu +#define CYREG_UDB_DSI1_HV_R8 0x400f41b0u +#define CYREG_UDB_DSI1_HV_R9 0x400f41b1u +#define CYREG_UDB_DSI1_HV_R10 0x400f41b2u +#define CYREG_UDB_DSI1_HV_R11 0x400f41b3u +#define CYREG_UDB_DSI1_HV_R12 0x400f41b4u +#define CYREG_UDB_DSI1_HV_R13 0x400f41b5u +#define CYREG_UDB_DSI1_HV_R14 0x400f41b6u +#define CYREG_UDB_DSI1_HV_R15 0x400f41b7u +#define CYREG_UDB_DSI1_DSIINP0 0x400f41c0u +#define CYREG_UDB_DSI1_DSIINP1 0x400f41c2u +#define CYREG_UDB_DSI1_DSIINP2 0x400f41c4u +#define CYREG_UDB_DSI1_DSIINP3 0x400f41c6u +#define CYREG_UDB_DSI1_DSIINP4 0x400f41c8u +#define CYREG_UDB_DSI1_DSIINP5 0x400f41cau +#define CYREG_UDB_DSI1_DSIOUTP0 0x400f41ccu +#define CYREG_UDB_DSI1_DSIOUTP1 0x400f41ceu +#define CYREG_UDB_DSI1_DSIOUTP2 0x400f41d0u +#define CYREG_UDB_DSI1_DSIOUTP3 0x400f41d2u +#define CYREG_UDB_DSI1_DSIOUTT0 0x400f41d4u +#define CYREG_UDB_DSI1_DSIOUTT1 0x400f41d6u +#define CYREG_UDB_DSI1_DSIOUTT2 0x400f41d8u +#define CYREG_UDB_DSI1_DSIOUTT3 0x400f41dau +#define CYREG_UDB_DSI1_DSIOUTT4 0x400f41dcu +#define CYREG_UDB_DSI1_DSIOUTT5 0x400f41deu +#define CYREG_UDB_DSI1_VS0 0x400f41e0u +#define CYREG_UDB_DSI1_VS1 0x400f41e2u +#define CYREG_UDB_DSI1_VS2 0x400f41e4u +#define CYREG_UDB_DSI1_VS3 0x400f41e6u +#define CYREG_UDB_DSI1_VS4 0x400f41e8u +#define CYREG_UDB_DSI1_VS5 0x400f41eau +#define CYREG_UDB_DSI1_VS6 0x400f41ecu +#define CYREG_UDB_DSI1_VS7 0x400f41eeu +#define CYDEV_UDB_DSI2_BASE 0x400f4200u +#define CYDEV_UDB_DSI2_SIZE 0x00000100u +#define CYREG_UDB_DSI2_HC0 0x400f4200u +#define CYREG_UDB_DSI2_HC1 0x400f4201u +#define CYREG_UDB_DSI2_HC2 0x400f4202u +#define CYREG_UDB_DSI2_HC3 0x400f4203u +#define CYREG_UDB_DSI2_HC4 0x400f4204u +#define CYREG_UDB_DSI2_HC5 0x400f4205u +#define CYREG_UDB_DSI2_HC6 0x400f4206u +#define CYREG_UDB_DSI2_HC7 0x400f4207u +#define CYREG_UDB_DSI2_HC8 0x400f4208u +#define CYREG_UDB_DSI2_HC9 0x400f4209u +#define CYREG_UDB_DSI2_HC10 0x400f420au +#define CYREG_UDB_DSI2_HC11 0x400f420bu +#define CYREG_UDB_DSI2_HC12 0x400f420cu +#define CYREG_UDB_DSI2_HC13 0x400f420du +#define CYREG_UDB_DSI2_HC14 0x400f420eu +#define CYREG_UDB_DSI2_HC15 0x400f420fu +#define CYREG_UDB_DSI2_HC16 0x400f4210u +#define CYREG_UDB_DSI2_HC17 0x400f4211u +#define CYREG_UDB_DSI2_HC18 0x400f4212u +#define CYREG_UDB_DSI2_HC19 0x400f4213u +#define CYREG_UDB_DSI2_HC20 0x400f4214u +#define CYREG_UDB_DSI2_HC21 0x400f4215u +#define CYREG_UDB_DSI2_HC22 0x400f4216u +#define CYREG_UDB_DSI2_HC23 0x400f4217u +#define CYREG_UDB_DSI2_HC24 0x400f4218u +#define CYREG_UDB_DSI2_HC25 0x400f4219u +#define CYREG_UDB_DSI2_HC26 0x400f421au +#define CYREG_UDB_DSI2_HC27 0x400f421bu +#define CYREG_UDB_DSI2_HC28 0x400f421cu +#define CYREG_UDB_DSI2_HC29 0x400f421du +#define CYREG_UDB_DSI2_HC30 0x400f421eu +#define CYREG_UDB_DSI2_HC31 0x400f421fu +#define CYREG_UDB_DSI2_HC32 0x400f4220u +#define CYREG_UDB_DSI2_HC33 0x400f4221u +#define CYREG_UDB_DSI2_HC34 0x400f4222u +#define CYREG_UDB_DSI2_HC35 0x400f4223u +#define CYREG_UDB_DSI2_HC36 0x400f4224u +#define CYREG_UDB_DSI2_HC37 0x400f4225u +#define CYREG_UDB_DSI2_HC38 0x400f4226u +#define CYREG_UDB_DSI2_HC39 0x400f4227u +#define CYREG_UDB_DSI2_HC40 0x400f4228u +#define CYREG_UDB_DSI2_HC41 0x400f4229u +#define CYREG_UDB_DSI2_HC42 0x400f422au +#define CYREG_UDB_DSI2_HC43 0x400f422bu +#define CYREG_UDB_DSI2_HC44 0x400f422cu +#define CYREG_UDB_DSI2_HC45 0x400f422du +#define CYREG_UDB_DSI2_HC46 0x400f422eu +#define CYREG_UDB_DSI2_HC47 0x400f422fu +#define CYREG_UDB_DSI2_HC48 0x400f4230u +#define CYREG_UDB_DSI2_HC49 0x400f4231u +#define CYREG_UDB_DSI2_HC50 0x400f4232u +#define CYREG_UDB_DSI2_HC51 0x400f4233u +#define CYREG_UDB_DSI2_HC52 0x400f4234u +#define CYREG_UDB_DSI2_HC53 0x400f4235u +#define CYREG_UDB_DSI2_HC54 0x400f4236u +#define CYREG_UDB_DSI2_HC55 0x400f4237u +#define CYREG_UDB_DSI2_HC56 0x400f4238u +#define CYREG_UDB_DSI2_HC57 0x400f4239u +#define CYREG_UDB_DSI2_HC58 0x400f423au +#define CYREG_UDB_DSI2_HC59 0x400f423bu +#define CYREG_UDB_DSI2_HC60 0x400f423cu +#define CYREG_UDB_DSI2_HC61 0x400f423du +#define CYREG_UDB_DSI2_HC62 0x400f423eu +#define CYREG_UDB_DSI2_HC63 0x400f423fu +#define CYREG_UDB_DSI2_HC64 0x400f4240u +#define CYREG_UDB_DSI2_HC65 0x400f4241u +#define CYREG_UDB_DSI2_HC66 0x400f4242u +#define CYREG_UDB_DSI2_HC67 0x400f4243u +#define CYREG_UDB_DSI2_HC68 0x400f4244u +#define CYREG_UDB_DSI2_HC69 0x400f4245u +#define CYREG_UDB_DSI2_HC70 0x400f4246u +#define CYREG_UDB_DSI2_HC71 0x400f4247u +#define CYREG_UDB_DSI2_HC72 0x400f4248u +#define CYREG_UDB_DSI2_HC73 0x400f4249u +#define CYREG_UDB_DSI2_HC74 0x400f424au +#define CYREG_UDB_DSI2_HC75 0x400f424bu +#define CYREG_UDB_DSI2_HC76 0x400f424cu +#define CYREG_UDB_DSI2_HC77 0x400f424du +#define CYREG_UDB_DSI2_HC78 0x400f424eu +#define CYREG_UDB_DSI2_HC79 0x400f424fu +#define CYREG_UDB_DSI2_HC80 0x400f4250u +#define CYREG_UDB_DSI2_HC81 0x400f4251u +#define CYREG_UDB_DSI2_HC82 0x400f4252u +#define CYREG_UDB_DSI2_HC83 0x400f4253u +#define CYREG_UDB_DSI2_HC84 0x400f4254u +#define CYREG_UDB_DSI2_HC85 0x400f4255u +#define CYREG_UDB_DSI2_HC86 0x400f4256u +#define CYREG_UDB_DSI2_HC87 0x400f4257u +#define CYREG_UDB_DSI2_HC88 0x400f4258u +#define CYREG_UDB_DSI2_HC89 0x400f4259u +#define CYREG_UDB_DSI2_HC90 0x400f425au +#define CYREG_UDB_DSI2_HC91 0x400f425bu +#define CYREG_UDB_DSI2_HC92 0x400f425cu +#define CYREG_UDB_DSI2_HC93 0x400f425du +#define CYREG_UDB_DSI2_HC94 0x400f425eu +#define CYREG_UDB_DSI2_HC95 0x400f425fu +#define CYREG_UDB_DSI2_HC96 0x400f4260u +#define CYREG_UDB_DSI2_HC97 0x400f4261u +#define CYREG_UDB_DSI2_HC98 0x400f4262u +#define CYREG_UDB_DSI2_HC99 0x400f4263u +#define CYREG_UDB_DSI2_HC100 0x400f4264u +#define CYREG_UDB_DSI2_HC101 0x400f4265u +#define CYREG_UDB_DSI2_HC102 0x400f4266u +#define CYREG_UDB_DSI2_HC103 0x400f4267u +#define CYREG_UDB_DSI2_HC104 0x400f4268u +#define CYREG_UDB_DSI2_HC105 0x400f4269u +#define CYREG_UDB_DSI2_HC106 0x400f426au +#define CYREG_UDB_DSI2_HC107 0x400f426bu +#define CYREG_UDB_DSI2_HC108 0x400f426cu +#define CYREG_UDB_DSI2_HC109 0x400f426du +#define CYREG_UDB_DSI2_HC110 0x400f426eu +#define CYREG_UDB_DSI2_HC111 0x400f426fu +#define CYREG_UDB_DSI2_HC112 0x400f4270u +#define CYREG_UDB_DSI2_HC113 0x400f4271u +#define CYREG_UDB_DSI2_HC114 0x400f4272u +#define CYREG_UDB_DSI2_HC115 0x400f4273u +#define CYREG_UDB_DSI2_HC116 0x400f4274u +#define CYREG_UDB_DSI2_HC117 0x400f4275u +#define CYREG_UDB_DSI2_HC118 0x400f4276u +#define CYREG_UDB_DSI2_HC119 0x400f4277u +#define CYREG_UDB_DSI2_HC120 0x400f4278u +#define CYREG_UDB_DSI2_HC121 0x400f4279u +#define CYREG_UDB_DSI2_HC122 0x400f427au +#define CYREG_UDB_DSI2_HC123 0x400f427bu +#define CYREG_UDB_DSI2_HC124 0x400f427cu +#define CYREG_UDB_DSI2_HC125 0x400f427du +#define CYREG_UDB_DSI2_HC126 0x400f427eu +#define CYREG_UDB_DSI2_HC127 0x400f427fu +#define CYREG_UDB_DSI2_HV_L0 0x400f4280u +#define CYREG_UDB_DSI2_HV_L1 0x400f4281u +#define CYREG_UDB_DSI2_HV_L2 0x400f4282u +#define CYREG_UDB_DSI2_HV_L3 0x400f4283u +#define CYREG_UDB_DSI2_HV_L4 0x400f4284u +#define CYREG_UDB_DSI2_HV_L5 0x400f4285u +#define CYREG_UDB_DSI2_HV_L6 0x400f4286u +#define CYREG_UDB_DSI2_HV_L7 0x400f4287u +#define CYREG_UDB_DSI2_HV_L8 0x400f4288u +#define CYREG_UDB_DSI2_HV_L9 0x400f4289u +#define CYREG_UDB_DSI2_HV_L10 0x400f428au +#define CYREG_UDB_DSI2_HV_L11 0x400f428bu +#define CYREG_UDB_DSI2_HV_L12 0x400f428cu +#define CYREG_UDB_DSI2_HV_L13 0x400f428du +#define CYREG_UDB_DSI2_HV_L14 0x400f428eu +#define CYREG_UDB_DSI2_HV_L15 0x400f428fu +#define CYREG_UDB_DSI2_HS0 0x400f4290u +#define CYREG_UDB_DSI2_HS1 0x400f4291u +#define CYREG_UDB_DSI2_HS2 0x400f4292u +#define CYREG_UDB_DSI2_HS3 0x400f4293u +#define CYREG_UDB_DSI2_HS4 0x400f4294u +#define CYREG_UDB_DSI2_HS5 0x400f4295u +#define CYREG_UDB_DSI2_HS6 0x400f4296u +#define CYREG_UDB_DSI2_HS7 0x400f4297u +#define CYREG_UDB_DSI2_HS8 0x400f4298u +#define CYREG_UDB_DSI2_HS9 0x400f4299u +#define CYREG_UDB_DSI2_HS10 0x400f429au +#define CYREG_UDB_DSI2_HS11 0x400f429bu +#define CYREG_UDB_DSI2_HS12 0x400f429cu +#define CYREG_UDB_DSI2_HS13 0x400f429du +#define CYREG_UDB_DSI2_HS14 0x400f429eu +#define CYREG_UDB_DSI2_HS15 0x400f429fu +#define CYREG_UDB_DSI2_HS16 0x400f42a0u +#define CYREG_UDB_DSI2_HS17 0x400f42a1u +#define CYREG_UDB_DSI2_HS18 0x400f42a2u +#define CYREG_UDB_DSI2_HS19 0x400f42a3u +#define CYREG_UDB_DSI2_HS20 0x400f42a4u +#define CYREG_UDB_DSI2_HS21 0x400f42a5u +#define CYREG_UDB_DSI2_HS22 0x400f42a6u +#define CYREG_UDB_DSI2_HS23 0x400f42a7u +#define CYREG_UDB_DSI2_HV_R0 0x400f42a8u +#define CYREG_UDB_DSI2_HV_R1 0x400f42a9u +#define CYREG_UDB_DSI2_HV_R2 0x400f42aau +#define CYREG_UDB_DSI2_HV_R3 0x400f42abu +#define CYREG_UDB_DSI2_HV_R4 0x400f42acu +#define CYREG_UDB_DSI2_HV_R5 0x400f42adu +#define CYREG_UDB_DSI2_HV_R6 0x400f42aeu +#define CYREG_UDB_DSI2_HV_R7 0x400f42afu +#define CYREG_UDB_DSI2_HV_R8 0x400f42b0u +#define CYREG_UDB_DSI2_HV_R9 0x400f42b1u +#define CYREG_UDB_DSI2_HV_R10 0x400f42b2u +#define CYREG_UDB_DSI2_HV_R11 0x400f42b3u +#define CYREG_UDB_DSI2_HV_R12 0x400f42b4u +#define CYREG_UDB_DSI2_HV_R13 0x400f42b5u +#define CYREG_UDB_DSI2_HV_R14 0x400f42b6u +#define CYREG_UDB_DSI2_HV_R15 0x400f42b7u +#define CYREG_UDB_DSI2_DSIINP0 0x400f42c0u +#define CYREG_UDB_DSI2_DSIINP1 0x400f42c2u +#define CYREG_UDB_DSI2_DSIINP2 0x400f42c4u +#define CYREG_UDB_DSI2_DSIINP3 0x400f42c6u +#define CYREG_UDB_DSI2_DSIINP4 0x400f42c8u +#define CYREG_UDB_DSI2_DSIINP5 0x400f42cau +#define CYREG_UDB_DSI2_DSIOUTP0 0x400f42ccu +#define CYREG_UDB_DSI2_DSIOUTP1 0x400f42ceu +#define CYREG_UDB_DSI2_DSIOUTP2 0x400f42d0u +#define CYREG_UDB_DSI2_DSIOUTP3 0x400f42d2u +#define CYREG_UDB_DSI2_DSIOUTT0 0x400f42d4u +#define CYREG_UDB_DSI2_DSIOUTT1 0x400f42d6u +#define CYREG_UDB_DSI2_DSIOUTT2 0x400f42d8u +#define CYREG_UDB_DSI2_DSIOUTT3 0x400f42dau +#define CYREG_UDB_DSI2_DSIOUTT4 0x400f42dcu +#define CYREG_UDB_DSI2_DSIOUTT5 0x400f42deu +#define CYREG_UDB_DSI2_VS0 0x400f42e0u +#define CYREG_UDB_DSI2_VS1 0x400f42e2u +#define CYREG_UDB_DSI2_VS2 0x400f42e4u +#define CYREG_UDB_DSI2_VS3 0x400f42e6u +#define CYREG_UDB_DSI2_VS4 0x400f42e8u +#define CYREG_UDB_DSI2_VS5 0x400f42eau +#define CYREG_UDB_DSI2_VS6 0x400f42ecu +#define CYREG_UDB_DSI2_VS7 0x400f42eeu +#define CYDEV_UDB_DSI3_BASE 0x400f4300u +#define CYDEV_UDB_DSI3_SIZE 0x00000100u +#define CYREG_UDB_DSI3_HC0 0x400f4300u +#define CYREG_UDB_DSI3_HC1 0x400f4301u +#define CYREG_UDB_DSI3_HC2 0x400f4302u +#define CYREG_UDB_DSI3_HC3 0x400f4303u +#define CYREG_UDB_DSI3_HC4 0x400f4304u +#define CYREG_UDB_DSI3_HC5 0x400f4305u +#define CYREG_UDB_DSI3_HC6 0x400f4306u +#define CYREG_UDB_DSI3_HC7 0x400f4307u +#define CYREG_UDB_DSI3_HC8 0x400f4308u +#define CYREG_UDB_DSI3_HC9 0x400f4309u +#define CYREG_UDB_DSI3_HC10 0x400f430au +#define CYREG_UDB_DSI3_HC11 0x400f430bu +#define CYREG_UDB_DSI3_HC12 0x400f430cu +#define CYREG_UDB_DSI3_HC13 0x400f430du +#define CYREG_UDB_DSI3_HC14 0x400f430eu +#define CYREG_UDB_DSI3_HC15 0x400f430fu +#define CYREG_UDB_DSI3_HC16 0x400f4310u +#define CYREG_UDB_DSI3_HC17 0x400f4311u +#define CYREG_UDB_DSI3_HC18 0x400f4312u +#define CYREG_UDB_DSI3_HC19 0x400f4313u +#define CYREG_UDB_DSI3_HC20 0x400f4314u +#define CYREG_UDB_DSI3_HC21 0x400f4315u +#define CYREG_UDB_DSI3_HC22 0x400f4316u +#define CYREG_UDB_DSI3_HC23 0x400f4317u +#define CYREG_UDB_DSI3_HC24 0x400f4318u +#define CYREG_UDB_DSI3_HC25 0x400f4319u +#define CYREG_UDB_DSI3_HC26 0x400f431au +#define CYREG_UDB_DSI3_HC27 0x400f431bu +#define CYREG_UDB_DSI3_HC28 0x400f431cu +#define CYREG_UDB_DSI3_HC29 0x400f431du +#define CYREG_UDB_DSI3_HC30 0x400f431eu +#define CYREG_UDB_DSI3_HC31 0x400f431fu +#define CYREG_UDB_DSI3_HC32 0x400f4320u +#define CYREG_UDB_DSI3_HC33 0x400f4321u +#define CYREG_UDB_DSI3_HC34 0x400f4322u +#define CYREG_UDB_DSI3_HC35 0x400f4323u +#define CYREG_UDB_DSI3_HC36 0x400f4324u +#define CYREG_UDB_DSI3_HC37 0x400f4325u +#define CYREG_UDB_DSI3_HC38 0x400f4326u +#define CYREG_UDB_DSI3_HC39 0x400f4327u +#define CYREG_UDB_DSI3_HC40 0x400f4328u +#define CYREG_UDB_DSI3_HC41 0x400f4329u +#define CYREG_UDB_DSI3_HC42 0x400f432au +#define CYREG_UDB_DSI3_HC43 0x400f432bu +#define CYREG_UDB_DSI3_HC44 0x400f432cu +#define CYREG_UDB_DSI3_HC45 0x400f432du +#define CYREG_UDB_DSI3_HC46 0x400f432eu +#define CYREG_UDB_DSI3_HC47 0x400f432fu +#define CYREG_UDB_DSI3_HC48 0x400f4330u +#define CYREG_UDB_DSI3_HC49 0x400f4331u +#define CYREG_UDB_DSI3_HC50 0x400f4332u +#define CYREG_UDB_DSI3_HC51 0x400f4333u +#define CYREG_UDB_DSI3_HC52 0x400f4334u +#define CYREG_UDB_DSI3_HC53 0x400f4335u +#define CYREG_UDB_DSI3_HC54 0x400f4336u +#define CYREG_UDB_DSI3_HC55 0x400f4337u +#define CYREG_UDB_DSI3_HC56 0x400f4338u +#define CYREG_UDB_DSI3_HC57 0x400f4339u +#define CYREG_UDB_DSI3_HC58 0x400f433au +#define CYREG_UDB_DSI3_HC59 0x400f433bu +#define CYREG_UDB_DSI3_HC60 0x400f433cu +#define CYREG_UDB_DSI3_HC61 0x400f433du +#define CYREG_UDB_DSI3_HC62 0x400f433eu +#define CYREG_UDB_DSI3_HC63 0x400f433fu +#define CYREG_UDB_DSI3_HC64 0x400f4340u +#define CYREG_UDB_DSI3_HC65 0x400f4341u +#define CYREG_UDB_DSI3_HC66 0x400f4342u +#define CYREG_UDB_DSI3_HC67 0x400f4343u +#define CYREG_UDB_DSI3_HC68 0x400f4344u +#define CYREG_UDB_DSI3_HC69 0x400f4345u +#define CYREG_UDB_DSI3_HC70 0x400f4346u +#define CYREG_UDB_DSI3_HC71 0x400f4347u +#define CYREG_UDB_DSI3_HC72 0x400f4348u +#define CYREG_UDB_DSI3_HC73 0x400f4349u +#define CYREG_UDB_DSI3_HC74 0x400f434au +#define CYREG_UDB_DSI3_HC75 0x400f434bu +#define CYREG_UDB_DSI3_HC76 0x400f434cu +#define CYREG_UDB_DSI3_HC77 0x400f434du +#define CYREG_UDB_DSI3_HC78 0x400f434eu +#define CYREG_UDB_DSI3_HC79 0x400f434fu +#define CYREG_UDB_DSI3_HC80 0x400f4350u +#define CYREG_UDB_DSI3_HC81 0x400f4351u +#define CYREG_UDB_DSI3_HC82 0x400f4352u +#define CYREG_UDB_DSI3_HC83 0x400f4353u +#define CYREG_UDB_DSI3_HC84 0x400f4354u +#define CYREG_UDB_DSI3_HC85 0x400f4355u +#define CYREG_UDB_DSI3_HC86 0x400f4356u +#define CYREG_UDB_DSI3_HC87 0x400f4357u +#define CYREG_UDB_DSI3_HC88 0x400f4358u +#define CYREG_UDB_DSI3_HC89 0x400f4359u +#define CYREG_UDB_DSI3_HC90 0x400f435au +#define CYREG_UDB_DSI3_HC91 0x400f435bu +#define CYREG_UDB_DSI3_HC92 0x400f435cu +#define CYREG_UDB_DSI3_HC93 0x400f435du +#define CYREG_UDB_DSI3_HC94 0x400f435eu +#define CYREG_UDB_DSI3_HC95 0x400f435fu +#define CYREG_UDB_DSI3_HC96 0x400f4360u +#define CYREG_UDB_DSI3_HC97 0x400f4361u +#define CYREG_UDB_DSI3_HC98 0x400f4362u +#define CYREG_UDB_DSI3_HC99 0x400f4363u +#define CYREG_UDB_DSI3_HC100 0x400f4364u +#define CYREG_UDB_DSI3_HC101 0x400f4365u +#define CYREG_UDB_DSI3_HC102 0x400f4366u +#define CYREG_UDB_DSI3_HC103 0x400f4367u +#define CYREG_UDB_DSI3_HC104 0x400f4368u +#define CYREG_UDB_DSI3_HC105 0x400f4369u +#define CYREG_UDB_DSI3_HC106 0x400f436au +#define CYREG_UDB_DSI3_HC107 0x400f436bu +#define CYREG_UDB_DSI3_HC108 0x400f436cu +#define CYREG_UDB_DSI3_HC109 0x400f436du +#define CYREG_UDB_DSI3_HC110 0x400f436eu +#define CYREG_UDB_DSI3_HC111 0x400f436fu +#define CYREG_UDB_DSI3_HC112 0x400f4370u +#define CYREG_UDB_DSI3_HC113 0x400f4371u +#define CYREG_UDB_DSI3_HC114 0x400f4372u +#define CYREG_UDB_DSI3_HC115 0x400f4373u +#define CYREG_UDB_DSI3_HC116 0x400f4374u +#define CYREG_UDB_DSI3_HC117 0x400f4375u +#define CYREG_UDB_DSI3_HC118 0x400f4376u +#define CYREG_UDB_DSI3_HC119 0x400f4377u +#define CYREG_UDB_DSI3_HC120 0x400f4378u +#define CYREG_UDB_DSI3_HC121 0x400f4379u +#define CYREG_UDB_DSI3_HC122 0x400f437au +#define CYREG_UDB_DSI3_HC123 0x400f437bu +#define CYREG_UDB_DSI3_HC124 0x400f437cu +#define CYREG_UDB_DSI3_HC125 0x400f437du +#define CYREG_UDB_DSI3_HC126 0x400f437eu +#define CYREG_UDB_DSI3_HC127 0x400f437fu +#define CYREG_UDB_DSI3_HV_L0 0x400f4380u +#define CYREG_UDB_DSI3_HV_L1 0x400f4381u +#define CYREG_UDB_DSI3_HV_L2 0x400f4382u +#define CYREG_UDB_DSI3_HV_L3 0x400f4383u +#define CYREG_UDB_DSI3_HV_L4 0x400f4384u +#define CYREG_UDB_DSI3_HV_L5 0x400f4385u +#define CYREG_UDB_DSI3_HV_L6 0x400f4386u +#define CYREG_UDB_DSI3_HV_L7 0x400f4387u +#define CYREG_UDB_DSI3_HV_L8 0x400f4388u +#define CYREG_UDB_DSI3_HV_L9 0x400f4389u +#define CYREG_UDB_DSI3_HV_L10 0x400f438au +#define CYREG_UDB_DSI3_HV_L11 0x400f438bu +#define CYREG_UDB_DSI3_HV_L12 0x400f438cu +#define CYREG_UDB_DSI3_HV_L13 0x400f438du +#define CYREG_UDB_DSI3_HV_L14 0x400f438eu +#define CYREG_UDB_DSI3_HV_L15 0x400f438fu +#define CYREG_UDB_DSI3_HS0 0x400f4390u +#define CYREG_UDB_DSI3_HS1 0x400f4391u +#define CYREG_UDB_DSI3_HS2 0x400f4392u +#define CYREG_UDB_DSI3_HS3 0x400f4393u +#define CYREG_UDB_DSI3_HS4 0x400f4394u +#define CYREG_UDB_DSI3_HS5 0x400f4395u +#define CYREG_UDB_DSI3_HS6 0x400f4396u +#define CYREG_UDB_DSI3_HS7 0x400f4397u +#define CYREG_UDB_DSI3_HS8 0x400f4398u +#define CYREG_UDB_DSI3_HS9 0x400f4399u +#define CYREG_UDB_DSI3_HS10 0x400f439au +#define CYREG_UDB_DSI3_HS11 0x400f439bu +#define CYREG_UDB_DSI3_HS12 0x400f439cu +#define CYREG_UDB_DSI3_HS13 0x400f439du +#define CYREG_UDB_DSI3_HS14 0x400f439eu +#define CYREG_UDB_DSI3_HS15 0x400f439fu +#define CYREG_UDB_DSI3_HS16 0x400f43a0u +#define CYREG_UDB_DSI3_HS17 0x400f43a1u +#define CYREG_UDB_DSI3_HS18 0x400f43a2u +#define CYREG_UDB_DSI3_HS19 0x400f43a3u +#define CYREG_UDB_DSI3_HS20 0x400f43a4u +#define CYREG_UDB_DSI3_HS21 0x400f43a5u +#define CYREG_UDB_DSI3_HS22 0x400f43a6u +#define CYREG_UDB_DSI3_HS23 0x400f43a7u +#define CYREG_UDB_DSI3_HV_R0 0x400f43a8u +#define CYREG_UDB_DSI3_HV_R1 0x400f43a9u +#define CYREG_UDB_DSI3_HV_R2 0x400f43aau +#define CYREG_UDB_DSI3_HV_R3 0x400f43abu +#define CYREG_UDB_DSI3_HV_R4 0x400f43acu +#define CYREG_UDB_DSI3_HV_R5 0x400f43adu +#define CYREG_UDB_DSI3_HV_R6 0x400f43aeu +#define CYREG_UDB_DSI3_HV_R7 0x400f43afu +#define CYREG_UDB_DSI3_HV_R8 0x400f43b0u +#define CYREG_UDB_DSI3_HV_R9 0x400f43b1u +#define CYREG_UDB_DSI3_HV_R10 0x400f43b2u +#define CYREG_UDB_DSI3_HV_R11 0x400f43b3u +#define CYREG_UDB_DSI3_HV_R12 0x400f43b4u +#define CYREG_UDB_DSI3_HV_R13 0x400f43b5u +#define CYREG_UDB_DSI3_HV_R14 0x400f43b6u +#define CYREG_UDB_DSI3_HV_R15 0x400f43b7u +#define CYREG_UDB_DSI3_DSIINP0 0x400f43c0u +#define CYREG_UDB_DSI3_DSIINP1 0x400f43c2u +#define CYREG_UDB_DSI3_DSIINP2 0x400f43c4u +#define CYREG_UDB_DSI3_DSIINP3 0x400f43c6u +#define CYREG_UDB_DSI3_DSIINP4 0x400f43c8u +#define CYREG_UDB_DSI3_DSIINP5 0x400f43cau +#define CYREG_UDB_DSI3_DSIOUTP0 0x400f43ccu +#define CYREG_UDB_DSI3_DSIOUTP1 0x400f43ceu +#define CYREG_UDB_DSI3_DSIOUTP2 0x400f43d0u +#define CYREG_UDB_DSI3_DSIOUTP3 0x400f43d2u +#define CYREG_UDB_DSI3_DSIOUTT0 0x400f43d4u +#define CYREG_UDB_DSI3_DSIOUTT1 0x400f43d6u +#define CYREG_UDB_DSI3_DSIOUTT2 0x400f43d8u +#define CYREG_UDB_DSI3_DSIOUTT3 0x400f43dau +#define CYREG_UDB_DSI3_DSIOUTT4 0x400f43dcu +#define CYREG_UDB_DSI3_DSIOUTT5 0x400f43deu +#define CYREG_UDB_DSI3_VS0 0x400f43e0u +#define CYREG_UDB_DSI3_VS1 0x400f43e2u +#define CYREG_UDB_DSI3_VS2 0x400f43e4u +#define CYREG_UDB_DSI3_VS3 0x400f43e6u +#define CYREG_UDB_DSI3_VS4 0x400f43e8u +#define CYREG_UDB_DSI3_VS5 0x400f43eau +#define CYREG_UDB_DSI3_VS6 0x400f43ecu +#define CYREG_UDB_DSI3_VS7 0x400f43eeu +#define CYDEV_UDB_PA0_BASE 0x400f5000u +#define CYDEV_UDB_PA0_SIZE 0x00000010u +#define CYREG_UDB_PA0_CFG0 0x400f5000u +#define CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET 0x00000002u +#define CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_OFF 0x00000000u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_ON 0x00000001u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL 0x00000003u +#define CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET 0x00000004u +#define CYFLD_UDB_PA_CLKIN_EN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKIN_EN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKIN_EN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_CLKIN_INV__OFFSET 0x00000005u +#define CYFLD_UDB_PA_CLKIN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKIN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKIN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_NC__OFFSET 0x00000006u +#define CYFLD_UDB_PA_NC__SIZE 0x00000002u +#define CYREG_UDB_PA0_CFG1 0x400f5001u +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET 0x00000002u +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_ON 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL 0x00000003u +#define CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET 0x00000004u +#define CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_EN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_CLKOUT_INV__OFFSET 0x00000005u +#define CYFLD_UDB_PA_CLKOUT_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_INV_INV 0x00000001u +#define CYREG_UDB_PA0_CFG2 0x400f5002u +#define CYFLD_UDB_PA_CLKIN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_CLKIN_SEL__SIZE 0x00000004u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP 0x00000009u +#define CYVAL_UDB_PA_CLKIN_SEL_PIN_RC 0x0000000cu +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 0x0000000du +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 0x0000000eu +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 0x0000000fu +#define CYFLD_UDB_PA_CLKOUT_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_PA_CLKOUT_SEL__SIZE 0x00000004u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP 0x00000009u +#define CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC 0x0000000cu +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 0x0000000du +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 0x0000000eu +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 0x0000000fu +#define CYREG_UDB_PA0_CFG3 0x400f5003u +#define CYFLD_UDB_PA_RES_IN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_RES_IN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_RES_IN_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_RES_IN_INV__OFFSET 0x00000002u +#define CYFLD_UDB_PA_RES_IN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_IN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_RES_IN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_NC0__OFFSET 0x00000003u +#define CYFLD_UDB_PA_NC0__SIZE 0x00000001u +#define CYFLD_UDB_PA_RES_OUT_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_PA_RES_OUT_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_RES_OUT_INV__OFFSET 0x00000006u +#define CYFLD_UDB_PA_RES_OUT_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_OUT_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_RES_OUT_INV_INV 0x00000001u +#define CYFLD_UDB_PA_NC7__OFFSET 0x00000007u +#define CYFLD_UDB_PA_NC7__SIZE 0x00000001u +#define CYREG_UDB_PA0_CFG4 0x400f5004u +#define CYFLD_UDB_PA_RES_IN_EN__OFFSET 0x00000000u +#define CYFLD_UDB_PA_RES_IN_EN__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_IN_EN_DISABLE 0x00000000u +#define CYVAL_UDB_PA_RES_IN_EN_ENABLE 0x00000001u +#define CYFLD_UDB_PA_RES_OUT_EN__OFFSET 0x00000001u +#define CYFLD_UDB_PA_RES_OUT_EN__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_OUT_EN_DISABLE 0x00000000u +#define CYVAL_UDB_PA_RES_OUT_EN_ENABLE 0x00000001u +#define CYFLD_UDB_PA_RES_OE_EN__OFFSET 0x00000002u +#define CYFLD_UDB_PA_RES_OE_EN__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_OE_EN_DISABLE 0x00000000u +#define CYVAL_UDB_PA_RES_OE_EN_ENABLE 0x00000001u +#define CYFLD_UDB_PA_NC7654__OFFSET 0x00000003u +#define CYFLD_UDB_PA_NC7654__SIZE 0x00000005u +#define CYREG_UDB_PA0_CFG5 0x400f5005u +#define CYFLD_UDB_PA_PIN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_PIN_SEL__SIZE 0x00000001u +#define CYVAL_UDB_PA_PIN_SEL_PIN0 0x00000000u +#define CYVAL_UDB_PA_PIN_SEL_PIN1 0x00000001u +#define CYVAL_UDB_PA_PIN_SEL_PIN2 0x00000002u +#define CYVAL_UDB_PA_PIN_SEL_PIN3 0x00000003u +#define CYVAL_UDB_PA_PIN_SEL_PIN4 0x00000004u +#define CYVAL_UDB_PA_PIN_SEL_PIN5 0x00000005u +#define CYVAL_UDB_PA_PIN_SEL_PIN6 0x00000006u +#define CYVAL_UDB_PA_PIN_SEL_PIN7 0x00000007u +#define CYREG_UDB_PA0_CFG6 0x400f5006u +#define CYFLD_UDB_PA_IN_SYNC0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_IN_SYNC0__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC0_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_IN_SYNC1__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC1_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_IN_SYNC2__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC2_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_IN_SYNC3__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC3_RSVD 0x00000003u +#define CYREG_UDB_PA0_CFG7 0x400f5007u +#define CYFLD_UDB_PA_IN_SYNC4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_IN_SYNC4__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC4_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_IN_SYNC5__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC5_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_IN_SYNC6__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC6_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_IN_SYNC7__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC7_RSVD 0x00000003u +#define CYREG_UDB_PA0_CFG8 0x400f5008u +#define CYFLD_UDB_PA_OUT_SYNC0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OUT_SYNC0__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OUT_SYNC1__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OUT_SYNC2__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OUT_SYNC3__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV 0x00000003u +#define CYREG_UDB_PA0_CFG9 0x400f5009u +#define CYFLD_UDB_PA_OUT_SYNC4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OUT_SYNC4__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OUT_SYNC5__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OUT_SYNC6__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OUT_SYNC7__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV 0x00000003u +#define CYREG_UDB_PA0_CFG10 0x400f500au +#define CYFLD_UDB_PA_DATA_SEL0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_DATA_SEL0__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_DATA_SEL1__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_DATA_SEL2__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_DATA_SEL3__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 0x00000003u +#define CYREG_UDB_PA0_CFG11 0x400f500bu +#define CYFLD_UDB_PA_DATA_SEL4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_DATA_SEL4__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_DATA_SEL5__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_DATA_SEL6__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_DATA_SEL7__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 0x00000003u +#define CYREG_UDB_PA0_CFG12 0x400f500cu +#define CYFLD_UDB_PA_OE_SEL0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OE_SEL0__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OE_SEL1__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OE_SEL2__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OE_SEL3__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 0x00000003u +#define CYREG_UDB_PA0_CFG13 0x400f500du +#define CYFLD_UDB_PA_OE_SEL4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OE_SEL4__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OE_SEL5__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OE_SEL6__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OE_SEL7__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 0x00000003u +#define CYREG_UDB_PA0_CFG14 0x400f500eu +#define CYFLD_UDB_PA_OE_SYNC0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OE_SYNC0__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 0x00000003u +#define CYFLD_UDB_PA_OE_SYNC1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OE_SYNC1__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 0x00000003u +#define CYFLD_UDB_PA_OE_SYNC2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OE_SYNC2__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 0x00000003u +#define CYFLD_UDB_PA_OE_SYNC3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OE_SYNC3__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 0x00000003u +#define CYDEV_UDB_PA1_BASE 0x400f5010u +#define CYDEV_UDB_PA1_SIZE 0x00000010u +#define CYREG_UDB_PA1_CFG0 0x400f5010u +#define CYREG_UDB_PA1_CFG1 0x400f5011u +#define CYREG_UDB_PA1_CFG2 0x400f5012u +#define CYREG_UDB_PA1_CFG3 0x400f5013u +#define CYREG_UDB_PA1_CFG4 0x400f5014u +#define CYREG_UDB_PA1_CFG5 0x400f5015u +#define CYREG_UDB_PA1_CFG6 0x400f5016u +#define CYREG_UDB_PA1_CFG7 0x400f5017u +#define CYREG_UDB_PA1_CFG8 0x400f5018u +#define CYREG_UDB_PA1_CFG9 0x400f5019u +#define CYREG_UDB_PA1_CFG10 0x400f501au +#define CYREG_UDB_PA1_CFG11 0x400f501bu +#define CYREG_UDB_PA1_CFG12 0x400f501cu +#define CYREG_UDB_PA1_CFG13 0x400f501du +#define CYREG_UDB_PA1_CFG14 0x400f501eu +#define CYDEV_UDB_PA2_BASE 0x400f5020u +#define CYDEV_UDB_PA2_SIZE 0x00000010u +#define CYREG_UDB_PA2_CFG0 0x400f5020u +#define CYREG_UDB_PA2_CFG1 0x400f5021u +#define CYREG_UDB_PA2_CFG2 0x400f5022u +#define CYREG_UDB_PA2_CFG3 0x400f5023u +#define CYREG_UDB_PA2_CFG4 0x400f5024u +#define CYREG_UDB_PA2_CFG5 0x400f5025u +#define CYREG_UDB_PA2_CFG6 0x400f5026u +#define CYREG_UDB_PA2_CFG7 0x400f5027u +#define CYREG_UDB_PA2_CFG8 0x400f5028u +#define CYREG_UDB_PA2_CFG9 0x400f5029u +#define CYREG_UDB_PA2_CFG10 0x400f502au +#define CYREG_UDB_PA2_CFG11 0x400f502bu +#define CYREG_UDB_PA2_CFG12 0x400f502cu +#define CYREG_UDB_PA2_CFG13 0x400f502du +#define CYREG_UDB_PA2_CFG14 0x400f502eu +#define CYDEV_UDB_PA3_BASE 0x400f5030u +#define CYDEV_UDB_PA3_SIZE 0x00000010u +#define CYREG_UDB_PA3_CFG0 0x400f5030u +#define CYREG_UDB_PA3_CFG1 0x400f5031u +#define CYREG_UDB_PA3_CFG2 0x400f5032u +#define CYREG_UDB_PA3_CFG3 0x400f5033u +#define CYREG_UDB_PA3_CFG4 0x400f5034u +#define CYREG_UDB_PA3_CFG5 0x400f5035u +#define CYREG_UDB_PA3_CFG6 0x400f5036u +#define CYREG_UDB_PA3_CFG7 0x400f5037u +#define CYREG_UDB_PA3_CFG8 0x400f5038u +#define CYREG_UDB_PA3_CFG9 0x400f5039u +#define CYREG_UDB_PA3_CFG10 0x400f503au +#define CYREG_UDB_PA3_CFG11 0x400f503bu +#define CYREG_UDB_PA3_CFG12 0x400f503cu +#define CYREG_UDB_PA3_CFG13 0x400f503du +#define CYREG_UDB_PA3_CFG14 0x400f503eu +#define CYDEV_UDB_BCTL0_BASE 0x400f6000u +#define CYDEV_UDB_BCTL0_SIZE 0x00001000u +#define CYREG_UDB_BCTL0_DRV 0x400f6000u +#define CYFLD_UDB_BCTL0_DRV__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_DRV__SIZE 0x00000008u +#define CYVAL_UDB_BCTL0_DRV_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DRV_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_MDCLK_EN 0x400f6001u +#define CYFLD_UDB_BCTL0_DCEN__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_DCEN__SIZE 0x00000008u +#define CYVAL_UDB_BCTL0_DCEN_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DCEN_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_MBCLK_EN 0x400f6002u +#define CYFLD_UDB_BCTL0_BCEN__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_BCEN__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_BCEN_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_BCEN_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_BOTSEL_L 0x400f6008u +#define CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_CLK_SEL0__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET 0x00000002u +#define CYFLD_UDB_BCTL0_CLK_SEL1__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET 0x00000004u +#define CYFLD_UDB_BCTL0_CLK_SEL2__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET 0x00000006u +#define CYFLD_UDB_BCTL0_CLK_SEL3__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT 0x00000003u +#define CYREG_UDB_BCTL0_BOTSEL_U 0x400f6009u +#define CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_CLK_SEL4__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET 0x00000002u +#define CYFLD_UDB_BCTL0_CLK_SEL5__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET 0x00000004u +#define CYFLD_UDB_BCTL0_CLK_SEL6__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET 0x00000006u +#define CYFLD_UDB_BCTL0_CLK_SEL7__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT 0x00000003u +#define CYREG_UDB_BCTL0_TOPSEL_L 0x400f600au +#define CYREG_UDB_BCTL0_TOPSEL_U 0x400f600bu +#define CYREG_UDB_BCTL0_QCLK_EN0 0x400f6010u +#define CYFLD_UDB_BCTL0_DCEN_Q__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_DCEN_Q__SIZE 0x00000008u +#define CYVAL_UDB_BCTL0_DCEN_Q_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DCEN_Q_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_BCEN_Q__OFFSET 0x00000008u +#define CYFLD_UDB_BCTL0_BCEN_Q__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_BCEN_Q_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_BCEN_Q_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET 0x00000009u +#define CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET 0x0000000au +#define CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET 0x0000000bu +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET 0x0000000cu +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET 0x0000000du +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB 0x00000000u +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB 0x00000001u +#define CYFLD_UDB_BCTL0_NC0__OFFSET 0x0000000eu +#define CYFLD_UDB_BCTL0_NC0__SIZE 0x00000001u +#define CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET 0x0000000fu +#define CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_QCLK_EN1 0x400f6012u +#define CYDEV_UDB_UDBIF_BASE 0x400f7000u +#define CYDEV_UDB_UDBIF_SIZE 0x00001000u +#define CYREG_UDB_UDBIF_BANK_CTL 0x400f7000u +#define CYFLD_UDB_UDBIF_DIS_COR__OFFSET 0x00000000u +#define CYFLD_UDB_UDBIF_DIS_COR__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_DIS_COR_NORMAL 0x00000000u +#define CYVAL_UDB_UDBIF_DIS_COR_DISABLE 0x00000001u +#define CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET 0x00000001u +#define CYFLD_UDB_UDBIF_ROUTE_EN__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE 0x00000000u +#define CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE 0x00000001u +#define CYFLD_UDB_UDBIF_BANK_EN__OFFSET 0x00000002u +#define CYFLD_UDB_UDBIF_BANK_EN__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_BANK_EN_DISABLE 0x00000000u +#define CYVAL_UDB_UDBIF_BANK_EN_ENABLE 0x00000001u +#define CYFLD_UDB_UDBIF_LOCK__OFFSET 0x00000003u +#define CYFLD_UDB_UDBIF_LOCK__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_LOCK_MUTABLE 0x00000000u +#define CYVAL_UDB_UDBIF_LOCK_LOCKED 0x00000001u +#define CYFLD_UDB_UDBIF_PIPE__OFFSET 0x00000004u +#define CYFLD_UDB_UDBIF_PIPE__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_PIPE_BYPASS 0x00000000u +#define CYVAL_UDB_UDBIF_PIPE_PIPELINED 0x00000001u +#define CYFLD_UDB_UDBIF_GLBL_WR__OFFSET 0x00000007u +#define CYFLD_UDB_UDBIF_GLBL_WR__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_GLBL_WR_DISABLE 0x00000000u +#define CYVAL_UDB_UDBIF_GLBL_WR_ENABLE 0x00000001u +#define CYREG_UDB_UDBIF_WAIT_CFG 0x400f7001u +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET 0x00000000u +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS 0x00000000u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT 0x00000003u +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET 0x00000002u +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT 0x00000000u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS 0x00000003u +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET 0x00000004u +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT 0x00000000u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS 0x00000003u +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET 0x00000006u +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT 0x00000000u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS 0x00000003u +#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x400f701cu +#define CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET 0x00000000u +#define CYFLD_UDB_UDBIF_EN_HFCLK__SIZE 0x00000001u +#define CYREG_UDB_INT_CFG 0x400f8000u +#define CYFLD_UDB_INT_MODE_CFG__OFFSET 0x00000000u +#define CYFLD_UDB_INT_MODE_CFG__SIZE 0x00000020u +#define CYVAL_UDB_INT_MODE_CFG_LEVEL 0x00000000u +#define CYVAL_UDB_INT_MODE_CFG_PULSE 0x00000001u +#define CYDEV_CTBM_BASE 0x40100000u +#define CYDEV_CTBM_SIZE 0x00010000u +#define CYREG_CTBM_CTB_CTRL 0x40100000u +#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001fu +#define CYFLD_CTBM_ENABLED__SIZE 0x00000001u +#define CYREG_CTBM_OA_RES0_CTRL 0x40100004u +#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002u +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002u +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004u +#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005u +#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006u +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008u +#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002u +#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000u +#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001u +#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002u +#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003u +#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000bu +#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001u +#define CYREG_CTBM_OA_RES1_CTRL 0x40100008u +#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002u +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002u +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004u +#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005u +#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006u +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008u +#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002u +#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000u +#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001u +#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002u +#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003u +#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000bu +#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001u +#define CYREG_CTBM_COMP_STAT 0x4010000cu +#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010u +#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001u +#define CYREG_CTBM_INTR 0x40100020u +#define CYFLD_CTBM_COMP0__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1__SIZE 0x00000001u +#define CYREG_CTBM_INTR_SET 0x40100024u +#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001u +#define CYREG_CTBM_INTR_MASK 0x40100028u +#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001u +#define CYREG_CTBM_INTR_MASKED 0x4010002cu +#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001u +#define CYREG_CTBM_DFT_CTRL 0x40100030u +#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003u +#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001fu +#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001u +#define CYREG_CTBM_OA0_SW 0x40100080u +#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001u +#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002u +#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001u +#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003u +#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001u +#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008u +#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001u +#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000eu +#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001u +#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012u +#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001u +#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015u +#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001u +#define CYREG_CTBM_OA0_SW_CLEAR 0x40100084u +#define CYREG_CTBM_OA1_SW 0x40100088u +#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001u +#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001u +#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001u +#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004u +#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001u +#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008u +#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001u +#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000eu +#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012u +#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013u +#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015u +#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001u +#define CYREG_CTBM_OA1_SW_CLEAR 0x4010008cu +#define CYREG_CTBM_CTB_SW_HW_CTRL 0x401000c0u +#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002u +#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001u +#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003u +#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001u +#define CYREG_CTBM_CTB_SW_STATUS 0x401000c4u +#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001cu +#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001du +#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001eu +#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001u +#define CYREG_CTBM_OA0_OFFSET_TRIM 0x40100f00u +#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM 0x40100f04u +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA0_COMP_TRIM 0x40100f08u +#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002u +#define CYREG_CTBM_OA1_OFFSET_TRIM 0x40100f0cu +#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM 0x40100f10u +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA1_COMP_TRIM 0x40100f14u +#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002u +#define CYDEV_SAR_BASE 0x401a0000u +#define CYDEV_SAR_SIZE 0x00010000u +#define CYREG_SAR_CTRL 0x401a0000u +#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004u +#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003u +#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000u +#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001u +#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002u +#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003u +#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004u +#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005u +#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006u +#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007u +#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007u +#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001u +#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009u +#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003u +#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000u +#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001u +#define CYVAL_SAR_NEG_SEL_P1 0x00000002u +#define CYVAL_SAR_NEG_SEL_P3 0x00000003u +#define CYVAL_SAR_NEG_SEL_P5 0x00000004u +#define CYVAL_SAR_NEG_SEL_P7 0x00000005u +#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006u +#define CYVAL_SAR_NEG_SEL_VREF 0x00000007u +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000du +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001u +#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000eu +#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002u +#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000u +#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001u +#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002u +#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003u +#define CYFLD_SAR_SPARE__OFFSET 0x00000010u +#define CYFLD_SAR_SPARE__SIZE 0x00000004u +#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018u +#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002u +#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000u +#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001u +#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002u +#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003u +#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001cu +#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001u +#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001du +#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001u +#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001eu +#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001u +#define CYFLD_SAR_ENABLED__OFFSET 0x0000001fu +#define CYFLD_SAR_ENABLED__SIZE 0x00000001u +#define CYREG_SAR_SAMPLE_CTRL 0x401a0004u +#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000u +#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000u +#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001u +#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001u +#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001u +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002u +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001u +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000u +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001u +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003u +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001u +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000u +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001u +#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004u +#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003u +#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007u +#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001u +#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010u +#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001u +#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011u +#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001u +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012u +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001u +#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013u +#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001u +#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001u +#define CYREG_SAR_SAMPLE_TIME01 0x401a0010u +#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000u +#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000au +#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010u +#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000au +#define CYREG_SAR_SAMPLE_TIME23 0x401a0014u +#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000u +#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000au +#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010u +#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000au +#define CYREG_SAR_RANGE_THRES 0x401a0018u +#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010u +#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010u +#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010u +#define CYREG_SAR_RANGE_COND 0x401a001cu +#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001eu +#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002u +#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000u +#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001u +#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002u +#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003u +#define CYREG_SAR_CHAN_EN 0x401a0020u +#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010u +#define CYREG_SAR_START_CTRL 0x401a0024u +#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000u +#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001u +#define CYREG_SAR_DFT_CTRL 0x401a0030u +#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000u +#define CYFLD_SAR_DLY_INC__SIZE 0x00000001u +#define CYFLD_SAR_HIZ__OFFSET 0x00000001u +#define CYFLD_SAR_HIZ__SIZE 0x00000001u +#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010u +#define CYFLD_SAR_DFT_INC__SIZE 0x00000004u +#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014u +#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003u +#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018u +#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004u +#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001cu +#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001u +#define CYFLD_SAR_DCEN__OFFSET 0x0000001du +#define CYFLD_SAR_DCEN__SIZE 0x00000001u +#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001fu +#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001u +#define CYREG_SAR_CHAN_CONFIG00 0x401a0080u +#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000u +#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003u +#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004u +#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003u +#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000u +#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001u +#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002u +#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003u +#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004u +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT 0x00000006u +#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007u +#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008u +#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001u +#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009u +#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_RESOLUTION_12B 0x00000000u +#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001u +#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000au +#define CYFLD_SAR_AVG_EN__SIZE 0x00000001u +#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000cu +#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002u +#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001u +#define CYREG_SAR_CHAN_CONFIG01 0x401a0084u +#define CYREG_SAR_CHAN_CONFIG02 0x401a0088u +#define CYREG_SAR_CHAN_CONFIG03 0x401a008cu +#define CYREG_SAR_CHAN_CONFIG04 0x401a0090u +#define CYREG_SAR_CHAN_CONFIG05 0x401a0094u +#define CYREG_SAR_CHAN_CONFIG06 0x401a0098u +#define CYREG_SAR_CHAN_CONFIG07 0x401a009cu +#define CYREG_SAR_CHAN_WORK00 0x401a0100u +#define CYFLD_SAR_WORK__OFFSET 0x00000000u +#define CYFLD_SAR_WORK__SIZE 0x00000010u +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001u +#define CYREG_SAR_CHAN_WORK01 0x401a0104u +#define CYREG_SAR_CHAN_WORK02 0x401a0108u +#define CYREG_SAR_CHAN_WORK03 0x401a010cu +#define CYREG_SAR_CHAN_WORK04 0x401a0110u +#define CYREG_SAR_CHAN_WORK05 0x401a0114u +#define CYREG_SAR_CHAN_WORK06 0x401a0118u +#define CYREG_SAR_CHAN_WORK07 0x401a011cu +#define CYREG_SAR_CHAN_RESULT00 0x401a0180u +#define CYFLD_SAR_RESULT__OFFSET 0x00000000u +#define CYFLD_SAR_RESULT__SIZE 0x00000010u +#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001du +#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001eu +#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001u +#define CYREG_SAR_CHAN_RESULT01 0x401a0184u +#define CYREG_SAR_CHAN_RESULT02 0x401a0188u +#define CYREG_SAR_CHAN_RESULT03 0x401a018cu +#define CYREG_SAR_CHAN_RESULT04 0x401a0190u +#define CYREG_SAR_CHAN_RESULT05 0x401a0194u +#define CYREG_SAR_CHAN_RESULT06 0x401a0198u +#define CYREG_SAR_CHAN_RESULT07 0x401a019cu +#define CYREG_SAR_CHAN_WORK_VALID 0x401a0200u +#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010u +#define CYREG_SAR_CHAN_RESULT_VALID 0x401a0204u +#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010u +#define CYREG_SAR_STATUS 0x401a0208u +#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000u +#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005u +#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001eu +#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001u +#define CYFLD_SAR_BUSY__OFFSET 0x0000001fu +#define CYFLD_SAR_BUSY__SIZE 0x00000001u +#define CYREG_SAR_AVG_STAT 0x401a020cu +#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000u +#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014u +#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018u +#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008u +#define CYREG_SAR_INTR 0x401a0210u +#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001u +#define CYREG_SAR_INTR_SET 0x401a0214u +#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_SET__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001u +#define CYREG_SAR_INTR_MASK 0x401a0218u +#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001u +#define CYREG_SAR_INTR_MASKED 0x401a021cu +#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001u +#define CYREG_SAR_SATURATE_INTR 0x401a0220u +#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_SET 0x401a0224u +#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_MASK 0x401a0228u +#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_MASKED 0x401a022cu +#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR 0x401a0230u +#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_SET 0x401a0234u +#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_MASK 0x401a0238u +#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_MASKED 0x401a023cu +#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010u +#define CYREG_SAR_INTR_CAUSE 0x401a0240u +#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001eu +#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001u +#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001fu +#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001u +#define CYREG_SAR_INJ_CHAN_CONFIG 0x401a0280u +#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000u +#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003u +#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003u +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004u +#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006u +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007u +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008u +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009u +#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000u +#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001u +#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000au +#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000cu +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002u +#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001eu +#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001u +#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001u +#define CYREG_SAR_INJ_RESULT 0x401a0290u +#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000u +#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010u +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001cu +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001du +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001eu +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH0 0x401a0300u +#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004u +#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005u +#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006u +#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007u +#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008u +#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009u +#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000au +#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000bu +#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000cu +#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000du +#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000eu +#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000fu +#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010u +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011u +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016u +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017u +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018u +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019u +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001au +#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001bu +#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001cu +#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001du +#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x401a0304u +#define CYREG_SAR_MUX_SWITCH1 0x401a0308u +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x401a030cu +#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x401a0340u +#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004u +#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005u +#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006u +#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007u +#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010u +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011u +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_STATUS 0x401a0348u +#define CYREG_SAR_PUMP_CTRL 0x401a0380u +#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000u +#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001u +#define CYREG_SAR_ANA_TRIM 0x401a0f00u +#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000u +#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003u +#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003u +#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001u +#define CYREG_SAR_WOUNDING 0x401a0f04u +#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000u +#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002u +#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000u +#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001u +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002u +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003u +#define CYDEV_CM0_BASE 0xe0000000u +#define CYDEV_CM0_SIZE 0x00100000u +#define CYREG_CM0_DWT_PID4 0xe0001fd0u +#define CYFLD_CM0_VALUE__OFFSET 0x00000000u +#define CYFLD_CM0_VALUE__SIZE 0x00000020u +#define CYREG_CM0_DWT_PID0 0xe0001fe0u +#define CYREG_CM0_DWT_PID1 0xe0001fe4u +#define CYREG_CM0_DWT_PID2 0xe0001fe8u +#define CYREG_CM0_DWT_PID3 0xe0001fecu +#define CYREG_CM0_DWT_CID0 0xe0001ff0u +#define CYREG_CM0_DWT_CID1 0xe0001ff4u +#define CYREG_CM0_DWT_CID2 0xe0001ff8u +#define CYREG_CM0_DWT_CID3 0xe0001ffcu +#define CYREG_CM0_BP_PID4 0xe0002fd0u +#define CYREG_CM0_BP_PID0 0xe0002fe0u +#define CYREG_CM0_BP_PID1 0xe0002fe4u +#define CYREG_CM0_BP_PID2 0xe0002fe8u +#define CYREG_CM0_BP_PID3 0xe0002fecu +#define CYREG_CM0_BP_CID0 0xe0002ff0u +#define CYREG_CM0_BP_CID1 0xe0002ff4u +#define CYREG_CM0_BP_CID2 0xe0002ff8u +#define CYREG_CM0_BP_CID3 0xe0002ffcu +#define CYREG_CM0_SYST_CSR 0xe000e010u +#define CYFLD_CM0_ENABLE__OFFSET 0x00000000u +#define CYFLD_CM0_ENABLE__SIZE 0x00000001u +#define CYFLD_CM0_TICKINT__OFFSET 0x00000001u +#define CYFLD_CM0_TICKINT__SIZE 0x00000001u +#define CYFLD_CM0_CLKSOURCE__OFFSET 0x00000002u +#define CYFLD_CM0_CLKSOURCE__SIZE 0x00000001u +#define CYFLD_CM0_COUNTFLAG__OFFSET 0x00000010u +#define CYFLD_CM0_COUNTFLAG__SIZE 0x00000001u +#define CYREG_CM0_SYST_RVR 0xe000e014u +#define CYFLD_CM0_RELOAD__OFFSET 0x00000000u +#define CYFLD_CM0_RELOAD__SIZE 0x00000018u +#define CYREG_CM0_SYST_CVR 0xe000e018u +#define CYFLD_CM0_CURRENT__OFFSET 0x00000000u +#define CYFLD_CM0_CURRENT__SIZE 0x00000018u +#define CYREG_CM0_SYST_CALIB 0xe000e01cu +#define CYFLD_CM0_TENMS__OFFSET 0x00000000u +#define CYFLD_CM0_TENMS__SIZE 0x00000018u +#define CYFLD_CM0_SKEW__OFFSET 0x0000001eu +#define CYFLD_CM0_SKEW__SIZE 0x00000001u +#define CYFLD_CM0_NOREF__OFFSET 0x0000001fu +#define CYFLD_CM0_NOREF__SIZE 0x00000001u +#define CYREG_CM0_ISER 0xe000e100u +#define CYFLD_CM0_SETENA__OFFSET 0x00000000u +#define CYFLD_CM0_SETENA__SIZE 0x00000020u +#define CYREG_CM0_ICER 0xe000e180u +#define CYFLD_CM0_CLRENA__OFFSET 0x00000000u +#define CYFLD_CM0_CLRENA__SIZE 0x00000020u +#define CYREG_CM0_ISPR 0xe000e200u +#define CYFLD_CM0_SETPEND__OFFSET 0x00000000u +#define CYFLD_CM0_SETPEND__SIZE 0x00000020u +#define CYREG_CM0_ICPR 0xe000e280u +#define CYFLD_CM0_CLRPEND__OFFSET 0x00000000u +#define CYFLD_CM0_CLRPEND__SIZE 0x00000020u +#define CYREG_CM0_IPR0 0xe000e400u +#define CYFLD_CM0_PRI_N0__OFFSET 0x00000006u +#define CYFLD_CM0_PRI_N0__SIZE 0x00000002u +#define CYFLD_CM0_PRI_N1__OFFSET 0x0000000eu +#define CYFLD_CM0_PRI_N1__SIZE 0x00000002u +#define CYFLD_CM0_PRI_N2__OFFSET 0x00000016u +#define CYFLD_CM0_PRI_N2__SIZE 0x00000002u +#define CYFLD_CM0_PRI_N3__OFFSET 0x0000001eu +#define CYFLD_CM0_PRI_N3__SIZE 0x00000002u +#define CYREG_CM0_IPR1 0xe000e404u +#define CYREG_CM0_IPR2 0xe000e408u +#define CYREG_CM0_IPR3 0xe000e40cu +#define CYREG_CM0_IPR4 0xe000e410u +#define CYREG_CM0_IPR5 0xe000e414u +#define CYREG_CM0_IPR6 0xe000e418u +#define CYREG_CM0_IPR7 0xe000e41cu +#define CYREG_CM0_CPUID 0xe000ed00u +#define CYFLD_CM0_REVISION__OFFSET 0x00000000u +#define CYFLD_CM0_REVISION__SIZE 0x00000004u +#define CYFLD_CM0_PARTNO__OFFSET 0x00000004u +#define CYFLD_CM0_PARTNO__SIZE 0x0000000cu +#define CYFLD_CM0_CONSTANT__OFFSET 0x00000010u +#define CYFLD_CM0_CONSTANT__SIZE 0x00000004u +#define CYFLD_CM0_VARIANT__OFFSET 0x00000014u +#define CYFLD_CM0_VARIANT__SIZE 0x00000004u +#define CYFLD_CM0_IMPLEMENTER__OFFSET 0x00000018u +#define CYFLD_CM0_IMPLEMENTER__SIZE 0x00000008u +#define CYREG_CM0_ICSR 0xe000ed04u +#define CYFLD_CM0_VECTACTIVE__OFFSET 0x00000000u +#define CYFLD_CM0_VECTACTIVE__SIZE 0x00000009u +#define CYFLD_CM0_VECTPENDING__OFFSET 0x0000000cu +#define CYFLD_CM0_VECTPENDING__SIZE 0x00000009u +#define CYFLD_CM0_ISRPENDING__OFFSET 0x00000016u +#define CYFLD_CM0_ISRPENDING__SIZE 0x00000001u +#define CYFLD_CM0_ISRPREEMPT__OFFSET 0x00000017u +#define CYFLD_CM0_ISRPREEMPT__SIZE 0x00000001u +#define CYFLD_CM0_PENDSTCLR__OFFSET 0x00000019u +#define CYFLD_CM0_PENDSTCLR__SIZE 0x00000001u +#define CYFLD_CM0_PENDSTSETb__OFFSET 0x0000001au +#define CYFLD_CM0_PENDSTSETb__SIZE 0x00000001u +#define CYFLD_CM0_PENDSVCLR__OFFSET 0x0000001bu +#define CYFLD_CM0_PENDSVCLR__SIZE 0x00000001u +#define CYFLD_CM0_PENDSVSET__OFFSET 0x0000001cu +#define CYFLD_CM0_PENDSVSET__SIZE 0x00000001u +#define CYFLD_CM0_NMIPENDSET__OFFSET 0x0000001fu +#define CYFLD_CM0_NMIPENDSET__SIZE 0x00000001u +#define CYREG_CM0_AIRCR 0xe000ed0cu +#define CYFLD_CM0_VECTCLRACTIVE__OFFSET 0x00000001u +#define CYFLD_CM0_VECTCLRACTIVE__SIZE 0x00000001u +#define CYFLD_CM0_SYSRESETREQ__OFFSET 0x00000002u +#define CYFLD_CM0_SYSRESETREQ__SIZE 0x00000001u +#define CYFLD_CM0_ENDIANNESS__OFFSET 0x0000000fu +#define CYFLD_CM0_ENDIANNESS__SIZE 0x00000001u +#define CYFLD_CM0_VECTKEY__OFFSET 0x00000010u +#define CYFLD_CM0_VECTKEY__SIZE 0x00000010u +#define CYREG_CM0_SCR 0xe000ed10u +#define CYFLD_CM0_SLEEPONEXIT__OFFSET 0x00000001u +#define CYFLD_CM0_SLEEPONEXIT__SIZE 0x00000001u +#define CYFLD_CM0_SLEEPDEEP__OFFSET 0x00000002u +#define CYFLD_CM0_SLEEPDEEP__SIZE 0x00000001u +#define CYFLD_CM0_SEVONPEND__OFFSET 0x00000004u +#define CYFLD_CM0_SEVONPEND__SIZE 0x00000001u +#define CYREG_CM0_CCR 0xe000ed14u +#define CYFLD_CM0_UNALIGN_TRP__OFFSET 0x00000003u +#define CYFLD_CM0_UNALIGN_TRP__SIZE 0x00000001u +#define CYFLD_CM0_STKALIGN__OFFSET 0x00000009u +#define CYFLD_CM0_STKALIGN__SIZE 0x00000001u +#define CYREG_CM0_SHPR2 0xe000ed1cu +#define CYFLD_CM0_PRI_11__OFFSET 0x0000001eu +#define CYFLD_CM0_PRI_11__SIZE 0x00000002u +#define CYREG_CM0_SHPR3 0xe000ed20u +#define CYFLD_CM0_PRI_14__OFFSET 0x00000016u +#define CYFLD_CM0_PRI_14__SIZE 0x00000002u +#define CYFLD_CM0_PRI_15__OFFSET 0x0000001eu +#define CYFLD_CM0_PRI_15__SIZE 0x00000002u +#define CYREG_CM0_SHCSR 0xe000ed24u +#define CYFLD_CM0_SVCALLPENDED__OFFSET 0x0000000fu +#define CYFLD_CM0_SVCALLPENDED__SIZE 0x00000001u +#define CYREG_CM0_SCS_PID4 0xe000efd0u +#define CYREG_CM0_SCS_PID0 0xe000efe0u +#define CYREG_CM0_SCS_PID1 0xe000efe4u +#define CYREG_CM0_SCS_PID2 0xe000efe8u +#define CYREG_CM0_SCS_PID3 0xe000efecu +#define CYREG_CM0_SCS_CID0 0xe000eff0u +#define CYREG_CM0_SCS_CID1 0xe000eff4u +#define CYREG_CM0_SCS_CID2 0xe000eff8u +#define CYREG_CM0_SCS_CID3 0xe000effcu +#define CYREG_CM0_ROM_SCS 0xe00ff000u +#define CYREG_CM0_ROM_DWT 0xe00ff004u +#define CYREG_CM0_ROM_BPU 0xe00ff008u +#define CYREG_CM0_ROM_END 0xe00ff00cu +#define CYREG_CM0_ROM_CSMT 0xe00fffccu +#define CYREG_CM0_ROM_PID4 0xe00fffd0u +#define CYREG_CM0_ROM_PID0 0xe00fffe0u +#define CYREG_CM0_ROM_PID1 0xe00fffe4u +#define CYREG_CM0_ROM_PID2 0xe00fffe8u +#define CYREG_CM0_ROM_PID3 0xe00fffecu +#define CYREG_CM0_ROM_CID0 0xe00ffff0u +#define CYREG_CM0_ROM_CID1 0xe00ffff4u +#define CYREG_CM0_ROM_CID2 0xe00ffff8u +#define CYREG_CM0_ROM_CID3 0xe00ffffcu +#define CYDEV_CoreSightTable_BASE 0xf0000000u +#define CYDEV_CoreSightTable_SIZE 0x00001000u +#define CYREG_CoreSightTable_DATA_MBASE 0xf0000000u +#define CYREG_CoreSightTable_DATA_MSIZE 0x00001000u +#define CYDEV_FLS_SECTOR_SIZE 0x00008000u +#define CYDEV_FLS_ROW_SIZE 0x00000080u +#endif /* CYDEVICE_TRM_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc new file mode 100644 index 0000000..62bbcb7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc @@ -0,0 +1,6494 @@ +/******************************************************************************* +* File Name: cydevicegnu_trm.inc +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00008000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00008000 +.set CYDEV_SFLASH_BASE, 0x0ffff000 +.set CYDEV_SFLASH_SIZE, 0x00000200 +.set CYREG_SFLASH_PROT_ROW00, 0x0ffff000 +.set CYFLD_SFLASH_DATA8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_DATA8__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_ROW01, 0x0ffff001 +.set CYREG_SFLASH_PROT_ROW02, 0x0ffff002 +.set CYREG_SFLASH_PROT_ROW03, 0x0ffff003 +.set CYREG_SFLASH_PROT_ROW04, 0x0ffff004 +.set CYREG_SFLASH_PROT_ROW05, 0x0ffff005 +.set CYREG_SFLASH_PROT_ROW06, 0x0ffff006 +.set CYREG_SFLASH_PROT_ROW07, 0x0ffff007 +.set CYREG_SFLASH_PROT_ROW08, 0x0ffff008 +.set CYREG_SFLASH_PROT_ROW09, 0x0ffff009 +.set CYREG_SFLASH_PROT_ROW10, 0x0ffff00a +.set CYREG_SFLASH_PROT_ROW11, 0x0ffff00b +.set CYREG_SFLASH_PROT_ROW12, 0x0ffff00c +.set CYREG_SFLASH_PROT_ROW13, 0x0ffff00d +.set CYREG_SFLASH_PROT_ROW14, 0x0ffff00e +.set CYREG_SFLASH_PROT_ROW15, 0x0ffff00f +.set CYREG_SFLASH_PROT_ROW16, 0x0ffff010 +.set CYREG_SFLASH_PROT_ROW17, 0x0ffff011 +.set CYREG_SFLASH_PROT_ROW18, 0x0ffff012 +.set CYREG_SFLASH_PROT_ROW19, 0x0ffff013 +.set CYREG_SFLASH_PROT_ROW20, 0x0ffff014 +.set CYREG_SFLASH_PROT_ROW21, 0x0ffff015 +.set CYREG_SFLASH_PROT_ROW22, 0x0ffff016 +.set CYREG_SFLASH_PROT_ROW23, 0x0ffff017 +.set CYREG_SFLASH_PROT_ROW24, 0x0ffff018 +.set CYREG_SFLASH_PROT_ROW25, 0x0ffff019 +.set CYREG_SFLASH_PROT_ROW26, 0x0ffff01a +.set CYREG_SFLASH_PROT_ROW27, 0x0ffff01b +.set CYREG_SFLASH_PROT_ROW28, 0x0ffff01c +.set CYREG_SFLASH_PROT_ROW29, 0x0ffff01d +.set CYREG_SFLASH_PROT_ROW30, 0x0ffff01e +.set CYREG_SFLASH_PROT_ROW31, 0x0ffff01f +.set CYREG_SFLASH_PROT_ROW32, 0x0ffff020 +.set CYREG_SFLASH_PROT_ROW33, 0x0ffff021 +.set CYREG_SFLASH_PROT_ROW34, 0x0ffff022 +.set CYREG_SFLASH_PROT_ROW35, 0x0ffff023 +.set CYREG_SFLASH_PROT_ROW36, 0x0ffff024 +.set CYREG_SFLASH_PROT_ROW37, 0x0ffff025 +.set CYREG_SFLASH_PROT_ROW38, 0x0ffff026 +.set CYREG_SFLASH_PROT_ROW39, 0x0ffff027 +.set CYREG_SFLASH_PROT_ROW40, 0x0ffff028 +.set CYREG_SFLASH_PROT_ROW41, 0x0ffff029 +.set CYREG_SFLASH_PROT_ROW42, 0x0ffff02a +.set CYREG_SFLASH_PROT_ROW43, 0x0ffff02b +.set CYREG_SFLASH_PROT_ROW44, 0x0ffff02c +.set CYREG_SFLASH_PROT_ROW45, 0x0ffff02d +.set CYREG_SFLASH_PROT_ROW46, 0x0ffff02e +.set CYREG_SFLASH_PROT_ROW47, 0x0ffff02f +.set CYREG_SFLASH_PROT_ROW48, 0x0ffff030 +.set CYREG_SFLASH_PROT_ROW49, 0x0ffff031 +.set CYREG_SFLASH_PROT_ROW50, 0x0ffff032 +.set CYREG_SFLASH_PROT_ROW51, 0x0ffff033 +.set CYREG_SFLASH_PROT_ROW52, 0x0ffff034 +.set CYREG_SFLASH_PROT_ROW53, 0x0ffff035 +.set CYREG_SFLASH_PROT_ROW54, 0x0ffff036 +.set CYREG_SFLASH_PROT_ROW55, 0x0ffff037 +.set CYREG_SFLASH_PROT_ROW56, 0x0ffff038 +.set CYREG_SFLASH_PROT_ROW57, 0x0ffff039 +.set CYREG_SFLASH_PROT_ROW58, 0x0ffff03a +.set CYREG_SFLASH_PROT_ROW59, 0x0ffff03b +.set CYREG_SFLASH_PROT_ROW60, 0x0ffff03c +.set CYREG_SFLASH_PROT_ROW61, 0x0ffff03d +.set CYREG_SFLASH_PROT_ROW62, 0x0ffff03e +.set CYREG_SFLASH_PROT_ROW63, 0x0ffff03f +.set CYREG_SFLASH_PROT_PROTECTION, 0x0ffff07f +.set CYFLD_SFLASH_PROT_LEVEL__OFFSET, 0x00000000 +.set CYFLD_SFLASH_PROT_LEVEL__SIZE, 0x00000002 +.set CYVAL_SFLASH_PROT_LEVEL_VIRGIN, 0x00000001 +.set CYVAL_SFLASH_PROT_LEVEL_OPEN, 0x00000000 +.set CYVAL_SFLASH_PROT_LEVEL_PROTECTED, 0x00000002 +.set CYVAL_SFLASH_PROT_LEVEL_KILL, 0x00000003 +.set CYREG_SFLASH_AV_PAIRS_8B000, 0x0ffff080 +.set CYREG_SFLASH_AV_PAIRS_8B001, 0x0ffff081 +.set CYREG_SFLASH_AV_PAIRS_8B002, 0x0ffff082 +.set CYREG_SFLASH_AV_PAIRS_8B003, 0x0ffff083 +.set CYREG_SFLASH_AV_PAIRS_8B004, 0x0ffff084 +.set CYREG_SFLASH_AV_PAIRS_8B005, 0x0ffff085 +.set CYREG_SFLASH_AV_PAIRS_8B006, 0x0ffff086 +.set CYREG_SFLASH_AV_PAIRS_8B007, 0x0ffff087 +.set CYREG_SFLASH_AV_PAIRS_8B008, 0x0ffff088 +.set CYREG_SFLASH_AV_PAIRS_8B009, 0x0ffff089 +.set CYREG_SFLASH_AV_PAIRS_8B010, 0x0ffff08a +.set CYREG_SFLASH_AV_PAIRS_8B011, 0x0ffff08b +.set CYREG_SFLASH_AV_PAIRS_8B012, 0x0ffff08c +.set CYREG_SFLASH_AV_PAIRS_8B013, 0x0ffff08d +.set CYREG_SFLASH_AV_PAIRS_8B014, 0x0ffff08e +.set CYREG_SFLASH_AV_PAIRS_8B015, 0x0ffff08f +.set CYREG_SFLASH_AV_PAIRS_8B016, 0x0ffff090 +.set CYREG_SFLASH_AV_PAIRS_8B017, 0x0ffff091 +.set CYREG_SFLASH_AV_PAIRS_8B018, 0x0ffff092 +.set CYREG_SFLASH_AV_PAIRS_8B019, 0x0ffff093 +.set CYREG_SFLASH_AV_PAIRS_8B020, 0x0ffff094 +.set CYREG_SFLASH_AV_PAIRS_8B021, 0x0ffff095 +.set CYREG_SFLASH_AV_PAIRS_8B022, 0x0ffff096 +.set CYREG_SFLASH_AV_PAIRS_8B023, 0x0ffff097 +.set CYREG_SFLASH_AV_PAIRS_8B024, 0x0ffff098 +.set CYREG_SFLASH_AV_PAIRS_8B025, 0x0ffff099 +.set CYREG_SFLASH_AV_PAIRS_8B026, 0x0ffff09a +.set CYREG_SFLASH_AV_PAIRS_8B027, 0x0ffff09b +.set CYREG_SFLASH_AV_PAIRS_8B028, 0x0ffff09c +.set CYREG_SFLASH_AV_PAIRS_8B029, 0x0ffff09d +.set CYREG_SFLASH_AV_PAIRS_8B030, 0x0ffff09e +.set CYREG_SFLASH_AV_PAIRS_8B031, 0x0ffff09f +.set CYREG_SFLASH_AV_PAIRS_8B032, 0x0ffff0a0 +.set CYREG_SFLASH_AV_PAIRS_8B033, 0x0ffff0a1 +.set CYREG_SFLASH_AV_PAIRS_8B034, 0x0ffff0a2 +.set CYREG_SFLASH_AV_PAIRS_8B035, 0x0ffff0a3 +.set CYREG_SFLASH_AV_PAIRS_8B036, 0x0ffff0a4 +.set CYREG_SFLASH_AV_PAIRS_8B037, 0x0ffff0a5 +.set CYREG_SFLASH_AV_PAIRS_8B038, 0x0ffff0a6 +.set CYREG_SFLASH_AV_PAIRS_8B039, 0x0ffff0a7 +.set CYREG_SFLASH_AV_PAIRS_8B040, 0x0ffff0a8 +.set CYREG_SFLASH_AV_PAIRS_8B041, 0x0ffff0a9 +.set CYREG_SFLASH_AV_PAIRS_8B042, 0x0ffff0aa +.set CYREG_SFLASH_AV_PAIRS_8B043, 0x0ffff0ab +.set CYREG_SFLASH_AV_PAIRS_8B044, 0x0ffff0ac +.set CYREG_SFLASH_AV_PAIRS_8B045, 0x0ffff0ad +.set CYREG_SFLASH_AV_PAIRS_8B046, 0x0ffff0ae +.set CYREG_SFLASH_AV_PAIRS_8B047, 0x0ffff0af +.set CYREG_SFLASH_AV_PAIRS_8B048, 0x0ffff0b0 +.set CYREG_SFLASH_AV_PAIRS_8B049, 0x0ffff0b1 +.set CYREG_SFLASH_AV_PAIRS_8B050, 0x0ffff0b2 +.set CYREG_SFLASH_AV_PAIRS_8B051, 0x0ffff0b3 +.set CYREG_SFLASH_AV_PAIRS_8B052, 0x0ffff0b4 +.set CYREG_SFLASH_AV_PAIRS_8B053, 0x0ffff0b5 +.set CYREG_SFLASH_AV_PAIRS_8B054, 0x0ffff0b6 +.set CYREG_SFLASH_AV_PAIRS_8B055, 0x0ffff0b7 +.set CYREG_SFLASH_AV_PAIRS_8B056, 0x0ffff0b8 +.set CYREG_SFLASH_AV_PAIRS_8B057, 0x0ffff0b9 +.set CYREG_SFLASH_AV_PAIRS_8B058, 0x0ffff0ba +.set CYREG_SFLASH_AV_PAIRS_8B059, 0x0ffff0bb +.set CYREG_SFLASH_AV_PAIRS_8B060, 0x0ffff0bc +.set CYREG_SFLASH_AV_PAIRS_8B061, 0x0ffff0bd +.set CYREG_SFLASH_AV_PAIRS_8B062, 0x0ffff0be +.set CYREG_SFLASH_AV_PAIRS_8B063, 0x0ffff0bf +.set CYREG_SFLASH_AV_PAIRS_8B064, 0x0ffff0c0 +.set CYREG_SFLASH_AV_PAIRS_8B065, 0x0ffff0c1 +.set CYREG_SFLASH_AV_PAIRS_8B066, 0x0ffff0c2 +.set CYREG_SFLASH_AV_PAIRS_8B067, 0x0ffff0c3 +.set CYREG_SFLASH_AV_PAIRS_8B068, 0x0ffff0c4 +.set CYREG_SFLASH_AV_PAIRS_8B069, 0x0ffff0c5 +.set CYREG_SFLASH_AV_PAIRS_8B070, 0x0ffff0c6 +.set CYREG_SFLASH_AV_PAIRS_8B071, 0x0ffff0c7 +.set CYREG_SFLASH_AV_PAIRS_8B072, 0x0ffff0c8 +.set CYREG_SFLASH_AV_PAIRS_8B073, 0x0ffff0c9 +.set CYREG_SFLASH_AV_PAIRS_8B074, 0x0ffff0ca +.set CYREG_SFLASH_AV_PAIRS_8B075, 0x0ffff0cb +.set CYREG_SFLASH_AV_PAIRS_8B076, 0x0ffff0cc +.set CYREG_SFLASH_AV_PAIRS_8B077, 0x0ffff0cd +.set CYREG_SFLASH_AV_PAIRS_8B078, 0x0ffff0ce +.set CYREG_SFLASH_AV_PAIRS_8B079, 0x0ffff0cf +.set CYREG_SFLASH_AV_PAIRS_8B080, 0x0ffff0d0 +.set CYREG_SFLASH_AV_PAIRS_8B081, 0x0ffff0d1 +.set CYREG_SFLASH_AV_PAIRS_8B082, 0x0ffff0d2 +.set CYREG_SFLASH_AV_PAIRS_8B083, 0x0ffff0d3 +.set CYREG_SFLASH_AV_PAIRS_8B084, 0x0ffff0d4 +.set CYREG_SFLASH_AV_PAIRS_8B085, 0x0ffff0d5 +.set CYREG_SFLASH_AV_PAIRS_8B086, 0x0ffff0d6 +.set CYREG_SFLASH_AV_PAIRS_8B087, 0x0ffff0d7 +.set CYREG_SFLASH_AV_PAIRS_8B088, 0x0ffff0d8 +.set CYREG_SFLASH_AV_PAIRS_8B089, 0x0ffff0d9 +.set CYREG_SFLASH_AV_PAIRS_8B090, 0x0ffff0da +.set CYREG_SFLASH_AV_PAIRS_8B091, 0x0ffff0db +.set CYREG_SFLASH_AV_PAIRS_8B092, 0x0ffff0dc +.set CYREG_SFLASH_AV_PAIRS_8B093, 0x0ffff0dd +.set CYREG_SFLASH_AV_PAIRS_8B094, 0x0ffff0de +.set CYREG_SFLASH_AV_PAIRS_8B095, 0x0ffff0df +.set CYREG_SFLASH_AV_PAIRS_8B096, 0x0ffff0e0 +.set CYREG_SFLASH_AV_PAIRS_8B097, 0x0ffff0e1 +.set CYREG_SFLASH_AV_PAIRS_8B098, 0x0ffff0e2 +.set CYREG_SFLASH_AV_PAIRS_8B099, 0x0ffff0e3 +.set CYREG_SFLASH_AV_PAIRS_8B100, 0x0ffff0e4 +.set CYREG_SFLASH_AV_PAIRS_8B101, 0x0ffff0e5 +.set CYREG_SFLASH_AV_PAIRS_8B102, 0x0ffff0e6 +.set CYREG_SFLASH_AV_PAIRS_8B103, 0x0ffff0e7 +.set CYREG_SFLASH_AV_PAIRS_8B104, 0x0ffff0e8 +.set CYREG_SFLASH_AV_PAIRS_8B105, 0x0ffff0e9 +.set CYREG_SFLASH_AV_PAIRS_8B106, 0x0ffff0ea +.set CYREG_SFLASH_AV_PAIRS_8B107, 0x0ffff0eb +.set CYREG_SFLASH_AV_PAIRS_8B108, 0x0ffff0ec +.set CYREG_SFLASH_AV_PAIRS_8B109, 0x0ffff0ed +.set CYREG_SFLASH_AV_PAIRS_8B110, 0x0ffff0ee +.set CYREG_SFLASH_AV_PAIRS_8B111, 0x0ffff0ef +.set CYREG_SFLASH_AV_PAIRS_8B112, 0x0ffff0f0 +.set CYREG_SFLASH_AV_PAIRS_8B113, 0x0ffff0f1 +.set CYREG_SFLASH_AV_PAIRS_8B114, 0x0ffff0f2 +.set CYREG_SFLASH_AV_PAIRS_8B115, 0x0ffff0f3 +.set CYREG_SFLASH_AV_PAIRS_8B116, 0x0ffff0f4 +.set CYREG_SFLASH_AV_PAIRS_8B117, 0x0ffff0f5 +.set CYREG_SFLASH_AV_PAIRS_8B118, 0x0ffff0f6 +.set CYREG_SFLASH_AV_PAIRS_8B119, 0x0ffff0f7 +.set CYREG_SFLASH_AV_PAIRS_8B120, 0x0ffff0f8 +.set CYREG_SFLASH_AV_PAIRS_8B121, 0x0ffff0f9 +.set CYREG_SFLASH_AV_PAIRS_8B122, 0x0ffff0fa +.set CYREG_SFLASH_AV_PAIRS_8B123, 0x0ffff0fb +.set CYREG_SFLASH_AV_PAIRS_8B124, 0x0ffff0fc +.set CYREG_SFLASH_AV_PAIRS_8B125, 0x0ffff0fd +.set CYREG_SFLASH_AV_PAIRS_8B126, 0x0ffff0fe +.set CYREG_SFLASH_AV_PAIRS_8B127, 0x0ffff0ff +.set CYREG_SFLASH_AV_PAIRS_32B00, 0x0ffff100 +.set CYFLD_SFLASH_DATA32__OFFSET, 0x00000000 +.set CYFLD_SFLASH_DATA32__SIZE, 0x00000020 +.set CYREG_SFLASH_AV_PAIRS_32B01, 0x0ffff104 +.set CYREG_SFLASH_AV_PAIRS_32B02, 0x0ffff108 +.set CYREG_SFLASH_AV_PAIRS_32B03, 0x0ffff10c +.set CYREG_SFLASH_AV_PAIRS_32B04, 0x0ffff110 +.set CYREG_SFLASH_AV_PAIRS_32B05, 0x0ffff114 +.set CYREG_SFLASH_AV_PAIRS_32B06, 0x0ffff118 +.set CYREG_SFLASH_AV_PAIRS_32B07, 0x0ffff11c +.set CYREG_SFLASH_AV_PAIRS_32B08, 0x0ffff120 +.set CYREG_SFLASH_AV_PAIRS_32B09, 0x0ffff124 +.set CYREG_SFLASH_AV_PAIRS_32B10, 0x0ffff128 +.set CYREG_SFLASH_AV_PAIRS_32B11, 0x0ffff12c +.set CYREG_SFLASH_AV_PAIRS_32B12, 0x0ffff130 +.set CYREG_SFLASH_AV_PAIRS_32B13, 0x0ffff134 +.set CYREG_SFLASH_AV_PAIRS_32B14, 0x0ffff138 +.set CYREG_SFLASH_AV_PAIRS_32B15, 0x0ffff13c +.set CYREG_SFLASH_CPUSS_WOUNDING, 0x0ffff140 +.set CYREG_SFLASH_SILICON_ID, 0x0ffff144 +.set CYFLD_SFLASH_ID__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ID__SIZE, 0x00000010 +.set CYREG_SFLASH_CPUSS_PRIV_RAM, 0x0ffff148 +.set CYREG_SFLASH_CPUSS_PRIV_FLASH, 0x0ffff14c +.set CYREG_SFLASH_HIB_KEY_DELAY, 0x0ffff150 +.set CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET, 0x00000000 +.set CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE, 0x0000000a +.set CYREG_SFLASH_DPSLP_KEY_DELAY, 0x0ffff152 +.set CYREG_SFLASH_SWD_CONFIG, 0x0ffff154 +.set CYFLD_SFLASH_SWD_SELECT__OFFSET, 0x00000000 +.set CYFLD_SFLASH_SWD_SELECT__SIZE, 0x00000001 +.set CYREG_SFLASH_SWD_LISTEN, 0x0ffff158 +.set CYFLD_SFLASH_CYCLES__OFFSET, 0x00000000 +.set CYFLD_SFLASH_CYCLES__SIZE, 0x00000020 +.set CYREG_SFLASH_FLASH_START, 0x0ffff15c +.set CYFLD_SFLASH_ADDRESS__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ADDRESS__SIZE, 0x00000020 +.set CYREG_SFLASH_CSD_TRIM1_HVIDAC, 0x0ffff160 +.set CYFLD_SFLASH_TRIM8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TRIM8__SIZE, 0x00000008 +.set CYREG_SFLASH_CSD_TRIM2_HVIDAC, 0x0ffff161 +.set CYREG_SFLASH_CSD_TRIM1_CSD, 0x0ffff162 +.set CYREG_SFLASH_CSD_TRIM2_CSD, 0x0ffff163 +.set CYREG_SFLASH_SAR_TEMP_MULTIPLIER, 0x0ffff164 +.set CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE, 0x00000010 +.set CYREG_SFLASH_SAR_TEMP_OFFSET, 0x0ffff166 +.set CYFLD_SFLASH_TEMP_OFFSET__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TEMP_OFFSET__SIZE, 0x00000010 +.set CYREG_SFLASH_SKIP_CHECKSUM, 0x0ffff169 +.set CYFLD_SFLASH_SKIP__OFFSET, 0x00000000 +.set CYFLD_SFLASH_SKIP__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_VIRGINKEY0, 0x0ffff170 +.set CYFLD_SFLASH_KEY8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_KEY8__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_VIRGINKEY1, 0x0ffff171 +.set CYREG_SFLASH_PROT_VIRGINKEY2, 0x0ffff172 +.set CYREG_SFLASH_PROT_VIRGINKEY3, 0x0ffff173 +.set CYREG_SFLASH_PROT_VIRGINKEY4, 0x0ffff174 +.set CYREG_SFLASH_PROT_VIRGINKEY5, 0x0ffff175 +.set CYREG_SFLASH_PROT_VIRGINKEY6, 0x0ffff176 +.set CYREG_SFLASH_PROT_VIRGINKEY7, 0x0ffff177 +.set CYREG_SFLASH_DIE_LOT0, 0x0ffff178 +.set CYFLD_SFLASH_LOT__OFFSET, 0x00000000 +.set CYFLD_SFLASH_LOT__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_LOT1, 0x0ffff179 +.set CYREG_SFLASH_DIE_LOT2, 0x0ffff17a +.set CYREG_SFLASH_DIE_WAFER, 0x0ffff17b +.set CYFLD_SFLASH_WAFER__OFFSET, 0x00000000 +.set CYFLD_SFLASH_WAFER__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_X, 0x0ffff17c +.set CYFLD_SFLASH_X__OFFSET, 0x00000000 +.set CYFLD_SFLASH_X__SIZE, 0x00000006 +.set CYFLD_SFLASH_CRI_PASS__OFFSET, 0x00000006 +.set CYFLD_SFLASH_CRI_PASS__SIZE, 0x00000002 +.set CYREG_SFLASH_DIE_Y, 0x0ffff17d +.set CYFLD_SFLASH_Y__OFFSET, 0x00000000 +.set CYFLD_SFLASH_Y__SIZE, 0x00000006 +.set CYFLD_SFLASH_CHI_PASS__OFFSET, 0x00000006 +.set CYFLD_SFLASH_CHI_PASS__SIZE, 0x00000002 +.set CYREG_SFLASH_DIE_SORT, 0x0ffff17e +.set CYFLD_SFLASH_S1_PASS__OFFSET, 0x00000000 +.set CYFLD_SFLASH_S1_PASS__SIZE, 0x00000002 +.set CYFLD_SFLASH_S2_PASS__OFFSET, 0x00000002 +.set CYFLD_SFLASH_S2_PASS__SIZE, 0x00000002 +.set CYFLD_SFLASH_S3_PASS__OFFSET, 0x00000004 +.set CYFLD_SFLASH_S3_PASS__SIZE, 0x00000002 +.set CYREG_SFLASH_DIE_MINOR, 0x0ffff17f +.set CYFLD_SFLASH_MINOR__OFFSET, 0x00000000 +.set CYFLD_SFLASH_MINOR__SIZE, 0x00000008 +.set CYREG_SFLASH_PE_TE_DATA00, 0x0ffff180 +.set CYREG_SFLASH_PE_TE_DATA01, 0x0ffff181 +.set CYREG_SFLASH_PE_TE_DATA02, 0x0ffff182 +.set CYREG_SFLASH_PE_TE_DATA03, 0x0ffff183 +.set CYREG_SFLASH_PE_TE_DATA04, 0x0ffff184 +.set CYREG_SFLASH_PE_TE_DATA05, 0x0ffff185 +.set CYREG_SFLASH_PE_TE_DATA06, 0x0ffff186 +.set CYREG_SFLASH_PE_TE_DATA07, 0x0ffff187 +.set CYREG_SFLASH_PE_TE_DATA08, 0x0ffff188 +.set CYREG_SFLASH_PE_TE_DATA09, 0x0ffff189 +.set CYREG_SFLASH_PE_TE_DATA10, 0x0ffff18a +.set CYREG_SFLASH_PE_TE_DATA11, 0x0ffff18b +.set CYREG_SFLASH_PE_TE_DATA12, 0x0ffff18c +.set CYREG_SFLASH_PE_TE_DATA13, 0x0ffff18d +.set CYREG_SFLASH_PE_TE_DATA14, 0x0ffff18e +.set CYREG_SFLASH_PE_TE_DATA15, 0x0ffff18f +.set CYREG_SFLASH_PE_TE_DATA16, 0x0ffff190 +.set CYREG_SFLASH_PE_TE_DATA17, 0x0ffff191 +.set CYREG_SFLASH_PE_TE_DATA18, 0x0ffff192 +.set CYREG_SFLASH_PE_TE_DATA19, 0x0ffff193 +.set CYREG_SFLASH_PE_TE_DATA20, 0x0ffff194 +.set CYREG_SFLASH_PE_TE_DATA21, 0x0ffff195 +.set CYREG_SFLASH_PE_TE_DATA22, 0x0ffff196 +.set CYREG_SFLASH_PE_TE_DATA23, 0x0ffff197 +.set CYREG_SFLASH_PE_TE_DATA24, 0x0ffff198 +.set CYREG_SFLASH_PE_TE_DATA25, 0x0ffff199 +.set CYREG_SFLASH_PE_TE_DATA26, 0x0ffff19a +.set CYREG_SFLASH_PE_TE_DATA27, 0x0ffff19b +.set CYREG_SFLASH_PE_TE_DATA28, 0x0ffff19c +.set CYREG_SFLASH_PE_TE_DATA29, 0x0ffff19d +.set CYREG_SFLASH_PE_TE_DATA30, 0x0ffff19e +.set CYREG_SFLASH_PE_TE_DATA31, 0x0ffff19f +.set CYREG_SFLASH_PP, 0x0ffff1a0 +.set CYFLD_SFLASH_PERIOD__OFFSET, 0x00000000 +.set CYFLD_SFLASH_PERIOD__SIZE, 0x00000018 +.set CYFLD_SFLASH_PDAC__OFFSET, 0x00000018 +.set CYFLD_SFLASH_PDAC__SIZE, 0x00000004 +.set CYFLD_SFLASH_NDAC__OFFSET, 0x0000001c +.set CYFLD_SFLASH_NDAC__SIZE, 0x00000004 +.set CYREG_SFLASH_E, 0x0ffff1a4 +.set CYREG_SFLASH_P, 0x0ffff1a8 +.set CYREG_SFLASH_EA_E, 0x0ffff1ac +.set CYREG_SFLASH_EA_P, 0x0ffff1b0 +.set CYREG_SFLASH_ES_E, 0x0ffff1b4 +.set CYREG_SFLASH_ES_P_EO, 0x0ffff1b8 +.set CYREG_SFLASH_E_VCTAT, 0x0ffff1bc +.set CYFLD_SFLASH_VCTAT_SLOPE__OFFSET, 0x00000000 +.set CYFLD_SFLASH_VCTAT_SLOPE__SIZE, 0x00000004 +.set CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET, 0x00000004 +.set CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE, 0x00000002 +.set CYFLD_SFLASH_VCTAT_ENABLE__OFFSET, 0x00000006 +.set CYFLD_SFLASH_VCTAT_ENABLE__SIZE, 0x00000001 +.set CYREG_SFLASH_P_VCTAT, 0x0ffff1bd +.set CYREG_SFLASH_MARGIN, 0x0ffff1be +.set CYFLD_SFLASH_MDAC__OFFSET, 0x00000000 +.set CYFLD_SFLASH_MDAC__SIZE, 0x00000008 +.set CYREG_SFLASH_SPCIF_TRIM1, 0x0ffff1bf +.set CYFLD_SFLASH_BDAC__OFFSET, 0x00000000 +.set CYFLD_SFLASH_BDAC__SIZE, 0x00000004 +.set CYREG_SFLASH_IMO_MAXF0, 0x0ffff1c0 +.set CYFLD_SFLASH_MAXFREQ__OFFSET, 0x00000000 +.set CYFLD_SFLASH_MAXFREQ__SIZE, 0x00000006 +.set CYREG_SFLASH_IMO_ABS0, 0x0ffff1c1 +.set CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ABS_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_SFLASH_IMO_TMPCO0, 0x0ffff1c2 +.set CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_SFLASH_IMO_MAXF1, 0x0ffff1c3 +.set CYREG_SFLASH_IMO_ABS1, 0x0ffff1c4 +.set CYREG_SFLASH_IMO_TMPCO1, 0x0ffff1c5 +.set CYREG_SFLASH_IMO_MAXF2, 0x0ffff1c6 +.set CYREG_SFLASH_IMO_ABS2, 0x0ffff1c7 +.set CYREG_SFLASH_IMO_TMPCO2, 0x0ffff1c8 +.set CYREG_SFLASH_IMO_MAXF3, 0x0ffff1c9 +.set CYREG_SFLASH_IMO_ABS3, 0x0ffff1ca +.set CYREG_SFLASH_IMO_TMPCO3, 0x0ffff1cb +.set CYREG_SFLASH_IMO_ABS4, 0x0ffff1cc +.set CYREG_SFLASH_IMO_TMPCO4, 0x0ffff1cd +.set CYREG_SFLASH_IMO_TRIM00, 0x0ffff1d0 +.set CYFLD_SFLASH_OFFSET__OFFSET, 0x00000000 +.set CYFLD_SFLASH_OFFSET__SIZE, 0x00000008 +.set CYREG_SFLASH_IMO_TRIM01, 0x0ffff1d1 +.set CYREG_SFLASH_IMO_TRIM02, 0x0ffff1d2 +.set CYREG_SFLASH_IMO_TRIM03, 0x0ffff1d3 +.set CYREG_SFLASH_IMO_TRIM04, 0x0ffff1d4 +.set CYREG_SFLASH_IMO_TRIM05, 0x0ffff1d5 +.set CYREG_SFLASH_IMO_TRIM06, 0x0ffff1d6 +.set CYREG_SFLASH_IMO_TRIM07, 0x0ffff1d7 +.set CYREG_SFLASH_IMO_TRIM08, 0x0ffff1d8 +.set CYREG_SFLASH_IMO_TRIM09, 0x0ffff1d9 +.set CYREG_SFLASH_IMO_TRIM10, 0x0ffff1da +.set CYREG_SFLASH_IMO_TRIM11, 0x0ffff1db +.set CYREG_SFLASH_IMO_TRIM12, 0x0ffff1dc +.set CYREG_SFLASH_IMO_TRIM13, 0x0ffff1dd +.set CYREG_SFLASH_IMO_TRIM14, 0x0ffff1de +.set CYREG_SFLASH_IMO_TRIM15, 0x0ffff1df +.set CYREG_SFLASH_IMO_TRIM16, 0x0ffff1e0 +.set CYREG_SFLASH_IMO_TRIM17, 0x0ffff1e1 +.set CYREG_SFLASH_IMO_TRIM18, 0x0ffff1e2 +.set CYREG_SFLASH_IMO_TRIM19, 0x0ffff1e3 +.set CYREG_SFLASH_IMO_TRIM20, 0x0ffff1e4 +.set CYREG_SFLASH_IMO_TRIM21, 0x0ffff1e5 +.set CYREG_SFLASH_IMO_TRIM22, 0x0ffff1e6 +.set CYREG_SFLASH_IMO_TRIM23, 0x0ffff1e7 +.set CYREG_SFLASH_IMO_TRIM24, 0x0ffff1e8 +.set CYREG_SFLASH_IMO_TRIM25, 0x0ffff1e9 +.set CYREG_SFLASH_IMO_TRIM26, 0x0ffff1ea +.set CYREG_SFLASH_IMO_TRIM27, 0x0ffff1eb +.set CYREG_SFLASH_IMO_TRIM28, 0x0ffff1ec +.set CYREG_SFLASH_IMO_TRIM29, 0x0ffff1ed +.set CYREG_SFLASH_IMO_TRIM30, 0x0ffff1ee +.set CYREG_SFLASH_IMO_TRIM31, 0x0ffff1ef +.set CYREG_SFLASH_IMO_TRIM32, 0x0ffff1f0 +.set CYREG_SFLASH_IMO_TRIM33, 0x0ffff1f1 +.set CYREG_SFLASH_IMO_TRIM34, 0x0ffff1f2 +.set CYREG_SFLASH_IMO_TRIM35, 0x0ffff1f3 +.set CYREG_SFLASH_IMO_TRIM36, 0x0ffff1f4 +.set CYREG_SFLASH_IMO_TRIM37, 0x0ffff1f5 +.set CYREG_SFLASH_IMO_TRIM38, 0x0ffff1f6 +.set CYREG_SFLASH_IMO_TRIM39, 0x0ffff1f7 +.set CYREG_SFLASH_IMO_TRIM40, 0x0ffff1f8 +.set CYREG_SFLASH_IMO_TRIM41, 0x0ffff1f9 +.set CYREG_SFLASH_IMO_TRIM42, 0x0ffff1fa +.set CYREG_SFLASH_IMO_TRIM43, 0x0ffff1fb +.set CYREG_SFLASH_IMO_TRIM44, 0x0ffff1fc +.set CYREG_SFLASH_IMO_TRIM45, 0x0ffff1fd +.set CYREG_SFLASH_CHECKSUM, 0x0ffff1fe +.set CYFLD_SFLASH_CHECKSUM__OFFSET, 0x00000000 +.set CYFLD_SFLASH_CHECKSUM__SIZE, 0x00000010 +.set CYDEV_SROM_BASE, 0x10000000 +.set CYDEV_SROM_SIZE, 0x00001000 +.set CYREG_SROM_DATA_MBASE, 0x10000000 +.set CYREG_SROM_DATA_MSIZE, 0x00001000 +.set CYDEV_SRAM_BASE, 0x20000000 +.set CYDEV_SRAM_SIZE, 0x00001000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00001000 +.set CYDEV_CPUSS_BASE, 0x40000000 +.set CYDEV_CPUSS_SIZE, 0x00010000 +.set CYREG_CPUSS_CONFIG, 0x40000000 +.set CYFLD_CPUSS_VECS_IN_RAM__OFFSET, 0x00000000 +.set CYFLD_CPUSS_VECS_IN_RAM__SIZE, 0x00000001 +.set CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET, 0x00000001 +.set CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE, 0x00000001 +.set CYREG_CPUSS_SYSREQ, 0x40000004 +.set CYFLD_CPUSS_COMMAND__OFFSET, 0x00000000 +.set CYFLD_CPUSS_COMMAND__SIZE, 0x00000010 +.set CYFLD_CPUSS_NO_RST_OVR__OFFSET, 0x0000001b +.set CYFLD_CPUSS_NO_RST_OVR__SIZE, 0x00000001 +.set CYFLD_CPUSS_PRIVILEGED__OFFSET, 0x0000001c +.set CYFLD_CPUSS_PRIVILEGED__SIZE, 0x00000001 +.set CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET, 0x0000001d +.set CYFLD_CPUSS_ROM_ACCESS_EN__SIZE, 0x00000001 +.set CYFLD_CPUSS_HMASTER__OFFSET, 0x0000001e +.set CYFLD_CPUSS_HMASTER__SIZE, 0x00000001 +.set CYFLD_CPUSS_SYSREQ__OFFSET, 0x0000001f +.set CYFLD_CPUSS_SYSREQ__SIZE, 0x00000001 +.set CYREG_CPUSS_SYSARG, 0x40000008 +.set CYFLD_CPUSS_ARG32__OFFSET, 0x00000000 +.set CYFLD_CPUSS_ARG32__SIZE, 0x00000020 +.set CYREG_CPUSS_PROTECTION, 0x4000000c +.set CYFLD_CPUSS_PROT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_PROT__SIZE, 0x00000004 +.set CYVAL_CPUSS_PROT_VIRGIN, 0x00000000 +.set CYVAL_CPUSS_PROT_OPEN, 0x00000001 +.set CYVAL_CPUSS_PROT_PROTECTED, 0x00000002 +.set CYVAL_CPUSS_PROT_KILL, 0x00000004 +.set CYVAL_CPUSS_PROT_BOOT, 0x00000008 +.set CYFLD_CPUSS_PROT_LOCK__OFFSET, 0x0000001f +.set CYFLD_CPUSS_PROT_LOCK__SIZE, 0x00000001 +.set CYREG_CPUSS_PRIV_ROM, 0x40000010 +.set CYFLD_CPUSS_ROM_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_ROM_LIMIT__SIZE, 0x00000008 +.set CYREG_CPUSS_PRIV_RAM, 0x40000014 +.set CYFLD_CPUSS_RAM_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_RAM_LIMIT__SIZE, 0x00000009 +.set CYREG_CPUSS_PRIV_FLASH, 0x40000018 +.set CYFLD_CPUSS_FLASH_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_FLASH_LIMIT__SIZE, 0x0000000b +.set CYREG_CPUSS_WOUNDING, 0x4000001c +.set CYFLD_CPUSS_RAM_SIZE__OFFSET, 0x00000000 +.set CYFLD_CPUSS_RAM_SIZE__SIZE, 0x00000009 +.set CYFLD_CPUSS_RAM_WOUND__OFFSET, 0x00000010 +.set CYFLD_CPUSS_RAM_WOUND__SIZE, 0x00000003 +.set CYVAL_CPUSS_RAM_WOUND_FULL, 0x00000000 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_2, 0x00000001 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_4, 0x00000002 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_8, 0x00000003 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_16, 0x00000004 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_32, 0x00000005 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_64, 0x00000006 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_128, 0x00000007 +.set CYFLD_CPUSS_FLASH_WOUND__OFFSET, 0x00000014 +.set CYFLD_CPUSS_FLASH_WOUND__SIZE, 0x00000003 +.set CYVAL_CPUSS_FLASH_WOUND_FULL, 0x00000000 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2, 0x00000001 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4, 0x00000002 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8, 0x00000003 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16, 0x00000004 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32, 0x00000005 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64, 0x00000006 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128, 0x00000007 +.set CYREG_CPUSS_INTR_SELECT, 0x40000020 +.set CYFLD_CPUSS_SELECT32__OFFSET, 0x00000000 +.set CYFLD_CPUSS_SELECT32__SIZE, 0x00000020 +.set CYDEV_HSIOM_BASE, 0x40010000 +.set CYDEV_HSIOM_SIZE, 0x00001000 +.set CYREG_HSIOM_PORT_SEL0, 0x40010000 +.set CYFLD_HSIOM_SEL0__OFFSET, 0x00000000 +.set CYFLD_HSIOM_SEL0__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL0_GPIO, 0x00000000 +.set CYVAL_HSIOM_SEL0_GPIO_DSI, 0x00000001 +.set CYVAL_HSIOM_SEL0_DSI_DSI, 0x00000002 +.set CYVAL_HSIOM_SEL0_DSI_GPIO, 0x00000003 +.set CYVAL_HSIOM_SEL0_CSD_SENSE, 0x00000004 +.set CYVAL_HSIOM_SEL0_CSD_SHIELD, 0x00000005 +.set CYVAL_HSIOM_SEL0_AMUXA, 0x00000006 +.set CYVAL_HSIOM_SEL0_AMUXB, 0x00000007 +.set CYVAL_HSIOM_SEL0_ACT_0, 0x00000008 +.set CYVAL_HSIOM_SEL0_ACT_1, 0x00000009 +.set CYVAL_HSIOM_SEL0_ACT_2, 0x0000000a +.set CYVAL_HSIOM_SEL0_ACT_3, 0x0000000b +.set CYVAL_HSIOM_SEL0_LCD_COM, 0x0000000c +.set CYVAL_HSIOM_SEL0_LCD_SEG, 0x0000000d +.set CYVAL_HSIOM_SEL0_DPSLP_0, 0x0000000e +.set CYVAL_HSIOM_SEL0_DPSLP_1, 0x0000000f +.set CYVAL_HSIOM_SEL0_COMP1_INP, 0x00000000 +.set CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1, 0x0000000f +.set CYFLD_HSIOM_SEL1__OFFSET, 0x00000004 +.set CYFLD_HSIOM_SEL1__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL1_COMP1_INN, 0x00000000 +.set CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2, 0x0000000f +.set CYFLD_HSIOM_SEL2__OFFSET, 0x00000008 +.set CYFLD_HSIOM_SEL2__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL2_COMP2_INP, 0x00000000 +.set CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3, 0x0000000f +.set CYFLD_HSIOM_SEL3__OFFSET, 0x0000000c +.set CYFLD_HSIOM_SEL3__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL3_COMP2_INN, 0x00000000 +.set CYFLD_HSIOM_SEL4__OFFSET, 0x00000010 +.set CYFLD_HSIOM_SEL4__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL4_SCB1_UART_RX, 0x00000009 +.set CYVAL_HSIOM_SEL4_SCB1_I2C_SCL, 0x0000000e +.set CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI, 0x0000000f +.set CYFLD_HSIOM_SEL5__OFFSET, 0x00000014 +.set CYFLD_HSIOM_SEL5__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL5_SCB1_UART_TX, 0x00000009 +.set CYVAL_HSIOM_SEL5_SCB1_I2C_SDA, 0x0000000e +.set CYVAL_HSIOM_SEL5_SCB1_SPI_MISO, 0x0000000f +.set CYFLD_HSIOM_SEL6__OFFSET, 0x00000018 +.set CYFLD_HSIOM_SEL6__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL6_EXT_CLK, 0x00000008 +.set CYVAL_HSIOM_SEL6_SCB1_SPI_CLK, 0x0000000f +.set CYFLD_HSIOM_SEL7__OFFSET, 0x0000001c +.set CYFLD_HSIOM_SEL7__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL7_WAKEUP, 0x0000000e +.set CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0, 0x0000000f +.set CYREG_HSIOM_PORT_SEL1, 0x40010004 +.set CYREG_HSIOM_PORT_SEL2, 0x40010008 +.set CYREG_HSIOM_PORT_SEL3, 0x4001000c +.set CYREG_HSIOM_PORT_SEL4, 0x40010010 +.set CYDEV_CLK_BASE, 0x40020000 +.set CYDEV_CLK_SIZE, 0x00010000 +.set CYREG_CLK_DIVIDER_A00, 0x40020000 +.set CYFLD_CLK_DIVIDER_A__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_A__SIZE, 0x00000010 +.set CYFLD_CLK_ENABLE_A__OFFSET, 0x0000001f +.set CYFLD_CLK_ENABLE_A__SIZE, 0x00000001 +.set CYREG_CLK_DIVIDER_A01, 0x40020004 +.set CYREG_CLK_DIVIDER_A02, 0x40020008 +.set CYREG_CLK_DIVIDER_B00, 0x40020040 +.set CYFLD_CLK_DIVIDER_B__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_B__SIZE, 0x00000010 +.set CYFLD_CLK_CASCADE_A_B__OFFSET, 0x0000001e +.set CYFLD_CLK_CASCADE_A_B__SIZE, 0x00000001 +.set CYFLD_CLK_ENABLE_B__OFFSET, 0x0000001f +.set CYFLD_CLK_ENABLE_B__SIZE, 0x00000001 +.set CYREG_CLK_DIVIDER_B01, 0x40020044 +.set CYREG_CLK_DIVIDER_B02, 0x40020048 +.set CYREG_CLK_DIVIDER_C00, 0x40020080 +.set CYFLD_CLK_DIVIDER_C__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_C__SIZE, 0x00000010 +.set CYFLD_CLK_CASCADE_B_C__OFFSET, 0x0000001e +.set CYFLD_CLK_CASCADE_B_C__SIZE, 0x00000001 +.set CYFLD_CLK_ENABLE_C__OFFSET, 0x0000001f +.set CYFLD_CLK_ENABLE_C__SIZE, 0x00000001 +.set CYREG_CLK_DIVIDER_C01, 0x40020084 +.set CYREG_CLK_DIVIDER_C02, 0x40020088 +.set CYREG_CLK_DIVIDER_FRAC_A00, 0x40020100 +.set CYFLD_CLK_FRAC_A__OFFSET, 0x00000010 +.set CYFLD_CLK_FRAC_A__SIZE, 0x00000005 +.set CYREG_CLK_DIVIDER_FRAC_B00, 0x40020140 +.set CYFLD_CLK_FRAC_B__OFFSET, 0x00000010 +.set CYFLD_CLK_FRAC_B__SIZE, 0x00000005 +.set CYREG_CLK_DIVIDER_FRAC_C00, 0x40020180 +.set CYFLD_CLK_FRAC_C__OFFSET, 0x00000010 +.set CYFLD_CLK_FRAC_C__SIZE, 0x00000005 +.set CYREG_CLK_SELECT00, 0x40020200 +.set CYFLD_CLK_DIVIDER_N__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_N__SIZE, 0x00000004 +.set CYFLD_CLK_DIVIDER_ABC__OFFSET, 0x00000004 +.set CYFLD_CLK_DIVIDER_ABC__SIZE, 0x00000002 +.set CYVAL_CLK_DIVIDER_ABC_OFF, 0x00000000 +.set CYVAL_CLK_DIVIDER_ABC_A, 0x00000001 +.set CYVAL_CLK_DIVIDER_ABC_B, 0x00000002 +.set CYVAL_CLK_DIVIDER_ABC_C, 0x00000003 +.set CYREG_CLK_SELECT01, 0x40020204 +.set CYREG_CLK_SELECT02, 0x40020208 +.set CYREG_CLK_SELECT03, 0x4002020c +.set CYREG_CLK_SELECT04, 0x40020210 +.set CYREG_CLK_SELECT05, 0x40020214 +.set CYREG_CLK_SELECT06, 0x40020218 +.set CYREG_CLK_SELECT07, 0x4002021c +.set CYREG_CLK_SELECT08, 0x40020220 +.set CYREG_CLK_SELECT09, 0x40020224 +.set CYREG_CLK_SELECT10, 0x40020228 +.set CYREG_CLK_SELECT11, 0x4002022c +.set CYREG_CLK_SELECT12, 0x40020230 +.set CYREG_CLK_SELECT13, 0x40020234 +.set CYREG_CLK_SELECT14, 0x40020238 +.set CYREG_CLK_SELECT15, 0x4002023c +.set CYDEV_TST_BASE, 0x40030000 +.set CYDEV_TST_SIZE, 0x00010000 +.set CYREG_TST_CTRL, 0x40030000 +.set CYFLD_TST_DAP_NO_ACCESS__OFFSET, 0x00000000 +.set CYFLD_TST_DAP_NO_ACCESS__SIZE, 0x00000001 +.set CYFLD_TST_DAP_NO_DEBUG__OFFSET, 0x00000001 +.set CYFLD_TST_DAP_NO_DEBUG__SIZE, 0x00000001 +.set CYFLD_TST_SWD_CONNECTED__OFFSET, 0x00000002 +.set CYFLD_TST_SWD_CONNECTED__SIZE, 0x00000001 +.set CYFLD_TST_TEST_RESET_EN_N__OFFSET, 0x00000008 +.set CYFLD_TST_TEST_RESET_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SET_EN_N__OFFSET, 0x00000009 +.set CYFLD_TST_TEST_SET_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_ICG_EN_N__OFFSET, 0x0000000a +.set CYFLD_TST_TEST_ICG_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET, 0x0000000b +.set CYFLD_TST_TEST_OCC0_1_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET, 0x0000000c +.set CYFLD_TST_TEST_OCC0_2_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET, 0x0000000d +.set CYFLD_TST_TEST_SLPISOLATE_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET, 0x0000000e +.set CYFLD_TST_TEST_SYSISOLATE_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET, 0x0000000f +.set CYFLD_TST_TEST_SLPRETAIN_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET, 0x00000010 +.set CYFLD_TST_TEST_SYSRETAIN_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SPARE1_EN__OFFSET, 0x00000011 +.set CYFLD_TST_TEST_SPARE1_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SPARE2_EN__OFFSET, 0x00000012 +.set CYFLD_TST_TEST_SPARE2_EN__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET, 0x00000018 +.set CYFLD_TST_SCAN_OCC_OBSERVE__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_TRF1__OFFSET, 0x00000019 +.set CYFLD_TST_SCAN_TRF1__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_TRF__OFFSET, 0x0000001a +.set CYFLD_TST_SCAN_TRF__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_IDDQ__OFFSET, 0x0000001b +.set CYFLD_TST_SCAN_IDDQ__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_COMPRESS__OFFSET, 0x0000001c +.set CYFLD_TST_SCAN_COMPRESS__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_MODE__OFFSET, 0x0000001d +.set CYFLD_TST_SCAN_MODE__SIZE, 0x00000001 +.set CYFLD_TST_PTM_MODE_EN__OFFSET, 0x0000001e +.set CYFLD_TST_PTM_MODE_EN__SIZE, 0x00000001 +.set CYREG_TST_ADFT_CTRL, 0x40030004 +.set CYFLD_TST_ENABLE__OFFSET, 0x0000001f +.set CYFLD_TST_ENABLE__SIZE, 0x00000001 +.set CYREG_TST_DDFT_CTRL, 0x40030008 +.set CYFLD_TST_DFT_SEL1__OFFSET, 0x00000000 +.set CYFLD_TST_DFT_SEL1__SIZE, 0x00000006 +.set CYVAL_TST_DFT_SEL1_VSS, 0x00000000 +.set CYVAL_TST_DFT_SEL1_CLK1, 0x00000001 +.set CYVAL_TST_DFT_SEL1_CLK2, 0x00000002 +.set CYVAL_TST_DFT_SEL1_PWR1, 0x00000003 +.set CYVAL_TST_DFT_SEL1_PWR2, 0x00000004 +.set CYVAL_TST_DFT_SEL1_VMON, 0x00000005 +.set CYVAL_TST_DFT_SEL1_TSS_VDDA_OK, 0x00000006 +.set CYVAL_TST_DFT_SEL1_ADFT_TRIP1, 0x00000007 +.set CYVAL_TST_DFT_SEL1_ADFT_TRIP2, 0x00000008 +.set CYVAL_TST_DFT_SEL1_TSS1, 0x00000009 +.set CYVAL_TST_DFT_SEL1_TSS2, 0x0000000a +.set CYVAL_TST_DFT_SEL1_TSS3, 0x0000000b +.set CYVAL_TST_DFT_SEL1_TSS4, 0x0000000c +.set CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS, 0x0000000d +.set CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI, 0x0000000e +.set CYFLD_TST_DFT_SEL2__OFFSET, 0x00000008 +.set CYFLD_TST_DFT_SEL2__SIZE, 0x00000006 +.set CYVAL_TST_DFT_SEL2_VSS, 0x00000000 +.set CYVAL_TST_DFT_SEL2_CLK1, 0x00000001 +.set CYVAL_TST_DFT_SEL2_CLK2, 0x00000002 +.set CYVAL_TST_DFT_SEL2_PWR1, 0x00000003 +.set CYVAL_TST_DFT_SEL2_PWR2, 0x00000004 +.set CYVAL_TST_DFT_SEL2_VMON, 0x00000005 +.set CYVAL_TST_DFT_SEL2_TSS_VDDA_OK, 0x00000006 +.set CYVAL_TST_DFT_SEL2_ADFT_TRIP1, 0x00000007 +.set CYVAL_TST_DFT_SEL2_ADFT_TRIP2, 0x00000008 +.set CYVAL_TST_DFT_SEL2_TSS1, 0x00000009 +.set CYVAL_TST_DFT_SEL2_TSS2, 0x0000000a +.set CYVAL_TST_DFT_SEL2_TSS3, 0x0000000b +.set CYVAL_TST_DFT_SEL2_TSS4, 0x0000000c +.set CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS, 0x0000000d +.set CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI, 0x0000000e +.set CYFLD_TST_EDGE__OFFSET, 0x0000001c +.set CYFLD_TST_EDGE__SIZE, 0x00000001 +.set CYVAL_TST_EDGE_POSEDGE, 0x00000000 +.set CYVAL_TST_EDGE_NEGEDGE, 0x00000001 +.set CYFLD_TST_DIVIDE__OFFSET, 0x0000001d +.set CYFLD_TST_DIVIDE__SIZE, 0x00000002 +.set CYVAL_TST_DIVIDE_DIRECT, 0x00000000 +.set CYVAL_TST_DIVIDE_DIV_BY_2, 0x00000001 +.set CYVAL_TST_DIVIDE_DIV_BY_4, 0x00000002 +.set CYVAL_TST_DIVIDE_DIV_BY_8, 0x00000003 +.set CYREG_TST_MODE, 0x40030014 +.set CYFLD_TST_TEST_MODE__OFFSET, 0x0000001f +.set CYFLD_TST_TEST_MODE__SIZE, 0x00000001 +.set CYREG_TST_TRIM_CNTR1, 0x40030018 +.set CYFLD_TST_COUNTER__OFFSET, 0x00000000 +.set CYFLD_TST_COUNTER__SIZE, 0x00000010 +.set CYFLD_TST_COUNTER_DONE__OFFSET, 0x0000001f +.set CYFLD_TST_COUNTER_DONE__SIZE, 0x00000001 +.set CYREG_TST_TRIM_CNTR2, 0x4003001c +.set CYDEV_PRT0_BASE, 0x40040000 +.set CYDEV_PRT0_SIZE, 0x00000100 +.set CYREG_PRT0_DR, 0x40040000 +.set CYFLD_PRT_DATAREG__OFFSET, 0x00000000 +.set CYFLD_PRT_DATAREG__SIZE, 0x00000008 +.set CYREG_PRT0_PS, 0x40040004 +.set CYFLD_PRT_PINSTATE__OFFSET, 0x00000000 +.set CYFLD_PRT_PINSTATE__SIZE, 0x00000008 +.set CYFLD_PRT_PINSTATE_FLT__OFFSET, 0x00000008 +.set CYFLD_PRT_PINSTATE_FLT__SIZE, 0x00000001 +.set CYREG_PRT0_PC, 0x40040008 +.set CYFLD_PRT_DM__OFFSET, 0x00000000 +.set CYFLD_PRT_DM__SIZE, 0x00000018 +.set CYVAL_PRT_DM_OFF, 0x00000000 +.set CYVAL_PRT_DM_INPUT, 0x00000001 +.set CYVAL_PRT_DM_0_PU, 0x00000002 +.set CYVAL_PRT_DM_PD_1, 0x00000003 +.set CYVAL_PRT_DM_0_Z, 0x00000004 +.set CYVAL_PRT_DM_Z_1, 0x00000005 +.set CYVAL_PRT_DM_0_1, 0x00000006 +.set CYVAL_PRT_DM_PD_PU, 0x00000007 +.set CYFLD_PRT_VTRIP_SEL__OFFSET, 0x00000018 +.set CYFLD_PRT_VTRIP_SEL__SIZE, 0x00000001 +.set CYFLD_PRT_SLOW__OFFSET, 0x00000019 +.set CYFLD_PRT_SLOW__SIZE, 0x00000001 +.set CYREG_PRT0_INTCFG, 0x4004000c +.set CYFLD_PRT_INTTYPE__OFFSET, 0x00000000 +.set CYFLD_PRT_INTTYPE__SIZE, 0x00000010 +.set CYVAL_PRT_INTTYPE_DISABLE, 0x00000000 +.set CYVAL_PRT_INTTYPE_RISING, 0x00000001 +.set CYVAL_PRT_INTTYPE_FALLING, 0x00000002 +.set CYVAL_PRT_INTTYPE_BOTH, 0x00000003 +.set CYFLD_PRT_INTTYPE_FLT__OFFSET, 0x00000010 +.set CYFLD_PRT_INTTYPE_FLT__SIZE, 0x00000002 +.set CYVAL_PRT_INTTYPE_FLT_DISABLE, 0x00000000 +.set CYVAL_PRT_INTTYPE_FLT_RISING, 0x00000001 +.set CYVAL_PRT_INTTYPE_FLT_FALLING, 0x00000002 +.set CYVAL_PRT_INTTYPE_FLT_BOTH, 0x00000003 +.set CYFLD_PRT_FLT_SELECT__OFFSET, 0x00000012 +.set CYFLD_PRT_FLT_SELECT__SIZE, 0x00000003 +.set CYREG_PRT0_INTSTAT, 0x40040010 +.set CYFLD_PRT_INTSTAT__OFFSET, 0x00000000 +.set CYFLD_PRT_INTSTAT__SIZE, 0x00000008 +.set CYFLD_PRT_INTSTAT_FLT__OFFSET, 0x00000008 +.set CYFLD_PRT_INTSTAT_FLT__SIZE, 0x00000001 +.set CYFLD_PRT_PS__OFFSET, 0x00000010 +.set CYFLD_PRT_PS__SIZE, 0x00000008 +.set CYFLD_PRT_PS_FLT__OFFSET, 0x00000018 +.set CYFLD_PRT_PS_FLT__SIZE, 0x00000001 +.set CYREG_PRT0_PC2, 0x40040018 +.set CYFLD_PRT_INP_DIS__OFFSET, 0x00000000 +.set CYFLD_PRT_INP_DIS__SIZE, 0x00000008 +.set CYDEV_PRT1_BASE, 0x40040100 +.set CYDEV_PRT1_SIZE, 0x00000100 +.set CYREG_PRT1_DR, 0x40040100 +.set CYREG_PRT1_PS, 0x40040104 +.set CYREG_PRT1_PC, 0x40040108 +.set CYREG_PRT1_INTCFG, 0x4004010c +.set CYREG_PRT1_INTSTAT, 0x40040110 +.set CYREG_PRT1_PC2, 0x40040118 +.set CYDEV_PRT2_BASE, 0x40040200 +.set CYDEV_PRT2_SIZE, 0x00000100 +.set CYREG_PRT2_DR, 0x40040200 +.set CYREG_PRT2_PS, 0x40040204 +.set CYREG_PRT2_PC, 0x40040208 +.set CYREG_PRT2_INTCFG, 0x4004020c +.set CYREG_PRT2_INTSTAT, 0x40040210 +.set CYREG_PRT2_PC2, 0x40040218 +.set CYDEV_PRT3_BASE, 0x40040300 +.set CYDEV_PRT3_SIZE, 0x00000100 +.set CYREG_PRT3_DR, 0x40040300 +.set CYREG_PRT3_PS, 0x40040304 +.set CYREG_PRT3_PC, 0x40040308 +.set CYREG_PRT3_INTCFG, 0x4004030c +.set CYREG_PRT3_INTSTAT, 0x40040310 +.set CYREG_PRT3_PC2, 0x40040318 +.set CYDEV_PRT4_BASE, 0x40040400 +.set CYDEV_PRT4_SIZE, 0x00000100 +.set CYREG_PRT4_DR, 0x40040400 +.set CYREG_PRT4_PS, 0x40040404 +.set CYREG_PRT4_PC, 0x40040408 +.set CYREG_PRT4_INTCFG, 0x4004040c +.set CYREG_PRT4_INTSTAT, 0x40040410 +.set CYREG_PRT4_PC2, 0x40040418 +.set CYDEV_TCPWM_BASE, 0x40050000 +.set CYDEV_TCPWM_SIZE, 0x00001000 +.set CYREG_TCPWM_CTRL, 0x40050000 +.set CYFLD_TCPWM_COUNTER_ENABLED__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_ENABLED__SIZE, 0x00000008 +.set CYREG_TCPWM_CMD, 0x40050008 +.set CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_CAPTURE__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_RELOAD__OFFSET, 0x00000008 +.set CYFLD_TCPWM_COUNTER_RELOAD__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_STOP__OFFSET, 0x00000010 +.set CYFLD_TCPWM_COUNTER_STOP__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_START__OFFSET, 0x00000018 +.set CYFLD_TCPWM_COUNTER_START__SIZE, 0x00000008 +.set CYREG_TCPWM_INTR_CAUSE, 0x4005000c +.set CYFLD_TCPWM_COUNTER_INT__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_INT__SIZE, 0x00000008 +.set CYDEV_TCPWM_CNT0_BASE, 0x40050100 +.set CYDEV_TCPWM_CNT0_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT0_CTRL, 0x40050100 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET, 0x00000001 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET, 0x00000003 +.set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_GENERIC__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_GENERIC__SIZE, 0x00000008 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY1, 0x00000000 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY2, 0x00000001 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY4, 0x00000002 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY8, 0x00000003 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY16, 0x00000004 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY32, 0x00000005 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY64, 0x00000006 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY128, 0x00000007 +.set CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET, 0x00000010 +.set CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP, 0x00000000 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN, 0x00000001 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1, 0x00000002 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2, 0x00000003 +.set CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET, 0x00000012 +.set CYFLD_TCPWM_CNT_ONE_SHOT__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET, 0x00000014 +.set CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1, 0x00000000 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2, 0x00000001 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4, 0x00000002 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT, 0x00000001 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT, 0x00000002 +.set CYFLD_TCPWM_CNT_MODE__OFFSET, 0x00000018 +.set CYFLD_TCPWM_CNT_MODE__SIZE, 0x00000003 +.set CYVAL_TCPWM_CNT_MODE_TIMER, 0x00000000 +.set CYVAL_TCPWM_CNT_MODE_CAPTURE, 0x00000002 +.set CYVAL_TCPWM_CNT_MODE_QUAD, 0x00000003 +.set CYVAL_TCPWM_CNT_MODE_PWM, 0x00000004 +.set CYVAL_TCPWM_CNT_MODE_PWM_DT, 0x00000005 +.set CYVAL_TCPWM_CNT_MODE_PWM_PR, 0x00000006 +.set CYREG_TCPWM_CNT0_STATUS, 0x40050104 +.set CYFLD_TCPWM_CNT_DOWN__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_DOWN__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_RUNNING__OFFSET, 0x0000001f +.set CYFLD_TCPWM_CNT_RUNNING__SIZE, 0x00000001 +.set CYREG_TCPWM_CNT0_COUNTER, 0x40050108 +.set CYFLD_TCPWM_CNT_COUNTER__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_COUNTER__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_CC, 0x4005010c +.set CYFLD_TCPWM_CNT_CC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CC__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_CC_BUFF, 0x40050110 +.set CYREG_TCPWM_CNT0_PERIOD, 0x40050114 +.set CYFLD_TCPWM_CNT_PERIOD__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_PERIOD__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_PERIOD_BUFF, 0x40050118 +.set CYREG_TCPWM_CNT0_TR_CTRL0, 0x40050120 +.set CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_COUNT_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_STOP_SEL__OFFSET, 0x0000000c +.set CYFLD_TCPWM_CNT_STOP_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_START_SEL__OFFSET, 0x00000010 +.set CYFLD_TCPWM_CNT_START_SEL__SIZE, 0x00000004 +.set CYREG_TCPWM_CNT0_TR_CTRL1, 0x40050124 +.set CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET, 0x00000006 +.set CYFLD_TCPWM_CNT_STOP_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_START_EDGE__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_START_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET, 0x00000003 +.set CYREG_TCPWM_CNT0_TR_CTRL2, 0x40050128 +.set CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE, 0x00000003 +.set CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE, 0x00000003 +.set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE, 0x00000003 +.set CYREG_TCPWM_CNT0_INTR, 0x40050130 +.set CYFLD_TCPWM_CNT_TC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_TC__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_CC_MATCH__OFFSET, 0x00000001 +.set CYFLD_TCPWM_CNT_CC_MATCH__SIZE, 0x00000001 +.set CYREG_TCPWM_CNT0_INTR_SET, 0x40050134 +.set CYREG_TCPWM_CNT0_INTR_MASK, 0x40050138 +.set CYREG_TCPWM_CNT0_INTR_MASKED, 0x4005013c +.set CYDEV_TCPWM_CNT1_BASE, 0x40050140 +.set CYDEV_TCPWM_CNT1_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT1_CTRL, 0x40050140 +.set CYREG_TCPWM_CNT1_STATUS, 0x40050144 +.set CYREG_TCPWM_CNT1_COUNTER, 0x40050148 +.set CYREG_TCPWM_CNT1_CC, 0x4005014c +.set CYREG_TCPWM_CNT1_CC_BUFF, 0x40050150 +.set CYREG_TCPWM_CNT1_PERIOD, 0x40050154 +.set CYREG_TCPWM_CNT1_PERIOD_BUFF, 0x40050158 +.set CYREG_TCPWM_CNT1_TR_CTRL0, 0x40050160 +.set CYREG_TCPWM_CNT1_TR_CTRL1, 0x40050164 +.set CYREG_TCPWM_CNT1_TR_CTRL2, 0x40050168 +.set CYREG_TCPWM_CNT1_INTR, 0x40050170 +.set CYREG_TCPWM_CNT1_INTR_SET, 0x40050174 +.set CYREG_TCPWM_CNT1_INTR_MASK, 0x40050178 +.set CYREG_TCPWM_CNT1_INTR_MASKED, 0x4005017c +.set CYDEV_TCPWM_CNT2_BASE, 0x40050180 +.set CYDEV_TCPWM_CNT2_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT2_CTRL, 0x40050180 +.set CYREG_TCPWM_CNT2_STATUS, 0x40050184 +.set CYREG_TCPWM_CNT2_COUNTER, 0x40050188 +.set CYREG_TCPWM_CNT2_CC, 0x4005018c +.set CYREG_TCPWM_CNT2_CC_BUFF, 0x40050190 +.set CYREG_TCPWM_CNT2_PERIOD, 0x40050194 +.set CYREG_TCPWM_CNT2_PERIOD_BUFF, 0x40050198 +.set CYREG_TCPWM_CNT2_TR_CTRL0, 0x400501a0 +.set CYREG_TCPWM_CNT2_TR_CTRL1, 0x400501a4 +.set CYREG_TCPWM_CNT2_TR_CTRL2, 0x400501a8 +.set CYREG_TCPWM_CNT2_INTR, 0x400501b0 +.set CYREG_TCPWM_CNT2_INTR_SET, 0x400501b4 +.set CYREG_TCPWM_CNT2_INTR_MASK, 0x400501b8 +.set CYREG_TCPWM_CNT2_INTR_MASKED, 0x400501bc +.set CYDEV_TCPWM_CNT3_BASE, 0x400501c0 +.set CYDEV_TCPWM_CNT3_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT3_CTRL, 0x400501c0 +.set CYREG_TCPWM_CNT3_STATUS, 0x400501c4 +.set CYREG_TCPWM_CNT3_COUNTER, 0x400501c8 +.set CYREG_TCPWM_CNT3_CC, 0x400501cc +.set CYREG_TCPWM_CNT3_CC_BUFF, 0x400501d0 +.set CYREG_TCPWM_CNT3_PERIOD, 0x400501d4 +.set CYREG_TCPWM_CNT3_PERIOD_BUFF, 0x400501d8 +.set CYREG_TCPWM_CNT3_TR_CTRL0, 0x400501e0 +.set CYREG_TCPWM_CNT3_TR_CTRL1, 0x400501e4 +.set CYREG_TCPWM_CNT3_TR_CTRL2, 0x400501e8 +.set CYREG_TCPWM_CNT3_INTR, 0x400501f0 +.set CYREG_TCPWM_CNT3_INTR_SET, 0x400501f4 +.set CYREG_TCPWM_CNT3_INTR_MASK, 0x400501f8 +.set CYREG_TCPWM_CNT3_INTR_MASKED, 0x400501fc +.set CYDEV_SCB0_BASE, 0x40060000 +.set CYDEV_SCB0_SIZE, 0x00010000 +.set CYREG_SCB0_CTRL, 0x40060000 +.set CYFLD_SCB_OVS__OFFSET, 0x00000000 +.set CYFLD_SCB_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_EC_AM_MODE__OFFSET, 0x00000008 +.set CYFLD_SCB_EC_AM_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_EC_OP_MODE__OFFSET, 0x00000009 +.set CYFLD_SCB_EC_OP_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_MODE__OFFSET, 0x0000000a +.set CYFLD_SCB_EZ_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_ADDR_ACCEPT__OFFSET, 0x00000010 +.set CYFLD_SCB_ADDR_ACCEPT__SIZE, 0x00000001 +.set CYFLD_SCB_BLOCK__OFFSET, 0x00000011 +.set CYFLD_SCB_BLOCK__SIZE, 0x00000001 +.set CYFLD_SCB_MODE__OFFSET, 0x00000018 +.set CYFLD_SCB_MODE__SIZE, 0x00000002 +.set CYVAL_SCB_MODE_I2C, 0x00000000 +.set CYVAL_SCB_MODE_SPI, 0x00000001 +.set CYVAL_SCB_MODE_UART, 0x00000002 +.set CYFLD_SCB_ENABLED__OFFSET, 0x0000001f +.set CYFLD_SCB_ENABLED__SIZE, 0x00000001 +.set CYREG_SCB0_STATUS, 0x40060004 +.set CYFLD_SCB_EC_BUSY__OFFSET, 0x00000000 +.set CYFLD_SCB_EC_BUSY__SIZE, 0x00000001 +.set CYREG_SCB0_SPI_CTRL, 0x40060020 +.set CYFLD_SCB_CONTINUOUS__OFFSET, 0x00000000 +.set CYFLD_SCB_CONTINUOUS__SIZE, 0x00000001 +.set CYFLD_SCB_SELECT_PRECEDE__OFFSET, 0x00000001 +.set CYFLD_SCB_SELECT_PRECEDE__SIZE, 0x00000001 +.set CYFLD_SCB_CPHA__OFFSET, 0x00000002 +.set CYFLD_SCB_CPHA__SIZE, 0x00000001 +.set CYFLD_SCB_CPOL__OFFSET, 0x00000003 +.set CYFLD_SCB_CPOL__SIZE, 0x00000001 +.set CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET, 0x00000004 +.set CYFLD_SCB_LATE_MISO_SAMPLE__SIZE, 0x00000001 +.set CYFLD_SCB_LOOPBACK__OFFSET, 0x00000010 +.set CYFLD_SCB_LOOPBACK__SIZE, 0x00000001 +.set CYFLD_SCB_SLAVE_SELECT__OFFSET, 0x0000001a +.set CYFLD_SCB_SLAVE_SELECT__SIZE, 0x00000002 +.set CYFLD_SCB_MASTER_MODE__OFFSET, 0x0000001f +.set CYFLD_SCB_MASTER_MODE__SIZE, 0x00000001 +.set CYREG_SCB0_SPI_STATUS, 0x40060024 +.set CYFLD_SCB_BUS_BUSY__OFFSET, 0x00000000 +.set CYFLD_SCB_BUS_BUSY__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_ADDR__OFFSET, 0x00000008 +.set CYFLD_SCB_EZ_ADDR__SIZE, 0x00000008 +.set CYREG_SCB0_UART_CTRL, 0x40060040 +.set CYREG_SCB0_UART_TX_CTRL, 0x40060044 +.set CYFLD_SCB_STOP_BITS__OFFSET, 0x00000000 +.set CYFLD_SCB_STOP_BITS__SIZE, 0x00000003 +.set CYFLD_SCB_PARITY__OFFSET, 0x00000004 +.set CYFLD_SCB_PARITY__SIZE, 0x00000001 +.set CYFLD_SCB_PARITY_ENABLED__OFFSET, 0x00000005 +.set CYFLD_SCB_PARITY_ENABLED__SIZE, 0x00000001 +.set CYFLD_SCB_RETRY_ON_NACK__OFFSET, 0x00000008 +.set CYFLD_SCB_RETRY_ON_NACK__SIZE, 0x00000001 +.set CYREG_SCB0_UART_RX_CTRL, 0x40060048 +.set CYFLD_SCB_POLARITY__OFFSET, 0x00000006 +.set CYFLD_SCB_POLARITY__SIZE, 0x00000001 +.set CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET, 0x00000009 +.set CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_MP_MODE__OFFSET, 0x0000000a +.set CYFLD_SCB_MP_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_LIN_MODE__OFFSET, 0x0000000c +.set CYFLD_SCB_LIN_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_SKIP_START__OFFSET, 0x0000000d +.set CYFLD_SCB_SKIP_START__SIZE, 0x00000001 +.set CYFLD_SCB_BREAK_WIDTH__OFFSET, 0x00000010 +.set CYFLD_SCB_BREAK_WIDTH__SIZE, 0x00000004 +.set CYREG_SCB0_UART_RX_STATUS, 0x4006004c +.set CYFLD_SCB_BR_COUNTER__OFFSET, 0x00000000 +.set CYFLD_SCB_BR_COUNTER__SIZE, 0x0000000c +.set CYREG_SCB0_I2C_CTRL, 0x40060060 +.set CYFLD_SCB_HIGH_PHASE_OVS__OFFSET, 0x00000000 +.set CYFLD_SCB_HIGH_PHASE_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_LOW_PHASE_OVS__OFFSET, 0x00000004 +.set CYFLD_SCB_LOW_PHASE_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_M_READY_DATA_ACK__OFFSET, 0x00000008 +.set CYFLD_SCB_M_READY_DATA_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET, 0x00000009 +.set CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_GENERAL_IGNORE__OFFSET, 0x0000000b +.set CYFLD_SCB_S_GENERAL_IGNORE__SIZE, 0x00000001 +.set CYFLD_SCB_S_READY_ADDR_ACK__OFFSET, 0x0000000c +.set CYFLD_SCB_S_READY_ADDR_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_READY_DATA_ACK__OFFSET, 0x0000000d +.set CYFLD_SCB_S_READY_DATA_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET, 0x0000000e +.set CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET, 0x0000000f +.set CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_SLAVE_MODE__OFFSET, 0x0000001e +.set CYFLD_SCB_SLAVE_MODE__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_STATUS, 0x40060064 +.set CYFLD_SCB_S_READ__OFFSET, 0x00000004 +.set CYFLD_SCB_S_READ__SIZE, 0x00000001 +.set CYFLD_SCB_M_READ__OFFSET, 0x00000005 +.set CYFLD_SCB_M_READ__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_M_CMD, 0x40060068 +.set CYFLD_SCB_M_START__OFFSET, 0x00000000 +.set CYFLD_SCB_M_START__SIZE, 0x00000001 +.set CYFLD_SCB_M_START_ON_IDLE__OFFSET, 0x00000001 +.set CYFLD_SCB_M_START_ON_IDLE__SIZE, 0x00000001 +.set CYFLD_SCB_M_ACK__OFFSET, 0x00000002 +.set CYFLD_SCB_M_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_NACK__OFFSET, 0x00000003 +.set CYFLD_SCB_M_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_STOP__OFFSET, 0x00000004 +.set CYFLD_SCB_M_STOP__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_S_CMD, 0x4006006c +.set CYFLD_SCB_S_ACK__OFFSET, 0x00000000 +.set CYFLD_SCB_S_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NACK__OFFSET, 0x00000001 +.set CYFLD_SCB_S_NACK__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_CFG, 0x40060070 +.set CYFLD_SCB_SDA_FILT_HYS__OFFSET, 0x00000000 +.set CYFLD_SCB_SDA_FILT_HYS__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_TRIM__OFFSET, 0x00000002 +.set CYFLD_SCB_SDA_FILT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SCL_FILT_HYS__OFFSET, 0x00000004 +.set CYFLD_SCB_SCL_FILT_HYS__SIZE, 0x00000002 +.set CYFLD_SCB_SCL_FILT_TRIM__OFFSET, 0x00000006 +.set CYFLD_SCB_SCL_FILT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET, 0x00000008 +.set CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET, 0x0000000a +.set CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_HS__OFFSET, 0x00000010 +.set CYFLD_SCB_SDA_FILT_HS__SIZE, 0x00000001 +.set CYFLD_SCB_SDA_FILT_ENABLED__OFFSET, 0x00000011 +.set CYFLD_SCB_SDA_FILT_ENABLED__SIZE, 0x00000001 +.set CYFLD_SCB_SCL_FILT_HS__OFFSET, 0x00000018 +.set CYFLD_SCB_SCL_FILT_HS__SIZE, 0x00000001 +.set CYFLD_SCB_SCL_FILT_ENABLED__OFFSET, 0x00000019 +.set CYFLD_SCB_SCL_FILT_ENABLED__SIZE, 0x00000001 +.set CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET, 0x0000001a +.set CYFLD_SCB_SDA_FILT_OUT_HS__SIZE, 0x00000001 +.set CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET, 0x0000001b +.set CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE, 0x00000001 +.set CYREG_SCB0_BIST_CONTROL, 0x40060100 +.set CYFLD_SCB_RAM_ADDR__OFFSET, 0x00000000 +.set CYFLD_SCB_RAM_ADDR__SIZE, 0x00000005 +.set CYFLD_SCB_RAM_OP1__OFFSET, 0x00000010 +.set CYFLD_SCB_RAM_OP1__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OP2__OFFSET, 0x00000012 +.set CYFLD_SCB_RAM_OP2__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OP3__OFFSET, 0x00000014 +.set CYFLD_SCB_RAM_OP3__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OP4__OFFSET, 0x00000016 +.set CYFLD_SCB_RAM_OP4__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OPCNT__OFFSET, 0x00000018 +.set CYFLD_SCB_RAM_OPCNT__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_PREADR__OFFSET, 0x0000001a +.set CYFLD_SCB_RAM_PREADR__SIZE, 0x00000001 +.set CYFLD_SCB_RAM_WORD__OFFSET, 0x0000001b +.set CYFLD_SCB_RAM_WORD__SIZE, 0x00000001 +.set CYFLD_SCB_RAM_FAIL__OFFSET, 0x0000001c +.set CYFLD_SCB_RAM_FAIL__SIZE, 0x00000001 +.set CYFLD_SCB_RAM_GO__OFFSET, 0x0000001d +.set CYFLD_SCB_RAM_GO__SIZE, 0x00000001 +.set CYREG_SCB0_BIST_DATA, 0x40060104 +.set CYFLD_SCB_RAM_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_RAM_DATA__SIZE, 0x00000010 +.set CYREG_SCB0_TX_CTRL, 0x40060200 +.set CYFLD_SCB_DATA_WIDTH__OFFSET, 0x00000000 +.set CYFLD_SCB_DATA_WIDTH__SIZE, 0x00000004 +.set CYFLD_SCB_MSB_FIRST__OFFSET, 0x00000008 +.set CYFLD_SCB_MSB_FIRST__SIZE, 0x00000001 +.set CYREG_SCB0_TX_FIFO_CTRL, 0x40060204 +.set CYFLD_SCB_TRIGGER_LEVEL__OFFSET, 0x00000000 +.set CYFLD_SCB_TRIGGER_LEVEL__SIZE, 0x00000003 +.set CYFLD_SCB_CLEAR__OFFSET, 0x00000010 +.set CYFLD_SCB_CLEAR__SIZE, 0x00000001 +.set CYFLD_SCB_FREEZE__OFFSET, 0x00000011 +.set CYFLD_SCB_FREEZE__SIZE, 0x00000001 +.set CYREG_SCB0_TX_FIFO_STATUS, 0x40060208 +.set CYFLD_SCB_USED__OFFSET, 0x00000000 +.set CYFLD_SCB_USED__SIZE, 0x00000004 +.set CYFLD_SCB_SR_VALID__OFFSET, 0x0000000f +.set CYFLD_SCB_SR_VALID__SIZE, 0x00000001 +.set CYFLD_SCB_RD_PTR__OFFSET, 0x00000010 +.set CYFLD_SCB_RD_PTR__SIZE, 0x00000003 +.set CYFLD_SCB_WR_PTR__OFFSET, 0x00000018 +.set CYFLD_SCB_WR_PTR__SIZE, 0x00000003 +.set CYREG_SCB0_TX_FIFO_WR, 0x40060240 +.set CYFLD_SCB_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_DATA__SIZE, 0x00000010 +.set CYREG_SCB0_RX_CTRL, 0x40060300 +.set CYFLD_SCB_MEDIAN__OFFSET, 0x00000009 +.set CYFLD_SCB_MEDIAN__SIZE, 0x00000001 +.set CYREG_SCB0_RX_FIFO_CTRL, 0x40060304 +.set CYREG_SCB0_RX_FIFO_STATUS, 0x40060308 +.set CYREG_SCB0_RX_MATCH, 0x40060310 +.set CYFLD_SCB_ADDR__OFFSET, 0x00000000 +.set CYFLD_SCB_ADDR__SIZE, 0x00000008 +.set CYFLD_SCB_MASK__OFFSET, 0x00000010 +.set CYFLD_SCB_MASK__SIZE, 0x00000008 +.set CYREG_SCB0_RX_FIFO_RD, 0x40060340 +.set CYREG_SCB0_RX_FIFO_RD_SILENT, 0x40060344 +.set CYREG_SCB0_EZ_DATA00, 0x40060400 +.set CYFLD_SCB_EZ_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_EZ_DATA__SIZE, 0x00000008 +.set CYREG_SCB0_EZ_DATA01, 0x40060404 +.set CYREG_SCB0_EZ_DATA02, 0x40060408 +.set CYREG_SCB0_EZ_DATA03, 0x4006040c +.set CYREG_SCB0_EZ_DATA04, 0x40060410 +.set CYREG_SCB0_EZ_DATA05, 0x40060414 +.set CYREG_SCB0_EZ_DATA06, 0x40060418 +.set CYREG_SCB0_EZ_DATA07, 0x4006041c +.set CYREG_SCB0_EZ_DATA08, 0x40060420 +.set CYREG_SCB0_EZ_DATA09, 0x40060424 +.set CYREG_SCB0_EZ_DATA10, 0x40060428 +.set CYREG_SCB0_EZ_DATA11, 0x4006042c +.set CYREG_SCB0_EZ_DATA12, 0x40060430 +.set CYREG_SCB0_EZ_DATA13, 0x40060434 +.set CYREG_SCB0_EZ_DATA14, 0x40060438 +.set CYREG_SCB0_EZ_DATA15, 0x4006043c +.set CYREG_SCB0_EZ_DATA16, 0x40060440 +.set CYREG_SCB0_EZ_DATA17, 0x40060444 +.set CYREG_SCB0_EZ_DATA18, 0x40060448 +.set CYREG_SCB0_EZ_DATA19, 0x4006044c +.set CYREG_SCB0_EZ_DATA20, 0x40060450 +.set CYREG_SCB0_EZ_DATA21, 0x40060454 +.set CYREG_SCB0_EZ_DATA22, 0x40060458 +.set CYREG_SCB0_EZ_DATA23, 0x4006045c +.set CYREG_SCB0_EZ_DATA24, 0x40060460 +.set CYREG_SCB0_EZ_DATA25, 0x40060464 +.set CYREG_SCB0_EZ_DATA26, 0x40060468 +.set CYREG_SCB0_EZ_DATA27, 0x4006046c +.set CYREG_SCB0_EZ_DATA28, 0x40060470 +.set CYREG_SCB0_EZ_DATA29, 0x40060474 +.set CYREG_SCB0_EZ_DATA30, 0x40060478 +.set CYREG_SCB0_EZ_DATA31, 0x4006047c +.set CYREG_SCB0_INTR_CAUSE, 0x40060e00 +.set CYFLD_SCB_M__OFFSET, 0x00000000 +.set CYFLD_SCB_M__SIZE, 0x00000001 +.set CYFLD_SCB_S__OFFSET, 0x00000001 +.set CYFLD_SCB_S__SIZE, 0x00000001 +.set CYFLD_SCB_TX__OFFSET, 0x00000002 +.set CYFLD_SCB_TX__SIZE, 0x00000001 +.set CYFLD_SCB_RX__OFFSET, 0x00000003 +.set CYFLD_SCB_RX__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_EC__OFFSET, 0x00000004 +.set CYFLD_SCB_I2C_EC__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EC__OFFSET, 0x00000005 +.set CYFLD_SCB_SPI_EC__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_I2C_EC, 0x40060e80 +.set CYFLD_SCB_WAKE_UP__OFFSET, 0x00000000 +.set CYFLD_SCB_WAKE_UP__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_STOP__OFFSET, 0x00000001 +.set CYFLD_SCB_EZ_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_WRITE_STOP__OFFSET, 0x00000002 +.set CYFLD_SCB_EZ_WRITE_STOP__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_I2C_EC_MASK, 0x40060e88 +.set CYREG_SCB0_INTR_I2C_EC_MASKED, 0x40060e8c +.set CYREG_SCB0_INTR_SPI_EC, 0x40060ec0 +.set CYREG_SCB0_INTR_SPI_EC_MASK, 0x40060ec8 +.set CYREG_SCB0_INTR_SPI_EC_MASKED, 0x40060ecc +.set CYREG_SCB0_INTR_M, 0x40060f00 +.set CYFLD_SCB_I2C_ARB_LOST__OFFSET, 0x00000000 +.set CYFLD_SCB_I2C_ARB_LOST__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_NACK__OFFSET, 0x00000001 +.set CYFLD_SCB_I2C_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_ACK__OFFSET, 0x00000002 +.set CYFLD_SCB_I2C_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_STOP__OFFSET, 0x00000004 +.set CYFLD_SCB_I2C_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_BUS_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_I2C_BUS_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_DONE__OFFSET, 0x00000009 +.set CYFLD_SCB_SPI_DONE__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_M_SET, 0x40060f04 +.set CYREG_SCB0_INTR_M_MASK, 0x40060f08 +.set CYREG_SCB0_INTR_M_MASKED, 0x40060f0c +.set CYREG_SCB0_INTR_S, 0x40060f40 +.set CYFLD_SCB_I2C_WRITE_STOP__OFFSET, 0x00000003 +.set CYFLD_SCB_I2C_WRITE_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_START__OFFSET, 0x00000005 +.set CYFLD_SCB_I2C_START__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_ADDR_MATCH__OFFSET, 0x00000006 +.set CYFLD_SCB_I2C_ADDR_MATCH__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_GENERAL__OFFSET, 0x00000007 +.set CYFLD_SCB_I2C_GENERAL__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET, 0x00000009 +.set CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EZ_STOP__OFFSET, 0x0000000a +.set CYFLD_SCB_SPI_EZ_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_BUS_ERROR__OFFSET, 0x0000000b +.set CYFLD_SCB_SPI_BUS_ERROR__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_S_SET, 0x40060f44 +.set CYREG_SCB0_INTR_S_MASK, 0x40060f48 +.set CYREG_SCB0_INTR_S_MASKED, 0x40060f4c +.set CYREG_SCB0_INTR_TX, 0x40060f80 +.set CYFLD_SCB_TRIGGER__OFFSET, 0x00000000 +.set CYFLD_SCB_TRIGGER__SIZE, 0x00000001 +.set CYFLD_SCB_NOT_FULL__OFFSET, 0x00000001 +.set CYFLD_SCB_NOT_FULL__SIZE, 0x00000001 +.set CYFLD_SCB_EMPTY__OFFSET, 0x00000004 +.set CYFLD_SCB_EMPTY__SIZE, 0x00000001 +.set CYFLD_SCB_OVERFLOW__OFFSET, 0x00000005 +.set CYFLD_SCB_OVERFLOW__SIZE, 0x00000001 +.set CYFLD_SCB_UNDERFLOW__OFFSET, 0x00000006 +.set CYFLD_SCB_UNDERFLOW__SIZE, 0x00000001 +.set CYFLD_SCB_BLOCKED__OFFSET, 0x00000007 +.set CYFLD_SCB_BLOCKED__SIZE, 0x00000001 +.set CYFLD_SCB_UART_NACK__OFFSET, 0x00000008 +.set CYFLD_SCB_UART_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_UART_DONE__OFFSET, 0x00000009 +.set CYFLD_SCB_UART_DONE__SIZE, 0x00000001 +.set CYFLD_SCB_UART_ARB_LOST__OFFSET, 0x0000000a +.set CYFLD_SCB_UART_ARB_LOST__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_TX_SET, 0x40060f84 +.set CYREG_SCB0_INTR_TX_MASK, 0x40060f88 +.set CYREG_SCB0_INTR_TX_MASKED, 0x40060f8c +.set CYREG_SCB0_INTR_RX, 0x40060fc0 +.set CYFLD_SCB_NOT_EMPTY__OFFSET, 0x00000002 +.set CYFLD_SCB_NOT_EMPTY__SIZE, 0x00000001 +.set CYFLD_SCB_FULL__OFFSET, 0x00000003 +.set CYFLD_SCB_FULL__SIZE, 0x00000001 +.set CYFLD_SCB_FRAME_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_FRAME_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_PARITY_ERROR__OFFSET, 0x00000009 +.set CYFLD_SCB_PARITY_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_BAUD_DETECT__OFFSET, 0x0000000a +.set CYFLD_SCB_BAUD_DETECT__SIZE, 0x00000001 +.set CYFLD_SCB_BREAK_DETECT__OFFSET, 0x0000000b +.set CYFLD_SCB_BREAK_DETECT__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_RX_SET, 0x40060fc4 +.set CYREG_SCB0_INTR_RX_MASK, 0x40060fc8 +.set CYREG_SCB0_INTR_RX_MASKED, 0x40060fcc +.set CYDEV_SCB1_BASE, 0x40070000 +.set CYDEV_SCB1_SIZE, 0x00010000 +.set CYREG_SCB1_CTRL, 0x40070000 +.set CYREG_SCB1_STATUS, 0x40070004 +.set CYREG_SCB1_SPI_CTRL, 0x40070020 +.set CYREG_SCB1_SPI_STATUS, 0x40070024 +.set CYREG_SCB1_UART_CTRL, 0x40070040 +.set CYREG_SCB1_UART_TX_CTRL, 0x40070044 +.set CYREG_SCB1_UART_RX_CTRL, 0x40070048 +.set CYREG_SCB1_UART_RX_STATUS, 0x4007004c +.set CYREG_SCB1_I2C_CTRL, 0x40070060 +.set CYREG_SCB1_I2C_STATUS, 0x40070064 +.set CYREG_SCB1_I2C_M_CMD, 0x40070068 +.set CYREG_SCB1_I2C_S_CMD, 0x4007006c +.set CYREG_SCB1_I2C_CFG, 0x40070070 +.set CYREG_SCB1_BIST_CONTROL, 0x40070100 +.set CYREG_SCB1_BIST_DATA, 0x40070104 +.set CYREG_SCB1_TX_CTRL, 0x40070200 +.set CYREG_SCB1_TX_FIFO_CTRL, 0x40070204 +.set CYREG_SCB1_TX_FIFO_STATUS, 0x40070208 +.set CYREG_SCB1_TX_FIFO_WR, 0x40070240 +.set CYREG_SCB1_RX_CTRL, 0x40070300 +.set CYREG_SCB1_RX_FIFO_CTRL, 0x40070304 +.set CYREG_SCB1_RX_FIFO_STATUS, 0x40070308 +.set CYREG_SCB1_RX_MATCH, 0x40070310 +.set CYREG_SCB1_RX_FIFO_RD, 0x40070340 +.set CYREG_SCB1_RX_FIFO_RD_SILENT, 0x40070344 +.set CYREG_SCB1_EZ_DATA00, 0x40070400 +.set CYREG_SCB1_EZ_DATA01, 0x40070404 +.set CYREG_SCB1_EZ_DATA02, 0x40070408 +.set CYREG_SCB1_EZ_DATA03, 0x4007040c +.set CYREG_SCB1_EZ_DATA04, 0x40070410 +.set CYREG_SCB1_EZ_DATA05, 0x40070414 +.set CYREG_SCB1_EZ_DATA06, 0x40070418 +.set CYREG_SCB1_EZ_DATA07, 0x4007041c +.set CYREG_SCB1_EZ_DATA08, 0x40070420 +.set CYREG_SCB1_EZ_DATA09, 0x40070424 +.set CYREG_SCB1_EZ_DATA10, 0x40070428 +.set CYREG_SCB1_EZ_DATA11, 0x4007042c +.set CYREG_SCB1_EZ_DATA12, 0x40070430 +.set CYREG_SCB1_EZ_DATA13, 0x40070434 +.set CYREG_SCB1_EZ_DATA14, 0x40070438 +.set CYREG_SCB1_EZ_DATA15, 0x4007043c +.set CYREG_SCB1_EZ_DATA16, 0x40070440 +.set CYREG_SCB1_EZ_DATA17, 0x40070444 +.set CYREG_SCB1_EZ_DATA18, 0x40070448 +.set CYREG_SCB1_EZ_DATA19, 0x4007044c +.set CYREG_SCB1_EZ_DATA20, 0x40070450 +.set CYREG_SCB1_EZ_DATA21, 0x40070454 +.set CYREG_SCB1_EZ_DATA22, 0x40070458 +.set CYREG_SCB1_EZ_DATA23, 0x4007045c +.set CYREG_SCB1_EZ_DATA24, 0x40070460 +.set CYREG_SCB1_EZ_DATA25, 0x40070464 +.set CYREG_SCB1_EZ_DATA26, 0x40070468 +.set CYREG_SCB1_EZ_DATA27, 0x4007046c +.set CYREG_SCB1_EZ_DATA28, 0x40070470 +.set CYREG_SCB1_EZ_DATA29, 0x40070474 +.set CYREG_SCB1_EZ_DATA30, 0x40070478 +.set CYREG_SCB1_EZ_DATA31, 0x4007047c +.set CYREG_SCB1_INTR_CAUSE, 0x40070e00 +.set CYREG_SCB1_INTR_I2C_EC, 0x40070e80 +.set CYREG_SCB1_INTR_I2C_EC_MASK, 0x40070e88 +.set CYREG_SCB1_INTR_I2C_EC_MASKED, 0x40070e8c +.set CYREG_SCB1_INTR_SPI_EC, 0x40070ec0 +.set CYREG_SCB1_INTR_SPI_EC_MASK, 0x40070ec8 +.set CYREG_SCB1_INTR_SPI_EC_MASKED, 0x40070ecc +.set CYREG_SCB1_INTR_M, 0x40070f00 +.set CYREG_SCB1_INTR_M_SET, 0x40070f04 +.set CYREG_SCB1_INTR_M_MASK, 0x40070f08 +.set CYREG_SCB1_INTR_M_MASKED, 0x40070f0c +.set CYREG_SCB1_INTR_S, 0x40070f40 +.set CYREG_SCB1_INTR_S_SET, 0x40070f44 +.set CYREG_SCB1_INTR_S_MASK, 0x40070f48 +.set CYREG_SCB1_INTR_S_MASKED, 0x40070f4c +.set CYREG_SCB1_INTR_TX, 0x40070f80 +.set CYREG_SCB1_INTR_TX_SET, 0x40070f84 +.set CYREG_SCB1_INTR_TX_MASK, 0x40070f88 +.set CYREG_SCB1_INTR_TX_MASKED, 0x40070f8c +.set CYREG_SCB1_INTR_RX, 0x40070fc0 +.set CYREG_SCB1_INTR_RX_SET, 0x40070fc4 +.set CYREG_SCB1_INTR_RX_MASK, 0x40070fc8 +.set CYREG_SCB1_INTR_RX_MASKED, 0x40070fcc +.set CYDEV_CSD_BASE, 0x40080000 +.set CYDEV_CSD_SIZE, 0x00010000 +.set CYREG_CSD_ID, 0x40080000 +.set CYFLD_CSD_ID__OFFSET, 0x00000000 +.set CYFLD_CSD_ID__SIZE, 0x00000010 +.set CYFLD_CSD_REVISION__OFFSET, 0x00000010 +.set CYFLD_CSD_REVISION__SIZE, 0x00000010 +.set CYREG_CSD_CONFIG, 0x40080004 +.set CYFLD_CSD_DSI_SAMPLE_EN__OFFSET, 0x00000000 +.set CYFLD_CSD_DSI_SAMPLE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_SAMPLE_SYNC__OFFSET, 0x00000001 +.set CYFLD_CSD_SAMPLE_SYNC__SIZE, 0x00000001 +.set CYFLD_CSD_PRS_CLEAR__OFFSET, 0x00000005 +.set CYFLD_CSD_PRS_CLEAR__SIZE, 0x00000001 +.set CYFLD_CSD_PRS_SELECT__OFFSET, 0x00000006 +.set CYFLD_CSD_PRS_SELECT__SIZE, 0x00000001 +.set CYVAL_CSD_PRS_SELECT_DIV2, 0x00000000 +.set CYVAL_CSD_PRS_SELECT_PRS, 0x00000001 +.set CYFLD_CSD_PRS_12_8__OFFSET, 0x00000007 +.set CYFLD_CSD_PRS_12_8__SIZE, 0x00000001 +.set CYVAL_CSD_PRS_12_8_8B, 0x00000000 +.set CYVAL_CSD_PRS_12_8_12B, 0x00000001 +.set CYFLD_CSD_DSI_SENSE_EN__OFFSET, 0x00000008 +.set CYFLD_CSD_DSI_SENSE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_SHIELD_DELAY__OFFSET, 0x00000009 +.set CYFLD_CSD_SHIELD_DELAY__SIZE, 0x00000002 +.set CYFLD_CSD_SENSE_COMP_BW__OFFSET, 0x0000000b +.set CYFLD_CSD_SENSE_COMP_BW__SIZE, 0x00000001 +.set CYVAL_CSD_SENSE_COMP_BW_LOW, 0x00000000 +.set CYVAL_CSD_SENSE_COMP_BW_HIGH, 0x00000001 +.set CYFLD_CSD_SENSE_EN__OFFSET, 0x0000000c +.set CYFLD_CSD_SENSE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_REFBUF_EN__OFFSET, 0x0000000d +.set CYFLD_CSD_REFBUF_EN__SIZE, 0x00000001 +.set CYFLD_CSD_COMP_MODE__OFFSET, 0x0000000e +.set CYFLD_CSD_COMP_MODE__SIZE, 0x00000001 +.set CYVAL_CSD_COMP_MODE_CHARGE_BUF, 0x00000000 +.set CYVAL_CSD_COMP_MODE_CHARGE_IO, 0x00000001 +.set CYFLD_CSD_COMP_PIN__OFFSET, 0x0000000f +.set CYFLD_CSD_COMP_PIN__SIZE, 0x00000001 +.set CYVAL_CSD_COMP_PIN_CHANNEL1, 0x00000000 +.set CYVAL_CSD_COMP_PIN_CHANNEL2, 0x00000001 +.set CYFLD_CSD_POLARITY__OFFSET, 0x00000010 +.set CYFLD_CSD_POLARITY__SIZE, 0x00000001 +.set CYVAL_CSD_POLARITY_VSSIO, 0x00000000 +.set CYVAL_CSD_POLARITY_VDDIO, 0x00000001 +.set CYFLD_CSD_POLARITY2__OFFSET, 0x00000011 +.set CYFLD_CSD_POLARITY2__SIZE, 0x00000001 +.set CYVAL_CSD_POLARITY2_VSSIO, 0x00000000 +.set CYVAL_CSD_POLARITY2_VDDIO, 0x00000001 +.set CYFLD_CSD_MUTUAL_CAP__OFFSET, 0x00000012 +.set CYFLD_CSD_MUTUAL_CAP__SIZE, 0x00000001 +.set CYVAL_CSD_MUTUAL_CAP_SELFCAP, 0x00000000 +.set CYVAL_CSD_MUTUAL_CAP_MUTUALCAP, 0x00000001 +.set CYFLD_CSD_SENSE_COMP_EN__OFFSET, 0x00000013 +.set CYFLD_CSD_SENSE_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CSD_REBUF_OUTSEL__OFFSET, 0x00000015 +.set CYFLD_CSD_REBUF_OUTSEL__SIZE, 0x00000001 +.set CYVAL_CSD_REBUF_OUTSEL_AMUXA, 0x00000000 +.set CYVAL_CSD_REBUF_OUTSEL_AMUXB, 0x00000001 +.set CYFLD_CSD_SENSE_INSEL__OFFSET, 0x00000016 +.set CYFLD_CSD_SENSE_INSEL__SIZE, 0x00000001 +.set CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1, 0x00000000 +.set CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA, 0x00000001 +.set CYFLD_CSD_REFBUF_DRV__OFFSET, 0x00000017 +.set CYFLD_CSD_REFBUF_DRV__SIZE, 0x00000002 +.set CYVAL_CSD_REFBUF_DRV_OFF, 0x00000000 +.set CYVAL_CSD_REFBUF_DRV_DRV_1, 0x00000001 +.set CYVAL_CSD_REFBUF_DRV_DRV_2, 0x00000002 +.set CYVAL_CSD_REFBUF_DRV_DRV_3, 0x00000003 +.set CYFLD_CSD_DDFTSEL__OFFSET, 0x0000001a +.set CYFLD_CSD_DDFTSEL__SIZE, 0x00000003 +.set CYVAL_CSD_DDFTSEL_NORMAL, 0x00000000 +.set CYVAL_CSD_DDFTSEL_CSD_SENSE, 0x00000001 +.set CYVAL_CSD_DDFTSEL_CSD_SHIELD, 0x00000002 +.set CYVAL_CSD_DDFTSEL_CLK_SAMPLE, 0x00000003 +.set CYVAL_CSD_DDFTSEL_COMP_OUT, 0x00000004 +.set CYFLD_CSD_ADFTEN__OFFSET, 0x0000001d +.set CYFLD_CSD_ADFTEN__SIZE, 0x00000001 +.set CYFLD_CSD_DDFTCOMP__OFFSET, 0x0000001e +.set CYFLD_CSD_DDFTCOMP__SIZE, 0x00000001 +.set CYVAL_CSD_DDFTCOMP_REFBUFCOMP, 0x00000000 +.set CYVAL_CSD_DDFTCOMP_SENSECOMP, 0x00000001 +.set CYFLD_CSD_ENABLE__OFFSET, 0x0000001f +.set CYFLD_CSD_ENABLE__SIZE, 0x00000001 +.set CYREG_CSD_IDAC, 0x40080008 +.set CYFLD_CSD_IDAC1__OFFSET, 0x00000000 +.set CYFLD_CSD_IDAC1__SIZE, 0x00000008 +.set CYFLD_CSD_IDAC1_MODE__OFFSET, 0x00000008 +.set CYFLD_CSD_IDAC1_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_IDAC1_MODE_OFF, 0x00000000 +.set CYVAL_CSD_IDAC1_MODE_FIXED, 0x00000001 +.set CYVAL_CSD_IDAC1_MODE_VARIABLE, 0x00000002 +.set CYVAL_CSD_IDAC1_MODE_DSI, 0x00000003 +.set CYFLD_CSD_IDAC1_RANGE__OFFSET, 0x0000000a +.set CYFLD_CSD_IDAC1_RANGE__SIZE, 0x00000001 +.set CYVAL_CSD_IDAC1_RANGE_4X, 0x00000000 +.set CYVAL_CSD_IDAC1_RANGE_8X, 0x00000001 +.set CYFLD_CSD_IDAC2__OFFSET, 0x00000010 +.set CYFLD_CSD_IDAC2__SIZE, 0x00000007 +.set CYFLD_CSD_IDAC2_MODE__OFFSET, 0x00000018 +.set CYFLD_CSD_IDAC2_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_IDAC2_MODE_OFF, 0x00000000 +.set CYVAL_CSD_IDAC2_MODE_FIXED, 0x00000001 +.set CYVAL_CSD_IDAC2_MODE_VARIABLE, 0x00000002 +.set CYVAL_CSD_IDAC2_MODE_DSI, 0x00000003 +.set CYFLD_CSD_IDAC2_RANGE__OFFSET, 0x0000001a +.set CYFLD_CSD_IDAC2_RANGE__SIZE, 0x00000001 +.set CYVAL_CSD_IDAC2_RANGE_4X, 0x00000000 +.set CYVAL_CSD_IDAC2_RANGE_8X, 0x00000001 +.set CYFLD_CSD_FEEDBACK_MODE__OFFSET, 0x0000001e +.set CYFLD_CSD_FEEDBACK_MODE__SIZE, 0x00000001 +.set CYVAL_CSD_FEEDBACK_MODE_FLOP, 0x00000000 +.set CYVAL_CSD_FEEDBACK_MODE_COMP, 0x00000001 +.set CYREG_CSD_COUNTER, 0x4008000c +.set CYFLD_CSD_COUNTER__OFFSET, 0x00000000 +.set CYFLD_CSD_COUNTER__SIZE, 0x00000010 +.set CYFLD_CSD_PERIOD__OFFSET, 0x00000010 +.set CYFLD_CSD_PERIOD__SIZE, 0x00000010 +.set CYREG_CSD_STATUS, 0x40080010 +.set CYFLD_CSD_CSD_CHARGE__OFFSET, 0x00000000 +.set CYFLD_CSD_CSD_CHARGE__SIZE, 0x00000001 +.set CYFLD_CSD_CSD_SENSE__OFFSET, 0x00000001 +.set CYFLD_CSD_CSD_SENSE__SIZE, 0x00000001 +.set CYFLD_CSD_COMP_OUT__OFFSET, 0x00000002 +.set CYFLD_CSD_COMP_OUT__SIZE, 0x00000001 +.set CYVAL_CSD_COMP_OUT_C_LT_VREF, 0x00000000 +.set CYVAL_CSD_COMP_OUT_C_GT_VREF, 0x00000001 +.set CYFLD_CSD_SAMPLE__OFFSET, 0x00000003 +.set CYFLD_CSD_SAMPLE__SIZE, 0x00000001 +.set CYREG_CSD_INTR, 0x40080014 +.set CYFLD_CSD_CSD__OFFSET, 0x00000000 +.set CYFLD_CSD_CSD__SIZE, 0x00000001 +.set CYREG_CSD_INTR_SET, 0x40080018 +.set CYREG_CSD_TRIM1, 0x4008ff00 +.set CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET, 0x00000000 +.set CYFLD_CSD_IDAC1_SRC_TRIM__SIZE, 0x00000004 +.set CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET, 0x00000004 +.set CYFLD_CSD_IDAC2_SRC_TRIM__SIZE, 0x00000004 +.set CYREG_CSD_TRIM2, 0x4008ff04 +.set CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET, 0x00000000 +.set CYFLD_CSD_IDAC1_SNK_TRIM__SIZE, 0x00000004 +.set CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET, 0x00000004 +.set CYFLD_CSD_IDAC2_SNK_TRIM__SIZE, 0x00000004 +.set CYDEV_LCD_BASE, 0x40090000 +.set CYDEV_LCD_SIZE, 0x00010000 +.set CYREG_LCD_ID, 0x40090000 +.set CYFLD_LCD_ID__OFFSET, 0x00000000 +.set CYFLD_LCD_ID__SIZE, 0x00000010 +.set CYFLD_LCD_REVISION__OFFSET, 0x00000010 +.set CYFLD_LCD_REVISION__SIZE, 0x00000010 +.set CYREG_LCD_DIVIDER, 0x40090004 +.set CYFLD_LCD_SUBFR_DIV__OFFSET, 0x00000000 +.set CYFLD_LCD_SUBFR_DIV__SIZE, 0x00000010 +.set CYFLD_LCD_DEAD_DIV__OFFSET, 0x00000010 +.set CYFLD_LCD_DEAD_DIV__SIZE, 0x00000010 +.set CYREG_LCD_CONTROL, 0x40090008 +.set CYFLD_LCD_LS_EN__OFFSET, 0x00000000 +.set CYFLD_LCD_LS_EN__SIZE, 0x00000001 +.set CYFLD_LCD_HS_EN__OFFSET, 0x00000001 +.set CYFLD_LCD_HS_EN__SIZE, 0x00000001 +.set CYFLD_LCD_LCD_MODE__OFFSET, 0x00000002 +.set CYFLD_LCD_LCD_MODE__SIZE, 0x00000001 +.set CYVAL_LCD_LCD_MODE_LS, 0x00000000 +.set CYVAL_LCD_LCD_MODE_HS, 0x00000001 +.set CYFLD_LCD_TYPE__OFFSET, 0x00000003 +.set CYFLD_LCD_TYPE__SIZE, 0x00000001 +.set CYVAL_LCD_TYPE_A, 0x00000000 +.set CYVAL_LCD_TYPE_B, 0x00000001 +.set CYFLD_LCD_OP_MODE__OFFSET, 0x00000004 +.set CYFLD_LCD_OP_MODE__SIZE, 0x00000001 +.set CYVAL_LCD_OP_MODE_PWM, 0x00000000 +.set CYVAL_LCD_OP_MODE_CORRELATION, 0x00000001 +.set CYFLD_LCD_BIAS__OFFSET, 0x00000005 +.set CYFLD_LCD_BIAS__SIZE, 0x00000002 +.set CYVAL_LCD_BIAS_HALF, 0x00000000 +.set CYVAL_LCD_BIAS_THIRD, 0x00000001 +.set CYVAL_LCD_BIAS_FOURTH, 0x00000002 +.set CYVAL_LCD_BIAS_FIFTH, 0x00000003 +.set CYFLD_LCD_COM_NUM__OFFSET, 0x00000008 +.set CYFLD_LCD_COM_NUM__SIZE, 0x00000004 +.set CYFLD_LCD_LS_EN_STAT__OFFSET, 0x0000001f +.set CYFLD_LCD_LS_EN_STAT__SIZE, 0x00000001 +.set CYREG_LCD_DATA00, 0x40090100 +.set CYFLD_LCD_DATA__OFFSET, 0x00000000 +.set CYFLD_LCD_DATA__SIZE, 0x00000020 +.set CYREG_LCD_DATA01, 0x40090104 +.set CYREG_LCD_DATA02, 0x40090108 +.set CYREG_LCD_DATA03, 0x4009010c +.set CYREG_LCD_DATA04, 0x40090110 +.set CYDEV_LPCOMP_BASE, 0x400a0000 +.set CYDEV_LPCOMP_SIZE, 0x00010000 +.set CYREG_LPCOMP_ID, 0x400a0000 +.set CYFLD_LPCOMP_ID__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_ID__SIZE, 0x00000010 +.set CYFLD_LPCOMP_REVISION__OFFSET, 0x00000010 +.set CYFLD_LPCOMP_REVISION__SIZE, 0x00000010 +.set CYREG_LPCOMP_CONFIG, 0x400a0004 +.set CYFLD_LPCOMP_MODE1__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_MODE1__SIZE, 0x00000002 +.set CYVAL_LPCOMP_MODE1_SLOW, 0x00000000 +.set CYVAL_LPCOMP_MODE1_FAST, 0x00000001 +.set CYVAL_LPCOMP_MODE1_ULP, 0x00000002 +.set CYFLD_LPCOMP_HYST1__OFFSET, 0x00000002 +.set CYFLD_LPCOMP_HYST1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_FILTER1__OFFSET, 0x00000003 +.set CYFLD_LPCOMP_FILTER1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_INTTYPE1__OFFSET, 0x00000004 +.set CYFLD_LPCOMP_INTTYPE1__SIZE, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE1_DISABLE, 0x00000000 +.set CYVAL_LPCOMP_INTTYPE1_RISING, 0x00000001 +.set CYVAL_LPCOMP_INTTYPE1_FALLING, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE1_BOTH, 0x00000003 +.set CYFLD_LPCOMP_OUT1__OFFSET, 0x00000006 +.set CYFLD_LPCOMP_OUT1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_ENABLE1__OFFSET, 0x00000007 +.set CYFLD_LPCOMP_ENABLE1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_MODE2__OFFSET, 0x00000008 +.set CYFLD_LPCOMP_MODE2__SIZE, 0x00000002 +.set CYVAL_LPCOMP_MODE2_SLOW, 0x00000000 +.set CYVAL_LPCOMP_MODE2_FAST, 0x00000001 +.set CYVAL_LPCOMP_MODE2_ULP, 0x00000002 +.set CYFLD_LPCOMP_HYST2__OFFSET, 0x0000000a +.set CYFLD_LPCOMP_HYST2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_FILTER2__OFFSET, 0x0000000b +.set CYFLD_LPCOMP_FILTER2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_INTTYPE2__OFFSET, 0x0000000c +.set CYFLD_LPCOMP_INTTYPE2__SIZE, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE2_DISABLE, 0x00000000 +.set CYVAL_LPCOMP_INTTYPE2_RISING, 0x00000001 +.set CYVAL_LPCOMP_INTTYPE2_FALLING, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE2_BOTH, 0x00000003 +.set CYFLD_LPCOMP_OUT2__OFFSET, 0x0000000e +.set CYFLD_LPCOMP_OUT2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_ENABLE2__OFFSET, 0x0000000f +.set CYFLD_LPCOMP_ENABLE2__SIZE, 0x00000001 +.set CYREG_LPCOMP_DFT, 0x400a0008 +.set CYFLD_LPCOMP_CAL_EN__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_CAL_EN__SIZE, 0x00000001 +.set CYFLD_LPCOMP_BYPASS__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_BYPASS__SIZE, 0x00000001 +.set CYREG_LPCOMP_INTR, 0x400a000c +.set CYFLD_LPCOMP_COMP1__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_COMP2__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_COMP2__SIZE, 0x00000001 +.set CYREG_LPCOMP_INTR_SET, 0x400a0010 +.set CYREG_LPCOMP_TRIM1, 0x400aff00 +.set CYFLD_LPCOMP_COMP1_TRIMA__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_TRIMA__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM2, 0x400aff04 +.set CYFLD_LPCOMP_COMP1_TRIMB__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_TRIMB__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM3, 0x400aff08 +.set CYFLD_LPCOMP_COMP2_TRIMA__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP2_TRIMA__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM4, 0x400aff0c +.set CYFLD_LPCOMP_COMP2_TRIMB__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP2_TRIMB__SIZE, 0x00000005 +.set CYREG_PWR_CONTROL, 0x400b0000 +.set CYFLD__POWER_MODE__OFFSET, 0x00000000 +.set CYFLD__POWER_MODE__SIZE, 0x00000004 +.set CYVAL__POWER_MODE_RESET, 0x00000000 +.set CYVAL__POWER_MODE_ACTIVE, 0x00000001 +.set CYVAL__POWER_MODE_SLEEP, 0x00000002 +.set CYVAL__POWER_MODE_DEEP_SLEEP, 0x00000003 +.set CYVAL__POWER_MODE_HIBERNATE, 0x00000004 +.set CYFLD__DEBUG_SESSION__OFFSET, 0x00000004 +.set CYFLD__DEBUG_SESSION__SIZE, 0x00000001 +.set CYVAL__DEBUG_SESSION_NO_SESSION, 0x00000000 +.set CYVAL__DEBUG_SESSION_SESSION_ACTIVE, 0x00000001 +.set CYFLD__LPM_READY__OFFSET, 0x00000005 +.set CYFLD__LPM_READY__SIZE, 0x00000001 +.set CYFLD__EXT_VCCD__OFFSET, 0x00000017 +.set CYFLD__EXT_VCCD__SIZE, 0x00000001 +.set CYFLD__HVMON_ENABLE__OFFSET, 0x00000018 +.set CYFLD__HVMON_ENABLE__SIZE, 0x00000001 +.set CYFLD__HVMON_RELOAD__OFFSET, 0x00000019 +.set CYFLD__HVMON_RELOAD__SIZE, 0x00000001 +.set CYFLD__FIMO_DISABLE__OFFSET, 0x0000001b +.set CYFLD__FIMO_DISABLE__SIZE, 0x00000001 +.set CYFLD__HIBERNATE_DISABLE__OFFSET, 0x0000001c +.set CYFLD__HIBERNATE_DISABLE__SIZE, 0x00000001 +.set CYFLD__LFCLK_SHORT__OFFSET, 0x0000001d +.set CYFLD__LFCLK_SHORT__SIZE, 0x00000001 +.set CYFLD__HIBERNATE__OFFSET, 0x0000001f +.set CYFLD__HIBERNATE__SIZE, 0x00000001 +.set CYVAL__HIBERNATE_DEEP_SLEEP, 0x00000000 +.set CYVAL__HIBERNATE_HIBERNATE, 0x00000001 +.set CYREG_PWR_INTR, 0x400b0004 +.set CYFLD__LVD__OFFSET, 0x00000001 +.set CYFLD__LVD__SIZE, 0x00000001 +.set CYREG_PWR_INTR_MASK, 0x400b0008 +.set CYREG_PWR_KEY_DELAY, 0x400b000c +.set CYFLD__WAKEUP_HOLDOFF__OFFSET, 0x00000000 +.set CYFLD__WAKEUP_HOLDOFF__SIZE, 0x0000000a +.set CYREG_PWR_PWRSYS_CONFIG, 0x400b0010 +.set CYFLD__HIB_TEST_EN__OFFSET, 0x00000008 +.set CYFLD__HIB_TEST_EN__SIZE, 0x00000001 +.set CYFLD__HIB_TEST_REP__OFFSET, 0x00000009 +.set CYFLD__HIB_TEST_REP__SIZE, 0x00000001 +.set CYREG_PWR_BG_CONFIG, 0x400b0014 +.set CYFLD__BG_DFT_EN__OFFSET, 0x00000000 +.set CYFLD__BG_DFT_EN__SIZE, 0x00000001 +.set CYFLD__BG_DFT_VREF_SEL__OFFSET, 0x00000001 +.set CYFLD__BG_DFT_VREF_SEL__SIZE, 0x00000004 +.set CYFLD__BG_DFT_CORE_SEL__OFFSET, 0x00000005 +.set CYFLD__BG_DFT_CORE_SEL__SIZE, 0x00000001 +.set CYFLD__BG_DFT_ICORE_SEL__OFFSET, 0x00000006 +.set CYFLD__BG_DFT_ICORE_SEL__SIZE, 0x00000002 +.set CYFLD__BG_DFT_VCORE_SEL__OFFSET, 0x00000008 +.set CYFLD__BG_DFT_VCORE_SEL__SIZE, 0x00000001 +.set CYFLD__VREF_EN__OFFSET, 0x00000010 +.set CYFLD__VREF_EN__SIZE, 0x00000003 +.set CYREG_PWR_VMON_CONFIG, 0x400b0018 +.set CYFLD__LVD_EN__OFFSET, 0x00000000 +.set CYFLD__LVD_EN__SIZE, 0x00000001 +.set CYFLD__LVD_SEL__OFFSET, 0x00000001 +.set CYFLD__LVD_SEL__SIZE, 0x00000004 +.set CYFLD__VMON_DDFT_SEL__OFFSET, 0x00000005 +.set CYFLD__VMON_DDFT_SEL__SIZE, 0x00000003 +.set CYFLD__VMON_ADFT_SEL__OFFSET, 0x00000008 +.set CYFLD__VMON_ADFT_SEL__SIZE, 0x00000002 +.set CYREG_PWR_DFT_SELECT, 0x400b001c +.set CYFLD__TVMON1_SEL__OFFSET, 0x00000000 +.set CYFLD__TVMON1_SEL__SIZE, 0x00000003 +.set CYFLD__TVMON2_SEL__OFFSET, 0x00000003 +.set CYFLD__TVMON2_SEL__SIZE, 0x00000003 +.set CYFLD__BYPASS__OFFSET, 0x00000006 +.set CYFLD__BYPASS__SIZE, 0x00000001 +.set CYFLD__ACTIVE_EN__OFFSET, 0x00000007 +.set CYFLD__ACTIVE_EN__SIZE, 0x00000001 +.set CYFLD__ACTIVE_INRUSH_DIS__OFFSET, 0x00000008 +.set CYFLD__ACTIVE_INRUSH_DIS__SIZE, 0x00000001 +.set CYFLD__LPCOMP_DIS__OFFSET, 0x00000009 +.set CYFLD__LPCOMP_DIS__SIZE, 0x00000001 +.set CYFLD__BLEED_EN__OFFSET, 0x0000000a +.set CYFLD__BLEED_EN__SIZE, 0x00000001 +.set CYFLD__IPOR_EN__OFFSET, 0x0000000b +.set CYFLD__IPOR_EN__SIZE, 0x00000001 +.set CYFLD__POWER_UP_RAW_BYP__OFFSET, 0x0000000c +.set CYFLD__POWER_UP_RAW_BYP__SIZE, 0x00000001 +.set CYFLD__POWER_UP_RAW_CTL__OFFSET, 0x0000000d +.set CYFLD__POWER_UP_RAW_CTL__SIZE, 0x00000001 +.set CYFLD__DEEPSLEEP_EN__OFFSET, 0x0000000e +.set CYFLD__DEEPSLEEP_EN__SIZE, 0x00000001 +.set CYFLD__RSVD_BYPASS__OFFSET, 0x0000000f +.set CYFLD__RSVD_BYPASS__SIZE, 0x00000001 +.set CYFLD__NWELL_OPEN__OFFSET, 0x00000010 +.set CYFLD__NWELL_OPEN__SIZE, 0x00000001 +.set CYFLD__HIBERNATE_OPEN__OFFSET, 0x00000011 +.set CYFLD__HIBERNATE_OPEN__SIZE, 0x00000001 +.set CYFLD__DEEPSLEEP_OPEN__OFFSET, 0x00000012 +.set CYFLD__DEEPSLEEP_OPEN__SIZE, 0x00000001 +.set CYFLD__QUIET_OPEN__OFFSET, 0x00000013 +.set CYFLD__QUIET_OPEN__SIZE, 0x00000001 +.set CYFLD__LFCLK_OPEN__OFFSET, 0x00000014 +.set CYFLD__LFCLK_OPEN__SIZE, 0x00000001 +.set CYFLD__QUIET_EN__OFFSET, 0x00000016 +.set CYFLD__QUIET_EN__SIZE, 0x00000001 +.set CYFLD__BREF_EN__OFFSET, 0x00000017 +.set CYFLD__BREF_EN__SIZE, 0x00000001 +.set CYFLD__BREF_OUTEN__OFFSET, 0x00000018 +.set CYFLD__BREF_OUTEN__SIZE, 0x00000001 +.set CYFLD__BREF_REFSW__OFFSET, 0x00000019 +.set CYFLD__BREF_REFSW__SIZE, 0x00000001 +.set CYFLD__BREF_TESTMODE__OFFSET, 0x0000001a +.set CYFLD__BREF_TESTMODE__SIZE, 0x00000001 +.set CYFLD__NWELL_DIS__OFFSET, 0x0000001b +.set CYFLD__NWELL_DIS__SIZE, 0x00000001 +.set CYFLD__HVMON_DFT_OVR__OFFSET, 0x0000001c +.set CYFLD__HVMON_DFT_OVR__SIZE, 0x00000001 +.set CYFLD__IMO_REFGEN_DIS__OFFSET, 0x0000001d +.set CYFLD__IMO_REFGEN_DIS__SIZE, 0x00000001 +.set CYFLD__POWER_UP_ACTIVE__OFFSET, 0x0000001e +.set CYFLD__POWER_UP_ACTIVE__SIZE, 0x00000001 +.set CYFLD__POWER_UP_HIBDPSLP__OFFSET, 0x0000001f +.set CYFLD__POWER_UP_HIBDPSLP__SIZE, 0x00000001 +.set CYREG_PWR_DDFT_SELECT, 0x400b0020 +.set CYFLD__DDFT1_SEL__OFFSET, 0x00000000 +.set CYFLD__DDFT1_SEL__SIZE, 0x00000004 +.set CYFLD__DDFT2_SEL__OFFSET, 0x00000004 +.set CYFLD__DDFT2_SEL__SIZE, 0x00000004 +.set CYREG_PWR_DFT_KEY, 0x400b0024 +.set CYFLD__KEY16__OFFSET, 0x00000000 +.set CYFLD__KEY16__SIZE, 0x00000010 +.set CYFLD__HBOD_OFF_AWAKE__OFFSET, 0x00000010 +.set CYFLD__HBOD_OFF_AWAKE__SIZE, 0x00000001 +.set CYFLD__BODS_OFF__OFFSET, 0x00000011 +.set CYFLD__BODS_OFF__SIZE, 0x00000001 +.set CYFLD__DFT_MODE__OFFSET, 0x00000012 +.set CYFLD__DFT_MODE__SIZE, 0x00000001 +.set CYFLD__IO_DISABLE_BYPASS__OFFSET, 0x00000013 +.set CYFLD__IO_DISABLE_BYPASS__SIZE, 0x00000001 +.set CYFLD__VMON_PD__OFFSET, 0x00000014 +.set CYFLD__VMON_PD__SIZE, 0x00000001 +.set CYREG_PWR_BOD_KEY, 0x400b0028 +.set CYREG_PWR_STOP, 0x400b002c +.set CYFLD__TOKEN__OFFSET, 0x00000000 +.set CYFLD__TOKEN__SIZE, 0x00000008 +.set CYFLD__UNLOCK__OFFSET, 0x00000008 +.set CYFLD__UNLOCK__SIZE, 0x00000008 +.set CYFLD__POLARITY__OFFSET, 0x00000010 +.set CYFLD__POLARITY__SIZE, 0x00000001 +.set CYFLD__FREEZE__OFFSET, 0x00000011 +.set CYFLD__FREEZE__SIZE, 0x00000001 +.set CYFLD__STOP__OFFSET, 0x0000001f +.set CYFLD__STOP__SIZE, 0x00000001 +.set CYREG_CLK_SELECT, 0x400b0100 +.set CYFLD__DIRECT_SEL__OFFSET, 0x00000000 +.set CYFLD__DIRECT_SEL__SIZE, 0x00000003 +.set CYVAL__DIRECT_SEL_IMO, 0x00000000 +.set CYVAL__DIRECT_SEL_EXTCLK, 0x00000001 +.set CYVAL__DIRECT_SEL_ECO, 0x00000002 +.set CYVAL__DIRECT_SEL_DSI0, 0x00000004 +.set CYVAL__DIRECT_SEL_DSI1, 0x00000005 +.set CYVAL__DIRECT_SEL_DSI2, 0x00000006 +.set CYVAL__DIRECT_SEL_DSI3, 0x00000007 +.set CYFLD__DBL_SEL__OFFSET, 0x00000003 +.set CYFLD__DBL_SEL__SIZE, 0x00000003 +.set CYVAL__DBL_SEL_IMO, 0x00000000 +.set CYVAL__DBL_SEL_EXTCLK, 0x00000001 +.set CYVAL__DBL_SEL_ECO, 0x00000002 +.set CYVAL__DBL_SEL_DSI0, 0x00000004 +.set CYVAL__DBL_SEL_DSI1, 0x00000005 +.set CYVAL__DBL_SEL_DSI2, 0x00000006 +.set CYVAL__DBL_SEL_DSI3, 0x00000007 +.set CYFLD__PLL_SEL__OFFSET, 0x00000006 +.set CYFLD__PLL_SEL__SIZE, 0x00000003 +.set CYVAL__PLL_SEL_IMO, 0x00000000 +.set CYVAL__PLL_SEL_EXTCLK, 0x00000001 +.set CYVAL__PLL_SEL_ECO, 0x00000002 +.set CYVAL__PLL_SEL_DPLL, 0x00000003 +.set CYVAL__PLL_SEL_DSI0, 0x00000004 +.set CYVAL__PLL_SEL_DSI1, 0x00000005 +.set CYVAL__PLL_SEL_DSI2, 0x00000006 +.set CYVAL__PLL_SEL_DSI3, 0x00000007 +.set CYFLD__DPLLIN_SEL__OFFSET, 0x00000009 +.set CYFLD__DPLLIN_SEL__SIZE, 0x00000003 +.set CYVAL__DPLLIN_SEL_IMO, 0x00000000 +.set CYVAL__DPLLIN_SEL_EXTCLK, 0x00000001 +.set CYVAL__DPLLIN_SEL_ECO, 0x00000002 +.set CYVAL__DPLLIN_SEL_DSI0, 0x00000004 +.set CYVAL__DPLLIN_SEL_DSI1, 0x00000005 +.set CYVAL__DPLLIN_SEL_DSI2, 0x00000006 +.set CYVAL__DPLLIN_SEL_DSI3, 0x00000007 +.set CYFLD__DPLLREF_SEL__OFFSET, 0x0000000c +.set CYFLD__DPLLREF_SEL__SIZE, 0x00000002 +.set CYVAL__DPLLREF_SEL_DSI0, 0x00000000 +.set CYVAL__DPLLREF_SEL_DSI1, 0x00000001 +.set CYVAL__DPLLREF_SEL_DSI2, 0x00000002 +.set CYVAL__DPLLREF_SEL_DSI3, 0x00000003 +.set CYFLD__WDT_LOCK__OFFSET, 0x0000000e +.set CYFLD__WDT_LOCK__SIZE, 0x00000002 +.set CYVAL__WDT_LOCK_NO_CHG, 0x00000000 +.set CYVAL__WDT_LOCK_CLR0, 0x00000001 +.set CYVAL__WDT_LOCK_CLR1, 0x00000002 +.set CYVAL__WDT_LOCK_SET01, 0x00000003 +.set CYFLD__HFCLK_SEL__OFFSET, 0x00000010 +.set CYFLD__HFCLK_SEL__SIZE, 0x00000002 +.set CYVAL__HFCLK_SEL_DIRECT_SEL, 0x00000000 +.set CYVAL__HFCLK_SEL_DBL, 0x00000001 +.set CYVAL__HFCLK_SEL_PLL, 0x00000002 +.set CYFLD__HALF_EN__OFFSET, 0x00000012 +.set CYFLD__HALF_EN__SIZE, 0x00000001 +.set CYFLD__SYSCLK_DIV__OFFSET, 0x00000013 +.set CYFLD__SYSCLK_DIV__SIZE, 0x00000003 +.set CYVAL__SYSCLK_DIV_NO_DIV, 0x00000000 +.set CYVAL__SYSCLK_DIV_DIV_BY_2, 0x00000001 +.set CYVAL__SYSCLK_DIV_DIV_BY_4, 0x00000002 +.set CYVAL__SYSCLK_DIV_DIV_BY_8, 0x00000003 +.set CYVAL__SYSCLK_DIV_DIV_BY_16, 0x00000004 +.set CYVAL__SYSCLK_DIV_DIV_BY_32, 0x00000005 +.set CYVAL__SYSCLK_DIV_DIV_BY_64, 0x00000006 +.set CYVAL__SYSCLK_DIV_DIV_BY_128, 0x00000007 +.set CYREG_CLK_ILO_CONFIG, 0x400b0104 +.set CYFLD__PD_MODE__OFFSET, 0x00000000 +.set CYFLD__PD_MODE__SIZE, 0x00000001 +.set CYVAL__PD_MODE_SLEEP, 0x00000000 +.set CYVAL__PD_MODE_COMA, 0x00000001 +.set CYFLD__TURBO__OFFSET, 0x00000001 +.set CYFLD__TURBO__SIZE, 0x00000001 +.set CYFLD__SATBIAS__OFFSET, 0x00000002 +.set CYFLD__SATBIAS__SIZE, 0x00000001 +.set CYVAL__SATBIAS_SATURATED, 0x00000000 +.set CYVAL__SATBIAS_SUBTHRESHOLD, 0x00000001 +.set CYFLD__ENABLE__OFFSET, 0x0000001f +.set CYFLD__ENABLE__SIZE, 0x00000001 +.set CYREG_CLK_IMO_CONFIG, 0x400b0108 +.set CYFLD__FLASHPUMP_SEL__OFFSET, 0x00000016 +.set CYFLD__FLASHPUMP_SEL__SIZE, 0x00000001 +.set CYVAL__FLASHPUMP_SEL_GND, 0x00000000 +.set CYVAL__FLASHPUMP_SEL_CLK36, 0x00000001 +.set CYFLD__EN_FASTBIAS__OFFSET, 0x00000017 +.set CYFLD__EN_FASTBIAS__SIZE, 0x00000001 +.set CYFLD__TEST_FASTBIAS__OFFSET, 0x00000018 +.set CYFLD__TEST_FASTBIAS__SIZE, 0x00000001 +.set CYFLD__PUMP_SEL__OFFSET, 0x00000019 +.set CYFLD__PUMP_SEL__SIZE, 0x00000003 +.set CYVAL__PUMP_SEL_GND, 0x00000000 +.set CYVAL__PUMP_SEL_IMO, 0x00000001 +.set CYVAL__PUMP_SEL_DBL, 0x00000002 +.set CYVAL__PUMP_SEL_CLK36, 0x00000003 +.set CYVAL__PUMP_SEL_FF1, 0x00000004 +.set CYFLD__TEST_USB_MODE__OFFSET, 0x0000001c +.set CYFLD__TEST_USB_MODE__SIZE, 0x00000001 +.set CYFLD__EN_CLK36__OFFSET, 0x0000001d +.set CYFLD__EN_CLK36__SIZE, 0x00000001 +.set CYFLD__EN_CLK2X__OFFSET, 0x0000001e +.set CYFLD__EN_CLK2X__SIZE, 0x00000001 +.set CYREG_CLK_IMO_SPREAD, 0x400b010c +.set CYFLD__SS_VALUE__OFFSET, 0x00000000 +.set CYFLD__SS_VALUE__SIZE, 0x00000005 +.set CYFLD__SS_MAX__OFFSET, 0x00000008 +.set CYFLD__SS_MAX__SIZE, 0x00000005 +.set CYFLD__SS_RANGE__OFFSET, 0x0000001c +.set CYFLD__SS_RANGE__SIZE, 0x00000002 +.set CYVAL__SS_RANGE_M1, 0x00000000 +.set CYVAL__SS_RANGE_M2, 0x00000001 +.set CYVAL__SS_RANGE_M4, 0x00000002 +.set CYFLD__SS_MODE__OFFSET, 0x0000001e +.set CYFLD__SS_MODE__SIZE, 0x00000002 +.set CYVAL__SS_MODE_OFF, 0x00000000 +.set CYVAL__SS_MODE_TRIANGLE, 0x00000001 +.set CYVAL__SS_MODE_LFSR, 0x00000002 +.set CYVAL__SS_MODE_DSI, 0x00000003 +.set CYREG_CLK_DFT_SELECT, 0x400b0110 +.set CYFLD__DFT_SEL1__OFFSET, 0x00000000 +.set CYFLD__DFT_SEL1__SIZE, 0x00000004 +.set CYVAL__DFT_SEL1_NC, 0x00000000 +.set CYVAL__DFT_SEL1_ILO, 0x00000001 +.set CYVAL__DFT_SEL1_WCO, 0x00000002 +.set CYVAL__DFT_SEL1_IMO, 0x00000003 +.set CYVAL__DFT_SEL1_ECO, 0x00000004 +.set CYVAL__DFT_SEL1_PLL, 0x00000005 +.set CYVAL__DFT_SEL1_DPLL_OUT, 0x00000006 +.set CYVAL__DFT_SEL1_DPLL_REF, 0x00000007 +.set CYVAL__DFT_SEL1_DBL, 0x00000008 +.set CYVAL__DFT_SEL1_IMO2X, 0x00000009 +.set CYVAL__DFT_SEL1_IMO36, 0x0000000a +.set CYVAL__DFT_SEL1_HFCLK, 0x0000000b +.set CYVAL__DFT_SEL1_LFCLK, 0x0000000c +.set CYVAL__DFT_SEL1_SYSCLK, 0x0000000d +.set CYVAL__DFT_SEL1_EXTCLK, 0x0000000e +.set CYVAL__DFT_SEL1_HALFSYSCLK, 0x0000000f +.set CYFLD__DFT_DIV1__OFFSET, 0x00000004 +.set CYFLD__DFT_DIV1__SIZE, 0x00000002 +.set CYVAL__DFT_DIV1_NO_DIV, 0x00000000 +.set CYVAL__DFT_DIV1_DIV_BY_2, 0x00000001 +.set CYVAL__DFT_DIV1_DIV_BY_4, 0x00000002 +.set CYVAL__DFT_DIV1_DIV_BY_8, 0x00000003 +.set CYFLD__DFT_SEL2__OFFSET, 0x00000008 +.set CYFLD__DFT_SEL2__SIZE, 0x00000004 +.set CYVAL__DFT_SEL2_NC, 0x00000000 +.set CYVAL__DFT_SEL2_ILO, 0x00000001 +.set CYVAL__DFT_SEL2_WCO, 0x00000002 +.set CYVAL__DFT_SEL2_IMO, 0x00000003 +.set CYVAL__DFT_SEL2_ECO, 0x00000004 +.set CYVAL__DFT_SEL2_PLL, 0x00000005 +.set CYVAL__DFT_SEL2_DPLL_OUT, 0x00000006 +.set CYVAL__DFT_SEL2_DPLL_REF, 0x00000007 +.set CYVAL__DFT_SEL2_DBL, 0x00000008 +.set CYVAL__DFT_SEL2_IMO2X, 0x00000009 +.set CYVAL__DFT_SEL2_IMO36, 0x0000000a +.set CYVAL__DFT_SEL2_HFCLK, 0x0000000b +.set CYVAL__DFT_SEL2_LFCLK, 0x0000000c +.set CYVAL__DFT_SEL2_SYSCLK, 0x0000000d +.set CYVAL__DFT_SEL2_EXTCLK, 0x0000000e +.set CYVAL__DFT_SEL2_HALFSYSCLK, 0x0000000f +.set CYFLD__DFT_DIV2__OFFSET, 0x0000000c +.set CYFLD__DFT_DIV2__SIZE, 0x00000002 +.set CYVAL__DFT_DIV2_NO_DIV, 0x00000000 +.set CYVAL__DFT_DIV2_DIV_BY_2, 0x00000001 +.set CYVAL__DFT_DIV2_DIV_BY_4, 0x00000002 +.set CYVAL__DFT_DIV2_DIV_BY_8, 0x00000003 +.set CYREG_WDT_CTRLOW, 0x400b0200 +.set CYFLD__WDT_CTR0__OFFSET, 0x00000000 +.set CYFLD__WDT_CTR0__SIZE, 0x00000010 +.set CYFLD__WDT_CTR1__OFFSET, 0x00000010 +.set CYFLD__WDT_CTR1__SIZE, 0x00000010 +.set CYREG_WDT_CTRHIGH, 0x400b0204 +.set CYFLD__WDT_CTR2__OFFSET, 0x00000000 +.set CYFLD__WDT_CTR2__SIZE, 0x00000020 +.set CYREG_WDT_MATCH, 0x400b0208 +.set CYFLD__WDT_MATCH0__OFFSET, 0x00000000 +.set CYFLD__WDT_MATCH0__SIZE, 0x00000010 +.set CYFLD__WDT_MATCH1__OFFSET, 0x00000010 +.set CYFLD__WDT_MATCH1__SIZE, 0x00000010 +.set CYREG_WDT_CONFIG, 0x400b020c +.set CYFLD__WDT_MODE0__OFFSET, 0x00000000 +.set CYFLD__WDT_MODE0__SIZE, 0x00000002 +.set CYVAL__WDT_MODE0_NOTHING, 0x00000000 +.set CYVAL__WDT_MODE0_INT, 0x00000001 +.set CYVAL__WDT_MODE0_RESET, 0x00000002 +.set CYVAL__WDT_MODE0_INT_THEN_RESET, 0x00000003 +.set CYFLD__WDT_CLEAR0__OFFSET, 0x00000002 +.set CYFLD__WDT_CLEAR0__SIZE, 0x00000001 +.set CYFLD__WDT_CASCADE0_1__OFFSET, 0x00000003 +.set CYFLD__WDT_CASCADE0_1__SIZE, 0x00000001 +.set CYFLD__WDT_MODE1__OFFSET, 0x00000008 +.set CYFLD__WDT_MODE1__SIZE, 0x00000002 +.set CYVAL__WDT_MODE1_NOTHING, 0x00000000 +.set CYVAL__WDT_MODE1_INT, 0x00000001 +.set CYVAL__WDT_MODE1_RESET, 0x00000002 +.set CYVAL__WDT_MODE1_INT_THEN_RESET, 0x00000003 +.set CYFLD__WDT_CLEAR1__OFFSET, 0x0000000a +.set CYFLD__WDT_CLEAR1__SIZE, 0x00000001 +.set CYFLD__WDT_CASCADE1_2__OFFSET, 0x0000000b +.set CYFLD__WDT_CASCADE1_2__SIZE, 0x00000001 +.set CYFLD__WDT_MODE2__OFFSET, 0x00000010 +.set CYFLD__WDT_MODE2__SIZE, 0x00000001 +.set CYVAL__WDT_MODE2_NOTHING, 0x00000000 +.set CYVAL__WDT_MODE2_INT, 0x00000001 +.set CYFLD__WDT_BITS2__OFFSET, 0x00000018 +.set CYFLD__WDT_BITS2__SIZE, 0x00000005 +.set CYFLD__LFCLK_SEL__OFFSET, 0x0000001e +.set CYFLD__LFCLK_SEL__SIZE, 0x00000002 +.set CYREG_WDT_CONTROL, 0x400b0210 +.set CYFLD__WDT_ENABLE0__OFFSET, 0x00000000 +.set CYFLD__WDT_ENABLE0__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLED0__OFFSET, 0x00000001 +.set CYFLD__WDT_ENABLED0__SIZE, 0x00000001 +.set CYFLD__WDT_INT0__OFFSET, 0x00000002 +.set CYFLD__WDT_INT0__SIZE, 0x00000001 +.set CYFLD__WDT_RESET0__OFFSET, 0x00000003 +.set CYFLD__WDT_RESET0__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLE1__OFFSET, 0x00000008 +.set CYFLD__WDT_ENABLE1__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLED1__OFFSET, 0x00000009 +.set CYFLD__WDT_ENABLED1__SIZE, 0x00000001 +.set CYFLD__WDT_INT1__OFFSET, 0x0000000a +.set CYFLD__WDT_INT1__SIZE, 0x00000001 +.set CYFLD__WDT_RESET1__OFFSET, 0x0000000b +.set CYFLD__WDT_RESET1__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLE2__OFFSET, 0x00000010 +.set CYFLD__WDT_ENABLE2__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLED2__OFFSET, 0x00000011 +.set CYFLD__WDT_ENABLED2__SIZE, 0x00000001 +.set CYFLD__WDT_INT2__OFFSET, 0x00000012 +.set CYFLD__WDT_INT2__SIZE, 0x00000001 +.set CYFLD__WDT_RESET2__OFFSET, 0x00000013 +.set CYFLD__WDT_RESET2__SIZE, 0x00000001 +.set CYREG_RES_CAUSE, 0x400b0300 +.set CYFLD__RESET_WDT__OFFSET, 0x00000000 +.set CYFLD__RESET_WDT__SIZE, 0x00000001 +.set CYFLD__RESET_DSBOD__OFFSET, 0x00000001 +.set CYFLD__RESET_DSBOD__SIZE, 0x00000001 +.set CYFLD__RESET_LOCKUP__OFFSET, 0x00000002 +.set CYFLD__RESET_LOCKUP__SIZE, 0x00000001 +.set CYFLD__RESET_PROT_FAULT__OFFSET, 0x00000003 +.set CYFLD__RESET_PROT_FAULT__SIZE, 0x00000001 +.set CYFLD__RESET_SOFT__OFFSET, 0x00000004 +.set CYFLD__RESET_SOFT__SIZE, 0x00000001 +.set CYFLD__RESET_HVBOD__OFFSET, 0x00000005 +.set CYFLD__RESET_HVBOD__SIZE, 0x00000001 +.set CYFLD__RESET_PBOD__OFFSET, 0x00000006 +.set CYFLD__RESET_PBOD__SIZE, 0x00000001 +.set CYFLD__RESET_XRES__OFFSET, 0x00000007 +.set CYFLD__RESET_XRES__SIZE, 0x00000001 +.set CYREG_PWR_PWRSYS_TRIM1, 0x400bff00 +.set CYFLD__HIB_BIAS_TRIM__OFFSET, 0x00000000 +.set CYFLD__HIB_BIAS_TRIM__SIZE, 0x00000003 +.set CYFLD__BOD_TURBO_THRESH__OFFSET, 0x00000003 +.set CYFLD__BOD_TURBO_THRESH__SIZE, 0x00000001 +.set CYFLD__BOD_TRIM_TRIP__OFFSET, 0x00000004 +.set CYFLD__BOD_TRIM_TRIP__SIZE, 0x00000004 +.set CYREG_PWR_PWRSYS_TRIM2, 0x400bff04 +.set CYFLD__LFCLK_TRIM_LOAD__OFFSET, 0x00000000 +.set CYFLD__LFCLK_TRIM_LOAD__SIZE, 0x00000002 +.set CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET, 0x00000002 +.set CYFLD__LFCLK_TRIM_VOLTAGE__SIZE, 0x00000002 +.set CYFLD__DPSLP_TRIM_LOAD__OFFSET, 0x00000004 +.set CYFLD__DPSLP_TRIM_LOAD__SIZE, 0x00000002 +.set CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET, 0x00000006 +.set CYFLD__DPSLP_TRIM_LEAKAGE__SIZE, 0x00000001 +.set CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET, 0x00000007 +.set CYFLD__DPSLP_TRIM_VOLTAGE__SIZE, 0x00000001 +.set CYREG_PWR_PWRSYS_TRIM3, 0x400bff08 +.set CYFLD__NWELL_TRIM__OFFSET, 0x00000000 +.set CYFLD__NWELL_TRIM__SIZE, 0x00000003 +.set CYFLD__QUIET_TRIM__OFFSET, 0x00000003 +.set CYFLD__QUIET_TRIM__SIZE, 0x00000005 +.set CYREG_PWR_PWRSYS_TRIM4, 0x400bff0c +.set CYFLD__HIB_TRIM_NWELL__OFFSET, 0x00000000 +.set CYFLD__HIB_TRIM_NWELL__SIZE, 0x00000002 +.set CYFLD__HIB_TRIM_LEAKAGE__OFFSET, 0x00000002 +.set CYFLD__HIB_TRIM_LEAKAGE__SIZE, 0x00000001 +.set CYFLD__HIB_TRIM_VOLTAGE__OFFSET, 0x00000003 +.set CYFLD__HIB_TRIM_VOLTAGE__SIZE, 0x00000001 +.set CYFLD__HIB_TRIM_REFERENCE__OFFSET, 0x00000004 +.set CYFLD__HIB_TRIM_REFERENCE__SIZE, 0x00000002 +.set CYREG_PWR_BG_TRIM1, 0x400bff10 +.set CYFLD__INL_TRIM_MAIN__OFFSET, 0x00000000 +.set CYFLD__INL_TRIM_MAIN__SIZE, 0x00000003 +.set CYFLD__INL_CROSS_MAIN__OFFSET, 0x00000003 +.set CYFLD__INL_CROSS_MAIN__SIZE, 0x00000004 +.set CYREG_PWR_BG_TRIM2, 0x400bff14 +.set CYFLD__VCTAT_SLOPE__OFFSET, 0x00000000 +.set CYFLD__VCTAT_SLOPE__SIZE, 0x00000004 +.set CYFLD__VCTAT_VOLTAGE__OFFSET, 0x00000004 +.set CYFLD__VCTAT_VOLTAGE__SIZE, 0x00000002 +.set CYFLD__VCTAT_ENABLE__OFFSET, 0x00000006 +.set CYFLD__VCTAT_ENABLE__SIZE, 0x00000001 +.set CYFLD__VCTAT_VOLTAGE_MSB__OFFSET, 0x00000007 +.set CYFLD__VCTAT_VOLTAGE_MSB__SIZE, 0x00000001 +.set CYREG_PWR_BG_TRIM3, 0x400bff18 +.set CYFLD__INL_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD__INL_TRIM_IMO__SIZE, 0x00000003 +.set CYFLD__INL_CROSS_IMO__OFFSET, 0x00000003 +.set CYFLD__INL_CROSS_IMO__SIZE, 0x00000004 +.set CYREG_PWR_BG_TRIM4, 0x400bff1c +.set CYFLD__ABS_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD__ABS_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_PWR_BG_TRIM5, 0x400bff20 +.set CYFLD__TMPCO_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD__TMPCO_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_CLK_ILO_TRIM, 0x400bff24 +.set CYFLD__TRIM__OFFSET, 0x00000000 +.set CYFLD__TRIM__SIZE, 0x00000004 +.set CYFLD__COARSE_TRIM__OFFSET, 0x00000004 +.set CYFLD__COARSE_TRIM__SIZE, 0x00000004 +.set CYREG_CLK_IMO_TRIM1, 0x400bff28 +.set CYFLD__OFFSET__OFFSET, 0x00000000 +.set CYFLD__OFFSET__SIZE, 0x00000008 +.set CYREG_CLK_IMO_TRIM2, 0x400bff2c +.set CYFLD__FREQ__OFFSET, 0x00000000 +.set CYFLD__FREQ__SIZE, 0x00000006 +.set CYREG_CLK_IMO_TRIM3, 0x400bff30 +.set CYFLD__TRIM_CLK36__OFFSET, 0x00000000 +.set CYFLD__TRIM_CLK36__SIZE, 0x00000004 +.set CYREG_CLK_IMO_TRIM4, 0x400bff34 +.set CYFLD__GAIN__OFFSET, 0x00000000 +.set CYFLD__GAIN__SIZE, 0x00000005 +.set CYFLD__FSOFFSET__OFFSET, 0x00000005 +.set CYFLD__FSOFFSET__SIZE, 0x00000003 +.set CYREG_PWR_RSVD_TRIM, 0x400bff38 +.set CYFLD__RSVD_TRIM__OFFSET, 0x00000000 +.set CYFLD__RSVD_TRIM__SIZE, 0x00000004 +.set CYDEV_SPCIF_BASE, 0x400e0000 +.set CYDEV_SPCIF_SIZE, 0x00010000 +.set CYREG_SPCIF_GEOMETRY, 0x400e0000 +.set CYFLD_SPCIF_FLASH__OFFSET, 0x00000000 +.set CYFLD_SPCIF_FLASH__SIZE, 0x00000010 +.set CYFLD_SPCIF_SFLASH__OFFSET, 0x00000010 +.set CYFLD_SPCIF_SFLASH__SIZE, 0x00000004 +.set CYFLD_SPCIF_NUM_FLASH__OFFSET, 0x00000014 +.set CYFLD_SPCIF_NUM_FLASH__SIZE, 0x00000002 +.set CYFLD_SPCIF_FLASH_ROW__OFFSET, 0x00000016 +.set CYFLD_SPCIF_FLASH_ROW__SIZE, 0x00000002 +.set CYFLD_SPCIF_NVL__OFFSET, 0x00000018 +.set CYFLD_SPCIF_NVL__SIZE, 0x00000007 +.set CYFLD_SPCIF_DE_CPD_LP__OFFSET, 0x0000001f +.set CYFLD_SPCIF_DE_CPD_LP__SIZE, 0x00000001 +.set CYREG_SPCIF_NVL_WR_DATA, 0x400e001c +.set CYFLD_SPCIF_DATA__OFFSET, 0x00000000 +.set CYFLD_SPCIF_DATA__SIZE, 0x00000008 +.set CYDEV_UDB_BASE, 0x400f0000 +.set CYDEV_UDB_SIZE, 0x00010000 +.set CYDEV_UDB_W8_BASE, 0x400f0000 +.set CYDEV_UDB_W8_SIZE, 0x00001000 +.set CYREG_UDB_W8_A0_00, 0x400f0000 +.set CYFLD_UDB_W8_A0__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_A0__SIZE, 0x00000008 +.set CYREG_UDB_W8_A0_01, 0x400f0001 +.set CYREG_UDB_W8_A0_02, 0x400f0002 +.set CYREG_UDB_W8_A0_03, 0x400f0003 +.set CYREG_UDB_W8_A1_00, 0x400f0010 +.set CYFLD_UDB_W8_A1__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_A1__SIZE, 0x00000008 +.set CYREG_UDB_W8_A1_01, 0x400f0011 +.set CYREG_UDB_W8_A1_02, 0x400f0012 +.set CYREG_UDB_W8_A1_03, 0x400f0013 +.set CYREG_UDB_W8_D0_00, 0x400f0020 +.set CYFLD_UDB_W8_D0__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_D0__SIZE, 0x00000008 +.set CYREG_UDB_W8_D0_01, 0x400f0021 +.set CYREG_UDB_W8_D0_02, 0x400f0022 +.set CYREG_UDB_W8_D0_03, 0x400f0023 +.set CYREG_UDB_W8_D1_00, 0x400f0030 +.set CYFLD_UDB_W8_D1__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_D1__SIZE, 0x00000008 +.set CYREG_UDB_W8_D1_01, 0x400f0031 +.set CYREG_UDB_W8_D1_02, 0x400f0032 +.set CYREG_UDB_W8_D1_03, 0x400f0033 +.set CYREG_UDB_W8_F0_00, 0x400f0040 +.set CYFLD_UDB_W8_F0__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_F0__SIZE, 0x00000008 +.set CYREG_UDB_W8_F0_01, 0x400f0041 +.set CYREG_UDB_W8_F0_02, 0x400f0042 +.set CYREG_UDB_W8_F0_03, 0x400f0043 +.set CYREG_UDB_W8_F1_00, 0x400f0050 +.set CYFLD_UDB_W8_F1__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_F1__SIZE, 0x00000008 +.set CYREG_UDB_W8_F1_01, 0x400f0051 +.set CYREG_UDB_W8_F1_02, 0x400f0052 +.set CYREG_UDB_W8_F1_03, 0x400f0053 +.set CYREG_UDB_W8_ST_00, 0x400f0060 +.set CYFLD_UDB_W8_ST__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_ST__SIZE, 0x00000008 +.set CYREG_UDB_W8_ST_01, 0x400f0061 +.set CYREG_UDB_W8_ST_02, 0x400f0062 +.set CYREG_UDB_W8_ST_03, 0x400f0063 +.set CYREG_UDB_W8_CTL_00, 0x400f0070 +.set CYFLD_UDB_W8_CTL__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_CTL__SIZE, 0x00000008 +.set CYREG_UDB_W8_CTL_01, 0x400f0071 +.set CYREG_UDB_W8_CTL_02, 0x400f0072 +.set CYREG_UDB_W8_CTL_03, 0x400f0073 +.set CYREG_UDB_W8_MSK_00, 0x400f0080 +.set CYFLD_UDB_W8_MSK__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_MSK__SIZE, 0x00000007 +.set CYREG_UDB_W8_MSK_01, 0x400f0081 +.set CYREG_UDB_W8_MSK_02, 0x400f0082 +.set CYREG_UDB_W8_MSK_03, 0x400f0083 +.set CYREG_UDB_W8_ACTL_00, 0x400f0090 +.set CYFLD_UDB_W8_FIFO0_CLR__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_FIFO0_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO0_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO0_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_W8_FIFO1_CLR__OFFSET, 0x00000001 +.set CYFLD_UDB_W8_FIFO1_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO1_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO1_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_W8_FIFO0_LVL__OFFSET, 0x00000002 +.set CYFLD_UDB_W8_FIFO0_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO0_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO0_LVL_MID, 0x00000001 +.set CYFLD_UDB_W8_FIFO1_LVL__OFFSET, 0x00000003 +.set CYFLD_UDB_W8_FIFO1_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO1_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO1_LVL_MID, 0x00000001 +.set CYFLD_UDB_W8_INT_EN__OFFSET, 0x00000004 +.set CYFLD_UDB_W8_INT_EN__SIZE, 0x00000001 +.set CYVAL_UDB_W8_INT_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_W8_INT_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_W8_CNT_START__OFFSET, 0x00000005 +.set CYFLD_UDB_W8_CNT_START__SIZE, 0x00000001 +.set CYVAL_UDB_W8_CNT_START_DISABLE, 0x00000000 +.set CYVAL_UDB_W8_CNT_START_ENABLE, 0x00000001 +.set CYREG_UDB_W8_ACTL_01, 0x400f0091 +.set CYREG_UDB_W8_ACTL_02, 0x400f0092 +.set CYREG_UDB_W8_ACTL_03, 0x400f0093 +.set CYREG_UDB_W8_MC_00, 0x400f00a0 +.set CYFLD_UDB_W8_PLD0_MC__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_PLD0_MC__SIZE, 0x00000004 +.set CYFLD_UDB_W8_PLD1_MC__OFFSET, 0x00000004 +.set CYFLD_UDB_W8_PLD1_MC__SIZE, 0x00000004 +.set CYREG_UDB_W8_MC_01, 0x400f00a1 +.set CYREG_UDB_W8_MC_02, 0x400f00a2 +.set CYREG_UDB_W8_MC_03, 0x400f00a3 +.set CYDEV_UDB_CAT16_BASE, 0x400f1000 +.set CYDEV_UDB_CAT16_SIZE, 0x00001000 +.set CYREG_UDB_CAT16_A_00, 0x400f1000 +.set CYFLD_UDB_CAT16_A0__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_A0__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_A1__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_A1__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_A_01, 0x400f1002 +.set CYREG_UDB_CAT16_A_02, 0x400f1004 +.set CYREG_UDB_CAT16_A_03, 0x400f1006 +.set CYREG_UDB_CAT16_D_00, 0x400f1040 +.set CYFLD_UDB_CAT16_D0__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_D0__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_D1__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_D1__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_D_01, 0x400f1042 +.set CYREG_UDB_CAT16_D_02, 0x400f1044 +.set CYREG_UDB_CAT16_D_03, 0x400f1046 +.set CYREG_UDB_CAT16_F_00, 0x400f1080 +.set CYFLD_UDB_CAT16_F0__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_F0__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_F1__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_F1__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_F_01, 0x400f1082 +.set CYREG_UDB_CAT16_F_02, 0x400f1084 +.set CYREG_UDB_CAT16_F_03, 0x400f1086 +.set CYREG_UDB_CAT16_CTL_ST_00, 0x400f10c0 +.set CYFLD_UDB_CAT16_ST__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_ST__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_CTL__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_CTL__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_CTL_ST_01, 0x400f10c2 +.set CYREG_UDB_CAT16_CTL_ST_02, 0x400f10c4 +.set CYREG_UDB_CAT16_CTL_ST_03, 0x400f10c6 +.set CYREG_UDB_CAT16_ACTL_MSK_00, 0x400f1100 +.set CYFLD_UDB_CAT16_MSK__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_MSK__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_FIFO0_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET, 0x00000009 +.set CYFLD_UDB_CAT16_FIFO1_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET, 0x0000000a +.set CYFLD_UDB_CAT16_FIFO0_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO0_LVL_MID, 0x00000001 +.set CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET, 0x0000000b +.set CYFLD_UDB_CAT16_FIFO1_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO1_LVL_MID, 0x00000001 +.set CYFLD_UDB_CAT16_INT_EN__OFFSET, 0x0000000c +.set CYFLD_UDB_CAT16_INT_EN__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_INT_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_CAT16_INT_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_CAT16_CNT_START__OFFSET, 0x0000000d +.set CYFLD_UDB_CAT16_CNT_START__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_CNT_START_DISABLE, 0x00000000 +.set CYVAL_UDB_CAT16_CNT_START_ENABLE, 0x00000001 +.set CYREG_UDB_CAT16_ACTL_MSK_01, 0x400f1102 +.set CYREG_UDB_CAT16_ACTL_MSK_02, 0x400f1104 +.set CYREG_UDB_CAT16_ACTL_MSK_03, 0x400f1106 +.set CYREG_UDB_CAT16_MC_00, 0x400f1140 +.set CYFLD_UDB_CAT16_PLD0_MC__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_PLD0_MC__SIZE, 0x00000004 +.set CYFLD_UDB_CAT16_PLD1_MC__OFFSET, 0x00000004 +.set CYFLD_UDB_CAT16_PLD1_MC__SIZE, 0x00000004 +.set CYREG_UDB_CAT16_MC_01, 0x400f1142 +.set CYREG_UDB_CAT16_MC_02, 0x400f1144 +.set CYREG_UDB_CAT16_MC_03, 0x400f1146 +.set CYDEV_UDB_W16_BASE, 0x400f1000 +.set CYDEV_UDB_W16_SIZE, 0x00001000 +.set CYREG_UDB_W16_A0_00, 0x400f1000 +.set CYFLD_UDB_W16_A0_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_A0_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_A0_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_A0_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_A0_01, 0x400f1002 +.set CYREG_UDB_W16_A0_02, 0x400f1004 +.set CYREG_UDB_W16_A1_00, 0x400f1020 +.set CYFLD_UDB_W16_A1_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_A1_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_A1_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_A1_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_A1_01, 0x400f1022 +.set CYREG_UDB_W16_A1_02, 0x400f1024 +.set CYREG_UDB_W16_D0_00, 0x400f1040 +.set CYFLD_UDB_W16_D0_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_D0_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_D0_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_D0_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_D0_01, 0x400f1042 +.set CYREG_UDB_W16_D0_02, 0x400f1044 +.set CYREG_UDB_W16_D1_00, 0x400f1060 +.set CYFLD_UDB_W16_D1_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_D1_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_D1_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_D1_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_D1_01, 0x400f1062 +.set CYREG_UDB_W16_D1_02, 0x400f1064 +.set CYREG_UDB_W16_F0_00, 0x400f1080 +.set CYFLD_UDB_W16_F0_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_F0_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_F0_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_F0_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_F0_01, 0x400f1082 +.set CYREG_UDB_W16_F0_02, 0x400f1084 +.set CYREG_UDB_W16_F1_00, 0x400f10a0 +.set CYFLD_UDB_W16_F1_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_F1_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_F1_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_F1_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_F1_01, 0x400f10a2 +.set CYREG_UDB_W16_F1_02, 0x400f10a4 +.set CYREG_UDB_W16_ST_00, 0x400f10c0 +.set CYFLD_UDB_W16_ST_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_ST_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_ST_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_ST_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_ST_01, 0x400f10c2 +.set CYREG_UDB_W16_ST_02, 0x400f10c4 +.set CYREG_UDB_W16_CTL_00, 0x400f10e0 +.set CYFLD_UDB_W16_CTL_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_CTL_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_CTL_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_CTL_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_CTL_01, 0x400f10e2 +.set CYREG_UDB_W16_CTL_02, 0x400f10e4 +.set CYREG_UDB_W16_MSK_00, 0x400f1100 +.set CYFLD_UDB_W16_MSK_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_MSK_LS__SIZE, 0x00000007 +.set CYFLD_UDB_W16_MSK_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_MSK_MS__SIZE, 0x00000007 +.set CYREG_UDB_W16_MSK_01, 0x400f1102 +.set CYREG_UDB_W16_MSK_02, 0x400f1104 +.set CYREG_UDB_W16_ACTL_00, 0x400f1120 +.set CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET, 0x00000002 +.set CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_LVL_LS_MID, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET, 0x00000003 +.set CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_LVL_LS_MID, 0x00000001 +.set CYFLD_UDB_W16_INT_EN_LS__OFFSET, 0x00000004 +.set CYFLD_UDB_W16_INT_EN_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_INT_EN_LS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_INT_EN_LS_ENABLE, 0x00000001 +.set CYFLD_UDB_W16_CNT_START_LS__OFFSET, 0x00000005 +.set CYFLD_UDB_W16_CNT_START_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_CNT_START_LS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_CNT_START_LS_ENABLE, 0x00000001 +.set CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET, 0x00000009 +.set CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET, 0x0000000a +.set CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_LVL_MS_MID, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET, 0x0000000b +.set CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_LVL_MS_MID, 0x00000001 +.set CYFLD_UDB_W16_INT_EN_MS__OFFSET, 0x0000000c +.set CYFLD_UDB_W16_INT_EN_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_INT_EN_MS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_INT_EN_MS_ENABLE, 0x00000001 +.set CYFLD_UDB_W16_CNT_START_MS__OFFSET, 0x0000000d +.set CYFLD_UDB_W16_CNT_START_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_CNT_START_MS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_CNT_START_MS_ENABLE, 0x00000001 +.set CYREG_UDB_W16_ACTL_01, 0x400f1122 +.set CYREG_UDB_W16_ACTL_02, 0x400f1124 +.set CYREG_UDB_W16_MC_00, 0x400f1140 +.set CYFLD_UDB_W16_PLD0_MC_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_PLD0_MC_LS__SIZE, 0x00000004 +.set CYFLD_UDB_W16_PLD1_MC_LS__OFFSET, 0x00000004 +.set CYFLD_UDB_W16_PLD1_MC_LS__SIZE, 0x00000004 +.set CYFLD_UDB_W16_PLD0_MC_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_PLD0_MC_MS__SIZE, 0x00000004 +.set CYFLD_UDB_W16_PLD1_MC_MS__OFFSET, 0x0000000c +.set CYFLD_UDB_W16_PLD1_MC_MS__SIZE, 0x00000004 +.set CYREG_UDB_W16_MC_01, 0x400f1142 +.set CYREG_UDB_W16_MC_02, 0x400f1144 +.set CYDEV_UDB_W32_BASE, 0x400f2000 +.set CYDEV_UDB_W32_SIZE, 0x00001000 +.set CYREG_UDB_W32_A0_00, 0x400f2000 +.set CYFLD_UDB_W32_A0_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_A0_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A0_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_A0_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A0_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_A0_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A0_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_A0_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_A1_00, 0x400f2040 +.set CYFLD_UDB_W32_A1_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_A1_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A1_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_A1_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A1_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_A1_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A1_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_A1_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_D0_00, 0x400f2080 +.set CYFLD_UDB_W32_D0_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_D0_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D0_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_D0_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D0_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_D0_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D0_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_D0_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_D1_00, 0x400f20c0 +.set CYFLD_UDB_W32_D1_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_D1_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D1_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_D1_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D1_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_D1_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D1_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_D1_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_F0_00, 0x400f2100 +.set CYFLD_UDB_W32_F0_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_F0_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F0_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_F0_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F0_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_F0_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F0_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_F0_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_F1_00, 0x400f2140 +.set CYFLD_UDB_W32_F1_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_F1_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F1_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_F1_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F1_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_F1_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F1_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_F1_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_ST_00, 0x400f2180 +.set CYFLD_UDB_W32_ST_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_ST_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_ST_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_ST_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_ST_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_ST_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_ST_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_ST_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_CTL_00, 0x400f21c0 +.set CYFLD_UDB_W32_CTL_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_CTL_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_CTL_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_CTL_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_CTL_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_CTL_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_CTL_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_CTL_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_MSK_00, 0x400f2200 +.set CYFLD_UDB_W32_MSK_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_MSK_0__SIZE, 0x00000007 +.set CYFLD_UDB_W32_MSK_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_MSK_1__SIZE, 0x00000007 +.set CYFLD_UDB_W32_MSK_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_MSK_2__SIZE, 0x00000007 +.set CYFLD_UDB_W32_MSK_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_MSK_3__SIZE, 0x00000007 +.set CYREG_UDB_W32_ACTL_00, 0x400f2240 +.set CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_FIFO0_CLR_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET, 0x00000002 +.set CYFLD_UDB_W32_FIFO0_LVL_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_0_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET, 0x00000003 +.set CYFLD_UDB_W32_FIFO1_LVL_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_0_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_0__OFFSET, 0x00000004 +.set CYFLD_UDB_W32_INT_EN_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_0_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_0_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_0__OFFSET, 0x00000005 +.set CYFLD_UDB_W32_CNT_START_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_0_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_0_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_FIFO0_CLR_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET, 0x00000009 +.set CYFLD_UDB_W32_FIFO1_CLR_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET, 0x0000000a +.set CYFLD_UDB_W32_FIFO0_LVL_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_1_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET, 0x0000000b +.set CYFLD_UDB_W32_FIFO1_LVL_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_1_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_1__OFFSET, 0x0000000c +.set CYFLD_UDB_W32_INT_EN_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_1_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_1_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_1__OFFSET, 0x0000000d +.set CYFLD_UDB_W32_CNT_START_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_1_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_1_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_FIFO0_CLR_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET, 0x00000011 +.set CYFLD_UDB_W32_FIFO1_CLR_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET, 0x00000012 +.set CYFLD_UDB_W32_FIFO0_LVL_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_2_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET, 0x00000013 +.set CYFLD_UDB_W32_FIFO1_LVL_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_2_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_2__OFFSET, 0x00000014 +.set CYFLD_UDB_W32_INT_EN_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_2_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_2_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_2__OFFSET, 0x00000015 +.set CYFLD_UDB_W32_CNT_START_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_2_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_2_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_FIFO0_CLR_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET, 0x00000019 +.set CYFLD_UDB_W32_FIFO1_CLR_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET, 0x0000001a +.set CYFLD_UDB_W32_FIFO0_LVL_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_3_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET, 0x0000001b +.set CYFLD_UDB_W32_FIFO1_LVL_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_3_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_3__OFFSET, 0x0000001c +.set CYFLD_UDB_W32_INT_EN_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_3_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_3_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_3__OFFSET, 0x0000001d +.set CYFLD_UDB_W32_CNT_START_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_3_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_3_ENABLE, 0x00000001 +.set CYREG_UDB_W32_MC_00, 0x400f2280 +.set CYFLD_UDB_W32_PLD0_MC_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_PLD0_MC_0__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_0__OFFSET, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_0__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD0_MC_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_PLD0_MC_1__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_1__OFFSET, 0x0000000c +.set CYFLD_UDB_W32_PLD1_MC_1__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD0_MC_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_PLD0_MC_2__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_2__OFFSET, 0x00000014 +.set CYFLD_UDB_W32_PLD1_MC_2__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD0_MC_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_PLD0_MC_3__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_3__OFFSET, 0x0000001c +.set CYFLD_UDB_W32_PLD1_MC_3__SIZE, 0x00000004 +.set CYDEV_UDB_P0_BASE, 0x400f3000 +.set CYDEV_UDB_P0_SIZE, 0x00000200 +.set CYDEV_UDB_P0_U0_BASE, 0x400f3000 +.set CYDEV_UDB_P0_U0_SIZE, 0x00000080 +.set CYREG_UDB_P0_U0_PLD_IT0, 0x400f3000 +.set CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET, 0x00000010 +.set CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET, 0x00000011 +.set CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET, 0x00000012 +.set CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET, 0x00000013 +.set CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET, 0x00000014 +.set CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET, 0x00000015 +.set CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET, 0x00000016 +.set CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET, 0x00000017 +.set CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET, 0x00000018 +.set CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET, 0x00000019 +.set CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET, 0x0000001a +.set CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET, 0x0000001b +.set CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET, 0x0000001c +.set CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET, 0x0000001d +.set CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET, 0x0000001e +.set CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET, 0x0000001f +.set CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_IT1, 0x400f3004 +.set CYREG_UDB_P0_U0_PLD_IT2, 0x400f3008 +.set CYREG_UDB_P0_U0_PLD_IT3, 0x400f300c +.set CYREG_UDB_P0_U0_PLD_IT4, 0x400f3010 +.set CYREG_UDB_P0_U0_PLD_IT5, 0x400f3014 +.set CYREG_UDB_P0_U0_PLD_IT6, 0x400f3018 +.set CYREG_UDB_P0_U0_PLD_IT7, 0x400f301c +.set CYREG_UDB_P0_U0_PLD_IT8, 0x400f3020 +.set CYREG_UDB_P0_U0_PLD_IT9, 0x400f3024 +.set CYREG_UDB_P0_U0_PLD_IT10, 0x400f3028 +.set CYREG_UDB_P0_U0_PLD_IT11, 0x400f302c +.set CYREG_UDB_P0_U0_PLD_ORT0, 0x400f3030 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_ORT1, 0x400f3032 +.set CYREG_UDB_P0_U0_PLD_ORT2, 0x400f3034 +.set CYREG_UDB_P0_U0_PLD_ORT3, 0x400f3036 +.set CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST, 0x400f3038 +.set CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB, 0x400f303a +.set CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L, 0x00000003 +.set CYREG_UDB_P0_U0_PLD_MC_SET_RESET, 0x400f303c +.set CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS, 0x400f303e +.set CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_NC1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC3__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_NC3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC5__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_NC5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC7__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_NC7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC9__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_NC9__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC11__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_NC11__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC13__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_NC13__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC15__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_NC15__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG0, 0x400f3040 +.set CYFLD_UDB_P_U_RAD0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RAD0__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_RAD0_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RAD0_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_RAD0_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_RAD0_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_RAD0_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_RAD0_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_RAD0_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_RAD0_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_RAD1__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_RAD1__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_RAD1_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RAD1_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_RAD1_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_RAD1_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_RAD1_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_RAD1_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_RAD1_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_RAD1_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG1, 0x400f3041 +.set CYFLD_UDB_P_U_RAD2__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RAD2__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_RAD2_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RAD2_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_RAD2_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_RAD2_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_RAD2_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_RAD2_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_RAD2_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_RAD2_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS, 0x00000001 +.set CYREG_UDB_P0_U0_CFG2, 0x400f3042 +.set CYFLD_UDB_P_U_F0_LD__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_F0_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_F0_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_F0_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_F0_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_F0_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_F0_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_F0_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_F0_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_F0_LD_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_F1_LD__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_F1_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_F1_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_F1_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_F1_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_F1_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_F1_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_F1_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_F1_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_F1_LD_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG3, 0x400f3043 +.set CYFLD_UDB_P_U_D0_LD__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_D0_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_D0_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_D0_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_D0_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_D0_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_D0_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_D0_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_D0_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_D0_LD_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_D1_LD__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_D1_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_D1_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_D1_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_D1_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_D1_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_D1_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_D1_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_D1_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_D1_LD_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG4, 0x400f3044 +.set CYFLD_UDB_P_U_SI_MUX__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_SI_MUX__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_SI_MUX_OFF, 0x00000000 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_SI_MUX_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_CI_MUX__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_CI_MUX__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_CI_MUX_OFF, 0x00000000 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_CI_MUX_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG5, 0x400f3045 +.set CYFLD_UDB_P_U_OUT0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT0__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT0_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT0_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT0_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT0_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT0_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT0_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT0_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT0_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT0_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT0_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT0_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT0_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT0_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT0_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT0_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT0_F1_BUS_STAT, 0x0000000f +.set CYFLD_UDB_P_U_OUT1__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_OUT1__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT1_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT1_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT1_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT1_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT1_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT1_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT1_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT1_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT1_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT1_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT1_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT1_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT1_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT1_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT1_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT1_F1_BUS_STAT, 0x0000000f +.set CYREG_UDB_P0_U0_CFG6, 0x400f3046 +.set CYFLD_UDB_P_U_OUT2__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT2__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT2_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT2_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT2_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT2_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT2_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT2_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT2_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT2_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT2_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT2_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT2_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT2_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT2_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT2_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT2_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT2_F1_BUS_STAT, 0x0000000f +.set CYFLD_UDB_P_U_OUT3__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_OUT3__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT3_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT3_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT3_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT3_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT3_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT3_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT3_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT3_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT3_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT3_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT3_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT3_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT3_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT3_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT3_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT3_F1_BUS_STAT, 0x0000000f +.set CYREG_UDB_P0_U0_CFG7, 0x400f3047 +.set CYFLD_UDB_P_U_OUT4__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT4__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT4_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT4_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT4_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT4_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT4_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT4_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT4_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT4_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT4_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT4_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT4_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT4_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT4_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT4_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT4_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT4_F1_BUS_STAT, 0x0000000f +.set CYFLD_UDB_P_U_OUT5__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_OUT5__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT5_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT5_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT5_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT5_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT5_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT5_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT5_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT5_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT5_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT5_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT5_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT5_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT5_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT5_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT5_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT5_F1_BUS_STAT, 0x0000000f +.set CYREG_UDB_P0_U0_CFG8, 0x400f3048 +.set CYFLD_UDB_P_U_OUT_SYNC__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT_SYNC__SIZE, 0x00000006 +.set CYVAL_UDB_P_U_OUT_SYNC_REGISTERED, 0x00000000 +.set CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC6__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_NC6__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG9, 0x400f3049 +.set CYFLD_UDB_P_U_AMASK__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_AMASK__SIZE, 0x00000008 +.set CYREG_UDB_P0_U0_CFG10, 0x400f304a +.set CYFLD_UDB_P_U_CMASK0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CMASK0__SIZE, 0x00000008 +.set CYREG_UDB_P0_U0_CFG11, 0x400f304b +.set CYREG_UDB_P0_U0_CFG12, 0x400f304c +.set CYFLD_UDB_P_U_SI_SELA__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_SI_SELA__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELA_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_SI_SELA_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_SI_SELA_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELA_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_SI_SELB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_SI_SELB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELB_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_SI_SELB_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_SI_SELB_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELB_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_DEF_SI__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_DEF_SI__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DEF_SI_DEFAULT_0, 0x00000000 +.set CYVAL_UDB_P_U_DEF_SI_DEFAULT_1, 0x00000001 +.set CYFLD_UDB_P_U_AMASK_EN__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_AMASK_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_AMASK_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_AMASK_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CMASK0_EN__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_CMASK0_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CMASK0_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CMASK0_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CMASK1_EN__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_CMASK1_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CMASK1_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CMASK1_EN_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG13, 0x400f304d +.set CYFLD_UDB_P_U_CI_SELA__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CI_SELA__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELA_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_CI_SELA_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_CI_SELA_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELA_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_CI_SELB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CI_SELB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELB_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_CI_SELB_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_CI_SELB_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELB_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_CMP_SELA__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_CMP_SELA__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELA_A1_D1, 0x00000000 +.set CYVAL_UDB_P_U_CMP_SELA_A1_A0, 0x00000001 +.set CYVAL_UDB_P_U_CMP_SELA_A0_D1, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELA_A0_A0, 0x00000003 +.set CYFLD_UDB_P_U_CMP_SELB__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_CMP_SELB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELB_A1_D1, 0x00000000 +.set CYVAL_UDB_P_U_CMP_SELB_A1_A0, 0x00000001 +.set CYVAL_UDB_P_U_CMP_SELB_A0_D1, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELB_A0_A0, 0x00000003 +.set CYREG_UDB_P0_U0_CFG14, 0x400f304e +.set CYFLD_UDB_P_U_CHAIN0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CHAIN0__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN0_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN0_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN1__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN1_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN1_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN_FB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CHAIN_FB__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN_FB_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN_FB_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_CHAIN_CMSB__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_MSB_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_MSB_SEL__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_MSB_SEL_BIT0, 0x00000000 +.set CYVAL_UDB_P_U_MSB_SEL_BIT1, 0x00000001 +.set CYVAL_UDB_P_U_MSB_SEL_BIT2, 0x00000002 +.set CYVAL_UDB_P_U_MSB_SEL_BIT3, 0x00000003 +.set CYVAL_UDB_P_U_MSB_SEL_BIT4, 0x00000004 +.set CYVAL_UDB_P_U_MSB_SEL_BIT5, 0x00000005 +.set CYVAL_UDB_P_U_MSB_SEL_BIT6, 0x00000006 +.set CYVAL_UDB_P_U_MSB_SEL_BIT7, 0x00000007 +.set CYFLD_UDB_P_U_MSB_EN__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_MSB_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_MSB_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_MSB_EN_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG15, 0x400f304f +.set CYFLD_UDB_P_U_F0_INSEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_F0_INSEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_F0_INSEL_INPUT, 0x00000000 +.set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0, 0x00000001 +.set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1, 0x00000002 +.set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU, 0x00000003 +.set CYFLD_UDB_P_U_F1_INSEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_F1_INSEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_F1_INSEL_INPUT, 0x00000000 +.set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0, 0x00000001 +.set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1, 0x00000002 +.set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU, 0x00000003 +.set CYFLD_UDB_P_U_MSB_SI__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_MSB_SI__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_MSB_SI_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_MSB_SI_MSB, 0x00000001 +.set CYFLD_UDB_P_U_PI_DYN__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PI_DYN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PI_DYN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PI_DYN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_SHIFT_SEL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_SHIFT_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB, 0x00000000 +.set CYVAL_UDB_P_U_SHIFT_SEL_SOR, 0x00000001 +.set CYFLD_UDB_P_U_PI_SEL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PI_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PI_SEL_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_PI_SEL_PARALLEL, 0x00000001 +.set CYREG_UDB_P0_U0_CFG16, 0x400f3050 +.set CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_WRK16_CONCAT__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE, 0x00000001 +.set CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_EXT_CRCPRS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL, 0x00000000 +.set CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_FIFO_ASYNC__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_EDGE__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_FIFO_EDGE__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_EDGE_LEVEL, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_EDGE_EDGE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_CAP__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_FIFO_CAP__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_CAP_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_CAP_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_FAST__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_FIFO_FAST__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_FAST_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_FAST_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_F0_CK_INV__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_F0_CK_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F0_CK_INV_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_F0_CK_INV_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_F1_CK_INV__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_F1_CK_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F1_CK_INV_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_F1_CK_INV_INVERT, 0x00000001 +.set CYREG_UDB_P0_U0_CFG17, 0x400f3051 +.set CYFLD_UDB_P_U_F0_DYN__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_F0_DYN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F0_DYN_STATIC, 0x00000000 +.set CYVAL_UDB_P_U_F0_DYN_DYNAMIC, 0x00000001 +.set CYFLD_UDB_P_U_F1_DYN__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_F1_DYN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F1_DYN_STATIC, 0x00000000 +.set CYVAL_UDB_P_U_F1_DYN_DYNAMIC, 0x00000001 +.set CYFLD_UDB_P_U_NC2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_NC2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG18, 0x400f3052 +.set CYFLD_UDB_P_U_CTL_MD0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CTL_MD0__SIZE, 0x00000008 +.set CYVAL_UDB_P_U_CTL_MD0_DIRECT, 0x00000000 +.set CYVAL_UDB_P_U_CTL_MD0_SYNC, 0x00000001 +.set CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC, 0x00000002 +.set CYVAL_UDB_P_U_CTL_MD0_PULSE, 0x00000003 +.set CYREG_UDB_P0_U0_CFG19, 0x400f3053 +.set CYFLD_UDB_P_U_CTL_MD1__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CTL_MD1__SIZE, 0x00000008 +.set CYVAL_UDB_P_U_CTL_MD1_DIRECT, 0x00000000 +.set CYVAL_UDB_P_U_CTL_MD1_SYNC, 0x00000001 +.set CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC, 0x00000002 +.set CYVAL_UDB_P_U_CTL_MD1_PULSE, 0x00000003 +.set CYREG_UDB_P0_U0_CFG20, 0x400f3054 +.set CYFLD_UDB_P_U_STAT_MD__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_STAT_MD__SIZE, 0x00000008 +.set CYREG_UDB_P0_U0_CFG21, 0x400f3055 +.set CYFLD_UDB_P_U_NC0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_NC0__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG22, 0x400f3056 +.set CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_SC_OUT_CTL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL, 0x00000000 +.set CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL, 0x00000001 +.set CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER, 0x00000002 +.set CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED, 0x00000003 +.set CYFLD_UDB_P_U_SC_INT_MD__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_SC_INT_MD__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_INT_MD_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_SC_INT_MD_INT_MODE, 0x00000001 +.set CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_SC_SYNC_MD__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE, 0x00000001 +.set CYFLD_UDB_P_U_SC_EXT_RES__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_SC_EXT_RES__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_EXT_RES_DISABLED, 0x00000000 +.set CYVAL_UDB_P_U_SC_EXT_RES_ENABLED, 0x00000001 +.set CYREG_UDB_P0_U0_CFG23, 0x400f3057 +.set CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CNT_LD_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CNT_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4, 0x00000000 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5, 0x00000001 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6, 0x00000002 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO, 0x00000003 +.set CYFLD_UDB_P_U_ROUTE_LD__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_ROUTE_LD__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ROUTE_LD_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_ROUTE_LD_ROUTED, 0x00000001 +.set CYFLD_UDB_P_U_ROUTE_EN__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_ROUTE_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ROUTE_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_ROUTE_EN_ROUTED, 0x00000001 +.set CYFLD_UDB_P_U_ALT_CNT__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_ALT_CNT__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE, 0x00000000 +.set CYVAL_UDB_P_U_ALT_CNT_ALT_MODE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG24, 0x400f3058 +.set CYFLD_UDB_P_U_RC_EN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RC_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_RC_EN_MODE__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_RC_EN_MODE__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_MODE_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RC_EN_MODE_ON, 0x00000001 +.set CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_MODE_LEVEL, 0x00000003 +.set CYFLD_UDB_P_U_RC_EN_INV__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_RC_EN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_RC_EN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_RC_EN_INV_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_RC_INV__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_RC_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_RC_INV_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_RC_INV_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_RC_RES_SEL1__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG25, 0x400f3059 +.set CYREG_UDB_P0_U0_CFG26, 0x400f305a +.set CYREG_UDB_P0_U0_CFG27, 0x400f305b +.set CYREG_UDB_P0_U0_CFG28, 0x400f305c +.set CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK, 0x00000009 +.set CYREG_UDB_P0_U0_CFG29, 0x400f305d +.set CYFLD_UDB_P_U_DP_CK_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_DP_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK, 0x00000009 +.set CYFLD_UDB_P_U_SC_CK_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_SC_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK, 0x00000009 +.set CYREG_UDB_P0_U0_CFG30, 0x400f305e +.set CYFLD_UDB_P_U_RES_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RES_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_RES_POL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_RES_POL_NEGATED, 0x00000000 +.set CYVAL_UDB_P_U_RES_POL_ASSERTED, 0x00000001 +.set CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_GUDB_WR__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_GUDB_WR__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_GUDB_WR_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_GUDB_WR_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_DP_RES_POL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_DP_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_DP_RES_POL_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_SC_RES_POL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_SC_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_SC_RES_POL_INVERT, 0x00000001 +.set CYREG_UDB_P0_U0_CFG31, 0x400f305f +.set CYFLD_UDB_P_U_ALT_RES__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_ALT_RES__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ALT_RES_COMPATIBLE, 0x00000000 +.set CYVAL_UDB_P_U_ALT_RES_ALTERNATE, 0x00000001 +.set CYFLD_UDB_P_U_EXT_SYNC__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_EXT_SYNC__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EXT_SYNC_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_EXT_SYNC_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_EN_RES_STAT__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_EN_RES_STAT__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EN_RES_STAT_NEGATED, 0x00000000 +.set CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED, 0x00000001 +.set CYFLD_UDB_P_U_EN_RES_DP__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_EN_RES_DP__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EN_RES_DP_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_EN_RES_DP_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_EXT_CK_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_RES_POL_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD1_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_RES_POL_INVERT, 0x00000001 +.set CYREG_UDB_P0_U0_DCFG0, 0x400f3060 +.set CYFLD_UDB_P_U_CMP_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CMP_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CMP_SEL_CFG_A, 0x00000000 +.set CYVAL_UDB_P_U_CMP_SEL_CFG_B, 0x00000001 +.set CYFLD_UDB_P_U_SI_SEL__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_SI_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SI_SEL_CFG_A, 0x00000000 +.set CYVAL_UDB_P_U_SI_SEL_CFG_B, 0x00000001 +.set CYFLD_UDB_P_U_CI_SEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CI_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CI_SEL_CFG_A, 0x00000000 +.set CYVAL_UDB_P_U_CI_SEL_CFG_B, 0x00000001 +.set CYFLD_UDB_P_U_CFB_EN__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_CFB_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CFB_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CFB_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_A1_WR_SRC__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_A1_WR_SRC__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE, 0x00000000 +.set CYVAL_UDB_P_U_A1_WR_SRC_ALU, 0x00000001 +.set CYVAL_UDB_P_U_A1_WR_SRC_D1, 0x00000002 +.set CYVAL_UDB_P_U_A1_WR_SRC_F1, 0x00000003 +.set CYFLD_UDB_P_U_A0_WR_SRC__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_A0_WR_SRC__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE, 0x00000000 +.set CYVAL_UDB_P_U_A0_WR_SRC_ALU, 0x00000001 +.set CYVAL_UDB_P_U_A0_WR_SRC_D0, 0x00000002 +.set CYVAL_UDB_P_U_A0_WR_SRC_F0, 0x00000003 +.set CYFLD_UDB_P_U_SHIFT__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_SHIFT__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SHIFT_NOSHIFT, 0x00000000 +.set CYVAL_UDB_P_U_SHIFT_LEFT, 0x00000001 +.set CYVAL_UDB_P_U_SHIFT_RIGHT, 0x00000002 +.set CYVAL_UDB_P_U_SHIFT_SWAP, 0x00000003 +.set CYFLD_UDB_P_U_SRC_B__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_SRC_B__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SRC_B_D0, 0x00000000 +.set CYVAL_UDB_P_U_SRC_B_D1, 0x00000001 +.set CYVAL_UDB_P_U_SRC_B_A0, 0x00000002 +.set CYVAL_UDB_P_U_SRC_B_A1, 0x00000003 +.set CYFLD_UDB_P_U_SRC_A__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_SRC_A__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SRC_A_A0, 0x00000000 +.set CYVAL_UDB_P_U_SRC_A_A1, 0x00000001 +.set CYFLD_UDB_P_U_FUNC__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_FUNC__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_FUNC_PASS, 0x00000000 +.set CYVAL_UDB_P_U_FUNC_INC_A, 0x00000001 +.set CYVAL_UDB_P_U_FUNC_DEC_A, 0x00000002 +.set CYVAL_UDB_P_U_FUNC_ADD, 0x00000003 +.set CYVAL_UDB_P_U_FUNC_SUB, 0x00000004 +.set CYVAL_UDB_P_U_FUNC_XOR, 0x00000005 +.set CYVAL_UDB_P_U_FUNC_AND, 0x00000006 +.set CYVAL_UDB_P_U_FUNC_OR, 0x00000007 +.set CYREG_UDB_P0_U0_DCFG1, 0x400f3062 +.set CYREG_UDB_P0_U0_DCFG2, 0x400f3064 +.set CYREG_UDB_P0_U0_DCFG3, 0x400f3066 +.set CYREG_UDB_P0_U0_DCFG4, 0x400f3068 +.set CYREG_UDB_P0_U0_DCFG5, 0x400f306a +.set CYREG_UDB_P0_U0_DCFG6, 0x400f306c +.set CYREG_UDB_P0_U0_DCFG7, 0x400f306e +.set CYDEV_UDB_P0_U1_BASE, 0x400f3080 +.set CYDEV_UDB_P0_U1_SIZE, 0x00000080 +.set CYREG_UDB_P0_U1_PLD_IT0, 0x400f3080 +.set CYREG_UDB_P0_U1_PLD_IT1, 0x400f3084 +.set CYREG_UDB_P0_U1_PLD_IT2, 0x400f3088 +.set CYREG_UDB_P0_U1_PLD_IT3, 0x400f308c +.set CYREG_UDB_P0_U1_PLD_IT4, 0x400f3090 +.set CYREG_UDB_P0_U1_PLD_IT5, 0x400f3094 +.set CYREG_UDB_P0_U1_PLD_IT6, 0x400f3098 +.set CYREG_UDB_P0_U1_PLD_IT7, 0x400f309c +.set CYREG_UDB_P0_U1_PLD_IT8, 0x400f30a0 +.set CYREG_UDB_P0_U1_PLD_IT9, 0x400f30a4 +.set CYREG_UDB_P0_U1_PLD_IT10, 0x400f30a8 +.set CYREG_UDB_P0_U1_PLD_IT11, 0x400f30ac +.set CYREG_UDB_P0_U1_PLD_ORT0, 0x400f30b0 +.set CYREG_UDB_P0_U1_PLD_ORT1, 0x400f30b2 +.set CYREG_UDB_P0_U1_PLD_ORT2, 0x400f30b4 +.set CYREG_UDB_P0_U1_PLD_ORT3, 0x400f30b6 +.set CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST, 0x400f30b8 +.set CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB, 0x400f30ba +.set CYREG_UDB_P0_U1_PLD_MC_SET_RESET, 0x400f30bc +.set CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS, 0x400f30be +.set CYREG_UDB_P0_U1_CFG0, 0x400f30c0 +.set CYREG_UDB_P0_U1_CFG1, 0x400f30c1 +.set CYREG_UDB_P0_U1_CFG2, 0x400f30c2 +.set CYREG_UDB_P0_U1_CFG3, 0x400f30c3 +.set CYREG_UDB_P0_U1_CFG4, 0x400f30c4 +.set CYREG_UDB_P0_U1_CFG5, 0x400f30c5 +.set CYREG_UDB_P0_U1_CFG6, 0x400f30c6 +.set CYREG_UDB_P0_U1_CFG7, 0x400f30c7 +.set CYREG_UDB_P0_U1_CFG8, 0x400f30c8 +.set CYREG_UDB_P0_U1_CFG9, 0x400f30c9 +.set CYREG_UDB_P0_U1_CFG10, 0x400f30ca +.set CYREG_UDB_P0_U1_CFG11, 0x400f30cb +.set CYREG_UDB_P0_U1_CFG12, 0x400f30cc +.set CYREG_UDB_P0_U1_CFG13, 0x400f30cd +.set CYREG_UDB_P0_U1_CFG14, 0x400f30ce +.set CYREG_UDB_P0_U1_CFG15, 0x400f30cf +.set CYREG_UDB_P0_U1_CFG16, 0x400f30d0 +.set CYREG_UDB_P0_U1_CFG17, 0x400f30d1 +.set CYREG_UDB_P0_U1_CFG18, 0x400f30d2 +.set CYREG_UDB_P0_U1_CFG19, 0x400f30d3 +.set CYREG_UDB_P0_U1_CFG20, 0x400f30d4 +.set CYREG_UDB_P0_U1_CFG21, 0x400f30d5 +.set CYREG_UDB_P0_U1_CFG22, 0x400f30d6 +.set CYREG_UDB_P0_U1_CFG23, 0x400f30d7 +.set CYREG_UDB_P0_U1_CFG24, 0x400f30d8 +.set CYREG_UDB_P0_U1_CFG25, 0x400f30d9 +.set CYREG_UDB_P0_U1_CFG26, 0x400f30da +.set CYREG_UDB_P0_U1_CFG27, 0x400f30db +.set CYREG_UDB_P0_U1_CFG28, 0x400f30dc +.set CYREG_UDB_P0_U1_CFG29, 0x400f30dd +.set CYREG_UDB_P0_U1_CFG30, 0x400f30de +.set CYREG_UDB_P0_U1_CFG31, 0x400f30df +.set CYREG_UDB_P0_U1_DCFG0, 0x400f30e0 +.set CYREG_UDB_P0_U1_DCFG1, 0x400f30e2 +.set CYREG_UDB_P0_U1_DCFG2, 0x400f30e4 +.set CYREG_UDB_P0_U1_DCFG3, 0x400f30e6 +.set CYREG_UDB_P0_U1_DCFG4, 0x400f30e8 +.set CYREG_UDB_P0_U1_DCFG5, 0x400f30ea +.set CYREG_UDB_P0_U1_DCFG6, 0x400f30ec +.set CYREG_UDB_P0_U1_DCFG7, 0x400f30ee +.set CYDEV_UDB_P0_ROUTE_BASE, 0x400f3100 +.set CYDEV_UDB_P0_ROUTE_SIZE, 0x00000100 +.set CYREG_UDB_P0_ROUTE_HC0, 0x400f3100 +.set CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_P0_ROUTE_HC1, 0x400f3101 +.set CYREG_UDB_P0_ROUTE_HC2, 0x400f3102 +.set CYREG_UDB_P0_ROUTE_HC3, 0x400f3103 +.set CYREG_UDB_P0_ROUTE_HC4, 0x400f3104 +.set CYREG_UDB_P0_ROUTE_HC5, 0x400f3105 +.set CYREG_UDB_P0_ROUTE_HC6, 0x400f3106 +.set CYREG_UDB_P0_ROUTE_HC7, 0x400f3107 +.set CYREG_UDB_P0_ROUTE_HC8, 0x400f3108 +.set CYREG_UDB_P0_ROUTE_HC9, 0x400f3109 +.set CYREG_UDB_P0_ROUTE_HC10, 0x400f310a +.set CYREG_UDB_P0_ROUTE_HC11, 0x400f310b +.set CYREG_UDB_P0_ROUTE_HC12, 0x400f310c +.set CYREG_UDB_P0_ROUTE_HC13, 0x400f310d +.set CYREG_UDB_P0_ROUTE_HC14, 0x400f310e +.set CYREG_UDB_P0_ROUTE_HC15, 0x400f310f +.set CYREG_UDB_P0_ROUTE_HC16, 0x400f3110 +.set CYREG_UDB_P0_ROUTE_HC17, 0x400f3111 +.set CYREG_UDB_P0_ROUTE_HC18, 0x400f3112 +.set CYREG_UDB_P0_ROUTE_HC19, 0x400f3113 +.set CYREG_UDB_P0_ROUTE_HC20, 0x400f3114 +.set CYREG_UDB_P0_ROUTE_HC21, 0x400f3115 +.set CYREG_UDB_P0_ROUTE_HC22, 0x400f3116 +.set CYREG_UDB_P0_ROUTE_HC23, 0x400f3117 +.set CYREG_UDB_P0_ROUTE_HC24, 0x400f3118 +.set CYREG_UDB_P0_ROUTE_HC25, 0x400f3119 +.set CYREG_UDB_P0_ROUTE_HC26, 0x400f311a +.set CYREG_UDB_P0_ROUTE_HC27, 0x400f311b +.set CYREG_UDB_P0_ROUTE_HC28, 0x400f311c +.set CYREG_UDB_P0_ROUTE_HC29, 0x400f311d +.set CYREG_UDB_P0_ROUTE_HC30, 0x400f311e +.set CYREG_UDB_P0_ROUTE_HC31, 0x400f311f +.set CYREG_UDB_P0_ROUTE_HC32, 0x400f3120 +.set CYREG_UDB_P0_ROUTE_HC33, 0x400f3121 +.set CYREG_UDB_P0_ROUTE_HC34, 0x400f3122 +.set CYREG_UDB_P0_ROUTE_HC35, 0x400f3123 +.set CYREG_UDB_P0_ROUTE_HC36, 0x400f3124 +.set CYREG_UDB_P0_ROUTE_HC37, 0x400f3125 +.set CYREG_UDB_P0_ROUTE_HC38, 0x400f3126 +.set CYREG_UDB_P0_ROUTE_HC39, 0x400f3127 +.set CYREG_UDB_P0_ROUTE_HC40, 0x400f3128 +.set CYREG_UDB_P0_ROUTE_HC41, 0x400f3129 +.set CYREG_UDB_P0_ROUTE_HC42, 0x400f312a +.set CYREG_UDB_P0_ROUTE_HC43, 0x400f312b +.set CYREG_UDB_P0_ROUTE_HC44, 0x400f312c +.set CYREG_UDB_P0_ROUTE_HC45, 0x400f312d +.set CYREG_UDB_P0_ROUTE_HC46, 0x400f312e +.set CYREG_UDB_P0_ROUTE_HC47, 0x400f312f +.set CYREG_UDB_P0_ROUTE_HC48, 0x400f3130 +.set CYREG_UDB_P0_ROUTE_HC49, 0x400f3131 +.set CYREG_UDB_P0_ROUTE_HC50, 0x400f3132 +.set CYREG_UDB_P0_ROUTE_HC51, 0x400f3133 +.set CYREG_UDB_P0_ROUTE_HC52, 0x400f3134 +.set CYREG_UDB_P0_ROUTE_HC53, 0x400f3135 +.set CYREG_UDB_P0_ROUTE_HC54, 0x400f3136 +.set CYREG_UDB_P0_ROUTE_HC55, 0x400f3137 +.set CYREG_UDB_P0_ROUTE_HC56, 0x400f3138 +.set CYREG_UDB_P0_ROUTE_HC57, 0x400f3139 +.set CYREG_UDB_P0_ROUTE_HC58, 0x400f313a +.set CYREG_UDB_P0_ROUTE_HC59, 0x400f313b +.set CYREG_UDB_P0_ROUTE_HC60, 0x400f313c +.set CYREG_UDB_P0_ROUTE_HC61, 0x400f313d +.set CYREG_UDB_P0_ROUTE_HC62, 0x400f313e +.set CYREG_UDB_P0_ROUTE_HC63, 0x400f313f +.set CYREG_UDB_P0_ROUTE_HC64, 0x400f3140 +.set CYREG_UDB_P0_ROUTE_HC65, 0x400f3141 +.set CYREG_UDB_P0_ROUTE_HC66, 0x400f3142 +.set CYREG_UDB_P0_ROUTE_HC67, 0x400f3143 +.set CYREG_UDB_P0_ROUTE_HC68, 0x400f3144 +.set CYREG_UDB_P0_ROUTE_HC69, 0x400f3145 +.set CYREG_UDB_P0_ROUTE_HC70, 0x400f3146 +.set CYREG_UDB_P0_ROUTE_HC71, 0x400f3147 +.set CYREG_UDB_P0_ROUTE_HC72, 0x400f3148 +.set CYREG_UDB_P0_ROUTE_HC73, 0x400f3149 +.set CYREG_UDB_P0_ROUTE_HC74, 0x400f314a +.set CYREG_UDB_P0_ROUTE_HC75, 0x400f314b +.set CYREG_UDB_P0_ROUTE_HC76, 0x400f314c +.set CYREG_UDB_P0_ROUTE_HC77, 0x400f314d +.set CYREG_UDB_P0_ROUTE_HC78, 0x400f314e +.set CYREG_UDB_P0_ROUTE_HC79, 0x400f314f +.set CYREG_UDB_P0_ROUTE_HC80, 0x400f3150 +.set CYREG_UDB_P0_ROUTE_HC81, 0x400f3151 +.set CYREG_UDB_P0_ROUTE_HC82, 0x400f3152 +.set CYREG_UDB_P0_ROUTE_HC83, 0x400f3153 +.set CYREG_UDB_P0_ROUTE_HC84, 0x400f3154 +.set CYREG_UDB_P0_ROUTE_HC85, 0x400f3155 +.set CYREG_UDB_P0_ROUTE_HC86, 0x400f3156 +.set CYREG_UDB_P0_ROUTE_HC87, 0x400f3157 +.set CYREG_UDB_P0_ROUTE_HC88, 0x400f3158 +.set CYREG_UDB_P0_ROUTE_HC89, 0x400f3159 +.set CYREG_UDB_P0_ROUTE_HC90, 0x400f315a +.set CYREG_UDB_P0_ROUTE_HC91, 0x400f315b +.set CYREG_UDB_P0_ROUTE_HC92, 0x400f315c +.set CYREG_UDB_P0_ROUTE_HC93, 0x400f315d +.set CYREG_UDB_P0_ROUTE_HC94, 0x400f315e +.set CYREG_UDB_P0_ROUTE_HC95, 0x400f315f +.set CYREG_UDB_P0_ROUTE_HC96, 0x400f3160 +.set CYREG_UDB_P0_ROUTE_HC97, 0x400f3161 +.set CYREG_UDB_P0_ROUTE_HC98, 0x400f3162 +.set CYREG_UDB_P0_ROUTE_HC99, 0x400f3163 +.set CYREG_UDB_P0_ROUTE_HC100, 0x400f3164 +.set CYREG_UDB_P0_ROUTE_HC101, 0x400f3165 +.set CYREG_UDB_P0_ROUTE_HC102, 0x400f3166 +.set CYREG_UDB_P0_ROUTE_HC103, 0x400f3167 +.set CYREG_UDB_P0_ROUTE_HC104, 0x400f3168 +.set CYREG_UDB_P0_ROUTE_HC105, 0x400f3169 +.set CYREG_UDB_P0_ROUTE_HC106, 0x400f316a +.set CYREG_UDB_P0_ROUTE_HC107, 0x400f316b +.set CYREG_UDB_P0_ROUTE_HC108, 0x400f316c +.set CYREG_UDB_P0_ROUTE_HC109, 0x400f316d +.set CYREG_UDB_P0_ROUTE_HC110, 0x400f316e +.set CYREG_UDB_P0_ROUTE_HC111, 0x400f316f +.set CYREG_UDB_P0_ROUTE_HC112, 0x400f3170 +.set CYREG_UDB_P0_ROUTE_HC113, 0x400f3171 +.set CYREG_UDB_P0_ROUTE_HC114, 0x400f3172 +.set CYREG_UDB_P0_ROUTE_HC115, 0x400f3173 +.set CYREG_UDB_P0_ROUTE_HC116, 0x400f3174 +.set CYREG_UDB_P0_ROUTE_HC117, 0x400f3175 +.set CYREG_UDB_P0_ROUTE_HC118, 0x400f3176 +.set CYREG_UDB_P0_ROUTE_HC119, 0x400f3177 +.set CYREG_UDB_P0_ROUTE_HC120, 0x400f3178 +.set CYREG_UDB_P0_ROUTE_HC121, 0x400f3179 +.set CYREG_UDB_P0_ROUTE_HC122, 0x400f317a +.set CYREG_UDB_P0_ROUTE_HC123, 0x400f317b +.set CYREG_UDB_P0_ROUTE_HC124, 0x400f317c +.set CYREG_UDB_P0_ROUTE_HC125, 0x400f317d +.set CYREG_UDB_P0_ROUTE_HC126, 0x400f317e +.set CYREG_UDB_P0_ROUTE_HC127, 0x400f317f +.set CYREG_UDB_P0_ROUTE_HV_L0, 0x400f3180 +.set CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_P0_ROUTE_HV_L1, 0x400f3181 +.set CYREG_UDB_P0_ROUTE_HV_L2, 0x400f3182 +.set CYREG_UDB_P0_ROUTE_HV_L3, 0x400f3183 +.set CYREG_UDB_P0_ROUTE_HV_L4, 0x400f3184 +.set CYREG_UDB_P0_ROUTE_HV_L5, 0x400f3185 +.set CYREG_UDB_P0_ROUTE_HV_L6, 0x400f3186 +.set CYREG_UDB_P0_ROUTE_HV_L7, 0x400f3187 +.set CYREG_UDB_P0_ROUTE_HV_L8, 0x400f3188 +.set CYREG_UDB_P0_ROUTE_HV_L9, 0x400f3189 +.set CYREG_UDB_P0_ROUTE_HV_L10, 0x400f318a +.set CYREG_UDB_P0_ROUTE_HV_L11, 0x400f318b +.set CYREG_UDB_P0_ROUTE_HV_L12, 0x400f318c +.set CYREG_UDB_P0_ROUTE_HV_L13, 0x400f318d +.set CYREG_UDB_P0_ROUTE_HV_L14, 0x400f318e +.set CYREG_UDB_P0_ROUTE_HV_L15, 0x400f318f +.set CYREG_UDB_P0_ROUTE_HS0, 0x400f3190 +.set CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_P0_ROUTE_HS1, 0x400f3191 +.set CYREG_UDB_P0_ROUTE_HS2, 0x400f3192 +.set CYREG_UDB_P0_ROUTE_HS3, 0x400f3193 +.set CYREG_UDB_P0_ROUTE_HS4, 0x400f3194 +.set CYREG_UDB_P0_ROUTE_HS5, 0x400f3195 +.set CYREG_UDB_P0_ROUTE_HS6, 0x400f3196 +.set CYREG_UDB_P0_ROUTE_HS7, 0x400f3197 +.set CYREG_UDB_P0_ROUTE_HS8, 0x400f3198 +.set CYREG_UDB_P0_ROUTE_HS9, 0x400f3199 +.set CYREG_UDB_P0_ROUTE_HS10, 0x400f319a +.set CYREG_UDB_P0_ROUTE_HS11, 0x400f319b +.set CYREG_UDB_P0_ROUTE_HS12, 0x400f319c +.set CYREG_UDB_P0_ROUTE_HS13, 0x400f319d +.set CYREG_UDB_P0_ROUTE_HS14, 0x400f319e +.set CYREG_UDB_P0_ROUTE_HS15, 0x400f319f +.set CYREG_UDB_P0_ROUTE_HS16, 0x400f31a0 +.set CYREG_UDB_P0_ROUTE_HS17, 0x400f31a1 +.set CYREG_UDB_P0_ROUTE_HS18, 0x400f31a2 +.set CYREG_UDB_P0_ROUTE_HS19, 0x400f31a3 +.set CYREG_UDB_P0_ROUTE_HS20, 0x400f31a4 +.set CYREG_UDB_P0_ROUTE_HS21, 0x400f31a5 +.set CYREG_UDB_P0_ROUTE_HS22, 0x400f31a6 +.set CYREG_UDB_P0_ROUTE_HS23, 0x400f31a7 +.set CYREG_UDB_P0_ROUTE_HV_R0, 0x400f31a8 +.set CYREG_UDB_P0_ROUTE_HV_R1, 0x400f31a9 +.set CYREG_UDB_P0_ROUTE_HV_R2, 0x400f31aa +.set CYREG_UDB_P0_ROUTE_HV_R3, 0x400f31ab +.set CYREG_UDB_P0_ROUTE_HV_R4, 0x400f31ac +.set CYREG_UDB_P0_ROUTE_HV_R5, 0x400f31ad +.set CYREG_UDB_P0_ROUTE_HV_R6, 0x400f31ae +.set CYREG_UDB_P0_ROUTE_HV_R7, 0x400f31af +.set CYREG_UDB_P0_ROUTE_HV_R8, 0x400f31b0 +.set CYREG_UDB_P0_ROUTE_HV_R9, 0x400f31b1 +.set CYREG_UDB_P0_ROUTE_HV_R10, 0x400f31b2 +.set CYREG_UDB_P0_ROUTE_HV_R11, 0x400f31b3 +.set CYREG_UDB_P0_ROUTE_HV_R12, 0x400f31b4 +.set CYREG_UDB_P0_ROUTE_HV_R13, 0x400f31b5 +.set CYREG_UDB_P0_ROUTE_HV_R14, 0x400f31b6 +.set CYREG_UDB_P0_ROUTE_HV_R15, 0x400f31b7 +.set CYREG_UDB_P0_ROUTE_PLD0IN0, 0x400f31c0 +.set CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_PI_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_P_ROUTE_PI_BOT__SIZE, 0x00000004 +.set CYREG_UDB_P0_ROUTE_PLD0IN1, 0x400f31c2 +.set CYREG_UDB_P0_ROUTE_PLD0IN2, 0x400f31c4 +.set CYREG_UDB_P0_ROUTE_PLD1IN0, 0x400f31ca +.set CYREG_UDB_P0_ROUTE_PLD1IN1, 0x400f31cc +.set CYREG_UDB_P0_ROUTE_PLD1IN2, 0x400f31ce +.set CYREG_UDB_P0_ROUTE_DPIN0, 0x400f31d0 +.set CYREG_UDB_P0_ROUTE_DPIN1, 0x400f31d2 +.set CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE, 0x00000002 +.set CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET, 0x00000004 +.set CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE, 0x00000002 +.set CYREG_UDB_P0_ROUTE_SCIN, 0x400f31d6 +.set CYREG_UDB_P0_ROUTE_SCIOIN, 0x400f31d8 +.set CYREG_UDB_P0_ROUTE_RCIN, 0x400f31de +.set CYREG_UDB_P0_ROUTE_VS0, 0x400f31e0 +.set CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_VS_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_P_ROUTE_VS_BOT__SIZE, 0x00000004 +.set CYREG_UDB_P0_ROUTE_VS1, 0x400f31e2 +.set CYREG_UDB_P0_ROUTE_VS2, 0x400f31e4 +.set CYREG_UDB_P0_ROUTE_VS3, 0x400f31e6 +.set CYREG_UDB_P0_ROUTE_VS4, 0x400f31e8 +.set CYREG_UDB_P0_ROUTE_VS5, 0x400f31ea +.set CYREG_UDB_P0_ROUTE_VS6, 0x400f31ec +.set CYREG_UDB_P0_ROUTE_VS7, 0x400f31ee +.set CYDEV_UDB_P1_BASE, 0x400f3200 +.set CYDEV_UDB_P1_SIZE, 0x00000200 +.set CYDEV_UDB_P1_U0_BASE, 0x400f3200 +.set CYDEV_UDB_P1_U0_SIZE, 0x00000080 +.set CYREG_UDB_P1_U0_PLD_IT0, 0x400f3200 +.set CYREG_UDB_P1_U0_PLD_IT1, 0x400f3204 +.set CYREG_UDB_P1_U0_PLD_IT2, 0x400f3208 +.set CYREG_UDB_P1_U0_PLD_IT3, 0x400f320c +.set CYREG_UDB_P1_U0_PLD_IT4, 0x400f3210 +.set CYREG_UDB_P1_U0_PLD_IT5, 0x400f3214 +.set CYREG_UDB_P1_U0_PLD_IT6, 0x400f3218 +.set CYREG_UDB_P1_U0_PLD_IT7, 0x400f321c +.set CYREG_UDB_P1_U0_PLD_IT8, 0x400f3220 +.set CYREG_UDB_P1_U0_PLD_IT9, 0x400f3224 +.set CYREG_UDB_P1_U0_PLD_IT10, 0x400f3228 +.set CYREG_UDB_P1_U0_PLD_IT11, 0x400f322c +.set CYREG_UDB_P1_U0_PLD_ORT0, 0x400f3230 +.set CYREG_UDB_P1_U0_PLD_ORT1, 0x400f3232 +.set CYREG_UDB_P1_U0_PLD_ORT2, 0x400f3234 +.set CYREG_UDB_P1_U0_PLD_ORT3, 0x400f3236 +.set CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST, 0x400f3238 +.set CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB, 0x400f323a +.set CYREG_UDB_P1_U0_PLD_MC_SET_RESET, 0x400f323c +.set CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS, 0x400f323e +.set CYREG_UDB_P1_U0_CFG0, 0x400f3240 +.set CYREG_UDB_P1_U0_CFG1, 0x400f3241 +.set CYREG_UDB_P1_U0_CFG2, 0x400f3242 +.set CYREG_UDB_P1_U0_CFG3, 0x400f3243 +.set CYREG_UDB_P1_U0_CFG4, 0x400f3244 +.set CYREG_UDB_P1_U0_CFG5, 0x400f3245 +.set CYREG_UDB_P1_U0_CFG6, 0x400f3246 +.set CYREG_UDB_P1_U0_CFG7, 0x400f3247 +.set CYREG_UDB_P1_U0_CFG8, 0x400f3248 +.set CYREG_UDB_P1_U0_CFG9, 0x400f3249 +.set CYREG_UDB_P1_U0_CFG10, 0x400f324a +.set CYREG_UDB_P1_U0_CFG11, 0x400f324b +.set CYREG_UDB_P1_U0_CFG12, 0x400f324c +.set CYREG_UDB_P1_U0_CFG13, 0x400f324d +.set CYREG_UDB_P1_U0_CFG14, 0x400f324e +.set CYREG_UDB_P1_U0_CFG15, 0x400f324f +.set CYREG_UDB_P1_U0_CFG16, 0x400f3250 +.set CYREG_UDB_P1_U0_CFG17, 0x400f3251 +.set CYREG_UDB_P1_U0_CFG18, 0x400f3252 +.set CYREG_UDB_P1_U0_CFG19, 0x400f3253 +.set CYREG_UDB_P1_U0_CFG20, 0x400f3254 +.set CYREG_UDB_P1_U0_CFG21, 0x400f3255 +.set CYREG_UDB_P1_U0_CFG22, 0x400f3256 +.set CYREG_UDB_P1_U0_CFG23, 0x400f3257 +.set CYREG_UDB_P1_U0_CFG24, 0x400f3258 +.set CYREG_UDB_P1_U0_CFG25, 0x400f3259 +.set CYREG_UDB_P1_U0_CFG26, 0x400f325a +.set CYREG_UDB_P1_U0_CFG27, 0x400f325b +.set CYREG_UDB_P1_U0_CFG28, 0x400f325c +.set CYREG_UDB_P1_U0_CFG29, 0x400f325d +.set CYREG_UDB_P1_U0_CFG30, 0x400f325e +.set CYREG_UDB_P1_U0_CFG31, 0x400f325f +.set CYREG_UDB_P1_U0_DCFG0, 0x400f3260 +.set CYREG_UDB_P1_U0_DCFG1, 0x400f3262 +.set CYREG_UDB_P1_U0_DCFG2, 0x400f3264 +.set CYREG_UDB_P1_U0_DCFG3, 0x400f3266 +.set CYREG_UDB_P1_U0_DCFG4, 0x400f3268 +.set CYREG_UDB_P1_U0_DCFG5, 0x400f326a +.set CYREG_UDB_P1_U0_DCFG6, 0x400f326c +.set CYREG_UDB_P1_U0_DCFG7, 0x400f326e +.set CYDEV_UDB_P1_U1_BASE, 0x400f3280 +.set CYDEV_UDB_P1_U1_SIZE, 0x00000080 +.set CYREG_UDB_P1_U1_PLD_IT0, 0x400f3280 +.set CYREG_UDB_P1_U1_PLD_IT1, 0x400f3284 +.set CYREG_UDB_P1_U1_PLD_IT2, 0x400f3288 +.set CYREG_UDB_P1_U1_PLD_IT3, 0x400f328c +.set CYREG_UDB_P1_U1_PLD_IT4, 0x400f3290 +.set CYREG_UDB_P1_U1_PLD_IT5, 0x400f3294 +.set CYREG_UDB_P1_U1_PLD_IT6, 0x400f3298 +.set CYREG_UDB_P1_U1_PLD_IT7, 0x400f329c +.set CYREG_UDB_P1_U1_PLD_IT8, 0x400f32a0 +.set CYREG_UDB_P1_U1_PLD_IT9, 0x400f32a4 +.set CYREG_UDB_P1_U1_PLD_IT10, 0x400f32a8 +.set CYREG_UDB_P1_U1_PLD_IT11, 0x400f32ac +.set CYREG_UDB_P1_U1_PLD_ORT0, 0x400f32b0 +.set CYREG_UDB_P1_U1_PLD_ORT1, 0x400f32b2 +.set CYREG_UDB_P1_U1_PLD_ORT2, 0x400f32b4 +.set CYREG_UDB_P1_U1_PLD_ORT3, 0x400f32b6 +.set CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST, 0x400f32b8 +.set CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB, 0x400f32ba +.set CYREG_UDB_P1_U1_PLD_MC_SET_RESET, 0x400f32bc +.set CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS, 0x400f32be +.set CYREG_UDB_P1_U1_CFG0, 0x400f32c0 +.set CYREG_UDB_P1_U1_CFG1, 0x400f32c1 +.set CYREG_UDB_P1_U1_CFG2, 0x400f32c2 +.set CYREG_UDB_P1_U1_CFG3, 0x400f32c3 +.set CYREG_UDB_P1_U1_CFG4, 0x400f32c4 +.set CYREG_UDB_P1_U1_CFG5, 0x400f32c5 +.set CYREG_UDB_P1_U1_CFG6, 0x400f32c6 +.set CYREG_UDB_P1_U1_CFG7, 0x400f32c7 +.set CYREG_UDB_P1_U1_CFG8, 0x400f32c8 +.set CYREG_UDB_P1_U1_CFG9, 0x400f32c9 +.set CYREG_UDB_P1_U1_CFG10, 0x400f32ca +.set CYREG_UDB_P1_U1_CFG11, 0x400f32cb +.set CYREG_UDB_P1_U1_CFG12, 0x400f32cc +.set CYREG_UDB_P1_U1_CFG13, 0x400f32cd +.set CYREG_UDB_P1_U1_CFG14, 0x400f32ce +.set CYREG_UDB_P1_U1_CFG15, 0x400f32cf +.set CYREG_UDB_P1_U1_CFG16, 0x400f32d0 +.set CYREG_UDB_P1_U1_CFG17, 0x400f32d1 +.set CYREG_UDB_P1_U1_CFG18, 0x400f32d2 +.set CYREG_UDB_P1_U1_CFG19, 0x400f32d3 +.set CYREG_UDB_P1_U1_CFG20, 0x400f32d4 +.set CYREG_UDB_P1_U1_CFG21, 0x400f32d5 +.set CYREG_UDB_P1_U1_CFG22, 0x400f32d6 +.set CYREG_UDB_P1_U1_CFG23, 0x400f32d7 +.set CYREG_UDB_P1_U1_CFG24, 0x400f32d8 +.set CYREG_UDB_P1_U1_CFG25, 0x400f32d9 +.set CYREG_UDB_P1_U1_CFG26, 0x400f32da +.set CYREG_UDB_P1_U1_CFG27, 0x400f32db +.set CYREG_UDB_P1_U1_CFG28, 0x400f32dc +.set CYREG_UDB_P1_U1_CFG29, 0x400f32dd +.set CYREG_UDB_P1_U1_CFG30, 0x400f32de +.set CYREG_UDB_P1_U1_CFG31, 0x400f32df +.set CYREG_UDB_P1_U1_DCFG0, 0x400f32e0 +.set CYREG_UDB_P1_U1_DCFG1, 0x400f32e2 +.set CYREG_UDB_P1_U1_DCFG2, 0x400f32e4 +.set CYREG_UDB_P1_U1_DCFG3, 0x400f32e6 +.set CYREG_UDB_P1_U1_DCFG4, 0x400f32e8 +.set CYREG_UDB_P1_U1_DCFG5, 0x400f32ea +.set CYREG_UDB_P1_U1_DCFG6, 0x400f32ec +.set CYREG_UDB_P1_U1_DCFG7, 0x400f32ee +.set CYDEV_UDB_P1_ROUTE_BASE, 0x400f3300 +.set CYDEV_UDB_P1_ROUTE_SIZE, 0x00000100 +.set CYREG_UDB_P1_ROUTE_HC0, 0x400f3300 +.set CYREG_UDB_P1_ROUTE_HC1, 0x400f3301 +.set CYREG_UDB_P1_ROUTE_HC2, 0x400f3302 +.set CYREG_UDB_P1_ROUTE_HC3, 0x400f3303 +.set CYREG_UDB_P1_ROUTE_HC4, 0x400f3304 +.set CYREG_UDB_P1_ROUTE_HC5, 0x400f3305 +.set CYREG_UDB_P1_ROUTE_HC6, 0x400f3306 +.set CYREG_UDB_P1_ROUTE_HC7, 0x400f3307 +.set CYREG_UDB_P1_ROUTE_HC8, 0x400f3308 +.set CYREG_UDB_P1_ROUTE_HC9, 0x400f3309 +.set CYREG_UDB_P1_ROUTE_HC10, 0x400f330a +.set CYREG_UDB_P1_ROUTE_HC11, 0x400f330b +.set CYREG_UDB_P1_ROUTE_HC12, 0x400f330c +.set CYREG_UDB_P1_ROUTE_HC13, 0x400f330d +.set CYREG_UDB_P1_ROUTE_HC14, 0x400f330e +.set CYREG_UDB_P1_ROUTE_HC15, 0x400f330f +.set CYREG_UDB_P1_ROUTE_HC16, 0x400f3310 +.set CYREG_UDB_P1_ROUTE_HC17, 0x400f3311 +.set CYREG_UDB_P1_ROUTE_HC18, 0x400f3312 +.set CYREG_UDB_P1_ROUTE_HC19, 0x400f3313 +.set CYREG_UDB_P1_ROUTE_HC20, 0x400f3314 +.set CYREG_UDB_P1_ROUTE_HC21, 0x400f3315 +.set CYREG_UDB_P1_ROUTE_HC22, 0x400f3316 +.set CYREG_UDB_P1_ROUTE_HC23, 0x400f3317 +.set CYREG_UDB_P1_ROUTE_HC24, 0x400f3318 +.set CYREG_UDB_P1_ROUTE_HC25, 0x400f3319 +.set CYREG_UDB_P1_ROUTE_HC26, 0x400f331a +.set CYREG_UDB_P1_ROUTE_HC27, 0x400f331b +.set CYREG_UDB_P1_ROUTE_HC28, 0x400f331c +.set CYREG_UDB_P1_ROUTE_HC29, 0x400f331d +.set CYREG_UDB_P1_ROUTE_HC30, 0x400f331e +.set CYREG_UDB_P1_ROUTE_HC31, 0x400f331f +.set CYREG_UDB_P1_ROUTE_HC32, 0x400f3320 +.set CYREG_UDB_P1_ROUTE_HC33, 0x400f3321 +.set CYREG_UDB_P1_ROUTE_HC34, 0x400f3322 +.set CYREG_UDB_P1_ROUTE_HC35, 0x400f3323 +.set CYREG_UDB_P1_ROUTE_HC36, 0x400f3324 +.set CYREG_UDB_P1_ROUTE_HC37, 0x400f3325 +.set CYREG_UDB_P1_ROUTE_HC38, 0x400f3326 +.set CYREG_UDB_P1_ROUTE_HC39, 0x400f3327 +.set CYREG_UDB_P1_ROUTE_HC40, 0x400f3328 +.set CYREG_UDB_P1_ROUTE_HC41, 0x400f3329 +.set CYREG_UDB_P1_ROUTE_HC42, 0x400f332a +.set CYREG_UDB_P1_ROUTE_HC43, 0x400f332b +.set CYREG_UDB_P1_ROUTE_HC44, 0x400f332c +.set CYREG_UDB_P1_ROUTE_HC45, 0x400f332d +.set CYREG_UDB_P1_ROUTE_HC46, 0x400f332e +.set CYREG_UDB_P1_ROUTE_HC47, 0x400f332f +.set CYREG_UDB_P1_ROUTE_HC48, 0x400f3330 +.set CYREG_UDB_P1_ROUTE_HC49, 0x400f3331 +.set CYREG_UDB_P1_ROUTE_HC50, 0x400f3332 +.set CYREG_UDB_P1_ROUTE_HC51, 0x400f3333 +.set CYREG_UDB_P1_ROUTE_HC52, 0x400f3334 +.set CYREG_UDB_P1_ROUTE_HC53, 0x400f3335 +.set CYREG_UDB_P1_ROUTE_HC54, 0x400f3336 +.set CYREG_UDB_P1_ROUTE_HC55, 0x400f3337 +.set CYREG_UDB_P1_ROUTE_HC56, 0x400f3338 +.set CYREG_UDB_P1_ROUTE_HC57, 0x400f3339 +.set CYREG_UDB_P1_ROUTE_HC58, 0x400f333a +.set CYREG_UDB_P1_ROUTE_HC59, 0x400f333b +.set CYREG_UDB_P1_ROUTE_HC60, 0x400f333c +.set CYREG_UDB_P1_ROUTE_HC61, 0x400f333d +.set CYREG_UDB_P1_ROUTE_HC62, 0x400f333e +.set CYREG_UDB_P1_ROUTE_HC63, 0x400f333f +.set CYREG_UDB_P1_ROUTE_HC64, 0x400f3340 +.set CYREG_UDB_P1_ROUTE_HC65, 0x400f3341 +.set CYREG_UDB_P1_ROUTE_HC66, 0x400f3342 +.set CYREG_UDB_P1_ROUTE_HC67, 0x400f3343 +.set CYREG_UDB_P1_ROUTE_HC68, 0x400f3344 +.set CYREG_UDB_P1_ROUTE_HC69, 0x400f3345 +.set CYREG_UDB_P1_ROUTE_HC70, 0x400f3346 +.set CYREG_UDB_P1_ROUTE_HC71, 0x400f3347 +.set CYREG_UDB_P1_ROUTE_HC72, 0x400f3348 +.set CYREG_UDB_P1_ROUTE_HC73, 0x400f3349 +.set CYREG_UDB_P1_ROUTE_HC74, 0x400f334a +.set CYREG_UDB_P1_ROUTE_HC75, 0x400f334b +.set CYREG_UDB_P1_ROUTE_HC76, 0x400f334c +.set CYREG_UDB_P1_ROUTE_HC77, 0x400f334d +.set CYREG_UDB_P1_ROUTE_HC78, 0x400f334e +.set CYREG_UDB_P1_ROUTE_HC79, 0x400f334f +.set CYREG_UDB_P1_ROUTE_HC80, 0x400f3350 +.set CYREG_UDB_P1_ROUTE_HC81, 0x400f3351 +.set CYREG_UDB_P1_ROUTE_HC82, 0x400f3352 +.set CYREG_UDB_P1_ROUTE_HC83, 0x400f3353 +.set CYREG_UDB_P1_ROUTE_HC84, 0x400f3354 +.set CYREG_UDB_P1_ROUTE_HC85, 0x400f3355 +.set CYREG_UDB_P1_ROUTE_HC86, 0x400f3356 +.set CYREG_UDB_P1_ROUTE_HC87, 0x400f3357 +.set CYREG_UDB_P1_ROUTE_HC88, 0x400f3358 +.set CYREG_UDB_P1_ROUTE_HC89, 0x400f3359 +.set CYREG_UDB_P1_ROUTE_HC90, 0x400f335a +.set CYREG_UDB_P1_ROUTE_HC91, 0x400f335b +.set CYREG_UDB_P1_ROUTE_HC92, 0x400f335c +.set CYREG_UDB_P1_ROUTE_HC93, 0x400f335d +.set CYREG_UDB_P1_ROUTE_HC94, 0x400f335e +.set CYREG_UDB_P1_ROUTE_HC95, 0x400f335f +.set CYREG_UDB_P1_ROUTE_HC96, 0x400f3360 +.set CYREG_UDB_P1_ROUTE_HC97, 0x400f3361 +.set CYREG_UDB_P1_ROUTE_HC98, 0x400f3362 +.set CYREG_UDB_P1_ROUTE_HC99, 0x400f3363 +.set CYREG_UDB_P1_ROUTE_HC100, 0x400f3364 +.set CYREG_UDB_P1_ROUTE_HC101, 0x400f3365 +.set CYREG_UDB_P1_ROUTE_HC102, 0x400f3366 +.set CYREG_UDB_P1_ROUTE_HC103, 0x400f3367 +.set CYREG_UDB_P1_ROUTE_HC104, 0x400f3368 +.set CYREG_UDB_P1_ROUTE_HC105, 0x400f3369 +.set CYREG_UDB_P1_ROUTE_HC106, 0x400f336a +.set CYREG_UDB_P1_ROUTE_HC107, 0x400f336b +.set CYREG_UDB_P1_ROUTE_HC108, 0x400f336c +.set CYREG_UDB_P1_ROUTE_HC109, 0x400f336d +.set CYREG_UDB_P1_ROUTE_HC110, 0x400f336e +.set CYREG_UDB_P1_ROUTE_HC111, 0x400f336f +.set CYREG_UDB_P1_ROUTE_HC112, 0x400f3370 +.set CYREG_UDB_P1_ROUTE_HC113, 0x400f3371 +.set CYREG_UDB_P1_ROUTE_HC114, 0x400f3372 +.set CYREG_UDB_P1_ROUTE_HC115, 0x400f3373 +.set CYREG_UDB_P1_ROUTE_HC116, 0x400f3374 +.set CYREG_UDB_P1_ROUTE_HC117, 0x400f3375 +.set CYREG_UDB_P1_ROUTE_HC118, 0x400f3376 +.set CYREG_UDB_P1_ROUTE_HC119, 0x400f3377 +.set CYREG_UDB_P1_ROUTE_HC120, 0x400f3378 +.set CYREG_UDB_P1_ROUTE_HC121, 0x400f3379 +.set CYREG_UDB_P1_ROUTE_HC122, 0x400f337a +.set CYREG_UDB_P1_ROUTE_HC123, 0x400f337b +.set CYREG_UDB_P1_ROUTE_HC124, 0x400f337c +.set CYREG_UDB_P1_ROUTE_HC125, 0x400f337d +.set CYREG_UDB_P1_ROUTE_HC126, 0x400f337e +.set CYREG_UDB_P1_ROUTE_HC127, 0x400f337f +.set CYREG_UDB_P1_ROUTE_HV_L0, 0x400f3380 +.set CYREG_UDB_P1_ROUTE_HV_L1, 0x400f3381 +.set CYREG_UDB_P1_ROUTE_HV_L2, 0x400f3382 +.set CYREG_UDB_P1_ROUTE_HV_L3, 0x400f3383 +.set CYREG_UDB_P1_ROUTE_HV_L4, 0x400f3384 +.set CYREG_UDB_P1_ROUTE_HV_L5, 0x400f3385 +.set CYREG_UDB_P1_ROUTE_HV_L6, 0x400f3386 +.set CYREG_UDB_P1_ROUTE_HV_L7, 0x400f3387 +.set CYREG_UDB_P1_ROUTE_HV_L8, 0x400f3388 +.set CYREG_UDB_P1_ROUTE_HV_L9, 0x400f3389 +.set CYREG_UDB_P1_ROUTE_HV_L10, 0x400f338a +.set CYREG_UDB_P1_ROUTE_HV_L11, 0x400f338b +.set CYREG_UDB_P1_ROUTE_HV_L12, 0x400f338c +.set CYREG_UDB_P1_ROUTE_HV_L13, 0x400f338d +.set CYREG_UDB_P1_ROUTE_HV_L14, 0x400f338e +.set CYREG_UDB_P1_ROUTE_HV_L15, 0x400f338f +.set CYREG_UDB_P1_ROUTE_HS0, 0x400f3390 +.set CYREG_UDB_P1_ROUTE_HS1, 0x400f3391 +.set CYREG_UDB_P1_ROUTE_HS2, 0x400f3392 +.set CYREG_UDB_P1_ROUTE_HS3, 0x400f3393 +.set CYREG_UDB_P1_ROUTE_HS4, 0x400f3394 +.set CYREG_UDB_P1_ROUTE_HS5, 0x400f3395 +.set CYREG_UDB_P1_ROUTE_HS6, 0x400f3396 +.set CYREG_UDB_P1_ROUTE_HS7, 0x400f3397 +.set CYREG_UDB_P1_ROUTE_HS8, 0x400f3398 +.set CYREG_UDB_P1_ROUTE_HS9, 0x400f3399 +.set CYREG_UDB_P1_ROUTE_HS10, 0x400f339a +.set CYREG_UDB_P1_ROUTE_HS11, 0x400f339b +.set CYREG_UDB_P1_ROUTE_HS12, 0x400f339c +.set CYREG_UDB_P1_ROUTE_HS13, 0x400f339d +.set CYREG_UDB_P1_ROUTE_HS14, 0x400f339e +.set CYREG_UDB_P1_ROUTE_HS15, 0x400f339f +.set CYREG_UDB_P1_ROUTE_HS16, 0x400f33a0 +.set CYREG_UDB_P1_ROUTE_HS17, 0x400f33a1 +.set CYREG_UDB_P1_ROUTE_HS18, 0x400f33a2 +.set CYREG_UDB_P1_ROUTE_HS19, 0x400f33a3 +.set CYREG_UDB_P1_ROUTE_HS20, 0x400f33a4 +.set CYREG_UDB_P1_ROUTE_HS21, 0x400f33a5 +.set CYREG_UDB_P1_ROUTE_HS22, 0x400f33a6 +.set CYREG_UDB_P1_ROUTE_HS23, 0x400f33a7 +.set CYREG_UDB_P1_ROUTE_HV_R0, 0x400f33a8 +.set CYREG_UDB_P1_ROUTE_HV_R1, 0x400f33a9 +.set CYREG_UDB_P1_ROUTE_HV_R2, 0x400f33aa +.set CYREG_UDB_P1_ROUTE_HV_R3, 0x400f33ab +.set CYREG_UDB_P1_ROUTE_HV_R4, 0x400f33ac +.set CYREG_UDB_P1_ROUTE_HV_R5, 0x400f33ad +.set CYREG_UDB_P1_ROUTE_HV_R6, 0x400f33ae +.set CYREG_UDB_P1_ROUTE_HV_R7, 0x400f33af +.set CYREG_UDB_P1_ROUTE_HV_R8, 0x400f33b0 +.set CYREG_UDB_P1_ROUTE_HV_R9, 0x400f33b1 +.set CYREG_UDB_P1_ROUTE_HV_R10, 0x400f33b2 +.set CYREG_UDB_P1_ROUTE_HV_R11, 0x400f33b3 +.set CYREG_UDB_P1_ROUTE_HV_R12, 0x400f33b4 +.set CYREG_UDB_P1_ROUTE_HV_R13, 0x400f33b5 +.set CYREG_UDB_P1_ROUTE_HV_R14, 0x400f33b6 +.set CYREG_UDB_P1_ROUTE_HV_R15, 0x400f33b7 +.set CYREG_UDB_P1_ROUTE_PLD0IN0, 0x400f33c0 +.set CYREG_UDB_P1_ROUTE_PLD0IN1, 0x400f33c2 +.set CYREG_UDB_P1_ROUTE_PLD0IN2, 0x400f33c4 +.set CYREG_UDB_P1_ROUTE_PLD1IN0, 0x400f33ca +.set CYREG_UDB_P1_ROUTE_PLD1IN1, 0x400f33cc +.set CYREG_UDB_P1_ROUTE_PLD1IN2, 0x400f33ce +.set CYREG_UDB_P1_ROUTE_DPIN0, 0x400f33d0 +.set CYREG_UDB_P1_ROUTE_DPIN1, 0x400f33d2 +.set CYREG_UDB_P1_ROUTE_SCIN, 0x400f33d6 +.set CYREG_UDB_P1_ROUTE_SCIOIN, 0x400f33d8 +.set CYREG_UDB_P1_ROUTE_RCIN, 0x400f33de +.set CYREG_UDB_P1_ROUTE_VS0, 0x400f33e0 +.set CYREG_UDB_P1_ROUTE_VS1, 0x400f33e2 +.set CYREG_UDB_P1_ROUTE_VS2, 0x400f33e4 +.set CYREG_UDB_P1_ROUTE_VS3, 0x400f33e6 +.set CYREG_UDB_P1_ROUTE_VS4, 0x400f33e8 +.set CYREG_UDB_P1_ROUTE_VS5, 0x400f33ea +.set CYREG_UDB_P1_ROUTE_VS6, 0x400f33ec +.set CYREG_UDB_P1_ROUTE_VS7, 0x400f33ee +.set CYDEV_UDB_DSI0_BASE, 0x400f4000 +.set CYDEV_UDB_DSI0_SIZE, 0x00000100 +.set CYREG_UDB_DSI0_HC0, 0x400f4000 +.set CYFLD_UDB_DSI_HC_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_HC_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_DSI0_HC1, 0x400f4001 +.set CYREG_UDB_DSI0_HC2, 0x400f4002 +.set CYREG_UDB_DSI0_HC3, 0x400f4003 +.set CYREG_UDB_DSI0_HC4, 0x400f4004 +.set CYREG_UDB_DSI0_HC5, 0x400f4005 +.set CYREG_UDB_DSI0_HC6, 0x400f4006 +.set CYREG_UDB_DSI0_HC7, 0x400f4007 +.set CYREG_UDB_DSI0_HC8, 0x400f4008 +.set CYREG_UDB_DSI0_HC9, 0x400f4009 +.set CYREG_UDB_DSI0_HC10, 0x400f400a +.set CYREG_UDB_DSI0_HC11, 0x400f400b +.set CYREG_UDB_DSI0_HC12, 0x400f400c +.set CYREG_UDB_DSI0_HC13, 0x400f400d +.set CYREG_UDB_DSI0_HC14, 0x400f400e +.set CYREG_UDB_DSI0_HC15, 0x400f400f +.set CYREG_UDB_DSI0_HC16, 0x400f4010 +.set CYREG_UDB_DSI0_HC17, 0x400f4011 +.set CYREG_UDB_DSI0_HC18, 0x400f4012 +.set CYREG_UDB_DSI0_HC19, 0x400f4013 +.set CYREG_UDB_DSI0_HC20, 0x400f4014 +.set CYREG_UDB_DSI0_HC21, 0x400f4015 +.set CYREG_UDB_DSI0_HC22, 0x400f4016 +.set CYREG_UDB_DSI0_HC23, 0x400f4017 +.set CYREG_UDB_DSI0_HC24, 0x400f4018 +.set CYREG_UDB_DSI0_HC25, 0x400f4019 +.set CYREG_UDB_DSI0_HC26, 0x400f401a +.set CYREG_UDB_DSI0_HC27, 0x400f401b +.set CYREG_UDB_DSI0_HC28, 0x400f401c +.set CYREG_UDB_DSI0_HC29, 0x400f401d +.set CYREG_UDB_DSI0_HC30, 0x400f401e +.set CYREG_UDB_DSI0_HC31, 0x400f401f +.set CYREG_UDB_DSI0_HC32, 0x400f4020 +.set CYREG_UDB_DSI0_HC33, 0x400f4021 +.set CYREG_UDB_DSI0_HC34, 0x400f4022 +.set CYREG_UDB_DSI0_HC35, 0x400f4023 +.set CYREG_UDB_DSI0_HC36, 0x400f4024 +.set CYREG_UDB_DSI0_HC37, 0x400f4025 +.set CYREG_UDB_DSI0_HC38, 0x400f4026 +.set CYREG_UDB_DSI0_HC39, 0x400f4027 +.set CYREG_UDB_DSI0_HC40, 0x400f4028 +.set CYREG_UDB_DSI0_HC41, 0x400f4029 +.set CYREG_UDB_DSI0_HC42, 0x400f402a +.set CYREG_UDB_DSI0_HC43, 0x400f402b +.set CYREG_UDB_DSI0_HC44, 0x400f402c +.set CYREG_UDB_DSI0_HC45, 0x400f402d +.set CYREG_UDB_DSI0_HC46, 0x400f402e +.set CYREG_UDB_DSI0_HC47, 0x400f402f +.set CYREG_UDB_DSI0_HC48, 0x400f4030 +.set CYREG_UDB_DSI0_HC49, 0x400f4031 +.set CYREG_UDB_DSI0_HC50, 0x400f4032 +.set CYREG_UDB_DSI0_HC51, 0x400f4033 +.set CYREG_UDB_DSI0_HC52, 0x400f4034 +.set CYREG_UDB_DSI0_HC53, 0x400f4035 +.set CYREG_UDB_DSI0_HC54, 0x400f4036 +.set CYREG_UDB_DSI0_HC55, 0x400f4037 +.set CYREG_UDB_DSI0_HC56, 0x400f4038 +.set CYREG_UDB_DSI0_HC57, 0x400f4039 +.set CYREG_UDB_DSI0_HC58, 0x400f403a +.set CYREG_UDB_DSI0_HC59, 0x400f403b +.set CYREG_UDB_DSI0_HC60, 0x400f403c +.set CYREG_UDB_DSI0_HC61, 0x400f403d +.set CYREG_UDB_DSI0_HC62, 0x400f403e +.set CYREG_UDB_DSI0_HC63, 0x400f403f +.set CYREG_UDB_DSI0_HC64, 0x400f4040 +.set CYREG_UDB_DSI0_HC65, 0x400f4041 +.set CYREG_UDB_DSI0_HC66, 0x400f4042 +.set CYREG_UDB_DSI0_HC67, 0x400f4043 +.set CYREG_UDB_DSI0_HC68, 0x400f4044 +.set CYREG_UDB_DSI0_HC69, 0x400f4045 +.set CYREG_UDB_DSI0_HC70, 0x400f4046 +.set CYREG_UDB_DSI0_HC71, 0x400f4047 +.set CYREG_UDB_DSI0_HC72, 0x400f4048 +.set CYREG_UDB_DSI0_HC73, 0x400f4049 +.set CYREG_UDB_DSI0_HC74, 0x400f404a +.set CYREG_UDB_DSI0_HC75, 0x400f404b +.set CYREG_UDB_DSI0_HC76, 0x400f404c +.set CYREG_UDB_DSI0_HC77, 0x400f404d +.set CYREG_UDB_DSI0_HC78, 0x400f404e +.set CYREG_UDB_DSI0_HC79, 0x400f404f +.set CYREG_UDB_DSI0_HC80, 0x400f4050 +.set CYREG_UDB_DSI0_HC81, 0x400f4051 +.set CYREG_UDB_DSI0_HC82, 0x400f4052 +.set CYREG_UDB_DSI0_HC83, 0x400f4053 +.set CYREG_UDB_DSI0_HC84, 0x400f4054 +.set CYREG_UDB_DSI0_HC85, 0x400f4055 +.set CYREG_UDB_DSI0_HC86, 0x400f4056 +.set CYREG_UDB_DSI0_HC87, 0x400f4057 +.set CYREG_UDB_DSI0_HC88, 0x400f4058 +.set CYREG_UDB_DSI0_HC89, 0x400f4059 +.set CYREG_UDB_DSI0_HC90, 0x400f405a +.set CYREG_UDB_DSI0_HC91, 0x400f405b +.set CYREG_UDB_DSI0_HC92, 0x400f405c +.set CYREG_UDB_DSI0_HC93, 0x400f405d +.set CYREG_UDB_DSI0_HC94, 0x400f405e +.set CYREG_UDB_DSI0_HC95, 0x400f405f +.set CYREG_UDB_DSI0_HC96, 0x400f4060 +.set CYREG_UDB_DSI0_HC97, 0x400f4061 +.set CYREG_UDB_DSI0_HC98, 0x400f4062 +.set CYREG_UDB_DSI0_HC99, 0x400f4063 +.set CYREG_UDB_DSI0_HC100, 0x400f4064 +.set CYREG_UDB_DSI0_HC101, 0x400f4065 +.set CYREG_UDB_DSI0_HC102, 0x400f4066 +.set CYREG_UDB_DSI0_HC103, 0x400f4067 +.set CYREG_UDB_DSI0_HC104, 0x400f4068 +.set CYREG_UDB_DSI0_HC105, 0x400f4069 +.set CYREG_UDB_DSI0_HC106, 0x400f406a +.set CYREG_UDB_DSI0_HC107, 0x400f406b +.set CYREG_UDB_DSI0_HC108, 0x400f406c +.set CYREG_UDB_DSI0_HC109, 0x400f406d +.set CYREG_UDB_DSI0_HC110, 0x400f406e +.set CYREG_UDB_DSI0_HC111, 0x400f406f +.set CYREG_UDB_DSI0_HC112, 0x400f4070 +.set CYREG_UDB_DSI0_HC113, 0x400f4071 +.set CYREG_UDB_DSI0_HC114, 0x400f4072 +.set CYREG_UDB_DSI0_HC115, 0x400f4073 +.set CYREG_UDB_DSI0_HC116, 0x400f4074 +.set CYREG_UDB_DSI0_HC117, 0x400f4075 +.set CYREG_UDB_DSI0_HC118, 0x400f4076 +.set CYREG_UDB_DSI0_HC119, 0x400f4077 +.set CYREG_UDB_DSI0_HC120, 0x400f4078 +.set CYREG_UDB_DSI0_HC121, 0x400f4079 +.set CYREG_UDB_DSI0_HC122, 0x400f407a +.set CYREG_UDB_DSI0_HC123, 0x400f407b +.set CYREG_UDB_DSI0_HC124, 0x400f407c +.set CYREG_UDB_DSI0_HC125, 0x400f407d +.set CYREG_UDB_DSI0_HC126, 0x400f407e +.set CYREG_UDB_DSI0_HC127, 0x400f407f +.set CYREG_UDB_DSI0_HV_L0, 0x400f4080 +.set CYFLD_UDB_DSI_HV_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_HV_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_DSI0_HV_L1, 0x400f4081 +.set CYREG_UDB_DSI0_HV_L2, 0x400f4082 +.set CYREG_UDB_DSI0_HV_L3, 0x400f4083 +.set CYREG_UDB_DSI0_HV_L4, 0x400f4084 +.set CYREG_UDB_DSI0_HV_L5, 0x400f4085 +.set CYREG_UDB_DSI0_HV_L6, 0x400f4086 +.set CYREG_UDB_DSI0_HV_L7, 0x400f4087 +.set CYREG_UDB_DSI0_HV_L8, 0x400f4088 +.set CYREG_UDB_DSI0_HV_L9, 0x400f4089 +.set CYREG_UDB_DSI0_HV_L10, 0x400f408a +.set CYREG_UDB_DSI0_HV_L11, 0x400f408b +.set CYREG_UDB_DSI0_HV_L12, 0x400f408c +.set CYREG_UDB_DSI0_HV_L13, 0x400f408d +.set CYREG_UDB_DSI0_HV_L14, 0x400f408e +.set CYREG_UDB_DSI0_HV_L15, 0x400f408f +.set CYREG_UDB_DSI0_HS0, 0x400f4090 +.set CYFLD_UDB_DSI_HS_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_HS_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_DSI0_HS1, 0x400f4091 +.set CYREG_UDB_DSI0_HS2, 0x400f4092 +.set CYREG_UDB_DSI0_HS3, 0x400f4093 +.set CYREG_UDB_DSI0_HS4, 0x400f4094 +.set CYREG_UDB_DSI0_HS5, 0x400f4095 +.set CYREG_UDB_DSI0_HS6, 0x400f4096 +.set CYREG_UDB_DSI0_HS7, 0x400f4097 +.set CYREG_UDB_DSI0_HS8, 0x400f4098 +.set CYREG_UDB_DSI0_HS9, 0x400f4099 +.set CYREG_UDB_DSI0_HS10, 0x400f409a +.set CYREG_UDB_DSI0_HS11, 0x400f409b +.set CYREG_UDB_DSI0_HS12, 0x400f409c +.set CYREG_UDB_DSI0_HS13, 0x400f409d +.set CYREG_UDB_DSI0_HS14, 0x400f409e +.set CYREG_UDB_DSI0_HS15, 0x400f409f +.set CYREG_UDB_DSI0_HS16, 0x400f40a0 +.set CYREG_UDB_DSI0_HS17, 0x400f40a1 +.set CYREG_UDB_DSI0_HS18, 0x400f40a2 +.set CYREG_UDB_DSI0_HS19, 0x400f40a3 +.set CYREG_UDB_DSI0_HS20, 0x400f40a4 +.set CYREG_UDB_DSI0_HS21, 0x400f40a5 +.set CYREG_UDB_DSI0_HS22, 0x400f40a6 +.set CYREG_UDB_DSI0_HS23, 0x400f40a7 +.set CYREG_UDB_DSI0_HV_R0, 0x400f40a8 +.set CYREG_UDB_DSI0_HV_R1, 0x400f40a9 +.set CYREG_UDB_DSI0_HV_R2, 0x400f40aa +.set CYREG_UDB_DSI0_HV_R3, 0x400f40ab +.set CYREG_UDB_DSI0_HV_R4, 0x400f40ac +.set CYREG_UDB_DSI0_HV_R5, 0x400f40ad +.set CYREG_UDB_DSI0_HV_R6, 0x400f40ae +.set CYREG_UDB_DSI0_HV_R7, 0x400f40af +.set CYREG_UDB_DSI0_HV_R8, 0x400f40b0 +.set CYREG_UDB_DSI0_HV_R9, 0x400f40b1 +.set CYREG_UDB_DSI0_HV_R10, 0x400f40b2 +.set CYREG_UDB_DSI0_HV_R11, 0x400f40b3 +.set CYREG_UDB_DSI0_HV_R12, 0x400f40b4 +.set CYREG_UDB_DSI0_HV_R13, 0x400f40b5 +.set CYREG_UDB_DSI0_HV_R14, 0x400f40b6 +.set CYREG_UDB_DSI0_HV_R15, 0x400f40b7 +.set CYREG_UDB_DSI0_DSIINP0, 0x400f40c0 +.set CYFLD_UDB_DSI_PI_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_PI_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_DSI_PI_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_DSI_PI_BOT__SIZE, 0x00000004 +.set CYREG_UDB_DSI0_DSIINP1, 0x400f40c2 +.set CYREG_UDB_DSI0_DSIINP2, 0x400f40c4 +.set CYREG_UDB_DSI0_DSIINP3, 0x400f40c6 +.set CYREG_UDB_DSI0_DSIINP4, 0x400f40c8 +.set CYREG_UDB_DSI0_DSIINP5, 0x400f40ca +.set CYREG_UDB_DSI0_DSIOUTP0, 0x400f40cc +.set CYREG_UDB_DSI0_DSIOUTP1, 0x400f40ce +.set CYREG_UDB_DSI0_DSIOUTP2, 0x400f40d0 +.set CYREG_UDB_DSI0_DSIOUTP3, 0x400f40d2 +.set CYREG_UDB_DSI0_DSIOUTT0, 0x400f40d4 +.set CYREG_UDB_DSI0_DSIOUTT1, 0x400f40d6 +.set CYREG_UDB_DSI0_DSIOUTT2, 0x400f40d8 +.set CYREG_UDB_DSI0_DSIOUTT3, 0x400f40da +.set CYREG_UDB_DSI0_DSIOUTT4, 0x400f40dc +.set CYREG_UDB_DSI0_DSIOUTT5, 0x400f40de +.set CYREG_UDB_DSI0_VS0, 0x400f40e0 +.set CYFLD_UDB_DSI_VS_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_VS_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_DSI_VS_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_DSI_VS_BOT__SIZE, 0x00000004 +.set CYREG_UDB_DSI0_VS1, 0x400f40e2 +.set CYREG_UDB_DSI0_VS2, 0x400f40e4 +.set CYREG_UDB_DSI0_VS3, 0x400f40e6 +.set CYREG_UDB_DSI0_VS4, 0x400f40e8 +.set CYREG_UDB_DSI0_VS5, 0x400f40ea +.set CYREG_UDB_DSI0_VS6, 0x400f40ec +.set CYREG_UDB_DSI0_VS7, 0x400f40ee +.set CYDEV_UDB_DSI1_BASE, 0x400f4100 +.set CYDEV_UDB_DSI1_SIZE, 0x00000100 +.set CYREG_UDB_DSI1_HC0, 0x400f4100 +.set CYREG_UDB_DSI1_HC1, 0x400f4101 +.set CYREG_UDB_DSI1_HC2, 0x400f4102 +.set CYREG_UDB_DSI1_HC3, 0x400f4103 +.set CYREG_UDB_DSI1_HC4, 0x400f4104 +.set CYREG_UDB_DSI1_HC5, 0x400f4105 +.set CYREG_UDB_DSI1_HC6, 0x400f4106 +.set CYREG_UDB_DSI1_HC7, 0x400f4107 +.set CYREG_UDB_DSI1_HC8, 0x400f4108 +.set CYREG_UDB_DSI1_HC9, 0x400f4109 +.set CYREG_UDB_DSI1_HC10, 0x400f410a +.set CYREG_UDB_DSI1_HC11, 0x400f410b +.set CYREG_UDB_DSI1_HC12, 0x400f410c +.set CYREG_UDB_DSI1_HC13, 0x400f410d +.set CYREG_UDB_DSI1_HC14, 0x400f410e +.set CYREG_UDB_DSI1_HC15, 0x400f410f +.set CYREG_UDB_DSI1_HC16, 0x400f4110 +.set CYREG_UDB_DSI1_HC17, 0x400f4111 +.set CYREG_UDB_DSI1_HC18, 0x400f4112 +.set CYREG_UDB_DSI1_HC19, 0x400f4113 +.set CYREG_UDB_DSI1_HC20, 0x400f4114 +.set CYREG_UDB_DSI1_HC21, 0x400f4115 +.set CYREG_UDB_DSI1_HC22, 0x400f4116 +.set CYREG_UDB_DSI1_HC23, 0x400f4117 +.set CYREG_UDB_DSI1_HC24, 0x400f4118 +.set CYREG_UDB_DSI1_HC25, 0x400f4119 +.set CYREG_UDB_DSI1_HC26, 0x400f411a +.set CYREG_UDB_DSI1_HC27, 0x400f411b +.set CYREG_UDB_DSI1_HC28, 0x400f411c +.set CYREG_UDB_DSI1_HC29, 0x400f411d +.set CYREG_UDB_DSI1_HC30, 0x400f411e +.set CYREG_UDB_DSI1_HC31, 0x400f411f +.set CYREG_UDB_DSI1_HC32, 0x400f4120 +.set CYREG_UDB_DSI1_HC33, 0x400f4121 +.set CYREG_UDB_DSI1_HC34, 0x400f4122 +.set CYREG_UDB_DSI1_HC35, 0x400f4123 +.set CYREG_UDB_DSI1_HC36, 0x400f4124 +.set CYREG_UDB_DSI1_HC37, 0x400f4125 +.set CYREG_UDB_DSI1_HC38, 0x400f4126 +.set CYREG_UDB_DSI1_HC39, 0x400f4127 +.set CYREG_UDB_DSI1_HC40, 0x400f4128 +.set CYREG_UDB_DSI1_HC41, 0x400f4129 +.set CYREG_UDB_DSI1_HC42, 0x400f412a +.set CYREG_UDB_DSI1_HC43, 0x400f412b +.set CYREG_UDB_DSI1_HC44, 0x400f412c +.set CYREG_UDB_DSI1_HC45, 0x400f412d +.set CYREG_UDB_DSI1_HC46, 0x400f412e +.set CYREG_UDB_DSI1_HC47, 0x400f412f +.set CYREG_UDB_DSI1_HC48, 0x400f4130 +.set CYREG_UDB_DSI1_HC49, 0x400f4131 +.set CYREG_UDB_DSI1_HC50, 0x400f4132 +.set CYREG_UDB_DSI1_HC51, 0x400f4133 +.set CYREG_UDB_DSI1_HC52, 0x400f4134 +.set CYREG_UDB_DSI1_HC53, 0x400f4135 +.set CYREG_UDB_DSI1_HC54, 0x400f4136 +.set CYREG_UDB_DSI1_HC55, 0x400f4137 +.set CYREG_UDB_DSI1_HC56, 0x400f4138 +.set CYREG_UDB_DSI1_HC57, 0x400f4139 +.set CYREG_UDB_DSI1_HC58, 0x400f413a +.set CYREG_UDB_DSI1_HC59, 0x400f413b +.set CYREG_UDB_DSI1_HC60, 0x400f413c +.set CYREG_UDB_DSI1_HC61, 0x400f413d +.set CYREG_UDB_DSI1_HC62, 0x400f413e +.set CYREG_UDB_DSI1_HC63, 0x400f413f +.set CYREG_UDB_DSI1_HC64, 0x400f4140 +.set CYREG_UDB_DSI1_HC65, 0x400f4141 +.set CYREG_UDB_DSI1_HC66, 0x400f4142 +.set CYREG_UDB_DSI1_HC67, 0x400f4143 +.set CYREG_UDB_DSI1_HC68, 0x400f4144 +.set CYREG_UDB_DSI1_HC69, 0x400f4145 +.set CYREG_UDB_DSI1_HC70, 0x400f4146 +.set CYREG_UDB_DSI1_HC71, 0x400f4147 +.set CYREG_UDB_DSI1_HC72, 0x400f4148 +.set CYREG_UDB_DSI1_HC73, 0x400f4149 +.set CYREG_UDB_DSI1_HC74, 0x400f414a +.set CYREG_UDB_DSI1_HC75, 0x400f414b +.set CYREG_UDB_DSI1_HC76, 0x400f414c +.set CYREG_UDB_DSI1_HC77, 0x400f414d +.set CYREG_UDB_DSI1_HC78, 0x400f414e +.set CYREG_UDB_DSI1_HC79, 0x400f414f +.set CYREG_UDB_DSI1_HC80, 0x400f4150 +.set CYREG_UDB_DSI1_HC81, 0x400f4151 +.set CYREG_UDB_DSI1_HC82, 0x400f4152 +.set CYREG_UDB_DSI1_HC83, 0x400f4153 +.set CYREG_UDB_DSI1_HC84, 0x400f4154 +.set CYREG_UDB_DSI1_HC85, 0x400f4155 +.set CYREG_UDB_DSI1_HC86, 0x400f4156 +.set CYREG_UDB_DSI1_HC87, 0x400f4157 +.set CYREG_UDB_DSI1_HC88, 0x400f4158 +.set CYREG_UDB_DSI1_HC89, 0x400f4159 +.set CYREG_UDB_DSI1_HC90, 0x400f415a +.set CYREG_UDB_DSI1_HC91, 0x400f415b +.set CYREG_UDB_DSI1_HC92, 0x400f415c +.set CYREG_UDB_DSI1_HC93, 0x400f415d +.set CYREG_UDB_DSI1_HC94, 0x400f415e +.set CYREG_UDB_DSI1_HC95, 0x400f415f +.set CYREG_UDB_DSI1_HC96, 0x400f4160 +.set CYREG_UDB_DSI1_HC97, 0x400f4161 +.set CYREG_UDB_DSI1_HC98, 0x400f4162 +.set CYREG_UDB_DSI1_HC99, 0x400f4163 +.set CYREG_UDB_DSI1_HC100, 0x400f4164 +.set CYREG_UDB_DSI1_HC101, 0x400f4165 +.set CYREG_UDB_DSI1_HC102, 0x400f4166 +.set CYREG_UDB_DSI1_HC103, 0x400f4167 +.set CYREG_UDB_DSI1_HC104, 0x400f4168 +.set CYREG_UDB_DSI1_HC105, 0x400f4169 +.set CYREG_UDB_DSI1_HC106, 0x400f416a +.set CYREG_UDB_DSI1_HC107, 0x400f416b +.set CYREG_UDB_DSI1_HC108, 0x400f416c +.set CYREG_UDB_DSI1_HC109, 0x400f416d +.set CYREG_UDB_DSI1_HC110, 0x400f416e +.set CYREG_UDB_DSI1_HC111, 0x400f416f +.set CYREG_UDB_DSI1_HC112, 0x400f4170 +.set CYREG_UDB_DSI1_HC113, 0x400f4171 +.set CYREG_UDB_DSI1_HC114, 0x400f4172 +.set CYREG_UDB_DSI1_HC115, 0x400f4173 +.set CYREG_UDB_DSI1_HC116, 0x400f4174 +.set CYREG_UDB_DSI1_HC117, 0x400f4175 +.set CYREG_UDB_DSI1_HC118, 0x400f4176 +.set CYREG_UDB_DSI1_HC119, 0x400f4177 +.set CYREG_UDB_DSI1_HC120, 0x400f4178 +.set CYREG_UDB_DSI1_HC121, 0x400f4179 +.set CYREG_UDB_DSI1_HC122, 0x400f417a +.set CYREG_UDB_DSI1_HC123, 0x400f417b +.set CYREG_UDB_DSI1_HC124, 0x400f417c +.set CYREG_UDB_DSI1_HC125, 0x400f417d +.set CYREG_UDB_DSI1_HC126, 0x400f417e +.set CYREG_UDB_DSI1_HC127, 0x400f417f +.set CYREG_UDB_DSI1_HV_L0, 0x400f4180 +.set CYREG_UDB_DSI1_HV_L1, 0x400f4181 +.set CYREG_UDB_DSI1_HV_L2, 0x400f4182 +.set CYREG_UDB_DSI1_HV_L3, 0x400f4183 +.set CYREG_UDB_DSI1_HV_L4, 0x400f4184 +.set CYREG_UDB_DSI1_HV_L5, 0x400f4185 +.set CYREG_UDB_DSI1_HV_L6, 0x400f4186 +.set CYREG_UDB_DSI1_HV_L7, 0x400f4187 +.set CYREG_UDB_DSI1_HV_L8, 0x400f4188 +.set CYREG_UDB_DSI1_HV_L9, 0x400f4189 +.set CYREG_UDB_DSI1_HV_L10, 0x400f418a +.set CYREG_UDB_DSI1_HV_L11, 0x400f418b +.set CYREG_UDB_DSI1_HV_L12, 0x400f418c +.set CYREG_UDB_DSI1_HV_L13, 0x400f418d +.set CYREG_UDB_DSI1_HV_L14, 0x400f418e +.set CYREG_UDB_DSI1_HV_L15, 0x400f418f +.set CYREG_UDB_DSI1_HS0, 0x400f4190 +.set CYREG_UDB_DSI1_HS1, 0x400f4191 +.set CYREG_UDB_DSI1_HS2, 0x400f4192 +.set CYREG_UDB_DSI1_HS3, 0x400f4193 +.set CYREG_UDB_DSI1_HS4, 0x400f4194 +.set CYREG_UDB_DSI1_HS5, 0x400f4195 +.set CYREG_UDB_DSI1_HS6, 0x400f4196 +.set CYREG_UDB_DSI1_HS7, 0x400f4197 +.set CYREG_UDB_DSI1_HS8, 0x400f4198 +.set CYREG_UDB_DSI1_HS9, 0x400f4199 +.set CYREG_UDB_DSI1_HS10, 0x400f419a +.set CYREG_UDB_DSI1_HS11, 0x400f419b +.set CYREG_UDB_DSI1_HS12, 0x400f419c +.set CYREG_UDB_DSI1_HS13, 0x400f419d +.set CYREG_UDB_DSI1_HS14, 0x400f419e +.set CYREG_UDB_DSI1_HS15, 0x400f419f +.set CYREG_UDB_DSI1_HS16, 0x400f41a0 +.set CYREG_UDB_DSI1_HS17, 0x400f41a1 +.set CYREG_UDB_DSI1_HS18, 0x400f41a2 +.set CYREG_UDB_DSI1_HS19, 0x400f41a3 +.set CYREG_UDB_DSI1_HS20, 0x400f41a4 +.set CYREG_UDB_DSI1_HS21, 0x400f41a5 +.set CYREG_UDB_DSI1_HS22, 0x400f41a6 +.set CYREG_UDB_DSI1_HS23, 0x400f41a7 +.set CYREG_UDB_DSI1_HV_R0, 0x400f41a8 +.set CYREG_UDB_DSI1_HV_R1, 0x400f41a9 +.set CYREG_UDB_DSI1_HV_R2, 0x400f41aa +.set CYREG_UDB_DSI1_HV_R3, 0x400f41ab +.set CYREG_UDB_DSI1_HV_R4, 0x400f41ac +.set CYREG_UDB_DSI1_HV_R5, 0x400f41ad +.set CYREG_UDB_DSI1_HV_R6, 0x400f41ae +.set CYREG_UDB_DSI1_HV_R7, 0x400f41af +.set CYREG_UDB_DSI1_HV_R8, 0x400f41b0 +.set CYREG_UDB_DSI1_HV_R9, 0x400f41b1 +.set CYREG_UDB_DSI1_HV_R10, 0x400f41b2 +.set CYREG_UDB_DSI1_HV_R11, 0x400f41b3 +.set CYREG_UDB_DSI1_HV_R12, 0x400f41b4 +.set CYREG_UDB_DSI1_HV_R13, 0x400f41b5 +.set CYREG_UDB_DSI1_HV_R14, 0x400f41b6 +.set CYREG_UDB_DSI1_HV_R15, 0x400f41b7 +.set CYREG_UDB_DSI1_DSIINP0, 0x400f41c0 +.set CYREG_UDB_DSI1_DSIINP1, 0x400f41c2 +.set CYREG_UDB_DSI1_DSIINP2, 0x400f41c4 +.set CYREG_UDB_DSI1_DSIINP3, 0x400f41c6 +.set CYREG_UDB_DSI1_DSIINP4, 0x400f41c8 +.set CYREG_UDB_DSI1_DSIINP5, 0x400f41ca +.set CYREG_UDB_DSI1_DSIOUTP0, 0x400f41cc +.set CYREG_UDB_DSI1_DSIOUTP1, 0x400f41ce +.set CYREG_UDB_DSI1_DSIOUTP2, 0x400f41d0 +.set CYREG_UDB_DSI1_DSIOUTP3, 0x400f41d2 +.set CYREG_UDB_DSI1_DSIOUTT0, 0x400f41d4 +.set CYREG_UDB_DSI1_DSIOUTT1, 0x400f41d6 +.set CYREG_UDB_DSI1_DSIOUTT2, 0x400f41d8 +.set CYREG_UDB_DSI1_DSIOUTT3, 0x400f41da +.set CYREG_UDB_DSI1_DSIOUTT4, 0x400f41dc +.set CYREG_UDB_DSI1_DSIOUTT5, 0x400f41de +.set CYREG_UDB_DSI1_VS0, 0x400f41e0 +.set CYREG_UDB_DSI1_VS1, 0x400f41e2 +.set CYREG_UDB_DSI1_VS2, 0x400f41e4 +.set CYREG_UDB_DSI1_VS3, 0x400f41e6 +.set CYREG_UDB_DSI1_VS4, 0x400f41e8 +.set CYREG_UDB_DSI1_VS5, 0x400f41ea +.set CYREG_UDB_DSI1_VS6, 0x400f41ec +.set CYREG_UDB_DSI1_VS7, 0x400f41ee +.set CYDEV_UDB_DSI2_BASE, 0x400f4200 +.set CYDEV_UDB_DSI2_SIZE, 0x00000100 +.set CYREG_UDB_DSI2_HC0, 0x400f4200 +.set CYREG_UDB_DSI2_HC1, 0x400f4201 +.set CYREG_UDB_DSI2_HC2, 0x400f4202 +.set CYREG_UDB_DSI2_HC3, 0x400f4203 +.set CYREG_UDB_DSI2_HC4, 0x400f4204 +.set CYREG_UDB_DSI2_HC5, 0x400f4205 +.set CYREG_UDB_DSI2_HC6, 0x400f4206 +.set CYREG_UDB_DSI2_HC7, 0x400f4207 +.set CYREG_UDB_DSI2_HC8, 0x400f4208 +.set CYREG_UDB_DSI2_HC9, 0x400f4209 +.set CYREG_UDB_DSI2_HC10, 0x400f420a +.set CYREG_UDB_DSI2_HC11, 0x400f420b +.set CYREG_UDB_DSI2_HC12, 0x400f420c +.set CYREG_UDB_DSI2_HC13, 0x400f420d +.set CYREG_UDB_DSI2_HC14, 0x400f420e +.set CYREG_UDB_DSI2_HC15, 0x400f420f +.set CYREG_UDB_DSI2_HC16, 0x400f4210 +.set CYREG_UDB_DSI2_HC17, 0x400f4211 +.set CYREG_UDB_DSI2_HC18, 0x400f4212 +.set CYREG_UDB_DSI2_HC19, 0x400f4213 +.set CYREG_UDB_DSI2_HC20, 0x400f4214 +.set CYREG_UDB_DSI2_HC21, 0x400f4215 +.set CYREG_UDB_DSI2_HC22, 0x400f4216 +.set CYREG_UDB_DSI2_HC23, 0x400f4217 +.set CYREG_UDB_DSI2_HC24, 0x400f4218 +.set CYREG_UDB_DSI2_HC25, 0x400f4219 +.set CYREG_UDB_DSI2_HC26, 0x400f421a +.set CYREG_UDB_DSI2_HC27, 0x400f421b +.set CYREG_UDB_DSI2_HC28, 0x400f421c +.set CYREG_UDB_DSI2_HC29, 0x400f421d +.set CYREG_UDB_DSI2_HC30, 0x400f421e +.set CYREG_UDB_DSI2_HC31, 0x400f421f +.set CYREG_UDB_DSI2_HC32, 0x400f4220 +.set CYREG_UDB_DSI2_HC33, 0x400f4221 +.set CYREG_UDB_DSI2_HC34, 0x400f4222 +.set CYREG_UDB_DSI2_HC35, 0x400f4223 +.set CYREG_UDB_DSI2_HC36, 0x400f4224 +.set CYREG_UDB_DSI2_HC37, 0x400f4225 +.set CYREG_UDB_DSI2_HC38, 0x400f4226 +.set CYREG_UDB_DSI2_HC39, 0x400f4227 +.set CYREG_UDB_DSI2_HC40, 0x400f4228 +.set CYREG_UDB_DSI2_HC41, 0x400f4229 +.set CYREG_UDB_DSI2_HC42, 0x400f422a +.set CYREG_UDB_DSI2_HC43, 0x400f422b +.set CYREG_UDB_DSI2_HC44, 0x400f422c +.set CYREG_UDB_DSI2_HC45, 0x400f422d +.set CYREG_UDB_DSI2_HC46, 0x400f422e +.set CYREG_UDB_DSI2_HC47, 0x400f422f +.set CYREG_UDB_DSI2_HC48, 0x400f4230 +.set CYREG_UDB_DSI2_HC49, 0x400f4231 +.set CYREG_UDB_DSI2_HC50, 0x400f4232 +.set CYREG_UDB_DSI2_HC51, 0x400f4233 +.set CYREG_UDB_DSI2_HC52, 0x400f4234 +.set CYREG_UDB_DSI2_HC53, 0x400f4235 +.set CYREG_UDB_DSI2_HC54, 0x400f4236 +.set CYREG_UDB_DSI2_HC55, 0x400f4237 +.set CYREG_UDB_DSI2_HC56, 0x400f4238 +.set CYREG_UDB_DSI2_HC57, 0x400f4239 +.set CYREG_UDB_DSI2_HC58, 0x400f423a +.set CYREG_UDB_DSI2_HC59, 0x400f423b +.set CYREG_UDB_DSI2_HC60, 0x400f423c +.set CYREG_UDB_DSI2_HC61, 0x400f423d +.set CYREG_UDB_DSI2_HC62, 0x400f423e +.set CYREG_UDB_DSI2_HC63, 0x400f423f +.set CYREG_UDB_DSI2_HC64, 0x400f4240 +.set CYREG_UDB_DSI2_HC65, 0x400f4241 +.set CYREG_UDB_DSI2_HC66, 0x400f4242 +.set CYREG_UDB_DSI2_HC67, 0x400f4243 +.set CYREG_UDB_DSI2_HC68, 0x400f4244 +.set CYREG_UDB_DSI2_HC69, 0x400f4245 +.set CYREG_UDB_DSI2_HC70, 0x400f4246 +.set CYREG_UDB_DSI2_HC71, 0x400f4247 +.set CYREG_UDB_DSI2_HC72, 0x400f4248 +.set CYREG_UDB_DSI2_HC73, 0x400f4249 +.set CYREG_UDB_DSI2_HC74, 0x400f424a +.set CYREG_UDB_DSI2_HC75, 0x400f424b +.set CYREG_UDB_DSI2_HC76, 0x400f424c +.set CYREG_UDB_DSI2_HC77, 0x400f424d +.set CYREG_UDB_DSI2_HC78, 0x400f424e +.set CYREG_UDB_DSI2_HC79, 0x400f424f +.set CYREG_UDB_DSI2_HC80, 0x400f4250 +.set CYREG_UDB_DSI2_HC81, 0x400f4251 +.set CYREG_UDB_DSI2_HC82, 0x400f4252 +.set CYREG_UDB_DSI2_HC83, 0x400f4253 +.set CYREG_UDB_DSI2_HC84, 0x400f4254 +.set CYREG_UDB_DSI2_HC85, 0x400f4255 +.set CYREG_UDB_DSI2_HC86, 0x400f4256 +.set CYREG_UDB_DSI2_HC87, 0x400f4257 +.set CYREG_UDB_DSI2_HC88, 0x400f4258 +.set CYREG_UDB_DSI2_HC89, 0x400f4259 +.set CYREG_UDB_DSI2_HC90, 0x400f425a +.set CYREG_UDB_DSI2_HC91, 0x400f425b +.set CYREG_UDB_DSI2_HC92, 0x400f425c +.set CYREG_UDB_DSI2_HC93, 0x400f425d +.set CYREG_UDB_DSI2_HC94, 0x400f425e +.set CYREG_UDB_DSI2_HC95, 0x400f425f +.set CYREG_UDB_DSI2_HC96, 0x400f4260 +.set CYREG_UDB_DSI2_HC97, 0x400f4261 +.set CYREG_UDB_DSI2_HC98, 0x400f4262 +.set CYREG_UDB_DSI2_HC99, 0x400f4263 +.set CYREG_UDB_DSI2_HC100, 0x400f4264 +.set CYREG_UDB_DSI2_HC101, 0x400f4265 +.set CYREG_UDB_DSI2_HC102, 0x400f4266 +.set CYREG_UDB_DSI2_HC103, 0x400f4267 +.set CYREG_UDB_DSI2_HC104, 0x400f4268 +.set CYREG_UDB_DSI2_HC105, 0x400f4269 +.set CYREG_UDB_DSI2_HC106, 0x400f426a +.set CYREG_UDB_DSI2_HC107, 0x400f426b +.set CYREG_UDB_DSI2_HC108, 0x400f426c +.set CYREG_UDB_DSI2_HC109, 0x400f426d +.set CYREG_UDB_DSI2_HC110, 0x400f426e +.set CYREG_UDB_DSI2_HC111, 0x400f426f +.set CYREG_UDB_DSI2_HC112, 0x400f4270 +.set CYREG_UDB_DSI2_HC113, 0x400f4271 +.set CYREG_UDB_DSI2_HC114, 0x400f4272 +.set CYREG_UDB_DSI2_HC115, 0x400f4273 +.set CYREG_UDB_DSI2_HC116, 0x400f4274 +.set CYREG_UDB_DSI2_HC117, 0x400f4275 +.set CYREG_UDB_DSI2_HC118, 0x400f4276 +.set CYREG_UDB_DSI2_HC119, 0x400f4277 +.set CYREG_UDB_DSI2_HC120, 0x400f4278 +.set CYREG_UDB_DSI2_HC121, 0x400f4279 +.set CYREG_UDB_DSI2_HC122, 0x400f427a +.set CYREG_UDB_DSI2_HC123, 0x400f427b +.set CYREG_UDB_DSI2_HC124, 0x400f427c +.set CYREG_UDB_DSI2_HC125, 0x400f427d +.set CYREG_UDB_DSI2_HC126, 0x400f427e +.set CYREG_UDB_DSI2_HC127, 0x400f427f +.set CYREG_UDB_DSI2_HV_L0, 0x400f4280 +.set CYREG_UDB_DSI2_HV_L1, 0x400f4281 +.set CYREG_UDB_DSI2_HV_L2, 0x400f4282 +.set CYREG_UDB_DSI2_HV_L3, 0x400f4283 +.set CYREG_UDB_DSI2_HV_L4, 0x400f4284 +.set CYREG_UDB_DSI2_HV_L5, 0x400f4285 +.set CYREG_UDB_DSI2_HV_L6, 0x400f4286 +.set CYREG_UDB_DSI2_HV_L7, 0x400f4287 +.set CYREG_UDB_DSI2_HV_L8, 0x400f4288 +.set CYREG_UDB_DSI2_HV_L9, 0x400f4289 +.set CYREG_UDB_DSI2_HV_L10, 0x400f428a +.set CYREG_UDB_DSI2_HV_L11, 0x400f428b +.set CYREG_UDB_DSI2_HV_L12, 0x400f428c +.set CYREG_UDB_DSI2_HV_L13, 0x400f428d +.set CYREG_UDB_DSI2_HV_L14, 0x400f428e +.set CYREG_UDB_DSI2_HV_L15, 0x400f428f +.set CYREG_UDB_DSI2_HS0, 0x400f4290 +.set CYREG_UDB_DSI2_HS1, 0x400f4291 +.set CYREG_UDB_DSI2_HS2, 0x400f4292 +.set CYREG_UDB_DSI2_HS3, 0x400f4293 +.set CYREG_UDB_DSI2_HS4, 0x400f4294 +.set CYREG_UDB_DSI2_HS5, 0x400f4295 +.set CYREG_UDB_DSI2_HS6, 0x400f4296 +.set CYREG_UDB_DSI2_HS7, 0x400f4297 +.set CYREG_UDB_DSI2_HS8, 0x400f4298 +.set CYREG_UDB_DSI2_HS9, 0x400f4299 +.set CYREG_UDB_DSI2_HS10, 0x400f429a +.set CYREG_UDB_DSI2_HS11, 0x400f429b +.set CYREG_UDB_DSI2_HS12, 0x400f429c +.set CYREG_UDB_DSI2_HS13, 0x400f429d +.set CYREG_UDB_DSI2_HS14, 0x400f429e +.set CYREG_UDB_DSI2_HS15, 0x400f429f +.set CYREG_UDB_DSI2_HS16, 0x400f42a0 +.set CYREG_UDB_DSI2_HS17, 0x400f42a1 +.set CYREG_UDB_DSI2_HS18, 0x400f42a2 +.set CYREG_UDB_DSI2_HS19, 0x400f42a3 +.set CYREG_UDB_DSI2_HS20, 0x400f42a4 +.set CYREG_UDB_DSI2_HS21, 0x400f42a5 +.set CYREG_UDB_DSI2_HS22, 0x400f42a6 +.set CYREG_UDB_DSI2_HS23, 0x400f42a7 +.set CYREG_UDB_DSI2_HV_R0, 0x400f42a8 +.set CYREG_UDB_DSI2_HV_R1, 0x400f42a9 +.set CYREG_UDB_DSI2_HV_R2, 0x400f42aa +.set CYREG_UDB_DSI2_HV_R3, 0x400f42ab +.set CYREG_UDB_DSI2_HV_R4, 0x400f42ac +.set CYREG_UDB_DSI2_HV_R5, 0x400f42ad +.set CYREG_UDB_DSI2_HV_R6, 0x400f42ae +.set CYREG_UDB_DSI2_HV_R7, 0x400f42af +.set CYREG_UDB_DSI2_HV_R8, 0x400f42b0 +.set CYREG_UDB_DSI2_HV_R9, 0x400f42b1 +.set CYREG_UDB_DSI2_HV_R10, 0x400f42b2 +.set CYREG_UDB_DSI2_HV_R11, 0x400f42b3 +.set CYREG_UDB_DSI2_HV_R12, 0x400f42b4 +.set CYREG_UDB_DSI2_HV_R13, 0x400f42b5 +.set CYREG_UDB_DSI2_HV_R14, 0x400f42b6 +.set CYREG_UDB_DSI2_HV_R15, 0x400f42b7 +.set CYREG_UDB_DSI2_DSIINP0, 0x400f42c0 +.set CYREG_UDB_DSI2_DSIINP1, 0x400f42c2 +.set CYREG_UDB_DSI2_DSIINP2, 0x400f42c4 +.set CYREG_UDB_DSI2_DSIINP3, 0x400f42c6 +.set CYREG_UDB_DSI2_DSIINP4, 0x400f42c8 +.set CYREG_UDB_DSI2_DSIINP5, 0x400f42ca +.set CYREG_UDB_DSI2_DSIOUTP0, 0x400f42cc +.set CYREG_UDB_DSI2_DSIOUTP1, 0x400f42ce +.set CYREG_UDB_DSI2_DSIOUTP2, 0x400f42d0 +.set CYREG_UDB_DSI2_DSIOUTP3, 0x400f42d2 +.set CYREG_UDB_DSI2_DSIOUTT0, 0x400f42d4 +.set CYREG_UDB_DSI2_DSIOUTT1, 0x400f42d6 +.set CYREG_UDB_DSI2_DSIOUTT2, 0x400f42d8 +.set CYREG_UDB_DSI2_DSIOUTT3, 0x400f42da +.set CYREG_UDB_DSI2_DSIOUTT4, 0x400f42dc +.set CYREG_UDB_DSI2_DSIOUTT5, 0x400f42de +.set CYREG_UDB_DSI2_VS0, 0x400f42e0 +.set CYREG_UDB_DSI2_VS1, 0x400f42e2 +.set CYREG_UDB_DSI2_VS2, 0x400f42e4 +.set CYREG_UDB_DSI2_VS3, 0x400f42e6 +.set CYREG_UDB_DSI2_VS4, 0x400f42e8 +.set CYREG_UDB_DSI2_VS5, 0x400f42ea +.set CYREG_UDB_DSI2_VS6, 0x400f42ec +.set CYREG_UDB_DSI2_VS7, 0x400f42ee +.set CYDEV_UDB_DSI3_BASE, 0x400f4300 +.set CYDEV_UDB_DSI3_SIZE, 0x00000100 +.set CYREG_UDB_DSI3_HC0, 0x400f4300 +.set CYREG_UDB_DSI3_HC1, 0x400f4301 +.set CYREG_UDB_DSI3_HC2, 0x400f4302 +.set CYREG_UDB_DSI3_HC3, 0x400f4303 +.set CYREG_UDB_DSI3_HC4, 0x400f4304 +.set CYREG_UDB_DSI3_HC5, 0x400f4305 +.set CYREG_UDB_DSI3_HC6, 0x400f4306 +.set CYREG_UDB_DSI3_HC7, 0x400f4307 +.set CYREG_UDB_DSI3_HC8, 0x400f4308 +.set CYREG_UDB_DSI3_HC9, 0x400f4309 +.set CYREG_UDB_DSI3_HC10, 0x400f430a +.set CYREG_UDB_DSI3_HC11, 0x400f430b +.set CYREG_UDB_DSI3_HC12, 0x400f430c +.set CYREG_UDB_DSI3_HC13, 0x400f430d +.set CYREG_UDB_DSI3_HC14, 0x400f430e +.set CYREG_UDB_DSI3_HC15, 0x400f430f +.set CYREG_UDB_DSI3_HC16, 0x400f4310 +.set CYREG_UDB_DSI3_HC17, 0x400f4311 +.set CYREG_UDB_DSI3_HC18, 0x400f4312 +.set CYREG_UDB_DSI3_HC19, 0x400f4313 +.set CYREG_UDB_DSI3_HC20, 0x400f4314 +.set CYREG_UDB_DSI3_HC21, 0x400f4315 +.set CYREG_UDB_DSI3_HC22, 0x400f4316 +.set CYREG_UDB_DSI3_HC23, 0x400f4317 +.set CYREG_UDB_DSI3_HC24, 0x400f4318 +.set CYREG_UDB_DSI3_HC25, 0x400f4319 +.set CYREG_UDB_DSI3_HC26, 0x400f431a +.set CYREG_UDB_DSI3_HC27, 0x400f431b +.set CYREG_UDB_DSI3_HC28, 0x400f431c +.set CYREG_UDB_DSI3_HC29, 0x400f431d +.set CYREG_UDB_DSI3_HC30, 0x400f431e +.set CYREG_UDB_DSI3_HC31, 0x400f431f +.set CYREG_UDB_DSI3_HC32, 0x400f4320 +.set CYREG_UDB_DSI3_HC33, 0x400f4321 +.set CYREG_UDB_DSI3_HC34, 0x400f4322 +.set CYREG_UDB_DSI3_HC35, 0x400f4323 +.set CYREG_UDB_DSI3_HC36, 0x400f4324 +.set CYREG_UDB_DSI3_HC37, 0x400f4325 +.set CYREG_UDB_DSI3_HC38, 0x400f4326 +.set CYREG_UDB_DSI3_HC39, 0x400f4327 +.set CYREG_UDB_DSI3_HC40, 0x400f4328 +.set CYREG_UDB_DSI3_HC41, 0x400f4329 +.set CYREG_UDB_DSI3_HC42, 0x400f432a +.set CYREG_UDB_DSI3_HC43, 0x400f432b +.set CYREG_UDB_DSI3_HC44, 0x400f432c +.set CYREG_UDB_DSI3_HC45, 0x400f432d +.set CYREG_UDB_DSI3_HC46, 0x400f432e +.set CYREG_UDB_DSI3_HC47, 0x400f432f +.set CYREG_UDB_DSI3_HC48, 0x400f4330 +.set CYREG_UDB_DSI3_HC49, 0x400f4331 +.set CYREG_UDB_DSI3_HC50, 0x400f4332 +.set CYREG_UDB_DSI3_HC51, 0x400f4333 +.set CYREG_UDB_DSI3_HC52, 0x400f4334 +.set CYREG_UDB_DSI3_HC53, 0x400f4335 +.set CYREG_UDB_DSI3_HC54, 0x400f4336 +.set CYREG_UDB_DSI3_HC55, 0x400f4337 +.set CYREG_UDB_DSI3_HC56, 0x400f4338 +.set CYREG_UDB_DSI3_HC57, 0x400f4339 +.set CYREG_UDB_DSI3_HC58, 0x400f433a +.set CYREG_UDB_DSI3_HC59, 0x400f433b +.set CYREG_UDB_DSI3_HC60, 0x400f433c +.set CYREG_UDB_DSI3_HC61, 0x400f433d +.set CYREG_UDB_DSI3_HC62, 0x400f433e +.set CYREG_UDB_DSI3_HC63, 0x400f433f +.set CYREG_UDB_DSI3_HC64, 0x400f4340 +.set CYREG_UDB_DSI3_HC65, 0x400f4341 +.set CYREG_UDB_DSI3_HC66, 0x400f4342 +.set CYREG_UDB_DSI3_HC67, 0x400f4343 +.set CYREG_UDB_DSI3_HC68, 0x400f4344 +.set CYREG_UDB_DSI3_HC69, 0x400f4345 +.set CYREG_UDB_DSI3_HC70, 0x400f4346 +.set CYREG_UDB_DSI3_HC71, 0x400f4347 +.set CYREG_UDB_DSI3_HC72, 0x400f4348 +.set CYREG_UDB_DSI3_HC73, 0x400f4349 +.set CYREG_UDB_DSI3_HC74, 0x400f434a +.set CYREG_UDB_DSI3_HC75, 0x400f434b +.set CYREG_UDB_DSI3_HC76, 0x400f434c +.set CYREG_UDB_DSI3_HC77, 0x400f434d +.set CYREG_UDB_DSI3_HC78, 0x400f434e +.set CYREG_UDB_DSI3_HC79, 0x400f434f +.set CYREG_UDB_DSI3_HC80, 0x400f4350 +.set CYREG_UDB_DSI3_HC81, 0x400f4351 +.set CYREG_UDB_DSI3_HC82, 0x400f4352 +.set CYREG_UDB_DSI3_HC83, 0x400f4353 +.set CYREG_UDB_DSI3_HC84, 0x400f4354 +.set CYREG_UDB_DSI3_HC85, 0x400f4355 +.set CYREG_UDB_DSI3_HC86, 0x400f4356 +.set CYREG_UDB_DSI3_HC87, 0x400f4357 +.set CYREG_UDB_DSI3_HC88, 0x400f4358 +.set CYREG_UDB_DSI3_HC89, 0x400f4359 +.set CYREG_UDB_DSI3_HC90, 0x400f435a +.set CYREG_UDB_DSI3_HC91, 0x400f435b +.set CYREG_UDB_DSI3_HC92, 0x400f435c +.set CYREG_UDB_DSI3_HC93, 0x400f435d +.set CYREG_UDB_DSI3_HC94, 0x400f435e +.set CYREG_UDB_DSI3_HC95, 0x400f435f +.set CYREG_UDB_DSI3_HC96, 0x400f4360 +.set CYREG_UDB_DSI3_HC97, 0x400f4361 +.set CYREG_UDB_DSI3_HC98, 0x400f4362 +.set CYREG_UDB_DSI3_HC99, 0x400f4363 +.set CYREG_UDB_DSI3_HC100, 0x400f4364 +.set CYREG_UDB_DSI3_HC101, 0x400f4365 +.set CYREG_UDB_DSI3_HC102, 0x400f4366 +.set CYREG_UDB_DSI3_HC103, 0x400f4367 +.set CYREG_UDB_DSI3_HC104, 0x400f4368 +.set CYREG_UDB_DSI3_HC105, 0x400f4369 +.set CYREG_UDB_DSI3_HC106, 0x400f436a +.set CYREG_UDB_DSI3_HC107, 0x400f436b +.set CYREG_UDB_DSI3_HC108, 0x400f436c +.set CYREG_UDB_DSI3_HC109, 0x400f436d +.set CYREG_UDB_DSI3_HC110, 0x400f436e +.set CYREG_UDB_DSI3_HC111, 0x400f436f +.set CYREG_UDB_DSI3_HC112, 0x400f4370 +.set CYREG_UDB_DSI3_HC113, 0x400f4371 +.set CYREG_UDB_DSI3_HC114, 0x400f4372 +.set CYREG_UDB_DSI3_HC115, 0x400f4373 +.set CYREG_UDB_DSI3_HC116, 0x400f4374 +.set CYREG_UDB_DSI3_HC117, 0x400f4375 +.set CYREG_UDB_DSI3_HC118, 0x400f4376 +.set CYREG_UDB_DSI3_HC119, 0x400f4377 +.set CYREG_UDB_DSI3_HC120, 0x400f4378 +.set CYREG_UDB_DSI3_HC121, 0x400f4379 +.set CYREG_UDB_DSI3_HC122, 0x400f437a +.set CYREG_UDB_DSI3_HC123, 0x400f437b +.set CYREG_UDB_DSI3_HC124, 0x400f437c +.set CYREG_UDB_DSI3_HC125, 0x400f437d +.set CYREG_UDB_DSI3_HC126, 0x400f437e +.set CYREG_UDB_DSI3_HC127, 0x400f437f +.set CYREG_UDB_DSI3_HV_L0, 0x400f4380 +.set CYREG_UDB_DSI3_HV_L1, 0x400f4381 +.set CYREG_UDB_DSI3_HV_L2, 0x400f4382 +.set CYREG_UDB_DSI3_HV_L3, 0x400f4383 +.set CYREG_UDB_DSI3_HV_L4, 0x400f4384 +.set CYREG_UDB_DSI3_HV_L5, 0x400f4385 +.set CYREG_UDB_DSI3_HV_L6, 0x400f4386 +.set CYREG_UDB_DSI3_HV_L7, 0x400f4387 +.set CYREG_UDB_DSI3_HV_L8, 0x400f4388 +.set CYREG_UDB_DSI3_HV_L9, 0x400f4389 +.set CYREG_UDB_DSI3_HV_L10, 0x400f438a +.set CYREG_UDB_DSI3_HV_L11, 0x400f438b +.set CYREG_UDB_DSI3_HV_L12, 0x400f438c +.set CYREG_UDB_DSI3_HV_L13, 0x400f438d +.set CYREG_UDB_DSI3_HV_L14, 0x400f438e +.set CYREG_UDB_DSI3_HV_L15, 0x400f438f +.set CYREG_UDB_DSI3_HS0, 0x400f4390 +.set CYREG_UDB_DSI3_HS1, 0x400f4391 +.set CYREG_UDB_DSI3_HS2, 0x400f4392 +.set CYREG_UDB_DSI3_HS3, 0x400f4393 +.set CYREG_UDB_DSI3_HS4, 0x400f4394 +.set CYREG_UDB_DSI3_HS5, 0x400f4395 +.set CYREG_UDB_DSI3_HS6, 0x400f4396 +.set CYREG_UDB_DSI3_HS7, 0x400f4397 +.set CYREG_UDB_DSI3_HS8, 0x400f4398 +.set CYREG_UDB_DSI3_HS9, 0x400f4399 +.set CYREG_UDB_DSI3_HS10, 0x400f439a +.set CYREG_UDB_DSI3_HS11, 0x400f439b +.set CYREG_UDB_DSI3_HS12, 0x400f439c +.set CYREG_UDB_DSI3_HS13, 0x400f439d +.set CYREG_UDB_DSI3_HS14, 0x400f439e +.set CYREG_UDB_DSI3_HS15, 0x400f439f +.set CYREG_UDB_DSI3_HS16, 0x400f43a0 +.set CYREG_UDB_DSI3_HS17, 0x400f43a1 +.set CYREG_UDB_DSI3_HS18, 0x400f43a2 +.set CYREG_UDB_DSI3_HS19, 0x400f43a3 +.set CYREG_UDB_DSI3_HS20, 0x400f43a4 +.set CYREG_UDB_DSI3_HS21, 0x400f43a5 +.set CYREG_UDB_DSI3_HS22, 0x400f43a6 +.set CYREG_UDB_DSI3_HS23, 0x400f43a7 +.set CYREG_UDB_DSI3_HV_R0, 0x400f43a8 +.set CYREG_UDB_DSI3_HV_R1, 0x400f43a9 +.set CYREG_UDB_DSI3_HV_R2, 0x400f43aa +.set CYREG_UDB_DSI3_HV_R3, 0x400f43ab +.set CYREG_UDB_DSI3_HV_R4, 0x400f43ac +.set CYREG_UDB_DSI3_HV_R5, 0x400f43ad +.set CYREG_UDB_DSI3_HV_R6, 0x400f43ae +.set CYREG_UDB_DSI3_HV_R7, 0x400f43af +.set CYREG_UDB_DSI3_HV_R8, 0x400f43b0 +.set CYREG_UDB_DSI3_HV_R9, 0x400f43b1 +.set CYREG_UDB_DSI3_HV_R10, 0x400f43b2 +.set CYREG_UDB_DSI3_HV_R11, 0x400f43b3 +.set CYREG_UDB_DSI3_HV_R12, 0x400f43b4 +.set CYREG_UDB_DSI3_HV_R13, 0x400f43b5 +.set CYREG_UDB_DSI3_HV_R14, 0x400f43b6 +.set CYREG_UDB_DSI3_HV_R15, 0x400f43b7 +.set CYREG_UDB_DSI3_DSIINP0, 0x400f43c0 +.set CYREG_UDB_DSI3_DSIINP1, 0x400f43c2 +.set CYREG_UDB_DSI3_DSIINP2, 0x400f43c4 +.set CYREG_UDB_DSI3_DSIINP3, 0x400f43c6 +.set CYREG_UDB_DSI3_DSIINP4, 0x400f43c8 +.set CYREG_UDB_DSI3_DSIINP5, 0x400f43ca +.set CYREG_UDB_DSI3_DSIOUTP0, 0x400f43cc +.set CYREG_UDB_DSI3_DSIOUTP1, 0x400f43ce +.set CYREG_UDB_DSI3_DSIOUTP2, 0x400f43d0 +.set CYREG_UDB_DSI3_DSIOUTP3, 0x400f43d2 +.set CYREG_UDB_DSI3_DSIOUTT0, 0x400f43d4 +.set CYREG_UDB_DSI3_DSIOUTT1, 0x400f43d6 +.set CYREG_UDB_DSI3_DSIOUTT2, 0x400f43d8 +.set CYREG_UDB_DSI3_DSIOUTT3, 0x400f43da +.set CYREG_UDB_DSI3_DSIOUTT4, 0x400f43dc +.set CYREG_UDB_DSI3_DSIOUTT5, 0x400f43de +.set CYREG_UDB_DSI3_VS0, 0x400f43e0 +.set CYREG_UDB_DSI3_VS1, 0x400f43e2 +.set CYREG_UDB_DSI3_VS2, 0x400f43e4 +.set CYREG_UDB_DSI3_VS3, 0x400f43e6 +.set CYREG_UDB_DSI3_VS4, 0x400f43e8 +.set CYREG_UDB_DSI3_VS5, 0x400f43ea +.set CYREG_UDB_DSI3_VS6, 0x400f43ec +.set CYREG_UDB_DSI3_VS7, 0x400f43ee +.set CYDEV_UDB_PA0_BASE, 0x400f5000 +.set CYDEV_UDB_PA0_SIZE, 0x00000010 +.set CYREG_UDB_PA0_CFG0, 0x400f5000 +.set CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_OFF, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_ON, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL, 0x00000003 +.set CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_CLKIN_EN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_EN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_EN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_CLKIN_INV__OFFSET, 0x00000005 +.set CYFLD_UDB_PA_CLKIN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_NC__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_NC__SIZE, 0x00000002 +.set CYREG_UDB_PA0_CFG1, 0x400f5001 +.set CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_ON, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL, 0x00000003 +.set CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_EN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_CLKOUT_INV__OFFSET, 0x00000005 +.set CYFLD_UDB_PA_CLKOUT_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_INV_INV, 0x00000001 +.set CYREG_UDB_PA0_CFG2, 0x400f5002 +.set CYFLD_UDB_PA_CLKIN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_CLKIN_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP, 0x00000009 +.set CYVAL_UDB_PA_CLKIN_SEL_PIN_RC, 0x0000000c +.set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0, 0x0000000d +.set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1, 0x0000000e +.set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2, 0x0000000f +.set CYFLD_UDB_PA_CLKOUT_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_CLKOUT_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP, 0x00000009 +.set CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC, 0x0000000c +.set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0, 0x0000000d +.set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1, 0x0000000e +.set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2, 0x0000000f +.set CYREG_UDB_PA0_CFG3, 0x400f5003 +.set CYFLD_UDB_PA_RES_IN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_RES_IN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_RES_IN_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_RES_IN_INV__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_RES_IN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_IN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_RES_IN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_NC0__OFFSET, 0x00000003 +.set CYFLD_UDB_PA_NC0__SIZE, 0x00000001 +.set CYFLD_UDB_PA_RES_OUT_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_RES_OUT_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_RES_OUT_INV__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_RES_OUT_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_OUT_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_RES_OUT_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_NC7__OFFSET, 0x00000007 +.set CYFLD_UDB_PA_NC7__SIZE, 0x00000001 +.set CYREG_UDB_PA0_CFG4, 0x400f5004 +.set CYFLD_UDB_PA_RES_IN_EN__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_RES_IN_EN__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_IN_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_PA_RES_IN_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_PA_RES_OUT_EN__OFFSET, 0x00000001 +.set CYFLD_UDB_PA_RES_OUT_EN__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_OUT_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_PA_RES_OUT_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_PA_RES_OE_EN__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_RES_OE_EN__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_OE_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_PA_RES_OE_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_PA_NC7654__OFFSET, 0x00000003 +.set CYFLD_UDB_PA_NC7654__SIZE, 0x00000005 +.set CYREG_UDB_PA0_CFG5, 0x400f5005 +.set CYFLD_UDB_PA_PIN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_PIN_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_PA_PIN_SEL_PIN0, 0x00000000 +.set CYVAL_UDB_PA_PIN_SEL_PIN1, 0x00000001 +.set CYVAL_UDB_PA_PIN_SEL_PIN2, 0x00000002 +.set CYVAL_UDB_PA_PIN_SEL_PIN3, 0x00000003 +.set CYVAL_UDB_PA_PIN_SEL_PIN4, 0x00000004 +.set CYVAL_UDB_PA_PIN_SEL_PIN5, 0x00000005 +.set CYVAL_UDB_PA_PIN_SEL_PIN6, 0x00000006 +.set CYVAL_UDB_PA_PIN_SEL_PIN7, 0x00000007 +.set CYREG_UDB_PA0_CFG6, 0x400f5006 +.set CYFLD_UDB_PA_IN_SYNC0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_IN_SYNC0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC0_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_IN_SYNC1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC1_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_IN_SYNC2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC2_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_IN_SYNC3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC3_RSVD, 0x00000003 +.set CYREG_UDB_PA0_CFG7, 0x400f5007 +.set CYFLD_UDB_PA_IN_SYNC4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_IN_SYNC4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC4_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_IN_SYNC5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC5_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_IN_SYNC6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC6_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_IN_SYNC7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC7_RSVD, 0x00000003 +.set CYREG_UDB_PA0_CFG8, 0x400f5008 +.set CYFLD_UDB_PA_OUT_SYNC0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OUT_SYNC0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC0_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OUT_SYNC1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC1_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OUT_SYNC2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC2_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OUT_SYNC3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC3_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV, 0x00000003 +.set CYREG_UDB_PA0_CFG9, 0x400f5009 +.set CYFLD_UDB_PA_OUT_SYNC4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OUT_SYNC4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC4_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OUT_SYNC5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC5_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OUT_SYNC6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC6_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OUT_SYNC7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC7_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV, 0x00000003 +.set CYREG_UDB_PA0_CFG10, 0x400f500a +.set CYFLD_UDB_PA_DATA_SEL0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_DATA_SEL0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_DATA_SEL1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_DATA_SEL2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_DATA_SEL3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG11, 0x400f500b +.set CYFLD_UDB_PA_DATA_SEL4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_DATA_SEL4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_DATA_SEL5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_DATA_SEL6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_DATA_SEL7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG12, 0x400f500c +.set CYFLD_UDB_PA_OE_SEL0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OE_SEL0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OE_SEL1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OE_SEL2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OE_SEL3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG13, 0x400f500d +.set CYFLD_UDB_PA_OE_SEL4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OE_SEL4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OE_SEL5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OE_SEL6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OE_SEL7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG14, 0x400f500e +.set CYFLD_UDB_PA_OE_SYNC0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OE_SYNC0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC0_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC0_CONSTANT0, 0x00000003 +.set CYFLD_UDB_PA_OE_SYNC1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OE_SYNC1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC1_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC1_CONSTANT0, 0x00000003 +.set CYFLD_UDB_PA_OE_SYNC2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OE_SYNC2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC2_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC2_CONSTANT0, 0x00000003 +.set CYFLD_UDB_PA_OE_SYNC3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OE_SYNC3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC3_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC3_CONSTANT0, 0x00000003 +.set CYDEV_UDB_PA1_BASE, 0x400f5010 +.set CYDEV_UDB_PA1_SIZE, 0x00000010 +.set CYREG_UDB_PA1_CFG0, 0x400f5010 +.set CYREG_UDB_PA1_CFG1, 0x400f5011 +.set CYREG_UDB_PA1_CFG2, 0x400f5012 +.set CYREG_UDB_PA1_CFG3, 0x400f5013 +.set CYREG_UDB_PA1_CFG4, 0x400f5014 +.set CYREG_UDB_PA1_CFG5, 0x400f5015 +.set CYREG_UDB_PA1_CFG6, 0x400f5016 +.set CYREG_UDB_PA1_CFG7, 0x400f5017 +.set CYREG_UDB_PA1_CFG8, 0x400f5018 +.set CYREG_UDB_PA1_CFG9, 0x400f5019 +.set CYREG_UDB_PA1_CFG10, 0x400f501a +.set CYREG_UDB_PA1_CFG11, 0x400f501b +.set CYREG_UDB_PA1_CFG12, 0x400f501c +.set CYREG_UDB_PA1_CFG13, 0x400f501d +.set CYREG_UDB_PA1_CFG14, 0x400f501e +.set CYDEV_UDB_PA2_BASE, 0x400f5020 +.set CYDEV_UDB_PA2_SIZE, 0x00000010 +.set CYREG_UDB_PA2_CFG0, 0x400f5020 +.set CYREG_UDB_PA2_CFG1, 0x400f5021 +.set CYREG_UDB_PA2_CFG2, 0x400f5022 +.set CYREG_UDB_PA2_CFG3, 0x400f5023 +.set CYREG_UDB_PA2_CFG4, 0x400f5024 +.set CYREG_UDB_PA2_CFG5, 0x400f5025 +.set CYREG_UDB_PA2_CFG6, 0x400f5026 +.set CYREG_UDB_PA2_CFG7, 0x400f5027 +.set CYREG_UDB_PA2_CFG8, 0x400f5028 +.set CYREG_UDB_PA2_CFG9, 0x400f5029 +.set CYREG_UDB_PA2_CFG10, 0x400f502a +.set CYREG_UDB_PA2_CFG11, 0x400f502b +.set CYREG_UDB_PA2_CFG12, 0x400f502c +.set CYREG_UDB_PA2_CFG13, 0x400f502d +.set CYREG_UDB_PA2_CFG14, 0x400f502e +.set CYDEV_UDB_PA3_BASE, 0x400f5030 +.set CYDEV_UDB_PA3_SIZE, 0x00000010 +.set CYREG_UDB_PA3_CFG0, 0x400f5030 +.set CYREG_UDB_PA3_CFG1, 0x400f5031 +.set CYREG_UDB_PA3_CFG2, 0x400f5032 +.set CYREG_UDB_PA3_CFG3, 0x400f5033 +.set CYREG_UDB_PA3_CFG4, 0x400f5034 +.set CYREG_UDB_PA3_CFG5, 0x400f5035 +.set CYREG_UDB_PA3_CFG6, 0x400f5036 +.set CYREG_UDB_PA3_CFG7, 0x400f5037 +.set CYREG_UDB_PA3_CFG8, 0x400f5038 +.set CYREG_UDB_PA3_CFG9, 0x400f5039 +.set CYREG_UDB_PA3_CFG10, 0x400f503a +.set CYREG_UDB_PA3_CFG11, 0x400f503b +.set CYREG_UDB_PA3_CFG12, 0x400f503c +.set CYREG_UDB_PA3_CFG13, 0x400f503d +.set CYREG_UDB_PA3_CFG14, 0x400f503e +.set CYDEV_UDB_BCTL0_BASE, 0x400f6000 +.set CYDEV_UDB_BCTL0_SIZE, 0x00001000 +.set CYREG_UDB_BCTL0_DRV, 0x400f6000 +.set CYFLD_UDB_BCTL0_DRV__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_DRV__SIZE, 0x00000008 +.set CYVAL_UDB_BCTL0_DRV_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DRV_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_MDCLK_EN, 0x400f6001 +.set CYFLD_UDB_BCTL0_DCEN__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_DCEN__SIZE, 0x00000008 +.set CYVAL_UDB_BCTL0_DCEN_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DCEN_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_MBCLK_EN, 0x400f6002 +.set CYFLD_UDB_BCTL0_BCEN__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_BCEN__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_BCEN_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_BCEN_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_BOTSEL_L, 0x400f6008 +.set CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_CLK_SEL0__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET, 0x00000002 +.set CYFLD_UDB_BCTL0_CLK_SEL1__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET, 0x00000004 +.set CYFLD_UDB_BCTL0_CLK_SEL2__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET, 0x00000006 +.set CYFLD_UDB_BCTL0_CLK_SEL3__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT, 0x00000003 +.set CYREG_UDB_BCTL0_BOTSEL_U, 0x400f6009 +.set CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_CLK_SEL4__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET, 0x00000002 +.set CYFLD_UDB_BCTL0_CLK_SEL5__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET, 0x00000004 +.set CYFLD_UDB_BCTL0_CLK_SEL6__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET, 0x00000006 +.set CYFLD_UDB_BCTL0_CLK_SEL7__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT, 0x00000003 +.set CYREG_UDB_BCTL0_TOPSEL_L, 0x400f600a +.set CYREG_UDB_BCTL0_TOPSEL_U, 0x400f600b +.set CYREG_UDB_BCTL0_QCLK_EN0, 0x400f6010 +.set CYFLD_UDB_BCTL0_DCEN_Q__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_DCEN_Q__SIZE, 0x00000008 +.set CYVAL_UDB_BCTL0_DCEN_Q_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DCEN_Q_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_BCEN_Q__OFFSET, 0x00000008 +.set CYFLD_UDB_BCTL0_BCEN_Q__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_BCEN_Q_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_BCEN_Q_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET, 0x00000009 +.set CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET, 0x0000000a +.set CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET, 0x0000000b +.set CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET, 0x0000000c +.set CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET, 0x0000000d +.set CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB, 0x00000000 +.set CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB, 0x00000001 +.set CYFLD_UDB_BCTL0_NC0__OFFSET, 0x0000000e +.set CYFLD_UDB_BCTL0_NC0__SIZE, 0x00000001 +.set CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET, 0x0000000f +.set CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_QCLK_EN1, 0x400f6012 +.set CYDEV_UDB_UDBIF_BASE, 0x400f7000 +.set CYDEV_UDB_UDBIF_SIZE, 0x00001000 +.set CYREG_UDB_UDBIF_BANK_CTL, 0x400f7000 +.set CYFLD_UDB_UDBIF_DIS_COR__OFFSET, 0x00000000 +.set CYFLD_UDB_UDBIF_DIS_COR__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_DIS_COR_NORMAL, 0x00000000 +.set CYVAL_UDB_UDBIF_DIS_COR_DISABLE, 0x00000001 +.set CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET, 0x00000001 +.set CYFLD_UDB_UDBIF_ROUTE_EN__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_UDBIF_BANK_EN__OFFSET, 0x00000002 +.set CYFLD_UDB_UDBIF_BANK_EN__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_BANK_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_BANK_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_UDBIF_LOCK__OFFSET, 0x00000003 +.set CYFLD_UDB_UDBIF_LOCK__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_LOCK_MUTABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_LOCK_LOCKED, 0x00000001 +.set CYFLD_UDB_UDBIF_PIPE__OFFSET, 0x00000004 +.set CYFLD_UDB_UDBIF_PIPE__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_PIPE_BYPASS, 0x00000000 +.set CYVAL_UDB_UDBIF_PIPE_PIPELINED, 0x00000001 +.set CYFLD_UDB_UDBIF_GLBL_WR__OFFSET, 0x00000007 +.set CYFLD_UDB_UDBIF_GLBL_WR__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_GLBL_WR_DISABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_GLBL_WR_ENABLE, 0x00000001 +.set CYREG_UDB_UDBIF_WAIT_CFG, 0x400f7001 +.set CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET, 0x00000000 +.set CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS, 0x00000000 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT, 0x00000003 +.set CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET, 0x00000002 +.set CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT, 0x00000000 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS, 0x00000003 +.set CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET, 0x00000004 +.set CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT, 0x00000000 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS, 0x00000003 +.set CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET, 0x00000006 +.set CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT, 0x00000000 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS, 0x00000003 +.set CYREG_UDB_UDBIF_INT_CLK_CTL, 0x400f701c +.set CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET, 0x00000000 +.set CYFLD_UDB_UDBIF_EN_HFCLK__SIZE, 0x00000001 +.set CYREG_UDB_INT_CFG, 0x400f8000 +.set CYFLD_UDB_INT_MODE_CFG__OFFSET, 0x00000000 +.set CYFLD_UDB_INT_MODE_CFG__SIZE, 0x00000020 +.set CYVAL_UDB_INT_MODE_CFG_LEVEL, 0x00000000 +.set CYVAL_UDB_INT_MODE_CFG_PULSE, 0x00000001 +.set CYDEV_CTBM_BASE, 0x40100000 +.set CYDEV_CTBM_SIZE, 0x00010000 +.set CYREG_CTBM_CTB_CTRL, 0x40100000 +.set CYFLD_CTBM_ENABLED__OFFSET, 0x0000001f +.set CYFLD_CTBM_ENABLED__SIZE, 0x00000001 +.set CYREG_CTBM_OA_RES0_CTRL, 0x40100004 +.set CYFLD_CTBM_OA0_PWR_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_PWR_MODE__SIZE, 0x00000002 +.set CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_COMP_EN__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA0_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_HYST_EN__OFFSET, 0x00000005 +.set CYFLD_CTBM_OA0_HYST_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET, 0x00000006 +.set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_COMPINT__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA0_COMPINT__SIZE, 0x00000002 +.set CYVAL_CTBM_OA0_COMPINT_DISABLE, 0x00000000 +.set CYVAL_CTBM_OA0_COMPINT_RISING, 0x00000001 +.set CYVAL_CTBM_OA0_COMPINT_FALLING, 0x00000002 +.set CYVAL_CTBM_OA0_COMPINT_BOTH, 0x00000003 +.set CYFLD_CTBM_OA0_PUMP_EN__OFFSET, 0x0000000b +.set CYFLD_CTBM_OA0_PUMP_EN__SIZE, 0x00000001 +.set CYREG_CTBM_OA_RES1_CTRL, 0x40100008 +.set CYFLD_CTBM_OA1_PWR_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_PWR_MODE__SIZE, 0x00000002 +.set CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMP_EN__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA1_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_HYST_EN__OFFSET, 0x00000005 +.set CYFLD_CTBM_OA1_HYST_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET, 0x00000006 +.set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMPINT__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA1_COMPINT__SIZE, 0x00000002 +.set CYVAL_CTBM_OA1_COMPINT_DISABLE, 0x00000000 +.set CYVAL_CTBM_OA1_COMPINT_RISING, 0x00000001 +.set CYVAL_CTBM_OA1_COMPINT_FALLING, 0x00000002 +.set CYVAL_CTBM_OA1_COMPINT_BOTH, 0x00000003 +.set CYFLD_CTBM_OA1_PUMP_EN__OFFSET, 0x0000000b +.set CYFLD_CTBM_OA1_PUMP_EN__SIZE, 0x00000001 +.set CYREG_CTBM_COMP_STAT, 0x4010000c +.set CYFLD_CTBM_OA0_COMP__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_COMP__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMP__OFFSET, 0x00000010 +.set CYFLD_CTBM_OA1_COMP__SIZE, 0x00000001 +.set CYREG_CTBM_INTR, 0x40100020 +.set CYFLD_CTBM_COMP0__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1__SIZE, 0x00000001 +.set CYREG_CTBM_INTR_SET, 0x40100024 +.set CYFLD_CTBM_COMP0_SET__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_SET__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_SET__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_SET__SIZE, 0x00000001 +.set CYREG_CTBM_INTR_MASK, 0x40100028 +.set CYFLD_CTBM_COMP0_MASK__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_MASK__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_MASK__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_MASK__SIZE, 0x00000001 +.set CYREG_CTBM_INTR_MASKED, 0x4010002c +.set CYFLD_CTBM_COMP0_MASKED__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_MASKED__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_MASKED__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_MASKED__SIZE, 0x00000001 +.set CYREG_CTBM_DFT_CTRL, 0x40100030 +.set CYFLD_CTBM_DFT_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_DFT_MODE__SIZE, 0x00000003 +.set CYFLD_CTBM_DFT_EN__OFFSET, 0x0000001f +.set CYFLD_CTBM_DFT_EN__SIZE, 0x00000001 +.set CYREG_CTBM_OA0_SW, 0x40100080 +.set CYFLD_CTBM_OA0P_A00__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0P_A00__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0P_A20__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA0P_A20__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0P_A30__OFFSET, 0x00000003 +.set CYFLD_CTBM_OA0P_A30__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0M_A11__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA0M_A11__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0M_A81__OFFSET, 0x0000000e +.set CYFLD_CTBM_OA0M_A81__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0O_D51__OFFSET, 0x00000012 +.set CYFLD_CTBM_OA0O_D51__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0O_D81__OFFSET, 0x00000015 +.set CYFLD_CTBM_OA0O_D81__SIZE, 0x00000001 +.set CYREG_CTBM_OA0_SW_CLEAR, 0x40100084 +.set CYREG_CTBM_OA1_SW, 0x40100088 +.set CYFLD_CTBM_OA1P_A03__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1P_A03__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1P_A13__OFFSET, 0x00000001 +.set CYFLD_CTBM_OA1P_A13__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1P_A43__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA1P_A43__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1M_A22__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA1M_A22__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1M_A82__OFFSET, 0x0000000e +.set CYFLD_CTBM_OA1M_A82__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D52__OFFSET, 0x00000012 +.set CYFLD_CTBM_OA1O_D52__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D62__OFFSET, 0x00000013 +.set CYFLD_CTBM_OA1O_D62__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D82__OFFSET, 0x00000015 +.set CYFLD_CTBM_OA1O_D82__SIZE, 0x00000001 +.set CYREG_CTBM_OA1_SW_CLEAR, 0x4010008c +.set CYREG_CTBM_CTB_SW_HW_CTRL, 0x401000c0 +.set CYFLD_CTBM_P2_HW_CTRL__OFFSET, 0x00000002 +.set CYFLD_CTBM_P2_HW_CTRL__SIZE, 0x00000001 +.set CYFLD_CTBM_P3_HW_CTRL__OFFSET, 0x00000003 +.set CYFLD_CTBM_P3_HW_CTRL__SIZE, 0x00000001 +.set CYREG_CTBM_CTB_SW_STATUS, 0x401000c4 +.set CYFLD_CTBM_OA0O_D51_STAT__OFFSET, 0x0000001c +.set CYFLD_CTBM_OA0O_D51_STAT__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D52_STAT__OFFSET, 0x0000001d +.set CYFLD_CTBM_OA1O_D52_STAT__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D62_STAT__OFFSET, 0x0000001e +.set CYFLD_CTBM_OA1O_D62_STAT__SIZE, 0x00000001 +.set CYREG_CTBM_OA0_OFFSET_TRIM, 0x40100f00 +.set CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM, 0x40100f04 +.set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA0_COMP_TRIM, 0x40100f08 +.set CYFLD_CTBM_OA0_COMP_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_COMP_TRIM__SIZE, 0x00000002 +.set CYREG_CTBM_OA1_OFFSET_TRIM, 0x40100f0c +.set CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM, 0x40100f10 +.set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA1_COMP_TRIM, 0x40100f14 +.set CYFLD_CTBM_OA1_COMP_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_COMP_TRIM__SIZE, 0x00000002 +.set CYDEV_SAR_BASE, 0x401a0000 +.set CYDEV_SAR_SIZE, 0x00010000 +.set CYREG_SAR_CTRL, 0x401a0000 +.set CYFLD_SAR_VREF_SEL__OFFSET, 0x00000004 +.set CYFLD_SAR_VREF_SEL__SIZE, 0x00000003 +.set CYVAL_SAR_VREF_SEL_VREF0, 0x00000000 +.set CYVAL_SAR_VREF_SEL_VREF1, 0x00000001 +.set CYVAL_SAR_VREF_SEL_VREF2, 0x00000002 +.set CYVAL_SAR_VREF_SEL_VREF_AROUTE, 0x00000003 +.set CYVAL_SAR_VREF_SEL_VBGR, 0x00000004 +.set CYVAL_SAR_VREF_SEL_VREF_EXT, 0x00000005 +.set CYVAL_SAR_VREF_SEL_VDDA_DIV_2, 0x00000006 +.set CYVAL_SAR_VREF_SEL_VDDA, 0x00000007 +.set CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET, 0x00000007 +.set CYFLD_SAR_VREF_BYP_CAP_EN__SIZE, 0x00000001 +.set CYFLD_SAR_NEG_SEL__OFFSET, 0x00000009 +.set CYFLD_SAR_NEG_SEL__SIZE, 0x00000003 +.set CYVAL_SAR_NEG_SEL_VSSA_KELVIN, 0x00000000 +.set CYVAL_SAR_NEG_SEL_ART_VSSA, 0x00000001 +.set CYVAL_SAR_NEG_SEL_P1, 0x00000002 +.set CYVAL_SAR_NEG_SEL_P3, 0x00000003 +.set CYVAL_SAR_NEG_SEL_P5, 0x00000004 +.set CYVAL_SAR_NEG_SEL_P7, 0x00000005 +.set CYVAL_SAR_NEG_SEL_ACORE, 0x00000006 +.set CYVAL_SAR_NEG_SEL_VREF, 0x00000007 +.set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET, 0x0000000d +.set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE, 0x00000001 +.set CYFLD_SAR_PWR_CTRL_VREF__OFFSET, 0x0000000e +.set CYFLD_SAR_PWR_CTRL_VREF__SIZE, 0x00000002 +.set CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR, 0x00000000 +.set CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR, 0x00000001 +.set CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR, 0x00000002 +.set CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR, 0x00000003 +.set CYFLD_SAR_SPARE__OFFSET, 0x00000010 +.set CYFLD_SAR_SPARE__SIZE, 0x00000004 +.set CYFLD_SAR_ICONT_LV__OFFSET, 0x00000018 +.set CYFLD_SAR_ICONT_LV__SIZE, 0x00000002 +.set CYVAL_SAR_ICONT_LV_NORMAL_PWR, 0x00000000 +.set CYVAL_SAR_ICONT_LV_HALF_PWR, 0x00000001 +.set CYVAL_SAR_ICONT_LV_MORE_PWR, 0x00000002 +.set CYVAL_SAR_ICONT_LV_QUARTER_PWR, 0x00000003 +.set CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET, 0x0000001c +.set CYFLD_SAR_DSI_SYNC_CONFIG__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_MODE__OFFSET, 0x0000001d +.set CYFLD_SAR_DSI_MODE__SIZE, 0x00000001 +.set CYFLD_SAR_SWITCH_DISABLE__OFFSET, 0x0000001e +.set CYFLD_SAR_SWITCH_DISABLE__SIZE, 0x00000001 +.set CYFLD_SAR_ENABLED__OFFSET, 0x0000001f +.set CYFLD_SAR_ENABLED__SIZE, 0x00000001 +.set CYREG_SAR_SAMPLE_CTRL, 0x401a0004 +.set CYFLD_SAR_SUB_RESOLUTION__OFFSET, 0x00000000 +.set CYFLD_SAR_SUB_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_SUB_RESOLUTION_8B, 0x00000000 +.set CYVAL_SAR_SUB_RESOLUTION_10B, 0x00000001 +.set CYFLD_SAR_LEFT_ALIGN__OFFSET, 0x00000001 +.set CYFLD_SAR_LEFT_ALIGN__SIZE, 0x00000001 +.set CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET, 0x00000002 +.set CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE, 0x00000001 +.set CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED, 0x00000000 +.set CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED, 0x00000001 +.set CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET, 0x00000003 +.set CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE, 0x00000001 +.set CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED, 0x00000000 +.set CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED, 0x00000001 +.set CYFLD_SAR_AVG_CNT__OFFSET, 0x00000004 +.set CYFLD_SAR_AVG_CNT__SIZE, 0x00000003 +.set CYFLD_SAR_AVG_SHIFT__OFFSET, 0x00000007 +.set CYFLD_SAR_AVG_SHIFT__SIZE, 0x00000001 +.set CYFLD_SAR_CONTINUOUS__OFFSET, 0x00000010 +.set CYFLD_SAR_CONTINUOUS__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_TRIGGER_EN__OFFSET, 0x00000011 +.set CYFLD_SAR_DSI_TRIGGER_EN__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET, 0x00000012 +.set CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET, 0x00000013 +.set CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE, 0x00000001 +.set CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_EOS_DSI_OUT_EN__SIZE, 0x00000001 +.set CYREG_SAR_SAMPLE_TIME01, 0x401a0010 +.set CYFLD_SAR_SAMPLE_TIME0__OFFSET, 0x00000000 +.set CYFLD_SAR_SAMPLE_TIME0__SIZE, 0x0000000a +.set CYFLD_SAR_SAMPLE_TIME1__OFFSET, 0x00000010 +.set CYFLD_SAR_SAMPLE_TIME1__SIZE, 0x0000000a +.set CYREG_SAR_SAMPLE_TIME23, 0x401a0014 +.set CYFLD_SAR_SAMPLE_TIME2__OFFSET, 0x00000000 +.set CYFLD_SAR_SAMPLE_TIME2__SIZE, 0x0000000a +.set CYFLD_SAR_SAMPLE_TIME3__OFFSET, 0x00000010 +.set CYFLD_SAR_SAMPLE_TIME3__SIZE, 0x0000000a +.set CYREG_SAR_RANGE_THRES, 0x401a0018 +.set CYFLD_SAR_RANGE_LOW__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_LOW__SIZE, 0x00000010 +.set CYFLD_SAR_RANGE_HIGH__OFFSET, 0x00000010 +.set CYFLD_SAR_RANGE_HIGH__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_COND, 0x401a001c +.set CYFLD_SAR_RANGE_COND__OFFSET, 0x0000001e +.set CYFLD_SAR_RANGE_COND__SIZE, 0x00000002 +.set CYVAL_SAR_RANGE_COND_BELOW, 0x00000000 +.set CYVAL_SAR_RANGE_COND_INSIDE, 0x00000001 +.set CYVAL_SAR_RANGE_COND_ABOVE, 0x00000002 +.set CYVAL_SAR_RANGE_COND_OUTSIDE, 0x00000003 +.set CYREG_SAR_CHAN_EN, 0x401a0020 +.set CYFLD_SAR_CHAN_EN__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_EN__SIZE, 0x00000010 +.set CYREG_SAR_START_CTRL, 0x401a0024 +.set CYFLD_SAR_FW_TRIGGER__OFFSET, 0x00000000 +.set CYFLD_SAR_FW_TRIGGER__SIZE, 0x00000001 +.set CYREG_SAR_DFT_CTRL, 0x401a0030 +.set CYFLD_SAR_DLY_INC__OFFSET, 0x00000000 +.set CYFLD_SAR_DLY_INC__SIZE, 0x00000001 +.set CYFLD_SAR_HIZ__OFFSET, 0x00000001 +.set CYFLD_SAR_HIZ__SIZE, 0x00000001 +.set CYFLD_SAR_DFT_INC__OFFSET, 0x00000010 +.set CYFLD_SAR_DFT_INC__SIZE, 0x00000004 +.set CYFLD_SAR_DFT_OUTC__OFFSET, 0x00000014 +.set CYFLD_SAR_DFT_OUTC__SIZE, 0x00000003 +.set CYFLD_SAR_SEL_CSEL_DFT__OFFSET, 0x00000018 +.set CYFLD_SAR_SEL_CSEL_DFT__SIZE, 0x00000004 +.set CYFLD_SAR_EN_CSEL_DFT__OFFSET, 0x0000001c +.set CYFLD_SAR_EN_CSEL_DFT__SIZE, 0x00000001 +.set CYFLD_SAR_DCEN__OFFSET, 0x0000001d +.set CYFLD_SAR_DCEN__SIZE, 0x00000001 +.set CYFLD_SAR_ADFT_OVERRIDE__OFFSET, 0x0000001f +.set CYFLD_SAR_ADFT_OVERRIDE__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_CONFIG00, 0x401a0080 +.set CYFLD_SAR_PIN_ADDR__OFFSET, 0x00000000 +.set CYFLD_SAR_PIN_ADDR__SIZE, 0x00000003 +.set CYFLD_SAR_PORT_ADDR__OFFSET, 0x00000004 +.set CYFLD_SAR_PORT_ADDR__SIZE, 0x00000003 +.set CYVAL_SAR_PORT_ADDR_SARMUX, 0x00000000 +.set CYVAL_SAR_PORT_ADDR_CTB0, 0x00000001 +.set CYVAL_SAR_PORT_ADDR_CTB1, 0x00000002 +.set CYVAL_SAR_PORT_ADDR_CTB2, 0x00000003 +.set CYVAL_SAR_PORT_ADDR_CTB3, 0x00000004 +.set CYVAL_SAR_PORT_ADDR_AROUTE_VIRT, 0x00000006 +.set CYVAL_SAR_PORT_ADDR_SARMUX_VIRT, 0x00000007 +.set CYFLD_SAR_DIFFERENTIAL_EN__OFFSET, 0x00000008 +.set CYFLD_SAR_DIFFERENTIAL_EN__SIZE, 0x00000001 +.set CYFLD_SAR_RESOLUTION__OFFSET, 0x00000009 +.set CYFLD_SAR_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_RESOLUTION_12B, 0x00000000 +.set CYVAL_SAR_RESOLUTION_SUBRES, 0x00000001 +.set CYFLD_SAR_AVG_EN__OFFSET, 0x0000000a +.set CYFLD_SAR_AVG_EN__SIZE, 0x00000001 +.set CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET, 0x0000000c +.set CYFLD_SAR_SAMPLE_TIME_SEL__SIZE, 0x00000002 +.set CYFLD_SAR_DSI_OUT_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_DSI_OUT_EN__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_CONFIG01, 0x401a0084 +.set CYREG_SAR_CHAN_CONFIG02, 0x401a0088 +.set CYREG_SAR_CHAN_CONFIG03, 0x401a008c +.set CYREG_SAR_CHAN_CONFIG04, 0x401a0090 +.set CYREG_SAR_CHAN_CONFIG05, 0x401a0094 +.set CYREG_SAR_CHAN_CONFIG06, 0x401a0098 +.set CYREG_SAR_CHAN_CONFIG07, 0x401a009c +.set CYREG_SAR_CHAN_WORK00, 0x401a0100 +.set CYFLD_SAR_WORK__OFFSET, 0x00000000 +.set CYFLD_SAR_WORK__SIZE, 0x00000010 +.set CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_WORK01, 0x401a0104 +.set CYREG_SAR_CHAN_WORK02, 0x401a0108 +.set CYREG_SAR_CHAN_WORK03, 0x401a010c +.set CYREG_SAR_CHAN_WORK04, 0x401a0110 +.set CYREG_SAR_CHAN_WORK05, 0x401a0114 +.set CYREG_SAR_CHAN_WORK06, 0x401a0118 +.set CYREG_SAR_CHAN_WORK07, 0x401a011c +.set CYREG_SAR_CHAN_RESULT00, 0x401a0180 +.set CYFLD_SAR_RESULT__OFFSET, 0x00000000 +.set CYFLD_SAR_RESULT__SIZE, 0x00000010 +.set CYFLD_SAR_SATURATE_INTR_MIR__OFFSET, 0x0000001d +.set CYFLD_SAR_SATURATE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_RANGE_INTR_MIR__OFFSET, 0x0000001e +.set CYFLD_SAR_RANGE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_RESULT01, 0x401a0184 +.set CYREG_SAR_CHAN_RESULT02, 0x401a0188 +.set CYREG_SAR_CHAN_RESULT03, 0x401a018c +.set CYREG_SAR_CHAN_RESULT04, 0x401a0190 +.set CYREG_SAR_CHAN_RESULT05, 0x401a0194 +.set CYREG_SAR_CHAN_RESULT06, 0x401a0198 +.set CYREG_SAR_CHAN_RESULT07, 0x401a019c +.set CYREG_SAR_CHAN_WORK_VALID, 0x401a0200 +.set CYFLD_SAR_CHAN_WORK_VALID__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_WORK_VALID__SIZE, 0x00000010 +.set CYREG_SAR_CHAN_RESULT_VALID, 0x401a0204 +.set CYFLD_SAR_CHAN_RESULT_VALID__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_RESULT_VALID__SIZE, 0x00000010 +.set CYREG_SAR_STATUS, 0x401a0208 +.set CYFLD_SAR_CUR_CHAN__OFFSET, 0x00000000 +.set CYFLD_SAR_CUR_CHAN__SIZE, 0x00000005 +.set CYFLD_SAR_SW_VREF_NEG__OFFSET, 0x0000001e +.set CYFLD_SAR_SW_VREF_NEG__SIZE, 0x00000001 +.set CYFLD_SAR_BUSY__OFFSET, 0x0000001f +.set CYFLD_SAR_BUSY__SIZE, 0x00000001 +.set CYREG_SAR_AVG_STAT, 0x401a020c +.set CYFLD_SAR_CUR_AVG_ACCU__OFFSET, 0x00000000 +.set CYFLD_SAR_CUR_AVG_ACCU__SIZE, 0x00000014 +.set CYFLD_SAR_CUR_AVG_CNT__OFFSET, 0x00000018 +.set CYFLD_SAR_CUR_AVG_CNT__SIZE, 0x00000008 +.set CYREG_SAR_INTR, 0x401a0210 +.set CYFLD_SAR_EOS_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_INTR__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_INTR__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_INTR__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_INTR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_INTR__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_INTR__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_INTR__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_INTR__SIZE, 0x00000001 +.set CYREG_SAR_INTR_SET, 0x401a0214 +.set CYFLD_SAR_EOS_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_SET__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_SET__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_SET__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_SET__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_SET__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_SET__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_SET__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_SET__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_SET__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_SET__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_SET__SIZE, 0x00000001 +.set CYREG_SAR_INTR_MASK, 0x401a0218 +.set CYFLD_SAR_EOS_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASK__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASK__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASK__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASK__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASK__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASK__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASK__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASK__SIZE, 0x00000001 +.set CYREG_SAR_INTR_MASKED, 0x401a021c +.set CYFLD_SAR_EOS_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASKED__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASKED__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASKED__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASKED__SIZE, 0x00000001 +.set CYREG_SAR_SATURATE_INTR, 0x401a0220 +.set CYFLD_SAR_SATURATE_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_INTR__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_SET, 0x401a0224 +.set CYFLD_SAR_SATURATE_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_SET__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_MASK, 0x401a0228 +.set CYFLD_SAR_SATURATE_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_MASK__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_MASKED, 0x401a022c +.set CYFLD_SAR_SATURATE_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_MASKED__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR, 0x401a0230 +.set CYFLD_SAR_RANGE_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_INTR__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_SET, 0x401a0234 +.set CYFLD_SAR_RANGE_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_SET__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_MASK, 0x401a0238 +.set CYFLD_SAR_RANGE_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_MASK__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_MASKED, 0x401a023c +.set CYFLD_SAR_RANGE_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_MASKED__SIZE, 0x00000010 +.set CYREG_SAR_INTR_CAUSE, 0x401a0240 +.set CYFLD_SAR_EOS_MASKED_MIR__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_SATURATE_MASKED_RED__OFFSET, 0x0000001e +.set CYFLD_SAR_SATURATE_MASKED_RED__SIZE, 0x00000001 +.set CYFLD_SAR_RANGE_MASKED_RED__OFFSET, 0x0000001f +.set CYFLD_SAR_RANGE_MASKED_RED__SIZE, 0x00000001 +.set CYREG_SAR_INJ_CHAN_CONFIG, 0x401a0280 +.set CYFLD_SAR_INJ_PIN_ADDR__OFFSET, 0x00000000 +.set CYFLD_SAR_INJ_PIN_ADDR__SIZE, 0x00000003 +.set CYFLD_SAR_INJ_PORT_ADDR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_PORT_ADDR__SIZE, 0x00000003 +.set CYVAL_SAR_INJ_PORT_ADDR_SARMUX, 0x00000000 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB0, 0x00000001 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB1, 0x00000002 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB2, 0x00000003 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB3, 0x00000004 +.set CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT, 0x00000006 +.set CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT, 0x00000007 +.set CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET, 0x00000008 +.set CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RESOLUTION__OFFSET, 0x00000009 +.set CYFLD_SAR_INJ_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_INJ_RESOLUTION_12B, 0x00000000 +.set CYVAL_SAR_INJ_RESOLUTION_SUBRES, 0x00000001 +.set CYFLD_SAR_INJ_AVG_EN__OFFSET, 0x0000000a +.set CYFLD_SAR_INJ_AVG_EN__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET, 0x0000000c +.set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE, 0x00000002 +.set CYFLD_SAR_INJ_TAILGATING__OFFSET, 0x0000001e +.set CYFLD_SAR_INJ_TAILGATING__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_START_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_INJ_START_EN__SIZE, 0x00000001 +.set CYREG_SAR_INJ_RESULT, 0x401a0290 +.set CYFLD_SAR_INJ_RESULT__OFFSET, 0x00000000 +.set CYFLD_SAR_INJ_RESULT__SIZE, 0x00000010 +.set CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET, 0x0000001c +.set CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET, 0x0000001d +.set CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET, 0x0000001e +.set CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH0, 0x401a0300 +.set CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET, 0x00000004 +.set CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET, 0x00000005 +.set CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET, 0x00000006 +.set CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET, 0x00000007 +.set CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET, 0x00000008 +.set CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET, 0x00000009 +.set CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET, 0x0000000a +.set CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET, 0x0000000b +.set CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET, 0x0000000c +.set CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET, 0x0000000d +.set CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET, 0x0000000e +.set CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET, 0x0000000f +.set CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET, 0x00000010 +.set CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET, 0x00000011 +.set CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET, 0x00000012 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET, 0x00000013 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET, 0x00000014 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET, 0x00000015 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET, 0x00000016 +.set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET, 0x00000017 +.set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET, 0x00000018 +.set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET, 0x00000019 +.set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET, 0x0000001a +.set CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET, 0x0000001b +.set CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET, 0x0000001c +.set CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET, 0x0000001d +.set CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_CLEAR0, 0x401a0304 +.set CYREG_SAR_MUX_SWITCH1, 0x401a0308 +.set CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_CLEAR1, 0x401a030c +.set CYREG_SAR_MUX_SWITCH_HW_CTRL, 0x401a0340 +.set CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_HW_CTRL_P0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P1__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_HW_CTRL_P2__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_HW_CTRL_P3__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET, 0x00000004 +.set CYFLD_SAR_MUX_HW_CTRL_P4__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET, 0x00000005 +.set CYFLD_SAR_MUX_HW_CTRL_P5__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET, 0x00000006 +.set CYFLD_SAR_MUX_HW_CTRL_P6__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET, 0x00000007 +.set CYFLD_SAR_MUX_HW_CTRL_P7__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET, 0x00000010 +.set CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET, 0x00000011 +.set CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET, 0x00000012 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET, 0x00000013 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET, 0x00000016 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET, 0x00000017 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_STATUS, 0x401a0348 +.set CYREG_SAR_PUMP_CTRL, 0x401a0380 +.set CYFLD_SAR_CLOCK_SEL__OFFSET, 0x00000000 +.set CYFLD_SAR_CLOCK_SEL__SIZE, 0x00000001 +.set CYREG_SAR_ANA_TRIM, 0x401a0f00 +.set CYFLD_SAR_CAP_TRIM__OFFSET, 0x00000000 +.set CYFLD_SAR_CAP_TRIM__SIZE, 0x00000003 +.set CYFLD_SAR_TRIMUNIT__OFFSET, 0x00000003 +.set CYFLD_SAR_TRIMUNIT__SIZE, 0x00000001 +.set CYREG_SAR_WOUNDING, 0x401a0f04 +.set CYFLD_SAR_WOUND_RESOLUTION__OFFSET, 0x00000000 +.set CYFLD_SAR_WOUND_RESOLUTION__SIZE, 0x00000002 +.set CYVAL_SAR_WOUND_RESOLUTION_12BIT, 0x00000000 +.set CYVAL_SAR_WOUND_RESOLUTION_10BIT, 0x00000001 +.set CYVAL_SAR_WOUND_RESOLUTION_8BIT, 0x00000002 +.set CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO, 0x00000003 +.set CYDEV_CM0_BASE, 0xe0000000 +.set CYDEV_CM0_SIZE, 0x00100000 +.set CYREG_CM0_DWT_PID4, 0xe0001fd0 +.set CYFLD_CM0_VALUE__OFFSET, 0x00000000 +.set CYFLD_CM0_VALUE__SIZE, 0x00000020 +.set CYREG_CM0_DWT_PID0, 0xe0001fe0 +.set CYREG_CM0_DWT_PID1, 0xe0001fe4 +.set CYREG_CM0_DWT_PID2, 0xe0001fe8 +.set CYREG_CM0_DWT_PID3, 0xe0001fec +.set CYREG_CM0_DWT_CID0, 0xe0001ff0 +.set CYREG_CM0_DWT_CID1, 0xe0001ff4 +.set CYREG_CM0_DWT_CID2, 0xe0001ff8 +.set CYREG_CM0_DWT_CID3, 0xe0001ffc +.set CYREG_CM0_BP_PID4, 0xe0002fd0 +.set CYREG_CM0_BP_PID0, 0xe0002fe0 +.set CYREG_CM0_BP_PID1, 0xe0002fe4 +.set CYREG_CM0_BP_PID2, 0xe0002fe8 +.set CYREG_CM0_BP_PID3, 0xe0002fec +.set CYREG_CM0_BP_CID0, 0xe0002ff0 +.set CYREG_CM0_BP_CID1, 0xe0002ff4 +.set CYREG_CM0_BP_CID2, 0xe0002ff8 +.set CYREG_CM0_BP_CID3, 0xe0002ffc +.set CYREG_CM0_SYST_CSR, 0xe000e010 +.set CYFLD_CM0_ENABLE__OFFSET, 0x00000000 +.set CYFLD_CM0_ENABLE__SIZE, 0x00000001 +.set CYFLD_CM0_TICKINT__OFFSET, 0x00000001 +.set CYFLD_CM0_TICKINT__SIZE, 0x00000001 +.set CYFLD_CM0_CLKSOURCE__OFFSET, 0x00000002 +.set CYFLD_CM0_CLKSOURCE__SIZE, 0x00000001 +.set CYFLD_CM0_COUNTFLAG__OFFSET, 0x00000010 +.set CYFLD_CM0_COUNTFLAG__SIZE, 0x00000001 +.set CYREG_CM0_SYST_RVR, 0xe000e014 +.set CYFLD_CM0_RELOAD__OFFSET, 0x00000000 +.set CYFLD_CM0_RELOAD__SIZE, 0x00000018 +.set CYREG_CM0_SYST_CVR, 0xe000e018 +.set CYFLD_CM0_CURRENT__OFFSET, 0x00000000 +.set CYFLD_CM0_CURRENT__SIZE, 0x00000018 +.set CYREG_CM0_SYST_CALIB, 0xe000e01c +.set CYFLD_CM0_TENMS__OFFSET, 0x00000000 +.set CYFLD_CM0_TENMS__SIZE, 0x00000018 +.set CYFLD_CM0_SKEW__OFFSET, 0x0000001e +.set CYFLD_CM0_SKEW__SIZE, 0x00000001 +.set CYFLD_CM0_NOREF__OFFSET, 0x0000001f +.set CYFLD_CM0_NOREF__SIZE, 0x00000001 +.set CYREG_CM0_ISER, 0xe000e100 +.set CYFLD_CM0_SETENA__OFFSET, 0x00000000 +.set CYFLD_CM0_SETENA__SIZE, 0x00000020 +.set CYREG_CM0_ICER, 0xe000e180 +.set CYFLD_CM0_CLRENA__OFFSET, 0x00000000 +.set CYFLD_CM0_CLRENA__SIZE, 0x00000020 +.set CYREG_CM0_ISPR, 0xe000e200 +.set CYFLD_CM0_SETPEND__OFFSET, 0x00000000 +.set CYFLD_CM0_SETPEND__SIZE, 0x00000020 +.set CYREG_CM0_ICPR, 0xe000e280 +.set CYFLD_CM0_CLRPEND__OFFSET, 0x00000000 +.set CYFLD_CM0_CLRPEND__SIZE, 0x00000020 +.set CYREG_CM0_IPR0, 0xe000e400 +.set CYFLD_CM0_PRI_N0__OFFSET, 0x00000006 +.set CYFLD_CM0_PRI_N0__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_N1__OFFSET, 0x0000000e +.set CYFLD_CM0_PRI_N1__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_N2__OFFSET, 0x00000016 +.set CYFLD_CM0_PRI_N2__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_N3__OFFSET, 0x0000001e +.set CYFLD_CM0_PRI_N3__SIZE, 0x00000002 +.set CYREG_CM0_IPR1, 0xe000e404 +.set CYREG_CM0_IPR2, 0xe000e408 +.set CYREG_CM0_IPR3, 0xe000e40c +.set CYREG_CM0_IPR4, 0xe000e410 +.set CYREG_CM0_IPR5, 0xe000e414 +.set CYREG_CM0_IPR6, 0xe000e418 +.set CYREG_CM0_IPR7, 0xe000e41c +.set CYREG_CM0_CPUID, 0xe000ed00 +.set CYFLD_CM0_REVISION__OFFSET, 0x00000000 +.set CYFLD_CM0_REVISION__SIZE, 0x00000004 +.set CYFLD_CM0_PARTNO__OFFSET, 0x00000004 +.set CYFLD_CM0_PARTNO__SIZE, 0x0000000c +.set CYFLD_CM0_CONSTANT__OFFSET, 0x00000010 +.set CYFLD_CM0_CONSTANT__SIZE, 0x00000004 +.set CYFLD_CM0_VARIANT__OFFSET, 0x00000014 +.set CYFLD_CM0_VARIANT__SIZE, 0x00000004 +.set CYFLD_CM0_IMPLEMENTER__OFFSET, 0x00000018 +.set CYFLD_CM0_IMPLEMENTER__SIZE, 0x00000008 +.set CYREG_CM0_ICSR, 0xe000ed04 +.set CYFLD_CM0_VECTACTIVE__OFFSET, 0x00000000 +.set CYFLD_CM0_VECTACTIVE__SIZE, 0x00000009 +.set CYFLD_CM0_VECTPENDING__OFFSET, 0x0000000c +.set CYFLD_CM0_VECTPENDING__SIZE, 0x00000009 +.set CYFLD_CM0_ISRPENDING__OFFSET, 0x00000016 +.set CYFLD_CM0_ISRPENDING__SIZE, 0x00000001 +.set CYFLD_CM0_ISRPREEMPT__OFFSET, 0x00000017 +.set CYFLD_CM0_ISRPREEMPT__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSTCLR__OFFSET, 0x00000019 +.set CYFLD_CM0_PENDSTCLR__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSTSETb__OFFSET, 0x0000001a +.set CYFLD_CM0_PENDSTSETb__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSVCLR__OFFSET, 0x0000001b +.set CYFLD_CM0_PENDSVCLR__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSVSET__OFFSET, 0x0000001c +.set CYFLD_CM0_PENDSVSET__SIZE, 0x00000001 +.set CYFLD_CM0_NMIPENDSET__OFFSET, 0x0000001f +.set CYFLD_CM0_NMIPENDSET__SIZE, 0x00000001 +.set CYREG_CM0_AIRCR, 0xe000ed0c +.set CYFLD_CM0_VECTCLRACTIVE__OFFSET, 0x00000001 +.set CYFLD_CM0_VECTCLRACTIVE__SIZE, 0x00000001 +.set CYFLD_CM0_SYSRESETREQ__OFFSET, 0x00000002 +.set CYFLD_CM0_SYSRESETREQ__SIZE, 0x00000001 +.set CYFLD_CM0_ENDIANNESS__OFFSET, 0x0000000f +.set CYFLD_CM0_ENDIANNESS__SIZE, 0x00000001 +.set CYFLD_CM0_VECTKEY__OFFSET, 0x00000010 +.set CYFLD_CM0_VECTKEY__SIZE, 0x00000010 +.set CYREG_CM0_SCR, 0xe000ed10 +.set CYFLD_CM0_SLEEPONEXIT__OFFSET, 0x00000001 +.set CYFLD_CM0_SLEEPONEXIT__SIZE, 0x00000001 +.set CYFLD_CM0_SLEEPDEEP__OFFSET, 0x00000002 +.set CYFLD_CM0_SLEEPDEEP__SIZE, 0x00000001 +.set CYFLD_CM0_SEVONPEND__OFFSET, 0x00000004 +.set CYFLD_CM0_SEVONPEND__SIZE, 0x00000001 +.set CYREG_CM0_CCR, 0xe000ed14 +.set CYFLD_CM0_UNALIGN_TRP__OFFSET, 0x00000003 +.set CYFLD_CM0_UNALIGN_TRP__SIZE, 0x00000001 +.set CYFLD_CM0_STKALIGN__OFFSET, 0x00000009 +.set CYFLD_CM0_STKALIGN__SIZE, 0x00000001 +.set CYREG_CM0_SHPR2, 0xe000ed1c +.set CYFLD_CM0_PRI_11__OFFSET, 0x0000001e +.set CYFLD_CM0_PRI_11__SIZE, 0x00000002 +.set CYREG_CM0_SHPR3, 0xe000ed20 +.set CYFLD_CM0_PRI_14__OFFSET, 0x00000016 +.set CYFLD_CM0_PRI_14__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_15__OFFSET, 0x0000001e +.set CYFLD_CM0_PRI_15__SIZE, 0x00000002 +.set CYREG_CM0_SHCSR, 0xe000ed24 +.set CYFLD_CM0_SVCALLPENDED__OFFSET, 0x0000000f +.set CYFLD_CM0_SVCALLPENDED__SIZE, 0x00000001 +.set CYREG_CM0_SCS_PID4, 0xe000efd0 +.set CYREG_CM0_SCS_PID0, 0xe000efe0 +.set CYREG_CM0_SCS_PID1, 0xe000efe4 +.set CYREG_CM0_SCS_PID2, 0xe000efe8 +.set CYREG_CM0_SCS_PID3, 0xe000efec +.set CYREG_CM0_SCS_CID0, 0xe000eff0 +.set CYREG_CM0_SCS_CID1, 0xe000eff4 +.set CYREG_CM0_SCS_CID2, 0xe000eff8 +.set CYREG_CM0_SCS_CID3, 0xe000effc +.set CYREG_CM0_ROM_SCS, 0xe00ff000 +.set CYREG_CM0_ROM_DWT, 0xe00ff004 +.set CYREG_CM0_ROM_BPU, 0xe00ff008 +.set CYREG_CM0_ROM_END, 0xe00ff00c +.set CYREG_CM0_ROM_CSMT, 0xe00fffcc +.set CYREG_CM0_ROM_PID4, 0xe00fffd0 +.set CYREG_CM0_ROM_PID0, 0xe00fffe0 +.set CYREG_CM0_ROM_PID1, 0xe00fffe4 +.set CYREG_CM0_ROM_PID2, 0xe00fffe8 +.set CYREG_CM0_ROM_PID3, 0xe00fffec +.set CYREG_CM0_ROM_CID0, 0xe00ffff0 +.set CYREG_CM0_ROM_CID1, 0xe00ffff4 +.set CYREG_CM0_ROM_CID2, 0xe00ffff8 +.set CYREG_CM0_ROM_CID3, 0xe00ffffc +.set CYDEV_CoreSightTable_BASE, 0xf0000000 +.set CYDEV_CoreSightTable_SIZE, 0x00001000 +.set CYREG_CoreSightTable_DATA_MBASE, 0xf0000000 +.set CYREG_CoreSightTable_DATA_MSIZE, 0x00001000 +.set CYDEV_FLS_SECTOR_SIZE, 0x00008000 +.set CYDEV_FLS_ROW_SIZE, 0x00000080 diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydeviceiar_trm.inc b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydeviceiar_trm.inc new file mode 100644 index 0000000..e4eb849 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydeviceiar_trm.inc @@ -0,0 +1,6493 @@ +; +; File Name: cydeviceiar_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00008000 +#define CYREG_FLASH_DATA_MBASE 0x00000000 +#define CYREG_FLASH_DATA_MSIZE 0x00008000 +#define CYDEV_SFLASH_BASE 0x0ffff000 +#define CYDEV_SFLASH_SIZE 0x00000200 +#define CYREG_SFLASH_PROT_ROW00 0x0ffff000 +#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000 +#define CYFLD_SFLASH_DATA8__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_ROW01 0x0ffff001 +#define CYREG_SFLASH_PROT_ROW02 0x0ffff002 +#define CYREG_SFLASH_PROT_ROW03 0x0ffff003 +#define CYREG_SFLASH_PROT_ROW04 0x0ffff004 +#define CYREG_SFLASH_PROT_ROW05 0x0ffff005 +#define CYREG_SFLASH_PROT_ROW06 0x0ffff006 +#define CYREG_SFLASH_PROT_ROW07 0x0ffff007 +#define CYREG_SFLASH_PROT_ROW08 0x0ffff008 +#define CYREG_SFLASH_PROT_ROW09 0x0ffff009 +#define CYREG_SFLASH_PROT_ROW10 0x0ffff00a +#define CYREG_SFLASH_PROT_ROW11 0x0ffff00b +#define CYREG_SFLASH_PROT_ROW12 0x0ffff00c +#define CYREG_SFLASH_PROT_ROW13 0x0ffff00d +#define CYREG_SFLASH_PROT_ROW14 0x0ffff00e +#define CYREG_SFLASH_PROT_ROW15 0x0ffff00f +#define CYREG_SFLASH_PROT_ROW16 0x0ffff010 +#define CYREG_SFLASH_PROT_ROW17 0x0ffff011 +#define CYREG_SFLASH_PROT_ROW18 0x0ffff012 +#define CYREG_SFLASH_PROT_ROW19 0x0ffff013 +#define CYREG_SFLASH_PROT_ROW20 0x0ffff014 +#define CYREG_SFLASH_PROT_ROW21 0x0ffff015 +#define CYREG_SFLASH_PROT_ROW22 0x0ffff016 +#define CYREG_SFLASH_PROT_ROW23 0x0ffff017 +#define CYREG_SFLASH_PROT_ROW24 0x0ffff018 +#define CYREG_SFLASH_PROT_ROW25 0x0ffff019 +#define CYREG_SFLASH_PROT_ROW26 0x0ffff01a +#define CYREG_SFLASH_PROT_ROW27 0x0ffff01b +#define CYREG_SFLASH_PROT_ROW28 0x0ffff01c +#define CYREG_SFLASH_PROT_ROW29 0x0ffff01d +#define CYREG_SFLASH_PROT_ROW30 0x0ffff01e +#define CYREG_SFLASH_PROT_ROW31 0x0ffff01f +#define CYREG_SFLASH_PROT_ROW32 0x0ffff020 +#define CYREG_SFLASH_PROT_ROW33 0x0ffff021 +#define CYREG_SFLASH_PROT_ROW34 0x0ffff022 +#define CYREG_SFLASH_PROT_ROW35 0x0ffff023 +#define CYREG_SFLASH_PROT_ROW36 0x0ffff024 +#define CYREG_SFLASH_PROT_ROW37 0x0ffff025 +#define CYREG_SFLASH_PROT_ROW38 0x0ffff026 +#define CYREG_SFLASH_PROT_ROW39 0x0ffff027 +#define CYREG_SFLASH_PROT_ROW40 0x0ffff028 +#define CYREG_SFLASH_PROT_ROW41 0x0ffff029 +#define CYREG_SFLASH_PROT_ROW42 0x0ffff02a +#define CYREG_SFLASH_PROT_ROW43 0x0ffff02b +#define CYREG_SFLASH_PROT_ROW44 0x0ffff02c +#define CYREG_SFLASH_PROT_ROW45 0x0ffff02d +#define CYREG_SFLASH_PROT_ROW46 0x0ffff02e +#define CYREG_SFLASH_PROT_ROW47 0x0ffff02f +#define CYREG_SFLASH_PROT_ROW48 0x0ffff030 +#define CYREG_SFLASH_PROT_ROW49 0x0ffff031 +#define CYREG_SFLASH_PROT_ROW50 0x0ffff032 +#define CYREG_SFLASH_PROT_ROW51 0x0ffff033 +#define CYREG_SFLASH_PROT_ROW52 0x0ffff034 +#define CYREG_SFLASH_PROT_ROW53 0x0ffff035 +#define CYREG_SFLASH_PROT_ROW54 0x0ffff036 +#define CYREG_SFLASH_PROT_ROW55 0x0ffff037 +#define CYREG_SFLASH_PROT_ROW56 0x0ffff038 +#define CYREG_SFLASH_PROT_ROW57 0x0ffff039 +#define CYREG_SFLASH_PROT_ROW58 0x0ffff03a +#define CYREG_SFLASH_PROT_ROW59 0x0ffff03b +#define CYREG_SFLASH_PROT_ROW60 0x0ffff03c +#define CYREG_SFLASH_PROT_ROW61 0x0ffff03d +#define CYREG_SFLASH_PROT_ROW62 0x0ffff03e +#define CYREG_SFLASH_PROT_ROW63 0x0ffff03f +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07f +#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000 +#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002 +#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001 +#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000 +#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002 +#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003 +#define CYREG_SFLASH_AV_PAIRS_8B000 0x0ffff080 +#define CYREG_SFLASH_AV_PAIRS_8B001 0x0ffff081 +#define CYREG_SFLASH_AV_PAIRS_8B002 0x0ffff082 +#define CYREG_SFLASH_AV_PAIRS_8B003 0x0ffff083 +#define CYREG_SFLASH_AV_PAIRS_8B004 0x0ffff084 +#define CYREG_SFLASH_AV_PAIRS_8B005 0x0ffff085 +#define CYREG_SFLASH_AV_PAIRS_8B006 0x0ffff086 +#define CYREG_SFLASH_AV_PAIRS_8B007 0x0ffff087 +#define CYREG_SFLASH_AV_PAIRS_8B008 0x0ffff088 +#define CYREG_SFLASH_AV_PAIRS_8B009 0x0ffff089 +#define CYREG_SFLASH_AV_PAIRS_8B010 0x0ffff08a +#define CYREG_SFLASH_AV_PAIRS_8B011 0x0ffff08b +#define CYREG_SFLASH_AV_PAIRS_8B012 0x0ffff08c +#define CYREG_SFLASH_AV_PAIRS_8B013 0x0ffff08d +#define CYREG_SFLASH_AV_PAIRS_8B014 0x0ffff08e +#define CYREG_SFLASH_AV_PAIRS_8B015 0x0ffff08f +#define CYREG_SFLASH_AV_PAIRS_8B016 0x0ffff090 +#define CYREG_SFLASH_AV_PAIRS_8B017 0x0ffff091 +#define CYREG_SFLASH_AV_PAIRS_8B018 0x0ffff092 +#define CYREG_SFLASH_AV_PAIRS_8B019 0x0ffff093 +#define CYREG_SFLASH_AV_PAIRS_8B020 0x0ffff094 +#define CYREG_SFLASH_AV_PAIRS_8B021 0x0ffff095 +#define CYREG_SFLASH_AV_PAIRS_8B022 0x0ffff096 +#define CYREG_SFLASH_AV_PAIRS_8B023 0x0ffff097 +#define CYREG_SFLASH_AV_PAIRS_8B024 0x0ffff098 +#define CYREG_SFLASH_AV_PAIRS_8B025 0x0ffff099 +#define CYREG_SFLASH_AV_PAIRS_8B026 0x0ffff09a +#define CYREG_SFLASH_AV_PAIRS_8B027 0x0ffff09b +#define CYREG_SFLASH_AV_PAIRS_8B028 0x0ffff09c +#define CYREG_SFLASH_AV_PAIRS_8B029 0x0ffff09d +#define CYREG_SFLASH_AV_PAIRS_8B030 0x0ffff09e +#define CYREG_SFLASH_AV_PAIRS_8B031 0x0ffff09f +#define CYREG_SFLASH_AV_PAIRS_8B032 0x0ffff0a0 +#define CYREG_SFLASH_AV_PAIRS_8B033 0x0ffff0a1 +#define CYREG_SFLASH_AV_PAIRS_8B034 0x0ffff0a2 +#define CYREG_SFLASH_AV_PAIRS_8B035 0x0ffff0a3 +#define CYREG_SFLASH_AV_PAIRS_8B036 0x0ffff0a4 +#define CYREG_SFLASH_AV_PAIRS_8B037 0x0ffff0a5 +#define CYREG_SFLASH_AV_PAIRS_8B038 0x0ffff0a6 +#define CYREG_SFLASH_AV_PAIRS_8B039 0x0ffff0a7 +#define CYREG_SFLASH_AV_PAIRS_8B040 0x0ffff0a8 +#define CYREG_SFLASH_AV_PAIRS_8B041 0x0ffff0a9 +#define CYREG_SFLASH_AV_PAIRS_8B042 0x0ffff0aa +#define CYREG_SFLASH_AV_PAIRS_8B043 0x0ffff0ab +#define CYREG_SFLASH_AV_PAIRS_8B044 0x0ffff0ac +#define CYREG_SFLASH_AV_PAIRS_8B045 0x0ffff0ad +#define CYREG_SFLASH_AV_PAIRS_8B046 0x0ffff0ae +#define CYREG_SFLASH_AV_PAIRS_8B047 0x0ffff0af +#define CYREG_SFLASH_AV_PAIRS_8B048 0x0ffff0b0 +#define CYREG_SFLASH_AV_PAIRS_8B049 0x0ffff0b1 +#define CYREG_SFLASH_AV_PAIRS_8B050 0x0ffff0b2 +#define CYREG_SFLASH_AV_PAIRS_8B051 0x0ffff0b3 +#define CYREG_SFLASH_AV_PAIRS_8B052 0x0ffff0b4 +#define CYREG_SFLASH_AV_PAIRS_8B053 0x0ffff0b5 +#define CYREG_SFLASH_AV_PAIRS_8B054 0x0ffff0b6 +#define CYREG_SFLASH_AV_PAIRS_8B055 0x0ffff0b7 +#define CYREG_SFLASH_AV_PAIRS_8B056 0x0ffff0b8 +#define CYREG_SFLASH_AV_PAIRS_8B057 0x0ffff0b9 +#define CYREG_SFLASH_AV_PAIRS_8B058 0x0ffff0ba +#define CYREG_SFLASH_AV_PAIRS_8B059 0x0ffff0bb +#define CYREG_SFLASH_AV_PAIRS_8B060 0x0ffff0bc +#define CYREG_SFLASH_AV_PAIRS_8B061 0x0ffff0bd +#define CYREG_SFLASH_AV_PAIRS_8B062 0x0ffff0be +#define CYREG_SFLASH_AV_PAIRS_8B063 0x0ffff0bf +#define CYREG_SFLASH_AV_PAIRS_8B064 0x0ffff0c0 +#define CYREG_SFLASH_AV_PAIRS_8B065 0x0ffff0c1 +#define CYREG_SFLASH_AV_PAIRS_8B066 0x0ffff0c2 +#define CYREG_SFLASH_AV_PAIRS_8B067 0x0ffff0c3 +#define CYREG_SFLASH_AV_PAIRS_8B068 0x0ffff0c4 +#define CYREG_SFLASH_AV_PAIRS_8B069 0x0ffff0c5 +#define CYREG_SFLASH_AV_PAIRS_8B070 0x0ffff0c6 +#define CYREG_SFLASH_AV_PAIRS_8B071 0x0ffff0c7 +#define CYREG_SFLASH_AV_PAIRS_8B072 0x0ffff0c8 +#define CYREG_SFLASH_AV_PAIRS_8B073 0x0ffff0c9 +#define CYREG_SFLASH_AV_PAIRS_8B074 0x0ffff0ca +#define CYREG_SFLASH_AV_PAIRS_8B075 0x0ffff0cb +#define CYREG_SFLASH_AV_PAIRS_8B076 0x0ffff0cc +#define CYREG_SFLASH_AV_PAIRS_8B077 0x0ffff0cd +#define CYREG_SFLASH_AV_PAIRS_8B078 0x0ffff0ce +#define CYREG_SFLASH_AV_PAIRS_8B079 0x0ffff0cf +#define CYREG_SFLASH_AV_PAIRS_8B080 0x0ffff0d0 +#define CYREG_SFLASH_AV_PAIRS_8B081 0x0ffff0d1 +#define CYREG_SFLASH_AV_PAIRS_8B082 0x0ffff0d2 +#define CYREG_SFLASH_AV_PAIRS_8B083 0x0ffff0d3 +#define CYREG_SFLASH_AV_PAIRS_8B084 0x0ffff0d4 +#define CYREG_SFLASH_AV_PAIRS_8B085 0x0ffff0d5 +#define CYREG_SFLASH_AV_PAIRS_8B086 0x0ffff0d6 +#define CYREG_SFLASH_AV_PAIRS_8B087 0x0ffff0d7 +#define CYREG_SFLASH_AV_PAIRS_8B088 0x0ffff0d8 +#define CYREG_SFLASH_AV_PAIRS_8B089 0x0ffff0d9 +#define CYREG_SFLASH_AV_PAIRS_8B090 0x0ffff0da +#define CYREG_SFLASH_AV_PAIRS_8B091 0x0ffff0db +#define CYREG_SFLASH_AV_PAIRS_8B092 0x0ffff0dc +#define CYREG_SFLASH_AV_PAIRS_8B093 0x0ffff0dd +#define CYREG_SFLASH_AV_PAIRS_8B094 0x0ffff0de +#define CYREG_SFLASH_AV_PAIRS_8B095 0x0ffff0df +#define CYREG_SFLASH_AV_PAIRS_8B096 0x0ffff0e0 +#define CYREG_SFLASH_AV_PAIRS_8B097 0x0ffff0e1 +#define CYREG_SFLASH_AV_PAIRS_8B098 0x0ffff0e2 +#define CYREG_SFLASH_AV_PAIRS_8B099 0x0ffff0e3 +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4 +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5 +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6 +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7 +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8 +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9 +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0ea +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0eb +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ec +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0ed +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0ee +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0ef +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0 +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1 +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2 +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3 +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4 +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5 +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6 +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7 +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8 +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9 +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fa +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fb +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fc +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fd +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0fe +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ff +#define CYREG_SFLASH_AV_PAIRS_32B00 0x0ffff100 +#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000 +#define CYFLD_SFLASH_DATA32__SIZE 0x00000020 +#define CYREG_SFLASH_AV_PAIRS_32B01 0x0ffff104 +#define CYREG_SFLASH_AV_PAIRS_32B02 0x0ffff108 +#define CYREG_SFLASH_AV_PAIRS_32B03 0x0ffff10c +#define CYREG_SFLASH_AV_PAIRS_32B04 0x0ffff110 +#define CYREG_SFLASH_AV_PAIRS_32B05 0x0ffff114 +#define CYREG_SFLASH_AV_PAIRS_32B06 0x0ffff118 +#define CYREG_SFLASH_AV_PAIRS_32B07 0x0ffff11c +#define CYREG_SFLASH_AV_PAIRS_32B08 0x0ffff120 +#define CYREG_SFLASH_AV_PAIRS_32B09 0x0ffff124 +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128 +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12c +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130 +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134 +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138 +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13c +#define CYREG_SFLASH_CPUSS_WOUNDING 0x0ffff140 +#define CYREG_SFLASH_SILICON_ID 0x0ffff144 +#define CYFLD_SFLASH_ID__OFFSET 0x00000000 +#define CYFLD_SFLASH_ID__SIZE 0x00000010 +#define CYREG_SFLASH_CPUSS_PRIV_RAM 0x0ffff148 +#define CYREG_SFLASH_CPUSS_PRIV_FLASH 0x0ffff14c +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150 +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000 +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000a +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152 +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154 +#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000 +#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001 +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158 +#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000 +#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020 +#define CYREG_SFLASH_FLASH_START 0x0ffff15c +#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000 +#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020 +#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160 +#define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000 +#define CYFLD_SFLASH_TRIM8__SIZE 0x00000008 +#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161 +#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162 +#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163 +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164 +#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000 +#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010 +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166 +#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000 +#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010 +#define CYREG_SFLASH_SKIP_CHECKSUM 0x0ffff169 +#define CYFLD_SFLASH_SKIP__OFFSET 0x00000000 +#define CYFLD_SFLASH_SKIP__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170 +#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000 +#define CYFLD_SFLASH_KEY8__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171 +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172 +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173 +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174 +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175 +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176 +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177 +#define CYREG_SFLASH_DIE_LOT0 0x0ffff178 +#define CYFLD_SFLASH_LOT__OFFSET 0x00000000 +#define CYFLD_SFLASH_LOT__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_LOT1 0x0ffff179 +#define CYREG_SFLASH_DIE_LOT2 0x0ffff17a +#define CYREG_SFLASH_DIE_WAFER 0x0ffff17b +#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000 +#define CYFLD_SFLASH_WAFER__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_X 0x0ffff17c +#define CYFLD_SFLASH_X__OFFSET 0x00000000 +#define CYFLD_SFLASH_X__SIZE 0x00000006 +#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000006 +#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000002 +#define CYREG_SFLASH_DIE_Y 0x0ffff17d +#define CYFLD_SFLASH_Y__OFFSET 0x00000000 +#define CYFLD_SFLASH_Y__SIZE 0x00000006 +#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000006 +#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000002 +#define CYREG_SFLASH_DIE_SORT 0x0ffff17e +#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000 +#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000002 +#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000002 +#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000002 +#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000004 +#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000002 +#define CYREG_SFLASH_DIE_MINOR 0x0ffff17f +#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000 +#define CYFLD_SFLASH_MINOR__SIZE 0x00000008 +#define CYREG_SFLASH_PE_TE_DATA00 0x0ffff180 +#define CYREG_SFLASH_PE_TE_DATA01 0x0ffff181 +#define CYREG_SFLASH_PE_TE_DATA02 0x0ffff182 +#define CYREG_SFLASH_PE_TE_DATA03 0x0ffff183 +#define CYREG_SFLASH_PE_TE_DATA04 0x0ffff184 +#define CYREG_SFLASH_PE_TE_DATA05 0x0ffff185 +#define CYREG_SFLASH_PE_TE_DATA06 0x0ffff186 +#define CYREG_SFLASH_PE_TE_DATA07 0x0ffff187 +#define CYREG_SFLASH_PE_TE_DATA08 0x0ffff188 +#define CYREG_SFLASH_PE_TE_DATA09 0x0ffff189 +#define CYREG_SFLASH_PE_TE_DATA10 0x0ffff18a +#define CYREG_SFLASH_PE_TE_DATA11 0x0ffff18b +#define CYREG_SFLASH_PE_TE_DATA12 0x0ffff18c +#define CYREG_SFLASH_PE_TE_DATA13 0x0ffff18d +#define CYREG_SFLASH_PE_TE_DATA14 0x0ffff18e +#define CYREG_SFLASH_PE_TE_DATA15 0x0ffff18f +#define CYREG_SFLASH_PE_TE_DATA16 0x0ffff190 +#define CYREG_SFLASH_PE_TE_DATA17 0x0ffff191 +#define CYREG_SFLASH_PE_TE_DATA18 0x0ffff192 +#define CYREG_SFLASH_PE_TE_DATA19 0x0ffff193 +#define CYREG_SFLASH_PE_TE_DATA20 0x0ffff194 +#define CYREG_SFLASH_PE_TE_DATA21 0x0ffff195 +#define CYREG_SFLASH_PE_TE_DATA22 0x0ffff196 +#define CYREG_SFLASH_PE_TE_DATA23 0x0ffff197 +#define CYREG_SFLASH_PE_TE_DATA24 0x0ffff198 +#define CYREG_SFLASH_PE_TE_DATA25 0x0ffff199 +#define CYREG_SFLASH_PE_TE_DATA26 0x0ffff19a +#define CYREG_SFLASH_PE_TE_DATA27 0x0ffff19b +#define CYREG_SFLASH_PE_TE_DATA28 0x0ffff19c +#define CYREG_SFLASH_PE_TE_DATA29 0x0ffff19d +#define CYREG_SFLASH_PE_TE_DATA30 0x0ffff19e +#define CYREG_SFLASH_PE_TE_DATA31 0x0ffff19f +#define CYREG_SFLASH_PP 0x0ffff1a0 +#define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000 +#define CYFLD_SFLASH_PERIOD__SIZE 0x00000018 +#define CYFLD_SFLASH_PDAC__OFFSET 0x00000018 +#define CYFLD_SFLASH_PDAC__SIZE 0x00000004 +#define CYFLD_SFLASH_NDAC__OFFSET 0x0000001c +#define CYFLD_SFLASH_NDAC__SIZE 0x00000004 +#define CYREG_SFLASH_E 0x0ffff1a4 +#define CYREG_SFLASH_P 0x0ffff1a8 +#define CYREG_SFLASH_EA_E 0x0ffff1ac +#define CYREG_SFLASH_EA_P 0x0ffff1b0 +#define CYREG_SFLASH_ES_E 0x0ffff1b4 +#define CYREG_SFLASH_ES_P_EO 0x0ffff1b8 +#define CYREG_SFLASH_E_VCTAT 0x0ffff1bc +#define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000 +#define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004 +#define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004 +#define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002 +#define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006 +#define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001 +#define CYREG_SFLASH_P_VCTAT 0x0ffff1bd +#define CYREG_SFLASH_MARGIN 0x0ffff1be +#define CYFLD_SFLASH_MDAC__OFFSET 0x00000000 +#define CYFLD_SFLASH_MDAC__SIZE 0x00000008 +#define CYREG_SFLASH_SPCIF_TRIM1 0x0ffff1bf +#define CYFLD_SFLASH_BDAC__OFFSET 0x00000000 +#define CYFLD_SFLASH_BDAC__SIZE 0x00000004 +#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0 +#define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000 +#define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006 +#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1 +#define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006 +#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2 +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006 +#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3 +#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4 +#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5 +#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6 +#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7 +#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8 +#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9 +#define CYREG_SFLASH_IMO_ABS3 0x0ffff1ca +#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cb +#define CYREG_SFLASH_IMO_ABS4 0x0ffff1cc +#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cd +#define CYREG_SFLASH_IMO_TRIM00 0x0ffff1d0 +#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000 +#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008 +#define CYREG_SFLASH_IMO_TRIM01 0x0ffff1d1 +#define CYREG_SFLASH_IMO_TRIM02 0x0ffff1d2 +#define CYREG_SFLASH_IMO_TRIM03 0x0ffff1d3 +#define CYREG_SFLASH_IMO_TRIM04 0x0ffff1d4 +#define CYREG_SFLASH_IMO_TRIM05 0x0ffff1d5 +#define CYREG_SFLASH_IMO_TRIM06 0x0ffff1d6 +#define CYREG_SFLASH_IMO_TRIM07 0x0ffff1d7 +#define CYREG_SFLASH_IMO_TRIM08 0x0ffff1d8 +#define CYREG_SFLASH_IMO_TRIM09 0x0ffff1d9 +#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1da +#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1db +#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dc +#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1dd +#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1de +#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1df +#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0 +#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1 +#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2 +#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3 +#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4 +#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5 +#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6 +#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7 +#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8 +#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9 +#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1ea +#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1eb +#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ec +#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1ed +#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1ee +#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1ef +#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0 +#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1 +#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2 +#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3 +#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4 +#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5 +#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6 +#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7 +#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8 +#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9 +#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fa +#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fb +#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fc +#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fd +#define CYREG_SFLASH_CHECKSUM 0x0ffff1fe +#define CYFLD_SFLASH_CHECKSUM__OFFSET 0x00000000 +#define CYFLD_SFLASH_CHECKSUM__SIZE 0x00000010 +#define CYDEV_SROM_BASE 0x10000000 +#define CYDEV_SROM_SIZE 0x00001000 +#define CYREG_SROM_DATA_MBASE 0x10000000 +#define CYREG_SROM_DATA_MSIZE 0x00001000 +#define CYDEV_SRAM_BASE 0x20000000 +#define CYDEV_SRAM_SIZE 0x00001000 +#define CYREG_SRAM_DATA_MBASE 0x20000000 +#define CYREG_SRAM_DATA_MSIZE 0x00001000 +#define CYDEV_CPUSS_BASE 0x40000000 +#define CYDEV_CPUSS_SIZE 0x00010000 +#define CYREG_CPUSS_CONFIG 0x40000000 +#define CYFLD_CPUSS_VECS_IN_RAM__OFFSET 0x00000000 +#define CYFLD_CPUSS_VECS_IN_RAM__SIZE 0x00000001 +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET 0x00000001 +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE 0x00000001 +#define CYREG_CPUSS_SYSREQ 0x40000004 +#define CYFLD_CPUSS_COMMAND__OFFSET 0x00000000 +#define CYFLD_CPUSS_COMMAND__SIZE 0x00000010 +#define CYFLD_CPUSS_NO_RST_OVR__OFFSET 0x0000001b +#define CYFLD_CPUSS_NO_RST_OVR__SIZE 0x00000001 +#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001c +#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001 +#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001d +#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001 +#define CYFLD_CPUSS_HMASTER__OFFSET 0x0000001e +#define CYFLD_CPUSS_HMASTER__SIZE 0x00000001 +#define CYFLD_CPUSS_SYSREQ__OFFSET 0x0000001f +#define CYFLD_CPUSS_SYSREQ__SIZE 0x00000001 +#define CYREG_CPUSS_SYSARG 0x40000008 +#define CYFLD_CPUSS_ARG32__OFFSET 0x00000000 +#define CYFLD_CPUSS_ARG32__SIZE 0x00000020 +#define CYREG_CPUSS_PROTECTION 0x4000000c +#define CYFLD_CPUSS_PROT__OFFSET 0x00000000 +#define CYFLD_CPUSS_PROT__SIZE 0x00000004 +#define CYVAL_CPUSS_PROT_VIRGIN 0x00000000 +#define CYVAL_CPUSS_PROT_OPEN 0x00000001 +#define CYVAL_CPUSS_PROT_PROTECTED 0x00000002 +#define CYVAL_CPUSS_PROT_KILL 0x00000004 +#define CYVAL_CPUSS_PROT_BOOT 0x00000008 +#define CYFLD_CPUSS_PROT_LOCK__OFFSET 0x0000001f +#define CYFLD_CPUSS_PROT_LOCK__SIZE 0x00000001 +#define CYREG_CPUSS_PRIV_ROM 0x40000010 +#define CYFLD_CPUSS_ROM_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_ROM_LIMIT__SIZE 0x00000008 +#define CYREG_CPUSS_PRIV_RAM 0x40000014 +#define CYFLD_CPUSS_RAM_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_RAM_LIMIT__SIZE 0x00000009 +#define CYREG_CPUSS_PRIV_FLASH 0x40000018 +#define CYFLD_CPUSS_FLASH_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_FLASH_LIMIT__SIZE 0x0000000b +#define CYREG_CPUSS_WOUNDING 0x4000001c +#define CYFLD_CPUSS_RAM_SIZE__OFFSET 0x00000000 +#define CYFLD_CPUSS_RAM_SIZE__SIZE 0x00000009 +#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010 +#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003 +#define CYVAL_CPUSS_RAM_WOUND_FULL 0x00000000 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 0x00000001 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 0x00000002 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 0x00000003 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 0x00000004 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 0x00000005 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 0x00000006 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 0x00000007 +#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014 +#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003 +#define CYVAL_CPUSS_FLASH_WOUND_FULL 0x00000000 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 0x00000001 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 0x00000002 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 0x00000003 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 0x00000004 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 0x00000005 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 0x00000006 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 0x00000007 +#define CYREG_CPUSS_INTR_SELECT 0x40000020 +#define CYFLD_CPUSS_SELECT32__OFFSET 0x00000000 +#define CYFLD_CPUSS_SELECT32__SIZE 0x00000020 +#define CYDEV_HSIOM_BASE 0x40010000 +#define CYDEV_HSIOM_SIZE 0x00001000 +#define CYREG_HSIOM_PORT_SEL0 0x40010000 +#define CYFLD_HSIOM_SEL0__OFFSET 0x00000000 +#define CYFLD_HSIOM_SEL0__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL0_GPIO 0x00000000 +#define CYVAL_HSIOM_SEL0_GPIO_DSI 0x00000001 +#define CYVAL_HSIOM_SEL0_DSI_DSI 0x00000002 +#define CYVAL_HSIOM_SEL0_DSI_GPIO 0x00000003 +#define CYVAL_HSIOM_SEL0_CSD_SENSE 0x00000004 +#define CYVAL_HSIOM_SEL0_CSD_SHIELD 0x00000005 +#define CYVAL_HSIOM_SEL0_AMUXA 0x00000006 +#define CYVAL_HSIOM_SEL0_AMUXB 0x00000007 +#define CYVAL_HSIOM_SEL0_ACT_0 0x00000008 +#define CYVAL_HSIOM_SEL0_ACT_1 0x00000009 +#define CYVAL_HSIOM_SEL0_ACT_2 0x0000000a +#define CYVAL_HSIOM_SEL0_ACT_3 0x0000000b +#define CYVAL_HSIOM_SEL0_LCD_COM 0x0000000c +#define CYVAL_HSIOM_SEL0_LCD_SEG 0x0000000d +#define CYVAL_HSIOM_SEL0_DPSLP_0 0x0000000e +#define CYVAL_HSIOM_SEL0_DPSLP_1 0x0000000f +#define CYVAL_HSIOM_SEL0_COMP1_INP 0x00000000 +#define CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 0x0000000f +#define CYFLD_HSIOM_SEL1__OFFSET 0x00000004 +#define CYFLD_HSIOM_SEL1__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL1_COMP1_INN 0x00000000 +#define CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 0x0000000f +#define CYFLD_HSIOM_SEL2__OFFSET 0x00000008 +#define CYFLD_HSIOM_SEL2__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL2_COMP2_INP 0x00000000 +#define CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 0x0000000f +#define CYFLD_HSIOM_SEL3__OFFSET 0x0000000c +#define CYFLD_HSIOM_SEL3__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL3_COMP2_INN 0x00000000 +#define CYFLD_HSIOM_SEL4__OFFSET 0x00000010 +#define CYFLD_HSIOM_SEL4__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL4_SCB1_UART_RX 0x00000009 +#define CYVAL_HSIOM_SEL4_SCB1_I2C_SCL 0x0000000e +#define CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI 0x0000000f +#define CYFLD_HSIOM_SEL5__OFFSET 0x00000014 +#define CYFLD_HSIOM_SEL5__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL5_SCB1_UART_TX 0x00000009 +#define CYVAL_HSIOM_SEL5_SCB1_I2C_SDA 0x0000000e +#define CYVAL_HSIOM_SEL5_SCB1_SPI_MISO 0x0000000f +#define CYFLD_HSIOM_SEL6__OFFSET 0x00000018 +#define CYFLD_HSIOM_SEL6__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL6_EXT_CLK 0x00000008 +#define CYVAL_HSIOM_SEL6_SCB1_SPI_CLK 0x0000000f +#define CYFLD_HSIOM_SEL7__OFFSET 0x0000001c +#define CYFLD_HSIOM_SEL7__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL7_WAKEUP 0x0000000e +#define CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 0x0000000f +#define CYREG_HSIOM_PORT_SEL1 0x40010004 +#define CYREG_HSIOM_PORT_SEL2 0x40010008 +#define CYREG_HSIOM_PORT_SEL3 0x4001000c +#define CYREG_HSIOM_PORT_SEL4 0x40010010 +#define CYDEV_CLK_BASE 0x40020000 +#define CYDEV_CLK_SIZE 0x00010000 +#define CYREG_CLK_DIVIDER_A00 0x40020000 +#define CYFLD_CLK_DIVIDER_A__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_A__SIZE 0x00000010 +#define CYFLD_CLK_ENABLE_A__OFFSET 0x0000001f +#define CYFLD_CLK_ENABLE_A__SIZE 0x00000001 +#define CYREG_CLK_DIVIDER_A01 0x40020004 +#define CYREG_CLK_DIVIDER_A02 0x40020008 +#define CYREG_CLK_DIVIDER_B00 0x40020040 +#define CYFLD_CLK_DIVIDER_B__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_B__SIZE 0x00000010 +#define CYFLD_CLK_CASCADE_A_B__OFFSET 0x0000001e +#define CYFLD_CLK_CASCADE_A_B__SIZE 0x00000001 +#define CYFLD_CLK_ENABLE_B__OFFSET 0x0000001f +#define CYFLD_CLK_ENABLE_B__SIZE 0x00000001 +#define CYREG_CLK_DIVIDER_B01 0x40020044 +#define CYREG_CLK_DIVIDER_B02 0x40020048 +#define CYREG_CLK_DIVIDER_C00 0x40020080 +#define CYFLD_CLK_DIVIDER_C__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_C__SIZE 0x00000010 +#define CYFLD_CLK_CASCADE_B_C__OFFSET 0x0000001e +#define CYFLD_CLK_CASCADE_B_C__SIZE 0x00000001 +#define CYFLD_CLK_ENABLE_C__OFFSET 0x0000001f +#define CYFLD_CLK_ENABLE_C__SIZE 0x00000001 +#define CYREG_CLK_DIVIDER_C01 0x40020084 +#define CYREG_CLK_DIVIDER_C02 0x40020088 +#define CYREG_CLK_DIVIDER_FRAC_A00 0x40020100 +#define CYFLD_CLK_FRAC_A__OFFSET 0x00000010 +#define CYFLD_CLK_FRAC_A__SIZE 0x00000005 +#define CYREG_CLK_DIVIDER_FRAC_B00 0x40020140 +#define CYFLD_CLK_FRAC_B__OFFSET 0x00000010 +#define CYFLD_CLK_FRAC_B__SIZE 0x00000005 +#define CYREG_CLK_DIVIDER_FRAC_C00 0x40020180 +#define CYFLD_CLK_FRAC_C__OFFSET 0x00000010 +#define CYFLD_CLK_FRAC_C__SIZE 0x00000005 +#define CYREG_CLK_SELECT00 0x40020200 +#define CYFLD_CLK_DIVIDER_N__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_N__SIZE 0x00000004 +#define CYFLD_CLK_DIVIDER_ABC__OFFSET 0x00000004 +#define CYFLD_CLK_DIVIDER_ABC__SIZE 0x00000002 +#define CYVAL_CLK_DIVIDER_ABC_OFF 0x00000000 +#define CYVAL_CLK_DIVIDER_ABC_A 0x00000001 +#define CYVAL_CLK_DIVIDER_ABC_B 0x00000002 +#define CYVAL_CLK_DIVIDER_ABC_C 0x00000003 +#define CYREG_CLK_SELECT01 0x40020204 +#define CYREG_CLK_SELECT02 0x40020208 +#define CYREG_CLK_SELECT03 0x4002020c +#define CYREG_CLK_SELECT04 0x40020210 +#define CYREG_CLK_SELECT05 0x40020214 +#define CYREG_CLK_SELECT06 0x40020218 +#define CYREG_CLK_SELECT07 0x4002021c +#define CYREG_CLK_SELECT08 0x40020220 +#define CYREG_CLK_SELECT09 0x40020224 +#define CYREG_CLK_SELECT10 0x40020228 +#define CYREG_CLK_SELECT11 0x4002022c +#define CYREG_CLK_SELECT12 0x40020230 +#define CYREG_CLK_SELECT13 0x40020234 +#define CYREG_CLK_SELECT14 0x40020238 +#define CYREG_CLK_SELECT15 0x4002023c +#define CYDEV_TST_BASE 0x40030000 +#define CYDEV_TST_SIZE 0x00010000 +#define CYREG_TST_CTRL 0x40030000 +#define CYFLD_TST_DAP_NO_ACCESS__OFFSET 0x00000000 +#define CYFLD_TST_DAP_NO_ACCESS__SIZE 0x00000001 +#define CYFLD_TST_DAP_NO_DEBUG__OFFSET 0x00000001 +#define CYFLD_TST_DAP_NO_DEBUG__SIZE 0x00000001 +#define CYFLD_TST_SWD_CONNECTED__OFFSET 0x00000002 +#define CYFLD_TST_SWD_CONNECTED__SIZE 0x00000001 +#define CYFLD_TST_TEST_RESET_EN_N__OFFSET 0x00000008 +#define CYFLD_TST_TEST_RESET_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_SET_EN_N__OFFSET 0x00000009 +#define CYFLD_TST_TEST_SET_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_ICG_EN_N__OFFSET 0x0000000a +#define CYFLD_TST_TEST_ICG_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET 0x0000000b +#define CYFLD_TST_TEST_OCC0_1_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET 0x0000000c +#define CYFLD_TST_TEST_OCC0_2_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET 0x0000000d +#define CYFLD_TST_TEST_SLPISOLATE_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET 0x0000000e +#define CYFLD_TST_TEST_SYSISOLATE_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET 0x0000000f +#define CYFLD_TST_TEST_SLPRETAIN_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET 0x00000010 +#define CYFLD_TST_TEST_SYSRETAIN_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SPARE1_EN__OFFSET 0x00000011 +#define CYFLD_TST_TEST_SPARE1_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SPARE2_EN__OFFSET 0x00000012 +#define CYFLD_TST_TEST_SPARE2_EN__SIZE 0x00000001 +#define CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET 0x00000018 +#define CYFLD_TST_SCAN_OCC_OBSERVE__SIZE 0x00000001 +#define CYFLD_TST_SCAN_TRF1__OFFSET 0x00000019 +#define CYFLD_TST_SCAN_TRF1__SIZE 0x00000001 +#define CYFLD_TST_SCAN_TRF__OFFSET 0x0000001a +#define CYFLD_TST_SCAN_TRF__SIZE 0x00000001 +#define CYFLD_TST_SCAN_IDDQ__OFFSET 0x0000001b +#define CYFLD_TST_SCAN_IDDQ__SIZE 0x00000001 +#define CYFLD_TST_SCAN_COMPRESS__OFFSET 0x0000001c +#define CYFLD_TST_SCAN_COMPRESS__SIZE 0x00000001 +#define CYFLD_TST_SCAN_MODE__OFFSET 0x0000001d +#define CYFLD_TST_SCAN_MODE__SIZE 0x00000001 +#define CYFLD_TST_PTM_MODE_EN__OFFSET 0x0000001e +#define CYFLD_TST_PTM_MODE_EN__SIZE 0x00000001 +#define CYREG_TST_ADFT_CTRL 0x40030004 +#define CYFLD_TST_ENABLE__OFFSET 0x0000001f +#define CYFLD_TST_ENABLE__SIZE 0x00000001 +#define CYREG_TST_DDFT_CTRL 0x40030008 +#define CYFLD_TST_DFT_SEL1__OFFSET 0x00000000 +#define CYFLD_TST_DFT_SEL1__SIZE 0x00000006 +#define CYVAL_TST_DFT_SEL1_VSS 0x00000000 +#define CYVAL_TST_DFT_SEL1_CLK1 0x00000001 +#define CYVAL_TST_DFT_SEL1_CLK2 0x00000002 +#define CYVAL_TST_DFT_SEL1_PWR1 0x00000003 +#define CYVAL_TST_DFT_SEL1_PWR2 0x00000004 +#define CYVAL_TST_DFT_SEL1_VMON 0x00000005 +#define CYVAL_TST_DFT_SEL1_TSS_VDDA_OK 0x00000006 +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP1 0x00000007 +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP2 0x00000008 +#define CYVAL_TST_DFT_SEL1_TSS1 0x00000009 +#define CYVAL_TST_DFT_SEL1_TSS2 0x0000000a +#define CYVAL_TST_DFT_SEL1_TSS3 0x0000000b +#define CYVAL_TST_DFT_SEL1_TSS4 0x0000000c +#define CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS 0x0000000d +#define CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI 0x0000000e +#define CYFLD_TST_DFT_SEL2__OFFSET 0x00000008 +#define CYFLD_TST_DFT_SEL2__SIZE 0x00000006 +#define CYVAL_TST_DFT_SEL2_VSS 0x00000000 +#define CYVAL_TST_DFT_SEL2_CLK1 0x00000001 +#define CYVAL_TST_DFT_SEL2_CLK2 0x00000002 +#define CYVAL_TST_DFT_SEL2_PWR1 0x00000003 +#define CYVAL_TST_DFT_SEL2_PWR2 0x00000004 +#define CYVAL_TST_DFT_SEL2_VMON 0x00000005 +#define CYVAL_TST_DFT_SEL2_TSS_VDDA_OK 0x00000006 +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP1 0x00000007 +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP2 0x00000008 +#define CYVAL_TST_DFT_SEL2_TSS1 0x00000009 +#define CYVAL_TST_DFT_SEL2_TSS2 0x0000000a +#define CYVAL_TST_DFT_SEL2_TSS3 0x0000000b +#define CYVAL_TST_DFT_SEL2_TSS4 0x0000000c +#define CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS 0x0000000d +#define CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI 0x0000000e +#define CYFLD_TST_EDGE__OFFSET 0x0000001c +#define CYFLD_TST_EDGE__SIZE 0x00000001 +#define CYVAL_TST_EDGE_POSEDGE 0x00000000 +#define CYVAL_TST_EDGE_NEGEDGE 0x00000001 +#define CYFLD_TST_DIVIDE__OFFSET 0x0000001d +#define CYFLD_TST_DIVIDE__SIZE 0x00000002 +#define CYVAL_TST_DIVIDE_DIRECT 0x00000000 +#define CYVAL_TST_DIVIDE_DIV_BY_2 0x00000001 +#define CYVAL_TST_DIVIDE_DIV_BY_4 0x00000002 +#define CYVAL_TST_DIVIDE_DIV_BY_8 0x00000003 +#define CYREG_TST_MODE 0x40030014 +#define CYFLD_TST_TEST_MODE__OFFSET 0x0000001f +#define CYFLD_TST_TEST_MODE__SIZE 0x00000001 +#define CYREG_TST_TRIM_CNTR1 0x40030018 +#define CYFLD_TST_COUNTER__OFFSET 0x00000000 +#define CYFLD_TST_COUNTER__SIZE 0x00000010 +#define CYFLD_TST_COUNTER_DONE__OFFSET 0x0000001f +#define CYFLD_TST_COUNTER_DONE__SIZE 0x00000001 +#define CYREG_TST_TRIM_CNTR2 0x4003001c +#define CYDEV_PRT0_BASE 0x40040000 +#define CYDEV_PRT0_SIZE 0x00000100 +#define CYREG_PRT0_DR 0x40040000 +#define CYFLD_PRT_DATAREG__OFFSET 0x00000000 +#define CYFLD_PRT_DATAREG__SIZE 0x00000008 +#define CYREG_PRT0_PS 0x40040004 +#define CYFLD_PRT_PINSTATE__OFFSET 0x00000000 +#define CYFLD_PRT_PINSTATE__SIZE 0x00000008 +#define CYFLD_PRT_PINSTATE_FLT__OFFSET 0x00000008 +#define CYFLD_PRT_PINSTATE_FLT__SIZE 0x00000001 +#define CYREG_PRT0_PC 0x40040008 +#define CYFLD_PRT_DM__OFFSET 0x00000000 +#define CYFLD_PRT_DM__SIZE 0x00000018 +#define CYVAL_PRT_DM_OFF 0x00000000 +#define CYVAL_PRT_DM_INPUT 0x00000001 +#define CYVAL_PRT_DM_0_PU 0x00000002 +#define CYVAL_PRT_DM_PD_1 0x00000003 +#define CYVAL_PRT_DM_0_Z 0x00000004 +#define CYVAL_PRT_DM_Z_1 0x00000005 +#define CYVAL_PRT_DM_0_1 0x00000006 +#define CYVAL_PRT_DM_PD_PU 0x00000007 +#define CYFLD_PRT_VTRIP_SEL__OFFSET 0x00000018 +#define CYFLD_PRT_VTRIP_SEL__SIZE 0x00000001 +#define CYFLD_PRT_SLOW__OFFSET 0x00000019 +#define CYFLD_PRT_SLOW__SIZE 0x00000001 +#define CYREG_PRT0_INTCFG 0x4004000c +#define CYFLD_PRT_INTTYPE__OFFSET 0x00000000 +#define CYFLD_PRT_INTTYPE__SIZE 0x00000010 +#define CYVAL_PRT_INTTYPE_DISABLE 0x00000000 +#define CYVAL_PRT_INTTYPE_RISING 0x00000001 +#define CYVAL_PRT_INTTYPE_FALLING 0x00000002 +#define CYVAL_PRT_INTTYPE_BOTH 0x00000003 +#define CYFLD_PRT_INTTYPE_FLT__OFFSET 0x00000010 +#define CYFLD_PRT_INTTYPE_FLT__SIZE 0x00000002 +#define CYVAL_PRT_INTTYPE_FLT_DISABLE 0x00000000 +#define CYVAL_PRT_INTTYPE_FLT_RISING 0x00000001 +#define CYVAL_PRT_INTTYPE_FLT_FALLING 0x00000002 +#define CYVAL_PRT_INTTYPE_FLT_BOTH 0x00000003 +#define CYFLD_PRT_FLT_SELECT__OFFSET 0x00000012 +#define CYFLD_PRT_FLT_SELECT__SIZE 0x00000003 +#define CYREG_PRT0_INTSTAT 0x40040010 +#define CYFLD_PRT_INTSTAT__OFFSET 0x00000000 +#define CYFLD_PRT_INTSTAT__SIZE 0x00000008 +#define CYFLD_PRT_INTSTAT_FLT__OFFSET 0x00000008 +#define CYFLD_PRT_INTSTAT_FLT__SIZE 0x00000001 +#define CYFLD_PRT_PS__OFFSET 0x00000010 +#define CYFLD_PRT_PS__SIZE 0x00000008 +#define CYFLD_PRT_PS_FLT__OFFSET 0x00000018 +#define CYFLD_PRT_PS_FLT__SIZE 0x00000001 +#define CYREG_PRT0_PC2 0x40040018 +#define CYFLD_PRT_INP_DIS__OFFSET 0x00000000 +#define CYFLD_PRT_INP_DIS__SIZE 0x00000008 +#define CYDEV_PRT1_BASE 0x40040100 +#define CYDEV_PRT1_SIZE 0x00000100 +#define CYREG_PRT1_DR 0x40040100 +#define CYREG_PRT1_PS 0x40040104 +#define CYREG_PRT1_PC 0x40040108 +#define CYREG_PRT1_INTCFG 0x4004010c +#define CYREG_PRT1_INTSTAT 0x40040110 +#define CYREG_PRT1_PC2 0x40040118 +#define CYDEV_PRT2_BASE 0x40040200 +#define CYDEV_PRT2_SIZE 0x00000100 +#define CYREG_PRT2_DR 0x40040200 +#define CYREG_PRT2_PS 0x40040204 +#define CYREG_PRT2_PC 0x40040208 +#define CYREG_PRT2_INTCFG 0x4004020c +#define CYREG_PRT2_INTSTAT 0x40040210 +#define CYREG_PRT2_PC2 0x40040218 +#define CYDEV_PRT3_BASE 0x40040300 +#define CYDEV_PRT3_SIZE 0x00000100 +#define CYREG_PRT3_DR 0x40040300 +#define CYREG_PRT3_PS 0x40040304 +#define CYREG_PRT3_PC 0x40040308 +#define CYREG_PRT3_INTCFG 0x4004030c +#define CYREG_PRT3_INTSTAT 0x40040310 +#define CYREG_PRT3_PC2 0x40040318 +#define CYDEV_PRT4_BASE 0x40040400 +#define CYDEV_PRT4_SIZE 0x00000100 +#define CYREG_PRT4_DR 0x40040400 +#define CYREG_PRT4_PS 0x40040404 +#define CYREG_PRT4_PC 0x40040408 +#define CYREG_PRT4_INTCFG 0x4004040c +#define CYREG_PRT4_INTSTAT 0x40040410 +#define CYREG_PRT4_PC2 0x40040418 +#define CYDEV_TCPWM_BASE 0x40050000 +#define CYDEV_TCPWM_SIZE 0x00001000 +#define CYREG_TCPWM_CTRL 0x40050000 +#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008 +#define CYREG_TCPWM_CMD 0x40050008 +#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008 +#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010 +#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018 +#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008 +#define CYREG_TCPWM_INTR_CAUSE 0x4005000c +#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008 +#define CYDEV_TCPWM_CNT0_BASE 0x40050100 +#define CYDEV_TCPWM_CNT0_SIZE 0x00000040 +#define CYREG_TCPWM_CNT0_CTRL 0x40050100 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003 +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007 +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010 +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003 +#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012 +#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014 +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002 +#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018 +#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003 +#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000 +#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002 +#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003 +#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004 +#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005 +#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006 +#define CYREG_TCPWM_CNT0_STATUS 0x40050104 +#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001f +#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001 +#define CYREG_TCPWM_CNT0_COUNTER 0x40050108 +#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_CC 0x4005010c +#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_CC_BUFF 0x40050110 +#define CYREG_TCPWM_CNT0_PERIOD 0x40050114 +#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40050118 +#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40050120 +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000c +#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010 +#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004 +#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40050124 +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006 +#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003 +#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40050128 +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003 +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003 +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003 +#define CYREG_TCPWM_CNT0_INTR 0x40050130 +#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001 +#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001 +#define CYREG_TCPWM_CNT0_INTR_SET 0x40050134 +#define CYREG_TCPWM_CNT0_INTR_MASK 0x40050138 +#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4005013c +#define CYDEV_TCPWM_CNT1_BASE 0x40050140 +#define CYDEV_TCPWM_CNT1_SIZE 0x00000040 +#define CYREG_TCPWM_CNT1_CTRL 0x40050140 +#define CYREG_TCPWM_CNT1_STATUS 0x40050144 +#define CYREG_TCPWM_CNT1_COUNTER 0x40050148 +#define CYREG_TCPWM_CNT1_CC 0x4005014c +#define CYREG_TCPWM_CNT1_CC_BUFF 0x40050150 +#define CYREG_TCPWM_CNT1_PERIOD 0x40050154 +#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40050158 +#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40050160 +#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40050164 +#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40050168 +#define CYREG_TCPWM_CNT1_INTR 0x40050170 +#define CYREG_TCPWM_CNT1_INTR_SET 0x40050174 +#define CYREG_TCPWM_CNT1_INTR_MASK 0x40050178 +#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4005017c +#define CYDEV_TCPWM_CNT2_BASE 0x40050180 +#define CYDEV_TCPWM_CNT2_SIZE 0x00000040 +#define CYREG_TCPWM_CNT2_CTRL 0x40050180 +#define CYREG_TCPWM_CNT2_STATUS 0x40050184 +#define CYREG_TCPWM_CNT2_COUNTER 0x40050188 +#define CYREG_TCPWM_CNT2_CC 0x4005018c +#define CYREG_TCPWM_CNT2_CC_BUFF 0x40050190 +#define CYREG_TCPWM_CNT2_PERIOD 0x40050194 +#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40050198 +#define CYREG_TCPWM_CNT2_TR_CTRL0 0x400501a0 +#define CYREG_TCPWM_CNT2_TR_CTRL1 0x400501a4 +#define CYREG_TCPWM_CNT2_TR_CTRL2 0x400501a8 +#define CYREG_TCPWM_CNT2_INTR 0x400501b0 +#define CYREG_TCPWM_CNT2_INTR_SET 0x400501b4 +#define CYREG_TCPWM_CNT2_INTR_MASK 0x400501b8 +#define CYREG_TCPWM_CNT2_INTR_MASKED 0x400501bc +#define CYDEV_TCPWM_CNT3_BASE 0x400501c0 +#define CYDEV_TCPWM_CNT3_SIZE 0x00000040 +#define CYREG_TCPWM_CNT3_CTRL 0x400501c0 +#define CYREG_TCPWM_CNT3_STATUS 0x400501c4 +#define CYREG_TCPWM_CNT3_COUNTER 0x400501c8 +#define CYREG_TCPWM_CNT3_CC 0x400501cc +#define CYREG_TCPWM_CNT3_CC_BUFF 0x400501d0 +#define CYREG_TCPWM_CNT3_PERIOD 0x400501d4 +#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x400501d8 +#define CYREG_TCPWM_CNT3_TR_CTRL0 0x400501e0 +#define CYREG_TCPWM_CNT3_TR_CTRL1 0x400501e4 +#define CYREG_TCPWM_CNT3_TR_CTRL2 0x400501e8 +#define CYREG_TCPWM_CNT3_INTR 0x400501f0 +#define CYREG_TCPWM_CNT3_INTR_SET 0x400501f4 +#define CYREG_TCPWM_CNT3_INTR_MASK 0x400501f8 +#define CYREG_TCPWM_CNT3_INTR_MASKED 0x400501fc +#define CYDEV_SCB0_BASE 0x40060000 +#define CYDEV_SCB0_SIZE 0x00010000 +#define CYREG_SCB0_CTRL 0x40060000 +#define CYFLD_SCB_OVS__OFFSET 0x00000000 +#define CYFLD_SCB_OVS__SIZE 0x00000004 +#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008 +#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001 +#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009 +#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001 +#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000a +#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001 +#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010 +#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001 +#define CYFLD_SCB_BLOCK__OFFSET 0x00000011 +#define CYFLD_SCB_BLOCK__SIZE 0x00000001 +#define CYFLD_SCB_MODE__OFFSET 0x00000018 +#define CYFLD_SCB_MODE__SIZE 0x00000002 +#define CYVAL_SCB_MODE_I2C 0x00000000 +#define CYVAL_SCB_MODE_SPI 0x00000001 +#define CYVAL_SCB_MODE_UART 0x00000002 +#define CYFLD_SCB_ENABLED__OFFSET 0x0000001f +#define CYFLD_SCB_ENABLED__SIZE 0x00000001 +#define CYREG_SCB0_STATUS 0x40060004 +#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000 +#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001 +#define CYREG_SCB0_SPI_CTRL 0x40060020 +#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000 +#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001 +#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001 +#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001 +#define CYFLD_SCB_CPHA__OFFSET 0x00000002 +#define CYFLD_SCB_CPHA__SIZE 0x00000001 +#define CYFLD_SCB_CPOL__OFFSET 0x00000003 +#define CYFLD_SCB_CPOL__SIZE 0x00000001 +#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004 +#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001 +#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010 +#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001 +#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001a +#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002 +#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001f +#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001 +#define CYREG_SCB0_SPI_STATUS 0x40060024 +#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000 +#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001 +#define CYFLD_SCB_EZ_ADDR__OFFSET 0x00000008 +#define CYFLD_SCB_EZ_ADDR__SIZE 0x00000008 +#define CYREG_SCB0_UART_CTRL 0x40060040 +#define CYREG_SCB0_UART_TX_CTRL 0x40060044 +#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000 +#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003 +#define CYFLD_SCB_PARITY__OFFSET 0x00000004 +#define CYFLD_SCB_PARITY__SIZE 0x00000001 +#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005 +#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001 +#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008 +#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001 +#define CYREG_SCB0_UART_RX_CTRL 0x40060048 +#define CYFLD_SCB_POLARITY__OFFSET 0x00000006 +#define CYFLD_SCB_POLARITY__SIZE 0x00000001 +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009 +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000a +#define CYFLD_SCB_MP_MODE__SIZE 0x00000001 +#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000c +#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001 +#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000d +#define CYFLD_SCB_SKIP_START__SIZE 0x00000001 +#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010 +#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004 +#define CYREG_SCB0_UART_RX_STATUS 0x4006004c +#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000 +#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000c +#define CYREG_SCB0_I2C_CTRL 0x40060060 +#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000 +#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004 +#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004 +#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004 +#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008 +#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001 +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009 +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001 +#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000b +#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001 +#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000c +#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000d +#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000e +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000f +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001 +#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001e +#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001 +#define CYREG_SCB0_I2C_STATUS 0x40060064 +#define CYFLD_SCB_S_READ__OFFSET 0x00000004 +#define CYFLD_SCB_S_READ__SIZE 0x00000001 +#define CYFLD_SCB_M_READ__OFFSET 0x00000005 +#define CYFLD_SCB_M_READ__SIZE 0x00000001 +#define CYREG_SCB0_I2C_M_CMD 0x40060068 +#define CYFLD_SCB_M_START__OFFSET 0x00000000 +#define CYFLD_SCB_M_START__SIZE 0x00000001 +#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001 +#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001 +#define CYFLD_SCB_M_ACK__OFFSET 0x00000002 +#define CYFLD_SCB_M_ACK__SIZE 0x00000001 +#define CYFLD_SCB_M_NACK__OFFSET 0x00000003 +#define CYFLD_SCB_M_NACK__SIZE 0x00000001 +#define CYFLD_SCB_M_STOP__OFFSET 0x00000004 +#define CYFLD_SCB_M_STOP__SIZE 0x00000001 +#define CYREG_SCB0_I2C_S_CMD 0x4006006c +#define CYFLD_SCB_S_ACK__OFFSET 0x00000000 +#define CYFLD_SCB_S_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NACK__OFFSET 0x00000001 +#define CYFLD_SCB_S_NACK__SIZE 0x00000001 +#define CYREG_SCB0_I2C_CFG 0x40060070 +#define CYFLD_SCB_SDA_FILT_HYS__OFFSET 0x00000000 +#define CYFLD_SCB_SDA_FILT_HYS__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_TRIM__OFFSET 0x00000002 +#define CYFLD_SCB_SDA_FILT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SCL_FILT_HYS__OFFSET 0x00000004 +#define CYFLD_SCB_SCL_FILT_HYS__SIZE 0x00000002 +#define CYFLD_SCB_SCL_FILT_TRIM__OFFSET 0x00000006 +#define CYFLD_SCB_SCL_FILT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET 0x00000008 +#define CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET 0x0000000a +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_HS__OFFSET 0x00000010 +#define CYFLD_SCB_SDA_FILT_HS__SIZE 0x00000001 +#define CYFLD_SCB_SDA_FILT_ENABLED__OFFSET 0x00000011 +#define CYFLD_SCB_SDA_FILT_ENABLED__SIZE 0x00000001 +#define CYFLD_SCB_SCL_FILT_HS__OFFSET 0x00000018 +#define CYFLD_SCB_SCL_FILT_HS__SIZE 0x00000001 +#define CYFLD_SCB_SCL_FILT_ENABLED__OFFSET 0x00000019 +#define CYFLD_SCB_SCL_FILT_ENABLED__SIZE 0x00000001 +#define CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET 0x0000001a +#define CYFLD_SCB_SDA_FILT_OUT_HS__SIZE 0x00000001 +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET 0x0000001b +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE 0x00000001 +#define CYREG_SCB0_BIST_CONTROL 0x40060100 +#define CYFLD_SCB_RAM_ADDR__OFFSET 0x00000000 +#define CYFLD_SCB_RAM_ADDR__SIZE 0x00000005 +#define CYFLD_SCB_RAM_OP1__OFFSET 0x00000010 +#define CYFLD_SCB_RAM_OP1__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OP2__OFFSET 0x00000012 +#define CYFLD_SCB_RAM_OP2__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OP3__OFFSET 0x00000014 +#define CYFLD_SCB_RAM_OP3__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OP4__OFFSET 0x00000016 +#define CYFLD_SCB_RAM_OP4__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OPCNT__OFFSET 0x00000018 +#define CYFLD_SCB_RAM_OPCNT__SIZE 0x00000002 +#define CYFLD_SCB_RAM_PREADR__OFFSET 0x0000001a +#define CYFLD_SCB_RAM_PREADR__SIZE 0x00000001 +#define CYFLD_SCB_RAM_WORD__OFFSET 0x0000001b +#define CYFLD_SCB_RAM_WORD__SIZE 0x00000001 +#define CYFLD_SCB_RAM_FAIL__OFFSET 0x0000001c +#define CYFLD_SCB_RAM_FAIL__SIZE 0x00000001 +#define CYFLD_SCB_RAM_GO__OFFSET 0x0000001d +#define CYFLD_SCB_RAM_GO__SIZE 0x00000001 +#define CYREG_SCB0_BIST_DATA 0x40060104 +#define CYFLD_SCB_RAM_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_RAM_DATA__SIZE 0x00000010 +#define CYREG_SCB0_TX_CTRL 0x40060200 +#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000 +#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004 +#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008 +#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001 +#define CYREG_SCB0_TX_FIFO_CTRL 0x40060204 +#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000 +#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000003 +#define CYFLD_SCB_CLEAR__OFFSET 0x00000010 +#define CYFLD_SCB_CLEAR__SIZE 0x00000001 +#define CYFLD_SCB_FREEZE__OFFSET 0x00000011 +#define CYFLD_SCB_FREEZE__SIZE 0x00000001 +#define CYREG_SCB0_TX_FIFO_STATUS 0x40060208 +#define CYFLD_SCB_USED__OFFSET 0x00000000 +#define CYFLD_SCB_USED__SIZE 0x00000004 +#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000f +#define CYFLD_SCB_SR_VALID__SIZE 0x00000001 +#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010 +#define CYFLD_SCB_RD_PTR__SIZE 0x00000003 +#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018 +#define CYFLD_SCB_WR_PTR__SIZE 0x00000003 +#define CYREG_SCB0_TX_FIFO_WR 0x40060240 +#define CYFLD_SCB_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_DATA__SIZE 0x00000010 +#define CYREG_SCB0_RX_CTRL 0x40060300 +#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009 +#define CYFLD_SCB_MEDIAN__SIZE 0x00000001 +#define CYREG_SCB0_RX_FIFO_CTRL 0x40060304 +#define CYREG_SCB0_RX_FIFO_STATUS 0x40060308 +#define CYREG_SCB0_RX_MATCH 0x40060310 +#define CYFLD_SCB_ADDR__OFFSET 0x00000000 +#define CYFLD_SCB_ADDR__SIZE 0x00000008 +#define CYFLD_SCB_MASK__OFFSET 0x00000010 +#define CYFLD_SCB_MASK__SIZE 0x00000008 +#define CYREG_SCB0_RX_FIFO_RD 0x40060340 +#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40060344 +#define CYREG_SCB0_EZ_DATA00 0x40060400 +#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008 +#define CYREG_SCB0_EZ_DATA01 0x40060404 +#define CYREG_SCB0_EZ_DATA02 0x40060408 +#define CYREG_SCB0_EZ_DATA03 0x4006040c +#define CYREG_SCB0_EZ_DATA04 0x40060410 +#define CYREG_SCB0_EZ_DATA05 0x40060414 +#define CYREG_SCB0_EZ_DATA06 0x40060418 +#define CYREG_SCB0_EZ_DATA07 0x4006041c +#define CYREG_SCB0_EZ_DATA08 0x40060420 +#define CYREG_SCB0_EZ_DATA09 0x40060424 +#define CYREG_SCB0_EZ_DATA10 0x40060428 +#define CYREG_SCB0_EZ_DATA11 0x4006042c +#define CYREG_SCB0_EZ_DATA12 0x40060430 +#define CYREG_SCB0_EZ_DATA13 0x40060434 +#define CYREG_SCB0_EZ_DATA14 0x40060438 +#define CYREG_SCB0_EZ_DATA15 0x4006043c +#define CYREG_SCB0_EZ_DATA16 0x40060440 +#define CYREG_SCB0_EZ_DATA17 0x40060444 +#define CYREG_SCB0_EZ_DATA18 0x40060448 +#define CYREG_SCB0_EZ_DATA19 0x4006044c +#define CYREG_SCB0_EZ_DATA20 0x40060450 +#define CYREG_SCB0_EZ_DATA21 0x40060454 +#define CYREG_SCB0_EZ_DATA22 0x40060458 +#define CYREG_SCB0_EZ_DATA23 0x4006045c +#define CYREG_SCB0_EZ_DATA24 0x40060460 +#define CYREG_SCB0_EZ_DATA25 0x40060464 +#define CYREG_SCB0_EZ_DATA26 0x40060468 +#define CYREG_SCB0_EZ_DATA27 0x4006046c +#define CYREG_SCB0_EZ_DATA28 0x40060470 +#define CYREG_SCB0_EZ_DATA29 0x40060474 +#define CYREG_SCB0_EZ_DATA30 0x40060478 +#define CYREG_SCB0_EZ_DATA31 0x4006047c +#define CYREG_SCB0_INTR_CAUSE 0x40060e00 +#define CYFLD_SCB_M__OFFSET 0x00000000 +#define CYFLD_SCB_M__SIZE 0x00000001 +#define CYFLD_SCB_S__OFFSET 0x00000001 +#define CYFLD_SCB_S__SIZE 0x00000001 +#define CYFLD_SCB_TX__OFFSET 0x00000002 +#define CYFLD_SCB_TX__SIZE 0x00000001 +#define CYFLD_SCB_RX__OFFSET 0x00000003 +#define CYFLD_SCB_RX__SIZE 0x00000001 +#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004 +#define CYFLD_SCB_I2C_EC__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005 +#define CYFLD_SCB_SPI_EC__SIZE 0x00000001 +#define CYREG_SCB0_INTR_I2C_EC 0x40060e80 +#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000 +#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001 +#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001 +#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001 +#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002 +#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001 +#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40060e88 +#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40060e8c +#define CYREG_SCB0_INTR_SPI_EC 0x40060ec0 +#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40060ec8 +#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40060ecc +#define CYREG_SCB0_INTR_M 0x40060f00 +#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000 +#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001 +#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001 +#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001 +#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002 +#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001 +#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004 +#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001 +#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009 +#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001 +#define CYREG_SCB0_INTR_M_SET 0x40060f04 +#define CYREG_SCB0_INTR_M_MASK 0x40060f08 +#define CYREG_SCB0_INTR_M_MASKED 0x40060f0c +#define CYREG_SCB0_INTR_S 0x40060f40 +#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003 +#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001 +#define CYFLD_SCB_I2C_START__OFFSET 0x00000005 +#define CYFLD_SCB_I2C_START__SIZE 0x00000001 +#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006 +#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001 +#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007 +#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009 +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000a +#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001 +#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000b +#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001 +#define CYREG_SCB0_INTR_S_SET 0x40060f44 +#define CYREG_SCB0_INTR_S_MASK 0x40060f48 +#define CYREG_SCB0_INTR_S_MASKED 0x40060f4c +#define CYREG_SCB0_INTR_TX 0x40060f80 +#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000 +#define CYFLD_SCB_TRIGGER__SIZE 0x00000001 +#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001 +#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001 +#define CYFLD_SCB_EMPTY__OFFSET 0x00000004 +#define CYFLD_SCB_EMPTY__SIZE 0x00000001 +#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005 +#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001 +#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006 +#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001 +#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007 +#define CYFLD_SCB_BLOCKED__SIZE 0x00000001 +#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008 +#define CYFLD_SCB_UART_NACK__SIZE 0x00000001 +#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009 +#define CYFLD_SCB_UART_DONE__SIZE 0x00000001 +#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000a +#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001 +#define CYREG_SCB0_INTR_TX_SET 0x40060f84 +#define CYREG_SCB0_INTR_TX_MASK 0x40060f88 +#define CYREG_SCB0_INTR_TX_MASKED 0x40060f8c +#define CYREG_SCB0_INTR_RX 0x40060fc0 +#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002 +#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001 +#define CYFLD_SCB_FULL__OFFSET 0x00000003 +#define CYFLD_SCB_FULL__SIZE 0x00000001 +#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009 +#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000a +#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001 +#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000b +#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001 +#define CYREG_SCB0_INTR_RX_SET 0x40060fc4 +#define CYREG_SCB0_INTR_RX_MASK 0x40060fc8 +#define CYREG_SCB0_INTR_RX_MASKED 0x40060fcc +#define CYDEV_SCB1_BASE 0x40070000 +#define CYDEV_SCB1_SIZE 0x00010000 +#define CYREG_SCB1_CTRL 0x40070000 +#define CYREG_SCB1_STATUS 0x40070004 +#define CYREG_SCB1_SPI_CTRL 0x40070020 +#define CYREG_SCB1_SPI_STATUS 0x40070024 +#define CYREG_SCB1_UART_CTRL 0x40070040 +#define CYREG_SCB1_UART_TX_CTRL 0x40070044 +#define CYREG_SCB1_UART_RX_CTRL 0x40070048 +#define CYREG_SCB1_UART_RX_STATUS 0x4007004c +#define CYREG_SCB1_I2C_CTRL 0x40070060 +#define CYREG_SCB1_I2C_STATUS 0x40070064 +#define CYREG_SCB1_I2C_M_CMD 0x40070068 +#define CYREG_SCB1_I2C_S_CMD 0x4007006c +#define CYREG_SCB1_I2C_CFG 0x40070070 +#define CYREG_SCB1_BIST_CONTROL 0x40070100 +#define CYREG_SCB1_BIST_DATA 0x40070104 +#define CYREG_SCB1_TX_CTRL 0x40070200 +#define CYREG_SCB1_TX_FIFO_CTRL 0x40070204 +#define CYREG_SCB1_TX_FIFO_STATUS 0x40070208 +#define CYREG_SCB1_TX_FIFO_WR 0x40070240 +#define CYREG_SCB1_RX_CTRL 0x40070300 +#define CYREG_SCB1_RX_FIFO_CTRL 0x40070304 +#define CYREG_SCB1_RX_FIFO_STATUS 0x40070308 +#define CYREG_SCB1_RX_MATCH 0x40070310 +#define CYREG_SCB1_RX_FIFO_RD 0x40070340 +#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40070344 +#define CYREG_SCB1_EZ_DATA00 0x40070400 +#define CYREG_SCB1_EZ_DATA01 0x40070404 +#define CYREG_SCB1_EZ_DATA02 0x40070408 +#define CYREG_SCB1_EZ_DATA03 0x4007040c +#define CYREG_SCB1_EZ_DATA04 0x40070410 +#define CYREG_SCB1_EZ_DATA05 0x40070414 +#define CYREG_SCB1_EZ_DATA06 0x40070418 +#define CYREG_SCB1_EZ_DATA07 0x4007041c +#define CYREG_SCB1_EZ_DATA08 0x40070420 +#define CYREG_SCB1_EZ_DATA09 0x40070424 +#define CYREG_SCB1_EZ_DATA10 0x40070428 +#define CYREG_SCB1_EZ_DATA11 0x4007042c +#define CYREG_SCB1_EZ_DATA12 0x40070430 +#define CYREG_SCB1_EZ_DATA13 0x40070434 +#define CYREG_SCB1_EZ_DATA14 0x40070438 +#define CYREG_SCB1_EZ_DATA15 0x4007043c +#define CYREG_SCB1_EZ_DATA16 0x40070440 +#define CYREG_SCB1_EZ_DATA17 0x40070444 +#define CYREG_SCB1_EZ_DATA18 0x40070448 +#define CYREG_SCB1_EZ_DATA19 0x4007044c +#define CYREG_SCB1_EZ_DATA20 0x40070450 +#define CYREG_SCB1_EZ_DATA21 0x40070454 +#define CYREG_SCB1_EZ_DATA22 0x40070458 +#define CYREG_SCB1_EZ_DATA23 0x4007045c +#define CYREG_SCB1_EZ_DATA24 0x40070460 +#define CYREG_SCB1_EZ_DATA25 0x40070464 +#define CYREG_SCB1_EZ_DATA26 0x40070468 +#define CYREG_SCB1_EZ_DATA27 0x4007046c +#define CYREG_SCB1_EZ_DATA28 0x40070470 +#define CYREG_SCB1_EZ_DATA29 0x40070474 +#define CYREG_SCB1_EZ_DATA30 0x40070478 +#define CYREG_SCB1_EZ_DATA31 0x4007047c +#define CYREG_SCB1_INTR_CAUSE 0x40070e00 +#define CYREG_SCB1_INTR_I2C_EC 0x40070e80 +#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40070e88 +#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40070e8c +#define CYREG_SCB1_INTR_SPI_EC 0x40070ec0 +#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40070ec8 +#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40070ecc +#define CYREG_SCB1_INTR_M 0x40070f00 +#define CYREG_SCB1_INTR_M_SET 0x40070f04 +#define CYREG_SCB1_INTR_M_MASK 0x40070f08 +#define CYREG_SCB1_INTR_M_MASKED 0x40070f0c +#define CYREG_SCB1_INTR_S 0x40070f40 +#define CYREG_SCB1_INTR_S_SET 0x40070f44 +#define CYREG_SCB1_INTR_S_MASK 0x40070f48 +#define CYREG_SCB1_INTR_S_MASKED 0x40070f4c +#define CYREG_SCB1_INTR_TX 0x40070f80 +#define CYREG_SCB1_INTR_TX_SET 0x40070f84 +#define CYREG_SCB1_INTR_TX_MASK 0x40070f88 +#define CYREG_SCB1_INTR_TX_MASKED 0x40070f8c +#define CYREG_SCB1_INTR_RX 0x40070fc0 +#define CYREG_SCB1_INTR_RX_SET 0x40070fc4 +#define CYREG_SCB1_INTR_RX_MASK 0x40070fc8 +#define CYREG_SCB1_INTR_RX_MASKED 0x40070fcc +#define CYDEV_CSD_BASE 0x40080000 +#define CYDEV_CSD_SIZE 0x00010000 +#define CYREG_CSD_ID 0x40080000 +#define CYFLD_CSD_ID__OFFSET 0x00000000 +#define CYFLD_CSD_ID__SIZE 0x00000010 +#define CYFLD_CSD_REVISION__OFFSET 0x00000010 +#define CYFLD_CSD_REVISION__SIZE 0x00000010 +#define CYREG_CSD_CONFIG 0x40080004 +#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000000 +#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001 +#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x00000001 +#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001 +#define CYFLD_CSD_PRS_CLEAR__OFFSET 0x00000005 +#define CYFLD_CSD_PRS_CLEAR__SIZE 0x00000001 +#define CYFLD_CSD_PRS_SELECT__OFFSET 0x00000006 +#define CYFLD_CSD_PRS_SELECT__SIZE 0x00000001 +#define CYVAL_CSD_PRS_SELECT_DIV2 0x00000000 +#define CYVAL_CSD_PRS_SELECT_PRS 0x00000001 +#define CYFLD_CSD_PRS_12_8__OFFSET 0x00000007 +#define CYFLD_CSD_PRS_12_8__SIZE 0x00000001 +#define CYVAL_CSD_PRS_12_8_8B 0x00000000 +#define CYVAL_CSD_PRS_12_8_12B 0x00000001 +#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x00000008 +#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001 +#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000009 +#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002 +#define CYFLD_CSD_SENSE_COMP_BW__OFFSET 0x0000000b +#define CYFLD_CSD_SENSE_COMP_BW__SIZE 0x00000001 +#define CYVAL_CSD_SENSE_COMP_BW_LOW 0x00000000 +#define CYVAL_CSD_SENSE_COMP_BW_HIGH 0x00000001 +#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000c +#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001 +#define CYFLD_CSD_REFBUF_EN__OFFSET 0x0000000d +#define CYFLD_CSD_REFBUF_EN__SIZE 0x00000001 +#define CYFLD_CSD_COMP_MODE__OFFSET 0x0000000e +#define CYFLD_CSD_COMP_MODE__SIZE 0x00000001 +#define CYVAL_CSD_COMP_MODE_CHARGE_BUF 0x00000000 +#define CYVAL_CSD_COMP_MODE_CHARGE_IO 0x00000001 +#define CYFLD_CSD_COMP_PIN__OFFSET 0x0000000f +#define CYFLD_CSD_COMP_PIN__SIZE 0x00000001 +#define CYVAL_CSD_COMP_PIN_CHANNEL1 0x00000000 +#define CYVAL_CSD_COMP_PIN_CHANNEL2 0x00000001 +#define CYFLD_CSD_POLARITY__OFFSET 0x00000010 +#define CYFLD_CSD_POLARITY__SIZE 0x00000001 +#define CYVAL_CSD_POLARITY_VSSIO 0x00000000 +#define CYVAL_CSD_POLARITY_VDDIO 0x00000001 +#define CYFLD_CSD_POLARITY2__OFFSET 0x00000011 +#define CYFLD_CSD_POLARITY2__SIZE 0x00000001 +#define CYVAL_CSD_POLARITY2_VSSIO 0x00000000 +#define CYVAL_CSD_POLARITY2_VDDIO 0x00000001 +#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012 +#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001 +#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000 +#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001 +#define CYFLD_CSD_SENSE_COMP_EN__OFFSET 0x00000013 +#define CYFLD_CSD_SENSE_COMP_EN__SIZE 0x00000001 +#define CYFLD_CSD_REBUF_OUTSEL__OFFSET 0x00000015 +#define CYFLD_CSD_REBUF_OUTSEL__SIZE 0x00000001 +#define CYVAL_CSD_REBUF_OUTSEL_AMUXA 0x00000000 +#define CYVAL_CSD_REBUF_OUTSEL_AMUXB 0x00000001 +#define CYFLD_CSD_SENSE_INSEL__OFFSET 0x00000016 +#define CYFLD_CSD_SENSE_INSEL__SIZE 0x00000001 +#define CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 0x00000000 +#define CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA 0x00000001 +#define CYFLD_CSD_REFBUF_DRV__OFFSET 0x00000017 +#define CYFLD_CSD_REFBUF_DRV__SIZE 0x00000002 +#define CYVAL_CSD_REFBUF_DRV_OFF 0x00000000 +#define CYVAL_CSD_REFBUF_DRV_DRV_1 0x00000001 +#define CYVAL_CSD_REFBUF_DRV_DRV_2 0x00000002 +#define CYVAL_CSD_REFBUF_DRV_DRV_3 0x00000003 +#define CYFLD_CSD_DDFTSEL__OFFSET 0x0000001a +#define CYFLD_CSD_DDFTSEL__SIZE 0x00000003 +#define CYVAL_CSD_DDFTSEL_NORMAL 0x00000000 +#define CYVAL_CSD_DDFTSEL_CSD_SENSE 0x00000001 +#define CYVAL_CSD_DDFTSEL_CSD_SHIELD 0x00000002 +#define CYVAL_CSD_DDFTSEL_CLK_SAMPLE 0x00000003 +#define CYVAL_CSD_DDFTSEL_COMP_OUT 0x00000004 +#define CYFLD_CSD_ADFTEN__OFFSET 0x0000001d +#define CYFLD_CSD_ADFTEN__SIZE 0x00000001 +#define CYFLD_CSD_DDFTCOMP__OFFSET 0x0000001e +#define CYFLD_CSD_DDFTCOMP__SIZE 0x00000001 +#define CYVAL_CSD_DDFTCOMP_REFBUFCOMP 0x00000000 +#define CYVAL_CSD_DDFTCOMP_SENSECOMP 0x00000001 +#define CYFLD_CSD_ENABLE__OFFSET 0x0000001f +#define CYFLD_CSD_ENABLE__SIZE 0x00000001 +#define CYREG_CSD_IDAC 0x40080008 +#define CYFLD_CSD_IDAC1__OFFSET 0x00000000 +#define CYFLD_CSD_IDAC1__SIZE 0x00000008 +#define CYFLD_CSD_IDAC1_MODE__OFFSET 0x00000008 +#define CYFLD_CSD_IDAC1_MODE__SIZE 0x00000002 +#define CYVAL_CSD_IDAC1_MODE_OFF 0x00000000 +#define CYVAL_CSD_IDAC1_MODE_FIXED 0x00000001 +#define CYVAL_CSD_IDAC1_MODE_VARIABLE 0x00000002 +#define CYVAL_CSD_IDAC1_MODE_DSI 0x00000003 +#define CYFLD_CSD_IDAC1_RANGE__OFFSET 0x0000000a +#define CYFLD_CSD_IDAC1_RANGE__SIZE 0x00000001 +#define CYVAL_CSD_IDAC1_RANGE_4X 0x00000000 +#define CYVAL_CSD_IDAC1_RANGE_8X 0x00000001 +#define CYFLD_CSD_IDAC2__OFFSET 0x00000010 +#define CYFLD_CSD_IDAC2__SIZE 0x00000007 +#define CYFLD_CSD_IDAC2_MODE__OFFSET 0x00000018 +#define CYFLD_CSD_IDAC2_MODE__SIZE 0x00000002 +#define CYVAL_CSD_IDAC2_MODE_OFF 0x00000000 +#define CYVAL_CSD_IDAC2_MODE_FIXED 0x00000001 +#define CYVAL_CSD_IDAC2_MODE_VARIABLE 0x00000002 +#define CYVAL_CSD_IDAC2_MODE_DSI 0x00000003 +#define CYFLD_CSD_IDAC2_RANGE__OFFSET 0x0000001a +#define CYFLD_CSD_IDAC2_RANGE__SIZE 0x00000001 +#define CYVAL_CSD_IDAC2_RANGE_4X 0x00000000 +#define CYVAL_CSD_IDAC2_RANGE_8X 0x00000001 +#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001e +#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001 +#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000 +#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001 +#define CYREG_CSD_COUNTER 0x4008000c +#define CYFLD_CSD_COUNTER__OFFSET 0x00000000 +#define CYFLD_CSD_COUNTER__SIZE 0x00000010 +#define CYFLD_CSD_PERIOD__OFFSET 0x00000010 +#define CYFLD_CSD_PERIOD__SIZE 0x00000010 +#define CYREG_CSD_STATUS 0x40080010 +#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000 +#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001 +#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001 +#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001 +#define CYFLD_CSD_COMP_OUT__OFFSET 0x00000002 +#define CYFLD_CSD_COMP_OUT__SIZE 0x00000001 +#define CYVAL_CSD_COMP_OUT_C_LT_VREF 0x00000000 +#define CYVAL_CSD_COMP_OUT_C_GT_VREF 0x00000001 +#define CYFLD_CSD_SAMPLE__OFFSET 0x00000003 +#define CYFLD_CSD_SAMPLE__SIZE 0x00000001 +#define CYREG_CSD_INTR 0x40080014 +#define CYFLD_CSD_CSD__OFFSET 0x00000000 +#define CYFLD_CSD_CSD__SIZE 0x00000001 +#define CYREG_CSD_INTR_SET 0x40080018 +#define CYREG_CSD_TRIM1 0x4008ff00 +#define CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET 0x00000000 +#define CYFLD_CSD_IDAC1_SRC_TRIM__SIZE 0x00000004 +#define CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET 0x00000004 +#define CYFLD_CSD_IDAC2_SRC_TRIM__SIZE 0x00000004 +#define CYREG_CSD_TRIM2 0x4008ff04 +#define CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET 0x00000000 +#define CYFLD_CSD_IDAC1_SNK_TRIM__SIZE 0x00000004 +#define CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET 0x00000004 +#define CYFLD_CSD_IDAC2_SNK_TRIM__SIZE 0x00000004 +#define CYDEV_LCD_BASE 0x40090000 +#define CYDEV_LCD_SIZE 0x00010000 +#define CYREG_LCD_ID 0x40090000 +#define CYFLD_LCD_ID__OFFSET 0x00000000 +#define CYFLD_LCD_ID__SIZE 0x00000010 +#define CYFLD_LCD_REVISION__OFFSET 0x00000010 +#define CYFLD_LCD_REVISION__SIZE 0x00000010 +#define CYREG_LCD_DIVIDER 0x40090004 +#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000 +#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010 +#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010 +#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010 +#define CYREG_LCD_CONTROL 0x40090008 +#define CYFLD_LCD_LS_EN__OFFSET 0x00000000 +#define CYFLD_LCD_LS_EN__SIZE 0x00000001 +#define CYFLD_LCD_HS_EN__OFFSET 0x00000001 +#define CYFLD_LCD_HS_EN__SIZE 0x00000001 +#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002 +#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001 +#define CYVAL_LCD_LCD_MODE_LS 0x00000000 +#define CYVAL_LCD_LCD_MODE_HS 0x00000001 +#define CYFLD_LCD_TYPE__OFFSET 0x00000003 +#define CYFLD_LCD_TYPE__SIZE 0x00000001 +#define CYVAL_LCD_TYPE_A 0x00000000 +#define CYVAL_LCD_TYPE_B 0x00000001 +#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004 +#define CYFLD_LCD_OP_MODE__SIZE 0x00000001 +#define CYVAL_LCD_OP_MODE_PWM 0x00000000 +#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001 +#define CYFLD_LCD_BIAS__OFFSET 0x00000005 +#define CYFLD_LCD_BIAS__SIZE 0x00000002 +#define CYVAL_LCD_BIAS_HALF 0x00000000 +#define CYVAL_LCD_BIAS_THIRD 0x00000001 +#define CYVAL_LCD_BIAS_FOURTH 0x00000002 +#define CYVAL_LCD_BIAS_FIFTH 0x00000003 +#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008 +#define CYFLD_LCD_COM_NUM__SIZE 0x00000004 +#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001f +#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001 +#define CYREG_LCD_DATA00 0x40090100 +#define CYFLD_LCD_DATA__OFFSET 0x00000000 +#define CYFLD_LCD_DATA__SIZE 0x00000020 +#define CYREG_LCD_DATA01 0x40090104 +#define CYREG_LCD_DATA02 0x40090108 +#define CYREG_LCD_DATA03 0x4009010c +#define CYREG_LCD_DATA04 0x40090110 +#define CYDEV_LPCOMP_BASE 0x400a0000 +#define CYDEV_LPCOMP_SIZE 0x00010000 +#define CYREG_LPCOMP_ID 0x400a0000 +#define CYFLD_LPCOMP_ID__OFFSET 0x00000000 +#define CYFLD_LPCOMP_ID__SIZE 0x00000010 +#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010 +#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010 +#define CYREG_LPCOMP_CONFIG 0x400a0004 +#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000 +#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002 +#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000 +#define CYVAL_LPCOMP_MODE1_FAST 0x00000001 +#define CYVAL_LPCOMP_MODE1_ULP 0x00000002 +#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002 +#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001 +#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003 +#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001 +#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004 +#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002 +#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000 +#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001 +#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002 +#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003 +#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006 +#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001 +#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007 +#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001 +#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008 +#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002 +#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000 +#define CYVAL_LPCOMP_MODE2_FAST 0x00000001 +#define CYVAL_LPCOMP_MODE2_ULP 0x00000002 +#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000a +#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001 +#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000b +#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001 +#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000c +#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002 +#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000 +#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001 +#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002 +#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003 +#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000e +#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001 +#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000f +#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001 +#define CYREG_LPCOMP_DFT 0x400a0008 +#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000 +#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001 +#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001 +#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001 +#define CYREG_LPCOMP_INTR 0x400a000c +#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001 +#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001 +#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001 +#define CYREG_LPCOMP_INTR_SET 0x400a0010 +#define CYREG_LPCOMP_TRIM1 0x400aff00 +#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM2 0x400aff04 +#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM3 0x400aff08 +#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM4 0x400aff0c +#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005 +#define CYREG_PWR_CONTROL 0x400b0000 +#define CYFLD__POWER_MODE__OFFSET 0x00000000 +#define CYFLD__POWER_MODE__SIZE 0x00000004 +#define CYVAL__POWER_MODE_RESET 0x00000000 +#define CYVAL__POWER_MODE_ACTIVE 0x00000001 +#define CYVAL__POWER_MODE_SLEEP 0x00000002 +#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003 +#define CYVAL__POWER_MODE_HIBERNATE 0x00000004 +#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004 +#define CYFLD__DEBUG_SESSION__SIZE 0x00000001 +#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000 +#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001 +#define CYFLD__LPM_READY__OFFSET 0x00000005 +#define CYFLD__LPM_READY__SIZE 0x00000001 +#define CYFLD__EXT_VCCD__OFFSET 0x00000017 +#define CYFLD__EXT_VCCD__SIZE 0x00000001 +#define CYFLD__HVMON_ENABLE__OFFSET 0x00000018 +#define CYFLD__HVMON_ENABLE__SIZE 0x00000001 +#define CYFLD__HVMON_RELOAD__OFFSET 0x00000019 +#define CYFLD__HVMON_RELOAD__SIZE 0x00000001 +#define CYFLD__FIMO_DISABLE__OFFSET 0x0000001b +#define CYFLD__FIMO_DISABLE__SIZE 0x00000001 +#define CYFLD__HIBERNATE_DISABLE__OFFSET 0x0000001c +#define CYFLD__HIBERNATE_DISABLE__SIZE 0x00000001 +#define CYFLD__LFCLK_SHORT__OFFSET 0x0000001d +#define CYFLD__LFCLK_SHORT__SIZE 0x00000001 +#define CYFLD__HIBERNATE__OFFSET 0x0000001f +#define CYFLD__HIBERNATE__SIZE 0x00000001 +#define CYVAL__HIBERNATE_DEEP_SLEEP 0x00000000 +#define CYVAL__HIBERNATE_HIBERNATE 0x00000001 +#define CYREG_PWR_INTR 0x400b0004 +#define CYFLD__LVD__OFFSET 0x00000001 +#define CYFLD__LVD__SIZE 0x00000001 +#define CYREG_PWR_INTR_MASK 0x400b0008 +#define CYREG_PWR_KEY_DELAY 0x400b000c +#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000 +#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000a +#define CYREG_PWR_PWRSYS_CONFIG 0x400b0010 +#define CYFLD__HIB_TEST_EN__OFFSET 0x00000008 +#define CYFLD__HIB_TEST_EN__SIZE 0x00000001 +#define CYFLD__HIB_TEST_REP__OFFSET 0x00000009 +#define CYFLD__HIB_TEST_REP__SIZE 0x00000001 +#define CYREG_PWR_BG_CONFIG 0x400b0014 +#define CYFLD__BG_DFT_EN__OFFSET 0x00000000 +#define CYFLD__BG_DFT_EN__SIZE 0x00000001 +#define CYFLD__BG_DFT_VREF_SEL__OFFSET 0x00000001 +#define CYFLD__BG_DFT_VREF_SEL__SIZE 0x00000004 +#define CYFLD__BG_DFT_CORE_SEL__OFFSET 0x00000005 +#define CYFLD__BG_DFT_CORE_SEL__SIZE 0x00000001 +#define CYFLD__BG_DFT_ICORE_SEL__OFFSET 0x00000006 +#define CYFLD__BG_DFT_ICORE_SEL__SIZE 0x00000002 +#define CYFLD__BG_DFT_VCORE_SEL__OFFSET 0x00000008 +#define CYFLD__BG_DFT_VCORE_SEL__SIZE 0x00000001 +#define CYFLD__VREF_EN__OFFSET 0x00000010 +#define CYFLD__VREF_EN__SIZE 0x00000003 +#define CYREG_PWR_VMON_CONFIG 0x400b0018 +#define CYFLD__LVD_EN__OFFSET 0x00000000 +#define CYFLD__LVD_EN__SIZE 0x00000001 +#define CYFLD__LVD_SEL__OFFSET 0x00000001 +#define CYFLD__LVD_SEL__SIZE 0x00000004 +#define CYFLD__VMON_DDFT_SEL__OFFSET 0x00000005 +#define CYFLD__VMON_DDFT_SEL__SIZE 0x00000003 +#define CYFLD__VMON_ADFT_SEL__OFFSET 0x00000008 +#define CYFLD__VMON_ADFT_SEL__SIZE 0x00000002 +#define CYREG_PWR_DFT_SELECT 0x400b001c +#define CYFLD__TVMON1_SEL__OFFSET 0x00000000 +#define CYFLD__TVMON1_SEL__SIZE 0x00000003 +#define CYFLD__TVMON2_SEL__OFFSET 0x00000003 +#define CYFLD__TVMON2_SEL__SIZE 0x00000003 +#define CYFLD__BYPASS__OFFSET 0x00000006 +#define CYFLD__BYPASS__SIZE 0x00000001 +#define CYFLD__ACTIVE_EN__OFFSET 0x00000007 +#define CYFLD__ACTIVE_EN__SIZE 0x00000001 +#define CYFLD__ACTIVE_INRUSH_DIS__OFFSET 0x00000008 +#define CYFLD__ACTIVE_INRUSH_DIS__SIZE 0x00000001 +#define CYFLD__LPCOMP_DIS__OFFSET 0x00000009 +#define CYFLD__LPCOMP_DIS__SIZE 0x00000001 +#define CYFLD__BLEED_EN__OFFSET 0x0000000a +#define CYFLD__BLEED_EN__SIZE 0x00000001 +#define CYFLD__IPOR_EN__OFFSET 0x0000000b +#define CYFLD__IPOR_EN__SIZE 0x00000001 +#define CYFLD__POWER_UP_RAW_BYP__OFFSET 0x0000000c +#define CYFLD__POWER_UP_RAW_BYP__SIZE 0x00000001 +#define CYFLD__POWER_UP_RAW_CTL__OFFSET 0x0000000d +#define CYFLD__POWER_UP_RAW_CTL__SIZE 0x00000001 +#define CYFLD__DEEPSLEEP_EN__OFFSET 0x0000000e +#define CYFLD__DEEPSLEEP_EN__SIZE 0x00000001 +#define CYFLD__RSVD_BYPASS__OFFSET 0x0000000f +#define CYFLD__RSVD_BYPASS__SIZE 0x00000001 +#define CYFLD__NWELL_OPEN__OFFSET 0x00000010 +#define CYFLD__NWELL_OPEN__SIZE 0x00000001 +#define CYFLD__HIBERNATE_OPEN__OFFSET 0x00000011 +#define CYFLD__HIBERNATE_OPEN__SIZE 0x00000001 +#define CYFLD__DEEPSLEEP_OPEN__OFFSET 0x00000012 +#define CYFLD__DEEPSLEEP_OPEN__SIZE 0x00000001 +#define CYFLD__QUIET_OPEN__OFFSET 0x00000013 +#define CYFLD__QUIET_OPEN__SIZE 0x00000001 +#define CYFLD__LFCLK_OPEN__OFFSET 0x00000014 +#define CYFLD__LFCLK_OPEN__SIZE 0x00000001 +#define CYFLD__QUIET_EN__OFFSET 0x00000016 +#define CYFLD__QUIET_EN__SIZE 0x00000001 +#define CYFLD__BREF_EN__OFFSET 0x00000017 +#define CYFLD__BREF_EN__SIZE 0x00000001 +#define CYFLD__BREF_OUTEN__OFFSET 0x00000018 +#define CYFLD__BREF_OUTEN__SIZE 0x00000001 +#define CYFLD__BREF_REFSW__OFFSET 0x00000019 +#define CYFLD__BREF_REFSW__SIZE 0x00000001 +#define CYFLD__BREF_TESTMODE__OFFSET 0x0000001a +#define CYFLD__BREF_TESTMODE__SIZE 0x00000001 +#define CYFLD__NWELL_DIS__OFFSET 0x0000001b +#define CYFLD__NWELL_DIS__SIZE 0x00000001 +#define CYFLD__HVMON_DFT_OVR__OFFSET 0x0000001c +#define CYFLD__HVMON_DFT_OVR__SIZE 0x00000001 +#define CYFLD__IMO_REFGEN_DIS__OFFSET 0x0000001d +#define CYFLD__IMO_REFGEN_DIS__SIZE 0x00000001 +#define CYFLD__POWER_UP_ACTIVE__OFFSET 0x0000001e +#define CYFLD__POWER_UP_ACTIVE__SIZE 0x00000001 +#define CYFLD__POWER_UP_HIBDPSLP__OFFSET 0x0000001f +#define CYFLD__POWER_UP_HIBDPSLP__SIZE 0x00000001 +#define CYREG_PWR_DDFT_SELECT 0x400b0020 +#define CYFLD__DDFT1_SEL__OFFSET 0x00000000 +#define CYFLD__DDFT1_SEL__SIZE 0x00000004 +#define CYFLD__DDFT2_SEL__OFFSET 0x00000004 +#define CYFLD__DDFT2_SEL__SIZE 0x00000004 +#define CYREG_PWR_DFT_KEY 0x400b0024 +#define CYFLD__KEY16__OFFSET 0x00000000 +#define CYFLD__KEY16__SIZE 0x00000010 +#define CYFLD__HBOD_OFF_AWAKE__OFFSET 0x00000010 +#define CYFLD__HBOD_OFF_AWAKE__SIZE 0x00000001 +#define CYFLD__BODS_OFF__OFFSET 0x00000011 +#define CYFLD__BODS_OFF__SIZE 0x00000001 +#define CYFLD__DFT_MODE__OFFSET 0x00000012 +#define CYFLD__DFT_MODE__SIZE 0x00000001 +#define CYFLD__IO_DISABLE_BYPASS__OFFSET 0x00000013 +#define CYFLD__IO_DISABLE_BYPASS__SIZE 0x00000001 +#define CYFLD__VMON_PD__OFFSET 0x00000014 +#define CYFLD__VMON_PD__SIZE 0x00000001 +#define CYREG_PWR_BOD_KEY 0x400b0028 +#define CYREG_PWR_STOP 0x400b002c +#define CYFLD__TOKEN__OFFSET 0x00000000 +#define CYFLD__TOKEN__SIZE 0x00000008 +#define CYFLD__UNLOCK__OFFSET 0x00000008 +#define CYFLD__UNLOCK__SIZE 0x00000008 +#define CYFLD__POLARITY__OFFSET 0x00000010 +#define CYFLD__POLARITY__SIZE 0x00000001 +#define CYFLD__FREEZE__OFFSET 0x00000011 +#define CYFLD__FREEZE__SIZE 0x00000001 +#define CYFLD__STOP__OFFSET 0x0000001f +#define CYFLD__STOP__SIZE 0x00000001 +#define CYREG_CLK_SELECT 0x400b0100 +#define CYFLD__DIRECT_SEL__OFFSET 0x00000000 +#define CYFLD__DIRECT_SEL__SIZE 0x00000003 +#define CYVAL__DIRECT_SEL_IMO 0x00000000 +#define CYVAL__DIRECT_SEL_EXTCLK 0x00000001 +#define CYVAL__DIRECT_SEL_ECO 0x00000002 +#define CYVAL__DIRECT_SEL_DSI0 0x00000004 +#define CYVAL__DIRECT_SEL_DSI1 0x00000005 +#define CYVAL__DIRECT_SEL_DSI2 0x00000006 +#define CYVAL__DIRECT_SEL_DSI3 0x00000007 +#define CYFLD__DBL_SEL__OFFSET 0x00000003 +#define CYFLD__DBL_SEL__SIZE 0x00000003 +#define CYVAL__DBL_SEL_IMO 0x00000000 +#define CYVAL__DBL_SEL_EXTCLK 0x00000001 +#define CYVAL__DBL_SEL_ECO 0x00000002 +#define CYVAL__DBL_SEL_DSI0 0x00000004 +#define CYVAL__DBL_SEL_DSI1 0x00000005 +#define CYVAL__DBL_SEL_DSI2 0x00000006 +#define CYVAL__DBL_SEL_DSI3 0x00000007 +#define CYFLD__PLL_SEL__OFFSET 0x00000006 +#define CYFLD__PLL_SEL__SIZE 0x00000003 +#define CYVAL__PLL_SEL_IMO 0x00000000 +#define CYVAL__PLL_SEL_EXTCLK 0x00000001 +#define CYVAL__PLL_SEL_ECO 0x00000002 +#define CYVAL__PLL_SEL_DPLL 0x00000003 +#define CYVAL__PLL_SEL_DSI0 0x00000004 +#define CYVAL__PLL_SEL_DSI1 0x00000005 +#define CYVAL__PLL_SEL_DSI2 0x00000006 +#define CYVAL__PLL_SEL_DSI3 0x00000007 +#define CYFLD__DPLLIN_SEL__OFFSET 0x00000009 +#define CYFLD__DPLLIN_SEL__SIZE 0x00000003 +#define CYVAL__DPLLIN_SEL_IMO 0x00000000 +#define CYVAL__DPLLIN_SEL_EXTCLK 0x00000001 +#define CYVAL__DPLLIN_SEL_ECO 0x00000002 +#define CYVAL__DPLLIN_SEL_DSI0 0x00000004 +#define CYVAL__DPLLIN_SEL_DSI1 0x00000005 +#define CYVAL__DPLLIN_SEL_DSI2 0x00000006 +#define CYVAL__DPLLIN_SEL_DSI3 0x00000007 +#define CYFLD__DPLLREF_SEL__OFFSET 0x0000000c +#define CYFLD__DPLLREF_SEL__SIZE 0x00000002 +#define CYVAL__DPLLREF_SEL_DSI0 0x00000000 +#define CYVAL__DPLLREF_SEL_DSI1 0x00000001 +#define CYVAL__DPLLREF_SEL_DSI2 0x00000002 +#define CYVAL__DPLLREF_SEL_DSI3 0x00000003 +#define CYFLD__WDT_LOCK__OFFSET 0x0000000e +#define CYFLD__WDT_LOCK__SIZE 0x00000002 +#define CYVAL__WDT_LOCK_NO_CHG 0x00000000 +#define CYVAL__WDT_LOCK_CLR0 0x00000001 +#define CYVAL__WDT_LOCK_CLR1 0x00000002 +#define CYVAL__WDT_LOCK_SET01 0x00000003 +#define CYFLD__HFCLK_SEL__OFFSET 0x00000010 +#define CYFLD__HFCLK_SEL__SIZE 0x00000002 +#define CYVAL__HFCLK_SEL_DIRECT_SEL 0x00000000 +#define CYVAL__HFCLK_SEL_DBL 0x00000001 +#define CYVAL__HFCLK_SEL_PLL 0x00000002 +#define CYFLD__HALF_EN__OFFSET 0x00000012 +#define CYFLD__HALF_EN__SIZE 0x00000001 +#define CYFLD__SYSCLK_DIV__OFFSET 0x00000013 +#define CYFLD__SYSCLK_DIV__SIZE 0x00000003 +#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000 +#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001 +#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002 +#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003 +#define CYVAL__SYSCLK_DIV_DIV_BY_16 0x00000004 +#define CYVAL__SYSCLK_DIV_DIV_BY_32 0x00000005 +#define CYVAL__SYSCLK_DIV_DIV_BY_64 0x00000006 +#define CYVAL__SYSCLK_DIV_DIV_BY_128 0x00000007 +#define CYREG_CLK_ILO_CONFIG 0x400b0104 +#define CYFLD__PD_MODE__OFFSET 0x00000000 +#define CYFLD__PD_MODE__SIZE 0x00000001 +#define CYVAL__PD_MODE_SLEEP 0x00000000 +#define CYVAL__PD_MODE_COMA 0x00000001 +#define CYFLD__TURBO__OFFSET 0x00000001 +#define CYFLD__TURBO__SIZE 0x00000001 +#define CYFLD__SATBIAS__OFFSET 0x00000002 +#define CYFLD__SATBIAS__SIZE 0x00000001 +#define CYVAL__SATBIAS_SATURATED 0x00000000 +#define CYVAL__SATBIAS_SUBTHRESHOLD 0x00000001 +#define CYFLD__ENABLE__OFFSET 0x0000001f +#define CYFLD__ENABLE__SIZE 0x00000001 +#define CYREG_CLK_IMO_CONFIG 0x400b0108 +#define CYFLD__FLASHPUMP_SEL__OFFSET 0x00000016 +#define CYFLD__FLASHPUMP_SEL__SIZE 0x00000001 +#define CYVAL__FLASHPUMP_SEL_GND 0x00000000 +#define CYVAL__FLASHPUMP_SEL_CLK36 0x00000001 +#define CYFLD__EN_FASTBIAS__OFFSET 0x00000017 +#define CYFLD__EN_FASTBIAS__SIZE 0x00000001 +#define CYFLD__TEST_FASTBIAS__OFFSET 0x00000018 +#define CYFLD__TEST_FASTBIAS__SIZE 0x00000001 +#define CYFLD__PUMP_SEL__OFFSET 0x00000019 +#define CYFLD__PUMP_SEL__SIZE 0x00000003 +#define CYVAL__PUMP_SEL_GND 0x00000000 +#define CYVAL__PUMP_SEL_IMO 0x00000001 +#define CYVAL__PUMP_SEL_DBL 0x00000002 +#define CYVAL__PUMP_SEL_CLK36 0x00000003 +#define CYVAL__PUMP_SEL_FF1 0x00000004 +#define CYFLD__TEST_USB_MODE__OFFSET 0x0000001c +#define CYFLD__TEST_USB_MODE__SIZE 0x00000001 +#define CYFLD__EN_CLK36__OFFSET 0x0000001d +#define CYFLD__EN_CLK36__SIZE 0x00000001 +#define CYFLD__EN_CLK2X__OFFSET 0x0000001e +#define CYFLD__EN_CLK2X__SIZE 0x00000001 +#define CYREG_CLK_IMO_SPREAD 0x400b010c +#define CYFLD__SS_VALUE__OFFSET 0x00000000 +#define CYFLD__SS_VALUE__SIZE 0x00000005 +#define CYFLD__SS_MAX__OFFSET 0x00000008 +#define CYFLD__SS_MAX__SIZE 0x00000005 +#define CYFLD__SS_RANGE__OFFSET 0x0000001c +#define CYFLD__SS_RANGE__SIZE 0x00000002 +#define CYVAL__SS_RANGE_M1 0x00000000 +#define CYVAL__SS_RANGE_M2 0x00000001 +#define CYVAL__SS_RANGE_M4 0x00000002 +#define CYFLD__SS_MODE__OFFSET 0x0000001e +#define CYFLD__SS_MODE__SIZE 0x00000002 +#define CYVAL__SS_MODE_OFF 0x00000000 +#define CYVAL__SS_MODE_TRIANGLE 0x00000001 +#define CYVAL__SS_MODE_LFSR 0x00000002 +#define CYVAL__SS_MODE_DSI 0x00000003 +#define CYREG_CLK_DFT_SELECT 0x400b0110 +#define CYFLD__DFT_SEL1__OFFSET 0x00000000 +#define CYFLD__DFT_SEL1__SIZE 0x00000004 +#define CYVAL__DFT_SEL1_NC 0x00000000 +#define CYVAL__DFT_SEL1_ILO 0x00000001 +#define CYVAL__DFT_SEL1_WCO 0x00000002 +#define CYVAL__DFT_SEL1_IMO 0x00000003 +#define CYVAL__DFT_SEL1_ECO 0x00000004 +#define CYVAL__DFT_SEL1_PLL 0x00000005 +#define CYVAL__DFT_SEL1_DPLL_OUT 0x00000006 +#define CYVAL__DFT_SEL1_DPLL_REF 0x00000007 +#define CYVAL__DFT_SEL1_DBL 0x00000008 +#define CYVAL__DFT_SEL1_IMO2X 0x00000009 +#define CYVAL__DFT_SEL1_IMO36 0x0000000a +#define CYVAL__DFT_SEL1_HFCLK 0x0000000b +#define CYVAL__DFT_SEL1_LFCLK 0x0000000c +#define CYVAL__DFT_SEL1_SYSCLK 0x0000000d +#define CYVAL__DFT_SEL1_EXTCLK 0x0000000e +#define CYVAL__DFT_SEL1_HALFSYSCLK 0x0000000f +#define CYFLD__DFT_DIV1__OFFSET 0x00000004 +#define CYFLD__DFT_DIV1__SIZE 0x00000002 +#define CYVAL__DFT_DIV1_NO_DIV 0x00000000 +#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001 +#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002 +#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003 +#define CYFLD__DFT_SEL2__OFFSET 0x00000008 +#define CYFLD__DFT_SEL2__SIZE 0x00000004 +#define CYVAL__DFT_SEL2_NC 0x00000000 +#define CYVAL__DFT_SEL2_ILO 0x00000001 +#define CYVAL__DFT_SEL2_WCO 0x00000002 +#define CYVAL__DFT_SEL2_IMO 0x00000003 +#define CYVAL__DFT_SEL2_ECO 0x00000004 +#define CYVAL__DFT_SEL2_PLL 0x00000005 +#define CYVAL__DFT_SEL2_DPLL_OUT 0x00000006 +#define CYVAL__DFT_SEL2_DPLL_REF 0x00000007 +#define CYVAL__DFT_SEL2_DBL 0x00000008 +#define CYVAL__DFT_SEL2_IMO2X 0x00000009 +#define CYVAL__DFT_SEL2_IMO36 0x0000000a +#define CYVAL__DFT_SEL2_HFCLK 0x0000000b +#define CYVAL__DFT_SEL2_LFCLK 0x0000000c +#define CYVAL__DFT_SEL2_SYSCLK 0x0000000d +#define CYVAL__DFT_SEL2_EXTCLK 0x0000000e +#define CYVAL__DFT_SEL2_HALFSYSCLK 0x0000000f +#define CYFLD__DFT_DIV2__OFFSET 0x0000000c +#define CYFLD__DFT_DIV2__SIZE 0x00000002 +#define CYVAL__DFT_DIV2_NO_DIV 0x00000000 +#define CYVAL__DFT_DIV2_DIV_BY_2 0x00000001 +#define CYVAL__DFT_DIV2_DIV_BY_4 0x00000002 +#define CYVAL__DFT_DIV2_DIV_BY_8 0x00000003 +#define CYREG_WDT_CTRLOW 0x400b0200 +#define CYFLD__WDT_CTR0__OFFSET 0x00000000 +#define CYFLD__WDT_CTR0__SIZE 0x00000010 +#define CYFLD__WDT_CTR1__OFFSET 0x00000010 +#define CYFLD__WDT_CTR1__SIZE 0x00000010 +#define CYREG_WDT_CTRHIGH 0x400b0204 +#define CYFLD__WDT_CTR2__OFFSET 0x00000000 +#define CYFLD__WDT_CTR2__SIZE 0x00000020 +#define CYREG_WDT_MATCH 0x400b0208 +#define CYFLD__WDT_MATCH0__OFFSET 0x00000000 +#define CYFLD__WDT_MATCH0__SIZE 0x00000010 +#define CYFLD__WDT_MATCH1__OFFSET 0x00000010 +#define CYFLD__WDT_MATCH1__SIZE 0x00000010 +#define CYREG_WDT_CONFIG 0x400b020c +#define CYFLD__WDT_MODE0__OFFSET 0x00000000 +#define CYFLD__WDT_MODE0__SIZE 0x00000002 +#define CYVAL__WDT_MODE0_NOTHING 0x00000000 +#define CYVAL__WDT_MODE0_INT 0x00000001 +#define CYVAL__WDT_MODE0_RESET 0x00000002 +#define CYVAL__WDT_MODE0_INT_THEN_RESET 0x00000003 +#define CYFLD__WDT_CLEAR0__OFFSET 0x00000002 +#define CYFLD__WDT_CLEAR0__SIZE 0x00000001 +#define CYFLD__WDT_CASCADE0_1__OFFSET 0x00000003 +#define CYFLD__WDT_CASCADE0_1__SIZE 0x00000001 +#define CYFLD__WDT_MODE1__OFFSET 0x00000008 +#define CYFLD__WDT_MODE1__SIZE 0x00000002 +#define CYVAL__WDT_MODE1_NOTHING 0x00000000 +#define CYVAL__WDT_MODE1_INT 0x00000001 +#define CYVAL__WDT_MODE1_RESET 0x00000002 +#define CYVAL__WDT_MODE1_INT_THEN_RESET 0x00000003 +#define CYFLD__WDT_CLEAR1__OFFSET 0x0000000a +#define CYFLD__WDT_CLEAR1__SIZE 0x00000001 +#define CYFLD__WDT_CASCADE1_2__OFFSET 0x0000000b +#define CYFLD__WDT_CASCADE1_2__SIZE 0x00000001 +#define CYFLD__WDT_MODE2__OFFSET 0x00000010 +#define CYFLD__WDT_MODE2__SIZE 0x00000001 +#define CYVAL__WDT_MODE2_NOTHING 0x00000000 +#define CYVAL__WDT_MODE2_INT 0x00000001 +#define CYFLD__WDT_BITS2__OFFSET 0x00000018 +#define CYFLD__WDT_BITS2__SIZE 0x00000005 +#define CYFLD__LFCLK_SEL__OFFSET 0x0000001e +#define CYFLD__LFCLK_SEL__SIZE 0x00000002 +#define CYREG_WDT_CONTROL 0x400b0210 +#define CYFLD__WDT_ENABLE0__OFFSET 0x00000000 +#define CYFLD__WDT_ENABLE0__SIZE 0x00000001 +#define CYFLD__WDT_ENABLED0__OFFSET 0x00000001 +#define CYFLD__WDT_ENABLED0__SIZE 0x00000001 +#define CYFLD__WDT_INT0__OFFSET 0x00000002 +#define CYFLD__WDT_INT0__SIZE 0x00000001 +#define CYFLD__WDT_RESET0__OFFSET 0x00000003 +#define CYFLD__WDT_RESET0__SIZE 0x00000001 +#define CYFLD__WDT_ENABLE1__OFFSET 0x00000008 +#define CYFLD__WDT_ENABLE1__SIZE 0x00000001 +#define CYFLD__WDT_ENABLED1__OFFSET 0x00000009 +#define CYFLD__WDT_ENABLED1__SIZE 0x00000001 +#define CYFLD__WDT_INT1__OFFSET 0x0000000a +#define CYFLD__WDT_INT1__SIZE 0x00000001 +#define CYFLD__WDT_RESET1__OFFSET 0x0000000b +#define CYFLD__WDT_RESET1__SIZE 0x00000001 +#define CYFLD__WDT_ENABLE2__OFFSET 0x00000010 +#define CYFLD__WDT_ENABLE2__SIZE 0x00000001 +#define CYFLD__WDT_ENABLED2__OFFSET 0x00000011 +#define CYFLD__WDT_ENABLED2__SIZE 0x00000001 +#define CYFLD__WDT_INT2__OFFSET 0x00000012 +#define CYFLD__WDT_INT2__SIZE 0x00000001 +#define CYFLD__WDT_RESET2__OFFSET 0x00000013 +#define CYFLD__WDT_RESET2__SIZE 0x00000001 +#define CYREG_RES_CAUSE 0x400b0300 +#define CYFLD__RESET_WDT__OFFSET 0x00000000 +#define CYFLD__RESET_WDT__SIZE 0x00000001 +#define CYFLD__RESET_DSBOD__OFFSET 0x00000001 +#define CYFLD__RESET_DSBOD__SIZE 0x00000001 +#define CYFLD__RESET_LOCKUP__OFFSET 0x00000002 +#define CYFLD__RESET_LOCKUP__SIZE 0x00000001 +#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003 +#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001 +#define CYFLD__RESET_SOFT__OFFSET 0x00000004 +#define CYFLD__RESET_SOFT__SIZE 0x00000001 +#define CYFLD__RESET_HVBOD__OFFSET 0x00000005 +#define CYFLD__RESET_HVBOD__SIZE 0x00000001 +#define CYFLD__RESET_PBOD__OFFSET 0x00000006 +#define CYFLD__RESET_PBOD__SIZE 0x00000001 +#define CYFLD__RESET_XRES__OFFSET 0x00000007 +#define CYFLD__RESET_XRES__SIZE 0x00000001 +#define CYREG_PWR_PWRSYS_TRIM1 0x400bff00 +#define CYFLD__HIB_BIAS_TRIM__OFFSET 0x00000000 +#define CYFLD__HIB_BIAS_TRIM__SIZE 0x00000003 +#define CYFLD__BOD_TURBO_THRESH__OFFSET 0x00000003 +#define CYFLD__BOD_TURBO_THRESH__SIZE 0x00000001 +#define CYFLD__BOD_TRIM_TRIP__OFFSET 0x00000004 +#define CYFLD__BOD_TRIM_TRIP__SIZE 0x00000004 +#define CYREG_PWR_PWRSYS_TRIM2 0x400bff04 +#define CYFLD__LFCLK_TRIM_LOAD__OFFSET 0x00000000 +#define CYFLD__LFCLK_TRIM_LOAD__SIZE 0x00000002 +#define CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET 0x00000002 +#define CYFLD__LFCLK_TRIM_VOLTAGE__SIZE 0x00000002 +#define CYFLD__DPSLP_TRIM_LOAD__OFFSET 0x00000004 +#define CYFLD__DPSLP_TRIM_LOAD__SIZE 0x00000002 +#define CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET 0x00000006 +#define CYFLD__DPSLP_TRIM_LEAKAGE__SIZE 0x00000001 +#define CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET 0x00000007 +#define CYFLD__DPSLP_TRIM_VOLTAGE__SIZE 0x00000001 +#define CYREG_PWR_PWRSYS_TRIM3 0x400bff08 +#define CYFLD__NWELL_TRIM__OFFSET 0x00000000 +#define CYFLD__NWELL_TRIM__SIZE 0x00000003 +#define CYFLD__QUIET_TRIM__OFFSET 0x00000003 +#define CYFLD__QUIET_TRIM__SIZE 0x00000005 +#define CYREG_PWR_PWRSYS_TRIM4 0x400bff0c +#define CYFLD__HIB_TRIM_NWELL__OFFSET 0x00000000 +#define CYFLD__HIB_TRIM_NWELL__SIZE 0x00000002 +#define CYFLD__HIB_TRIM_LEAKAGE__OFFSET 0x00000002 +#define CYFLD__HIB_TRIM_LEAKAGE__SIZE 0x00000001 +#define CYFLD__HIB_TRIM_VOLTAGE__OFFSET 0x00000003 +#define CYFLD__HIB_TRIM_VOLTAGE__SIZE 0x00000001 +#define CYFLD__HIB_TRIM_REFERENCE__OFFSET 0x00000004 +#define CYFLD__HIB_TRIM_REFERENCE__SIZE 0x00000002 +#define CYREG_PWR_BG_TRIM1 0x400bff10 +#define CYFLD__INL_TRIM_MAIN__OFFSET 0x00000000 +#define CYFLD__INL_TRIM_MAIN__SIZE 0x00000003 +#define CYFLD__INL_CROSS_MAIN__OFFSET 0x00000003 +#define CYFLD__INL_CROSS_MAIN__SIZE 0x00000004 +#define CYREG_PWR_BG_TRIM2 0x400bff14 +#define CYFLD__VCTAT_SLOPE__OFFSET 0x00000000 +#define CYFLD__VCTAT_SLOPE__SIZE 0x00000004 +#define CYFLD__VCTAT_VOLTAGE__OFFSET 0x00000004 +#define CYFLD__VCTAT_VOLTAGE__SIZE 0x00000002 +#define CYFLD__VCTAT_ENABLE__OFFSET 0x00000006 +#define CYFLD__VCTAT_ENABLE__SIZE 0x00000001 +#define CYFLD__VCTAT_VOLTAGE_MSB__OFFSET 0x00000007 +#define CYFLD__VCTAT_VOLTAGE_MSB__SIZE 0x00000001 +#define CYREG_PWR_BG_TRIM3 0x400bff18 +#define CYFLD__INL_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD__INL_TRIM_IMO__SIZE 0x00000003 +#define CYFLD__INL_CROSS_IMO__OFFSET 0x00000003 +#define CYFLD__INL_CROSS_IMO__SIZE 0x00000004 +#define CYREG_PWR_BG_TRIM4 0x400bff1c +#define CYFLD__ABS_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD__ABS_TRIM_IMO__SIZE 0x00000006 +#define CYREG_PWR_BG_TRIM5 0x400bff20 +#define CYFLD__TMPCO_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD__TMPCO_TRIM_IMO__SIZE 0x00000006 +#define CYREG_CLK_ILO_TRIM 0x400bff24 +#define CYFLD__TRIM__OFFSET 0x00000000 +#define CYFLD__TRIM__SIZE 0x00000004 +#define CYFLD__COARSE_TRIM__OFFSET 0x00000004 +#define CYFLD__COARSE_TRIM__SIZE 0x00000004 +#define CYREG_CLK_IMO_TRIM1 0x400bff28 +#define CYFLD__OFFSET__OFFSET 0x00000000 +#define CYFLD__OFFSET__SIZE 0x00000008 +#define CYREG_CLK_IMO_TRIM2 0x400bff2c +#define CYFLD__FREQ__OFFSET 0x00000000 +#define CYFLD__FREQ__SIZE 0x00000006 +#define CYREG_CLK_IMO_TRIM3 0x400bff30 +#define CYFLD__TRIM_CLK36__OFFSET 0x00000000 +#define CYFLD__TRIM_CLK36__SIZE 0x00000004 +#define CYREG_CLK_IMO_TRIM4 0x400bff34 +#define CYFLD__GAIN__OFFSET 0x00000000 +#define CYFLD__GAIN__SIZE 0x00000005 +#define CYFLD__FSOFFSET__OFFSET 0x00000005 +#define CYFLD__FSOFFSET__SIZE 0x00000003 +#define CYREG_PWR_RSVD_TRIM 0x400bff38 +#define CYFLD__RSVD_TRIM__OFFSET 0x00000000 +#define CYFLD__RSVD_TRIM__SIZE 0x00000004 +#define CYDEV_SPCIF_BASE 0x400e0000 +#define CYDEV_SPCIF_SIZE 0x00010000 +#define CYREG_SPCIF_GEOMETRY 0x400e0000 +#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000 +#define CYFLD_SPCIF_FLASH__SIZE 0x00000010 +#define CYFLD_SPCIF_SFLASH__OFFSET 0x00000010 +#define CYFLD_SPCIF_SFLASH__SIZE 0x00000004 +#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014 +#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002 +#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016 +#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002 +#define CYFLD_SPCIF_NVL__OFFSET 0x00000018 +#define CYFLD_SPCIF_NVL__SIZE 0x00000007 +#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001f +#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001 +#define CYREG_SPCIF_NVL_WR_DATA 0x400e001c +#define CYFLD_SPCIF_DATA__OFFSET 0x00000000 +#define CYFLD_SPCIF_DATA__SIZE 0x00000008 +#define CYDEV_UDB_BASE 0x400f0000 +#define CYDEV_UDB_SIZE 0x00010000 +#define CYDEV_UDB_W8_BASE 0x400f0000 +#define CYDEV_UDB_W8_SIZE 0x00001000 +#define CYREG_UDB_W8_A0_00 0x400f0000 +#define CYFLD_UDB_W8_A0__OFFSET 0x00000000 +#define CYFLD_UDB_W8_A0__SIZE 0x00000008 +#define CYREG_UDB_W8_A0_01 0x400f0001 +#define CYREG_UDB_W8_A0_02 0x400f0002 +#define CYREG_UDB_W8_A0_03 0x400f0003 +#define CYREG_UDB_W8_A1_00 0x400f0010 +#define CYFLD_UDB_W8_A1__OFFSET 0x00000000 +#define CYFLD_UDB_W8_A1__SIZE 0x00000008 +#define CYREG_UDB_W8_A1_01 0x400f0011 +#define CYREG_UDB_W8_A1_02 0x400f0012 +#define CYREG_UDB_W8_A1_03 0x400f0013 +#define CYREG_UDB_W8_D0_00 0x400f0020 +#define CYFLD_UDB_W8_D0__OFFSET 0x00000000 +#define CYFLD_UDB_W8_D0__SIZE 0x00000008 +#define CYREG_UDB_W8_D0_01 0x400f0021 +#define CYREG_UDB_W8_D0_02 0x400f0022 +#define CYREG_UDB_W8_D0_03 0x400f0023 +#define CYREG_UDB_W8_D1_00 0x400f0030 +#define CYFLD_UDB_W8_D1__OFFSET 0x00000000 +#define CYFLD_UDB_W8_D1__SIZE 0x00000008 +#define CYREG_UDB_W8_D1_01 0x400f0031 +#define CYREG_UDB_W8_D1_02 0x400f0032 +#define CYREG_UDB_W8_D1_03 0x400f0033 +#define CYREG_UDB_W8_F0_00 0x400f0040 +#define CYFLD_UDB_W8_F0__OFFSET 0x00000000 +#define CYFLD_UDB_W8_F0__SIZE 0x00000008 +#define CYREG_UDB_W8_F0_01 0x400f0041 +#define CYREG_UDB_W8_F0_02 0x400f0042 +#define CYREG_UDB_W8_F0_03 0x400f0043 +#define CYREG_UDB_W8_F1_00 0x400f0050 +#define CYFLD_UDB_W8_F1__OFFSET 0x00000000 +#define CYFLD_UDB_W8_F1__SIZE 0x00000008 +#define CYREG_UDB_W8_F1_01 0x400f0051 +#define CYREG_UDB_W8_F1_02 0x400f0052 +#define CYREG_UDB_W8_F1_03 0x400f0053 +#define CYREG_UDB_W8_ST_00 0x400f0060 +#define CYFLD_UDB_W8_ST__OFFSET 0x00000000 +#define CYFLD_UDB_W8_ST__SIZE 0x00000008 +#define CYREG_UDB_W8_ST_01 0x400f0061 +#define CYREG_UDB_W8_ST_02 0x400f0062 +#define CYREG_UDB_W8_ST_03 0x400f0063 +#define CYREG_UDB_W8_CTL_00 0x400f0070 +#define CYFLD_UDB_W8_CTL__OFFSET 0x00000000 +#define CYFLD_UDB_W8_CTL__SIZE 0x00000008 +#define CYREG_UDB_W8_CTL_01 0x400f0071 +#define CYREG_UDB_W8_CTL_02 0x400f0072 +#define CYREG_UDB_W8_CTL_03 0x400f0073 +#define CYREG_UDB_W8_MSK_00 0x400f0080 +#define CYFLD_UDB_W8_MSK__OFFSET 0x00000000 +#define CYFLD_UDB_W8_MSK__SIZE 0x00000007 +#define CYREG_UDB_W8_MSK_01 0x400f0081 +#define CYREG_UDB_W8_MSK_02 0x400f0082 +#define CYREG_UDB_W8_MSK_03 0x400f0083 +#define CYREG_UDB_W8_ACTL_00 0x400f0090 +#define CYFLD_UDB_W8_FIFO0_CLR__OFFSET 0x00000000 +#define CYFLD_UDB_W8_FIFO0_CLR__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO0_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO0_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_W8_FIFO1_CLR__OFFSET 0x00000001 +#define CYFLD_UDB_W8_FIFO1_CLR__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO1_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO1_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_W8_FIFO0_LVL__OFFSET 0x00000002 +#define CYFLD_UDB_W8_FIFO0_LVL__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO0_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO0_LVL_MID 0x00000001 +#define CYFLD_UDB_W8_FIFO1_LVL__OFFSET 0x00000003 +#define CYFLD_UDB_W8_FIFO1_LVL__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO1_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO1_LVL_MID 0x00000001 +#define CYFLD_UDB_W8_INT_EN__OFFSET 0x00000004 +#define CYFLD_UDB_W8_INT_EN__SIZE 0x00000001 +#define CYVAL_UDB_W8_INT_EN_DISABLE 0x00000000 +#define CYVAL_UDB_W8_INT_EN_ENABLE 0x00000001 +#define CYFLD_UDB_W8_CNT_START__OFFSET 0x00000005 +#define CYFLD_UDB_W8_CNT_START__SIZE 0x00000001 +#define CYVAL_UDB_W8_CNT_START_DISABLE 0x00000000 +#define CYVAL_UDB_W8_CNT_START_ENABLE 0x00000001 +#define CYREG_UDB_W8_ACTL_01 0x400f0091 +#define CYREG_UDB_W8_ACTL_02 0x400f0092 +#define CYREG_UDB_W8_ACTL_03 0x400f0093 +#define CYREG_UDB_W8_MC_00 0x400f00a0 +#define CYFLD_UDB_W8_PLD0_MC__OFFSET 0x00000000 +#define CYFLD_UDB_W8_PLD0_MC__SIZE 0x00000004 +#define CYFLD_UDB_W8_PLD1_MC__OFFSET 0x00000004 +#define CYFLD_UDB_W8_PLD1_MC__SIZE 0x00000004 +#define CYREG_UDB_W8_MC_01 0x400f00a1 +#define CYREG_UDB_W8_MC_02 0x400f00a2 +#define CYREG_UDB_W8_MC_03 0x400f00a3 +#define CYDEV_UDB_CAT16_BASE 0x400f1000 +#define CYDEV_UDB_CAT16_SIZE 0x00001000 +#define CYREG_UDB_CAT16_A_00 0x400f1000 +#define CYFLD_UDB_CAT16_A0__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_A0__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_A1__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_A1__SIZE 0x00000008 +#define CYREG_UDB_CAT16_A_01 0x400f1002 +#define CYREG_UDB_CAT16_A_02 0x400f1004 +#define CYREG_UDB_CAT16_A_03 0x400f1006 +#define CYREG_UDB_CAT16_D_00 0x400f1040 +#define CYFLD_UDB_CAT16_D0__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_D0__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_D1__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_D1__SIZE 0x00000008 +#define CYREG_UDB_CAT16_D_01 0x400f1042 +#define CYREG_UDB_CAT16_D_02 0x400f1044 +#define CYREG_UDB_CAT16_D_03 0x400f1046 +#define CYREG_UDB_CAT16_F_00 0x400f1080 +#define CYFLD_UDB_CAT16_F0__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_F0__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_F1__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_F1__SIZE 0x00000008 +#define CYREG_UDB_CAT16_F_01 0x400f1082 +#define CYREG_UDB_CAT16_F_02 0x400f1084 +#define CYREG_UDB_CAT16_F_03 0x400f1086 +#define CYREG_UDB_CAT16_CTL_ST_00 0x400f10c0 +#define CYFLD_UDB_CAT16_ST__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_ST__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_CTL__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_CTL__SIZE 0x00000008 +#define CYREG_UDB_CAT16_CTL_ST_01 0x400f10c2 +#define CYREG_UDB_CAT16_CTL_ST_02 0x400f10c4 +#define CYREG_UDB_CAT16_CTL_ST_03 0x400f10c6 +#define CYREG_UDB_CAT16_ACTL_MSK_00 0x400f1100 +#define CYFLD_UDB_CAT16_MSK__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_MSK__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_FIFO0_CLR__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET 0x00000009 +#define CYFLD_UDB_CAT16_FIFO1_CLR__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET 0x0000000a +#define CYFLD_UDB_CAT16_FIFO0_LVL__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO0_LVL_MID 0x00000001 +#define CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET 0x0000000b +#define CYFLD_UDB_CAT16_FIFO1_LVL__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO1_LVL_MID 0x00000001 +#define CYFLD_UDB_CAT16_INT_EN__OFFSET 0x0000000c +#define CYFLD_UDB_CAT16_INT_EN__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_INT_EN_DISABLE 0x00000000 +#define CYVAL_UDB_CAT16_INT_EN_ENABLE 0x00000001 +#define CYFLD_UDB_CAT16_CNT_START__OFFSET 0x0000000d +#define CYFLD_UDB_CAT16_CNT_START__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_CNT_START_DISABLE 0x00000000 +#define CYVAL_UDB_CAT16_CNT_START_ENABLE 0x00000001 +#define CYREG_UDB_CAT16_ACTL_MSK_01 0x400f1102 +#define CYREG_UDB_CAT16_ACTL_MSK_02 0x400f1104 +#define CYREG_UDB_CAT16_ACTL_MSK_03 0x400f1106 +#define CYREG_UDB_CAT16_MC_00 0x400f1140 +#define CYFLD_UDB_CAT16_PLD0_MC__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_PLD0_MC__SIZE 0x00000004 +#define CYFLD_UDB_CAT16_PLD1_MC__OFFSET 0x00000004 +#define CYFLD_UDB_CAT16_PLD1_MC__SIZE 0x00000004 +#define CYREG_UDB_CAT16_MC_01 0x400f1142 +#define CYREG_UDB_CAT16_MC_02 0x400f1144 +#define CYREG_UDB_CAT16_MC_03 0x400f1146 +#define CYDEV_UDB_W16_BASE 0x400f1000 +#define CYDEV_UDB_W16_SIZE 0x00001000 +#define CYREG_UDB_W16_A0_00 0x400f1000 +#define CYFLD_UDB_W16_A0_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_A0_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_A0_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_A0_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_A0_01 0x400f1002 +#define CYREG_UDB_W16_A0_02 0x400f1004 +#define CYREG_UDB_W16_A1_00 0x400f1020 +#define CYFLD_UDB_W16_A1_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_A1_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_A1_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_A1_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_A1_01 0x400f1022 +#define CYREG_UDB_W16_A1_02 0x400f1024 +#define CYREG_UDB_W16_D0_00 0x400f1040 +#define CYFLD_UDB_W16_D0_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_D0_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_D0_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_D0_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_D0_01 0x400f1042 +#define CYREG_UDB_W16_D0_02 0x400f1044 +#define CYREG_UDB_W16_D1_00 0x400f1060 +#define CYFLD_UDB_W16_D1_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_D1_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_D1_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_D1_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_D1_01 0x400f1062 +#define CYREG_UDB_W16_D1_02 0x400f1064 +#define CYREG_UDB_W16_F0_00 0x400f1080 +#define CYFLD_UDB_W16_F0_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_F0_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_F0_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_F0_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_F0_01 0x400f1082 +#define CYREG_UDB_W16_F0_02 0x400f1084 +#define CYREG_UDB_W16_F1_00 0x400f10a0 +#define CYFLD_UDB_W16_F1_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_F1_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_F1_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_F1_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_F1_01 0x400f10a2 +#define CYREG_UDB_W16_F1_02 0x400f10a4 +#define CYREG_UDB_W16_ST_00 0x400f10c0 +#define CYFLD_UDB_W16_ST_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_ST_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_ST_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_ST_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_ST_01 0x400f10c2 +#define CYREG_UDB_W16_ST_02 0x400f10c4 +#define CYREG_UDB_W16_CTL_00 0x400f10e0 +#define CYFLD_UDB_W16_CTL_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_CTL_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_CTL_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_CTL_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_CTL_01 0x400f10e2 +#define CYREG_UDB_W16_CTL_02 0x400f10e4 +#define CYREG_UDB_W16_MSK_00 0x400f1100 +#define CYFLD_UDB_W16_MSK_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_MSK_LS__SIZE 0x00000007 +#define CYFLD_UDB_W16_MSK_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_MSK_MS__SIZE 0x00000007 +#define CYREG_UDB_W16_MSK_01 0x400f1102 +#define CYREG_UDB_W16_MSK_02 0x400f1104 +#define CYREG_UDB_W16_ACTL_00 0x400f1120 +#define CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET 0x00000001 +#define CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET 0x00000002 +#define CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_LVL_LS_MID 0x00000001 +#define CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET 0x00000003 +#define CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_LVL_LS_MID 0x00000001 +#define CYFLD_UDB_W16_INT_EN_LS__OFFSET 0x00000004 +#define CYFLD_UDB_W16_INT_EN_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_INT_EN_LS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_INT_EN_LS_ENABLE 0x00000001 +#define CYFLD_UDB_W16_CNT_START_LS__OFFSET 0x00000005 +#define CYFLD_UDB_W16_CNT_START_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_CNT_START_LS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_CNT_START_LS_ENABLE 0x00000001 +#define CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET 0x00000009 +#define CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET 0x0000000a +#define CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_LVL_MS_MID 0x00000001 +#define CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET 0x0000000b +#define CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_LVL_MS_MID 0x00000001 +#define CYFLD_UDB_W16_INT_EN_MS__OFFSET 0x0000000c +#define CYFLD_UDB_W16_INT_EN_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_INT_EN_MS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_INT_EN_MS_ENABLE 0x00000001 +#define CYFLD_UDB_W16_CNT_START_MS__OFFSET 0x0000000d +#define CYFLD_UDB_W16_CNT_START_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_CNT_START_MS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_CNT_START_MS_ENABLE 0x00000001 +#define CYREG_UDB_W16_ACTL_01 0x400f1122 +#define CYREG_UDB_W16_ACTL_02 0x400f1124 +#define CYREG_UDB_W16_MC_00 0x400f1140 +#define CYFLD_UDB_W16_PLD0_MC_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_PLD0_MC_LS__SIZE 0x00000004 +#define CYFLD_UDB_W16_PLD1_MC_LS__OFFSET 0x00000004 +#define CYFLD_UDB_W16_PLD1_MC_LS__SIZE 0x00000004 +#define CYFLD_UDB_W16_PLD0_MC_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_PLD0_MC_MS__SIZE 0x00000004 +#define CYFLD_UDB_W16_PLD1_MC_MS__OFFSET 0x0000000c +#define CYFLD_UDB_W16_PLD1_MC_MS__SIZE 0x00000004 +#define CYREG_UDB_W16_MC_01 0x400f1142 +#define CYREG_UDB_W16_MC_02 0x400f1144 +#define CYDEV_UDB_W32_BASE 0x400f2000 +#define CYDEV_UDB_W32_SIZE 0x00001000 +#define CYREG_UDB_W32_A0_00 0x400f2000 +#define CYFLD_UDB_W32_A0_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_A0_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_A0_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_A0_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_A0_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_A0_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_A0_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_A0_3__SIZE 0x00000008 +#define CYREG_UDB_W32_A1_00 0x400f2040 +#define CYFLD_UDB_W32_A1_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_A1_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_A1_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_A1_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_A1_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_A1_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_A1_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_A1_3__SIZE 0x00000008 +#define CYREG_UDB_W32_D0_00 0x400f2080 +#define CYFLD_UDB_W32_D0_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_D0_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_D0_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_D0_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_D0_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_D0_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_D0_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_D0_3__SIZE 0x00000008 +#define CYREG_UDB_W32_D1_00 0x400f20c0 +#define CYFLD_UDB_W32_D1_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_D1_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_D1_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_D1_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_D1_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_D1_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_D1_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_D1_3__SIZE 0x00000008 +#define CYREG_UDB_W32_F0_00 0x400f2100 +#define CYFLD_UDB_W32_F0_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_F0_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_F0_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_F0_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_F0_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_F0_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_F0_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_F0_3__SIZE 0x00000008 +#define CYREG_UDB_W32_F1_00 0x400f2140 +#define CYFLD_UDB_W32_F1_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_F1_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_F1_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_F1_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_F1_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_F1_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_F1_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_F1_3__SIZE 0x00000008 +#define CYREG_UDB_W32_ST_00 0x400f2180 +#define CYFLD_UDB_W32_ST_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_ST_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_ST_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_ST_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_ST_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_ST_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_ST_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_ST_3__SIZE 0x00000008 +#define CYREG_UDB_W32_CTL_00 0x400f21c0 +#define CYFLD_UDB_W32_CTL_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_CTL_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_CTL_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_CTL_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_CTL_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_CTL_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_CTL_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_CTL_3__SIZE 0x00000008 +#define CYREG_UDB_W32_MSK_00 0x400f2200 +#define CYFLD_UDB_W32_MSK_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_MSK_0__SIZE 0x00000007 +#define CYFLD_UDB_W32_MSK_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_MSK_1__SIZE 0x00000007 +#define CYFLD_UDB_W32_MSK_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_MSK_2__SIZE 0x00000007 +#define CYFLD_UDB_W32_MSK_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_MSK_3__SIZE 0x00000007 +#define CYREG_UDB_W32_ACTL_00 0x400f2240 +#define CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_FIFO0_CLR_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET 0x00000002 +#define CYFLD_UDB_W32_FIFO0_LVL_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_0_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET 0x00000003 +#define CYFLD_UDB_W32_FIFO1_LVL_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_0_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_0__OFFSET 0x00000004 +#define CYFLD_UDB_W32_INT_EN_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_0_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_0_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_0__OFFSET 0x00000005 +#define CYFLD_UDB_W32_CNT_START_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_0_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_0_ENABLE 0x00000001 +#define CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_FIFO0_CLR_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET 0x00000009 +#define CYFLD_UDB_W32_FIFO1_CLR_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET 0x0000000a +#define CYFLD_UDB_W32_FIFO0_LVL_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_1_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET 0x0000000b +#define CYFLD_UDB_W32_FIFO1_LVL_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_1_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_1__OFFSET 0x0000000c +#define CYFLD_UDB_W32_INT_EN_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_1_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_1_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_1__OFFSET 0x0000000d +#define CYFLD_UDB_W32_CNT_START_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_1_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_1_ENABLE 0x00000001 +#define CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_FIFO0_CLR_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET 0x00000011 +#define CYFLD_UDB_W32_FIFO1_CLR_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET 0x00000012 +#define CYFLD_UDB_W32_FIFO0_LVL_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_2_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET 0x00000013 +#define CYFLD_UDB_W32_FIFO1_LVL_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_2_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_2__OFFSET 0x00000014 +#define CYFLD_UDB_W32_INT_EN_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_2_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_2_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_2__OFFSET 0x00000015 +#define CYFLD_UDB_W32_CNT_START_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_2_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_2_ENABLE 0x00000001 +#define CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_FIFO0_CLR_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET 0x00000019 +#define CYFLD_UDB_W32_FIFO1_CLR_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET 0x0000001a +#define CYFLD_UDB_W32_FIFO0_LVL_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_3_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET 0x0000001b +#define CYFLD_UDB_W32_FIFO1_LVL_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_3_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_3__OFFSET 0x0000001c +#define CYFLD_UDB_W32_INT_EN_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_3_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_3_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_3__OFFSET 0x0000001d +#define CYFLD_UDB_W32_CNT_START_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_3_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_3_ENABLE 0x00000001 +#define CYREG_UDB_W32_MC_00 0x400f2280 +#define CYFLD_UDB_W32_PLD0_MC_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_PLD0_MC_0__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_0__OFFSET 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_0__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD0_MC_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_PLD0_MC_1__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_1__OFFSET 0x0000000c +#define CYFLD_UDB_W32_PLD1_MC_1__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD0_MC_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_PLD0_MC_2__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_2__OFFSET 0x00000014 +#define CYFLD_UDB_W32_PLD1_MC_2__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD0_MC_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_PLD0_MC_3__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_3__OFFSET 0x0000001c +#define CYFLD_UDB_W32_PLD1_MC_3__SIZE 0x00000004 +#define CYDEV_UDB_P0_BASE 0x400f3000 +#define CYDEV_UDB_P0_SIZE 0x00000200 +#define CYDEV_UDB_P0_U0_BASE 0x400f3000 +#define CYDEV_UDB_P0_U0_SIZE 0x00000080 +#define CYREG_UDB_P0_U0_PLD_IT0 0x400f3000 +#define CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET 0x00000010 +#define CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET 0x00000011 +#define CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET 0x00000012 +#define CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET 0x00000013 +#define CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET 0x00000014 +#define CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET 0x00000015 +#define CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET 0x00000016 +#define CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET 0x00000017 +#define CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET 0x00000018 +#define CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET 0x00000019 +#define CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET 0x0000001a +#define CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET 0x0000001b +#define CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET 0x0000001c +#define CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET 0x0000001d +#define CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET 0x0000001e +#define CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET 0x0000001f +#define CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_PLD_IT1 0x400f3004 +#define CYREG_UDB_P0_U0_PLD_IT2 0x400f3008 +#define CYREG_UDB_P0_U0_PLD_IT3 0x400f300c +#define CYREG_UDB_P0_U0_PLD_IT4 0x400f3010 +#define CYREG_UDB_P0_U0_PLD_IT5 0x400f3014 +#define CYREG_UDB_P0_U0_PLD_IT6 0x400f3018 +#define CYREG_UDB_P0_U0_PLD_IT7 0x400f301c +#define CYREG_UDB_P0_U0_PLD_IT8 0x400f3020 +#define CYREG_UDB_P0_U0_PLD_IT9 0x400f3024 +#define CYREG_UDB_P0_U0_PLD_IT10 0x400f3028 +#define CYREG_UDB_P0_U0_PLD_IT11 0x400f302c +#define CYREG_UDB_P0_U0_PLD_ORT0 0x400f3030 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_PLD_ORT1 0x400f3032 +#define CYREG_UDB_P0_U0_PLD_ORT2 0x400f3034 +#define CYREG_UDB_P0_U0_PLD_ORT3 0x400f3036 +#define CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST 0x400f3038 +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED 0x00000001 +#define CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB 0x400f303a +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L 0x00000003 +#define CYREG_UDB_P0_U0_PLD_MC_SET_RESET 0x400f303c +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS 0x400f303e +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_NC1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC3__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_NC3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC5__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_NC5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC7__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_NC7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC9__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_NC9__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC11__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_NC11__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC13__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_NC13__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC15__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_NC15__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG0 0x400f3040 +#define CYFLD_UDB_P_U_RAD0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RAD0__SIZE 0x00000003 +#define CYVAL_UDB_P_U_RAD0_OFF 0x00000000 +#define CYVAL_UDB_P_U_RAD0_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_RAD0_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_RAD0_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_RAD0_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_RAD0_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_RAD0_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_RAD0_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_RAD1__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_RAD1__SIZE 0x00000003 +#define CYVAL_UDB_P_U_RAD1_OFF 0x00000000 +#define CYVAL_UDB_P_U_RAD1_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_RAD1_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_RAD1_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_RAD1_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_RAD1_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_RAD1_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_RAD1_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG1 0x400f3041 +#define CYFLD_UDB_P_U_RAD2__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RAD2__SIZE 0x00000003 +#define CYVAL_UDB_P_U_RAD2_OFF 0x00000000 +#define CYVAL_UDB_P_U_RAD2_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_RAD2_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_RAD2_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_RAD2_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_RAD2_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_RAD2_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_RAD2_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS 0x00000001 +#define CYREG_UDB_P0_U0_CFG2 0x400f3042 +#define CYFLD_UDB_P_U_F0_LD__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_F0_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_F0_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_F0_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_F0_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_F0_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_F0_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_F0_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_F0_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_F0_LD_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_F1_LD__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_F1_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_F1_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_F1_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_F1_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_F1_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_F1_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_F1_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_F1_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_F1_LD_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG3 0x400f3043 +#define CYFLD_UDB_P_U_D0_LD__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_D0_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_D0_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_D0_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_D0_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_D0_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_D0_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_D0_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_D0_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_D0_LD_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_D1_LD__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_D1_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_D1_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_D1_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_D1_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_D1_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_D1_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_D1_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_D1_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_D1_LD_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG4 0x400f3044 +#define CYFLD_UDB_P_U_SI_MUX__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_SI_MUX__SIZE 0x00000003 +#define CYVAL_UDB_P_U_SI_MUX_OFF 0x00000000 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_SI_MUX_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_CI_MUX__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_CI_MUX__SIZE 0x00000003 +#define CYVAL_UDB_P_U_CI_MUX_OFF 0x00000000 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_CI_MUX_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG5 0x400f3045 +#define CYFLD_UDB_P_U_OUT0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT0__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT0_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT0_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT0_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT0_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT0_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT0_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT0_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT0_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT0_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT0_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT0_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT0_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT0_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT0_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT0_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT0_F1_BUS_STAT 0x0000000f +#define CYFLD_UDB_P_U_OUT1__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_OUT1__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT1_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT1_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT1_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT1_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT1_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT1_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT1_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT1_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT1_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT1_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT1_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT1_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT1_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT1_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT1_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT1_F1_BUS_STAT 0x0000000f +#define CYREG_UDB_P0_U0_CFG6 0x400f3046 +#define CYFLD_UDB_P_U_OUT2__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT2__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT2_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT2_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT2_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT2_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT2_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT2_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT2_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT2_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT2_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT2_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT2_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT2_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT2_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT2_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT2_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT2_F1_BUS_STAT 0x0000000f +#define CYFLD_UDB_P_U_OUT3__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_OUT3__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT3_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT3_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT3_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT3_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT3_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT3_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT3_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT3_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT3_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT3_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT3_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT3_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT3_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT3_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT3_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT3_F1_BUS_STAT 0x0000000f +#define CYREG_UDB_P0_U0_CFG7 0x400f3047 +#define CYFLD_UDB_P_U_OUT4__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT4__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT4_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT4_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT4_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT4_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT4_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT4_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT4_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT4_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT4_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT4_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT4_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT4_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT4_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT4_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT4_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT4_F1_BUS_STAT 0x0000000f +#define CYFLD_UDB_P_U_OUT5__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_OUT5__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT5_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT5_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT5_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT5_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT5_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT5_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT5_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT5_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT5_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT5_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT5_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT5_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT5_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT5_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT5_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT5_F1_BUS_STAT 0x0000000f +#define CYREG_UDB_P0_U0_CFG8 0x400f3048 +#define CYFLD_UDB_P_U_OUT_SYNC__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT_SYNC__SIZE 0x00000006 +#define CYVAL_UDB_P_U_OUT_SYNC_REGISTERED 0x00000000 +#define CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC6__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_NC6__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG9 0x400f3049 +#define CYFLD_UDB_P_U_AMASK__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_AMASK__SIZE 0x00000008 +#define CYREG_UDB_P0_U0_CFG10 0x400f304a +#define CYFLD_UDB_P_U_CMASK0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CMASK0__SIZE 0x00000008 +#define CYREG_UDB_P0_U0_CFG11 0x400f304b +#define CYREG_UDB_P0_U0_CFG12 0x400f304c +#define CYFLD_UDB_P_U_SI_SELA__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_SI_SELA__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELA_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_SI_SELA_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_SI_SELA_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELA_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_SI_SELB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_SI_SELB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELB_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_SI_SELB_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_SI_SELB_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELB_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_DEF_SI__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_DEF_SI__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 0x00000000 +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 0x00000001 +#define CYFLD_UDB_P_U_AMASK_EN__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_AMASK_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_AMASK_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_AMASK_EN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CMASK0_EN__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_CMASK0_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CMASK0_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CMASK0_EN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CMASK1_EN__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_CMASK1_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CMASK1_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CMASK1_EN_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_CFG13 0x400f304d +#define CYFLD_UDB_P_U_CI_SELA__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CI_SELA__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELA_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_CI_SELA_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_CI_SELA_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELA_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_CI_SELB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CI_SELB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELB_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_CI_SELB_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_CI_SELB_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELB_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_CMP_SELA__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_CMP_SELA__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELA_A1_D1 0x00000000 +#define CYVAL_UDB_P_U_CMP_SELA_A1_A0 0x00000001 +#define CYVAL_UDB_P_U_CMP_SELA_A0_D1 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELA_A0_A0 0x00000003 +#define CYFLD_UDB_P_U_CMP_SELB__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_CMP_SELB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELB_A1_D1 0x00000000 +#define CYVAL_UDB_P_U_CMP_SELB_A1_A0 0x00000001 +#define CYVAL_UDB_P_U_CMP_SELB_A0_D1 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELB_A0_A0 0x00000003 +#define CYREG_UDB_P0_U0_CFG14 0x400f304e +#define CYFLD_UDB_P_U_CHAIN0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CHAIN0__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN0_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN0_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CHAIN1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_CHAIN1__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN1_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN1_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CHAIN_FB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CHAIN_FB__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN_FB_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN_FB_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_CHAIN_CMSB__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_MSB_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_MSB_SEL__SIZE 0x00000003 +#define CYVAL_UDB_P_U_MSB_SEL_BIT0 0x00000000 +#define CYVAL_UDB_P_U_MSB_SEL_BIT1 0x00000001 +#define CYVAL_UDB_P_U_MSB_SEL_BIT2 0x00000002 +#define CYVAL_UDB_P_U_MSB_SEL_BIT3 0x00000003 +#define CYVAL_UDB_P_U_MSB_SEL_BIT4 0x00000004 +#define CYVAL_UDB_P_U_MSB_SEL_BIT5 0x00000005 +#define CYVAL_UDB_P_U_MSB_SEL_BIT6 0x00000006 +#define CYVAL_UDB_P_U_MSB_SEL_BIT7 0x00000007 +#define CYFLD_UDB_P_U_MSB_EN__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_MSB_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_MSB_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_MSB_EN_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_CFG15 0x400f304f +#define CYFLD_UDB_P_U_F0_INSEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_F0_INSEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_F0_INSEL_INPUT 0x00000000 +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 0x00000001 +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 0x00000002 +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU 0x00000003 +#define CYFLD_UDB_P_U_F1_INSEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_F1_INSEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_F1_INSEL_INPUT 0x00000000 +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 0x00000001 +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 0x00000002 +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU 0x00000003 +#define CYFLD_UDB_P_U_MSB_SI__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_MSB_SI__SIZE 0x00000001 +#define CYVAL_UDB_P_U_MSB_SI_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_MSB_SI_MSB 0x00000001 +#define CYFLD_UDB_P_U_PI_DYN__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PI_DYN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PI_DYN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PI_DYN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_SHIFT_SEL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_SHIFT_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB 0x00000000 +#define CYVAL_UDB_P_U_SHIFT_SEL_SOR 0x00000001 +#define CYFLD_UDB_P_U_PI_SEL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PI_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PI_SEL_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_PI_SEL_PARALLEL 0x00000001 +#define CYREG_UDB_P0_U0_CFG16 0x400f3050 +#define CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_WRK16_CONCAT__SIZE 0x00000001 +#define CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE 0x00000001 +#define CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_EXT_CRCPRS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL 0x00000000 +#define CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL 0x00000001 +#define CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_FIFO_ASYNC__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_EDGE__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_FIFO_EDGE__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_EDGE_LEVEL 0x00000000 +#define CYVAL_UDB_P_U_FIFO_EDGE_EDGE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_CAP__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_FIFO_CAP__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_CAP_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_CAP_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_FAST__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_FIFO_FAST__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_FAST_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_FAST_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_F0_CK_INV__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_F0_CK_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F0_CK_INV_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_F0_CK_INV_INVERT 0x00000001 +#define CYFLD_UDB_P_U_F1_CK_INV__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_F1_CK_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F1_CK_INV_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_F1_CK_INV_INVERT 0x00000001 +#define CYREG_UDB_P0_U0_CFG17 0x400f3051 +#define CYFLD_UDB_P_U_F0_DYN__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_F0_DYN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F0_DYN_STATIC 0x00000000 +#define CYVAL_UDB_P_U_F0_DYN_DYNAMIC 0x00000001 +#define CYFLD_UDB_P_U_F1_DYN__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_F1_DYN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F1_DYN_STATIC 0x00000000 +#define CYVAL_UDB_P_U_F1_DYN_DYNAMIC 0x00000001 +#define CYFLD_UDB_P_U_NC2__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_NC2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_CFG18 0x400f3052 +#define CYFLD_UDB_P_U_CTL_MD0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CTL_MD0__SIZE 0x00000008 +#define CYVAL_UDB_P_U_CTL_MD0_DIRECT 0x00000000 +#define CYVAL_UDB_P_U_CTL_MD0_SYNC 0x00000001 +#define CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC 0x00000002 +#define CYVAL_UDB_P_U_CTL_MD0_PULSE 0x00000003 +#define CYREG_UDB_P0_U0_CFG19 0x400f3053 +#define CYFLD_UDB_P_U_CTL_MD1__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CTL_MD1__SIZE 0x00000008 +#define CYVAL_UDB_P_U_CTL_MD1_DIRECT 0x00000000 +#define CYVAL_UDB_P_U_CTL_MD1_SYNC 0x00000001 +#define CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC 0x00000002 +#define CYVAL_UDB_P_U_CTL_MD1_PULSE 0x00000003 +#define CYREG_UDB_P0_U0_CFG20 0x400f3054 +#define CYFLD_UDB_P_U_STAT_MD__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_STAT_MD__SIZE 0x00000008 +#define CYREG_UDB_P0_U0_CFG21 0x400f3055 +#define CYFLD_UDB_P_U_NC0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_NC0__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG22 0x400f3056 +#define CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_SC_OUT_CTL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL 0x00000000 +#define CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL 0x00000001 +#define CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER 0x00000002 +#define CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED 0x00000003 +#define CYFLD_UDB_P_U_SC_INT_MD__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_SC_INT_MD__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_INT_MD_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_SC_INT_MD_INT_MODE 0x00000001 +#define CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_SC_SYNC_MD__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE 0x00000001 +#define CYFLD_UDB_P_U_SC_EXT_RES__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_SC_EXT_RES__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_EXT_RES_DISABLED 0x00000000 +#define CYVAL_UDB_P_U_SC_EXT_RES_ENABLED 0x00000001 +#define CYREG_UDB_P0_U0_CFG23 0x400f3057 +#define CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CNT_LD_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 0x00000000 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 0x00000001 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 0x00000002 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 0x00000003 +#define CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CNT_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 0x00000000 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 0x00000001 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 0x00000002 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO 0x00000003 +#define CYFLD_UDB_P_U_ROUTE_LD__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_ROUTE_LD__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ROUTE_LD_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_ROUTE_LD_ROUTED 0x00000001 +#define CYFLD_UDB_P_U_ROUTE_EN__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_ROUTE_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ROUTE_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_ROUTE_EN_ROUTED 0x00000001 +#define CYFLD_UDB_P_U_ALT_CNT__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_ALT_CNT__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE 0x00000000 +#define CYVAL_UDB_P_U_ALT_CNT_ALT_MODE 0x00000001 +#define CYREG_UDB_P0_U0_CFG24 0x400f3058 +#define CYFLD_UDB_P_U_RC_EN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RC_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 0x00000000 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 0x00000001 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 0x00000003 +#define CYFLD_UDB_P_U_RC_EN_MODE__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_RC_EN_MODE__SIZE 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_MODE_OFF 0x00000000 +#define CYVAL_UDB_P_U_RC_EN_MODE_ON 0x00000001 +#define CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_MODE_LEVEL 0x00000003 +#define CYFLD_UDB_P_U_RC_EN_INV__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_RC_EN_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_RC_EN_INV_NOINV 0x00000000 +#define CYVAL_UDB_P_U_RC_EN_INV_INVERT 0x00000001 +#define CYFLD_UDB_P_U_RC_INV__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_RC_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_RC_INV_NOINV 0x00000000 +#define CYVAL_UDB_P_U_RC_INV_INVERT 0x00000001 +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE 0x00000001 +#define CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_RC_RES_SEL1__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG25 0x400f3059 +#define CYREG_UDB_P0_U0_CFG26 0x400f305a +#define CYREG_UDB_P0_U0_CFG27 0x400f305b +#define CYREG_UDB_P0_U0_CFG28 0x400f305c +#define CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK 0x00000009 +#define CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK 0x00000009 +#define CYREG_UDB_P0_U0_CFG29 0x400f305d +#define CYFLD_UDB_P_U_DP_CK_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_DP_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK 0x00000009 +#define CYFLD_UDB_P_U_SC_CK_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_SC_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK 0x00000009 +#define CYREG_UDB_P0_U0_CFG30 0x400f305e +#define CYFLD_UDB_P_U_RES_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RES_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN0 0x00000000 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN1 0x00000001 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN2 0x00000002 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN3 0x00000003 +#define CYFLD_UDB_P_U_RES_POL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_RES_POL_NEGATED 0x00000000 +#define CYVAL_UDB_P_U_RES_POL_ASSERTED 0x00000001 +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_GUDB_WR__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_GUDB_WR__SIZE 0x00000001 +#define CYVAL_UDB_P_U_GUDB_WR_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_GUDB_WR_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_DP_RES_POL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_DP_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_DP_RES_POL_INVERT 0x00000001 +#define CYFLD_UDB_P_U_SC_RES_POL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_SC_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_SC_RES_POL_INVERT 0x00000001 +#define CYREG_UDB_P0_U0_CFG31 0x400f305f +#define CYFLD_UDB_P_U_ALT_RES__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_ALT_RES__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ALT_RES_COMPATIBLE 0x00000000 +#define CYVAL_UDB_P_U_ALT_RES_ALTERNATE 0x00000001 +#define CYFLD_UDB_P_U_EXT_SYNC__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_EXT_SYNC__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EXT_SYNC_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_EXT_SYNC_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_EN_RES_STAT__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_EN_RES_STAT__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EN_RES_STAT_NEGATED 0x00000000 +#define CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED 0x00000001 +#define CYFLD_UDB_P_U_EN_RES_DP__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_EN_RES_DP__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EN_RES_DP_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_EN_RES_DP_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_EXT_CK_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 0x00000000 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 0x00000001 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 0x00000002 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 0x00000003 +#define CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_RES_POL_INVERT 0x00000001 +#define CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD1_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_RES_POL_INVERT 0x00000001 +#define CYREG_UDB_P0_U0_DCFG0 0x400f3060 +#define CYFLD_UDB_P_U_CMP_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CMP_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CMP_SEL_CFG_A 0x00000000 +#define CYVAL_UDB_P_U_CMP_SEL_CFG_B 0x00000001 +#define CYFLD_UDB_P_U_SI_SEL__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_SI_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SI_SEL_CFG_A 0x00000000 +#define CYVAL_UDB_P_U_SI_SEL_CFG_B 0x00000001 +#define CYFLD_UDB_P_U_CI_SEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CI_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CI_SEL_CFG_A 0x00000000 +#define CYVAL_UDB_P_U_CI_SEL_CFG_B 0x00000001 +#define CYFLD_UDB_P_U_CFB_EN__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_CFB_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CFB_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CFB_EN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_A1_WR_SRC__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_A1_WR_SRC__SIZE 0x00000002 +#define CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE 0x00000000 +#define CYVAL_UDB_P_U_A1_WR_SRC_ALU 0x00000001 +#define CYVAL_UDB_P_U_A1_WR_SRC_D1 0x00000002 +#define CYVAL_UDB_P_U_A1_WR_SRC_F1 0x00000003 +#define CYFLD_UDB_P_U_A0_WR_SRC__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_A0_WR_SRC__SIZE 0x00000002 +#define CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE 0x00000000 +#define CYVAL_UDB_P_U_A0_WR_SRC_ALU 0x00000001 +#define CYVAL_UDB_P_U_A0_WR_SRC_D0 0x00000002 +#define CYVAL_UDB_P_U_A0_WR_SRC_F0 0x00000003 +#define CYFLD_UDB_P_U_SHIFT__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_SHIFT__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SHIFT_NOSHIFT 0x00000000 +#define CYVAL_UDB_P_U_SHIFT_LEFT 0x00000001 +#define CYVAL_UDB_P_U_SHIFT_RIGHT 0x00000002 +#define CYVAL_UDB_P_U_SHIFT_SWAP 0x00000003 +#define CYFLD_UDB_P_U_SRC_B__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_SRC_B__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SRC_B_D0 0x00000000 +#define CYVAL_UDB_P_U_SRC_B_D1 0x00000001 +#define CYVAL_UDB_P_U_SRC_B_A0 0x00000002 +#define CYVAL_UDB_P_U_SRC_B_A1 0x00000003 +#define CYFLD_UDB_P_U_SRC_A__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_SRC_A__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SRC_A_A0 0x00000000 +#define CYVAL_UDB_P_U_SRC_A_A1 0x00000001 +#define CYFLD_UDB_P_U_FUNC__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_FUNC__SIZE 0x00000003 +#define CYVAL_UDB_P_U_FUNC_PASS 0x00000000 +#define CYVAL_UDB_P_U_FUNC_INC_A 0x00000001 +#define CYVAL_UDB_P_U_FUNC_DEC_A 0x00000002 +#define CYVAL_UDB_P_U_FUNC_ADD 0x00000003 +#define CYVAL_UDB_P_U_FUNC_SUB 0x00000004 +#define CYVAL_UDB_P_U_FUNC_XOR 0x00000005 +#define CYVAL_UDB_P_U_FUNC_AND 0x00000006 +#define CYVAL_UDB_P_U_FUNC_OR 0x00000007 +#define CYREG_UDB_P0_U0_DCFG1 0x400f3062 +#define CYREG_UDB_P0_U0_DCFG2 0x400f3064 +#define CYREG_UDB_P0_U0_DCFG3 0x400f3066 +#define CYREG_UDB_P0_U0_DCFG4 0x400f3068 +#define CYREG_UDB_P0_U0_DCFG5 0x400f306a +#define CYREG_UDB_P0_U0_DCFG6 0x400f306c +#define CYREG_UDB_P0_U0_DCFG7 0x400f306e +#define CYDEV_UDB_P0_U1_BASE 0x400f3080 +#define CYDEV_UDB_P0_U1_SIZE 0x00000080 +#define CYREG_UDB_P0_U1_PLD_IT0 0x400f3080 +#define CYREG_UDB_P0_U1_PLD_IT1 0x400f3084 +#define CYREG_UDB_P0_U1_PLD_IT2 0x400f3088 +#define CYREG_UDB_P0_U1_PLD_IT3 0x400f308c +#define CYREG_UDB_P0_U1_PLD_IT4 0x400f3090 +#define CYREG_UDB_P0_U1_PLD_IT5 0x400f3094 +#define CYREG_UDB_P0_U1_PLD_IT6 0x400f3098 +#define CYREG_UDB_P0_U1_PLD_IT7 0x400f309c +#define CYREG_UDB_P0_U1_PLD_IT8 0x400f30a0 +#define CYREG_UDB_P0_U1_PLD_IT9 0x400f30a4 +#define CYREG_UDB_P0_U1_PLD_IT10 0x400f30a8 +#define CYREG_UDB_P0_U1_PLD_IT11 0x400f30ac +#define CYREG_UDB_P0_U1_PLD_ORT0 0x400f30b0 +#define CYREG_UDB_P0_U1_PLD_ORT1 0x400f30b2 +#define CYREG_UDB_P0_U1_PLD_ORT2 0x400f30b4 +#define CYREG_UDB_P0_U1_PLD_ORT3 0x400f30b6 +#define CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST 0x400f30b8 +#define CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB 0x400f30ba +#define CYREG_UDB_P0_U1_PLD_MC_SET_RESET 0x400f30bc +#define CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS 0x400f30be +#define CYREG_UDB_P0_U1_CFG0 0x400f30c0 +#define CYREG_UDB_P0_U1_CFG1 0x400f30c1 +#define CYREG_UDB_P0_U1_CFG2 0x400f30c2 +#define CYREG_UDB_P0_U1_CFG3 0x400f30c3 +#define CYREG_UDB_P0_U1_CFG4 0x400f30c4 +#define CYREG_UDB_P0_U1_CFG5 0x400f30c5 +#define CYREG_UDB_P0_U1_CFG6 0x400f30c6 +#define CYREG_UDB_P0_U1_CFG7 0x400f30c7 +#define CYREG_UDB_P0_U1_CFG8 0x400f30c8 +#define CYREG_UDB_P0_U1_CFG9 0x400f30c9 +#define CYREG_UDB_P0_U1_CFG10 0x400f30ca +#define CYREG_UDB_P0_U1_CFG11 0x400f30cb +#define CYREG_UDB_P0_U1_CFG12 0x400f30cc +#define CYREG_UDB_P0_U1_CFG13 0x400f30cd +#define CYREG_UDB_P0_U1_CFG14 0x400f30ce +#define CYREG_UDB_P0_U1_CFG15 0x400f30cf +#define CYREG_UDB_P0_U1_CFG16 0x400f30d0 +#define CYREG_UDB_P0_U1_CFG17 0x400f30d1 +#define CYREG_UDB_P0_U1_CFG18 0x400f30d2 +#define CYREG_UDB_P0_U1_CFG19 0x400f30d3 +#define CYREG_UDB_P0_U1_CFG20 0x400f30d4 +#define CYREG_UDB_P0_U1_CFG21 0x400f30d5 +#define CYREG_UDB_P0_U1_CFG22 0x400f30d6 +#define CYREG_UDB_P0_U1_CFG23 0x400f30d7 +#define CYREG_UDB_P0_U1_CFG24 0x400f30d8 +#define CYREG_UDB_P0_U1_CFG25 0x400f30d9 +#define CYREG_UDB_P0_U1_CFG26 0x400f30da +#define CYREG_UDB_P0_U1_CFG27 0x400f30db +#define CYREG_UDB_P0_U1_CFG28 0x400f30dc +#define CYREG_UDB_P0_U1_CFG29 0x400f30dd +#define CYREG_UDB_P0_U1_CFG30 0x400f30de +#define CYREG_UDB_P0_U1_CFG31 0x400f30df +#define CYREG_UDB_P0_U1_DCFG0 0x400f30e0 +#define CYREG_UDB_P0_U1_DCFG1 0x400f30e2 +#define CYREG_UDB_P0_U1_DCFG2 0x400f30e4 +#define CYREG_UDB_P0_U1_DCFG3 0x400f30e6 +#define CYREG_UDB_P0_U1_DCFG4 0x400f30e8 +#define CYREG_UDB_P0_U1_DCFG5 0x400f30ea +#define CYREG_UDB_P0_U1_DCFG6 0x400f30ec +#define CYREG_UDB_P0_U1_DCFG7 0x400f30ee +#define CYDEV_UDB_P0_ROUTE_BASE 0x400f3100 +#define CYDEV_UDB_P0_ROUTE_SIZE 0x00000100 +#define CYREG_UDB_P0_ROUTE_HC0 0x400f3100 +#define CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE 0x00000008 +#define CYREG_UDB_P0_ROUTE_HC1 0x400f3101 +#define CYREG_UDB_P0_ROUTE_HC2 0x400f3102 +#define CYREG_UDB_P0_ROUTE_HC3 0x400f3103 +#define CYREG_UDB_P0_ROUTE_HC4 0x400f3104 +#define CYREG_UDB_P0_ROUTE_HC5 0x400f3105 +#define CYREG_UDB_P0_ROUTE_HC6 0x400f3106 +#define CYREG_UDB_P0_ROUTE_HC7 0x400f3107 +#define CYREG_UDB_P0_ROUTE_HC8 0x400f3108 +#define CYREG_UDB_P0_ROUTE_HC9 0x400f3109 +#define CYREG_UDB_P0_ROUTE_HC10 0x400f310a +#define CYREG_UDB_P0_ROUTE_HC11 0x400f310b +#define CYREG_UDB_P0_ROUTE_HC12 0x400f310c +#define CYREG_UDB_P0_ROUTE_HC13 0x400f310d +#define CYREG_UDB_P0_ROUTE_HC14 0x400f310e +#define CYREG_UDB_P0_ROUTE_HC15 0x400f310f +#define CYREG_UDB_P0_ROUTE_HC16 0x400f3110 +#define CYREG_UDB_P0_ROUTE_HC17 0x400f3111 +#define CYREG_UDB_P0_ROUTE_HC18 0x400f3112 +#define CYREG_UDB_P0_ROUTE_HC19 0x400f3113 +#define CYREG_UDB_P0_ROUTE_HC20 0x400f3114 +#define CYREG_UDB_P0_ROUTE_HC21 0x400f3115 +#define CYREG_UDB_P0_ROUTE_HC22 0x400f3116 +#define CYREG_UDB_P0_ROUTE_HC23 0x400f3117 +#define CYREG_UDB_P0_ROUTE_HC24 0x400f3118 +#define CYREG_UDB_P0_ROUTE_HC25 0x400f3119 +#define CYREG_UDB_P0_ROUTE_HC26 0x400f311a +#define CYREG_UDB_P0_ROUTE_HC27 0x400f311b +#define CYREG_UDB_P0_ROUTE_HC28 0x400f311c +#define CYREG_UDB_P0_ROUTE_HC29 0x400f311d +#define CYREG_UDB_P0_ROUTE_HC30 0x400f311e +#define CYREG_UDB_P0_ROUTE_HC31 0x400f311f +#define CYREG_UDB_P0_ROUTE_HC32 0x400f3120 +#define CYREG_UDB_P0_ROUTE_HC33 0x400f3121 +#define CYREG_UDB_P0_ROUTE_HC34 0x400f3122 +#define CYREG_UDB_P0_ROUTE_HC35 0x400f3123 +#define CYREG_UDB_P0_ROUTE_HC36 0x400f3124 +#define CYREG_UDB_P0_ROUTE_HC37 0x400f3125 +#define CYREG_UDB_P0_ROUTE_HC38 0x400f3126 +#define CYREG_UDB_P0_ROUTE_HC39 0x400f3127 +#define CYREG_UDB_P0_ROUTE_HC40 0x400f3128 +#define CYREG_UDB_P0_ROUTE_HC41 0x400f3129 +#define CYREG_UDB_P0_ROUTE_HC42 0x400f312a +#define CYREG_UDB_P0_ROUTE_HC43 0x400f312b +#define CYREG_UDB_P0_ROUTE_HC44 0x400f312c +#define CYREG_UDB_P0_ROUTE_HC45 0x400f312d +#define CYREG_UDB_P0_ROUTE_HC46 0x400f312e +#define CYREG_UDB_P0_ROUTE_HC47 0x400f312f +#define CYREG_UDB_P0_ROUTE_HC48 0x400f3130 +#define CYREG_UDB_P0_ROUTE_HC49 0x400f3131 +#define CYREG_UDB_P0_ROUTE_HC50 0x400f3132 +#define CYREG_UDB_P0_ROUTE_HC51 0x400f3133 +#define CYREG_UDB_P0_ROUTE_HC52 0x400f3134 +#define CYREG_UDB_P0_ROUTE_HC53 0x400f3135 +#define CYREG_UDB_P0_ROUTE_HC54 0x400f3136 +#define CYREG_UDB_P0_ROUTE_HC55 0x400f3137 +#define CYREG_UDB_P0_ROUTE_HC56 0x400f3138 +#define CYREG_UDB_P0_ROUTE_HC57 0x400f3139 +#define CYREG_UDB_P0_ROUTE_HC58 0x400f313a +#define CYREG_UDB_P0_ROUTE_HC59 0x400f313b +#define CYREG_UDB_P0_ROUTE_HC60 0x400f313c +#define CYREG_UDB_P0_ROUTE_HC61 0x400f313d +#define CYREG_UDB_P0_ROUTE_HC62 0x400f313e +#define CYREG_UDB_P0_ROUTE_HC63 0x400f313f +#define CYREG_UDB_P0_ROUTE_HC64 0x400f3140 +#define CYREG_UDB_P0_ROUTE_HC65 0x400f3141 +#define CYREG_UDB_P0_ROUTE_HC66 0x400f3142 +#define CYREG_UDB_P0_ROUTE_HC67 0x400f3143 +#define CYREG_UDB_P0_ROUTE_HC68 0x400f3144 +#define CYREG_UDB_P0_ROUTE_HC69 0x400f3145 +#define CYREG_UDB_P0_ROUTE_HC70 0x400f3146 +#define CYREG_UDB_P0_ROUTE_HC71 0x400f3147 +#define CYREG_UDB_P0_ROUTE_HC72 0x400f3148 +#define CYREG_UDB_P0_ROUTE_HC73 0x400f3149 +#define CYREG_UDB_P0_ROUTE_HC74 0x400f314a +#define CYREG_UDB_P0_ROUTE_HC75 0x400f314b +#define CYREG_UDB_P0_ROUTE_HC76 0x400f314c +#define CYREG_UDB_P0_ROUTE_HC77 0x400f314d +#define CYREG_UDB_P0_ROUTE_HC78 0x400f314e +#define CYREG_UDB_P0_ROUTE_HC79 0x400f314f +#define CYREG_UDB_P0_ROUTE_HC80 0x400f3150 +#define CYREG_UDB_P0_ROUTE_HC81 0x400f3151 +#define CYREG_UDB_P0_ROUTE_HC82 0x400f3152 +#define CYREG_UDB_P0_ROUTE_HC83 0x400f3153 +#define CYREG_UDB_P0_ROUTE_HC84 0x400f3154 +#define CYREG_UDB_P0_ROUTE_HC85 0x400f3155 +#define CYREG_UDB_P0_ROUTE_HC86 0x400f3156 +#define CYREG_UDB_P0_ROUTE_HC87 0x400f3157 +#define CYREG_UDB_P0_ROUTE_HC88 0x400f3158 +#define CYREG_UDB_P0_ROUTE_HC89 0x400f3159 +#define CYREG_UDB_P0_ROUTE_HC90 0x400f315a +#define CYREG_UDB_P0_ROUTE_HC91 0x400f315b +#define CYREG_UDB_P0_ROUTE_HC92 0x400f315c +#define CYREG_UDB_P0_ROUTE_HC93 0x400f315d +#define CYREG_UDB_P0_ROUTE_HC94 0x400f315e +#define CYREG_UDB_P0_ROUTE_HC95 0x400f315f +#define CYREG_UDB_P0_ROUTE_HC96 0x400f3160 +#define CYREG_UDB_P0_ROUTE_HC97 0x400f3161 +#define CYREG_UDB_P0_ROUTE_HC98 0x400f3162 +#define CYREG_UDB_P0_ROUTE_HC99 0x400f3163 +#define CYREG_UDB_P0_ROUTE_HC100 0x400f3164 +#define CYREG_UDB_P0_ROUTE_HC101 0x400f3165 +#define CYREG_UDB_P0_ROUTE_HC102 0x400f3166 +#define CYREG_UDB_P0_ROUTE_HC103 0x400f3167 +#define CYREG_UDB_P0_ROUTE_HC104 0x400f3168 +#define CYREG_UDB_P0_ROUTE_HC105 0x400f3169 +#define CYREG_UDB_P0_ROUTE_HC106 0x400f316a +#define CYREG_UDB_P0_ROUTE_HC107 0x400f316b +#define CYREG_UDB_P0_ROUTE_HC108 0x400f316c +#define CYREG_UDB_P0_ROUTE_HC109 0x400f316d +#define CYREG_UDB_P0_ROUTE_HC110 0x400f316e +#define CYREG_UDB_P0_ROUTE_HC111 0x400f316f +#define CYREG_UDB_P0_ROUTE_HC112 0x400f3170 +#define CYREG_UDB_P0_ROUTE_HC113 0x400f3171 +#define CYREG_UDB_P0_ROUTE_HC114 0x400f3172 +#define CYREG_UDB_P0_ROUTE_HC115 0x400f3173 +#define CYREG_UDB_P0_ROUTE_HC116 0x400f3174 +#define CYREG_UDB_P0_ROUTE_HC117 0x400f3175 +#define CYREG_UDB_P0_ROUTE_HC118 0x400f3176 +#define CYREG_UDB_P0_ROUTE_HC119 0x400f3177 +#define CYREG_UDB_P0_ROUTE_HC120 0x400f3178 +#define CYREG_UDB_P0_ROUTE_HC121 0x400f3179 +#define CYREG_UDB_P0_ROUTE_HC122 0x400f317a +#define CYREG_UDB_P0_ROUTE_HC123 0x400f317b +#define CYREG_UDB_P0_ROUTE_HC124 0x400f317c +#define CYREG_UDB_P0_ROUTE_HC125 0x400f317d +#define CYREG_UDB_P0_ROUTE_HC126 0x400f317e +#define CYREG_UDB_P0_ROUTE_HC127 0x400f317f +#define CYREG_UDB_P0_ROUTE_HV_L0 0x400f3180 +#define CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE 0x00000008 +#define CYREG_UDB_P0_ROUTE_HV_L1 0x400f3181 +#define CYREG_UDB_P0_ROUTE_HV_L2 0x400f3182 +#define CYREG_UDB_P0_ROUTE_HV_L3 0x400f3183 +#define CYREG_UDB_P0_ROUTE_HV_L4 0x400f3184 +#define CYREG_UDB_P0_ROUTE_HV_L5 0x400f3185 +#define CYREG_UDB_P0_ROUTE_HV_L6 0x400f3186 +#define CYREG_UDB_P0_ROUTE_HV_L7 0x400f3187 +#define CYREG_UDB_P0_ROUTE_HV_L8 0x400f3188 +#define CYREG_UDB_P0_ROUTE_HV_L9 0x400f3189 +#define CYREG_UDB_P0_ROUTE_HV_L10 0x400f318a +#define CYREG_UDB_P0_ROUTE_HV_L11 0x400f318b +#define CYREG_UDB_P0_ROUTE_HV_L12 0x400f318c +#define CYREG_UDB_P0_ROUTE_HV_L13 0x400f318d +#define CYREG_UDB_P0_ROUTE_HV_L14 0x400f318e +#define CYREG_UDB_P0_ROUTE_HV_L15 0x400f318f +#define CYREG_UDB_P0_ROUTE_HS0 0x400f3190 +#define CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE 0x00000008 +#define CYREG_UDB_P0_ROUTE_HS1 0x400f3191 +#define CYREG_UDB_P0_ROUTE_HS2 0x400f3192 +#define CYREG_UDB_P0_ROUTE_HS3 0x400f3193 +#define CYREG_UDB_P0_ROUTE_HS4 0x400f3194 +#define CYREG_UDB_P0_ROUTE_HS5 0x400f3195 +#define CYREG_UDB_P0_ROUTE_HS6 0x400f3196 +#define CYREG_UDB_P0_ROUTE_HS7 0x400f3197 +#define CYREG_UDB_P0_ROUTE_HS8 0x400f3198 +#define CYREG_UDB_P0_ROUTE_HS9 0x400f3199 +#define CYREG_UDB_P0_ROUTE_HS10 0x400f319a +#define CYREG_UDB_P0_ROUTE_HS11 0x400f319b +#define CYREG_UDB_P0_ROUTE_HS12 0x400f319c +#define CYREG_UDB_P0_ROUTE_HS13 0x400f319d +#define CYREG_UDB_P0_ROUTE_HS14 0x400f319e +#define CYREG_UDB_P0_ROUTE_HS15 0x400f319f +#define CYREG_UDB_P0_ROUTE_HS16 0x400f31a0 +#define CYREG_UDB_P0_ROUTE_HS17 0x400f31a1 +#define CYREG_UDB_P0_ROUTE_HS18 0x400f31a2 +#define CYREG_UDB_P0_ROUTE_HS19 0x400f31a3 +#define CYREG_UDB_P0_ROUTE_HS20 0x400f31a4 +#define CYREG_UDB_P0_ROUTE_HS21 0x400f31a5 +#define CYREG_UDB_P0_ROUTE_HS22 0x400f31a6 +#define CYREG_UDB_P0_ROUTE_HS23 0x400f31a7 +#define CYREG_UDB_P0_ROUTE_HV_R0 0x400f31a8 +#define CYREG_UDB_P0_ROUTE_HV_R1 0x400f31a9 +#define CYREG_UDB_P0_ROUTE_HV_R2 0x400f31aa +#define CYREG_UDB_P0_ROUTE_HV_R3 0x400f31ab +#define CYREG_UDB_P0_ROUTE_HV_R4 0x400f31ac +#define CYREG_UDB_P0_ROUTE_HV_R5 0x400f31ad +#define CYREG_UDB_P0_ROUTE_HV_R6 0x400f31ae +#define CYREG_UDB_P0_ROUTE_HV_R7 0x400f31af +#define CYREG_UDB_P0_ROUTE_HV_R8 0x400f31b0 +#define CYREG_UDB_P0_ROUTE_HV_R9 0x400f31b1 +#define CYREG_UDB_P0_ROUTE_HV_R10 0x400f31b2 +#define CYREG_UDB_P0_ROUTE_HV_R11 0x400f31b3 +#define CYREG_UDB_P0_ROUTE_HV_R12 0x400f31b4 +#define CYREG_UDB_P0_ROUTE_HV_R13 0x400f31b5 +#define CYREG_UDB_P0_ROUTE_HV_R14 0x400f31b6 +#define CYREG_UDB_P0_ROUTE_HV_R15 0x400f31b7 +#define CYREG_UDB_P0_ROUTE_PLD0IN0 0x400f31c0 +#define CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_PI_TOP__SIZE 0x00000004 +#define CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_P_ROUTE_PI_BOT__SIZE 0x00000004 +#define CYREG_UDB_P0_ROUTE_PLD0IN1 0x400f31c2 +#define CYREG_UDB_P0_ROUTE_PLD0IN2 0x400f31c4 +#define CYREG_UDB_P0_ROUTE_PLD1IN0 0x400f31ca +#define CYREG_UDB_P0_ROUTE_PLD1IN1 0x400f31cc +#define CYREG_UDB_P0_ROUTE_PLD1IN2 0x400f31ce +#define CYREG_UDB_P0_ROUTE_DPIN0 0x400f31d0 +#define CYREG_UDB_P0_ROUTE_DPIN1 0x400f31d2 +#define CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET 0x00000002 +#define CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE 0x00000002 +#define CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET 0x00000004 +#define CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE 0x00000002 +#define CYREG_UDB_P0_ROUTE_SCIN 0x400f31d6 +#define CYREG_UDB_P0_ROUTE_SCIOIN 0x400f31d8 +#define CYREG_UDB_P0_ROUTE_RCIN 0x400f31de +#define CYREG_UDB_P0_ROUTE_VS0 0x400f31e0 +#define CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_VS_TOP__SIZE 0x00000004 +#define CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_P_ROUTE_VS_BOT__SIZE 0x00000004 +#define CYREG_UDB_P0_ROUTE_VS1 0x400f31e2 +#define CYREG_UDB_P0_ROUTE_VS2 0x400f31e4 +#define CYREG_UDB_P0_ROUTE_VS3 0x400f31e6 +#define CYREG_UDB_P0_ROUTE_VS4 0x400f31e8 +#define CYREG_UDB_P0_ROUTE_VS5 0x400f31ea +#define CYREG_UDB_P0_ROUTE_VS6 0x400f31ec +#define CYREG_UDB_P0_ROUTE_VS7 0x400f31ee +#define CYDEV_UDB_P1_BASE 0x400f3200 +#define CYDEV_UDB_P1_SIZE 0x00000200 +#define CYDEV_UDB_P1_U0_BASE 0x400f3200 +#define CYDEV_UDB_P1_U0_SIZE 0x00000080 +#define CYREG_UDB_P1_U0_PLD_IT0 0x400f3200 +#define CYREG_UDB_P1_U0_PLD_IT1 0x400f3204 +#define CYREG_UDB_P1_U0_PLD_IT2 0x400f3208 +#define CYREG_UDB_P1_U0_PLD_IT3 0x400f320c +#define CYREG_UDB_P1_U0_PLD_IT4 0x400f3210 +#define CYREG_UDB_P1_U0_PLD_IT5 0x400f3214 +#define CYREG_UDB_P1_U0_PLD_IT6 0x400f3218 +#define CYREG_UDB_P1_U0_PLD_IT7 0x400f321c +#define CYREG_UDB_P1_U0_PLD_IT8 0x400f3220 +#define CYREG_UDB_P1_U0_PLD_IT9 0x400f3224 +#define CYREG_UDB_P1_U0_PLD_IT10 0x400f3228 +#define CYREG_UDB_P1_U0_PLD_IT11 0x400f322c +#define CYREG_UDB_P1_U0_PLD_ORT0 0x400f3230 +#define CYREG_UDB_P1_U0_PLD_ORT1 0x400f3232 +#define CYREG_UDB_P1_U0_PLD_ORT2 0x400f3234 +#define CYREG_UDB_P1_U0_PLD_ORT3 0x400f3236 +#define CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST 0x400f3238 +#define CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB 0x400f323a +#define CYREG_UDB_P1_U0_PLD_MC_SET_RESET 0x400f323c +#define CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS 0x400f323e +#define CYREG_UDB_P1_U0_CFG0 0x400f3240 +#define CYREG_UDB_P1_U0_CFG1 0x400f3241 +#define CYREG_UDB_P1_U0_CFG2 0x400f3242 +#define CYREG_UDB_P1_U0_CFG3 0x400f3243 +#define CYREG_UDB_P1_U0_CFG4 0x400f3244 +#define CYREG_UDB_P1_U0_CFG5 0x400f3245 +#define CYREG_UDB_P1_U0_CFG6 0x400f3246 +#define CYREG_UDB_P1_U0_CFG7 0x400f3247 +#define CYREG_UDB_P1_U0_CFG8 0x400f3248 +#define CYREG_UDB_P1_U0_CFG9 0x400f3249 +#define CYREG_UDB_P1_U0_CFG10 0x400f324a +#define CYREG_UDB_P1_U0_CFG11 0x400f324b +#define CYREG_UDB_P1_U0_CFG12 0x400f324c +#define CYREG_UDB_P1_U0_CFG13 0x400f324d +#define CYREG_UDB_P1_U0_CFG14 0x400f324e +#define CYREG_UDB_P1_U0_CFG15 0x400f324f +#define CYREG_UDB_P1_U0_CFG16 0x400f3250 +#define CYREG_UDB_P1_U0_CFG17 0x400f3251 +#define CYREG_UDB_P1_U0_CFG18 0x400f3252 +#define CYREG_UDB_P1_U0_CFG19 0x400f3253 +#define CYREG_UDB_P1_U0_CFG20 0x400f3254 +#define CYREG_UDB_P1_U0_CFG21 0x400f3255 +#define CYREG_UDB_P1_U0_CFG22 0x400f3256 +#define CYREG_UDB_P1_U0_CFG23 0x400f3257 +#define CYREG_UDB_P1_U0_CFG24 0x400f3258 +#define CYREG_UDB_P1_U0_CFG25 0x400f3259 +#define CYREG_UDB_P1_U0_CFG26 0x400f325a +#define CYREG_UDB_P1_U0_CFG27 0x400f325b +#define CYREG_UDB_P1_U0_CFG28 0x400f325c +#define CYREG_UDB_P1_U0_CFG29 0x400f325d +#define CYREG_UDB_P1_U0_CFG30 0x400f325e +#define CYREG_UDB_P1_U0_CFG31 0x400f325f +#define CYREG_UDB_P1_U0_DCFG0 0x400f3260 +#define CYREG_UDB_P1_U0_DCFG1 0x400f3262 +#define CYREG_UDB_P1_U0_DCFG2 0x400f3264 +#define CYREG_UDB_P1_U0_DCFG3 0x400f3266 +#define CYREG_UDB_P1_U0_DCFG4 0x400f3268 +#define CYREG_UDB_P1_U0_DCFG5 0x400f326a +#define CYREG_UDB_P1_U0_DCFG6 0x400f326c +#define CYREG_UDB_P1_U0_DCFG7 0x400f326e +#define CYDEV_UDB_P1_U1_BASE 0x400f3280 +#define CYDEV_UDB_P1_U1_SIZE 0x00000080 +#define CYREG_UDB_P1_U1_PLD_IT0 0x400f3280 +#define CYREG_UDB_P1_U1_PLD_IT1 0x400f3284 +#define CYREG_UDB_P1_U1_PLD_IT2 0x400f3288 +#define CYREG_UDB_P1_U1_PLD_IT3 0x400f328c +#define CYREG_UDB_P1_U1_PLD_IT4 0x400f3290 +#define CYREG_UDB_P1_U1_PLD_IT5 0x400f3294 +#define CYREG_UDB_P1_U1_PLD_IT6 0x400f3298 +#define CYREG_UDB_P1_U1_PLD_IT7 0x400f329c +#define CYREG_UDB_P1_U1_PLD_IT8 0x400f32a0 +#define CYREG_UDB_P1_U1_PLD_IT9 0x400f32a4 +#define CYREG_UDB_P1_U1_PLD_IT10 0x400f32a8 +#define CYREG_UDB_P1_U1_PLD_IT11 0x400f32ac +#define CYREG_UDB_P1_U1_PLD_ORT0 0x400f32b0 +#define CYREG_UDB_P1_U1_PLD_ORT1 0x400f32b2 +#define CYREG_UDB_P1_U1_PLD_ORT2 0x400f32b4 +#define CYREG_UDB_P1_U1_PLD_ORT3 0x400f32b6 +#define CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST 0x400f32b8 +#define CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB 0x400f32ba +#define CYREG_UDB_P1_U1_PLD_MC_SET_RESET 0x400f32bc +#define CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS 0x400f32be +#define CYREG_UDB_P1_U1_CFG0 0x400f32c0 +#define CYREG_UDB_P1_U1_CFG1 0x400f32c1 +#define CYREG_UDB_P1_U1_CFG2 0x400f32c2 +#define CYREG_UDB_P1_U1_CFG3 0x400f32c3 +#define CYREG_UDB_P1_U1_CFG4 0x400f32c4 +#define CYREG_UDB_P1_U1_CFG5 0x400f32c5 +#define CYREG_UDB_P1_U1_CFG6 0x400f32c6 +#define CYREG_UDB_P1_U1_CFG7 0x400f32c7 +#define CYREG_UDB_P1_U1_CFG8 0x400f32c8 +#define CYREG_UDB_P1_U1_CFG9 0x400f32c9 +#define CYREG_UDB_P1_U1_CFG10 0x400f32ca +#define CYREG_UDB_P1_U1_CFG11 0x400f32cb +#define CYREG_UDB_P1_U1_CFG12 0x400f32cc +#define CYREG_UDB_P1_U1_CFG13 0x400f32cd +#define CYREG_UDB_P1_U1_CFG14 0x400f32ce +#define CYREG_UDB_P1_U1_CFG15 0x400f32cf +#define CYREG_UDB_P1_U1_CFG16 0x400f32d0 +#define CYREG_UDB_P1_U1_CFG17 0x400f32d1 +#define CYREG_UDB_P1_U1_CFG18 0x400f32d2 +#define CYREG_UDB_P1_U1_CFG19 0x400f32d3 +#define CYREG_UDB_P1_U1_CFG20 0x400f32d4 +#define CYREG_UDB_P1_U1_CFG21 0x400f32d5 +#define CYREG_UDB_P1_U1_CFG22 0x400f32d6 +#define CYREG_UDB_P1_U1_CFG23 0x400f32d7 +#define CYREG_UDB_P1_U1_CFG24 0x400f32d8 +#define CYREG_UDB_P1_U1_CFG25 0x400f32d9 +#define CYREG_UDB_P1_U1_CFG26 0x400f32da +#define CYREG_UDB_P1_U1_CFG27 0x400f32db +#define CYREG_UDB_P1_U1_CFG28 0x400f32dc +#define CYREG_UDB_P1_U1_CFG29 0x400f32dd +#define CYREG_UDB_P1_U1_CFG30 0x400f32de +#define CYREG_UDB_P1_U1_CFG31 0x400f32df +#define CYREG_UDB_P1_U1_DCFG0 0x400f32e0 +#define CYREG_UDB_P1_U1_DCFG1 0x400f32e2 +#define CYREG_UDB_P1_U1_DCFG2 0x400f32e4 +#define CYREG_UDB_P1_U1_DCFG3 0x400f32e6 +#define CYREG_UDB_P1_U1_DCFG4 0x400f32e8 +#define CYREG_UDB_P1_U1_DCFG5 0x400f32ea +#define CYREG_UDB_P1_U1_DCFG6 0x400f32ec +#define CYREG_UDB_P1_U1_DCFG7 0x400f32ee +#define CYDEV_UDB_P1_ROUTE_BASE 0x400f3300 +#define CYDEV_UDB_P1_ROUTE_SIZE 0x00000100 +#define CYREG_UDB_P1_ROUTE_HC0 0x400f3300 +#define CYREG_UDB_P1_ROUTE_HC1 0x400f3301 +#define CYREG_UDB_P1_ROUTE_HC2 0x400f3302 +#define CYREG_UDB_P1_ROUTE_HC3 0x400f3303 +#define CYREG_UDB_P1_ROUTE_HC4 0x400f3304 +#define CYREG_UDB_P1_ROUTE_HC5 0x400f3305 +#define CYREG_UDB_P1_ROUTE_HC6 0x400f3306 +#define CYREG_UDB_P1_ROUTE_HC7 0x400f3307 +#define CYREG_UDB_P1_ROUTE_HC8 0x400f3308 +#define CYREG_UDB_P1_ROUTE_HC9 0x400f3309 +#define CYREG_UDB_P1_ROUTE_HC10 0x400f330a +#define CYREG_UDB_P1_ROUTE_HC11 0x400f330b +#define CYREG_UDB_P1_ROUTE_HC12 0x400f330c +#define CYREG_UDB_P1_ROUTE_HC13 0x400f330d +#define CYREG_UDB_P1_ROUTE_HC14 0x400f330e +#define CYREG_UDB_P1_ROUTE_HC15 0x400f330f +#define CYREG_UDB_P1_ROUTE_HC16 0x400f3310 +#define CYREG_UDB_P1_ROUTE_HC17 0x400f3311 +#define CYREG_UDB_P1_ROUTE_HC18 0x400f3312 +#define CYREG_UDB_P1_ROUTE_HC19 0x400f3313 +#define CYREG_UDB_P1_ROUTE_HC20 0x400f3314 +#define CYREG_UDB_P1_ROUTE_HC21 0x400f3315 +#define CYREG_UDB_P1_ROUTE_HC22 0x400f3316 +#define CYREG_UDB_P1_ROUTE_HC23 0x400f3317 +#define CYREG_UDB_P1_ROUTE_HC24 0x400f3318 +#define CYREG_UDB_P1_ROUTE_HC25 0x400f3319 +#define CYREG_UDB_P1_ROUTE_HC26 0x400f331a +#define CYREG_UDB_P1_ROUTE_HC27 0x400f331b +#define CYREG_UDB_P1_ROUTE_HC28 0x400f331c +#define CYREG_UDB_P1_ROUTE_HC29 0x400f331d +#define CYREG_UDB_P1_ROUTE_HC30 0x400f331e +#define CYREG_UDB_P1_ROUTE_HC31 0x400f331f +#define CYREG_UDB_P1_ROUTE_HC32 0x400f3320 +#define CYREG_UDB_P1_ROUTE_HC33 0x400f3321 +#define CYREG_UDB_P1_ROUTE_HC34 0x400f3322 +#define CYREG_UDB_P1_ROUTE_HC35 0x400f3323 +#define CYREG_UDB_P1_ROUTE_HC36 0x400f3324 +#define CYREG_UDB_P1_ROUTE_HC37 0x400f3325 +#define CYREG_UDB_P1_ROUTE_HC38 0x400f3326 +#define CYREG_UDB_P1_ROUTE_HC39 0x400f3327 +#define CYREG_UDB_P1_ROUTE_HC40 0x400f3328 +#define CYREG_UDB_P1_ROUTE_HC41 0x400f3329 +#define CYREG_UDB_P1_ROUTE_HC42 0x400f332a +#define CYREG_UDB_P1_ROUTE_HC43 0x400f332b +#define CYREG_UDB_P1_ROUTE_HC44 0x400f332c +#define CYREG_UDB_P1_ROUTE_HC45 0x400f332d +#define CYREG_UDB_P1_ROUTE_HC46 0x400f332e +#define CYREG_UDB_P1_ROUTE_HC47 0x400f332f +#define CYREG_UDB_P1_ROUTE_HC48 0x400f3330 +#define CYREG_UDB_P1_ROUTE_HC49 0x400f3331 +#define CYREG_UDB_P1_ROUTE_HC50 0x400f3332 +#define CYREG_UDB_P1_ROUTE_HC51 0x400f3333 +#define CYREG_UDB_P1_ROUTE_HC52 0x400f3334 +#define CYREG_UDB_P1_ROUTE_HC53 0x400f3335 +#define CYREG_UDB_P1_ROUTE_HC54 0x400f3336 +#define CYREG_UDB_P1_ROUTE_HC55 0x400f3337 +#define CYREG_UDB_P1_ROUTE_HC56 0x400f3338 +#define CYREG_UDB_P1_ROUTE_HC57 0x400f3339 +#define CYREG_UDB_P1_ROUTE_HC58 0x400f333a +#define CYREG_UDB_P1_ROUTE_HC59 0x400f333b +#define CYREG_UDB_P1_ROUTE_HC60 0x400f333c +#define CYREG_UDB_P1_ROUTE_HC61 0x400f333d +#define CYREG_UDB_P1_ROUTE_HC62 0x400f333e +#define CYREG_UDB_P1_ROUTE_HC63 0x400f333f +#define CYREG_UDB_P1_ROUTE_HC64 0x400f3340 +#define CYREG_UDB_P1_ROUTE_HC65 0x400f3341 +#define CYREG_UDB_P1_ROUTE_HC66 0x400f3342 +#define CYREG_UDB_P1_ROUTE_HC67 0x400f3343 +#define CYREG_UDB_P1_ROUTE_HC68 0x400f3344 +#define CYREG_UDB_P1_ROUTE_HC69 0x400f3345 +#define CYREG_UDB_P1_ROUTE_HC70 0x400f3346 +#define CYREG_UDB_P1_ROUTE_HC71 0x400f3347 +#define CYREG_UDB_P1_ROUTE_HC72 0x400f3348 +#define CYREG_UDB_P1_ROUTE_HC73 0x400f3349 +#define CYREG_UDB_P1_ROUTE_HC74 0x400f334a +#define CYREG_UDB_P1_ROUTE_HC75 0x400f334b +#define CYREG_UDB_P1_ROUTE_HC76 0x400f334c +#define CYREG_UDB_P1_ROUTE_HC77 0x400f334d +#define CYREG_UDB_P1_ROUTE_HC78 0x400f334e +#define CYREG_UDB_P1_ROUTE_HC79 0x400f334f +#define CYREG_UDB_P1_ROUTE_HC80 0x400f3350 +#define CYREG_UDB_P1_ROUTE_HC81 0x400f3351 +#define CYREG_UDB_P1_ROUTE_HC82 0x400f3352 +#define CYREG_UDB_P1_ROUTE_HC83 0x400f3353 +#define CYREG_UDB_P1_ROUTE_HC84 0x400f3354 +#define CYREG_UDB_P1_ROUTE_HC85 0x400f3355 +#define CYREG_UDB_P1_ROUTE_HC86 0x400f3356 +#define CYREG_UDB_P1_ROUTE_HC87 0x400f3357 +#define CYREG_UDB_P1_ROUTE_HC88 0x400f3358 +#define CYREG_UDB_P1_ROUTE_HC89 0x400f3359 +#define CYREG_UDB_P1_ROUTE_HC90 0x400f335a +#define CYREG_UDB_P1_ROUTE_HC91 0x400f335b +#define CYREG_UDB_P1_ROUTE_HC92 0x400f335c +#define CYREG_UDB_P1_ROUTE_HC93 0x400f335d +#define CYREG_UDB_P1_ROUTE_HC94 0x400f335e +#define CYREG_UDB_P1_ROUTE_HC95 0x400f335f +#define CYREG_UDB_P1_ROUTE_HC96 0x400f3360 +#define CYREG_UDB_P1_ROUTE_HC97 0x400f3361 +#define CYREG_UDB_P1_ROUTE_HC98 0x400f3362 +#define CYREG_UDB_P1_ROUTE_HC99 0x400f3363 +#define CYREG_UDB_P1_ROUTE_HC100 0x400f3364 +#define CYREG_UDB_P1_ROUTE_HC101 0x400f3365 +#define CYREG_UDB_P1_ROUTE_HC102 0x400f3366 +#define CYREG_UDB_P1_ROUTE_HC103 0x400f3367 +#define CYREG_UDB_P1_ROUTE_HC104 0x400f3368 +#define CYREG_UDB_P1_ROUTE_HC105 0x400f3369 +#define CYREG_UDB_P1_ROUTE_HC106 0x400f336a +#define CYREG_UDB_P1_ROUTE_HC107 0x400f336b +#define CYREG_UDB_P1_ROUTE_HC108 0x400f336c +#define CYREG_UDB_P1_ROUTE_HC109 0x400f336d +#define CYREG_UDB_P1_ROUTE_HC110 0x400f336e +#define CYREG_UDB_P1_ROUTE_HC111 0x400f336f +#define CYREG_UDB_P1_ROUTE_HC112 0x400f3370 +#define CYREG_UDB_P1_ROUTE_HC113 0x400f3371 +#define CYREG_UDB_P1_ROUTE_HC114 0x400f3372 +#define CYREG_UDB_P1_ROUTE_HC115 0x400f3373 +#define CYREG_UDB_P1_ROUTE_HC116 0x400f3374 +#define CYREG_UDB_P1_ROUTE_HC117 0x400f3375 +#define CYREG_UDB_P1_ROUTE_HC118 0x400f3376 +#define CYREG_UDB_P1_ROUTE_HC119 0x400f3377 +#define CYREG_UDB_P1_ROUTE_HC120 0x400f3378 +#define CYREG_UDB_P1_ROUTE_HC121 0x400f3379 +#define CYREG_UDB_P1_ROUTE_HC122 0x400f337a +#define CYREG_UDB_P1_ROUTE_HC123 0x400f337b +#define CYREG_UDB_P1_ROUTE_HC124 0x400f337c +#define CYREG_UDB_P1_ROUTE_HC125 0x400f337d +#define CYREG_UDB_P1_ROUTE_HC126 0x400f337e +#define CYREG_UDB_P1_ROUTE_HC127 0x400f337f +#define CYREG_UDB_P1_ROUTE_HV_L0 0x400f3380 +#define CYREG_UDB_P1_ROUTE_HV_L1 0x400f3381 +#define CYREG_UDB_P1_ROUTE_HV_L2 0x400f3382 +#define CYREG_UDB_P1_ROUTE_HV_L3 0x400f3383 +#define CYREG_UDB_P1_ROUTE_HV_L4 0x400f3384 +#define CYREG_UDB_P1_ROUTE_HV_L5 0x400f3385 +#define CYREG_UDB_P1_ROUTE_HV_L6 0x400f3386 +#define CYREG_UDB_P1_ROUTE_HV_L7 0x400f3387 +#define CYREG_UDB_P1_ROUTE_HV_L8 0x400f3388 +#define CYREG_UDB_P1_ROUTE_HV_L9 0x400f3389 +#define CYREG_UDB_P1_ROUTE_HV_L10 0x400f338a +#define CYREG_UDB_P1_ROUTE_HV_L11 0x400f338b +#define CYREG_UDB_P1_ROUTE_HV_L12 0x400f338c +#define CYREG_UDB_P1_ROUTE_HV_L13 0x400f338d +#define CYREG_UDB_P1_ROUTE_HV_L14 0x400f338e +#define CYREG_UDB_P1_ROUTE_HV_L15 0x400f338f +#define CYREG_UDB_P1_ROUTE_HS0 0x400f3390 +#define CYREG_UDB_P1_ROUTE_HS1 0x400f3391 +#define CYREG_UDB_P1_ROUTE_HS2 0x400f3392 +#define CYREG_UDB_P1_ROUTE_HS3 0x400f3393 +#define CYREG_UDB_P1_ROUTE_HS4 0x400f3394 +#define CYREG_UDB_P1_ROUTE_HS5 0x400f3395 +#define CYREG_UDB_P1_ROUTE_HS6 0x400f3396 +#define CYREG_UDB_P1_ROUTE_HS7 0x400f3397 +#define CYREG_UDB_P1_ROUTE_HS8 0x400f3398 +#define CYREG_UDB_P1_ROUTE_HS9 0x400f3399 +#define CYREG_UDB_P1_ROUTE_HS10 0x400f339a +#define CYREG_UDB_P1_ROUTE_HS11 0x400f339b +#define CYREG_UDB_P1_ROUTE_HS12 0x400f339c +#define CYREG_UDB_P1_ROUTE_HS13 0x400f339d +#define CYREG_UDB_P1_ROUTE_HS14 0x400f339e +#define CYREG_UDB_P1_ROUTE_HS15 0x400f339f +#define CYREG_UDB_P1_ROUTE_HS16 0x400f33a0 +#define CYREG_UDB_P1_ROUTE_HS17 0x400f33a1 +#define CYREG_UDB_P1_ROUTE_HS18 0x400f33a2 +#define CYREG_UDB_P1_ROUTE_HS19 0x400f33a3 +#define CYREG_UDB_P1_ROUTE_HS20 0x400f33a4 +#define CYREG_UDB_P1_ROUTE_HS21 0x400f33a5 +#define CYREG_UDB_P1_ROUTE_HS22 0x400f33a6 +#define CYREG_UDB_P1_ROUTE_HS23 0x400f33a7 +#define CYREG_UDB_P1_ROUTE_HV_R0 0x400f33a8 +#define CYREG_UDB_P1_ROUTE_HV_R1 0x400f33a9 +#define CYREG_UDB_P1_ROUTE_HV_R2 0x400f33aa +#define CYREG_UDB_P1_ROUTE_HV_R3 0x400f33ab +#define CYREG_UDB_P1_ROUTE_HV_R4 0x400f33ac +#define CYREG_UDB_P1_ROUTE_HV_R5 0x400f33ad +#define CYREG_UDB_P1_ROUTE_HV_R6 0x400f33ae +#define CYREG_UDB_P1_ROUTE_HV_R7 0x400f33af +#define CYREG_UDB_P1_ROUTE_HV_R8 0x400f33b0 +#define CYREG_UDB_P1_ROUTE_HV_R9 0x400f33b1 +#define CYREG_UDB_P1_ROUTE_HV_R10 0x400f33b2 +#define CYREG_UDB_P1_ROUTE_HV_R11 0x400f33b3 +#define CYREG_UDB_P1_ROUTE_HV_R12 0x400f33b4 +#define CYREG_UDB_P1_ROUTE_HV_R13 0x400f33b5 +#define CYREG_UDB_P1_ROUTE_HV_R14 0x400f33b6 +#define CYREG_UDB_P1_ROUTE_HV_R15 0x400f33b7 +#define CYREG_UDB_P1_ROUTE_PLD0IN0 0x400f33c0 +#define CYREG_UDB_P1_ROUTE_PLD0IN1 0x400f33c2 +#define CYREG_UDB_P1_ROUTE_PLD0IN2 0x400f33c4 +#define CYREG_UDB_P1_ROUTE_PLD1IN0 0x400f33ca +#define CYREG_UDB_P1_ROUTE_PLD1IN1 0x400f33cc +#define CYREG_UDB_P1_ROUTE_PLD1IN2 0x400f33ce +#define CYREG_UDB_P1_ROUTE_DPIN0 0x400f33d0 +#define CYREG_UDB_P1_ROUTE_DPIN1 0x400f33d2 +#define CYREG_UDB_P1_ROUTE_SCIN 0x400f33d6 +#define CYREG_UDB_P1_ROUTE_SCIOIN 0x400f33d8 +#define CYREG_UDB_P1_ROUTE_RCIN 0x400f33de +#define CYREG_UDB_P1_ROUTE_VS0 0x400f33e0 +#define CYREG_UDB_P1_ROUTE_VS1 0x400f33e2 +#define CYREG_UDB_P1_ROUTE_VS2 0x400f33e4 +#define CYREG_UDB_P1_ROUTE_VS3 0x400f33e6 +#define CYREG_UDB_P1_ROUTE_VS4 0x400f33e8 +#define CYREG_UDB_P1_ROUTE_VS5 0x400f33ea +#define CYREG_UDB_P1_ROUTE_VS6 0x400f33ec +#define CYREG_UDB_P1_ROUTE_VS7 0x400f33ee +#define CYDEV_UDB_DSI0_BASE 0x400f4000 +#define CYDEV_UDB_DSI0_SIZE 0x00000100 +#define CYREG_UDB_DSI0_HC0 0x400f4000 +#define CYFLD_UDB_DSI_HC_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_HC_BYTE__SIZE 0x00000008 +#define CYREG_UDB_DSI0_HC1 0x400f4001 +#define CYREG_UDB_DSI0_HC2 0x400f4002 +#define CYREG_UDB_DSI0_HC3 0x400f4003 +#define CYREG_UDB_DSI0_HC4 0x400f4004 +#define CYREG_UDB_DSI0_HC5 0x400f4005 +#define CYREG_UDB_DSI0_HC6 0x400f4006 +#define CYREG_UDB_DSI0_HC7 0x400f4007 +#define CYREG_UDB_DSI0_HC8 0x400f4008 +#define CYREG_UDB_DSI0_HC9 0x400f4009 +#define CYREG_UDB_DSI0_HC10 0x400f400a +#define CYREG_UDB_DSI0_HC11 0x400f400b +#define CYREG_UDB_DSI0_HC12 0x400f400c +#define CYREG_UDB_DSI0_HC13 0x400f400d +#define CYREG_UDB_DSI0_HC14 0x400f400e +#define CYREG_UDB_DSI0_HC15 0x400f400f +#define CYREG_UDB_DSI0_HC16 0x400f4010 +#define CYREG_UDB_DSI0_HC17 0x400f4011 +#define CYREG_UDB_DSI0_HC18 0x400f4012 +#define CYREG_UDB_DSI0_HC19 0x400f4013 +#define CYREG_UDB_DSI0_HC20 0x400f4014 +#define CYREG_UDB_DSI0_HC21 0x400f4015 +#define CYREG_UDB_DSI0_HC22 0x400f4016 +#define CYREG_UDB_DSI0_HC23 0x400f4017 +#define CYREG_UDB_DSI0_HC24 0x400f4018 +#define CYREG_UDB_DSI0_HC25 0x400f4019 +#define CYREG_UDB_DSI0_HC26 0x400f401a +#define CYREG_UDB_DSI0_HC27 0x400f401b +#define CYREG_UDB_DSI0_HC28 0x400f401c +#define CYREG_UDB_DSI0_HC29 0x400f401d +#define CYREG_UDB_DSI0_HC30 0x400f401e +#define CYREG_UDB_DSI0_HC31 0x400f401f +#define CYREG_UDB_DSI0_HC32 0x400f4020 +#define CYREG_UDB_DSI0_HC33 0x400f4021 +#define CYREG_UDB_DSI0_HC34 0x400f4022 +#define CYREG_UDB_DSI0_HC35 0x400f4023 +#define CYREG_UDB_DSI0_HC36 0x400f4024 +#define CYREG_UDB_DSI0_HC37 0x400f4025 +#define CYREG_UDB_DSI0_HC38 0x400f4026 +#define CYREG_UDB_DSI0_HC39 0x400f4027 +#define CYREG_UDB_DSI0_HC40 0x400f4028 +#define CYREG_UDB_DSI0_HC41 0x400f4029 +#define CYREG_UDB_DSI0_HC42 0x400f402a +#define CYREG_UDB_DSI0_HC43 0x400f402b +#define CYREG_UDB_DSI0_HC44 0x400f402c +#define CYREG_UDB_DSI0_HC45 0x400f402d +#define CYREG_UDB_DSI0_HC46 0x400f402e +#define CYREG_UDB_DSI0_HC47 0x400f402f +#define CYREG_UDB_DSI0_HC48 0x400f4030 +#define CYREG_UDB_DSI0_HC49 0x400f4031 +#define CYREG_UDB_DSI0_HC50 0x400f4032 +#define CYREG_UDB_DSI0_HC51 0x400f4033 +#define CYREG_UDB_DSI0_HC52 0x400f4034 +#define CYREG_UDB_DSI0_HC53 0x400f4035 +#define CYREG_UDB_DSI0_HC54 0x400f4036 +#define CYREG_UDB_DSI0_HC55 0x400f4037 +#define CYREG_UDB_DSI0_HC56 0x400f4038 +#define CYREG_UDB_DSI0_HC57 0x400f4039 +#define CYREG_UDB_DSI0_HC58 0x400f403a +#define CYREG_UDB_DSI0_HC59 0x400f403b +#define CYREG_UDB_DSI0_HC60 0x400f403c +#define CYREG_UDB_DSI0_HC61 0x400f403d +#define CYREG_UDB_DSI0_HC62 0x400f403e +#define CYREG_UDB_DSI0_HC63 0x400f403f +#define CYREG_UDB_DSI0_HC64 0x400f4040 +#define CYREG_UDB_DSI0_HC65 0x400f4041 +#define CYREG_UDB_DSI0_HC66 0x400f4042 +#define CYREG_UDB_DSI0_HC67 0x400f4043 +#define CYREG_UDB_DSI0_HC68 0x400f4044 +#define CYREG_UDB_DSI0_HC69 0x400f4045 +#define CYREG_UDB_DSI0_HC70 0x400f4046 +#define CYREG_UDB_DSI0_HC71 0x400f4047 +#define CYREG_UDB_DSI0_HC72 0x400f4048 +#define CYREG_UDB_DSI0_HC73 0x400f4049 +#define CYREG_UDB_DSI0_HC74 0x400f404a +#define CYREG_UDB_DSI0_HC75 0x400f404b +#define CYREG_UDB_DSI0_HC76 0x400f404c +#define CYREG_UDB_DSI0_HC77 0x400f404d +#define CYREG_UDB_DSI0_HC78 0x400f404e +#define CYREG_UDB_DSI0_HC79 0x400f404f +#define CYREG_UDB_DSI0_HC80 0x400f4050 +#define CYREG_UDB_DSI0_HC81 0x400f4051 +#define CYREG_UDB_DSI0_HC82 0x400f4052 +#define CYREG_UDB_DSI0_HC83 0x400f4053 +#define CYREG_UDB_DSI0_HC84 0x400f4054 +#define CYREG_UDB_DSI0_HC85 0x400f4055 +#define CYREG_UDB_DSI0_HC86 0x400f4056 +#define CYREG_UDB_DSI0_HC87 0x400f4057 +#define CYREG_UDB_DSI0_HC88 0x400f4058 +#define CYREG_UDB_DSI0_HC89 0x400f4059 +#define CYREG_UDB_DSI0_HC90 0x400f405a +#define CYREG_UDB_DSI0_HC91 0x400f405b +#define CYREG_UDB_DSI0_HC92 0x400f405c +#define CYREG_UDB_DSI0_HC93 0x400f405d +#define CYREG_UDB_DSI0_HC94 0x400f405e +#define CYREG_UDB_DSI0_HC95 0x400f405f +#define CYREG_UDB_DSI0_HC96 0x400f4060 +#define CYREG_UDB_DSI0_HC97 0x400f4061 +#define CYREG_UDB_DSI0_HC98 0x400f4062 +#define CYREG_UDB_DSI0_HC99 0x400f4063 +#define CYREG_UDB_DSI0_HC100 0x400f4064 +#define CYREG_UDB_DSI0_HC101 0x400f4065 +#define CYREG_UDB_DSI0_HC102 0x400f4066 +#define CYREG_UDB_DSI0_HC103 0x400f4067 +#define CYREG_UDB_DSI0_HC104 0x400f4068 +#define CYREG_UDB_DSI0_HC105 0x400f4069 +#define CYREG_UDB_DSI0_HC106 0x400f406a +#define CYREG_UDB_DSI0_HC107 0x400f406b +#define CYREG_UDB_DSI0_HC108 0x400f406c +#define CYREG_UDB_DSI0_HC109 0x400f406d +#define CYREG_UDB_DSI0_HC110 0x400f406e +#define CYREG_UDB_DSI0_HC111 0x400f406f +#define CYREG_UDB_DSI0_HC112 0x400f4070 +#define CYREG_UDB_DSI0_HC113 0x400f4071 +#define CYREG_UDB_DSI0_HC114 0x400f4072 +#define CYREG_UDB_DSI0_HC115 0x400f4073 +#define CYREG_UDB_DSI0_HC116 0x400f4074 +#define CYREG_UDB_DSI0_HC117 0x400f4075 +#define CYREG_UDB_DSI0_HC118 0x400f4076 +#define CYREG_UDB_DSI0_HC119 0x400f4077 +#define CYREG_UDB_DSI0_HC120 0x400f4078 +#define CYREG_UDB_DSI0_HC121 0x400f4079 +#define CYREG_UDB_DSI0_HC122 0x400f407a +#define CYREG_UDB_DSI0_HC123 0x400f407b +#define CYREG_UDB_DSI0_HC124 0x400f407c +#define CYREG_UDB_DSI0_HC125 0x400f407d +#define CYREG_UDB_DSI0_HC126 0x400f407e +#define CYREG_UDB_DSI0_HC127 0x400f407f +#define CYREG_UDB_DSI0_HV_L0 0x400f4080 +#define CYFLD_UDB_DSI_HV_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_HV_BYTE__SIZE 0x00000008 +#define CYREG_UDB_DSI0_HV_L1 0x400f4081 +#define CYREG_UDB_DSI0_HV_L2 0x400f4082 +#define CYREG_UDB_DSI0_HV_L3 0x400f4083 +#define CYREG_UDB_DSI0_HV_L4 0x400f4084 +#define CYREG_UDB_DSI0_HV_L5 0x400f4085 +#define CYREG_UDB_DSI0_HV_L6 0x400f4086 +#define CYREG_UDB_DSI0_HV_L7 0x400f4087 +#define CYREG_UDB_DSI0_HV_L8 0x400f4088 +#define CYREG_UDB_DSI0_HV_L9 0x400f4089 +#define CYREG_UDB_DSI0_HV_L10 0x400f408a +#define CYREG_UDB_DSI0_HV_L11 0x400f408b +#define CYREG_UDB_DSI0_HV_L12 0x400f408c +#define CYREG_UDB_DSI0_HV_L13 0x400f408d +#define CYREG_UDB_DSI0_HV_L14 0x400f408e +#define CYREG_UDB_DSI0_HV_L15 0x400f408f +#define CYREG_UDB_DSI0_HS0 0x400f4090 +#define CYFLD_UDB_DSI_HS_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_HS_BYTE__SIZE 0x00000008 +#define CYREG_UDB_DSI0_HS1 0x400f4091 +#define CYREG_UDB_DSI0_HS2 0x400f4092 +#define CYREG_UDB_DSI0_HS3 0x400f4093 +#define CYREG_UDB_DSI0_HS4 0x400f4094 +#define CYREG_UDB_DSI0_HS5 0x400f4095 +#define CYREG_UDB_DSI0_HS6 0x400f4096 +#define CYREG_UDB_DSI0_HS7 0x400f4097 +#define CYREG_UDB_DSI0_HS8 0x400f4098 +#define CYREG_UDB_DSI0_HS9 0x400f4099 +#define CYREG_UDB_DSI0_HS10 0x400f409a +#define CYREG_UDB_DSI0_HS11 0x400f409b +#define CYREG_UDB_DSI0_HS12 0x400f409c +#define CYREG_UDB_DSI0_HS13 0x400f409d +#define CYREG_UDB_DSI0_HS14 0x400f409e +#define CYREG_UDB_DSI0_HS15 0x400f409f +#define CYREG_UDB_DSI0_HS16 0x400f40a0 +#define CYREG_UDB_DSI0_HS17 0x400f40a1 +#define CYREG_UDB_DSI0_HS18 0x400f40a2 +#define CYREG_UDB_DSI0_HS19 0x400f40a3 +#define CYREG_UDB_DSI0_HS20 0x400f40a4 +#define CYREG_UDB_DSI0_HS21 0x400f40a5 +#define CYREG_UDB_DSI0_HS22 0x400f40a6 +#define CYREG_UDB_DSI0_HS23 0x400f40a7 +#define CYREG_UDB_DSI0_HV_R0 0x400f40a8 +#define CYREG_UDB_DSI0_HV_R1 0x400f40a9 +#define CYREG_UDB_DSI0_HV_R2 0x400f40aa +#define CYREG_UDB_DSI0_HV_R3 0x400f40ab +#define CYREG_UDB_DSI0_HV_R4 0x400f40ac +#define CYREG_UDB_DSI0_HV_R5 0x400f40ad +#define CYREG_UDB_DSI0_HV_R6 0x400f40ae +#define CYREG_UDB_DSI0_HV_R7 0x400f40af +#define CYREG_UDB_DSI0_HV_R8 0x400f40b0 +#define CYREG_UDB_DSI0_HV_R9 0x400f40b1 +#define CYREG_UDB_DSI0_HV_R10 0x400f40b2 +#define CYREG_UDB_DSI0_HV_R11 0x400f40b3 +#define CYREG_UDB_DSI0_HV_R12 0x400f40b4 +#define CYREG_UDB_DSI0_HV_R13 0x400f40b5 +#define CYREG_UDB_DSI0_HV_R14 0x400f40b6 +#define CYREG_UDB_DSI0_HV_R15 0x400f40b7 +#define CYREG_UDB_DSI0_DSIINP0 0x400f40c0 +#define CYFLD_UDB_DSI_PI_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_PI_TOP__SIZE 0x00000004 +#define CYFLD_UDB_DSI_PI_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_DSI_PI_BOT__SIZE 0x00000004 +#define CYREG_UDB_DSI0_DSIINP1 0x400f40c2 +#define CYREG_UDB_DSI0_DSIINP2 0x400f40c4 +#define CYREG_UDB_DSI0_DSIINP3 0x400f40c6 +#define CYREG_UDB_DSI0_DSIINP4 0x400f40c8 +#define CYREG_UDB_DSI0_DSIINP5 0x400f40ca +#define CYREG_UDB_DSI0_DSIOUTP0 0x400f40cc +#define CYREG_UDB_DSI0_DSIOUTP1 0x400f40ce +#define CYREG_UDB_DSI0_DSIOUTP2 0x400f40d0 +#define CYREG_UDB_DSI0_DSIOUTP3 0x400f40d2 +#define CYREG_UDB_DSI0_DSIOUTT0 0x400f40d4 +#define CYREG_UDB_DSI0_DSIOUTT1 0x400f40d6 +#define CYREG_UDB_DSI0_DSIOUTT2 0x400f40d8 +#define CYREG_UDB_DSI0_DSIOUTT3 0x400f40da +#define CYREG_UDB_DSI0_DSIOUTT4 0x400f40dc +#define CYREG_UDB_DSI0_DSIOUTT5 0x400f40de +#define CYREG_UDB_DSI0_VS0 0x400f40e0 +#define CYFLD_UDB_DSI_VS_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_VS_TOP__SIZE 0x00000004 +#define CYFLD_UDB_DSI_VS_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_DSI_VS_BOT__SIZE 0x00000004 +#define CYREG_UDB_DSI0_VS1 0x400f40e2 +#define CYREG_UDB_DSI0_VS2 0x400f40e4 +#define CYREG_UDB_DSI0_VS3 0x400f40e6 +#define CYREG_UDB_DSI0_VS4 0x400f40e8 +#define CYREG_UDB_DSI0_VS5 0x400f40ea +#define CYREG_UDB_DSI0_VS6 0x400f40ec +#define CYREG_UDB_DSI0_VS7 0x400f40ee +#define CYDEV_UDB_DSI1_BASE 0x400f4100 +#define CYDEV_UDB_DSI1_SIZE 0x00000100 +#define CYREG_UDB_DSI1_HC0 0x400f4100 +#define CYREG_UDB_DSI1_HC1 0x400f4101 +#define CYREG_UDB_DSI1_HC2 0x400f4102 +#define CYREG_UDB_DSI1_HC3 0x400f4103 +#define CYREG_UDB_DSI1_HC4 0x400f4104 +#define CYREG_UDB_DSI1_HC5 0x400f4105 +#define CYREG_UDB_DSI1_HC6 0x400f4106 +#define CYREG_UDB_DSI1_HC7 0x400f4107 +#define CYREG_UDB_DSI1_HC8 0x400f4108 +#define CYREG_UDB_DSI1_HC9 0x400f4109 +#define CYREG_UDB_DSI1_HC10 0x400f410a +#define CYREG_UDB_DSI1_HC11 0x400f410b +#define CYREG_UDB_DSI1_HC12 0x400f410c +#define CYREG_UDB_DSI1_HC13 0x400f410d +#define CYREG_UDB_DSI1_HC14 0x400f410e +#define CYREG_UDB_DSI1_HC15 0x400f410f +#define CYREG_UDB_DSI1_HC16 0x400f4110 +#define CYREG_UDB_DSI1_HC17 0x400f4111 +#define CYREG_UDB_DSI1_HC18 0x400f4112 +#define CYREG_UDB_DSI1_HC19 0x400f4113 +#define CYREG_UDB_DSI1_HC20 0x400f4114 +#define CYREG_UDB_DSI1_HC21 0x400f4115 +#define CYREG_UDB_DSI1_HC22 0x400f4116 +#define CYREG_UDB_DSI1_HC23 0x400f4117 +#define CYREG_UDB_DSI1_HC24 0x400f4118 +#define CYREG_UDB_DSI1_HC25 0x400f4119 +#define CYREG_UDB_DSI1_HC26 0x400f411a +#define CYREG_UDB_DSI1_HC27 0x400f411b +#define CYREG_UDB_DSI1_HC28 0x400f411c +#define CYREG_UDB_DSI1_HC29 0x400f411d +#define CYREG_UDB_DSI1_HC30 0x400f411e +#define CYREG_UDB_DSI1_HC31 0x400f411f +#define CYREG_UDB_DSI1_HC32 0x400f4120 +#define CYREG_UDB_DSI1_HC33 0x400f4121 +#define CYREG_UDB_DSI1_HC34 0x400f4122 +#define CYREG_UDB_DSI1_HC35 0x400f4123 +#define CYREG_UDB_DSI1_HC36 0x400f4124 +#define CYREG_UDB_DSI1_HC37 0x400f4125 +#define CYREG_UDB_DSI1_HC38 0x400f4126 +#define CYREG_UDB_DSI1_HC39 0x400f4127 +#define CYREG_UDB_DSI1_HC40 0x400f4128 +#define CYREG_UDB_DSI1_HC41 0x400f4129 +#define CYREG_UDB_DSI1_HC42 0x400f412a +#define CYREG_UDB_DSI1_HC43 0x400f412b +#define CYREG_UDB_DSI1_HC44 0x400f412c +#define CYREG_UDB_DSI1_HC45 0x400f412d +#define CYREG_UDB_DSI1_HC46 0x400f412e +#define CYREG_UDB_DSI1_HC47 0x400f412f +#define CYREG_UDB_DSI1_HC48 0x400f4130 +#define CYREG_UDB_DSI1_HC49 0x400f4131 +#define CYREG_UDB_DSI1_HC50 0x400f4132 +#define CYREG_UDB_DSI1_HC51 0x400f4133 +#define CYREG_UDB_DSI1_HC52 0x400f4134 +#define CYREG_UDB_DSI1_HC53 0x400f4135 +#define CYREG_UDB_DSI1_HC54 0x400f4136 +#define CYREG_UDB_DSI1_HC55 0x400f4137 +#define CYREG_UDB_DSI1_HC56 0x400f4138 +#define CYREG_UDB_DSI1_HC57 0x400f4139 +#define CYREG_UDB_DSI1_HC58 0x400f413a +#define CYREG_UDB_DSI1_HC59 0x400f413b +#define CYREG_UDB_DSI1_HC60 0x400f413c +#define CYREG_UDB_DSI1_HC61 0x400f413d +#define CYREG_UDB_DSI1_HC62 0x400f413e +#define CYREG_UDB_DSI1_HC63 0x400f413f +#define CYREG_UDB_DSI1_HC64 0x400f4140 +#define CYREG_UDB_DSI1_HC65 0x400f4141 +#define CYREG_UDB_DSI1_HC66 0x400f4142 +#define CYREG_UDB_DSI1_HC67 0x400f4143 +#define CYREG_UDB_DSI1_HC68 0x400f4144 +#define CYREG_UDB_DSI1_HC69 0x400f4145 +#define CYREG_UDB_DSI1_HC70 0x400f4146 +#define CYREG_UDB_DSI1_HC71 0x400f4147 +#define CYREG_UDB_DSI1_HC72 0x400f4148 +#define CYREG_UDB_DSI1_HC73 0x400f4149 +#define CYREG_UDB_DSI1_HC74 0x400f414a +#define CYREG_UDB_DSI1_HC75 0x400f414b +#define CYREG_UDB_DSI1_HC76 0x400f414c +#define CYREG_UDB_DSI1_HC77 0x400f414d +#define CYREG_UDB_DSI1_HC78 0x400f414e +#define CYREG_UDB_DSI1_HC79 0x400f414f +#define CYREG_UDB_DSI1_HC80 0x400f4150 +#define CYREG_UDB_DSI1_HC81 0x400f4151 +#define CYREG_UDB_DSI1_HC82 0x400f4152 +#define CYREG_UDB_DSI1_HC83 0x400f4153 +#define CYREG_UDB_DSI1_HC84 0x400f4154 +#define CYREG_UDB_DSI1_HC85 0x400f4155 +#define CYREG_UDB_DSI1_HC86 0x400f4156 +#define CYREG_UDB_DSI1_HC87 0x400f4157 +#define CYREG_UDB_DSI1_HC88 0x400f4158 +#define CYREG_UDB_DSI1_HC89 0x400f4159 +#define CYREG_UDB_DSI1_HC90 0x400f415a +#define CYREG_UDB_DSI1_HC91 0x400f415b +#define CYREG_UDB_DSI1_HC92 0x400f415c +#define CYREG_UDB_DSI1_HC93 0x400f415d +#define CYREG_UDB_DSI1_HC94 0x400f415e +#define CYREG_UDB_DSI1_HC95 0x400f415f +#define CYREG_UDB_DSI1_HC96 0x400f4160 +#define CYREG_UDB_DSI1_HC97 0x400f4161 +#define CYREG_UDB_DSI1_HC98 0x400f4162 +#define CYREG_UDB_DSI1_HC99 0x400f4163 +#define CYREG_UDB_DSI1_HC100 0x400f4164 +#define CYREG_UDB_DSI1_HC101 0x400f4165 +#define CYREG_UDB_DSI1_HC102 0x400f4166 +#define CYREG_UDB_DSI1_HC103 0x400f4167 +#define CYREG_UDB_DSI1_HC104 0x400f4168 +#define CYREG_UDB_DSI1_HC105 0x400f4169 +#define CYREG_UDB_DSI1_HC106 0x400f416a +#define CYREG_UDB_DSI1_HC107 0x400f416b +#define CYREG_UDB_DSI1_HC108 0x400f416c +#define CYREG_UDB_DSI1_HC109 0x400f416d +#define CYREG_UDB_DSI1_HC110 0x400f416e +#define CYREG_UDB_DSI1_HC111 0x400f416f +#define CYREG_UDB_DSI1_HC112 0x400f4170 +#define CYREG_UDB_DSI1_HC113 0x400f4171 +#define CYREG_UDB_DSI1_HC114 0x400f4172 +#define CYREG_UDB_DSI1_HC115 0x400f4173 +#define CYREG_UDB_DSI1_HC116 0x400f4174 +#define CYREG_UDB_DSI1_HC117 0x400f4175 +#define CYREG_UDB_DSI1_HC118 0x400f4176 +#define CYREG_UDB_DSI1_HC119 0x400f4177 +#define CYREG_UDB_DSI1_HC120 0x400f4178 +#define CYREG_UDB_DSI1_HC121 0x400f4179 +#define CYREG_UDB_DSI1_HC122 0x400f417a +#define CYREG_UDB_DSI1_HC123 0x400f417b +#define CYREG_UDB_DSI1_HC124 0x400f417c +#define CYREG_UDB_DSI1_HC125 0x400f417d +#define CYREG_UDB_DSI1_HC126 0x400f417e +#define CYREG_UDB_DSI1_HC127 0x400f417f +#define CYREG_UDB_DSI1_HV_L0 0x400f4180 +#define CYREG_UDB_DSI1_HV_L1 0x400f4181 +#define CYREG_UDB_DSI1_HV_L2 0x400f4182 +#define CYREG_UDB_DSI1_HV_L3 0x400f4183 +#define CYREG_UDB_DSI1_HV_L4 0x400f4184 +#define CYREG_UDB_DSI1_HV_L5 0x400f4185 +#define CYREG_UDB_DSI1_HV_L6 0x400f4186 +#define CYREG_UDB_DSI1_HV_L7 0x400f4187 +#define CYREG_UDB_DSI1_HV_L8 0x400f4188 +#define CYREG_UDB_DSI1_HV_L9 0x400f4189 +#define CYREG_UDB_DSI1_HV_L10 0x400f418a +#define CYREG_UDB_DSI1_HV_L11 0x400f418b +#define CYREG_UDB_DSI1_HV_L12 0x400f418c +#define CYREG_UDB_DSI1_HV_L13 0x400f418d +#define CYREG_UDB_DSI1_HV_L14 0x400f418e +#define CYREG_UDB_DSI1_HV_L15 0x400f418f +#define CYREG_UDB_DSI1_HS0 0x400f4190 +#define CYREG_UDB_DSI1_HS1 0x400f4191 +#define CYREG_UDB_DSI1_HS2 0x400f4192 +#define CYREG_UDB_DSI1_HS3 0x400f4193 +#define CYREG_UDB_DSI1_HS4 0x400f4194 +#define CYREG_UDB_DSI1_HS5 0x400f4195 +#define CYREG_UDB_DSI1_HS6 0x400f4196 +#define CYREG_UDB_DSI1_HS7 0x400f4197 +#define CYREG_UDB_DSI1_HS8 0x400f4198 +#define CYREG_UDB_DSI1_HS9 0x400f4199 +#define CYREG_UDB_DSI1_HS10 0x400f419a +#define CYREG_UDB_DSI1_HS11 0x400f419b +#define CYREG_UDB_DSI1_HS12 0x400f419c +#define CYREG_UDB_DSI1_HS13 0x400f419d +#define CYREG_UDB_DSI1_HS14 0x400f419e +#define CYREG_UDB_DSI1_HS15 0x400f419f +#define CYREG_UDB_DSI1_HS16 0x400f41a0 +#define CYREG_UDB_DSI1_HS17 0x400f41a1 +#define CYREG_UDB_DSI1_HS18 0x400f41a2 +#define CYREG_UDB_DSI1_HS19 0x400f41a3 +#define CYREG_UDB_DSI1_HS20 0x400f41a4 +#define CYREG_UDB_DSI1_HS21 0x400f41a5 +#define CYREG_UDB_DSI1_HS22 0x400f41a6 +#define CYREG_UDB_DSI1_HS23 0x400f41a7 +#define CYREG_UDB_DSI1_HV_R0 0x400f41a8 +#define CYREG_UDB_DSI1_HV_R1 0x400f41a9 +#define CYREG_UDB_DSI1_HV_R2 0x400f41aa +#define CYREG_UDB_DSI1_HV_R3 0x400f41ab +#define CYREG_UDB_DSI1_HV_R4 0x400f41ac +#define CYREG_UDB_DSI1_HV_R5 0x400f41ad +#define CYREG_UDB_DSI1_HV_R6 0x400f41ae +#define CYREG_UDB_DSI1_HV_R7 0x400f41af +#define CYREG_UDB_DSI1_HV_R8 0x400f41b0 +#define CYREG_UDB_DSI1_HV_R9 0x400f41b1 +#define CYREG_UDB_DSI1_HV_R10 0x400f41b2 +#define CYREG_UDB_DSI1_HV_R11 0x400f41b3 +#define CYREG_UDB_DSI1_HV_R12 0x400f41b4 +#define CYREG_UDB_DSI1_HV_R13 0x400f41b5 +#define CYREG_UDB_DSI1_HV_R14 0x400f41b6 +#define CYREG_UDB_DSI1_HV_R15 0x400f41b7 +#define CYREG_UDB_DSI1_DSIINP0 0x400f41c0 +#define CYREG_UDB_DSI1_DSIINP1 0x400f41c2 +#define CYREG_UDB_DSI1_DSIINP2 0x400f41c4 +#define CYREG_UDB_DSI1_DSIINP3 0x400f41c6 +#define CYREG_UDB_DSI1_DSIINP4 0x400f41c8 +#define CYREG_UDB_DSI1_DSIINP5 0x400f41ca +#define CYREG_UDB_DSI1_DSIOUTP0 0x400f41cc +#define CYREG_UDB_DSI1_DSIOUTP1 0x400f41ce +#define CYREG_UDB_DSI1_DSIOUTP2 0x400f41d0 +#define CYREG_UDB_DSI1_DSIOUTP3 0x400f41d2 +#define CYREG_UDB_DSI1_DSIOUTT0 0x400f41d4 +#define CYREG_UDB_DSI1_DSIOUTT1 0x400f41d6 +#define CYREG_UDB_DSI1_DSIOUTT2 0x400f41d8 +#define CYREG_UDB_DSI1_DSIOUTT3 0x400f41da +#define CYREG_UDB_DSI1_DSIOUTT4 0x400f41dc +#define CYREG_UDB_DSI1_DSIOUTT5 0x400f41de +#define CYREG_UDB_DSI1_VS0 0x400f41e0 +#define CYREG_UDB_DSI1_VS1 0x400f41e2 +#define CYREG_UDB_DSI1_VS2 0x400f41e4 +#define CYREG_UDB_DSI1_VS3 0x400f41e6 +#define CYREG_UDB_DSI1_VS4 0x400f41e8 +#define CYREG_UDB_DSI1_VS5 0x400f41ea +#define CYREG_UDB_DSI1_VS6 0x400f41ec +#define CYREG_UDB_DSI1_VS7 0x400f41ee +#define CYDEV_UDB_DSI2_BASE 0x400f4200 +#define CYDEV_UDB_DSI2_SIZE 0x00000100 +#define CYREG_UDB_DSI2_HC0 0x400f4200 +#define CYREG_UDB_DSI2_HC1 0x400f4201 +#define CYREG_UDB_DSI2_HC2 0x400f4202 +#define CYREG_UDB_DSI2_HC3 0x400f4203 +#define CYREG_UDB_DSI2_HC4 0x400f4204 +#define CYREG_UDB_DSI2_HC5 0x400f4205 +#define CYREG_UDB_DSI2_HC6 0x400f4206 +#define CYREG_UDB_DSI2_HC7 0x400f4207 +#define CYREG_UDB_DSI2_HC8 0x400f4208 +#define CYREG_UDB_DSI2_HC9 0x400f4209 +#define CYREG_UDB_DSI2_HC10 0x400f420a +#define CYREG_UDB_DSI2_HC11 0x400f420b +#define CYREG_UDB_DSI2_HC12 0x400f420c +#define CYREG_UDB_DSI2_HC13 0x400f420d +#define CYREG_UDB_DSI2_HC14 0x400f420e +#define CYREG_UDB_DSI2_HC15 0x400f420f +#define CYREG_UDB_DSI2_HC16 0x400f4210 +#define CYREG_UDB_DSI2_HC17 0x400f4211 +#define CYREG_UDB_DSI2_HC18 0x400f4212 +#define CYREG_UDB_DSI2_HC19 0x400f4213 +#define CYREG_UDB_DSI2_HC20 0x400f4214 +#define CYREG_UDB_DSI2_HC21 0x400f4215 +#define CYREG_UDB_DSI2_HC22 0x400f4216 +#define CYREG_UDB_DSI2_HC23 0x400f4217 +#define CYREG_UDB_DSI2_HC24 0x400f4218 +#define CYREG_UDB_DSI2_HC25 0x400f4219 +#define CYREG_UDB_DSI2_HC26 0x400f421a +#define CYREG_UDB_DSI2_HC27 0x400f421b +#define CYREG_UDB_DSI2_HC28 0x400f421c +#define CYREG_UDB_DSI2_HC29 0x400f421d +#define CYREG_UDB_DSI2_HC30 0x400f421e +#define CYREG_UDB_DSI2_HC31 0x400f421f +#define CYREG_UDB_DSI2_HC32 0x400f4220 +#define CYREG_UDB_DSI2_HC33 0x400f4221 +#define CYREG_UDB_DSI2_HC34 0x400f4222 +#define CYREG_UDB_DSI2_HC35 0x400f4223 +#define CYREG_UDB_DSI2_HC36 0x400f4224 +#define CYREG_UDB_DSI2_HC37 0x400f4225 +#define CYREG_UDB_DSI2_HC38 0x400f4226 +#define CYREG_UDB_DSI2_HC39 0x400f4227 +#define CYREG_UDB_DSI2_HC40 0x400f4228 +#define CYREG_UDB_DSI2_HC41 0x400f4229 +#define CYREG_UDB_DSI2_HC42 0x400f422a +#define CYREG_UDB_DSI2_HC43 0x400f422b +#define CYREG_UDB_DSI2_HC44 0x400f422c +#define CYREG_UDB_DSI2_HC45 0x400f422d +#define CYREG_UDB_DSI2_HC46 0x400f422e +#define CYREG_UDB_DSI2_HC47 0x400f422f +#define CYREG_UDB_DSI2_HC48 0x400f4230 +#define CYREG_UDB_DSI2_HC49 0x400f4231 +#define CYREG_UDB_DSI2_HC50 0x400f4232 +#define CYREG_UDB_DSI2_HC51 0x400f4233 +#define CYREG_UDB_DSI2_HC52 0x400f4234 +#define CYREG_UDB_DSI2_HC53 0x400f4235 +#define CYREG_UDB_DSI2_HC54 0x400f4236 +#define CYREG_UDB_DSI2_HC55 0x400f4237 +#define CYREG_UDB_DSI2_HC56 0x400f4238 +#define CYREG_UDB_DSI2_HC57 0x400f4239 +#define CYREG_UDB_DSI2_HC58 0x400f423a +#define CYREG_UDB_DSI2_HC59 0x400f423b +#define CYREG_UDB_DSI2_HC60 0x400f423c +#define CYREG_UDB_DSI2_HC61 0x400f423d +#define CYREG_UDB_DSI2_HC62 0x400f423e +#define CYREG_UDB_DSI2_HC63 0x400f423f +#define CYREG_UDB_DSI2_HC64 0x400f4240 +#define CYREG_UDB_DSI2_HC65 0x400f4241 +#define CYREG_UDB_DSI2_HC66 0x400f4242 +#define CYREG_UDB_DSI2_HC67 0x400f4243 +#define CYREG_UDB_DSI2_HC68 0x400f4244 +#define CYREG_UDB_DSI2_HC69 0x400f4245 +#define CYREG_UDB_DSI2_HC70 0x400f4246 +#define CYREG_UDB_DSI2_HC71 0x400f4247 +#define CYREG_UDB_DSI2_HC72 0x400f4248 +#define CYREG_UDB_DSI2_HC73 0x400f4249 +#define CYREG_UDB_DSI2_HC74 0x400f424a +#define CYREG_UDB_DSI2_HC75 0x400f424b +#define CYREG_UDB_DSI2_HC76 0x400f424c +#define CYREG_UDB_DSI2_HC77 0x400f424d +#define CYREG_UDB_DSI2_HC78 0x400f424e +#define CYREG_UDB_DSI2_HC79 0x400f424f +#define CYREG_UDB_DSI2_HC80 0x400f4250 +#define CYREG_UDB_DSI2_HC81 0x400f4251 +#define CYREG_UDB_DSI2_HC82 0x400f4252 +#define CYREG_UDB_DSI2_HC83 0x400f4253 +#define CYREG_UDB_DSI2_HC84 0x400f4254 +#define CYREG_UDB_DSI2_HC85 0x400f4255 +#define CYREG_UDB_DSI2_HC86 0x400f4256 +#define CYREG_UDB_DSI2_HC87 0x400f4257 +#define CYREG_UDB_DSI2_HC88 0x400f4258 +#define CYREG_UDB_DSI2_HC89 0x400f4259 +#define CYREG_UDB_DSI2_HC90 0x400f425a +#define CYREG_UDB_DSI2_HC91 0x400f425b +#define CYREG_UDB_DSI2_HC92 0x400f425c +#define CYREG_UDB_DSI2_HC93 0x400f425d +#define CYREG_UDB_DSI2_HC94 0x400f425e +#define CYREG_UDB_DSI2_HC95 0x400f425f +#define CYREG_UDB_DSI2_HC96 0x400f4260 +#define CYREG_UDB_DSI2_HC97 0x400f4261 +#define CYREG_UDB_DSI2_HC98 0x400f4262 +#define CYREG_UDB_DSI2_HC99 0x400f4263 +#define CYREG_UDB_DSI2_HC100 0x400f4264 +#define CYREG_UDB_DSI2_HC101 0x400f4265 +#define CYREG_UDB_DSI2_HC102 0x400f4266 +#define CYREG_UDB_DSI2_HC103 0x400f4267 +#define CYREG_UDB_DSI2_HC104 0x400f4268 +#define CYREG_UDB_DSI2_HC105 0x400f4269 +#define CYREG_UDB_DSI2_HC106 0x400f426a +#define CYREG_UDB_DSI2_HC107 0x400f426b +#define CYREG_UDB_DSI2_HC108 0x400f426c +#define CYREG_UDB_DSI2_HC109 0x400f426d +#define CYREG_UDB_DSI2_HC110 0x400f426e +#define CYREG_UDB_DSI2_HC111 0x400f426f +#define CYREG_UDB_DSI2_HC112 0x400f4270 +#define CYREG_UDB_DSI2_HC113 0x400f4271 +#define CYREG_UDB_DSI2_HC114 0x400f4272 +#define CYREG_UDB_DSI2_HC115 0x400f4273 +#define CYREG_UDB_DSI2_HC116 0x400f4274 +#define CYREG_UDB_DSI2_HC117 0x400f4275 +#define CYREG_UDB_DSI2_HC118 0x400f4276 +#define CYREG_UDB_DSI2_HC119 0x400f4277 +#define CYREG_UDB_DSI2_HC120 0x400f4278 +#define CYREG_UDB_DSI2_HC121 0x400f4279 +#define CYREG_UDB_DSI2_HC122 0x400f427a +#define CYREG_UDB_DSI2_HC123 0x400f427b +#define CYREG_UDB_DSI2_HC124 0x400f427c +#define CYREG_UDB_DSI2_HC125 0x400f427d +#define CYREG_UDB_DSI2_HC126 0x400f427e +#define CYREG_UDB_DSI2_HC127 0x400f427f +#define CYREG_UDB_DSI2_HV_L0 0x400f4280 +#define CYREG_UDB_DSI2_HV_L1 0x400f4281 +#define CYREG_UDB_DSI2_HV_L2 0x400f4282 +#define CYREG_UDB_DSI2_HV_L3 0x400f4283 +#define CYREG_UDB_DSI2_HV_L4 0x400f4284 +#define CYREG_UDB_DSI2_HV_L5 0x400f4285 +#define CYREG_UDB_DSI2_HV_L6 0x400f4286 +#define CYREG_UDB_DSI2_HV_L7 0x400f4287 +#define CYREG_UDB_DSI2_HV_L8 0x400f4288 +#define CYREG_UDB_DSI2_HV_L9 0x400f4289 +#define CYREG_UDB_DSI2_HV_L10 0x400f428a +#define CYREG_UDB_DSI2_HV_L11 0x400f428b +#define CYREG_UDB_DSI2_HV_L12 0x400f428c +#define CYREG_UDB_DSI2_HV_L13 0x400f428d +#define CYREG_UDB_DSI2_HV_L14 0x400f428e +#define CYREG_UDB_DSI2_HV_L15 0x400f428f +#define CYREG_UDB_DSI2_HS0 0x400f4290 +#define CYREG_UDB_DSI2_HS1 0x400f4291 +#define CYREG_UDB_DSI2_HS2 0x400f4292 +#define CYREG_UDB_DSI2_HS3 0x400f4293 +#define CYREG_UDB_DSI2_HS4 0x400f4294 +#define CYREG_UDB_DSI2_HS5 0x400f4295 +#define CYREG_UDB_DSI2_HS6 0x400f4296 +#define CYREG_UDB_DSI2_HS7 0x400f4297 +#define CYREG_UDB_DSI2_HS8 0x400f4298 +#define CYREG_UDB_DSI2_HS9 0x400f4299 +#define CYREG_UDB_DSI2_HS10 0x400f429a +#define CYREG_UDB_DSI2_HS11 0x400f429b +#define CYREG_UDB_DSI2_HS12 0x400f429c +#define CYREG_UDB_DSI2_HS13 0x400f429d +#define CYREG_UDB_DSI2_HS14 0x400f429e +#define CYREG_UDB_DSI2_HS15 0x400f429f +#define CYREG_UDB_DSI2_HS16 0x400f42a0 +#define CYREG_UDB_DSI2_HS17 0x400f42a1 +#define CYREG_UDB_DSI2_HS18 0x400f42a2 +#define CYREG_UDB_DSI2_HS19 0x400f42a3 +#define CYREG_UDB_DSI2_HS20 0x400f42a4 +#define CYREG_UDB_DSI2_HS21 0x400f42a5 +#define CYREG_UDB_DSI2_HS22 0x400f42a6 +#define CYREG_UDB_DSI2_HS23 0x400f42a7 +#define CYREG_UDB_DSI2_HV_R0 0x400f42a8 +#define CYREG_UDB_DSI2_HV_R1 0x400f42a9 +#define CYREG_UDB_DSI2_HV_R2 0x400f42aa +#define CYREG_UDB_DSI2_HV_R3 0x400f42ab +#define CYREG_UDB_DSI2_HV_R4 0x400f42ac +#define CYREG_UDB_DSI2_HV_R5 0x400f42ad +#define CYREG_UDB_DSI2_HV_R6 0x400f42ae +#define CYREG_UDB_DSI2_HV_R7 0x400f42af +#define CYREG_UDB_DSI2_HV_R8 0x400f42b0 +#define CYREG_UDB_DSI2_HV_R9 0x400f42b1 +#define CYREG_UDB_DSI2_HV_R10 0x400f42b2 +#define CYREG_UDB_DSI2_HV_R11 0x400f42b3 +#define CYREG_UDB_DSI2_HV_R12 0x400f42b4 +#define CYREG_UDB_DSI2_HV_R13 0x400f42b5 +#define CYREG_UDB_DSI2_HV_R14 0x400f42b6 +#define CYREG_UDB_DSI2_HV_R15 0x400f42b7 +#define CYREG_UDB_DSI2_DSIINP0 0x400f42c0 +#define CYREG_UDB_DSI2_DSIINP1 0x400f42c2 +#define CYREG_UDB_DSI2_DSIINP2 0x400f42c4 +#define CYREG_UDB_DSI2_DSIINP3 0x400f42c6 +#define CYREG_UDB_DSI2_DSIINP4 0x400f42c8 +#define CYREG_UDB_DSI2_DSIINP5 0x400f42ca +#define CYREG_UDB_DSI2_DSIOUTP0 0x400f42cc +#define CYREG_UDB_DSI2_DSIOUTP1 0x400f42ce +#define CYREG_UDB_DSI2_DSIOUTP2 0x400f42d0 +#define CYREG_UDB_DSI2_DSIOUTP3 0x400f42d2 +#define CYREG_UDB_DSI2_DSIOUTT0 0x400f42d4 +#define CYREG_UDB_DSI2_DSIOUTT1 0x400f42d6 +#define CYREG_UDB_DSI2_DSIOUTT2 0x400f42d8 +#define CYREG_UDB_DSI2_DSIOUTT3 0x400f42da +#define CYREG_UDB_DSI2_DSIOUTT4 0x400f42dc +#define CYREG_UDB_DSI2_DSIOUTT5 0x400f42de +#define CYREG_UDB_DSI2_VS0 0x400f42e0 +#define CYREG_UDB_DSI2_VS1 0x400f42e2 +#define CYREG_UDB_DSI2_VS2 0x400f42e4 +#define CYREG_UDB_DSI2_VS3 0x400f42e6 +#define CYREG_UDB_DSI2_VS4 0x400f42e8 +#define CYREG_UDB_DSI2_VS5 0x400f42ea +#define CYREG_UDB_DSI2_VS6 0x400f42ec +#define CYREG_UDB_DSI2_VS7 0x400f42ee +#define CYDEV_UDB_DSI3_BASE 0x400f4300 +#define CYDEV_UDB_DSI3_SIZE 0x00000100 +#define CYREG_UDB_DSI3_HC0 0x400f4300 +#define CYREG_UDB_DSI3_HC1 0x400f4301 +#define CYREG_UDB_DSI3_HC2 0x400f4302 +#define CYREG_UDB_DSI3_HC3 0x400f4303 +#define CYREG_UDB_DSI3_HC4 0x400f4304 +#define CYREG_UDB_DSI3_HC5 0x400f4305 +#define CYREG_UDB_DSI3_HC6 0x400f4306 +#define CYREG_UDB_DSI3_HC7 0x400f4307 +#define CYREG_UDB_DSI3_HC8 0x400f4308 +#define CYREG_UDB_DSI3_HC9 0x400f4309 +#define CYREG_UDB_DSI3_HC10 0x400f430a +#define CYREG_UDB_DSI3_HC11 0x400f430b +#define CYREG_UDB_DSI3_HC12 0x400f430c +#define CYREG_UDB_DSI3_HC13 0x400f430d +#define CYREG_UDB_DSI3_HC14 0x400f430e +#define CYREG_UDB_DSI3_HC15 0x400f430f +#define CYREG_UDB_DSI3_HC16 0x400f4310 +#define CYREG_UDB_DSI3_HC17 0x400f4311 +#define CYREG_UDB_DSI3_HC18 0x400f4312 +#define CYREG_UDB_DSI3_HC19 0x400f4313 +#define CYREG_UDB_DSI3_HC20 0x400f4314 +#define CYREG_UDB_DSI3_HC21 0x400f4315 +#define CYREG_UDB_DSI3_HC22 0x400f4316 +#define CYREG_UDB_DSI3_HC23 0x400f4317 +#define CYREG_UDB_DSI3_HC24 0x400f4318 +#define CYREG_UDB_DSI3_HC25 0x400f4319 +#define CYREG_UDB_DSI3_HC26 0x400f431a +#define CYREG_UDB_DSI3_HC27 0x400f431b +#define CYREG_UDB_DSI3_HC28 0x400f431c +#define CYREG_UDB_DSI3_HC29 0x400f431d +#define CYREG_UDB_DSI3_HC30 0x400f431e +#define CYREG_UDB_DSI3_HC31 0x400f431f +#define CYREG_UDB_DSI3_HC32 0x400f4320 +#define CYREG_UDB_DSI3_HC33 0x400f4321 +#define CYREG_UDB_DSI3_HC34 0x400f4322 +#define CYREG_UDB_DSI3_HC35 0x400f4323 +#define CYREG_UDB_DSI3_HC36 0x400f4324 +#define CYREG_UDB_DSI3_HC37 0x400f4325 +#define CYREG_UDB_DSI3_HC38 0x400f4326 +#define CYREG_UDB_DSI3_HC39 0x400f4327 +#define CYREG_UDB_DSI3_HC40 0x400f4328 +#define CYREG_UDB_DSI3_HC41 0x400f4329 +#define CYREG_UDB_DSI3_HC42 0x400f432a +#define CYREG_UDB_DSI3_HC43 0x400f432b +#define CYREG_UDB_DSI3_HC44 0x400f432c +#define CYREG_UDB_DSI3_HC45 0x400f432d +#define CYREG_UDB_DSI3_HC46 0x400f432e +#define CYREG_UDB_DSI3_HC47 0x400f432f +#define CYREG_UDB_DSI3_HC48 0x400f4330 +#define CYREG_UDB_DSI3_HC49 0x400f4331 +#define CYREG_UDB_DSI3_HC50 0x400f4332 +#define CYREG_UDB_DSI3_HC51 0x400f4333 +#define CYREG_UDB_DSI3_HC52 0x400f4334 +#define CYREG_UDB_DSI3_HC53 0x400f4335 +#define CYREG_UDB_DSI3_HC54 0x400f4336 +#define CYREG_UDB_DSI3_HC55 0x400f4337 +#define CYREG_UDB_DSI3_HC56 0x400f4338 +#define CYREG_UDB_DSI3_HC57 0x400f4339 +#define CYREG_UDB_DSI3_HC58 0x400f433a +#define CYREG_UDB_DSI3_HC59 0x400f433b +#define CYREG_UDB_DSI3_HC60 0x400f433c +#define CYREG_UDB_DSI3_HC61 0x400f433d +#define CYREG_UDB_DSI3_HC62 0x400f433e +#define CYREG_UDB_DSI3_HC63 0x400f433f +#define CYREG_UDB_DSI3_HC64 0x400f4340 +#define CYREG_UDB_DSI3_HC65 0x400f4341 +#define CYREG_UDB_DSI3_HC66 0x400f4342 +#define CYREG_UDB_DSI3_HC67 0x400f4343 +#define CYREG_UDB_DSI3_HC68 0x400f4344 +#define CYREG_UDB_DSI3_HC69 0x400f4345 +#define CYREG_UDB_DSI3_HC70 0x400f4346 +#define CYREG_UDB_DSI3_HC71 0x400f4347 +#define CYREG_UDB_DSI3_HC72 0x400f4348 +#define CYREG_UDB_DSI3_HC73 0x400f4349 +#define CYREG_UDB_DSI3_HC74 0x400f434a +#define CYREG_UDB_DSI3_HC75 0x400f434b +#define CYREG_UDB_DSI3_HC76 0x400f434c +#define CYREG_UDB_DSI3_HC77 0x400f434d +#define CYREG_UDB_DSI3_HC78 0x400f434e +#define CYREG_UDB_DSI3_HC79 0x400f434f +#define CYREG_UDB_DSI3_HC80 0x400f4350 +#define CYREG_UDB_DSI3_HC81 0x400f4351 +#define CYREG_UDB_DSI3_HC82 0x400f4352 +#define CYREG_UDB_DSI3_HC83 0x400f4353 +#define CYREG_UDB_DSI3_HC84 0x400f4354 +#define CYREG_UDB_DSI3_HC85 0x400f4355 +#define CYREG_UDB_DSI3_HC86 0x400f4356 +#define CYREG_UDB_DSI3_HC87 0x400f4357 +#define CYREG_UDB_DSI3_HC88 0x400f4358 +#define CYREG_UDB_DSI3_HC89 0x400f4359 +#define CYREG_UDB_DSI3_HC90 0x400f435a +#define CYREG_UDB_DSI3_HC91 0x400f435b +#define CYREG_UDB_DSI3_HC92 0x400f435c +#define CYREG_UDB_DSI3_HC93 0x400f435d +#define CYREG_UDB_DSI3_HC94 0x400f435e +#define CYREG_UDB_DSI3_HC95 0x400f435f +#define CYREG_UDB_DSI3_HC96 0x400f4360 +#define CYREG_UDB_DSI3_HC97 0x400f4361 +#define CYREG_UDB_DSI3_HC98 0x400f4362 +#define CYREG_UDB_DSI3_HC99 0x400f4363 +#define CYREG_UDB_DSI3_HC100 0x400f4364 +#define CYREG_UDB_DSI3_HC101 0x400f4365 +#define CYREG_UDB_DSI3_HC102 0x400f4366 +#define CYREG_UDB_DSI3_HC103 0x400f4367 +#define CYREG_UDB_DSI3_HC104 0x400f4368 +#define CYREG_UDB_DSI3_HC105 0x400f4369 +#define CYREG_UDB_DSI3_HC106 0x400f436a +#define CYREG_UDB_DSI3_HC107 0x400f436b +#define CYREG_UDB_DSI3_HC108 0x400f436c +#define CYREG_UDB_DSI3_HC109 0x400f436d +#define CYREG_UDB_DSI3_HC110 0x400f436e +#define CYREG_UDB_DSI3_HC111 0x400f436f +#define CYREG_UDB_DSI3_HC112 0x400f4370 +#define CYREG_UDB_DSI3_HC113 0x400f4371 +#define CYREG_UDB_DSI3_HC114 0x400f4372 +#define CYREG_UDB_DSI3_HC115 0x400f4373 +#define CYREG_UDB_DSI3_HC116 0x400f4374 +#define CYREG_UDB_DSI3_HC117 0x400f4375 +#define CYREG_UDB_DSI3_HC118 0x400f4376 +#define CYREG_UDB_DSI3_HC119 0x400f4377 +#define CYREG_UDB_DSI3_HC120 0x400f4378 +#define CYREG_UDB_DSI3_HC121 0x400f4379 +#define CYREG_UDB_DSI3_HC122 0x400f437a +#define CYREG_UDB_DSI3_HC123 0x400f437b +#define CYREG_UDB_DSI3_HC124 0x400f437c +#define CYREG_UDB_DSI3_HC125 0x400f437d +#define CYREG_UDB_DSI3_HC126 0x400f437e +#define CYREG_UDB_DSI3_HC127 0x400f437f +#define CYREG_UDB_DSI3_HV_L0 0x400f4380 +#define CYREG_UDB_DSI3_HV_L1 0x400f4381 +#define CYREG_UDB_DSI3_HV_L2 0x400f4382 +#define CYREG_UDB_DSI3_HV_L3 0x400f4383 +#define CYREG_UDB_DSI3_HV_L4 0x400f4384 +#define CYREG_UDB_DSI3_HV_L5 0x400f4385 +#define CYREG_UDB_DSI3_HV_L6 0x400f4386 +#define CYREG_UDB_DSI3_HV_L7 0x400f4387 +#define CYREG_UDB_DSI3_HV_L8 0x400f4388 +#define CYREG_UDB_DSI3_HV_L9 0x400f4389 +#define CYREG_UDB_DSI3_HV_L10 0x400f438a +#define CYREG_UDB_DSI3_HV_L11 0x400f438b +#define CYREG_UDB_DSI3_HV_L12 0x400f438c +#define CYREG_UDB_DSI3_HV_L13 0x400f438d +#define CYREG_UDB_DSI3_HV_L14 0x400f438e +#define CYREG_UDB_DSI3_HV_L15 0x400f438f +#define CYREG_UDB_DSI3_HS0 0x400f4390 +#define CYREG_UDB_DSI3_HS1 0x400f4391 +#define CYREG_UDB_DSI3_HS2 0x400f4392 +#define CYREG_UDB_DSI3_HS3 0x400f4393 +#define CYREG_UDB_DSI3_HS4 0x400f4394 +#define CYREG_UDB_DSI3_HS5 0x400f4395 +#define CYREG_UDB_DSI3_HS6 0x400f4396 +#define CYREG_UDB_DSI3_HS7 0x400f4397 +#define CYREG_UDB_DSI3_HS8 0x400f4398 +#define CYREG_UDB_DSI3_HS9 0x400f4399 +#define CYREG_UDB_DSI3_HS10 0x400f439a +#define CYREG_UDB_DSI3_HS11 0x400f439b +#define CYREG_UDB_DSI3_HS12 0x400f439c +#define CYREG_UDB_DSI3_HS13 0x400f439d +#define CYREG_UDB_DSI3_HS14 0x400f439e +#define CYREG_UDB_DSI3_HS15 0x400f439f +#define CYREG_UDB_DSI3_HS16 0x400f43a0 +#define CYREG_UDB_DSI3_HS17 0x400f43a1 +#define CYREG_UDB_DSI3_HS18 0x400f43a2 +#define CYREG_UDB_DSI3_HS19 0x400f43a3 +#define CYREG_UDB_DSI3_HS20 0x400f43a4 +#define CYREG_UDB_DSI3_HS21 0x400f43a5 +#define CYREG_UDB_DSI3_HS22 0x400f43a6 +#define CYREG_UDB_DSI3_HS23 0x400f43a7 +#define CYREG_UDB_DSI3_HV_R0 0x400f43a8 +#define CYREG_UDB_DSI3_HV_R1 0x400f43a9 +#define CYREG_UDB_DSI3_HV_R2 0x400f43aa +#define CYREG_UDB_DSI3_HV_R3 0x400f43ab +#define CYREG_UDB_DSI3_HV_R4 0x400f43ac +#define CYREG_UDB_DSI3_HV_R5 0x400f43ad +#define CYREG_UDB_DSI3_HV_R6 0x400f43ae +#define CYREG_UDB_DSI3_HV_R7 0x400f43af +#define CYREG_UDB_DSI3_HV_R8 0x400f43b0 +#define CYREG_UDB_DSI3_HV_R9 0x400f43b1 +#define CYREG_UDB_DSI3_HV_R10 0x400f43b2 +#define CYREG_UDB_DSI3_HV_R11 0x400f43b3 +#define CYREG_UDB_DSI3_HV_R12 0x400f43b4 +#define CYREG_UDB_DSI3_HV_R13 0x400f43b5 +#define CYREG_UDB_DSI3_HV_R14 0x400f43b6 +#define CYREG_UDB_DSI3_HV_R15 0x400f43b7 +#define CYREG_UDB_DSI3_DSIINP0 0x400f43c0 +#define CYREG_UDB_DSI3_DSIINP1 0x400f43c2 +#define CYREG_UDB_DSI3_DSIINP2 0x400f43c4 +#define CYREG_UDB_DSI3_DSIINP3 0x400f43c6 +#define CYREG_UDB_DSI3_DSIINP4 0x400f43c8 +#define CYREG_UDB_DSI3_DSIINP5 0x400f43ca +#define CYREG_UDB_DSI3_DSIOUTP0 0x400f43cc +#define CYREG_UDB_DSI3_DSIOUTP1 0x400f43ce +#define CYREG_UDB_DSI3_DSIOUTP2 0x400f43d0 +#define CYREG_UDB_DSI3_DSIOUTP3 0x400f43d2 +#define CYREG_UDB_DSI3_DSIOUTT0 0x400f43d4 +#define CYREG_UDB_DSI3_DSIOUTT1 0x400f43d6 +#define CYREG_UDB_DSI3_DSIOUTT2 0x400f43d8 +#define CYREG_UDB_DSI3_DSIOUTT3 0x400f43da +#define CYREG_UDB_DSI3_DSIOUTT4 0x400f43dc +#define CYREG_UDB_DSI3_DSIOUTT5 0x400f43de +#define CYREG_UDB_DSI3_VS0 0x400f43e0 +#define CYREG_UDB_DSI3_VS1 0x400f43e2 +#define CYREG_UDB_DSI3_VS2 0x400f43e4 +#define CYREG_UDB_DSI3_VS3 0x400f43e6 +#define CYREG_UDB_DSI3_VS4 0x400f43e8 +#define CYREG_UDB_DSI3_VS5 0x400f43ea +#define CYREG_UDB_DSI3_VS6 0x400f43ec +#define CYREG_UDB_DSI3_VS7 0x400f43ee +#define CYDEV_UDB_PA0_BASE 0x400f5000 +#define CYDEV_UDB_PA0_SIZE 0x00000010 +#define CYREG_UDB_PA0_CFG0 0x400f5000 +#define CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET 0x00000002 +#define CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_OFF 0x00000000 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_ON 0x00000001 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL 0x00000003 +#define CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET 0x00000004 +#define CYFLD_UDB_PA_CLKIN_EN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKIN_EN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKIN_EN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_CLKIN_INV__OFFSET 0x00000005 +#define CYFLD_UDB_PA_CLKIN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKIN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKIN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_NC__OFFSET 0x00000006 +#define CYFLD_UDB_PA_NC__SIZE 0x00000002 +#define CYREG_UDB_PA0_CFG1 0x400f5001 +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET 0x00000002 +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_ON 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL 0x00000003 +#define CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET 0x00000004 +#define CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_EN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_CLKOUT_INV__OFFSET 0x00000005 +#define CYFLD_UDB_PA_CLKOUT_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_INV_INV 0x00000001 +#define CYREG_UDB_PA0_CFG2 0x400f5002 +#define CYFLD_UDB_PA_CLKIN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_CLKIN_SEL__SIZE 0x00000004 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP 0x00000009 +#define CYVAL_UDB_PA_CLKIN_SEL_PIN_RC 0x0000000c +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 0x0000000d +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 0x0000000e +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 0x0000000f +#define CYFLD_UDB_PA_CLKOUT_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_PA_CLKOUT_SEL__SIZE 0x00000004 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP 0x00000009 +#define CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC 0x0000000c +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 0x0000000d +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 0x0000000e +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 0x0000000f +#define CYREG_UDB_PA0_CFG3 0x400f5003 +#define CYFLD_UDB_PA_RES_IN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_RES_IN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_RES_IN_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_RES_IN_INV__OFFSET 0x00000002 +#define CYFLD_UDB_PA_RES_IN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_IN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_RES_IN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_NC0__OFFSET 0x00000003 +#define CYFLD_UDB_PA_NC0__SIZE 0x00000001 +#define CYFLD_UDB_PA_RES_OUT_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_PA_RES_OUT_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_RES_OUT_INV__OFFSET 0x00000006 +#define CYFLD_UDB_PA_RES_OUT_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_OUT_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_RES_OUT_INV_INV 0x00000001 +#define CYFLD_UDB_PA_NC7__OFFSET 0x00000007 +#define CYFLD_UDB_PA_NC7__SIZE 0x00000001 +#define CYREG_UDB_PA0_CFG4 0x400f5004 +#define CYFLD_UDB_PA_RES_IN_EN__OFFSET 0x00000000 +#define CYFLD_UDB_PA_RES_IN_EN__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_IN_EN_DISABLE 0x00000000 +#define CYVAL_UDB_PA_RES_IN_EN_ENABLE 0x00000001 +#define CYFLD_UDB_PA_RES_OUT_EN__OFFSET 0x00000001 +#define CYFLD_UDB_PA_RES_OUT_EN__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_OUT_EN_DISABLE 0x00000000 +#define CYVAL_UDB_PA_RES_OUT_EN_ENABLE 0x00000001 +#define CYFLD_UDB_PA_RES_OE_EN__OFFSET 0x00000002 +#define CYFLD_UDB_PA_RES_OE_EN__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_OE_EN_DISABLE 0x00000000 +#define CYVAL_UDB_PA_RES_OE_EN_ENABLE 0x00000001 +#define CYFLD_UDB_PA_NC7654__OFFSET 0x00000003 +#define CYFLD_UDB_PA_NC7654__SIZE 0x00000005 +#define CYREG_UDB_PA0_CFG5 0x400f5005 +#define CYFLD_UDB_PA_PIN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_PIN_SEL__SIZE 0x00000001 +#define CYVAL_UDB_PA_PIN_SEL_PIN0 0x00000000 +#define CYVAL_UDB_PA_PIN_SEL_PIN1 0x00000001 +#define CYVAL_UDB_PA_PIN_SEL_PIN2 0x00000002 +#define CYVAL_UDB_PA_PIN_SEL_PIN3 0x00000003 +#define CYVAL_UDB_PA_PIN_SEL_PIN4 0x00000004 +#define CYVAL_UDB_PA_PIN_SEL_PIN5 0x00000005 +#define CYVAL_UDB_PA_PIN_SEL_PIN6 0x00000006 +#define CYVAL_UDB_PA_PIN_SEL_PIN7 0x00000007 +#define CYREG_UDB_PA0_CFG6 0x400f5006 +#define CYFLD_UDB_PA_IN_SYNC0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_IN_SYNC0__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC0_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_IN_SYNC1__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC1_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_IN_SYNC2__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC2_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_IN_SYNC3__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC3_RSVD 0x00000003 +#define CYREG_UDB_PA0_CFG7 0x400f5007 +#define CYFLD_UDB_PA_IN_SYNC4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_IN_SYNC4__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC4_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_IN_SYNC5__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC5_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_IN_SYNC6__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC6_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_IN_SYNC7__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC7_RSVD 0x00000003 +#define CYREG_UDB_PA0_CFG8 0x400f5008 +#define CYFLD_UDB_PA_OUT_SYNC0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OUT_SYNC0__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OUT_SYNC1__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OUT_SYNC2__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OUT_SYNC3__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV 0x00000003 +#define CYREG_UDB_PA0_CFG9 0x400f5009 +#define CYFLD_UDB_PA_OUT_SYNC4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OUT_SYNC4__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OUT_SYNC5__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OUT_SYNC6__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OUT_SYNC7__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV 0x00000003 +#define CYREG_UDB_PA0_CFG10 0x400f500a +#define CYFLD_UDB_PA_DATA_SEL0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_DATA_SEL0__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_DATA_SEL1__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_DATA_SEL2__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_DATA_SEL3__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 0x00000003 +#define CYREG_UDB_PA0_CFG11 0x400f500b +#define CYFLD_UDB_PA_DATA_SEL4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_DATA_SEL4__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_DATA_SEL5__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_DATA_SEL6__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_DATA_SEL7__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 0x00000003 +#define CYREG_UDB_PA0_CFG12 0x400f500c +#define CYFLD_UDB_PA_OE_SEL0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OE_SEL0__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OE_SEL1__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OE_SEL2__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OE_SEL3__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 0x00000003 +#define CYREG_UDB_PA0_CFG13 0x400f500d +#define CYFLD_UDB_PA_OE_SEL4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OE_SEL4__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OE_SEL5__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OE_SEL6__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OE_SEL7__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 0x00000003 +#define CYREG_UDB_PA0_CFG14 0x400f500e +#define CYFLD_UDB_PA_OE_SYNC0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OE_SYNC0__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 0x00000003 +#define CYFLD_UDB_PA_OE_SYNC1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OE_SYNC1__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 0x00000003 +#define CYFLD_UDB_PA_OE_SYNC2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OE_SYNC2__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 0x00000003 +#define CYFLD_UDB_PA_OE_SYNC3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OE_SYNC3__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 0x00000003 +#define CYDEV_UDB_PA1_BASE 0x400f5010 +#define CYDEV_UDB_PA1_SIZE 0x00000010 +#define CYREG_UDB_PA1_CFG0 0x400f5010 +#define CYREG_UDB_PA1_CFG1 0x400f5011 +#define CYREG_UDB_PA1_CFG2 0x400f5012 +#define CYREG_UDB_PA1_CFG3 0x400f5013 +#define CYREG_UDB_PA1_CFG4 0x400f5014 +#define CYREG_UDB_PA1_CFG5 0x400f5015 +#define CYREG_UDB_PA1_CFG6 0x400f5016 +#define CYREG_UDB_PA1_CFG7 0x400f5017 +#define CYREG_UDB_PA1_CFG8 0x400f5018 +#define CYREG_UDB_PA1_CFG9 0x400f5019 +#define CYREG_UDB_PA1_CFG10 0x400f501a +#define CYREG_UDB_PA1_CFG11 0x400f501b +#define CYREG_UDB_PA1_CFG12 0x400f501c +#define CYREG_UDB_PA1_CFG13 0x400f501d +#define CYREG_UDB_PA1_CFG14 0x400f501e +#define CYDEV_UDB_PA2_BASE 0x400f5020 +#define CYDEV_UDB_PA2_SIZE 0x00000010 +#define CYREG_UDB_PA2_CFG0 0x400f5020 +#define CYREG_UDB_PA2_CFG1 0x400f5021 +#define CYREG_UDB_PA2_CFG2 0x400f5022 +#define CYREG_UDB_PA2_CFG3 0x400f5023 +#define CYREG_UDB_PA2_CFG4 0x400f5024 +#define CYREG_UDB_PA2_CFG5 0x400f5025 +#define CYREG_UDB_PA2_CFG6 0x400f5026 +#define CYREG_UDB_PA2_CFG7 0x400f5027 +#define CYREG_UDB_PA2_CFG8 0x400f5028 +#define CYREG_UDB_PA2_CFG9 0x400f5029 +#define CYREG_UDB_PA2_CFG10 0x400f502a +#define CYREG_UDB_PA2_CFG11 0x400f502b +#define CYREG_UDB_PA2_CFG12 0x400f502c +#define CYREG_UDB_PA2_CFG13 0x400f502d +#define CYREG_UDB_PA2_CFG14 0x400f502e +#define CYDEV_UDB_PA3_BASE 0x400f5030 +#define CYDEV_UDB_PA3_SIZE 0x00000010 +#define CYREG_UDB_PA3_CFG0 0x400f5030 +#define CYREG_UDB_PA3_CFG1 0x400f5031 +#define CYREG_UDB_PA3_CFG2 0x400f5032 +#define CYREG_UDB_PA3_CFG3 0x400f5033 +#define CYREG_UDB_PA3_CFG4 0x400f5034 +#define CYREG_UDB_PA3_CFG5 0x400f5035 +#define CYREG_UDB_PA3_CFG6 0x400f5036 +#define CYREG_UDB_PA3_CFG7 0x400f5037 +#define CYREG_UDB_PA3_CFG8 0x400f5038 +#define CYREG_UDB_PA3_CFG9 0x400f5039 +#define CYREG_UDB_PA3_CFG10 0x400f503a +#define CYREG_UDB_PA3_CFG11 0x400f503b +#define CYREG_UDB_PA3_CFG12 0x400f503c +#define CYREG_UDB_PA3_CFG13 0x400f503d +#define CYREG_UDB_PA3_CFG14 0x400f503e +#define CYDEV_UDB_BCTL0_BASE 0x400f6000 +#define CYDEV_UDB_BCTL0_SIZE 0x00001000 +#define CYREG_UDB_BCTL0_DRV 0x400f6000 +#define CYFLD_UDB_BCTL0_DRV__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_DRV__SIZE 0x00000008 +#define CYVAL_UDB_BCTL0_DRV_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DRV_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_MDCLK_EN 0x400f6001 +#define CYFLD_UDB_BCTL0_DCEN__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_DCEN__SIZE 0x00000008 +#define CYVAL_UDB_BCTL0_DCEN_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DCEN_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_MBCLK_EN 0x400f6002 +#define CYFLD_UDB_BCTL0_BCEN__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_BCEN__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_BCEN_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_BCEN_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_BOTSEL_L 0x400f6008 +#define CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_CLK_SEL0__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET 0x00000002 +#define CYFLD_UDB_BCTL0_CLK_SEL1__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET 0x00000004 +#define CYFLD_UDB_BCTL0_CLK_SEL2__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET 0x00000006 +#define CYFLD_UDB_BCTL0_CLK_SEL3__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT 0x00000003 +#define CYREG_UDB_BCTL0_BOTSEL_U 0x400f6009 +#define CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_CLK_SEL4__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET 0x00000002 +#define CYFLD_UDB_BCTL0_CLK_SEL5__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET 0x00000004 +#define CYFLD_UDB_BCTL0_CLK_SEL6__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET 0x00000006 +#define CYFLD_UDB_BCTL0_CLK_SEL7__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT 0x00000003 +#define CYREG_UDB_BCTL0_TOPSEL_L 0x400f600a +#define CYREG_UDB_BCTL0_TOPSEL_U 0x400f600b +#define CYREG_UDB_BCTL0_QCLK_EN0 0x400f6010 +#define CYFLD_UDB_BCTL0_DCEN_Q__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_DCEN_Q__SIZE 0x00000008 +#define CYVAL_UDB_BCTL0_DCEN_Q_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DCEN_Q_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_BCEN_Q__OFFSET 0x00000008 +#define CYFLD_UDB_BCTL0_BCEN_Q__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_BCEN_Q_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_BCEN_Q_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET 0x00000009 +#define CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET 0x0000000a +#define CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET 0x0000000b +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET 0x0000000c +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET 0x0000000d +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB 0x00000000 +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB 0x00000001 +#define CYFLD_UDB_BCTL0_NC0__OFFSET 0x0000000e +#define CYFLD_UDB_BCTL0_NC0__SIZE 0x00000001 +#define CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET 0x0000000f +#define CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_QCLK_EN1 0x400f6012 +#define CYDEV_UDB_UDBIF_BASE 0x400f7000 +#define CYDEV_UDB_UDBIF_SIZE 0x00001000 +#define CYREG_UDB_UDBIF_BANK_CTL 0x400f7000 +#define CYFLD_UDB_UDBIF_DIS_COR__OFFSET 0x00000000 +#define CYFLD_UDB_UDBIF_DIS_COR__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_DIS_COR_NORMAL 0x00000000 +#define CYVAL_UDB_UDBIF_DIS_COR_DISABLE 0x00000001 +#define CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET 0x00000001 +#define CYFLD_UDB_UDBIF_ROUTE_EN__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE 0x00000000 +#define CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE 0x00000001 +#define CYFLD_UDB_UDBIF_BANK_EN__OFFSET 0x00000002 +#define CYFLD_UDB_UDBIF_BANK_EN__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_BANK_EN_DISABLE 0x00000000 +#define CYVAL_UDB_UDBIF_BANK_EN_ENABLE 0x00000001 +#define CYFLD_UDB_UDBIF_LOCK__OFFSET 0x00000003 +#define CYFLD_UDB_UDBIF_LOCK__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_LOCK_MUTABLE 0x00000000 +#define CYVAL_UDB_UDBIF_LOCK_LOCKED 0x00000001 +#define CYFLD_UDB_UDBIF_PIPE__OFFSET 0x00000004 +#define CYFLD_UDB_UDBIF_PIPE__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_PIPE_BYPASS 0x00000000 +#define CYVAL_UDB_UDBIF_PIPE_PIPELINED 0x00000001 +#define CYFLD_UDB_UDBIF_GLBL_WR__OFFSET 0x00000007 +#define CYFLD_UDB_UDBIF_GLBL_WR__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_GLBL_WR_DISABLE 0x00000000 +#define CYVAL_UDB_UDBIF_GLBL_WR_ENABLE 0x00000001 +#define CYREG_UDB_UDBIF_WAIT_CFG 0x400f7001 +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET 0x00000000 +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS 0x00000000 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT 0x00000003 +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET 0x00000002 +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT 0x00000000 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS 0x00000003 +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET 0x00000004 +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT 0x00000000 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS 0x00000003 +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET 0x00000006 +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT 0x00000000 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS 0x00000003 +#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x400f701c +#define CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET 0x00000000 +#define CYFLD_UDB_UDBIF_EN_HFCLK__SIZE 0x00000001 +#define CYREG_UDB_INT_CFG 0x400f8000 +#define CYFLD_UDB_INT_MODE_CFG__OFFSET 0x00000000 +#define CYFLD_UDB_INT_MODE_CFG__SIZE 0x00000020 +#define CYVAL_UDB_INT_MODE_CFG_LEVEL 0x00000000 +#define CYVAL_UDB_INT_MODE_CFG_PULSE 0x00000001 +#define CYDEV_CTBM_BASE 0x40100000 +#define CYDEV_CTBM_SIZE 0x00010000 +#define CYREG_CTBM_CTB_CTRL 0x40100000 +#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001f +#define CYFLD_CTBM_ENABLED__SIZE 0x00000001 +#define CYREG_CTBM_OA_RES0_CTRL 0x40100004 +#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002 +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002 +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004 +#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005 +#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006 +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008 +#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002 +#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000 +#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001 +#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002 +#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003 +#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000b +#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001 +#define CYREG_CTBM_OA_RES1_CTRL 0x40100008 +#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002 +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002 +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004 +#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005 +#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006 +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008 +#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002 +#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000 +#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001 +#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002 +#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003 +#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000b +#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001 +#define CYREG_CTBM_COMP_STAT 0x4010000c +#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010 +#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001 +#define CYREG_CTBM_INTR 0x40100020 +#define CYFLD_CTBM_COMP0__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1__SIZE 0x00000001 +#define CYREG_CTBM_INTR_SET 0x40100024 +#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001 +#define CYREG_CTBM_INTR_MASK 0x40100028 +#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001 +#define CYREG_CTBM_INTR_MASKED 0x4010002c +#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001 +#define CYREG_CTBM_DFT_CTRL 0x40100030 +#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003 +#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001f +#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001 +#define CYREG_CTBM_OA0_SW 0x40100080 +#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001 +#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002 +#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001 +#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003 +#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001 +#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008 +#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001 +#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000e +#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001 +#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012 +#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001 +#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015 +#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001 +#define CYREG_CTBM_OA0_SW_CLEAR 0x40100084 +#define CYREG_CTBM_OA1_SW 0x40100088 +#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001 +#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001 +#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001 +#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004 +#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001 +#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008 +#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001 +#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000e +#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012 +#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013 +#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015 +#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001 +#define CYREG_CTBM_OA1_SW_CLEAR 0x4010008c +#define CYREG_CTBM_CTB_SW_HW_CTRL 0x401000c0 +#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002 +#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001 +#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003 +#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001 +#define CYREG_CTBM_CTB_SW_STATUS 0x401000c4 +#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001c +#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001d +#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001e +#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001 +#define CYREG_CTBM_OA0_OFFSET_TRIM 0x40100f00 +#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM 0x40100f04 +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA0_COMP_TRIM 0x40100f08 +#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002 +#define CYREG_CTBM_OA1_OFFSET_TRIM 0x40100f0c +#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM 0x40100f10 +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA1_COMP_TRIM 0x40100f14 +#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002 +#define CYDEV_SAR_BASE 0x401a0000 +#define CYDEV_SAR_SIZE 0x00010000 +#define CYREG_SAR_CTRL 0x401a0000 +#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004 +#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003 +#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000 +#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001 +#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002 +#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003 +#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004 +#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005 +#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006 +#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007 +#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007 +#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001 +#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009 +#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003 +#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000 +#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001 +#define CYVAL_SAR_NEG_SEL_P1 0x00000002 +#define CYVAL_SAR_NEG_SEL_P3 0x00000003 +#define CYVAL_SAR_NEG_SEL_P5 0x00000004 +#define CYVAL_SAR_NEG_SEL_P7 0x00000005 +#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006 +#define CYVAL_SAR_NEG_SEL_VREF 0x00000007 +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000d +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001 +#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000e +#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002 +#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000 +#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001 +#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002 +#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003 +#define CYFLD_SAR_SPARE__OFFSET 0x00000010 +#define CYFLD_SAR_SPARE__SIZE 0x00000004 +#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018 +#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002 +#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000 +#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001 +#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002 +#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003 +#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001c +#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001 +#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001d +#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001 +#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001e +#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001 +#define CYFLD_SAR_ENABLED__OFFSET 0x0000001f +#define CYFLD_SAR_ENABLED__SIZE 0x00000001 +#define CYREG_SAR_SAMPLE_CTRL 0x401a0004 +#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000 +#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000 +#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001 +#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001 +#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001 +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002 +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001 +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000 +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001 +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003 +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001 +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000 +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001 +#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004 +#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003 +#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007 +#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001 +#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010 +#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001 +#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011 +#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001 +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012 +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001 +#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013 +#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001 +#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001f +#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001 +#define CYREG_SAR_SAMPLE_TIME01 0x401a0010 +#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000 +#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000a +#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010 +#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000a +#define CYREG_SAR_SAMPLE_TIME23 0x401a0014 +#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000 +#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000a +#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010 +#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000a +#define CYREG_SAR_RANGE_THRES 0x401a0018 +#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010 +#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010 +#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010 +#define CYREG_SAR_RANGE_COND 0x401a001c +#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001e +#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002 +#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000 +#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001 +#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002 +#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003 +#define CYREG_SAR_CHAN_EN 0x401a0020 +#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010 +#define CYREG_SAR_START_CTRL 0x401a0024 +#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000 +#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001 +#define CYREG_SAR_DFT_CTRL 0x401a0030 +#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000 +#define CYFLD_SAR_DLY_INC__SIZE 0x00000001 +#define CYFLD_SAR_HIZ__OFFSET 0x00000001 +#define CYFLD_SAR_HIZ__SIZE 0x00000001 +#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010 +#define CYFLD_SAR_DFT_INC__SIZE 0x00000004 +#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014 +#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003 +#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018 +#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004 +#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001c +#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001 +#define CYFLD_SAR_DCEN__OFFSET 0x0000001d +#define CYFLD_SAR_DCEN__SIZE 0x00000001 +#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001f +#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001 +#define CYREG_SAR_CHAN_CONFIG00 0x401a0080 +#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000 +#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003 +#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004 +#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003 +#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000 +#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001 +#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002 +#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003 +#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004 +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT 0x00000006 +#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007 +#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008 +#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001 +#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009 +#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_RESOLUTION_12B 0x00000000 +#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001 +#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000a +#define CYFLD_SAR_AVG_EN__SIZE 0x00000001 +#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000c +#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002 +#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001f +#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001 +#define CYREG_SAR_CHAN_CONFIG01 0x401a0084 +#define CYREG_SAR_CHAN_CONFIG02 0x401a0088 +#define CYREG_SAR_CHAN_CONFIG03 0x401a008c +#define CYREG_SAR_CHAN_CONFIG04 0x401a0090 +#define CYREG_SAR_CHAN_CONFIG05 0x401a0094 +#define CYREG_SAR_CHAN_CONFIG06 0x401a0098 +#define CYREG_SAR_CHAN_CONFIG07 0x401a009c +#define CYREG_SAR_CHAN_WORK00 0x401a0100 +#define CYFLD_SAR_WORK__OFFSET 0x00000000 +#define CYFLD_SAR_WORK__SIZE 0x00000010 +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001 +#define CYREG_SAR_CHAN_WORK01 0x401a0104 +#define CYREG_SAR_CHAN_WORK02 0x401a0108 +#define CYREG_SAR_CHAN_WORK03 0x401a010c +#define CYREG_SAR_CHAN_WORK04 0x401a0110 +#define CYREG_SAR_CHAN_WORK05 0x401a0114 +#define CYREG_SAR_CHAN_WORK06 0x401a0118 +#define CYREG_SAR_CHAN_WORK07 0x401a011c +#define CYREG_SAR_CHAN_RESULT00 0x401a0180 +#define CYFLD_SAR_RESULT__OFFSET 0x00000000 +#define CYFLD_SAR_RESULT__SIZE 0x00000010 +#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001d +#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001e +#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001 +#define CYREG_SAR_CHAN_RESULT01 0x401a0184 +#define CYREG_SAR_CHAN_RESULT02 0x401a0188 +#define CYREG_SAR_CHAN_RESULT03 0x401a018c +#define CYREG_SAR_CHAN_RESULT04 0x401a0190 +#define CYREG_SAR_CHAN_RESULT05 0x401a0194 +#define CYREG_SAR_CHAN_RESULT06 0x401a0198 +#define CYREG_SAR_CHAN_RESULT07 0x401a019c +#define CYREG_SAR_CHAN_WORK_VALID 0x401a0200 +#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010 +#define CYREG_SAR_CHAN_RESULT_VALID 0x401a0204 +#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010 +#define CYREG_SAR_STATUS 0x401a0208 +#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000 +#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005 +#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001e +#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001 +#define CYFLD_SAR_BUSY__OFFSET 0x0000001f +#define CYFLD_SAR_BUSY__SIZE 0x00000001 +#define CYREG_SAR_AVG_STAT 0x401a020c +#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000 +#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014 +#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018 +#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008 +#define CYREG_SAR_INTR 0x401a0210 +#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001 +#define CYREG_SAR_INTR_SET 0x401a0214 +#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_SET__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001 +#define CYREG_SAR_INTR_MASK 0x401a0218 +#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001 +#define CYREG_SAR_INTR_MASKED 0x401a021c +#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001 +#define CYREG_SAR_SATURATE_INTR 0x401a0220 +#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_SET 0x401a0224 +#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_MASK 0x401a0228 +#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_MASKED 0x401a022c +#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR 0x401a0230 +#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_SET 0x401a0234 +#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_MASK 0x401a0238 +#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_MASKED 0x401a023c +#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010 +#define CYREG_SAR_INTR_CAUSE 0x401a0240 +#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001e +#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001 +#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001f +#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001 +#define CYREG_SAR_INJ_CHAN_CONFIG 0x401a0280 +#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000 +#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003 +#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003 +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004 +#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006 +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007 +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008 +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009 +#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000 +#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001 +#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000a +#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000c +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002 +#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001e +#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001 +#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001f +#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001 +#define CYREG_SAR_INJ_RESULT 0x401a0290 +#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000 +#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010 +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001c +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001d +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001e +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH0 0x401a0300 +#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004 +#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005 +#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006 +#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007 +#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008 +#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009 +#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000a +#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000b +#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000c +#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000d +#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000e +#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000f +#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010 +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011 +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016 +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017 +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018 +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019 +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001a +#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001b +#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001c +#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001d +#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x401a0304 +#define CYREG_SAR_MUX_SWITCH1 0x401a0308 +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x401a030c +#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x401a0340 +#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004 +#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005 +#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006 +#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007 +#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010 +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011 +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_STATUS 0x401a0348 +#define CYREG_SAR_PUMP_CTRL 0x401a0380 +#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000 +#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001 +#define CYREG_SAR_ANA_TRIM 0x401a0f00 +#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000 +#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003 +#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003 +#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001 +#define CYREG_SAR_WOUNDING 0x401a0f04 +#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000 +#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002 +#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000 +#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001 +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002 +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003 +#define CYDEV_CM0_BASE 0xe0000000 +#define CYDEV_CM0_SIZE 0x00100000 +#define CYREG_CM0_DWT_PID4 0xe0001fd0 +#define CYFLD_CM0_VALUE__OFFSET 0x00000000 +#define CYFLD_CM0_VALUE__SIZE 0x00000020 +#define CYREG_CM0_DWT_PID0 0xe0001fe0 +#define CYREG_CM0_DWT_PID1 0xe0001fe4 +#define CYREG_CM0_DWT_PID2 0xe0001fe8 +#define CYREG_CM0_DWT_PID3 0xe0001fec +#define CYREG_CM0_DWT_CID0 0xe0001ff0 +#define CYREG_CM0_DWT_CID1 0xe0001ff4 +#define CYREG_CM0_DWT_CID2 0xe0001ff8 +#define CYREG_CM0_DWT_CID3 0xe0001ffc +#define CYREG_CM0_BP_PID4 0xe0002fd0 +#define CYREG_CM0_BP_PID0 0xe0002fe0 +#define CYREG_CM0_BP_PID1 0xe0002fe4 +#define CYREG_CM0_BP_PID2 0xe0002fe8 +#define CYREG_CM0_BP_PID3 0xe0002fec +#define CYREG_CM0_BP_CID0 0xe0002ff0 +#define CYREG_CM0_BP_CID1 0xe0002ff4 +#define CYREG_CM0_BP_CID2 0xe0002ff8 +#define CYREG_CM0_BP_CID3 0xe0002ffc +#define CYREG_CM0_SYST_CSR 0xe000e010 +#define CYFLD_CM0_ENABLE__OFFSET 0x00000000 +#define CYFLD_CM0_ENABLE__SIZE 0x00000001 +#define CYFLD_CM0_TICKINT__OFFSET 0x00000001 +#define CYFLD_CM0_TICKINT__SIZE 0x00000001 +#define CYFLD_CM0_CLKSOURCE__OFFSET 0x00000002 +#define CYFLD_CM0_CLKSOURCE__SIZE 0x00000001 +#define CYFLD_CM0_COUNTFLAG__OFFSET 0x00000010 +#define CYFLD_CM0_COUNTFLAG__SIZE 0x00000001 +#define CYREG_CM0_SYST_RVR 0xe000e014 +#define CYFLD_CM0_RELOAD__OFFSET 0x00000000 +#define CYFLD_CM0_RELOAD__SIZE 0x00000018 +#define CYREG_CM0_SYST_CVR 0xe000e018 +#define CYFLD_CM0_CURRENT__OFFSET 0x00000000 +#define CYFLD_CM0_CURRENT__SIZE 0x00000018 +#define CYREG_CM0_SYST_CALIB 0xe000e01c +#define CYFLD_CM0_TENMS__OFFSET 0x00000000 +#define CYFLD_CM0_TENMS__SIZE 0x00000018 +#define CYFLD_CM0_SKEW__OFFSET 0x0000001e +#define CYFLD_CM0_SKEW__SIZE 0x00000001 +#define CYFLD_CM0_NOREF__OFFSET 0x0000001f +#define CYFLD_CM0_NOREF__SIZE 0x00000001 +#define CYREG_CM0_ISER 0xe000e100 +#define CYFLD_CM0_SETENA__OFFSET 0x00000000 +#define CYFLD_CM0_SETENA__SIZE 0x00000020 +#define CYREG_CM0_ICER 0xe000e180 +#define CYFLD_CM0_CLRENA__OFFSET 0x00000000 +#define CYFLD_CM0_CLRENA__SIZE 0x00000020 +#define CYREG_CM0_ISPR 0xe000e200 +#define CYFLD_CM0_SETPEND__OFFSET 0x00000000 +#define CYFLD_CM0_SETPEND__SIZE 0x00000020 +#define CYREG_CM0_ICPR 0xe000e280 +#define CYFLD_CM0_CLRPEND__OFFSET 0x00000000 +#define CYFLD_CM0_CLRPEND__SIZE 0x00000020 +#define CYREG_CM0_IPR0 0xe000e400 +#define CYFLD_CM0_PRI_N0__OFFSET 0x00000006 +#define CYFLD_CM0_PRI_N0__SIZE 0x00000002 +#define CYFLD_CM0_PRI_N1__OFFSET 0x0000000e +#define CYFLD_CM0_PRI_N1__SIZE 0x00000002 +#define CYFLD_CM0_PRI_N2__OFFSET 0x00000016 +#define CYFLD_CM0_PRI_N2__SIZE 0x00000002 +#define CYFLD_CM0_PRI_N3__OFFSET 0x0000001e +#define CYFLD_CM0_PRI_N3__SIZE 0x00000002 +#define CYREG_CM0_IPR1 0xe000e404 +#define CYREG_CM0_IPR2 0xe000e408 +#define CYREG_CM0_IPR3 0xe000e40c +#define CYREG_CM0_IPR4 0xe000e410 +#define CYREG_CM0_IPR5 0xe000e414 +#define CYREG_CM0_IPR6 0xe000e418 +#define CYREG_CM0_IPR7 0xe000e41c +#define CYREG_CM0_CPUID 0xe000ed00 +#define CYFLD_CM0_REVISION__OFFSET 0x00000000 +#define CYFLD_CM0_REVISION__SIZE 0x00000004 +#define CYFLD_CM0_PARTNO__OFFSET 0x00000004 +#define CYFLD_CM0_PARTNO__SIZE 0x0000000c +#define CYFLD_CM0_CONSTANT__OFFSET 0x00000010 +#define CYFLD_CM0_CONSTANT__SIZE 0x00000004 +#define CYFLD_CM0_VARIANT__OFFSET 0x00000014 +#define CYFLD_CM0_VARIANT__SIZE 0x00000004 +#define CYFLD_CM0_IMPLEMENTER__OFFSET 0x00000018 +#define CYFLD_CM0_IMPLEMENTER__SIZE 0x00000008 +#define CYREG_CM0_ICSR 0xe000ed04 +#define CYFLD_CM0_VECTACTIVE__OFFSET 0x00000000 +#define CYFLD_CM0_VECTACTIVE__SIZE 0x00000009 +#define CYFLD_CM0_VECTPENDING__OFFSET 0x0000000c +#define CYFLD_CM0_VECTPENDING__SIZE 0x00000009 +#define CYFLD_CM0_ISRPENDING__OFFSET 0x00000016 +#define CYFLD_CM0_ISRPENDING__SIZE 0x00000001 +#define CYFLD_CM0_ISRPREEMPT__OFFSET 0x00000017 +#define CYFLD_CM0_ISRPREEMPT__SIZE 0x00000001 +#define CYFLD_CM0_PENDSTCLR__OFFSET 0x00000019 +#define CYFLD_CM0_PENDSTCLR__SIZE 0x00000001 +#define CYFLD_CM0_PENDSTSETb__OFFSET 0x0000001a +#define CYFLD_CM0_PENDSTSETb__SIZE 0x00000001 +#define CYFLD_CM0_PENDSVCLR__OFFSET 0x0000001b +#define CYFLD_CM0_PENDSVCLR__SIZE 0x00000001 +#define CYFLD_CM0_PENDSVSET__OFFSET 0x0000001c +#define CYFLD_CM0_PENDSVSET__SIZE 0x00000001 +#define CYFLD_CM0_NMIPENDSET__OFFSET 0x0000001f +#define CYFLD_CM0_NMIPENDSET__SIZE 0x00000001 +#define CYREG_CM0_AIRCR 0xe000ed0c +#define CYFLD_CM0_VECTCLRACTIVE__OFFSET 0x00000001 +#define CYFLD_CM0_VECTCLRACTIVE__SIZE 0x00000001 +#define CYFLD_CM0_SYSRESETREQ__OFFSET 0x00000002 +#define CYFLD_CM0_SYSRESETREQ__SIZE 0x00000001 +#define CYFLD_CM0_ENDIANNESS__OFFSET 0x0000000f +#define CYFLD_CM0_ENDIANNESS__SIZE 0x00000001 +#define CYFLD_CM0_VECTKEY__OFFSET 0x00000010 +#define CYFLD_CM0_VECTKEY__SIZE 0x00000010 +#define CYREG_CM0_SCR 0xe000ed10 +#define CYFLD_CM0_SLEEPONEXIT__OFFSET 0x00000001 +#define CYFLD_CM0_SLEEPONEXIT__SIZE 0x00000001 +#define CYFLD_CM0_SLEEPDEEP__OFFSET 0x00000002 +#define CYFLD_CM0_SLEEPDEEP__SIZE 0x00000001 +#define CYFLD_CM0_SEVONPEND__OFFSET 0x00000004 +#define CYFLD_CM0_SEVONPEND__SIZE 0x00000001 +#define CYREG_CM0_CCR 0xe000ed14 +#define CYFLD_CM0_UNALIGN_TRP__OFFSET 0x00000003 +#define CYFLD_CM0_UNALIGN_TRP__SIZE 0x00000001 +#define CYFLD_CM0_STKALIGN__OFFSET 0x00000009 +#define CYFLD_CM0_STKALIGN__SIZE 0x00000001 +#define CYREG_CM0_SHPR2 0xe000ed1c +#define CYFLD_CM0_PRI_11__OFFSET 0x0000001e +#define CYFLD_CM0_PRI_11__SIZE 0x00000002 +#define CYREG_CM0_SHPR3 0xe000ed20 +#define CYFLD_CM0_PRI_14__OFFSET 0x00000016 +#define CYFLD_CM0_PRI_14__SIZE 0x00000002 +#define CYFLD_CM0_PRI_15__OFFSET 0x0000001e +#define CYFLD_CM0_PRI_15__SIZE 0x00000002 +#define CYREG_CM0_SHCSR 0xe000ed24 +#define CYFLD_CM0_SVCALLPENDED__OFFSET 0x0000000f +#define CYFLD_CM0_SVCALLPENDED__SIZE 0x00000001 +#define CYREG_CM0_SCS_PID4 0xe000efd0 +#define CYREG_CM0_SCS_PID0 0xe000efe0 +#define CYREG_CM0_SCS_PID1 0xe000efe4 +#define CYREG_CM0_SCS_PID2 0xe000efe8 +#define CYREG_CM0_SCS_PID3 0xe000efec +#define CYREG_CM0_SCS_CID0 0xe000eff0 +#define CYREG_CM0_SCS_CID1 0xe000eff4 +#define CYREG_CM0_SCS_CID2 0xe000eff8 +#define CYREG_CM0_SCS_CID3 0xe000effc +#define CYREG_CM0_ROM_SCS 0xe00ff000 +#define CYREG_CM0_ROM_DWT 0xe00ff004 +#define CYREG_CM0_ROM_BPU 0xe00ff008 +#define CYREG_CM0_ROM_END 0xe00ff00c +#define CYREG_CM0_ROM_CSMT 0xe00fffcc +#define CYREG_CM0_ROM_PID4 0xe00fffd0 +#define CYREG_CM0_ROM_PID0 0xe00fffe0 +#define CYREG_CM0_ROM_PID1 0xe00fffe4 +#define CYREG_CM0_ROM_PID2 0xe00fffe8 +#define CYREG_CM0_ROM_PID3 0xe00fffec +#define CYREG_CM0_ROM_CID0 0xe00ffff0 +#define CYREG_CM0_ROM_CID1 0xe00ffff4 +#define CYREG_CM0_ROM_CID2 0xe00ffff8 +#define CYREG_CM0_ROM_CID3 0xe00ffffc +#define CYDEV_CoreSightTable_BASE 0xf0000000 +#define CYDEV_CoreSightTable_SIZE 0x00001000 +#define CYREG_CoreSightTable_DATA_MBASE 0xf0000000 +#define CYREG_CoreSightTable_DATA_MSIZE 0x00001000 +#define CYDEV_FLS_SECTOR_SIZE 0x00008000 +#define CYDEV_FLS_ROW_SIZE 0x00000080 diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicerv_trm.inc b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicerv_trm.inc new file mode 100644 index 0000000..3431da4 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydevicerv_trm.inc @@ -0,0 +1,19450 @@ +; +; File Name: cydevicerv_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SFLASH_BASE +CYDEV_SFLASH_BASE EQU 0x0ffff000 + ENDIF + IF :LNOT::DEF:CYDEV_SFLASH_SIZE +CYDEV_SFLASH_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW00 +CYREG_SFLASH_PROT_ROW00 EQU 0x0ffff000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA8__OFFSET +CYFLD_SFLASH_DATA8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA8__SIZE +CYFLD_SFLASH_DATA8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW01 +CYREG_SFLASH_PROT_ROW01 EQU 0x0ffff001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW02 +CYREG_SFLASH_PROT_ROW02 EQU 0x0ffff002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW03 +CYREG_SFLASH_PROT_ROW03 EQU 0x0ffff003 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW04 +CYREG_SFLASH_PROT_ROW04 EQU 0x0ffff004 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW05 +CYREG_SFLASH_PROT_ROW05 EQU 0x0ffff005 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW06 +CYREG_SFLASH_PROT_ROW06 EQU 0x0ffff006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW07 +CYREG_SFLASH_PROT_ROW07 EQU 0x0ffff007 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW08 +CYREG_SFLASH_PROT_ROW08 EQU 0x0ffff008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW09 +CYREG_SFLASH_PROT_ROW09 EQU 0x0ffff009 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW10 +CYREG_SFLASH_PROT_ROW10 EQU 0x0ffff00a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW11 +CYREG_SFLASH_PROT_ROW11 EQU 0x0ffff00b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW12 +CYREG_SFLASH_PROT_ROW12 EQU 0x0ffff00c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW13 +CYREG_SFLASH_PROT_ROW13 EQU 0x0ffff00d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW14 +CYREG_SFLASH_PROT_ROW14 EQU 0x0ffff00e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW15 +CYREG_SFLASH_PROT_ROW15 EQU 0x0ffff00f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW16 +CYREG_SFLASH_PROT_ROW16 EQU 0x0ffff010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW17 +CYREG_SFLASH_PROT_ROW17 EQU 0x0ffff011 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW18 +CYREG_SFLASH_PROT_ROW18 EQU 0x0ffff012 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW19 +CYREG_SFLASH_PROT_ROW19 EQU 0x0ffff013 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW20 +CYREG_SFLASH_PROT_ROW20 EQU 0x0ffff014 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW21 +CYREG_SFLASH_PROT_ROW21 EQU 0x0ffff015 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW22 +CYREG_SFLASH_PROT_ROW22 EQU 0x0ffff016 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW23 +CYREG_SFLASH_PROT_ROW23 EQU 0x0ffff017 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW24 +CYREG_SFLASH_PROT_ROW24 EQU 0x0ffff018 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW25 +CYREG_SFLASH_PROT_ROW25 EQU 0x0ffff019 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW26 +CYREG_SFLASH_PROT_ROW26 EQU 0x0ffff01a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW27 +CYREG_SFLASH_PROT_ROW27 EQU 0x0ffff01b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW28 +CYREG_SFLASH_PROT_ROW28 EQU 0x0ffff01c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW29 +CYREG_SFLASH_PROT_ROW29 EQU 0x0ffff01d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW30 +CYREG_SFLASH_PROT_ROW30 EQU 0x0ffff01e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW31 +CYREG_SFLASH_PROT_ROW31 EQU 0x0ffff01f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW32 +CYREG_SFLASH_PROT_ROW32 EQU 0x0ffff020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW33 +CYREG_SFLASH_PROT_ROW33 EQU 0x0ffff021 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW34 +CYREG_SFLASH_PROT_ROW34 EQU 0x0ffff022 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW35 +CYREG_SFLASH_PROT_ROW35 EQU 0x0ffff023 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW36 +CYREG_SFLASH_PROT_ROW36 EQU 0x0ffff024 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW37 +CYREG_SFLASH_PROT_ROW37 EQU 0x0ffff025 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW38 +CYREG_SFLASH_PROT_ROW38 EQU 0x0ffff026 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW39 +CYREG_SFLASH_PROT_ROW39 EQU 0x0ffff027 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW40 +CYREG_SFLASH_PROT_ROW40 EQU 0x0ffff028 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW41 +CYREG_SFLASH_PROT_ROW41 EQU 0x0ffff029 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW42 +CYREG_SFLASH_PROT_ROW42 EQU 0x0ffff02a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW43 +CYREG_SFLASH_PROT_ROW43 EQU 0x0ffff02b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW44 +CYREG_SFLASH_PROT_ROW44 EQU 0x0ffff02c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW45 +CYREG_SFLASH_PROT_ROW45 EQU 0x0ffff02d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW46 +CYREG_SFLASH_PROT_ROW46 EQU 0x0ffff02e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW47 +CYREG_SFLASH_PROT_ROW47 EQU 0x0ffff02f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW48 +CYREG_SFLASH_PROT_ROW48 EQU 0x0ffff030 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW49 +CYREG_SFLASH_PROT_ROW49 EQU 0x0ffff031 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW50 +CYREG_SFLASH_PROT_ROW50 EQU 0x0ffff032 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW51 +CYREG_SFLASH_PROT_ROW51 EQU 0x0ffff033 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW52 +CYREG_SFLASH_PROT_ROW52 EQU 0x0ffff034 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW53 +CYREG_SFLASH_PROT_ROW53 EQU 0x0ffff035 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW54 +CYREG_SFLASH_PROT_ROW54 EQU 0x0ffff036 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW55 +CYREG_SFLASH_PROT_ROW55 EQU 0x0ffff037 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW56 +CYREG_SFLASH_PROT_ROW56 EQU 0x0ffff038 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW57 +CYREG_SFLASH_PROT_ROW57 EQU 0x0ffff039 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW58 +CYREG_SFLASH_PROT_ROW58 EQU 0x0ffff03a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW59 +CYREG_SFLASH_PROT_ROW59 EQU 0x0ffff03b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW60 +CYREG_SFLASH_PROT_ROW60 EQU 0x0ffff03c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW61 +CYREG_SFLASH_PROT_ROW61 EQU 0x0ffff03d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW62 +CYREG_SFLASH_PROT_ROW62 EQU 0x0ffff03e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW63 +CYREG_SFLASH_PROT_ROW63 EQU 0x0ffff03f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_PROTECTION +CYREG_SFLASH_PROT_PROTECTION EQU 0x0ffff07f + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PROT_LEVEL__OFFSET +CYFLD_SFLASH_PROT_LEVEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PROT_LEVEL__SIZE +CYFLD_SFLASH_PROT_LEVEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_VIRGIN +CYVAL_SFLASH_PROT_LEVEL_VIRGIN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_OPEN +CYVAL_SFLASH_PROT_LEVEL_OPEN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_PROTECTED +CYVAL_SFLASH_PROT_LEVEL_PROTECTED EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_KILL +CYVAL_SFLASH_PROT_LEVEL_KILL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B000 +CYREG_SFLASH_AV_PAIRS_8B000 EQU 0x0ffff080 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B001 +CYREG_SFLASH_AV_PAIRS_8B001 EQU 0x0ffff081 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B002 +CYREG_SFLASH_AV_PAIRS_8B002 EQU 0x0ffff082 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B003 +CYREG_SFLASH_AV_PAIRS_8B003 EQU 0x0ffff083 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B004 +CYREG_SFLASH_AV_PAIRS_8B004 EQU 0x0ffff084 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B005 +CYREG_SFLASH_AV_PAIRS_8B005 EQU 0x0ffff085 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B006 +CYREG_SFLASH_AV_PAIRS_8B006 EQU 0x0ffff086 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B007 +CYREG_SFLASH_AV_PAIRS_8B007 EQU 0x0ffff087 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B008 +CYREG_SFLASH_AV_PAIRS_8B008 EQU 0x0ffff088 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B009 +CYREG_SFLASH_AV_PAIRS_8B009 EQU 0x0ffff089 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B010 +CYREG_SFLASH_AV_PAIRS_8B010 EQU 0x0ffff08a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B011 +CYREG_SFLASH_AV_PAIRS_8B011 EQU 0x0ffff08b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B012 +CYREG_SFLASH_AV_PAIRS_8B012 EQU 0x0ffff08c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B013 +CYREG_SFLASH_AV_PAIRS_8B013 EQU 0x0ffff08d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B014 +CYREG_SFLASH_AV_PAIRS_8B014 EQU 0x0ffff08e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B015 +CYREG_SFLASH_AV_PAIRS_8B015 EQU 0x0ffff08f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B016 +CYREG_SFLASH_AV_PAIRS_8B016 EQU 0x0ffff090 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B017 +CYREG_SFLASH_AV_PAIRS_8B017 EQU 0x0ffff091 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B018 +CYREG_SFLASH_AV_PAIRS_8B018 EQU 0x0ffff092 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B019 +CYREG_SFLASH_AV_PAIRS_8B019 EQU 0x0ffff093 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B020 +CYREG_SFLASH_AV_PAIRS_8B020 EQU 0x0ffff094 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B021 +CYREG_SFLASH_AV_PAIRS_8B021 EQU 0x0ffff095 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B022 +CYREG_SFLASH_AV_PAIRS_8B022 EQU 0x0ffff096 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B023 +CYREG_SFLASH_AV_PAIRS_8B023 EQU 0x0ffff097 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B024 +CYREG_SFLASH_AV_PAIRS_8B024 EQU 0x0ffff098 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B025 +CYREG_SFLASH_AV_PAIRS_8B025 EQU 0x0ffff099 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B026 +CYREG_SFLASH_AV_PAIRS_8B026 EQU 0x0ffff09a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B027 +CYREG_SFLASH_AV_PAIRS_8B027 EQU 0x0ffff09b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B028 +CYREG_SFLASH_AV_PAIRS_8B028 EQU 0x0ffff09c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B029 +CYREG_SFLASH_AV_PAIRS_8B029 EQU 0x0ffff09d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B030 +CYREG_SFLASH_AV_PAIRS_8B030 EQU 0x0ffff09e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B031 +CYREG_SFLASH_AV_PAIRS_8B031 EQU 0x0ffff09f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B032 +CYREG_SFLASH_AV_PAIRS_8B032 EQU 0x0ffff0a0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B033 +CYREG_SFLASH_AV_PAIRS_8B033 EQU 0x0ffff0a1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B034 +CYREG_SFLASH_AV_PAIRS_8B034 EQU 0x0ffff0a2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B035 +CYREG_SFLASH_AV_PAIRS_8B035 EQU 0x0ffff0a3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B036 +CYREG_SFLASH_AV_PAIRS_8B036 EQU 0x0ffff0a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B037 +CYREG_SFLASH_AV_PAIRS_8B037 EQU 0x0ffff0a5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B038 +CYREG_SFLASH_AV_PAIRS_8B038 EQU 0x0ffff0a6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B039 +CYREG_SFLASH_AV_PAIRS_8B039 EQU 0x0ffff0a7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B040 +CYREG_SFLASH_AV_PAIRS_8B040 EQU 0x0ffff0a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B041 +CYREG_SFLASH_AV_PAIRS_8B041 EQU 0x0ffff0a9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B042 +CYREG_SFLASH_AV_PAIRS_8B042 EQU 0x0ffff0aa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B043 +CYREG_SFLASH_AV_PAIRS_8B043 EQU 0x0ffff0ab + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B044 +CYREG_SFLASH_AV_PAIRS_8B044 EQU 0x0ffff0ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B045 +CYREG_SFLASH_AV_PAIRS_8B045 EQU 0x0ffff0ad + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B046 +CYREG_SFLASH_AV_PAIRS_8B046 EQU 0x0ffff0ae + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B047 +CYREG_SFLASH_AV_PAIRS_8B047 EQU 0x0ffff0af + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B048 +CYREG_SFLASH_AV_PAIRS_8B048 EQU 0x0ffff0b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B049 +CYREG_SFLASH_AV_PAIRS_8B049 EQU 0x0ffff0b1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B050 +CYREG_SFLASH_AV_PAIRS_8B050 EQU 0x0ffff0b2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B051 +CYREG_SFLASH_AV_PAIRS_8B051 EQU 0x0ffff0b3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B052 +CYREG_SFLASH_AV_PAIRS_8B052 EQU 0x0ffff0b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B053 +CYREG_SFLASH_AV_PAIRS_8B053 EQU 0x0ffff0b5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B054 +CYREG_SFLASH_AV_PAIRS_8B054 EQU 0x0ffff0b6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B055 +CYREG_SFLASH_AV_PAIRS_8B055 EQU 0x0ffff0b7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B056 +CYREG_SFLASH_AV_PAIRS_8B056 EQU 0x0ffff0b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B057 +CYREG_SFLASH_AV_PAIRS_8B057 EQU 0x0ffff0b9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B058 +CYREG_SFLASH_AV_PAIRS_8B058 EQU 0x0ffff0ba + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B059 +CYREG_SFLASH_AV_PAIRS_8B059 EQU 0x0ffff0bb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B060 +CYREG_SFLASH_AV_PAIRS_8B060 EQU 0x0ffff0bc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B061 +CYREG_SFLASH_AV_PAIRS_8B061 EQU 0x0ffff0bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B062 +CYREG_SFLASH_AV_PAIRS_8B062 EQU 0x0ffff0be + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B063 +CYREG_SFLASH_AV_PAIRS_8B063 EQU 0x0ffff0bf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B064 +CYREG_SFLASH_AV_PAIRS_8B064 EQU 0x0ffff0c0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B065 +CYREG_SFLASH_AV_PAIRS_8B065 EQU 0x0ffff0c1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B066 +CYREG_SFLASH_AV_PAIRS_8B066 EQU 0x0ffff0c2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B067 +CYREG_SFLASH_AV_PAIRS_8B067 EQU 0x0ffff0c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B068 +CYREG_SFLASH_AV_PAIRS_8B068 EQU 0x0ffff0c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B069 +CYREG_SFLASH_AV_PAIRS_8B069 EQU 0x0ffff0c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B070 +CYREG_SFLASH_AV_PAIRS_8B070 EQU 0x0ffff0c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B071 +CYREG_SFLASH_AV_PAIRS_8B071 EQU 0x0ffff0c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B072 +CYREG_SFLASH_AV_PAIRS_8B072 EQU 0x0ffff0c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B073 +CYREG_SFLASH_AV_PAIRS_8B073 EQU 0x0ffff0c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B074 +CYREG_SFLASH_AV_PAIRS_8B074 EQU 0x0ffff0ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B075 +CYREG_SFLASH_AV_PAIRS_8B075 EQU 0x0ffff0cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B076 +CYREG_SFLASH_AV_PAIRS_8B076 EQU 0x0ffff0cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B077 +CYREG_SFLASH_AV_PAIRS_8B077 EQU 0x0ffff0cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B078 +CYREG_SFLASH_AV_PAIRS_8B078 EQU 0x0ffff0ce + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B079 +CYREG_SFLASH_AV_PAIRS_8B079 EQU 0x0ffff0cf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B080 +CYREG_SFLASH_AV_PAIRS_8B080 EQU 0x0ffff0d0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B081 +CYREG_SFLASH_AV_PAIRS_8B081 EQU 0x0ffff0d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B082 +CYREG_SFLASH_AV_PAIRS_8B082 EQU 0x0ffff0d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B083 +CYREG_SFLASH_AV_PAIRS_8B083 EQU 0x0ffff0d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B084 +CYREG_SFLASH_AV_PAIRS_8B084 EQU 0x0ffff0d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B085 +CYREG_SFLASH_AV_PAIRS_8B085 EQU 0x0ffff0d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B086 +CYREG_SFLASH_AV_PAIRS_8B086 EQU 0x0ffff0d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B087 +CYREG_SFLASH_AV_PAIRS_8B087 EQU 0x0ffff0d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B088 +CYREG_SFLASH_AV_PAIRS_8B088 EQU 0x0ffff0d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B089 +CYREG_SFLASH_AV_PAIRS_8B089 EQU 0x0ffff0d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B090 +CYREG_SFLASH_AV_PAIRS_8B090 EQU 0x0ffff0da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B091 +CYREG_SFLASH_AV_PAIRS_8B091 EQU 0x0ffff0db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B092 +CYREG_SFLASH_AV_PAIRS_8B092 EQU 0x0ffff0dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B093 +CYREG_SFLASH_AV_PAIRS_8B093 EQU 0x0ffff0dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B094 +CYREG_SFLASH_AV_PAIRS_8B094 EQU 0x0ffff0de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B095 +CYREG_SFLASH_AV_PAIRS_8B095 EQU 0x0ffff0df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B096 +CYREG_SFLASH_AV_PAIRS_8B096 EQU 0x0ffff0e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B097 +CYREG_SFLASH_AV_PAIRS_8B097 EQU 0x0ffff0e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B098 +CYREG_SFLASH_AV_PAIRS_8B098 EQU 0x0ffff0e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B099 +CYREG_SFLASH_AV_PAIRS_8B099 EQU 0x0ffff0e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B100 +CYREG_SFLASH_AV_PAIRS_8B100 EQU 0x0ffff0e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B101 +CYREG_SFLASH_AV_PAIRS_8B101 EQU 0x0ffff0e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B102 +CYREG_SFLASH_AV_PAIRS_8B102 EQU 0x0ffff0e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B103 +CYREG_SFLASH_AV_PAIRS_8B103 EQU 0x0ffff0e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B104 +CYREG_SFLASH_AV_PAIRS_8B104 EQU 0x0ffff0e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B105 +CYREG_SFLASH_AV_PAIRS_8B105 EQU 0x0ffff0e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B106 +CYREG_SFLASH_AV_PAIRS_8B106 EQU 0x0ffff0ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B107 +CYREG_SFLASH_AV_PAIRS_8B107 EQU 0x0ffff0eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B108 +CYREG_SFLASH_AV_PAIRS_8B108 EQU 0x0ffff0ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B109 +CYREG_SFLASH_AV_PAIRS_8B109 EQU 0x0ffff0ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B110 +CYREG_SFLASH_AV_PAIRS_8B110 EQU 0x0ffff0ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B111 +CYREG_SFLASH_AV_PAIRS_8B111 EQU 0x0ffff0ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B112 +CYREG_SFLASH_AV_PAIRS_8B112 EQU 0x0ffff0f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B113 +CYREG_SFLASH_AV_PAIRS_8B113 EQU 0x0ffff0f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B114 +CYREG_SFLASH_AV_PAIRS_8B114 EQU 0x0ffff0f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B115 +CYREG_SFLASH_AV_PAIRS_8B115 EQU 0x0ffff0f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B116 +CYREG_SFLASH_AV_PAIRS_8B116 EQU 0x0ffff0f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B117 +CYREG_SFLASH_AV_PAIRS_8B117 EQU 0x0ffff0f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B118 +CYREG_SFLASH_AV_PAIRS_8B118 EQU 0x0ffff0f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B119 +CYREG_SFLASH_AV_PAIRS_8B119 EQU 0x0ffff0f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B120 +CYREG_SFLASH_AV_PAIRS_8B120 EQU 0x0ffff0f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B121 +CYREG_SFLASH_AV_PAIRS_8B121 EQU 0x0ffff0f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B122 +CYREG_SFLASH_AV_PAIRS_8B122 EQU 0x0ffff0fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B123 +CYREG_SFLASH_AV_PAIRS_8B123 EQU 0x0ffff0fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B124 +CYREG_SFLASH_AV_PAIRS_8B124 EQU 0x0ffff0fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B125 +CYREG_SFLASH_AV_PAIRS_8B125 EQU 0x0ffff0fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B126 +CYREG_SFLASH_AV_PAIRS_8B126 EQU 0x0ffff0fe + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B127 +CYREG_SFLASH_AV_PAIRS_8B127 EQU 0x0ffff0ff + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B00 +CYREG_SFLASH_AV_PAIRS_32B00 EQU 0x0ffff100 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA32__OFFSET +CYFLD_SFLASH_DATA32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA32__SIZE +CYFLD_SFLASH_DATA32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B01 +CYREG_SFLASH_AV_PAIRS_32B01 EQU 0x0ffff104 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B02 +CYREG_SFLASH_AV_PAIRS_32B02 EQU 0x0ffff108 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B03 +CYREG_SFLASH_AV_PAIRS_32B03 EQU 0x0ffff10c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B04 +CYREG_SFLASH_AV_PAIRS_32B04 EQU 0x0ffff110 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B05 +CYREG_SFLASH_AV_PAIRS_32B05 EQU 0x0ffff114 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B06 +CYREG_SFLASH_AV_PAIRS_32B06 EQU 0x0ffff118 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B07 +CYREG_SFLASH_AV_PAIRS_32B07 EQU 0x0ffff11c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B08 +CYREG_SFLASH_AV_PAIRS_32B08 EQU 0x0ffff120 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B09 +CYREG_SFLASH_AV_PAIRS_32B09 EQU 0x0ffff124 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B10 +CYREG_SFLASH_AV_PAIRS_32B10 EQU 0x0ffff128 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B11 +CYREG_SFLASH_AV_PAIRS_32B11 EQU 0x0ffff12c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B12 +CYREG_SFLASH_AV_PAIRS_32B12 EQU 0x0ffff130 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B13 +CYREG_SFLASH_AV_PAIRS_32B13 EQU 0x0ffff134 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B14 +CYREG_SFLASH_AV_PAIRS_32B14 EQU 0x0ffff138 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B15 +CYREG_SFLASH_AV_PAIRS_32B15 EQU 0x0ffff13c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CPUSS_WOUNDING +CYREG_SFLASH_CPUSS_WOUNDING EQU 0x0ffff140 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SILICON_ID +CYREG_SFLASH_SILICON_ID EQU 0x0ffff144 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ID__OFFSET +CYFLD_SFLASH_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ID__SIZE +CYFLD_SFLASH_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CPUSS_PRIV_RAM +CYREG_SFLASH_CPUSS_PRIV_RAM EQU 0x0ffff148 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CPUSS_PRIV_FLASH +CYREG_SFLASH_CPUSS_PRIV_FLASH EQU 0x0ffff14c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_HIB_KEY_DELAY +CYREG_SFLASH_HIB_KEY_DELAY EQU 0x0ffff150 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET +CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE +CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DPSLP_KEY_DELAY +CYREG_SFLASH_DPSLP_KEY_DELAY EQU 0x0ffff152 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SWD_CONFIG +CYREG_SFLASH_SWD_CONFIG EQU 0x0ffff154 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SWD_SELECT__OFFSET +CYFLD_SFLASH_SWD_SELECT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SWD_SELECT__SIZE +CYFLD_SFLASH_SWD_SELECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SWD_LISTEN +CYREG_SFLASH_SWD_LISTEN EQU 0x0ffff158 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CYCLES__OFFSET +CYFLD_SFLASH_CYCLES__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CYCLES__SIZE +CYFLD_SFLASH_CYCLES__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_FLASH_START +CYREG_SFLASH_FLASH_START EQU 0x0ffff15c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ADDRESS__OFFSET +CYFLD_SFLASH_ADDRESS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ADDRESS__SIZE +CYFLD_SFLASH_ADDRESS__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM1_HVIDAC +CYREG_SFLASH_CSD_TRIM1_HVIDAC EQU 0x0ffff160 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TRIM8__OFFSET +CYFLD_SFLASH_TRIM8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TRIM8__SIZE +CYFLD_SFLASH_TRIM8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM2_HVIDAC +CYREG_SFLASH_CSD_TRIM2_HVIDAC EQU 0x0ffff161 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM1_CSD +CYREG_SFLASH_CSD_TRIM1_CSD EQU 0x0ffff162 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM2_CSD +CYREG_SFLASH_CSD_TRIM2_CSD EQU 0x0ffff163 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_MULTIPLIER +CYREG_SFLASH_SAR_TEMP_MULTIPLIER EQU 0x0ffff164 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET +CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE +CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_OFFSET +CYREG_SFLASH_SAR_TEMP_OFFSET EQU 0x0ffff166 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__OFFSET +CYFLD_SFLASH_TEMP_OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__SIZE +CYFLD_SFLASH_TEMP_OFFSET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SKIP_CHECKSUM +CYREG_SFLASH_SKIP_CHECKSUM EQU 0x0ffff169 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SKIP__OFFSET +CYFLD_SFLASH_SKIP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SKIP__SIZE +CYFLD_SFLASH_SKIP__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY0 +CYREG_SFLASH_PROT_VIRGINKEY0 EQU 0x0ffff170 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_KEY8__OFFSET +CYFLD_SFLASH_KEY8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_KEY8__SIZE +CYFLD_SFLASH_KEY8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY1 +CYREG_SFLASH_PROT_VIRGINKEY1 EQU 0x0ffff171 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY2 +CYREG_SFLASH_PROT_VIRGINKEY2 EQU 0x0ffff172 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY3 +CYREG_SFLASH_PROT_VIRGINKEY3 EQU 0x0ffff173 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY4 +CYREG_SFLASH_PROT_VIRGINKEY4 EQU 0x0ffff174 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY5 +CYREG_SFLASH_PROT_VIRGINKEY5 EQU 0x0ffff175 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY6 +CYREG_SFLASH_PROT_VIRGINKEY6 EQU 0x0ffff176 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY7 +CYREG_SFLASH_PROT_VIRGINKEY7 EQU 0x0ffff177 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT0 +CYREG_SFLASH_DIE_LOT0 EQU 0x0ffff178 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_LOT__OFFSET +CYFLD_SFLASH_LOT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_LOT__SIZE +CYFLD_SFLASH_LOT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT1 +CYREG_SFLASH_DIE_LOT1 EQU 0x0ffff179 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT2 +CYREG_SFLASH_DIE_LOT2 EQU 0x0ffff17a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_WAFER +CYREG_SFLASH_DIE_WAFER EQU 0x0ffff17b + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAFER__OFFSET +CYFLD_SFLASH_WAFER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAFER__SIZE +CYFLD_SFLASH_WAFER__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_X +CYREG_SFLASH_DIE_X EQU 0x0ffff17c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_X__OFFSET +CYFLD_SFLASH_X__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_X__SIZE +CYFLD_SFLASH_X__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CRI_PASS__OFFSET +CYFLD_SFLASH_CRI_PASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CRI_PASS__SIZE +CYFLD_SFLASH_CRI_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_Y +CYREG_SFLASH_DIE_Y EQU 0x0ffff17d + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_Y__OFFSET +CYFLD_SFLASH_Y__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_Y__SIZE +CYFLD_SFLASH_Y__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHI_PASS__OFFSET +CYFLD_SFLASH_CHI_PASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHI_PASS__SIZE +CYFLD_SFLASH_CHI_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_SORT +CYREG_SFLASH_DIE_SORT EQU 0x0ffff17e + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S1_PASS__OFFSET +CYFLD_SFLASH_S1_PASS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S1_PASS__SIZE +CYFLD_SFLASH_S1_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S2_PASS__OFFSET +CYFLD_SFLASH_S2_PASS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S2_PASS__SIZE +CYFLD_SFLASH_S2_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S3_PASS__OFFSET +CYFLD_SFLASH_S3_PASS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S3_PASS__SIZE +CYFLD_SFLASH_S3_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_MINOR +CYREG_SFLASH_DIE_MINOR EQU 0x0ffff17f + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MINOR__OFFSET +CYFLD_SFLASH_MINOR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MINOR__SIZE +CYFLD_SFLASH_MINOR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA00 +CYREG_SFLASH_PE_TE_DATA00 EQU 0x0ffff180 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA01 +CYREG_SFLASH_PE_TE_DATA01 EQU 0x0ffff181 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA02 +CYREG_SFLASH_PE_TE_DATA02 EQU 0x0ffff182 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA03 +CYREG_SFLASH_PE_TE_DATA03 EQU 0x0ffff183 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA04 +CYREG_SFLASH_PE_TE_DATA04 EQU 0x0ffff184 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA05 +CYREG_SFLASH_PE_TE_DATA05 EQU 0x0ffff185 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA06 +CYREG_SFLASH_PE_TE_DATA06 EQU 0x0ffff186 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA07 +CYREG_SFLASH_PE_TE_DATA07 EQU 0x0ffff187 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA08 +CYREG_SFLASH_PE_TE_DATA08 EQU 0x0ffff188 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA09 +CYREG_SFLASH_PE_TE_DATA09 EQU 0x0ffff189 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA10 +CYREG_SFLASH_PE_TE_DATA10 EQU 0x0ffff18a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA11 +CYREG_SFLASH_PE_TE_DATA11 EQU 0x0ffff18b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA12 +CYREG_SFLASH_PE_TE_DATA12 EQU 0x0ffff18c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA13 +CYREG_SFLASH_PE_TE_DATA13 EQU 0x0ffff18d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA14 +CYREG_SFLASH_PE_TE_DATA14 EQU 0x0ffff18e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA15 +CYREG_SFLASH_PE_TE_DATA15 EQU 0x0ffff18f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA16 +CYREG_SFLASH_PE_TE_DATA16 EQU 0x0ffff190 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA17 +CYREG_SFLASH_PE_TE_DATA17 EQU 0x0ffff191 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA18 +CYREG_SFLASH_PE_TE_DATA18 EQU 0x0ffff192 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA19 +CYREG_SFLASH_PE_TE_DATA19 EQU 0x0ffff193 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA20 +CYREG_SFLASH_PE_TE_DATA20 EQU 0x0ffff194 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA21 +CYREG_SFLASH_PE_TE_DATA21 EQU 0x0ffff195 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA22 +CYREG_SFLASH_PE_TE_DATA22 EQU 0x0ffff196 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA23 +CYREG_SFLASH_PE_TE_DATA23 EQU 0x0ffff197 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA24 +CYREG_SFLASH_PE_TE_DATA24 EQU 0x0ffff198 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA25 +CYREG_SFLASH_PE_TE_DATA25 EQU 0x0ffff199 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA26 +CYREG_SFLASH_PE_TE_DATA26 EQU 0x0ffff19a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA27 +CYREG_SFLASH_PE_TE_DATA27 EQU 0x0ffff19b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA28 +CYREG_SFLASH_PE_TE_DATA28 EQU 0x0ffff19c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA29 +CYREG_SFLASH_PE_TE_DATA29 EQU 0x0ffff19d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA30 +CYREG_SFLASH_PE_TE_DATA30 EQU 0x0ffff19e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA31 +CYREG_SFLASH_PE_TE_DATA31 EQU 0x0ffff19f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PP +CYREG_SFLASH_PP EQU 0x0ffff1a0 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PERIOD__OFFSET +CYFLD_SFLASH_PERIOD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PERIOD__SIZE +CYFLD_SFLASH_PERIOD__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PDAC__OFFSET +CYFLD_SFLASH_PDAC__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PDAC__SIZE +CYFLD_SFLASH_PDAC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_NDAC__OFFSET +CYFLD_SFLASH_NDAC__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_NDAC__SIZE +CYFLD_SFLASH_NDAC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_E +CYREG_SFLASH_E EQU 0x0ffff1a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_P +CYREG_SFLASH_P EQU 0x0ffff1a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_EA_E +CYREG_SFLASH_EA_E EQU 0x0ffff1ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_EA_P +CYREG_SFLASH_EA_P EQU 0x0ffff1b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_ES_E +CYREG_SFLASH_ES_E EQU 0x0ffff1b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_ES_P_EO +CYREG_SFLASH_ES_P_EO EQU 0x0ffff1b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_E_VCTAT +CYREG_SFLASH_E_VCTAT EQU 0x0ffff1bc + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_SLOPE__OFFSET +CYFLD_SFLASH_VCTAT_SLOPE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_SLOPE__SIZE +CYFLD_SFLASH_VCTAT_SLOPE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET +CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE +CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_ENABLE__OFFSET +CYFLD_SFLASH_VCTAT_ENABLE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_ENABLE__SIZE +CYFLD_SFLASH_VCTAT_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_P_VCTAT +CYREG_SFLASH_P_VCTAT EQU 0x0ffff1bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MARGIN +CYREG_SFLASH_MARGIN EQU 0x0ffff1be + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MDAC__OFFSET +CYFLD_SFLASH_MDAC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MDAC__SIZE +CYFLD_SFLASH_MDAC__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SPCIF_TRIM1 +CYREG_SFLASH_SPCIF_TRIM1 EQU 0x0ffff1bf + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_BDAC__OFFSET +CYFLD_SFLASH_BDAC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_BDAC__SIZE +CYFLD_SFLASH_BDAC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF0 +CYREG_SFLASH_IMO_MAXF0 EQU 0x0ffff1c0 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MAXFREQ__OFFSET +CYFLD_SFLASH_MAXFREQ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MAXFREQ__SIZE +CYFLD_SFLASH_MAXFREQ__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS0 +CYREG_SFLASH_IMO_ABS0 EQU 0x0ffff1c1 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET +CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ABS_TRIM_IMO__SIZE +CYFLD_SFLASH_ABS_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO0 +CYREG_SFLASH_IMO_TMPCO0 EQU 0x0ffff1c2 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET +CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE +CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF1 +CYREG_SFLASH_IMO_MAXF1 EQU 0x0ffff1c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS1 +CYREG_SFLASH_IMO_ABS1 EQU 0x0ffff1c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO1 +CYREG_SFLASH_IMO_TMPCO1 EQU 0x0ffff1c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF2 +CYREG_SFLASH_IMO_MAXF2 EQU 0x0ffff1c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS2 +CYREG_SFLASH_IMO_ABS2 EQU 0x0ffff1c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO2 +CYREG_SFLASH_IMO_TMPCO2 EQU 0x0ffff1c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF3 +CYREG_SFLASH_IMO_MAXF3 EQU 0x0ffff1c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS3 +CYREG_SFLASH_IMO_ABS3 EQU 0x0ffff1ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO3 +CYREG_SFLASH_IMO_TMPCO3 EQU 0x0ffff1cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS4 +CYREG_SFLASH_IMO_ABS4 EQU 0x0ffff1cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO4 +CYREG_SFLASH_IMO_TMPCO4 EQU 0x0ffff1cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM00 +CYREG_SFLASH_IMO_TRIM00 EQU 0x0ffff1d0 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_OFFSET__OFFSET +CYFLD_SFLASH_OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_OFFSET__SIZE +CYFLD_SFLASH_OFFSET__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM01 +CYREG_SFLASH_IMO_TRIM01 EQU 0x0ffff1d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM02 +CYREG_SFLASH_IMO_TRIM02 EQU 0x0ffff1d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM03 +CYREG_SFLASH_IMO_TRIM03 EQU 0x0ffff1d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM04 +CYREG_SFLASH_IMO_TRIM04 EQU 0x0ffff1d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM05 +CYREG_SFLASH_IMO_TRIM05 EQU 0x0ffff1d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM06 +CYREG_SFLASH_IMO_TRIM06 EQU 0x0ffff1d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM07 +CYREG_SFLASH_IMO_TRIM07 EQU 0x0ffff1d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM08 +CYREG_SFLASH_IMO_TRIM08 EQU 0x0ffff1d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM09 +CYREG_SFLASH_IMO_TRIM09 EQU 0x0ffff1d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM10 +CYREG_SFLASH_IMO_TRIM10 EQU 0x0ffff1da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM11 +CYREG_SFLASH_IMO_TRIM11 EQU 0x0ffff1db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM12 +CYREG_SFLASH_IMO_TRIM12 EQU 0x0ffff1dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM13 +CYREG_SFLASH_IMO_TRIM13 EQU 0x0ffff1dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM14 +CYREG_SFLASH_IMO_TRIM14 EQU 0x0ffff1de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM15 +CYREG_SFLASH_IMO_TRIM15 EQU 0x0ffff1df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM16 +CYREG_SFLASH_IMO_TRIM16 EQU 0x0ffff1e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM17 +CYREG_SFLASH_IMO_TRIM17 EQU 0x0ffff1e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM18 +CYREG_SFLASH_IMO_TRIM18 EQU 0x0ffff1e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM19 +CYREG_SFLASH_IMO_TRIM19 EQU 0x0ffff1e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM20 +CYREG_SFLASH_IMO_TRIM20 EQU 0x0ffff1e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM21 +CYREG_SFLASH_IMO_TRIM21 EQU 0x0ffff1e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM22 +CYREG_SFLASH_IMO_TRIM22 EQU 0x0ffff1e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM23 +CYREG_SFLASH_IMO_TRIM23 EQU 0x0ffff1e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM24 +CYREG_SFLASH_IMO_TRIM24 EQU 0x0ffff1e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM25 +CYREG_SFLASH_IMO_TRIM25 EQU 0x0ffff1e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM26 +CYREG_SFLASH_IMO_TRIM26 EQU 0x0ffff1ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM27 +CYREG_SFLASH_IMO_TRIM27 EQU 0x0ffff1eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM28 +CYREG_SFLASH_IMO_TRIM28 EQU 0x0ffff1ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM29 +CYREG_SFLASH_IMO_TRIM29 EQU 0x0ffff1ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM30 +CYREG_SFLASH_IMO_TRIM30 EQU 0x0ffff1ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM31 +CYREG_SFLASH_IMO_TRIM31 EQU 0x0ffff1ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM32 +CYREG_SFLASH_IMO_TRIM32 EQU 0x0ffff1f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM33 +CYREG_SFLASH_IMO_TRIM33 EQU 0x0ffff1f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM34 +CYREG_SFLASH_IMO_TRIM34 EQU 0x0ffff1f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM35 +CYREG_SFLASH_IMO_TRIM35 EQU 0x0ffff1f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM36 +CYREG_SFLASH_IMO_TRIM36 EQU 0x0ffff1f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM37 +CYREG_SFLASH_IMO_TRIM37 EQU 0x0ffff1f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM38 +CYREG_SFLASH_IMO_TRIM38 EQU 0x0ffff1f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM39 +CYREG_SFLASH_IMO_TRIM39 EQU 0x0ffff1f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM40 +CYREG_SFLASH_IMO_TRIM40 EQU 0x0ffff1f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM41 +CYREG_SFLASH_IMO_TRIM41 EQU 0x0ffff1f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM42 +CYREG_SFLASH_IMO_TRIM42 EQU 0x0ffff1fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM43 +CYREG_SFLASH_IMO_TRIM43 EQU 0x0ffff1fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM44 +CYREG_SFLASH_IMO_TRIM44 EQU 0x0ffff1fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM45 +CYREG_SFLASH_IMO_TRIM45 EQU 0x0ffff1fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CHECKSUM +CYREG_SFLASH_CHECKSUM EQU 0x0ffff1fe + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHECKSUM__OFFSET +CYFLD_SFLASH_CHECKSUM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHECKSUM__SIZE +CYFLD_SFLASH_CHECKSUM__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_SROM_BASE +CYDEV_SROM_BASE EQU 0x10000000 + ENDIF + IF :LNOT::DEF:CYDEV_SROM_SIZE +CYDEV_SROM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SROM_DATA_MBASE +CYREG_SROM_DATA_MBASE EQU 0x10000000 + ENDIF + IF :LNOT::DEF:CYREG_SROM_DATA_MSIZE +CYREG_SROM_DATA_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CPUSS_BASE +CYDEV_CPUSS_BASE EQU 0x40000000 + ENDIF + IF :LNOT::DEF:CYDEV_CPUSS_SIZE +CYDEV_CPUSS_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_CONFIG +CYREG_CPUSS_CONFIG EQU 0x40000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_VECS_IN_RAM__OFFSET +CYFLD_CPUSS_VECS_IN_RAM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_VECS_IN_RAM__SIZE +CYFLD_CPUSS_VECS_IN_RAM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET +CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE +CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SYSREQ +CYREG_CPUSS_SYSREQ EQU 0x40000004 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_COMMAND__OFFSET +CYFLD_CPUSS_COMMAND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_COMMAND__SIZE +CYFLD_CPUSS_COMMAND__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_NO_RST_OVR__OFFSET +CYFLD_CPUSS_NO_RST_OVR__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_NO_RST_OVR__SIZE +CYFLD_CPUSS_NO_RST_OVR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PRIVILEGED__OFFSET +CYFLD_CPUSS_PRIVILEGED__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PRIVILEGED__SIZE +CYFLD_CPUSS_PRIVILEGED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET +CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_ACCESS_EN__SIZE +CYFLD_CPUSS_ROM_ACCESS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_HMASTER__OFFSET +CYFLD_CPUSS_HMASTER__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_HMASTER__SIZE +CYFLD_CPUSS_HMASTER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSREQ__OFFSET +CYFLD_CPUSS_SYSREQ__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSREQ__SIZE +CYFLD_CPUSS_SYSREQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SYSARG +CYREG_CPUSS_SYSARG EQU 0x40000008 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ARG32__OFFSET +CYFLD_CPUSS_ARG32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ARG32__SIZE +CYFLD_CPUSS_ARG32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PROTECTION +CYREG_CPUSS_PROTECTION EQU 0x4000000c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT__OFFSET +CYFLD_CPUSS_PROT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT__SIZE +CYFLD_CPUSS_PROT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_VIRGIN +CYVAL_CPUSS_PROT_VIRGIN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_OPEN +CYVAL_CPUSS_PROT_OPEN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_PROTECTED +CYVAL_CPUSS_PROT_PROTECTED EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_KILL +CYVAL_CPUSS_PROT_KILL EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_BOOT +CYVAL_CPUSS_PROT_BOOT EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT_LOCK__OFFSET +CYFLD_CPUSS_PROT_LOCK__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT_LOCK__SIZE +CYFLD_CPUSS_PROT_LOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_ROM +CYREG_CPUSS_PRIV_ROM EQU 0x40000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_LIMIT__OFFSET +CYFLD_CPUSS_ROM_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_LIMIT__SIZE +CYFLD_CPUSS_ROM_LIMIT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_RAM +CYREG_CPUSS_PRIV_RAM EQU 0x40000014 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_LIMIT__OFFSET +CYFLD_CPUSS_RAM_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_LIMIT__SIZE +CYFLD_CPUSS_RAM_LIMIT__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_FLASH +CYREG_CPUSS_PRIV_FLASH EQU 0x40000018 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_LIMIT__OFFSET +CYFLD_CPUSS_FLASH_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_LIMIT__SIZE +CYFLD_CPUSS_FLASH_LIMIT__SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_WOUNDING +CYREG_CPUSS_WOUNDING EQU 0x4000001c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_SIZE__OFFSET +CYFLD_CPUSS_RAM_SIZE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_SIZE__SIZE +CYFLD_CPUSS_RAM_SIZE__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__OFFSET +CYFLD_CPUSS_RAM_WOUND__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__SIZE +CYFLD_CPUSS_RAM_WOUND__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_FULL +CYVAL_CPUSS_RAM_WOUND_FULL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__OFFSET +CYFLD_CPUSS_FLASH_WOUND__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__SIZE +CYFLD_CPUSS_FLASH_WOUND__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_FULL +CYVAL_CPUSS_FLASH_WOUND_FULL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_INTR_SELECT +CYREG_CPUSS_INTR_SELECT EQU 0x40000020 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SELECT32__OFFSET +CYFLD_CPUSS_SELECT32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SELECT32__SIZE +CYFLD_CPUSS_SELECT32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_HSIOM_BASE +CYDEV_HSIOM_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_HSIOM_SIZE +CYDEV_HSIOM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL0 +CYREG_HSIOM_PORT_SEL0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL0__OFFSET +CYFLD_HSIOM_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL0__SIZE +CYFLD_HSIOM_SEL0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_GPIO +CYVAL_HSIOM_SEL0_GPIO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_GPIO_DSI +CYVAL_HSIOM_SEL0_GPIO_DSI EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DSI_DSI +CYVAL_HSIOM_SEL0_DSI_DSI EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DSI_GPIO +CYVAL_HSIOM_SEL0_DSI_GPIO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_CSD_SENSE +CYVAL_HSIOM_SEL0_CSD_SENSE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_CSD_SHIELD +CYVAL_HSIOM_SEL0_CSD_SHIELD EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_AMUXA +CYVAL_HSIOM_SEL0_AMUXA EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_AMUXB +CYVAL_HSIOM_SEL0_AMUXB EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_0 +CYVAL_HSIOM_SEL0_ACT_0 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_1 +CYVAL_HSIOM_SEL0_ACT_1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_2 +CYVAL_HSIOM_SEL0_ACT_2 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_3 +CYVAL_HSIOM_SEL0_ACT_3 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_LCD_COM +CYVAL_HSIOM_SEL0_LCD_COM EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_LCD_SEG +CYVAL_HSIOM_SEL0_LCD_SEG EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DPSLP_0 +CYVAL_HSIOM_SEL0_DPSLP_0 EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DPSLP_1 +CYVAL_HSIOM_SEL0_DPSLP_1 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_COMP1_INP +CYVAL_HSIOM_SEL0_COMP1_INP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 +CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL1__OFFSET +CYFLD_HSIOM_SEL1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL1__SIZE +CYFLD_HSIOM_SEL1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL1_COMP1_INN +CYVAL_HSIOM_SEL1_COMP1_INN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 +CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL2__OFFSET +CYFLD_HSIOM_SEL2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL2__SIZE +CYFLD_HSIOM_SEL2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL2_COMP2_INP +CYVAL_HSIOM_SEL2_COMP2_INP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 +CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL3__OFFSET +CYFLD_HSIOM_SEL3__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL3__SIZE +CYFLD_HSIOM_SEL3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL3_COMP2_INN +CYVAL_HSIOM_SEL3_COMP2_INN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL4__OFFSET +CYFLD_HSIOM_SEL4__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL4__SIZE +CYFLD_HSIOM_SEL4__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL4_SCB1_UART_RX +CYVAL_HSIOM_SEL4_SCB1_UART_RX EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL4_SCB1_I2C_SCL +CYVAL_HSIOM_SEL4_SCB1_I2C_SCL EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI +CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL5__OFFSET +CYFLD_HSIOM_SEL5__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL5__SIZE +CYFLD_HSIOM_SEL5__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL5_SCB1_UART_TX +CYVAL_HSIOM_SEL5_SCB1_UART_TX EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL5_SCB1_I2C_SDA +CYVAL_HSIOM_SEL5_SCB1_I2C_SDA EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL5_SCB1_SPI_MISO +CYVAL_HSIOM_SEL5_SCB1_SPI_MISO EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL6__OFFSET +CYFLD_HSIOM_SEL6__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL6__SIZE +CYFLD_HSIOM_SEL6__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL6_EXT_CLK +CYVAL_HSIOM_SEL6_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL6_SCB1_SPI_CLK +CYVAL_HSIOM_SEL6_SCB1_SPI_CLK EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL7__OFFSET +CYFLD_HSIOM_SEL7__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL7__SIZE +CYFLD_HSIOM_SEL7__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL7_WAKEUP +CYVAL_HSIOM_SEL7_WAKEUP EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 +CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL1 +CYREG_HSIOM_PORT_SEL1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL2 +CYREG_HSIOM_PORT_SEL2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL3 +CYREG_HSIOM_PORT_SEL3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL4 +CYREG_HSIOM_PORT_SEL4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_CLK_BASE +CYDEV_CLK_BASE EQU 0x40020000 + ENDIF + IF :LNOT::DEF:CYDEV_CLK_SIZE +CYDEV_CLK_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_A00 +CYREG_CLK_DIVIDER_A00 EQU 0x40020000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_A__OFFSET +CYFLD_CLK_DIVIDER_A__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_A__SIZE +CYFLD_CLK_DIVIDER_A__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_A__OFFSET +CYFLD_CLK_ENABLE_A__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_A__SIZE +CYFLD_CLK_ENABLE_A__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_A01 +CYREG_CLK_DIVIDER_A01 EQU 0x40020004 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_A02 +CYREG_CLK_DIVIDER_A02 EQU 0x40020008 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_B00 +CYREG_CLK_DIVIDER_B00 EQU 0x40020040 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_B__OFFSET +CYFLD_CLK_DIVIDER_B__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_B__SIZE +CYFLD_CLK_DIVIDER_B__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_A_B__OFFSET +CYFLD_CLK_CASCADE_A_B__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_A_B__SIZE +CYFLD_CLK_CASCADE_A_B__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_B__OFFSET +CYFLD_CLK_ENABLE_B__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_B__SIZE +CYFLD_CLK_ENABLE_B__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_B01 +CYREG_CLK_DIVIDER_B01 EQU 0x40020044 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_B02 +CYREG_CLK_DIVIDER_B02 EQU 0x40020048 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_C00 +CYREG_CLK_DIVIDER_C00 EQU 0x40020080 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_C__OFFSET +CYFLD_CLK_DIVIDER_C__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_C__SIZE +CYFLD_CLK_DIVIDER_C__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_B_C__OFFSET +CYFLD_CLK_CASCADE_B_C__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_B_C__SIZE +CYFLD_CLK_CASCADE_B_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_C__OFFSET +CYFLD_CLK_ENABLE_C__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_C__SIZE +CYFLD_CLK_ENABLE_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_C01 +CYREG_CLK_DIVIDER_C01 EQU 0x40020084 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_C02 +CYREG_CLK_DIVIDER_C02 EQU 0x40020088 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_FRAC_A00 +CYREG_CLK_DIVIDER_FRAC_A00 EQU 0x40020100 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_A__OFFSET +CYFLD_CLK_FRAC_A__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_A__SIZE +CYFLD_CLK_FRAC_A__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_FRAC_B00 +CYREG_CLK_DIVIDER_FRAC_B00 EQU 0x40020140 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_B__OFFSET +CYFLD_CLK_FRAC_B__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_B__SIZE +CYFLD_CLK_FRAC_B__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_FRAC_C00 +CYREG_CLK_DIVIDER_FRAC_C00 EQU 0x40020180 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_C__OFFSET +CYFLD_CLK_FRAC_C__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_C__SIZE +CYFLD_CLK_FRAC_C__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT00 +CYREG_CLK_SELECT00 EQU 0x40020200 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_N__OFFSET +CYFLD_CLK_DIVIDER_N__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_N__SIZE +CYFLD_CLK_DIVIDER_N__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_ABC__OFFSET +CYFLD_CLK_DIVIDER_ABC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_ABC__SIZE +CYFLD_CLK_DIVIDER_ABC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_OFF +CYVAL_CLK_DIVIDER_ABC_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_A +CYVAL_CLK_DIVIDER_ABC_A EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_B +CYVAL_CLK_DIVIDER_ABC_B EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_C +CYVAL_CLK_DIVIDER_ABC_C EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT01 +CYREG_CLK_SELECT01 EQU 0x40020204 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT02 +CYREG_CLK_SELECT02 EQU 0x40020208 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT03 +CYREG_CLK_SELECT03 EQU 0x4002020c + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT04 +CYREG_CLK_SELECT04 EQU 0x40020210 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT05 +CYREG_CLK_SELECT05 EQU 0x40020214 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT06 +CYREG_CLK_SELECT06 EQU 0x40020218 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT07 +CYREG_CLK_SELECT07 EQU 0x4002021c + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT08 +CYREG_CLK_SELECT08 EQU 0x40020220 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT09 +CYREG_CLK_SELECT09 EQU 0x40020224 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT10 +CYREG_CLK_SELECT10 EQU 0x40020228 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT11 +CYREG_CLK_SELECT11 EQU 0x4002022c + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT12 +CYREG_CLK_SELECT12 EQU 0x40020230 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT13 +CYREG_CLK_SELECT13 EQU 0x40020234 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT14 +CYREG_CLK_SELECT14 EQU 0x40020238 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT15 +CYREG_CLK_SELECT15 EQU 0x4002023c + ENDIF + IF :LNOT::DEF:CYDEV_TST_BASE +CYDEV_TST_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_TST_SIZE +CYDEV_TST_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_TST_CTRL +CYREG_TST_CTRL EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_ACCESS__OFFSET +CYFLD_TST_DAP_NO_ACCESS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_ACCESS__SIZE +CYFLD_TST_DAP_NO_ACCESS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_DEBUG__OFFSET +CYFLD_TST_DAP_NO_DEBUG__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_DEBUG__SIZE +CYFLD_TST_DAP_NO_DEBUG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SWD_CONNECTED__OFFSET +CYFLD_TST_SWD_CONNECTED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SWD_CONNECTED__SIZE +CYFLD_TST_SWD_CONNECTED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_RESET_EN_N__OFFSET +CYFLD_TST_TEST_RESET_EN_N__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_RESET_EN_N__SIZE +CYFLD_TST_TEST_RESET_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SET_EN_N__OFFSET +CYFLD_TST_TEST_SET_EN_N__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SET_EN_N__SIZE +CYFLD_TST_TEST_SET_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_ICG_EN_N__OFFSET +CYFLD_TST_TEST_ICG_EN_N__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_ICG_EN_N__SIZE +CYFLD_TST_TEST_ICG_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET +CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_1_EN_N__SIZE +CYFLD_TST_TEST_OCC0_1_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET +CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_2_EN_N__SIZE +CYFLD_TST_TEST_OCC0_2_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET +CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPISOLATE_EN__SIZE +CYFLD_TST_TEST_SLPISOLATE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET +CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSISOLATE_EN__SIZE +CYFLD_TST_TEST_SYSISOLATE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET +CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPRETAIN_EN__SIZE +CYFLD_TST_TEST_SLPRETAIN_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET +CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSRETAIN_EN__SIZE +CYFLD_TST_TEST_SYSRETAIN_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE1_EN__OFFSET +CYFLD_TST_TEST_SPARE1_EN__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE1_EN__SIZE +CYFLD_TST_TEST_SPARE1_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE2_EN__OFFSET +CYFLD_TST_TEST_SPARE2_EN__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE2_EN__SIZE +CYFLD_TST_TEST_SPARE2_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET +CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_OCC_OBSERVE__SIZE +CYFLD_TST_SCAN_OCC_OBSERVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF1__OFFSET +CYFLD_TST_SCAN_TRF1__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF1__SIZE +CYFLD_TST_SCAN_TRF1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF__OFFSET +CYFLD_TST_SCAN_TRF__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF__SIZE +CYFLD_TST_SCAN_TRF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_IDDQ__OFFSET +CYFLD_TST_SCAN_IDDQ__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_IDDQ__SIZE +CYFLD_TST_SCAN_IDDQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_COMPRESS__OFFSET +CYFLD_TST_SCAN_COMPRESS__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_COMPRESS__SIZE +CYFLD_TST_SCAN_COMPRESS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_MODE__OFFSET +CYFLD_TST_SCAN_MODE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_MODE__SIZE +CYFLD_TST_SCAN_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_PTM_MODE_EN__OFFSET +CYFLD_TST_PTM_MODE_EN__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_TST_PTM_MODE_EN__SIZE +CYFLD_TST_PTM_MODE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_ADFT_CTRL +CYREG_TST_ADFT_CTRL EQU 0x40030004 + ENDIF + IF :LNOT::DEF:CYFLD_TST_ENABLE__OFFSET +CYFLD_TST_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TST_ENABLE__SIZE +CYFLD_TST_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_DDFT_CTRL +CYREG_TST_DDFT_CTRL EQU 0x40030008 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL1__OFFSET +CYFLD_TST_DFT_SEL1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL1__SIZE +CYFLD_TST_DFT_SEL1__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_VSS +CYVAL_TST_DFT_SEL1_VSS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_CLK1 +CYVAL_TST_DFT_SEL1_CLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_CLK2 +CYVAL_TST_DFT_SEL1_CLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_PWR1 +CYVAL_TST_DFT_SEL1_PWR1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_PWR2 +CYVAL_TST_DFT_SEL1_PWR2 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_VMON +CYVAL_TST_DFT_SEL1_VMON EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS_VDDA_OK +CYVAL_TST_DFT_SEL1_TSS_VDDA_OK EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_ADFT_TRIP1 +CYVAL_TST_DFT_SEL1_ADFT_TRIP1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_ADFT_TRIP2 +CYVAL_TST_DFT_SEL1_ADFT_TRIP2 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS1 +CYVAL_TST_DFT_SEL1_TSS1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS2 +CYVAL_TST_DFT_SEL1_TSS2 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS3 +CYVAL_TST_DFT_SEL1_TSS3 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS4 +CYVAL_TST_DFT_SEL1_TSS4 EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS +CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI +CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL2__OFFSET +CYFLD_TST_DFT_SEL2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL2__SIZE +CYFLD_TST_DFT_SEL2__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_VSS +CYVAL_TST_DFT_SEL2_VSS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_CLK1 +CYVAL_TST_DFT_SEL2_CLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_CLK2 +CYVAL_TST_DFT_SEL2_CLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_PWR1 +CYVAL_TST_DFT_SEL2_PWR1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_PWR2 +CYVAL_TST_DFT_SEL2_PWR2 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_VMON +CYVAL_TST_DFT_SEL2_VMON EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS_VDDA_OK +CYVAL_TST_DFT_SEL2_TSS_VDDA_OK EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_ADFT_TRIP1 +CYVAL_TST_DFT_SEL2_ADFT_TRIP1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_ADFT_TRIP2 +CYVAL_TST_DFT_SEL2_ADFT_TRIP2 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS1 +CYVAL_TST_DFT_SEL2_TSS1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS2 +CYVAL_TST_DFT_SEL2_TSS2 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS3 +CYVAL_TST_DFT_SEL2_TSS3 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS4 +CYVAL_TST_DFT_SEL2_TSS4 EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS +CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI +CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_TST_EDGE__OFFSET +CYFLD_TST_EDGE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_TST_EDGE__SIZE +CYFLD_TST_EDGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_EDGE_POSEDGE +CYVAL_TST_EDGE_POSEDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_EDGE_NEGEDGE +CYVAL_TST_EDGE_NEGEDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DIVIDE__OFFSET +CYFLD_TST_DIVIDE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_TST_DIVIDE__SIZE +CYFLD_TST_DIVIDE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIRECT +CYVAL_TST_DIVIDE_DIRECT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIV_BY_2 +CYVAL_TST_DIVIDE_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIV_BY_4 +CYVAL_TST_DIVIDE_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIV_BY_8 +CYVAL_TST_DIVIDE_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TST_MODE +CYREG_TST_MODE EQU 0x40030014 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_MODE__OFFSET +CYFLD_TST_TEST_MODE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_MODE__SIZE +CYFLD_TST_TEST_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_TRIM_CNTR1 +CYREG_TST_TRIM_CNTR1 EQU 0x40030018 + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER__OFFSET +CYFLD_TST_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER__SIZE +CYFLD_TST_COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER_DONE__OFFSET +CYFLD_TST_COUNTER_DONE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER_DONE__SIZE +CYFLD_TST_COUNTER_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_TRIM_CNTR2 +CYREG_TST_TRIM_CNTR2 EQU 0x4003001c + ENDIF + IF :LNOT::DEF:CYDEV_PRT0_BASE +CYDEV_PRT0_BASE EQU 0x40040000 + ENDIF + IF :LNOT::DEF:CYDEV_PRT0_SIZE +CYDEV_PRT0_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40040000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DATAREG__OFFSET +CYFLD_PRT_DATAREG__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DATAREG__SIZE +CYFLD_PRT_DATAREG__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40040004 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE__OFFSET +CYFLD_PRT_PINSTATE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE__SIZE +CYFLD_PRT_PINSTATE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE_FLT__OFFSET +CYFLD_PRT_PINSTATE_FLT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE_FLT__SIZE +CYFLD_PRT_PINSTATE_FLT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC +CYREG_PRT0_PC EQU 0x40040008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DM__OFFSET +CYFLD_PRT_DM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DM__SIZE +CYFLD_PRT_DM__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_OFF +CYVAL_PRT_DM_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_INPUT +CYVAL_PRT_DM_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_0_PU +CYVAL_PRT_DM_0_PU EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_PD_1 +CYVAL_PRT_DM_PD_1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_0_Z +CYVAL_PRT_DM_0_Z EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_Z_1 +CYVAL_PRT_DM_Z_1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_0_1 +CYVAL_PRT_DM_0_1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_PD_PU +CYVAL_PRT_DM_PD_PU EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_VTRIP_SEL__OFFSET +CYFLD_PRT_VTRIP_SEL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_VTRIP_SEL__SIZE +CYFLD_PRT_VTRIP_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_SLOW__OFFSET +CYFLD_PRT_SLOW__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_SLOW__SIZE +CYFLD_PRT_SLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INTCFG +CYREG_PRT0_INTCFG EQU 0x4004000c + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE__OFFSET +CYFLD_PRT_INTTYPE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE__SIZE +CYFLD_PRT_INTTYPE__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_DISABLE +CYVAL_PRT_INTTYPE_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_RISING +CYVAL_PRT_INTTYPE_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FALLING +CYVAL_PRT_INTTYPE_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_BOTH +CYVAL_PRT_INTTYPE_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE_FLT__OFFSET +CYFLD_PRT_INTTYPE_FLT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE_FLT__SIZE +CYFLD_PRT_INTTYPE_FLT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_DISABLE +CYVAL_PRT_INTTYPE_FLT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_RISING +CYVAL_PRT_INTTYPE_FLT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_FALLING +CYVAL_PRT_INTTYPE_FLT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_BOTH +CYVAL_PRT_INTTYPE_FLT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_FLT_SELECT__OFFSET +CYFLD_PRT_FLT_SELECT__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_FLT_SELECT__SIZE +CYFLD_PRT_FLT_SELECT__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INTSTAT +CYREG_PRT0_INTSTAT EQU 0x40040010 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT__OFFSET +CYFLD_PRT_INTSTAT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT__SIZE +CYFLD_PRT_INTSTAT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT_FLT__OFFSET +CYFLD_PRT_INTSTAT_FLT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT_FLT__SIZE +CYFLD_PRT_INTSTAT_FLT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS__OFFSET +CYFLD_PRT_PS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS__SIZE +CYFLD_PRT_PS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS_FLT__OFFSET +CYFLD_PRT_PS_FLT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS_FLT__SIZE +CYFLD_PRT_PS_FLT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40040018 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INP_DIS__OFFSET +CYFLD_PRT_INP_DIS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INP_DIS__SIZE +CYFLD_PRT_INP_DIS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PRT1_BASE +CYDEV_PRT1_BASE EQU 0x40040100 + ENDIF + IF :LNOT::DEF:CYDEV_PRT1_SIZE +CYDEV_PRT1_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40040100 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40040104 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC +CYREG_PRT1_PC EQU 0x40040108 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INTCFG +CYREG_PRT1_INTCFG EQU 0x4004010c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INTSTAT +CYREG_PRT1_INTSTAT EQU 0x40040110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x40040118 + ENDIF + IF :LNOT::DEF:CYDEV_PRT2_BASE +CYDEV_PRT2_BASE EQU 0x40040200 + ENDIF + IF :LNOT::DEF:CYDEV_PRT2_SIZE +CYDEV_PRT2_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40040200 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40040204 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC +CYREG_PRT2_PC EQU 0x40040208 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INTCFG +CYREG_PRT2_INTCFG EQU 0x4004020c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INTSTAT +CYREG_PRT2_INTSTAT EQU 0x40040210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40040218 + ENDIF + IF :LNOT::DEF:CYDEV_PRT3_BASE +CYDEV_PRT3_BASE EQU 0x40040300 + ENDIF + IF :LNOT::DEF:CYDEV_PRT3_SIZE +CYDEV_PRT3_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40040300 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40040304 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC +CYREG_PRT3_PC EQU 0x40040308 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INTCFG +CYREG_PRT3_INTCFG EQU 0x4004030c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INTSTAT +CYREG_PRT3_INTSTAT EQU 0x40040310 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x40040318 + ENDIF + IF :LNOT::DEF:CYDEV_PRT4_BASE +CYDEV_PRT4_BASE EQU 0x40040400 + ENDIF + IF :LNOT::DEF:CYDEV_PRT4_SIZE +CYDEV_PRT4_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40040400 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40040404 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC +CYREG_PRT4_PC EQU 0x40040408 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INTCFG +CYREG_PRT4_INTCFG EQU 0x4004040c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INTSTAT +CYREG_PRT4_INTSTAT EQU 0x40040410 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40040418 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_BASE +CYDEV_TCPWM_BASE EQU 0x40050000 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_SIZE +CYDEV_TCPWM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CTRL +CYREG_TCPWM_CTRL EQU 0x40050000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_ENABLED__OFFSET +CYFLD_TCPWM_COUNTER_ENABLED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_ENABLED__SIZE +CYFLD_TCPWM_COUNTER_ENABLED__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CMD +CYREG_TCPWM_CMD EQU 0x40050008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET +CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_CAPTURE__SIZE +CYFLD_TCPWM_COUNTER_CAPTURE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_RELOAD__OFFSET +CYFLD_TCPWM_COUNTER_RELOAD__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_RELOAD__SIZE +CYFLD_TCPWM_COUNTER_RELOAD__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_STOP__OFFSET +CYFLD_TCPWM_COUNTER_STOP__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_STOP__SIZE +CYFLD_TCPWM_COUNTER_STOP__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_START__OFFSET +CYFLD_TCPWM_COUNTER_START__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_START__SIZE +CYFLD_TCPWM_COUNTER_START__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_INTR_CAUSE +CYREG_TCPWM_INTR_CAUSE EQU 0x4005000c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_INT__OFFSET +CYFLD_TCPWM_COUNTER_INT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_INT__SIZE +CYFLD_TCPWM_COUNTER_INT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT0_BASE +CYDEV_TCPWM_CNT0_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT0_SIZE +CYDEV_TCPWM_CNT0_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CTRL +CYREG_TCPWM_CNT0_CTRL EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET +CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE +CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET +CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE +CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET +CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE +CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET +CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE +CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_GENERIC__OFFSET +CYFLD_TCPWM_CNT_GENERIC__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_GENERIC__SIZE +CYFLD_TCPWM_CNT_GENERIC__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY1 +CYVAL_TCPWM_CNT_GENERIC_DIVBY1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY2 +CYVAL_TCPWM_CNT_GENERIC_DIVBY2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY4 +CYVAL_TCPWM_CNT_GENERIC_DIVBY4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY8 +CYVAL_TCPWM_CNT_GENERIC_DIVBY8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY16 +CYVAL_TCPWM_CNT_GENERIC_DIVBY16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY32 +CYVAL_TCPWM_CNT_GENERIC_DIVBY32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY64 +CYVAL_TCPWM_CNT_GENERIC_DIVBY64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY128 +CYVAL_TCPWM_CNT_GENERIC_DIVBY128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET +CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE +CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET +CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_ONE_SHOT__SIZE +CYFLD_TCPWM_CNT_ONE_SHOT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET +CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE +CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT +CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT +CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_MODE__OFFSET +CYFLD_TCPWM_CNT_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_MODE__SIZE +CYFLD_TCPWM_CNT_MODE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_TIMER +CYVAL_TCPWM_CNT_MODE_TIMER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_CAPTURE +CYVAL_TCPWM_CNT_MODE_CAPTURE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_QUAD +CYVAL_TCPWM_CNT_MODE_QUAD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM +CYVAL_TCPWM_CNT_MODE_PWM EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM_DT +CYVAL_TCPWM_CNT_MODE_PWM_DT EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM_PR +CYVAL_TCPWM_CNT_MODE_PWM_PR EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_STATUS +CYREG_TCPWM_CNT0_STATUS EQU 0x40050104 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_DOWN__OFFSET +CYFLD_TCPWM_CNT_DOWN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_DOWN__SIZE +CYFLD_TCPWM_CNT_DOWN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RUNNING__OFFSET +CYFLD_TCPWM_CNT_RUNNING__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RUNNING__SIZE +CYFLD_TCPWM_CNT_RUNNING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_COUNTER +CYREG_TCPWM_CNT0_COUNTER EQU 0x40050108 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNTER__OFFSET +CYFLD_TCPWM_CNT_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNTER__SIZE +CYFLD_TCPWM_CNT_COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CC +CYREG_TCPWM_CNT0_CC EQU 0x4005010c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC__OFFSET +CYFLD_TCPWM_CNT_CC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC__SIZE +CYFLD_TCPWM_CNT_CC__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CC_BUFF +CYREG_TCPWM_CNT0_CC_BUFF EQU 0x40050110 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_PERIOD +CYREG_TCPWM_CNT0_PERIOD EQU 0x40050114 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PERIOD__OFFSET +CYFLD_TCPWM_CNT_PERIOD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PERIOD__SIZE +CYFLD_TCPWM_CNT_PERIOD__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_PERIOD_BUFF +CYREG_TCPWM_CNT0_PERIOD_BUFF EQU 0x40050118 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL0 +CYREG_TCPWM_CNT0_TR_CTRL0 EQU 0x40050120 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET +CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE +CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET +CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_SEL__SIZE +CYFLD_TCPWM_CNT_COUNT_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET +CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE +CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_SEL__OFFSET +CYFLD_TCPWM_CNT_STOP_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_SEL__SIZE +CYFLD_TCPWM_CNT_STOP_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_SEL__OFFSET +CYFLD_TCPWM_CNT_START_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_SEL__SIZE +CYFLD_TCPWM_CNT_START_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL1 +CYREG_TCPWM_CNT0_TR_CTRL1 EQU 0x40050124 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET +CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE +CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET +CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE +CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET +CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE +CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET +CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_EDGE__SIZE +CYFLD_TCPWM_CNT_STOP_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_EDGE__OFFSET +CYFLD_TCPWM_CNT_START_EDGE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_EDGE__SIZE +CYFLD_TCPWM_CNT_START_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL2 +CYREG_TCPWM_CNT0_TR_CTRL2 EQU 0x40050128 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET +CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE +CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET +CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR +CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT +CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET +CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE +CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET +CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR +CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT +CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET +CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE +CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR +CYREG_TCPWM_CNT0_INTR EQU 0x40050130 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_TC__OFFSET +CYFLD_TCPWM_CNT_TC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_TC__SIZE +CYFLD_TCPWM_CNT_TC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH__OFFSET +CYFLD_TCPWM_CNT_CC_MATCH__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH__SIZE +CYFLD_TCPWM_CNT_CC_MATCH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_SET +CYREG_TCPWM_CNT0_INTR_SET EQU 0x40050134 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_MASK +CYREG_TCPWM_CNT0_INTR_MASK EQU 0x40050138 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_MASKED +CYREG_TCPWM_CNT0_INTR_MASKED EQU 0x4005013c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT1_BASE +CYDEV_TCPWM_CNT1_BASE EQU 0x40050140 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT1_SIZE +CYDEV_TCPWM_CNT1_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CTRL +CYREG_TCPWM_CNT1_CTRL EQU 0x40050140 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_STATUS +CYREG_TCPWM_CNT1_STATUS EQU 0x40050144 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_COUNTER +CYREG_TCPWM_CNT1_COUNTER EQU 0x40050148 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CC +CYREG_TCPWM_CNT1_CC EQU 0x4005014c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CC_BUFF +CYREG_TCPWM_CNT1_CC_BUFF EQU 0x40050150 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_PERIOD +CYREG_TCPWM_CNT1_PERIOD EQU 0x40050154 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_PERIOD_BUFF +CYREG_TCPWM_CNT1_PERIOD_BUFF EQU 0x40050158 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL0 +CYREG_TCPWM_CNT1_TR_CTRL0 EQU 0x40050160 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL1 +CYREG_TCPWM_CNT1_TR_CTRL1 EQU 0x40050164 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL2 +CYREG_TCPWM_CNT1_TR_CTRL2 EQU 0x40050168 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR +CYREG_TCPWM_CNT1_INTR EQU 0x40050170 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_SET +CYREG_TCPWM_CNT1_INTR_SET EQU 0x40050174 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_MASK +CYREG_TCPWM_CNT1_INTR_MASK EQU 0x40050178 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_MASKED +CYREG_TCPWM_CNT1_INTR_MASKED EQU 0x4005017c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT2_BASE +CYDEV_TCPWM_CNT2_BASE EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT2_SIZE +CYDEV_TCPWM_CNT2_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CTRL +CYREG_TCPWM_CNT2_CTRL EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_STATUS +CYREG_TCPWM_CNT2_STATUS EQU 0x40050184 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_COUNTER +CYREG_TCPWM_CNT2_COUNTER EQU 0x40050188 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CC +CYREG_TCPWM_CNT2_CC EQU 0x4005018c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CC_BUFF +CYREG_TCPWM_CNT2_CC_BUFF EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_PERIOD +CYREG_TCPWM_CNT2_PERIOD EQU 0x40050194 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_PERIOD_BUFF +CYREG_TCPWM_CNT2_PERIOD_BUFF EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL0 +CYREG_TCPWM_CNT2_TR_CTRL0 EQU 0x400501a0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL1 +CYREG_TCPWM_CNT2_TR_CTRL1 EQU 0x400501a4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL2 +CYREG_TCPWM_CNT2_TR_CTRL2 EQU 0x400501a8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR +CYREG_TCPWM_CNT2_INTR EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_SET +CYREG_TCPWM_CNT2_INTR_SET EQU 0x400501b4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_MASK +CYREG_TCPWM_CNT2_INTR_MASK EQU 0x400501b8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_MASKED +CYREG_TCPWM_CNT2_INTR_MASKED EQU 0x400501bc + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT3_BASE +CYDEV_TCPWM_CNT3_BASE EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT3_SIZE +CYDEV_TCPWM_CNT3_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CTRL +CYREG_TCPWM_CNT3_CTRL EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_STATUS +CYREG_TCPWM_CNT3_STATUS EQU 0x400501c4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_COUNTER +CYREG_TCPWM_CNT3_COUNTER EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CC +CYREG_TCPWM_CNT3_CC EQU 0x400501cc + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CC_BUFF +CYREG_TCPWM_CNT3_CC_BUFF EQU 0x400501d0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_PERIOD +CYREG_TCPWM_CNT3_PERIOD EQU 0x400501d4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_PERIOD_BUFF +CYREG_TCPWM_CNT3_PERIOD_BUFF EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL0 +CYREG_TCPWM_CNT3_TR_CTRL0 EQU 0x400501e0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL1 +CYREG_TCPWM_CNT3_TR_CTRL1 EQU 0x400501e4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL2 +CYREG_TCPWM_CNT3_TR_CTRL2 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR +CYREG_TCPWM_CNT3_INTR EQU 0x400501f0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_SET +CYREG_TCPWM_CNT3_INTR_SET EQU 0x400501f4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_MASK +CYREG_TCPWM_CNT3_INTR_MASK EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_MASKED +CYREG_TCPWM_CNT3_INTR_MASKED EQU 0x400501fc + ENDIF + IF :LNOT::DEF:CYDEV_SCB0_BASE +CYDEV_SCB0_BASE EQU 0x40060000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB0_SIZE +CYDEV_SCB0_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_CTRL +CYREG_SCB0_CTRL EQU 0x40060000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVS__OFFSET +CYFLD_SCB_OVS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVS__SIZE +CYFLD_SCB_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_AM_MODE__OFFSET +CYFLD_SCB_EC_AM_MODE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_AM_MODE__SIZE +CYFLD_SCB_EC_AM_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_OP_MODE__OFFSET +CYFLD_SCB_EC_OP_MODE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_OP_MODE__SIZE +CYFLD_SCB_EC_OP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_MODE__OFFSET +CYFLD_SCB_EZ_MODE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_MODE__SIZE +CYFLD_SCB_EZ_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR_ACCEPT__OFFSET +CYFLD_SCB_ADDR_ACCEPT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR_ACCEPT__SIZE +CYFLD_SCB_ADDR_ACCEPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCK__OFFSET +CYFLD_SCB_BLOCK__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCK__SIZE +CYFLD_SCB_BLOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MODE__OFFSET +CYFLD_SCB_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MODE__SIZE +CYFLD_SCB_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_I2C +CYVAL_SCB_MODE_I2C EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_SPI +CYVAL_SCB_MODE_SPI EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_UART +CYVAL_SCB_MODE_UART EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ENABLED__OFFSET +CYFLD_SCB_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ENABLED__SIZE +CYFLD_SCB_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_STATUS +CYREG_SCB0_STATUS EQU 0x40060004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_BUSY__OFFSET +CYFLD_SCB_EC_BUSY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_BUSY__SIZE +CYFLD_SCB_EC_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_SPI_CTRL +CYREG_SCB0_SPI_CTRL EQU 0x40060020 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CONTINUOUS__OFFSET +CYFLD_SCB_CONTINUOUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CONTINUOUS__SIZE +CYFLD_SCB_CONTINUOUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SELECT_PRECEDE__OFFSET +CYFLD_SCB_SELECT_PRECEDE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SELECT_PRECEDE__SIZE +CYFLD_SCB_SELECT_PRECEDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPHA__OFFSET +CYFLD_SCB_CPHA__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPHA__SIZE +CYFLD_SCB_CPHA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPOL__OFFSET +CYFLD_SCB_CPOL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPOL__SIZE +CYFLD_SCB_CPOL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET +CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LATE_MISO_SAMPLE__SIZE +CYFLD_SCB_LATE_MISO_SAMPLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOOPBACK__OFFSET +CYFLD_SCB_LOOPBACK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOOPBACK__SIZE +CYFLD_SCB_LOOPBACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_SELECT__OFFSET +CYFLD_SCB_SLAVE_SELECT__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_SELECT__SIZE +CYFLD_SCB_SLAVE_SELECT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASTER_MODE__OFFSET +CYFLD_SCB_MASTER_MODE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASTER_MODE__SIZE +CYFLD_SCB_MASTER_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_SPI_STATUS +CYREG_SCB0_SPI_STATUS EQU 0x40060024 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BUS_BUSY__OFFSET +CYFLD_SCB_BUS_BUSY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BUS_BUSY__SIZE +CYFLD_SCB_BUS_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_ADDR__OFFSET +CYFLD_SCB_EZ_ADDR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_ADDR__SIZE +CYFLD_SCB_EZ_ADDR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_CTRL +CYREG_SCB0_UART_CTRL EQU 0x40060040 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_TX_CTRL +CYREG_SCB0_UART_TX_CTRL EQU 0x40060044 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_STOP_BITS__OFFSET +CYFLD_SCB_STOP_BITS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_STOP_BITS__SIZE +CYFLD_SCB_STOP_BITS__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY__OFFSET +CYFLD_SCB_PARITY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY__SIZE +CYFLD_SCB_PARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ENABLED__OFFSET +CYFLD_SCB_PARITY_ENABLED__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ENABLED__SIZE +CYFLD_SCB_PARITY_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RETRY_ON_NACK__OFFSET +CYFLD_SCB_RETRY_ON_NACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RETRY_ON_NACK__SIZE +CYFLD_SCB_RETRY_ON_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_RX_CTRL +CYREG_SCB0_UART_RX_CTRL EQU 0x40060048 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_POLARITY__OFFSET +CYFLD_SCB_POLARITY__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_POLARITY__SIZE +CYFLD_SCB_POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET +CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE +CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET +CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE +CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MP_MODE__OFFSET +CYFLD_SCB_MP_MODE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MP_MODE__SIZE +CYFLD_SCB_MP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LIN_MODE__OFFSET +CYFLD_SCB_LIN_MODE__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LIN_MODE__SIZE +CYFLD_SCB_LIN_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SKIP_START__OFFSET +CYFLD_SCB_SKIP_START__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SKIP_START__SIZE +CYFLD_SCB_SKIP_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_WIDTH__OFFSET +CYFLD_SCB_BREAK_WIDTH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_WIDTH__SIZE +CYFLD_SCB_BREAK_WIDTH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_RX_STATUS +CYREG_SCB0_UART_RX_STATUS EQU 0x4006004c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BR_COUNTER__OFFSET +CYFLD_SCB_BR_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BR_COUNTER__SIZE +CYFLD_SCB_BR_COUNTER__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_CTRL +CYREG_SCB0_I2C_CTRL EQU 0x40060060 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_HIGH_PHASE_OVS__OFFSET +CYFLD_SCB_HIGH_PHASE_OVS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_HIGH_PHASE_OVS__SIZE +CYFLD_SCB_HIGH_PHASE_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOW_PHASE_OVS__OFFSET +CYFLD_SCB_LOW_PHASE_OVS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOW_PHASE_OVS__SIZE +CYFLD_SCB_LOW_PHASE_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READY_DATA_ACK__OFFSET +CYFLD_SCB_M_READY_DATA_ACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READY_DATA_ACK__SIZE +CYFLD_SCB_M_READY_DATA_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET +CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE +CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_GENERAL_IGNORE__OFFSET +CYFLD_SCB_S_GENERAL_IGNORE__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_GENERAL_IGNORE__SIZE +CYFLD_SCB_S_GENERAL_IGNORE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_ADDR_ACK__OFFSET +CYFLD_SCB_S_READY_ADDR_ACK__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_ADDR_ACK__SIZE +CYFLD_SCB_S_READY_ADDR_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_DATA_ACK__OFFSET +CYFLD_SCB_S_READY_DATA_ACK__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_DATA_ACK__SIZE +CYFLD_SCB_S_READY_DATA_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET +CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE +CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET +CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE +CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_MODE__OFFSET +CYFLD_SCB_SLAVE_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_MODE__SIZE +CYFLD_SCB_SLAVE_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_STATUS +CYREG_SCB0_I2C_STATUS EQU 0x40060064 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READ__OFFSET +CYFLD_SCB_S_READ__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READ__SIZE +CYFLD_SCB_S_READ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READ__OFFSET +CYFLD_SCB_M_READ__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READ__SIZE +CYFLD_SCB_M_READ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_M_CMD +CYREG_SCB0_I2C_M_CMD EQU 0x40060068 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START__OFFSET +CYFLD_SCB_M_START__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START__SIZE +CYFLD_SCB_M_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START_ON_IDLE__OFFSET +CYFLD_SCB_M_START_ON_IDLE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START_ON_IDLE__SIZE +CYFLD_SCB_M_START_ON_IDLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_ACK__OFFSET +CYFLD_SCB_M_ACK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_ACK__SIZE +CYFLD_SCB_M_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NACK__OFFSET +CYFLD_SCB_M_NACK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NACK__SIZE +CYFLD_SCB_M_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_STOP__OFFSET +CYFLD_SCB_M_STOP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_STOP__SIZE +CYFLD_SCB_M_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_S_CMD +CYREG_SCB0_I2C_S_CMD EQU 0x4006006c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_ACK__OFFSET +CYFLD_SCB_S_ACK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_ACK__SIZE +CYFLD_SCB_S_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NACK__OFFSET +CYFLD_SCB_S_NACK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NACK__SIZE +CYFLD_SCB_S_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_CFG +CYREG_SCB0_I2C_CFG EQU 0x40060070 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HYS__OFFSET +CYFLD_SCB_SDA_FILT_HYS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HYS__SIZE +CYFLD_SCB_SDA_FILT_HYS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_TRIM__OFFSET +CYFLD_SCB_SDA_FILT_TRIM__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_TRIM__SIZE +CYFLD_SCB_SDA_FILT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HYS__OFFSET +CYFLD_SCB_SCL_FILT_HYS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HYS__SIZE +CYFLD_SCB_SCL_FILT_HYS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_TRIM__OFFSET +CYFLD_SCB_SCL_FILT_TRIM__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_TRIM__SIZE +CYFLD_SCB_SCL_FILT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET +CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE +CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET +CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE +CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HS__OFFSET +CYFLD_SCB_SDA_FILT_HS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HS__SIZE +CYFLD_SCB_SDA_FILT_HS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_ENABLED__OFFSET +CYFLD_SCB_SDA_FILT_ENABLED__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_ENABLED__SIZE +CYFLD_SCB_SDA_FILT_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HS__OFFSET +CYFLD_SCB_SCL_FILT_HS__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HS__SIZE +CYFLD_SCB_SCL_FILT_HS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_ENABLED__OFFSET +CYFLD_SCB_SCL_FILT_ENABLED__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_ENABLED__SIZE +CYFLD_SCB_SCL_FILT_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET +CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HS__SIZE +CYFLD_SCB_SDA_FILT_OUT_HS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET +CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE +CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_BIST_CONTROL +CYREG_SCB0_BIST_CONTROL EQU 0x40060100 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_ADDR__OFFSET +CYFLD_SCB_RAM_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_ADDR__SIZE +CYFLD_SCB_RAM_ADDR__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP1__OFFSET +CYFLD_SCB_RAM_OP1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP1__SIZE +CYFLD_SCB_RAM_OP1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP2__OFFSET +CYFLD_SCB_RAM_OP2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP2__SIZE +CYFLD_SCB_RAM_OP2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP3__OFFSET +CYFLD_SCB_RAM_OP3__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP3__SIZE +CYFLD_SCB_RAM_OP3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP4__OFFSET +CYFLD_SCB_RAM_OP4__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP4__SIZE +CYFLD_SCB_RAM_OP4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OPCNT__OFFSET +CYFLD_SCB_RAM_OPCNT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OPCNT__SIZE +CYFLD_SCB_RAM_OPCNT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_PREADR__OFFSET +CYFLD_SCB_RAM_PREADR__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_PREADR__SIZE +CYFLD_SCB_RAM_PREADR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_WORD__OFFSET +CYFLD_SCB_RAM_WORD__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_WORD__SIZE +CYFLD_SCB_RAM_WORD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_FAIL__OFFSET +CYFLD_SCB_RAM_FAIL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_FAIL__SIZE +CYFLD_SCB_RAM_FAIL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_GO__OFFSET +CYFLD_SCB_RAM_GO__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_GO__SIZE +CYFLD_SCB_RAM_GO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_BIST_DATA +CYREG_SCB0_BIST_DATA EQU 0x40060104 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_DATA__OFFSET +CYFLD_SCB_RAM_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_DATA__SIZE +CYFLD_SCB_RAM_DATA__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_CTRL +CYREG_SCB0_TX_CTRL EQU 0x40060200 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA_WIDTH__OFFSET +CYFLD_SCB_DATA_WIDTH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA_WIDTH__SIZE +CYFLD_SCB_DATA_WIDTH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MSB_FIRST__OFFSET +CYFLD_SCB_MSB_FIRST__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MSB_FIRST__SIZE +CYFLD_SCB_MSB_FIRST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_CTRL +CYREG_SCB0_TX_FIFO_CTRL EQU 0x40060204 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER_LEVEL__OFFSET +CYFLD_SCB_TRIGGER_LEVEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER_LEVEL__SIZE +CYFLD_SCB_TRIGGER_LEVEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CLEAR__OFFSET +CYFLD_SCB_CLEAR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CLEAR__SIZE +CYFLD_SCB_CLEAR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FREEZE__OFFSET +CYFLD_SCB_FREEZE__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FREEZE__SIZE +CYFLD_SCB_FREEZE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_STATUS +CYREG_SCB0_TX_FIFO_STATUS EQU 0x40060208 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_USED__OFFSET +CYFLD_SCB_USED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_USED__SIZE +CYFLD_SCB_USED__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SR_VALID__OFFSET +CYFLD_SCB_SR_VALID__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SR_VALID__SIZE +CYFLD_SCB_SR_VALID__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RD_PTR__OFFSET +CYFLD_SCB_RD_PTR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RD_PTR__SIZE +CYFLD_SCB_RD_PTR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WR_PTR__OFFSET +CYFLD_SCB_WR_PTR__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WR_PTR__SIZE +CYFLD_SCB_WR_PTR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_WR +CYREG_SCB0_TX_FIFO_WR EQU 0x40060240 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA__OFFSET +CYFLD_SCB_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA__SIZE +CYFLD_SCB_DATA__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_CTRL +CYREG_SCB0_RX_CTRL EQU 0x40060300 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MEDIAN__OFFSET +CYFLD_SCB_MEDIAN__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MEDIAN__SIZE +CYFLD_SCB_MEDIAN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_CTRL +CYREG_SCB0_RX_FIFO_CTRL EQU 0x40060304 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_STATUS +CYREG_SCB0_RX_FIFO_STATUS EQU 0x40060308 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_MATCH +CYREG_SCB0_RX_MATCH EQU 0x40060310 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR__OFFSET +CYFLD_SCB_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR__SIZE +CYFLD_SCB_ADDR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASK__OFFSET +CYFLD_SCB_MASK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASK__SIZE +CYFLD_SCB_MASK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_RD +CYREG_SCB0_RX_FIFO_RD EQU 0x40060340 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_RD_SILENT +CYREG_SCB0_RX_FIFO_RD_SILENT EQU 0x40060344 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA00 +CYREG_SCB0_EZ_DATA00 EQU 0x40060400 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_DATA__OFFSET +CYFLD_SCB_EZ_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_DATA__SIZE +CYFLD_SCB_EZ_DATA__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA01 +CYREG_SCB0_EZ_DATA01 EQU 0x40060404 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA02 +CYREG_SCB0_EZ_DATA02 EQU 0x40060408 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA03 +CYREG_SCB0_EZ_DATA03 EQU 0x4006040c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA04 +CYREG_SCB0_EZ_DATA04 EQU 0x40060410 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA05 +CYREG_SCB0_EZ_DATA05 EQU 0x40060414 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA06 +CYREG_SCB0_EZ_DATA06 EQU 0x40060418 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA07 +CYREG_SCB0_EZ_DATA07 EQU 0x4006041c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA08 +CYREG_SCB0_EZ_DATA08 EQU 0x40060420 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA09 +CYREG_SCB0_EZ_DATA09 EQU 0x40060424 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA10 +CYREG_SCB0_EZ_DATA10 EQU 0x40060428 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA11 +CYREG_SCB0_EZ_DATA11 EQU 0x4006042c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA12 +CYREG_SCB0_EZ_DATA12 EQU 0x40060430 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA13 +CYREG_SCB0_EZ_DATA13 EQU 0x40060434 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA14 +CYREG_SCB0_EZ_DATA14 EQU 0x40060438 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA15 +CYREG_SCB0_EZ_DATA15 EQU 0x4006043c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA16 +CYREG_SCB0_EZ_DATA16 EQU 0x40060440 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA17 +CYREG_SCB0_EZ_DATA17 EQU 0x40060444 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA18 +CYREG_SCB0_EZ_DATA18 EQU 0x40060448 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA19 +CYREG_SCB0_EZ_DATA19 EQU 0x4006044c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA20 +CYREG_SCB0_EZ_DATA20 EQU 0x40060450 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA21 +CYREG_SCB0_EZ_DATA21 EQU 0x40060454 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA22 +CYREG_SCB0_EZ_DATA22 EQU 0x40060458 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA23 +CYREG_SCB0_EZ_DATA23 EQU 0x4006045c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA24 +CYREG_SCB0_EZ_DATA24 EQU 0x40060460 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA25 +CYREG_SCB0_EZ_DATA25 EQU 0x40060464 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA26 +CYREG_SCB0_EZ_DATA26 EQU 0x40060468 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA27 +CYREG_SCB0_EZ_DATA27 EQU 0x4006046c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA28 +CYREG_SCB0_EZ_DATA28 EQU 0x40060470 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA29 +CYREG_SCB0_EZ_DATA29 EQU 0x40060474 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA30 +CYREG_SCB0_EZ_DATA30 EQU 0x40060478 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA31 +CYREG_SCB0_EZ_DATA31 EQU 0x4006047c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_CAUSE +CYREG_SCB0_INTR_CAUSE EQU 0x40060e00 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M__OFFSET +CYFLD_SCB_M__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M__SIZE +CYFLD_SCB_M__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S__OFFSET +CYFLD_SCB_S__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S__SIZE +CYFLD_SCB_S__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TX__OFFSET +CYFLD_SCB_TX__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TX__SIZE +CYFLD_SCB_TX__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RX__OFFSET +CYFLD_SCB_RX__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RX__SIZE +CYFLD_SCB_RX__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC__OFFSET +CYFLD_SCB_I2C_EC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC__SIZE +CYFLD_SCB_I2C_EC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC__OFFSET +CYFLD_SCB_SPI_EC__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC__SIZE +CYFLD_SCB_SPI_EC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC +CYREG_SCB0_INTR_I2C_EC EQU 0x40060e80 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WAKE_UP__OFFSET +CYFLD_SCB_WAKE_UP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WAKE_UP__SIZE +CYFLD_SCB_WAKE_UP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_STOP__OFFSET +CYFLD_SCB_EZ_STOP__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_STOP__SIZE +CYFLD_SCB_EZ_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_WRITE_STOP__OFFSET +CYFLD_SCB_EZ_WRITE_STOP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_WRITE_STOP__SIZE +CYFLD_SCB_EZ_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC_MASK +CYREG_SCB0_INTR_I2C_EC_MASK EQU 0x40060e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC_MASKED +CYREG_SCB0_INTR_I2C_EC_MASKED EQU 0x40060e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC +CYREG_SCB0_INTR_SPI_EC EQU 0x40060ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC_MASK +CYREG_SCB0_INTR_SPI_EC_MASK EQU 0x40060ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC_MASKED +CYREG_SCB0_INTR_SPI_EC_MASKED EQU 0x40060ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M +CYREG_SCB0_INTR_M EQU 0x40060f00 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ARB_LOST__OFFSET +CYFLD_SCB_I2C_ARB_LOST__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ARB_LOST__SIZE +CYFLD_SCB_I2C_ARB_LOST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_NACK__OFFSET +CYFLD_SCB_I2C_NACK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_NACK__SIZE +CYFLD_SCB_I2C_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ACK__OFFSET +CYFLD_SCB_I2C_ACK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ACK__SIZE +CYFLD_SCB_I2C_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_STOP__OFFSET +CYFLD_SCB_I2C_STOP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_STOP__SIZE +CYFLD_SCB_I2C_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_BUS_ERROR__OFFSET +CYFLD_SCB_I2C_BUS_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_BUS_ERROR__SIZE +CYFLD_SCB_I2C_BUS_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_DONE__OFFSET +CYFLD_SCB_SPI_DONE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_DONE__SIZE +CYFLD_SCB_SPI_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_SET +CYREG_SCB0_INTR_M_SET EQU 0x40060f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_MASK +CYREG_SCB0_INTR_M_MASK EQU 0x40060f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_MASKED +CYREG_SCB0_INTR_M_MASKED EQU 0x40060f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S +CYREG_SCB0_INTR_S EQU 0x40060f40 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_WRITE_STOP__OFFSET +CYFLD_SCB_I2C_WRITE_STOP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_WRITE_STOP__SIZE +CYFLD_SCB_I2C_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_START__OFFSET +CYFLD_SCB_I2C_START__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_START__SIZE +CYFLD_SCB_I2C_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ADDR_MATCH__OFFSET +CYFLD_SCB_I2C_ADDR_MATCH__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ADDR_MATCH__SIZE +CYFLD_SCB_I2C_ADDR_MATCH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_GENERAL__OFFSET +CYFLD_SCB_I2C_GENERAL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_GENERAL__SIZE +CYFLD_SCB_I2C_GENERAL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET +CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE +CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_STOP__OFFSET +CYFLD_SCB_SPI_EZ_STOP__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_STOP__SIZE +CYFLD_SCB_SPI_EZ_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_BUS_ERROR__OFFSET +CYFLD_SCB_SPI_BUS_ERROR__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_BUS_ERROR__SIZE +CYFLD_SCB_SPI_BUS_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_SET +CYREG_SCB0_INTR_S_SET EQU 0x40060f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_MASK +CYREG_SCB0_INTR_S_MASK EQU 0x40060f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_MASKED +CYREG_SCB0_INTR_S_MASKED EQU 0x40060f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX +CYREG_SCB0_INTR_TX EQU 0x40060f80 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER__OFFSET +CYFLD_SCB_TRIGGER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER__SIZE +CYFLD_SCB_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_FULL__OFFSET +CYFLD_SCB_NOT_FULL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_FULL__SIZE +CYFLD_SCB_NOT_FULL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EMPTY__OFFSET +CYFLD_SCB_EMPTY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EMPTY__SIZE +CYFLD_SCB_EMPTY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVERFLOW__OFFSET +CYFLD_SCB_OVERFLOW__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVERFLOW__SIZE +CYFLD_SCB_OVERFLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UNDERFLOW__OFFSET +CYFLD_SCB_UNDERFLOW__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UNDERFLOW__SIZE +CYFLD_SCB_UNDERFLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCKED__OFFSET +CYFLD_SCB_BLOCKED__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCKED__SIZE +CYFLD_SCB_BLOCKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_NACK__OFFSET +CYFLD_SCB_UART_NACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_NACK__SIZE +CYFLD_SCB_UART_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_DONE__OFFSET +CYFLD_SCB_UART_DONE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_DONE__SIZE +CYFLD_SCB_UART_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_ARB_LOST__OFFSET +CYFLD_SCB_UART_ARB_LOST__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_ARB_LOST__SIZE +CYFLD_SCB_UART_ARB_LOST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_SET +CYREG_SCB0_INTR_TX_SET EQU 0x40060f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_MASK +CYREG_SCB0_INTR_TX_MASK EQU 0x40060f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_MASKED +CYREG_SCB0_INTR_TX_MASKED EQU 0x40060f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX +CYREG_SCB0_INTR_RX EQU 0x40060fc0 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_EMPTY__OFFSET +CYFLD_SCB_NOT_EMPTY__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_EMPTY__SIZE +CYFLD_SCB_NOT_EMPTY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FULL__OFFSET +CYFLD_SCB_FULL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FULL__SIZE +CYFLD_SCB_FULL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FRAME_ERROR__OFFSET +CYFLD_SCB_FRAME_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FRAME_ERROR__SIZE +CYFLD_SCB_FRAME_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ERROR__OFFSET +CYFLD_SCB_PARITY_ERROR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ERROR__SIZE +CYFLD_SCB_PARITY_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BAUD_DETECT__OFFSET +CYFLD_SCB_BAUD_DETECT__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BAUD_DETECT__SIZE +CYFLD_SCB_BAUD_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_DETECT__OFFSET +CYFLD_SCB_BREAK_DETECT__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_DETECT__SIZE +CYFLD_SCB_BREAK_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_SET +CYREG_SCB0_INTR_RX_SET EQU 0x40060fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_MASK +CYREG_SCB0_INTR_RX_MASK EQU 0x40060fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_MASKED +CYREG_SCB0_INTR_RX_MASKED EQU 0x40060fcc + ENDIF + IF :LNOT::DEF:CYDEV_SCB1_BASE +CYDEV_SCB1_BASE EQU 0x40070000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB1_SIZE +CYDEV_SCB1_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_CTRL +CYREG_SCB1_CTRL EQU 0x40070000 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_STATUS +CYREG_SCB1_STATUS EQU 0x40070004 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_SPI_CTRL +CYREG_SCB1_SPI_CTRL EQU 0x40070020 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_SPI_STATUS +CYREG_SCB1_SPI_STATUS EQU 0x40070024 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_CTRL +CYREG_SCB1_UART_CTRL EQU 0x40070040 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_TX_CTRL +CYREG_SCB1_UART_TX_CTRL EQU 0x40070044 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_RX_CTRL +CYREG_SCB1_UART_RX_CTRL EQU 0x40070048 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_RX_STATUS +CYREG_SCB1_UART_RX_STATUS EQU 0x4007004c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_CTRL +CYREG_SCB1_I2C_CTRL EQU 0x40070060 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_STATUS +CYREG_SCB1_I2C_STATUS EQU 0x40070064 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_M_CMD +CYREG_SCB1_I2C_M_CMD EQU 0x40070068 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_S_CMD +CYREG_SCB1_I2C_S_CMD EQU 0x4007006c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_CFG +CYREG_SCB1_I2C_CFG EQU 0x40070070 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_BIST_CONTROL +CYREG_SCB1_BIST_CONTROL EQU 0x40070100 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_BIST_DATA +CYREG_SCB1_BIST_DATA EQU 0x40070104 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_CTRL +CYREG_SCB1_TX_CTRL EQU 0x40070200 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_CTRL +CYREG_SCB1_TX_FIFO_CTRL EQU 0x40070204 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_STATUS +CYREG_SCB1_TX_FIFO_STATUS EQU 0x40070208 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_WR +CYREG_SCB1_TX_FIFO_WR EQU 0x40070240 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_CTRL +CYREG_SCB1_RX_CTRL EQU 0x40070300 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_CTRL +CYREG_SCB1_RX_FIFO_CTRL EQU 0x40070304 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_STATUS +CYREG_SCB1_RX_FIFO_STATUS EQU 0x40070308 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_MATCH +CYREG_SCB1_RX_MATCH EQU 0x40070310 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_RD +CYREG_SCB1_RX_FIFO_RD EQU 0x40070340 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_RD_SILENT +CYREG_SCB1_RX_FIFO_RD_SILENT EQU 0x40070344 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA00 +CYREG_SCB1_EZ_DATA00 EQU 0x40070400 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA01 +CYREG_SCB1_EZ_DATA01 EQU 0x40070404 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA02 +CYREG_SCB1_EZ_DATA02 EQU 0x40070408 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA03 +CYREG_SCB1_EZ_DATA03 EQU 0x4007040c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA04 +CYREG_SCB1_EZ_DATA04 EQU 0x40070410 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA05 +CYREG_SCB1_EZ_DATA05 EQU 0x40070414 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA06 +CYREG_SCB1_EZ_DATA06 EQU 0x40070418 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA07 +CYREG_SCB1_EZ_DATA07 EQU 0x4007041c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA08 +CYREG_SCB1_EZ_DATA08 EQU 0x40070420 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA09 +CYREG_SCB1_EZ_DATA09 EQU 0x40070424 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA10 +CYREG_SCB1_EZ_DATA10 EQU 0x40070428 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA11 +CYREG_SCB1_EZ_DATA11 EQU 0x4007042c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA12 +CYREG_SCB1_EZ_DATA12 EQU 0x40070430 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA13 +CYREG_SCB1_EZ_DATA13 EQU 0x40070434 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA14 +CYREG_SCB1_EZ_DATA14 EQU 0x40070438 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA15 +CYREG_SCB1_EZ_DATA15 EQU 0x4007043c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA16 +CYREG_SCB1_EZ_DATA16 EQU 0x40070440 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA17 +CYREG_SCB1_EZ_DATA17 EQU 0x40070444 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA18 +CYREG_SCB1_EZ_DATA18 EQU 0x40070448 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA19 +CYREG_SCB1_EZ_DATA19 EQU 0x4007044c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA20 +CYREG_SCB1_EZ_DATA20 EQU 0x40070450 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA21 +CYREG_SCB1_EZ_DATA21 EQU 0x40070454 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA22 +CYREG_SCB1_EZ_DATA22 EQU 0x40070458 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA23 +CYREG_SCB1_EZ_DATA23 EQU 0x4007045c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA24 +CYREG_SCB1_EZ_DATA24 EQU 0x40070460 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA25 +CYREG_SCB1_EZ_DATA25 EQU 0x40070464 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA26 +CYREG_SCB1_EZ_DATA26 EQU 0x40070468 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA27 +CYREG_SCB1_EZ_DATA27 EQU 0x4007046c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA28 +CYREG_SCB1_EZ_DATA28 EQU 0x40070470 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA29 +CYREG_SCB1_EZ_DATA29 EQU 0x40070474 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA30 +CYREG_SCB1_EZ_DATA30 EQU 0x40070478 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA31 +CYREG_SCB1_EZ_DATA31 EQU 0x4007047c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_CAUSE +CYREG_SCB1_INTR_CAUSE EQU 0x40070e00 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC +CYREG_SCB1_INTR_I2C_EC EQU 0x40070e80 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC_MASK +CYREG_SCB1_INTR_I2C_EC_MASK EQU 0x40070e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC_MASKED +CYREG_SCB1_INTR_I2C_EC_MASKED EQU 0x40070e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC +CYREG_SCB1_INTR_SPI_EC EQU 0x40070ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC_MASK +CYREG_SCB1_INTR_SPI_EC_MASK EQU 0x40070ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC_MASKED +CYREG_SCB1_INTR_SPI_EC_MASKED EQU 0x40070ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M +CYREG_SCB1_INTR_M EQU 0x40070f00 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_SET +CYREG_SCB1_INTR_M_SET EQU 0x40070f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_MASK +CYREG_SCB1_INTR_M_MASK EQU 0x40070f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_MASKED +CYREG_SCB1_INTR_M_MASKED EQU 0x40070f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S +CYREG_SCB1_INTR_S EQU 0x40070f40 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_SET +CYREG_SCB1_INTR_S_SET EQU 0x40070f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_MASK +CYREG_SCB1_INTR_S_MASK EQU 0x40070f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_MASKED +CYREG_SCB1_INTR_S_MASKED EQU 0x40070f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX +CYREG_SCB1_INTR_TX EQU 0x40070f80 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_SET +CYREG_SCB1_INTR_TX_SET EQU 0x40070f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_MASK +CYREG_SCB1_INTR_TX_MASK EQU 0x40070f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_MASKED +CYREG_SCB1_INTR_TX_MASKED EQU 0x40070f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX +CYREG_SCB1_INTR_RX EQU 0x40070fc0 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_SET +CYREG_SCB1_INTR_RX_SET EQU 0x40070fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_MASK +CYREG_SCB1_INTR_RX_MASK EQU 0x40070fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_MASKED +CYREG_SCB1_INTR_RX_MASKED EQU 0x40070fcc + ENDIF + IF :LNOT::DEF:CYDEV_CSD_BASE +CYDEV_CSD_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_CSD_SIZE +CYDEV_CSD_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CSD_ID +CYREG_CSD_ID EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ID__OFFSET +CYFLD_CSD_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ID__SIZE +CYFLD_CSD_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REVISION__OFFSET +CYFLD_CSD_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REVISION__SIZE +CYFLD_CSD_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CSD_CONFIG +CYREG_CSD_CONFIG EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SAMPLE_EN__OFFSET +CYFLD_CSD_DSI_SAMPLE_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SAMPLE_EN__SIZE +CYFLD_CSD_DSI_SAMPLE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE_SYNC__OFFSET +CYFLD_CSD_SAMPLE_SYNC__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE_SYNC__SIZE +CYFLD_CSD_SAMPLE_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_CLEAR__OFFSET +CYFLD_CSD_PRS_CLEAR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_CLEAR__SIZE +CYFLD_CSD_PRS_CLEAR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_SELECT__OFFSET +CYFLD_CSD_PRS_SELECT__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_SELECT__SIZE +CYFLD_CSD_PRS_SELECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_SELECT_DIV2 +CYVAL_CSD_PRS_SELECT_DIV2 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_SELECT_PRS +CYVAL_CSD_PRS_SELECT_PRS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_12_8__OFFSET +CYFLD_CSD_PRS_12_8__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_12_8__SIZE +CYFLD_CSD_PRS_12_8__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_12_8_8B +CYVAL_CSD_PRS_12_8_8B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_12_8_12B +CYVAL_CSD_PRS_12_8_12B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SENSE_EN__OFFSET +CYFLD_CSD_DSI_SENSE_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SENSE_EN__SIZE +CYFLD_CSD_DSI_SENSE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SHIELD_DELAY__OFFSET +CYFLD_CSD_SHIELD_DELAY__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SHIELD_DELAY__SIZE +CYFLD_CSD_SHIELD_DELAY__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_BW__OFFSET +CYFLD_CSD_SENSE_COMP_BW__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_BW__SIZE +CYFLD_CSD_SENSE_COMP_BW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_COMP_BW_LOW +CYVAL_CSD_SENSE_COMP_BW_LOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_COMP_BW_HIGH +CYVAL_CSD_SENSE_COMP_BW_HIGH EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_EN__OFFSET +CYFLD_CSD_SENSE_EN__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_EN__SIZE +CYFLD_CSD_SENSE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_EN__OFFSET +CYFLD_CSD_REFBUF_EN__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_EN__SIZE +CYFLD_CSD_REFBUF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_MODE__OFFSET +CYFLD_CSD_COMP_MODE__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_MODE__SIZE +CYFLD_CSD_COMP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_MODE_CHARGE_BUF +CYVAL_CSD_COMP_MODE_CHARGE_BUF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_MODE_CHARGE_IO +CYVAL_CSD_COMP_MODE_CHARGE_IO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_PIN__OFFSET +CYFLD_CSD_COMP_PIN__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_PIN__SIZE +CYFLD_CSD_COMP_PIN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_PIN_CHANNEL1 +CYVAL_CSD_COMP_PIN_CHANNEL1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_PIN_CHANNEL2 +CYVAL_CSD_COMP_PIN_CHANNEL2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY__OFFSET +CYFLD_CSD_POLARITY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY__SIZE +CYFLD_CSD_POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_VSSIO +CYVAL_CSD_POLARITY_VSSIO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_VDDIO +CYVAL_CSD_POLARITY_VDDIO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY2__OFFSET +CYFLD_CSD_POLARITY2__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY2__SIZE +CYFLD_CSD_POLARITY2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY2_VSSIO +CYVAL_CSD_POLARITY2_VSSIO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY2_VDDIO +CYVAL_CSD_POLARITY2_VDDIO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_MUTUAL_CAP__OFFSET +CYFLD_CSD_MUTUAL_CAP__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_MUTUAL_CAP__SIZE +CYFLD_CSD_MUTUAL_CAP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_MUTUAL_CAP_SELFCAP +CYVAL_CSD_MUTUAL_CAP_SELFCAP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_MUTUAL_CAP_MUTUALCAP +CYVAL_CSD_MUTUAL_CAP_MUTUALCAP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_EN__OFFSET +CYFLD_CSD_SENSE_COMP_EN__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_EN__SIZE +CYFLD_CSD_SENSE_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REBUF_OUTSEL__OFFSET +CYFLD_CSD_REBUF_OUTSEL__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REBUF_OUTSEL__SIZE +CYFLD_CSD_REBUF_OUTSEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REBUF_OUTSEL_AMUXA +CYVAL_CSD_REBUF_OUTSEL_AMUXA EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REBUF_OUTSEL_AMUXB +CYVAL_CSD_REBUF_OUTSEL_AMUXB EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_INSEL__OFFSET +CYFLD_CSD_SENSE_INSEL__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_INSEL__SIZE +CYFLD_CSD_SENSE_INSEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 +CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA +CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_DRV__OFFSET +CYFLD_CSD_REFBUF_DRV__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_DRV__SIZE +CYFLD_CSD_REFBUF_DRV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_OFF +CYVAL_CSD_REFBUF_DRV_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_DRV_1 +CYVAL_CSD_REFBUF_DRV_DRV_1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_DRV_2 +CYVAL_CSD_REFBUF_DRV_DRV_2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_DRV_3 +CYVAL_CSD_REFBUF_DRV_DRV_3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTSEL__OFFSET +CYFLD_CSD_DDFTSEL__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTSEL__SIZE +CYFLD_CSD_DDFTSEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_NORMAL +CYVAL_CSD_DDFTSEL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_CSD_SENSE +CYVAL_CSD_DDFTSEL_CSD_SENSE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_CSD_SHIELD +CYVAL_CSD_DDFTSEL_CSD_SHIELD EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_CLK_SAMPLE +CYVAL_CSD_DDFTSEL_CLK_SAMPLE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_COMP_OUT +CYVAL_CSD_DDFTSEL_COMP_OUT EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADFTEN__OFFSET +CYFLD_CSD_ADFTEN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADFTEN__SIZE +CYFLD_CSD_ADFTEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTCOMP__OFFSET +CYFLD_CSD_DDFTCOMP__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTCOMP__SIZE +CYFLD_CSD_DDFTCOMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTCOMP_REFBUFCOMP +CYVAL_CSD_DDFTCOMP_REFBUFCOMP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTCOMP_SENSECOMP +CYVAL_CSD_DDFTCOMP_SENSECOMP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ENABLE__OFFSET +CYFLD_CSD_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ENABLE__SIZE +CYFLD_CSD_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_IDAC +CYREG_CSD_IDAC EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1__OFFSET +CYFLD_CSD_IDAC1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1__SIZE +CYFLD_CSD_IDAC1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_MODE__OFFSET +CYFLD_CSD_IDAC1_MODE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_MODE__SIZE +CYFLD_CSD_IDAC1_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_OFF +CYVAL_CSD_IDAC1_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_FIXED +CYVAL_CSD_IDAC1_MODE_FIXED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_VARIABLE +CYVAL_CSD_IDAC1_MODE_VARIABLE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_DSI +CYVAL_CSD_IDAC1_MODE_DSI EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_RANGE__OFFSET +CYFLD_CSD_IDAC1_RANGE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_RANGE__SIZE +CYFLD_CSD_IDAC1_RANGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_RANGE_4X +CYVAL_CSD_IDAC1_RANGE_4X EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_RANGE_8X +CYVAL_CSD_IDAC1_RANGE_8X EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2__OFFSET +CYFLD_CSD_IDAC2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2__SIZE +CYFLD_CSD_IDAC2__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_MODE__OFFSET +CYFLD_CSD_IDAC2_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_MODE__SIZE +CYFLD_CSD_IDAC2_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_OFF +CYVAL_CSD_IDAC2_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_FIXED +CYVAL_CSD_IDAC2_MODE_FIXED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_VARIABLE +CYVAL_CSD_IDAC2_MODE_VARIABLE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_DSI +CYVAL_CSD_IDAC2_MODE_DSI EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_RANGE__OFFSET +CYFLD_CSD_IDAC2_RANGE__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_RANGE__SIZE +CYFLD_CSD_IDAC2_RANGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_RANGE_4X +CYVAL_CSD_IDAC2_RANGE_4X EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_RANGE_8X +CYVAL_CSD_IDAC2_RANGE_8X EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FEEDBACK_MODE__OFFSET +CYFLD_CSD_FEEDBACK_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FEEDBACK_MODE__SIZE +CYFLD_CSD_FEEDBACK_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FEEDBACK_MODE_FLOP +CYVAL_CSD_FEEDBACK_MODE_FLOP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FEEDBACK_MODE_COMP +CYVAL_CSD_FEEDBACK_MODE_COMP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_COUNTER +CYREG_CSD_COUNTER EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COUNTER__OFFSET +CYFLD_CSD_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COUNTER__SIZE +CYFLD_CSD_COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PERIOD__OFFSET +CYFLD_CSD_PERIOD__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PERIOD__SIZE +CYFLD_CSD_PERIOD__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CSD_STATUS +CYREG_CSD_STATUS EQU 0x40080010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_CHARGE__OFFSET +CYFLD_CSD_CSD_CHARGE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_CHARGE__SIZE +CYFLD_CSD_CSD_CHARGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_SENSE__OFFSET +CYFLD_CSD_CSD_SENSE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_SENSE__SIZE +CYFLD_CSD_CSD_SENSE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_OUT__OFFSET +CYFLD_CSD_COMP_OUT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_OUT__SIZE +CYFLD_CSD_COMP_OUT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_OUT_C_LT_VREF +CYVAL_CSD_COMP_OUT_C_LT_VREF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_OUT_C_GT_VREF +CYVAL_CSD_COMP_OUT_C_GT_VREF EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE__OFFSET +CYFLD_CSD_SAMPLE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE__SIZE +CYFLD_CSD_SAMPLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR +CYREG_CSD_INTR EQU 0x40080014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD__OFFSET +CYFLD_CSD_CSD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD__SIZE +CYFLD_CSD_CSD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR_SET +CYREG_CSD_INTR_SET EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_CSD_TRIM1 +CYREG_CSD_TRIM1 EQU 0x4008ff00 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET +CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SRC_TRIM__SIZE +CYFLD_CSD_IDAC1_SRC_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET +CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SRC_TRIM__SIZE +CYFLD_CSD_IDAC2_SRC_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CSD_TRIM2 +CYREG_CSD_TRIM2 EQU 0x4008ff04 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET +CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SNK_TRIM__SIZE +CYFLD_CSD_IDAC1_SNK_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET +CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SNK_TRIM__SIZE +CYFLD_CSD_IDAC2_SNK_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_LCD_BASE +CYDEV_LCD_BASE EQU 0x40090000 + ENDIF + IF :LNOT::DEF:CYDEV_LCD_SIZE +CYDEV_LCD_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_LCD_ID +CYREG_LCD_ID EQU 0x40090000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_ID__OFFSET +CYFLD_LCD_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_ID__SIZE +CYFLD_LCD_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_REVISION__OFFSET +CYFLD_LCD_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_REVISION__SIZE +CYFLD_LCD_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DIVIDER +CYREG_LCD_DIVIDER EQU 0x40090004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_SUBFR_DIV__OFFSET +CYFLD_LCD_SUBFR_DIV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_SUBFR_DIV__SIZE +CYFLD_LCD_SUBFR_DIV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DEAD_DIV__OFFSET +CYFLD_LCD_DEAD_DIV__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DEAD_DIV__SIZE +CYFLD_LCD_DEAD_DIV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LCD_CONTROL +CYREG_LCD_CONTROL EQU 0x40090008 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN__OFFSET +CYFLD_LCD_LS_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN__SIZE +CYFLD_LCD_LS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_HS_EN__OFFSET +CYFLD_LCD_HS_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_HS_EN__SIZE +CYFLD_LCD_HS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LCD_MODE__OFFSET +CYFLD_LCD_LCD_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LCD_MODE__SIZE +CYFLD_LCD_LCD_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_LCD_MODE_LS +CYVAL_LCD_LCD_MODE_LS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_LCD_MODE_HS +CYVAL_LCD_LCD_MODE_HS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_TYPE__OFFSET +CYFLD_LCD_TYPE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_TYPE__SIZE +CYFLD_LCD_TYPE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_TYPE_A +CYVAL_LCD_TYPE_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_TYPE_B +CYVAL_LCD_TYPE_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_OP_MODE__OFFSET +CYFLD_LCD_OP_MODE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_OP_MODE__SIZE +CYFLD_LCD_OP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_OP_MODE_PWM +CYVAL_LCD_OP_MODE_PWM EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_OP_MODE_CORRELATION +CYVAL_LCD_OP_MODE_CORRELATION EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_BIAS__OFFSET +CYFLD_LCD_BIAS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_BIAS__SIZE +CYFLD_LCD_BIAS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_HALF +CYVAL_LCD_BIAS_HALF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_THIRD +CYVAL_LCD_BIAS_THIRD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_FOURTH +CYVAL_LCD_BIAS_FOURTH EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_FIFTH +CYVAL_LCD_BIAS_FIFTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_COM_NUM__OFFSET +CYFLD_LCD_COM_NUM__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_COM_NUM__SIZE +CYFLD_LCD_COM_NUM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN_STAT__OFFSET +CYFLD_LCD_LS_EN_STAT__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN_STAT__SIZE +CYFLD_LCD_LS_EN_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA00 +CYREG_LCD_DATA00 EQU 0x40090100 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DATA__OFFSET +CYFLD_LCD_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DATA__SIZE +CYFLD_LCD_DATA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA01 +CYREG_LCD_DATA01 EQU 0x40090104 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA02 +CYREG_LCD_DATA02 EQU 0x40090108 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA03 +CYREG_LCD_DATA03 EQU 0x4009010c + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA04 +CYREG_LCD_DATA04 EQU 0x40090110 + ENDIF + IF :LNOT::DEF:CYDEV_LPCOMP_BASE +CYDEV_LPCOMP_BASE EQU 0x400a0000 + ENDIF + IF :LNOT::DEF:CYDEV_LPCOMP_SIZE +CYDEV_LPCOMP_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_ID +CYREG_LPCOMP_ID EQU 0x400a0000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ID__OFFSET +CYFLD_LPCOMP_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ID__SIZE +CYFLD_LPCOMP_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_REVISION__OFFSET +CYFLD_LPCOMP_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_REVISION__SIZE +CYFLD_LPCOMP_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_CONFIG +CYREG_LPCOMP_CONFIG EQU 0x400a0004 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE1__OFFSET +CYFLD_LPCOMP_MODE1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE1__SIZE +CYFLD_LPCOMP_MODE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_SLOW +CYVAL_LPCOMP_MODE1_SLOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_FAST +CYVAL_LPCOMP_MODE1_FAST EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_ULP +CYVAL_LPCOMP_MODE1_ULP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST1__OFFSET +CYFLD_LPCOMP_HYST1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST1__SIZE +CYFLD_LPCOMP_HYST1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER1__OFFSET +CYFLD_LPCOMP_FILTER1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER1__SIZE +CYFLD_LPCOMP_FILTER1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE1__OFFSET +CYFLD_LPCOMP_INTTYPE1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE1__SIZE +CYFLD_LPCOMP_INTTYPE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_DISABLE +CYVAL_LPCOMP_INTTYPE1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_RISING +CYVAL_LPCOMP_INTTYPE1_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_FALLING +CYVAL_LPCOMP_INTTYPE1_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_BOTH +CYVAL_LPCOMP_INTTYPE1_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT1__OFFSET +CYFLD_LPCOMP_OUT1__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT1__SIZE +CYFLD_LPCOMP_OUT1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE1__OFFSET +CYFLD_LPCOMP_ENABLE1__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE1__SIZE +CYFLD_LPCOMP_ENABLE1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE2__OFFSET +CYFLD_LPCOMP_MODE2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE2__SIZE +CYFLD_LPCOMP_MODE2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_SLOW +CYVAL_LPCOMP_MODE2_SLOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_FAST +CYVAL_LPCOMP_MODE2_FAST EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_ULP +CYVAL_LPCOMP_MODE2_ULP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST2__OFFSET +CYFLD_LPCOMP_HYST2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST2__SIZE +CYFLD_LPCOMP_HYST2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER2__OFFSET +CYFLD_LPCOMP_FILTER2__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER2__SIZE +CYFLD_LPCOMP_FILTER2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE2__OFFSET +CYFLD_LPCOMP_INTTYPE2__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE2__SIZE +CYFLD_LPCOMP_INTTYPE2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_DISABLE +CYVAL_LPCOMP_INTTYPE2_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_RISING +CYVAL_LPCOMP_INTTYPE2_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_FALLING +CYVAL_LPCOMP_INTTYPE2_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_BOTH +CYVAL_LPCOMP_INTTYPE2_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT2__OFFSET +CYFLD_LPCOMP_OUT2__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT2__SIZE +CYFLD_LPCOMP_OUT2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE2__OFFSET +CYFLD_LPCOMP_ENABLE2__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE2__SIZE +CYFLD_LPCOMP_ENABLE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_DFT +CYREG_LPCOMP_DFT EQU 0x400a0008 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_CAL_EN__OFFSET +CYFLD_LPCOMP_CAL_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_CAL_EN__SIZE +CYFLD_LPCOMP_CAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_BYPASS__OFFSET +CYFLD_LPCOMP_BYPASS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_BYPASS__SIZE +CYFLD_LPCOMP_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR +CYREG_LPCOMP_INTR EQU 0x400a000c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1__OFFSET +CYFLD_LPCOMP_COMP1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1__SIZE +CYFLD_LPCOMP_COMP1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2__OFFSET +CYFLD_LPCOMP_COMP2__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2__SIZE +CYFLD_LPCOMP_COMP2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR_SET +CYREG_LPCOMP_INTR_SET EQU 0x400a0010 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM1 +CYREG_LPCOMP_TRIM1 EQU 0x400aff00 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMA__OFFSET +CYFLD_LPCOMP_COMP1_TRIMA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMA__SIZE +CYFLD_LPCOMP_COMP1_TRIMA__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM2 +CYREG_LPCOMP_TRIM2 EQU 0x400aff04 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMB__OFFSET +CYFLD_LPCOMP_COMP1_TRIMB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMB__SIZE +CYFLD_LPCOMP_COMP1_TRIMB__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM3 +CYREG_LPCOMP_TRIM3 EQU 0x400aff08 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMA__OFFSET +CYFLD_LPCOMP_COMP2_TRIMA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMA__SIZE +CYFLD_LPCOMP_COMP2_TRIMA__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM4 +CYREG_LPCOMP_TRIM4 EQU 0x400aff0c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMB__OFFSET +CYFLD_LPCOMP_COMP2_TRIMB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMB__SIZE +CYFLD_LPCOMP_COMP2_TRIMB__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_PWR_CONTROL +CYREG_PWR_CONTROL EQU 0x400b0000 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_MODE__OFFSET +CYFLD__POWER_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_MODE__SIZE +CYFLD__POWER_MODE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_RESET +CYVAL__POWER_MODE_RESET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_ACTIVE +CYVAL__POWER_MODE_ACTIVE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_SLEEP +CYVAL__POWER_MODE_SLEEP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_DEEP_SLEEP +CYVAL__POWER_MODE_DEEP_SLEEP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_HIBERNATE +CYVAL__POWER_MODE_HIBERNATE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DEBUG_SESSION__OFFSET +CYFLD__DEBUG_SESSION__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DEBUG_SESSION__SIZE +CYFLD__DEBUG_SESSION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DEBUG_SESSION_NO_SESSION +CYVAL__DEBUG_SESSION_NO_SESSION EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DEBUG_SESSION_SESSION_ACTIVE +CYVAL__DEBUG_SESSION_SESSION_ACTIVE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LPM_READY__OFFSET +CYFLD__LPM_READY__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__LPM_READY__SIZE +CYFLD__LPM_READY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EXT_VCCD__OFFSET +CYFLD__EXT_VCCD__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD__EXT_VCCD__SIZE +CYFLD__EXT_VCCD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_ENABLE__OFFSET +CYFLD__HVMON_ENABLE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_ENABLE__SIZE +CYFLD__HVMON_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_RELOAD__OFFSET +CYFLD__HVMON_RELOAD__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_RELOAD__SIZE +CYFLD__HVMON_RELOAD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__FIMO_DISABLE__OFFSET +CYFLD__FIMO_DISABLE__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD__FIMO_DISABLE__SIZE +CYFLD__FIMO_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_DISABLE__OFFSET +CYFLD__HIBERNATE_DISABLE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_DISABLE__SIZE +CYFLD__HIBERNATE_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SHORT__OFFSET +CYFLD__LFCLK_SHORT__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SHORT__SIZE +CYFLD__LFCLK_SHORT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE__OFFSET +CYFLD__HIBERNATE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE__SIZE +CYFLD__HIBERNATE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__HIBERNATE_DEEP_SLEEP +CYVAL__HIBERNATE_DEEP_SLEEP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__HIBERNATE_HIBERNATE +CYVAL__HIBERNATE_HIBERNATE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_INTR +CYREG_PWR_INTR EQU 0x400b0004 + ENDIF + IF :LNOT::DEF:CYFLD__LVD__OFFSET +CYFLD__LVD__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LVD__SIZE +CYFLD__LVD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_INTR_MASK +CYREG_PWR_INTR_MASK EQU 0x400b0008 + ENDIF + IF :LNOT::DEF:CYREG_PWR_KEY_DELAY +CYREG_PWR_KEY_DELAY EQU 0x400b000c + ENDIF + IF :LNOT::DEF:CYFLD__WAKEUP_HOLDOFF__OFFSET +CYFLD__WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WAKEUP_HOLDOFF__SIZE +CYFLD__WAKEUP_HOLDOFF__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_CONFIG +CYREG_PWR_PWRSYS_CONFIG EQU 0x400b0010 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_EN__OFFSET +CYFLD__HIB_TEST_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_EN__SIZE +CYFLD__HIB_TEST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_REP__OFFSET +CYFLD__HIB_TEST_REP__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_REP__SIZE +CYFLD__HIB_TEST_REP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_CONFIG +CYREG_PWR_BG_CONFIG EQU 0x400b0014 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_EN__OFFSET +CYFLD__BG_DFT_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_EN__SIZE +CYFLD__BG_DFT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VREF_SEL__OFFSET +CYFLD__BG_DFT_VREF_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VREF_SEL__SIZE +CYFLD__BG_DFT_VREF_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_CORE_SEL__OFFSET +CYFLD__BG_DFT_CORE_SEL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_CORE_SEL__SIZE +CYFLD__BG_DFT_CORE_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_ICORE_SEL__OFFSET +CYFLD__BG_DFT_ICORE_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_ICORE_SEL__SIZE +CYFLD__BG_DFT_ICORE_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VCORE_SEL__OFFSET +CYFLD__BG_DFT_VCORE_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VCORE_SEL__SIZE +CYFLD__BG_DFT_VCORE_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__VREF_EN__OFFSET +CYFLD__VREF_EN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__VREF_EN__SIZE +CYFLD__VREF_EN__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_PWR_VMON_CONFIG +CYREG_PWR_VMON_CONFIG EQU 0x400b0018 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_EN__OFFSET +CYFLD__LVD_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_EN__SIZE +CYFLD__LVD_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_SEL__OFFSET +CYFLD__LVD_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_SEL__SIZE +CYFLD__LVD_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_DDFT_SEL__OFFSET +CYFLD__VMON_DDFT_SEL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_DDFT_SEL__SIZE +CYFLD__VMON_DDFT_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_ADFT_SEL__OFFSET +CYFLD__VMON_ADFT_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_ADFT_SEL__SIZE +CYFLD__VMON_ADFT_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWR_DFT_SELECT +CYREG_PWR_DFT_SELECT EQU 0x400b001c + ENDIF + IF :LNOT::DEF:CYFLD__TVMON1_SEL__OFFSET +CYFLD__TVMON1_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TVMON1_SEL__SIZE +CYFLD__TVMON1_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__TVMON2_SEL__OFFSET +CYFLD__TVMON2_SEL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__TVMON2_SEL__SIZE +CYFLD__TVMON2_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__BYPASS__OFFSET +CYFLD__BYPASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__BYPASS__SIZE +CYFLD__BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_EN__OFFSET +CYFLD__ACTIVE_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_EN__SIZE +CYFLD__ACTIVE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_INRUSH_DIS__OFFSET +CYFLD__ACTIVE_INRUSH_DIS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_INRUSH_DIS__SIZE +CYFLD__ACTIVE_INRUSH_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LPCOMP_DIS__OFFSET +CYFLD__LPCOMP_DIS__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__LPCOMP_DIS__SIZE +CYFLD__LPCOMP_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BLEED_EN__OFFSET +CYFLD__BLEED_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD__BLEED_EN__SIZE +CYFLD__BLEED_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__IPOR_EN__OFFSET +CYFLD__IPOR_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD__IPOR_EN__SIZE +CYFLD__IPOR_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_BYP__OFFSET +CYFLD__POWER_UP_RAW_BYP__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_BYP__SIZE +CYFLD__POWER_UP_RAW_BYP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_CTL__OFFSET +CYFLD__POWER_UP_RAW_CTL__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_CTL__SIZE +CYFLD__POWER_UP_RAW_CTL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_EN__OFFSET +CYFLD__DEEPSLEEP_EN__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_EN__SIZE +CYFLD__DEEPSLEEP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_BYPASS__OFFSET +CYFLD__RSVD_BYPASS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_BYPASS__SIZE +CYFLD__RSVD_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_OPEN__OFFSET +CYFLD__NWELL_OPEN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_OPEN__SIZE +CYFLD__NWELL_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_OPEN__OFFSET +CYFLD__HIBERNATE_OPEN__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_OPEN__SIZE +CYFLD__HIBERNATE_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_OPEN__OFFSET +CYFLD__DEEPSLEEP_OPEN__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_OPEN__SIZE +CYFLD__DEEPSLEEP_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_OPEN__OFFSET +CYFLD__QUIET_OPEN__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_OPEN__SIZE +CYFLD__QUIET_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_OPEN__OFFSET +CYFLD__LFCLK_OPEN__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_OPEN__SIZE +CYFLD__LFCLK_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_EN__OFFSET +CYFLD__QUIET_EN__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_EN__SIZE +CYFLD__QUIET_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_EN__OFFSET +CYFLD__BREF_EN__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_EN__SIZE +CYFLD__BREF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_OUTEN__OFFSET +CYFLD__BREF_OUTEN__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_OUTEN__SIZE +CYFLD__BREF_OUTEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_REFSW__OFFSET +CYFLD__BREF_REFSW__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_REFSW__SIZE +CYFLD__BREF_REFSW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_TESTMODE__OFFSET +CYFLD__BREF_TESTMODE__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD__BREF_TESTMODE__SIZE +CYFLD__BREF_TESTMODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_DIS__OFFSET +CYFLD__NWELL_DIS__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_DIS__SIZE +CYFLD__NWELL_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_DFT_OVR__OFFSET +CYFLD__HVMON_DFT_OVR__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_DFT_OVR__SIZE +CYFLD__HVMON_DFT_OVR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__IMO_REFGEN_DIS__OFFSET +CYFLD__IMO_REFGEN_DIS__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD__IMO_REFGEN_DIS__SIZE +CYFLD__IMO_REFGEN_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_ACTIVE__OFFSET +CYFLD__POWER_UP_ACTIVE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_ACTIVE__SIZE +CYFLD__POWER_UP_ACTIVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_HIBDPSLP__OFFSET +CYFLD__POWER_UP_HIBDPSLP__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_HIBDPSLP__SIZE +CYFLD__POWER_UP_HIBDPSLP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_DDFT_SELECT +CYREG_PWR_DDFT_SELECT EQU 0x400b0020 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT1_SEL__OFFSET +CYFLD__DDFT1_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT1_SEL__SIZE +CYFLD__DDFT1_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT2_SEL__OFFSET +CYFLD__DDFT2_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT2_SEL__SIZE +CYFLD__DDFT2_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_DFT_KEY +CYREG_PWR_DFT_KEY EQU 0x400b0024 + ENDIF + IF :LNOT::DEF:CYFLD__KEY16__OFFSET +CYFLD__KEY16__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__KEY16__SIZE +CYFLD__KEY16__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__HBOD_OFF_AWAKE__OFFSET +CYFLD__HBOD_OFF_AWAKE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__HBOD_OFF_AWAKE__SIZE +CYFLD__HBOD_OFF_AWAKE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BODS_OFF__OFFSET +CYFLD__BODS_OFF__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__BODS_OFF__SIZE +CYFLD__BODS_OFF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_MODE__OFFSET +CYFLD__DFT_MODE__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_MODE__SIZE +CYFLD__DFT_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__IO_DISABLE_BYPASS__OFFSET +CYFLD__IO_DISABLE_BYPASS__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__IO_DISABLE_BYPASS__SIZE +CYFLD__IO_DISABLE_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_PD__OFFSET +CYFLD__VMON_PD__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_PD__SIZE +CYFLD__VMON_PD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BOD_KEY +CYREG_PWR_BOD_KEY EQU 0x400b0028 + ENDIF + IF :LNOT::DEF:CYREG_PWR_STOP +CYREG_PWR_STOP EQU 0x400b002c + ENDIF + IF :LNOT::DEF:CYFLD__TOKEN__OFFSET +CYFLD__TOKEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TOKEN__SIZE +CYFLD__TOKEN__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__UNLOCK__OFFSET +CYFLD__UNLOCK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__UNLOCK__SIZE +CYFLD__UNLOCK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__POLARITY__OFFSET +CYFLD__POLARITY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__POLARITY__SIZE +CYFLD__POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__FREEZE__OFFSET +CYFLD__FREEZE__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__FREEZE__SIZE +CYFLD__FREEZE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__STOP__OFFSET +CYFLD__STOP__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__STOP__SIZE +CYFLD__STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT +CYREG_CLK_SELECT EQU 0x400b0100 + ENDIF + IF :LNOT::DEF:CYFLD__DIRECT_SEL__OFFSET +CYFLD__DIRECT_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DIRECT_SEL__SIZE +CYFLD__DIRECT_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_IMO +CYVAL__DIRECT_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_EXTCLK +CYVAL__DIRECT_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_ECO +CYVAL__DIRECT_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI0 +CYVAL__DIRECT_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI1 +CYVAL__DIRECT_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI2 +CYVAL__DIRECT_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI3 +CYVAL__DIRECT_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DBL_SEL__OFFSET +CYFLD__DBL_SEL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__DBL_SEL__SIZE +CYFLD__DBL_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_IMO +CYVAL__DBL_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_EXTCLK +CYVAL__DBL_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_ECO +CYVAL__DBL_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI0 +CYVAL__DBL_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI1 +CYVAL__DBL_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI2 +CYVAL__DBL_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI3 +CYVAL__DBL_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__PLL_SEL__OFFSET +CYFLD__PLL_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__PLL_SEL__SIZE +CYFLD__PLL_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_IMO +CYVAL__PLL_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_EXTCLK +CYVAL__PLL_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_ECO +CYVAL__PLL_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DPLL +CYVAL__PLL_SEL_DPLL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI0 +CYVAL__PLL_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI1 +CYVAL__PLL_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI2 +CYVAL__PLL_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI3 +CYVAL__PLL_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DPLLIN_SEL__OFFSET +CYFLD__DPLLIN_SEL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__DPLLIN_SEL__SIZE +CYFLD__DPLLIN_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_IMO +CYVAL__DPLLIN_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_EXTCLK +CYVAL__DPLLIN_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_ECO +CYVAL__DPLLIN_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI0 +CYVAL__DPLLIN_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI1 +CYVAL__DPLLIN_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI2 +CYVAL__DPLLIN_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI3 +CYVAL__DPLLIN_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DPLLREF_SEL__OFFSET +CYFLD__DPLLREF_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD__DPLLREF_SEL__SIZE +CYFLD__DPLLREF_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI0 +CYVAL__DPLLREF_SEL_DSI0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI1 +CYVAL__DPLLREF_SEL_DSI1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI2 +CYVAL__DPLLREF_SEL_DSI2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI3 +CYVAL__DPLLREF_SEL_DSI3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_LOCK__OFFSET +CYFLD__WDT_LOCK__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD__WDT_LOCK__SIZE +CYFLD__WDT_LOCK__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_NO_CHG +CYVAL__WDT_LOCK_NO_CHG EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_CLR0 +CYVAL__WDT_LOCK_CLR0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_CLR1 +CYVAL__WDT_LOCK_CLR1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_SET01 +CYVAL__WDT_LOCK_SET01 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_SEL__OFFSET +CYFLD__HFCLK_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_SEL__SIZE +CYFLD__HFCLK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_DIRECT_SEL +CYVAL__HFCLK_SEL_DIRECT_SEL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_DBL +CYVAL__HFCLK_SEL_DBL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_PLL +CYVAL__HFCLK_SEL_PLL EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HALF_EN__OFFSET +CYFLD__HALF_EN__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__HALF_EN__SIZE +CYFLD__HALF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__SYSCLK_DIV__OFFSET +CYFLD__SYSCLK_DIV__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__SYSCLK_DIV__SIZE +CYFLD__SYSCLK_DIV__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_NO_DIV +CYVAL__SYSCLK_DIV_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_2 +CYVAL__SYSCLK_DIV_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_4 +CYVAL__SYSCLK_DIV_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_8 +CYVAL__SYSCLK_DIV_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_16 +CYVAL__SYSCLK_DIV_DIV_BY_16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_32 +CYVAL__SYSCLK_DIV_DIV_BY_32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_64 +CYVAL__SYSCLK_DIV_DIV_BY_64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_128 +CYVAL__SYSCLK_DIV_DIV_BY_128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_CLK_ILO_CONFIG +CYREG_CLK_ILO_CONFIG EQU 0x400b0104 + ENDIF + IF :LNOT::DEF:CYFLD__PD_MODE__OFFSET +CYFLD__PD_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__PD_MODE__SIZE +CYFLD__PD_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__PD_MODE_SLEEP +CYVAL__PD_MODE_SLEEP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__PD_MODE_COMA +CYVAL__PD_MODE_COMA EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TURBO__OFFSET +CYFLD__TURBO__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TURBO__SIZE +CYFLD__TURBO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__SATBIAS__OFFSET +CYFLD__SATBIAS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__SATBIAS__SIZE +CYFLD__SATBIAS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SATBIAS_SATURATED +CYVAL__SATBIAS_SATURATED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SATBIAS_SUBTHRESHOLD +CYVAL__SATBIAS_SUBTHRESHOLD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__ENABLE__OFFSET +CYFLD__ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__ENABLE__SIZE +CYFLD__ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_CONFIG +CYREG_CLK_IMO_CONFIG EQU 0x400b0108 + ENDIF + IF :LNOT::DEF:CYFLD__FLASHPUMP_SEL__OFFSET +CYFLD__FLASHPUMP_SEL__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD__FLASHPUMP_SEL__SIZE +CYFLD__FLASHPUMP_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__FLASHPUMP_SEL_GND +CYVAL__FLASHPUMP_SEL_GND EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__FLASHPUMP_SEL_CLK36 +CYVAL__FLASHPUMP_SEL_CLK36 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EN_FASTBIAS__OFFSET +CYFLD__EN_FASTBIAS__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD__EN_FASTBIAS__SIZE +CYFLD__EN_FASTBIAS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_FASTBIAS__OFFSET +CYFLD__TEST_FASTBIAS__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_FASTBIAS__SIZE +CYFLD__TEST_FASTBIAS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__PUMP_SEL__OFFSET +CYFLD__PUMP_SEL__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD__PUMP_SEL__SIZE +CYFLD__PUMP_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_GND +CYVAL__PUMP_SEL_GND EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_IMO +CYVAL__PUMP_SEL_IMO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_DBL +CYVAL__PUMP_SEL_DBL EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_CLK36 +CYVAL__PUMP_SEL_CLK36 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_FF1 +CYVAL__PUMP_SEL_FF1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_USB_MODE__OFFSET +CYFLD__TEST_USB_MODE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__TEST_USB_MODE__SIZE +CYFLD__TEST_USB_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK36__OFFSET +CYFLD__EN_CLK36__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK36__SIZE +CYFLD__EN_CLK36__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK2X__OFFSET +CYFLD__EN_CLK2X__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK2X__SIZE +CYFLD__EN_CLK2X__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_SPREAD +CYREG_CLK_IMO_SPREAD EQU 0x400b010c + ENDIF + IF :LNOT::DEF:CYFLD__SS_VALUE__OFFSET +CYFLD__SS_VALUE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__SS_VALUE__SIZE +CYFLD__SS_VALUE__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__SS_MAX__OFFSET +CYFLD__SS_MAX__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__SS_MAX__SIZE +CYFLD__SS_MAX__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__SS_RANGE__OFFSET +CYFLD__SS_RANGE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__SS_RANGE__SIZE +CYFLD__SS_RANGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SS_RANGE_M1 +CYVAL__SS_RANGE_M1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SS_RANGE_M2 +CYVAL__SS_RANGE_M2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SS_RANGE_M4 +CYVAL__SS_RANGE_M4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__SS_MODE__OFFSET +CYFLD__SS_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__SS_MODE__SIZE +CYFLD__SS_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_OFF +CYVAL__SS_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_TRIANGLE +CYVAL__SS_MODE_TRIANGLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_LFSR +CYVAL__SS_MODE_LFSR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_DSI +CYVAL__SS_MODE_DSI EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DFT_SELECT +CYREG_CLK_DFT_SELECT EQU 0x400b0110 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL1__OFFSET +CYFLD__DFT_SEL1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL1__SIZE +CYFLD__DFT_SEL1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_NC +CYVAL__DFT_SEL1_NC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_ILO +CYVAL__DFT_SEL1_ILO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_WCO +CYVAL__DFT_SEL1_WCO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_IMO +CYVAL__DFT_SEL1_IMO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_ECO +CYVAL__DFT_SEL1_ECO EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_PLL +CYVAL__DFT_SEL1_PLL EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_DPLL_OUT +CYVAL__DFT_SEL1_DPLL_OUT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_DPLL_REF +CYVAL__DFT_SEL1_DPLL_REF EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_DBL +CYVAL__DFT_SEL1_DBL EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_IMO2X +CYVAL__DFT_SEL1_IMO2X EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_IMO36 +CYVAL__DFT_SEL1_IMO36 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_HFCLK +CYVAL__DFT_SEL1_HFCLK EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_LFCLK +CYVAL__DFT_SEL1_LFCLK EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SYSCLK +CYVAL__DFT_SEL1_SYSCLK EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_EXTCLK +CYVAL__DFT_SEL1_EXTCLK EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_HALFSYSCLK +CYVAL__DFT_SEL1_HALFSYSCLK EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV1__OFFSET +CYFLD__DFT_DIV1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV1__SIZE +CYFLD__DFT_DIV1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_NO_DIV +CYVAL__DFT_DIV1_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_2 +CYVAL__DFT_DIV1_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_4 +CYVAL__DFT_DIV1_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_8 +CYVAL__DFT_DIV1_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL2__OFFSET +CYFLD__DFT_SEL2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL2__SIZE +CYFLD__DFT_SEL2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_NC +CYVAL__DFT_SEL2_NC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_ILO +CYVAL__DFT_SEL2_ILO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_WCO +CYVAL__DFT_SEL2_WCO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_IMO +CYVAL__DFT_SEL2_IMO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_ECO +CYVAL__DFT_SEL2_ECO EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_PLL +CYVAL__DFT_SEL2_PLL EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_DPLL_OUT +CYVAL__DFT_SEL2_DPLL_OUT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_DPLL_REF +CYVAL__DFT_SEL2_DPLL_REF EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_DBL +CYVAL__DFT_SEL2_DBL EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_IMO2X +CYVAL__DFT_SEL2_IMO2X EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_IMO36 +CYVAL__DFT_SEL2_IMO36 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_HFCLK +CYVAL__DFT_SEL2_HFCLK EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_LFCLK +CYVAL__DFT_SEL2_LFCLK EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_SYSCLK +CYVAL__DFT_SEL2_SYSCLK EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_EXTCLK +CYVAL__DFT_SEL2_EXTCLK EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_HALFSYSCLK +CYVAL__DFT_SEL2_HALFSYSCLK EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV2__OFFSET +CYFLD__DFT_DIV2__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV2__SIZE +CYFLD__DFT_DIV2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_NO_DIV +CYVAL__DFT_DIV2_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_DIV_BY_2 +CYVAL__DFT_DIV2_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_DIV_BY_4 +CYVAL__DFT_DIV2_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_DIV_BY_8 +CYVAL__DFT_DIV2_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CTRLOW +CYREG_WDT_CTRLOW EQU 0x400b0200 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR0__OFFSET +CYFLD__WDT_CTR0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR0__SIZE +CYFLD__WDT_CTR0__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR1__OFFSET +CYFLD__WDT_CTR1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR1__SIZE +CYFLD__WDT_CTR1__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CTRHIGH +CYREG_WDT_CTRHIGH EQU 0x400b0204 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR2__OFFSET +CYFLD__WDT_CTR2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR2__SIZE +CYFLD__WDT_CTR2__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_WDT_MATCH +CYREG_WDT_MATCH EQU 0x400b0208 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH0__OFFSET +CYFLD__WDT_MATCH0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH0__SIZE +CYFLD__WDT_MATCH0__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH1__OFFSET +CYFLD__WDT_MATCH1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH1__SIZE +CYFLD__WDT_MATCH1__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CONFIG +CYREG_WDT_CONFIG EQU 0x400b020c + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE0__OFFSET +CYFLD__WDT_MODE0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE0__SIZE +CYFLD__WDT_MODE0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_NOTHING +CYVAL__WDT_MODE0_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_INT +CYVAL__WDT_MODE0_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_RESET +CYVAL__WDT_MODE0_RESET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_INT_THEN_RESET +CYVAL__WDT_MODE0_INT_THEN_RESET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR0__OFFSET +CYFLD__WDT_CLEAR0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR0__SIZE +CYFLD__WDT_CLEAR0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE0_1__OFFSET +CYFLD__WDT_CASCADE0_1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE0_1__SIZE +CYFLD__WDT_CASCADE0_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE1__OFFSET +CYFLD__WDT_MODE1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE1__SIZE +CYFLD__WDT_MODE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_NOTHING +CYVAL__WDT_MODE1_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_INT +CYVAL__WDT_MODE1_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_RESET +CYVAL__WDT_MODE1_RESET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_INT_THEN_RESET +CYVAL__WDT_MODE1_INT_THEN_RESET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR1__OFFSET +CYFLD__WDT_CLEAR1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR1__SIZE +CYFLD__WDT_CLEAR1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE1_2__OFFSET +CYFLD__WDT_CASCADE1_2__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE1_2__SIZE +CYFLD__WDT_CASCADE1_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE2__OFFSET +CYFLD__WDT_MODE2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE2__SIZE +CYFLD__WDT_MODE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE2_NOTHING +CYVAL__WDT_MODE2_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE2_INT +CYVAL__WDT_MODE2_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_BITS2__OFFSET +CYFLD__WDT_BITS2__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_BITS2__SIZE +CYFLD__WDT_BITS2__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SEL__OFFSET +CYFLD__LFCLK_SEL__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SEL__SIZE +CYFLD__LFCLK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CONTROL +CYREG_WDT_CONTROL EQU 0x400b0210 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE0__OFFSET +CYFLD__WDT_ENABLE0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE0__SIZE +CYFLD__WDT_ENABLE0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED0__OFFSET +CYFLD__WDT_ENABLED0__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED0__SIZE +CYFLD__WDT_ENABLED0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT0__OFFSET +CYFLD__WDT_INT0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT0__SIZE +CYFLD__WDT_INT0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET0__OFFSET +CYFLD__WDT_RESET0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET0__SIZE +CYFLD__WDT_RESET0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE1__OFFSET +CYFLD__WDT_ENABLE1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE1__SIZE +CYFLD__WDT_ENABLE1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED1__OFFSET +CYFLD__WDT_ENABLED1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED1__SIZE +CYFLD__WDT_ENABLED1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT1__OFFSET +CYFLD__WDT_INT1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT1__SIZE +CYFLD__WDT_INT1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET1__OFFSET +CYFLD__WDT_RESET1__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET1__SIZE +CYFLD__WDT_RESET1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE2__OFFSET +CYFLD__WDT_ENABLE2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE2__SIZE +CYFLD__WDT_ENABLE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED2__OFFSET +CYFLD__WDT_ENABLED2__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED2__SIZE +CYFLD__WDT_ENABLED2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT2__OFFSET +CYFLD__WDT_INT2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT2__SIZE +CYFLD__WDT_INT2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET2__OFFSET +CYFLD__WDT_RESET2__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET2__SIZE +CYFLD__WDT_RESET2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_RES_CAUSE +CYREG_RES_CAUSE EQU 0x400b0300 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_WDT__OFFSET +CYFLD__RESET_WDT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_WDT__SIZE +CYFLD__RESET_WDT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_DSBOD__OFFSET +CYFLD__RESET_DSBOD__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_DSBOD__SIZE +CYFLD__RESET_DSBOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_LOCKUP__OFFSET +CYFLD__RESET_LOCKUP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_LOCKUP__SIZE +CYFLD__RESET_LOCKUP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PROT_FAULT__OFFSET +CYFLD__RESET_PROT_FAULT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PROT_FAULT__SIZE +CYFLD__RESET_PROT_FAULT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_SOFT__OFFSET +CYFLD__RESET_SOFT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_SOFT__SIZE +CYFLD__RESET_SOFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_HVBOD__OFFSET +CYFLD__RESET_HVBOD__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_HVBOD__SIZE +CYFLD__RESET_HVBOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PBOD__OFFSET +CYFLD__RESET_PBOD__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PBOD__SIZE +CYFLD__RESET_PBOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_XRES__OFFSET +CYFLD__RESET_XRES__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_XRES__SIZE +CYFLD__RESET_XRES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM1 +CYREG_PWR_PWRSYS_TRIM1 EQU 0x400bff00 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_BIAS_TRIM__OFFSET +CYFLD__HIB_BIAS_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_BIAS_TRIM__SIZE +CYFLD__HIB_BIAS_TRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TURBO_THRESH__OFFSET +CYFLD__BOD_TURBO_THRESH__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TURBO_THRESH__SIZE +CYFLD__BOD_TURBO_THRESH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TRIM_TRIP__OFFSET +CYFLD__BOD_TRIM_TRIP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TRIM_TRIP__SIZE +CYFLD__BOD_TRIM_TRIP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM2 +CYREG_PWR_PWRSYS_TRIM2 EQU 0x400bff04 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_LOAD__OFFSET +CYFLD__LFCLK_TRIM_LOAD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_LOAD__SIZE +CYFLD__LFCLK_TRIM_LOAD__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET +CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_VOLTAGE__SIZE +CYFLD__LFCLK_TRIM_VOLTAGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LOAD__OFFSET +CYFLD__DPSLP_TRIM_LOAD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LOAD__SIZE +CYFLD__DPSLP_TRIM_LOAD__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET +CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LEAKAGE__SIZE +CYFLD__DPSLP_TRIM_LEAKAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET +CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_VOLTAGE__SIZE +CYFLD__DPSLP_TRIM_VOLTAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM3 +CYREG_PWR_PWRSYS_TRIM3 EQU 0x400bff08 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_TRIM__OFFSET +CYFLD__NWELL_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_TRIM__SIZE +CYFLD__NWELL_TRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_TRIM__OFFSET +CYFLD__QUIET_TRIM__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_TRIM__SIZE +CYFLD__QUIET_TRIM__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM4 +CYREG_PWR_PWRSYS_TRIM4 EQU 0x400bff0c + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_NWELL__OFFSET +CYFLD__HIB_TRIM_NWELL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_NWELL__SIZE +CYFLD__HIB_TRIM_NWELL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_LEAKAGE__OFFSET +CYFLD__HIB_TRIM_LEAKAGE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_LEAKAGE__SIZE +CYFLD__HIB_TRIM_LEAKAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_VOLTAGE__OFFSET +CYFLD__HIB_TRIM_VOLTAGE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_VOLTAGE__SIZE +CYFLD__HIB_TRIM_VOLTAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_REFERENCE__OFFSET +CYFLD__HIB_TRIM_REFERENCE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_REFERENCE__SIZE +CYFLD__HIB_TRIM_REFERENCE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM1 +CYREG_PWR_BG_TRIM1 EQU 0x400bff10 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_MAIN__OFFSET +CYFLD__INL_TRIM_MAIN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_MAIN__SIZE +CYFLD__INL_TRIM_MAIN__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_MAIN__OFFSET +CYFLD__INL_CROSS_MAIN__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_MAIN__SIZE +CYFLD__INL_CROSS_MAIN__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM2 +CYREG_PWR_BG_TRIM2 EQU 0x400bff14 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_SLOPE__OFFSET +CYFLD__VCTAT_SLOPE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_SLOPE__SIZE +CYFLD__VCTAT_SLOPE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE__OFFSET +CYFLD__VCTAT_VOLTAGE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE__SIZE +CYFLD__VCTAT_VOLTAGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_ENABLE__OFFSET +CYFLD__VCTAT_ENABLE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_ENABLE__SIZE +CYFLD__VCTAT_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE_MSB__OFFSET +CYFLD__VCTAT_VOLTAGE_MSB__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE_MSB__SIZE +CYFLD__VCTAT_VOLTAGE_MSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM3 +CYREG_PWR_BG_TRIM3 EQU 0x400bff18 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_IMO__OFFSET +CYFLD__INL_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_IMO__SIZE +CYFLD__INL_TRIM_IMO__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_IMO__OFFSET +CYFLD__INL_CROSS_IMO__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_IMO__SIZE +CYFLD__INL_CROSS_IMO__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM4 +CYREG_PWR_BG_TRIM4 EQU 0x400bff1c + ENDIF + IF :LNOT::DEF:CYFLD__ABS_TRIM_IMO__OFFSET +CYFLD__ABS_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__ABS_TRIM_IMO__SIZE +CYFLD__ABS_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM5 +CYREG_PWR_BG_TRIM5 EQU 0x400bff20 + ENDIF + IF :LNOT::DEF:CYFLD__TMPCO_TRIM_IMO__OFFSET +CYFLD__TMPCO_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TMPCO_TRIM_IMO__SIZE +CYFLD__TMPCO_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CLK_ILO_TRIM +CYREG_CLK_ILO_TRIM EQU 0x400bff24 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM__OFFSET +CYFLD__TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM__SIZE +CYFLD__TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__COARSE_TRIM__OFFSET +CYFLD__COARSE_TRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__COARSE_TRIM__SIZE +CYFLD__COARSE_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM1 +CYREG_CLK_IMO_TRIM1 EQU 0x400bff28 + ENDIF + IF :LNOT::DEF:CYFLD__OFFSET__OFFSET +CYFLD__OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__OFFSET__SIZE +CYFLD__OFFSET__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM2 +CYREG_CLK_IMO_TRIM2 EQU 0x400bff2c + ENDIF + IF :LNOT::DEF:CYFLD__FREQ__OFFSET +CYFLD__FREQ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__FREQ__SIZE +CYFLD__FREQ__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM3 +CYREG_CLK_IMO_TRIM3 EQU 0x400bff30 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM_CLK36__OFFSET +CYFLD__TRIM_CLK36__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM_CLK36__SIZE +CYFLD__TRIM_CLK36__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM4 +CYREG_CLK_IMO_TRIM4 EQU 0x400bff34 + ENDIF + IF :LNOT::DEF:CYFLD__GAIN__OFFSET +CYFLD__GAIN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__GAIN__SIZE +CYFLD__GAIN__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__FSOFFSET__OFFSET +CYFLD__FSOFFSET__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__FSOFFSET__SIZE +CYFLD__FSOFFSET__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_PWR_RSVD_TRIM +CYREG_PWR_RSVD_TRIM EQU 0x400bff38 + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_TRIM__OFFSET +CYFLD__RSVD_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_TRIM__SIZE +CYFLD__RSVD_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_SPCIF_BASE +CYDEV_SPCIF_BASE EQU 0x400e0000 + ENDIF + IF :LNOT::DEF:CYDEV_SPCIF_SIZE +CYDEV_SPCIF_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_GEOMETRY +CYREG_SPCIF_GEOMETRY EQU 0x400e0000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH__OFFSET +CYFLD_SPCIF_FLASH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH__SIZE +CYFLD_SPCIF_FLASH__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_SFLASH__OFFSET +CYFLD_SPCIF_SFLASH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_SFLASH__SIZE +CYFLD_SPCIF_SFLASH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NUM_FLASH__OFFSET +CYFLD_SPCIF_NUM_FLASH__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NUM_FLASH__SIZE +CYFLD_SPCIF_NUM_FLASH__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH_ROW__OFFSET +CYFLD_SPCIF_FLASH_ROW__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH_ROW__SIZE +CYFLD_SPCIF_FLASH_ROW__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NVL__OFFSET +CYFLD_SPCIF_NVL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NVL__SIZE +CYFLD_SPCIF_NVL__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DE_CPD_LP__OFFSET +CYFLD_SPCIF_DE_CPD_LP__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DE_CPD_LP__SIZE +CYFLD_SPCIF_DE_CPD_LP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_NVL_WR_DATA +CYREG_SPCIF_NVL_WR_DATA EQU 0x400e001c + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DATA__OFFSET +CYFLD_SPCIF_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DATA__SIZE +CYFLD_SPCIF_DATA__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_BASE +CYDEV_UDB_BASE EQU 0x400f0000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_SIZE +CYDEV_UDB_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W8_BASE +CYDEV_UDB_W8_BASE EQU 0x400f0000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W8_SIZE +CYDEV_UDB_W8_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_00 +CYREG_UDB_W8_A0_00 EQU 0x400f0000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A0__OFFSET +CYFLD_UDB_W8_A0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A0__SIZE +CYFLD_UDB_W8_A0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_01 +CYREG_UDB_W8_A0_01 EQU 0x400f0001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_02 +CYREG_UDB_W8_A0_02 EQU 0x400f0002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_03 +CYREG_UDB_W8_A0_03 EQU 0x400f0003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_00 +CYREG_UDB_W8_A1_00 EQU 0x400f0010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A1__OFFSET +CYFLD_UDB_W8_A1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A1__SIZE +CYFLD_UDB_W8_A1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_01 +CYREG_UDB_W8_A1_01 EQU 0x400f0011 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_02 +CYREG_UDB_W8_A1_02 EQU 0x400f0012 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_03 +CYREG_UDB_W8_A1_03 EQU 0x400f0013 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_00 +CYREG_UDB_W8_D0_00 EQU 0x400f0020 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D0__OFFSET +CYFLD_UDB_W8_D0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D0__SIZE +CYFLD_UDB_W8_D0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_01 +CYREG_UDB_W8_D0_01 EQU 0x400f0021 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_02 +CYREG_UDB_W8_D0_02 EQU 0x400f0022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_03 +CYREG_UDB_W8_D0_03 EQU 0x400f0023 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_00 +CYREG_UDB_W8_D1_00 EQU 0x400f0030 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D1__OFFSET +CYFLD_UDB_W8_D1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D1__SIZE +CYFLD_UDB_W8_D1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_01 +CYREG_UDB_W8_D1_01 EQU 0x400f0031 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_02 +CYREG_UDB_W8_D1_02 EQU 0x400f0032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_03 +CYREG_UDB_W8_D1_03 EQU 0x400f0033 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_00 +CYREG_UDB_W8_F0_00 EQU 0x400f0040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F0__OFFSET +CYFLD_UDB_W8_F0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F0__SIZE +CYFLD_UDB_W8_F0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_01 +CYREG_UDB_W8_F0_01 EQU 0x400f0041 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_02 +CYREG_UDB_W8_F0_02 EQU 0x400f0042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_03 +CYREG_UDB_W8_F0_03 EQU 0x400f0043 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_00 +CYREG_UDB_W8_F1_00 EQU 0x400f0050 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F1__OFFSET +CYFLD_UDB_W8_F1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F1__SIZE +CYFLD_UDB_W8_F1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_01 +CYREG_UDB_W8_F1_01 EQU 0x400f0051 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_02 +CYREG_UDB_W8_F1_02 EQU 0x400f0052 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_03 +CYREG_UDB_W8_F1_03 EQU 0x400f0053 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_00 +CYREG_UDB_W8_ST_00 EQU 0x400f0060 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_ST__OFFSET +CYFLD_UDB_W8_ST__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_ST__SIZE +CYFLD_UDB_W8_ST__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_01 +CYREG_UDB_W8_ST_01 EQU 0x400f0061 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_02 +CYREG_UDB_W8_ST_02 EQU 0x400f0062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_03 +CYREG_UDB_W8_ST_03 EQU 0x400f0063 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_00 +CYREG_UDB_W8_CTL_00 EQU 0x400f0070 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CTL__OFFSET +CYFLD_UDB_W8_CTL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CTL__SIZE +CYFLD_UDB_W8_CTL__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_01 +CYREG_UDB_W8_CTL_01 EQU 0x400f0071 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_02 +CYREG_UDB_W8_CTL_02 EQU 0x400f0072 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_03 +CYREG_UDB_W8_CTL_03 EQU 0x400f0073 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_00 +CYREG_UDB_W8_MSK_00 EQU 0x400f0080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_MSK__OFFSET +CYFLD_UDB_W8_MSK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_MSK__SIZE +CYFLD_UDB_W8_MSK__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_01 +CYREG_UDB_W8_MSK_01 EQU 0x400f0081 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_02 +CYREG_UDB_W8_MSK_02 EQU 0x400f0082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_03 +CYREG_UDB_W8_MSK_03 EQU 0x400f0083 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_00 +CYREG_UDB_W8_ACTL_00 EQU 0x400f0090 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_CLR__OFFSET +CYFLD_UDB_W8_FIFO0_CLR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_CLR__SIZE +CYFLD_UDB_W8_FIFO0_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_CLR_NORMAL +CYVAL_UDB_W8_FIFO0_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_CLR_CLEAR +CYVAL_UDB_W8_FIFO0_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_CLR__OFFSET +CYFLD_UDB_W8_FIFO1_CLR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_CLR__SIZE +CYFLD_UDB_W8_FIFO1_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_CLR_NORMAL +CYVAL_UDB_W8_FIFO1_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_CLR_CLEAR +CYVAL_UDB_W8_FIFO1_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_LVL__OFFSET +CYFLD_UDB_W8_FIFO0_LVL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_LVL__SIZE +CYFLD_UDB_W8_FIFO0_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_LVL_NORMAL +CYVAL_UDB_W8_FIFO0_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_LVL_MID +CYVAL_UDB_W8_FIFO0_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_LVL__OFFSET +CYFLD_UDB_W8_FIFO1_LVL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_LVL__SIZE +CYFLD_UDB_W8_FIFO1_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_LVL_NORMAL +CYVAL_UDB_W8_FIFO1_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_LVL_MID +CYVAL_UDB_W8_FIFO1_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_INT_EN__OFFSET +CYFLD_UDB_W8_INT_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_INT_EN__SIZE +CYFLD_UDB_W8_INT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_INT_EN_DISABLE +CYVAL_UDB_W8_INT_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_INT_EN_ENABLE +CYVAL_UDB_W8_INT_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CNT_START__OFFSET +CYFLD_UDB_W8_CNT_START__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CNT_START__SIZE +CYFLD_UDB_W8_CNT_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_CNT_START_DISABLE +CYVAL_UDB_W8_CNT_START_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_CNT_START_ENABLE +CYVAL_UDB_W8_CNT_START_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_01 +CYREG_UDB_W8_ACTL_01 EQU 0x400f0091 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_02 +CYREG_UDB_W8_ACTL_02 EQU 0x400f0092 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_03 +CYREG_UDB_W8_ACTL_03 EQU 0x400f0093 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_00 +CYREG_UDB_W8_MC_00 EQU 0x400f00a0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD0_MC__OFFSET +CYFLD_UDB_W8_PLD0_MC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD0_MC__SIZE +CYFLD_UDB_W8_PLD0_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD1_MC__OFFSET +CYFLD_UDB_W8_PLD1_MC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD1_MC__SIZE +CYFLD_UDB_W8_PLD1_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_01 +CYREG_UDB_W8_MC_01 EQU 0x400f00a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_02 +CYREG_UDB_W8_MC_02 EQU 0x400f00a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_03 +CYREG_UDB_W8_MC_03 EQU 0x400f00a3 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_CAT16_BASE +CYDEV_UDB_CAT16_BASE EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_CAT16_SIZE +CYDEV_UDB_CAT16_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_00 +CYREG_UDB_CAT16_A_00 EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A0__OFFSET +CYFLD_UDB_CAT16_A0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A0__SIZE +CYFLD_UDB_CAT16_A0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A1__OFFSET +CYFLD_UDB_CAT16_A1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A1__SIZE +CYFLD_UDB_CAT16_A1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_01 +CYREG_UDB_CAT16_A_01 EQU 0x400f1002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_02 +CYREG_UDB_CAT16_A_02 EQU 0x400f1004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_03 +CYREG_UDB_CAT16_A_03 EQU 0x400f1006 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_00 +CYREG_UDB_CAT16_D_00 EQU 0x400f1040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D0__OFFSET +CYFLD_UDB_CAT16_D0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D0__SIZE +CYFLD_UDB_CAT16_D0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D1__OFFSET +CYFLD_UDB_CAT16_D1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D1__SIZE +CYFLD_UDB_CAT16_D1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_01 +CYREG_UDB_CAT16_D_01 EQU 0x400f1042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_02 +CYREG_UDB_CAT16_D_02 EQU 0x400f1044 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_03 +CYREG_UDB_CAT16_D_03 EQU 0x400f1046 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_00 +CYREG_UDB_CAT16_F_00 EQU 0x400f1080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F0__OFFSET +CYFLD_UDB_CAT16_F0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F0__SIZE +CYFLD_UDB_CAT16_F0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F1__OFFSET +CYFLD_UDB_CAT16_F1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F1__SIZE +CYFLD_UDB_CAT16_F1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_01 +CYREG_UDB_CAT16_F_01 EQU 0x400f1082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_02 +CYREG_UDB_CAT16_F_02 EQU 0x400f1084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_03 +CYREG_UDB_CAT16_F_03 EQU 0x400f1086 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_00 +CYREG_UDB_CAT16_CTL_ST_00 EQU 0x400f10c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_ST__OFFSET +CYFLD_UDB_CAT16_ST__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_ST__SIZE +CYFLD_UDB_CAT16_ST__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CTL__OFFSET +CYFLD_UDB_CAT16_CTL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CTL__SIZE +CYFLD_UDB_CAT16_CTL__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_01 +CYREG_UDB_CAT16_CTL_ST_01 EQU 0x400f10c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_02 +CYREG_UDB_CAT16_CTL_ST_02 EQU 0x400f10c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_03 +CYREG_UDB_CAT16_CTL_ST_03 EQU 0x400f10c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_00 +CYREG_UDB_CAT16_ACTL_MSK_00 EQU 0x400f1100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_MSK__OFFSET +CYFLD_UDB_CAT16_MSK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_MSK__SIZE +CYFLD_UDB_CAT16_MSK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET +CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_CLR__SIZE +CYFLD_UDB_CAT16_FIFO0_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL +CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR +CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET +CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_CLR__SIZE +CYFLD_UDB_CAT16_FIFO1_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL +CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR +CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET +CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_LVL__SIZE +CYFLD_UDB_CAT16_FIFO0_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL +CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_LVL_MID +CYVAL_UDB_CAT16_FIFO0_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET +CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_LVL__SIZE +CYFLD_UDB_CAT16_FIFO1_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL +CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_LVL_MID +CYVAL_UDB_CAT16_FIFO1_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_INT_EN__OFFSET +CYFLD_UDB_CAT16_INT_EN__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_INT_EN__SIZE +CYFLD_UDB_CAT16_INT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_INT_EN_DISABLE +CYVAL_UDB_CAT16_INT_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_INT_EN_ENABLE +CYVAL_UDB_CAT16_INT_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CNT_START__OFFSET +CYFLD_UDB_CAT16_CNT_START__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CNT_START__SIZE +CYFLD_UDB_CAT16_CNT_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_CNT_START_DISABLE +CYVAL_UDB_CAT16_CNT_START_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_CNT_START_ENABLE +CYVAL_UDB_CAT16_CNT_START_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_01 +CYREG_UDB_CAT16_ACTL_MSK_01 EQU 0x400f1102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_02 +CYREG_UDB_CAT16_ACTL_MSK_02 EQU 0x400f1104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_03 +CYREG_UDB_CAT16_ACTL_MSK_03 EQU 0x400f1106 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_00 +CYREG_UDB_CAT16_MC_00 EQU 0x400f1140 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD0_MC__OFFSET +CYFLD_UDB_CAT16_PLD0_MC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD0_MC__SIZE +CYFLD_UDB_CAT16_PLD0_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD1_MC__OFFSET +CYFLD_UDB_CAT16_PLD1_MC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD1_MC__SIZE +CYFLD_UDB_CAT16_PLD1_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_01 +CYREG_UDB_CAT16_MC_01 EQU 0x400f1142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_02 +CYREG_UDB_CAT16_MC_02 EQU 0x400f1144 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_03 +CYREG_UDB_CAT16_MC_03 EQU 0x400f1146 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W16_BASE +CYDEV_UDB_W16_BASE EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W16_SIZE +CYDEV_UDB_W16_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A0_00 +CYREG_UDB_W16_A0_00 EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_LS__OFFSET +CYFLD_UDB_W16_A0_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_LS__SIZE +CYFLD_UDB_W16_A0_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_MS__OFFSET +CYFLD_UDB_W16_A0_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_MS__SIZE +CYFLD_UDB_W16_A0_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A0_01 +CYREG_UDB_W16_A0_01 EQU 0x400f1002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A0_02 +CYREG_UDB_W16_A0_02 EQU 0x400f1004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A1_00 +CYREG_UDB_W16_A1_00 EQU 0x400f1020 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_LS__OFFSET +CYFLD_UDB_W16_A1_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_LS__SIZE +CYFLD_UDB_W16_A1_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_MS__OFFSET +CYFLD_UDB_W16_A1_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_MS__SIZE +CYFLD_UDB_W16_A1_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A1_01 +CYREG_UDB_W16_A1_01 EQU 0x400f1022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A1_02 +CYREG_UDB_W16_A1_02 EQU 0x400f1024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D0_00 +CYREG_UDB_W16_D0_00 EQU 0x400f1040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_LS__OFFSET +CYFLD_UDB_W16_D0_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_LS__SIZE +CYFLD_UDB_W16_D0_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_MS__OFFSET +CYFLD_UDB_W16_D0_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_MS__SIZE +CYFLD_UDB_W16_D0_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D0_01 +CYREG_UDB_W16_D0_01 EQU 0x400f1042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D0_02 +CYREG_UDB_W16_D0_02 EQU 0x400f1044 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D1_00 +CYREG_UDB_W16_D1_00 EQU 0x400f1060 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_LS__OFFSET +CYFLD_UDB_W16_D1_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_LS__SIZE +CYFLD_UDB_W16_D1_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_MS__OFFSET +CYFLD_UDB_W16_D1_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_MS__SIZE +CYFLD_UDB_W16_D1_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D1_01 +CYREG_UDB_W16_D1_01 EQU 0x400f1062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D1_02 +CYREG_UDB_W16_D1_02 EQU 0x400f1064 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F0_00 +CYREG_UDB_W16_F0_00 EQU 0x400f1080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_LS__OFFSET +CYFLD_UDB_W16_F0_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_LS__SIZE +CYFLD_UDB_W16_F0_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_MS__OFFSET +CYFLD_UDB_W16_F0_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_MS__SIZE +CYFLD_UDB_W16_F0_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F0_01 +CYREG_UDB_W16_F0_01 EQU 0x400f1082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F0_02 +CYREG_UDB_W16_F0_02 EQU 0x400f1084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F1_00 +CYREG_UDB_W16_F1_00 EQU 0x400f10a0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_LS__OFFSET +CYFLD_UDB_W16_F1_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_LS__SIZE +CYFLD_UDB_W16_F1_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_MS__OFFSET +CYFLD_UDB_W16_F1_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_MS__SIZE +CYFLD_UDB_W16_F1_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F1_01 +CYREG_UDB_W16_F1_01 EQU 0x400f10a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F1_02 +CYREG_UDB_W16_F1_02 EQU 0x400f10a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ST_00 +CYREG_UDB_W16_ST_00 EQU 0x400f10c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_LS__OFFSET +CYFLD_UDB_W16_ST_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_LS__SIZE +CYFLD_UDB_W16_ST_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_MS__OFFSET +CYFLD_UDB_W16_ST_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_MS__SIZE +CYFLD_UDB_W16_ST_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ST_01 +CYREG_UDB_W16_ST_01 EQU 0x400f10c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ST_02 +CYREG_UDB_W16_ST_02 EQU 0x400f10c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_CTL_00 +CYREG_UDB_W16_CTL_00 EQU 0x400f10e0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_LS__OFFSET +CYFLD_UDB_W16_CTL_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_LS__SIZE +CYFLD_UDB_W16_CTL_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_MS__OFFSET +CYFLD_UDB_W16_CTL_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_MS__SIZE +CYFLD_UDB_W16_CTL_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_CTL_01 +CYREG_UDB_W16_CTL_01 EQU 0x400f10e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_CTL_02 +CYREG_UDB_W16_CTL_02 EQU 0x400f10e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MSK_00 +CYREG_UDB_W16_MSK_00 EQU 0x400f1100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_LS__OFFSET +CYFLD_UDB_W16_MSK_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_LS__SIZE +CYFLD_UDB_W16_MSK_LS__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_MS__OFFSET +CYFLD_UDB_W16_MSK_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_MS__SIZE +CYFLD_UDB_W16_MSK_MS__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MSK_01 +CYREG_UDB_W16_MSK_01 EQU 0x400f1102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MSK_02 +CYREG_UDB_W16_MSK_02 EQU 0x400f1104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ACTL_00 +CYREG_UDB_W16_ACTL_00 EQU 0x400f1120 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET +CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE +CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL +CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR +CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET +CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE +CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL +CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR +CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET +CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE +CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL +CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_LS_MID +CYVAL_UDB_W16_FIFO0_LVL_LS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET +CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE +CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL +CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_LS_MID +CYVAL_UDB_W16_FIFO1_LVL_LS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_LS__OFFSET +CYFLD_UDB_W16_INT_EN_LS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_LS__SIZE +CYFLD_UDB_W16_INT_EN_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_LS_DISABLE +CYVAL_UDB_W16_INT_EN_LS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_LS_ENABLE +CYVAL_UDB_W16_INT_EN_LS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_LS__OFFSET +CYFLD_UDB_W16_CNT_START_LS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_LS__SIZE +CYFLD_UDB_W16_CNT_START_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_LS_DISABLE +CYVAL_UDB_W16_CNT_START_LS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_LS_ENABLE +CYVAL_UDB_W16_CNT_START_LS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET +CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE +CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL +CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR +CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET +CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE +CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL +CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR +CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET +CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE +CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL +CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_MS_MID +CYVAL_UDB_W16_FIFO0_LVL_MS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET +CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE +CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL +CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_MS_MID +CYVAL_UDB_W16_FIFO1_LVL_MS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_MS__OFFSET +CYFLD_UDB_W16_INT_EN_MS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_MS__SIZE +CYFLD_UDB_W16_INT_EN_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_MS_DISABLE +CYVAL_UDB_W16_INT_EN_MS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_MS_ENABLE +CYVAL_UDB_W16_INT_EN_MS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_MS__OFFSET +CYFLD_UDB_W16_CNT_START_MS__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_MS__SIZE +CYFLD_UDB_W16_CNT_START_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_MS_DISABLE +CYVAL_UDB_W16_CNT_START_MS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_MS_ENABLE +CYVAL_UDB_W16_CNT_START_MS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ACTL_01 +CYREG_UDB_W16_ACTL_01 EQU 0x400f1122 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ACTL_02 +CYREG_UDB_W16_ACTL_02 EQU 0x400f1124 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MC_00 +CYREG_UDB_W16_MC_00 EQU 0x400f1140 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_LS__OFFSET +CYFLD_UDB_W16_PLD0_MC_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_LS__SIZE +CYFLD_UDB_W16_PLD0_MC_LS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_LS__OFFSET +CYFLD_UDB_W16_PLD1_MC_LS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_LS__SIZE +CYFLD_UDB_W16_PLD1_MC_LS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_MS__OFFSET +CYFLD_UDB_W16_PLD0_MC_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_MS__SIZE +CYFLD_UDB_W16_PLD0_MC_MS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_MS__OFFSET +CYFLD_UDB_W16_PLD1_MC_MS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_MS__SIZE +CYFLD_UDB_W16_PLD1_MC_MS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MC_01 +CYREG_UDB_W16_MC_01 EQU 0x400f1142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MC_02 +CYREG_UDB_W16_MC_02 EQU 0x400f1144 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W32_BASE +CYDEV_UDB_W32_BASE EQU 0x400f2000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W32_SIZE +CYDEV_UDB_W32_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_A0_00 +CYREG_UDB_W32_A0_00 EQU 0x400f2000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_0__OFFSET +CYFLD_UDB_W32_A0_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_0__SIZE +CYFLD_UDB_W32_A0_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_1__OFFSET +CYFLD_UDB_W32_A0_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_1__SIZE +CYFLD_UDB_W32_A0_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_2__OFFSET +CYFLD_UDB_W32_A0_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_2__SIZE +CYFLD_UDB_W32_A0_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_3__OFFSET +CYFLD_UDB_W32_A0_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_3__SIZE +CYFLD_UDB_W32_A0_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_A1_00 +CYREG_UDB_W32_A1_00 EQU 0x400f2040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_0__OFFSET +CYFLD_UDB_W32_A1_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_0__SIZE +CYFLD_UDB_W32_A1_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_1__OFFSET +CYFLD_UDB_W32_A1_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_1__SIZE +CYFLD_UDB_W32_A1_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_2__OFFSET +CYFLD_UDB_W32_A1_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_2__SIZE +CYFLD_UDB_W32_A1_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_3__OFFSET +CYFLD_UDB_W32_A1_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_3__SIZE +CYFLD_UDB_W32_A1_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_D0_00 +CYREG_UDB_W32_D0_00 EQU 0x400f2080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_0__OFFSET +CYFLD_UDB_W32_D0_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_0__SIZE +CYFLD_UDB_W32_D0_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_1__OFFSET +CYFLD_UDB_W32_D0_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_1__SIZE +CYFLD_UDB_W32_D0_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_2__OFFSET +CYFLD_UDB_W32_D0_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_2__SIZE +CYFLD_UDB_W32_D0_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_3__OFFSET +CYFLD_UDB_W32_D0_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_3__SIZE +CYFLD_UDB_W32_D0_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_D1_00 +CYREG_UDB_W32_D1_00 EQU 0x400f20c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_0__OFFSET +CYFLD_UDB_W32_D1_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_0__SIZE +CYFLD_UDB_W32_D1_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_1__OFFSET +CYFLD_UDB_W32_D1_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_1__SIZE +CYFLD_UDB_W32_D1_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_2__OFFSET +CYFLD_UDB_W32_D1_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_2__SIZE +CYFLD_UDB_W32_D1_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_3__OFFSET +CYFLD_UDB_W32_D1_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_3__SIZE +CYFLD_UDB_W32_D1_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_F0_00 +CYREG_UDB_W32_F0_00 EQU 0x400f2100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_0__OFFSET +CYFLD_UDB_W32_F0_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_0__SIZE +CYFLD_UDB_W32_F0_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_1__OFFSET +CYFLD_UDB_W32_F0_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_1__SIZE +CYFLD_UDB_W32_F0_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_2__OFFSET +CYFLD_UDB_W32_F0_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_2__SIZE +CYFLD_UDB_W32_F0_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_3__OFFSET +CYFLD_UDB_W32_F0_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_3__SIZE +CYFLD_UDB_W32_F0_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_F1_00 +CYREG_UDB_W32_F1_00 EQU 0x400f2140 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_0__OFFSET +CYFLD_UDB_W32_F1_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_0__SIZE +CYFLD_UDB_W32_F1_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_1__OFFSET +CYFLD_UDB_W32_F1_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_1__SIZE +CYFLD_UDB_W32_F1_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_2__OFFSET +CYFLD_UDB_W32_F1_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_2__SIZE +CYFLD_UDB_W32_F1_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_3__OFFSET +CYFLD_UDB_W32_F1_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_3__SIZE +CYFLD_UDB_W32_F1_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_ST_00 +CYREG_UDB_W32_ST_00 EQU 0x400f2180 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_0__OFFSET +CYFLD_UDB_W32_ST_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_0__SIZE +CYFLD_UDB_W32_ST_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_1__OFFSET +CYFLD_UDB_W32_ST_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_1__SIZE +CYFLD_UDB_W32_ST_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_2__OFFSET +CYFLD_UDB_W32_ST_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_2__SIZE +CYFLD_UDB_W32_ST_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_3__OFFSET +CYFLD_UDB_W32_ST_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_3__SIZE +CYFLD_UDB_W32_ST_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_CTL_00 +CYREG_UDB_W32_CTL_00 EQU 0x400f21c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_0__OFFSET +CYFLD_UDB_W32_CTL_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_0__SIZE +CYFLD_UDB_W32_CTL_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_1__OFFSET +CYFLD_UDB_W32_CTL_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_1__SIZE +CYFLD_UDB_W32_CTL_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_2__OFFSET +CYFLD_UDB_W32_CTL_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_2__SIZE +CYFLD_UDB_W32_CTL_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_3__OFFSET +CYFLD_UDB_W32_CTL_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_3__SIZE +CYFLD_UDB_W32_CTL_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_MSK_00 +CYREG_UDB_W32_MSK_00 EQU 0x400f2200 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_0__OFFSET +CYFLD_UDB_W32_MSK_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_0__SIZE +CYFLD_UDB_W32_MSK_0__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_1__OFFSET +CYFLD_UDB_W32_MSK_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_1__SIZE +CYFLD_UDB_W32_MSK_1__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_2__OFFSET +CYFLD_UDB_W32_MSK_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_2__SIZE +CYFLD_UDB_W32_MSK_2__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_3__OFFSET +CYFLD_UDB_W32_MSK_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_3__SIZE +CYFLD_UDB_W32_MSK_3__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_ACTL_00 +CYREG_UDB_W32_ACTL_00 EQU 0x400f2240 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_0__SIZE +CYFLD_UDB_W32_FIFO0_CLR_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_0__SIZE +CYFLD_UDB_W32_FIFO1_CLR_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_0__SIZE +CYFLD_UDB_W32_FIFO0_LVL_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_0_MID +CYVAL_UDB_W32_FIFO0_LVL_0_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_0__SIZE +CYFLD_UDB_W32_FIFO1_LVL_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_0_MID +CYVAL_UDB_W32_FIFO1_LVL_0_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_0__OFFSET +CYFLD_UDB_W32_INT_EN_0__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_0__SIZE +CYFLD_UDB_W32_INT_EN_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_0_DISABLE +CYVAL_UDB_W32_INT_EN_0_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_0_ENABLE +CYVAL_UDB_W32_INT_EN_0_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_0__OFFSET +CYFLD_UDB_W32_CNT_START_0__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_0__SIZE +CYFLD_UDB_W32_CNT_START_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_0_DISABLE +CYVAL_UDB_W32_CNT_START_0_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_0_ENABLE +CYVAL_UDB_W32_CNT_START_0_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_1__SIZE +CYFLD_UDB_W32_FIFO0_CLR_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_1__SIZE +CYFLD_UDB_W32_FIFO1_CLR_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_1__SIZE +CYFLD_UDB_W32_FIFO0_LVL_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_1_MID +CYVAL_UDB_W32_FIFO0_LVL_1_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_1__SIZE +CYFLD_UDB_W32_FIFO1_LVL_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_1_MID +CYVAL_UDB_W32_FIFO1_LVL_1_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_1__OFFSET +CYFLD_UDB_W32_INT_EN_1__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_1__SIZE +CYFLD_UDB_W32_INT_EN_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_1_DISABLE +CYVAL_UDB_W32_INT_EN_1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_1_ENABLE +CYVAL_UDB_W32_INT_EN_1_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_1__OFFSET +CYFLD_UDB_W32_CNT_START_1__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_1__SIZE +CYFLD_UDB_W32_CNT_START_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_1_DISABLE +CYVAL_UDB_W32_CNT_START_1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_1_ENABLE +CYVAL_UDB_W32_CNT_START_1_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_2__SIZE +CYFLD_UDB_W32_FIFO0_CLR_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_2__SIZE +CYFLD_UDB_W32_FIFO1_CLR_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_2__SIZE +CYFLD_UDB_W32_FIFO0_LVL_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_2_MID +CYVAL_UDB_W32_FIFO0_LVL_2_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_2__SIZE +CYFLD_UDB_W32_FIFO1_LVL_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_2_MID +CYVAL_UDB_W32_FIFO1_LVL_2_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_2__OFFSET +CYFLD_UDB_W32_INT_EN_2__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_2__SIZE +CYFLD_UDB_W32_INT_EN_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_2_DISABLE +CYVAL_UDB_W32_INT_EN_2_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_2_ENABLE +CYVAL_UDB_W32_INT_EN_2_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_2__OFFSET +CYFLD_UDB_W32_CNT_START_2__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_2__SIZE +CYFLD_UDB_W32_CNT_START_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_2_DISABLE +CYVAL_UDB_W32_CNT_START_2_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_2_ENABLE +CYVAL_UDB_W32_CNT_START_2_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_3__SIZE +CYFLD_UDB_W32_FIFO0_CLR_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_3__SIZE +CYFLD_UDB_W32_FIFO1_CLR_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_3__SIZE +CYFLD_UDB_W32_FIFO0_LVL_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_3_MID +CYVAL_UDB_W32_FIFO0_LVL_3_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_3__SIZE +CYFLD_UDB_W32_FIFO1_LVL_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_3_MID +CYVAL_UDB_W32_FIFO1_LVL_3_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_3__OFFSET +CYFLD_UDB_W32_INT_EN_3__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_3__SIZE +CYFLD_UDB_W32_INT_EN_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_3_DISABLE +CYVAL_UDB_W32_INT_EN_3_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_3_ENABLE +CYVAL_UDB_W32_INT_EN_3_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_3__OFFSET +CYFLD_UDB_W32_CNT_START_3__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_3__SIZE +CYFLD_UDB_W32_CNT_START_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_3_DISABLE +CYVAL_UDB_W32_CNT_START_3_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_3_ENABLE +CYVAL_UDB_W32_CNT_START_3_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_MC_00 +CYREG_UDB_W32_MC_00 EQU 0x400f2280 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_0__OFFSET +CYFLD_UDB_W32_PLD0_MC_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_0__SIZE +CYFLD_UDB_W32_PLD0_MC_0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_0__OFFSET +CYFLD_UDB_W32_PLD1_MC_0__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_0__SIZE +CYFLD_UDB_W32_PLD1_MC_0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_1__OFFSET +CYFLD_UDB_W32_PLD0_MC_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_1__SIZE +CYFLD_UDB_W32_PLD0_MC_1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_1__OFFSET +CYFLD_UDB_W32_PLD1_MC_1__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_1__SIZE +CYFLD_UDB_W32_PLD1_MC_1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_2__OFFSET +CYFLD_UDB_W32_PLD0_MC_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_2__SIZE +CYFLD_UDB_W32_PLD0_MC_2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_2__OFFSET +CYFLD_UDB_W32_PLD1_MC_2__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_2__SIZE +CYFLD_UDB_W32_PLD1_MC_2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_3__OFFSET +CYFLD_UDB_W32_PLD0_MC_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_3__SIZE +CYFLD_UDB_W32_PLD0_MC_3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_3__OFFSET +CYFLD_UDB_W32_PLD1_MC_3__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_3__SIZE +CYFLD_UDB_W32_PLD1_MC_3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_BASE +CYDEV_UDB_P0_BASE EQU 0x400f3000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_SIZE +CYDEV_UDB_P0_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U0_BASE +CYDEV_UDB_P0_U0_BASE EQU 0x400f3000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U0_SIZE +CYDEV_UDB_P0_U0_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT0 +CYREG_UDB_P0_U0_PLD_IT0 EQU 0x400f3000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT1 +CYREG_UDB_P0_U0_PLD_IT1 EQU 0x400f3004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT2 +CYREG_UDB_P0_U0_PLD_IT2 EQU 0x400f3008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT3 +CYREG_UDB_P0_U0_PLD_IT3 EQU 0x400f300c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT4 +CYREG_UDB_P0_U0_PLD_IT4 EQU 0x400f3010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT5 +CYREG_UDB_P0_U0_PLD_IT5 EQU 0x400f3014 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT6 +CYREG_UDB_P0_U0_PLD_IT6 EQU 0x400f3018 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT7 +CYREG_UDB_P0_U0_PLD_IT7 EQU 0x400f301c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT8 +CYREG_UDB_P0_U0_PLD_IT8 EQU 0x400f3020 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT9 +CYREG_UDB_P0_U0_PLD_IT9 EQU 0x400f3024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT10 +CYREG_UDB_P0_U0_PLD_IT10 EQU 0x400f3028 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT11 +CYREG_UDB_P0_U0_PLD_IT11 EQU 0x400f302c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT0 +CYREG_UDB_P0_U0_PLD_ORT0 EQU 0x400f3030 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT1 +CYREG_UDB_P0_U0_PLD_ORT1 EQU 0x400f3032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT2 +CYREG_UDB_P0_U0_PLD_ORT2 EQU 0x400f3034 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT3 +CYREG_UDB_P0_U0_PLD_ORT3 EQU 0x400f3036 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST EQU 0x400f3038 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB +CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB EQU 0x400f303a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_SET_RESET +CYREG_UDB_P0_U0_PLD_MC_SET_RESET EQU 0x400f303c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS +CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS EQU 0x400f303e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC1__OFFSET +CYFLD_UDB_P_U_NC1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC1__SIZE +CYFLD_UDB_P_U_NC1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC3__OFFSET +CYFLD_UDB_P_U_NC3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC3__SIZE +CYFLD_UDB_P_U_NC3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC5__OFFSET +CYFLD_UDB_P_U_NC5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC5__SIZE +CYFLD_UDB_P_U_NC5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC7__OFFSET +CYFLD_UDB_P_U_NC7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC7__SIZE +CYFLD_UDB_P_U_NC7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC9__OFFSET +CYFLD_UDB_P_U_NC9__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC9__SIZE +CYFLD_UDB_P_U_NC9__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC11__OFFSET +CYFLD_UDB_P_U_NC11__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC11__SIZE +CYFLD_UDB_P_U_NC11__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC13__OFFSET +CYFLD_UDB_P_U_NC13__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC13__SIZE +CYFLD_UDB_P_U_NC13__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC15__OFFSET +CYFLD_UDB_P_U_NC15__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC15__SIZE +CYFLD_UDB_P_U_NC15__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG0 +CYREG_UDB_P0_U0_CFG0 EQU 0x400f3040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD0__OFFSET +CYFLD_UDB_P_U_RAD0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD0__SIZE +CYFLD_UDB_P_U_RAD0__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_OFF +CYVAL_UDB_P_U_RAD0_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN0 +CYVAL_UDB_P_U_RAD0_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN1 +CYVAL_UDB_P_U_RAD0_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN2 +CYVAL_UDB_P_U_RAD0_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN3 +CYVAL_UDB_P_U_RAD0_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN4 +CYVAL_UDB_P_U_RAD0_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN5 +CYVAL_UDB_P_U_RAD0_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_RESERVED +CYVAL_UDB_P_U_RAD0_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD1__OFFSET +CYFLD_UDB_P_U_RAD1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD1__SIZE +CYFLD_UDB_P_U_RAD1__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_OFF +CYVAL_UDB_P_U_RAD1_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN0 +CYVAL_UDB_P_U_RAD1_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN1 +CYVAL_UDB_P_U_RAD1_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN2 +CYVAL_UDB_P_U_RAD1_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN3 +CYVAL_UDB_P_U_RAD1_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN4 +CYVAL_UDB_P_U_RAD1_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN5 +CYVAL_UDB_P_U_RAD1_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_RESERVED +CYVAL_UDB_P_U_RAD1_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG1 +CYREG_UDB_P0_U0_CFG1 EQU 0x400f3041 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD2__OFFSET +CYFLD_UDB_P_U_RAD2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD2__SIZE +CYFLD_UDB_P_U_RAD2__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_OFF +CYVAL_UDB_P_U_RAD2_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN0 +CYVAL_UDB_P_U_RAD2_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN1 +CYVAL_UDB_P_U_RAD2_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN2 +CYVAL_UDB_P_U_RAD2_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN3 +CYVAL_UDB_P_U_RAD2_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN4 +CYVAL_UDB_P_U_RAD2_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN5 +CYVAL_UDB_P_U_RAD2_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_RESERVED +CYVAL_UDB_P_U_RAD2_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG2 +CYREG_UDB_P0_U0_CFG2 EQU 0x400f3042 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_LD__OFFSET +CYFLD_UDB_P_U_F0_LD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_LD__SIZE +CYFLD_UDB_P_U_F0_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_OFF +CYVAL_UDB_P_U_F0_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN0 +CYVAL_UDB_P_U_F0_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN1 +CYVAL_UDB_P_U_F0_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN2 +CYVAL_UDB_P_U_F0_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN3 +CYVAL_UDB_P_U_F0_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN4 +CYVAL_UDB_P_U_F0_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN5 +CYVAL_UDB_P_U_F0_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_RESERVED +CYVAL_UDB_P_U_F0_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_LD__OFFSET +CYFLD_UDB_P_U_F1_LD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_LD__SIZE +CYFLD_UDB_P_U_F1_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_OFF +CYVAL_UDB_P_U_F1_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN0 +CYVAL_UDB_P_U_F1_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN1 +CYVAL_UDB_P_U_F1_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN2 +CYVAL_UDB_P_U_F1_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN3 +CYVAL_UDB_P_U_F1_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN4 +CYVAL_UDB_P_U_F1_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN5 +CYVAL_UDB_P_U_F1_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_RESERVED +CYVAL_UDB_P_U_F1_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG3 +CYREG_UDB_P0_U0_CFG3 EQU 0x400f3043 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D0_LD__OFFSET +CYFLD_UDB_P_U_D0_LD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D0_LD__SIZE +CYFLD_UDB_P_U_D0_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_OFF +CYVAL_UDB_P_U_D0_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN0 +CYVAL_UDB_P_U_D0_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN1 +CYVAL_UDB_P_U_D0_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN2 +CYVAL_UDB_P_U_D0_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN3 +CYVAL_UDB_P_U_D0_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN4 +CYVAL_UDB_P_U_D0_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN5 +CYVAL_UDB_P_U_D0_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_RESERVED +CYVAL_UDB_P_U_D0_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D1_LD__OFFSET +CYFLD_UDB_P_U_D1_LD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D1_LD__SIZE +CYFLD_UDB_P_U_D1_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_OFF +CYVAL_UDB_P_U_D1_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN0 +CYVAL_UDB_P_U_D1_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN1 +CYVAL_UDB_P_U_D1_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN2 +CYVAL_UDB_P_U_D1_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN3 +CYVAL_UDB_P_U_D1_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN4 +CYVAL_UDB_P_U_D1_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN5 +CYVAL_UDB_P_U_D1_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_RESERVED +CYVAL_UDB_P_U_D1_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG4 +CYREG_UDB_P0_U0_CFG4 EQU 0x400f3044 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_MUX__OFFSET +CYFLD_UDB_P_U_SI_MUX__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_MUX__SIZE +CYFLD_UDB_P_U_SI_MUX__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_OFF +CYVAL_UDB_P_U_SI_MUX_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN0 +CYVAL_UDB_P_U_SI_MUX_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN1 +CYVAL_UDB_P_U_SI_MUX_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN2 +CYVAL_UDB_P_U_SI_MUX_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN3 +CYVAL_UDB_P_U_SI_MUX_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN4 +CYVAL_UDB_P_U_SI_MUX_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN5 +CYVAL_UDB_P_U_SI_MUX_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_RESERVED +CYVAL_UDB_P_U_SI_MUX_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_MUX__OFFSET +CYFLD_UDB_P_U_CI_MUX__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_MUX__SIZE +CYFLD_UDB_P_U_CI_MUX__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_OFF +CYVAL_UDB_P_U_CI_MUX_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN0 +CYVAL_UDB_P_U_CI_MUX_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN1 +CYVAL_UDB_P_U_CI_MUX_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN2 +CYVAL_UDB_P_U_CI_MUX_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN3 +CYVAL_UDB_P_U_CI_MUX_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN4 +CYVAL_UDB_P_U_CI_MUX_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN5 +CYVAL_UDB_P_U_CI_MUX_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_RESERVED +CYVAL_UDB_P_U_CI_MUX_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG5 +CYREG_UDB_P0_U0_CFG5 EQU 0x400f3045 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT0__OFFSET +CYFLD_UDB_P_U_OUT0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT0__SIZE +CYFLD_UDB_P_U_OUT0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CE0 +CYVAL_UDB_P_U_OUT0_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CL0 +CYVAL_UDB_P_U_OUT0_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_Z0 +CYVAL_UDB_P_U_OUT0_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_FF0 +CYVAL_UDB_P_U_OUT0_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CE1 +CYVAL_UDB_P_U_OUT0_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CL1 +CYVAL_UDB_P_U_OUT0_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_Z1 +CYVAL_UDB_P_U_OUT0_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_FF1 +CYVAL_UDB_P_U_OUT0_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_OV_MSB +CYVAL_UDB_P_U_OUT0_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CO_MSB +CYVAL_UDB_P_U_OUT0_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CMSBO +CYVAL_UDB_P_U_OUT0_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_SO +CYVAL_UDB_P_U_OUT0_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F0_BLK_STAT +CYVAL_UDB_P_U_OUT0_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F1_BLK_STAT +CYVAL_UDB_P_U_OUT0_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F0_BUS_STAT +CYVAL_UDB_P_U_OUT0_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F1_BUS_STAT +CYVAL_UDB_P_U_OUT0_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT1__OFFSET +CYFLD_UDB_P_U_OUT1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT1__SIZE +CYFLD_UDB_P_U_OUT1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CE0 +CYVAL_UDB_P_U_OUT1_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CL0 +CYVAL_UDB_P_U_OUT1_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_Z0 +CYVAL_UDB_P_U_OUT1_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_FF0 +CYVAL_UDB_P_U_OUT1_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CE1 +CYVAL_UDB_P_U_OUT1_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CL1 +CYVAL_UDB_P_U_OUT1_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_Z1 +CYVAL_UDB_P_U_OUT1_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_FF1 +CYVAL_UDB_P_U_OUT1_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_OV_MSB +CYVAL_UDB_P_U_OUT1_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CO_MSB +CYVAL_UDB_P_U_OUT1_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CMSBO +CYVAL_UDB_P_U_OUT1_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_SO +CYVAL_UDB_P_U_OUT1_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F0_BLK_STAT +CYVAL_UDB_P_U_OUT1_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F1_BLK_STAT +CYVAL_UDB_P_U_OUT1_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F0_BUS_STAT +CYVAL_UDB_P_U_OUT1_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F1_BUS_STAT +CYVAL_UDB_P_U_OUT1_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG6 +CYREG_UDB_P0_U0_CFG6 EQU 0x400f3046 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT2__OFFSET +CYFLD_UDB_P_U_OUT2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT2__SIZE +CYFLD_UDB_P_U_OUT2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CE0 +CYVAL_UDB_P_U_OUT2_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CL0 +CYVAL_UDB_P_U_OUT2_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_Z0 +CYVAL_UDB_P_U_OUT2_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_FF0 +CYVAL_UDB_P_U_OUT2_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CE1 +CYVAL_UDB_P_U_OUT2_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CL1 +CYVAL_UDB_P_U_OUT2_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_Z1 +CYVAL_UDB_P_U_OUT2_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_FF1 +CYVAL_UDB_P_U_OUT2_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_OV_MSB +CYVAL_UDB_P_U_OUT2_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CO_MSB +CYVAL_UDB_P_U_OUT2_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CMSBO +CYVAL_UDB_P_U_OUT2_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_SO +CYVAL_UDB_P_U_OUT2_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F0_BLK_STAT +CYVAL_UDB_P_U_OUT2_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F1_BLK_STAT +CYVAL_UDB_P_U_OUT2_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F0_BUS_STAT +CYVAL_UDB_P_U_OUT2_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F1_BUS_STAT +CYVAL_UDB_P_U_OUT2_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT3__OFFSET +CYFLD_UDB_P_U_OUT3__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT3__SIZE +CYFLD_UDB_P_U_OUT3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CE0 +CYVAL_UDB_P_U_OUT3_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CL0 +CYVAL_UDB_P_U_OUT3_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_Z0 +CYVAL_UDB_P_U_OUT3_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_FF0 +CYVAL_UDB_P_U_OUT3_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CE1 +CYVAL_UDB_P_U_OUT3_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CL1 +CYVAL_UDB_P_U_OUT3_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_Z1 +CYVAL_UDB_P_U_OUT3_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_FF1 +CYVAL_UDB_P_U_OUT3_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_OV_MSB +CYVAL_UDB_P_U_OUT3_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CO_MSB +CYVAL_UDB_P_U_OUT3_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CMSBO +CYVAL_UDB_P_U_OUT3_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_SO +CYVAL_UDB_P_U_OUT3_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F0_BLK_STAT +CYVAL_UDB_P_U_OUT3_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F1_BLK_STAT +CYVAL_UDB_P_U_OUT3_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F0_BUS_STAT +CYVAL_UDB_P_U_OUT3_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F1_BUS_STAT +CYVAL_UDB_P_U_OUT3_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG7 +CYREG_UDB_P0_U0_CFG7 EQU 0x400f3047 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT4__OFFSET +CYFLD_UDB_P_U_OUT4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT4__SIZE +CYFLD_UDB_P_U_OUT4__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CE0 +CYVAL_UDB_P_U_OUT4_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CL0 +CYVAL_UDB_P_U_OUT4_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_Z0 +CYVAL_UDB_P_U_OUT4_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_FF0 +CYVAL_UDB_P_U_OUT4_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CE1 +CYVAL_UDB_P_U_OUT4_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CL1 +CYVAL_UDB_P_U_OUT4_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_Z1 +CYVAL_UDB_P_U_OUT4_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_FF1 +CYVAL_UDB_P_U_OUT4_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_OV_MSB +CYVAL_UDB_P_U_OUT4_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CO_MSB +CYVAL_UDB_P_U_OUT4_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CMSBO +CYVAL_UDB_P_U_OUT4_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_SO +CYVAL_UDB_P_U_OUT4_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F0_BLK_STAT +CYVAL_UDB_P_U_OUT4_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F1_BLK_STAT +CYVAL_UDB_P_U_OUT4_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F0_BUS_STAT +CYVAL_UDB_P_U_OUT4_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F1_BUS_STAT +CYVAL_UDB_P_U_OUT4_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT5__OFFSET +CYFLD_UDB_P_U_OUT5__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT5__SIZE +CYFLD_UDB_P_U_OUT5__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CE0 +CYVAL_UDB_P_U_OUT5_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CL0 +CYVAL_UDB_P_U_OUT5_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_Z0 +CYVAL_UDB_P_U_OUT5_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_FF0 +CYVAL_UDB_P_U_OUT5_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CE1 +CYVAL_UDB_P_U_OUT5_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CL1 +CYVAL_UDB_P_U_OUT5_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_Z1 +CYVAL_UDB_P_U_OUT5_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_FF1 +CYVAL_UDB_P_U_OUT5_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_OV_MSB +CYVAL_UDB_P_U_OUT5_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CO_MSB +CYVAL_UDB_P_U_OUT5_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CMSBO +CYVAL_UDB_P_U_OUT5_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_SO +CYVAL_UDB_P_U_OUT5_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F0_BLK_STAT +CYVAL_UDB_P_U_OUT5_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F1_BLK_STAT +CYVAL_UDB_P_U_OUT5_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F0_BUS_STAT +CYVAL_UDB_P_U_OUT5_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F1_BUS_STAT +CYVAL_UDB_P_U_OUT5_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG8 +CYREG_UDB_P0_U0_CFG8 EQU 0x400f3048 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT_SYNC__OFFSET +CYFLD_UDB_P_U_OUT_SYNC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT_SYNC__SIZE +CYFLD_UDB_P_U_OUT_SYNC__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT_SYNC_REGISTERED +CYVAL_UDB_P_U_OUT_SYNC_REGISTERED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL +CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC6__OFFSET +CYFLD_UDB_P_U_NC6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC6__SIZE +CYFLD_UDB_P_U_NC6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG9 +CYREG_UDB_P0_U0_CFG9 EQU 0x400f3049 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK__OFFSET +CYFLD_UDB_P_U_AMASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK__SIZE +CYFLD_UDB_P_U_AMASK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG10 +CYREG_UDB_P0_U0_CFG10 EQU 0x400f304a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0__OFFSET +CYFLD_UDB_P_U_CMASK0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0__SIZE +CYFLD_UDB_P_U_CMASK0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG11 +CYREG_UDB_P0_U0_CFG11 EQU 0x400f304b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG12 +CYREG_UDB_P0_U0_CFG12 EQU 0x400f304c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELA__OFFSET +CYFLD_UDB_P_U_SI_SELA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELA__SIZE +CYFLD_UDB_P_U_SI_SELA__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_DEFAULT +CYVAL_UDB_P_U_SI_SELA_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_REGISTERED +CYVAL_UDB_P_U_SI_SELA_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_ROUTE +CYVAL_UDB_P_U_SI_SELA_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_CHAIN +CYVAL_UDB_P_U_SI_SELA_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELB__OFFSET +CYFLD_UDB_P_U_SI_SELB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELB__SIZE +CYFLD_UDB_P_U_SI_SELB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_DEFAULT +CYVAL_UDB_P_U_SI_SELB_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_REGISTERED +CYVAL_UDB_P_U_SI_SELB_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_ROUTE +CYVAL_UDB_P_U_SI_SELB_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_CHAIN +CYVAL_UDB_P_U_SI_SELB_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DEF_SI__OFFSET +CYFLD_UDB_P_U_DEF_SI__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DEF_SI__SIZE +CYFLD_UDB_P_U_DEF_SI__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 +CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 +CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK_EN__OFFSET +CYFLD_UDB_P_U_AMASK_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK_EN__SIZE +CYFLD_UDB_P_U_AMASK_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_AMASK_EN_DISABLE +CYVAL_UDB_P_U_AMASK_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_AMASK_EN_ENABLE +CYVAL_UDB_P_U_AMASK_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0_EN__OFFSET +CYFLD_UDB_P_U_CMASK0_EN__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0_EN__SIZE +CYFLD_UDB_P_U_CMASK0_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK0_EN_DISABLE +CYVAL_UDB_P_U_CMASK0_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK0_EN_ENABLE +CYVAL_UDB_P_U_CMASK0_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK1_EN__OFFSET +CYFLD_UDB_P_U_CMASK1_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK1_EN__SIZE +CYFLD_UDB_P_U_CMASK1_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK1_EN_DISABLE +CYVAL_UDB_P_U_CMASK1_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK1_EN_ENABLE +CYVAL_UDB_P_U_CMASK1_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG13 +CYREG_UDB_P0_U0_CFG13 EQU 0x400f304d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELA__OFFSET +CYFLD_UDB_P_U_CI_SELA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELA__SIZE +CYFLD_UDB_P_U_CI_SELA__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_DEFAULT +CYVAL_UDB_P_U_CI_SELA_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_REGISTERED +CYVAL_UDB_P_U_CI_SELA_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_ROUTE +CYVAL_UDB_P_U_CI_SELA_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_CHAIN +CYVAL_UDB_P_U_CI_SELA_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELB__OFFSET +CYFLD_UDB_P_U_CI_SELB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELB__SIZE +CYFLD_UDB_P_U_CI_SELB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_DEFAULT +CYVAL_UDB_P_U_CI_SELB_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_REGISTERED +CYVAL_UDB_P_U_CI_SELB_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_ROUTE +CYVAL_UDB_P_U_CI_SELB_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_CHAIN +CYVAL_UDB_P_U_CI_SELB_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELA__OFFSET +CYFLD_UDB_P_U_CMP_SELA__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELA__SIZE +CYFLD_UDB_P_U_CMP_SELA__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A1_D1 +CYVAL_UDB_P_U_CMP_SELA_A1_D1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A1_A0 +CYVAL_UDB_P_U_CMP_SELA_A1_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A0_D1 +CYVAL_UDB_P_U_CMP_SELA_A0_D1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A0_A0 +CYVAL_UDB_P_U_CMP_SELA_A0_A0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELB__OFFSET +CYFLD_UDB_P_U_CMP_SELB__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELB__SIZE +CYFLD_UDB_P_U_CMP_SELB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A1_D1 +CYVAL_UDB_P_U_CMP_SELB_A1_D1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A1_A0 +CYVAL_UDB_P_U_CMP_SELB_A1_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A0_D1 +CYVAL_UDB_P_U_CMP_SELB_A0_D1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A0_A0 +CYVAL_UDB_P_U_CMP_SELB_A0_A0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG14 +CYREG_UDB_P0_U0_CFG14 EQU 0x400f304e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN0__OFFSET +CYFLD_UDB_P_U_CHAIN0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN0__SIZE +CYFLD_UDB_P_U_CHAIN0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN0_DISABLE +CYVAL_UDB_P_U_CHAIN0_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN0_ENABLE +CYVAL_UDB_P_U_CHAIN0_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN1__OFFSET +CYFLD_UDB_P_U_CHAIN1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN1__SIZE +CYFLD_UDB_P_U_CHAIN1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN1_DISABLE +CYVAL_UDB_P_U_CHAIN1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN1_ENABLE +CYVAL_UDB_P_U_CHAIN1_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_FB__OFFSET +CYFLD_UDB_P_U_CHAIN_FB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_FB__SIZE +CYFLD_UDB_P_U_CHAIN_FB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_FB_DISABLE +CYVAL_UDB_P_U_CHAIN_FB_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_FB_ENABLE +CYVAL_UDB_P_U_CHAIN_FB_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET +CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_CMSB__SIZE +CYFLD_UDB_P_U_CHAIN_CMSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE +CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE +CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SEL__OFFSET +CYFLD_UDB_P_U_MSB_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SEL__SIZE +CYFLD_UDB_P_U_MSB_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT0 +CYVAL_UDB_P_U_MSB_SEL_BIT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT1 +CYVAL_UDB_P_U_MSB_SEL_BIT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT2 +CYVAL_UDB_P_U_MSB_SEL_BIT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT3 +CYVAL_UDB_P_U_MSB_SEL_BIT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT4 +CYVAL_UDB_P_U_MSB_SEL_BIT4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT5 +CYVAL_UDB_P_U_MSB_SEL_BIT5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT6 +CYVAL_UDB_P_U_MSB_SEL_BIT6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT7 +CYVAL_UDB_P_U_MSB_SEL_BIT7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_EN__OFFSET +CYFLD_UDB_P_U_MSB_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_EN__SIZE +CYFLD_UDB_P_U_MSB_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_EN_DISABLE +CYVAL_UDB_P_U_MSB_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_EN_ENABLE +CYVAL_UDB_P_U_MSB_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG15 +CYREG_UDB_P0_U0_CFG15 EQU 0x400f304f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_INSEL__OFFSET +CYFLD_UDB_P_U_F0_INSEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_INSEL__SIZE +CYFLD_UDB_P_U_F0_INSEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_INPUT +CYVAL_UDB_P_U_F0_INSEL_INPUT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 +CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 +CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU +CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_INSEL__OFFSET +CYFLD_UDB_P_U_F1_INSEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_INSEL__SIZE +CYFLD_UDB_P_U_F1_INSEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_INPUT +CYVAL_UDB_P_U_F1_INSEL_INPUT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 +CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 +CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU +CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SI__OFFSET +CYFLD_UDB_P_U_MSB_SI__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SI__SIZE +CYFLD_UDB_P_U_MSB_SI__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SI_DEFAULT +CYVAL_UDB_P_U_MSB_SI_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SI_MSB +CYVAL_UDB_P_U_MSB_SI_MSB EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_DYN__OFFSET +CYFLD_UDB_P_U_PI_DYN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_DYN__SIZE +CYFLD_UDB_P_U_PI_DYN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_DYN_DISABLE +CYVAL_UDB_P_U_PI_DYN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_DYN_ENABLE +CYVAL_UDB_P_U_PI_DYN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT_SEL__OFFSET +CYFLD_UDB_P_U_SHIFT_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT_SEL__SIZE +CYFLD_UDB_P_U_SHIFT_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB +CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_SEL_SOR +CYVAL_UDB_P_U_SHIFT_SEL_SOR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_SEL__OFFSET +CYFLD_UDB_P_U_PI_SEL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_SEL__SIZE +CYFLD_UDB_P_U_PI_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_SEL_NORMAL +CYVAL_UDB_P_U_PI_SEL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_SEL_PARALLEL +CYVAL_UDB_P_U_PI_SEL_PARALLEL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG16 +CYREG_UDB_P0_U0_CFG16 EQU 0x400f3050 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET +CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_WRK16_CONCAT__SIZE +CYFLD_UDB_P_U_WRK16_CONCAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT +CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE +CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET +CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CRCPRS__SIZE +CYFLD_UDB_P_U_EXT_CRCPRS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL +CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL +CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET +CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ASYNC__SIZE +CYFLD_UDB_P_U_FIFO_ASYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE +CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE +CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_EDGE__OFFSET +CYFLD_UDB_P_U_FIFO_EDGE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_EDGE__SIZE +CYFLD_UDB_P_U_FIFO_EDGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_EDGE_LEVEL +CYVAL_UDB_P_U_FIFO_EDGE_LEVEL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_EDGE_EDGE +CYVAL_UDB_P_U_FIFO_EDGE_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_CAP__OFFSET +CYFLD_UDB_P_U_FIFO_CAP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_CAP__SIZE +CYFLD_UDB_P_U_FIFO_CAP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_CAP_DISABLE +CYVAL_UDB_P_U_FIFO_CAP_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_CAP_ENABLE +CYVAL_UDB_P_U_FIFO_CAP_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_FAST__OFFSET +CYFLD_UDB_P_U_FIFO_FAST__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_FAST__SIZE +CYFLD_UDB_P_U_FIFO_FAST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_FAST_DISABLE +CYVAL_UDB_P_U_FIFO_FAST_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_FAST_ENABLE +CYVAL_UDB_P_U_FIFO_FAST_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_CK_INV__OFFSET +CYFLD_UDB_P_U_F0_CK_INV__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_CK_INV__SIZE +CYFLD_UDB_P_U_F0_CK_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_CK_INV_NORMAL +CYVAL_UDB_P_U_F0_CK_INV_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_CK_INV_INVERT +CYVAL_UDB_P_U_F0_CK_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_CK_INV__OFFSET +CYFLD_UDB_P_U_F1_CK_INV__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_CK_INV__SIZE +CYFLD_UDB_P_U_F1_CK_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_CK_INV_NORMAL +CYVAL_UDB_P_U_F1_CK_INV_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_CK_INV_INVERT +CYVAL_UDB_P_U_F1_CK_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG17 +CYREG_UDB_P0_U0_CFG17 EQU 0x400f3051 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_DYN__OFFSET +CYFLD_UDB_P_U_F0_DYN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_DYN__SIZE +CYFLD_UDB_P_U_F0_DYN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_DYN_STATIC +CYVAL_UDB_P_U_F0_DYN_STATIC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_DYN_DYNAMIC +CYVAL_UDB_P_U_F0_DYN_DYNAMIC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_DYN__OFFSET +CYFLD_UDB_P_U_F1_DYN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_DYN__SIZE +CYFLD_UDB_P_U_F1_DYN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_DYN_STATIC +CYVAL_UDB_P_U_F1_DYN_STATIC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_DYN_DYNAMIC +CYVAL_UDB_P_U_F1_DYN_DYNAMIC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC2__OFFSET +CYFLD_UDB_P_U_NC2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC2__SIZE +CYFLD_UDB_P_U_NC2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET +CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE +CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE +CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE +CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG18 +CYREG_UDB_P0_U0_CFG18 EQU 0x400f3052 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD0__OFFSET +CYFLD_UDB_P_U_CTL_MD0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD0__SIZE +CYFLD_UDB_P_U_CTL_MD0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_DIRECT +CYVAL_UDB_P_U_CTL_MD0_DIRECT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_SYNC +CYVAL_UDB_P_U_CTL_MD0_SYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC +CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_PULSE +CYVAL_UDB_P_U_CTL_MD0_PULSE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG19 +CYREG_UDB_P0_U0_CFG19 EQU 0x400f3053 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD1__OFFSET +CYFLD_UDB_P_U_CTL_MD1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD1__SIZE +CYFLD_UDB_P_U_CTL_MD1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_DIRECT +CYVAL_UDB_P_U_CTL_MD1_DIRECT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_SYNC +CYVAL_UDB_P_U_CTL_MD1_SYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC +CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_PULSE +CYVAL_UDB_P_U_CTL_MD1_PULSE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG20 +CYREG_UDB_P0_U0_CFG20 EQU 0x400f3054 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_STAT_MD__OFFSET +CYFLD_UDB_P_U_STAT_MD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_STAT_MD__SIZE +CYFLD_UDB_P_U_STAT_MD__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG21 +CYREG_UDB_P0_U0_CFG21 EQU 0x400f3055 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC0__OFFSET +CYFLD_UDB_P_U_NC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC0__SIZE +CYFLD_UDB_P_U_NC0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG22 +CYREG_UDB_P0_U0_CFG22 EQU 0x400f3056 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET +CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_OUT_CTL__SIZE +CYFLD_UDB_P_U_SC_OUT_CTL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL +CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL +CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER +CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED +CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_INT_MD__OFFSET +CYFLD_UDB_P_U_SC_INT_MD__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_INT_MD__SIZE +CYFLD_UDB_P_U_SC_INT_MD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_INT_MD_NORMAL +CYVAL_UDB_P_U_SC_INT_MD_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_INT_MD_INT_MODE +CYVAL_UDB_P_U_SC_INT_MD_INT_MODE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET +CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_SYNC_MD__SIZE +CYFLD_UDB_P_U_SC_SYNC_MD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL +CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE +CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_EXT_RES__OFFSET +CYFLD_UDB_P_U_SC_EXT_RES__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_EXT_RES__SIZE +CYFLD_UDB_P_U_SC_EXT_RES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_EXT_RES_DISABLED +CYVAL_UDB_P_U_SC_EXT_RES_DISABLED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_EXT_RES_ENABLED +CYVAL_UDB_P_U_SC_EXT_RES_ENABLED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG23 +CYREG_UDB_P0_U0_CFG23 EQU 0x400f3057 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET +CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_LD_SEL__SIZE +CYFLD_UDB_P_U_CNT_LD_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET +CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_EN_SEL__SIZE +CYFLD_UDB_P_U_CNT_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_LD__OFFSET +CYFLD_UDB_P_U_ROUTE_LD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_LD__SIZE +CYFLD_UDB_P_U_ROUTE_LD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_LD_DISABLE +CYVAL_UDB_P_U_ROUTE_LD_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_LD_ROUTED +CYVAL_UDB_P_U_ROUTE_LD_ROUTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_EN__OFFSET +CYFLD_UDB_P_U_ROUTE_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_EN__SIZE +CYFLD_UDB_P_U_ROUTE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_EN_DISABLE +CYVAL_UDB_P_U_ROUTE_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_EN_ROUTED +CYVAL_UDB_P_U_ROUTE_EN_ROUTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_CNT__OFFSET +CYFLD_UDB_P_U_ALT_CNT__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_CNT__SIZE +CYFLD_UDB_P_U_ALT_CNT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE +CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_CNT_ALT_MODE +CYVAL_UDB_P_U_ALT_CNT_ALT_MODE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG24 +CYREG_UDB_P0_U0_CFG24 EQU 0x400f3058 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_SEL__OFFSET +CYFLD_UDB_P_U_RC_EN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_SEL__SIZE +CYFLD_UDB_P_U_RC_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_MODE__OFFSET +CYFLD_UDB_P_U_RC_EN_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_MODE__SIZE +CYFLD_UDB_P_U_RC_EN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_OFF +CYVAL_UDB_P_U_RC_EN_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_ON +CYVAL_UDB_P_U_RC_EN_MODE_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE +CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_LEVEL +CYVAL_UDB_P_U_RC_EN_MODE_LEVEL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_INV__OFFSET +CYFLD_UDB_P_U_RC_EN_INV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_INV__SIZE +CYFLD_UDB_P_U_RC_EN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_INV_NOINV +CYVAL_UDB_P_U_RC_EN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_INV_INVERT +CYVAL_UDB_P_U_RC_EN_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_INV__OFFSET +CYFLD_UDB_P_U_RC_INV__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_INV__SIZE +CYFLD_UDB_P_U_RC_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_INV_NOINV +CYVAL_UDB_P_U_RC_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_INV_INVERT +CYVAL_UDB_P_U_RC_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET +CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE +CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET +CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL1__SIZE +CYFLD_UDB_P_U_RC_RES_SEL1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG25 +CYREG_UDB_P0_U0_CFG25 EQU 0x400f3059 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG26 +CYREG_UDB_P0_U0_CFG26 EQU 0x400f305a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG27 +CYREG_UDB_P0_U0_CFG27 EQU 0x400f305b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG28 +CYREG_UDB_P0_U0_CFG28 EQU 0x400f305c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE +CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK +CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE +CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK +CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG29 +CYREG_UDB_P0_U0_CFG29 EQU 0x400f305d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_CK_SEL__OFFSET +CYFLD_UDB_P_U_DP_CK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_CK_SEL__SIZE +CYFLD_UDB_P_U_DP_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK +CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_CK_SEL__OFFSET +CYFLD_UDB_P_U_SC_CK_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_CK_SEL__SIZE +CYFLD_UDB_P_U_SC_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK +CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG30 +CYREG_UDB_P0_U0_CFG30 EQU 0x400f305e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_SEL__OFFSET +CYFLD_UDB_P_U_RES_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_SEL__SIZE +CYFLD_UDB_P_U_RES_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN0 +CYVAL_UDB_P_U_RES_SEL_RC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN1 +CYVAL_UDB_P_U_RES_SEL_RC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN2 +CYVAL_UDB_P_U_RES_SEL_RC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN3 +CYVAL_UDB_P_U_RES_SEL_RC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_POL__OFFSET +CYFLD_UDB_P_U_RES_POL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_POL__SIZE +CYFLD_UDB_P_U_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_POL_NEGATED +CYVAL_UDB_P_U_RES_POL_NEGATED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_POL_ASSERTED +CYVAL_UDB_P_U_RES_POL_ASSERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET +CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE +CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE +CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE +CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_GUDB_WR__OFFSET +CYFLD_UDB_P_U_GUDB_WR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_GUDB_WR__SIZE +CYFLD_UDB_P_U_GUDB_WR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_GUDB_WR_DISABLE +CYVAL_UDB_P_U_GUDB_WR_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_GUDB_WR_ENABLE +CYVAL_UDB_P_U_GUDB_WR_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RES_POL__OFFSET +CYFLD_UDB_P_U_DP_RES_POL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RES_POL__SIZE +CYFLD_UDB_P_U_DP_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RES_POL_NOINV +CYVAL_UDB_P_U_DP_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RES_POL_INVERT +CYVAL_UDB_P_U_DP_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_RES_POL__OFFSET +CYFLD_UDB_P_U_SC_RES_POL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_RES_POL__SIZE +CYFLD_UDB_P_U_SC_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_RES_POL_NOINV +CYVAL_UDB_P_U_SC_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_RES_POL_INVERT +CYVAL_UDB_P_U_SC_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG31 +CYREG_UDB_P0_U0_CFG31 EQU 0x400f305f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_RES__OFFSET +CYFLD_UDB_P_U_ALT_RES__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_RES__SIZE +CYFLD_UDB_P_U_ALT_RES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_RES_COMPATIBLE +CYVAL_UDB_P_U_ALT_RES_COMPATIBLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_RES_ALTERNATE +CYVAL_UDB_P_U_ALT_RES_ALTERNATE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_SYNC__OFFSET +CYFLD_UDB_P_U_EXT_SYNC__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_SYNC__SIZE +CYFLD_UDB_P_U_EXT_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_SYNC_DISABLE +CYVAL_UDB_P_U_EXT_SYNC_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_SYNC_ENABLE +CYVAL_UDB_P_U_EXT_SYNC_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_STAT__OFFSET +CYFLD_UDB_P_U_EN_RES_STAT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_STAT__SIZE +CYFLD_UDB_P_U_EN_RES_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_STAT_NEGATED +CYVAL_UDB_P_U_EN_RES_STAT_NEGATED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED +CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_DP__OFFSET +CYFLD_UDB_P_U_EN_RES_DP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_DP__SIZE +CYFLD_UDB_P_U_EN_RES_DP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_DP_DISABLE +CYVAL_UDB_P_U_EN_RES_DP_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_DP_ENABLE +CYVAL_UDB_P_U_EN_RES_DP_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET +CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CK_SEL__SIZE +CYFLD_UDB_P_U_EXT_CK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET +CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_RES_POL__SIZE +CYFLD_UDB_P_U_PLD0_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_RES_POL_NOINV +CYVAL_UDB_P_U_PLD0_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_RES_POL_INVERT +CYVAL_UDB_P_U_PLD0_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET +CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_RES_POL__SIZE +CYFLD_UDB_P_U_PLD1_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_RES_POL_NOINV +CYVAL_UDB_P_U_PLD1_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_RES_POL_INVERT +CYVAL_UDB_P_U_PLD1_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG0 +CYREG_UDB_P0_U0_DCFG0 EQU 0x400f3060 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SEL__OFFSET +CYFLD_UDB_P_U_CMP_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SEL__SIZE +CYFLD_UDB_P_U_CMP_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SEL_CFG_A +CYVAL_UDB_P_U_CMP_SEL_CFG_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SEL_CFG_B +CYVAL_UDB_P_U_CMP_SEL_CFG_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SEL__OFFSET +CYFLD_UDB_P_U_SI_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SEL__SIZE +CYFLD_UDB_P_U_SI_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SEL_CFG_A +CYVAL_UDB_P_U_SI_SEL_CFG_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SEL_CFG_B +CYVAL_UDB_P_U_SI_SEL_CFG_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SEL__OFFSET +CYFLD_UDB_P_U_CI_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SEL__SIZE +CYFLD_UDB_P_U_CI_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SEL_CFG_A +CYVAL_UDB_P_U_CI_SEL_CFG_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SEL_CFG_B +CYVAL_UDB_P_U_CI_SEL_CFG_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CFB_EN__OFFSET +CYFLD_UDB_P_U_CFB_EN__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CFB_EN__SIZE +CYFLD_UDB_P_U_CFB_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CFB_EN_DISABLE +CYVAL_UDB_P_U_CFB_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CFB_EN_ENABLE +CYVAL_UDB_P_U_CFB_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A1_WR_SRC__OFFSET +CYFLD_UDB_P_U_A1_WR_SRC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A1_WR_SRC__SIZE +CYFLD_UDB_P_U_A1_WR_SRC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE +CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_ALU +CYVAL_UDB_P_U_A1_WR_SRC_ALU EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_D1 +CYVAL_UDB_P_U_A1_WR_SRC_D1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_F1 +CYVAL_UDB_P_U_A1_WR_SRC_F1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A0_WR_SRC__OFFSET +CYFLD_UDB_P_U_A0_WR_SRC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A0_WR_SRC__SIZE +CYFLD_UDB_P_U_A0_WR_SRC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE +CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_ALU +CYVAL_UDB_P_U_A0_WR_SRC_ALU EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_D0 +CYVAL_UDB_P_U_A0_WR_SRC_D0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_F0 +CYVAL_UDB_P_U_A0_WR_SRC_F0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT__OFFSET +CYFLD_UDB_P_U_SHIFT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT__SIZE +CYFLD_UDB_P_U_SHIFT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_NOSHIFT +CYVAL_UDB_P_U_SHIFT_NOSHIFT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_LEFT +CYVAL_UDB_P_U_SHIFT_LEFT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_RIGHT +CYVAL_UDB_P_U_SHIFT_RIGHT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_SWAP +CYVAL_UDB_P_U_SHIFT_SWAP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_B__OFFSET +CYFLD_UDB_P_U_SRC_B__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_B__SIZE +CYFLD_UDB_P_U_SRC_B__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_D0 +CYVAL_UDB_P_U_SRC_B_D0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_D1 +CYVAL_UDB_P_U_SRC_B_D1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_A0 +CYVAL_UDB_P_U_SRC_B_A0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_A1 +CYVAL_UDB_P_U_SRC_B_A1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_A__OFFSET +CYFLD_UDB_P_U_SRC_A__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_A__SIZE +CYFLD_UDB_P_U_SRC_A__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_A_A0 +CYVAL_UDB_P_U_SRC_A_A0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_A_A1 +CYVAL_UDB_P_U_SRC_A_A1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FUNC__OFFSET +CYFLD_UDB_P_U_FUNC__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FUNC__SIZE +CYFLD_UDB_P_U_FUNC__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_PASS +CYVAL_UDB_P_U_FUNC_PASS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_INC_A +CYVAL_UDB_P_U_FUNC_INC_A EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_DEC_A +CYVAL_UDB_P_U_FUNC_DEC_A EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_ADD +CYVAL_UDB_P_U_FUNC_ADD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_SUB +CYVAL_UDB_P_U_FUNC_SUB EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_XOR +CYVAL_UDB_P_U_FUNC_XOR EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_AND +CYVAL_UDB_P_U_FUNC_AND EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_OR +CYVAL_UDB_P_U_FUNC_OR EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG1 +CYREG_UDB_P0_U0_DCFG1 EQU 0x400f3062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG2 +CYREG_UDB_P0_U0_DCFG2 EQU 0x400f3064 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG3 +CYREG_UDB_P0_U0_DCFG3 EQU 0x400f3066 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG4 +CYREG_UDB_P0_U0_DCFG4 EQU 0x400f3068 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG5 +CYREG_UDB_P0_U0_DCFG5 EQU 0x400f306a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG6 +CYREG_UDB_P0_U0_DCFG6 EQU 0x400f306c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG7 +CYREG_UDB_P0_U0_DCFG7 EQU 0x400f306e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U1_BASE +CYDEV_UDB_P0_U1_BASE EQU 0x400f3080 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U1_SIZE +CYDEV_UDB_P0_U1_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT0 +CYREG_UDB_P0_U1_PLD_IT0 EQU 0x400f3080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT1 +CYREG_UDB_P0_U1_PLD_IT1 EQU 0x400f3084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT2 +CYREG_UDB_P0_U1_PLD_IT2 EQU 0x400f3088 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT3 +CYREG_UDB_P0_U1_PLD_IT3 EQU 0x400f308c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT4 +CYREG_UDB_P0_U1_PLD_IT4 EQU 0x400f3090 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT5 +CYREG_UDB_P0_U1_PLD_IT5 EQU 0x400f3094 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT6 +CYREG_UDB_P0_U1_PLD_IT6 EQU 0x400f3098 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT7 +CYREG_UDB_P0_U1_PLD_IT7 EQU 0x400f309c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT8 +CYREG_UDB_P0_U1_PLD_IT8 EQU 0x400f30a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT9 +CYREG_UDB_P0_U1_PLD_IT9 EQU 0x400f30a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT10 +CYREG_UDB_P0_U1_PLD_IT10 EQU 0x400f30a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT11 +CYREG_UDB_P0_U1_PLD_IT11 EQU 0x400f30ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT0 +CYREG_UDB_P0_U1_PLD_ORT0 EQU 0x400f30b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT1 +CYREG_UDB_P0_U1_PLD_ORT1 EQU 0x400f30b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT2 +CYREG_UDB_P0_U1_PLD_ORT2 EQU 0x400f30b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT3 +CYREG_UDB_P0_U1_PLD_ORT3 EQU 0x400f30b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST EQU 0x400f30b8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB +CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB EQU 0x400f30ba + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_SET_RESET +CYREG_UDB_P0_U1_PLD_MC_SET_RESET EQU 0x400f30bc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS +CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS EQU 0x400f30be + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG0 +CYREG_UDB_P0_U1_CFG0 EQU 0x400f30c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG1 +CYREG_UDB_P0_U1_CFG1 EQU 0x400f30c1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG2 +CYREG_UDB_P0_U1_CFG2 EQU 0x400f30c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG3 +CYREG_UDB_P0_U1_CFG3 EQU 0x400f30c3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG4 +CYREG_UDB_P0_U1_CFG4 EQU 0x400f30c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG5 +CYREG_UDB_P0_U1_CFG5 EQU 0x400f30c5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG6 +CYREG_UDB_P0_U1_CFG6 EQU 0x400f30c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG7 +CYREG_UDB_P0_U1_CFG7 EQU 0x400f30c7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG8 +CYREG_UDB_P0_U1_CFG8 EQU 0x400f30c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG9 +CYREG_UDB_P0_U1_CFG9 EQU 0x400f30c9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG10 +CYREG_UDB_P0_U1_CFG10 EQU 0x400f30ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG11 +CYREG_UDB_P0_U1_CFG11 EQU 0x400f30cb + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG12 +CYREG_UDB_P0_U1_CFG12 EQU 0x400f30cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG13 +CYREG_UDB_P0_U1_CFG13 EQU 0x400f30cd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG14 +CYREG_UDB_P0_U1_CFG14 EQU 0x400f30ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG15 +CYREG_UDB_P0_U1_CFG15 EQU 0x400f30cf + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG16 +CYREG_UDB_P0_U1_CFG16 EQU 0x400f30d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG17 +CYREG_UDB_P0_U1_CFG17 EQU 0x400f30d1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG18 +CYREG_UDB_P0_U1_CFG18 EQU 0x400f30d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG19 +CYREG_UDB_P0_U1_CFG19 EQU 0x400f30d3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG20 +CYREG_UDB_P0_U1_CFG20 EQU 0x400f30d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG21 +CYREG_UDB_P0_U1_CFG21 EQU 0x400f30d5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG22 +CYREG_UDB_P0_U1_CFG22 EQU 0x400f30d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG23 +CYREG_UDB_P0_U1_CFG23 EQU 0x400f30d7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG24 +CYREG_UDB_P0_U1_CFG24 EQU 0x400f30d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG25 +CYREG_UDB_P0_U1_CFG25 EQU 0x400f30d9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG26 +CYREG_UDB_P0_U1_CFG26 EQU 0x400f30da + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG27 +CYREG_UDB_P0_U1_CFG27 EQU 0x400f30db + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG28 +CYREG_UDB_P0_U1_CFG28 EQU 0x400f30dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG29 +CYREG_UDB_P0_U1_CFG29 EQU 0x400f30dd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG30 +CYREG_UDB_P0_U1_CFG30 EQU 0x400f30de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG31 +CYREG_UDB_P0_U1_CFG31 EQU 0x400f30df + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG0 +CYREG_UDB_P0_U1_DCFG0 EQU 0x400f30e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG1 +CYREG_UDB_P0_U1_DCFG1 EQU 0x400f30e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG2 +CYREG_UDB_P0_U1_DCFG2 EQU 0x400f30e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG3 +CYREG_UDB_P0_U1_DCFG3 EQU 0x400f30e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG4 +CYREG_UDB_P0_U1_DCFG4 EQU 0x400f30e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG5 +CYREG_UDB_P0_U1_DCFG5 EQU 0x400f30ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG6 +CYREG_UDB_P0_U1_DCFG6 EQU 0x400f30ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG7 +CYREG_UDB_P0_U1_DCFG7 EQU 0x400f30ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_ROUTE_BASE +CYDEV_UDB_P0_ROUTE_BASE EQU 0x400f3100 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_ROUTE_SIZE +CYDEV_UDB_P0_ROUTE_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC0 +CYREG_UDB_P0_ROUTE_HC0 EQU 0x400f3100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET +CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE +CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC1 +CYREG_UDB_P0_ROUTE_HC1 EQU 0x400f3101 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC2 +CYREG_UDB_P0_ROUTE_HC2 EQU 0x400f3102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC3 +CYREG_UDB_P0_ROUTE_HC3 EQU 0x400f3103 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC4 +CYREG_UDB_P0_ROUTE_HC4 EQU 0x400f3104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC5 +CYREG_UDB_P0_ROUTE_HC5 EQU 0x400f3105 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC6 +CYREG_UDB_P0_ROUTE_HC6 EQU 0x400f3106 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC7 +CYREG_UDB_P0_ROUTE_HC7 EQU 0x400f3107 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC8 +CYREG_UDB_P0_ROUTE_HC8 EQU 0x400f3108 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC9 +CYREG_UDB_P0_ROUTE_HC9 EQU 0x400f3109 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC10 +CYREG_UDB_P0_ROUTE_HC10 EQU 0x400f310a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC11 +CYREG_UDB_P0_ROUTE_HC11 EQU 0x400f310b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC12 +CYREG_UDB_P0_ROUTE_HC12 EQU 0x400f310c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC13 +CYREG_UDB_P0_ROUTE_HC13 EQU 0x400f310d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC14 +CYREG_UDB_P0_ROUTE_HC14 EQU 0x400f310e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC15 +CYREG_UDB_P0_ROUTE_HC15 EQU 0x400f310f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC16 +CYREG_UDB_P0_ROUTE_HC16 EQU 0x400f3110 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC17 +CYREG_UDB_P0_ROUTE_HC17 EQU 0x400f3111 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC18 +CYREG_UDB_P0_ROUTE_HC18 EQU 0x400f3112 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC19 +CYREG_UDB_P0_ROUTE_HC19 EQU 0x400f3113 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC20 +CYREG_UDB_P0_ROUTE_HC20 EQU 0x400f3114 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC21 +CYREG_UDB_P0_ROUTE_HC21 EQU 0x400f3115 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC22 +CYREG_UDB_P0_ROUTE_HC22 EQU 0x400f3116 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC23 +CYREG_UDB_P0_ROUTE_HC23 EQU 0x400f3117 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC24 +CYREG_UDB_P0_ROUTE_HC24 EQU 0x400f3118 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC25 +CYREG_UDB_P0_ROUTE_HC25 EQU 0x400f3119 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC26 +CYREG_UDB_P0_ROUTE_HC26 EQU 0x400f311a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC27 +CYREG_UDB_P0_ROUTE_HC27 EQU 0x400f311b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC28 +CYREG_UDB_P0_ROUTE_HC28 EQU 0x400f311c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC29 +CYREG_UDB_P0_ROUTE_HC29 EQU 0x400f311d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC30 +CYREG_UDB_P0_ROUTE_HC30 EQU 0x400f311e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC31 +CYREG_UDB_P0_ROUTE_HC31 EQU 0x400f311f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC32 +CYREG_UDB_P0_ROUTE_HC32 EQU 0x400f3120 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC33 +CYREG_UDB_P0_ROUTE_HC33 EQU 0x400f3121 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC34 +CYREG_UDB_P0_ROUTE_HC34 EQU 0x400f3122 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC35 +CYREG_UDB_P0_ROUTE_HC35 EQU 0x400f3123 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC36 +CYREG_UDB_P0_ROUTE_HC36 EQU 0x400f3124 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC37 +CYREG_UDB_P0_ROUTE_HC37 EQU 0x400f3125 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC38 +CYREG_UDB_P0_ROUTE_HC38 EQU 0x400f3126 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC39 +CYREG_UDB_P0_ROUTE_HC39 EQU 0x400f3127 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC40 +CYREG_UDB_P0_ROUTE_HC40 EQU 0x400f3128 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC41 +CYREG_UDB_P0_ROUTE_HC41 EQU 0x400f3129 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC42 +CYREG_UDB_P0_ROUTE_HC42 EQU 0x400f312a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC43 +CYREG_UDB_P0_ROUTE_HC43 EQU 0x400f312b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC44 +CYREG_UDB_P0_ROUTE_HC44 EQU 0x400f312c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC45 +CYREG_UDB_P0_ROUTE_HC45 EQU 0x400f312d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC46 +CYREG_UDB_P0_ROUTE_HC46 EQU 0x400f312e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC47 +CYREG_UDB_P0_ROUTE_HC47 EQU 0x400f312f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC48 +CYREG_UDB_P0_ROUTE_HC48 EQU 0x400f3130 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC49 +CYREG_UDB_P0_ROUTE_HC49 EQU 0x400f3131 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC50 +CYREG_UDB_P0_ROUTE_HC50 EQU 0x400f3132 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC51 +CYREG_UDB_P0_ROUTE_HC51 EQU 0x400f3133 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC52 +CYREG_UDB_P0_ROUTE_HC52 EQU 0x400f3134 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC53 +CYREG_UDB_P0_ROUTE_HC53 EQU 0x400f3135 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC54 +CYREG_UDB_P0_ROUTE_HC54 EQU 0x400f3136 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC55 +CYREG_UDB_P0_ROUTE_HC55 EQU 0x400f3137 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC56 +CYREG_UDB_P0_ROUTE_HC56 EQU 0x400f3138 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC57 +CYREG_UDB_P0_ROUTE_HC57 EQU 0x400f3139 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC58 +CYREG_UDB_P0_ROUTE_HC58 EQU 0x400f313a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC59 +CYREG_UDB_P0_ROUTE_HC59 EQU 0x400f313b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC60 +CYREG_UDB_P0_ROUTE_HC60 EQU 0x400f313c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC61 +CYREG_UDB_P0_ROUTE_HC61 EQU 0x400f313d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC62 +CYREG_UDB_P0_ROUTE_HC62 EQU 0x400f313e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC63 +CYREG_UDB_P0_ROUTE_HC63 EQU 0x400f313f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC64 +CYREG_UDB_P0_ROUTE_HC64 EQU 0x400f3140 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC65 +CYREG_UDB_P0_ROUTE_HC65 EQU 0x400f3141 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC66 +CYREG_UDB_P0_ROUTE_HC66 EQU 0x400f3142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC67 +CYREG_UDB_P0_ROUTE_HC67 EQU 0x400f3143 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC68 +CYREG_UDB_P0_ROUTE_HC68 EQU 0x400f3144 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC69 +CYREG_UDB_P0_ROUTE_HC69 EQU 0x400f3145 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC70 +CYREG_UDB_P0_ROUTE_HC70 EQU 0x400f3146 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC71 +CYREG_UDB_P0_ROUTE_HC71 EQU 0x400f3147 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC72 +CYREG_UDB_P0_ROUTE_HC72 EQU 0x400f3148 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC73 +CYREG_UDB_P0_ROUTE_HC73 EQU 0x400f3149 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC74 +CYREG_UDB_P0_ROUTE_HC74 EQU 0x400f314a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC75 +CYREG_UDB_P0_ROUTE_HC75 EQU 0x400f314b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC76 +CYREG_UDB_P0_ROUTE_HC76 EQU 0x400f314c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC77 +CYREG_UDB_P0_ROUTE_HC77 EQU 0x400f314d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC78 +CYREG_UDB_P0_ROUTE_HC78 EQU 0x400f314e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC79 +CYREG_UDB_P0_ROUTE_HC79 EQU 0x400f314f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC80 +CYREG_UDB_P0_ROUTE_HC80 EQU 0x400f3150 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC81 +CYREG_UDB_P0_ROUTE_HC81 EQU 0x400f3151 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC82 +CYREG_UDB_P0_ROUTE_HC82 EQU 0x400f3152 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC83 +CYREG_UDB_P0_ROUTE_HC83 EQU 0x400f3153 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC84 +CYREG_UDB_P0_ROUTE_HC84 EQU 0x400f3154 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC85 +CYREG_UDB_P0_ROUTE_HC85 EQU 0x400f3155 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC86 +CYREG_UDB_P0_ROUTE_HC86 EQU 0x400f3156 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC87 +CYREG_UDB_P0_ROUTE_HC87 EQU 0x400f3157 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC88 +CYREG_UDB_P0_ROUTE_HC88 EQU 0x400f3158 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC89 +CYREG_UDB_P0_ROUTE_HC89 EQU 0x400f3159 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC90 +CYREG_UDB_P0_ROUTE_HC90 EQU 0x400f315a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC91 +CYREG_UDB_P0_ROUTE_HC91 EQU 0x400f315b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC92 +CYREG_UDB_P0_ROUTE_HC92 EQU 0x400f315c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC93 +CYREG_UDB_P0_ROUTE_HC93 EQU 0x400f315d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC94 +CYREG_UDB_P0_ROUTE_HC94 EQU 0x400f315e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC95 +CYREG_UDB_P0_ROUTE_HC95 EQU 0x400f315f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC96 +CYREG_UDB_P0_ROUTE_HC96 EQU 0x400f3160 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC97 +CYREG_UDB_P0_ROUTE_HC97 EQU 0x400f3161 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC98 +CYREG_UDB_P0_ROUTE_HC98 EQU 0x400f3162 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC99 +CYREG_UDB_P0_ROUTE_HC99 EQU 0x400f3163 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC100 +CYREG_UDB_P0_ROUTE_HC100 EQU 0x400f3164 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC101 +CYREG_UDB_P0_ROUTE_HC101 EQU 0x400f3165 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC102 +CYREG_UDB_P0_ROUTE_HC102 EQU 0x400f3166 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC103 +CYREG_UDB_P0_ROUTE_HC103 EQU 0x400f3167 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC104 +CYREG_UDB_P0_ROUTE_HC104 EQU 0x400f3168 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC105 +CYREG_UDB_P0_ROUTE_HC105 EQU 0x400f3169 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC106 +CYREG_UDB_P0_ROUTE_HC106 EQU 0x400f316a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC107 +CYREG_UDB_P0_ROUTE_HC107 EQU 0x400f316b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC108 +CYREG_UDB_P0_ROUTE_HC108 EQU 0x400f316c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC109 +CYREG_UDB_P0_ROUTE_HC109 EQU 0x400f316d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC110 +CYREG_UDB_P0_ROUTE_HC110 EQU 0x400f316e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC111 +CYREG_UDB_P0_ROUTE_HC111 EQU 0x400f316f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC112 +CYREG_UDB_P0_ROUTE_HC112 EQU 0x400f3170 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC113 +CYREG_UDB_P0_ROUTE_HC113 EQU 0x400f3171 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC114 +CYREG_UDB_P0_ROUTE_HC114 EQU 0x400f3172 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC115 +CYREG_UDB_P0_ROUTE_HC115 EQU 0x400f3173 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC116 +CYREG_UDB_P0_ROUTE_HC116 EQU 0x400f3174 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC117 +CYREG_UDB_P0_ROUTE_HC117 EQU 0x400f3175 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC118 +CYREG_UDB_P0_ROUTE_HC118 EQU 0x400f3176 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC119 +CYREG_UDB_P0_ROUTE_HC119 EQU 0x400f3177 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC120 +CYREG_UDB_P0_ROUTE_HC120 EQU 0x400f3178 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC121 +CYREG_UDB_P0_ROUTE_HC121 EQU 0x400f3179 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC122 +CYREG_UDB_P0_ROUTE_HC122 EQU 0x400f317a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC123 +CYREG_UDB_P0_ROUTE_HC123 EQU 0x400f317b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC124 +CYREG_UDB_P0_ROUTE_HC124 EQU 0x400f317c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC125 +CYREG_UDB_P0_ROUTE_HC125 EQU 0x400f317d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC126 +CYREG_UDB_P0_ROUTE_HC126 EQU 0x400f317e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC127 +CYREG_UDB_P0_ROUTE_HC127 EQU 0x400f317f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L0 +CYREG_UDB_P0_ROUTE_HV_L0 EQU 0x400f3180 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET +CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE +CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L1 +CYREG_UDB_P0_ROUTE_HV_L1 EQU 0x400f3181 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L2 +CYREG_UDB_P0_ROUTE_HV_L2 EQU 0x400f3182 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L3 +CYREG_UDB_P0_ROUTE_HV_L3 EQU 0x400f3183 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L4 +CYREG_UDB_P0_ROUTE_HV_L4 EQU 0x400f3184 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L5 +CYREG_UDB_P0_ROUTE_HV_L5 EQU 0x400f3185 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L6 +CYREG_UDB_P0_ROUTE_HV_L6 EQU 0x400f3186 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L7 +CYREG_UDB_P0_ROUTE_HV_L7 EQU 0x400f3187 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L8 +CYREG_UDB_P0_ROUTE_HV_L8 EQU 0x400f3188 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L9 +CYREG_UDB_P0_ROUTE_HV_L9 EQU 0x400f3189 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L10 +CYREG_UDB_P0_ROUTE_HV_L10 EQU 0x400f318a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L11 +CYREG_UDB_P0_ROUTE_HV_L11 EQU 0x400f318b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L12 +CYREG_UDB_P0_ROUTE_HV_L12 EQU 0x400f318c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L13 +CYREG_UDB_P0_ROUTE_HV_L13 EQU 0x400f318d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L14 +CYREG_UDB_P0_ROUTE_HV_L14 EQU 0x400f318e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L15 +CYREG_UDB_P0_ROUTE_HV_L15 EQU 0x400f318f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS0 +CYREG_UDB_P0_ROUTE_HS0 EQU 0x400f3190 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET +CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE +CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS1 +CYREG_UDB_P0_ROUTE_HS1 EQU 0x400f3191 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS2 +CYREG_UDB_P0_ROUTE_HS2 EQU 0x400f3192 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS3 +CYREG_UDB_P0_ROUTE_HS3 EQU 0x400f3193 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS4 +CYREG_UDB_P0_ROUTE_HS4 EQU 0x400f3194 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS5 +CYREG_UDB_P0_ROUTE_HS5 EQU 0x400f3195 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS6 +CYREG_UDB_P0_ROUTE_HS6 EQU 0x400f3196 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS7 +CYREG_UDB_P0_ROUTE_HS7 EQU 0x400f3197 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS8 +CYREG_UDB_P0_ROUTE_HS8 EQU 0x400f3198 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS9 +CYREG_UDB_P0_ROUTE_HS9 EQU 0x400f3199 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS10 +CYREG_UDB_P0_ROUTE_HS10 EQU 0x400f319a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS11 +CYREG_UDB_P0_ROUTE_HS11 EQU 0x400f319b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS12 +CYREG_UDB_P0_ROUTE_HS12 EQU 0x400f319c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS13 +CYREG_UDB_P0_ROUTE_HS13 EQU 0x400f319d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS14 +CYREG_UDB_P0_ROUTE_HS14 EQU 0x400f319e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS15 +CYREG_UDB_P0_ROUTE_HS15 EQU 0x400f319f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS16 +CYREG_UDB_P0_ROUTE_HS16 EQU 0x400f31a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS17 +CYREG_UDB_P0_ROUTE_HS17 EQU 0x400f31a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS18 +CYREG_UDB_P0_ROUTE_HS18 EQU 0x400f31a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS19 +CYREG_UDB_P0_ROUTE_HS19 EQU 0x400f31a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS20 +CYREG_UDB_P0_ROUTE_HS20 EQU 0x400f31a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS21 +CYREG_UDB_P0_ROUTE_HS21 EQU 0x400f31a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS22 +CYREG_UDB_P0_ROUTE_HS22 EQU 0x400f31a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS23 +CYREG_UDB_P0_ROUTE_HS23 EQU 0x400f31a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R0 +CYREG_UDB_P0_ROUTE_HV_R0 EQU 0x400f31a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R1 +CYREG_UDB_P0_ROUTE_HV_R1 EQU 0x400f31a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R2 +CYREG_UDB_P0_ROUTE_HV_R2 EQU 0x400f31aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R3 +CYREG_UDB_P0_ROUTE_HV_R3 EQU 0x400f31ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R4 +CYREG_UDB_P0_ROUTE_HV_R4 EQU 0x400f31ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R5 +CYREG_UDB_P0_ROUTE_HV_R5 EQU 0x400f31ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R6 +CYREG_UDB_P0_ROUTE_HV_R6 EQU 0x400f31ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R7 +CYREG_UDB_P0_ROUTE_HV_R7 EQU 0x400f31af + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R8 +CYREG_UDB_P0_ROUTE_HV_R8 EQU 0x400f31b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R9 +CYREG_UDB_P0_ROUTE_HV_R9 EQU 0x400f31b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R10 +CYREG_UDB_P0_ROUTE_HV_R10 EQU 0x400f31b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R11 +CYREG_UDB_P0_ROUTE_HV_R11 EQU 0x400f31b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R12 +CYREG_UDB_P0_ROUTE_HV_R12 EQU 0x400f31b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R13 +CYREG_UDB_P0_ROUTE_HV_R13 EQU 0x400f31b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R14 +CYREG_UDB_P0_ROUTE_HV_R14 EQU 0x400f31b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R15 +CYREG_UDB_P0_ROUTE_HV_R15 EQU 0x400f31b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD0IN0 +CYREG_UDB_P0_ROUTE_PLD0IN0 EQU 0x400f31c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET +CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP__SIZE +CYFLD_UDB_P_ROUTE_PI_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET +CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT__SIZE +CYFLD_UDB_P_ROUTE_PI_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD0IN1 +CYREG_UDB_P0_ROUTE_PLD0IN1 EQU 0x400f31c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD0IN2 +CYREG_UDB_P0_ROUTE_PLD0IN2 EQU 0x400f31c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD1IN0 +CYREG_UDB_P0_ROUTE_PLD1IN0 EQU 0x400f31ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD1IN1 +CYREG_UDB_P0_ROUTE_PLD1IN1 EQU 0x400f31cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD1IN2 +CYREG_UDB_P0_ROUTE_PLD1IN2 EQU 0x400f31ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_DPIN0 +CYREG_UDB_P0_ROUTE_DPIN0 EQU 0x400f31d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_DPIN1 +CYREG_UDB_P0_ROUTE_DPIN1 EQU 0x400f31d2 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET +CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE +CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET +CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE +CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_SCIN +CYREG_UDB_P0_ROUTE_SCIN EQU 0x400f31d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_SCIOIN +CYREG_UDB_P0_ROUTE_SCIOIN EQU 0x400f31d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_RCIN +CYREG_UDB_P0_ROUTE_RCIN EQU 0x400f31de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS0 +CYREG_UDB_P0_ROUTE_VS0 EQU 0x400f31e0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET +CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_TOP__SIZE +CYFLD_UDB_P_ROUTE_VS_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET +CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_BOT__SIZE +CYFLD_UDB_P_ROUTE_VS_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS1 +CYREG_UDB_P0_ROUTE_VS1 EQU 0x400f31e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS2 +CYREG_UDB_P0_ROUTE_VS2 EQU 0x400f31e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS3 +CYREG_UDB_P0_ROUTE_VS3 EQU 0x400f31e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS4 +CYREG_UDB_P0_ROUTE_VS4 EQU 0x400f31e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS5 +CYREG_UDB_P0_ROUTE_VS5 EQU 0x400f31ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS6 +CYREG_UDB_P0_ROUTE_VS6 EQU 0x400f31ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS7 +CYREG_UDB_P0_ROUTE_VS7 EQU 0x400f31ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_BASE +CYDEV_UDB_P1_BASE EQU 0x400f3200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_SIZE +CYDEV_UDB_P1_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U0_BASE +CYDEV_UDB_P1_U0_BASE EQU 0x400f3200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U0_SIZE +CYDEV_UDB_P1_U0_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT0 +CYREG_UDB_P1_U0_PLD_IT0 EQU 0x400f3200 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT1 +CYREG_UDB_P1_U0_PLD_IT1 EQU 0x400f3204 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT2 +CYREG_UDB_P1_U0_PLD_IT2 EQU 0x400f3208 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT3 +CYREG_UDB_P1_U0_PLD_IT3 EQU 0x400f320c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT4 +CYREG_UDB_P1_U0_PLD_IT4 EQU 0x400f3210 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT5 +CYREG_UDB_P1_U0_PLD_IT5 EQU 0x400f3214 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT6 +CYREG_UDB_P1_U0_PLD_IT6 EQU 0x400f3218 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT7 +CYREG_UDB_P1_U0_PLD_IT7 EQU 0x400f321c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT8 +CYREG_UDB_P1_U0_PLD_IT8 EQU 0x400f3220 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT9 +CYREG_UDB_P1_U0_PLD_IT9 EQU 0x400f3224 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT10 +CYREG_UDB_P1_U0_PLD_IT10 EQU 0x400f3228 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT11 +CYREG_UDB_P1_U0_PLD_IT11 EQU 0x400f322c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT0 +CYREG_UDB_P1_U0_PLD_ORT0 EQU 0x400f3230 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT1 +CYREG_UDB_P1_U0_PLD_ORT1 EQU 0x400f3232 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT2 +CYREG_UDB_P1_U0_PLD_ORT2 EQU 0x400f3234 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT3 +CYREG_UDB_P1_U0_PLD_ORT3 EQU 0x400f3236 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST EQU 0x400f3238 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB +CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB EQU 0x400f323a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_SET_RESET +CYREG_UDB_P1_U0_PLD_MC_SET_RESET EQU 0x400f323c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS +CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS EQU 0x400f323e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG0 +CYREG_UDB_P1_U0_CFG0 EQU 0x400f3240 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG1 +CYREG_UDB_P1_U0_CFG1 EQU 0x400f3241 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG2 +CYREG_UDB_P1_U0_CFG2 EQU 0x400f3242 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG3 +CYREG_UDB_P1_U0_CFG3 EQU 0x400f3243 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG4 +CYREG_UDB_P1_U0_CFG4 EQU 0x400f3244 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG5 +CYREG_UDB_P1_U0_CFG5 EQU 0x400f3245 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG6 +CYREG_UDB_P1_U0_CFG6 EQU 0x400f3246 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG7 +CYREG_UDB_P1_U0_CFG7 EQU 0x400f3247 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG8 +CYREG_UDB_P1_U0_CFG8 EQU 0x400f3248 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG9 +CYREG_UDB_P1_U0_CFG9 EQU 0x400f3249 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG10 +CYREG_UDB_P1_U0_CFG10 EQU 0x400f324a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG11 +CYREG_UDB_P1_U0_CFG11 EQU 0x400f324b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG12 +CYREG_UDB_P1_U0_CFG12 EQU 0x400f324c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG13 +CYREG_UDB_P1_U0_CFG13 EQU 0x400f324d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG14 +CYREG_UDB_P1_U0_CFG14 EQU 0x400f324e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG15 +CYREG_UDB_P1_U0_CFG15 EQU 0x400f324f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG16 +CYREG_UDB_P1_U0_CFG16 EQU 0x400f3250 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG17 +CYREG_UDB_P1_U0_CFG17 EQU 0x400f3251 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG18 +CYREG_UDB_P1_U0_CFG18 EQU 0x400f3252 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG19 +CYREG_UDB_P1_U0_CFG19 EQU 0x400f3253 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG20 +CYREG_UDB_P1_U0_CFG20 EQU 0x400f3254 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG21 +CYREG_UDB_P1_U0_CFG21 EQU 0x400f3255 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG22 +CYREG_UDB_P1_U0_CFG22 EQU 0x400f3256 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG23 +CYREG_UDB_P1_U0_CFG23 EQU 0x400f3257 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG24 +CYREG_UDB_P1_U0_CFG24 EQU 0x400f3258 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG25 +CYREG_UDB_P1_U0_CFG25 EQU 0x400f3259 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG26 +CYREG_UDB_P1_U0_CFG26 EQU 0x400f325a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG27 +CYREG_UDB_P1_U0_CFG27 EQU 0x400f325b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG28 +CYREG_UDB_P1_U0_CFG28 EQU 0x400f325c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG29 +CYREG_UDB_P1_U0_CFG29 EQU 0x400f325d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG30 +CYREG_UDB_P1_U0_CFG30 EQU 0x400f325e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG31 +CYREG_UDB_P1_U0_CFG31 EQU 0x400f325f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG0 +CYREG_UDB_P1_U0_DCFG0 EQU 0x400f3260 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG1 +CYREG_UDB_P1_U0_DCFG1 EQU 0x400f3262 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG2 +CYREG_UDB_P1_U0_DCFG2 EQU 0x400f3264 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG3 +CYREG_UDB_P1_U0_DCFG3 EQU 0x400f3266 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG4 +CYREG_UDB_P1_U0_DCFG4 EQU 0x400f3268 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG5 +CYREG_UDB_P1_U0_DCFG5 EQU 0x400f326a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG6 +CYREG_UDB_P1_U0_DCFG6 EQU 0x400f326c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG7 +CYREG_UDB_P1_U0_DCFG7 EQU 0x400f326e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U1_BASE +CYDEV_UDB_P1_U1_BASE EQU 0x400f3280 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U1_SIZE +CYDEV_UDB_P1_U1_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT0 +CYREG_UDB_P1_U1_PLD_IT0 EQU 0x400f3280 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT1 +CYREG_UDB_P1_U1_PLD_IT1 EQU 0x400f3284 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT2 +CYREG_UDB_P1_U1_PLD_IT2 EQU 0x400f3288 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT3 +CYREG_UDB_P1_U1_PLD_IT3 EQU 0x400f328c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT4 +CYREG_UDB_P1_U1_PLD_IT4 EQU 0x400f3290 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT5 +CYREG_UDB_P1_U1_PLD_IT5 EQU 0x400f3294 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT6 +CYREG_UDB_P1_U1_PLD_IT6 EQU 0x400f3298 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT7 +CYREG_UDB_P1_U1_PLD_IT7 EQU 0x400f329c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT8 +CYREG_UDB_P1_U1_PLD_IT8 EQU 0x400f32a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT9 +CYREG_UDB_P1_U1_PLD_IT9 EQU 0x400f32a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT10 +CYREG_UDB_P1_U1_PLD_IT10 EQU 0x400f32a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT11 +CYREG_UDB_P1_U1_PLD_IT11 EQU 0x400f32ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT0 +CYREG_UDB_P1_U1_PLD_ORT0 EQU 0x400f32b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT1 +CYREG_UDB_P1_U1_PLD_ORT1 EQU 0x400f32b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT2 +CYREG_UDB_P1_U1_PLD_ORT2 EQU 0x400f32b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT3 +CYREG_UDB_P1_U1_PLD_ORT3 EQU 0x400f32b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST EQU 0x400f32b8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB +CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB EQU 0x400f32ba + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_SET_RESET +CYREG_UDB_P1_U1_PLD_MC_SET_RESET EQU 0x400f32bc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS +CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS EQU 0x400f32be + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG0 +CYREG_UDB_P1_U1_CFG0 EQU 0x400f32c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG1 +CYREG_UDB_P1_U1_CFG1 EQU 0x400f32c1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG2 +CYREG_UDB_P1_U1_CFG2 EQU 0x400f32c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG3 +CYREG_UDB_P1_U1_CFG3 EQU 0x400f32c3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG4 +CYREG_UDB_P1_U1_CFG4 EQU 0x400f32c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG5 +CYREG_UDB_P1_U1_CFG5 EQU 0x400f32c5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG6 +CYREG_UDB_P1_U1_CFG6 EQU 0x400f32c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG7 +CYREG_UDB_P1_U1_CFG7 EQU 0x400f32c7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG8 +CYREG_UDB_P1_U1_CFG8 EQU 0x400f32c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG9 +CYREG_UDB_P1_U1_CFG9 EQU 0x400f32c9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG10 +CYREG_UDB_P1_U1_CFG10 EQU 0x400f32ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG11 +CYREG_UDB_P1_U1_CFG11 EQU 0x400f32cb + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG12 +CYREG_UDB_P1_U1_CFG12 EQU 0x400f32cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG13 +CYREG_UDB_P1_U1_CFG13 EQU 0x400f32cd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG14 +CYREG_UDB_P1_U1_CFG14 EQU 0x400f32ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG15 +CYREG_UDB_P1_U1_CFG15 EQU 0x400f32cf + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG16 +CYREG_UDB_P1_U1_CFG16 EQU 0x400f32d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG17 +CYREG_UDB_P1_U1_CFG17 EQU 0x400f32d1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG18 +CYREG_UDB_P1_U1_CFG18 EQU 0x400f32d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG19 +CYREG_UDB_P1_U1_CFG19 EQU 0x400f32d3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG20 +CYREG_UDB_P1_U1_CFG20 EQU 0x400f32d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG21 +CYREG_UDB_P1_U1_CFG21 EQU 0x400f32d5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG22 +CYREG_UDB_P1_U1_CFG22 EQU 0x400f32d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG23 +CYREG_UDB_P1_U1_CFG23 EQU 0x400f32d7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG24 +CYREG_UDB_P1_U1_CFG24 EQU 0x400f32d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG25 +CYREG_UDB_P1_U1_CFG25 EQU 0x400f32d9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG26 +CYREG_UDB_P1_U1_CFG26 EQU 0x400f32da + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG27 +CYREG_UDB_P1_U1_CFG27 EQU 0x400f32db + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG28 +CYREG_UDB_P1_U1_CFG28 EQU 0x400f32dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG29 +CYREG_UDB_P1_U1_CFG29 EQU 0x400f32dd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG30 +CYREG_UDB_P1_U1_CFG30 EQU 0x400f32de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG31 +CYREG_UDB_P1_U1_CFG31 EQU 0x400f32df + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG0 +CYREG_UDB_P1_U1_DCFG0 EQU 0x400f32e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG1 +CYREG_UDB_P1_U1_DCFG1 EQU 0x400f32e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG2 +CYREG_UDB_P1_U1_DCFG2 EQU 0x400f32e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG3 +CYREG_UDB_P1_U1_DCFG3 EQU 0x400f32e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG4 +CYREG_UDB_P1_U1_DCFG4 EQU 0x400f32e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG5 +CYREG_UDB_P1_U1_DCFG5 EQU 0x400f32ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG6 +CYREG_UDB_P1_U1_DCFG6 EQU 0x400f32ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG7 +CYREG_UDB_P1_U1_DCFG7 EQU 0x400f32ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_ROUTE_BASE +CYDEV_UDB_P1_ROUTE_BASE EQU 0x400f3300 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_ROUTE_SIZE +CYDEV_UDB_P1_ROUTE_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC0 +CYREG_UDB_P1_ROUTE_HC0 EQU 0x400f3300 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC1 +CYREG_UDB_P1_ROUTE_HC1 EQU 0x400f3301 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC2 +CYREG_UDB_P1_ROUTE_HC2 EQU 0x400f3302 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC3 +CYREG_UDB_P1_ROUTE_HC3 EQU 0x400f3303 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC4 +CYREG_UDB_P1_ROUTE_HC4 EQU 0x400f3304 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC5 +CYREG_UDB_P1_ROUTE_HC5 EQU 0x400f3305 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC6 +CYREG_UDB_P1_ROUTE_HC6 EQU 0x400f3306 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC7 +CYREG_UDB_P1_ROUTE_HC7 EQU 0x400f3307 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC8 +CYREG_UDB_P1_ROUTE_HC8 EQU 0x400f3308 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC9 +CYREG_UDB_P1_ROUTE_HC9 EQU 0x400f3309 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC10 +CYREG_UDB_P1_ROUTE_HC10 EQU 0x400f330a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC11 +CYREG_UDB_P1_ROUTE_HC11 EQU 0x400f330b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC12 +CYREG_UDB_P1_ROUTE_HC12 EQU 0x400f330c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC13 +CYREG_UDB_P1_ROUTE_HC13 EQU 0x400f330d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC14 +CYREG_UDB_P1_ROUTE_HC14 EQU 0x400f330e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC15 +CYREG_UDB_P1_ROUTE_HC15 EQU 0x400f330f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC16 +CYREG_UDB_P1_ROUTE_HC16 EQU 0x400f3310 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC17 +CYREG_UDB_P1_ROUTE_HC17 EQU 0x400f3311 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC18 +CYREG_UDB_P1_ROUTE_HC18 EQU 0x400f3312 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC19 +CYREG_UDB_P1_ROUTE_HC19 EQU 0x400f3313 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC20 +CYREG_UDB_P1_ROUTE_HC20 EQU 0x400f3314 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC21 +CYREG_UDB_P1_ROUTE_HC21 EQU 0x400f3315 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC22 +CYREG_UDB_P1_ROUTE_HC22 EQU 0x400f3316 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC23 +CYREG_UDB_P1_ROUTE_HC23 EQU 0x400f3317 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC24 +CYREG_UDB_P1_ROUTE_HC24 EQU 0x400f3318 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC25 +CYREG_UDB_P1_ROUTE_HC25 EQU 0x400f3319 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC26 +CYREG_UDB_P1_ROUTE_HC26 EQU 0x400f331a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC27 +CYREG_UDB_P1_ROUTE_HC27 EQU 0x400f331b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC28 +CYREG_UDB_P1_ROUTE_HC28 EQU 0x400f331c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC29 +CYREG_UDB_P1_ROUTE_HC29 EQU 0x400f331d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC30 +CYREG_UDB_P1_ROUTE_HC30 EQU 0x400f331e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC31 +CYREG_UDB_P1_ROUTE_HC31 EQU 0x400f331f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC32 +CYREG_UDB_P1_ROUTE_HC32 EQU 0x400f3320 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC33 +CYREG_UDB_P1_ROUTE_HC33 EQU 0x400f3321 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC34 +CYREG_UDB_P1_ROUTE_HC34 EQU 0x400f3322 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC35 +CYREG_UDB_P1_ROUTE_HC35 EQU 0x400f3323 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC36 +CYREG_UDB_P1_ROUTE_HC36 EQU 0x400f3324 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC37 +CYREG_UDB_P1_ROUTE_HC37 EQU 0x400f3325 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC38 +CYREG_UDB_P1_ROUTE_HC38 EQU 0x400f3326 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC39 +CYREG_UDB_P1_ROUTE_HC39 EQU 0x400f3327 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC40 +CYREG_UDB_P1_ROUTE_HC40 EQU 0x400f3328 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC41 +CYREG_UDB_P1_ROUTE_HC41 EQU 0x400f3329 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC42 +CYREG_UDB_P1_ROUTE_HC42 EQU 0x400f332a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC43 +CYREG_UDB_P1_ROUTE_HC43 EQU 0x400f332b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC44 +CYREG_UDB_P1_ROUTE_HC44 EQU 0x400f332c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC45 +CYREG_UDB_P1_ROUTE_HC45 EQU 0x400f332d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC46 +CYREG_UDB_P1_ROUTE_HC46 EQU 0x400f332e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC47 +CYREG_UDB_P1_ROUTE_HC47 EQU 0x400f332f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC48 +CYREG_UDB_P1_ROUTE_HC48 EQU 0x400f3330 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC49 +CYREG_UDB_P1_ROUTE_HC49 EQU 0x400f3331 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC50 +CYREG_UDB_P1_ROUTE_HC50 EQU 0x400f3332 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC51 +CYREG_UDB_P1_ROUTE_HC51 EQU 0x400f3333 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC52 +CYREG_UDB_P1_ROUTE_HC52 EQU 0x400f3334 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC53 +CYREG_UDB_P1_ROUTE_HC53 EQU 0x400f3335 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC54 +CYREG_UDB_P1_ROUTE_HC54 EQU 0x400f3336 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC55 +CYREG_UDB_P1_ROUTE_HC55 EQU 0x400f3337 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC56 +CYREG_UDB_P1_ROUTE_HC56 EQU 0x400f3338 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC57 +CYREG_UDB_P1_ROUTE_HC57 EQU 0x400f3339 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC58 +CYREG_UDB_P1_ROUTE_HC58 EQU 0x400f333a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC59 +CYREG_UDB_P1_ROUTE_HC59 EQU 0x400f333b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC60 +CYREG_UDB_P1_ROUTE_HC60 EQU 0x400f333c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC61 +CYREG_UDB_P1_ROUTE_HC61 EQU 0x400f333d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC62 +CYREG_UDB_P1_ROUTE_HC62 EQU 0x400f333e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC63 +CYREG_UDB_P1_ROUTE_HC63 EQU 0x400f333f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC64 +CYREG_UDB_P1_ROUTE_HC64 EQU 0x400f3340 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC65 +CYREG_UDB_P1_ROUTE_HC65 EQU 0x400f3341 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC66 +CYREG_UDB_P1_ROUTE_HC66 EQU 0x400f3342 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC67 +CYREG_UDB_P1_ROUTE_HC67 EQU 0x400f3343 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC68 +CYREG_UDB_P1_ROUTE_HC68 EQU 0x400f3344 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC69 +CYREG_UDB_P1_ROUTE_HC69 EQU 0x400f3345 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC70 +CYREG_UDB_P1_ROUTE_HC70 EQU 0x400f3346 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC71 +CYREG_UDB_P1_ROUTE_HC71 EQU 0x400f3347 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC72 +CYREG_UDB_P1_ROUTE_HC72 EQU 0x400f3348 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC73 +CYREG_UDB_P1_ROUTE_HC73 EQU 0x400f3349 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC74 +CYREG_UDB_P1_ROUTE_HC74 EQU 0x400f334a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC75 +CYREG_UDB_P1_ROUTE_HC75 EQU 0x400f334b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC76 +CYREG_UDB_P1_ROUTE_HC76 EQU 0x400f334c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC77 +CYREG_UDB_P1_ROUTE_HC77 EQU 0x400f334d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC78 +CYREG_UDB_P1_ROUTE_HC78 EQU 0x400f334e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC79 +CYREG_UDB_P1_ROUTE_HC79 EQU 0x400f334f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC80 +CYREG_UDB_P1_ROUTE_HC80 EQU 0x400f3350 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC81 +CYREG_UDB_P1_ROUTE_HC81 EQU 0x400f3351 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC82 +CYREG_UDB_P1_ROUTE_HC82 EQU 0x400f3352 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC83 +CYREG_UDB_P1_ROUTE_HC83 EQU 0x400f3353 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC84 +CYREG_UDB_P1_ROUTE_HC84 EQU 0x400f3354 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC85 +CYREG_UDB_P1_ROUTE_HC85 EQU 0x400f3355 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC86 +CYREG_UDB_P1_ROUTE_HC86 EQU 0x400f3356 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC87 +CYREG_UDB_P1_ROUTE_HC87 EQU 0x400f3357 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC88 +CYREG_UDB_P1_ROUTE_HC88 EQU 0x400f3358 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC89 +CYREG_UDB_P1_ROUTE_HC89 EQU 0x400f3359 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC90 +CYREG_UDB_P1_ROUTE_HC90 EQU 0x400f335a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC91 +CYREG_UDB_P1_ROUTE_HC91 EQU 0x400f335b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC92 +CYREG_UDB_P1_ROUTE_HC92 EQU 0x400f335c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC93 +CYREG_UDB_P1_ROUTE_HC93 EQU 0x400f335d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC94 +CYREG_UDB_P1_ROUTE_HC94 EQU 0x400f335e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC95 +CYREG_UDB_P1_ROUTE_HC95 EQU 0x400f335f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC96 +CYREG_UDB_P1_ROUTE_HC96 EQU 0x400f3360 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC97 +CYREG_UDB_P1_ROUTE_HC97 EQU 0x400f3361 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC98 +CYREG_UDB_P1_ROUTE_HC98 EQU 0x400f3362 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC99 +CYREG_UDB_P1_ROUTE_HC99 EQU 0x400f3363 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC100 +CYREG_UDB_P1_ROUTE_HC100 EQU 0x400f3364 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC101 +CYREG_UDB_P1_ROUTE_HC101 EQU 0x400f3365 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC102 +CYREG_UDB_P1_ROUTE_HC102 EQU 0x400f3366 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC103 +CYREG_UDB_P1_ROUTE_HC103 EQU 0x400f3367 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC104 +CYREG_UDB_P1_ROUTE_HC104 EQU 0x400f3368 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC105 +CYREG_UDB_P1_ROUTE_HC105 EQU 0x400f3369 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC106 +CYREG_UDB_P1_ROUTE_HC106 EQU 0x400f336a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC107 +CYREG_UDB_P1_ROUTE_HC107 EQU 0x400f336b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC108 +CYREG_UDB_P1_ROUTE_HC108 EQU 0x400f336c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC109 +CYREG_UDB_P1_ROUTE_HC109 EQU 0x400f336d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC110 +CYREG_UDB_P1_ROUTE_HC110 EQU 0x400f336e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC111 +CYREG_UDB_P1_ROUTE_HC111 EQU 0x400f336f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC112 +CYREG_UDB_P1_ROUTE_HC112 EQU 0x400f3370 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC113 +CYREG_UDB_P1_ROUTE_HC113 EQU 0x400f3371 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC114 +CYREG_UDB_P1_ROUTE_HC114 EQU 0x400f3372 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC115 +CYREG_UDB_P1_ROUTE_HC115 EQU 0x400f3373 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC116 +CYREG_UDB_P1_ROUTE_HC116 EQU 0x400f3374 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC117 +CYREG_UDB_P1_ROUTE_HC117 EQU 0x400f3375 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC118 +CYREG_UDB_P1_ROUTE_HC118 EQU 0x400f3376 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC119 +CYREG_UDB_P1_ROUTE_HC119 EQU 0x400f3377 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC120 +CYREG_UDB_P1_ROUTE_HC120 EQU 0x400f3378 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC121 +CYREG_UDB_P1_ROUTE_HC121 EQU 0x400f3379 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC122 +CYREG_UDB_P1_ROUTE_HC122 EQU 0x400f337a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC123 +CYREG_UDB_P1_ROUTE_HC123 EQU 0x400f337b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC124 +CYREG_UDB_P1_ROUTE_HC124 EQU 0x400f337c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC125 +CYREG_UDB_P1_ROUTE_HC125 EQU 0x400f337d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC126 +CYREG_UDB_P1_ROUTE_HC126 EQU 0x400f337e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC127 +CYREG_UDB_P1_ROUTE_HC127 EQU 0x400f337f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L0 +CYREG_UDB_P1_ROUTE_HV_L0 EQU 0x400f3380 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L1 +CYREG_UDB_P1_ROUTE_HV_L1 EQU 0x400f3381 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L2 +CYREG_UDB_P1_ROUTE_HV_L2 EQU 0x400f3382 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L3 +CYREG_UDB_P1_ROUTE_HV_L3 EQU 0x400f3383 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L4 +CYREG_UDB_P1_ROUTE_HV_L4 EQU 0x400f3384 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L5 +CYREG_UDB_P1_ROUTE_HV_L5 EQU 0x400f3385 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L6 +CYREG_UDB_P1_ROUTE_HV_L6 EQU 0x400f3386 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L7 +CYREG_UDB_P1_ROUTE_HV_L7 EQU 0x400f3387 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L8 +CYREG_UDB_P1_ROUTE_HV_L8 EQU 0x400f3388 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L9 +CYREG_UDB_P1_ROUTE_HV_L9 EQU 0x400f3389 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L10 +CYREG_UDB_P1_ROUTE_HV_L10 EQU 0x400f338a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L11 +CYREG_UDB_P1_ROUTE_HV_L11 EQU 0x400f338b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L12 +CYREG_UDB_P1_ROUTE_HV_L12 EQU 0x400f338c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L13 +CYREG_UDB_P1_ROUTE_HV_L13 EQU 0x400f338d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L14 +CYREG_UDB_P1_ROUTE_HV_L14 EQU 0x400f338e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L15 +CYREG_UDB_P1_ROUTE_HV_L15 EQU 0x400f338f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS0 +CYREG_UDB_P1_ROUTE_HS0 EQU 0x400f3390 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS1 +CYREG_UDB_P1_ROUTE_HS1 EQU 0x400f3391 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS2 +CYREG_UDB_P1_ROUTE_HS2 EQU 0x400f3392 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS3 +CYREG_UDB_P1_ROUTE_HS3 EQU 0x400f3393 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS4 +CYREG_UDB_P1_ROUTE_HS4 EQU 0x400f3394 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS5 +CYREG_UDB_P1_ROUTE_HS5 EQU 0x400f3395 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS6 +CYREG_UDB_P1_ROUTE_HS6 EQU 0x400f3396 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS7 +CYREG_UDB_P1_ROUTE_HS7 EQU 0x400f3397 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS8 +CYREG_UDB_P1_ROUTE_HS8 EQU 0x400f3398 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS9 +CYREG_UDB_P1_ROUTE_HS9 EQU 0x400f3399 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS10 +CYREG_UDB_P1_ROUTE_HS10 EQU 0x400f339a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS11 +CYREG_UDB_P1_ROUTE_HS11 EQU 0x400f339b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS12 +CYREG_UDB_P1_ROUTE_HS12 EQU 0x400f339c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS13 +CYREG_UDB_P1_ROUTE_HS13 EQU 0x400f339d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS14 +CYREG_UDB_P1_ROUTE_HS14 EQU 0x400f339e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS15 +CYREG_UDB_P1_ROUTE_HS15 EQU 0x400f339f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS16 +CYREG_UDB_P1_ROUTE_HS16 EQU 0x400f33a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS17 +CYREG_UDB_P1_ROUTE_HS17 EQU 0x400f33a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS18 +CYREG_UDB_P1_ROUTE_HS18 EQU 0x400f33a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS19 +CYREG_UDB_P1_ROUTE_HS19 EQU 0x400f33a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS20 +CYREG_UDB_P1_ROUTE_HS20 EQU 0x400f33a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS21 +CYREG_UDB_P1_ROUTE_HS21 EQU 0x400f33a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS22 +CYREG_UDB_P1_ROUTE_HS22 EQU 0x400f33a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS23 +CYREG_UDB_P1_ROUTE_HS23 EQU 0x400f33a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R0 +CYREG_UDB_P1_ROUTE_HV_R0 EQU 0x400f33a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R1 +CYREG_UDB_P1_ROUTE_HV_R1 EQU 0x400f33a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R2 +CYREG_UDB_P1_ROUTE_HV_R2 EQU 0x400f33aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R3 +CYREG_UDB_P1_ROUTE_HV_R3 EQU 0x400f33ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R4 +CYREG_UDB_P1_ROUTE_HV_R4 EQU 0x400f33ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R5 +CYREG_UDB_P1_ROUTE_HV_R5 EQU 0x400f33ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R6 +CYREG_UDB_P1_ROUTE_HV_R6 EQU 0x400f33ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R7 +CYREG_UDB_P1_ROUTE_HV_R7 EQU 0x400f33af + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R8 +CYREG_UDB_P1_ROUTE_HV_R8 EQU 0x400f33b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R9 +CYREG_UDB_P1_ROUTE_HV_R9 EQU 0x400f33b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R10 +CYREG_UDB_P1_ROUTE_HV_R10 EQU 0x400f33b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R11 +CYREG_UDB_P1_ROUTE_HV_R11 EQU 0x400f33b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R12 +CYREG_UDB_P1_ROUTE_HV_R12 EQU 0x400f33b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R13 +CYREG_UDB_P1_ROUTE_HV_R13 EQU 0x400f33b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R14 +CYREG_UDB_P1_ROUTE_HV_R14 EQU 0x400f33b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R15 +CYREG_UDB_P1_ROUTE_HV_R15 EQU 0x400f33b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD0IN0 +CYREG_UDB_P1_ROUTE_PLD0IN0 EQU 0x400f33c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD0IN1 +CYREG_UDB_P1_ROUTE_PLD0IN1 EQU 0x400f33c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD0IN2 +CYREG_UDB_P1_ROUTE_PLD0IN2 EQU 0x400f33c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD1IN0 +CYREG_UDB_P1_ROUTE_PLD1IN0 EQU 0x400f33ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD1IN1 +CYREG_UDB_P1_ROUTE_PLD1IN1 EQU 0x400f33cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD1IN2 +CYREG_UDB_P1_ROUTE_PLD1IN2 EQU 0x400f33ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_DPIN0 +CYREG_UDB_P1_ROUTE_DPIN0 EQU 0x400f33d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_DPIN1 +CYREG_UDB_P1_ROUTE_DPIN1 EQU 0x400f33d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_SCIN +CYREG_UDB_P1_ROUTE_SCIN EQU 0x400f33d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_SCIOIN +CYREG_UDB_P1_ROUTE_SCIOIN EQU 0x400f33d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_RCIN +CYREG_UDB_P1_ROUTE_RCIN EQU 0x400f33de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS0 +CYREG_UDB_P1_ROUTE_VS0 EQU 0x400f33e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS1 +CYREG_UDB_P1_ROUTE_VS1 EQU 0x400f33e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS2 +CYREG_UDB_P1_ROUTE_VS2 EQU 0x400f33e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS3 +CYREG_UDB_P1_ROUTE_VS3 EQU 0x400f33e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS4 +CYREG_UDB_P1_ROUTE_VS4 EQU 0x400f33e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS5 +CYREG_UDB_P1_ROUTE_VS5 EQU 0x400f33ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS6 +CYREG_UDB_P1_ROUTE_VS6 EQU 0x400f33ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS7 +CYREG_UDB_P1_ROUTE_VS7 EQU 0x400f33ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI0_BASE +CYDEV_UDB_DSI0_BASE EQU 0x400f4000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI0_SIZE +CYDEV_UDB_DSI0_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC0 +CYREG_UDB_DSI0_HC0 EQU 0x400f4000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HC_BYTE__OFFSET +CYFLD_UDB_DSI_HC_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HC_BYTE__SIZE +CYFLD_UDB_DSI_HC_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC1 +CYREG_UDB_DSI0_HC1 EQU 0x400f4001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC2 +CYREG_UDB_DSI0_HC2 EQU 0x400f4002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC3 +CYREG_UDB_DSI0_HC3 EQU 0x400f4003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC4 +CYREG_UDB_DSI0_HC4 EQU 0x400f4004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC5 +CYREG_UDB_DSI0_HC5 EQU 0x400f4005 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC6 +CYREG_UDB_DSI0_HC6 EQU 0x400f4006 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC7 +CYREG_UDB_DSI0_HC7 EQU 0x400f4007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC8 +CYREG_UDB_DSI0_HC8 EQU 0x400f4008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC9 +CYREG_UDB_DSI0_HC9 EQU 0x400f4009 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC10 +CYREG_UDB_DSI0_HC10 EQU 0x400f400a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC11 +CYREG_UDB_DSI0_HC11 EQU 0x400f400b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC12 +CYREG_UDB_DSI0_HC12 EQU 0x400f400c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC13 +CYREG_UDB_DSI0_HC13 EQU 0x400f400d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC14 +CYREG_UDB_DSI0_HC14 EQU 0x400f400e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC15 +CYREG_UDB_DSI0_HC15 EQU 0x400f400f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC16 +CYREG_UDB_DSI0_HC16 EQU 0x400f4010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC17 +CYREG_UDB_DSI0_HC17 EQU 0x400f4011 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC18 +CYREG_UDB_DSI0_HC18 EQU 0x400f4012 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC19 +CYREG_UDB_DSI0_HC19 EQU 0x400f4013 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC20 +CYREG_UDB_DSI0_HC20 EQU 0x400f4014 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC21 +CYREG_UDB_DSI0_HC21 EQU 0x400f4015 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC22 +CYREG_UDB_DSI0_HC22 EQU 0x400f4016 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC23 +CYREG_UDB_DSI0_HC23 EQU 0x400f4017 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC24 +CYREG_UDB_DSI0_HC24 EQU 0x400f4018 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC25 +CYREG_UDB_DSI0_HC25 EQU 0x400f4019 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC26 +CYREG_UDB_DSI0_HC26 EQU 0x400f401a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC27 +CYREG_UDB_DSI0_HC27 EQU 0x400f401b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC28 +CYREG_UDB_DSI0_HC28 EQU 0x400f401c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC29 +CYREG_UDB_DSI0_HC29 EQU 0x400f401d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC30 +CYREG_UDB_DSI0_HC30 EQU 0x400f401e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC31 +CYREG_UDB_DSI0_HC31 EQU 0x400f401f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC32 +CYREG_UDB_DSI0_HC32 EQU 0x400f4020 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC33 +CYREG_UDB_DSI0_HC33 EQU 0x400f4021 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC34 +CYREG_UDB_DSI0_HC34 EQU 0x400f4022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC35 +CYREG_UDB_DSI0_HC35 EQU 0x400f4023 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC36 +CYREG_UDB_DSI0_HC36 EQU 0x400f4024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC37 +CYREG_UDB_DSI0_HC37 EQU 0x400f4025 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC38 +CYREG_UDB_DSI0_HC38 EQU 0x400f4026 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC39 +CYREG_UDB_DSI0_HC39 EQU 0x400f4027 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC40 +CYREG_UDB_DSI0_HC40 EQU 0x400f4028 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC41 +CYREG_UDB_DSI0_HC41 EQU 0x400f4029 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC42 +CYREG_UDB_DSI0_HC42 EQU 0x400f402a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC43 +CYREG_UDB_DSI0_HC43 EQU 0x400f402b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC44 +CYREG_UDB_DSI0_HC44 EQU 0x400f402c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC45 +CYREG_UDB_DSI0_HC45 EQU 0x400f402d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC46 +CYREG_UDB_DSI0_HC46 EQU 0x400f402e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC47 +CYREG_UDB_DSI0_HC47 EQU 0x400f402f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC48 +CYREG_UDB_DSI0_HC48 EQU 0x400f4030 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC49 +CYREG_UDB_DSI0_HC49 EQU 0x400f4031 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC50 +CYREG_UDB_DSI0_HC50 EQU 0x400f4032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC51 +CYREG_UDB_DSI0_HC51 EQU 0x400f4033 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC52 +CYREG_UDB_DSI0_HC52 EQU 0x400f4034 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC53 +CYREG_UDB_DSI0_HC53 EQU 0x400f4035 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC54 +CYREG_UDB_DSI0_HC54 EQU 0x400f4036 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC55 +CYREG_UDB_DSI0_HC55 EQU 0x400f4037 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC56 +CYREG_UDB_DSI0_HC56 EQU 0x400f4038 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC57 +CYREG_UDB_DSI0_HC57 EQU 0x400f4039 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC58 +CYREG_UDB_DSI0_HC58 EQU 0x400f403a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC59 +CYREG_UDB_DSI0_HC59 EQU 0x400f403b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC60 +CYREG_UDB_DSI0_HC60 EQU 0x400f403c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC61 +CYREG_UDB_DSI0_HC61 EQU 0x400f403d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC62 +CYREG_UDB_DSI0_HC62 EQU 0x400f403e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC63 +CYREG_UDB_DSI0_HC63 EQU 0x400f403f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC64 +CYREG_UDB_DSI0_HC64 EQU 0x400f4040 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC65 +CYREG_UDB_DSI0_HC65 EQU 0x400f4041 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC66 +CYREG_UDB_DSI0_HC66 EQU 0x400f4042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC67 +CYREG_UDB_DSI0_HC67 EQU 0x400f4043 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC68 +CYREG_UDB_DSI0_HC68 EQU 0x400f4044 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC69 +CYREG_UDB_DSI0_HC69 EQU 0x400f4045 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC70 +CYREG_UDB_DSI0_HC70 EQU 0x400f4046 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC71 +CYREG_UDB_DSI0_HC71 EQU 0x400f4047 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC72 +CYREG_UDB_DSI0_HC72 EQU 0x400f4048 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC73 +CYREG_UDB_DSI0_HC73 EQU 0x400f4049 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC74 +CYREG_UDB_DSI0_HC74 EQU 0x400f404a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC75 +CYREG_UDB_DSI0_HC75 EQU 0x400f404b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC76 +CYREG_UDB_DSI0_HC76 EQU 0x400f404c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC77 +CYREG_UDB_DSI0_HC77 EQU 0x400f404d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC78 +CYREG_UDB_DSI0_HC78 EQU 0x400f404e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC79 +CYREG_UDB_DSI0_HC79 EQU 0x400f404f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC80 +CYREG_UDB_DSI0_HC80 EQU 0x400f4050 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC81 +CYREG_UDB_DSI0_HC81 EQU 0x400f4051 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC82 +CYREG_UDB_DSI0_HC82 EQU 0x400f4052 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC83 +CYREG_UDB_DSI0_HC83 EQU 0x400f4053 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC84 +CYREG_UDB_DSI0_HC84 EQU 0x400f4054 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC85 +CYREG_UDB_DSI0_HC85 EQU 0x400f4055 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC86 +CYREG_UDB_DSI0_HC86 EQU 0x400f4056 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC87 +CYREG_UDB_DSI0_HC87 EQU 0x400f4057 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC88 +CYREG_UDB_DSI0_HC88 EQU 0x400f4058 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC89 +CYREG_UDB_DSI0_HC89 EQU 0x400f4059 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC90 +CYREG_UDB_DSI0_HC90 EQU 0x400f405a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC91 +CYREG_UDB_DSI0_HC91 EQU 0x400f405b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC92 +CYREG_UDB_DSI0_HC92 EQU 0x400f405c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC93 +CYREG_UDB_DSI0_HC93 EQU 0x400f405d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC94 +CYREG_UDB_DSI0_HC94 EQU 0x400f405e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC95 +CYREG_UDB_DSI0_HC95 EQU 0x400f405f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC96 +CYREG_UDB_DSI0_HC96 EQU 0x400f4060 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC97 +CYREG_UDB_DSI0_HC97 EQU 0x400f4061 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC98 +CYREG_UDB_DSI0_HC98 EQU 0x400f4062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC99 +CYREG_UDB_DSI0_HC99 EQU 0x400f4063 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC100 +CYREG_UDB_DSI0_HC100 EQU 0x400f4064 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC101 +CYREG_UDB_DSI0_HC101 EQU 0x400f4065 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC102 +CYREG_UDB_DSI0_HC102 EQU 0x400f4066 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC103 +CYREG_UDB_DSI0_HC103 EQU 0x400f4067 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC104 +CYREG_UDB_DSI0_HC104 EQU 0x400f4068 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC105 +CYREG_UDB_DSI0_HC105 EQU 0x400f4069 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC106 +CYREG_UDB_DSI0_HC106 EQU 0x400f406a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC107 +CYREG_UDB_DSI0_HC107 EQU 0x400f406b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC108 +CYREG_UDB_DSI0_HC108 EQU 0x400f406c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC109 +CYREG_UDB_DSI0_HC109 EQU 0x400f406d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC110 +CYREG_UDB_DSI0_HC110 EQU 0x400f406e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC111 +CYREG_UDB_DSI0_HC111 EQU 0x400f406f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC112 +CYREG_UDB_DSI0_HC112 EQU 0x400f4070 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC113 +CYREG_UDB_DSI0_HC113 EQU 0x400f4071 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC114 +CYREG_UDB_DSI0_HC114 EQU 0x400f4072 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC115 +CYREG_UDB_DSI0_HC115 EQU 0x400f4073 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC116 +CYREG_UDB_DSI0_HC116 EQU 0x400f4074 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC117 +CYREG_UDB_DSI0_HC117 EQU 0x400f4075 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC118 +CYREG_UDB_DSI0_HC118 EQU 0x400f4076 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC119 +CYREG_UDB_DSI0_HC119 EQU 0x400f4077 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC120 +CYREG_UDB_DSI0_HC120 EQU 0x400f4078 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC121 +CYREG_UDB_DSI0_HC121 EQU 0x400f4079 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC122 +CYREG_UDB_DSI0_HC122 EQU 0x400f407a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC123 +CYREG_UDB_DSI0_HC123 EQU 0x400f407b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC124 +CYREG_UDB_DSI0_HC124 EQU 0x400f407c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC125 +CYREG_UDB_DSI0_HC125 EQU 0x400f407d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC126 +CYREG_UDB_DSI0_HC126 EQU 0x400f407e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC127 +CYREG_UDB_DSI0_HC127 EQU 0x400f407f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L0 +CYREG_UDB_DSI0_HV_L0 EQU 0x400f4080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HV_BYTE__OFFSET +CYFLD_UDB_DSI_HV_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HV_BYTE__SIZE +CYFLD_UDB_DSI_HV_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L1 +CYREG_UDB_DSI0_HV_L1 EQU 0x400f4081 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L2 +CYREG_UDB_DSI0_HV_L2 EQU 0x400f4082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L3 +CYREG_UDB_DSI0_HV_L3 EQU 0x400f4083 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L4 +CYREG_UDB_DSI0_HV_L4 EQU 0x400f4084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L5 +CYREG_UDB_DSI0_HV_L5 EQU 0x400f4085 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L6 +CYREG_UDB_DSI0_HV_L6 EQU 0x400f4086 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L7 +CYREG_UDB_DSI0_HV_L7 EQU 0x400f4087 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L8 +CYREG_UDB_DSI0_HV_L8 EQU 0x400f4088 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L9 +CYREG_UDB_DSI0_HV_L9 EQU 0x400f4089 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L10 +CYREG_UDB_DSI0_HV_L10 EQU 0x400f408a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L11 +CYREG_UDB_DSI0_HV_L11 EQU 0x400f408b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L12 +CYREG_UDB_DSI0_HV_L12 EQU 0x400f408c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L13 +CYREG_UDB_DSI0_HV_L13 EQU 0x400f408d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L14 +CYREG_UDB_DSI0_HV_L14 EQU 0x400f408e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L15 +CYREG_UDB_DSI0_HV_L15 EQU 0x400f408f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS0 +CYREG_UDB_DSI0_HS0 EQU 0x400f4090 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HS_BYTE__OFFSET +CYFLD_UDB_DSI_HS_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HS_BYTE__SIZE +CYFLD_UDB_DSI_HS_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS1 +CYREG_UDB_DSI0_HS1 EQU 0x400f4091 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS2 +CYREG_UDB_DSI0_HS2 EQU 0x400f4092 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS3 +CYREG_UDB_DSI0_HS3 EQU 0x400f4093 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS4 +CYREG_UDB_DSI0_HS4 EQU 0x400f4094 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS5 +CYREG_UDB_DSI0_HS5 EQU 0x400f4095 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS6 +CYREG_UDB_DSI0_HS6 EQU 0x400f4096 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS7 +CYREG_UDB_DSI0_HS7 EQU 0x400f4097 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS8 +CYREG_UDB_DSI0_HS8 EQU 0x400f4098 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS9 +CYREG_UDB_DSI0_HS9 EQU 0x400f4099 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS10 +CYREG_UDB_DSI0_HS10 EQU 0x400f409a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS11 +CYREG_UDB_DSI0_HS11 EQU 0x400f409b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS12 +CYREG_UDB_DSI0_HS12 EQU 0x400f409c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS13 +CYREG_UDB_DSI0_HS13 EQU 0x400f409d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS14 +CYREG_UDB_DSI0_HS14 EQU 0x400f409e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS15 +CYREG_UDB_DSI0_HS15 EQU 0x400f409f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS16 +CYREG_UDB_DSI0_HS16 EQU 0x400f40a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS17 +CYREG_UDB_DSI0_HS17 EQU 0x400f40a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS18 +CYREG_UDB_DSI0_HS18 EQU 0x400f40a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS19 +CYREG_UDB_DSI0_HS19 EQU 0x400f40a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS20 +CYREG_UDB_DSI0_HS20 EQU 0x400f40a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS21 +CYREG_UDB_DSI0_HS21 EQU 0x400f40a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS22 +CYREG_UDB_DSI0_HS22 EQU 0x400f40a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS23 +CYREG_UDB_DSI0_HS23 EQU 0x400f40a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R0 +CYREG_UDB_DSI0_HV_R0 EQU 0x400f40a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R1 +CYREG_UDB_DSI0_HV_R1 EQU 0x400f40a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R2 +CYREG_UDB_DSI0_HV_R2 EQU 0x400f40aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R3 +CYREG_UDB_DSI0_HV_R3 EQU 0x400f40ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R4 +CYREG_UDB_DSI0_HV_R4 EQU 0x400f40ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R5 +CYREG_UDB_DSI0_HV_R5 EQU 0x400f40ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R6 +CYREG_UDB_DSI0_HV_R6 EQU 0x400f40ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R7 +CYREG_UDB_DSI0_HV_R7 EQU 0x400f40af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R8 +CYREG_UDB_DSI0_HV_R8 EQU 0x400f40b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R9 +CYREG_UDB_DSI0_HV_R9 EQU 0x400f40b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R10 +CYREG_UDB_DSI0_HV_R10 EQU 0x400f40b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R11 +CYREG_UDB_DSI0_HV_R11 EQU 0x400f40b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R12 +CYREG_UDB_DSI0_HV_R12 EQU 0x400f40b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R13 +CYREG_UDB_DSI0_HV_R13 EQU 0x400f40b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R14 +CYREG_UDB_DSI0_HV_R14 EQU 0x400f40b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R15 +CYREG_UDB_DSI0_HV_R15 EQU 0x400f40b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP0 +CYREG_UDB_DSI0_DSIINP0 EQU 0x400f40c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_TOP__OFFSET +CYFLD_UDB_DSI_PI_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_TOP__SIZE +CYFLD_UDB_DSI_PI_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_BOT__OFFSET +CYFLD_UDB_DSI_PI_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_BOT__SIZE +CYFLD_UDB_DSI_PI_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP1 +CYREG_UDB_DSI0_DSIINP1 EQU 0x400f40c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP2 +CYREG_UDB_DSI0_DSIINP2 EQU 0x400f40c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP3 +CYREG_UDB_DSI0_DSIINP3 EQU 0x400f40c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP4 +CYREG_UDB_DSI0_DSIINP4 EQU 0x400f40c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP5 +CYREG_UDB_DSI0_DSIINP5 EQU 0x400f40ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP0 +CYREG_UDB_DSI0_DSIOUTP0 EQU 0x400f40cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP1 +CYREG_UDB_DSI0_DSIOUTP1 EQU 0x400f40ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP2 +CYREG_UDB_DSI0_DSIOUTP2 EQU 0x400f40d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP3 +CYREG_UDB_DSI0_DSIOUTP3 EQU 0x400f40d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT0 +CYREG_UDB_DSI0_DSIOUTT0 EQU 0x400f40d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT1 +CYREG_UDB_DSI0_DSIOUTT1 EQU 0x400f40d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT2 +CYREG_UDB_DSI0_DSIOUTT2 EQU 0x400f40d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT3 +CYREG_UDB_DSI0_DSIOUTT3 EQU 0x400f40da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT4 +CYREG_UDB_DSI0_DSIOUTT4 EQU 0x400f40dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT5 +CYREG_UDB_DSI0_DSIOUTT5 EQU 0x400f40de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS0 +CYREG_UDB_DSI0_VS0 EQU 0x400f40e0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_TOP__OFFSET +CYFLD_UDB_DSI_VS_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_TOP__SIZE +CYFLD_UDB_DSI_VS_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_BOT__OFFSET +CYFLD_UDB_DSI_VS_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_BOT__SIZE +CYFLD_UDB_DSI_VS_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS1 +CYREG_UDB_DSI0_VS1 EQU 0x400f40e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS2 +CYREG_UDB_DSI0_VS2 EQU 0x400f40e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS3 +CYREG_UDB_DSI0_VS3 EQU 0x400f40e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS4 +CYREG_UDB_DSI0_VS4 EQU 0x400f40e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS5 +CYREG_UDB_DSI0_VS5 EQU 0x400f40ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS6 +CYREG_UDB_DSI0_VS6 EQU 0x400f40ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS7 +CYREG_UDB_DSI0_VS7 EQU 0x400f40ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI1_BASE +CYDEV_UDB_DSI1_BASE EQU 0x400f4100 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI1_SIZE +CYDEV_UDB_DSI1_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC0 +CYREG_UDB_DSI1_HC0 EQU 0x400f4100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC1 +CYREG_UDB_DSI1_HC1 EQU 0x400f4101 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC2 +CYREG_UDB_DSI1_HC2 EQU 0x400f4102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC3 +CYREG_UDB_DSI1_HC3 EQU 0x400f4103 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC4 +CYREG_UDB_DSI1_HC4 EQU 0x400f4104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC5 +CYREG_UDB_DSI1_HC5 EQU 0x400f4105 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC6 +CYREG_UDB_DSI1_HC6 EQU 0x400f4106 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC7 +CYREG_UDB_DSI1_HC7 EQU 0x400f4107 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC8 +CYREG_UDB_DSI1_HC8 EQU 0x400f4108 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC9 +CYREG_UDB_DSI1_HC9 EQU 0x400f4109 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC10 +CYREG_UDB_DSI1_HC10 EQU 0x400f410a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC11 +CYREG_UDB_DSI1_HC11 EQU 0x400f410b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC12 +CYREG_UDB_DSI1_HC12 EQU 0x400f410c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC13 +CYREG_UDB_DSI1_HC13 EQU 0x400f410d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC14 +CYREG_UDB_DSI1_HC14 EQU 0x400f410e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC15 +CYREG_UDB_DSI1_HC15 EQU 0x400f410f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC16 +CYREG_UDB_DSI1_HC16 EQU 0x400f4110 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC17 +CYREG_UDB_DSI1_HC17 EQU 0x400f4111 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC18 +CYREG_UDB_DSI1_HC18 EQU 0x400f4112 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC19 +CYREG_UDB_DSI1_HC19 EQU 0x400f4113 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC20 +CYREG_UDB_DSI1_HC20 EQU 0x400f4114 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC21 +CYREG_UDB_DSI1_HC21 EQU 0x400f4115 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC22 +CYREG_UDB_DSI1_HC22 EQU 0x400f4116 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC23 +CYREG_UDB_DSI1_HC23 EQU 0x400f4117 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC24 +CYREG_UDB_DSI1_HC24 EQU 0x400f4118 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC25 +CYREG_UDB_DSI1_HC25 EQU 0x400f4119 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC26 +CYREG_UDB_DSI1_HC26 EQU 0x400f411a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC27 +CYREG_UDB_DSI1_HC27 EQU 0x400f411b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC28 +CYREG_UDB_DSI1_HC28 EQU 0x400f411c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC29 +CYREG_UDB_DSI1_HC29 EQU 0x400f411d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC30 +CYREG_UDB_DSI1_HC30 EQU 0x400f411e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC31 +CYREG_UDB_DSI1_HC31 EQU 0x400f411f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC32 +CYREG_UDB_DSI1_HC32 EQU 0x400f4120 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC33 +CYREG_UDB_DSI1_HC33 EQU 0x400f4121 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC34 +CYREG_UDB_DSI1_HC34 EQU 0x400f4122 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC35 +CYREG_UDB_DSI1_HC35 EQU 0x400f4123 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC36 +CYREG_UDB_DSI1_HC36 EQU 0x400f4124 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC37 +CYREG_UDB_DSI1_HC37 EQU 0x400f4125 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC38 +CYREG_UDB_DSI1_HC38 EQU 0x400f4126 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC39 +CYREG_UDB_DSI1_HC39 EQU 0x400f4127 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC40 +CYREG_UDB_DSI1_HC40 EQU 0x400f4128 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC41 +CYREG_UDB_DSI1_HC41 EQU 0x400f4129 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC42 +CYREG_UDB_DSI1_HC42 EQU 0x400f412a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC43 +CYREG_UDB_DSI1_HC43 EQU 0x400f412b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC44 +CYREG_UDB_DSI1_HC44 EQU 0x400f412c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC45 +CYREG_UDB_DSI1_HC45 EQU 0x400f412d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC46 +CYREG_UDB_DSI1_HC46 EQU 0x400f412e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC47 +CYREG_UDB_DSI1_HC47 EQU 0x400f412f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC48 +CYREG_UDB_DSI1_HC48 EQU 0x400f4130 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC49 +CYREG_UDB_DSI1_HC49 EQU 0x400f4131 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC50 +CYREG_UDB_DSI1_HC50 EQU 0x400f4132 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC51 +CYREG_UDB_DSI1_HC51 EQU 0x400f4133 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC52 +CYREG_UDB_DSI1_HC52 EQU 0x400f4134 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC53 +CYREG_UDB_DSI1_HC53 EQU 0x400f4135 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC54 +CYREG_UDB_DSI1_HC54 EQU 0x400f4136 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC55 +CYREG_UDB_DSI1_HC55 EQU 0x400f4137 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC56 +CYREG_UDB_DSI1_HC56 EQU 0x400f4138 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC57 +CYREG_UDB_DSI1_HC57 EQU 0x400f4139 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC58 +CYREG_UDB_DSI1_HC58 EQU 0x400f413a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC59 +CYREG_UDB_DSI1_HC59 EQU 0x400f413b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC60 +CYREG_UDB_DSI1_HC60 EQU 0x400f413c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC61 +CYREG_UDB_DSI1_HC61 EQU 0x400f413d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC62 +CYREG_UDB_DSI1_HC62 EQU 0x400f413e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC63 +CYREG_UDB_DSI1_HC63 EQU 0x400f413f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC64 +CYREG_UDB_DSI1_HC64 EQU 0x400f4140 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC65 +CYREG_UDB_DSI1_HC65 EQU 0x400f4141 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC66 +CYREG_UDB_DSI1_HC66 EQU 0x400f4142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC67 +CYREG_UDB_DSI1_HC67 EQU 0x400f4143 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC68 +CYREG_UDB_DSI1_HC68 EQU 0x400f4144 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC69 +CYREG_UDB_DSI1_HC69 EQU 0x400f4145 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC70 +CYREG_UDB_DSI1_HC70 EQU 0x400f4146 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC71 +CYREG_UDB_DSI1_HC71 EQU 0x400f4147 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC72 +CYREG_UDB_DSI1_HC72 EQU 0x400f4148 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC73 +CYREG_UDB_DSI1_HC73 EQU 0x400f4149 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC74 +CYREG_UDB_DSI1_HC74 EQU 0x400f414a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC75 +CYREG_UDB_DSI1_HC75 EQU 0x400f414b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC76 +CYREG_UDB_DSI1_HC76 EQU 0x400f414c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC77 +CYREG_UDB_DSI1_HC77 EQU 0x400f414d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC78 +CYREG_UDB_DSI1_HC78 EQU 0x400f414e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC79 +CYREG_UDB_DSI1_HC79 EQU 0x400f414f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC80 +CYREG_UDB_DSI1_HC80 EQU 0x400f4150 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC81 +CYREG_UDB_DSI1_HC81 EQU 0x400f4151 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC82 +CYREG_UDB_DSI1_HC82 EQU 0x400f4152 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC83 +CYREG_UDB_DSI1_HC83 EQU 0x400f4153 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC84 +CYREG_UDB_DSI1_HC84 EQU 0x400f4154 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC85 +CYREG_UDB_DSI1_HC85 EQU 0x400f4155 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC86 +CYREG_UDB_DSI1_HC86 EQU 0x400f4156 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC87 +CYREG_UDB_DSI1_HC87 EQU 0x400f4157 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC88 +CYREG_UDB_DSI1_HC88 EQU 0x400f4158 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC89 +CYREG_UDB_DSI1_HC89 EQU 0x400f4159 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC90 +CYREG_UDB_DSI1_HC90 EQU 0x400f415a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC91 +CYREG_UDB_DSI1_HC91 EQU 0x400f415b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC92 +CYREG_UDB_DSI1_HC92 EQU 0x400f415c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC93 +CYREG_UDB_DSI1_HC93 EQU 0x400f415d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC94 +CYREG_UDB_DSI1_HC94 EQU 0x400f415e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC95 +CYREG_UDB_DSI1_HC95 EQU 0x400f415f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC96 +CYREG_UDB_DSI1_HC96 EQU 0x400f4160 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC97 +CYREG_UDB_DSI1_HC97 EQU 0x400f4161 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC98 +CYREG_UDB_DSI1_HC98 EQU 0x400f4162 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC99 +CYREG_UDB_DSI1_HC99 EQU 0x400f4163 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC100 +CYREG_UDB_DSI1_HC100 EQU 0x400f4164 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC101 +CYREG_UDB_DSI1_HC101 EQU 0x400f4165 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC102 +CYREG_UDB_DSI1_HC102 EQU 0x400f4166 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC103 +CYREG_UDB_DSI1_HC103 EQU 0x400f4167 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC104 +CYREG_UDB_DSI1_HC104 EQU 0x400f4168 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC105 +CYREG_UDB_DSI1_HC105 EQU 0x400f4169 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC106 +CYREG_UDB_DSI1_HC106 EQU 0x400f416a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC107 +CYREG_UDB_DSI1_HC107 EQU 0x400f416b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC108 +CYREG_UDB_DSI1_HC108 EQU 0x400f416c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC109 +CYREG_UDB_DSI1_HC109 EQU 0x400f416d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC110 +CYREG_UDB_DSI1_HC110 EQU 0x400f416e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC111 +CYREG_UDB_DSI1_HC111 EQU 0x400f416f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC112 +CYREG_UDB_DSI1_HC112 EQU 0x400f4170 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC113 +CYREG_UDB_DSI1_HC113 EQU 0x400f4171 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC114 +CYREG_UDB_DSI1_HC114 EQU 0x400f4172 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC115 +CYREG_UDB_DSI1_HC115 EQU 0x400f4173 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC116 +CYREG_UDB_DSI1_HC116 EQU 0x400f4174 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC117 +CYREG_UDB_DSI1_HC117 EQU 0x400f4175 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC118 +CYREG_UDB_DSI1_HC118 EQU 0x400f4176 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC119 +CYREG_UDB_DSI1_HC119 EQU 0x400f4177 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC120 +CYREG_UDB_DSI1_HC120 EQU 0x400f4178 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC121 +CYREG_UDB_DSI1_HC121 EQU 0x400f4179 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC122 +CYREG_UDB_DSI1_HC122 EQU 0x400f417a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC123 +CYREG_UDB_DSI1_HC123 EQU 0x400f417b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC124 +CYREG_UDB_DSI1_HC124 EQU 0x400f417c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC125 +CYREG_UDB_DSI1_HC125 EQU 0x400f417d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC126 +CYREG_UDB_DSI1_HC126 EQU 0x400f417e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC127 +CYREG_UDB_DSI1_HC127 EQU 0x400f417f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L0 +CYREG_UDB_DSI1_HV_L0 EQU 0x400f4180 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L1 +CYREG_UDB_DSI1_HV_L1 EQU 0x400f4181 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L2 +CYREG_UDB_DSI1_HV_L2 EQU 0x400f4182 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L3 +CYREG_UDB_DSI1_HV_L3 EQU 0x400f4183 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L4 +CYREG_UDB_DSI1_HV_L4 EQU 0x400f4184 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L5 +CYREG_UDB_DSI1_HV_L5 EQU 0x400f4185 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L6 +CYREG_UDB_DSI1_HV_L6 EQU 0x400f4186 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L7 +CYREG_UDB_DSI1_HV_L7 EQU 0x400f4187 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L8 +CYREG_UDB_DSI1_HV_L8 EQU 0x400f4188 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L9 +CYREG_UDB_DSI1_HV_L9 EQU 0x400f4189 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L10 +CYREG_UDB_DSI1_HV_L10 EQU 0x400f418a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L11 +CYREG_UDB_DSI1_HV_L11 EQU 0x400f418b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L12 +CYREG_UDB_DSI1_HV_L12 EQU 0x400f418c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L13 +CYREG_UDB_DSI1_HV_L13 EQU 0x400f418d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L14 +CYREG_UDB_DSI1_HV_L14 EQU 0x400f418e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L15 +CYREG_UDB_DSI1_HV_L15 EQU 0x400f418f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS0 +CYREG_UDB_DSI1_HS0 EQU 0x400f4190 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS1 +CYREG_UDB_DSI1_HS1 EQU 0x400f4191 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS2 +CYREG_UDB_DSI1_HS2 EQU 0x400f4192 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS3 +CYREG_UDB_DSI1_HS3 EQU 0x400f4193 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS4 +CYREG_UDB_DSI1_HS4 EQU 0x400f4194 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS5 +CYREG_UDB_DSI1_HS5 EQU 0x400f4195 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS6 +CYREG_UDB_DSI1_HS6 EQU 0x400f4196 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS7 +CYREG_UDB_DSI1_HS7 EQU 0x400f4197 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS8 +CYREG_UDB_DSI1_HS8 EQU 0x400f4198 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS9 +CYREG_UDB_DSI1_HS9 EQU 0x400f4199 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS10 +CYREG_UDB_DSI1_HS10 EQU 0x400f419a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS11 +CYREG_UDB_DSI1_HS11 EQU 0x400f419b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS12 +CYREG_UDB_DSI1_HS12 EQU 0x400f419c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS13 +CYREG_UDB_DSI1_HS13 EQU 0x400f419d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS14 +CYREG_UDB_DSI1_HS14 EQU 0x400f419e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS15 +CYREG_UDB_DSI1_HS15 EQU 0x400f419f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS16 +CYREG_UDB_DSI1_HS16 EQU 0x400f41a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS17 +CYREG_UDB_DSI1_HS17 EQU 0x400f41a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS18 +CYREG_UDB_DSI1_HS18 EQU 0x400f41a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS19 +CYREG_UDB_DSI1_HS19 EQU 0x400f41a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS20 +CYREG_UDB_DSI1_HS20 EQU 0x400f41a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS21 +CYREG_UDB_DSI1_HS21 EQU 0x400f41a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS22 +CYREG_UDB_DSI1_HS22 EQU 0x400f41a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS23 +CYREG_UDB_DSI1_HS23 EQU 0x400f41a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R0 +CYREG_UDB_DSI1_HV_R0 EQU 0x400f41a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R1 +CYREG_UDB_DSI1_HV_R1 EQU 0x400f41a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R2 +CYREG_UDB_DSI1_HV_R2 EQU 0x400f41aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R3 +CYREG_UDB_DSI1_HV_R3 EQU 0x400f41ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R4 +CYREG_UDB_DSI1_HV_R4 EQU 0x400f41ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R5 +CYREG_UDB_DSI1_HV_R5 EQU 0x400f41ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R6 +CYREG_UDB_DSI1_HV_R6 EQU 0x400f41ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R7 +CYREG_UDB_DSI1_HV_R7 EQU 0x400f41af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R8 +CYREG_UDB_DSI1_HV_R8 EQU 0x400f41b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R9 +CYREG_UDB_DSI1_HV_R9 EQU 0x400f41b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R10 +CYREG_UDB_DSI1_HV_R10 EQU 0x400f41b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R11 +CYREG_UDB_DSI1_HV_R11 EQU 0x400f41b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R12 +CYREG_UDB_DSI1_HV_R12 EQU 0x400f41b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R13 +CYREG_UDB_DSI1_HV_R13 EQU 0x400f41b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R14 +CYREG_UDB_DSI1_HV_R14 EQU 0x400f41b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R15 +CYREG_UDB_DSI1_HV_R15 EQU 0x400f41b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP0 +CYREG_UDB_DSI1_DSIINP0 EQU 0x400f41c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP1 +CYREG_UDB_DSI1_DSIINP1 EQU 0x400f41c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP2 +CYREG_UDB_DSI1_DSIINP2 EQU 0x400f41c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP3 +CYREG_UDB_DSI1_DSIINP3 EQU 0x400f41c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP4 +CYREG_UDB_DSI1_DSIINP4 EQU 0x400f41c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP5 +CYREG_UDB_DSI1_DSIINP5 EQU 0x400f41ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP0 +CYREG_UDB_DSI1_DSIOUTP0 EQU 0x400f41cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP1 +CYREG_UDB_DSI1_DSIOUTP1 EQU 0x400f41ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP2 +CYREG_UDB_DSI1_DSIOUTP2 EQU 0x400f41d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP3 +CYREG_UDB_DSI1_DSIOUTP3 EQU 0x400f41d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT0 +CYREG_UDB_DSI1_DSIOUTT0 EQU 0x400f41d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT1 +CYREG_UDB_DSI1_DSIOUTT1 EQU 0x400f41d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT2 +CYREG_UDB_DSI1_DSIOUTT2 EQU 0x400f41d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT3 +CYREG_UDB_DSI1_DSIOUTT3 EQU 0x400f41da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT4 +CYREG_UDB_DSI1_DSIOUTT4 EQU 0x400f41dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT5 +CYREG_UDB_DSI1_DSIOUTT5 EQU 0x400f41de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS0 +CYREG_UDB_DSI1_VS0 EQU 0x400f41e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS1 +CYREG_UDB_DSI1_VS1 EQU 0x400f41e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS2 +CYREG_UDB_DSI1_VS2 EQU 0x400f41e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS3 +CYREG_UDB_DSI1_VS3 EQU 0x400f41e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS4 +CYREG_UDB_DSI1_VS4 EQU 0x400f41e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS5 +CYREG_UDB_DSI1_VS5 EQU 0x400f41ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS6 +CYREG_UDB_DSI1_VS6 EQU 0x400f41ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS7 +CYREG_UDB_DSI1_VS7 EQU 0x400f41ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI2_BASE +CYDEV_UDB_DSI2_BASE EQU 0x400f4200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI2_SIZE +CYDEV_UDB_DSI2_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC0 +CYREG_UDB_DSI2_HC0 EQU 0x400f4200 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC1 +CYREG_UDB_DSI2_HC1 EQU 0x400f4201 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC2 +CYREG_UDB_DSI2_HC2 EQU 0x400f4202 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC3 +CYREG_UDB_DSI2_HC3 EQU 0x400f4203 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC4 +CYREG_UDB_DSI2_HC4 EQU 0x400f4204 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC5 +CYREG_UDB_DSI2_HC5 EQU 0x400f4205 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC6 +CYREG_UDB_DSI2_HC6 EQU 0x400f4206 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC7 +CYREG_UDB_DSI2_HC7 EQU 0x400f4207 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC8 +CYREG_UDB_DSI2_HC8 EQU 0x400f4208 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC9 +CYREG_UDB_DSI2_HC9 EQU 0x400f4209 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC10 +CYREG_UDB_DSI2_HC10 EQU 0x400f420a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC11 +CYREG_UDB_DSI2_HC11 EQU 0x400f420b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC12 +CYREG_UDB_DSI2_HC12 EQU 0x400f420c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC13 +CYREG_UDB_DSI2_HC13 EQU 0x400f420d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC14 +CYREG_UDB_DSI2_HC14 EQU 0x400f420e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC15 +CYREG_UDB_DSI2_HC15 EQU 0x400f420f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC16 +CYREG_UDB_DSI2_HC16 EQU 0x400f4210 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC17 +CYREG_UDB_DSI2_HC17 EQU 0x400f4211 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC18 +CYREG_UDB_DSI2_HC18 EQU 0x400f4212 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC19 +CYREG_UDB_DSI2_HC19 EQU 0x400f4213 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC20 +CYREG_UDB_DSI2_HC20 EQU 0x400f4214 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC21 +CYREG_UDB_DSI2_HC21 EQU 0x400f4215 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC22 +CYREG_UDB_DSI2_HC22 EQU 0x400f4216 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC23 +CYREG_UDB_DSI2_HC23 EQU 0x400f4217 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC24 +CYREG_UDB_DSI2_HC24 EQU 0x400f4218 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC25 +CYREG_UDB_DSI2_HC25 EQU 0x400f4219 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC26 +CYREG_UDB_DSI2_HC26 EQU 0x400f421a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC27 +CYREG_UDB_DSI2_HC27 EQU 0x400f421b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC28 +CYREG_UDB_DSI2_HC28 EQU 0x400f421c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC29 +CYREG_UDB_DSI2_HC29 EQU 0x400f421d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC30 +CYREG_UDB_DSI2_HC30 EQU 0x400f421e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC31 +CYREG_UDB_DSI2_HC31 EQU 0x400f421f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC32 +CYREG_UDB_DSI2_HC32 EQU 0x400f4220 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC33 +CYREG_UDB_DSI2_HC33 EQU 0x400f4221 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC34 +CYREG_UDB_DSI2_HC34 EQU 0x400f4222 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC35 +CYREG_UDB_DSI2_HC35 EQU 0x400f4223 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC36 +CYREG_UDB_DSI2_HC36 EQU 0x400f4224 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC37 +CYREG_UDB_DSI2_HC37 EQU 0x400f4225 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC38 +CYREG_UDB_DSI2_HC38 EQU 0x400f4226 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC39 +CYREG_UDB_DSI2_HC39 EQU 0x400f4227 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC40 +CYREG_UDB_DSI2_HC40 EQU 0x400f4228 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC41 +CYREG_UDB_DSI2_HC41 EQU 0x400f4229 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC42 +CYREG_UDB_DSI2_HC42 EQU 0x400f422a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC43 +CYREG_UDB_DSI2_HC43 EQU 0x400f422b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC44 +CYREG_UDB_DSI2_HC44 EQU 0x400f422c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC45 +CYREG_UDB_DSI2_HC45 EQU 0x400f422d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC46 +CYREG_UDB_DSI2_HC46 EQU 0x400f422e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC47 +CYREG_UDB_DSI2_HC47 EQU 0x400f422f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC48 +CYREG_UDB_DSI2_HC48 EQU 0x400f4230 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC49 +CYREG_UDB_DSI2_HC49 EQU 0x400f4231 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC50 +CYREG_UDB_DSI2_HC50 EQU 0x400f4232 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC51 +CYREG_UDB_DSI2_HC51 EQU 0x400f4233 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC52 +CYREG_UDB_DSI2_HC52 EQU 0x400f4234 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC53 +CYREG_UDB_DSI2_HC53 EQU 0x400f4235 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC54 +CYREG_UDB_DSI2_HC54 EQU 0x400f4236 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC55 +CYREG_UDB_DSI2_HC55 EQU 0x400f4237 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC56 +CYREG_UDB_DSI2_HC56 EQU 0x400f4238 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC57 +CYREG_UDB_DSI2_HC57 EQU 0x400f4239 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC58 +CYREG_UDB_DSI2_HC58 EQU 0x400f423a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC59 +CYREG_UDB_DSI2_HC59 EQU 0x400f423b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC60 +CYREG_UDB_DSI2_HC60 EQU 0x400f423c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC61 +CYREG_UDB_DSI2_HC61 EQU 0x400f423d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC62 +CYREG_UDB_DSI2_HC62 EQU 0x400f423e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC63 +CYREG_UDB_DSI2_HC63 EQU 0x400f423f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC64 +CYREG_UDB_DSI2_HC64 EQU 0x400f4240 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC65 +CYREG_UDB_DSI2_HC65 EQU 0x400f4241 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC66 +CYREG_UDB_DSI2_HC66 EQU 0x400f4242 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC67 +CYREG_UDB_DSI2_HC67 EQU 0x400f4243 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC68 +CYREG_UDB_DSI2_HC68 EQU 0x400f4244 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC69 +CYREG_UDB_DSI2_HC69 EQU 0x400f4245 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC70 +CYREG_UDB_DSI2_HC70 EQU 0x400f4246 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC71 +CYREG_UDB_DSI2_HC71 EQU 0x400f4247 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC72 +CYREG_UDB_DSI2_HC72 EQU 0x400f4248 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC73 +CYREG_UDB_DSI2_HC73 EQU 0x400f4249 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC74 +CYREG_UDB_DSI2_HC74 EQU 0x400f424a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC75 +CYREG_UDB_DSI2_HC75 EQU 0x400f424b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC76 +CYREG_UDB_DSI2_HC76 EQU 0x400f424c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC77 +CYREG_UDB_DSI2_HC77 EQU 0x400f424d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC78 +CYREG_UDB_DSI2_HC78 EQU 0x400f424e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC79 +CYREG_UDB_DSI2_HC79 EQU 0x400f424f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC80 +CYREG_UDB_DSI2_HC80 EQU 0x400f4250 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC81 +CYREG_UDB_DSI2_HC81 EQU 0x400f4251 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC82 +CYREG_UDB_DSI2_HC82 EQU 0x400f4252 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC83 +CYREG_UDB_DSI2_HC83 EQU 0x400f4253 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC84 +CYREG_UDB_DSI2_HC84 EQU 0x400f4254 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC85 +CYREG_UDB_DSI2_HC85 EQU 0x400f4255 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC86 +CYREG_UDB_DSI2_HC86 EQU 0x400f4256 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC87 +CYREG_UDB_DSI2_HC87 EQU 0x400f4257 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC88 +CYREG_UDB_DSI2_HC88 EQU 0x400f4258 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC89 +CYREG_UDB_DSI2_HC89 EQU 0x400f4259 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC90 +CYREG_UDB_DSI2_HC90 EQU 0x400f425a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC91 +CYREG_UDB_DSI2_HC91 EQU 0x400f425b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC92 +CYREG_UDB_DSI2_HC92 EQU 0x400f425c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC93 +CYREG_UDB_DSI2_HC93 EQU 0x400f425d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC94 +CYREG_UDB_DSI2_HC94 EQU 0x400f425e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC95 +CYREG_UDB_DSI2_HC95 EQU 0x400f425f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC96 +CYREG_UDB_DSI2_HC96 EQU 0x400f4260 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC97 +CYREG_UDB_DSI2_HC97 EQU 0x400f4261 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC98 +CYREG_UDB_DSI2_HC98 EQU 0x400f4262 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC99 +CYREG_UDB_DSI2_HC99 EQU 0x400f4263 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC100 +CYREG_UDB_DSI2_HC100 EQU 0x400f4264 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC101 +CYREG_UDB_DSI2_HC101 EQU 0x400f4265 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC102 +CYREG_UDB_DSI2_HC102 EQU 0x400f4266 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC103 +CYREG_UDB_DSI2_HC103 EQU 0x400f4267 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC104 +CYREG_UDB_DSI2_HC104 EQU 0x400f4268 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC105 +CYREG_UDB_DSI2_HC105 EQU 0x400f4269 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC106 +CYREG_UDB_DSI2_HC106 EQU 0x400f426a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC107 +CYREG_UDB_DSI2_HC107 EQU 0x400f426b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC108 +CYREG_UDB_DSI2_HC108 EQU 0x400f426c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC109 +CYREG_UDB_DSI2_HC109 EQU 0x400f426d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC110 +CYREG_UDB_DSI2_HC110 EQU 0x400f426e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC111 +CYREG_UDB_DSI2_HC111 EQU 0x400f426f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC112 +CYREG_UDB_DSI2_HC112 EQU 0x400f4270 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC113 +CYREG_UDB_DSI2_HC113 EQU 0x400f4271 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC114 +CYREG_UDB_DSI2_HC114 EQU 0x400f4272 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC115 +CYREG_UDB_DSI2_HC115 EQU 0x400f4273 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC116 +CYREG_UDB_DSI2_HC116 EQU 0x400f4274 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC117 +CYREG_UDB_DSI2_HC117 EQU 0x400f4275 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC118 +CYREG_UDB_DSI2_HC118 EQU 0x400f4276 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC119 +CYREG_UDB_DSI2_HC119 EQU 0x400f4277 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC120 +CYREG_UDB_DSI2_HC120 EQU 0x400f4278 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC121 +CYREG_UDB_DSI2_HC121 EQU 0x400f4279 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC122 +CYREG_UDB_DSI2_HC122 EQU 0x400f427a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC123 +CYREG_UDB_DSI2_HC123 EQU 0x400f427b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC124 +CYREG_UDB_DSI2_HC124 EQU 0x400f427c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC125 +CYREG_UDB_DSI2_HC125 EQU 0x400f427d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC126 +CYREG_UDB_DSI2_HC126 EQU 0x400f427e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC127 +CYREG_UDB_DSI2_HC127 EQU 0x400f427f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L0 +CYREG_UDB_DSI2_HV_L0 EQU 0x400f4280 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L1 +CYREG_UDB_DSI2_HV_L1 EQU 0x400f4281 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L2 +CYREG_UDB_DSI2_HV_L2 EQU 0x400f4282 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L3 +CYREG_UDB_DSI2_HV_L3 EQU 0x400f4283 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L4 +CYREG_UDB_DSI2_HV_L4 EQU 0x400f4284 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L5 +CYREG_UDB_DSI2_HV_L5 EQU 0x400f4285 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L6 +CYREG_UDB_DSI2_HV_L6 EQU 0x400f4286 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L7 +CYREG_UDB_DSI2_HV_L7 EQU 0x400f4287 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L8 +CYREG_UDB_DSI2_HV_L8 EQU 0x400f4288 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L9 +CYREG_UDB_DSI2_HV_L9 EQU 0x400f4289 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L10 +CYREG_UDB_DSI2_HV_L10 EQU 0x400f428a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L11 +CYREG_UDB_DSI2_HV_L11 EQU 0x400f428b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L12 +CYREG_UDB_DSI2_HV_L12 EQU 0x400f428c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L13 +CYREG_UDB_DSI2_HV_L13 EQU 0x400f428d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L14 +CYREG_UDB_DSI2_HV_L14 EQU 0x400f428e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L15 +CYREG_UDB_DSI2_HV_L15 EQU 0x400f428f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS0 +CYREG_UDB_DSI2_HS0 EQU 0x400f4290 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS1 +CYREG_UDB_DSI2_HS1 EQU 0x400f4291 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS2 +CYREG_UDB_DSI2_HS2 EQU 0x400f4292 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS3 +CYREG_UDB_DSI2_HS3 EQU 0x400f4293 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS4 +CYREG_UDB_DSI2_HS4 EQU 0x400f4294 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS5 +CYREG_UDB_DSI2_HS5 EQU 0x400f4295 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS6 +CYREG_UDB_DSI2_HS6 EQU 0x400f4296 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS7 +CYREG_UDB_DSI2_HS7 EQU 0x400f4297 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS8 +CYREG_UDB_DSI2_HS8 EQU 0x400f4298 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS9 +CYREG_UDB_DSI2_HS9 EQU 0x400f4299 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS10 +CYREG_UDB_DSI2_HS10 EQU 0x400f429a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS11 +CYREG_UDB_DSI2_HS11 EQU 0x400f429b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS12 +CYREG_UDB_DSI2_HS12 EQU 0x400f429c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS13 +CYREG_UDB_DSI2_HS13 EQU 0x400f429d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS14 +CYREG_UDB_DSI2_HS14 EQU 0x400f429e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS15 +CYREG_UDB_DSI2_HS15 EQU 0x400f429f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS16 +CYREG_UDB_DSI2_HS16 EQU 0x400f42a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS17 +CYREG_UDB_DSI2_HS17 EQU 0x400f42a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS18 +CYREG_UDB_DSI2_HS18 EQU 0x400f42a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS19 +CYREG_UDB_DSI2_HS19 EQU 0x400f42a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS20 +CYREG_UDB_DSI2_HS20 EQU 0x400f42a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS21 +CYREG_UDB_DSI2_HS21 EQU 0x400f42a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS22 +CYREG_UDB_DSI2_HS22 EQU 0x400f42a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS23 +CYREG_UDB_DSI2_HS23 EQU 0x400f42a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R0 +CYREG_UDB_DSI2_HV_R0 EQU 0x400f42a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R1 +CYREG_UDB_DSI2_HV_R1 EQU 0x400f42a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R2 +CYREG_UDB_DSI2_HV_R2 EQU 0x400f42aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R3 +CYREG_UDB_DSI2_HV_R3 EQU 0x400f42ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R4 +CYREG_UDB_DSI2_HV_R4 EQU 0x400f42ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R5 +CYREG_UDB_DSI2_HV_R5 EQU 0x400f42ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R6 +CYREG_UDB_DSI2_HV_R6 EQU 0x400f42ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R7 +CYREG_UDB_DSI2_HV_R7 EQU 0x400f42af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R8 +CYREG_UDB_DSI2_HV_R8 EQU 0x400f42b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R9 +CYREG_UDB_DSI2_HV_R9 EQU 0x400f42b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R10 +CYREG_UDB_DSI2_HV_R10 EQU 0x400f42b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R11 +CYREG_UDB_DSI2_HV_R11 EQU 0x400f42b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R12 +CYREG_UDB_DSI2_HV_R12 EQU 0x400f42b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R13 +CYREG_UDB_DSI2_HV_R13 EQU 0x400f42b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R14 +CYREG_UDB_DSI2_HV_R14 EQU 0x400f42b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R15 +CYREG_UDB_DSI2_HV_R15 EQU 0x400f42b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP0 +CYREG_UDB_DSI2_DSIINP0 EQU 0x400f42c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP1 +CYREG_UDB_DSI2_DSIINP1 EQU 0x400f42c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP2 +CYREG_UDB_DSI2_DSIINP2 EQU 0x400f42c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP3 +CYREG_UDB_DSI2_DSIINP3 EQU 0x400f42c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP4 +CYREG_UDB_DSI2_DSIINP4 EQU 0x400f42c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP5 +CYREG_UDB_DSI2_DSIINP5 EQU 0x400f42ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP0 +CYREG_UDB_DSI2_DSIOUTP0 EQU 0x400f42cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP1 +CYREG_UDB_DSI2_DSIOUTP1 EQU 0x400f42ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP2 +CYREG_UDB_DSI2_DSIOUTP2 EQU 0x400f42d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP3 +CYREG_UDB_DSI2_DSIOUTP3 EQU 0x400f42d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT0 +CYREG_UDB_DSI2_DSIOUTT0 EQU 0x400f42d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT1 +CYREG_UDB_DSI2_DSIOUTT1 EQU 0x400f42d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT2 +CYREG_UDB_DSI2_DSIOUTT2 EQU 0x400f42d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT3 +CYREG_UDB_DSI2_DSIOUTT3 EQU 0x400f42da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT4 +CYREG_UDB_DSI2_DSIOUTT4 EQU 0x400f42dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT5 +CYREG_UDB_DSI2_DSIOUTT5 EQU 0x400f42de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS0 +CYREG_UDB_DSI2_VS0 EQU 0x400f42e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS1 +CYREG_UDB_DSI2_VS1 EQU 0x400f42e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS2 +CYREG_UDB_DSI2_VS2 EQU 0x400f42e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS3 +CYREG_UDB_DSI2_VS3 EQU 0x400f42e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS4 +CYREG_UDB_DSI2_VS4 EQU 0x400f42e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS5 +CYREG_UDB_DSI2_VS5 EQU 0x400f42ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS6 +CYREG_UDB_DSI2_VS6 EQU 0x400f42ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS7 +CYREG_UDB_DSI2_VS7 EQU 0x400f42ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI3_BASE +CYDEV_UDB_DSI3_BASE EQU 0x400f4300 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI3_SIZE +CYDEV_UDB_DSI3_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC0 +CYREG_UDB_DSI3_HC0 EQU 0x400f4300 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC1 +CYREG_UDB_DSI3_HC1 EQU 0x400f4301 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC2 +CYREG_UDB_DSI3_HC2 EQU 0x400f4302 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC3 +CYREG_UDB_DSI3_HC3 EQU 0x400f4303 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC4 +CYREG_UDB_DSI3_HC4 EQU 0x400f4304 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC5 +CYREG_UDB_DSI3_HC5 EQU 0x400f4305 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC6 +CYREG_UDB_DSI3_HC6 EQU 0x400f4306 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC7 +CYREG_UDB_DSI3_HC7 EQU 0x400f4307 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC8 +CYREG_UDB_DSI3_HC8 EQU 0x400f4308 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC9 +CYREG_UDB_DSI3_HC9 EQU 0x400f4309 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC10 +CYREG_UDB_DSI3_HC10 EQU 0x400f430a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC11 +CYREG_UDB_DSI3_HC11 EQU 0x400f430b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC12 +CYREG_UDB_DSI3_HC12 EQU 0x400f430c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC13 +CYREG_UDB_DSI3_HC13 EQU 0x400f430d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC14 +CYREG_UDB_DSI3_HC14 EQU 0x400f430e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC15 +CYREG_UDB_DSI3_HC15 EQU 0x400f430f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC16 +CYREG_UDB_DSI3_HC16 EQU 0x400f4310 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC17 +CYREG_UDB_DSI3_HC17 EQU 0x400f4311 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC18 +CYREG_UDB_DSI3_HC18 EQU 0x400f4312 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC19 +CYREG_UDB_DSI3_HC19 EQU 0x400f4313 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC20 +CYREG_UDB_DSI3_HC20 EQU 0x400f4314 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC21 +CYREG_UDB_DSI3_HC21 EQU 0x400f4315 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC22 +CYREG_UDB_DSI3_HC22 EQU 0x400f4316 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC23 +CYREG_UDB_DSI3_HC23 EQU 0x400f4317 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC24 +CYREG_UDB_DSI3_HC24 EQU 0x400f4318 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC25 +CYREG_UDB_DSI3_HC25 EQU 0x400f4319 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC26 +CYREG_UDB_DSI3_HC26 EQU 0x400f431a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC27 +CYREG_UDB_DSI3_HC27 EQU 0x400f431b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC28 +CYREG_UDB_DSI3_HC28 EQU 0x400f431c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC29 +CYREG_UDB_DSI3_HC29 EQU 0x400f431d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC30 +CYREG_UDB_DSI3_HC30 EQU 0x400f431e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC31 +CYREG_UDB_DSI3_HC31 EQU 0x400f431f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC32 +CYREG_UDB_DSI3_HC32 EQU 0x400f4320 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC33 +CYREG_UDB_DSI3_HC33 EQU 0x400f4321 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC34 +CYREG_UDB_DSI3_HC34 EQU 0x400f4322 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC35 +CYREG_UDB_DSI3_HC35 EQU 0x400f4323 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC36 +CYREG_UDB_DSI3_HC36 EQU 0x400f4324 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC37 +CYREG_UDB_DSI3_HC37 EQU 0x400f4325 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC38 +CYREG_UDB_DSI3_HC38 EQU 0x400f4326 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC39 +CYREG_UDB_DSI3_HC39 EQU 0x400f4327 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC40 +CYREG_UDB_DSI3_HC40 EQU 0x400f4328 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC41 +CYREG_UDB_DSI3_HC41 EQU 0x400f4329 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC42 +CYREG_UDB_DSI3_HC42 EQU 0x400f432a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC43 +CYREG_UDB_DSI3_HC43 EQU 0x400f432b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC44 +CYREG_UDB_DSI3_HC44 EQU 0x400f432c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC45 +CYREG_UDB_DSI3_HC45 EQU 0x400f432d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC46 +CYREG_UDB_DSI3_HC46 EQU 0x400f432e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC47 +CYREG_UDB_DSI3_HC47 EQU 0x400f432f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC48 +CYREG_UDB_DSI3_HC48 EQU 0x400f4330 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC49 +CYREG_UDB_DSI3_HC49 EQU 0x400f4331 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC50 +CYREG_UDB_DSI3_HC50 EQU 0x400f4332 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC51 +CYREG_UDB_DSI3_HC51 EQU 0x400f4333 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC52 +CYREG_UDB_DSI3_HC52 EQU 0x400f4334 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC53 +CYREG_UDB_DSI3_HC53 EQU 0x400f4335 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC54 +CYREG_UDB_DSI3_HC54 EQU 0x400f4336 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC55 +CYREG_UDB_DSI3_HC55 EQU 0x400f4337 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC56 +CYREG_UDB_DSI3_HC56 EQU 0x400f4338 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC57 +CYREG_UDB_DSI3_HC57 EQU 0x400f4339 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC58 +CYREG_UDB_DSI3_HC58 EQU 0x400f433a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC59 +CYREG_UDB_DSI3_HC59 EQU 0x400f433b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC60 +CYREG_UDB_DSI3_HC60 EQU 0x400f433c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC61 +CYREG_UDB_DSI3_HC61 EQU 0x400f433d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC62 +CYREG_UDB_DSI3_HC62 EQU 0x400f433e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC63 +CYREG_UDB_DSI3_HC63 EQU 0x400f433f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC64 +CYREG_UDB_DSI3_HC64 EQU 0x400f4340 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC65 +CYREG_UDB_DSI3_HC65 EQU 0x400f4341 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC66 +CYREG_UDB_DSI3_HC66 EQU 0x400f4342 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC67 +CYREG_UDB_DSI3_HC67 EQU 0x400f4343 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC68 +CYREG_UDB_DSI3_HC68 EQU 0x400f4344 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC69 +CYREG_UDB_DSI3_HC69 EQU 0x400f4345 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC70 +CYREG_UDB_DSI3_HC70 EQU 0x400f4346 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC71 +CYREG_UDB_DSI3_HC71 EQU 0x400f4347 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC72 +CYREG_UDB_DSI3_HC72 EQU 0x400f4348 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC73 +CYREG_UDB_DSI3_HC73 EQU 0x400f4349 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC74 +CYREG_UDB_DSI3_HC74 EQU 0x400f434a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC75 +CYREG_UDB_DSI3_HC75 EQU 0x400f434b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC76 +CYREG_UDB_DSI3_HC76 EQU 0x400f434c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC77 +CYREG_UDB_DSI3_HC77 EQU 0x400f434d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC78 +CYREG_UDB_DSI3_HC78 EQU 0x400f434e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC79 +CYREG_UDB_DSI3_HC79 EQU 0x400f434f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC80 +CYREG_UDB_DSI3_HC80 EQU 0x400f4350 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC81 +CYREG_UDB_DSI3_HC81 EQU 0x400f4351 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC82 +CYREG_UDB_DSI3_HC82 EQU 0x400f4352 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC83 +CYREG_UDB_DSI3_HC83 EQU 0x400f4353 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC84 +CYREG_UDB_DSI3_HC84 EQU 0x400f4354 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC85 +CYREG_UDB_DSI3_HC85 EQU 0x400f4355 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC86 +CYREG_UDB_DSI3_HC86 EQU 0x400f4356 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC87 +CYREG_UDB_DSI3_HC87 EQU 0x400f4357 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC88 +CYREG_UDB_DSI3_HC88 EQU 0x400f4358 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC89 +CYREG_UDB_DSI3_HC89 EQU 0x400f4359 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC90 +CYREG_UDB_DSI3_HC90 EQU 0x400f435a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC91 +CYREG_UDB_DSI3_HC91 EQU 0x400f435b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC92 +CYREG_UDB_DSI3_HC92 EQU 0x400f435c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC93 +CYREG_UDB_DSI3_HC93 EQU 0x400f435d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC94 +CYREG_UDB_DSI3_HC94 EQU 0x400f435e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC95 +CYREG_UDB_DSI3_HC95 EQU 0x400f435f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC96 +CYREG_UDB_DSI3_HC96 EQU 0x400f4360 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC97 +CYREG_UDB_DSI3_HC97 EQU 0x400f4361 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC98 +CYREG_UDB_DSI3_HC98 EQU 0x400f4362 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC99 +CYREG_UDB_DSI3_HC99 EQU 0x400f4363 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC100 +CYREG_UDB_DSI3_HC100 EQU 0x400f4364 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC101 +CYREG_UDB_DSI3_HC101 EQU 0x400f4365 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC102 +CYREG_UDB_DSI3_HC102 EQU 0x400f4366 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC103 +CYREG_UDB_DSI3_HC103 EQU 0x400f4367 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC104 +CYREG_UDB_DSI3_HC104 EQU 0x400f4368 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC105 +CYREG_UDB_DSI3_HC105 EQU 0x400f4369 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC106 +CYREG_UDB_DSI3_HC106 EQU 0x400f436a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC107 +CYREG_UDB_DSI3_HC107 EQU 0x400f436b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC108 +CYREG_UDB_DSI3_HC108 EQU 0x400f436c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC109 +CYREG_UDB_DSI3_HC109 EQU 0x400f436d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC110 +CYREG_UDB_DSI3_HC110 EQU 0x400f436e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC111 +CYREG_UDB_DSI3_HC111 EQU 0x400f436f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC112 +CYREG_UDB_DSI3_HC112 EQU 0x400f4370 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC113 +CYREG_UDB_DSI3_HC113 EQU 0x400f4371 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC114 +CYREG_UDB_DSI3_HC114 EQU 0x400f4372 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC115 +CYREG_UDB_DSI3_HC115 EQU 0x400f4373 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC116 +CYREG_UDB_DSI3_HC116 EQU 0x400f4374 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC117 +CYREG_UDB_DSI3_HC117 EQU 0x400f4375 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC118 +CYREG_UDB_DSI3_HC118 EQU 0x400f4376 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC119 +CYREG_UDB_DSI3_HC119 EQU 0x400f4377 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC120 +CYREG_UDB_DSI3_HC120 EQU 0x400f4378 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC121 +CYREG_UDB_DSI3_HC121 EQU 0x400f4379 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC122 +CYREG_UDB_DSI3_HC122 EQU 0x400f437a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC123 +CYREG_UDB_DSI3_HC123 EQU 0x400f437b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC124 +CYREG_UDB_DSI3_HC124 EQU 0x400f437c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC125 +CYREG_UDB_DSI3_HC125 EQU 0x400f437d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC126 +CYREG_UDB_DSI3_HC126 EQU 0x400f437e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC127 +CYREG_UDB_DSI3_HC127 EQU 0x400f437f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L0 +CYREG_UDB_DSI3_HV_L0 EQU 0x400f4380 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L1 +CYREG_UDB_DSI3_HV_L1 EQU 0x400f4381 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L2 +CYREG_UDB_DSI3_HV_L2 EQU 0x400f4382 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L3 +CYREG_UDB_DSI3_HV_L3 EQU 0x400f4383 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L4 +CYREG_UDB_DSI3_HV_L4 EQU 0x400f4384 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L5 +CYREG_UDB_DSI3_HV_L5 EQU 0x400f4385 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L6 +CYREG_UDB_DSI3_HV_L6 EQU 0x400f4386 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L7 +CYREG_UDB_DSI3_HV_L7 EQU 0x400f4387 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L8 +CYREG_UDB_DSI3_HV_L8 EQU 0x400f4388 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L9 +CYREG_UDB_DSI3_HV_L9 EQU 0x400f4389 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L10 +CYREG_UDB_DSI3_HV_L10 EQU 0x400f438a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L11 +CYREG_UDB_DSI3_HV_L11 EQU 0x400f438b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L12 +CYREG_UDB_DSI3_HV_L12 EQU 0x400f438c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L13 +CYREG_UDB_DSI3_HV_L13 EQU 0x400f438d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L14 +CYREG_UDB_DSI3_HV_L14 EQU 0x400f438e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L15 +CYREG_UDB_DSI3_HV_L15 EQU 0x400f438f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS0 +CYREG_UDB_DSI3_HS0 EQU 0x400f4390 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS1 +CYREG_UDB_DSI3_HS1 EQU 0x400f4391 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS2 +CYREG_UDB_DSI3_HS2 EQU 0x400f4392 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS3 +CYREG_UDB_DSI3_HS3 EQU 0x400f4393 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS4 +CYREG_UDB_DSI3_HS4 EQU 0x400f4394 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS5 +CYREG_UDB_DSI3_HS5 EQU 0x400f4395 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS6 +CYREG_UDB_DSI3_HS6 EQU 0x400f4396 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS7 +CYREG_UDB_DSI3_HS7 EQU 0x400f4397 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS8 +CYREG_UDB_DSI3_HS8 EQU 0x400f4398 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS9 +CYREG_UDB_DSI3_HS9 EQU 0x400f4399 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS10 +CYREG_UDB_DSI3_HS10 EQU 0x400f439a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS11 +CYREG_UDB_DSI3_HS11 EQU 0x400f439b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS12 +CYREG_UDB_DSI3_HS12 EQU 0x400f439c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS13 +CYREG_UDB_DSI3_HS13 EQU 0x400f439d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS14 +CYREG_UDB_DSI3_HS14 EQU 0x400f439e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS15 +CYREG_UDB_DSI3_HS15 EQU 0x400f439f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS16 +CYREG_UDB_DSI3_HS16 EQU 0x400f43a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS17 +CYREG_UDB_DSI3_HS17 EQU 0x400f43a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS18 +CYREG_UDB_DSI3_HS18 EQU 0x400f43a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS19 +CYREG_UDB_DSI3_HS19 EQU 0x400f43a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS20 +CYREG_UDB_DSI3_HS20 EQU 0x400f43a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS21 +CYREG_UDB_DSI3_HS21 EQU 0x400f43a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS22 +CYREG_UDB_DSI3_HS22 EQU 0x400f43a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS23 +CYREG_UDB_DSI3_HS23 EQU 0x400f43a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R0 +CYREG_UDB_DSI3_HV_R0 EQU 0x400f43a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R1 +CYREG_UDB_DSI3_HV_R1 EQU 0x400f43a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R2 +CYREG_UDB_DSI3_HV_R2 EQU 0x400f43aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R3 +CYREG_UDB_DSI3_HV_R3 EQU 0x400f43ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R4 +CYREG_UDB_DSI3_HV_R4 EQU 0x400f43ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R5 +CYREG_UDB_DSI3_HV_R5 EQU 0x400f43ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R6 +CYREG_UDB_DSI3_HV_R6 EQU 0x400f43ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R7 +CYREG_UDB_DSI3_HV_R7 EQU 0x400f43af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R8 +CYREG_UDB_DSI3_HV_R8 EQU 0x400f43b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R9 +CYREG_UDB_DSI3_HV_R9 EQU 0x400f43b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R10 +CYREG_UDB_DSI3_HV_R10 EQU 0x400f43b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R11 +CYREG_UDB_DSI3_HV_R11 EQU 0x400f43b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R12 +CYREG_UDB_DSI3_HV_R12 EQU 0x400f43b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R13 +CYREG_UDB_DSI3_HV_R13 EQU 0x400f43b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R14 +CYREG_UDB_DSI3_HV_R14 EQU 0x400f43b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R15 +CYREG_UDB_DSI3_HV_R15 EQU 0x400f43b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP0 +CYREG_UDB_DSI3_DSIINP0 EQU 0x400f43c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP1 +CYREG_UDB_DSI3_DSIINP1 EQU 0x400f43c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP2 +CYREG_UDB_DSI3_DSIINP2 EQU 0x400f43c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP3 +CYREG_UDB_DSI3_DSIINP3 EQU 0x400f43c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP4 +CYREG_UDB_DSI3_DSIINP4 EQU 0x400f43c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP5 +CYREG_UDB_DSI3_DSIINP5 EQU 0x400f43ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP0 +CYREG_UDB_DSI3_DSIOUTP0 EQU 0x400f43cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP1 +CYREG_UDB_DSI3_DSIOUTP1 EQU 0x400f43ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP2 +CYREG_UDB_DSI3_DSIOUTP2 EQU 0x400f43d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP3 +CYREG_UDB_DSI3_DSIOUTP3 EQU 0x400f43d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT0 +CYREG_UDB_DSI3_DSIOUTT0 EQU 0x400f43d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT1 +CYREG_UDB_DSI3_DSIOUTT1 EQU 0x400f43d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT2 +CYREG_UDB_DSI3_DSIOUTT2 EQU 0x400f43d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT3 +CYREG_UDB_DSI3_DSIOUTT3 EQU 0x400f43da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT4 +CYREG_UDB_DSI3_DSIOUTT4 EQU 0x400f43dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT5 +CYREG_UDB_DSI3_DSIOUTT5 EQU 0x400f43de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS0 +CYREG_UDB_DSI3_VS0 EQU 0x400f43e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS1 +CYREG_UDB_DSI3_VS1 EQU 0x400f43e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS2 +CYREG_UDB_DSI3_VS2 EQU 0x400f43e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS3 +CYREG_UDB_DSI3_VS3 EQU 0x400f43e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS4 +CYREG_UDB_DSI3_VS4 EQU 0x400f43e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS5 +CYREG_UDB_DSI3_VS5 EQU 0x400f43ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS6 +CYREG_UDB_DSI3_VS6 EQU 0x400f43ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS7 +CYREG_UDB_DSI3_VS7 EQU 0x400f43ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA0_BASE +CYDEV_UDB_PA0_BASE EQU 0x400f5000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA0_SIZE +CYDEV_UDB_PA0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG0 +CYREG_UDB_PA0_CFG0 EQU 0x400f5000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET +CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE +CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC +CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET +CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE +CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_OFF +CYVAL_UDB_PA_CLKIN_EN_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_ON +CYVAL_UDB_PA_CLKIN_EN_MODE_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE +CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL +CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET +CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_INV__SIZE +CYFLD_UDB_PA_CLKIN_EN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_INV_NOINV +CYVAL_UDB_PA_CLKIN_EN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_INV_INV +CYVAL_UDB_PA_CLKIN_EN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_INV__OFFSET +CYFLD_UDB_PA_CLKIN_INV__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_INV__SIZE +CYFLD_UDB_PA_CLKIN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_INV_NOINV +CYVAL_UDB_PA_CLKIN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_INV_INV +CYVAL_UDB_PA_CLKIN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC__OFFSET +CYFLD_UDB_PA_NC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC__SIZE +CYFLD_UDB_PA_NC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG1 +CYREG_UDB_PA0_CFG1 EQU 0x400f5001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET +CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE +CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC +CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET +CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE +CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF +CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_ON +CYVAL_UDB_PA_CLKOUT_EN_MODE_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE +CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL +CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET +CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE +CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV +CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_INV_INV +CYVAL_UDB_PA_CLKOUT_EN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_INV__OFFSET +CYFLD_UDB_PA_CLKOUT_INV__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_INV__SIZE +CYFLD_UDB_PA_CLKOUT_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_INV_NOINV +CYVAL_UDB_PA_CLKOUT_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_INV_INV +CYVAL_UDB_PA_CLKOUT_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG2 +CYREG_UDB_PA0_CFG2 EQU 0x400f5002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_SEL__OFFSET +CYFLD_UDB_PA_CLKIN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_SEL__SIZE +CYFLD_UDB_PA_CLKIN_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK0 +CYVAL_UDB_PA_CLKIN_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK1 +CYVAL_UDB_PA_CLKIN_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK2 +CYVAL_UDB_PA_CLKIN_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK3 +CYVAL_UDB_PA_CLKIN_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK4 +CYVAL_UDB_PA_CLKIN_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK5 +CYVAL_UDB_PA_CLKIN_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK6 +CYVAL_UDB_PA_CLKIN_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK7 +CYVAL_UDB_PA_CLKIN_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP +CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_PIN_RC +CYVAL_UDB_PA_CLKIN_SEL_PIN_RC EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_SEL__OFFSET +CYFLD_UDB_PA_CLKOUT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_SEL__SIZE +CYFLD_UDB_PA_CLKOUT_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP +CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC +CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG3 +CYREG_UDB_PA0_CFG3 EQU 0x400f5003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_SEL__OFFSET +CYFLD_UDB_PA_RES_IN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_SEL__SIZE +CYFLD_UDB_PA_RES_IN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_PIN_RC +CYVAL_UDB_PA_RES_IN_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 +CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 +CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 +CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_INV__OFFSET +CYFLD_UDB_PA_RES_IN_INV__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_INV__SIZE +CYFLD_UDB_PA_RES_IN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_INV_NOINV +CYVAL_UDB_PA_RES_IN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_INV_INV +CYVAL_UDB_PA_RES_IN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC0__OFFSET +CYFLD_UDB_PA_NC0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC0__SIZE +CYFLD_UDB_PA_NC0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_SEL__OFFSET +CYFLD_UDB_PA_RES_OUT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_SEL__SIZE +CYFLD_UDB_PA_RES_OUT_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC +CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 +CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 +CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 +CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_INV__OFFSET +CYFLD_UDB_PA_RES_OUT_INV__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_INV__SIZE +CYFLD_UDB_PA_RES_OUT_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_INV_NOINV +CYVAL_UDB_PA_RES_OUT_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_INV_INV +CYVAL_UDB_PA_RES_OUT_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7__OFFSET +CYFLD_UDB_PA_NC7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7__SIZE +CYFLD_UDB_PA_NC7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG4 +CYREG_UDB_PA0_CFG4 EQU 0x400f5004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_EN__OFFSET +CYFLD_UDB_PA_RES_IN_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_EN__SIZE +CYFLD_UDB_PA_RES_IN_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_EN_DISABLE +CYVAL_UDB_PA_RES_IN_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_EN_ENABLE +CYVAL_UDB_PA_RES_IN_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_EN__OFFSET +CYFLD_UDB_PA_RES_OUT_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_EN__SIZE +CYFLD_UDB_PA_RES_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_EN_DISABLE +CYVAL_UDB_PA_RES_OUT_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_EN_ENABLE +CYVAL_UDB_PA_RES_OUT_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OE_EN__OFFSET +CYFLD_UDB_PA_RES_OE_EN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OE_EN__SIZE +CYFLD_UDB_PA_RES_OE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OE_EN_DISABLE +CYVAL_UDB_PA_RES_OE_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OE_EN_ENABLE +CYVAL_UDB_PA_RES_OE_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7654__OFFSET +CYFLD_UDB_PA_NC7654__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7654__SIZE +CYFLD_UDB_PA_NC7654__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG5 +CYREG_UDB_PA0_CFG5 EQU 0x400f5005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_PIN_SEL__OFFSET +CYFLD_UDB_PA_PIN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_PIN_SEL__SIZE +CYFLD_UDB_PA_PIN_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN0 +CYVAL_UDB_PA_PIN_SEL_PIN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN1 +CYVAL_UDB_PA_PIN_SEL_PIN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN2 +CYVAL_UDB_PA_PIN_SEL_PIN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN3 +CYVAL_UDB_PA_PIN_SEL_PIN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN4 +CYVAL_UDB_PA_PIN_SEL_PIN4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN5 +CYVAL_UDB_PA_PIN_SEL_PIN5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN6 +CYVAL_UDB_PA_PIN_SEL_PIN6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN7 +CYVAL_UDB_PA_PIN_SEL_PIN7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG6 +CYREG_UDB_PA0_CFG6 EQU 0x400f5006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC0__OFFSET +CYFLD_UDB_PA_IN_SYNC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC0__SIZE +CYFLD_UDB_PA_IN_SYNC0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_RSVD +CYVAL_UDB_PA_IN_SYNC0_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC1__OFFSET +CYFLD_UDB_PA_IN_SYNC1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC1__SIZE +CYFLD_UDB_PA_IN_SYNC1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_RSVD +CYVAL_UDB_PA_IN_SYNC1_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC2__OFFSET +CYFLD_UDB_PA_IN_SYNC2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC2__SIZE +CYFLD_UDB_PA_IN_SYNC2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_RSVD +CYVAL_UDB_PA_IN_SYNC2_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC3__OFFSET +CYFLD_UDB_PA_IN_SYNC3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC3__SIZE +CYFLD_UDB_PA_IN_SYNC3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_RSVD +CYVAL_UDB_PA_IN_SYNC3_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG7 +CYREG_UDB_PA0_CFG7 EQU 0x400f5007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC4__OFFSET +CYFLD_UDB_PA_IN_SYNC4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC4__SIZE +CYFLD_UDB_PA_IN_SYNC4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_RSVD +CYVAL_UDB_PA_IN_SYNC4_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC5__OFFSET +CYFLD_UDB_PA_IN_SYNC5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC5__SIZE +CYFLD_UDB_PA_IN_SYNC5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_RSVD +CYVAL_UDB_PA_IN_SYNC5_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC6__OFFSET +CYFLD_UDB_PA_IN_SYNC6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC6__SIZE +CYFLD_UDB_PA_IN_SYNC6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_RSVD +CYVAL_UDB_PA_IN_SYNC6_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC7__OFFSET +CYFLD_UDB_PA_IN_SYNC7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC7__SIZE +CYFLD_UDB_PA_IN_SYNC7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_RSVD +CYVAL_UDB_PA_IN_SYNC7_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG8 +CYREG_UDB_PA0_CFG8 EQU 0x400f5008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC0__OFFSET +CYFLD_UDB_PA_OUT_SYNC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC0__SIZE +CYFLD_UDB_PA_OUT_SYNC0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_CLOCK +CYVAL_UDB_PA_OUT_SYNC0_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC1__OFFSET +CYFLD_UDB_PA_OUT_SYNC1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC1__SIZE +CYFLD_UDB_PA_OUT_SYNC1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_CLOCK +CYVAL_UDB_PA_OUT_SYNC1_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC2__OFFSET +CYFLD_UDB_PA_OUT_SYNC2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC2__SIZE +CYFLD_UDB_PA_OUT_SYNC2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_CLOCK +CYVAL_UDB_PA_OUT_SYNC2_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC3__OFFSET +CYFLD_UDB_PA_OUT_SYNC3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC3__SIZE +CYFLD_UDB_PA_OUT_SYNC3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_CLOCK +CYVAL_UDB_PA_OUT_SYNC3_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG9 +CYREG_UDB_PA0_CFG9 EQU 0x400f5009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC4__OFFSET +CYFLD_UDB_PA_OUT_SYNC4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC4__SIZE +CYFLD_UDB_PA_OUT_SYNC4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_CLOCK +CYVAL_UDB_PA_OUT_SYNC4_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC5__OFFSET +CYFLD_UDB_PA_OUT_SYNC5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC5__SIZE +CYFLD_UDB_PA_OUT_SYNC5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_CLOCK +CYVAL_UDB_PA_OUT_SYNC5_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC6__OFFSET +CYFLD_UDB_PA_OUT_SYNC6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC6__SIZE +CYFLD_UDB_PA_OUT_SYNC6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_CLOCK +CYVAL_UDB_PA_OUT_SYNC6_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC7__OFFSET +CYFLD_UDB_PA_OUT_SYNC7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC7__SIZE +CYFLD_UDB_PA_OUT_SYNC7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_CLOCK +CYVAL_UDB_PA_OUT_SYNC7_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG10 +CYREG_UDB_PA0_CFG10 EQU 0x400f500a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL0__OFFSET +CYFLD_UDB_PA_DATA_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL0__SIZE +CYFLD_UDB_PA_DATA_SEL0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL1__OFFSET +CYFLD_UDB_PA_DATA_SEL1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL1__SIZE +CYFLD_UDB_PA_DATA_SEL1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL2__OFFSET +CYFLD_UDB_PA_DATA_SEL2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL2__SIZE +CYFLD_UDB_PA_DATA_SEL2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL3__OFFSET +CYFLD_UDB_PA_DATA_SEL3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL3__SIZE +CYFLD_UDB_PA_DATA_SEL3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG11 +CYREG_UDB_PA0_CFG11 EQU 0x400f500b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL4__OFFSET +CYFLD_UDB_PA_DATA_SEL4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL4__SIZE +CYFLD_UDB_PA_DATA_SEL4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL5__OFFSET +CYFLD_UDB_PA_DATA_SEL5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL5__SIZE +CYFLD_UDB_PA_DATA_SEL5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL6__OFFSET +CYFLD_UDB_PA_DATA_SEL6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL6__SIZE +CYFLD_UDB_PA_DATA_SEL6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL7__OFFSET +CYFLD_UDB_PA_DATA_SEL7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL7__SIZE +CYFLD_UDB_PA_DATA_SEL7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG12 +CYREG_UDB_PA0_CFG12 EQU 0x400f500c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL0__OFFSET +CYFLD_UDB_PA_OE_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL0__SIZE +CYFLD_UDB_PA_OE_SEL0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL1__OFFSET +CYFLD_UDB_PA_OE_SEL1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL1__SIZE +CYFLD_UDB_PA_OE_SEL1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL2__OFFSET +CYFLD_UDB_PA_OE_SEL2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL2__SIZE +CYFLD_UDB_PA_OE_SEL2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL3__OFFSET +CYFLD_UDB_PA_OE_SEL3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL3__SIZE +CYFLD_UDB_PA_OE_SEL3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG13 +CYREG_UDB_PA0_CFG13 EQU 0x400f500d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL4__OFFSET +CYFLD_UDB_PA_OE_SEL4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL4__SIZE +CYFLD_UDB_PA_OE_SEL4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL5__OFFSET +CYFLD_UDB_PA_OE_SEL5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL5__SIZE +CYFLD_UDB_PA_OE_SEL5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL6__OFFSET +CYFLD_UDB_PA_OE_SEL6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL6__SIZE +CYFLD_UDB_PA_OE_SEL6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL7__OFFSET +CYFLD_UDB_PA_OE_SEL7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL7__SIZE +CYFLD_UDB_PA_OE_SEL7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG14 +CYREG_UDB_PA0_CFG14 EQU 0x400f500e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC0__OFFSET +CYFLD_UDB_PA_OE_SYNC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC0__SIZE +CYFLD_UDB_PA_OE_SYNC0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC1__OFFSET +CYFLD_UDB_PA_OE_SYNC1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC1__SIZE +CYFLD_UDB_PA_OE_SYNC1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC2__OFFSET +CYFLD_UDB_PA_OE_SYNC2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC2__SIZE +CYFLD_UDB_PA_OE_SYNC2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC3__OFFSET +CYFLD_UDB_PA_OE_SYNC3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC3__SIZE +CYFLD_UDB_PA_OE_SYNC3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA1_BASE +CYDEV_UDB_PA1_BASE EQU 0x400f5010 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA1_SIZE +CYDEV_UDB_PA1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG0 +CYREG_UDB_PA1_CFG0 EQU 0x400f5010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG1 +CYREG_UDB_PA1_CFG1 EQU 0x400f5011 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG2 +CYREG_UDB_PA1_CFG2 EQU 0x400f5012 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG3 +CYREG_UDB_PA1_CFG3 EQU 0x400f5013 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG4 +CYREG_UDB_PA1_CFG4 EQU 0x400f5014 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG5 +CYREG_UDB_PA1_CFG5 EQU 0x400f5015 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG6 +CYREG_UDB_PA1_CFG6 EQU 0x400f5016 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG7 +CYREG_UDB_PA1_CFG7 EQU 0x400f5017 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG8 +CYREG_UDB_PA1_CFG8 EQU 0x400f5018 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG9 +CYREG_UDB_PA1_CFG9 EQU 0x400f5019 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG10 +CYREG_UDB_PA1_CFG10 EQU 0x400f501a + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG11 +CYREG_UDB_PA1_CFG11 EQU 0x400f501b + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG12 +CYREG_UDB_PA1_CFG12 EQU 0x400f501c + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG13 +CYREG_UDB_PA1_CFG13 EQU 0x400f501d + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG14 +CYREG_UDB_PA1_CFG14 EQU 0x400f501e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA2_BASE +CYDEV_UDB_PA2_BASE EQU 0x400f5020 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA2_SIZE +CYDEV_UDB_PA2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG0 +CYREG_UDB_PA2_CFG0 EQU 0x400f5020 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG1 +CYREG_UDB_PA2_CFG1 EQU 0x400f5021 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG2 +CYREG_UDB_PA2_CFG2 EQU 0x400f5022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG3 +CYREG_UDB_PA2_CFG3 EQU 0x400f5023 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG4 +CYREG_UDB_PA2_CFG4 EQU 0x400f5024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG5 +CYREG_UDB_PA2_CFG5 EQU 0x400f5025 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG6 +CYREG_UDB_PA2_CFG6 EQU 0x400f5026 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG7 +CYREG_UDB_PA2_CFG7 EQU 0x400f5027 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG8 +CYREG_UDB_PA2_CFG8 EQU 0x400f5028 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG9 +CYREG_UDB_PA2_CFG9 EQU 0x400f5029 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG10 +CYREG_UDB_PA2_CFG10 EQU 0x400f502a + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG11 +CYREG_UDB_PA2_CFG11 EQU 0x400f502b + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG12 +CYREG_UDB_PA2_CFG12 EQU 0x400f502c + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG13 +CYREG_UDB_PA2_CFG13 EQU 0x400f502d + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG14 +CYREG_UDB_PA2_CFG14 EQU 0x400f502e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA3_BASE +CYDEV_UDB_PA3_BASE EQU 0x400f5030 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA3_SIZE +CYDEV_UDB_PA3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG0 +CYREG_UDB_PA3_CFG0 EQU 0x400f5030 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG1 +CYREG_UDB_PA3_CFG1 EQU 0x400f5031 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG2 +CYREG_UDB_PA3_CFG2 EQU 0x400f5032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG3 +CYREG_UDB_PA3_CFG3 EQU 0x400f5033 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG4 +CYREG_UDB_PA3_CFG4 EQU 0x400f5034 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG5 +CYREG_UDB_PA3_CFG5 EQU 0x400f5035 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG6 +CYREG_UDB_PA3_CFG6 EQU 0x400f5036 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG7 +CYREG_UDB_PA3_CFG7 EQU 0x400f5037 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG8 +CYREG_UDB_PA3_CFG8 EQU 0x400f5038 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG9 +CYREG_UDB_PA3_CFG9 EQU 0x400f5039 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG10 +CYREG_UDB_PA3_CFG10 EQU 0x400f503a + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG11 +CYREG_UDB_PA3_CFG11 EQU 0x400f503b + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG12 +CYREG_UDB_PA3_CFG12 EQU 0x400f503c + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG13 +CYREG_UDB_PA3_CFG13 EQU 0x400f503d + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG14 +CYREG_UDB_PA3_CFG14 EQU 0x400f503e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_BCTL0_BASE +CYDEV_UDB_BCTL0_BASE EQU 0x400f6000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_BCTL0_SIZE +CYDEV_UDB_BCTL0_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_DRV +CYREG_UDB_BCTL0_DRV EQU 0x400f6000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DRV__OFFSET +CYFLD_UDB_BCTL0_DRV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DRV__SIZE +CYFLD_UDB_BCTL0_DRV__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DRV_DISABLE +CYVAL_UDB_BCTL0_DRV_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DRV_ENABLE +CYVAL_UDB_BCTL0_DRV_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_MDCLK_EN +CYREG_UDB_BCTL0_MDCLK_EN EQU 0x400f6001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN__OFFSET +CYFLD_UDB_BCTL0_DCEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN__SIZE +CYFLD_UDB_BCTL0_DCEN__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_DISABLE +CYVAL_UDB_BCTL0_DCEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_ENABLE +CYVAL_UDB_BCTL0_DCEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_MBCLK_EN +CYREG_UDB_BCTL0_MBCLK_EN EQU 0x400f6002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN__OFFSET +CYFLD_UDB_BCTL0_BCEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN__SIZE +CYFLD_UDB_BCTL0_BCEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_DISABLE +CYVAL_UDB_BCTL0_BCEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_ENABLE +CYVAL_UDB_BCTL0_BCEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_BOTSEL_L +CYREG_UDB_BCTL0_BOTSEL_L EQU 0x400f6008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL0__SIZE +CYFLD_UDB_BCTL0_CLK_SEL0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL1__SIZE +CYFLD_UDB_BCTL0_CLK_SEL1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL2__SIZE +CYFLD_UDB_BCTL0_CLK_SEL2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL3__SIZE +CYFLD_UDB_BCTL0_CLK_SEL3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_BOTSEL_U +CYREG_UDB_BCTL0_BOTSEL_U EQU 0x400f6009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL4__SIZE +CYFLD_UDB_BCTL0_CLK_SEL4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL5__SIZE +CYFLD_UDB_BCTL0_CLK_SEL5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL6__SIZE +CYFLD_UDB_BCTL0_CLK_SEL6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL7__SIZE +CYFLD_UDB_BCTL0_CLK_SEL7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_TOPSEL_L +CYREG_UDB_BCTL0_TOPSEL_L EQU 0x400f600a + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_TOPSEL_U +CYREG_UDB_BCTL0_TOPSEL_U EQU 0x400f600b + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_QCLK_EN0 +CYREG_UDB_BCTL0_QCLK_EN0 EQU 0x400f6010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN_Q__OFFSET +CYFLD_UDB_BCTL0_DCEN_Q__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN_Q__SIZE +CYFLD_UDB_BCTL0_DCEN_Q__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_Q_DISABLE +CYVAL_UDB_BCTL0_DCEN_Q_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_Q_ENABLE +CYVAL_UDB_BCTL0_DCEN_Q_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN_Q__OFFSET +CYFLD_UDB_BCTL0_BCEN_Q__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN_Q__SIZE +CYFLD_UDB_BCTL0_BCEN_Q__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_Q_DISABLE +CYVAL_UDB_BCTL0_BCEN_Q_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_Q_ENABLE +CYVAL_UDB_BCTL0_BCEN_Q_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET +CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE +CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE +CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE +CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET +CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE +CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE +CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE +CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET +CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE +CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE +CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE +CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET +CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE +CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE +CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE +CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET +CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE +CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB +CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB +CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_NC0__OFFSET +CYFLD_UDB_BCTL0_NC0__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_NC0__SIZE +CYFLD_UDB_BCTL0_NC0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET +CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE +CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE +CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE +CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_QCLK_EN1 +CYREG_UDB_BCTL0_QCLK_EN1 EQU 0x400f6012 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_UDBIF_BASE +CYDEV_UDB_UDBIF_BASE EQU 0x400f7000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_UDBIF_SIZE +CYDEV_UDB_UDBIF_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_UDBIF_BANK_CTL +CYREG_UDB_UDBIF_BANK_CTL EQU 0x400f7000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_DIS_COR__OFFSET +CYFLD_UDB_UDBIF_DIS_COR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_DIS_COR__SIZE +CYFLD_UDB_UDBIF_DIS_COR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_DIS_COR_NORMAL +CYVAL_UDB_UDBIF_DIS_COR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_DIS_COR_DISABLE +CYVAL_UDB_UDBIF_DIS_COR_DISABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET +CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_ROUTE_EN__SIZE +CYFLD_UDB_UDBIF_ROUTE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE +CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE +CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_BANK_EN__OFFSET +CYFLD_UDB_UDBIF_BANK_EN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_BANK_EN__SIZE +CYFLD_UDB_UDBIF_BANK_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_BANK_EN_DISABLE +CYVAL_UDB_UDBIF_BANK_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_BANK_EN_ENABLE +CYVAL_UDB_UDBIF_BANK_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_LOCK__OFFSET +CYFLD_UDB_UDBIF_LOCK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_LOCK__SIZE +CYFLD_UDB_UDBIF_LOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_LOCK_MUTABLE +CYVAL_UDB_UDBIF_LOCK_MUTABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_LOCK_LOCKED +CYVAL_UDB_UDBIF_LOCK_LOCKED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_PIPE__OFFSET +CYFLD_UDB_UDBIF_PIPE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_PIPE__SIZE +CYFLD_UDB_UDBIF_PIPE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_PIPE_BYPASS +CYVAL_UDB_UDBIF_PIPE_BYPASS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_PIPE_PIPELINED +CYVAL_UDB_UDBIF_PIPE_PIPELINED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_GLBL_WR__OFFSET +CYFLD_UDB_UDBIF_GLBL_WR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_GLBL_WR__SIZE +CYFLD_UDB_UDBIF_GLBL_WR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_GLBL_WR_DISABLE +CYVAL_UDB_UDBIF_GLBL_WR_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_GLBL_WR_ENABLE +CYVAL_UDB_UDBIF_GLBL_WR_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_UDBIF_WAIT_CFG +CYREG_UDB_UDBIF_WAIT_CFG EQU 0x400f7001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET +CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE +CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS +CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS +CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET +CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE +CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS +CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS +CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET +CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE +CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS +CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS +CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET +CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE +CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS +CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS +CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_UDBIF_INT_CLK_CTL +CYREG_UDB_UDBIF_INT_CLK_CTL EQU 0x400f701c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET +CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_EN_HFCLK__SIZE +CYFLD_UDB_UDBIF_EN_HFCLK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_INT_CFG +CYREG_UDB_INT_CFG EQU 0x400f8000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_INT_MODE_CFG__OFFSET +CYFLD_UDB_INT_MODE_CFG__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_INT_MODE_CFG__SIZE +CYFLD_UDB_INT_MODE_CFG__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_INT_MODE_CFG_LEVEL +CYVAL_UDB_INT_MODE_CFG_LEVEL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_INT_MODE_CFG_PULSE +CYVAL_UDB_INT_MODE_CFG_PULSE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_CTBM_BASE +CYDEV_CTBM_BASE EQU 0x40100000 + ENDIF + IF :LNOT::DEF:CYDEV_CTBM_SIZE +CYDEV_CTBM_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_CTB_CTRL +CYREG_CTBM_CTB_CTRL EQU 0x40100000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_ENABLED__OFFSET +CYFLD_CTBM_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_ENABLED__SIZE +CYFLD_CTBM_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA_RES0_CTRL +CYREG_CTBM_OA_RES0_CTRL EQU 0x40100004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PWR_MODE__OFFSET +CYFLD_CTBM_OA0_PWR_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PWR_MODE__SIZE +CYFLD_CTBM_OA0_PWR_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET +CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE +CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_EN__OFFSET +CYFLD_CTBM_OA0_COMP_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_EN__SIZE +CYFLD_CTBM_OA0_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_HYST_EN__OFFSET +CYFLD_CTBM_OA0_HYST_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_HYST_EN__SIZE +CYFLD_CTBM_OA0_HYST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET +CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE +CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMPINT__OFFSET +CYFLD_CTBM_OA0_COMPINT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMPINT__SIZE +CYFLD_CTBM_OA0_COMPINT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_DISABLE +CYVAL_CTBM_OA0_COMPINT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_RISING +CYVAL_CTBM_OA0_COMPINT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_FALLING +CYVAL_CTBM_OA0_COMPINT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_BOTH +CYVAL_CTBM_OA0_COMPINT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PUMP_EN__OFFSET +CYFLD_CTBM_OA0_PUMP_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PUMP_EN__SIZE +CYFLD_CTBM_OA0_PUMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA_RES1_CTRL +CYREG_CTBM_OA_RES1_CTRL EQU 0x40100008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PWR_MODE__OFFSET +CYFLD_CTBM_OA1_PWR_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PWR_MODE__SIZE +CYFLD_CTBM_OA1_PWR_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET +CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE +CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_EN__OFFSET +CYFLD_CTBM_OA1_COMP_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_EN__SIZE +CYFLD_CTBM_OA1_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_HYST_EN__OFFSET +CYFLD_CTBM_OA1_HYST_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_HYST_EN__SIZE +CYFLD_CTBM_OA1_HYST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET +CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE +CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMPINT__OFFSET +CYFLD_CTBM_OA1_COMPINT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMPINT__SIZE +CYFLD_CTBM_OA1_COMPINT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_DISABLE +CYVAL_CTBM_OA1_COMPINT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_RISING +CYVAL_CTBM_OA1_COMPINT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_FALLING +CYVAL_CTBM_OA1_COMPINT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_BOTH +CYVAL_CTBM_OA1_COMPINT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PUMP_EN__OFFSET +CYFLD_CTBM_OA1_PUMP_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PUMP_EN__SIZE +CYFLD_CTBM_OA1_PUMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_COMP_STAT +CYREG_CTBM_COMP_STAT EQU 0x4010000c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP__OFFSET +CYFLD_CTBM_OA0_COMP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP__SIZE +CYFLD_CTBM_OA0_COMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP__OFFSET +CYFLD_CTBM_OA1_COMP__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP__SIZE +CYFLD_CTBM_OA1_COMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR +CYREG_CTBM_INTR EQU 0x40100020 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0__OFFSET +CYFLD_CTBM_COMP0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0__SIZE +CYFLD_CTBM_COMP0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1__OFFSET +CYFLD_CTBM_COMP1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1__SIZE +CYFLD_CTBM_COMP1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR_SET +CYREG_CTBM_INTR_SET EQU 0x40100024 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_SET__OFFSET +CYFLD_CTBM_COMP0_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_SET__SIZE +CYFLD_CTBM_COMP0_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_SET__OFFSET +CYFLD_CTBM_COMP1_SET__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_SET__SIZE +CYFLD_CTBM_COMP1_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR_MASK +CYREG_CTBM_INTR_MASK EQU 0x40100028 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASK__OFFSET +CYFLD_CTBM_COMP0_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASK__SIZE +CYFLD_CTBM_COMP0_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASK__OFFSET +CYFLD_CTBM_COMP1_MASK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASK__SIZE +CYFLD_CTBM_COMP1_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR_MASKED +CYREG_CTBM_INTR_MASKED EQU 0x4010002c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASKED__OFFSET +CYFLD_CTBM_COMP0_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASKED__SIZE +CYFLD_CTBM_COMP0_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASKED__OFFSET +CYFLD_CTBM_COMP1_MASKED__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASKED__SIZE +CYFLD_CTBM_COMP1_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_DFT_CTRL +CYREG_CTBM_DFT_CTRL EQU 0x40100030 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_MODE__OFFSET +CYFLD_CTBM_DFT_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_MODE__SIZE +CYFLD_CTBM_DFT_MODE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_EN__OFFSET +CYFLD_CTBM_DFT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_EN__SIZE +CYFLD_CTBM_DFT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_SW +CYREG_CTBM_OA0_SW EQU 0x40100080 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A00__OFFSET +CYFLD_CTBM_OA0P_A00__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A00__SIZE +CYFLD_CTBM_OA0P_A00__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A20__OFFSET +CYFLD_CTBM_OA0P_A20__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A20__SIZE +CYFLD_CTBM_OA0P_A20__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A30__OFFSET +CYFLD_CTBM_OA0P_A30__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A30__SIZE +CYFLD_CTBM_OA0P_A30__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A11__OFFSET +CYFLD_CTBM_OA0M_A11__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A11__SIZE +CYFLD_CTBM_OA0M_A11__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A81__OFFSET +CYFLD_CTBM_OA0M_A81__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A81__SIZE +CYFLD_CTBM_OA0M_A81__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51__OFFSET +CYFLD_CTBM_OA0O_D51__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51__SIZE +CYFLD_CTBM_OA0O_D51__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D81__OFFSET +CYFLD_CTBM_OA0O_D81__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D81__SIZE +CYFLD_CTBM_OA0O_D81__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_SW_CLEAR +CYREG_CTBM_OA0_SW_CLEAR EQU 0x40100084 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_SW +CYREG_CTBM_OA1_SW EQU 0x40100088 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A03__OFFSET +CYFLD_CTBM_OA1P_A03__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A03__SIZE +CYFLD_CTBM_OA1P_A03__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A13__OFFSET +CYFLD_CTBM_OA1P_A13__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A13__SIZE +CYFLD_CTBM_OA1P_A13__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A43__OFFSET +CYFLD_CTBM_OA1P_A43__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A43__SIZE +CYFLD_CTBM_OA1P_A43__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A22__OFFSET +CYFLD_CTBM_OA1M_A22__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A22__SIZE +CYFLD_CTBM_OA1M_A22__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A82__OFFSET +CYFLD_CTBM_OA1M_A82__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A82__SIZE +CYFLD_CTBM_OA1M_A82__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52__OFFSET +CYFLD_CTBM_OA1O_D52__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52__SIZE +CYFLD_CTBM_OA1O_D52__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62__OFFSET +CYFLD_CTBM_OA1O_D62__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62__SIZE +CYFLD_CTBM_OA1O_D62__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D82__OFFSET +CYFLD_CTBM_OA1O_D82__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D82__SIZE +CYFLD_CTBM_OA1O_D82__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_SW_CLEAR +CYREG_CTBM_OA1_SW_CLEAR EQU 0x4010008c + ENDIF + IF :LNOT::DEF:CYREG_CTBM_CTB_SW_HW_CTRL +CYREG_CTBM_CTB_SW_HW_CTRL EQU 0x401000c0 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P2_HW_CTRL__OFFSET +CYFLD_CTBM_P2_HW_CTRL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P2_HW_CTRL__SIZE +CYFLD_CTBM_P2_HW_CTRL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P3_HW_CTRL__OFFSET +CYFLD_CTBM_P3_HW_CTRL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P3_HW_CTRL__SIZE +CYFLD_CTBM_P3_HW_CTRL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_CTB_SW_STATUS +CYREG_CTBM_CTB_SW_STATUS EQU 0x401000c4 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51_STAT__OFFSET +CYFLD_CTBM_OA0O_D51_STAT__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51_STAT__SIZE +CYFLD_CTBM_OA0O_D51_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52_STAT__OFFSET +CYFLD_CTBM_OA1O_D52_STAT__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52_STAT__SIZE +CYFLD_CTBM_OA1O_D52_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62_STAT__OFFSET +CYFLD_CTBM_OA1O_D62_STAT__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62_STAT__SIZE +CYFLD_CTBM_OA1O_D62_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_OFFSET_TRIM +CYREG_CTBM_OA0_OFFSET_TRIM EQU 0x40100f00 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM +CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM EQU 0x40100f04 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_COMP_TRIM +CYREG_CTBM_OA0_COMP_TRIM EQU 0x40100f08 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_TRIM__OFFSET +CYFLD_CTBM_OA0_COMP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_TRIM__SIZE +CYFLD_CTBM_OA0_COMP_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_OFFSET_TRIM +CYREG_CTBM_OA1_OFFSET_TRIM EQU 0x40100f0c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM +CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM EQU 0x40100f10 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_COMP_TRIM +CYREG_CTBM_OA1_COMP_TRIM EQU 0x40100f14 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_TRIM__OFFSET +CYFLD_CTBM_OA1_COMP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_TRIM__SIZE +CYFLD_CTBM_OA1_COMP_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SAR_BASE +CYDEV_SAR_BASE EQU 0x401a0000 + ENDIF + IF :LNOT::DEF:CYDEV_SAR_SIZE +CYDEV_SAR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CTRL +CYREG_SAR_CTRL EQU 0x401a0000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_SEL__OFFSET +CYFLD_SAR_VREF_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_SEL__SIZE +CYFLD_SAR_VREF_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF0 +CYVAL_SAR_VREF_SEL_VREF0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF1 +CYVAL_SAR_VREF_SEL_VREF1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF2 +CYVAL_SAR_VREF_SEL_VREF2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF_AROUTE +CYVAL_SAR_VREF_SEL_VREF_AROUTE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VBGR +CYVAL_SAR_VREF_SEL_VBGR EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF_EXT +CYVAL_SAR_VREF_SEL_VREF_EXT EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VDDA_DIV_2 +CYVAL_SAR_VREF_SEL_VDDA_DIV_2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VDDA +CYVAL_SAR_VREF_SEL_VDDA EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET +CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_BYP_CAP_EN__SIZE +CYFLD_SAR_VREF_BYP_CAP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_NEG_SEL__OFFSET +CYFLD_SAR_NEG_SEL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_NEG_SEL__SIZE +CYFLD_SAR_NEG_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_VSSA_KELVIN +CYVAL_SAR_NEG_SEL_VSSA_KELVIN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_ART_VSSA +CYVAL_SAR_NEG_SEL_ART_VSSA EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P1 +CYVAL_SAR_NEG_SEL_P1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P3 +CYVAL_SAR_NEG_SEL_P3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P5 +CYVAL_SAR_NEG_SEL_P5 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P7 +CYVAL_SAR_NEG_SEL_P7 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_ACORE +CYVAL_SAR_NEG_SEL_ACORE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_VREF +CYVAL_SAR_NEG_SEL_VREF EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET +CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE +CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PWR_CTRL_VREF__OFFSET +CYFLD_SAR_PWR_CTRL_VREF__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PWR_CTRL_VREF__SIZE +CYFLD_SAR_PWR_CTRL_VREF__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR +CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR +CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR +CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR +CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SPARE__OFFSET +CYFLD_SAR_SPARE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SPARE__SIZE +CYFLD_SAR_SPARE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ICONT_LV__OFFSET +CYFLD_SAR_ICONT_LV__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ICONT_LV__SIZE +CYFLD_SAR_ICONT_LV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_NORMAL_PWR +CYVAL_SAR_ICONT_LV_NORMAL_PWR EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_HALF_PWR +CYVAL_SAR_ICONT_LV_HALF_PWR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_MORE_PWR +CYVAL_SAR_ICONT_LV_MORE_PWR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_QUARTER_PWR +CYVAL_SAR_ICONT_LV_QUARTER_PWR EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET +CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_CONFIG__SIZE +CYFLD_SAR_DSI_SYNC_CONFIG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_MODE__OFFSET +CYFLD_SAR_DSI_MODE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_MODE__SIZE +CYFLD_SAR_DSI_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SWITCH_DISABLE__OFFSET +CYFLD_SAR_SWITCH_DISABLE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SWITCH_DISABLE__SIZE +CYFLD_SAR_SWITCH_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ENABLED__OFFSET +CYFLD_SAR_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ENABLED__SIZE +CYFLD_SAR_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_CTRL +CYREG_SAR_SAMPLE_CTRL EQU 0x401a0004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SUB_RESOLUTION__OFFSET +CYFLD_SAR_SUB_RESOLUTION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SUB_RESOLUTION__SIZE +CYFLD_SAR_SUB_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SUB_RESOLUTION_8B +CYVAL_SAR_SUB_RESOLUTION_8B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SUB_RESOLUTION_10B +CYVAL_SAR_SUB_RESOLUTION_10B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_LEFT_ALIGN__OFFSET +CYFLD_SAR_LEFT_ALIGN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_LEFT_ALIGN__SIZE +CYFLD_SAR_LEFT_ALIGN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET +CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE +CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED +CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED +CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET +CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE +CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED +CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED +CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_CNT__OFFSET +CYFLD_SAR_AVG_CNT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_CNT__SIZE +CYFLD_SAR_AVG_CNT__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_SHIFT__OFFSET +CYFLD_SAR_AVG_SHIFT__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_SHIFT__SIZE +CYFLD_SAR_AVG_SHIFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CONTINUOUS__OFFSET +CYFLD_SAR_CONTINUOUS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CONTINUOUS__SIZE +CYFLD_SAR_CONTINUOUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_EN__OFFSET +CYFLD_SAR_DSI_TRIGGER_EN__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_EN__SIZE +CYFLD_SAR_DSI_TRIGGER_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET +CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE +CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET +CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE +CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET +CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_DSI_OUT_EN__SIZE +CYFLD_SAR_EOS_DSI_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_TIME01 +CYREG_SAR_SAMPLE_TIME01 EQU 0x401a0010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME0__OFFSET +CYFLD_SAR_SAMPLE_TIME0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME0__SIZE +CYFLD_SAR_SAMPLE_TIME0__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME1__OFFSET +CYFLD_SAR_SAMPLE_TIME1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME1__SIZE +CYFLD_SAR_SAMPLE_TIME1__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_TIME23 +CYREG_SAR_SAMPLE_TIME23 EQU 0x401a0014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME2__OFFSET +CYFLD_SAR_SAMPLE_TIME2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME2__SIZE +CYFLD_SAR_SAMPLE_TIME2__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME3__OFFSET +CYFLD_SAR_SAMPLE_TIME3__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME3__SIZE +CYFLD_SAR_SAMPLE_TIME3__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_THRES +CYREG_SAR_RANGE_THRES EQU 0x401a0018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_LOW__OFFSET +CYFLD_SAR_RANGE_LOW__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_LOW__SIZE +CYFLD_SAR_RANGE_LOW__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_HIGH__OFFSET +CYFLD_SAR_RANGE_HIGH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_HIGH__SIZE +CYFLD_SAR_RANGE_HIGH__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_COND +CYREG_SAR_RANGE_COND EQU 0x401a001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_COND__OFFSET +CYFLD_SAR_RANGE_COND__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_COND__SIZE +CYFLD_SAR_RANGE_COND__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_BELOW +CYVAL_SAR_RANGE_COND_BELOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_INSIDE +CYVAL_SAR_RANGE_COND_INSIDE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_ABOVE +CYVAL_SAR_RANGE_COND_ABOVE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_OUTSIDE +CYVAL_SAR_RANGE_COND_OUTSIDE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_EN +CYREG_SAR_CHAN_EN EQU 0x401a0020 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_EN__OFFSET +CYFLD_SAR_CHAN_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_EN__SIZE +CYFLD_SAR_CHAN_EN__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_START_CTRL +CYREG_SAR_START_CTRL EQU 0x401a0024 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_TRIGGER__OFFSET +CYFLD_SAR_FW_TRIGGER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_TRIGGER__SIZE +CYFLD_SAR_FW_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_DFT_CTRL +CYREG_SAR_DFT_CTRL EQU 0x401a0030 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DLY_INC__OFFSET +CYFLD_SAR_DLY_INC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DLY_INC__SIZE +CYFLD_SAR_DLY_INC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_HIZ__OFFSET +CYFLD_SAR_HIZ__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_HIZ__SIZE +CYFLD_SAR_HIZ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_INC__OFFSET +CYFLD_SAR_DFT_INC__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_INC__SIZE +CYFLD_SAR_DFT_INC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_OUTC__OFFSET +CYFLD_SAR_DFT_OUTC__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_OUTC__SIZE +CYFLD_SAR_DFT_OUTC__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SEL_CSEL_DFT__OFFSET +CYFLD_SAR_SEL_CSEL_DFT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SEL_CSEL_DFT__SIZE +CYFLD_SAR_SEL_CSEL_DFT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EN_CSEL_DFT__OFFSET +CYFLD_SAR_EN_CSEL_DFT__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EN_CSEL_DFT__SIZE +CYFLD_SAR_EN_CSEL_DFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DCEN__OFFSET +CYFLD_SAR_DCEN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DCEN__SIZE +CYFLD_SAR_DCEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ADFT_OVERRIDE__OFFSET +CYFLD_SAR_ADFT_OVERRIDE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ADFT_OVERRIDE__SIZE +CYFLD_SAR_ADFT_OVERRIDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG00 +CYREG_SAR_CHAN_CONFIG00 EQU 0x401a0080 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PIN_ADDR__OFFSET +CYFLD_SAR_PIN_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PIN_ADDR__SIZE +CYFLD_SAR_PIN_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PORT_ADDR__OFFSET +CYFLD_SAR_PORT_ADDR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PORT_ADDR__SIZE +CYFLD_SAR_PORT_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_SARMUX +CYVAL_SAR_PORT_ADDR_SARMUX EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB0 +CYVAL_SAR_PORT_ADDR_CTB0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB1 +CYVAL_SAR_PORT_ADDR_CTB1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB2 +CYVAL_SAR_PORT_ADDR_CTB2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB3 +CYVAL_SAR_PORT_ADDR_CTB3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_AROUTE_VIRT +CYVAL_SAR_PORT_ADDR_AROUTE_VIRT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_SARMUX_VIRT +CYVAL_SAR_PORT_ADDR_SARMUX_VIRT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_EN__OFFSET +CYFLD_SAR_DIFFERENTIAL_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_EN__SIZE +CYFLD_SAR_DIFFERENTIAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESOLUTION__OFFSET +CYFLD_SAR_RESOLUTION__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESOLUTION__SIZE +CYFLD_SAR_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RESOLUTION_12B +CYVAL_SAR_RESOLUTION_12B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RESOLUTION_SUBRES +CYVAL_SAR_RESOLUTION_SUBRES EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_EN__OFFSET +CYFLD_SAR_AVG_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_EN__SIZE +CYFLD_SAR_AVG_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET +CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME_SEL__SIZE +CYFLD_SAR_SAMPLE_TIME_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_OUT_EN__OFFSET +CYFLD_SAR_DSI_OUT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_OUT_EN__SIZE +CYFLD_SAR_DSI_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG01 +CYREG_SAR_CHAN_CONFIG01 EQU 0x401a0084 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG02 +CYREG_SAR_CHAN_CONFIG02 EQU 0x401a0088 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG03 +CYREG_SAR_CHAN_CONFIG03 EQU 0x401a008c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG04 +CYREG_SAR_CHAN_CONFIG04 EQU 0x401a0090 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG05 +CYREG_SAR_CHAN_CONFIG05 EQU 0x401a0094 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG06 +CYREG_SAR_CHAN_CONFIG06 EQU 0x401a0098 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG07 +CYREG_SAR_CHAN_CONFIG07 EQU 0x401a009c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK00 +CYREG_SAR_CHAN_WORK00 EQU 0x401a0100 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WORK__OFFSET +CYFLD_SAR_WORK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WORK__SIZE +CYFLD_SAR_WORK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET +CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE +CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK01 +CYREG_SAR_CHAN_WORK01 EQU 0x401a0104 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK02 +CYREG_SAR_CHAN_WORK02 EQU 0x401a0108 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK03 +CYREG_SAR_CHAN_WORK03 EQU 0x401a010c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK04 +CYREG_SAR_CHAN_WORK04 EQU 0x401a0110 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK05 +CYREG_SAR_CHAN_WORK05 EQU 0x401a0114 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK06 +CYREG_SAR_CHAN_WORK06 EQU 0x401a0118 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK07 +CYREG_SAR_CHAN_WORK07 EQU 0x401a011c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT00 +CYREG_SAR_CHAN_RESULT00 EQU 0x401a0180 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESULT__OFFSET +CYFLD_SAR_RESULT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESULT__SIZE +CYFLD_SAR_RESULT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR_MIR__OFFSET +CYFLD_SAR_SATURATE_INTR_MIR__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR_MIR__SIZE +CYFLD_SAR_SATURATE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR_MIR__OFFSET +CYFLD_SAR_RANGE_INTR_MIR__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR_MIR__SIZE +CYFLD_SAR_RANGE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET +CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE +CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT01 +CYREG_SAR_CHAN_RESULT01 EQU 0x401a0184 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT02 +CYREG_SAR_CHAN_RESULT02 EQU 0x401a0188 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT03 +CYREG_SAR_CHAN_RESULT03 EQU 0x401a018c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT04 +CYREG_SAR_CHAN_RESULT04 EQU 0x401a0190 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT05 +CYREG_SAR_CHAN_RESULT05 EQU 0x401a0194 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT06 +CYREG_SAR_CHAN_RESULT06 EQU 0x401a0198 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT07 +CYREG_SAR_CHAN_RESULT07 EQU 0x401a019c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK_VALID +CYREG_SAR_CHAN_WORK_VALID EQU 0x401a0200 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID__OFFSET +CYFLD_SAR_CHAN_WORK_VALID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID__SIZE +CYFLD_SAR_CHAN_WORK_VALID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT_VALID +CYREG_SAR_CHAN_RESULT_VALID EQU 0x401a0204 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID__OFFSET +CYFLD_SAR_CHAN_RESULT_VALID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID__SIZE +CYFLD_SAR_CHAN_RESULT_VALID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_STATUS +CYREG_SAR_STATUS EQU 0x401a0208 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_CHAN__OFFSET +CYFLD_SAR_CUR_CHAN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_CHAN__SIZE +CYFLD_SAR_CUR_CHAN__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SW_VREF_NEG__OFFSET +CYFLD_SAR_SW_VREF_NEG__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SW_VREF_NEG__SIZE +CYFLD_SAR_SW_VREF_NEG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BUSY__OFFSET +CYFLD_SAR_BUSY__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BUSY__SIZE +CYFLD_SAR_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_AVG_STAT +CYREG_SAR_AVG_STAT EQU 0x401a020c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_ACCU__OFFSET +CYFLD_SAR_CUR_AVG_ACCU__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_ACCU__SIZE +CYFLD_SAR_CUR_AVG_ACCU__SIZE EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_CNT__OFFSET +CYFLD_SAR_CUR_AVG_CNT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_CNT__SIZE +CYFLD_SAR_CUR_AVG_CNT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR +CYREG_SAR_INTR EQU 0x401a0210 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_INTR__OFFSET +CYFLD_SAR_EOS_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_INTR__SIZE +CYFLD_SAR_EOS_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_INTR__OFFSET +CYFLD_SAR_OVERFLOW_INTR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_INTR__SIZE +CYFLD_SAR_OVERFLOW_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_INTR__OFFSET +CYFLD_SAR_FW_COLLISION_INTR__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_INTR__SIZE +CYFLD_SAR_FW_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_INTR__OFFSET +CYFLD_SAR_DSI_COLLISION_INTR__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_INTR__SIZE +CYFLD_SAR_DSI_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR__OFFSET +CYFLD_SAR_INJ_EOC_INTR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR__SIZE +CYFLD_SAR_INJ_EOC_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR__OFFSET +CYFLD_SAR_INJ_SATURATE_INTR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR__SIZE +CYFLD_SAR_INJ_SATURATE_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR__OFFSET +CYFLD_SAR_INJ_RANGE_INTR__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR__SIZE +CYFLD_SAR_INJ_RANGE_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR__OFFSET +CYFLD_SAR_INJ_COLLISION_INTR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR__SIZE +CYFLD_SAR_INJ_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_SET +CYREG_SAR_INTR_SET EQU 0x401a0214 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_SET__OFFSET +CYFLD_SAR_EOS_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_SET__SIZE +CYFLD_SAR_EOS_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_SET__OFFSET +CYFLD_SAR_OVERFLOW_SET__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_SET__SIZE +CYFLD_SAR_OVERFLOW_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_SET__OFFSET +CYFLD_SAR_FW_COLLISION_SET__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_SET__SIZE +CYFLD_SAR_FW_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_SET__OFFSET +CYFLD_SAR_DSI_COLLISION_SET__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_SET__SIZE +CYFLD_SAR_DSI_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_SET__OFFSET +CYFLD_SAR_INJ_EOC_SET__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_SET__SIZE +CYFLD_SAR_INJ_EOC_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_SET__OFFSET +CYFLD_SAR_INJ_SATURATE_SET__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_SET__SIZE +CYFLD_SAR_INJ_SATURATE_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_SET__OFFSET +CYFLD_SAR_INJ_RANGE_SET__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_SET__SIZE +CYFLD_SAR_INJ_RANGE_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_SET__OFFSET +CYFLD_SAR_INJ_COLLISION_SET__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_SET__SIZE +CYFLD_SAR_INJ_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_MASK +CYREG_SAR_INTR_MASK EQU 0x401a0218 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASK__OFFSET +CYFLD_SAR_EOS_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASK__SIZE +CYFLD_SAR_EOS_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASK__OFFSET +CYFLD_SAR_OVERFLOW_MASK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASK__SIZE +CYFLD_SAR_OVERFLOW_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASK__OFFSET +CYFLD_SAR_FW_COLLISION_MASK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASK__SIZE +CYFLD_SAR_FW_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASK__OFFSET +CYFLD_SAR_DSI_COLLISION_MASK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASK__SIZE +CYFLD_SAR_DSI_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASK__OFFSET +CYFLD_SAR_INJ_EOC_MASK__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASK__SIZE +CYFLD_SAR_INJ_EOC_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASK__OFFSET +CYFLD_SAR_INJ_SATURATE_MASK__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASK__SIZE +CYFLD_SAR_INJ_SATURATE_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASK__OFFSET +CYFLD_SAR_INJ_RANGE_MASK__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASK__SIZE +CYFLD_SAR_INJ_RANGE_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASK__OFFSET +CYFLD_SAR_INJ_COLLISION_MASK__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASK__SIZE +CYFLD_SAR_INJ_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_MASKED +CYREG_SAR_INTR_MASKED EQU 0x401a021c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED__OFFSET +CYFLD_SAR_EOS_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED__SIZE +CYFLD_SAR_EOS_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED__OFFSET +CYFLD_SAR_OVERFLOW_MASKED__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED__SIZE +CYFLD_SAR_OVERFLOW_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED__OFFSET +CYFLD_SAR_FW_COLLISION_MASKED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED__SIZE +CYFLD_SAR_FW_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET +CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED__SIZE +CYFLD_SAR_DSI_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED__OFFSET +CYFLD_SAR_INJ_EOC_MASKED__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED__SIZE +CYFLD_SAR_INJ_EOC_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET +CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED__SIZE +CYFLD_SAR_INJ_SATURATE_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED__OFFSET +CYFLD_SAR_INJ_RANGE_MASKED__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED__SIZE +CYFLD_SAR_INJ_RANGE_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET +CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED__SIZE +CYFLD_SAR_INJ_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR +CYREG_SAR_SATURATE_INTR EQU 0x401a0220 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR__OFFSET +CYFLD_SAR_SATURATE_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR__SIZE +CYFLD_SAR_SATURATE_INTR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_SET +CYREG_SAR_SATURATE_INTR_SET EQU 0x401a0224 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_SET__OFFSET +CYFLD_SAR_SATURATE_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_SET__SIZE +CYFLD_SAR_SATURATE_SET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_MASK +CYREG_SAR_SATURATE_INTR_MASK EQU 0x401a0228 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASK__OFFSET +CYFLD_SAR_SATURATE_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASK__SIZE +CYFLD_SAR_SATURATE_MASK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_MASKED +CYREG_SAR_SATURATE_INTR_MASKED EQU 0x401a022c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED__OFFSET +CYFLD_SAR_SATURATE_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED__SIZE +CYFLD_SAR_SATURATE_MASKED__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR +CYREG_SAR_RANGE_INTR EQU 0x401a0230 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR__OFFSET +CYFLD_SAR_RANGE_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR__SIZE +CYFLD_SAR_RANGE_INTR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_SET +CYREG_SAR_RANGE_INTR_SET EQU 0x401a0234 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_SET__OFFSET +CYFLD_SAR_RANGE_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_SET__SIZE +CYFLD_SAR_RANGE_SET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_MASK +CYREG_SAR_RANGE_INTR_MASK EQU 0x401a0238 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASK__OFFSET +CYFLD_SAR_RANGE_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASK__SIZE +CYFLD_SAR_RANGE_MASK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_MASKED +CYREG_SAR_RANGE_INTR_MASKED EQU 0x401a023c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED__OFFSET +CYFLD_SAR_RANGE_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED__SIZE +CYFLD_SAR_RANGE_MASKED__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_CAUSE +CYREG_SAR_INTR_CAUSE EQU 0x401a0240 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED_MIR__OFFSET +CYFLD_SAR_EOS_MASKED_MIR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED_MIR__SIZE +CYFLD_SAR_EOS_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET +CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE +CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE +CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE +CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE +CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED_RED__OFFSET +CYFLD_SAR_SATURATE_MASKED_RED__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED_RED__SIZE +CYFLD_SAR_SATURATE_MASKED_RED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED_RED__OFFSET +CYFLD_SAR_RANGE_MASKED_RED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED_RED__SIZE +CYFLD_SAR_RANGE_MASKED_RED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INJ_CHAN_CONFIG +CYREG_SAR_INJ_CHAN_CONFIG EQU 0x401a0280 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PIN_ADDR__OFFSET +CYFLD_SAR_INJ_PIN_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PIN_ADDR__SIZE +CYFLD_SAR_INJ_PIN_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PORT_ADDR__OFFSET +CYFLD_SAR_INJ_PORT_ADDR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PORT_ADDR__SIZE +CYFLD_SAR_INJ_PORT_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_SARMUX +CYVAL_SAR_INJ_PORT_ADDR_SARMUX EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB0 +CYVAL_SAR_INJ_PORT_ADDR_CTB0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB1 +CYVAL_SAR_INJ_PORT_ADDR_CTB1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB2 +CYVAL_SAR_INJ_PORT_ADDR_CTB2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB3 +CYVAL_SAR_INJ_PORT_ADDR_CTB3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT +CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT +CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET +CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE +CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESOLUTION__OFFSET +CYFLD_SAR_INJ_RESOLUTION__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESOLUTION__SIZE +CYFLD_SAR_INJ_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_RESOLUTION_12B +CYVAL_SAR_INJ_RESOLUTION_12B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_RESOLUTION_SUBRES +CYVAL_SAR_INJ_RESOLUTION_SUBRES EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_AVG_EN__OFFSET +CYFLD_SAR_INJ_AVG_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_AVG_EN__SIZE +CYFLD_SAR_INJ_AVG_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET +CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE +CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_TAILGATING__OFFSET +CYFLD_SAR_INJ_TAILGATING__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_TAILGATING__SIZE +CYFLD_SAR_INJ_TAILGATING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_START_EN__OFFSET +CYFLD_SAR_INJ_START_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_START_EN__SIZE +CYFLD_SAR_INJ_START_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INJ_RESULT +CYREG_SAR_INJ_RESULT EQU 0x401a0290 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESULT__OFFSET +CYFLD_SAR_INJ_RESULT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESULT__SIZE +CYFLD_SAR_INJ_RESULT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET +CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE +CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET +CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE +CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET +CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE +CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET +CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE +CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH0 +CYREG_SAR_MUX_SWITCH0 EQU 0x401a0300 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE +CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE +CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET +CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE +CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET +CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE +CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET +CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE +CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET +CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE +CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_CLEAR0 +CYREG_SAR_MUX_SWITCH_CLEAR0 EQU 0x401a0304 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH1 +CYREG_SAR_MUX_SWITCH1 EQU 0x401a0308 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET +CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE +CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET +CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE +CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET +CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE +CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET +CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE +CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_CLEAR1 +CYREG_SAR_MUX_SWITCH_CLEAR1 EQU 0x401a030c + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_HW_CTRL +CYREG_SAR_MUX_SWITCH_HW_CTRL EQU 0x401a0340 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P0__SIZE +CYFLD_SAR_MUX_HW_CTRL_P0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P1__SIZE +CYFLD_SAR_MUX_HW_CTRL_P1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P2__SIZE +CYFLD_SAR_MUX_HW_CTRL_P2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P3__SIZE +CYFLD_SAR_MUX_HW_CTRL_P3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P4__SIZE +CYFLD_SAR_MUX_HW_CTRL_P4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P5__SIZE +CYFLD_SAR_MUX_HW_CTRL_P5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P6__SIZE +CYFLD_SAR_MUX_HW_CTRL_P6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P7__SIZE +CYFLD_SAR_MUX_HW_CTRL_P7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET +CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE +CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET +CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE +CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET +CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE +CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET +CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE +CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_STATUS +CYREG_SAR_MUX_SWITCH_STATUS EQU 0x401a0348 + ENDIF + IF :LNOT::DEF:CYREG_SAR_PUMP_CTRL +CYREG_SAR_PUMP_CTRL EQU 0x401a0380 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CLOCK_SEL__OFFSET +CYFLD_SAR_CLOCK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CLOCK_SEL__SIZE +CYFLD_SAR_CLOCK_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_ANA_TRIM +CYREG_SAR_ANA_TRIM EQU 0x401a0f00 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CAP_TRIM__OFFSET +CYFLD_SAR_CAP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CAP_TRIM__SIZE +CYFLD_SAR_CAP_TRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_TRIMUNIT__OFFSET +CYFLD_SAR_TRIMUNIT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_TRIMUNIT__SIZE +CYFLD_SAR_TRIMUNIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_WOUNDING +CYREG_SAR_WOUNDING EQU 0x401a0f04 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WOUND_RESOLUTION__OFFSET +CYFLD_SAR_WOUND_RESOLUTION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WOUND_RESOLUTION__SIZE +CYFLD_SAR_WOUND_RESOLUTION__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_12BIT +CYVAL_SAR_WOUND_RESOLUTION_12BIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_10BIT +CYVAL_SAR_WOUND_RESOLUTION_10BIT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_8BIT +CYVAL_SAR_WOUND_RESOLUTION_8BIT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO +CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CM0_BASE +CYDEV_CM0_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_CM0_SIZE +CYDEV_CM0_SIZE EQU 0x00100000 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID4 +CYREG_CM0_DWT_PID4 EQU 0xe0001fd0 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VALUE__OFFSET +CYFLD_CM0_VALUE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VALUE__SIZE +CYFLD_CM0_VALUE__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID0 +CYREG_CM0_DWT_PID0 EQU 0xe0001fe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID1 +CYREG_CM0_DWT_PID1 EQU 0xe0001fe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID2 +CYREG_CM0_DWT_PID2 EQU 0xe0001fe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID3 +CYREG_CM0_DWT_PID3 EQU 0xe0001fec + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID0 +CYREG_CM0_DWT_CID0 EQU 0xe0001ff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID1 +CYREG_CM0_DWT_CID1 EQU 0xe0001ff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID2 +CYREG_CM0_DWT_CID2 EQU 0xe0001ff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID3 +CYREG_CM0_DWT_CID3 EQU 0xe0001ffc + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID4 +CYREG_CM0_BP_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID0 +CYREG_CM0_BP_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID1 +CYREG_CM0_BP_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID2 +CYREG_CM0_BP_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID3 +CYREG_CM0_BP_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID0 +CYREG_CM0_BP_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID1 +CYREG_CM0_BP_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID2 +CYREG_CM0_BP_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID3 +CYREG_CM0_BP_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_CSR +CYREG_CM0_SYST_CSR EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENABLE__OFFSET +CYFLD_CM0_ENABLE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENABLE__SIZE +CYFLD_CM0_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TICKINT__OFFSET +CYFLD_CM0_TICKINT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TICKINT__SIZE +CYFLD_CM0_TICKINT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLKSOURCE__OFFSET +CYFLD_CM0_CLKSOURCE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLKSOURCE__SIZE +CYFLD_CM0_CLKSOURCE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_COUNTFLAG__OFFSET +CYFLD_CM0_COUNTFLAG__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_COUNTFLAG__SIZE +CYFLD_CM0_COUNTFLAG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_RVR +CYREG_CM0_SYST_RVR EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_RELOAD__OFFSET +CYFLD_CM0_RELOAD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_RELOAD__SIZE +CYFLD_CM0_RELOAD__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_CVR +CYREG_CM0_SYST_CVR EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CURRENT__OFFSET +CYFLD_CM0_CURRENT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CURRENT__SIZE +CYFLD_CM0_CURRENT__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_CALIB +CYREG_CM0_SYST_CALIB EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TENMS__OFFSET +CYFLD_CM0_TENMS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TENMS__SIZE +CYFLD_CM0_TENMS__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SKEW__OFFSET +CYFLD_CM0_SKEW__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SKEW__SIZE +CYFLD_CM0_SKEW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NOREF__OFFSET +CYFLD_CM0_NOREF__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NOREF__SIZE +CYFLD_CM0_NOREF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ISER +CYREG_CM0_ISER EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETENA__OFFSET +CYFLD_CM0_SETENA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETENA__SIZE +CYFLD_CM0_SETENA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ICER +CYREG_CM0_ICER EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRENA__OFFSET +CYFLD_CM0_CLRENA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRENA__SIZE +CYFLD_CM0_CLRENA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ISPR +CYREG_CM0_ISPR EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETPEND__OFFSET +CYFLD_CM0_SETPEND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETPEND__SIZE +CYFLD_CM0_SETPEND__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ICPR +CYREG_CM0_ICPR EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRPEND__OFFSET +CYFLD_CM0_CLRPEND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRPEND__SIZE +CYFLD_CM0_CLRPEND__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR0 +CYREG_CM0_IPR0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N0__OFFSET +CYFLD_CM0_PRI_N0__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N0__SIZE +CYFLD_CM0_PRI_N0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N1__OFFSET +CYFLD_CM0_PRI_N1__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N1__SIZE +CYFLD_CM0_PRI_N1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N2__OFFSET +CYFLD_CM0_PRI_N2__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N2__SIZE +CYFLD_CM0_PRI_N2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N3__OFFSET +CYFLD_CM0_PRI_N3__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N3__SIZE +CYFLD_CM0_PRI_N3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR1 +CYREG_CM0_IPR1 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR2 +CYREG_CM0_IPR2 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR3 +CYREG_CM0_IPR3 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR4 +CYREG_CM0_IPR4 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR5 +CYREG_CM0_IPR5 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR6 +CYREG_CM0_IPR6 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR7 +CYREG_CM0_IPR7 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_CM0_CPUID +CYREG_CM0_CPUID EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_REVISION__OFFSET +CYFLD_CM0_REVISION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_REVISION__SIZE +CYFLD_CM0_REVISION__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PARTNO__OFFSET +CYFLD_CM0_PARTNO__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PARTNO__SIZE +CYFLD_CM0_PARTNO__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CONSTANT__OFFSET +CYFLD_CM0_CONSTANT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CONSTANT__SIZE +CYFLD_CM0_CONSTANT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VARIANT__OFFSET +CYFLD_CM0_VARIANT__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VARIANT__SIZE +CYFLD_CM0_VARIANT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_IMPLEMENTER__OFFSET +CYFLD_CM0_IMPLEMENTER__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_IMPLEMENTER__SIZE +CYFLD_CM0_IMPLEMENTER__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ICSR +CYREG_CM0_ICSR EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTACTIVE__OFFSET +CYFLD_CM0_VECTACTIVE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTACTIVE__SIZE +CYFLD_CM0_VECTACTIVE__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTPENDING__OFFSET +CYFLD_CM0_VECTPENDING__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTPENDING__SIZE +CYFLD_CM0_VECTPENDING__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPENDING__OFFSET +CYFLD_CM0_ISRPENDING__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPENDING__SIZE +CYFLD_CM0_ISRPENDING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPREEMPT__OFFSET +CYFLD_CM0_ISRPREEMPT__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPREEMPT__SIZE +CYFLD_CM0_ISRPREEMPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTCLR__OFFSET +CYFLD_CM0_PENDSTCLR__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTCLR__SIZE +CYFLD_CM0_PENDSTCLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTSETb__OFFSET +CYFLD_CM0_PENDSTSETb__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTSETb__SIZE +CYFLD_CM0_PENDSTSETb__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVCLR__OFFSET +CYFLD_CM0_PENDSVCLR__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVCLR__SIZE +CYFLD_CM0_PENDSVCLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVSET__OFFSET +CYFLD_CM0_PENDSVSET__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVSET__SIZE +CYFLD_CM0_PENDSVSET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NMIPENDSET__OFFSET +CYFLD_CM0_NMIPENDSET__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NMIPENDSET__SIZE +CYFLD_CM0_NMIPENDSET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_AIRCR +CYREG_CM0_AIRCR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTCLRACTIVE__OFFSET +CYFLD_CM0_VECTCLRACTIVE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTCLRACTIVE__SIZE +CYFLD_CM0_VECTCLRACTIVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SYSRESETREQ__OFFSET +CYFLD_CM0_SYSRESETREQ__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SYSRESETREQ__SIZE +CYFLD_CM0_SYSRESETREQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENDIANNESS__OFFSET +CYFLD_CM0_ENDIANNESS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENDIANNESS__SIZE +CYFLD_CM0_ENDIANNESS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTKEY__OFFSET +CYFLD_CM0_VECTKEY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTKEY__SIZE +CYFLD_CM0_VECTKEY__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCR +CYREG_CM0_SCR EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPONEXIT__OFFSET +CYFLD_CM0_SLEEPONEXIT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPONEXIT__SIZE +CYFLD_CM0_SLEEPONEXIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPDEEP__OFFSET +CYFLD_CM0_SLEEPDEEP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPDEEP__SIZE +CYFLD_CM0_SLEEPDEEP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SEVONPEND__OFFSET +CYFLD_CM0_SEVONPEND__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SEVONPEND__SIZE +CYFLD_CM0_SEVONPEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_CCR +CYREG_CM0_CCR EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_UNALIGN_TRP__OFFSET +CYFLD_CM0_UNALIGN_TRP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_UNALIGN_TRP__SIZE +CYFLD_CM0_UNALIGN_TRP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_STKALIGN__OFFSET +CYFLD_CM0_STKALIGN__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_STKALIGN__SIZE +CYFLD_CM0_STKALIGN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SHPR2 +CYREG_CM0_SHPR2 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_11__OFFSET +CYFLD_CM0_PRI_11__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_11__SIZE +CYFLD_CM0_PRI_11__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SHPR3 +CYREG_CM0_SHPR3 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_14__OFFSET +CYFLD_CM0_PRI_14__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_14__SIZE +CYFLD_CM0_PRI_14__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_15__OFFSET +CYFLD_CM0_PRI_15__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_15__SIZE +CYFLD_CM0_PRI_15__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SHCSR +CYREG_CM0_SHCSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SVCALLPENDED__OFFSET +CYFLD_CM0_SVCALLPENDED__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SVCALLPENDED__SIZE +CYFLD_CM0_SVCALLPENDED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID4 +CYREG_CM0_SCS_PID4 EQU 0xe000efd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID0 +CYREG_CM0_SCS_PID0 EQU 0xe000efe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID1 +CYREG_CM0_SCS_PID1 EQU 0xe000efe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID2 +CYREG_CM0_SCS_PID2 EQU 0xe000efe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID3 +CYREG_CM0_SCS_PID3 EQU 0xe000efec + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID0 +CYREG_CM0_SCS_CID0 EQU 0xe000eff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID1 +CYREG_CM0_SCS_CID1 EQU 0xe000eff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID2 +CYREG_CM0_SCS_CID2 EQU 0xe000eff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID3 +CYREG_CM0_SCS_CID3 EQU 0xe000effc + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_SCS +CYREG_CM0_ROM_SCS EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_DWT +CYREG_CM0_ROM_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_BPU +CYREG_CM0_ROM_BPU EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_END +CYREG_CM0_ROM_END EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CSMT +CYREG_CM0_ROM_CSMT EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID4 +CYREG_CM0_ROM_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID0 +CYREG_CM0_ROM_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID1 +CYREG_CM0_ROM_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID2 +CYREG_CM0_ROM_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID3 +CYREG_CM0_ROM_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID0 +CYREG_CM0_ROM_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID1 +CYREG_CM0_ROM_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID2 +CYREG_CM0_ROM_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID3 +CYREG_CM0_ROM_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_CoreSightTable_BASE +CYDEV_CoreSightTable_BASE EQU 0xf0000000 + ENDIF + IF :LNOT::DEF:CYDEV_CoreSightTable_SIZE +CYDEV_CoreSightTable_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_CoreSightTable_DATA_MBASE +CYREG_CoreSightTable_DATA_MBASE EQU 0xf0000000 + ENDIF + IF :LNOT::DEF:CYREG_CoreSightTable_DATA_MSIZE +CYREG_CoreSightTable_DATA_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000080 + ENDIF + END diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydisabledsheets.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydisabledsheets.h new file mode 100644 index 0000000..8178873 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter.h new file mode 100644 index 0000000..91fb364 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter.h @@ -0,0 +1,502 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include "cydevice_trm.h" + +/* ADC */ +#define ADC_cy_psoc4_sar__SAR_ANA_TRIM CYREG_SAR_ANA_TRIM +#define ADC_cy_psoc4_sar__SAR_AVG_STAT CYREG_SAR_AVG_STAT +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 CYREG_SAR_CHAN_CONFIG00 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 CYREG_SAR_CHAN_CONFIG01 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 CYREG_SAR_CHAN_CONFIG02 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 CYREG_SAR_CHAN_CONFIG03 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 CYREG_SAR_CHAN_CONFIG04 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 CYREG_SAR_CHAN_CONFIG05 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 CYREG_SAR_CHAN_CONFIG06 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 CYREG_SAR_CHAN_CONFIG07 +#define ADC_cy_psoc4_sar__SAR_CHAN_EN CYREG_SAR_CHAN_EN +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID CYREG_SAR_CHAN_RESULT_VALID +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 CYREG_SAR_CHAN_RESULT00 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 CYREG_SAR_CHAN_RESULT01 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 CYREG_SAR_CHAN_RESULT02 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 CYREG_SAR_CHAN_RESULT03 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 CYREG_SAR_CHAN_RESULT04 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 CYREG_SAR_CHAN_RESULT05 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 CYREG_SAR_CHAN_RESULT06 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 CYREG_SAR_CHAN_RESULT07 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID CYREG_SAR_CHAN_WORK_VALID +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK00 CYREG_SAR_CHAN_WORK00 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK01 CYREG_SAR_CHAN_WORK01 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK02 CYREG_SAR_CHAN_WORK02 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK03 CYREG_SAR_CHAN_WORK03 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK04 CYREG_SAR_CHAN_WORK04 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK05 CYREG_SAR_CHAN_WORK05 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK06 CYREG_SAR_CHAN_WORK06 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK07 CYREG_SAR_CHAN_WORK07 +#define ADC_cy_psoc4_sar__SAR_CTRL CYREG_SAR_CTRL +#define ADC_cy_psoc4_sar__SAR_DFT_CTRL CYREG_SAR_DFT_CTRL +#define ADC_cy_psoc4_sar__SAR_INTR CYREG_SAR_INTR +#define ADC_cy_psoc4_sar__SAR_INTR_CAUSE CYREG_SAR_INTR_CAUSE +#define ADC_cy_psoc4_sar__SAR_INTR_MASK CYREG_SAR_INTR_MASK +#define ADC_cy_psoc4_sar__SAR_INTR_MASKED CYREG_SAR_INTR_MASKED +#define ADC_cy_psoc4_sar__SAR_INTR_SET CYREG_SAR_INTR_SET +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0 CYREG_SAR_MUX_SWITCH_CLEAR0 +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1 CYREG_SAR_MUX_SWITCH_CLEAR1 +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL CYREG_SAR_MUX_SWITCH_HW_CTRL +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS CYREG_SAR_MUX_SWITCH_STATUS +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 CYREG_SAR_MUX_SWITCH0 +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH1 CYREG_SAR_MUX_SWITCH1 +#define ADC_cy_psoc4_sar__SAR_NUMBER 0u +#define ADC_cy_psoc4_sar__SAR_PUMP_CTRL CYREG_SAR_PUMP_CTRL +#define ADC_cy_psoc4_sar__SAR_RANGE_COND CYREG_SAR_RANGE_COND +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR CYREG_SAR_RANGE_INTR +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK CYREG_SAR_RANGE_INTR_MASK +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED CYREG_SAR_RANGE_INTR_MASKED +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET CYREG_SAR_RANGE_INTR_SET +#define ADC_cy_psoc4_sar__SAR_RANGE_THRES CYREG_SAR_RANGE_THRES +#define ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL CYREG_SAR_SAMPLE_CTRL +#define ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 CYREG_SAR_SAMPLE_TIME01 +#define ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 CYREG_SAR_SAMPLE_TIME23 +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR CYREG_SAR_SATURATE_INTR +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK CYREG_SAR_SATURATE_INTR_MASK +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED CYREG_SAR_SATURATE_INTR_MASKED +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET CYREG_SAR_SATURATE_INTR_SET +#define ADC_cy_psoc4_sar__SAR_START_CTRL CYREG_SAR_START_CTRL +#define ADC_cy_psoc4_sar__SAR_STATUS CYREG_SAR_STATUS +#define ADC_cy_psoc4_sar__SAR_WOUNDING CYREG_SAR_WOUNDING +#define ADC_intClock__DIVIDER_MASK 0x0000FFFFu +#define ADC_intClock__ENABLE CYREG_CLK_DIVIDER_A00 +#define ADC_intClock__ENABLE_MASK 0x80000000u +#define ADC_intClock__MASK 0x80000000u +#define ADC_intClock__REGISTER CYREG_CLK_DIVIDER_A00 +#define ADC_IRQ__INTC_CLR_EN_REG CYREG_CM0_ICER +#define ADC_IRQ__INTC_CLR_PD_REG CYREG_CM0_ICPR +#define ADC_IRQ__INTC_MASK 0x4000u +#define ADC_IRQ__INTC_NUMBER 14u +#define ADC_IRQ__INTC_PRIOR_MASK 0xC00000u +#define ADC_IRQ__INTC_PRIOR_NUM 3u +#define ADC_IRQ__INTC_PRIOR_REG CYREG_CM0_IPR3 +#define ADC_IRQ__INTC_SET_EN_REG CYREG_CM0_ISER +#define ADC_IRQ__INTC_SET_PD_REG CYREG_CM0_ISPR + +/* LED */ +#define LED__0__DM__MASK 0x1C0000u +#define LED__0__DM__SHIFT 18u +#define LED__0__DR CYREG_PRT1_DR +#define LED__0__HSIOM CYREG_HSIOM_PORT_SEL1 +#define LED__0__HSIOM_MASK 0x0F000000u +#define LED__0__HSIOM_SHIFT 24u +#define LED__0__INTCFG CYREG_PRT1_INTCFG +#define LED__0__INTSTAT CYREG_PRT1_INTSTAT +#define LED__0__MASK 0x40u +#define LED__0__PA__CFG0 CYREG_UDB_PA1_CFG0 +#define LED__0__PA__CFG1 CYREG_UDB_PA1_CFG1 +#define LED__0__PA__CFG10 CYREG_UDB_PA1_CFG10 +#define LED__0__PA__CFG11 CYREG_UDB_PA1_CFG11 +#define LED__0__PA__CFG12 CYREG_UDB_PA1_CFG12 +#define LED__0__PA__CFG13 CYREG_UDB_PA1_CFG13 +#define LED__0__PA__CFG14 CYREG_UDB_PA1_CFG14 +#define LED__0__PA__CFG2 CYREG_UDB_PA1_CFG2 +#define LED__0__PA__CFG3 CYREG_UDB_PA1_CFG3 +#define LED__0__PA__CFG4 CYREG_UDB_PA1_CFG4 +#define LED__0__PA__CFG5 CYREG_UDB_PA1_CFG5 +#define LED__0__PA__CFG6 CYREG_UDB_PA1_CFG6 +#define LED__0__PA__CFG7 CYREG_UDB_PA1_CFG7 +#define LED__0__PA__CFG8 CYREG_UDB_PA1_CFG8 +#define LED__0__PA__CFG9 CYREG_UDB_PA1_CFG9 +#define LED__0__PC CYREG_PRT1_PC +#define LED__0__PC2 CYREG_PRT1_PC2 +#define LED__0__PORT 1u +#define LED__0__PS CYREG_PRT1_PS +#define LED__0__SHIFT 6u +#define LED__DR CYREG_PRT1_DR +#define LED__INTCFG CYREG_PRT1_INTCFG +#define LED__INTSTAT CYREG_PRT1_INTSTAT +#define LED__MASK 0x40u +#define LED__PA__CFG0 CYREG_UDB_PA1_CFG0 +#define LED__PA__CFG1 CYREG_UDB_PA1_CFG1 +#define LED__PA__CFG10 CYREG_UDB_PA1_CFG10 +#define LED__PA__CFG11 CYREG_UDB_PA1_CFG11 +#define LED__PA__CFG12 CYREG_UDB_PA1_CFG12 +#define LED__PA__CFG13 CYREG_UDB_PA1_CFG13 +#define LED__PA__CFG14 CYREG_UDB_PA1_CFG14 +#define LED__PA__CFG2 CYREG_UDB_PA1_CFG2 +#define LED__PA__CFG3 CYREG_UDB_PA1_CFG3 +#define LED__PA__CFG4 CYREG_UDB_PA1_CFG4 +#define LED__PA__CFG5 CYREG_UDB_PA1_CFG5 +#define LED__PA__CFG6 CYREG_UDB_PA1_CFG6 +#define LED__PA__CFG7 CYREG_UDB_PA1_CFG7 +#define LED__PA__CFG8 CYREG_UDB_PA1_CFG8 +#define LED__PA__CFG9 CYREG_UDB_PA1_CFG9 +#define LED__PC CYREG_PRT1_PC +#define LED__PC2 CYREG_PRT1_PC2 +#define LED__PORT 1u +#define LED__PS CYREG_PRT1_PS +#define LED__SHIFT 6u + +/* UART */ +#define UART_SCB__BIST_CONTROL CYREG_SCB0_BIST_CONTROL +#define UART_SCB__BIST_DATA CYREG_SCB0_BIST_DATA +#define UART_SCB__CTRL CYREG_SCB0_CTRL +#define UART_SCB__EZ_DATA00 CYREG_SCB0_EZ_DATA00 +#define UART_SCB__EZ_DATA01 CYREG_SCB0_EZ_DATA01 +#define UART_SCB__EZ_DATA02 CYREG_SCB0_EZ_DATA02 +#define UART_SCB__EZ_DATA03 CYREG_SCB0_EZ_DATA03 +#define UART_SCB__EZ_DATA04 CYREG_SCB0_EZ_DATA04 +#define UART_SCB__EZ_DATA05 CYREG_SCB0_EZ_DATA05 +#define UART_SCB__EZ_DATA06 CYREG_SCB0_EZ_DATA06 +#define UART_SCB__EZ_DATA07 CYREG_SCB0_EZ_DATA07 +#define UART_SCB__EZ_DATA08 CYREG_SCB0_EZ_DATA08 +#define UART_SCB__EZ_DATA09 CYREG_SCB0_EZ_DATA09 +#define UART_SCB__EZ_DATA10 CYREG_SCB0_EZ_DATA10 +#define UART_SCB__EZ_DATA11 CYREG_SCB0_EZ_DATA11 +#define UART_SCB__EZ_DATA12 CYREG_SCB0_EZ_DATA12 +#define UART_SCB__EZ_DATA13 CYREG_SCB0_EZ_DATA13 +#define UART_SCB__EZ_DATA14 CYREG_SCB0_EZ_DATA14 +#define UART_SCB__EZ_DATA15 CYREG_SCB0_EZ_DATA15 +#define UART_SCB__EZ_DATA16 CYREG_SCB0_EZ_DATA16 +#define UART_SCB__EZ_DATA17 CYREG_SCB0_EZ_DATA17 +#define UART_SCB__EZ_DATA18 CYREG_SCB0_EZ_DATA18 +#define UART_SCB__EZ_DATA19 CYREG_SCB0_EZ_DATA19 +#define UART_SCB__EZ_DATA20 CYREG_SCB0_EZ_DATA20 +#define UART_SCB__EZ_DATA21 CYREG_SCB0_EZ_DATA21 +#define UART_SCB__EZ_DATA22 CYREG_SCB0_EZ_DATA22 +#define UART_SCB__EZ_DATA23 CYREG_SCB0_EZ_DATA23 +#define UART_SCB__EZ_DATA24 CYREG_SCB0_EZ_DATA24 +#define UART_SCB__EZ_DATA25 CYREG_SCB0_EZ_DATA25 +#define UART_SCB__EZ_DATA26 CYREG_SCB0_EZ_DATA26 +#define UART_SCB__EZ_DATA27 CYREG_SCB0_EZ_DATA27 +#define UART_SCB__EZ_DATA28 CYREG_SCB0_EZ_DATA28 +#define UART_SCB__EZ_DATA29 CYREG_SCB0_EZ_DATA29 +#define UART_SCB__EZ_DATA30 CYREG_SCB0_EZ_DATA30 +#define UART_SCB__EZ_DATA31 CYREG_SCB0_EZ_DATA31 +#define UART_SCB__I2C_CFG CYREG_SCB0_I2C_CFG +#define UART_SCB__I2C_CTRL CYREG_SCB0_I2C_CTRL +#define UART_SCB__I2C_M_CMD CYREG_SCB0_I2C_M_CMD +#define UART_SCB__I2C_S_CMD CYREG_SCB0_I2C_S_CMD +#define UART_SCB__I2C_STATUS CYREG_SCB0_I2C_STATUS +#define UART_SCB__INTR_CAUSE CYREG_SCB0_INTR_CAUSE +#define UART_SCB__INTR_I2C_EC CYREG_SCB0_INTR_I2C_EC +#define UART_SCB__INTR_I2C_EC_MASK CYREG_SCB0_INTR_I2C_EC_MASK +#define UART_SCB__INTR_I2C_EC_MASKED CYREG_SCB0_INTR_I2C_EC_MASKED +#define UART_SCB__INTR_M CYREG_SCB0_INTR_M +#define UART_SCB__INTR_M_MASK CYREG_SCB0_INTR_M_MASK +#define UART_SCB__INTR_M_MASKED CYREG_SCB0_INTR_M_MASKED +#define UART_SCB__INTR_M_SET CYREG_SCB0_INTR_M_SET +#define UART_SCB__INTR_RX CYREG_SCB0_INTR_RX +#define UART_SCB__INTR_RX_MASK CYREG_SCB0_INTR_RX_MASK +#define UART_SCB__INTR_RX_MASKED CYREG_SCB0_INTR_RX_MASKED +#define UART_SCB__INTR_RX_SET CYREG_SCB0_INTR_RX_SET +#define UART_SCB__INTR_S CYREG_SCB0_INTR_S +#define UART_SCB__INTR_S_MASK CYREG_SCB0_INTR_S_MASK +#define UART_SCB__INTR_S_MASKED CYREG_SCB0_INTR_S_MASKED +#define UART_SCB__INTR_S_SET CYREG_SCB0_INTR_S_SET +#define UART_SCB__INTR_SPI_EC CYREG_SCB0_INTR_SPI_EC +#define UART_SCB__INTR_SPI_EC_MASK CYREG_SCB0_INTR_SPI_EC_MASK +#define UART_SCB__INTR_SPI_EC_MASKED CYREG_SCB0_INTR_SPI_EC_MASKED +#define UART_SCB__INTR_TX CYREG_SCB0_INTR_TX +#define UART_SCB__INTR_TX_MASK CYREG_SCB0_INTR_TX_MASK +#define UART_SCB__INTR_TX_MASKED CYREG_SCB0_INTR_TX_MASKED +#define UART_SCB__INTR_TX_SET CYREG_SCB0_INTR_TX_SET +#define UART_SCB__RX_CTRL CYREG_SCB0_RX_CTRL +#define UART_SCB__RX_FIFO_CTRL CYREG_SCB0_RX_FIFO_CTRL +#define UART_SCB__RX_FIFO_RD CYREG_SCB0_RX_FIFO_RD +#define UART_SCB__RX_FIFO_RD_SILENT CYREG_SCB0_RX_FIFO_RD_SILENT +#define UART_SCB__RX_FIFO_STATUS CYREG_SCB0_RX_FIFO_STATUS +#define UART_SCB__RX_MATCH CYREG_SCB0_RX_MATCH +#define UART_SCB__SPI_CTRL CYREG_SCB0_SPI_CTRL +#define UART_SCB__SPI_STATUS CYREG_SCB0_SPI_STATUS +#define UART_SCB__SS0_POSISTION 0u +#define UART_SCB__SS1_POSISTION 1u +#define UART_SCB__SS2_POSISTION 2u +#define UART_SCB__SS3_POSISTION 3u +#define UART_SCB__STATUS CYREG_SCB0_STATUS +#define UART_SCB__TX_CTRL CYREG_SCB0_TX_CTRL +#define UART_SCB__TX_FIFO_CTRL CYREG_SCB0_TX_FIFO_CTRL +#define UART_SCB__TX_FIFO_STATUS CYREG_SCB0_TX_FIFO_STATUS +#define UART_SCB__TX_FIFO_WR CYREG_SCB0_TX_FIFO_WR +#define UART_SCB__UART_CTRL CYREG_SCB0_UART_CTRL +#define UART_SCB__UART_RX_CTRL CYREG_SCB0_UART_RX_CTRL +#define UART_SCB__UART_RX_STATUS CYREG_SCB0_UART_RX_STATUS +#define UART_SCB__UART_TX_CTRL CYREG_SCB0_UART_TX_CTRL +#define UART_SCBCLK__DIVIDER_MASK 0x0000FFFFu +#define UART_SCBCLK__ENABLE CYREG_CLK_DIVIDER_B00 +#define UART_SCBCLK__ENABLE_MASK 0x80000000u +#define UART_SCBCLK__MASK 0x80000000u +#define UART_SCBCLK__REGISTER CYREG_CLK_DIVIDER_B00 +#define UART_tx__0__DM__MASK 0x38u +#define UART_tx__0__DM__SHIFT 3u +#define UART_tx__0__DR CYREG_PRT4_DR +#define UART_tx__0__HSIOM CYREG_HSIOM_PORT_SEL4 +#define UART_tx__0__HSIOM_GPIO 0u +#define UART_tx__0__HSIOM_I2C 14u +#define UART_tx__0__HSIOM_I2C_SDA 14u +#define UART_tx__0__HSIOM_MASK 0x000000F0u +#define UART_tx__0__HSIOM_SHIFT 4u +#define UART_tx__0__HSIOM_SPI 15u +#define UART_tx__0__HSIOM_SPI_MISO 15u +#define UART_tx__0__HSIOM_UART 9u +#define UART_tx__0__HSIOM_UART_TX 9u +#define UART_tx__0__INTCFG CYREG_PRT4_INTCFG +#define UART_tx__0__INTSTAT CYREG_PRT4_INTSTAT +#define UART_tx__0__MASK 0x02u +#define UART_tx__0__PC CYREG_PRT4_PC +#define UART_tx__0__PC2 CYREG_PRT4_PC2 +#define UART_tx__0__PORT 4u +#define UART_tx__0__PS CYREG_PRT4_PS +#define UART_tx__0__SHIFT 1u +#define UART_tx__DR CYREG_PRT4_DR +#define UART_tx__INTCFG CYREG_PRT4_INTCFG +#define UART_tx__INTSTAT CYREG_PRT4_INTSTAT +#define UART_tx__MASK 0x02u +#define UART_tx__PC CYREG_PRT4_PC +#define UART_tx__PC2 CYREG_PRT4_PC2 +#define UART_tx__PORT 4u +#define UART_tx__PS CYREG_PRT4_PS +#define UART_tx__SHIFT 1u + +/* Input_1 */ +#define Input_1__0__DM__MASK 0xE00u +#define Input_1__0__DM__SHIFT 9u +#define Input_1__0__DR CYREG_PRT2_DR +#define Input_1__0__HSIOM CYREG_HSIOM_PORT_SEL2 +#define Input_1__0__HSIOM_MASK 0x0000F000u +#define Input_1__0__HSIOM_SHIFT 12u +#define Input_1__0__INTCFG CYREG_PRT2_INTCFG +#define Input_1__0__INTSTAT CYREG_PRT2_INTSTAT +#define Input_1__0__MASK 0x08u +#define Input_1__0__PA__CFG0 CYREG_UDB_PA2_CFG0 +#define Input_1__0__PA__CFG1 CYREG_UDB_PA2_CFG1 +#define Input_1__0__PA__CFG10 CYREG_UDB_PA2_CFG10 +#define Input_1__0__PA__CFG11 CYREG_UDB_PA2_CFG11 +#define Input_1__0__PA__CFG12 CYREG_UDB_PA2_CFG12 +#define Input_1__0__PA__CFG13 CYREG_UDB_PA2_CFG13 +#define Input_1__0__PA__CFG14 CYREG_UDB_PA2_CFG14 +#define Input_1__0__PA__CFG2 CYREG_UDB_PA2_CFG2 +#define Input_1__0__PA__CFG3 CYREG_UDB_PA2_CFG3 +#define Input_1__0__PA__CFG4 CYREG_UDB_PA2_CFG4 +#define Input_1__0__PA__CFG5 CYREG_UDB_PA2_CFG5 +#define Input_1__0__PA__CFG6 CYREG_UDB_PA2_CFG6 +#define Input_1__0__PA__CFG7 CYREG_UDB_PA2_CFG7 +#define Input_1__0__PA__CFG8 CYREG_UDB_PA2_CFG8 +#define Input_1__0__PA__CFG9 CYREG_UDB_PA2_CFG9 +#define Input_1__0__PC CYREG_PRT2_PC +#define Input_1__0__PC2 CYREG_PRT2_PC2 +#define Input_1__0__PORT 2u +#define Input_1__0__PS CYREG_PRT2_PS +#define Input_1__0__SHIFT 3u +#define Input_1__DR CYREG_PRT2_DR +#define Input_1__INTCFG CYREG_PRT2_INTCFG +#define Input_1__INTSTAT CYREG_PRT2_INTSTAT +#define Input_1__MASK 0x08u +#define Input_1__PA__CFG0 CYREG_UDB_PA2_CFG0 +#define Input_1__PA__CFG1 CYREG_UDB_PA2_CFG1 +#define Input_1__PA__CFG10 CYREG_UDB_PA2_CFG10 +#define Input_1__PA__CFG11 CYREG_UDB_PA2_CFG11 +#define Input_1__PA__CFG12 CYREG_UDB_PA2_CFG12 +#define Input_1__PA__CFG13 CYREG_UDB_PA2_CFG13 +#define Input_1__PA__CFG14 CYREG_UDB_PA2_CFG14 +#define Input_1__PA__CFG2 CYREG_UDB_PA2_CFG2 +#define Input_1__PA__CFG3 CYREG_UDB_PA2_CFG3 +#define Input_1__PA__CFG4 CYREG_UDB_PA2_CFG4 +#define Input_1__PA__CFG5 CYREG_UDB_PA2_CFG5 +#define Input_1__PA__CFG6 CYREG_UDB_PA2_CFG6 +#define Input_1__PA__CFG7 CYREG_UDB_PA2_CFG7 +#define Input_1__PA__CFG8 CYREG_UDB_PA2_CFG8 +#define Input_1__PA__CFG9 CYREG_UDB_PA2_CFG9 +#define Input_1__PC CYREG_PRT2_PC +#define Input_1__PC2 CYREG_PRT2_PC2 +#define Input_1__PORT 2u +#define Input_1__PS CYREG_PRT2_PS +#define Input_1__SHIFT 3u + +/* Miscellaneous */ +#define CY_PROJECT_NAME "ADC-UART" +#define CY_VERSION "PSoC Creator 4.2" +#define CYDEV_BANDGAP_VOLTAGE 1.024 +#define CYDEV_BCLK__HFCLK__HZ 24000000U +#define CYDEV_BCLK__HFCLK__KHZ 24000U +#define CYDEV_BCLK__HFCLK__MHZ 24U +#define CYDEV_BCLK__SYSCLK__HZ 24000000U +#define CYDEV_BCLK__SYSCLK__KHZ 24000U +#define CYDEV_BCLK__SYSCLK__MHZ 24U +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4 +#define CYDEV_CHIP_JTAG_ID 0x04C81193u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4A +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u +#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u +#define CYDEV_CHIP_REV_TMA4_ES 17u +#define CYDEV_CHIP_REV_TMA4_ES2 33u +#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u +#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u +#define CYDEV_CHIP_REVISION_4G_ES 17u +#define CYDEV_CHIP_REVISION_4G_ES2 33u +#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u +#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4A_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED +#define CYDEV_CONFIG_READ_ACCELERATOR 1 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_DEBUG_PROTECT_KILL 4 +#define CYDEV_DEBUG_PROTECT_OPEN 1 +#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN +#define CYDEV_DEBUG_PROTECT_PROTECTED 2 +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DFT_SELECT_CLK0 1u +#define CYDEV_DFT_SELECT_CLK1 2u +#define CYDEV_HEAP_SIZE 0x0100 +#define CYDEV_IMO_TRIMMED_BY_USB 0u +#define CYDEV_IMO_TRIMMED_BY_WCO 0u +#define CYDEV_IS_EXPORTING_CODE 0 +#define CYDEV_IS_IMPORTING_CODE 0 +#define CYDEV_PROJ_TYPE 0 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LAUNCHER 5 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_STACK_SIZE 0x0400 +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5.0 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5.0 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_WDT_GENERATE_ISR 0u +#define CYIPBLOCK_M0S8_CTBM_VERSION 0 +#define CYIPBLOCK_m0s8cpuss_VERSION 0 +#define CYIPBLOCK_m0s8csd_VERSION 0 +#define CYIPBLOCK_m0s8gpio2_VERSION 0 +#define CYIPBLOCK_m0s8hsiom4a_VERSION 0 +#define CYIPBLOCK_m0s8lcd_VERSION 0 +#define CYIPBLOCK_m0s8lpcomp_VERSION 0 +#define CYIPBLOCK_m0s8pclk_VERSION 0 +#define CYIPBLOCK_m0s8sar_VERSION 0 +#define CYIPBLOCK_m0s8scb_VERSION 0 +#define CYIPBLOCK_m0s8srssv2_VERSION 1 +#define CYIPBLOCK_m0s8tcpwm_VERSION 0 +#define CYIPBLOCK_m0s8udbif_VERSION 0 +#define CYIPBLOCK_S8_GPIO_VERSION 2 +#define CYDEV_BOOTLOADER_ENABLE 0 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter_cfg.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter_cfg.c new file mode 100644 index 0000000..02d1175 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter_cfg.c @@ -0,0 +1,315 @@ + +/******************************************************************************* +* File Name: cyfitter_cfg.c +* +* PSoC Creator 4.2 +* +* Description: +* This file contains device initialization code. +* Except for the user defined sections in CyClockStartupError(), this file should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" +#include "cyfitter_cfg.h" +#include "cyapicallbacks.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #ifndef CY_CFG_SECTION + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #endif + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u + + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* `#START CyClockStartupError` */ + + + + /* `#END` */ + + while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +} +#endif + + + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +CY_CFG_SECTION +static void ClockSetup(void) +{ + /* Enable HALF_EN before trimming for the flash accelerator. */ + CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u)); + + /* Setup and trim IMO based on desired frequency. */ + CySysClkWriteImoFreq(24u); + + /* Disable HALF_EN since it is not required at this IMO frequency. */ + CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu)); + /* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */ + CY_SET_REG32((void *)(CYREG_CLK_ILO_CONFIG), 0x80000006u); + + + /* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */ + CY_SET_REG32((void *)(CYREG_CLK_SELECT02), 0x00000020u); + CY_SET_REG32((void *)(CYREG_CLK_SELECT07), 0x00000010u); + + /* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */ + CY_SET_REG32((void *)(CYREG_CLK_IMO_CONFIG), 0x82000000u); + + /* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */ + CY_SET_REG32((void *)(CYREG_CLK_SELECT), 0x00000000u); + + /* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */ + CY_SET_REG32((void *)(CYREG_CLK_DIVIDER_A00), 0x80000017u); + + /* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */ + CY_SET_REG32((void *)(CYREG_CLK_DIVIDER_B00), 0x80000138u); + + CY_SET_REG32((void *)(CYREG_WDT_CONFIG), 0x00000000u); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + CY_SET_XTND_REG32((void CYFAR *)CYREG_SAR_MUX_SWITCH0, 0x00000008u); +} + + + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_SECTION +void cyfitter_cfg(void) +{ + /* Disable interrupts by default. Let user enable if/when they want. */ + CyGlobalIntDisable; + + { + + CYPACKED typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED_ATTR cfg_memset_t; + + static const cfg_memset_t CYCODE cfg_memset_list[] = { + /* address, size */ + {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, + {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); + } + + /* HSIOM Starting address: CYDEV_HSIOM_BASE */ + CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); + CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL4), 0x00000090u); + + /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ + CY_SET_REG32((void *)(CYDEV_UDB_PA1_BASE), 0x00990000u); + + /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ + CY_SET_REG32((void *)(CYDEV_UDB_PA2_BASE), 0x00990000u); + + /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ + CY_SET_REG32((void *)(CYDEV_UDB_PA3_BASE), 0x00990000u); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u)); + } + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + /* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */ + CY_SET_REG32((void *)(CYDEV_PRT1_BASE), 0x00000040u); + CY_SET_REG32((void *)(CYREG_PRT1_PC), 0x00100000u); + + /* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */ + CY_SET_REG32((void *)(CYDEV_PRT2_BASE), 0x00000008u); + CY_SET_REG32((void *)(CYREG_PRT2_PC2), 0x00000008u); + + /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ + CY_SET_REG32((void *)(CYREG_PRT3_PC), 0x00000D80u); + + /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ + CY_SET_REG32((void *)(CYDEV_PRT4_BASE), 0x00000002u); + CY_SET_REG32((void *)(CYREG_PRT4_PC), 0x00000030u); + CY_SET_REG32((void *)(CYREG_PRT4_PC2), 0x00000002u); + + + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + +} diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter_cfg.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter_cfg.h new file mode 100644 index 0000000..c5ca4c7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitter_cfg.h @@ -0,0 +1,29 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides basic startup and mux configuration settings +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include "cytypes.h" + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfittergnu.inc b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfittergnu.inc new file mode 100644 index 0000000..98e67a6 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfittergnu.inc @@ -0,0 +1,496 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu_trm.inc" + +/* ADC */ +.set ADC_cy_psoc4_sar__SAR_ANA_TRIM, CYREG_SAR_ANA_TRIM +.set ADC_cy_psoc4_sar__SAR_AVG_STAT, CYREG_SAR_AVG_STAT +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00, CYREG_SAR_CHAN_CONFIG00 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01, CYREG_SAR_CHAN_CONFIG01 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02, CYREG_SAR_CHAN_CONFIG02 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03, CYREG_SAR_CHAN_CONFIG03 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04, CYREG_SAR_CHAN_CONFIG04 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05, CYREG_SAR_CHAN_CONFIG05 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06, CYREG_SAR_CHAN_CONFIG06 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07, CYREG_SAR_CHAN_CONFIG07 +.set ADC_cy_psoc4_sar__SAR_CHAN_EN, CYREG_SAR_CHAN_EN +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID, CYREG_SAR_CHAN_RESULT_VALID +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT00, CYREG_SAR_CHAN_RESULT00 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT01, CYREG_SAR_CHAN_RESULT01 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT02, CYREG_SAR_CHAN_RESULT02 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT03, CYREG_SAR_CHAN_RESULT03 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT04, CYREG_SAR_CHAN_RESULT04 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT05, CYREG_SAR_CHAN_RESULT05 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT06, CYREG_SAR_CHAN_RESULT06 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT07, CYREG_SAR_CHAN_RESULT07 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID, CYREG_SAR_CHAN_WORK_VALID +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK00, CYREG_SAR_CHAN_WORK00 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK01, CYREG_SAR_CHAN_WORK01 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK02, CYREG_SAR_CHAN_WORK02 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK03, CYREG_SAR_CHAN_WORK03 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK04, CYREG_SAR_CHAN_WORK04 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK05, CYREG_SAR_CHAN_WORK05 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK06, CYREG_SAR_CHAN_WORK06 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK07, CYREG_SAR_CHAN_WORK07 +.set ADC_cy_psoc4_sar__SAR_CTRL, CYREG_SAR_CTRL +.set ADC_cy_psoc4_sar__SAR_DFT_CTRL, CYREG_SAR_DFT_CTRL +.set ADC_cy_psoc4_sar__SAR_INTR, CYREG_SAR_INTR +.set ADC_cy_psoc4_sar__SAR_INTR_CAUSE, CYREG_SAR_INTR_CAUSE +.set ADC_cy_psoc4_sar__SAR_INTR_MASK, CYREG_SAR_INTR_MASK +.set ADC_cy_psoc4_sar__SAR_INTR_MASKED, CYREG_SAR_INTR_MASKED +.set ADC_cy_psoc4_sar__SAR_INTR_SET, CYREG_SAR_INTR_SET +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0, CYREG_SAR_MUX_SWITCH_CLEAR0 +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1, CYREG_SAR_MUX_SWITCH_CLEAR1 +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL, CYREG_SAR_MUX_SWITCH_HW_CTRL +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS, CYREG_SAR_MUX_SWITCH_STATUS +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH0, CYREG_SAR_MUX_SWITCH0 +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH1, CYREG_SAR_MUX_SWITCH1 +.set ADC_cy_psoc4_sar__SAR_NUMBER, 0 +.set ADC_cy_psoc4_sar__SAR_PUMP_CTRL, CYREG_SAR_PUMP_CTRL +.set ADC_cy_psoc4_sar__SAR_RANGE_COND, CYREG_SAR_RANGE_COND +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR, CYREG_SAR_RANGE_INTR +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK, CYREG_SAR_RANGE_INTR_MASK +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED, CYREG_SAR_RANGE_INTR_MASKED +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET, CYREG_SAR_RANGE_INTR_SET +.set ADC_cy_psoc4_sar__SAR_RANGE_THRES, CYREG_SAR_RANGE_THRES +.set ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL, CYREG_SAR_SAMPLE_CTRL +.set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01, CYREG_SAR_SAMPLE_TIME01 +.set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23, CYREG_SAR_SAMPLE_TIME23 +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR, CYREG_SAR_SATURATE_INTR +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK, CYREG_SAR_SATURATE_INTR_MASK +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED, CYREG_SAR_SATURATE_INTR_MASKED +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET, CYREG_SAR_SATURATE_INTR_SET +.set ADC_cy_psoc4_sar__SAR_START_CTRL, CYREG_SAR_START_CTRL +.set ADC_cy_psoc4_sar__SAR_STATUS, CYREG_SAR_STATUS +.set ADC_cy_psoc4_sar__SAR_WOUNDING, CYREG_SAR_WOUNDING +.set ADC_intClock__DIVIDER_MASK, 0x0000FFFF +.set ADC_intClock__ENABLE, CYREG_CLK_DIVIDER_A00 +.set ADC_intClock__ENABLE_MASK, 0x80000000 +.set ADC_intClock__MASK, 0x80000000 +.set ADC_intClock__REGISTER, CYREG_CLK_DIVIDER_A00 +.set ADC_IRQ__INTC_CLR_EN_REG, CYREG_CM0_ICER +.set ADC_IRQ__INTC_CLR_PD_REG, CYREG_CM0_ICPR +.set ADC_IRQ__INTC_MASK, 0x4000 +.set ADC_IRQ__INTC_NUMBER, 14 +.set ADC_IRQ__INTC_PRIOR_MASK, 0xC00000 +.set ADC_IRQ__INTC_PRIOR_NUM, 3 +.set ADC_IRQ__INTC_PRIOR_REG, CYREG_CM0_IPR3 +.set ADC_IRQ__INTC_SET_EN_REG, CYREG_CM0_ISER +.set ADC_IRQ__INTC_SET_PD_REG, CYREG_CM0_ISPR + +/* LED */ +.set LED__0__DM__MASK, 0x1C0000 +.set LED__0__DM__SHIFT, 18 +.set LED__0__DR, CYREG_PRT1_DR +.set LED__0__HSIOM, CYREG_HSIOM_PORT_SEL1 +.set LED__0__HSIOM_MASK, 0x0F000000 +.set LED__0__HSIOM_SHIFT, 24 +.set LED__0__INTCFG, CYREG_PRT1_INTCFG +.set LED__0__INTSTAT, CYREG_PRT1_INTSTAT +.set LED__0__MASK, 0x40 +.set LED__0__PA__CFG0, CYREG_UDB_PA1_CFG0 +.set LED__0__PA__CFG1, CYREG_UDB_PA1_CFG1 +.set LED__0__PA__CFG10, CYREG_UDB_PA1_CFG10 +.set LED__0__PA__CFG11, CYREG_UDB_PA1_CFG11 +.set LED__0__PA__CFG12, CYREG_UDB_PA1_CFG12 +.set LED__0__PA__CFG13, CYREG_UDB_PA1_CFG13 +.set LED__0__PA__CFG14, CYREG_UDB_PA1_CFG14 +.set LED__0__PA__CFG2, CYREG_UDB_PA1_CFG2 +.set LED__0__PA__CFG3, CYREG_UDB_PA1_CFG3 +.set LED__0__PA__CFG4, CYREG_UDB_PA1_CFG4 +.set LED__0__PA__CFG5, CYREG_UDB_PA1_CFG5 +.set LED__0__PA__CFG6, CYREG_UDB_PA1_CFG6 +.set LED__0__PA__CFG7, CYREG_UDB_PA1_CFG7 +.set LED__0__PA__CFG8, CYREG_UDB_PA1_CFG8 +.set LED__0__PA__CFG9, CYREG_UDB_PA1_CFG9 +.set LED__0__PC, CYREG_PRT1_PC +.set LED__0__PC2, CYREG_PRT1_PC2 +.set LED__0__PORT, 1 +.set LED__0__PS, CYREG_PRT1_PS +.set LED__0__SHIFT, 6 +.set LED__DR, CYREG_PRT1_DR +.set LED__INTCFG, CYREG_PRT1_INTCFG +.set LED__INTSTAT, CYREG_PRT1_INTSTAT +.set LED__MASK, 0x40 +.set LED__PA__CFG0, CYREG_UDB_PA1_CFG0 +.set LED__PA__CFG1, CYREG_UDB_PA1_CFG1 +.set LED__PA__CFG10, CYREG_UDB_PA1_CFG10 +.set LED__PA__CFG11, CYREG_UDB_PA1_CFG11 +.set LED__PA__CFG12, CYREG_UDB_PA1_CFG12 +.set LED__PA__CFG13, CYREG_UDB_PA1_CFG13 +.set LED__PA__CFG14, CYREG_UDB_PA1_CFG14 +.set LED__PA__CFG2, CYREG_UDB_PA1_CFG2 +.set LED__PA__CFG3, CYREG_UDB_PA1_CFG3 +.set LED__PA__CFG4, CYREG_UDB_PA1_CFG4 +.set LED__PA__CFG5, CYREG_UDB_PA1_CFG5 +.set LED__PA__CFG6, CYREG_UDB_PA1_CFG6 +.set LED__PA__CFG7, CYREG_UDB_PA1_CFG7 +.set LED__PA__CFG8, CYREG_UDB_PA1_CFG8 +.set LED__PA__CFG9, CYREG_UDB_PA1_CFG9 +.set LED__PC, CYREG_PRT1_PC +.set LED__PC2, CYREG_PRT1_PC2 +.set LED__PORT, 1 +.set LED__PS, CYREG_PRT1_PS +.set LED__SHIFT, 6 + +/* UART */ +.set UART_SCB__BIST_CONTROL, CYREG_SCB0_BIST_CONTROL +.set UART_SCB__BIST_DATA, CYREG_SCB0_BIST_DATA +.set UART_SCB__CTRL, CYREG_SCB0_CTRL +.set UART_SCB__EZ_DATA00, CYREG_SCB0_EZ_DATA00 +.set UART_SCB__EZ_DATA01, CYREG_SCB0_EZ_DATA01 +.set UART_SCB__EZ_DATA02, CYREG_SCB0_EZ_DATA02 +.set UART_SCB__EZ_DATA03, CYREG_SCB0_EZ_DATA03 +.set UART_SCB__EZ_DATA04, CYREG_SCB0_EZ_DATA04 +.set UART_SCB__EZ_DATA05, CYREG_SCB0_EZ_DATA05 +.set UART_SCB__EZ_DATA06, CYREG_SCB0_EZ_DATA06 +.set UART_SCB__EZ_DATA07, CYREG_SCB0_EZ_DATA07 +.set UART_SCB__EZ_DATA08, CYREG_SCB0_EZ_DATA08 +.set UART_SCB__EZ_DATA09, CYREG_SCB0_EZ_DATA09 +.set UART_SCB__EZ_DATA10, CYREG_SCB0_EZ_DATA10 +.set UART_SCB__EZ_DATA11, CYREG_SCB0_EZ_DATA11 +.set UART_SCB__EZ_DATA12, CYREG_SCB0_EZ_DATA12 +.set UART_SCB__EZ_DATA13, CYREG_SCB0_EZ_DATA13 +.set UART_SCB__EZ_DATA14, CYREG_SCB0_EZ_DATA14 +.set UART_SCB__EZ_DATA15, CYREG_SCB0_EZ_DATA15 +.set UART_SCB__EZ_DATA16, CYREG_SCB0_EZ_DATA16 +.set UART_SCB__EZ_DATA17, CYREG_SCB0_EZ_DATA17 +.set UART_SCB__EZ_DATA18, CYREG_SCB0_EZ_DATA18 +.set UART_SCB__EZ_DATA19, CYREG_SCB0_EZ_DATA19 +.set UART_SCB__EZ_DATA20, CYREG_SCB0_EZ_DATA20 +.set UART_SCB__EZ_DATA21, CYREG_SCB0_EZ_DATA21 +.set UART_SCB__EZ_DATA22, CYREG_SCB0_EZ_DATA22 +.set UART_SCB__EZ_DATA23, CYREG_SCB0_EZ_DATA23 +.set UART_SCB__EZ_DATA24, CYREG_SCB0_EZ_DATA24 +.set UART_SCB__EZ_DATA25, CYREG_SCB0_EZ_DATA25 +.set UART_SCB__EZ_DATA26, CYREG_SCB0_EZ_DATA26 +.set UART_SCB__EZ_DATA27, CYREG_SCB0_EZ_DATA27 +.set UART_SCB__EZ_DATA28, CYREG_SCB0_EZ_DATA28 +.set UART_SCB__EZ_DATA29, CYREG_SCB0_EZ_DATA29 +.set UART_SCB__EZ_DATA30, CYREG_SCB0_EZ_DATA30 +.set UART_SCB__EZ_DATA31, CYREG_SCB0_EZ_DATA31 +.set UART_SCB__I2C_CFG, CYREG_SCB0_I2C_CFG +.set UART_SCB__I2C_CTRL, CYREG_SCB0_I2C_CTRL +.set UART_SCB__I2C_M_CMD, CYREG_SCB0_I2C_M_CMD +.set UART_SCB__I2C_S_CMD, CYREG_SCB0_I2C_S_CMD +.set UART_SCB__I2C_STATUS, CYREG_SCB0_I2C_STATUS +.set UART_SCB__INTR_CAUSE, CYREG_SCB0_INTR_CAUSE +.set UART_SCB__INTR_I2C_EC, CYREG_SCB0_INTR_I2C_EC +.set UART_SCB__INTR_I2C_EC_MASK, CYREG_SCB0_INTR_I2C_EC_MASK +.set UART_SCB__INTR_I2C_EC_MASKED, CYREG_SCB0_INTR_I2C_EC_MASKED +.set UART_SCB__INTR_M, CYREG_SCB0_INTR_M +.set UART_SCB__INTR_M_MASK, CYREG_SCB0_INTR_M_MASK +.set UART_SCB__INTR_M_MASKED, CYREG_SCB0_INTR_M_MASKED +.set UART_SCB__INTR_M_SET, CYREG_SCB0_INTR_M_SET +.set UART_SCB__INTR_RX, CYREG_SCB0_INTR_RX +.set UART_SCB__INTR_RX_MASK, CYREG_SCB0_INTR_RX_MASK +.set UART_SCB__INTR_RX_MASKED, CYREG_SCB0_INTR_RX_MASKED +.set UART_SCB__INTR_RX_SET, CYREG_SCB0_INTR_RX_SET +.set UART_SCB__INTR_S, CYREG_SCB0_INTR_S +.set UART_SCB__INTR_S_MASK, CYREG_SCB0_INTR_S_MASK +.set UART_SCB__INTR_S_MASKED, CYREG_SCB0_INTR_S_MASKED +.set UART_SCB__INTR_S_SET, CYREG_SCB0_INTR_S_SET +.set UART_SCB__INTR_SPI_EC, CYREG_SCB0_INTR_SPI_EC +.set UART_SCB__INTR_SPI_EC_MASK, CYREG_SCB0_INTR_SPI_EC_MASK +.set UART_SCB__INTR_SPI_EC_MASKED, CYREG_SCB0_INTR_SPI_EC_MASKED +.set UART_SCB__INTR_TX, CYREG_SCB0_INTR_TX +.set UART_SCB__INTR_TX_MASK, CYREG_SCB0_INTR_TX_MASK +.set UART_SCB__INTR_TX_MASKED, CYREG_SCB0_INTR_TX_MASKED +.set UART_SCB__INTR_TX_SET, CYREG_SCB0_INTR_TX_SET +.set UART_SCB__RX_CTRL, CYREG_SCB0_RX_CTRL +.set UART_SCB__RX_FIFO_CTRL, CYREG_SCB0_RX_FIFO_CTRL +.set UART_SCB__RX_FIFO_RD, CYREG_SCB0_RX_FIFO_RD +.set UART_SCB__RX_FIFO_RD_SILENT, CYREG_SCB0_RX_FIFO_RD_SILENT +.set UART_SCB__RX_FIFO_STATUS, CYREG_SCB0_RX_FIFO_STATUS +.set UART_SCB__RX_MATCH, CYREG_SCB0_RX_MATCH +.set UART_SCB__SPI_CTRL, CYREG_SCB0_SPI_CTRL +.set UART_SCB__SPI_STATUS, CYREG_SCB0_SPI_STATUS +.set UART_SCB__SS0_POSISTION, 0 +.set UART_SCB__SS1_POSISTION, 1 +.set UART_SCB__SS2_POSISTION, 2 +.set UART_SCB__SS3_POSISTION, 3 +.set UART_SCB__STATUS, CYREG_SCB0_STATUS +.set UART_SCB__TX_CTRL, CYREG_SCB0_TX_CTRL +.set UART_SCB__TX_FIFO_CTRL, CYREG_SCB0_TX_FIFO_CTRL +.set UART_SCB__TX_FIFO_STATUS, CYREG_SCB0_TX_FIFO_STATUS +.set UART_SCB__TX_FIFO_WR, CYREG_SCB0_TX_FIFO_WR +.set UART_SCB__UART_CTRL, CYREG_SCB0_UART_CTRL +.set UART_SCB__UART_RX_CTRL, CYREG_SCB0_UART_RX_CTRL +.set UART_SCB__UART_RX_STATUS, CYREG_SCB0_UART_RX_STATUS +.set UART_SCB__UART_TX_CTRL, CYREG_SCB0_UART_TX_CTRL +.set UART_SCBCLK__DIVIDER_MASK, 0x0000FFFF +.set UART_SCBCLK__ENABLE, CYREG_CLK_DIVIDER_B00 +.set UART_SCBCLK__ENABLE_MASK, 0x80000000 +.set UART_SCBCLK__MASK, 0x80000000 +.set UART_SCBCLK__REGISTER, CYREG_CLK_DIVIDER_B00 +.set UART_tx__0__DM__MASK, 0x38 +.set UART_tx__0__DM__SHIFT, 3 +.set UART_tx__0__DR, CYREG_PRT4_DR +.set UART_tx__0__HSIOM, CYREG_HSIOM_PORT_SEL4 +.set UART_tx__0__HSIOM_GPIO, 0 +.set UART_tx__0__HSIOM_I2C, 14 +.set UART_tx__0__HSIOM_I2C_SDA, 14 +.set UART_tx__0__HSIOM_MASK, 0x000000F0 +.set UART_tx__0__HSIOM_SHIFT, 4 +.set UART_tx__0__HSIOM_SPI, 15 +.set UART_tx__0__HSIOM_SPI_MISO, 15 +.set UART_tx__0__HSIOM_UART, 9 +.set UART_tx__0__HSIOM_UART_TX, 9 +.set UART_tx__0__INTCFG, CYREG_PRT4_INTCFG +.set UART_tx__0__INTSTAT, CYREG_PRT4_INTSTAT +.set UART_tx__0__MASK, 0x02 +.set UART_tx__0__PC, CYREG_PRT4_PC +.set UART_tx__0__PC2, CYREG_PRT4_PC2 +.set UART_tx__0__PORT, 4 +.set UART_tx__0__PS, CYREG_PRT4_PS +.set UART_tx__0__SHIFT, 1 +.set UART_tx__DR, CYREG_PRT4_DR +.set UART_tx__INTCFG, CYREG_PRT4_INTCFG +.set UART_tx__INTSTAT, CYREG_PRT4_INTSTAT +.set UART_tx__MASK, 0x02 +.set UART_tx__PC, CYREG_PRT4_PC +.set UART_tx__PC2, CYREG_PRT4_PC2 +.set UART_tx__PORT, 4 +.set UART_tx__PS, CYREG_PRT4_PS +.set UART_tx__SHIFT, 1 + +/* Input_1 */ +.set Input_1__0__DM__MASK, 0xE00 +.set Input_1__0__DM__SHIFT, 9 +.set Input_1__0__DR, CYREG_PRT2_DR +.set Input_1__0__HSIOM, CYREG_HSIOM_PORT_SEL2 +.set Input_1__0__HSIOM_MASK, 0x0000F000 +.set Input_1__0__HSIOM_SHIFT, 12 +.set Input_1__0__INTCFG, CYREG_PRT2_INTCFG +.set Input_1__0__INTSTAT, CYREG_PRT2_INTSTAT +.set Input_1__0__MASK, 0x08 +.set Input_1__0__PA__CFG0, CYREG_UDB_PA2_CFG0 +.set Input_1__0__PA__CFG1, CYREG_UDB_PA2_CFG1 +.set Input_1__0__PA__CFG10, CYREG_UDB_PA2_CFG10 +.set Input_1__0__PA__CFG11, CYREG_UDB_PA2_CFG11 +.set Input_1__0__PA__CFG12, CYREG_UDB_PA2_CFG12 +.set Input_1__0__PA__CFG13, CYREG_UDB_PA2_CFG13 +.set Input_1__0__PA__CFG14, CYREG_UDB_PA2_CFG14 +.set Input_1__0__PA__CFG2, CYREG_UDB_PA2_CFG2 +.set Input_1__0__PA__CFG3, CYREG_UDB_PA2_CFG3 +.set Input_1__0__PA__CFG4, CYREG_UDB_PA2_CFG4 +.set Input_1__0__PA__CFG5, CYREG_UDB_PA2_CFG5 +.set Input_1__0__PA__CFG6, CYREG_UDB_PA2_CFG6 +.set Input_1__0__PA__CFG7, CYREG_UDB_PA2_CFG7 +.set Input_1__0__PA__CFG8, CYREG_UDB_PA2_CFG8 +.set Input_1__0__PA__CFG9, CYREG_UDB_PA2_CFG9 +.set Input_1__0__PC, CYREG_PRT2_PC +.set Input_1__0__PC2, CYREG_PRT2_PC2 +.set Input_1__0__PORT, 2 +.set Input_1__0__PS, CYREG_PRT2_PS +.set Input_1__0__SHIFT, 3 +.set Input_1__DR, CYREG_PRT2_DR +.set Input_1__INTCFG, CYREG_PRT2_INTCFG +.set Input_1__INTSTAT, CYREG_PRT2_INTSTAT +.set Input_1__MASK, 0x08 +.set Input_1__PA__CFG0, CYREG_UDB_PA2_CFG0 +.set Input_1__PA__CFG1, CYREG_UDB_PA2_CFG1 +.set Input_1__PA__CFG10, CYREG_UDB_PA2_CFG10 +.set Input_1__PA__CFG11, CYREG_UDB_PA2_CFG11 +.set Input_1__PA__CFG12, CYREG_UDB_PA2_CFG12 +.set Input_1__PA__CFG13, CYREG_UDB_PA2_CFG13 +.set Input_1__PA__CFG14, CYREG_UDB_PA2_CFG14 +.set Input_1__PA__CFG2, CYREG_UDB_PA2_CFG2 +.set Input_1__PA__CFG3, CYREG_UDB_PA2_CFG3 +.set Input_1__PA__CFG4, CYREG_UDB_PA2_CFG4 +.set Input_1__PA__CFG5, CYREG_UDB_PA2_CFG5 +.set Input_1__PA__CFG6, CYREG_UDB_PA2_CFG6 +.set Input_1__PA__CFG7, CYREG_UDB_PA2_CFG7 +.set Input_1__PA__CFG8, CYREG_UDB_PA2_CFG8 +.set Input_1__PA__CFG9, CYREG_UDB_PA2_CFG9 +.set Input_1__PC, CYREG_PRT2_PC +.set Input_1__PC2, CYREG_PRT2_PC2 +.set Input_1__PORT, 2 +.set Input_1__PS, CYREG_PRT2_PS +.set Input_1__SHIFT, 3 + +/* Miscellaneous */ +.set CYDEV_BCLK__HFCLK__HZ, 24000000 +.set CYDEV_BCLK__HFCLK__KHZ, 24000 +.set CYDEV_BCLK__HFCLK__MHZ, 24 +.set CYDEV_BCLK__SYSCLK__HZ, 24000000 +.set CYDEV_BCLK__SYSCLK__KHZ, 24000 +.set CYDEV_BCLK__SYSCLK__MHZ, 24 +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PSOC4A, 18 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4 +.set CYDEV_CHIP_JTAG_ID, 0x04C81193 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 18 +.set CYDEV_CHIP_MEMBER_4D, 13 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 19 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 17 +.set CYDEV_CHIP_MEMBER_4I, 23 +.set CYDEV_CHIP_MEMBER_4J, 14 +.set CYDEV_CHIP_MEMBER_4K, 15 +.set CYDEV_CHIP_MEMBER_4L, 22 +.set CYDEV_CHIP_MEMBER_4M, 21 +.set CYDEV_CHIP_MEMBER_4N, 10 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 20 +.set CYDEV_CHIP_MEMBER_4Q, 12 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 11 +.set CYDEV_CHIP_MEMBER_4T, 9 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_4V, 16 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 24 +.set CYDEV_CHIP_MEMBER_FM3, 28 +.set CYDEV_CHIP_MEMBER_FM4, 29 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4A +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1 +.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1 +.set CYDEV_CHIP_REV_TMA4_ES, 17 +.set CYDEV_CHIP_REV_TMA4_ES2, 33 +.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 +.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0 +.set CYDEV_CHIP_REVISION_4G_ES, 17 +.set CYDEV_CHIP_REVISION_4G_ES2, 33 +.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_ES, 17 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 +.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4A_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED +.set CYDEV_CONFIG_READ_ACCELERATOR, 1 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_DEBUG_PROTECT_KILL, 4 +.set CYDEV_DEBUG_PROTECT_OPEN, 1 +.set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_OPEN +.set CYDEV_DEBUG_PROTECT_PROTECTED, 2 +.set CYDEV_DEBUGGING_DPS_Disable, 3 +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD +.set CYDEV_DEBUGGING_ENABLE, 1 +.set CYDEV_DFT_SELECT_CLK0, 1 +.set CYDEV_DFT_SELECT_CLK1, 2 +.set CYDEV_HEAP_SIZE, 0x0100 +.set CYDEV_IMO_TRIMMED_BY_USB, 0 +.set CYDEV_IMO_TRIMMED_BY_WCO, 0 +.set CYDEV_IS_EXPORTING_CODE, 0 +.set CYDEV_IS_IMPORTING_CODE, 0 +.set CYDEV_PROJ_TYPE, 0 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LAUNCHER, 5 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_STACK_SIZE, 0x0400 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 0 +.set CYDEV_VDDA_MV, 5000 +.set CYDEV_VDDD_MV, 5000 +.set CYDEV_WDT_GENERATE_ISR, 0 +.set CYIPBLOCK_M0S8_CTBM_VERSION, 0 +.set CYIPBLOCK_m0s8cpuss_VERSION, 0 +.set CYIPBLOCK_m0s8csd_VERSION, 0 +.set CYIPBLOCK_m0s8gpio2_VERSION, 0 +.set CYIPBLOCK_m0s8hsiom4a_VERSION, 0 +.set CYIPBLOCK_m0s8lcd_VERSION, 0 +.set CYIPBLOCK_m0s8lpcomp_VERSION, 0 +.set CYIPBLOCK_m0s8pclk_VERSION, 0 +.set CYIPBLOCK_m0s8sar_VERSION, 0 +.set CYIPBLOCK_m0s8scb_VERSION, 0 +.set CYIPBLOCK_m0s8srssv2_VERSION, 1 +.set CYIPBLOCK_m0s8tcpwm_VERSION, 0 +.set CYIPBLOCK_m0s8udbif_VERSION, 0 +.set CYIPBLOCK_S8_GPIO_VERSION, 2 +.set CYDEV_BOOTLOADER_ENABLE, 0 +.endif diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitteriar.inc b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitteriar.inc new file mode 100644 index 0000000..2a81a83 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitteriar.inc @@ -0,0 +1,496 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#ifndef INCLUDED_CYFITTERIAR_INC +#define INCLUDED_CYFITTERIAR_INC + INCLUDE cydeviceiar_trm.inc + +/* ADC */ +ADC_cy_psoc4_sar__SAR_ANA_TRIM EQU CYREG_SAR_ANA_TRIM +ADC_cy_psoc4_sar__SAR_AVG_STAT EQU CYREG_SAR_AVG_STAT +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 EQU CYREG_SAR_CHAN_CONFIG00 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 EQU CYREG_SAR_CHAN_CONFIG01 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 EQU CYREG_SAR_CHAN_CONFIG02 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 EQU CYREG_SAR_CHAN_CONFIG03 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 EQU CYREG_SAR_CHAN_CONFIG04 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 EQU CYREG_SAR_CHAN_CONFIG05 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 EQU CYREG_SAR_CHAN_CONFIG06 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 EQU CYREG_SAR_CHAN_CONFIG07 +ADC_cy_psoc4_sar__SAR_CHAN_EN EQU CYREG_SAR_CHAN_EN +ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID EQU CYREG_SAR_CHAN_RESULT_VALID +ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 EQU CYREG_SAR_CHAN_RESULT00 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 EQU CYREG_SAR_CHAN_RESULT01 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 EQU CYREG_SAR_CHAN_RESULT02 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 EQU CYREG_SAR_CHAN_RESULT03 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 EQU CYREG_SAR_CHAN_RESULT04 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 EQU CYREG_SAR_CHAN_RESULT05 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 EQU CYREG_SAR_CHAN_RESULT06 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 EQU CYREG_SAR_CHAN_RESULT07 +ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID EQU CYREG_SAR_CHAN_WORK_VALID +ADC_cy_psoc4_sar__SAR_CHAN_WORK00 EQU CYREG_SAR_CHAN_WORK00 +ADC_cy_psoc4_sar__SAR_CHAN_WORK01 EQU CYREG_SAR_CHAN_WORK01 +ADC_cy_psoc4_sar__SAR_CHAN_WORK02 EQU CYREG_SAR_CHAN_WORK02 +ADC_cy_psoc4_sar__SAR_CHAN_WORK03 EQU CYREG_SAR_CHAN_WORK03 +ADC_cy_psoc4_sar__SAR_CHAN_WORK04 EQU CYREG_SAR_CHAN_WORK04 +ADC_cy_psoc4_sar__SAR_CHAN_WORK05 EQU CYREG_SAR_CHAN_WORK05 +ADC_cy_psoc4_sar__SAR_CHAN_WORK06 EQU CYREG_SAR_CHAN_WORK06 +ADC_cy_psoc4_sar__SAR_CHAN_WORK07 EQU CYREG_SAR_CHAN_WORK07 +ADC_cy_psoc4_sar__SAR_CTRL EQU CYREG_SAR_CTRL +ADC_cy_psoc4_sar__SAR_DFT_CTRL EQU CYREG_SAR_DFT_CTRL +ADC_cy_psoc4_sar__SAR_INTR EQU CYREG_SAR_INTR +ADC_cy_psoc4_sar__SAR_INTR_CAUSE EQU CYREG_SAR_INTR_CAUSE +ADC_cy_psoc4_sar__SAR_INTR_MASK EQU CYREG_SAR_INTR_MASK +ADC_cy_psoc4_sar__SAR_INTR_MASKED EQU CYREG_SAR_INTR_MASKED +ADC_cy_psoc4_sar__SAR_INTR_SET EQU CYREG_SAR_INTR_SET +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0 EQU CYREG_SAR_MUX_SWITCH_CLEAR0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1 EQU CYREG_SAR_MUX_SWITCH_CLEAR1 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL EQU CYREG_SAR_MUX_SWITCH_HW_CTRL +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS EQU CYREG_SAR_MUX_SWITCH_STATUS +ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 EQU CYREG_SAR_MUX_SWITCH0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH1 EQU CYREG_SAR_MUX_SWITCH1 +ADC_cy_psoc4_sar__SAR_NUMBER EQU 0 +ADC_cy_psoc4_sar__SAR_PUMP_CTRL EQU CYREG_SAR_PUMP_CTRL +ADC_cy_psoc4_sar__SAR_RANGE_COND EQU CYREG_SAR_RANGE_COND +ADC_cy_psoc4_sar__SAR_RANGE_INTR EQU CYREG_SAR_RANGE_INTR +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK EQU CYREG_SAR_RANGE_INTR_MASK +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED EQU CYREG_SAR_RANGE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET EQU CYREG_SAR_RANGE_INTR_SET +ADC_cy_psoc4_sar__SAR_RANGE_THRES EQU CYREG_SAR_RANGE_THRES +ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL EQU CYREG_SAR_SAMPLE_CTRL +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 EQU CYREG_SAR_SAMPLE_TIME01 +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 EQU CYREG_SAR_SAMPLE_TIME23 +ADC_cy_psoc4_sar__SAR_SATURATE_INTR EQU CYREG_SAR_SATURATE_INTR +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK EQU CYREG_SAR_SATURATE_INTR_MASK +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED EQU CYREG_SAR_SATURATE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET EQU CYREG_SAR_SATURATE_INTR_SET +ADC_cy_psoc4_sar__SAR_START_CTRL EQU CYREG_SAR_START_CTRL +ADC_cy_psoc4_sar__SAR_STATUS EQU CYREG_SAR_STATUS +ADC_cy_psoc4_sar__SAR_WOUNDING EQU CYREG_SAR_WOUNDING +ADC_intClock__DIVIDER_MASK EQU 0x0000FFFF +ADC_intClock__ENABLE EQU CYREG_CLK_DIVIDER_A00 +ADC_intClock__ENABLE_MASK EQU 0x80000000 +ADC_intClock__MASK EQU 0x80000000 +ADC_intClock__REGISTER EQU CYREG_CLK_DIVIDER_A00 +ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER +ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR +ADC_IRQ__INTC_MASK EQU 0x4000 +ADC_IRQ__INTC_NUMBER EQU 14 +ADC_IRQ__INTC_PRIOR_MASK EQU 0xC00000 +ADC_IRQ__INTC_PRIOR_NUM EQU 3 +ADC_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR3 +ADC_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER +ADC_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR + +/* LED */ +LED__0__DM__MASK EQU 0x1C0000 +LED__0__DM__SHIFT EQU 18 +LED__0__DR EQU CYREG_PRT1_DR +LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1 +LED__0__HSIOM_MASK EQU 0x0F000000 +LED__0__HSIOM_SHIFT EQU 24 +LED__0__INTCFG EQU CYREG_PRT1_INTCFG +LED__0__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__0__MASK EQU 0x40 +LED__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__0__PC EQU CYREG_PRT1_PC +LED__0__PC2 EQU CYREG_PRT1_PC2 +LED__0__PORT EQU 1 +LED__0__PS EQU CYREG_PRT1_PS +LED__0__SHIFT EQU 6 +LED__DR EQU CYREG_PRT1_DR +LED__INTCFG EQU CYREG_PRT1_INTCFG +LED__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__MASK EQU 0x40 +LED__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__PC EQU CYREG_PRT1_PC +LED__PC2 EQU CYREG_PRT1_PC2 +LED__PORT EQU 1 +LED__PS EQU CYREG_PRT1_PS +LED__SHIFT EQU 6 + +/* UART */ +UART_SCB__BIST_CONTROL EQU CYREG_SCB0_BIST_CONTROL +UART_SCB__BIST_DATA EQU CYREG_SCB0_BIST_DATA +UART_SCB__CTRL EQU CYREG_SCB0_CTRL +UART_SCB__EZ_DATA00 EQU CYREG_SCB0_EZ_DATA00 +UART_SCB__EZ_DATA01 EQU CYREG_SCB0_EZ_DATA01 +UART_SCB__EZ_DATA02 EQU CYREG_SCB0_EZ_DATA02 +UART_SCB__EZ_DATA03 EQU CYREG_SCB0_EZ_DATA03 +UART_SCB__EZ_DATA04 EQU CYREG_SCB0_EZ_DATA04 +UART_SCB__EZ_DATA05 EQU CYREG_SCB0_EZ_DATA05 +UART_SCB__EZ_DATA06 EQU CYREG_SCB0_EZ_DATA06 +UART_SCB__EZ_DATA07 EQU CYREG_SCB0_EZ_DATA07 +UART_SCB__EZ_DATA08 EQU CYREG_SCB0_EZ_DATA08 +UART_SCB__EZ_DATA09 EQU CYREG_SCB0_EZ_DATA09 +UART_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10 +UART_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11 +UART_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12 +UART_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13 +UART_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14 +UART_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15 +UART_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16 +UART_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17 +UART_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18 +UART_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19 +UART_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20 +UART_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21 +UART_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22 +UART_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23 +UART_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24 +UART_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25 +UART_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26 +UART_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27 +UART_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28 +UART_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29 +UART_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30 +UART_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31 +UART_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG +UART_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL +UART_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD +UART_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD +UART_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS +UART_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE +UART_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC +UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK +UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED +UART_SCB__INTR_M EQU CYREG_SCB0_INTR_M +UART_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK +UART_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED +UART_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET +UART_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX +UART_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK +UART_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED +UART_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET +UART_SCB__INTR_S EQU CYREG_SCB0_INTR_S +UART_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK +UART_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED +UART_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET +UART_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC +UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK +UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED +UART_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX +UART_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK +UART_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED +UART_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET +UART_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL +UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL +UART_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD +UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT +UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS +UART_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH +UART_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL +UART_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS +UART_SCB__SS0_POSISTION EQU 0 +UART_SCB__SS1_POSISTION EQU 1 +UART_SCB__SS2_POSISTION EQU 2 +UART_SCB__SS3_POSISTION EQU 3 +UART_SCB__STATUS EQU CYREG_SCB0_STATUS +UART_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL +UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL +UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS +UART_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR +UART_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL +UART_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL +UART_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS +UART_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL +UART_SCBCLK__DIVIDER_MASK EQU 0x0000FFFF +UART_SCBCLK__ENABLE EQU CYREG_CLK_DIVIDER_B00 +UART_SCBCLK__ENABLE_MASK EQU 0x80000000 +UART_SCBCLK__MASK EQU 0x80000000 +UART_SCBCLK__REGISTER EQU CYREG_CLK_DIVIDER_B00 +UART_tx__0__DM__MASK EQU 0x38 +UART_tx__0__DM__SHIFT EQU 3 +UART_tx__0__DR EQU CYREG_PRT4_DR +UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +UART_tx__0__HSIOM_GPIO EQU 0 +UART_tx__0__HSIOM_I2C EQU 14 +UART_tx__0__HSIOM_I2C_SDA EQU 14 +UART_tx__0__HSIOM_MASK EQU 0x000000F0 +UART_tx__0__HSIOM_SHIFT EQU 4 +UART_tx__0__HSIOM_SPI EQU 15 +UART_tx__0__HSIOM_SPI_MISO EQU 15 +UART_tx__0__HSIOM_UART EQU 9 +UART_tx__0__HSIOM_UART_TX EQU 9 +UART_tx__0__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__0__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__0__MASK EQU 0x02 +UART_tx__0__PC EQU CYREG_PRT4_PC +UART_tx__0__PC2 EQU CYREG_PRT4_PC2 +UART_tx__0__PORT EQU 4 +UART_tx__0__PS EQU CYREG_PRT4_PS +UART_tx__0__SHIFT EQU 1 +UART_tx__DR EQU CYREG_PRT4_DR +UART_tx__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__MASK EQU 0x02 +UART_tx__PC EQU CYREG_PRT4_PC +UART_tx__PC2 EQU CYREG_PRT4_PC2 +UART_tx__PORT EQU 4 +UART_tx__PS EQU CYREG_PRT4_PS +UART_tx__SHIFT EQU 1 + +/* Input_1 */ +Input_1__0__DM__MASK EQU 0xE00 +Input_1__0__DM__SHIFT EQU 9 +Input_1__0__DR EQU CYREG_PRT2_DR +Input_1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 +Input_1__0__HSIOM_MASK EQU 0x0000F000 +Input_1__0__HSIOM_SHIFT EQU 12 +Input_1__0__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__0__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__0__MASK EQU 0x08 +Input_1__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__0__PC EQU CYREG_PRT2_PC +Input_1__0__PC2 EQU CYREG_PRT2_PC2 +Input_1__0__PORT EQU 2 +Input_1__0__PS EQU CYREG_PRT2_PS +Input_1__0__SHIFT EQU 3 +Input_1__DR EQU CYREG_PRT2_DR +Input_1__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__MASK EQU 0x08 +Input_1__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__PC EQU CYREG_PRT2_PC +Input_1__PC2 EQU CYREG_PRT2_PC2 +Input_1__PORT EQU 2 +Input_1__PS EQU CYREG_PRT2_PS +Input_1__SHIFT EQU 3 + +/* Miscellaneous */ +CYDEV_BCLK__HFCLK__HZ EQU 24000000 +CYDEV_BCLK__HFCLK__KHZ EQU 24000 +CYDEV_BCLK__HFCLK__MHZ EQU 24 +CYDEV_BCLK__SYSCLK__HZ EQU 24000000 +CYDEV_BCLK__SYSCLK__KHZ EQU 24000 +CYDEV_BCLK__SYSCLK__MHZ EQU 24 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 +CYDEV_CHIP_JTAG_ID EQU 0x04C81193 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4A +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4A_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_READ_ACCELERATOR EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_PROTECT_KILL EQU 4 +CYDEV_DEBUG_PROTECT_OPEN EQU 1 +CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN +CYDEV_DEBUG_PROTECT_PROTECTED EQU 2 +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DFT_SELECT_CLK0 EQU 1 +CYDEV_DFT_SELECT_CLK1 EQU 2 +CYDEV_HEAP_SIZE EQU 0x0100 +CYDEV_IMO_TRIMMED_BY_USB EQU 0 +CYDEV_IMO_TRIMMED_BY_WCO EQU 0 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 0 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_STACK_SIZE EQU 0x0400 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_WDT_GENERATE_ISR EQU 0 +CYIPBLOCK_M0S8_CTBM_VERSION EQU 0 +CYIPBLOCK_m0s8cpuss_VERSION EQU 0 +CYIPBLOCK_m0s8csd_VERSION EQU 0 +CYIPBLOCK_m0s8gpio2_VERSION EQU 0 +CYIPBLOCK_m0s8hsiom4a_VERSION EQU 0 +CYIPBLOCK_m0s8lcd_VERSION EQU 0 +CYIPBLOCK_m0s8lpcomp_VERSION EQU 0 +CYIPBLOCK_m0s8pclk_VERSION EQU 0 +CYIPBLOCK_m0s8sar_VERSION EQU 0 +CYIPBLOCK_m0s8scb_VERSION EQU 0 +CYIPBLOCK_m0s8srssv2_VERSION EQU 1 +CYIPBLOCK_m0s8tcpwm_VERSION EQU 0 +CYIPBLOCK_m0s8udbif_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 2 +CYDEV_BOOTLOADER_ENABLE EQU 0 + +#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitterrv.inc b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitterrv.inc new file mode 100644 index 0000000..8f6f1e4 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyfitterrv.inc @@ -0,0 +1,496 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv_trm.inc + +; ADC +ADC_cy_psoc4_sar__SAR_ANA_TRIM EQU CYREG_SAR_ANA_TRIM +ADC_cy_psoc4_sar__SAR_AVG_STAT EQU CYREG_SAR_AVG_STAT +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 EQU CYREG_SAR_CHAN_CONFIG00 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 EQU CYREG_SAR_CHAN_CONFIG01 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 EQU CYREG_SAR_CHAN_CONFIG02 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 EQU CYREG_SAR_CHAN_CONFIG03 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 EQU CYREG_SAR_CHAN_CONFIG04 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 EQU CYREG_SAR_CHAN_CONFIG05 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 EQU CYREG_SAR_CHAN_CONFIG06 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 EQU CYREG_SAR_CHAN_CONFIG07 +ADC_cy_psoc4_sar__SAR_CHAN_EN EQU CYREG_SAR_CHAN_EN +ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID EQU CYREG_SAR_CHAN_RESULT_VALID +ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 EQU CYREG_SAR_CHAN_RESULT00 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 EQU CYREG_SAR_CHAN_RESULT01 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 EQU CYREG_SAR_CHAN_RESULT02 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 EQU CYREG_SAR_CHAN_RESULT03 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 EQU CYREG_SAR_CHAN_RESULT04 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 EQU CYREG_SAR_CHAN_RESULT05 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 EQU CYREG_SAR_CHAN_RESULT06 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 EQU CYREG_SAR_CHAN_RESULT07 +ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID EQU CYREG_SAR_CHAN_WORK_VALID +ADC_cy_psoc4_sar__SAR_CHAN_WORK00 EQU CYREG_SAR_CHAN_WORK00 +ADC_cy_psoc4_sar__SAR_CHAN_WORK01 EQU CYREG_SAR_CHAN_WORK01 +ADC_cy_psoc4_sar__SAR_CHAN_WORK02 EQU CYREG_SAR_CHAN_WORK02 +ADC_cy_psoc4_sar__SAR_CHAN_WORK03 EQU CYREG_SAR_CHAN_WORK03 +ADC_cy_psoc4_sar__SAR_CHAN_WORK04 EQU CYREG_SAR_CHAN_WORK04 +ADC_cy_psoc4_sar__SAR_CHAN_WORK05 EQU CYREG_SAR_CHAN_WORK05 +ADC_cy_psoc4_sar__SAR_CHAN_WORK06 EQU CYREG_SAR_CHAN_WORK06 +ADC_cy_psoc4_sar__SAR_CHAN_WORK07 EQU CYREG_SAR_CHAN_WORK07 +ADC_cy_psoc4_sar__SAR_CTRL EQU CYREG_SAR_CTRL +ADC_cy_psoc4_sar__SAR_DFT_CTRL EQU CYREG_SAR_DFT_CTRL +ADC_cy_psoc4_sar__SAR_INTR EQU CYREG_SAR_INTR +ADC_cy_psoc4_sar__SAR_INTR_CAUSE EQU CYREG_SAR_INTR_CAUSE +ADC_cy_psoc4_sar__SAR_INTR_MASK EQU CYREG_SAR_INTR_MASK +ADC_cy_psoc4_sar__SAR_INTR_MASKED EQU CYREG_SAR_INTR_MASKED +ADC_cy_psoc4_sar__SAR_INTR_SET EQU CYREG_SAR_INTR_SET +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0 EQU CYREG_SAR_MUX_SWITCH_CLEAR0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1 EQU CYREG_SAR_MUX_SWITCH_CLEAR1 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL EQU CYREG_SAR_MUX_SWITCH_HW_CTRL +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS EQU CYREG_SAR_MUX_SWITCH_STATUS +ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 EQU CYREG_SAR_MUX_SWITCH0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH1 EQU CYREG_SAR_MUX_SWITCH1 +ADC_cy_psoc4_sar__SAR_NUMBER EQU 0 +ADC_cy_psoc4_sar__SAR_PUMP_CTRL EQU CYREG_SAR_PUMP_CTRL +ADC_cy_psoc4_sar__SAR_RANGE_COND EQU CYREG_SAR_RANGE_COND +ADC_cy_psoc4_sar__SAR_RANGE_INTR EQU CYREG_SAR_RANGE_INTR +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK EQU CYREG_SAR_RANGE_INTR_MASK +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED EQU CYREG_SAR_RANGE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET EQU CYREG_SAR_RANGE_INTR_SET +ADC_cy_psoc4_sar__SAR_RANGE_THRES EQU CYREG_SAR_RANGE_THRES +ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL EQU CYREG_SAR_SAMPLE_CTRL +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 EQU CYREG_SAR_SAMPLE_TIME01 +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 EQU CYREG_SAR_SAMPLE_TIME23 +ADC_cy_psoc4_sar__SAR_SATURATE_INTR EQU CYREG_SAR_SATURATE_INTR +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK EQU CYREG_SAR_SATURATE_INTR_MASK +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED EQU CYREG_SAR_SATURATE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET EQU CYREG_SAR_SATURATE_INTR_SET +ADC_cy_psoc4_sar__SAR_START_CTRL EQU CYREG_SAR_START_CTRL +ADC_cy_psoc4_sar__SAR_STATUS EQU CYREG_SAR_STATUS +ADC_cy_psoc4_sar__SAR_WOUNDING EQU CYREG_SAR_WOUNDING +ADC_intClock__DIVIDER_MASK EQU 0x0000FFFF +ADC_intClock__ENABLE EQU CYREG_CLK_DIVIDER_A00 +ADC_intClock__ENABLE_MASK EQU 0x80000000 +ADC_intClock__MASK EQU 0x80000000 +ADC_intClock__REGISTER EQU CYREG_CLK_DIVIDER_A00 +ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER +ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR +ADC_IRQ__INTC_MASK EQU 0x4000 +ADC_IRQ__INTC_NUMBER EQU 14 +ADC_IRQ__INTC_PRIOR_MASK EQU 0xC00000 +ADC_IRQ__INTC_PRIOR_NUM EQU 3 +ADC_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR3 +ADC_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER +ADC_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR + +; LED +LED__0__DM__MASK EQU 0x1C0000 +LED__0__DM__SHIFT EQU 18 +LED__0__DR EQU CYREG_PRT1_DR +LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1 +LED__0__HSIOM_MASK EQU 0x0F000000 +LED__0__HSIOM_SHIFT EQU 24 +LED__0__INTCFG EQU CYREG_PRT1_INTCFG +LED__0__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__0__MASK EQU 0x40 +LED__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__0__PC EQU CYREG_PRT1_PC +LED__0__PC2 EQU CYREG_PRT1_PC2 +LED__0__PORT EQU 1 +LED__0__PS EQU CYREG_PRT1_PS +LED__0__SHIFT EQU 6 +LED__DR EQU CYREG_PRT1_DR +LED__INTCFG EQU CYREG_PRT1_INTCFG +LED__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__MASK EQU 0x40 +LED__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__PC EQU CYREG_PRT1_PC +LED__PC2 EQU CYREG_PRT1_PC2 +LED__PORT EQU 1 +LED__PS EQU CYREG_PRT1_PS +LED__SHIFT EQU 6 + +; UART +UART_SCB__BIST_CONTROL EQU CYREG_SCB0_BIST_CONTROL +UART_SCB__BIST_DATA EQU CYREG_SCB0_BIST_DATA +UART_SCB__CTRL EQU CYREG_SCB0_CTRL +UART_SCB__EZ_DATA00 EQU CYREG_SCB0_EZ_DATA00 +UART_SCB__EZ_DATA01 EQU CYREG_SCB0_EZ_DATA01 +UART_SCB__EZ_DATA02 EQU CYREG_SCB0_EZ_DATA02 +UART_SCB__EZ_DATA03 EQU CYREG_SCB0_EZ_DATA03 +UART_SCB__EZ_DATA04 EQU CYREG_SCB0_EZ_DATA04 +UART_SCB__EZ_DATA05 EQU CYREG_SCB0_EZ_DATA05 +UART_SCB__EZ_DATA06 EQU CYREG_SCB0_EZ_DATA06 +UART_SCB__EZ_DATA07 EQU CYREG_SCB0_EZ_DATA07 +UART_SCB__EZ_DATA08 EQU CYREG_SCB0_EZ_DATA08 +UART_SCB__EZ_DATA09 EQU CYREG_SCB0_EZ_DATA09 +UART_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10 +UART_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11 +UART_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12 +UART_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13 +UART_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14 +UART_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15 +UART_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16 +UART_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17 +UART_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18 +UART_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19 +UART_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20 +UART_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21 +UART_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22 +UART_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23 +UART_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24 +UART_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25 +UART_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26 +UART_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27 +UART_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28 +UART_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29 +UART_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30 +UART_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31 +UART_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG +UART_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL +UART_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD +UART_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD +UART_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS +UART_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE +UART_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC +UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK +UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED +UART_SCB__INTR_M EQU CYREG_SCB0_INTR_M +UART_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK +UART_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED +UART_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET +UART_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX +UART_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK +UART_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED +UART_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET +UART_SCB__INTR_S EQU CYREG_SCB0_INTR_S +UART_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK +UART_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED +UART_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET +UART_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC +UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK +UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED +UART_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX +UART_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK +UART_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED +UART_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET +UART_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL +UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL +UART_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD +UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT +UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS +UART_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH +UART_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL +UART_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS +UART_SCB__SS0_POSISTION EQU 0 +UART_SCB__SS1_POSISTION EQU 1 +UART_SCB__SS2_POSISTION EQU 2 +UART_SCB__SS3_POSISTION EQU 3 +UART_SCB__STATUS EQU CYREG_SCB0_STATUS +UART_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL +UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL +UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS +UART_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR +UART_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL +UART_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL +UART_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS +UART_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL +UART_SCBCLK__DIVIDER_MASK EQU 0x0000FFFF +UART_SCBCLK__ENABLE EQU CYREG_CLK_DIVIDER_B00 +UART_SCBCLK__ENABLE_MASK EQU 0x80000000 +UART_SCBCLK__MASK EQU 0x80000000 +UART_SCBCLK__REGISTER EQU CYREG_CLK_DIVIDER_B00 +UART_tx__0__DM__MASK EQU 0x38 +UART_tx__0__DM__SHIFT EQU 3 +UART_tx__0__DR EQU CYREG_PRT4_DR +UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +UART_tx__0__HSIOM_GPIO EQU 0 +UART_tx__0__HSIOM_I2C EQU 14 +UART_tx__0__HSIOM_I2C_SDA EQU 14 +UART_tx__0__HSIOM_MASK EQU 0x000000F0 +UART_tx__0__HSIOM_SHIFT EQU 4 +UART_tx__0__HSIOM_SPI EQU 15 +UART_tx__0__HSIOM_SPI_MISO EQU 15 +UART_tx__0__HSIOM_UART EQU 9 +UART_tx__0__HSIOM_UART_TX EQU 9 +UART_tx__0__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__0__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__0__MASK EQU 0x02 +UART_tx__0__PC EQU CYREG_PRT4_PC +UART_tx__0__PC2 EQU CYREG_PRT4_PC2 +UART_tx__0__PORT EQU 4 +UART_tx__0__PS EQU CYREG_PRT4_PS +UART_tx__0__SHIFT EQU 1 +UART_tx__DR EQU CYREG_PRT4_DR +UART_tx__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__MASK EQU 0x02 +UART_tx__PC EQU CYREG_PRT4_PC +UART_tx__PC2 EQU CYREG_PRT4_PC2 +UART_tx__PORT EQU 4 +UART_tx__PS EQU CYREG_PRT4_PS +UART_tx__SHIFT EQU 1 + +; Input_1 +Input_1__0__DM__MASK EQU 0xE00 +Input_1__0__DM__SHIFT EQU 9 +Input_1__0__DR EQU CYREG_PRT2_DR +Input_1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 +Input_1__0__HSIOM_MASK EQU 0x0000F000 +Input_1__0__HSIOM_SHIFT EQU 12 +Input_1__0__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__0__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__0__MASK EQU 0x08 +Input_1__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__0__PC EQU CYREG_PRT2_PC +Input_1__0__PC2 EQU CYREG_PRT2_PC2 +Input_1__0__PORT EQU 2 +Input_1__0__PS EQU CYREG_PRT2_PS +Input_1__0__SHIFT EQU 3 +Input_1__DR EQU CYREG_PRT2_DR +Input_1__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__MASK EQU 0x08 +Input_1__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__PC EQU CYREG_PRT2_PC +Input_1__PC2 EQU CYREG_PRT2_PC2 +Input_1__PORT EQU 2 +Input_1__PS EQU CYREG_PRT2_PS +Input_1__SHIFT EQU 3 + +; Miscellaneous +CYDEV_BCLK__HFCLK__HZ EQU 24000000 +CYDEV_BCLK__HFCLK__KHZ EQU 24000 +CYDEV_BCLK__HFCLK__MHZ EQU 24 +CYDEV_BCLK__SYSCLK__HZ EQU 24000000 +CYDEV_BCLK__SYSCLK__KHZ EQU 24000 +CYDEV_BCLK__SYSCLK__MHZ EQU 24 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 +CYDEV_CHIP_JTAG_ID EQU 0x04C81193 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4A +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4A_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_READ_ACCELERATOR EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_PROTECT_KILL EQU 4 +CYDEV_DEBUG_PROTECT_OPEN EQU 1 +CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN +CYDEV_DEBUG_PROTECT_PROTECTED EQU 2 +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DFT_SELECT_CLK0 EQU 1 +CYDEV_DFT_SELECT_CLK1 EQU 2 +CYDEV_HEAP_SIZE EQU 0x0100 +CYDEV_IMO_TRIMMED_BY_USB EQU 0 +CYDEV_IMO_TRIMMED_BY_WCO EQU 0 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 0 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_STACK_SIZE EQU 0x0400 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_WDT_GENERATE_ISR EQU 0 +CYIPBLOCK_M0S8_CTBM_VERSION EQU 0 +CYIPBLOCK_m0s8cpuss_VERSION EQU 0 +CYIPBLOCK_m0s8csd_VERSION EQU 0 +CYIPBLOCK_m0s8gpio2_VERSION EQU 0 +CYIPBLOCK_m0s8hsiom4a_VERSION EQU 0 +CYIPBLOCK_m0s8lcd_VERSION EQU 0 +CYIPBLOCK_m0s8lpcomp_VERSION EQU 0 +CYIPBLOCK_m0s8pclk_VERSION EQU 0 +CYIPBLOCK_m0s8sar_VERSION EQU 0 +CYIPBLOCK_m0s8scb_VERSION EQU 0 +CYIPBLOCK_m0s8srssv2_VERSION EQU 1 +CYIPBLOCK_m0s8tcpwm_VERSION EQU 0 +CYIPBLOCK_m0s8udbif_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 2 +CYDEV_BOOTLOADER_ENABLE EQU 0 + ENDIF + END diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cymetadata.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cymetadata.c new file mode 100644 index 0000000..def5fcd --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cymetadata.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: cymetadata.c +* +* PSoC Creator 4.2 +* +* Description: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "stdint.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_FLASH_PROT_SECTION +#define CY_FLASH_PROT_SECTION __attribute__ ((__section__(".cyflashprotect"), used)) +#endif +CY_FLASH_PROT_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyflashprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_flashprotect[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_META_SECTION +#define CY_META_SECTION __attribute__ ((__section__(".cymeta"), used)) +#endif +CY_META_SECTION +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_metadata[] = { + 0x00u, 0x02u, 0x04u, 0xC8u, 0x11u, 0x93u, 0x11u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_CHIP_PROT_SECTION +#define CY_CHIP_PROT_SECTION __attribute__ ((__section__(".cychipprotect"), used)) +#endif +CY_CHIP_PROT_SECTION +#elif defined(__ICCARM__) +#pragma location=".cychipprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_chipprotect[] = { + 0x01u +}; diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cypins.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cypins.h new file mode 100644 index 0000000..53a0b29 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cypins.h @@ -0,0 +1,324 @@ +/******************************************************************************* +* \file cypins.h +* \version 5.70 +* +* \brief This file contains the function prototypes and constants used for +* port/pin in access and control. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cytypes.h" + +/** +* \addtogroup group_pins Pins +* \brief For PSoC 4, there are status registers, data output registers, and port +configuration registers only, so the macro takes two arguments: port register +and pin number. Each port has these registers addresses defined: +CYREG_PRTx_DR +CYREG_PRTx_PS +CYREG_PRTx_PC + +The x is the port number, and the second argument is the pin number. + +* @{ +*/ + +/** @} group_pins */ + + +/************************************** +* Register Constants +**************************************/ + + +#define CY_SYS_PINS_PC_DATAOUT ((uint32) 0x01u) +#define CY_SYS_PINS_PC_DRIVE_MODE_BITS ((uint32) 0x03u) +#define CY_SYS_PINS_PC_DRIVE_MODE_MASK ((uint32) 0x07u) + + +/************************************** +* API Parameter Constants +**************************************/ + +/* SetPinDriveMode */ +#define CY_SYS_PINS_DM_ALG_HIZ ((uint32) 0x00u) +#define CY_SYS_PINS_DM_DIG_HIZ ((uint32) 0x01u) +#define CY_SYS_PINS_DM_RES_UP ((uint32) 0x02u) +#define CY_SYS_PINS_DM_RES_DWN ((uint32) 0x03u) +#define CY_SYS_PINS_DM_OD_LO ((uint32) 0x04u) +#define CY_SYS_PINS_DM_OD_HI ((uint32) 0x05u) +#define CY_SYS_PINS_DM_STRONG ((uint32) 0x06u) +#define CY_SYS_PINS_DM_RES_UPDWN ((uint32) 0x07u) + + +/************************************** +* Compatibility Macros +**************************************/ + +#if(CY_IP_HOBTO_DEVICE) + #define CYREG_PRT0_DR (CYREG_GPIO_PRT0_DR) + #define CYREG_PRT0_PS (CYREG_GPIO_PRT0_PS) + #define CYREG_PRT0_PC (CYREG_GPIO_PRT0_PC) + + #define CYREG_PRT1_DR (CYREG_GPIO_PRT1_DR) + #define CYREG_PRT1_PS (CYREG_GPIO_PRT1_PS) + #define CYREG_PRT1_PC (CYREG_GPIO_PRT1_PC) + + #define CYREG_PRT2_DR (CYREG_GPIO_PRT2_DR) + #define CYREG_PRT2_PS (CYREG_GPIO_PRT2_PS) + #define CYREG_PRT2_PC (CYREG_GPIO_PRT2_PC) + + #define CYREG_PRT3_DR (CYREG_GPIO_PRT3_DR) + #define CYREG_PRT3_PS (CYREG_GPIO_PRT3_PS) + #define CYREG_PRT3_PC (CYREG_GPIO_PRT3_PC) + + #define CYREG_PRT4_DR (CYREG_GPIO_PRT4_DR) + #define CYREG_PRT4_PS (CYREG_GPIO_PRT4_PS) + #define CYREG_PRT4_PC (CYREG_GPIO_PRT4_PC) + + #define CYREG_PRT5_DR (CYREG_GPIO_PRT5_DR) + #define CYREG_PRT5_PS (CYREG_GPIO_PRT5_PS) + #define CYREG_PRT5_PC (CYREG_GPIO_PRT5_PC) + + #define CYREG_PRT6_DR (CYREG_GPIO_PRT6_DR) + #define CYREG_PRT6_PS (CYREG_GPIO_PRT6_PS) + #define CYREG_PRT6_PC (CYREG_GPIO_PRT6_PC) + + #define CYREG_PRT7_DR (CYREG_GPIO_PRT7_DR) + #define CYREG_PRT7_PS (CYREG_GPIO_PRT7_PS) + #define CYREG_PRT7_PC (CYREG_GPIO_PRT7_PC) + + #define CYREG_PRT8_DR (CYREG_GPIO_PRT8_DR) + #define CYREG_PRT8_PS (CYREG_GPIO_PRT8_PS) + #define CYREG_PRT8_PC (CYREG_GPIO_PRT8_PC) + + #define CYREG_PRT9_DR (CYREG_GPIO_PRT9_DR) + #define CYREG_PRT9_PS (CYREG_GPIO_PRT9_PS) + #define CYREG_PRT9_PC (CYREG_GPIO_PRT9_PC) + + #define CYREG_PRT10_DR (CYREG_GPIO_PRT10_DR) + #define CYREG_PRT10_PS (CYREG_GPIO_PRT10_PS) + #define CYREG_PRT10_PC (CYREG_GPIO_PRT10_PC) + + #define CYREG_PRT11_DR (CYREG_GPIO_PRT11_DR) + #define CYREG_PRT11_PS (CYREG_GPIO_PRT11_PS) + #define CYREG_PRT11_PC (CYREG_GPIO_PRT11_PC) + + #define CYREG_PRT12_DR (CYREG_GPIO_PRT12_DR) + #define CYREG_PRT12_PS (CYREG_GPIO_PRT12_PS) + #define CYREG_PRT12_PC (CYREG_GPIO_PRT12_PC) + + #define CYREG_PRT13_DR (CYREG_GPIO_PRT13_DR) + #define CYREG_PRT13_PS (CYREG_GPIO_PRT13_PS) + #define CYREG_PRT13_PC (CYREG_GPIO_PRT13_PC) + + #define CYREG_PRT14_DR (CYREG_GPIO_PRT14_DR) + #define CYREG_PRT14_PS (CYREG_GPIO_PRT14_PS) + #define CYREG_PRT14_PC (CYREG_GPIO_PRT14_PC) + + #define CYREG_PRT15_DR (CYREG_GPIO_PRT15_DR) + #define CYREG_PRT15_PS (CYREG_GPIO_PRT15_PS) + #define CYREG_PRT15_PC (CYREG_GPIO_PRT15_PC) + +#else + + #define CYREG_GPIO_PRT0_DR (CYREG_PRT0_DR) + #define CYREG_GPIO_PRT0_PS (CYREG_PRT0_PS) + #define CYREG_GPIO_PRT0_PC (CYREG_PRT0_PC) + + #define CYREG_GPIO_PRT1_DR (CYREG_PRT1_DR) + #define CYREG_GPIO_PRT1_PS (CYREG_PRT1_PS) + #define CYREG_GPIO_PRT1_PC (CYREG_PRT1_PC) + + #define CYREG_GPIO_PRT2_DR (CYREG_PRT2_DR) + #define CYREG_GPIO_PRT2_PS (CYREG_PRT2_PS) + #define CYREG_GPIO_PRT2_PC (CYREG_PRT2_PC) + + #define CYREG_GPIO_PRT3_DR (CYREG_PRT3_DR) + #define CYREG_GPIO_PRT3_PS (CYREG_PRT3_PS) + #define CYREG_GPIO_PRT3_PC (CYREG_PRT3_PC) + + #define CYREG_GPIO_PRT4_DR (CYREG_PRT4_DR) + #define CYREG_GPIO_PRT4_PS (CYREG_PRT4_PS) + #define CYREG_GPIO_PRT4_PC (CYREG_PRT4_PC) +#endif /* (CY_IP_HOBTO_DEVICE) */ + + +/************************************** +* Pin API Macros +**************************************/ + +/** +* \defgroup group_pins Pins +* @{ +*/ + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_READ_PIN +****************************************************************************//** +* +* Reads the current value on the pin (pin state, PS). +* +* \param portPS Address of the port pin status register (uint32). Definitions +* for each port are provided in the cydevice_trm.h file in the form: +* CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends on the +* selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +* \return Zero - logic low, non-zero - logic high. +* +*******************************************************************************/ +#define CY_SYS_PINS_READ_PIN(portPS, pin) \ + (( *(reg32 *)(portPS) >> (pin)) & CY_SYS_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_SET_PIN +****************************************************************************//** +* +* Set the output value for the pin (data register, DR) to a logic high. +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portDR Address of the port output pin data register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends +* on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +*******************************************************************************/ +#define CY_SYS_PINS_SET_PIN(portDR, pin) \ + ( *(reg32 *)(portDR) |= (CY_SYS_PINS_PC_DATAOUT << (pin)) ) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_CLEAR_PIN +****************************************************************************//** +* +* This macro sets the state of the specified pin to zero. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portDR Address of the port output pin data register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number +* depends on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected device. +* +*******************************************************************************/ +#define CY_SYS_PINS_CLEAR_PIN(portDR, pin) \ + ( *(reg32 *)(portDR) &= ~(CY_SYS_PINS_PC_DATAOUT << (pin)) ) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_SET_DRIVE_MODE +****************************************************************************//** +* +* Sets the drive mode for the pin (DM). +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portPC: Address of the port configuration register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number +* depends on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected device. +* +* \param mode Desired drive mode. +* +* Define Source +* CY_SYS_PINS_DM_ALG_HIZ Analog HiZ +* CY_SYS_PINS_DM_DIG_HIZ Digital HiZ +* CY_SYS_PINS_DM_RES_UP Resistive pull up +* CY_SYS_PINS_DM_RES_DWN Resistive pull down +* CY_SYS_PINS_DM_OD_LO Open drain - drive low +* CY_SYS_PINS_DM_OD_HI Open drain - drive high +* CY_SYS_PINS_DM_STRONG Strong CMOS Output +* CY_SYS_PINS_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CY_SYS_PINS_SET_DRIVE_MODE(portPC, pin, mode) \ + ( *(reg32 *)(portPC) = (*(reg32 *)(portPC) & \ + ~(CY_SYS_PINS_PC_DRIVE_MODE_MASK << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS))) | \ + ((mode) << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS))) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_READ_DRIVE_MODE +****************************************************************************//** +* +* Reads the drive mode for the pin (DM). +* +* \param portPC Address of the port configuration register (uint32). Definitions +* for each port are provided in the cydevice_trm.h file in the form: +* CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends on the +* selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +* \return mode Current drive mode for the pin: +* - CY_SYS_PINS_DM_ALG_HIZ Analog HiZ +* - CY_SYS_PINS_DM_DIG_HIZ Digital HiZ +* - CY_SYS_PINS_DM_RES_UP Resistive pull up +* - CY_SYS_PINS_DM_RES_DWN Resistive pull down +* - CY_SYS_PINS_DM_OD_LO Open drain - drive low +* - CY_SYS_PINS_DM_OD_HI Open drain - drive high +* - CY_SYS_PINS_DM_STRONG Strong CMOS Output +* - CY_SYS_PINS_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CY_SYS_PINS_READ_DRIVE_MODE(portPC, pin) \ + (( *(reg32 *)(portPC) & \ + (CY_SYS_PINS_PC_DRIVE_MODE_MASK << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS)) ) >> \ + (pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS) + +/** @} group_pins */ + +/* Defines function macros for mapping PSoC 4 per-pin functions to PSoC 3/5LP style functions */ +#define CyPins_ReadPin(name) (CY_SYS_PINS_READ_PIN (name ## _PS, name ## _SHIFT)) +#define CyPins_SetPin(name) (CY_SYS_PINS_SET_PIN (name ## _DR, name ## _SHIFT)) +#define CyPins_ClearPin(name) (CY_SYS_PINS_CLEAR_PIN (name ## _DR, name ## _SHIFT)) +#define CyPins_SetPinDriveMode(name, mode) (CY_SYS_PINS_SET_DRIVE_MODE (name ## _PC, name ## _SHIFT, mode)) +#define CyPins_ReadPinDriveMode(name) (CY_SYS_PINS_READ_DRIVE_MODE(name ## _PC, name ## _SHIFT)) + + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cytypes.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cytypes.h new file mode 100644 index 0000000..d5b3a84 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cytypes.h @@ -0,0 +1,1496 @@ +/***************************************************************************//** +* \file cytypes.h +* \version 5.70 +* +* \brief CyTypes provides register access macros and approved types for use in +* firmware. +* +* \note Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of the type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) +#else + #define CY_PSOC4_4000 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) + +#ifdef CYDEV_CHIP_MEMBER_4F + #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) + #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) +#else + #define CY_PSOC4_4100BL (0u != 0u) + #define CY_PSOC4_4200BL (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4F */ + +#ifdef CYDEV_CHIP_MEMBER_4M + #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) + #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) +#else + #define CY_PSOC4_4100M (0u != 0u) + #define CY_PSOC4_4200M (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4M */ + +#ifdef CYDEV_CHIP_MEMBER_4H + #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H) +#else + #define CY_PSOC4_4200D (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4H */ + +#ifdef CYDEV_CHIP_MEMBER_4L + #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L) +#else + #define CY_PSOC4_4200L (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4L */ + +#ifdef CYDEV_CHIP_MEMBER_4U + #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U) +#else + #define CY_PSOC4_4000U (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4U */ + +#ifdef CYDEV_CHIP_MEMBER_4J + #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J) +#else + #define CY_PSOC4_4000S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4J */ + +#ifdef CYDEV_CHIP_MEMBER_4K + #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K) +#else + #define CY_PSOC4_4100S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4K */ + +#ifdef CYDEV_CHIP_MEMBER_4I + #define CY_PSOC4_4400 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4I) +#else + #define CY_PSOC4_4400 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4I */ + +#ifdef CYDEV_CHIP_MEMBER_4E + #define CY_CCG2 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4E) +#else + #define CY_CCG2 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4E */ + +#ifdef CYDEV_CHIP_MEMBER_4O + #define CY_CCG3 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4O) +#else + #define CY_CCG3 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4O */ + +#ifdef CYDEV_CHIP_MEMBER_4R + #define CY_CCG3PA (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4R) +#else + #define CY_CCG3PA (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4R */ + +#ifdef CYDEV_CHIP_MEMBER_4N + #define CY_CCG4 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4N) +#else + #define CY_CCG4 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4N */ + +#ifdef CYDEV_CHIP_MEMBER_4S + #define CY_CCG5 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4S) +#else + #define CY_CCG5 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4S */ + +#ifdef CYDEV_CHIP_MEMBER_4P + #define CY_PSOC4_4100BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) + #define CY_PSOC4_4200BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) +#else + #define CY_PSOC4_4100BLII (0u != 0u) + #define CY_PSOC4_4200BLII (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4P */ + +#ifdef CYDEV_CHIP_MEMBER_4V + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) +#else + #define CY_PSOC4_4100MS (0u != 0u) + #define CY_PSOC4_4100MS (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4V */ + +#define CY_IP_HOBTO_DEVICE (!(1 == 1)) + + +/******************************************************************************* +* IP blocks +*******************************************************************************/ +#if (CY_PSOC4) + + /* Using SRSSv2 or SRS-Lite */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_SRSSV2 (1 != 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #else + #define CY_IP_SRSSV2 (0 == 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSSV3 (0 == 1) + #define CY_IP_CPUSSV2 (0 == 1) + #define CY_IP_CPUSS (1 == 1) + #else + #define CY_IP_CPUSSV3 (0 != 0) + #define CY_IP_CPUSSV2 (0 != 0) + #define CY_IP_CPUSS (0 == 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_CPUSS_CM0 (0 == 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_CPUSS_CM0 (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0) + #else + #define CY_IP_CPUSS_CM0 (0 == 0) + #define CY_IP_CPUSS_CM0PLUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash memory present or not (1=Flash present, 0=Flash not present) */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0) + #else + #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Product uses FLASH-Lite or regular FLASH */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */ + #define CY_IP_FS (0 != 0) /* FS */ + #define CY_IP_FSLT (0 != 0) /* FSLT */ + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Enable simultaneous execution/programming in multi-macro devices */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_MACROS (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_MACROS (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_MACROS (1u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Number of interrupt request inputs to CM0 */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_INT_NR (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_INT_NR (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_INT_NR (32u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Presence of the BLESS IP block */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (CYIPBLOCK_m0s8bless_VERSION == 3) + #else + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_USBDEV (0 != 0) + #else + #define CY_IP_USBDEV (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /*************************************************************************** + * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use + * the 36MHz Oscillator for Flash operation. Instead, flash write function + * ensures that the charge pump clock and the higher frequency clock (HFCLK) + * are set to the IMO at 48MHz prior to writing the flash. + ***************************************************************************/ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Watch Crystal Oscillator (WCO) is present (32kHz) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #if (CY_IP_BLESSV3) + #define CY_IP_WCO_WCOV2 (0 == 0) + #define CY_IP_WCO_BLESS (0 != 0) + #else + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_BLESS (0 == 0) + #endif + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 == 1) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_WCOV2 || CY_IP_WCO_SRSSV2) + + /* External Crystal Oscillator is present (high frequency) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + + #if (CY_IP_BLESSV3) + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 == 0) + #else + #define CY_IP_ECO_BLESS (0 == 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #endif + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (-1 == 1) + #define CY_IP_ECO_SRSSLT ((0 != 0) && (0 != 0)) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2 || CY_IP_ECO_BLESSV3 || CY_IP_ECO_SRSSLT) + + /* PLL is present */ + #if (CY_IP_HOBTO_DEVICE) + #if(CY_IP_SRSSV2) + #define CY_IP_PLL ((-1 != 0) || \ + (-1 != 0)) + + #define CY_IP_PLL_NR (-1u + \ + -1u) + + #elif (CY_IP_SRSSLT) + #define CY_IP_PLL (-1 == 1) + + #define CY_IP_PLL_NR (1) + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_SRSSV2) */ + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash Macro 0 has extra rows */ + #if (CY_IP_HOBTO_DEVICE) + #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0 + #define CY_SFLASH_XTRA_ROWS (0 == 0) + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */ + + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_USBDEV) + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0) + #endif /* (CY_IP_USBDEV) */ + + + #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0) + #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */ + + + /* DW/DMA Controller present (0=No, 1=Yes) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_DMAC_PRESENT (-1 == 1) + #else + #define CY_IP_DMAC_PRESENT (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_DMAC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_PASS (0 == 1) + #else + #define CY_IP_PASS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + + /* Number of external slave ports on System Interconnect */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SL_NR (-1) + #else + #define CY_IP_SL_NR (-1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + +#else + + #if (CY_PSOC3) + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #else /* PSoC 5LP */ + #define CY_SYSTICK_LFCLK_SOURCE (0 == 0) + #endif /* (CY_PSOC3) */ + +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* The components version defines. Available started from cy_boot 4.20 +* Use the following construction in order to identify cy_boot version: +* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20) +*******************************************************************************/ +#define CY_BOOT_4_20 (420u) +#define CY_BOOT_5_0 (500u) +#define CY_BOOT_5_10 (510u) +#define CY_BOOT_5_20 (520u) +#define CY_BOOT_5_30 (530u) +#define CY_BOOT_5_40 (540u) +#define CY_BOOT_5_50 (550u) +#define CY_BOOT_5_60 (560u) +#define CY_BOOT_5_70 (570u) +#define CY_BOOT_VERSION (CY_BOOT_5_70) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + + /* Specifies a minimum alignment (in bytes) for variables of the + * specified type. + */ + #define CY_ALIGN(align) __align(align) + + + /* Attached to an enum, struct, or union type definition, specified that + * the minimum required memory be used to represent the type. + */ + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE __inline + #elif defined (__GNUC__) + + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE inline + #elif defined (__ICCARM__) + + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #define CY_PACKED __packed + #define CY_PACKED_ATTR + #define CY_INLINE inline + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +#define CY_M_PI (3.14159265358979323846264338327) + + +/** +* \addtogroup group_register_access +A library of macros provides read and write access to the registers of the device. These macros are used with the +defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made +using these macros and not the functions that are used to implement the macros. This allows for device independent code +generation. + +The PSoC 4 processor architecture use little endian ordering. + +SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However, +the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this +little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider +the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers, +as well as function calls that are passed an array of bytes in memory. + +The PSoC 4 requires these accesses to be aligned to the width of the transaction. + +The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might +ignore the transfer and Hard Fault exception will be generated. + +*/ + +/** @} group_register_access */ + + +/** +* \addtogroup group_register_access_macros Register Access +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC3) + /******************************************************************************* + * Macro Name: CY_GET_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * Identical to \ref CY_GET_REG8 for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * Identical to \ref CY_SET_REG8 for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ +/** @} group_register_access_macros */ + + +/** +* \addtogroup group_register_access_bits Bit Manipulation +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC4) + + /******************************************************************************* + * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName) + ****************************************************************************//** + * + * Returns the bit field mask for the specified register size and bit field + * name. + * + * \param regSize Size of the register in bits. + * \param bitFieldName Fully qualified name of the bit field. The biFieldName + * is automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * \return Returns the bit mask. + * + *******************************************************************************/ + #define CY_GET_FIELD_MASK(regSize, bitFieldName) \ + ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\ + ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET) + + + /******************************************************************************* + * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register will remain uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on 32-bit and 16-bit width registers will generate a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG8_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 8-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers, generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG8((registerName), \ + ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \ + (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \ + (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hardfault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG16_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 16-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerNam The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG16((registerName), \ + ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \ + (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\ + (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The Fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields, please, refer to + * a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, otherwise. + * The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG32_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 32-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG32((registerName), \ + ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \ + (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \ + (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_FIELD(regValue, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_FIELD(regValue, bitFieldName) \ + (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value within a given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads and \ref CY_SET_REG32 for atomic writes. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to the respective PSoC family register TRM. + * + *******************************************************************************/ + #define CY_SET_FIELD(regValue, bitFieldName, value) \ + ((regValue) = \ + ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \ + ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET))) + +#endif /* (CY_PSOC4) */ + +/** @} group_register_access_bits */ + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu))) + + +/******************************************************************************* +* Defines the standard return values used in PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 5.10 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_IP_S8FS CY_IP_FS + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ +#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#define CY_UDB_V1 (!CY_UDB_V0) +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + +#if (!CY_PSOC4) + + /* Device is PSoC 3 and the revision is ES2 or earlier */ + #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + + /* Device is PSoC 3 and the revision is ES3 or later */ + #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + + /* Device is PSoC 5 and the revision is ES1 or earlier */ + #define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + + /* Device is PSoC 5 and the revision is ES2 or later */ + #define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* (!CY_PSOC4) */ + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyutils.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyutils.c new file mode 100644 index 0000000..a9eb657 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/cyutils.c @@ -0,0 +1,75 @@ +/***************************************************************************//** +* \file cyutils.c +* \version 5.70 +* +* \brief Provides a function to handle 24-bit value writes. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + ************************************************************************//** + * + * Writes a 24-bit value to the specified register. + * + * \param addr The address where data must be written. + * \param value The data that must be written. + * + * \reentrant No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + ************************************************************************//** + * + * Reads the 24-bit value from the specified register. + * + * \param addr The address where data must be read. + * + * \reentrant No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 const volatile * addr) + { + uint8 const volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 const volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/exported_symbols.txt b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/exported_symbols.txt new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/project.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/project.h new file mode 100644 index 0000000..ac1bda3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/project.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: project.h +* +* PSoC Creator 4.2 +* +* Description: +* It contains references to all generated header files and should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "cyfitter_cfg.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "cydisabledsheets.h" +#include "LED.h" +#include "LED_aliases.h" +#include "UART.h" +#include "UART_SPI_UART.h" +#include "UART_PINS.h" +#include "UART_SPI_UART_PVT.h" +#include "UART_PVT.h" +#include "UART_BOOT.h" +#include "Input_1.h" +#include "Input_1_aliases.h" +#include "ADC.h" +#include "UART_SCBCLK.h" +#include "UART_tx.h" +#include "UART_tx_aliases.h" +#include "ADC_IRQ.h" +#include "ADC_intClock.h" +#include "cy_em_eeprom.h" +#include "core_cm0_psoc4.h" +#include "CyFlash.h" +#include "CyLib.h" +#include "cyPm.h" +#include "cytypes.h" +#include "cypins.h" +#include "CyLFClk.h" + +/*[]*/ + diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/renamed_symbols.txt b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/renamed_symbols.txt new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4100S/TopDesign.ctl b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4100S/TopDesign.ctl new file mode 100644 index 0000000..74cb25c --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4100S/TopDesign.ctl @@ -0,0 +1,31 @@ +-- ============================================================================= +-- The following directives assign pins to the locations specific for the +-- CY8CKIT-041 kit. +-- ============================================================================= + +-- === UART === +attribute port_location of \UART:rx(0)\ : label is "PORT(0,4)"; +attribute port_location of \UART:tx(0)\ : label is "PORT(0,5)"; + +-- === I2C === +attribute port_location of \I2C:scl(0)\ : label is "PORT(3,0)"; +attribute port_location of \I2C:sda(0)\ : label is "PORT(3,1)"; + +-- === RGB LED === +attribute port_location of LED(0) : label is "PORT(3,4)"; -- RED LED +attribute port_location of REPLACE_WITH_ACTUAL_PIN_NAME(0) : label is "PORT(2,6)"; -- GREEN LED +attribute port_location of REPLACE_WITH_ACTUAL_PIN_NAME(0) : label is "PORT(3,6)"; -- BLUE LED + +-- === USER SWITCH === +attribute port_location of SW2(0) : label is "PORT(0,7)"; + +attribute port_location of Differential_In_1(0) : label is "PORT(2,0)"; +attribute port_location of Differential_In_2(0) : label is "PORT(2,1)"; +attribute port_location of Input_3(0) : label is "PORT(2,2)"; +attribute port_location of Input_4(0) : label is "PORT(2,3)"; +attribute port_location of Out_1(0) : label is "PORT(1,2)"; +attribute port_location of Out_2(0) : label is "PORT(1,3)"; +attribute port_location of Preamp_In_1(0) : label is "PORT(1,0)"; +attribute port_location of Preamp_In_2(0) : label is "PORT(1,5)"; +attribute port_location of Inv_1(0) : label is "PORT(1,1)"; +attribute port_location of Inv_2(0) : label is "PORT(1,4)"; \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200 BLE/TopDesign.ctl b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200 BLE/TopDesign.ctl new file mode 100644 index 0000000..5af034a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200 BLE/TopDesign.ctl @@ -0,0 +1,24 @@ +-- ============================================================================= +-- The following directives assign pins to the locations specific for the +-- CY8CKIT-042-BLE kit. +-- ============================================================================= + +-- === UART === +attribute port_location of \UART:tx(0)\ : label is "PORT(1,5)"; + +-- === RGB LED === +attribute port_location of LED(0) : label is "PORT(2,6)"; -- RED LED + +-- === USER SWITCH === +attribute port_location of SW2(0) : label is "PORT(2,7)"; + +attribute port_location of Differential_In_1(0) : label is "PORT(3,0)"; +attribute port_location of Differential_In_2(0) : label is "PORT(3,1)"; +attribute port_location of Input_3(0) : label is "PORT(3,2)"; +attribute port_location of Input_4(0) : label is "PORT(3,3)"; +attribute port_location of Out_1(0) : label is "PORT(2,2)"; +attribute port_location of Out_2(0) : label is "PORT(2,3)"; +attribute port_location of Preamp_In_1(0) : label is "PORT(2,0)"; +attribute port_location of Preamp_In_2(0) : label is "PORT(2,5)"; +attribute port_location of Inv_1(0) : label is "PORT(2,1)"; +attribute port_location of Inv_2(0) : label is "PORT(2,4)"; \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200/TopDesign.ctl b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200/TopDesign.ctl new file mode 100644 index 0000000..c7ade80 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200/TopDesign.ctl @@ -0,0 +1,24 @@ +-- ============================================================================= +-- The following directives assign pins to the locations specific for the +-- CY8CKIT-042 kit. +-- ============================================================================= + +-- === UART === +attribute port_location of \UART:tx(0)\ : label is "PORT(0,5)"; + +-- === RGB LED === +attribute port_location of LED(0) : label is "PORT(1,6)"; -- RED LED + +-- === USER SWITCH === +attribute port_location of SW2(0) : label is "PORT(0,7)"; + +attribute port_location of Differential_In_1(0) : label is "PORT(2,0)"; +attribute port_location of Differential_In_2(0) : label is "PORT(2,1)"; +attribute port_location of Input_3(0) : label is "PORT(2,2)"; +attribute port_location of Input_4(0) : label is "PORT(2,3)"; +attribute port_location of Out_1(0) : label is "PORT(1,2)"; +attribute port_location of Out_2(0) : label is "PORT(1,3)"; +attribute port_location of Preamp_In_1(0) : label is "PORT(1,0)"; +attribute port_location of Preamp_In_2(0) : label is "PORT(1,5)"; +attribute port_location of Inv_1(0) : label is "PORT(1,1)"; +attribute port_location of Inv_2(0) : label is "PORT(1,4)"; \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200L/TopDesign.ctl b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200L/TopDesign.ctl new file mode 100644 index 0000000..8d7e4e3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200L/TopDesign.ctl @@ -0,0 +1,26 @@ +-- ============================================================================= +-- The following directives assign pins to the locations specific for the +-- CY8CKIT-046 kit. +-- ============================================================================= + +-- === UART === +attribute port_location of \UART:tx(0)\ : label is "PORT(3,1)"; + +-- === RGB LED === +attribute port_location of LED(0) : label is "PORT(5,2)"; -- RED LED +attribute port_location of REPLACE_WITH_ACTUAL_PIN_NAME(0) : label is "PORT(5,3)"; -- GREEN LED +attribute port_location of REPLACE_WITH_ACTUAL_PIN_NAME(0) : label is "PORT(5,4)"; -- BLUE LED + +-- === USER SWITCH === +attribute port_location of SW2(0) : label is "PORT(0,7)"; + +attribute port_location of Differential_In_1(0) : label is "PORT(2,0)"; +attribute port_location of Differential_In_2(0) : label is "PORT(2,1)"; +attribute port_location of Input_3(0) : label is "PORT(2,2)"; +attribute port_location of Input_4(0) : label is "PORT(2,3)"; +attribute port_location of Out_1(0) : label is "PORT(1,2)"; +attribute port_location of Out_2(0) : label is "PORT(1,3)"; +attribute port_location of Preamp_In_1(0) : label is "PORT(1,0)"; +attribute port_location of Preamp_In_2(0) : label is "PORT(1,7)"; +attribute port_location of Inv_1(0) : label is "PORT(1,1)"; +attribute port_location of Inv_2(0) : label is "PORT(1,4)"; \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200M/TopDesign.ctl b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200M/TopDesign.ctl new file mode 100644 index 0000000..3386bd6 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/TopDesign/PSoC4/PSoC 4200M/TopDesign.ctl @@ -0,0 +1,24 @@ +-- ============================================================================= +-- The following directives assign pins to the locations specific for the +-- CY8CKIT-044 kit. +-- ============================================================================= + +-- === UART === +attribute port_location of \UART:tx(0)\ : label is "PORT(7,1)"; + +-- === RGB LED === +attribute port_location of LED(0) : label is "PORT(0,6)"; -- RED LED + +-- === USER SWITCH === +attribute port_location of SW2(0) : label is "PORT(0,7)"; + +attribute port_location of Differential_In_1(0) : label is "PORT(2,0)"; +attribute port_location of Differential_In_2(0) : label is "PORT(2,1)"; +attribute port_location of Input_3(0) : label is "PORT(2,2)"; +attribute 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b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.bvf new file mode 100644 index 0000000..45684a2 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.bvf @@ -0,0 +1,21 @@ + +---------------------------------------------------------------------- + +Verifying bitstream. + +----------------------------------------------------------------------- + + +---------Mapping jacks.--------- + + +---------Processing bitstream.--------- + + + +---------------------------------------------------------------------- + +Bitstream verification passed. + +----------------------------------------------------------------------- + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.ctl b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.ctl new file mode 100644 index 0000000..6638cda --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.ctl @@ -0,0 +1,34 @@ +-- ====================================================================== +-- ADC-UART.ctl generated from ADC-UART +-- 07/17/2020 at 10:59 +-- This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! +-- ====================================================================== + +-- TopDesign +-- ============================================================================= +-- The following directives assign pins to the locations specific for the +-- CY8CKIT-042 kit. +-- ============================================================================= + +-- === UART === +attribute port_location of \UART:tx(0)\ : label is "PORT(0,5)"; + +-- === RGB LED === +attribute port_location of LED(0) : label is "PORT(1,6)"; -- RED LED + +-- === USER SWITCH === +attribute port_location of SW2(0) : label is "PORT(0,7)"; + +attribute port_location of Differential_In_1(0) : label is "PORT(2,0)"; +attribute port_location of Differential_In_2(0) : label is "PORT(2,1)"; +attribute port_location of Input_3(0) : label is "PORT(2,2)"; +attribute port_location of Input_4(0) : label is "PORT(2,3)"; +attribute port_location of Out_1(0) : label is "PORT(1,2)"; +attribute port_location of Out_2(0) : label is "PORT(1,3)"; +attribute port_location of Preamp_In_1(0) : label is "PORT(1,0)"; +attribute port_location of Preamp_In_2(0) : label is "PORT(1,5)"; +attribute port_location of Inv_1(0) : label is "PORT(1,1)"; +attribute port_location of Inv_2(0) : label is "PORT(1,4)"; +-- PSoC Clock Editor +-- Directives Editor +-- Analog Device Editor diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.cycdx b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.cycdx new file mode 100644 index 0000000..cfa1a33 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.cycdx @@ -0,0 +1,736 @@ + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.cyfit b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.cyfit new file mode 100644 index 0000000000000000000000000000000000000000..66d23265a63023b4549c4f9be7a044fa0071aa7d GIT binary patch literal 134062 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zxm?!%TnEaJ6@O~{uhhf;1N?Lc@^Xs*hUQ(n(*Kzq;s3n<5d!>AN)rCDfrXj8xq*|3 zu(ij(L5#&yRCy;rfcRmEe;IG`A5c*E-@v~GAOBMmPb=WRe`hUm6f8+n|+5dwF ffc`K1|Mv6pQlMb}WI_CSjr}x%8StNG4e);en9VUh literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.dsf b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.dsf new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.pci b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.pci new file mode 100644 index 0000000..1f9e108 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.pci @@ -0,0 +1,12 @@ +# ADC-UART +# 2020-07-17 08:59:52Z + +# IO_2@[IOP=(3)][IoId=(2)] is reserved: SWDDebugEnabled +dont_use_io iocell 3 2 +# IO_3@[IOP=(3)][IoId=(3)] is reserved: SWDDebugEnabled +dont_use_io iocell 3 3 +set_location "ClockGenBlock" m0s8clockgenblockcell -1 -1 0 +set_io "LED(0)" iocell 1 6 +set_io "\UART:tx(0)\" iocell 4 1 +set_io "Input_1(0)" iocell 2 3 +set_location "\ADC:cy_psoc4_sar\" p4sarcell -1 -1 0 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.pco b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.pco new file mode 100644 index 0000000..55dba3d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.pco @@ -0,0 +1,15 @@ +# ADC-UART +# 2020-07-17 08:59:53Z + +# IO_2@[IOP=(3)][IoId=(2)] is reserved: SWDDebugEnabled +dont_use_io iocell 3 2 +# IO_3@[IOP=(3)][IoId=(3)] is reserved: SWDDebugEnabled +dont_use_io iocell 3 3 +set_location "ClockGenBlock" m0s8clockgenblockcell -1 -1 0 +set_location "ClockBlock" m0s8clockblockcell -1 -1 0 +set_io "LED(0)" iocell 1 6 +set_io "\UART:tx(0)\" iocell 4 1 +set_io "Input_1(0)" iocell 2 3 +set_location "\UART:SCB\" m0s8scbcell -1 -1 0 +set_location "\ADC:IRQ\" interrupt -1 -1 14 +set_location "\ADC:cy_psoc4_sar\" p4sarcell -1 -1 0 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.plc_log b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.plc_log new file mode 100644 index 0000000..a891b4f --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.plc_log @@ -0,0 +1,3 @@ +I2659: No Constrained paths were found. The placer will run in non-timing driven mode. +I2076: Total run-time: 0.2 sec. + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.route b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.route new file mode 100644 index 0000000..23cba46 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.route @@ -0,0 +1,17 @@ +net ClockBlock_HFCLK + term ":m0s8clockblockcell.hfclk" + switch ":m0s8clockblockcell.hfclk==>:interrupt_14.clock" + term ":interrupt_14.clock" +end ClockBlock_HFCLK +net \ADC:Net_3112\ + term ":p4sarcell.irq" + switch ":p4sarcell.irq==>:interrupt_idmux_14.in_0" + switch ":interrupt_idmux_14.interrupt_idmux_14__out==>:interrupt_14.interrupt" + term ":interrupt_14.interrupt" +end \ADC:Net_3112\ +net \UART:tx_wire\ + term ":m0s8scbcell_0.uart_tx" + switch ":m0s8scbcell_0.uart_tx==>:ioport4:hsiom_out1.fixed_ACT_1" + switch ":ioport4:hsiom_out1.hsiom1_out==>:ioport4:pin1.pin_input" + term ":ioport4:pin1.pin_input" +end \UART:tx_wire\ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.rpt b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.rpt new file mode 100644 index 0000000..6565bf3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.rpt @@ -0,0 +1,830 @@ +Loading plugins phase: Elapsed time ==> 0s.198ms + +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -d CY8C4245AXI-483 -s D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE + + + +Elaboration phase: Elapsed time ==> 1s.872ms + + +HDL generation phase: Elapsed time ==> 0s.056ms + + + | | | | | | | + _________________ + -| |- + -| |- + -| |- + -| CYPRESS |- + -| |- + -| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41 + -| |- Copyright (C) 1991-2001 Cypress Semiconductor + |_______________| + | | | | | | | + +====================================================================== +Compiling: ADC-UART.v +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 ADC-UART.v -verilog +====================================================================== + +====================================================================== +Compiling: ADC-UART.v +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 ADC-UART.v -verilog +====================================================================== + +====================================================================== +Compiling: ADC-UART.v +Program : vlogfe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 -verilog ADC-UART.v +====================================================================== + +vlogfe V6.3 IR 41: Verilog parser +Fri Jul 17 10:59:50 2020 + + +====================================================================== +Compiling: ADC-UART.v +Program : vpp +Options : -yv2 -q10 ADC-UART.v +====================================================================== + +vpp V6.3 IR 41: Verilog Pre-Processor +Fri Jul 17 10:59:50 2020 + +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v' + +vpp: No errors. + +Library 'work' => directory 'lcpsoc3' +General_symbol_table +General_symbol_table +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Using control file 'ADC-UART.ctl'. + +vlogfe: No errors. + + +====================================================================== +Compiling: ADC-UART.v +Program : tovif +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 -verilog ADC-UART.v +====================================================================== + +tovif V6.3 IR 41: High-level synthesis +Fri Jul 17 10:59:51 2020 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'. + +tovif: No errors. + + +====================================================================== +Compiling: ADC-UART.v +Program : topld +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -dcpsoc3 -verilog ADC-UART.v +====================================================================== + +topld V6.3 IR 41: Synthesis and optimization +Fri Jul 17 10:59:51 2020 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\codegentemp\ADC-UART.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. + +---------------------------------------------------------- +Detecting unused logic. +---------------------------------------------------------- + User names + \UART:Net_1257\ + \UART:uncfg_rx_irq\ + \UART:Net_1099\ + \UART:Net_1258\ + Net_647 + Net_656 + Net_657 + Net_658 + Net_659 + Net_660 + Net_661 + Net_662 + Net_646 + Net_674 + \ADC:Net_3125\ + \ADC:Net_3126\ + + +Deleted 16 User equations/components. +Deleted 0 Synthesized equations/components. + +------------------------------------------------------ +Alias Detection +------------------------------------------------------ +Aliasing one to tmpOE__LED_net_0 +Aliasing \UART:select_s_wire\ to zero +Aliasing \UART:rx_wire\ to zero +Aliasing \UART:sclk_s_wire\ to zero +Aliasing \UART:mosi_s_wire\ to zero +Aliasing \UART:miso_m_wire\ to zero +Aliasing \UART:tmpOE__tx_net_0\ to tmpOE__LED_net_0 +Aliasing \UART:cts_wire\ to zero +Aliasing tmpOE__Input_1_net_0 to tmpOE__LED_net_0 +Aliasing \ADC:Net_3107\ to zero +Aliasing \ADC:Net_3106\ to zero +Aliasing \ADC:Net_3105\ to zero +Aliasing \ADC:Net_3104\ to zero +Aliasing \ADC:Net_3103\ to zero +Aliasing \ADC:Net_3207_1\ to zero +Aliasing \ADC:Net_3207_0\ to zero +Aliasing \ADC:Net_3235\ to zero +Removing Lhs of wire one[7] = tmpOE__LED_net_0[1] +Removing Lhs of wire \UART:select_s_wire\[11] = zero[2] +Removing Lhs of wire \UART:rx_wire\[12] = zero[2] +Removing Lhs of wire \UART:Net_1170\[15] = \UART:Net_847\[10] +Removing Lhs of wire \UART:sclk_s_wire\[16] = zero[2] +Removing Lhs of wire \UART:mosi_s_wire\[17] = zero[2] +Removing Lhs of wire \UART:miso_m_wire\[18] = zero[2] +Removing Lhs of wire \UART:tmpOE__tx_net_0\[20] = tmpOE__LED_net_0[1] +Removing Lhs of wire \UART:cts_wire\[28] = zero[2] +Removing Lhs of wire tmpOE__Input_1_net_0[59] = tmpOE__LED_net_0[1] +Removing Lhs of wire \ADC:Net_3107\[137] = zero[2] +Removing Lhs of wire \ADC:Net_3106\[138] = zero[2] +Removing Lhs of wire \ADC:Net_3105\[139] = zero[2] +Removing Lhs of wire \ADC:Net_3104\[140] = zero[2] +Removing Lhs of wire \ADC:Net_3103\[141] = zero[2] +Removing Lhs of wire \ADC:Net_17\[183] = \ADC:Net_1845\[68] +Removing Lhs of wire \ADC:Net_3207_1\[205] = zero[2] +Removing Lhs of wire \ADC:Net_3207_0\[206] = zero[2] +Removing Lhs of wire \ADC:Net_3235\[207] = zero[2] + +------------------------------------------------------ +Aliased 0 equations, 19 wires. +------------------------------------------------------ + +---------------------------------------------------------- +Circuit simplification +---------------------------------------------------------- + +Substituting virtuals - pass 1: + + +---------------------------------------------------------- +Circuit simplification results: + + Expanded 0 signals. + Turned 0 signals into soft nodes. + Maximum default expansion cost was set at 3. +---------------------------------------------------------- + +topld: No errors. + +CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp +Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya "-.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj" -dcpsoc3 ADC-UART.v -verilog + +Warp synthesis phase: Elapsed time ==> 2s.101ms + + +cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Friday, 17 July 2020 10:59:51 +Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj -d CY8C4245AXI-483 ADC-UART.v -verilog + + +Design parsing phase: Elapsed time ==> 0s.009ms + + + +Info: mpr.M0053: Information from the design wide resources Pin Editor has overridden the control file entry for "\UART:tx(0)\". (App=cydsfit) + + Fixed Function Clock 7: Automatic-assigning clock 'ADC_intClock'. Signal=\ADC:Net_1845_ff7\ + Fixed Function Clock 2: Automatic-assigning clock 'UART_SCBCLK'. Signal=\UART:Net_847_ff2\ + + + +ADD: pft.M0040: information: The following 1 pin(s) will be assigned a location by the fitter: Input_1(0) + + +Removing unused cells resulting from optimization +Done removing unused cells. + + + + + + + +------------------------------------------------------------ +Design Equations +------------------------------------------------------------ + + + ------------------------------------------------------------ + Pin listing + ------------------------------------------------------------ + + Pin : Name = LED(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: OPEN_DRAIN_LO + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(0)__PA , + annotation => Net_644 , + pad => LED(0)_PAD ); + Properties: + { + port_location = "PORT(1,6)" + } + + Pin : Name = \UART:tx(0)\ + Attributes: + In Group/Port: True + In Sync Option: NOSYNC + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: CMOS + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => \UART:tx(0)\__PA , + pin_input => \UART:tx_wire\ , + pad => \UART:tx(0)_PAD\ ); + Properties: + { + port_location = "PORT(0,5)" + } + + Pin : Name = Input_1(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: HI_Z_ANALOG + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: True + Can contain Digital: False + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: ANALOG + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Input_1(0)__PA , + analog_term => Net_563 , + pad => Input_1(0)_PAD ); + + + + + + + + + + + + + + + + + + + + ------------------------------------------------------------ + Interrupt listing + ------------------------------------------------------------ + + interrupt: Name =\ADC:IRQ\ + PORT MAP ( + interrupt => \ADC:Net_3112\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + + + +------------------------------------------------------------ +Technology mapping summary +------------------------------------------------------------ + +Resource Type : Used : Free : Max : % Used +============================================================ +Digital Clocks : 0 : 4 : 4 : 0.00 % +Interrupts : 1 : 31 : 32 : 3.13 % +IO : 5 : 31 : 36 : 13.89 % +Segment LCD : 0 : 1 : 1 : 0.00 % +CapSense : 0 : 1 : 1 : 0.00 % +Die Temp : 0 : 1 : 1 : 0.00 % +Serial Communication (SCB) : 1 : 1 : 2 : 50.00 % +Timer/Counter/PWM : 0 : 4 : 4 : 0.00 % +UDB : : : : + Macrocells : 0 : 32 : 32 : 0.00 % + Unique P-terms : 0 : 64 : 64 : 0.00 % + Total P-terms : 0 : : : + Datapath Cells : 0 : 4 : 4 : 0.00 % + Status Cells : 0 : 4 : 4 : 0.00 % + Control Cells : 0 : 4 : 4 : 0.00 % +Comparator/Opamp : 0 : 2 : 2 : 0.00 % +LP Comparator : 0 : 2 : 2 : 0.00 % +SAR ADC : 1 : 0 : 1 : 100.00 % +DAC : : : : + 7-bit IDAC : 0 : 1 : 1 : 0.00 % + 8-bit IDAC : 0 : 1 : 1 : 0.00 % + +Technology Mapping: Elapsed time ==> 0s.011ms +Tech Mapping phase: Elapsed time ==> 0s.032ms + + + + + +Cell : Block +========================================================================= +LED(0) : [IOP=(1)][IoId=(6)] +\UART:tx(0)\ : [IOP=(4)][IoId=(1)] +ClockGenBlock : CLK_GEN_[FFB(CLK_GEN,0)] +\UART:SCB\ : SCB_[FFB(SCB,0)] +\ADC:cy_psoc4_sar\ : SARADC_[FFB(SARADC,0)] +Input_1(0) : [IOP=(2)][IoId=(0)] + + + + +Elapsed time ==> 0.1269260s + +Analog Placement phase: Elapsed time ==> 0s.262ms + + + +Route success=True, Iterations=1 Elapsed=0.0020510 secs + +Analog Routing phase: Elapsed time ==> 0s.002ms + + +============ Analog Final Answer Routes ============ +Dump of CyAnalogRoutingResultsDB +Map of net to items { + Net: Net_563 { + sarmux_vplus + SARMUX0_sw3 + p2_3 + } + Net: \ADC:Net_3113\ { + } + Net: \ADC:mux_bus_minus_0\ { + } + Net: \ADC:mux_bus_minus_1\ { + } + Net: \ADC:mux_bus_plus_1\ { + } +} +Map of item to net { + sarmux_vplus -> Net_563 + SARMUX0_sw3 -> Net_563 + p2_3 -> Net_563 +} +Mux Info { +} +Analog Code Generation phase: Elapsed time ==> 0s.018ms + + + +I2659: No Constrained paths were found. The placer will run in non-timing driven mode. +I2076: Total run-time: 0.2 sec. + + + + +No PLDs were packed. + +PLD Packing: Elapsed time ==> 0s.000ms + + + +Initial Partitioning Summary not displayed at this verbose level. + +Final Partitioning Summary not displayed at this verbose level. +Partitioning: Elapsed time ==> 0s.007ms + + + +------------------------------------------------------------ +Final Placement Summary +------------------------------------------------------------ + + Resource Type : Count : Avg Inputs : Avg Outputs + ======================================================== + UDB : 0 : 0.00 : 0.00 + + + +------------------------------------------------------------ +Component Placement Details +------------------------------------------------------------ +UDB [UDB=(0,0)] is empty. +UDB [UDB=(0,1)] is empty. +UDB [UDB=(1,0)] is empty. +UDB [UDB=(1,1)] is empty. +Intr container @ [IntrContainer=(0)]: + Intr@ [IntrContainer=(0)][IntrId=(14)] + interrupt: Name =\ADC:IRQ\ + PORT MAP ( + interrupt => \ADC:Net_3112\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } +Port 0 contains the following IO cells: +Port 1 contains the following IO cells: +[IoId=6]: +Pin : Name = LED(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: OPEN_DRAIN_LO + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(0)__PA , + annotation => Net_644 , + pad => LED(0)_PAD ); + Properties: + { + port_location = "PORT(1,6)" + } + +Port 2 contains the following IO cells: +[IoId=3]: +Pin : Name = Input_1(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: HI_Z_ANALOG + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: True + Can contain Digital: False + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: ANALOG + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Input_1(0)__PA , + analog_term => Net_563 , + pad => Input_1(0)_PAD ); + Properties: + { + } + +Port 3 contains the following IO cells: +Port 4 contains the following IO cells: +[IoId=1]: +Pin : Name = \UART:tx(0)\ + Attributes: + In Group/Port: True + In Sync Option: NOSYNC + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: CMOS + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => \UART:tx(0)\__PA , + pin_input => \UART:tx_wire\ , + pad => \UART:tx(0)_PAD\ ); + Properties: + { + port_location = "PORT(0,5)" + } + +ARM group 0: empty +Clock group 0: + Clock Block @ F(Clock,0): + m0s8clockblockcell: Name =ClockBlock + PORT MAP ( + hfclk => ClockBlock_HFCLK , + imo => ClockBlock_IMO , + ext => ClockBlock_EXTCLK , + sysclk => ClockBlock_SYSCLK , + ilo => ClockBlock_ILO , + lfclk => ClockBlock_LFCLK , + dsi_in_0 => ClockBlock_Routed1 , + ff_div_7 => \ADC:Net_1845_ff7\ , + ff_div_2 => \UART:Net_847_ff2\ ); + Properties: + { + } +LCD group 0: empty +PICU group 0: empty +LPCOMP group 0: empty +SCB group 0: + SCB Block @ F(SCB,0): + m0s8scbcell: Name =\UART:SCB\ + PORT MAP ( + clock => \UART:Net_847_ff2\ , + interrupt => Net_648 , + uart_tx => \UART:tx_wire\ , + uart_rts => \UART:rts_wire\ , + mosi_m => \UART:mosi_m_wire\ , + select_m_3 => \UART:select_m_wire_3\ , + select_m_2 => \UART:select_m_wire_2\ , + select_m_1 => \UART:select_m_wire_1\ , + select_m_0 => \UART:select_m_wire_0\ , + sclk_m => \UART:sclk_m_wire\ , + miso_s => \UART:miso_s_wire\ , + tr_tx_req => Net_671 , + tr_rx_req => Net_670 ); + Properties: + { + cy_registers = "" + scb_mode = 2 + } +CSD group 0: empty +CSIDAC8 group 0: empty +CSIDAC7 group 0: empty +TCPWM group 0: empty +OA group 0: empty +TEMP group 0: empty +SARADC group 0: + SAR ADC @ F(SARADC,0): + p4sarcell: Name =\ADC:cy_psoc4_sar\ + PORT MAP ( + vplus => Net_563 , + vminus => \ADC:mux_bus_minus_0\ , + vref => \ADC:Net_3113\ , + ext_vref => \ADC:Net_3225\ , + clock => \ADC:Net_1845_ff7\ , + sample_done => Net_666 , + chan_id_valid => \ADC:Net_3108\ , + chan_id_3 => \ADC:Net_3109_3\ , + chan_id_2 => \ADC:Net_3109_2\ , + chan_id_1 => \ADC:Net_3109_1\ , + chan_id_0 => \ADC:Net_3109_0\ , + data_valid => \ADC:Net_3110\ , + data_11 => \ADC:Net_3111_11\ , + data_10 => \ADC:Net_3111_10\ , + data_9 => \ADC:Net_3111_9\ , + data_8 => \ADC:Net_3111_8\ , + data_7 => \ADC:Net_3111_7\ , + data_6 => \ADC:Net_3111_6\ , + data_5 => \ADC:Net_3111_5\ , + data_4 => \ADC:Net_3111_4\ , + data_3 => \ADC:Net_3111_3\ , + data_2 => \ADC:Net_3111_2\ , + data_1 => \ADC:Net_3111_1\ , + data_0 => \ADC:Net_3111_0\ , + eos_intr => Net_667 , + irq => \ADC:Net_3112\ ); + Properties: + { + cy_registers = "" + } +CLK_GEN group 0: + M0S8 Clock Gen Block @ F(CLK_GEN,0): + m0s8clockgenblockcell: Name =ClockGenBlock + PORT MAP ( + ); + Properties: + { + } +LPCOMPBLOCK group 0: empty +PASSBLOCK group 0: empty +WCO group 0: empty +SRSS group 0: empty +CPUSS group 0: empty +EXCO group 0: empty + + + +------------------------------------------------------------ +Port Configuration report +------------------------------------------------------------ + | | | Interrupt | | | +Port | Pin | Fixed | Type | Drive Mode | Name | Connections +-----+-----+-------+-----------+------------------+--------------+------------------- + 1 | 6 | * | NONE | OPEN_DRAIN_LO | LED(0) | +-----+-----+-------+-----------+------------------+--------------+------------------- + 2 | 3 | | NONE | HI_Z_ANALOG | Input_1(0) | Analog(Net_563) +-----+-----+-------+-----------+------------------+--------------+------------------- + 4 | 1 | * | NONE | CMOS_OUT | \UART:tx(0)\ | In(\UART:tx_wire\) +------------------------------------------------------------------------------------- + + + +Digital component placer commit/Report: Elapsed time ==> 0s.005ms +Digital Placement phase: Elapsed time ==> 0s.876ms + + +"C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/route_arch-rrg.cydata" --vh2-path "ADC-UART_r.vh2" --pcf-path "ADC-UART.pco" --des-name "ADC-UART" --dsf-path "ADC-UART.dsf" --sdc-path "ADC-UART.sdc" --lib-path "ADC-UART_r.lib" +Routing successful. +Digital Routing phase: Elapsed time ==> 0s.748ms + + +Bitstream Generation phase: Elapsed time ==> 0s.160ms + + +Bitstream Verification phase: Elapsed time ==> 0s.019ms + + +Timing report is in ADC-UART_timing.html. +Static timing analysis phase: Elapsed time ==> 0s.625ms + + +Data reporting phase: Elapsed time ==> 0s.000ms + + +Design database save phase: Elapsed time ==> 0s.145ms + +cydsfit: Elapsed time ==> 2s.953ms + +Fitter phase: Elapsed time ==> 2s.953ms +API generation phase: Elapsed time ==> 1s.480ms +Dependency generation phase: Elapsed time ==> 0s.028ms +Cleanup phase: Elapsed time ==> 0s.004ms diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.rt_log b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.rt_log new file mode 100644 index 0000000..b26f33a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.rt_log @@ -0,0 +1,22 @@ + + SoftJin Router, Version 1.0 + +I1203: Reading Design ADC-UART +I1204: Reading netlist from file ADC-UART_r.vh2 +I1206: Completed Reading of file ADC-UART_r.vh2 +I1204: Reading placement from file ADC-UART.pco +I1206: Completed Reading of file ADC-UART.pco +I1204: Reading timing library from file ADC-UART_r.lib +I1206: Completed Reading of file ADC-UART_r.lib +I1204: Reading timing constraints from file ADC-UART.sdc +I1206: Completed Reading of file ADC-UART.sdc +I1204: Reading architecture from file C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/route_arch-rrg.cydata +I1206: Completed Reading of file C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/route_arch-rrg.cydata +I1209: Started routing +I1223: Total Nets : 3 +I1212: Iteration 1 : 0 unrouted : 0 seconds +I1215: Routing is successful +I1207: Completed routing +I1210: Writing routes +I1218: Exiting the router +I1224: Total Time : 0 seconds diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.sdc b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.sdc new file mode 100644 index 0000000..21f3368 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.sdc @@ -0,0 +1,19 @@ +# THIS FILE IS AUTOMATICALLY GENERATED +# Project: D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj +# Date: Fri, 17 Jul 2020 08:59:54 GMT +#set_units -time ns +create_clock -name {ADC_intClock(FFB)} -period 1000 -waveform {0 500} [list [get_pins {ClockBlock/ff_div_7}]] +create_clock -name {UART_SCBCLK(FFB)} -period 13041.666666666666 -waveform {0 6520.83333333333} [list [get_pins {ClockBlock/ff_div_2}]] +create_clock -name {CyRouted1} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/dsi_in_0}]] +create_clock -name {CyILO} -period 31250 -waveform {0 15625} [list [get_pins {ClockBlock/ilo}]] +create_clock -name {CyLFCLK} -period 31250 -waveform {0 15625} [list [get_pins {ClockBlock/lfclk}]] +create_clock -name {CyIMO} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/imo}]] +create_clock -name {CyHFCLK} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/hfclk}]] +create_clock -name {CySYSCLK} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/sysclk}]] +create_generated_clock -name {ADC_intClock} -source [get_pins {ClockBlock/hfclk}] -edges {1 25 49} [list] +create_generated_clock -name {UART_SCBCLK} -source [get_pins {ClockBlock/hfclk}] -edges {1 313 627} [list] + + +# Component constraints for D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\TopDesign\TopDesign.cysch +# Project: D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj +# Date: Fri, 17 Jul 2020 08:59:49 GMT diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.sdf b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.sdf new file mode 100644 index 0000000..3cee1cb --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.sdf @@ -0,0 +1,27 @@ +(DELAYFILE + (SDFVERSION "IEEE 1497 4.0") + (DATE "2020-07-17T08:59:54Z") + (DESIGN "ADC-UART") + (VENDOR "Cypress Semiconductor") + (PROGRAM "PSoC Creator") + (VERSION " 4.2") + (DIVIDER .) + (TIMESCALE 1 ns) + (CELL + (CELLTYPE "ADC-UART") + (INSTANCE *) + (DELAY + (ABSOLUTE + (INTERCONNECT ClockBlock.hfclk \\ADC\:IRQ\\.clock (0.000:0.000:0.000)) + (INTERCONNECT ClockBlock.ff_div_7 \\ADC\:cy_psoc4_sar\\.clock (0.000:0.000:0.000)) + (INTERCONNECT \\ADC\:cy_psoc4_sar\\.irq \\ADC\:IRQ\\.interrupt (1.000:1.000:1.000)) + (INTERCONNECT ClockBlock.ff_div_2 \\UART\:SCB\\.clock (0.000:0.000:0.000)) + (INTERCONNECT \\UART\:tx\(0\)\\.pad_out \\UART\:tx\(0\)\\.pad_in (0.000:0.000:0.000)) + (INTERCONNECT \\UART\:SCB\\.uart_tx \\UART\:tx\(0\)\\.pin_input (0.000:0.000:0.000)) + (INTERCONNECT LED\(0\)_PAD LED\(0\).pad_in (0.000:0.000:0.000)) + (INTERCONNECT \\UART\:tx\(0\)\\.pad_out \\UART\:tx\(0\)_PAD\\ (0.000:0.000:0.000)) + (INTERCONNECT \\UART\:tx\(0\)_PAD\\ \\UART\:tx\(0\)\\.pad_in (0.000:0.000:0.000)) + ) + ) + ) +) diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.svd b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.svd new file mode 100644 index 0000000..c545640 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.svd @@ -0,0 +1,4030 @@ + + + CY8C4245AXI_483 + 0.1 + PSoC 4200 + 8 + 32 + + + ADC + Sequencing SAR ADC + 0x0 + + 0 + 0x0 + registers + + + + CTRL + Analog control register + 0x401A0000 + 32 + read-write + 0 + 0 + + + VREF_SEL + SARADC internal VREF selection + 4 + 6 + read-write + + + VREF_BYP_CAP_EN + VREF bypass cap enable for when VREF buffer is on + 7 + 7 + read-write + + + NEG_SEL + SARADC internal NEG selection for Single ended conversion + 9 + 11 + read-write + + + SAR_HW_CTRL_NEGVREF + Hardware control: 0=firmware, 1=hardware. + 13 + 13 + read-write + + + PWR_CTRL_VREF + VREF buffer low power mode. + 14 + 15 + read-write + + + SPARE + Spare controls + 16 + 19 + read-write + + + ICONT_LV + SARADC low power mode + 24 + 25 + read-write + + + DSI_SYNC_CONFIG + Synchronize the DSI config signals to peripheral clock domain + 28 + 28 + read-write + + + DSI_MODE + SAR sequencer takes configuration from DSI signals + 29 + 29 + read-write + + + SWITCH_DISABLE + Disable SAR sequencer from enabling routing switches + 30 + 30 + read-write + + + ENABLED + 0: SAR IP disabled, 1: SAR IP enabled. + 31 + 31 + read-write + + + + + SAMPLE_CTRL + Sample control register + 0x401A0004 + 32 + read-write + 0 + 0 + + + SUB_RESOLUTION + Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit). + 0 + 0 + read-write + + + LEFT_ALIGN + Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. + 1 + 1 + read-write + + + SINGLE_ENDED_SIGNED + Output data from a single ended conversion as a signed value + 2 + 2 + read-write + + + DIFFERENTIAL_SIGNED + Output data from a differential conversion as a signed value + 3 + 3 + read-write + + + AVG_CNT + Averaging Count for channels that have over sampling enabled + 4 + 6 + read-write + + + AVG_SHIFT + Averaging shifting: after averaging the result is shifted right to fit in the sample resolution, i.e. 12 bits. + 7 + 7 + read-write + + + CONTINUOUS + 0: Wait for next FW_TRIGGER or hardware trigger before scanning enabled channels. 1: Continuously scan enabled channels.. + 16 + 16 + read-write + + + DSI_TRIGGER_EN + 0: firmware trigger only, 1: enable hardware (DSI) trigger. + 17 + 17 + read-write + + + DSI_TRIGGER_LEVEL + 0: DSI trigger signal is a pulse input, 1: DSI trigger signal is a level inpu.t + 18 + 18 + read-write + + + DSI_SYNC_TRIGGER + 0: bypass clock domain synchronisation of the DSI trigger signal, 1: synchronize the DSI trigger signal to the SAR clock domain. + 19 + 19 + read-write + + + EOS_DSI_OUT_EN + Enable to output EOS_INTR to DSI + 31 + 31 + read-write + + + + + SAMPLE_TIME01 + Sample time specification ST0 and ST1 + 0x401A0010 + 32 + read-write + 0 + 0 + + + SAMPLE_TIME0 + Sample time0 (aperture) in ADC clock cycles + 0 + 9 + read-write + + + SAMPLE_TIME1 + Sample time1 + 16 + 25 + read-write + + + + + SAMPLE_TIME23 + Sample time specification ST2 and ST3 + 0x401A0014 + 32 + read-write + 0 + 0 + + + SAMPLE_TIME2 + Sample time2 + 0 + 9 + read-write + + + SAMPLE_TIME3 + Sample time3 + 16 + 25 + read-write + + + + + RANGE_THRES + Global range detect threshold register + 0x401A0018 + 32 + read-write + 0 + 0 + + + RANGE_LOW + Low threshold for range detect + 0 + 15 + read-write + + + RANGE_HIGH + High threshold for range detect + 16 + 31 + read-write + + + + + RANGE_COND + Global range detect mode register + 0x401A001C + 32 + read-write + 0 + 0 + + + RANGE_COND + Range condition select + 30 + 31 + read-write + + + + + CHAN_EN + Enable bits for the channels + 0x401A0020 + 32 + read-write + 0 + 0 + + + CHAN_EN + Channel enable. 0: the corresponding channel is disabled. 1: the corresponding channel is enabled, it will be included in the next scan. + 0 + 15 + read-write + + + + + START_CTRL + Start control register (firmware trigger) + 0x401A0024 + 32 + read-write + 0 + 0 + + + FW_TRIGGER + When firmware writes a 1 here it will trigger the next scan of enabled channels + 0 + 0 + read-write + + + + + DFT_CTRL + DFT control register + 0x401A0030 + 32 + read-write + 0 + 0 + + + CHAN_CONFIG0 + Channel0 configuration register + 0x401A0080 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG1 + Channel1 configuration register + 0x401A0084 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG2 + Channel2 configuration register + 0x401A0088 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG3 + Channel3 configuration register + 0x401A008C + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG4 + Channel4 configuration register + 0x401A0090 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG5 + Channel5 configuration register + 0x401A0094 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG6 + Channel6 configuration register + 0x401A0098 + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_CONFIG7 + Channel7 configuration register + 0x401A009C + 32 + read-write + 0 + 0 + + + PIN_ADDR + Address of the pin to be sampled by this channel + 0 + 2 + read-write + + + PORT_ADDR + Address of the port that contains the pin to be sampled by this channel + 4 + 6 + read-write + + + DIFFERENTIAL_EN + Differential enable for this channel + 8 + 8 + read-write + + + RESOLUTION + Resolution for this channel + 9 + 9 + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s). + 10 + 10 + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel. + 12 + 13 + read-write + + + DSI_OUT_EN + DSI data output enable for this channel + 31 + 31 + read-write + + + + + CHAN_WORK0 + Channel0 working data register + 0x401A0100 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK1 + Channel1 working data register + 0x401A0104 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK2 + Channel2 working data register + 0x401A0108 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK3 + Channel3 working data register + 0x401A010C + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK4 + Channel4 working data register + 0x401A0110 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK5 + Channel5 working data register + 0x401A0114 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK6 + Channel6 working data register + 0x401A0118 + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_WORK7 + Channel7 working data register + 0x401A011C + 32 + read-write + 0 + 0 + + + WORK + SAR conversion working data of the channel + 0 + 15 + read-only + + + CHAN_WORK_VALID_MIR + Mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register + 31 + 31 + read-only + + + + + CHAN_RESULT0 + Channel0 result data register + 0x401A0180 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT1 + Channel1 result data register + 0x401A0184 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT2 + Channel2 result data register + 0x401A0188 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT3 + Channel3 result data register + 0x401A018C + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT4 + Channel4 result data register + 0x401A0190 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT5 + Channel5 result data register + 0x401A0194 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT6 + Channel6 result data register + 0x401A0198 + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_RESULT7 + Channel7 result data register + 0x401A019C + 32 + read-write + 0 + 0 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + 0 + 15 + read-only + + + SATURATE_INTR_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 29 + 29 + read-only + + + RANGE_INTR_MIR + Mirror bit of corresponding bit in SAR_RANGE_INTR register + 30 + 30 + read-only + + + CHAN_RESULT_VALID_MIR + Mirror bit of corresponding bit in SAR_SATURATE_INTR register + 31 + 31 + read-only + + + + + CHAN_WORK_VALID + Channel working data register valid bits + 0x401A0200 + 32 + read-write + 0 + 0 + + + CHAN_WORK_VALID + If set the corresponding WORK data is valid, i.e. was already sampled during the current scan. + 0 + 15 + read-only + + + + + CHAN_RESULT_VALID + Channel result data register valid bits + 0x401A0204 + 32 + read-write + 0 + 0 + + + CHAN_RESULT_VALID + If set the corresponding RESULT data is valid, i.e. was sampled during the last scan. + 0 + 15 + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x401A0208 + 32 + read-write + 0 + 0 + + + AVG_STAT + Current averaging status (for debug) + 0x401A020C + 32 + read-write + 0 + 0 + + + INTR + Interrupt request register + 0x401A0210 + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + INTR_SET + Not really a register, intended for verification/debug. When read, this register reflects the interrupt request register. + 0x401A0214 + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + INTR_MASK + Interrupt mask register + 0x401A0218 + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x401A021C + 32 + read-write + 0 + 0 + + + EOS_INTR + End Of Scan Interrupt + 0 + 0 + read-write + + + OVERFLOW_INTR + Overflow Interrupt + 1 + 1 + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt + 2 + 2 + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt + 3 + 3 + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt + 4 + 4 + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt + 5 + 5 + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt + 6 + 6 + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt + 7 + 7 + read-write + + + + + SATURATE_INTR + Saturate interrupt request register + 0x401A0220 + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + SATURATE_INTR_SET + Saturate interrupt set request register + 0x401A0224 + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + SATURATE_INTR_MASK + Saturate interrupt mask register + 0x401A0228 + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + SATURATE_INTR_MASKED + Saturate interrupt masked request register + 0x401A022C + 32 + read-write + 0 + 0 + + + SATURATE_INTR + Saturate Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR + Range detect interrupt request register + 0x401A0230 + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR_SET + Range detect interrupt set request register + 0x401A0234 + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR_MASK + Range detect interrupt mask register + 0x401A0238 + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + RANGE_INTR_MASKED + Range interrupt masked request register + 0x401A023C + 32 + read-write + 0 + 0 + + + RANGE_INTR + Range detect Interrupt + 0 + 15 + read-write + + + + + INTR_CAUSE + Interrupt cause register + 0x401A0240 + 32 + read-write + 0 + 0 + + + MUX_SWITCH0 + SARMUX Firmware switch controls + 0x401A0300 + 32 + read-write + 0 + 0 + + + MUX_SWITCH_CLEAR0 + SARMUX Firmware switch control clear + 0x401A0304 + 32 + read-write + 0 + 0 + + + MUX_SWITCH1 + SARMUX Firmware switch controls + 0x401A0308 + 32 + read-write + 0 + 0 + + + MUX_SWITCH_CLEAR1 + SARMUX Firmware switch control clear + 0x401A030C + 32 + read-write + 0 + 0 + + + MUX_SWITCH_HW_CTRL + SARMUX switch hardware control + 0x401A0340 + 32 + read-write + 0 + 0 + + + MUX_SWITCH_STATUS + SARMUX switch status + 0x401A0348 + 32 + read-write + 0 + 0 + + + PUMP_CTRL + Switch pump control + 0x401A0380 + 32 + read-write + 0 + 0 + + + ANA_TRIM + Analog trim register + 0x401A0F00 + 32 + read-write + 0 + 0 + + + WOUNDING + SAR wounding register + 0x401A0F04 + 32 + read-write + 0 + 0 + + + WOUND_RESOLUTION + Maximum SAR resolution allowed + 0 + 1 + read-only + + + + + + + UART + Serial Communication Block + 0x0 + + 0 + 0x0 + registers + + + + Cy_CTRL + Generic control register + 0x40060000 + 32 + read-write + 0 + 0 + + + OVS + Serial interface bit period oversampling factor expressed in lP clock cycles. Used for SPI and UART functionality. OVS + 1 IP clock cycles constitute a single serial interface clock/bit cycle. + 0 + 3 + read-write + + + EC_AM_MODE + Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI).In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. + 8 + 8 + read-write + + + EC_OP_MODE + Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. + 9 + 9 + read-write + + + EZ_MODE + Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. + 10 + 10 + read-write + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').his field is used in the I2C mode. + 16 + 16 + read-write + + + BLOCK + If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0') + 17 + 17 + read-write + + + MODE + Mode of operation: I2C = 0, SPI = 1, UART = 2 + 24 + 25 + read-write + + + ENABLED + IP enabled ('1') or not ('0'). + 31 + 31 + read-write + + + + + Cy_SPI_CTRL + SPI control register + 0x40060020 + 32 + read-write + 0 + 0 + + + CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). + 0 + 0 + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. + 1 + 1 + read-write + + + CPHA + Only applicable in SPI Motorola submode. Indicates the clock phase. + 2 + 2 + read-write + + + CPOL + Only applicable in SPI Motorola submode. Indicates the clock polarity. + 3 + 3 + read-write + + + LATE_MISO_SAMPLE + Only applicable in master mode. Changes the SCLK edge on which MISO is captured. + 4 + 4 + read-write + + + LOOPBACK + Local loopback control. + 16 + 16 + read-write + + + MODE + Submode of SPI operation: Motorola = 0, Texas Instruments = 1, National Semiconducturs = 2. + 24 + 25 + read-write + + + SLAVE_SELECT + Selects one of the four SPI slave select signals: SS0 = 0, SS1 = 1 , SS2 = 2, SS3 = 3. + 26 + 27 + read-write + + + MASTER_MODE + Master ('1') or slave ('0') mode. + 31 + 31 + read-write + + + + + Cy_SPI_STATUS + SPI status register + 0x40060024 + 32 + read-write + 0 + 0 + + + BUS_BUSY + SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction + 0 + 0 + read-only + + + + + Cy_UART_CTRL + Extended Configuration Register + 0x40060040 + 32 + read-write + 0 + 0 + + + LOOPBACK + Local loopback control. + 16 + 16 + read-write + + + MODE + Submode of UART operation: Standard = 0, Smart Card = 1, IrDA = 2. + 24 + 25 + read-write + + + + + Cy_UART_TX_CTRL + Extended Configuration Register + 0x40060044 + 32 + read-write + 0 + 0 + + + STOP_BTIS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. + 0 + 2 + read-write + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity + 4 + 4 + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware. + 5 + 5 + read-write + + + RETRY_ON_NACK + When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. + 8 + 8 + read-write + + + + + Cy_UART_RX_CTRL + Extended Configuration Register + 0x40060048 + 32 + read-write + 0 + 0 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. + 0 + 2 + read-write + + + PARITY + Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. + 4 + 4 + read-write + + + PARITY_ENABLED + Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. + 5 + 5 + read-write + + + POLARITY + Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. + 6 + 6 + read-write + + + DROP_ON_PARITY_ERR + Behaviour when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + 8 + 8 + read-write + + + DROP_ON_FRAME_ERR + Behaviour when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + 9 + 9 + read-write + + + MP_MODE + Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. + 10 + 10 + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data + 12 + 12 + read-write + + + SKIP_START + Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. + 13 + 13 + read-write + + + BREAK_WIDTH + Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. + 16 + 19 + read-write + + + + + Cy_I2C_CTRL + Slave address and mask register + 0x40060060 + 32 + read-write + 0 + 0 + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. + 0 + 3 + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period + 4 + 7 + read-write + + + M_READY_DATA_ACK + When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. + 8 + 8 + read-write + + + M_NOT_READY_DATA_NACK + When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). + 9 + 9 + read-write + + + S_GENERAL_IGNORE + When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. + 11 + 11 + read-write + + + S_READY_ADDR_ACK + When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full + 12 + 12 + read-write + + + S_READY_DATA_ACK + When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full + 13 + 13 + read-write + + + S_NOT_READY_ADDR_NACK + When '1', a received address by the slave is immediately ACK'd when the receiver FIFO is not full + 14 + 14 + read-write + + + S_NOT_READY_DATA_NACK + When '1' a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. When '1' clock stretching is performed (till the receiver FIFO is no longer full). + 15 + 15 + read-write + + + LOOPBACK + Local loopback control + 16 + 16 + read-write + + + SLAVE_MODE + Slave mode enabled ('1') or not ('0'). + 30 + 30 + read-write + + + MASTER_MODE + Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. + 31 + 31 + read-write + + + + + Cy_I2C_STATUS + Slave address and mask register + 0x40060064 + 32 + read-write + 0 + 0 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'). + 0 + 0 + read-only + + + S_READ + I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0'. + 4 + 4 + read-only + + + M_READ + I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. + 5 + 5 + read-only + + + + + Cy_I2C_M_CMD + Slave address and mask register + 0x40060068 + 32 + read-write + 0 + 0 + + + M_START + When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. When this action is performed, the hardware sets this field to '0'. + 0 + 0 + read-write + + + M_IDLE_START + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). When this action is performed, the hardware sets this field to '0'. + 1 + 1 + read-write + + + M_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + 2 + 2 + read-write + + + M_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. + 3 + 3 + read-write + + + M_STOP + When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. This command has a higher priority than I2C_M_CMD.M_START: in situations where both a STOP and a REPEATED START could be transmitted, M_STOP takes precedence over M_START. + 4 + 4 + read-write + + + + + Cy_I2C_S_CMD + I2C slave command register + 0x4006006C + 32 + read-write + 0 + 0 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + 0 + 0 + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0' + 1 + 1 + read-write + + + + + Cy_I2C_CFG + I2C control register + 0x40060070 + 32 + read-write + 0 + 0 + + + SDA_FILT_HYS + No description available + 0 + 1 + read-write + + + SDA_FILT_TRIM + No description available + 2 + 3 + read-write + + + SCL_FILT_HYS + No description available + 4 + 5 + read-write + + + SCL_FILT_TRIM + No description available + 6 + 7 + read-write + + + SDA_FILT_OUT_HYS + No description available + 8 + 8 + read-write + + + SDA_FILT_OUT_TRIM + No description available + 10 + 11 + read-write + + + SDA_FILT_HS + No description available + 16 + 16 + read-write + + + SDA_FILT_ENABLED + No description available + 17 + 17 + read-write + + + SCL_FILT_HS + No description available + 24 + 24 + read-write + + + SCL_FILT_ENABLED + No description available + 25 + 25 + read-write + + + SDA_FILT_OUT_HS + No description available + 26 + 26 + read-write + + + SDA_FILT_OUT_ENABLED + No description available + 27 + 27 + read-write + + + + + Cy_TX_CTRL + Transmitter control register + 0x40060200 + 32 + read-write + 0 + 0 + + + DATA_WIDTH + Data frame width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. + 0 + 3 + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + 8 + 8 + read-write + + + ENABLED + Transmitter enabled. + 31 + 31 + read-write + + + + + Cy_TX_FIFO_CTRL + Transmitter FIFO control register + 0x40060204 + 32 + read-write + 0 + 0 + + + TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the amount of this field, a transmitter trigger event is generated. + 0 + 2 + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + 16 + 16 + read-write + + + FREEZE + When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. + 17 + 17 + read-write + + + + + Cy_TX_FIFO_STATUS + Transmitter FIFO status register + 0x40060208 + 32 + read-write + 0 + 0 + + + USED + Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to 8. + 0 + 3 + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0') + 15 + 15 + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + 16 + 18 + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + 24 + 26 + read-only + + + + + Cy_TX_FIFO_WR + Transmitter FIFO write register + 0x40060240 + 32 + read-write + 0 + 0 + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. + 0 + 15 + write-only + + + + + Cy_RX_CTRL + Receiver control register + 0x40060300 + 32 + read-write + 0 + 0 + + + DATA_WIDTH + Data frame width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. + 0 + 3 + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). + 8 + 8 + read-write + + + MEDIAN + Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. + 9 + 9 + read-write + + + ENABLED + Receiver enabled + 31 + 31 + read-write + + + + + Cy_RX_FIFO_CTRL + Receiver FIFO control register + 0x40060304 + 32 + read-write + 0 + 0 + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the amount of this field, a receiver trigger event is generated. + 0 + 2 + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + 16 + 16 + read-write + + + FREEZE + When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. + 17 + 17 + read-write + + + + + Cy_RX_FIFO_STATUS + Receiver FIFO status registerS + 0x40060308 + 32 + read-write + 0 + 0 + + + USED + Amount of entries in the receiver FIFO. The value of this field ranges from 0 to 8. + 0 + 3 + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). + 15 + 15 + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + 16 + 18 + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + 24 + 26 + read-only + + + + + Cy_RX_MATCH + Slave address and mask register + 0x40060310 + 32 + read-write + 0 + 0 + + + ADDR + Slave device address. For UART multi-processor mode all eight bits a reused. For I2C, bit 0 of the register is not used. + 0 + 7 + read-write + + + MASK + Slave device address mask. This field is a 8 bit mask that specifies which of the ADDR field bits in the SCB_RX_MATCH_ADDR register take part in the matching of the slave address. + 16 + 23 + read-write + + + + + Cy_RX_FIFO_RD + Receiver FIFO read register + 0x40060340 + 32 + read-write + 0 + 0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO. + 0 + 15 + read-only + + + + + Cy_INTR_CAUSE + Interrupt cause register + 0x40060E00 + 32 + read-write + 0 + 0 + + + MASTER + Master interrupt active. + 0 + 0 + read-only + + + SLAVE + Slave interrupt active. + 1 + 1 + read-only + + + TX + Transmitter interrupt active. + 2 + 2 + read-only + + + RX + Receiver interrupt active. + 3 + 3 + read-only + + + I2C_EC + Externally clock I2C interrupt active. + 4 + 4 + read-only + + + SPI_EC + Externally clocked SPI interrupt active. + 5 + 5 + read-only + + + + + Cy_INTR_I2C_EC + Externally clocked I2C interrupt request register + 0x40060E80 + 32 + read-write + 0 + 0 + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). Only used when EC_AM is '1'. + 0 + 0 + read-write + + + + + Cy_INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask register + 0x40060E88 + 32 + read-write + 0 + 0 + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + + + Cy_INTR_I2C_EC_MASKED + Externally clocked SPI interrupt masked register + 0x40060E8C + 32 + read-write + 0 + 0 + + + WAKE_UP + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + + + Cy_INTR_INTR_SPI_EC + Externally clocked SPI interrupt request register + 0x40060EC0 + 32 + read-write + 0 + 0 + + + WAKE_UP + Wake up request. Active on incoming slave request when externally clocked selection is '1'. + 0 + 0 + read-write + + + + + Cy_INTR_INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask register + 0x40060EC8 + 32 + read-write + 0 + 0 + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + + + Cy_INTR_INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked register + 0x40060ECC + 32 + read-write + 0 + 0 + + + WAKE_UP + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + + + Cy_INTR_M + Master interrupt request register. + 0x40060F00 + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. + 0 + 0 + read-write + + + I2C_NACK + I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). + 1 + 1 + read-write + + + I2C_ACK + I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). + 2 + 2 + read-write + + + I2C_STOP + I2C master STOP. Set to '1', when the master has transmitted a STOP. + 4 + 4 + read-write + + + I2C_BUS_ERR + I2C master bus error (unexpected detection of START or STOP condition). + 8 + 8 + read-write + + + SPI_DONE + SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO is empty. + 9 + 9 + read-write + + + + + Cy_INTR_M_SET + Master interrupt set request register + 0x40060F04 + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_BUS_ERR + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + 9 + 9 + read-write + + + + + Cy_INTR_M_MASK + Master interrupt mask register + 0x40060F08 + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_BUS_ERR + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + 9 + 9 + read-write + + + + + Cy_INTR_M_MASKED + Master interrupt masked request register + 0x40060F0C + 32 + read-write + 0 + 0 + + + I2C_LOST_ARB + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + I2C_NACK + Logical and of corresponding request and mask bits. + 1 + 1 + read-write + + + I2C_ACK + Logical and of corresponding request and mask bits. + 2 + 2 + read-write + + + I2C_STOP + Logical and of corresponding request and mask bits. + 4 + 4 + read-write + + + I2C_BUS_ERR + Logical and of corresponding request and mask bits. + 8 + 8 + read-write + + + SPI_DONE + Logical and of corresponding request and mask bits. + 9 + 9 + read-write + + + + + Cy_INTR_S + Slave interrupt request register + 0x40060F40 + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). + 0 + 0 + read-write + + + I2C_NACK + I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). + 1 + 1 + read-write + + + I2C_ACK + I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). + 2 + 2 + read-write + + + I2C_WRITE_STOP + I2C STOP event for I2C write transfer intended for this slave (address matching is performed).Set to '1', when STOP or REPEATED START event is detected. + 3 + 3 + read-write + + + I2C_STOP + I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected + 4 + 4 + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. + 6 + 6 + read-write + + + I2C_GENERAL + I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO + 7 + 7 + read-write + + + I2C_BUS_ERR + I2C slave bus error (unexpected detection of START or STOP condition). + 8 + 8 + read-write + + + SPI_BUS_ERR + SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + 11 + 11 + read-write + + + + + Cy_INTR_S_SET + Slave interrupt set request register + 0x40060F44 + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + 3 + 3 + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + 6 + 6 + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + 7 + 7 + read-write + + + I2C_BUS_ERR + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_BUS_ERR + Write with '1' to set corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_S_MASK + Slave interrupt mask register + 0x40060F48 + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + 1 + 1 + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + 2 + 2 + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + 3 + 3 + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + 4 + 4 + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + 6 + 6 + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + 7 + 7 + read-write + + + I2C_BUS_ERR + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + SPI_BUS_ERR + Mask bit for corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_S_MASKED + Slave interrupt masked register + 0x40060F4C + 32 + read-write + 0 + 0 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + I2C_NACK + Logical and of corresponding request and mask bits. + 1 + 1 + read-write + + + I2C_ACK + Logical and of corresponding request and mask bits. + 2 + 2 + read-write + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + 3 + 3 + read-write + + + I2C_STOP + Logical and of corresponding request and mask bits. + 4 + 4 + read-write + + + I2C_START + Logical and of corresponding request and mask bits. + 5 + 5 + read-write + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + 6 + 6 + read-write + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + 7 + 7 + read-write + + + SPI_BUS_ERR + Logical and of corresponding request and mask bits. + 11 + 11 + read-write + + + + + Cy_INTR_TX + Transmitter interrupt request register + 0x40060F80 + 32 + read-write + 0 + 0 + + + TRIGGER + Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTL. + 0 + 0 + read-write + + + NOT_FULL + TX FIFO is not full. + 1 + 1 + read-write + + + EMPTY + TX FIFO is empty; i.e. it has 0 entries. + 4 + 4 + read-write + + + OVERFLOW + Attempt to write to a full TX FIFO. + 5 + 5 + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. + 6 + 6 + read-write + + + UART_NACK + UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. + 8 + 8 + read-write + + + UART_DONE + UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO; i.e. EMPTY is '1'. Set to '1', when event is detected. + 9 + 9 + read-write + + + UART_ARB_LOST + UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. + 10 + 10 + read-write + + + + + Cy_INTR_TX_SET + Transmitter interrupt set request register + 0x40060F84 + 32 + read-write + 0 + 0 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + 1 + 1 + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + 4 + 4 + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 6 + 6 + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + 9 + 9 + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + 10 + 10 + read-write + + + + + Cy_INTR_TX_MASK + Transmitter interrupt mask request register + 0x40060F88 + 32 + read-write + 0 + 0 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + 1 + 1 + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + 4 + 4 + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + 6 + 6 + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + 9 + 9 + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + 10 + 10 + read-write + + + + + Cy_INTR_TX_MASKED + Transmitter interrupt masked request register + 0x40060F8C + 32 + read-write + 0 + 0 + + + TRIGGER + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + NOT_FULL + Logical and of corresponding request and mask bits. + 1 + 1 + read-write + + + EMPTY + Logical and of corresponding request and mask bits. + 4 + 4 + read-write + + + OVERFLOW + Logical and of corresponding request and mask bits. + 5 + 5 + read-write + + + UNDERFLOW + Logical and of corresponding request and mask bits. + 6 + 6 + read-write + + + UART_NACK + Logical and of corresponding request and mask bits. + 8 + 8 + read-write + + + UART_DONE + Logical and of corresponding request and mask bits. + 9 + 9 + read-write + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + 10 + 10 + read-write + + + + + Cy_INTR_RX + Receiver interrupt request register + 0x40060FC0 + 32 + read-write + 0 + 0 + + + TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL. + 0 + 0 + read-write + + + NOT_EMPTY + RX FIFO is not empty. + 2 + 2 + read-write + + + FULL + RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. + 3 + 3 + read-write + + + OVERFLOW + Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. + 5 + 5 + read-write + + + UNDERFLOW + Attempt to read from an empty RX FIFO. + 6 + 6 + read-write + + + FRAME_ERR + Frame error in received data frame. Set to '1', when event is detected. + 8 + 8 + read-write + + + PARITY_ERR + Parity error in received data frame. Set to '1', when event is detected. + 9 + 9 + read-write + + + BAUD_DETECT + LIN baud rate detection is completed. + 10 + 10 + read-write + + + BREAK_DETECT + Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. + 11 + 11 + read-write + + + + + Cy_INTR_RX_SET + Receiver interrupt set request register + 0x40060FC4 + 32 + read-write + 0 + 0 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + 2 + 2 + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt request register. + 3 + 3 + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + 6 + 6 + read-write + + + FRAME_ERR + Write with '1' to set corresponding bit in interrupt request register. + 8 + 8 + read-write + + + PARITY_ERR + Write with '1' to set corresponding bit in interrupt request register. + 9 + 9 + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt request register. + 10 + 10 + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_RX_MASK + Receiver interrupt mask register + 0x40060FC8 + 32 + read-write + 0 + 0 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + 0 + 0 + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + 2 + 2 + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + 3 + 3 + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + 5 + 5 + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + 6 + 6 + read-write + + + FRAME_ERR + Mask bit for corresponding bit in interrupt request register. + 8 + 8 + read-write + + + PARITY_ERR + Mask bit for corresponding bit in interrupt request register. + 9 + 9 + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + 10 + 10 + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + 11 + 11 + read-write + + + + + Cy_INTR_RX_MASKED + Receiver interrupt masked register + 0x40060FCC + 32 + read-write + 0 + 0 + + + TRIGGER + Logical and of corresponding request and mask bits. + 0 + 0 + read-write + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + 2 + 2 + read-write + + + FULL + Logical and of corresponding request and mask bits. + 3 + 3 + read-write + + + OVERFLOW + Logical and of corresponding request and mask bits. + 5 + 5 + read-write + + + UNDERFLOW + Logical and of corresponding request and mask bits. + 6 + 6 + read-write + + + FRAME_ERR + Logical and of corresponding request and mask bits + 8 + 8 + read-write + + + PARITY_ERR + Logical and of corresponding request and mask bits + 9 + 9 + read-write + + + BAUD_DETECT + Logical and of corresponding request and mask bits + 10 + 10 + read-write + + + BREAK_DETECT + Logical and of corresponding request and mask bits + 11 + 11 + read-write + + + + + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.tr b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.tr new file mode 100644 index 0000000..1c33dc3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.tr @@ -0,0 +1,103 @@ +##################################################################### + Table of Contents +===================================================================== + 1::Clock Frequency Summary + 2::Clock Relationship Summary + 3::Datasheet Report + 3.1::Setup to Clock + 3.2::Clock to Out + 3.3::Pad to Pad + 4::Path Details for Clock Frequency Summary + 5::Path Details for Clock Relationship Summary +===================================================================== + End of Table of Contents +##################################################################### + +##################################################################### + 1::Clock Frequency Summary +===================================================================== +Number of clocks: 10 +Clock: ADC_intClock | N/A | Target: 1.00 MHz | +Clock: ADC_intClock(FFB) | N/A | Target: 1.00 MHz | +Clock: CyHFCLK | N/A | Target: 24.00 MHz | +Clock: CyILO | N/A | Target: 0.03 MHz | +Clock: CyIMO | N/A | Target: 24.00 MHz | +Clock: CyLFCLK | N/A | Target: 0.03 MHz | +Clock: CyRouted1 | N/A | Target: 24.00 MHz | +Clock: CySYSCLK | N/A | Target: 24.00 MHz | +Clock: UART_SCBCLK | N/A | Target: 0.08 MHz | +Clock: UART_SCBCLK(FFB) | N/A | Target: 0.08 MHz | + + ===================================================================== + End of Clock Frequency Summary + ##################################################################### + + + ##################################################################### + 2::Clock Relationship Summary + ===================================================================== + +Launch Clock Capture Clock Constraint(R-R) Slack(R-R) Constraint(R-F) Slack(R-F) Constraint(F-F) Slack(F-F) Constraint(F-R) Slack(F-R) + + ===================================================================== + End of Clock Relationship Summary + ##################################################################### + + + ##################################################################### + 3::Datasheet Report + +All values are in Picoseconds + ===================================================================== + +3.1::Setup to Clock +------------------- + +Port Name Setup to Clk Clock Name:Phase +--------- ------------ ---------------- + + +-----------------------3.2::Clock to Out +---------------------------------------- + +Port Name Clock to Out Clock Name:Phase +--------- ------------ ---------------- + + +-------------------------3.3::Pad to Pad +---------------------------------------- + +Port Name (Source) Port Name (Destination) Delay +------------------ ----------------------- ----- + +===================================================================== + End of Datasheet Report +##################################################################### +##################################################################### + 4::Path Details for Clock Frequency Summary + +===================================================================== + End of Path Details for Clock Frequency Summary +##################################################################### + + +##################################################################### + 5::Path Details for Clock Relationship Summary +===================================================================== + + +===================================================================== + End of Path Details for Clock Relationship Summary +##################################################################### + +##################################################################### + Detailed Report for all timing paths +===================================================================== +===================================================================== + End of Detailed Report for all timing paths +##################################################################### + +##################################################################### + End of Timing Report +##################################################################### + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.v b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.v new file mode 100644 index 0000000..80894bc --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.v @@ -0,0 +1,1219 @@ +// ====================================================================== +// ADC-UART.v generated from TopDesign.cysch +// 07/17/2020 at 10:59 +// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! +// ====================================================================== + +/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */ +`define CYDEV_CHIP_DIE_LEOPARD 1 +`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3 +`define CYDEV_CHIP_REV_LEOPARD_ES3 3 +`define CYDEV_CHIP_REV_LEOPARD_ES2 1 +`define CYDEV_CHIP_REV_LEOPARD_ES1 0 +`define CYDEV_CHIP_DIE_PSOC5LP 2 +`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0 +`define CYDEV_CHIP_REV_PSOC5LP_ES0 0 +`define CYDEV_CHIP_DIE_PSOC5TM 3 +`define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1 +`define CYDEV_CHIP_REV_PSOC5TM_ES1 1 +`define CYDEV_CHIP_REV_PSOC5TM_ES0 0 +`define CYDEV_CHIP_DIE_TMA4 4 +`define CYDEV_CHIP_REV_TMA4_PRODUCTION 17 +`define CYDEV_CHIP_REV_TMA4_ES 17 +`define CYDEV_CHIP_REV_TMA4_ES2 33 +`define CYDEV_CHIP_DIE_PSOC4A 5 +`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17 +`define CYDEV_CHIP_REV_PSOC4A_ES0 17 +`define CYDEV_CHIP_DIE_PSOC6ABLE2 6 +`define CYDEV_CHIP_REV_PSOC6ABLE2_ES 17 +`define CYDEV_CHIP_REV_PSOC6ABLE2_PRODUCTION 33 +`define CYDEV_CHIP_REV_PSOC6ABLE2_NO_UDB 33 +`define CYDEV_CHIP_DIE_VOLANS 7 +`define CYDEV_CHIP_REV_VOLANS_PRODUCTION 0 +`define CYDEV_CHIP_DIE_BERRYPECKER 8 +`define CYDEV_CHIP_REV_BERRYPECKER_PRODUCTION 0 +`define CYDEV_CHIP_DIE_CRANE 9 +`define CYDEV_CHIP_REV_CRANE_PRODUCTION 0 +`define CYDEV_CHIP_DIE_FM3 10 +`define CYDEV_CHIP_REV_FM3_PRODUCTION 0 +`define CYDEV_CHIP_DIE_FM4 11 +`define CYDEV_CHIP_REV_FM4_PRODUCTION 0 +`define CYDEV_CHIP_DIE_EXPECT 5 +`define CYDEV_CHIP_REV_EXPECT 17 +`define CYDEV_CHIP_DIE_ACTUAL 5 +/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */ +`define CYDEV_CHIP_FAMILY_PSOC3 1 +`define CYDEV_CHIP_FAMILY_PSOC4 2 +`define CYDEV_CHIP_FAMILY_PSOC5 3 +`define CYDEV_CHIP_FAMILY_PSOC6 4 +`define CYDEV_CHIP_FAMILY_FM0P 5 +`define CYDEV_CHIP_FAMILY_FM3 6 +`define CYDEV_CHIP_FAMILY_FM4 7 +`define CYDEV_CHIP_FAMILY_UNKNOWN 0 +`define CYDEV_CHIP_MEMBER_UNKNOWN 0 +`define CYDEV_CHIP_MEMBER_3A 1 +`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3 +`define CYDEV_CHIP_REVISION_3A_ES3 3 +`define CYDEV_CHIP_REVISION_3A_ES2 1 +`define CYDEV_CHIP_REVISION_3A_ES1 0 +`define CYDEV_CHIP_MEMBER_5B 2 +`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0 +`define CYDEV_CHIP_REVISION_5B_ES0 0 +`define CYDEV_CHIP_MEMBER_5A 3 +`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1 +`define CYDEV_CHIP_REVISION_5A_ES1 1 +`define CYDEV_CHIP_REVISION_5A_ES0 0 +`define CYDEV_CHIP_MEMBER_4G 4 +`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17 +`define CYDEV_CHIP_REVISION_4G_ES 17 +`define CYDEV_CHIP_REVISION_4G_ES2 33 +`define CYDEV_CHIP_MEMBER_4U 5 +`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4E 6 +`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0 +`define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0 +`define CYDEV_CHIP_MEMBER_4O 7 +`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4R 8 +`define CYDEV_CHIP_REVISION_4R_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4T 9 +`define CYDEV_CHIP_REVISION_4T_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4N 10 +`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4S 11 +`define CYDEV_CHIP_REVISION_4S_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4Q 12 +`define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4D 13 +`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4J 14 +`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4K 15 +`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4V 16 +`define CYDEV_CHIP_REVISION_4V_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4H 17 +`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4A 18 +`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17 +`define CYDEV_CHIP_REVISION_4A_ES0 17 +`define CYDEV_CHIP_MEMBER_4F 19 +`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0 +`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0 +`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0 +`define CYDEV_CHIP_MEMBER_4P 20 +`define CYDEV_CHIP_REVISION_4P_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4M 21 +`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4L 22 +`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_4I 23 +`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_6A 24 +`define CYDEV_CHIP_REVISION_6A_ES 17 +`define CYDEV_CHIP_REVISION_6A_PRODUCTION 33 +`define CYDEV_CHIP_REVISION_6A_NO_UDB 33 +`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25 +`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26 +`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27 +`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_FM3 28 +`define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0 +`define CYDEV_CHIP_MEMBER_FM4 29 +`define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0 +`define CYDEV_CHIP_FAMILY_USED 2 +`define CYDEV_CHIP_MEMBER_USED 18 +`define CYDEV_CHIP_REVISION_USED 17 +// Component: cy_virtualmux_v1_0 +`ifdef CY_BLK_DIR +`undef CY_BLK_DIR +`endif + +`ifdef WARP +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v" +`else +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v" +`endif + +// Component: ZeroTerminal +`ifdef CY_BLK_DIR +`undef CY_BLK_DIR +`endif + +`ifdef WARP +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v" +`else +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v" +`endif + +// Component: or_v1_0 +`ifdef CY_BLK_DIR +`undef CY_BLK_DIR +`endif + +`ifdef WARP +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v" +`else +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v" +`endif + +// SCB_P4_v4_0(ApplySbClockParam=false, BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, DBGW_SCB_IP_V2=false, DW_Hide_i2c=true, DW_Hide_Scbv0Feature=false, DW_Hide_Scbv2Feature=true, DW_Hide_Spi=true, DW_Hide_Uart=false, DW_Hide_UartFlowControl=true, DW_INTR_SPI_EC=, DW_INTR_SPI_EC_MASK=, DW_INTR_SPI_EC_MASKED=, DW_SPI_CTRL=, DW_SPI_STATUS=, DW_UART_CTRL=UART_SCB__UART_CTRL, DW_UART_FLOW_CTRL=, DW_UART_RX_CTRL=UART_SCB__UART_RX_CTRL, DW_UART_TX_CTRL=UART_SCB__UART_TX_CTRL, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cBusVoltage=3.3, EzI2cByteModeEnable=false, EzI2cClkFreqDes=1550, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cShowTerminals=false, EzI2cSlaveAddressMask=254, EzI2cSlewRate=0, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cAcceptGeneralCall=false, I2cBusVoltage=3.3, I2cBusVoltageLevel=, I2cByteModeEnable=false, I2cClkFreqDes=1550, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cManualOversampleControl=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cShowTerminals=false, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cSlewRate=0, I2cSlewRateSettings=0, I2cTermsEnable=false, I2cWakeEnable=false, PinLocationP4A=true, PinName0Unconfig=uart_rx_i2c_scl_spi_mosi, PinName0UnconfigWake=uart_rx_wake_i2c_scl_spi_mosi, PinName1Unconfig=uart_tx_i2c_sda_spi_miso, PinName2Unconfig=spi_sclk, PinName3Unconfig=spi_ss0, Pn0Unconfig=RX_SCL_MOSI, Pn0UnconfigWake=RX_WAKE_SCL_MOSI, Pn1Unconfig=TX_SDA_MISO, Pn2Unconfig=SCLK, Pn3Unconfig=SS0, RemoveI2cPins=true, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=true, RemoveSpiMasterMiso=true, RemoveSpiMasterMosi=true, RemoveSpiMasterPins=true, RemoveSpiMasterSclk=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlaveMiso=true, RemoveSpiSlaveMosi=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartCtsPin=true, RemoveUartRtsPin=true, RemoveUartRxPin=true, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=false, RxTriggerOutputEnable=false, ScbClkFreqDes=76.8, ScbClkMinusTolerance=5, ScbClkPlusTolerance=5, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=4, ScbModeHw=2, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, ScbSymbolVisibility=0, SpiBitRate=1000, SpiBitsOrder=1, SpiByteModeEnable=false, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiFreeRunningSclk=false, SpiInterruptMode=1, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiManualOversampleControl=true, SpiMasterMode=false, SpiMedianFilterEnable=false, SpimMisoTermEnable=false, SpimMosiTermEnable=false, SpiMode=0, SpimSclkTermEnable=false, SpimSs0TermEnable=false, SpimSs1TermEnable=false, SpimSs2TermEnable=false, SpimSs3TermEnable=false, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRemoveMiso=false, SpiRemoveMosi=false, SpiRemoveSclk=false, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxOutputEnable=false, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSlaveMode=false, SpiSmartioEnable=false, SpisMisoTermEnable=false, SpisMosiTermEnable=false, SpiSs0Polarity=0, SpiSs1Polarity=0, SpiSs2Polarity=0, SpiSs3Polarity=0, SpisSclkTermEnable=false, SpisSsTermEnable=false, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxOutputEnable=false, SpiTxTriggerLevel=0, SpiWakeEnable=false, TriggerOutputEnable=false, TxTriggerOutputEnable=false, UartByteModeEnable=false, UartClkFreqDes=76.8, UartClockFromTerm=false, UartCtsEnable=false, UartCtsPolarity=0, UartCtsTermEnable=false, UartDataRate=9600, UartDirection=2, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxBreakDetected=false, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=false, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=8, UartParityType=2, UartRtsEnable=false, UartRtsPolarity=0, UartRtsTermEnable=false, UartRtsTriggerLevel=4, UartRxBreakWidth=11, UartRxBufferSize=8, UartRxEnable=false, UartRxIntrMask=0, UartRxOutputEnable=false, UartRxTermEnable=false, UartRxTriggerLevel=7, UartRxTxTermEnable=false, UartSmartioEnable=false, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxOutputEnable=false, UartTxTermEnable=false, UartTxTriggerLevel=0, UartWakeEnable=false, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMMENT=, CY_COMPONENT_NAME=SCB_P4_v4_0, CY_CONFIG_TITLE=UART, CY_CONST_CONFIG=true, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=UART, CY_INSTANCE_SHORT_NAME=UART, CY_MAJOR_VERSION=4, CY_MINOR_VERSION=0, CY_PDL_DRIVER_NAME=, CY_PDL_DRIVER_REQ_VERSION=, CY_PDL_DRIVER_SUBGROUP=, CY_PDL_DRIVER_VARIANT=, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 4.2, INSTANCE_NAME=UART, ) +module SCB_P4_v4_0_0 ( + cts_in, + rts_out, + interrupt, + clock, + rx_dma_out, + tx_dma_out, + s_mosi, + s_sclk, + s_ss, + m_miso, + m_mosi, + m_sclk, + m_ss0, + m_ss1, + m_ss2, + m_ss3, + s_miso, + rx_in, + tx_out, + scl_b, + sda_b, + rx_tx_out); + input cts_in; + output rts_out; + output interrupt; + input clock; + output rx_dma_out; + output tx_dma_out; + input s_mosi; + input s_sclk; + input s_ss; + input m_miso; + output m_mosi; + output m_sclk; + output m_ss0; + output m_ss1; + output m_ss2; + output m_ss3; + output s_miso; + input rx_in; + output tx_out; + inout scl_b; + inout sda_b; + output rx_tx_out; + + + wire uncfg_rx_irq; + wire sclk_m_wire; + wire Net_1264; + wire Net_1258; + wire rx_irq; + wire [3:0] select_m_wire; + wire Net_1099; + wire Net_1090; + wire Net_467; + wire Net_1316; + wire Net_252; + wire Net_1089; + wire Net_1320; + wire Net_1257; + wire sclk_s_wire; + wire Net_1268; + wire Net_1297; + wire Net_547; + wire Net_1001; + wire mosi_s_wire; + wire rts_wire; + wire mosi_m_wire; + wire Net_891; + wire Net_1263; + wire miso_s_wire; + wire cts_wire; + wire Net_899; + wire tx_wire; + wire Net_1028; + wire rx_wire; + wire Net_916; + wire Net_1000; + wire miso_m_wire; + wire Net_1172; + wire Net_1170; + wire select_s_wire; + wire Net_847; + + + cy_clock_v1_0 + #(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/2dc2d7a8-ce2b-43c7-af4a-821c8cd73ccf"), + .source_clock_id(""), + .divisor(0), + .period("13020833333.3333"), + .is_direct(0), + .is_digital(0)) + SCBCLK + (.clock_out(Net_847)); + + + // select_s_VM (cy_virtualmux_v1_0) + assign select_s_wire = s_ss; + + // rx_VM (cy_virtualmux_v1_0) + assign rx_wire = rx_in; + + // rx_wake_VM (cy_virtualmux_v1_0) + assign Net_1257 = uncfg_rx_irq; + + // clock_VM (cy_virtualmux_v1_0) + assign Net_1170 = Net_847; + + // sclk_s_VM (cy_virtualmux_v1_0) + assign sclk_s_wire = s_sclk; + + // mosi_s_VM (cy_virtualmux_v1_0) + assign mosi_s_wire = s_mosi; + + // miso_m_VM (cy_virtualmux_v1_0) + assign miso_m_wire = m_miso; + + wire [0:0] tmpOE__tx_net; + wire [0:0] tmpFB_0__tx_net; + wire [0:0] tmpIO_0__tx_net; + wire [0:0] tmpINTERRUPT_0__tx_net; + electrical [0:0] tmpSIOVREF__tx_net; + + cy_psoc3_pins_v1_10 + #(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/23b8206d-1c77-4e61-be4a-b4037d5de5fc"), + .drive_mode(3'b110), + .ibuf_enabled(1'b0), + .init_dr_st(1'b1), + .input_clk_en(0), + .input_sync(1'b0), + .input_sync_mode(1'b0), + .intr_mode(2'b00), + .invert_in_clock(0), + .invert_in_clock_en(0), + .invert_in_reset(0), + .invert_out_clock(0), + .invert_out_clock_en(0), + .invert_out_reset(0), + .io_voltage(""), + .layout_mode("CONTIGUOUS"), + .oe_conn(1'b0), + .oe_reset(0), + .oe_sync(1'b0), + .output_clk_en(0), + .output_clock_mode(1'b0), + .output_conn(1'b1), + .output_mode(1'b0), + .output_reset(0), + .output_sync(1'b0), + .pa_in_clock(-1), + .pa_in_clock_en(-1), + .pa_in_reset(-1), + .pa_out_clock(-1), + .pa_out_clock_en(-1), + .pa_out_reset(-1), + .pin_aliases(""), + .pin_mode("B"), + .por_state(4), + .sio_group_cnt(0), + .sio_hyst(1'b1), + .sio_ibuf(""), + .sio_info(2'b00), + .sio_obuf(""), + .sio_refsel(""), + .sio_vtrip(""), + .sio_hifreq(""), + .sio_vohsel(""), + .slew_rate(1'b0), + .spanning(0), + .use_annotation(1'b0), + .vtrip(2'b00), + .width(1), + .ovt_hyst_trim(1'b0), + .ovt_needed(1'b0), + .ovt_slew_control(2'b00), + .input_buffer_sel(2'b00)) + tx + (.oe(tmpOE__tx_net), + .y({tx_wire}), + .fb({tmpFB_0__tx_net[0:0]}), + .io({tmpIO_0__tx_net[0:0]}), + .siovref(tmpSIOVREF__tx_net), + .interrupt({tmpINTERRUPT_0__tx_net[0:0]}), + .in_clock({1'b0}), + .in_clock_en({1'b1}), + .in_reset({1'b0}), + .out_clock({1'b0}), + .out_clock_en({1'b1}), + .out_reset({1'b0})); + + assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; + + ZeroTerminal ZeroTerminal_7 ( + .z(Net_1099)); + + + assign Net_1258 = Net_1099 | Net_847; + + // cts_VM (cy_virtualmux_v1_0) + assign cts_wire = cts_in; + + cy_m0s8_scb_v2_0 SCB ( + .rx(rx_wire), + .miso_m(miso_m_wire), + .select_m(select_m_wire[3:0]), + .sclk_m(sclk_m_wire), + .mosi_s(mosi_s_wire), + .select_s(select_s_wire), + .sclk_s(sclk_s_wire), + .mosi_m(mosi_m_wire), + .scl(scl_b), + .sda(sda_b), + .tx(tx_wire), + .miso_s(miso_s_wire), + .interrupt(interrupt), + .cts(cts_wire), + .rts(rts_wire), + .tx_req(tx_dma_out), + .rx_req(rx_dma_out), + .clock(Net_1170)); + defparam SCB.scb_mode = 2; + + // Device_VM4 (cy_virtualmux_v1_0) + assign uncfg_rx_irq = Net_1028; + + + assign rts_out = rts_wire; + + assign m_mosi = mosi_m_wire; + + assign m_sclk = sclk_m_wire; + + assign m_ss0 = select_m_wire[0]; + + assign m_ss1 = select_m_wire[1]; + + assign m_ss2 = select_m_wire[2]; + + assign m_ss3 = select_m_wire[3]; + + assign s_miso = miso_s_wire; + + assign tx_out = tx_wire; + + assign rx_tx_out = tx_wire; + + +endmodule + +// Component: cy_analog_virtualmux_v1_0 +`ifdef CY_BLK_DIR +`undef CY_BLK_DIR +`endif + +`ifdef WARP +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v" +`else +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v" +`endif + +// Component: Bus_Connect_v2_50 +`ifdef CY_BLK_DIR +`undef CY_BLK_DIR +`endif + +`ifdef WARP +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v" +`else +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v" +`endif + +// ADC_SAR_SEQ_P4_v2_50(AdcAClock=2, AdcAdjust=1, AdcAlternateResolution=0, AdcAvgMode=1, AdcAvgSamplesNum=7, AdcBClock=2, AdcCClock=2, AdcChannelsEnConf=1, AdcChannelsModeConf=0, AdcClock=1, AdcClockFrequency=1000000, AdcCompareMode=3, AdcDataFormatJustification=0, AdcDClock=2, AdcDedicatedExtVref=false, AdcDifferentialResultFormat=0, AdcHighLimit=1534, AdcInjChannelEnabled=false, AdcInputBufGain=0, AdcLowLimit=511, AdcMaxResolution=12, AdcSampleMode=0, AdcSarMuxChannelConfig=0, AdcSequencedChannels=1, AdcSingleEndedNegativeInput=0, AdcSingleResultFormat=1, AdcSymbolHasSingleEndedInputChannel=false, AdcTotalChannels=1, AdcVrefSelect=1, AdcVrefVoltage_mV=3487, rm_int=false, SeqChannelsConfigTable=falseTwelveDifffalseAClocksfalsefalsetrueTwelveSingletrueAClockstruefalse, TermMode_aclk=0, TermMode_eoc=0, TermMode_sdone=0, TermMode_soc=0, TermMode_vinMinus0=0, TermMode_vinMinus1=0, TermMode_vinMinus10=0, TermMode_vinMinus11=0, TermMode_vinMinus12=0, TermMode_vinMinus13=0, TermMode_vinMinus14=0, TermMode_vinMinus15=0, TermMode_vinMinus2=0, TermMode_vinMinus3=0, TermMode_vinMinus4=0, TermMode_vinMinus5=0, TermMode_vinMinus6=0, TermMode_vinMinus7=0, TermMode_vinMinus8=0, TermMode_vinMinus9=0, TermMode_vinMinusINJ=0, TermMode_vinNeg=0, TermMode_vinPlus0=0, TermMode_vinPlus1=0, TermMode_vinPlus10=0, TermMode_vinPlus11=0, TermMode_vinPlus12=0, TermMode_vinPlus13=0, TermMode_vinPlus14=0, TermMode_vinPlus15=0, TermMode_vinPlus2=0, TermMode_vinPlus3=0, TermMode_vinPlus4=0, TermMode_vinPlus5=0, TermMode_vinPlus6=0, TermMode_vinPlus7=0, TermMode_vinPlus8=0, TermMode_vinPlus9=0, TermMode_vinPlusINJ=0, TermMode_Vref=0, TermVisibility_aclk=false, TermVisibility_eoc=true, TermVisibility_sdone=true, TermVisibility_soc=false, TermVisibility_vinMinus0=false, TermVisibility_vinMinus1=false, TermVisibility_vinMinus10=false, TermVisibility_vinMinus11=false, TermVisibility_vinMinus12=false, TermVisibility_vinMinus13=false, TermVisibility_vinMinus14=false, TermVisibility_vinMinus15=false, TermVisibility_vinMinus2=false, TermVisibility_vinMinus3=false, TermVisibility_vinMinus4=false, TermVisibility_vinMinus5=false, TermVisibility_vinMinus6=false, TermVisibility_vinMinus7=false, TermVisibility_vinMinus8=false, TermVisibility_vinMinus9=false, TermVisibility_vinMinusINJ=false, TermVisibility_vinNeg=false, TermVisibility_vinPlus0=true, TermVisibility_vinPlus1=false, TermVisibility_vinPlus10=false, TermVisibility_vinPlus11=false, TermVisibility_vinPlus12=false, TermVisibility_vinPlus13=false, TermVisibility_vinPlus14=false, TermVisibility_vinPlus15=false, TermVisibility_vinPlus2=false, TermVisibility_vinPlus3=false, TermVisibility_vinPlus4=false, TermVisibility_vinPlus5=false, TermVisibility_vinPlus6=false, TermVisibility_vinPlus7=false, TermVisibility_vinPlus8=false, TermVisibility_vinPlus9=false, TermVisibility_vinPlusINJ=false, TermVisibility_Vref=false, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMMENT=, CY_COMPONENT_NAME=ADC_SAR_SEQ_P4_v2_50, CY_CONFIG_TITLE=ADC, CY_CONST_CONFIG=true, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=ADC, CY_INSTANCE_SHORT_NAME=ADC, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=50, CY_PDL_DRIVER_NAME=, CY_PDL_DRIVER_REQ_VERSION=, CY_PDL_DRIVER_SUBGROUP=, CY_PDL_DRIVER_VARIANT=, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 4.2, INSTANCE_NAME=ADC, ) +module ADC_SAR_SEQ_P4_v2_50_1 ( + Vref, + sdone, + eoc, + aclk, + vinPlus0, + soc); + inout Vref; + electrical Vref; + output sdone; + output eoc; + input aclk; + inout vinPlus0; + electrical vinPlus0; + input soc; + + + wire Net_3209; + electrical Net_3164; + wire Net_3128; + wire [11:0] Net_3111; + wire Net_3110; + wire [3:0] Net_3109; + wire Net_3108; + electrical Net_3166; + electrical Net_3167; + electrical Net_3168; + electrical Net_3169; + electrical Net_3170; + electrical Net_3171; + electrical Net_3172; + electrical Net_3173; + electrical Net_3174; + electrical Net_3175; + electrical Net_3176; + electrical Net_3177; + electrical Net_3178; + electrical Net_3179; + electrical Net_3180; + electrical muxout_plus; + electrical Net_3181; + electrical muxout_minus; + electrical Net_3227; + electrical Net_3113; + electrical Net_3225; + electrical [16:0] mux_bus_minus; + electrical [16:0] mux_bus_plus; + electrical Net_3226; + wire Net_3103; + wire Net_3104; + wire Net_3105; + wire Net_3106; + wire Net_3107; + electrical Net_3165; + electrical Net_3182; + electrical Net_3183; + electrical Net_3184; + electrical Net_3185; + electrical Net_3186; + electrical Net_3187; + electrical Net_3188; + electrical Net_3189; + electrical Net_3190; + electrical Net_3191; + electrical Net_3192; + electrical Net_3193; + electrical Net_3194; + electrical Net_3195; + electrical Net_3196; + electrical Net_3197; + electrical Net_3198; + electrical Net_3132; + electrical Net_3133; + electrical Net_3134; + electrical Net_3135; + electrical Net_3136; + electrical Net_3137; + electrical Net_3138; + electrical Net_3139; + electrical Net_3140; + electrical Net_3141; + electrical Net_3142; + electrical Net_3143; + electrical Net_3144; + electrical Net_3145; + electrical Net_3146; + electrical Net_3147; + electrical Net_3148; + electrical Net_3149; + electrical Net_3150; + electrical Net_3151; + electrical Net_3152; + electrical Net_3153; + electrical Net_3154; + electrical Net_3159; + electrical Net_3157; + electrical Net_3158; + electrical Net_3160; + electrical Net_3161; + electrical Net_3162; + electrical Net_3163; + electrical Net_3156; + electrical Net_3155; + wire Net_3120; + electrical Net_3119; + electrical Net_3118; + wire Net_3124; + electrical Net_3122; + electrical Net_3117; + electrical Net_3121; + electrical Net_3123; + wire Net_3112; + wire Net_3126; + wire Net_3125; + electrical Net_2793; + electrical Net_2794; + electrical Net_1851; + electrical [0:0] Net_2580; + electrical [0:0] Net_2375; + electrical [0:0] Net_1450; + electrical Net_3046; + electrical Net_3016; + wire Net_3235; + electrical Net_2099; + wire Net_17; + wire Net_1845; + electrical Net_2020; + electrical Net_124; + electrical Net_2102; + wire [1:0] Net_3207; + electrical Net_8; + electrical Net_43; + + ZeroTerminal ZeroTerminal_8 ( + .z(Net_3125)); + + + assign Net_3126 = Net_3125 | Net_1845; + + + cy_isr_v1_0 + #(.int_type(2'b10)) + IRQ + (.int_signal(Net_3112)); + + + cy_analog_noconnect_v1_0 cy_analog_noconnect_44 ( + .noconnect(Net_3123)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_40 ( + .noconnect(Net_3121)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_39 ( + .noconnect(Net_3117)); + + // cy_analog_virtualmux_43 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_43_connect(Net_124, muxout_minus); + defparam cy_analog_virtualmux_43_connect.sig_width = 1; + + // cy_analog_virtualmux_42 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_42_connect(Net_2020, muxout_plus); + defparam cy_analog_virtualmux_42_connect.sig_width = 1; + + cy_analog_noconnect_v1_0 cy_analog_noconnect_38 ( + .noconnect(Net_3118)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_41 ( + .noconnect(Net_3119)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_43 ( + .noconnect(Net_3122)); + + // adc_plus_in_sel (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 adc_plus_in_sel_connect(muxout_plus, mux_bus_plus[0]); + defparam adc_plus_in_sel_connect.sig_width = 1; + + Bus_Connect_v2_50 Connect_1 ( + .in_bus(mux_bus_plus[16:0]), + .out_bus(Net_1450[0:0])); + defparam Connect_1.in_width = 17; + defparam Connect_1.out_width = 1; + + // adc_minus_in_sel (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 adc_minus_in_sel_connect(muxout_minus, mux_bus_minus[0]); + defparam adc_minus_in_sel_connect.sig_width = 1; + + cy_analog_noconnect_v1_0 cy_analog_noconnect_3 ( + .noconnect(Net_1851)); + + // cy_analog_virtualmux_37 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_37_connect(Net_3016, mux_bus_plus[1]); + defparam cy_analog_virtualmux_37_connect.sig_width = 1; + + cy_analog_noconnect_v1_0 cy_analog_noconnect_21 ( + .noconnect(Net_3147)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_20 ( + .noconnect(Net_3146)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_19 ( + .noconnect(Net_3145)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_18 ( + .noconnect(Net_3144)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_17 ( + .noconnect(Net_3143)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_16 ( + .noconnect(Net_3142)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_15 ( + .noconnect(Net_3141)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_14 ( + .noconnect(Net_3140)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_13 ( + .noconnect(Net_3139)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_12 ( + .noconnect(Net_3138)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_11 ( + .noconnect(Net_3137)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_10 ( + .noconnect(Net_3136)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_9 ( + .noconnect(Net_3135)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_8 ( + .noconnect(Net_3134)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_7 ( + .noconnect(Net_3133)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_6 ( + .noconnect(Net_3132)); + + // cy_analog_virtualmux_36 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_36_connect(Net_3046, mux_bus_minus[1]); + defparam cy_analog_virtualmux_36_connect.sig_width = 1; + + cy_analog_noconnect_v1_0 cy_analog_noconnect_37 ( + .noconnect(Net_3165)); + + ZeroTerminal ZeroTerminal_5 ( + .z(Net_3107)); + + ZeroTerminal ZeroTerminal_4 ( + .z(Net_3106)); + + ZeroTerminal ZeroTerminal_3 ( + .z(Net_3105)); + + ZeroTerminal ZeroTerminal_2 ( + .z(Net_3104)); + + ZeroTerminal ZeroTerminal_1 ( + .z(Net_3103)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_1 ( + .noconnect(Net_3113)); + + // ext_vref_sel (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 ext_vref_sel_connect(Net_43, Net_3225); + defparam ext_vref_sel_connect.sig_width = 1; + + Bus_Connect_v2_50 Connect_2 ( + .in_bus(mux_bus_minus[16:0]), + .out_bus(Net_2375[0:0])); + defparam Connect_2.in_width = 17; + defparam Connect_2.out_width = 1; + + cy_analog_noconnect_v1_0 cy_analog_noconnect_35 ( + .noconnect(Net_3181)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_34 ( + .noconnect(Net_3180)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_33 ( + .noconnect(Net_3179)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_32 ( + .noconnect(Net_3178)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_31 ( + .noconnect(Net_3177)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_30 ( + .noconnect(Net_3176)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_29 ( + .noconnect(Net_3175)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_28 ( + .noconnect(Net_3174)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_27 ( + .noconnect(Net_3173)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_26 ( + .noconnect(Net_3172)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_25 ( + .noconnect(Net_3171)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_24 ( + .noconnect(Net_3170)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_23 ( + .noconnect(Net_3169)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_22 ( + .noconnect(Net_3168)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_4 ( + .noconnect(Net_3167)); + + cy_analog_noconnect_v1_0 cy_analog_noconnect_2 ( + .noconnect(Net_3166)); + + // int_vref_sel (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 int_vref_sel_connect(Net_8, Net_3113); + defparam int_vref_sel_connect.sig_width = 1; + + // clk_src_sel (cy_virtualmux_v1_0) + assign Net_17 = Net_1845; + + cy_psoc4_sar_v1_0 cy_psoc4_sar ( + .vplus(Net_2020), + .vminus(Net_124), + .vref(Net_8), + .ext_vref(Net_43), + .clock(Net_17), + .sw_negvref(Net_3103), + .cfg_st_sel(Net_3207[1:0]), + .cfg_average(Net_3104), + .cfg_resolution(Net_3105), + .cfg_differential(Net_3106), + .trigger(Net_3235), + .data_hilo_sel(Net_3107), + .sample_done(sdone), + .chan_id_valid(Net_3108), + .chan_id(Net_3109[3:0]), + .data_valid(Net_3110), + .eos_intr(eoc), + .data(Net_3111[11:0]), + .irq(Net_3112)); + + // ext_vneg_sel (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 ext_vneg_sel_connect(Net_2580[0:0], Net_1851); + defparam ext_vneg_sel_connect.sig_width = 1; + + // VMux_soc (cy_virtualmux_v1_0) + assign Net_3235 = soc; + + ZeroTerminal ZeroTerminal_6 ( + .z(Net_3207[0])); + + ZeroTerminal ZeroTerminal_7 ( + .z(Net_3207[1])); + + // cy_analog_virtualmux_vplus0 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus0_connect(mux_bus_plus[0], vinPlus0); + defparam cy_analog_virtualmux_vplus0_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus1 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus1_connect(mux_bus_plus[1], Net_3132); + defparam cy_analog_virtualmux_vplus1_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus2 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus2_connect(mux_bus_plus[2], Net_3133); + defparam cy_analog_virtualmux_vplus2_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus3 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus3_connect(mux_bus_plus[3], Net_3134); + defparam cy_analog_virtualmux_vplus3_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus4 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus4_connect(mux_bus_plus[4], Net_3135); + defparam cy_analog_virtualmux_vplus4_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus5 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus5_connect(mux_bus_plus[5], Net_3136); + defparam cy_analog_virtualmux_vplus5_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus6 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus6_connect(mux_bus_plus[6], Net_3137); + defparam cy_analog_virtualmux_vplus6_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus7 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus7_connect(mux_bus_plus[7], Net_3138); + defparam cy_analog_virtualmux_vplus7_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus8 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus8_connect(mux_bus_plus[8], Net_3139); + defparam cy_analog_virtualmux_vplus8_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus9 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus9_connect(mux_bus_plus[9], Net_3140); + defparam cy_analog_virtualmux_vplus9_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus10 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus10_connect(mux_bus_plus[10], Net_3141); + defparam cy_analog_virtualmux_vplus10_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus11 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus11_connect(mux_bus_plus[11], Net_3142); + defparam cy_analog_virtualmux_vplus11_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus12 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus12_connect(mux_bus_plus[12], Net_3143); + defparam cy_analog_virtualmux_vplus12_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus13 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus13_connect(mux_bus_plus[13], Net_3144); + defparam cy_analog_virtualmux_vplus13_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus14 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus14_connect(mux_bus_plus[14], Net_3145); + defparam cy_analog_virtualmux_vplus14_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus15 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus15_connect(mux_bus_plus[15], Net_3146); + defparam cy_analog_virtualmux_vplus15_connect.sig_width = 1; + + // cy_analog_virtualmux_vplus_inj (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vplus_inj_connect(Net_3016, Net_3147); + defparam cy_analog_virtualmux_vplus_inj_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus0 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus0_connect(mux_bus_minus[0], Net_3166); + defparam cy_analog_virtualmux_vminus0_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus1 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus1_connect(mux_bus_minus[1], Net_3167); + defparam cy_analog_virtualmux_vminus1_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus2 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus2_connect(mux_bus_minus[2], Net_3168); + defparam cy_analog_virtualmux_vminus2_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus3 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus3_connect(mux_bus_minus[3], Net_3169); + defparam cy_analog_virtualmux_vminus3_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus4 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus4_connect(mux_bus_minus[4], Net_3170); + defparam cy_analog_virtualmux_vminus4_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus5 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus5_connect(mux_bus_minus[5], Net_3171); + defparam cy_analog_virtualmux_vminus5_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus6 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus6_connect(mux_bus_minus[6], Net_3172); + defparam cy_analog_virtualmux_vminus6_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus7 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus7_connect(mux_bus_minus[7], Net_3173); + defparam cy_analog_virtualmux_vminus7_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus8 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus8_connect(mux_bus_minus[8], Net_3174); + defparam cy_analog_virtualmux_vminus8_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus9 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus9_connect(mux_bus_minus[9], Net_3175); + defparam cy_analog_virtualmux_vminus9_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus10 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus10_connect(mux_bus_minus[10], Net_3176); + defparam cy_analog_virtualmux_vminus10_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus11 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus11_connect(mux_bus_minus[11], Net_3177); + defparam cy_analog_virtualmux_vminus11_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus12 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus12_connect(mux_bus_minus[12], Net_3178); + defparam cy_analog_virtualmux_vminus12_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus13 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus13_connect(mux_bus_minus[13], Net_3179); + defparam cy_analog_virtualmux_vminus13_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus14 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus14_connect(mux_bus_minus[14], Net_3180); + defparam cy_analog_virtualmux_vminus14_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus15 (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus15_connect(mux_bus_minus[15], Net_3181); + defparam cy_analog_virtualmux_vminus15_connect.sig_width = 1; + + // cy_analog_virtualmux_vminus_inj (cy_analog_virtualmux_v1_0) + cy_connect_v1_0 cy_analog_virtualmux_vminus_inj_connect(Net_3046, Net_3165); + defparam cy_analog_virtualmux_vminus_inj_connect.sig_width = 1; + + + cy_clock_v1_0 + #(.id("9a67a4bd-024a-4dec-ac06-ad54a4dde89a/5c71752a-e182-47ca-942c-9cb20adbdf2f"), + .source_clock_id(""), + .divisor(0), + .period("1000000000"), + .is_direct(0), + .is_digital(0)) + intClock + (.clock_out(Net_1845)); + + + cy_analog_noconnect_v1_0 cy_analog_noconnect_5 ( + .noconnect(Net_3227)); + + + +endmodule + +// top +module top ; + + wire Net_669; + wire Net_668; + wire Net_667; + wire Net_666; + electrical Net_665; + electrical Net_664; + wire Net_674; + wire Net_673; + wire Net_672; + wire Net_646; + wire Net_663; + wire Net_662; + wire Net_661; + wire Net_660; + wire Net_659; + wire Net_658; + wire Net_657; + wire Net_656; + wire Net_655; + wire Net_654; + wire Net_653; + wire Net_652; + wire Net_671; + wire Net_670; + wire Net_649; + wire Net_648; + wire Net_647; + wire Net_645; + electrical Net_644; + electrical Net_563; + electrical Net_342; + electrical Net_290; + + wire [0:0] tmpOE__LED_net; + wire [0:0] tmpFB_0__LED_net; + wire [0:0] tmpIO_0__LED_net; + wire [0:0] tmpINTERRUPT_0__LED_net; + electrical [0:0] tmpSIOVREF__LED_net; + + cy_psoc3_pins_v1_10 + #(.id("52f31aa9-2f0a-497d-9a1f-1424095e13e6"), + .drive_mode(3'b100), + .ibuf_enabled(1'b1), + .init_dr_st(1'b1), + .input_clk_en(0), + .input_sync(1'b1), + .input_sync_mode(1'b0), + .intr_mode(2'b00), + .invert_in_clock(0), + .invert_in_clock_en(0), + .invert_in_reset(0), + .invert_out_clock(0), + .invert_out_clock_en(0), + .invert_out_reset(0), + .io_voltage(""), + .layout_mode("CONTIGUOUS"), + .oe_conn(1'b0), + .oe_reset(0), + .oe_sync(1'b0), + .output_clk_en(0), + .output_clock_mode(1'b0), + .output_conn(1'b0), + .output_mode(1'b0), + .output_reset(0), + .output_sync(1'b0), + .pa_in_clock(-1), + .pa_in_clock_en(-1), + .pa_in_reset(-1), + .pa_out_clock(-1), + .pa_out_clock_en(-1), + .pa_out_reset(-1), + .pin_aliases(""), + .pin_mode("O"), + .por_state(4), + .sio_group_cnt(0), + .sio_hyst(1'b1), + .sio_ibuf(""), + .sio_info(2'b00), + .sio_obuf(""), + .sio_refsel(""), + .sio_vtrip(""), + .sio_hifreq(""), + .sio_vohsel(""), + .slew_rate(1'b0), + .spanning(0), + .use_annotation(1'b1), + .vtrip(2'b10), + .width(1), + .ovt_hyst_trim(1'b0), + .ovt_needed(1'b0), + .ovt_slew_control(2'b00), + .input_buffer_sel(2'b00)) + LED + (.oe(tmpOE__LED_net), + .y({1'b0}), + .fb({tmpFB_0__LED_net[0:0]}), + .io({tmpIO_0__LED_net[0:0]}), + .siovref(tmpSIOVREF__LED_net), + .interrupt({tmpINTERRUPT_0__LED_net[0:0]}), + .annotation({Net_644}), + .in_clock({1'b0}), + .in_clock_en({1'b1}), + .in_reset({1'b0}), + .out_clock({1'b0}), + .out_clock_en({1'b1}), + .out_reset({1'b0})); + + assign tmpOE__LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; + + SCB_P4_v4_0_0 UART ( + .cts_in(1'b0), + .rts_out(Net_647), + .interrupt(Net_648), + .clock(1'b0), + .rx_dma_out(Net_670), + .tx_dma_out(Net_671), + .s_mosi(1'b0), + .s_sclk(1'b0), + .s_ss(1'b0), + .m_miso(1'b0), + .m_mosi(Net_656), + .m_sclk(Net_657), + .m_ss0(Net_658), + .m_ss1(Net_659), + .m_ss2(Net_660), + .m_ss3(Net_661), + .s_miso(Net_662), + .rx_in(1'b0), + .tx_out(Net_646), + .scl_b(Net_672), + .sda_b(Net_673), + .rx_tx_out(Net_674)); + + cy_annotation_universal_v1_0 PWR ( + .connect({ + Net_664 + }) + ); + defparam PWR.comp_name = "Power_v1_0"; + defparam PWR.port_names = "T1"; + defparam PWR.width = 1; + + cy_annotation_universal_v1_0 R ( + .connect({ + Net_290, + Net_644 + }) + ); + defparam R.comp_name = "Resistor_v1_0"; + defparam R.port_names = "T1, T2"; + defparam R.width = 2; + + wire [0:0] tmpOE__Input_1_net; + wire [0:0] tmpFB_0__Input_1_net; + wire [0:0] tmpIO_0__Input_1_net; + wire [0:0] tmpINTERRUPT_0__Input_1_net; + electrical [0:0] tmpSIOVREF__Input_1_net; + + cy_psoc3_pins_v1_10 + #(.id("0b0fcf5d-629b-4f61-a95a-c0d71e4b1f3e"), + .drive_mode(3'b000), + .ibuf_enabled(1'b0), + .init_dr_st(1'b1), + .input_clk_en(0), + .input_sync(1'b1), + .input_sync_mode(1'b0), + .intr_mode(2'b00), + .invert_in_clock(0), + .invert_in_clock_en(0), + .invert_in_reset(0), + .invert_out_clock(0), + .invert_out_clock_en(0), + .invert_out_reset(0), + .io_voltage(""), + .layout_mode("CONTIGUOUS"), + .oe_conn(1'b0), + .oe_reset(0), + .oe_sync(1'b0), + .output_clk_en(0), + .output_clock_mode(1'b0), + .output_conn(1'b0), + .output_mode(1'b0), + .output_reset(0), + .output_sync(1'b0), + .pa_in_clock(-1), + .pa_in_clock_en(-1), + .pa_in_reset(-1), + .pa_out_clock(-1), + .pa_out_clock_en(-1), + .pa_out_reset(-1), + .pin_aliases(""), + .pin_mode("A"), + .por_state(4), + .sio_group_cnt(0), + .sio_hyst(1'b1), + .sio_ibuf(""), + .sio_info(2'b00), + .sio_obuf(""), + .sio_refsel(""), + .sio_vtrip(""), + .sio_hifreq(""), + .sio_vohsel(""), + .slew_rate(1'b0), + .spanning(0), + .use_annotation(1'b1), + .vtrip(2'b10), + .width(1), + .ovt_hyst_trim(1'b0), + .ovt_needed(1'b0), + .ovt_slew_control(2'b00), + .input_buffer_sel(2'b00)) + Input_1 + (.oe(tmpOE__Input_1_net), + .y({1'b0}), + .fb({tmpFB_0__Input_1_net[0:0]}), + .analog({Net_563}), + .io({tmpIO_0__Input_1_net[0:0]}), + .siovref(tmpSIOVREF__Input_1_net), + .interrupt({tmpINTERRUPT_0__Input_1_net[0:0]}), + .annotation({Net_342}), + .in_clock({1'b0}), + .in_clock_en({1'b1}), + .in_reset({1'b0}), + .out_clock({1'b0}), + .out_clock_en({1'b1}), + .out_reset({1'b0})); + + assign tmpOE__Input_1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; + + ADC_SAR_SEQ_P4_v2_50_1 ADC ( + .Vref(Net_665), + .sdone(Net_666), + .eoc(Net_667), + .aclk(1'b0), + .vinPlus0(Net_563), + .soc(1'b0)); + + cy_annotation_universal_v1_0 LED1 ( + .connect({ + Net_664, + Net_290 + }) + ); + defparam LED1.comp_name = "LED_v1_0"; + defparam LED1.port_names = "A, K"; + defparam LED1.width = 2; + + + +endmodule + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.vh2 b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.vh2 new file mode 100644 index 0000000..5988c8e --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.vh2 @@ -0,0 +1,802 @@ +-- +-- Conversion of ADC-UART.v to vh2: +-- +-- Cypress Semiconductor - WARP Version 6.3 IR 41 +-- Fri Jul 17 10:59:51 2020 +-- + +USE cypress.cypress.all; +USE cypress.rtlpkg.all; +ENTITY top_RTL IS +ATTRIBUTE part_name of top_RTL:TYPE IS "cpsoc3"; +END top_RTL; +-------------------------------------------------------- +ARCHITECTURE R_T_L OF top_RTL IS +SIGNAL tmpOE__LED_net_0 : bit; +SIGNAL zero : bit; +SIGNAL tmpFB_0__LED_net_0 : bit; +SIGNAL tmpIO_0__LED_net_0 : bit; +TERMINAL tmpSIOVREF__LED_net_0 : bit; +TERMINAL Net_644 : bit; +SIGNAL one : bit; +SIGNAL tmpINTERRUPT_0__LED_net_0 : bit; +SIGNAL \UART:Net_847\ : bit; +SIGNAL \UART:select_s_wire\ : bit; +SIGNAL \UART:rx_wire\ : bit; +SIGNAL \UART:Net_1257\ : bit; +SIGNAL \UART:uncfg_rx_irq\ : bit; +SIGNAL \UART:Net_1170\ : bit; +SIGNAL \UART:sclk_s_wire\ : bit; +SIGNAL \UART:mosi_s_wire\ : bit; +SIGNAL \UART:miso_m_wire\ : bit; +SIGNAL \UART:tmpOE__tx_net_0\ : bit; +SIGNAL \UART:tx_wire\ : bit; +SIGNAL \UART:tmpFB_0__tx_net_0\ : bit; +SIGNAL \UART:tmpIO_0__tx_net_0\ : bit; +TERMINAL \UART:tmpSIOVREF__tx_net_0\ : bit; +SIGNAL \UART:tmpINTERRUPT_0__tx_net_0\ : bit; +SIGNAL \UART:Net_1099\ : bit; +SIGNAL \UART:Net_1258\ : bit; +SIGNAL \UART:cts_wire\ : bit; +SIGNAL Net_648 : bit; +SIGNAL \UART:rts_wire\ : bit; +SIGNAL \UART:mosi_m_wire\ : bit; +SIGNAL \UART:select_m_wire_3\ : bit; +SIGNAL \UART:select_m_wire_2\ : bit; +SIGNAL \UART:select_m_wire_1\ : bit; +SIGNAL \UART:select_m_wire_0\ : bit; +SIGNAL \UART:sclk_m_wire\ : bit; +SIGNAL \UART:miso_s_wire\ : bit; +SIGNAL Net_672 : bit; +SIGNAL Net_673 : bit; +SIGNAL Net_671 : bit; +SIGNAL Net_670 : bit; +SIGNAL \UART:Net_1028\ : bit; +SIGNAL Net_647 : bit; +SIGNAL Net_656 : bit; +SIGNAL Net_657 : bit; +SIGNAL Net_658 : bit; +SIGNAL Net_659 : bit; +SIGNAL Net_660 : bit; +SIGNAL Net_661 : bit; +SIGNAL Net_662 : bit; +SIGNAL Net_646 : bit; +SIGNAL Net_674 : bit; +TERMINAL Net_664 : bit; +TERMINAL Net_290 : bit; +SIGNAL tmpOE__Input_1_net_0 : bit; +SIGNAL tmpFB_0__Input_1_net_0 : bit; +TERMINAL Net_563 : bit; +SIGNAL tmpIO_0__Input_1_net_0 : bit; +TERMINAL tmpSIOVREF__Input_1_net_0 : bit; +TERMINAL Net_342 : bit; +SIGNAL tmpINTERRUPT_0__Input_1_net_0 : bit; +SIGNAL \ADC:Net_3125\ : bit; +SIGNAL \ADC:Net_3126\ : bit; +SIGNAL \ADC:Net_1845\ : bit; +SIGNAL \ADC:Net_3112\ : bit; +TERMINAL \ADC:Net_3123\ : bit; +TERMINAL \ADC:Net_3121\ : bit; +TERMINAL \ADC:Net_3117\ : bit; +TERMINAL \ADC:Net_124\ : bit; +TERMINAL \ADC:muxout_minus\ : bit; +TERMINAL \ADC:Net_2020\ : bit; +TERMINAL \ADC:muxout_plus\ : bit; +TERMINAL \ADC:Net_3118\ : bit; +TERMINAL \ADC:Net_3119\ : bit; +TERMINAL \ADC:Net_3122\ : bit; +TERMINAL \ADC:mux_bus_plus_0\ : bit; +TERMINAL \ADC:Net_1450_0\ : bit; +TERMINAL \ADC:mux_bus_minus_0\ : bit; +TERMINAL \ADC:Net_1851\ : bit; +TERMINAL \ADC:Net_3016\ : bit; +TERMINAL \ADC:mux_bus_plus_1\ : bit; +TERMINAL \ADC:Net_3147\ : bit; +TERMINAL \ADC:Net_3146\ : bit; +TERMINAL \ADC:Net_3145\ : bit; +TERMINAL \ADC:Net_3144\ : bit; +TERMINAL \ADC:Net_3143\ : bit; +TERMINAL \ADC:Net_3142\ : bit; +TERMINAL \ADC:Net_3141\ : bit; +TERMINAL \ADC:Net_3140\ : bit; +TERMINAL \ADC:Net_3139\ : bit; +TERMINAL \ADC:Net_3138\ : bit; +TERMINAL \ADC:Net_3137\ : bit; +TERMINAL \ADC:Net_3136\ : bit; +TERMINAL \ADC:Net_3135\ : bit; +TERMINAL \ADC:Net_3134\ : bit; +TERMINAL \ADC:Net_3133\ : bit; +TERMINAL \ADC:Net_3132\ : bit; +TERMINAL \ADC:Net_3046\ : bit; +TERMINAL \ADC:mux_bus_minus_1\ : bit; +TERMINAL \ADC:Net_3165\ : bit; +SIGNAL \ADC:Net_3107\ : bit; +SIGNAL \ADC:Net_3106\ : bit; +SIGNAL \ADC:Net_3105\ : bit; +SIGNAL \ADC:Net_3104\ : bit; +SIGNAL \ADC:Net_3103\ : bit; +TERMINAL \ADC:Net_3113\ : bit; +TERMINAL \ADC:Net_43\ : bit; +TERMINAL \ADC:Net_3225\ : bit; +TERMINAL \ADC:Net_2375_0\ : bit; +TERMINAL \ADC:Net_3181\ : bit; +TERMINAL \ADC:Net_3180\ : bit; +TERMINAL \ADC:Net_3179\ : bit; +TERMINAL \ADC:Net_3178\ : bit; +TERMINAL \ADC:Net_3177\ : bit; +TERMINAL \ADC:Net_3176\ : bit; +TERMINAL \ADC:Net_3175\ : bit; +TERMINAL \ADC:Net_3174\ : bit; +TERMINAL \ADC:Net_3173\ : bit; +TERMINAL \ADC:Net_3172\ : bit; +TERMINAL \ADC:Net_3171\ : bit; +TERMINAL \ADC:Net_3170\ : bit; +TERMINAL \ADC:Net_3169\ : bit; +TERMINAL \ADC:Net_3168\ : bit; +TERMINAL \ADC:Net_3167\ : bit; +TERMINAL \ADC:Net_3166\ : bit; +TERMINAL \ADC:Net_8\ : bit; +SIGNAL \ADC:Net_17\ : bit; +SIGNAL Net_666 : bit; +SIGNAL \ADC:Net_3108\ : bit; +SIGNAL \ADC:Net_3109_3\ : bit; +SIGNAL \ADC:Net_3109_2\ : bit; +SIGNAL \ADC:Net_3109_1\ : bit; +SIGNAL \ADC:Net_3109_0\ : bit; +SIGNAL \ADC:Net_3110\ : bit; +SIGNAL \ADC:Net_3111_11\ : bit; +SIGNAL \ADC:Net_3111_10\ : bit; +SIGNAL \ADC:Net_3111_9\ : bit; +SIGNAL \ADC:Net_3111_8\ : bit; +SIGNAL \ADC:Net_3111_7\ : bit; +SIGNAL \ADC:Net_3111_6\ : bit; +SIGNAL \ADC:Net_3111_5\ : bit; +SIGNAL \ADC:Net_3111_4\ : bit; +SIGNAL \ADC:Net_3111_3\ : bit; +SIGNAL \ADC:Net_3111_2\ : bit; +SIGNAL \ADC:Net_3111_1\ : bit; +SIGNAL \ADC:Net_3111_0\ : bit; +SIGNAL Net_667 : bit; +SIGNAL \ADC:Net_3207_1\ : bit; +SIGNAL \ADC:Net_3207_0\ : bit; +SIGNAL \ADC:Net_3235\ : bit; +TERMINAL \ADC:Net_2580_0\ : bit; +TERMINAL \ADC:mux_bus_plus_2\ : bit; +TERMINAL \ADC:mux_bus_plus_3\ : bit; +TERMINAL \ADC:mux_bus_plus_4\ : bit; +TERMINAL \ADC:mux_bus_plus_5\ : bit; +TERMINAL \ADC:mux_bus_plus_6\ : bit; +TERMINAL \ADC:mux_bus_plus_7\ : bit; +TERMINAL \ADC:mux_bus_plus_8\ : bit; +TERMINAL \ADC:mux_bus_plus_9\ : bit; +TERMINAL \ADC:mux_bus_plus_10\ : bit; +TERMINAL \ADC:mux_bus_plus_11\ : bit; +TERMINAL \ADC:mux_bus_plus_12\ : bit; +TERMINAL \ADC:mux_bus_plus_13\ : bit; +TERMINAL \ADC:mux_bus_plus_14\ : bit; +TERMINAL \ADC:mux_bus_plus_15\ : bit; +TERMINAL \ADC:mux_bus_minus_2\ : bit; +TERMINAL \ADC:mux_bus_minus_3\ : bit; +TERMINAL \ADC:mux_bus_minus_4\ : bit; +TERMINAL \ADC:mux_bus_minus_5\ : bit; +TERMINAL \ADC:mux_bus_minus_6\ : bit; +TERMINAL \ADC:mux_bus_minus_7\ : bit; +TERMINAL \ADC:mux_bus_minus_8\ : bit; +TERMINAL \ADC:mux_bus_minus_9\ : bit; +TERMINAL \ADC:mux_bus_minus_10\ : bit; +TERMINAL \ADC:mux_bus_minus_11\ : bit; +TERMINAL \ADC:mux_bus_minus_12\ : bit; +TERMINAL \ADC:mux_bus_minus_13\ : bit; +TERMINAL \ADC:mux_bus_minus_14\ : bit; +TERMINAL \ADC:mux_bus_minus_15\ : bit; +TERMINAL \ADC:Net_3227\ : bit; +BEGIN + +zero <= ('0') ; + +tmpOE__LED_net_0 <= ('1') ; + +LED:cy_psoc3_pins_v1_10 + GENERIC MAP(id=>"52f31aa9-2f0a-497d-9a1f-1424095e13e6", + drive_mode=>"100", + ibuf_enabled=>"1", + init_dr_st=>"1", + input_sync=>"1", + input_clk_en=>'0', + input_sync_mode=>"0", + intr_mode=>"00", + invert_in_clock=>'0', + invert_in_clock_en=>'0', + invert_in_reset=>'0', + invert_out_clock=>'0', + invert_out_clock_en=>'0', + invert_out_reset=>'0', + io_voltage=>"", + layout_mode=>"CONTIGUOUS", + output_conn=>"0", + output_sync=>"0", + output_clk_en=>'0', + output_mode=>"0", + output_reset=>'0', + output_clock_mode=>"0", + oe_sync=>"0", + oe_conn=>"0", + oe_reset=>'0', + pin_aliases=>"", + pin_mode=>"O", + por_state=>4, + sio_group_cnt=>0, + sio_hifreq=>"00000000", + sio_hyst=>"1", + sio_ibuf=>"00000000", + sio_info=>"00", + sio_obuf=>"00000000", + sio_refsel=>"00000000", + sio_vtrip=>"00000000", + sio_vohsel=>"00000000", + slew_rate=>"0", + spanning=>'0', + sw_only=>'0', + vtrip=>"10", + width=>1, + port_alias_required=>'0', + port_alias_group=>"", + use_annotation=>"1", + pa_in_clock=>-1, + pa_in_clock_en=>-1, + pa_in_reset=>-1, + pa_out_clock=>-1, + pa_out_clock_en=>-1, + pa_out_reset=>-1, + ovt_needed=>"0", + ovt_slew_control=>"00", + ovt_hyst_trim=>"0", + input_buffer_sel=>"00") + PORT MAP(oe=>(tmpOE__LED_net_0), + y=>(zero), + fb=>(tmpFB_0__LED_net_0), + analog=>(open), + io=>(tmpIO_0__LED_net_0), + siovref=>(tmpSIOVREF__LED_net_0), + annotation=>Net_644, + in_clock=>zero, + in_clock_en=>tmpOE__LED_net_0, + in_reset=>zero, + out_clock=>zero, + out_clock_en=>tmpOE__LED_net_0, + out_reset=>zero, + interrupt=>tmpINTERRUPT_0__LED_net_0); +\UART:SCBCLK\:cy_clock_v1_0 + GENERIC MAP(cy_registers=>"", + id=>"1ec6effd-8f31-4dd5-a825-0c49238d524e/2dc2d7a8-ce2b-43c7-af4a-821c8cd73ccf", + source_clock_id=>"", + divisor=>0, + period=>"13020833333.3333", + is_direct=>'0', + is_digital=>'0') + PORT MAP(clock_out=>\UART:Net_847\, + dig_domain_out=>open); +\UART:tx\:cy_psoc3_pins_v1_10 + GENERIC MAP(id=>"1ec6effd-8f31-4dd5-a825-0c49238d524e/23b8206d-1c77-4e61-be4a-b4037d5de5fc", + drive_mode=>"110", + ibuf_enabled=>"0", + init_dr_st=>"1", + input_sync=>"0", + input_clk_en=>'0', + input_sync_mode=>"0", + intr_mode=>"00", + invert_in_clock=>'0', + invert_in_clock_en=>'0', + invert_in_reset=>'0', + invert_out_clock=>'0', + invert_out_clock_en=>'0', + invert_out_reset=>'0', + io_voltage=>"", + layout_mode=>"CONTIGUOUS", + output_conn=>"1", + output_sync=>"0", + output_clk_en=>'0', + output_mode=>"0", + output_reset=>'0', + output_clock_mode=>"0", + oe_sync=>"0", + oe_conn=>"0", + oe_reset=>'0', + pin_aliases=>"", + pin_mode=>"B", + por_state=>4, + sio_group_cnt=>0, + sio_hifreq=>"00000000", + sio_hyst=>"1", + sio_ibuf=>"00000000", + sio_info=>"00", + sio_obuf=>"00000000", + sio_refsel=>"00000000", + sio_vtrip=>"00000000", + sio_vohsel=>"00000000", + slew_rate=>"0", + spanning=>'0', + sw_only=>'0', + vtrip=>"00", + width=>1, + port_alias_required=>'0', + port_alias_group=>"", + use_annotation=>"0", + pa_in_clock=>-1, + pa_in_clock_en=>-1, + pa_in_reset=>-1, + pa_out_clock=>-1, + pa_out_clock_en=>-1, + pa_out_reset=>-1, + ovt_needed=>"0", + ovt_slew_control=>"00", + ovt_hyst_trim=>"0", + input_buffer_sel=>"00") + PORT MAP(oe=>(tmpOE__LED_net_0), + y=>\UART:tx_wire\, + fb=>(\UART:tmpFB_0__tx_net_0\), + analog=>(open), + io=>(\UART:tmpIO_0__tx_net_0\), + siovref=>(\UART:tmpSIOVREF__tx_net_0\), + annotation=>(open), + in_clock=>zero, + in_clock_en=>tmpOE__LED_net_0, + in_reset=>zero, + out_clock=>zero, + out_clock_en=>tmpOE__LED_net_0, + out_reset=>zero, + interrupt=>\UART:tmpINTERRUPT_0__tx_net_0\); +\UART:SCB\:cy_m0s8_scb_v2_0 + GENERIC MAP(cy_registers=>"", + scb_mode=>2) + PORT MAP(clock=>\UART:Net_847\, + interrupt=>Net_648, + rx=>zero, + tx=>\UART:tx_wire\, + cts=>zero, + rts=>\UART:rts_wire\, + mosi_m=>\UART:mosi_m_wire\, + miso_m=>zero, + select_m=>(\UART:select_m_wire_3\, \UART:select_m_wire_2\, \UART:select_m_wire_1\, \UART:select_m_wire_0\), + sclk_m=>\UART:sclk_m_wire\, + mosi_s=>zero, + miso_s=>\UART:miso_s_wire\, + select_s=>zero, + sclk_s=>zero, + scl=>Net_672, + sda=>Net_673, + tx_req=>Net_671, + rx_req=>Net_670); +PWR:cy_annotation_universal_v1_0 + GENERIC MAP(comp_name=>"Power_v1_0", + port_names=>"T1", + width=>1) + PORT MAP(connect=>Net_664); +R:cy_annotation_universal_v1_0 + GENERIC MAP(comp_name=>"Resistor_v1_0", + port_names=>"T1, T2", + width=>2) + PORT MAP(connect=>(Net_290, Net_644)); +Input_1:cy_psoc3_pins_v1_10 + GENERIC MAP(id=>"0b0fcf5d-629b-4f61-a95a-c0d71e4b1f3e", + drive_mode=>"000", + ibuf_enabled=>"0", + init_dr_st=>"1", + input_sync=>"1", + input_clk_en=>'0', + input_sync_mode=>"0", + intr_mode=>"00", + invert_in_clock=>'0', + invert_in_clock_en=>'0', + invert_in_reset=>'0', + invert_out_clock=>'0', + invert_out_clock_en=>'0', + invert_out_reset=>'0', + io_voltage=>"", + layout_mode=>"CONTIGUOUS", + output_conn=>"0", + output_sync=>"0", + output_clk_en=>'0', + output_mode=>"0", + output_reset=>'0', + output_clock_mode=>"0", + oe_sync=>"0", + oe_conn=>"0", + oe_reset=>'0', + pin_aliases=>"", + pin_mode=>"A", + por_state=>4, + sio_group_cnt=>0, + sio_hifreq=>"00000000", + sio_hyst=>"1", + sio_ibuf=>"00000000", + sio_info=>"00", + sio_obuf=>"00000000", + sio_refsel=>"00000000", + sio_vtrip=>"00000000", + sio_vohsel=>"00000000", + slew_rate=>"0", + spanning=>'0', + sw_only=>'0', + vtrip=>"10", + width=>1, + port_alias_required=>'0', + port_alias_group=>"", + use_annotation=>"1", + pa_in_clock=>-1, + pa_in_clock_en=>-1, + pa_in_reset=>-1, + pa_out_clock=>-1, + pa_out_clock_en=>-1, + pa_out_reset=>-1, + ovt_needed=>"0", + ovt_slew_control=>"00", + ovt_hyst_trim=>"0", + input_buffer_sel=>"00") + PORT MAP(oe=>(tmpOE__LED_net_0), + y=>(zero), + fb=>(tmpFB_0__Input_1_net_0), + analog=>Net_563, + io=>(tmpIO_0__Input_1_net_0), + siovref=>(tmpSIOVREF__Input_1_net_0), + annotation=>Net_342, + in_clock=>zero, + in_clock_en=>tmpOE__LED_net_0, + in_reset=>zero, + out_clock=>zero, + out_clock_en=>tmpOE__LED_net_0, + out_reset=>zero, + interrupt=>tmpINTERRUPT_0__Input_1_net_0); +\ADC:IRQ\:cy_isr_v1_0 + GENERIC MAP(int_type=>"10", + is_nmi=>'0') + PORT MAP(int_signal=>\ADC:Net_3112\); +\ADC:cy_analog_noconnect_44\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3123\); +\ADC:cy_analog_noconnect_40\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3121\); +\ADC:cy_analog_noconnect_39\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3117\); +\ADC:cy_analog_virtualmux_43_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_124\, + signal2=>\ADC:muxout_minus\); +\ADC:cy_analog_virtualmux_42_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_2020\, + signal2=>\ADC:muxout_plus\); +\ADC:cy_analog_noconnect_38\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3118\); +\ADC:cy_analog_noconnect_41\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3119\); +\ADC:cy_analog_noconnect_43\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3122\); +\ADC:adc_plus_in_sel_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:muxout_plus\, + signal2=>\ADC:mux_bus_plus_0\); +\ADC:Connect_1:bus_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>(\ADC:mux_bus_plus_0\), + signal2=>(\ADC:Net_1450_0\)); +\ADC:adc_minus_in_sel_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:muxout_minus\, + signal2=>\ADC:mux_bus_minus_0\); +\ADC:cy_analog_noconnect_3\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_1851\); +\ADC:cy_analog_virtualmux_37_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_3016\, + signal2=>\ADC:mux_bus_plus_1\); +\ADC:cy_analog_noconnect_21\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3147\); +\ADC:cy_analog_noconnect_20\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3146\); +\ADC:cy_analog_noconnect_19\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3145\); +\ADC:cy_analog_noconnect_18\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3144\); +\ADC:cy_analog_noconnect_17\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3143\); +\ADC:cy_analog_noconnect_16\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3142\); +\ADC:cy_analog_noconnect_15\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3141\); +\ADC:cy_analog_noconnect_14\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3140\); +\ADC:cy_analog_noconnect_13\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3139\); +\ADC:cy_analog_noconnect_12\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3138\); +\ADC:cy_analog_noconnect_11\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3137\); +\ADC:cy_analog_noconnect_10\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3136\); +\ADC:cy_analog_noconnect_9\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3135\); +\ADC:cy_analog_noconnect_8\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3134\); +\ADC:cy_analog_noconnect_7\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3133\); +\ADC:cy_analog_noconnect_6\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3132\); +\ADC:cy_analog_virtualmux_36_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_3046\, + signal2=>\ADC:mux_bus_minus_1\); +\ADC:cy_analog_noconnect_37\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3165\); +\ADC:cy_analog_noconnect_1\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3113\); +\ADC:ext_vref_sel_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_43\, + signal2=>\ADC:Net_3225\); +\ADC:Connect_2:bus_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>(\ADC:mux_bus_minus_0\), + signal2=>(\ADC:Net_2375_0\)); +\ADC:cy_analog_noconnect_35\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3181\); +\ADC:cy_analog_noconnect_34\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3180\); +\ADC:cy_analog_noconnect_33\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3179\); +\ADC:cy_analog_noconnect_32\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3178\); +\ADC:cy_analog_noconnect_31\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3177\); +\ADC:cy_analog_noconnect_30\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3176\); +\ADC:cy_analog_noconnect_29\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3175\); +\ADC:cy_analog_noconnect_28\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3174\); +\ADC:cy_analog_noconnect_27\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3173\); +\ADC:cy_analog_noconnect_26\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3172\); +\ADC:cy_analog_noconnect_25\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3171\); +\ADC:cy_analog_noconnect_24\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3170\); +\ADC:cy_analog_noconnect_23\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3169\); +\ADC:cy_analog_noconnect_22\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3168\); +\ADC:cy_analog_noconnect_4\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3167\); +\ADC:cy_analog_noconnect_2\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3166\); +\ADC:int_vref_sel_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_8\, + signal2=>\ADC:Net_3113\); +\ADC:cy_psoc4_sar\:cy_psoc4_sar_v1_0 + GENERIC MAP(cy_registers=>"") + PORT MAP(vplus=>\ADC:Net_2020\, + vminus=>\ADC:Net_124\, + vref=>\ADC:Net_8\, + ext_vref=>\ADC:Net_43\, + clock=>\ADC:Net_1845\, + sample_done=>Net_666, + chan_id_valid=>\ADC:Net_3108\, + chan_id=>(\ADC:Net_3109_3\, \ADC:Net_3109_2\, \ADC:Net_3109_1\, \ADC:Net_3109_0\), + data_valid=>\ADC:Net_3110\, + data=>(\ADC:Net_3111_11\, \ADC:Net_3111_10\, \ADC:Net_3111_9\, \ADC:Net_3111_8\, + \ADC:Net_3111_7\, \ADC:Net_3111_6\, \ADC:Net_3111_5\, \ADC:Net_3111_4\, + \ADC:Net_3111_3\, \ADC:Net_3111_2\, \ADC:Net_3111_1\, \ADC:Net_3111_0\), + eos_intr=>Net_667, + irq=>\ADC:Net_3112\, + sw_negvref=>zero, + cfg_st_sel=>(zero, zero), + cfg_average=>zero, + cfg_resolution=>zero, + cfg_differential=>zero, + trigger=>zero, + data_hilo_sel=>zero); +\ADC:ext_vneg_sel_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>(\ADC:Net_2580_0\), + signal2=>\ADC:Net_1851\); +\ADC:cy_analog_virtualmux_vplus0_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_0\, + signal2=>Net_563); +\ADC:cy_analog_virtualmux_vplus1_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_1\, + signal2=>\ADC:Net_3132\); +\ADC:cy_analog_virtualmux_vplus2_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_2\, + signal2=>\ADC:Net_3133\); +\ADC:cy_analog_virtualmux_vplus3_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_3\, + signal2=>\ADC:Net_3134\); +\ADC:cy_analog_virtualmux_vplus4_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_4\, + signal2=>\ADC:Net_3135\); +\ADC:cy_analog_virtualmux_vplus5_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_5\, + signal2=>\ADC:Net_3136\); +\ADC:cy_analog_virtualmux_vplus6_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_6\, + signal2=>\ADC:Net_3137\); +\ADC:cy_analog_virtualmux_vplus7_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_7\, + signal2=>\ADC:Net_3138\); +\ADC:cy_analog_virtualmux_vplus8_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_8\, + signal2=>\ADC:Net_3139\); +\ADC:cy_analog_virtualmux_vplus9_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_9\, + signal2=>\ADC:Net_3140\); +\ADC:cy_analog_virtualmux_vplus10_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_10\, + signal2=>\ADC:Net_3141\); +\ADC:cy_analog_virtualmux_vplus11_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_11\, + signal2=>\ADC:Net_3142\); +\ADC:cy_analog_virtualmux_vplus12_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_12\, + signal2=>\ADC:Net_3143\); +\ADC:cy_analog_virtualmux_vplus13_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_13\, + signal2=>\ADC:Net_3144\); +\ADC:cy_analog_virtualmux_vplus14_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_14\, + signal2=>\ADC:Net_3145\); +\ADC:cy_analog_virtualmux_vplus15_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_plus_15\, + signal2=>\ADC:Net_3146\); +\ADC:cy_analog_virtualmux_vplus_inj_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_3016\, + signal2=>\ADC:Net_3147\); +\ADC:cy_analog_virtualmux_vminus0_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_0\, + signal2=>\ADC:Net_3166\); +\ADC:cy_analog_virtualmux_vminus1_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_1\, + signal2=>\ADC:Net_3167\); +\ADC:cy_analog_virtualmux_vminus2_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_2\, + signal2=>\ADC:Net_3168\); +\ADC:cy_analog_virtualmux_vminus3_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_3\, + signal2=>\ADC:Net_3169\); +\ADC:cy_analog_virtualmux_vminus4_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_4\, + signal2=>\ADC:Net_3170\); +\ADC:cy_analog_virtualmux_vminus5_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_5\, + signal2=>\ADC:Net_3171\); +\ADC:cy_analog_virtualmux_vminus6_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_6\, + signal2=>\ADC:Net_3172\); +\ADC:cy_analog_virtualmux_vminus7_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_7\, + signal2=>\ADC:Net_3173\); +\ADC:cy_analog_virtualmux_vminus8_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_8\, + signal2=>\ADC:Net_3174\); +\ADC:cy_analog_virtualmux_vminus9_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_9\, + signal2=>\ADC:Net_3175\); +\ADC:cy_analog_virtualmux_vminus10_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_10\, + signal2=>\ADC:Net_3176\); +\ADC:cy_analog_virtualmux_vminus11_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_11\, + signal2=>\ADC:Net_3177\); +\ADC:cy_analog_virtualmux_vminus12_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_12\, + signal2=>\ADC:Net_3178\); +\ADC:cy_analog_virtualmux_vminus13_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_13\, + signal2=>\ADC:Net_3179\); +\ADC:cy_analog_virtualmux_vminus14_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_14\, + signal2=>\ADC:Net_3180\); +\ADC:cy_analog_virtualmux_vminus15_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:mux_bus_minus_15\, + signal2=>\ADC:Net_3181\); +\ADC:cy_analog_virtualmux_vminus_inj_connect\:cy_connect_v1_0 + GENERIC MAP(sig_width=>1, + is_net_join=>'0') + PORT MAP(signal1=>\ADC:Net_3046\, + signal2=>\ADC:Net_3165\); +\ADC:intClock\:cy_clock_v1_0 + GENERIC MAP(cy_registers=>"", + id=>"9a67a4bd-024a-4dec-ac06-ad54a4dde89a/5c71752a-e182-47ca-942c-9cb20adbdf2f", + source_clock_id=>"", + divisor=>0, + period=>"1000000000", + is_direct=>'0', + is_digital=>'0') + PORT MAP(clock_out=>\ADC:Net_1845\, + dig_domain_out=>open); +\ADC:cy_analog_noconnect_5\:cy_analog_noconnect_v1_0 + PORT MAP(noconnect=>\ADC:Net_3227\); +LED1:cy_annotation_universal_v1_0 + GENERIC MAP(comp_name=>"LED_v1_0", + port_names=>"A, K", + width=>2) + PORT MAP(connect=>(Net_664, Net_290)); + +END R_T_L; diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.wde b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.wde new file mode 100644 index 0000000..38e1638 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART.wde @@ -0,0 +1,12 @@ +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif +ADC-UART.ctl +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v +ADC-UART.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Bus_Connect_v2_50\Bus_Connect_v2_50.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.lib b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.lib new file mode 100644 index 0000000..4f12547 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.lib @@ -0,0 +1,533 @@ +library (timing) { + timescale : 1ns; + capacitive_load_unit (1,ff); + include_file(device.lib); + cell (iocell1) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.205; + intrinsic_fall : 12.205; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.819; + intrinsic_fall : 13.819; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 6.106; + intrinsic_fall : 6.106; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 7.555; + intrinsic_fall : 7.555; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 12.020; + intrinsic_fall : 12.020; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 14.424; + intrinsic_fall : 14.424; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 12.922; + intrinsic_fall : 12.922; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.420; + intrinsic_fall : 15.420; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.446; + intrinsic_fall : 12.446; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.717; + intrinsic_fall : 14.717; + } + } + } + cell (iocell2) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 11.665; + intrinsic_fall : 11.665; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.279; + intrinsic_fall : 13.279; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 6.746; + intrinsic_fall : 6.746; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 8.195; + intrinsic_fall : 8.195; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 12.660; + intrinsic_fall : 12.660; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 15.064; + intrinsic_fall : 15.064; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.462; + intrinsic_fall : 15.462; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 17.960; + intrinsic_fall : 17.960; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 11.906; + intrinsic_fall : 11.906; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.177; + intrinsic_fall : 14.177; + } + } + } + cell (iocell3) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.845; + intrinsic_fall : 12.845; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.459; + intrinsic_fall : 14.459; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 8.356; + intrinsic_fall : 8.356; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 9.805; + intrinsic_fall : 9.805; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 14.270; + intrinsic_fall : 14.270; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.674; + intrinsic_fall : 16.674; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 16.092; + intrinsic_fall : 16.092; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 18.590; + intrinsic_fall : 18.590; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.086; + intrinsic_fall : 13.086; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 15.357; + intrinsic_fall : 15.357; + } + } + } +} diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.pco b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.pco new file mode 100644 index 0000000..dab073d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.pco @@ -0,0 +1,10 @@ +dont_use_io iocell 3 2 +dont_use_io iocell 3 3 +set_location "ClockBlock" m0s8clockblockcell -1 -1 0 +set_location "ClockGenBlock" m0s8clockgenblockcell -1 -1 0 +set_io "\UART:tx(0)\" iocell 4 1 +set_location "\ADC:IRQ\" interrupt -1 -1 14 +set_io "LED(0)" iocell 1 6 +set_io "Input_1(0)" iocell 2 3 +set_location "\UART:SCB\" m0s8scbcell -1 -1 0 +set_location "\ADC:cy_psoc4_sar\" p4sarcell -1 -1 0 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.vh2 b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.vh2 new file mode 100644 index 0000000..3f2067c --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_p.vh2 @@ -0,0 +1,666 @@ +-- Project: ADC-UART +-- Generated: 07/17/2020 10:59:52 +-- PSoC Creator 4.2 + +ENTITY \ADC-UART\ IS + PORT( + LED(0)_PAD : OUT std_ulogic; + \UART:tx(0)_PAD\ : INOUT std_ulogic); + ATTRIBUTE voltage_VDDA OF __DEFAULT__ : ENTITY IS 5e0; + ATTRIBUTE voltage_VDDD OF __DEFAULT__ : ENTITY IS 5e0; +END \ADC-UART\; + +ARCHITECTURE __DEFAULT__ OF \ADC-UART\ IS + SIGNAL ClockBlock_EXTCLK : bit; + SIGNAL ClockBlock_HFCLK : bit; + ATTRIBUTE global_signal OF ClockBlock_HFCLK : SIGNAL IS true; + SIGNAL ClockBlock_ILO : bit; + SIGNAL ClockBlock_IMO : bit; + SIGNAL ClockBlock_LFCLK : bit; + SIGNAL ClockBlock_Routed1 : bit; + SIGNAL ClockBlock_SYSCLK : bit; + SIGNAL Input_1(0)__PA : bit; + SIGNAL LED(0)__PA : bit; + SIGNAL Net_648 : bit; + SIGNAL Net_666 : bit; + SIGNAL Net_667 : bit; + SIGNAL Net_670 : bit; + SIGNAL Net_671 : bit; + SIGNAL \ADC:Net_1845_ff7\ : bit; + ATTRIBUTE global_signal OF \ADC:Net_1845_ff7\ : SIGNAL IS true; + SIGNAL \ADC:Net_3108\ : bit; + SIGNAL \ADC:Net_3109_0\ : bit; + SIGNAL \ADC:Net_3109_1\ : bit; + SIGNAL \ADC:Net_3109_2\ : bit; + SIGNAL \ADC:Net_3109_3\ : bit; + SIGNAL \ADC:Net_3110\ : bit; + SIGNAL \ADC:Net_3111_0\ : bit; + SIGNAL \ADC:Net_3111_10\ : bit; + SIGNAL \ADC:Net_3111_11\ : bit; + SIGNAL \ADC:Net_3111_1\ : bit; + SIGNAL \ADC:Net_3111_2\ : bit; + SIGNAL \ADC:Net_3111_3\ : bit; + SIGNAL \ADC:Net_3111_4\ : bit; + SIGNAL \ADC:Net_3111_5\ : bit; + SIGNAL \ADC:Net_3111_6\ : bit; + SIGNAL \ADC:Net_3111_7\ : bit; + SIGNAL \ADC:Net_3111_8\ : bit; + SIGNAL \ADC:Net_3111_9\ : bit; + SIGNAL \ADC:Net_3112\ : bit; + SIGNAL \UART:Net_847_ff2\ : bit; + ATTRIBUTE global_signal OF \UART:Net_847_ff2\ : SIGNAL IS true; + SIGNAL \UART:miso_s_wire\ : bit; + SIGNAL \UART:mosi_m_wire\ : bit; + SIGNAL \UART:rts_wire\ : bit; + SIGNAL \UART:sclk_m_wire\ : bit; + SIGNAL \UART:select_m_wire_0\ : bit; + SIGNAL \UART:select_m_wire_1\ : bit; + SIGNAL \UART:select_m_wire_2\ : bit; + SIGNAL \UART:select_m_wire_3\ : bit; + SIGNAL \\\UART:tx(0)\\__PA\ : bit; + SIGNAL \UART:tx_wire\ : bit; + SIGNAL __ONE__ : bit; + ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; + SIGNAL __ZERO__ : bit; + ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; + SIGNAL tmpOE__LED_net_0 : bit; + ATTRIBUTE POWER OF tmpOE__LED_net_0 : SIGNAL IS true; + SIGNAL zero : bit; + ATTRIBUTE GROUND OF zero : SIGNAL IS true; + ATTRIBUTE Location OF ClockGenBlock : LABEL IS "F(CLK_GEN,0)"; + ATTRIBUTE lib_model OF LED(0) : LABEL IS "iocell1"; + ATTRIBUTE Location OF LED(0) : LABEL IS "P1[6]"; + ATTRIBUTE lib_model OF \UART:tx(0)\ : LABEL IS "iocell2"; + ATTRIBUTE Location OF \UART:tx(0)\ : LABEL IS "P4[1]"; + ATTRIBUTE lib_model OF Input_1(0) : LABEL IS "iocell3"; + ATTRIBUTE Location OF Input_1(0) : LABEL IS "P2[3]"; + ATTRIBUTE Location OF \ADC:cy_psoc4_sar\ : LABEL IS "F(SARADC,0)"; + COMPONENT interrupt + PORT ( + interrupt : IN std_ulogic; + clock : IN std_ulogic); + END COMPONENT; + COMPONENT iocell + PORT ( + oe : IN std_ulogic; + fb : OUT std_ulogic; + pa_out : OUT std_ulogic; + pin_input : IN std_ulogic; + pad_in : IN std_ulogic; + pad_out : OUT std_ulogic; + oe_reg : OUT std_ulogic; + oe_internal : IN std_ulogic; + in_clock : IN std_ulogic; + in_clock_en : IN std_ulogic; + in_reset : IN std_ulogic; + out_clock : IN std_ulogic; + out_clock_en : IN std_ulogic; + out_reset : IN std_ulogic); + END COMPONENT; + COMPONENT logicalport + PORT ( + interrupt : OUT std_ulogic; + precharge : IN std_ulogic; + in_clock : IN std_ulogic; + in_clock_en : IN std_ulogic; + in_reset : IN std_ulogic; + out_clock : IN std_ulogic; + out_clock_en : IN std_ulogic; + out_reset : IN std_ulogic); + END COMPONENT; + COMPONENT m0s8clockblockcell + PORT ( + imo : OUT std_ulogic; + ext : OUT std_ulogic; + eco : OUT std_ulogic; + ilo : OUT std_ulogic; + wco : OUT std_ulogic; + dbl : OUT std_ulogic; + pll : OUT std_ulogic; + dpll : OUT std_ulogic; + dsi_out_0 : IN std_ulogic; + dsi_out_1 : IN std_ulogic; + dsi_out_2 : IN std_ulogic; + dsi_out_3 : IN std_ulogic; + lfclk : OUT std_ulogic; + hfclk : OUT std_ulogic; + sysclk : OUT std_ulogic; + halfsysclk : OUT std_ulogic; + udb_div_0 : OUT std_ulogic; + udb_div_1 : OUT std_ulogic; + udb_div_2 : OUT std_ulogic; + udb_div_3 : OUT std_ulogic; + udb_div_4 : OUT std_ulogic; + udb_div_5 : OUT std_ulogic; + udb_div_6 : OUT std_ulogic; + udb_div_7 : OUT std_ulogic; + udb_div_8 : OUT std_ulogic; + udb_div_9 : OUT std_ulogic; + udb_div_10 : OUT std_ulogic; + udb_div_11 : OUT std_ulogic; + udb_div_12 : OUT std_ulogic; + udb_div_13 : OUT std_ulogic; + udb_div_14 : OUT std_ulogic; + udb_div_15 : OUT std_ulogic; + uab_div_0 : OUT std_ulogic; + uab_div_1 : OUT std_ulogic; + uab_div_2 : OUT std_ulogic; + uab_div_3 : OUT std_ulogic; + ff_div_0 : OUT std_ulogic; + ff_div_1 : OUT std_ulogic; + ff_div_2 : OUT std_ulogic; + ff_div_3 : OUT std_ulogic; + ff_div_4 : OUT std_ulogic; + ff_div_5 : OUT std_ulogic; + ff_div_6 : OUT std_ulogic; + ff_div_7 : OUT std_ulogic; + ff_div_8 : OUT std_ulogic; + ff_div_9 : OUT std_ulogic; + ff_div_10 : OUT std_ulogic; + ff_div_11 : OUT std_ulogic; + ff_div_12 : OUT std_ulogic; + ff_div_13 : OUT std_ulogic; + ff_div_14 : OUT std_ulogic; + ff_div_15 : OUT std_ulogic; + ff_div_16 : OUT std_ulogic; + ff_div_17 : OUT std_ulogic; + ff_div_18 : OUT std_ulogic; + ff_div_19 : OUT std_ulogic; + ff_div_20 : OUT std_ulogic; + ff_div_21 : OUT std_ulogic; + ff_div_22 : OUT std_ulogic; + ff_div_23 : OUT std_ulogic; + ff_div_24 : OUT std_ulogic; + ff_div_25 : OUT std_ulogic; + ff_div_26 : OUT std_ulogic; + ff_div_27 : OUT std_ulogic; + ff_div_28 : OUT std_ulogic; + ff_div_29 : OUT std_ulogic; + ff_div_30 : OUT std_ulogic; + ff_div_31 : OUT std_ulogic; + ff_div_32 : OUT std_ulogic; + ff_div_33 : OUT std_ulogic; + ff_div_34 : OUT std_ulogic; + ff_div_35 : OUT std_ulogic; + ff_div_36 : OUT std_ulogic; + ff_div_37 : OUT std_ulogic; + ff_div_38 : OUT std_ulogic; + ff_div_39 : OUT std_ulogic; + ff_div_40 : OUT std_ulogic; + ff_div_41 : OUT std_ulogic; + ff_div_42 : OUT std_ulogic; + ff_div_43 : OUT std_ulogic; + ff_div_44 : OUT std_ulogic; + ff_div_45 : OUT std_ulogic; + ff_div_46 : OUT std_ulogic; + ff_div_47 : OUT std_ulogic; + ff_div_48 : OUT std_ulogic; + ff_div_49 : OUT std_ulogic; + ff_div_50 : OUT std_ulogic; + ff_div_51 : OUT std_ulogic; + ff_div_52 : OUT std_ulogic; + ff_div_53 : OUT std_ulogic; + ff_div_54 : OUT std_ulogic; + ff_div_55 : OUT std_ulogic; + ff_div_56 : OUT std_ulogic; + ff_div_57 : OUT std_ulogic; + ff_div_58 : OUT std_ulogic; + ff_div_59 : OUT std_ulogic; + ff_div_60 : OUT std_ulogic; + ff_div_61 : OUT std_ulogic; + ff_div_62 : OUT std_ulogic; + ff_div_63 : OUT std_ulogic; + dsi_in_0 : OUT std_ulogic; + dsi_in_1 : OUT std_ulogic; + dsi_in_2 : OUT std_ulogic; + dsi_in_3 : OUT std_ulogic); + END COMPONENT; + COMPONENT m0s8clockgenblockcell + PORT ( + gen_clk_in_0 : IN std_ulogic; + gen_clk_in_1 : IN std_ulogic; + gen_clk_in_2 : IN std_ulogic; + gen_clk_in_3 : IN std_ulogic; + gen_clk_in_4 : IN std_ulogic; + gen_clk_in_5 : IN std_ulogic; + gen_clk_in_6 : IN std_ulogic; + gen_clk_in_7 : IN std_ulogic; + gen_clk_out_0 : OUT std_ulogic; + gen_clk_out_1 : OUT std_ulogic; + gen_clk_out_2 : OUT std_ulogic; + gen_clk_out_3 : OUT std_ulogic; + gen_clk_out_4 : OUT std_ulogic; + gen_clk_out_5 : OUT std_ulogic; + gen_clk_out_6 : OUT std_ulogic; + gen_clk_out_7 : OUT std_ulogic); + END COMPONENT; + COMPONENT m0s8scbcell + PORT ( + clock : IN std_ulogic; + interrupt : OUT std_ulogic; + uart_cts : IN std_ulogic; + uart_rts : OUT std_ulogic; + uart_rx : IN std_ulogic; + uart_tx : OUT std_ulogic; + mosi_m : OUT std_ulogic; + miso_m : IN std_ulogic; + select_m_0 : OUT std_ulogic; + select_m_1 : OUT std_ulogic; + select_m_2 : OUT std_ulogic; + select_m_3 : OUT std_ulogic; + sclk_m : OUT std_ulogic; + mosi_s : IN std_ulogic; + miso_s : OUT std_ulogic; + select_s : IN std_ulogic; + sclk_s : IN std_ulogic; + i2c_scl : IN std_ulogic; + i2c_sda : IN std_ulogic; + tr_rx_req : OUT std_ulogic; + tr_tx_req : OUT std_ulogic); + END COMPONENT; + COMPONENT p4sarcell + PORT ( + clock : IN std_ulogic; + sample_done : OUT std_ulogic; + chan_id_valid : OUT std_ulogic; + chan_id_0 : OUT std_ulogic; + chan_id_1 : OUT std_ulogic; + chan_id_2 : OUT std_ulogic; + chan_id_3 : OUT std_ulogic; + data_valid : OUT std_ulogic; + data_0 : OUT std_ulogic; + data_1 : OUT std_ulogic; + data_2 : OUT std_ulogic; + data_3 : OUT std_ulogic; + data_4 : OUT std_ulogic; + data_5 : OUT std_ulogic; + data_6 : OUT std_ulogic; + data_7 : OUT std_ulogic; + data_8 : OUT std_ulogic; + data_9 : OUT std_ulogic; + data_10 : OUT std_ulogic; + data_11 : OUT std_ulogic; + eos_intr : OUT std_ulogic; + tr_sar_out : OUT std_ulogic; + irq : OUT std_ulogic; + sw_negvref : IN std_ulogic; + cfg_st_sel_0 : IN std_ulogic; + cfg_st_sel_1 : IN std_ulogic; + cfg_average : IN std_ulogic; + cfg_resolution : IN std_ulogic; + cfg_differential : IN std_ulogic; + tr_sar_in : IN std_ulogic; + data_hilo_sel : IN std_ulogic; + swctrl_0 : IN std_ulogic; + swctrl_1 : IN std_ulogic; + data_out_0 : IN std_ulogic; + data_out_1 : IN std_ulogic; + data_out_2 : IN std_ulogic; + data_out_3 : IN std_ulogic; + data_out_4 : IN std_ulogic; + data_out_5 : IN std_ulogic; + data_out_6 : IN std_ulogic; + data_out_7 : IN std_ulogic; + data_oe_0 : IN std_ulogic; + data_oe_1 : IN std_ulogic; + data_oe_2 : IN std_ulogic; + data_oe_3 : IN std_ulogic); + END COMPONENT; +BEGIN + + ClockGenBlock:m0s8clockgenblockcell; + + ClockBlock:m0s8clockblockcell + PORT MAP( + hfclk => ClockBlock_HFCLK, + imo => ClockBlock_IMO, + ext => ClockBlock_EXTCLK, + sysclk => ClockBlock_SYSCLK, + ilo => ClockBlock_ILO, + lfclk => ClockBlock_LFCLK, + dsi_in_0 => ClockBlock_Routed1, + ff_div_7 => \ADC:Net_1845_ff7\, + ff_div_2 => \UART:Net_847_ff2\); + + LED:logicalport + GENERIC MAP( + drive_mode => "100", + ibuf_enabled => "1", + id => "52f31aa9-2f0a-497d-9a1f-1424095e13e6", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "0", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "O", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "1", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + LED(0):iocell + GENERIC MAP( + port_location => "PORT(1,6)", + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "LED", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => LED(0)__PA, + oe => open, + pad_in => LED(0)_PAD, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + \UART:tx\:logicalport + GENERIC MAP( + drive_mode => "110", + ibuf_enabled => "0", + id => "1ec6effd-8f31-4dd5-a825-0c49238d524e/23b8206d-1c77-4e61-be4a-b4037d5de5fc", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "0", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "1", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "B", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "0", + vtrip => "00", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + \UART:tx(0)\:iocell + GENERIC MAP( + port_location => "PORT(0,5)", + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "\UART:tx\", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => \\\UART:tx(0)\\__PA\, + oe => open, + pin_input => \UART:tx_wire\, + pad_out => \UART:tx(0)_PAD\, + pad_in => \UART:tx(0)_PAD\, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + Input_1:logicalport + GENERIC MAP( + drive_mode => "000", + ibuf_enabled => "0", + id => "0b0fcf5d-629b-4f61-a95a-c0d71e4b1f3e", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "0", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "A", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "1", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + Input_1(0):iocell + GENERIC MAP( + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "Input_1", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000010") + PORT MAP( + pa_out => Input_1(0)__PA, + oe => open, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + \UART:SCB\:m0s8scbcell + GENERIC MAP( + cy_registers => "", + scb_mode => 2) + PORT MAP( + clock => \UART:Net_847_ff2\, + interrupt => Net_648, + uart_rx => open, + uart_tx => \UART:tx_wire\, + uart_cts => open, + uart_rts => \UART:rts_wire\, + mosi_m => \UART:mosi_m_wire\, + miso_m => open, + select_m_3 => \UART:select_m_wire_3\, + select_m_2 => \UART:select_m_wire_2\, + select_m_1 => \UART:select_m_wire_1\, + select_m_0 => \UART:select_m_wire_0\, + sclk_m => \UART:sclk_m_wire\, + mosi_s => open, + miso_s => \UART:miso_s_wire\, + select_s => open, + sclk_s => open, + tr_tx_req => Net_671, + tr_rx_req => Net_670); + + \ADC:IRQ\:interrupt + GENERIC MAP( + int_type => "10", + is_nmi => 0) + PORT MAP( + interrupt => \ADC:Net_3112\, + clock => ClockBlock_HFCLK); + + \ADC:cy_psoc4_sar\:p4sarcell + GENERIC MAP( + cy_registers => "") + PORT MAP( + clock => \ADC:Net_1845_ff7\, + sample_done => Net_666, + chan_id_valid => \ADC:Net_3108\, + chan_id_3 => \ADC:Net_3109_3\, + chan_id_2 => \ADC:Net_3109_2\, + chan_id_1 => \ADC:Net_3109_1\, + chan_id_0 => \ADC:Net_3109_0\, + data_valid => \ADC:Net_3110\, + data_11 => \ADC:Net_3111_11\, + data_10 => \ADC:Net_3111_10\, + data_9 => \ADC:Net_3111_9\, + data_8 => \ADC:Net_3111_8\, + data_7 => \ADC:Net_3111_7\, + data_6 => \ADC:Net_3111_6\, + data_5 => \ADC:Net_3111_5\, + data_4 => \ADC:Net_3111_4\, + data_3 => \ADC:Net_3111_3\, + data_2 => \ADC:Net_3111_2\, + data_1 => \ADC:Net_3111_1\, + data_0 => \ADC:Net_3111_0\, + eos_intr => Net_667, + irq => \ADC:Net_3112\, + sw_negvref => open, + cfg_st_sel_1 => open, + cfg_st_sel_0 => open, + cfg_average => open, + cfg_resolution => open, + cfg_differential => open, + tr_sar_in => open, + data_hilo_sel => open); + +END __DEFAULT__; diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_r.lib b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_r.lib new file mode 100644 index 0000000..4f12547 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_r.lib @@ -0,0 +1,533 @@ +library (timing) { + timescale : 1ns; + capacitive_load_unit (1,ff); + include_file(device.lib); + cell (iocell1) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.205; + intrinsic_fall : 12.205; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.819; + intrinsic_fall : 13.819; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 6.106; + intrinsic_fall : 6.106; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 7.555; + intrinsic_fall : 7.555; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 12.020; + intrinsic_fall : 12.020; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 14.424; + intrinsic_fall : 14.424; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 12.922; + intrinsic_fall : 12.922; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.420; + intrinsic_fall : 15.420; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.446; + intrinsic_fall : 12.446; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.717; + intrinsic_fall : 14.717; + } + } + } + cell (iocell2) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 11.665; + intrinsic_fall : 11.665; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.279; + intrinsic_fall : 13.279; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 6.746; + intrinsic_fall : 6.746; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 8.195; + intrinsic_fall : 8.195; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 12.660; + intrinsic_fall : 12.660; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 15.064; + intrinsic_fall : 15.064; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.462; + intrinsic_fall : 15.462; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 17.960; + intrinsic_fall : 17.960; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 11.906; + intrinsic_fall : 11.906; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.177; + intrinsic_fall : 14.177; + } + } + } + cell (iocell3) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.845; + intrinsic_fall : 12.845; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.459; + intrinsic_fall : 14.459; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 8.356; + intrinsic_fall : 8.356; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 9.805; + intrinsic_fall : 9.805; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 14.270; + intrinsic_fall : 14.270; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.674; + intrinsic_fall : 16.674; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 16.092; + intrinsic_fall : 16.092; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 18.590; + intrinsic_fall : 18.590; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.086; + intrinsic_fall : 13.086; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 15.357; + intrinsic_fall : 15.357; + } + } + } +} diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_r.vh2 b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_r.vh2 new file mode 100644 index 0000000..2bf2636 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_r.vh2 @@ -0,0 +1,669 @@ +-- Project: ADC-UART +-- Generated: 07/17/2020 10:59:53 +-- PSoC Creator 4.2 + +ENTITY \ADC-UART\ IS + PORT( + LED(0)_PAD : OUT std_ulogic; + \UART:tx(0)_PAD\ : INOUT std_ulogic); + ATTRIBUTE voltage_VDDA OF __DEFAULT__ : ENTITY IS 5e0; + ATTRIBUTE voltage_VDDD OF __DEFAULT__ : ENTITY IS 5e0; +END \ADC-UART\; + +ARCHITECTURE __DEFAULT__ OF \ADC-UART\ IS + SIGNAL ClockBlock_EXTCLK : bit; + SIGNAL ClockBlock_HFCLK : bit; + ATTRIBUTE global_signal OF ClockBlock_HFCLK : SIGNAL IS true; + SIGNAL ClockBlock_ILO : bit; + SIGNAL ClockBlock_IMO : bit; + SIGNAL ClockBlock_LFCLK : bit; + SIGNAL ClockBlock_Routed1 : bit; + SIGNAL ClockBlock_SYSCLK : bit; + SIGNAL Input_1(0)__PA : bit; + SIGNAL LED(0)__PA : bit; + SIGNAL Net_648 : bit; + SIGNAL Net_666 : bit; + SIGNAL Net_667 : bit; + SIGNAL Net_670 : bit; + SIGNAL Net_671 : bit; + SIGNAL \ADC:Net_1845_ff7\ : bit; + ATTRIBUTE global_signal OF \ADC:Net_1845_ff7\ : SIGNAL IS true; + SIGNAL \ADC:Net_3108\ : bit; + SIGNAL \ADC:Net_3109_0\ : bit; + SIGNAL \ADC:Net_3109_1\ : bit; + SIGNAL \ADC:Net_3109_2\ : bit; + SIGNAL \ADC:Net_3109_3\ : bit; + SIGNAL \ADC:Net_3110\ : bit; + SIGNAL \ADC:Net_3111_0\ : bit; + SIGNAL \ADC:Net_3111_10\ : bit; + SIGNAL \ADC:Net_3111_11\ : bit; + SIGNAL \ADC:Net_3111_1\ : bit; + SIGNAL \ADC:Net_3111_2\ : bit; + SIGNAL \ADC:Net_3111_3\ : bit; + SIGNAL \ADC:Net_3111_4\ : bit; + SIGNAL \ADC:Net_3111_5\ : bit; + SIGNAL \ADC:Net_3111_6\ : bit; + SIGNAL \ADC:Net_3111_7\ : bit; + SIGNAL \ADC:Net_3111_8\ : bit; + SIGNAL \ADC:Net_3111_9\ : bit; + SIGNAL \ADC:Net_3112\ : bit; + SIGNAL \UART:Net_847_ff2\ : bit; + ATTRIBUTE global_signal OF \UART:Net_847_ff2\ : SIGNAL IS true; + SIGNAL \UART:miso_s_wire\ : bit; + SIGNAL \UART:mosi_m_wire\ : bit; + SIGNAL \UART:rts_wire\ : bit; + SIGNAL \UART:sclk_m_wire\ : bit; + SIGNAL \UART:select_m_wire_0\ : bit; + SIGNAL \UART:select_m_wire_1\ : bit; + SIGNAL \UART:select_m_wire_2\ : bit; + SIGNAL \UART:select_m_wire_3\ : bit; + SIGNAL \\\UART:tx(0)\\__PA\ : bit; + SIGNAL \UART:tx_wire\ : bit; + SIGNAL __ONE__ : bit; + ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; + SIGNAL __ZERO__ : bit; + ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; + SIGNAL tmpOE__LED_net_0 : bit; + ATTRIBUTE POWER OF tmpOE__LED_net_0 : SIGNAL IS true; + SIGNAL zero : bit; + ATTRIBUTE GROUND OF zero : SIGNAL IS true; + ATTRIBUTE Location OF ClockGenBlock : LABEL IS "F(CLK_GEN,0)"; + ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; + ATTRIBUTE lib_model OF LED(0) : LABEL IS "iocell1"; + ATTRIBUTE Location OF LED(0) : LABEL IS "P1[6]"; + ATTRIBUTE lib_model OF \UART:tx(0)\ : LABEL IS "iocell2"; + ATTRIBUTE Location OF \UART:tx(0)\ : LABEL IS "P4[1]"; + ATTRIBUTE lib_model OF Input_1(0) : LABEL IS "iocell3"; + ATTRIBUTE Location OF Input_1(0) : LABEL IS "P2[3]"; + ATTRIBUTE Location OF \UART:SCB\ : LABEL IS "F(SCB,0)"; + ATTRIBUTE Location OF \ADC:IRQ\ : LABEL IS "[IntrContainer=(0)][IntrId=(14)]"; + ATTRIBUTE Location OF \ADC:cy_psoc4_sar\ : LABEL IS "F(SARADC,0)"; + COMPONENT interrupt + PORT ( + interrupt : IN std_ulogic; + clock : IN std_ulogic); + END COMPONENT; + COMPONENT iocell + PORT ( + oe : IN std_ulogic; + fb : OUT std_ulogic; + pa_out : OUT std_ulogic; + pin_input : IN std_ulogic; + pad_in : IN std_ulogic; + pad_out : OUT std_ulogic; + oe_reg : OUT std_ulogic; + oe_internal : IN std_ulogic; + in_clock : IN std_ulogic; + in_clock_en : IN std_ulogic; + in_reset : IN std_ulogic; + out_clock : IN std_ulogic; + out_clock_en : IN std_ulogic; + out_reset : IN std_ulogic); + END COMPONENT; + COMPONENT logicalport + PORT ( + interrupt : OUT std_ulogic; + precharge : IN std_ulogic; + in_clock : IN std_ulogic; + in_clock_en : IN std_ulogic; + in_reset : IN std_ulogic; + out_clock : IN std_ulogic; + out_clock_en : IN std_ulogic; + out_reset : IN std_ulogic); + END COMPONENT; + COMPONENT m0s8clockblockcell + PORT ( + imo : OUT std_ulogic; + ext : OUT std_ulogic; + eco : OUT std_ulogic; + ilo : OUT std_ulogic; + wco : OUT std_ulogic; + dbl : OUT std_ulogic; + pll : OUT std_ulogic; + dpll : OUT std_ulogic; + dsi_out_0 : IN std_ulogic; + dsi_out_1 : IN std_ulogic; + dsi_out_2 : IN std_ulogic; + dsi_out_3 : IN std_ulogic; + lfclk : OUT std_ulogic; + hfclk : OUT std_ulogic; + sysclk : OUT std_ulogic; + halfsysclk : OUT std_ulogic; + udb_div_0 : OUT std_ulogic; + udb_div_1 : OUT std_ulogic; + udb_div_2 : OUT std_ulogic; + udb_div_3 : OUT std_ulogic; + udb_div_4 : OUT std_ulogic; + udb_div_5 : OUT std_ulogic; + udb_div_6 : OUT std_ulogic; + udb_div_7 : OUT std_ulogic; + udb_div_8 : OUT std_ulogic; + udb_div_9 : OUT std_ulogic; + udb_div_10 : OUT std_ulogic; + udb_div_11 : OUT std_ulogic; + udb_div_12 : OUT std_ulogic; + udb_div_13 : OUT std_ulogic; + udb_div_14 : OUT std_ulogic; + udb_div_15 : OUT std_ulogic; + uab_div_0 : OUT std_ulogic; + uab_div_1 : OUT std_ulogic; + uab_div_2 : OUT std_ulogic; + uab_div_3 : OUT std_ulogic; + ff_div_0 : OUT std_ulogic; + ff_div_1 : OUT std_ulogic; + ff_div_2 : OUT std_ulogic; + ff_div_3 : OUT std_ulogic; + ff_div_4 : OUT std_ulogic; + ff_div_5 : OUT std_ulogic; + ff_div_6 : OUT std_ulogic; + ff_div_7 : OUT std_ulogic; + ff_div_8 : OUT std_ulogic; + ff_div_9 : OUT std_ulogic; + ff_div_10 : OUT std_ulogic; + ff_div_11 : OUT std_ulogic; + ff_div_12 : OUT std_ulogic; + ff_div_13 : OUT std_ulogic; + ff_div_14 : OUT std_ulogic; + ff_div_15 : OUT std_ulogic; + ff_div_16 : OUT std_ulogic; + ff_div_17 : OUT std_ulogic; + ff_div_18 : OUT std_ulogic; + ff_div_19 : OUT std_ulogic; + ff_div_20 : OUT std_ulogic; + ff_div_21 : OUT std_ulogic; + ff_div_22 : OUT std_ulogic; + ff_div_23 : OUT std_ulogic; + ff_div_24 : OUT std_ulogic; + ff_div_25 : OUT std_ulogic; + ff_div_26 : OUT std_ulogic; + ff_div_27 : OUT std_ulogic; + ff_div_28 : OUT std_ulogic; + ff_div_29 : OUT std_ulogic; + ff_div_30 : OUT std_ulogic; + ff_div_31 : OUT std_ulogic; + ff_div_32 : OUT std_ulogic; + ff_div_33 : OUT std_ulogic; + ff_div_34 : OUT std_ulogic; + ff_div_35 : OUT std_ulogic; + ff_div_36 : OUT std_ulogic; + ff_div_37 : OUT std_ulogic; + ff_div_38 : OUT std_ulogic; + ff_div_39 : OUT std_ulogic; + ff_div_40 : OUT std_ulogic; + ff_div_41 : OUT std_ulogic; + ff_div_42 : OUT std_ulogic; + ff_div_43 : OUT std_ulogic; + ff_div_44 : OUT std_ulogic; + ff_div_45 : OUT std_ulogic; + ff_div_46 : OUT std_ulogic; + ff_div_47 : OUT std_ulogic; + ff_div_48 : OUT std_ulogic; + ff_div_49 : OUT std_ulogic; + ff_div_50 : OUT std_ulogic; + ff_div_51 : OUT std_ulogic; + ff_div_52 : OUT std_ulogic; + ff_div_53 : OUT std_ulogic; + ff_div_54 : OUT std_ulogic; + ff_div_55 : OUT std_ulogic; + ff_div_56 : OUT std_ulogic; + ff_div_57 : OUT std_ulogic; + ff_div_58 : OUT std_ulogic; + ff_div_59 : OUT std_ulogic; + ff_div_60 : OUT std_ulogic; + ff_div_61 : OUT std_ulogic; + ff_div_62 : OUT std_ulogic; + ff_div_63 : OUT std_ulogic; + dsi_in_0 : OUT std_ulogic; + dsi_in_1 : OUT std_ulogic; + dsi_in_2 : OUT std_ulogic; + dsi_in_3 : OUT std_ulogic); + END COMPONENT; + COMPONENT m0s8clockgenblockcell + PORT ( + gen_clk_in_0 : IN std_ulogic; + gen_clk_in_1 : IN std_ulogic; + gen_clk_in_2 : IN std_ulogic; + gen_clk_in_3 : IN std_ulogic; + gen_clk_in_4 : IN std_ulogic; + gen_clk_in_5 : IN std_ulogic; + gen_clk_in_6 : IN std_ulogic; + gen_clk_in_7 : IN std_ulogic; + gen_clk_out_0 : OUT std_ulogic; + gen_clk_out_1 : OUT std_ulogic; + gen_clk_out_2 : OUT std_ulogic; + gen_clk_out_3 : OUT std_ulogic; + gen_clk_out_4 : OUT std_ulogic; + gen_clk_out_5 : OUT std_ulogic; + gen_clk_out_6 : OUT std_ulogic; + gen_clk_out_7 : OUT std_ulogic); + END COMPONENT; + COMPONENT m0s8scbcell + PORT ( + clock : IN std_ulogic; + interrupt : OUT std_ulogic; + uart_cts : IN std_ulogic; + uart_rts : OUT std_ulogic; + uart_rx : IN std_ulogic; + uart_tx : OUT std_ulogic; + mosi_m : OUT std_ulogic; + miso_m : IN std_ulogic; + select_m_0 : OUT std_ulogic; + select_m_1 : OUT std_ulogic; + select_m_2 : OUT std_ulogic; + select_m_3 : OUT std_ulogic; + sclk_m : OUT std_ulogic; + mosi_s : IN std_ulogic; + miso_s : OUT std_ulogic; + select_s : IN std_ulogic; + sclk_s : IN std_ulogic; + i2c_scl : IN std_ulogic; + i2c_sda : IN std_ulogic; + tr_rx_req : OUT std_ulogic; + tr_tx_req : OUT std_ulogic); + END COMPONENT; + COMPONENT p4sarcell + PORT ( + clock : IN std_ulogic; + sample_done : OUT std_ulogic; + chan_id_valid : OUT std_ulogic; + chan_id_0 : OUT std_ulogic; + chan_id_1 : OUT std_ulogic; + chan_id_2 : OUT std_ulogic; + chan_id_3 : OUT std_ulogic; + data_valid : OUT std_ulogic; + data_0 : OUT std_ulogic; + data_1 : OUT std_ulogic; + data_2 : OUT std_ulogic; + data_3 : OUT std_ulogic; + data_4 : OUT std_ulogic; + data_5 : OUT std_ulogic; + data_6 : OUT std_ulogic; + data_7 : OUT std_ulogic; + data_8 : OUT std_ulogic; + data_9 : OUT std_ulogic; + data_10 : OUT std_ulogic; + data_11 : OUT std_ulogic; + eos_intr : OUT std_ulogic; + tr_sar_out : OUT std_ulogic; + irq : OUT std_ulogic; + sw_negvref : IN std_ulogic; + cfg_st_sel_0 : IN std_ulogic; + cfg_st_sel_1 : IN std_ulogic; + cfg_average : IN std_ulogic; + cfg_resolution : IN std_ulogic; + cfg_differential : IN std_ulogic; + tr_sar_in : IN std_ulogic; + data_hilo_sel : IN std_ulogic; + swctrl_0 : IN std_ulogic; + swctrl_1 : IN std_ulogic; + data_out_0 : IN std_ulogic; + data_out_1 : IN std_ulogic; + data_out_2 : IN std_ulogic; + data_out_3 : IN std_ulogic; + data_out_4 : IN std_ulogic; + data_out_5 : IN std_ulogic; + data_out_6 : IN std_ulogic; + data_out_7 : IN std_ulogic; + data_oe_0 : IN std_ulogic; + data_oe_1 : IN std_ulogic; + data_oe_2 : IN std_ulogic; + data_oe_3 : IN std_ulogic); + END COMPONENT; +BEGIN + + ClockGenBlock:m0s8clockgenblockcell; + + ClockBlock:m0s8clockblockcell + PORT MAP( + hfclk => ClockBlock_HFCLK, + imo => ClockBlock_IMO, + ext => ClockBlock_EXTCLK, + sysclk => ClockBlock_SYSCLK, + ilo => ClockBlock_ILO, + lfclk => ClockBlock_LFCLK, + dsi_in_0 => ClockBlock_Routed1, + ff_div_7 => \ADC:Net_1845_ff7\, + ff_div_2 => \UART:Net_847_ff2\); + + LED:logicalport + GENERIC MAP( + drive_mode => "100", + ibuf_enabled => "1", + id => "52f31aa9-2f0a-497d-9a1f-1424095e13e6", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "0", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "O", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "1", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + LED(0):iocell + GENERIC MAP( + port_location => "PORT(1,6)", + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "LED", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => LED(0)__PA, + oe => open, + pad_in => LED(0)_PAD, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + \UART:tx\:logicalport + GENERIC MAP( + drive_mode => "110", + ibuf_enabled => "0", + id => "1ec6effd-8f31-4dd5-a825-0c49238d524e/23b8206d-1c77-4e61-be4a-b4037d5de5fc", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "0", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "1", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "B", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "0", + vtrip => "00", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + \UART:tx(0)\:iocell + GENERIC MAP( + port_location => "PORT(0,5)", + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "\UART:tx\", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => \\\UART:tx(0)\\__PA\, + oe => open, + pin_input => \UART:tx_wire\, + pad_out => \UART:tx(0)_PAD\, + pad_in => \UART:tx(0)_PAD\, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + Input_1:logicalport + GENERIC MAP( + drive_mode => "000", + ibuf_enabled => "0", + id => "0b0fcf5d-629b-4f61-a95a-c0d71e4b1f3e", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "0", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "A", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "1", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + Input_1(0):iocell + GENERIC MAP( + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "Input_1", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000010") + PORT MAP( + pa_out => Input_1(0)__PA, + oe => open, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + \UART:SCB\:m0s8scbcell + GENERIC MAP( + cy_registers => "", + scb_mode => 2) + PORT MAP( + clock => \UART:Net_847_ff2\, + interrupt => Net_648, + uart_rx => open, + uart_tx => \UART:tx_wire\, + uart_cts => open, + uart_rts => \UART:rts_wire\, + mosi_m => \UART:mosi_m_wire\, + miso_m => open, + select_m_3 => \UART:select_m_wire_3\, + select_m_2 => \UART:select_m_wire_2\, + select_m_1 => \UART:select_m_wire_1\, + select_m_0 => \UART:select_m_wire_0\, + sclk_m => \UART:sclk_m_wire\, + mosi_s => open, + miso_s => \UART:miso_s_wire\, + select_s => open, + sclk_s => open, + tr_tx_req => Net_671, + tr_rx_req => Net_670); + + \ADC:IRQ\:interrupt + GENERIC MAP( + int_type => "10", + is_nmi => 0) + PORT MAP( + interrupt => \ADC:Net_3112\, + clock => ClockBlock_HFCLK); + + \ADC:cy_psoc4_sar\:p4sarcell + GENERIC MAP( + cy_registers => "") + PORT MAP( + clock => \ADC:Net_1845_ff7\, + sample_done => Net_666, + chan_id_valid => \ADC:Net_3108\, + chan_id_3 => \ADC:Net_3109_3\, + chan_id_2 => \ADC:Net_3109_2\, + chan_id_1 => \ADC:Net_3109_1\, + chan_id_0 => \ADC:Net_3109_0\, + data_valid => \ADC:Net_3110\, + data_11 => \ADC:Net_3111_11\, + data_10 => \ADC:Net_3111_10\, + data_9 => \ADC:Net_3111_9\, + data_8 => \ADC:Net_3111_8\, + data_7 => \ADC:Net_3111_7\, + data_6 => \ADC:Net_3111_6\, + data_5 => \ADC:Net_3111_5\, + data_4 => \ADC:Net_3111_4\, + data_3 => \ADC:Net_3111_3\, + data_2 => \ADC:Net_3111_2\, + data_1 => \ADC:Net_3111_1\, + data_0 => \ADC:Net_3111_0\, + eos_intr => Net_667, + irq => \ADC:Net_3112\, + sw_negvref => open, + cfg_st_sel_1 => open, + cfg_st_sel_0 => open, + cfg_average => open, + cfg_resolution => open, + cfg_differential => open, + tr_sar_in => open, + data_hilo_sel => open); + +END __DEFAULT__; diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_t.lib b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_t.lib new file mode 100644 index 0000000..4f12547 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_t.lib @@ -0,0 +1,533 @@ +library (timing) { + timescale : 1ns; + capacitive_load_unit (1,ff); + include_file(device.lib); + cell (iocell1) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.205; + intrinsic_fall : 12.205; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.819; + intrinsic_fall : 13.819; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 6.106; + intrinsic_fall : 6.106; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 7.555; + intrinsic_fall : 7.555; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 12.020; + intrinsic_fall : 12.020; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 14.424; + intrinsic_fall : 14.424; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 12.922; + intrinsic_fall : 12.922; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.420; + intrinsic_fall : 15.420; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.446; + intrinsic_fall : 12.446; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.717; + intrinsic_fall : 14.717; + } + } + } + cell (iocell2) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 11.665; + intrinsic_fall : 11.665; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.279; + intrinsic_fall : 13.279; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 6.746; + intrinsic_fall : 6.746; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 8.195; + intrinsic_fall : 8.195; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 12.660; + intrinsic_fall : 12.660; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 15.064; + intrinsic_fall : 15.064; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.462; + intrinsic_fall : 15.462; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 17.960; + intrinsic_fall : 17.960; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 11.906; + intrinsic_fall : 11.906; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.177; + intrinsic_fall : 14.177; + } + } + } + cell (iocell3) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (in_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.483; + intrinsic_fall : 0.483; + } + timing () { + timing_type : removal_rising; + related_pin : "in_clock"; + intrinsic_rise : 0.202; + intrinsic_fall : 0.202; + } + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.500; + intrinsic_fall : 0.500; + } + timing () { + timing_type : setup_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.750; + intrinsic_fall : 0.750; + } + timing () { + timing_type : hold_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (out_reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.374; + intrinsic_fall : 0.374; + } + timing () { + timing_type : removal_rising; + related_pin : "out_clock"; + intrinsic_rise : 0.296; + intrinsic_fall : 0.296; + } + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 12.845; + intrinsic_fall : 12.845; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 14.459; + intrinsic_fall : 14.459; + } + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (oe_internal) { + direction : input; + } + pin (oe_reg) { + direction : output; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 8.356; + intrinsic_fall : 8.356; + } + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 9.805; + intrinsic_fall : 9.805; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 14.270; + intrinsic_fall : 14.270; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.674; + intrinsic_fall : 16.674; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 16.092; + intrinsic_fall : 16.092; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 18.590; + intrinsic_fall : 18.590; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 13.086; + intrinsic_fall : 13.086; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 15.357; + intrinsic_fall : 15.357; + } + } + } +} diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_t.vh2 b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_t.vh2 new file mode 100644 index 0000000..10fad06 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_t.vh2 @@ -0,0 +1,669 @@ +-- Project: D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj +-- Generated: 07/17/2020 10:59:54 +-- PSoC Creator 4.2 + +ENTITY \ADC-UART\ IS + PORT( + LED(0)_PAD : OUT std_ulogic; + \UART:tx(0)_PAD\ : INOUT std_ulogic); + ATTRIBUTE voltage_VDDA OF __DEFAULT__ : ENTITY IS 5e0; + ATTRIBUTE voltage_VDDD OF __DEFAULT__ : ENTITY IS 5e0; +END \ADC-UART\; + +ARCHITECTURE __DEFAULT__ OF \ADC-UART\ IS + SIGNAL ClockBlock_EXTCLK : bit; + SIGNAL ClockBlock_HFCLK : bit; + ATTRIBUTE global_signal OF ClockBlock_HFCLK : SIGNAL IS true; + SIGNAL ClockBlock_ILO : bit; + SIGNAL ClockBlock_IMO : bit; + SIGNAL ClockBlock_LFCLK : bit; + SIGNAL ClockBlock_Routed1 : bit; + SIGNAL ClockBlock_SYSCLK : bit; + SIGNAL Input_1(0)__PA : bit; + SIGNAL LED(0)__PA : bit; + SIGNAL Net_648 : bit; + SIGNAL Net_666 : bit; + SIGNAL Net_667 : bit; + SIGNAL Net_670 : bit; + SIGNAL Net_671 : bit; + SIGNAL \ADC:Net_1845_ff7\ : bit; + ATTRIBUTE global_signal OF \ADC:Net_1845_ff7\ : SIGNAL IS true; + SIGNAL \ADC:Net_3108\ : bit; + SIGNAL \ADC:Net_3109_0\ : bit; + SIGNAL \ADC:Net_3109_1\ : bit; + SIGNAL \ADC:Net_3109_2\ : bit; + SIGNAL \ADC:Net_3109_3\ : bit; + SIGNAL \ADC:Net_3110\ : bit; + SIGNAL \ADC:Net_3111_0\ : bit; + SIGNAL \ADC:Net_3111_10\ : bit; + SIGNAL \ADC:Net_3111_11\ : bit; + SIGNAL \ADC:Net_3111_1\ : bit; + SIGNAL \ADC:Net_3111_2\ : bit; + SIGNAL \ADC:Net_3111_3\ : bit; + SIGNAL \ADC:Net_3111_4\ : bit; + SIGNAL \ADC:Net_3111_5\ : bit; + SIGNAL \ADC:Net_3111_6\ : bit; + SIGNAL \ADC:Net_3111_7\ : bit; + SIGNAL \ADC:Net_3111_8\ : bit; + SIGNAL \ADC:Net_3111_9\ : bit; + SIGNAL \ADC:Net_3112\ : bit; + SIGNAL \UART:Net_847_ff2\ : bit; + ATTRIBUTE global_signal OF \UART:Net_847_ff2\ : SIGNAL IS true; + SIGNAL \UART:miso_s_wire\ : bit; + SIGNAL \UART:mosi_m_wire\ : bit; + SIGNAL \UART:rts_wire\ : bit; + SIGNAL \UART:sclk_m_wire\ : bit; + SIGNAL \UART:select_m_wire_0\ : bit; + SIGNAL \UART:select_m_wire_1\ : bit; + SIGNAL \UART:select_m_wire_2\ : bit; + SIGNAL \UART:select_m_wire_3\ : bit; + SIGNAL \\\UART:tx(0)\\__PA\ : bit; + SIGNAL \UART:tx_wire\ : bit; + SIGNAL __ONE__ : bit; + ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; + SIGNAL __ZERO__ : bit; + ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; + SIGNAL tmpOE__LED_net_0 : bit; + ATTRIBUTE POWER OF tmpOE__LED_net_0 : SIGNAL IS true; + SIGNAL zero : bit; + ATTRIBUTE GROUND OF zero : SIGNAL IS true; + ATTRIBUTE Location OF ClockGenBlock : LABEL IS "F(CLK_GEN,0)"; + ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; + ATTRIBUTE lib_model OF LED(0) : LABEL IS "iocell1"; + ATTRIBUTE Location OF LED(0) : LABEL IS "P1[6]"; + ATTRIBUTE lib_model OF \UART:tx(0)\ : LABEL IS "iocell2"; + ATTRIBUTE Location OF \UART:tx(0)\ : LABEL IS "P4[1]"; + ATTRIBUTE lib_model OF Input_1(0) : LABEL IS "iocell3"; + ATTRIBUTE Location OF Input_1(0) : LABEL IS "P2[3]"; + ATTRIBUTE Location OF \UART:SCB\ : LABEL IS "F(SCB,0)"; + ATTRIBUTE Location OF \ADC:IRQ\ : LABEL IS "[IntrContainer=(0)][IntrId=(14)]"; + ATTRIBUTE Location OF \ADC:cy_psoc4_sar\ : LABEL IS "F(SARADC,0)"; + COMPONENT interrupt + PORT ( + interrupt : IN std_ulogic; + clock : IN std_ulogic); + END COMPONENT; + COMPONENT iocell + PORT ( + oe : IN std_ulogic; + fb : OUT std_ulogic; + pa_out : OUT std_ulogic; + pin_input : IN std_ulogic; + pad_in : IN std_ulogic; + pad_out : OUT std_ulogic; + oe_reg : OUT std_ulogic; + oe_internal : IN std_ulogic; + in_clock : IN std_ulogic; + in_clock_en : IN std_ulogic; + in_reset : IN std_ulogic; + out_clock : IN std_ulogic; + out_clock_en : IN std_ulogic; + out_reset : IN std_ulogic); + END COMPONENT; + COMPONENT logicalport + PORT ( + interrupt : OUT std_ulogic; + precharge : IN std_ulogic; + in_clock : IN std_ulogic; + in_clock_en : IN std_ulogic; + in_reset : IN std_ulogic; + out_clock : IN std_ulogic; + out_clock_en : IN std_ulogic; + out_reset : IN std_ulogic); + END COMPONENT; + COMPONENT m0s8clockblockcell + PORT ( + imo : OUT std_ulogic; + ext : OUT std_ulogic; + eco : OUT std_ulogic; + ilo : OUT std_ulogic; + wco : OUT std_ulogic; + dbl : OUT std_ulogic; + pll : OUT std_ulogic; + dpll : OUT std_ulogic; + dsi_out_0 : IN std_ulogic; + dsi_out_1 : IN std_ulogic; + dsi_out_2 : IN std_ulogic; + dsi_out_3 : IN std_ulogic; + lfclk : OUT std_ulogic; + hfclk : OUT std_ulogic; + sysclk : OUT std_ulogic; + halfsysclk : OUT std_ulogic; + udb_div_0 : OUT std_ulogic; + udb_div_1 : OUT std_ulogic; + udb_div_2 : OUT std_ulogic; + udb_div_3 : OUT std_ulogic; + udb_div_4 : OUT std_ulogic; + udb_div_5 : OUT std_ulogic; + udb_div_6 : OUT std_ulogic; + udb_div_7 : OUT std_ulogic; + udb_div_8 : OUT std_ulogic; + udb_div_9 : OUT std_ulogic; + udb_div_10 : OUT std_ulogic; + udb_div_11 : OUT std_ulogic; + udb_div_12 : OUT std_ulogic; + udb_div_13 : OUT std_ulogic; + udb_div_14 : OUT std_ulogic; + udb_div_15 : OUT std_ulogic; + uab_div_0 : OUT std_ulogic; + uab_div_1 : OUT std_ulogic; + uab_div_2 : OUT std_ulogic; + uab_div_3 : OUT std_ulogic; + ff_div_0 : OUT std_ulogic; + ff_div_1 : OUT std_ulogic; + ff_div_2 : OUT std_ulogic; + ff_div_3 : OUT std_ulogic; + ff_div_4 : OUT std_ulogic; + ff_div_5 : OUT std_ulogic; + ff_div_6 : OUT std_ulogic; + ff_div_7 : OUT std_ulogic; + ff_div_8 : OUT std_ulogic; + ff_div_9 : OUT std_ulogic; + ff_div_10 : OUT std_ulogic; + ff_div_11 : OUT std_ulogic; + ff_div_12 : OUT std_ulogic; + ff_div_13 : OUT std_ulogic; + ff_div_14 : OUT std_ulogic; + ff_div_15 : OUT std_ulogic; + ff_div_16 : OUT std_ulogic; + ff_div_17 : OUT std_ulogic; + ff_div_18 : OUT std_ulogic; + ff_div_19 : OUT std_ulogic; + ff_div_20 : OUT std_ulogic; + ff_div_21 : OUT std_ulogic; + ff_div_22 : OUT std_ulogic; + ff_div_23 : OUT std_ulogic; + ff_div_24 : OUT std_ulogic; + ff_div_25 : OUT std_ulogic; + ff_div_26 : OUT std_ulogic; + ff_div_27 : OUT std_ulogic; + ff_div_28 : OUT std_ulogic; + ff_div_29 : OUT std_ulogic; + ff_div_30 : OUT std_ulogic; + ff_div_31 : OUT std_ulogic; + ff_div_32 : OUT std_ulogic; + ff_div_33 : OUT std_ulogic; + ff_div_34 : OUT std_ulogic; + ff_div_35 : OUT std_ulogic; + ff_div_36 : OUT std_ulogic; + ff_div_37 : OUT std_ulogic; + ff_div_38 : OUT std_ulogic; + ff_div_39 : OUT std_ulogic; + ff_div_40 : OUT std_ulogic; + ff_div_41 : OUT std_ulogic; + ff_div_42 : OUT std_ulogic; + ff_div_43 : OUT std_ulogic; + ff_div_44 : OUT std_ulogic; + ff_div_45 : OUT std_ulogic; + ff_div_46 : OUT std_ulogic; + ff_div_47 : OUT std_ulogic; + ff_div_48 : OUT std_ulogic; + ff_div_49 : OUT std_ulogic; + ff_div_50 : OUT std_ulogic; + ff_div_51 : OUT std_ulogic; + ff_div_52 : OUT std_ulogic; + ff_div_53 : OUT std_ulogic; + ff_div_54 : OUT std_ulogic; + ff_div_55 : OUT std_ulogic; + ff_div_56 : OUT std_ulogic; + ff_div_57 : OUT std_ulogic; + ff_div_58 : OUT std_ulogic; + ff_div_59 : OUT std_ulogic; + ff_div_60 : OUT std_ulogic; + ff_div_61 : OUT std_ulogic; + ff_div_62 : OUT std_ulogic; + ff_div_63 : OUT std_ulogic; + dsi_in_0 : OUT std_ulogic; + dsi_in_1 : OUT std_ulogic; + dsi_in_2 : OUT std_ulogic; + dsi_in_3 : OUT std_ulogic); + END COMPONENT; + COMPONENT m0s8clockgenblockcell + PORT ( + gen_clk_in_0 : IN std_ulogic; + gen_clk_in_1 : IN std_ulogic; + gen_clk_in_2 : IN std_ulogic; + gen_clk_in_3 : IN std_ulogic; + gen_clk_in_4 : IN std_ulogic; + gen_clk_in_5 : IN std_ulogic; + gen_clk_in_6 : IN std_ulogic; + gen_clk_in_7 : IN std_ulogic; + gen_clk_out_0 : OUT std_ulogic; + gen_clk_out_1 : OUT std_ulogic; + gen_clk_out_2 : OUT std_ulogic; + gen_clk_out_3 : OUT std_ulogic; + gen_clk_out_4 : OUT std_ulogic; + gen_clk_out_5 : OUT std_ulogic; + gen_clk_out_6 : OUT std_ulogic; + gen_clk_out_7 : OUT std_ulogic); + END COMPONENT; + COMPONENT m0s8scbcell + PORT ( + clock : IN std_ulogic; + interrupt : OUT std_ulogic; + uart_cts : IN std_ulogic; + uart_rts : OUT std_ulogic; + uart_rx : IN std_ulogic; + uart_tx : OUT std_ulogic; + mosi_m : OUT std_ulogic; + miso_m : IN std_ulogic; + select_m_0 : OUT std_ulogic; + select_m_1 : OUT std_ulogic; + select_m_2 : OUT std_ulogic; + select_m_3 : OUT std_ulogic; + sclk_m : OUT std_ulogic; + mosi_s : IN std_ulogic; + miso_s : OUT std_ulogic; + select_s : IN std_ulogic; + sclk_s : IN std_ulogic; + i2c_scl : IN std_ulogic; + i2c_sda : IN std_ulogic; + tr_rx_req : OUT std_ulogic; + tr_tx_req : OUT std_ulogic); + END COMPONENT; + COMPONENT p4sarcell + PORT ( + clock : IN std_ulogic; + sample_done : OUT std_ulogic; + chan_id_valid : OUT std_ulogic; + chan_id_0 : OUT std_ulogic; + chan_id_1 : OUT std_ulogic; + chan_id_2 : OUT std_ulogic; + chan_id_3 : OUT std_ulogic; + data_valid : OUT std_ulogic; + data_0 : OUT std_ulogic; + data_1 : OUT std_ulogic; + data_2 : OUT std_ulogic; + data_3 : OUT std_ulogic; + data_4 : OUT std_ulogic; + data_5 : OUT std_ulogic; + data_6 : OUT std_ulogic; + data_7 : OUT std_ulogic; + data_8 : OUT std_ulogic; + data_9 : OUT std_ulogic; + data_10 : OUT std_ulogic; + data_11 : OUT std_ulogic; + eos_intr : OUT std_ulogic; + tr_sar_out : OUT std_ulogic; + irq : OUT std_ulogic; + sw_negvref : IN std_ulogic; + cfg_st_sel_0 : IN std_ulogic; + cfg_st_sel_1 : IN std_ulogic; + cfg_average : IN std_ulogic; + cfg_resolution : IN std_ulogic; + cfg_differential : IN std_ulogic; + tr_sar_in : IN std_ulogic; + data_hilo_sel : IN std_ulogic; + swctrl_0 : IN std_ulogic; + swctrl_1 : IN std_ulogic; + data_out_0 : IN std_ulogic; + data_out_1 : IN std_ulogic; + data_out_2 : IN std_ulogic; + data_out_3 : IN std_ulogic; + data_out_4 : IN std_ulogic; + data_out_5 : IN std_ulogic; + data_out_6 : IN std_ulogic; + data_out_7 : IN std_ulogic; + data_oe_0 : IN std_ulogic; + data_oe_1 : IN std_ulogic; + data_oe_2 : IN std_ulogic; + data_oe_3 : IN std_ulogic); + END COMPONENT; +BEGIN + + ClockGenBlock:m0s8clockgenblockcell; + + ClockBlock:m0s8clockblockcell + PORT MAP( + hfclk => ClockBlock_HFCLK, + imo => ClockBlock_IMO, + ext => ClockBlock_EXTCLK, + sysclk => ClockBlock_SYSCLK, + ilo => ClockBlock_ILO, + lfclk => ClockBlock_LFCLK, + dsi_in_0 => ClockBlock_Routed1, + ff_div_7 => \ADC:Net_1845_ff7\, + ff_div_2 => \UART:Net_847_ff2\); + + LED:logicalport + GENERIC MAP( + drive_mode => "100", + ibuf_enabled => "1", + id => "52f31aa9-2f0a-497d-9a1f-1424095e13e6", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "0", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "O", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "1", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + LED(0):iocell + GENERIC MAP( + port_location => "PORT(1,6)", + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "LED", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => LED(0)__PA, + oe => open, + pad_in => LED(0)_PAD, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + \UART:tx\:logicalport + GENERIC MAP( + drive_mode => "110", + ibuf_enabled => "0", + id => "1ec6effd-8f31-4dd5-a825-0c49238d524e/23b8206d-1c77-4e61-be4a-b4037d5de5fc", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "0", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "1", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "B", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "0", + vtrip => "00", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + \UART:tx(0)\:iocell + GENERIC MAP( + port_location => "PORT(0,5)", + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "\UART:tx\", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => \\\UART:tx(0)\\__PA\, + oe => open, + pin_input => \UART:tx_wire\, + pad_out => \UART:tx(0)_PAD\, + pad_in => \UART:tx(0)_PAD\, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + Input_1:logicalport + GENERIC MAP( + drive_mode => "000", + ibuf_enabled => "0", + id => "0b0fcf5d-629b-4f61-a95a-c0d71e4b1f3e", + init_dr_st => "1", + input_buffer_sel => "00", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "0", + output_mode => "0", + output_reset => 0, + output_sync => "0", + ovt_hyst_trim => "0", + ovt_needed => "0", + ovt_slew_control => "00", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "A", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "00000000", + sio_hyst => "1", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vohsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "1", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + Input_1(0):iocell + GENERIC MAP( + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "Input_1", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000010") + PORT MAP( + pa_out => Input_1(0)__PA, + oe => open, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + \UART:SCB\:m0s8scbcell + GENERIC MAP( + cy_registers => "", + scb_mode => 2) + PORT MAP( + clock => \UART:Net_847_ff2\, + interrupt => Net_648, + uart_rx => open, + uart_tx => \UART:tx_wire\, + uart_cts => open, + uart_rts => \UART:rts_wire\, + mosi_m => \UART:mosi_m_wire\, + miso_m => open, + select_m_3 => \UART:select_m_wire_3\, + select_m_2 => \UART:select_m_wire_2\, + select_m_1 => \UART:select_m_wire_1\, + select_m_0 => \UART:select_m_wire_0\, + sclk_m => \UART:sclk_m_wire\, + mosi_s => open, + miso_s => \UART:miso_s_wire\, + select_s => open, + sclk_s => open, + tr_tx_req => Net_671, + tr_rx_req => Net_670); + + \ADC:IRQ\:interrupt + GENERIC MAP( + int_type => "10", + is_nmi => 0) + PORT MAP( + interrupt => \ADC:Net_3112\, + clock => ClockBlock_HFCLK); + + \ADC:cy_psoc4_sar\:p4sarcell + GENERIC MAP( + cy_registers => "") + PORT MAP( + clock => \ADC:Net_1845_ff7\, + sample_done => Net_666, + chan_id_valid => \ADC:Net_3108\, + chan_id_3 => \ADC:Net_3109_3\, + chan_id_2 => \ADC:Net_3109_2\, + chan_id_1 => \ADC:Net_3109_1\, + chan_id_0 => \ADC:Net_3109_0\, + data_valid => \ADC:Net_3110\, + data_11 => \ADC:Net_3111_11\, + data_10 => \ADC:Net_3111_10\, + data_9 => \ADC:Net_3111_9\, + data_8 => \ADC:Net_3111_8\, + data_7 => \ADC:Net_3111_7\, + data_6 => \ADC:Net_3111_6\, + data_5 => \ADC:Net_3111_5\, + data_4 => \ADC:Net_3111_4\, + data_3 => \ADC:Net_3111_3\, + data_2 => \ADC:Net_3111_2\, + data_1 => \ADC:Net_3111_1\, + data_0 => \ADC:Net_3111_0\, + eos_intr => Net_667, + irq => \ADC:Net_3112\, + sw_negvref => open, + cfg_st_sel_1 => open, + cfg_st_sel_0 => open, + cfg_average => open, + cfg_resolution => open, + cfg_differential => open, + tr_sar_in => open, + data_hilo_sel => open); + +END __DEFAULT__; diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_timing.html b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_timing.html new file mode 100644 index 0000000..d5ea766 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_timing.html @@ -0,0 +1,672 @@ + + + + +Static Timing Analysis Report + + + + + + +

Static Timing Analysis

+ + + + + + + + + + + + + + + +
Project : ADC-UART
Build Time : 07/17/20 10:59:54
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5.0
+ +
+
No Timing Violations
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
ADC_intClock(FFB)ADC_intClock(FFB)1.000 MHz1.000 MHz N/A
CyHFCLKCyHFCLK24.000 MHz24.000 MHz N/A
ADC_intClockCyHFCLK1.000 MHz1.000 MHz N/A
UART_SCBCLKCyHFCLK76.677 kHz76.677 kHz N/A
CyILOCyILO32.000 kHz32.000 kHz N/A
CyIMOCyIMO24.000 MHz24.000 MHz N/A
CyLFCLKCyLFCLK32.000 kHz32.000 kHz N/A
CyRouted1CyRouted124.000 MHz24.000 MHz N/A
CySYSCLKCySYSCLK24.000 MHz24.000 MHz N/A
UART_SCBCLK(FFB)UART_SCBCLK(FFB)76.677 kHz76.677 kHz N/A
+
+
+ + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_u.sdc b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_u.sdc new file mode 100644 index 0000000..ed06b90 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC-UART_u.sdc @@ -0,0 +1,3 @@ +# Component constraints for D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\TopDesign\TopDesign.cysch +# Project: D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj +# Date: Fri, 17 Jul 2020 08:59:49 GMT diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC.c new file mode 100644 index 0000000..f313f71 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC.c @@ -0,0 +1,881 @@ +/******************************************************************************* +* File Name: ADC.c +* Version 2.50 +* +* Description: +* This file provides the source code to the API for the Sequencing Successive +* Approximation ADC Component Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC.h" + + +/*************************************** +* Global data allocation +***************************************/ +uint8 ADC_initVar = 0u; +volatile int16 ADC_offset[ADC_TOTAL_CHANNELS_NUM]; +volatile int32 ADC_countsPer10Volt[ADC_TOTAL_CHANNELS_NUM]; /* Gain compensation */ + + +/*************************************** +* Local data allocation +***************************************/ +/* Channels configuration generated by customiser */ +static const uint32 CYCODE ADC_channelsConfig[] = { 0x00000402u }; + + +/******************************************************************************* +* Function Name: ADC_Start +******************************************************************************** +* +* Summary: +* Performs all required initialization for this component +* and enables the power. The power will be set to the appropriate +* power based on the clock frequency. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* The ADC_initVar variable is used to indicate when/if initial +* configuration of this component has happened. The variable is initialized to +* zero and set to 1 the first time ADC_Start() is called. This allows for +* component Re-Start without re-initialization in all subsequent calls to the +* ADC_Start() routine. +* If re-initialization of the component is required the variable should be set +* to zero before call of ADC_Start() routine, or the user may call +* ADC_Init() and ADC_Enable() as done in the +* ADC_Start() routine. +* +*******************************************************************************/ +void ADC_Start(void) +{ + /* If not Initialized then initialize all required hardware and software */ + if(ADC_initVar == 0u) + { + ADC_Init(); + ADC_initVar = 1u; + } + ADC_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_Init +******************************************************************************** +* +* Summary: +* Initialize component's parameters to the parameters set by user in the +* customizer of the component placed onto schematic. Usually called in +* ADC_Start(). +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* The ADC_offset variable is initialized. +* +*******************************************************************************/ +void ADC_Init(void) +{ + uint32 chNum; + uint32 tmpRegVal; + int32 counts; + + #if(ADC_TOTAL_CHANNELS_NUM > 1u) + static const uint8 CYCODE ADC_InputsPlacement[] = + { + (uint8)(ADC_cy_psoc4_sarmux_8__CH_0_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_0_PIN + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_1_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_1_PIN + #if(ADC_TOTAL_CHANNELS_NUM > 2u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_2_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_2_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 2u */ + #if(ADC_TOTAL_CHANNELS_NUM > 3u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_3_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_3_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 3u */ + #if(ADC_TOTAL_CHANNELS_NUM > 4u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_4_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_4_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 4u */ + #if(ADC_TOTAL_CHANNELS_NUM > 5u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_5_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_5_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 5u */ + #if(ADC_TOTAL_CHANNELS_NUM > 6u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_6_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_6_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 6u */ + #if(ADC_TOTAL_CHANNELS_NUM > 7u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_7_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_7_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 7u */ + #if(ADC_TOTAL_CHANNELS_NUM > 8u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_8_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_8_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 8u */ + #if(ADC_TOTAL_CHANNELS_NUM > 9u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_9_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_9_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 9u */ + #if(ADC_TOTAL_CHANNELS_NUM > 10u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_10_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_10_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 10u */ + #if(ADC_TOTAL_CHANNELS_NUM > 11u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_11_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_11_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 11u */ + #if(ADC_TOTAL_CHANNELS_NUM > 12u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_12_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_12_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 12u */ + #if(ADC_TOTAL_CHANNELS_NUM > 13u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_13_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_13_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 13u */ + #if(ADC_TOTAL_CHANNELS_NUM > 14u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_14_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_14_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 14u */ + #if(ADC_TOTAL_CHANNELS_NUM > 15u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_15_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_15_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 15u */ + #if(ADC_TOTAL_CHANNELS_NUM > 16u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_16_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_16_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 16u */ + }; + #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */ + + #if(ADC_IRQ_REMOVE == 0u) + /* Start and set interrupt vector */ + CyIntSetPriority(ADC_INTC_NUMBER, ADC_INTC_PRIOR_NUMBER); + (void)CyIntSetVector(ADC_INTC_NUMBER, &ADC_ISR); + #endif /* End ADC_IRQ_REMOVE */ + + /* Init SAR and MUX registers */ + ADC_SAR_CHAN_EN_REG = ADC_DEFAULT_EN_CHANNELS; + ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | + /* Enable the SAR internal pump when global pump is enabled */ + (((ADC_PUMP_CTRL_REG & ADC_PUMP_CTRL_ENABLED) != 0u) ? + ADC_BOOSTPUMP_EN : 0u); + ADC_SAR_SAMPLE_CTRL_REG = ADC_DEFAULT_SAMPLE_CTRL_REG_CFG; + ADC_SAR_RANGE_THRES_REG = ADC_DEFAULT_RANGE_THRES_REG_CFG; + ADC_SAR_RANGE_COND_REG = ADC_COMPARE_MODE; + ADC_SAR_SAMPLE_TIME01_REG = ADC_DEFAULT_SAMPLE_TIME01_REG_CFG; + ADC_SAR_SAMPLE_TIME23_REG = ADC_DEFAULT_SAMPLE_TIME23_REG_CFG; + + /* Connect Vm to VSSA when even one channel is single-ended or multiple channels configured */ + #if(ADC_DEFAULT_MUX_SWITCH0 != 0u) + ADC_MUX_SWITCH0_REG |= ADC_DEFAULT_MUX_SWITCH0; + /* Set MUX_HW_CTRL_VSSA in MUX_SWITCH_HW_CTRL when multiple channels enabled */ + #if(ADC_TOTAL_CHANNELS_NUM > 1u) + ADC_MUX_SWITCH_HW_CTRL_REG |= ADC_DEFAULT_MUX_SWITCH0; + #endif /* ADC_TOTAL_CHANNELS_NUM > 1u */ + #endif /*ADC_CHANNELS_MODE !=0 */ + + ADC_SAR_SATURATE_INTR_MASK_REG = 0u; + ADC_SAR_RANGE_INTR_MASK_REG = 0u; + ADC_SAR_INTR_MASK_REG = ADC_SAR_INTR_MASK; + + #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) + ADC_ANA_TRIM_REG = ADC_TRIM_COEF; + #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */ + + /* Read and modify default configuration based on characterization */ + tmpRegVal = ADC_SAR_DFT_CTRL_REG; + tmpRegVal &= (uint32)~ADC_DCEN; + + #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) + #if(ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 2)) + tmpRegVal |= ADC_SEL_CSEL_DFT_CHAR; + #else /* clock speed < 9 Mhz */ + tmpRegVal |= ADC_DLY_INC; + #endif /* clock speed > 9 Mhz */ + #else + #if ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \ + (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)) + tmpRegVal |= ADC_DLY_INC; + #else + tmpRegVal |= ADC_DCEN; + tmpRegVal &= (uint32)~ADC_DLY_INC; + #endif /* ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \ + (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)) */ + #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */ + + ADC_SAR_DFT_CTRL_REG = tmpRegVal; + + #if(ADC_MAX_RESOLUTION != ADC_RESOLUTION_12) + ADC_WOUNDING_REG = ADC_ALT_WOUNDING; + #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */ + + for(chNum = 0u; chNum < ADC_TOTAL_CHANNELS_NUM; chNum++) + { + tmpRegVal = (ADC_channelsConfig[chNum] & ADC_CHANNEL_CONFIG_MASK); + #if(ADC_TOTAL_CHANNELS_NUM > 1u) + tmpRegVal |= ADC_InputsPlacement[chNum]; + #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */ + + + /* When the part is limited to 10-bit then the SUB_RESOLUTION bit + * will be ignored and the RESOLUTION bit selects between 10-bit + * (0) and 8-bit (1) resolution. + */ + #if((ADC_MAX_RESOLUTION != ADC_RESOLUTION_12) && \ + (ADC_ALT_WOUNDING == ADC_WOUNDING_10BIT)) + tmpRegVal &= (uint32)(~ADC_ALT_RESOLUTION_ON); + #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */ + + #if(ADC_INJ_CHANNEL_ENABLED) + if(chNum < ADC_SEQUENCED_CHANNELS_NUM) + #endif /* ADC_INJ_CHANNEL_ENABLED */ + { + CY_SET_REG32((reg32 *)(ADC_SAR_CHAN_CONFIG_IND + (uint32)(chNum << 2)), tmpRegVal); + + if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u) + { + ADC_SAR_SATURATE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + } + + if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u) + { + ADC_SAR_RANGE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + } + } + #if(ADC_INJ_CHANNEL_ENABLED) + else + { + CY_SET_REG32(ADC_SAR_INJ_CHAN_CONFIG_PTR, tmpRegVal | ADC_INJ_TAILGATING); + + if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u) + { + ADC_SAR_INTR_MASK_REG |= ADC_INJ_SATURATE_MASK; + } + + if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u) + { + ADC_SAR_INTR_MASK_REG |= ADC_INJ_RANGE_MASK; + } + } + #endif /* ADC_INJ_CHANNEL_ENABLED */ + + if((ADC_channelsConfig[chNum] & ADC_ALT_RESOLUTION_ON) != 0u) + { + counts = (int32)ADC_DEFAULT_MAX_WRK_ALT; + } + else + { + counts = (int32)ADC_SAR_WRK_MAX_12BIT; + } + + if((ADC_channelsConfig[chNum] & ADC_DIFFERENTIAL_EN) == 0u) + { + #if((ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED) && \ + (ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF)) + /* Set offset to the minus half scale to convert results to unsigned format */ + ADC_offset[chNum] = (int16)(counts / -2); + #else + ADC_offset[chNum] = 0; + #endif /* end DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED */ + } + else /* Differential channel */ + { + #if(ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED) + /* Set offset to the half scale to convert results to signed format */ + ADC_offset[chNum] = (int16)(counts / 2); + #else + ADC_offset[chNum] = 0; + #endif /* end ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED */ + } + /* Calculate gain in counts per 10 volts with rounding */ + ADC_countsPer10Volt[chNum] = (int16)(((counts * ADC_10MV_COUNTS) + + ADC_DEFAULT_VREF_MV_VALUE) / (ADC_DEFAULT_VREF_MV_VALUE * 2)); + } +} + +/******************************************************************************* +* Function Name: ADC_SAR_1_Enable +******************************************************************************** +* +* Summary: +* Enables the clock and analog power for SAR ADC. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_Enable(void) +{ + if (0u == (ADC_SAR_CTRL_REG & ADC_ENABLE)) + { + #if(ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) + + while (0u != (ADC_SAR_STATUS_REG & ADC_STATUS_BUSY)) + { + /* wait for SAR to go idle to avoid deadlock */ + } + #endif /* (ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) */ + + ADC_SAR_CTRL_REG |= ADC_ENABLE; + + /* The block is ready to use 10 us after the enable signal is set high. */ + CyDelayUs(ADC_10US_DELAY); + } +} + + +/******************************************************************************* +* Function Name: ADC_Stop +******************************************************************************** +* +* Summary: +* This function stops ADC conversions and puts the ADC into its lowest power +* mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_Stop(void) +{ + ADC_SAR_CTRL_REG &= (uint32)~ADC_ENABLE; +} + + +/******************************************************************************* +* Function Name: ADC_StartConvert +******************************************************************************** +* +* Summary: +* Description: +* For free running mode, this API starts the conversion process and it +* runs continuously. +* +* In a triggered mode, this routine triggers every conversion by +* writing into the FW_TRIGGER bit in SAR_START_CTRL reg. In triggered mode, +* every conversion has to start by this API. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_StartConvert(void) +{ + #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + ADC_SAR_SAMPLE_CTRL_REG |= ADC_CONTINUOUS_EN; + #else /* Firmware trigger */ + ADC_SAR_START_CTRL_REG = ADC_FW_TRIGGER; + #endif /* End ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ + +} + + +/******************************************************************************* +* Function Name: ADC_StopConvert +******************************************************************************** +* +* Summary: +* Forces the ADC to stop all conversions. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_StopConvert(void) +{ + #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + ADC_SAR_SAMPLE_CTRL_REG &= (uint32)(~ADC_CONTINUOUS_EN); + #endif /* ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ +} + + +/******************************************************************************* +* Function Name: ADC_IsEndConversion +******************************************************************************** +* +* Summary: +* Description: Checks for ADC end of conversion for the case one +* channel and end of scan for the case of multiple channels. It acts +* as a software version of the EOC. This function provides the +* programmer with two options. In one mode this function +* immediately returns with the conversion status. In the other mode, +* the function does not return (blocking) until the conversion has +* completed. +* +* Parameters: +* ADC_RETURN_STATUS -> Immediately returns conversion result status +* ADC_WAIT_FOR_RESULT -> Does not return until ADC complete +* ADC_RETURN_STATUS_INJ -> Immediately returns conversion result status +* for injection channel +* ADC_WAIT_FOR_RESULT_INJ -> Does not return until ADC completes injection +* channel conversion +* +* Return: +* If a non-zero value is returned, the last conversion or scan has completed. +* If the returned value is zero, the ADC is still in the process of a scan. +* +*******************************************************************************/ +uint32 ADC_IsEndConversion(uint32 retMode) +{ + uint32 status = 0u; + + if((retMode & (ADC_RETURN_STATUS | ADC_WAIT_FOR_RESULT)) != 0u) + { + do + { + status = ADC_SAR_INTR_REG & ADC_EOS_MASK; + }while((status == 0u) && ((retMode & ADC_WAIT_FOR_RESULT) != 0u)); + + if(status != 0u) + { + /* Clear EOS bit */ + ADC_SAR_INTR_REG = ADC_EOS_MASK; + } + } + + #if(ADC_INJ_CHANNEL_ENABLED) + if((retMode & (ADC_RETURN_STATUS_INJ | ADC_WAIT_FOR_RESULT_INJ)) != 0u) + { + do + { + status |= ADC_SAR_INTR_REG & ADC_INJ_EOC_MASK; + }while(((status & ADC_INJ_EOC_MASK) == 0u) && + ((retMode & ADC_WAIT_FOR_RESULT_INJ) != 0u)); + + if((status & ADC_INJ_EOC_MASK) != 0u) + { + /* Clear Injection EOS bit */ + ADC_SAR_INTR_REG = ADC_INJ_EOC_MASK; + } + } + #endif /* ADC_INJ_CHANNEL_ENABLED */ + + return (status); +} + + +/******************************************************************************* +* Function Name: ADC_GetResult16 +******************************************************************************** +* +* Summary: +* Gets the data available in the SAR DATA register. +* +* Parameters: +* chan: The ADC channel in which to return the result. The first channel +* is 0 and the injection channel if enabled is the number of valid channels. +* +* Return: +* Returns converted data as a signed 16-bit integer +* +*******************************************************************************/ +int16 ADC_GetResult16(uint32 chan) +{ + uint32 result; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + if(chan < ADC_SEQUENCED_CHANNELS_NUM) + { + result = CY_GET_REG32((reg32 *)(ADC_SAR_CHAN_RESULT_IND + (uint32)(chan << 2u))) & + ADC_RESULT_MASK; + } + else + { + #if(ADC_INJ_CHANNEL_ENABLED) + result = ADC_SAR_INJ_RESULT_REG & ADC_RESULT_MASK; + #else + result = 0u; + #endif /* ADC_INJ_CHANNEL_ENABLED */ + } + + return ( (int16)result ); +} + + +/******************************************************************************* +* Function Name: ADC_SetChanMask +******************************************************************************** +* +* Summary: +* Sets the channel enable mask. +* +* Parameters: +* mask: Sets which channels that will be +* scanned. Setting bits for channels that do not exist will have no +* effect. For example, if only 6 channels were enabled, setting a +* mask of 0x0103 would only enable the last two channels (0 and 1). +* This API will not enable the injection channel. +* Examples: If the component is setup to sequence through 8 +* channels, a mask of 0x000F would enable channels 0, 1, 2, and 3. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetChanMask(uint32 mask) +{ + ADC_SAR_CHAN_EN_REG = mask & ADC_MAX_CHANNELS_EN_MASK; +} + +#if(ADC_INJ_CHANNEL_ENABLED) + + + /******************************************************************************* + * Function Name: ADC_EnableInjection + ******************************************************************************** + * + * Summary: + * Enables the injection channel for the next scan only. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void ADC_EnableInjection(void) + { + ADC_SAR_INJ_CHAN_CONFIG_REG |= ADC_INJ_CHAN_EN; + } + +#endif /* ADC_INJ_CHANNEL_ENABLED */ + + +/******************************************************************************* +* Function Name: ADC_SetLowLimit +******************************************************************************** +* +* Summary: +* Sets the low limit parameter for a limit condition. +* +* Parameters: +* lowLimit: The low limit for a limit condition. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetLowLimit(uint32 lowLimit) +{ + ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_LOW_MASK); + ADC_SAR_RANGE_THRES_REG |= lowLimit & ADC_RANGE_LOW_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SetHighLimit +******************************************************************************** +* +* Summary: +* Sets the low limit parameter for a limit condition. +* +* Parameters: +* highLimit: The high limit for a limit condition. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetHighLimit(uint32 highLimit) +{ + ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_HIGH_MASK); + ADC_SAR_RANGE_THRES_REG |= (uint32)(highLimit << ADC_RANGE_HIGH_OFFSET); +} + + +/******************************************************************************* +* Function Name: ADC_SetLimitMask +******************************************************************************** +* +* Summary: +* Sets the channel limit condition mask. +* +* Parameters: +* mask: Sets which channels that may cause a +* limit condition interrupt. Setting bits for channels that do not exist +* will have no effect. For example, if only 6 channels were enabled, +* setting a mask of 0x0103 would only enable the last two channels (0 and 1). +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetLimitMask(uint32 mask) +{ + ADC_SAR_RANGE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SetSatMask +******************************************************************************** +* +* Summary: +* Sets the channel saturation event mask. +* +* Parameters: +* mask: Sets which channels that may cause a +* saturation event interrupt. Setting bits for channels that do not exist +* will have no effect. For example, if only 8 channels were enabled, +* setting a mask of 0x01C0 would only enable two channels (6 and 7). +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetSatMask(uint32 mask) +{ + ADC_SAR_SATURATE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SetOffset +******************************************************************************** +* +* Summary: +* Description: Sets the ADC offset which is used by the functions +* ADC_CountsTo_uVolts, ADC_CountsTo_mVolts and ADC_CountsTo_Volts +* to substract the offset from the given reading +* before calculating the voltage conversion. +* +* Parameters: +* chan: ADC channel number. +* offset: This value is a measured value when the +* inputs are shorted or connected to the same input voltage. +* +* Return: +* None. +* +* Global variables: +* ADC_Offset: Modified to set the user provided offset. +* +*******************************************************************************/ +void ADC_SetOffset(uint32 chan, int16 offset) +{ + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + ADC_offset[chan] = offset; +} + + +/******************************************************************************* +* Function Name: ADC_SetGain +******************************************************************************** +* +* Summary: +* Description: Sets the ADC gain in counts per 10 volt for the voltage +* conversion functions below. This value is set by default by the +* reference and input range settings. It should only be used to further +* calibrate the ADC with a known input or if an external reference is +* used. Affects the ADC_CountsTo_uVolts, ADC_CountsTo_mVolts +* and ADC_CountsTo_Volts functions by supplying the correct +* conversion between ADC counts and voltage. +* +* Parameters: +* chan: ADC channel number. +* adcGain: ADC gain in counts per 10 volts. +* +* Return: +* None. +* +* Global variables: +* ADC_CountsPer10Volt: modified to set the ADC gain in counts +* per 10 volt. +* +*******************************************************************************/ +void ADC_SetGain(uint32 chan, int32 adcGain) +{ + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + ADC_countsPer10Volt[chan] = adcGain; +} + + +#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT) + + + /******************************************************************************* + * Function Name: ADC_CountsTo_mVolts + ******************************************************************************** + * + * Summary: + * This function converts ADC counts to mVolts + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * adcCounts: Result from the ADC conversion + * + * Return: + * Results in mVolts + * + * Global variables: + * ADC_countsPer10Volt: used to convert ADC counts to mVolts. + * ADC_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + *******************************************************************************/ + int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts) + { + int16 mVolts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_offset[chan]; + + mVolts = (int16)((((int32)adcCounts * ADC_10MV_COUNTS) + ( (adcCounts > 0) ? + (ADC_countsPer10Volt[chan] / 2) : (-(ADC_countsPer10Volt[chan] / 2)) )) + / ADC_countsPer10Volt[chan]); + + return( mVolts ); + } + + + /******************************************************************************* + * Function Name: ADC_CountsTo_uVolts + ******************************************************************************** + * + * Summary: + * This function converts ADC counts to micro Volts + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * adcCounts: Result from the ADC conversion + * + * Return: + * Results in uVolts + * + * Global variables: + * ADC_countsPer10Volt: used to convert ADC counts to uVolts. + * ADC_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + * Theory: + * Care must be taken to not exceed the maximum value for a 31 bit signed + * number in the conversion to uVolts and at the same time not loose + * resolution. + * To convert adcCounts to microVolts it is required to be multiplied + * on 10 million and later divide on gain in counts per 10V. + * + *******************************************************************************/ + int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts) + { + int64 uVolts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_offset[chan]; + + uVolts = ((int64)adcCounts * ADC_10UV_COUNTS) / ADC_countsPer10Volt[chan]; + + return( (int32)uVolts ); + } + + + /******************************************************************************* + * Function Name: ADC_CountsTo_Volts + ******************************************************************************** + * + * Summary: + * Converts the ADC output to Volts as a floating point number. + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * Result from the ADC conversion + * + * Return: + * Results in Volts + * + * Global variables: + * ADC_countsPer10Volt: used to convert ADC counts to Volts. + * ADC_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + *******************************************************************************/ + float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts) + { + float32 volts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_offset[chan]; + + volts = ((float32)adcCounts * ADC_10V_COUNTS) / (float32)ADC_countsPer10Volt[chan]; + + return( volts ); + } + +#endif /* End ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC.h new file mode 100644 index 0000000..78a0469 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC.h @@ -0,0 +1,713 @@ +/******************************************************************************* +* File Name: ADC.h +* Version 2.50 +* +* Description: +* This file contains the function prototypes and constants used in +* the Sequencing Successive Approximation ADC Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_ADC_SAR_SEQ_ADC_H) +#define CY_ADC_SAR_SEQ_ADC_H + +#include "cytypes.h" +#include "CyLib.h" + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint32 dftRegVal; +} ADC_BACKUP_STRUCT; + + +/************************************** +* Enumerated Types and Parameters +**************************************/ + +/* Clock Source setting constants */ +#define ADC__EXTERNAL 0 +#define ADC__INTERNAL 1 + +/* Sample Mode setting constants */ +#define ADC__FREERUNNING 0 +#define ADC__HARDWARESOC 1 + +/* Reference type setting constants */ +#define ADC__VDDA_2 0 +#define ADC__VDDA 1 +#define ADC__INTERNAL1024 2 +#define ADC__INTERNAL1024BYPASSED 3 +#define ADC__INTERNALVREF 4 +#define ADC__INTERNALVREFBYPASSED 5 +#define ADC__VDDA_2BYPASSED 6 +#define ADC__EXTERNALVREF 7 + +/* Input buffer gain setting constants */ +#define ADC__DISABLED 0 +#define ADC__ONE 1 +#define ADC__TWO 2 +#define ADC__FOUR 3 +#define ADC__EIGHT 4 +#define ADC__SIXTEEN 5 + +/* Negative input setting sonstants in single ended mode */ +#define ADC__VSS 0 +#define ADC__VREF 1 +#define ADC__OTHER 2 + +/* Compare mode setting constants: +* Mode0 - Disable +* Mode1 - Result < Low_Limit +* Mode2 - Low_Limit <= Result < High_Limit +* Mode3 - High_Limit <= Result +* Mode4 - (Result < Low_Limit) or (High_Limit <= Result) +*/ +#define ADC__MODE0 0 +#define ADC__MODE1 1 +#define ADC__MODE2 2 +#define ADC__MODE3 3 + +#define ADC__RES8 0 +#define ADC__RES10 1 + +#define ADC__RIGHT 0 +#define ADC__LEFT 1 + +#define ADC__FSIGNED 1 +#define ADC__FUNSIGNED 0 + +#define ADC__ACCUMULATE 0 +#define ADC__FIXEDRESOLUTION 1 + + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#define ADC_CY_SAR_IP_VER0 (0u) +#define ADC_CY_SAR_IP_VER1 (1u) + +#if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define ADC_CY_SAR_IP_VER (ADC_CY_SAR_IP_VER0) +#else /* Other devices */ + #define ADC_CY_SAR_IP_VER (ADC_CY_SAR_IP_VER1) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + +/*************************************** +* Initial Parameter Constants +***************************************/ +#define ADC_DEFAULT_SAMPLE_MODE_SEL (0u) +#define ADC_DEFAULT_VREF_SEL (1u) +#define ADC_DEFAULT_NEG_INPUT_SEL (0u) +#define ADC_DEFAULT_ALT_RESOLUTION_SEL (0u) +#define ADC_DEFAULT_JUSTIFICATION_SEL (0u) +#define ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL (0u) +#define ADC_DEFAULT_SE_RESULT_FORMAT_SEL (1u) +#define ADC_DEFAULT_CLOCK_SOURCE (1u) +#define ADC_DEFAULT_VREF_MV_VALUE (5000) +#define ADC_DEFAULT_BUFFER_GAIN (0u) +#define ADC_DEFAULT_AVG_SAMPLES_NUM (7u) +#define ADC_DEFAULT_AVG_SAMPLES_DIV (7u < 4u) ? (int16)(0x100u >> (7u - 7u)) : (int16)(0x100u >> 4u) +#define ADC_DEFAULT_AVG_MODE (1u) +#define ADC_MAX_RESOLUTION (12u) +#define ADC_DEFAULT_LOW_LIMIT (511u) +#define ADC_DEFAULT_HIGH_LIMIT (1534u) +#define ADC_DEFAULT_COMPARE_MODE (3u) +#define ADC_DEFAULT_ACLKS_NUM (2u) +#define ADC_DEFAULT_BCLKS_NUM (2u) +#define ADC_DEFAULT_CCLKS_NUM (2u) +#define ADC_DEFAULT_DCLKS_NUM (2u) +#define ADC_TOTAL_CHANNELS_NUM (1u) +#define ADC_SEQUENCED_CHANNELS_NUM (1u) +#define ADC_DEFAULT_EN_CHANNELS (1u) +#define ADC_NOMINAL_CLOCK_FREQ (1000000) +#define ADC_INJ_CHANNEL_ENABLED (0u) +#define ADC_IRQ_REMOVE (0u) + +/* Determines whether the configuration contains external negative input. */ +#define ADC_SINGLE_PRESENT (0u) +#define ADC_CHANNELS_MODE (0u) +#define ADC_MAX_CHANNELS_EN_MASK (0xffffu >> (16u - ADC_SEQUENCED_CHANNELS_NUM)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void ADC_Start(void); +void ADC_Stop(void); +void ADC_Init(void); +void ADC_Enable(void); +void ADC_StartConvert(void); +void ADC_StopConvert(void); +uint32 ADC_IsEndConversion(uint32 retMode); +int16 ADC_GetResult16(uint32 chan); +void ADC_SetChanMask(uint32 mask); +void ADC_SetLowLimit(uint32 lowLimit); +void ADC_SetHighLimit(uint32 highLimit); +void ADC_SetLimitMask(uint32 mask); +void ADC_SetSatMask(uint32 mask); +void ADC_SetOffset(uint32 chan, int16 offset); +void ADC_SetGain(uint32 chan, int32 adcGain); +#if(ADC_INJ_CHANNEL_ENABLED) + void ADC_EnableInjection(void); +#endif /* ADC_INJ_CHANNEL_ENABLED */ +#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT) + int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts); + int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts); + float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts); +#endif /* End ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */ +void ADC_Sleep(void); +void ADC_Wakeup(void); +void ADC_SaveConfig(void); +void ADC_RestoreConfig(void); + +CY_ISR_PROTO( ADC_ISR ); + + +/************************************** +* API Constants +**************************************/ +/* Constants for Sleep mode states */ +#define ADC_DISABLED (0x00u) +#define ADC_ENABLED (0x01u) +#define ADC_STARTED (0x02u) +#define ADC_BOOSTPUMP_ENABLED (0x04u) + +/* Constants for IsEndConversion() "retMode" parameter */ +#define ADC_RETURN_STATUS (0x01u) +#define ADC_WAIT_FOR_RESULT (0x02u) +#define ADC_RETURN_STATUS_INJ (0x04u) +#define ADC_WAIT_FOR_RESULT_INJ (0x08u) + +#define ADC_MAX_FREQUENCY (18000000) /*18Mhz*/ + +#define ADC_RESOLUTION_12 (12u) +#define ADC_RESOLUTION_10 (10u) +#define ADC_RESOLUTION_8 (8u) + +#define ADC_10US_DELAY (10u) + +#define ADC_10V_COUNTS (10.0F) +#define ADC_10MV_COUNTS (10000) +#define ADC_10UV_COUNTS (10000000L) + + +/*************************************** +* Global variables external identifier +***************************************/ + +extern uint8 ADC_initVar; +extern volatile int16 ADC_offset[ADC_TOTAL_CHANNELS_NUM]; +extern volatile int32 ADC_countsPer10Volt[ADC_TOTAL_CHANNELS_NUM]; + + +/*************************************** +* Registers +***************************************/ + +#define ADC_SAR_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CTRL ) +#define ADC_SAR_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CTRL ) + +#define ADC_SAR_SAMPLE_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL ) +#define ADC_SAR_SAMPLE_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL ) + +#define ADC_SAR_SAMPLE_TIME01_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 ) +#define ADC_SAR_SAMPLE_TIME01_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 ) + +#define ADC_SAR_SAMPLE_TIME23_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 ) +#define ADC_SAR_SAMPLE_TIME23_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 ) + +#define ADC_SAR_RANGE_THRES_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_THRES ) +#define ADC_SAR_RANGE_THRES_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_THRES ) + +#define ADC_SAR_RANGE_COND_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_COND ) +#define ADC_SAR_RANGE_COND_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_COND ) + +#define ADC_SAR_CHAN_EN_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_EN ) +#define ADC_SAR_CHAN_EN_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_EN ) + +#define ADC_SAR_START_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_START_CTRL ) +#define ADC_SAR_START_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_START_CTRL ) + +#define ADC_SAR_DFT_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_DFT_CTRL ) +#define ADC_SAR_DFT_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_DFT_CTRL ) + +#define ADC_SAR_CHAN_CONFIG_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 ) +#define ADC_SAR_CHAN_CONFIG_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 ) +#define ADC_SAR_CHAN_CONFIG_IND ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 + +#define ADC_SAR_CHAN_WORK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK00 ) +#define ADC_SAR_CHAN_WORK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK00 ) + +#define ADC_SAR_CHAN_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_CHAN_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_CHAN_RESULT_IND ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 + +#define ADC_SAR_CHAN0_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_CHAN0_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) + +#define ADC_SAR_CHAN1_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 ) +#define ADC_SAR_CHAN1_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 ) + +#define ADC_SAR_CHAN2_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 ) +#define ADC_SAR_CHAN2_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 ) + +#define ADC_SAR_CHAN3_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 ) +#define ADC_SAR_CHAN3_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 ) + +#define ADC_SAR_CHAN4_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 ) +#define ADC_SAR_CHAN4_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 ) + +#define ADC_SAR_CHAN5_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 ) +#define ADC_SAR_CHAN5_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 ) + +#define ADC_SAR_CHAN6_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 ) +#define ADC_SAR_CHAN6_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 ) + +#define ADC_SAR_CHAN7_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 ) +#define ADC_SAR_CHAN7_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 ) + +#if(ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) + #define ADC_SAR_CHAN8_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 ) + #define ADC_SAR_CHAN8_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 ) + + #define ADC_SAR_CHAN9_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 ) + #define ADC_SAR_CHAN9_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 ) + + #define ADC_SAR_CHAN10_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 ) + #define ADC_SAR_CHAN10_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 ) + + #define ADC_SAR_CHAN11_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 ) + #define ADC_SAR_CHAN11_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 ) + + #define ADC_SAR_CHAN12_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 ) + #define ADC_SAR_CHAN12_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 ) + + #define ADC_SAR_CHAN13_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 ) + #define ADC_SAR_CHAN13_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 ) + + #define ADC_SAR_CHAN14_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 ) + #define ADC_SAR_CHAN14_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 ) + + #define ADC_SAR_CHAN15_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 ) + #define ADC_SAR_CHAN15_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 ) +#endif /* (ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) */ + +#define ADC_SAR_CHAN_WORK_VALID_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID) +#define ADC_SAR_CHAN_WORK_VALID_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID) + +#define ADC_SAR_CHAN_RESULT_VALID_REG ( *(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID ) +#define ADC_SAR_CHAN_RESULT_VALID_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID ) + +#define ADC_SAR_STATUS_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_STATUS ) +#define ADC_SAR_STATUS_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_STATUS ) + +#define ADC_SAR_AVG_START_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_AVG_STAT ) +#define ADC_SAR_AVG_START_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_AVG_STAT ) + +#define ADC_SAR_INTR_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR ) +#define ADC_SAR_INTR_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR ) + +#define ADC_SAR_INTR_SET_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_SET ) +#define ADC_SAR_INTR_SET_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_SET ) + +#define ADC_SAR_INTR_MASK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASK ) +#define ADC_SAR_INTR_MASK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASK ) + +#define ADC_SAR_INTR_MASKED_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASKED ) +#define ADC_SAR_INTR_MASKED_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASKED ) + +#define ADC_SAR_SATURATE_INTR_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR ) +#define ADC_SAR_SATURATE_INTR_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR ) + +#define ADC_SAR_SATURATE_INTR_SET_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET ) +#define ADC_SAR_SATURATE_INTR_SET_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET ) + +#define ADC_SAR_SATURATE_INTR_MASK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK ) +#define ADC_SAR_SATURATE_INTR_MASK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK ) + +#define ADC_SAR_SATURATE_INTR_MASKED_REG \ + (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED ) +#define ADC_SAR_SATURATE_INTR_MASKED_PTR \ + ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED ) + +#define ADC_SAR_RANGE_INTR_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR ) +#define ADC_SAR_RANGE_INTR_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR ) + +#define ADC_SAR_RANGE_INTR_SET_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET ) +#define ADC_SAR_RANGE_INTR_SET_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET ) + +#define ADC_SAR_RANGE_INTR_MASK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK ) +#define ADC_SAR_RANGE_INTR_MASK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK ) + +#define ADC_SAR_RANGE_INTR_MASKED_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED ) +#define ADC_SAR_RANGE_INTR_MASKED_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED ) + +#define ADC_SAR_INTR_CAUSE_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_CAUSE ) +#define ADC_SAR_INTR_CAUSE_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_CAUSE ) + +#if(ADC_INJ_CHANNEL_ENABLED) + #define ADC_SAR_INJ_CHAN_CONFIG_REG \ + (*(reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG ) + #define ADC_SAR_INJ_CHAN_CONFIG_PTR \ + ( (reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG ) + + #define ADC_SAR_INJ_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_RESULT ) + #define ADC_SAR_INJ_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_RESULT ) +#endif /* ADC_INJ_CHANNEL_ENABLED */ + +#define ADC_MUX_SWITCH0_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 ) +#define ADC_MUX_SWITCH0_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 ) + +#define ADC_MUX_SWITCH_HW_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL ) +#define ADC_MUX_SWITCH_HW_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL ) + +#define ADC_PUMP_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_PUMP_CTRL ) +#define ADC_PUMP_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_PUMP_CTRL ) + +#define ADC_ANA_TRIM_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_ANA_TRIM ) +#define ADC_ANA_TRIM_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_ANA_TRIM ) + +#define ADC_WOUNDING_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_WOUNDING ) +#define ADC_WOUNDING_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_WOUNDING ) + + +/************************************** +* Register Constants +**************************************/ +#define ADC_INTC_NUMBER (ADC_IRQ__INTC_NUMBER) +#define ADC_INTC_PRIOR_NUMBER (ADC_IRQ__INTC_PRIOR_NUM) + +/* defines for CTRL register */ +#define ADC_VREF_INTERNAL1024 (0x00000040Lu) +#define ADC_VREF_EXTERNAL (0x00000050Lu) +#define ADC_VREF_VDDA_2 (0x00000060Lu) +#define ADC_VREF_VDDA (0x00000070Lu) +#define ADC_VREF_INTERNAL1024BYPASSED (0x000000C0Lu) +#define ADC_VREF_VDDA_2BYPASSED (0x000000E0Lu) +#define ADC_VREF_INTERNALVREF (0x00000040Lu) +#define ADC_VREF_INTERNALVREFBYPASSED (0x000000C0Lu) + +#define ADC_NEG_VSSA_KELVIN (0x00000000Lu) +#define ADC_NEG_VSSA (0x00000200Lu) +#define ADC_NEG_VREF (0x00000E00Lu) +#if(ADC_TOTAL_CHANNELS_NUM > 1u) + #define ADC_NEG_OTHER (uint16)((uint16)ADC_cy_psoc4_sarmux_8__VNEG0 << 9u) +#else + #define ADC_NEG_OTHER (0) +#endif /* ADC_TOTAL_CHANNELS_NUM > 1u */ + +#define ADC_SAR_HW_CTRL_NEGVREF (0x00002000Lu) + +#define ADC_BOOSTPUMP_EN (0x00100000Lu) + +#define ADC_NORMAL_PWR (0x00000000Lu) +#define ADC_HALF_PWR (0x01000000Lu) +#define ADC_MORE_PWR (0x02000000Lu) +#define ADC_QUARTER_PWR (0x03000000Lu) +#define ADC_DEEPSLEEP_ON (0x08000000Lu) + +#define ADC_DSI_SYNC_CONFIG (0x10000000Lu) +#define ADC_DSI_MODE (0x20000000Lu) +#define ADC_SWITCH_DISABLE (0x40000000Lu) +#define ADC_ENABLE (0x80000000Lu) + +/* defines for STATUS register */ +#define ADC_STATUS_BUSY (0x80000000Lu) + +/* defines for SAMPLE_CTRL register */ +#define ADC_ALT_RESOLUTION_10BIT (0x00000001Lu) +#define ADC_ALT_RESOLUTION_8BIT (0x00000000Lu) + +#define ADC_DATA_ALIGN_LEFT (0x00000002Lu) +#define ADC_DATA_ALIGN_RIGHT (0x00000000Lu) + +#define ADC_SE_SIGNED_RESULT (0x00000004Lu) +#define ADC_SE_UNSIGNED_RESULT (0x00000000Lu) + +#define ADC_DIFF_SIGNED_RESULT (0x00000008Lu) +#define ADC_DIFF_UNSIGNED_RESULT (0x00000000Lu) + +#define ADC_AVG_CNT_OFFSET (4u) +#define ADC_AVG_CNT_MASK (0x00000070Lu) +#define ADC_AVG_SHIFT (0x00000080Lu) + +#define ADC_CONTINUOUS_EN (0x00010000Lu) +#define ADC_DSI_TRIGGER_EN (0x00020000Lu) +#define ADC_DSI_TRIGGER_LEVEL (0x00040000Lu) +#define ADC_DSI_SYNC_TRIGGER (0x00080000Lu) +#define ADC_EOS_DSI_OUT_EN (0x80000000Lu) + +/* defines for SAMPLE_TIME01 / SAMPLE_TIME23 registers */ +#define ADC_SAMPLE_TIME13_OFFSET (16u) +#define ADC_SAMPLE_TIME02_MASK (0x000003FFLu) +#define ADC_SAMPLE_TIME13_MASK (0x03FF0000Lu) + +/* defines for RANGE_THRES registers */ +#define ADC_RANGE_HIGH_OFFSET (16u) +#define ADC_RANGE_HIGH_MASK (0xFFFF0000Lu) +#define ADC_RANGE_LOW_MASK (0x0000FFFFLu) + +/* defines for RANGE_COND register */ +/* Compare mode setting constants: +* BELOW - Result < Low_Limit +* INSIDE - Low_Limit <= Result < High_Limit +* ABOVE - High_Limit <= Result +* OUTSIDE - (Result < Low_Limit) or (High_Limit <= Result) +*/ +#define ADC_CMP_MODE_BELOW (0x00000000Lu) +#define ADC_CMP_MODE_INSIDE (0x40000000Lu) +#define ADC_CMP_MODE_ABOVE (0x80000000Lu) +#define ADC_CMP_MODE_OUTSIDE (0xC0000000Lu) +#define ADC_CMP_OFFSET (30u) + +/* defines for _START_CTRL register */ +#define ADC_FW_TRIGGER (0x00000001Lu) + +/* defines for DFT_CTRL register */ +#define ADC_DLY_INC (0x00000001Lu) +#define ADC_HIZ (0x00000002Lu) +#define ADC_DFT_INC_MASK (0x000F0000Lu) +#define ADC_DFT_OUTC_MASK (0x00700000Lu) +#define ADC_SEL_CSEL_DFT_MASK (0x0F000000Lu) + +/* configuration for clock speed > 9 Mhz based on +* characterization results +*/ +#define ADC_SEL_CSEL_DFT_CHAR (0x03000000Lu) +#define ADC_EN_CSEL_DFT (0x10000000Lu) +#define ADC_DCEN (0x20000000Lu) +#define ADC_ADFT_OVERRIDE (0x80000000Lu) + +/* defines for CHAN_CONFIG / DIE_CHAN_CONFIG register +* and channelsConfig parameter +*/ +#define ADC_SARMUX_VIRT_SELECT (0x00000070Lu) +#define ADC_DIFFERENTIAL_EN (0x00000100Lu) +#define ADC_ALT_RESOLUTION_ON (0x00000200Lu) +#define ADC_AVERAGING_EN (0x00000400Lu) + +#define ADC_SAMPLE_TIME_SEL_SHIFT (12u) +#define ADC_SAMPLE_TIME_SEL_MASK (0x00003000Lu) + +#define ADC_CHANNEL_CONFIG_MASK (0x00003700Lu) + +/* for CHAN_CONFIG only */ +#define ADC_DSI_OUT_EN (0x80000000Lu) + +/* for INJ_CHAN_CONFIG only */ +#define ADC_INJ_TAILGATING (0x40000000Lu) +#define ADC_INJ_CHAN_EN (0x80000000Lu) + +/* defines for CHAN_WORK register */ +#define ADC_SAR_WRK_MAX_12BIT (0x00001000Lu) +#define ADC_SAR_WRK_MAX_10BIT (0x00000400Lu) +#define ADC_SAR_WRK_MAX_8BIT (0x00000100Lu) + +/* defines for CHAN_RESULT register */ +#define ADC_RESULT_MASK (0x0000FFFFLu) +#define ADC_SATURATE_INTR_MIR (0x20000000Lu) +#define ADC_RANGE_INTR_MIR (0x40000000Lu) +#define ADC_CHAN_RESULT_VALID_MIR (0x80000000Lu) + +/* defines for INTR_MASK register */ +#define ADC_EOS_MASK (0x00000001Lu) +#define ADC_OVERFLOW_MASK (0x00000002Lu) +#define ADC_FW_COLLISION_MASK (0x00000004Lu) +#define ADC_DSI_COLLISION_MASK (0x00000008Lu) +#define ADC_INJ_EOC_MASK (0x00000010Lu) +#define ADC_INJ_SATURATE_MASK (0x00000020Lu) +#define ADC_INJ_RANGE_MASK (0x00000040Lu) +#define ADC_INJ_COLLISION_MASK (0x00000080Lu) + +/* defines for INJ_RESULT register */ +#define ADC_INJ_COLLISION_INTR_MIR (0x10000000Lu) +#define ADC_INJ_SATURATE_INTR_MIR (0x20000000Lu) +#define ADC_INJ_RANGE_INTR_MIR (0x40000000Lu) +#define ADC_INJ_EOC_INTR_MIR (0x80000000Lu) + +/* defines for MUX_SWITCH0 register */ +#define ADC_MUX_FW_VSSA_VMINUS (0x00010000Lu) + +/* defines for PUMP_CTRL register */ +#define ADC_PUMP_CTRL_ENABLED (0x80000000Lu) + +/* additional defines for channelsConfig parameter */ +#define ADC_IS_SATURATE_EN_MASK (0x00000001Lu) +#define ADC_IS_RANGE_CTRL_EN_MASK (0x00000002Lu) + +/* defines for WOUNDING register */ +#define ADC_WOUNDING_12BIT (0x00000000Lu) +#define ADC_WOUNDING_10BIT (0x00000001Lu) +#define ADC_WOUNDING_8BIT (0x00000002Lu) + +/* Trim value based on characterization */ +#define ADC_TRIM_COEF (2u) + +#if(ADC_MAX_RESOLUTION == ADC_RESOLUTION_10) + #define ADC_ALT_WOUNDING ADC_WOUNDING_10BIT +#else + #define ADC_ALT_WOUNDING ADC_WOUNDING_8BIT +#endif /* ADC_MAX_RESOLUTION == ADC_RESOLUTION_10 */ + +#if(ADC_DEFAULT_VREF_SEL == ADC__VDDA_2) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_VDDA_2 +#elif(ADC_DEFAULT_VREF_SEL == ADC__VDDA) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_VDDA +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNAL1024 +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024BYPASSED) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNAL1024BYPASSED +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNALVREF +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREFBYPASSED) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNALVREFBYPASSED +#elif(ADC_DEFAULT_VREF_SEL == ADC__VDDA_2BYPASSED) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_VDDA_2BYPASSED +#else + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_EXTERNAL +#endif /* ADC_DEFAULT_VREF_SEL == ADC__VDDA_2 */ + +#if(ADC_DEFAULT_NEG_INPUT_SEL == ADC__VSS) + /* Connect NEG input of SARADC to VSSA close to the SARADC for single channel mode */ + #if(ADC_TOTAL_CHANNELS_NUM == 1u) + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_VSSA + #else + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_VSSA_KELVIN + #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ + /* Do not connect VSSA to VMINUS when one channel in differential mode used */ + #if((ADC_TOTAL_CHANNELS_NUM == 1u) && (ADC_CHANNELS_MODE != 0u)) + #define ADC_DEFAULT_MUX_SWITCH0 0u + #else /* miltiple channels or one single channel */ + #define ADC_DEFAULT_MUX_SWITCH0 ADC_MUX_FW_VSSA_VMINUS + #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ +#elif(ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF) + /* Do not connect VNEG to VREF when one channel in differential mode used */ + #if((ADC_TOTAL_CHANNELS_NUM == 1u) && (ADC_CHANNELS_MODE != 0u)) + #define ADC_DEFAULT_SE_NEG_INPUT 0u + #else /* miltiple channels or one single channel */ + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_VREF + #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ + #define ADC_DEFAULT_MUX_SWITCH0 0u +#elif (ADC_SINGLE_PRESENT != 0u) + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_OTHER + #define ADC_DEFAULT_MUX_SWITCH0 0u +#else + #define ADC_DEFAULT_SE_NEG_INPUT 0u + #define ADC_DEFAULT_MUX_SWITCH0 0u +#endif /* ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF */ + +/* If the SAR is configured for multiple channels, always set SAR_HW_CTRL_NEGVREF to 1 */ +#if(ADC_TOTAL_CHANNELS_NUM == 1u) + #define ADC_DEFAULT_HW_CTRL_NEGVREF 0u +#else + #define ADC_DEFAULT_HW_CTRL_NEGVREF ADC_SAR_HW_CTRL_NEGVREF +#endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ + + +#if(ADC_DEFAULT_ALT_RESOLUTION_SEL == ADC__RES8) + #define ADC_DEFAULT_ALT_RESOLUTION (ADC_ALT_RESOLUTION_8BIT) + #define ADC_DEFAULT_MAX_WRK_ALT (ADC_SAR_WRK_MAX_8BIT) +#else + #define ADC_DEFAULT_ALT_RESOLUTION (ADC_ALT_RESOLUTION_10BIT) + #define ADC_DEFAULT_MAX_WRK_ALT (ADC_SAR_WRK_MAX_10BIT) +#endif /* End ADC_DEFAULT_ALT_RESOLUTION_SEL == ADC__RES8 */ + +#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT) + #define ADC_DEFAULT_JUSTIFICATION ADC_DATA_ALIGN_RIGHT +#else + #define ADC_DEFAULT_JUSTIFICATION ADC_DATA_ALIGN_LEFT +#endif /* ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */ + +#if(ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FSIGNED) + #define ADC_DEFAULT_DIFF_RESULT_FORMAT ADC_DIFF_SIGNED_RESULT +#else + #define ADC_DEFAULT_DIFF_RESULT_FORMAT ADC_DIFF_UNSIGNED_RESULT +#endif /* ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FSIGNED */ + +#if(ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED) + #define ADC_DEFAULT_SE_RESULT_FORMAT ADC_SE_SIGNED_RESULT +#else + #define ADC_DEFAULT_SE_RESULT_FORMAT ADC_SE_UNSIGNED_RESULT +#endif /* ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED */ + +#if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + #define ADC_DSI_TRIGGER 0u +#else /* Firmware trigger */ + #define ADC_DSI_TRIGGER (ADC_DSI_TRIGGER_EN | ADC_DSI_SYNC_TRIGGER) +#endif /* End ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ + +#if(ADC_INJ_CHANNEL_ENABLED) + #define ADC_SAR_INTR_MASK (ADC_EOS_MASK | ADC_INJ_EOC_MASK) +#else + #define ADC_SAR_INTR_MASK (ADC_EOS_MASK) +#endif /* ADC_INJ_CHANNEL_ENABLED*/ + +#if(ADC_DEFAULT_AVG_MODE == ADC__FIXEDRESOLUTION) + #define ADC_AVG_SHIFT_MODE ADC_AVG_SHIFT +#else + #define ADC_AVG_SHIFT_MODE 0u +#endif /* End ADC_DEFAULT_AVG_MODE */ + +#define ADC_COMPARE_MODE (uint32)((uint32)(ADC_DEFAULT_COMPARE_MODE) \ + << ADC_CMP_OFFSET) + +#if(ADC_TOTAL_CHANNELS_NUM > 1u) + #define ADC_DEFAULT_SWITCH_CONF 0u +#else /* Disable SAR sequencer from enabling routing switches in single channel mode */ + #define ADC_DEFAULT_SWITCH_CONF ADC_SWITCH_DISABLE +#endif /* End ADC_TOTAL_CHANNELS_NUM > 1 */ + +#define ADC_DEFAULT_POWER \ + ((ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 4)) ? ADC_NORMAL_PWR : \ + ((ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 8)) ? ADC_HALF_PWR : \ + ADC_QUARTER_PWR)) + +#define ADC_DEFAULT_CTRL_REG_CFG (ADC_DEFAULT_VREF_SOURCE \ + | ADC_DEFAULT_SE_NEG_INPUT \ + | ADC_DEFAULT_HW_CTRL_NEGVREF \ + | ADC_DEFAULT_POWER \ + | ADC_DSI_SYNC_CONFIG \ + | ADC_DEFAULT_SWITCH_CONF) + +#define ADC_DEFAULT_SAMPLE_CTRL_REG_CFG (ADC_DEFAULT_DIFF_RESULT_FORMAT \ + | ADC_DEFAULT_SE_RESULT_FORMAT \ + | ADC_DEFAULT_JUSTIFICATION \ + | ADC_DEFAULT_ALT_RESOLUTION \ + | (uint8)(ADC_DEFAULT_AVG_SAMPLES_NUM \ + << ADC_AVG_CNT_OFFSET) \ + | ADC_AVG_SHIFT_MODE \ + | ADC_DSI_TRIGGER \ + | ADC_EOS_DSI_OUT_EN) + +#define ADC_DEFAULT_RANGE_THRES_REG_CFG (ADC_DEFAULT_LOW_LIMIT \ + | (uint32)((uint32)ADC_DEFAULT_HIGH_LIMIT << ADC_RANGE_HIGH_OFFSET)) + +#define ADC_DEFAULT_SAMPLE_TIME01_REG_CFG (ADC_DEFAULT_ACLKS_NUM \ + | (uint32)((uint32)ADC_DEFAULT_BCLKS_NUM << ADC_SAMPLE_TIME13_OFFSET)) + +#define ADC_DEFAULT_SAMPLE_TIME23_REG_CFG (ADC_DEFAULT_CCLKS_NUM \ + | (uint32)((uint32)ADC_DEFAULT_DCLKS_NUM << ADC_SAMPLE_TIME13_OFFSET)) + + +#endif /* End CY_ADC_SAR_SEQ_ADC_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_INT.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_INT.c new file mode 100644 index 0000000..5b3cc04 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_INT.c @@ -0,0 +1,78 @@ +/******************************************************************************* +* File Name: ADC_INT.c +* Version 2.50 +* +* Description: +* This file contains the code that operates during the ADC_SAR interrupt +* service routine. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC.h" +#include "cyapicallbacks.h" + + +/****************************************************************************** +* Custom Declarations and Variables +* - add user inlcude files, prototypes and variables between the following +* #START and #END tags +******************************************************************************/ +/* `#START ADC_SYS_VAR` */ + +/* `#END` */ + +#if(ADC_IRQ_REMOVE == 0u) + + + /****************************************************************************** + * Function Name: ADC_ISR + ******************************************************************************* + * + * Summary: + * Handle Interrupt Service Routine. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Reentrant: + * No. + * + ******************************************************************************/ + CY_ISR( ADC_ISR ) + { + uint32 intr_status; + + /* Read interrupt status register */ + intr_status = ADC_SAR_INTR_REG; + + #ifdef ADC_ISR_INTERRUPT_CALLBACK + ADC_ISR_InterruptCallback(); + #endif /* ADC_ISR_INTERRUPT_CALLBACK */ + + + /************************************************************************ + * Custom Code + * - add user ISR code between the following #START and #END tags + *************************************************************************/ + /* `#START MAIN_ADC_ISR` */ + + /* `#END` */ + + /* Clear handled interrupt */ + ADC_SAR_INTR_REG = intr_status; + } + +#endif /* End ADC_IRQ_REMOVE */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_IRQ.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_IRQ.c new file mode 100644 index 0000000..677a33d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_IRQ.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: ADC_IRQ.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(ADC_IRQ__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START ADC_IRQ_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: ADC_IRQ_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Start(void) +{ + /* For all we know the interrupt is active. */ + ADC_IRQ_Disable(); + + /* Set the ISR to point to the ADC_IRQ Interrupt. */ + ADC_IRQ_SetVector(&ADC_IRQ_Interrupt); + + /* Set the priority. */ + ADC_IRQ_SetPriority((uint8)ADC_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + ADC_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + ADC_IRQ_Disable(); + + /* Set the ISR to point to the ADC_IRQ Interrupt. */ + ADC_IRQ_SetVector(address); + + /* Set the priority. */ + ADC_IRQ_SetPriority((uint8)ADC_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + ADC_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Stop(void) +{ + /* Disable this interrupt. */ + ADC_IRQ_Disable(); + + /* Set the ISR to point to the passive one. */ + ADC_IRQ_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for ADC_IRQ. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(ADC_IRQ_Interrupt) +{ + #ifdef ADC_IRQ_INTERRUPT_INTERRUPT_CALLBACK + ADC_IRQ_Interrupt_InterruptCallback(); + #endif /* ADC_IRQ_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START ADC_IRQ_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling ADC_IRQ_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use ADC_IRQ_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + ADC_IRQ__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress ADC_IRQ_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + ADC_IRQ__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling ADC_IRQ_Start or ADC_IRQ_StartEx will +* override any effect this API would have had. This API should only be called +* after ADC_IRQ_Start or ADC_IRQ_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((ADC_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *ADC_IRQ_INTC_PRIOR = (*ADC_IRQ_INTC_PRIOR & (uint32)(~ADC_IRQ__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 ADC_IRQ_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((ADC_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*ADC_IRQ_INTC_PRIOR & ADC_IRQ__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Enable(void) +{ + /* Enable the general interrupt. */ + *ADC_IRQ_INTC_SET_EN = ADC_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 ADC_IRQ_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*ADC_IRQ_INTC_SET_EN & (uint32)ADC_IRQ__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Disable(void) +{ + /* Disable the general interrupt. */ + *ADC_IRQ_INTC_CLR_EN = ADC_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void ADC_IRQ_SetPending(void) +{ + *ADC_IRQ_INTC_SET_PD = ADC_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_ClearPending(void) +{ + *ADC_IRQ_INTC_CLR_PD = ADC_IRQ__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_IRQ.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_IRQ.h new file mode 100644 index 0000000..d91008a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_IRQ.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* File Name: ADC_IRQ.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_ADC_IRQ_H) +#define CY_ISR_ADC_IRQ_H + + +#include +#include + +/* Interrupt Controller API. */ +void ADC_IRQ_Start(void); +void ADC_IRQ_StartEx(cyisraddress address); +void ADC_IRQ_Stop(void); + +CY_ISR_PROTO(ADC_IRQ_Interrupt); + +void ADC_IRQ_SetVector(cyisraddress address); +cyisraddress ADC_IRQ_GetVector(void); + +void ADC_IRQ_SetPriority(uint8 priority); +uint8 ADC_IRQ_GetPriority(void); + +void ADC_IRQ_Enable(void); +uint8 ADC_IRQ_GetState(void); +void ADC_IRQ_Disable(void); + +void ADC_IRQ_SetPending(void); +void ADC_IRQ_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the ADC_IRQ ISR. */ +#define ADC_IRQ_INTC_VECTOR ((reg32 *) ADC_IRQ__INTC_VECT) + +/* Address of the ADC_IRQ ISR priority. */ +#define ADC_IRQ_INTC_PRIOR ((reg32 *) ADC_IRQ__INTC_PRIOR_REG) + +/* Priority of the ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_PRIOR_NUMBER ADC_IRQ__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_SET_EN ((reg32 *) ADC_IRQ__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_CLR_EN ((reg32 *) ADC_IRQ__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the ADC_IRQ interrupt state to pending. */ +#define ADC_IRQ_INTC_SET_PD ((reg32 *) ADC_IRQ__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_CLR_PD ((reg32 *) ADC_IRQ__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_ADC_IRQ_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_PM.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_PM.c new file mode 100644 index 0000000..b159bba --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_PM.c @@ -0,0 +1,158 @@ +/******************************************************************************* +* File Name: ADC_PM.c +* Version 2.50 +* +* Description: +* This file provides Sleep/WakeUp APIs functionality. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC.h" + + +/*************************************** +* Local data allocation +***************************************/ + +static ADC_BACKUP_STRUCT ADC_backup = +{ + ADC_DISABLED, + 0u +}; + + +/******************************************************************************* +* Function Name: ADC_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SaveConfig(void) +{ + /* All configuration registers are marked as [reset_all_retention] */ +} + + +/******************************************************************************* +* Function Name: ADC_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_RestoreConfig(void) +{ + /* All configuration registers are marked as [reset_all_retention] */ +} + + +/******************************************************************************* +* Function Name: ADC_Sleep +******************************************************************************** +* +* Summary: +* Stops the ADC operation and saves the configuration registers and component +* enable state. Should be called just prior to entering sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* ADC_backup - modified. +* +*******************************************************************************/ +void ADC_Sleep(void) +{ + /* During deepsleep/ hibernate mode keep SARMUX active, i.e. do not open + * all switches (disconnect), to be used for ADFT + */ + ADC_backup.dftRegVal = ADC_SAR_DFT_CTRL_REG & (uint32)~ADC_ADFT_OVERRIDE; + ADC_SAR_DFT_CTRL_REG |= ADC_ADFT_OVERRIDE; + if((ADC_SAR_CTRL_REG & ADC_ENABLE) != 0u) + { + if((ADC_SAR_SAMPLE_CTRL_REG & ADC_CONTINUOUS_EN) != 0u) + { + ADC_backup.enableState = ADC_ENABLED | ADC_STARTED; + } + else + { + ADC_backup.enableState = ADC_ENABLED; + } + ADC_StopConvert(); + ADC_Stop(); + + /* Disable the SAR internal pump before entering the chip low power mode */ + if((ADC_SAR_CTRL_REG & ADC_BOOSTPUMP_EN) != 0u) + { + ADC_SAR_CTRL_REG &= (uint32)~ADC_BOOSTPUMP_EN; + ADC_backup.enableState |= ADC_BOOSTPUMP_ENABLED; + } + } + else + { + ADC_backup.enableState = ADC_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: ADC_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component enable state and configuration registers. +* This should be called just after awaking from sleep mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* ADC_backup - used. +* +*******************************************************************************/ +void ADC_Wakeup(void) +{ + ADC_SAR_DFT_CTRL_REG = ADC_backup.dftRegVal; + if(ADC_backup.enableState != ADC_DISABLED) + { + /* Enable the SAR internal pump */ + if((ADC_backup.enableState & ADC_BOOSTPUMP_ENABLED) != 0u) + { + ADC_SAR_CTRL_REG |= ADC_BOOSTPUMP_EN; + } + ADC_Enable(); + if((ADC_backup.enableState & ADC_STARTED) != 0u) + { + ADC_StartConvert(); + } + } +} +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_intClock.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_intClock.c new file mode 100644 index 0000000..0ade334 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_intClock.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: ADC_intClock.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "ADC_intClock.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: ADC_intClock_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void ADC_intClock_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((ADC_intClock_CMD_REG & ADC_intClock_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + ADC_intClock_CMD_REG = + ((uint32)ADC_intClock__DIV_ID << ADC_intClock_CMD_DIV_SHIFT)| + (alignClkDiv << ADC_intClock_CMD_PA_DIV_SHIFT) | + (uint32)ADC_intClock_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: ADC_intClock_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void ADC_intClock_Start(void) +{ + /* Set the bit to enable the clock. */ + ADC_intClock_ENABLE_REG |= ADC_intClock__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: ADC_intClock_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void ADC_intClock_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((ADC_intClock_CMD_REG & ADC_intClock_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + ADC_intClock_CMD_REG = + ((uint32)ADC_intClock__DIV_ID << ADC_intClock_CMD_DIV_SHIFT)| + ((uint32)ADC_intClock_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + ADC_intClock_ENABLE_REG &= (uint32)(~ADC_intClock__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: ADC_intClock_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void ADC_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (ADC_intClock__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = ADC_intClock_DIV_REG & + (uint32)(~(uint32)(ADC_intClock_DIV_INT_MASK | ADC_intClock_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << ADC_intClock_DIV_INT_SHIFT) & ADC_intClock_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << ADC_intClock_DIV_FRAC_SHIFT) & ADC_intClock_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = ADC_intClock_DIV_REG & (uint32)(~(uint32)ADC_intClock__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* ADC_intClock__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + ADC_intClock_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: ADC_intClock_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 ADC_intClock_GetDividerRegister(void) +{ + return (uint16)((ADC_intClock_DIV_REG & ADC_intClock_DIV_INT_MASK) + >> ADC_intClock_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: ADC_intClock_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 ADC_intClock_GetFractionalDividerRegister(void) +{ +#if defined (ADC_intClock__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((ADC_intClock_DIV_REG & ADC_intClock_DIV_FRAC_MASK) + >> ADC_intClock_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* ADC_intClock__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_intClock.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_intClock.h new file mode 100644 index 0000000..1f0e651 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/ADC_intClock.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* File Name: ADC_intClock.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_ADC_intClock_H) +#define CY_CLOCK_ADC_intClock_H + +#include +#include + + +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void ADC_intClock_StartEx(uint32 alignClkDiv); +#define ADC_intClock_Start() \ + ADC_intClock_StartEx(ADC_intClock__PA_DIV_ID) + +#else + +void ADC_intClock_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void ADC_intClock_Stop(void); + +void ADC_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 ADC_intClock_GetDividerRegister(void); +uint8 ADC_intClock_GetFractionalDividerRegister(void); + +#define ADC_intClock_Enable() ADC_intClock_Start() +#define ADC_intClock_Disable() ADC_intClock_Stop() +#define ADC_intClock_SetDividerRegister(clkDivider, reset) \ + ADC_intClock_SetFractionalDividerRegister((clkDivider), 0u) +#define ADC_intClock_SetDivider(clkDivider) ADC_intClock_SetDividerRegister((clkDivider), 1u) +#define ADC_intClock_SetDividerValue(clkDivider) ADC_intClock_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define ADC_intClock_DIV_ID ADC_intClock__DIV_ID + +#define ADC_intClock_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define ADC_intClock_CTRL_REG (*(reg32 *)ADC_intClock__CTRL_REGISTER) +#define ADC_intClock_DIV_REG (*(reg32 *)ADC_intClock__DIV_REGISTER) + +#define ADC_intClock_CMD_DIV_SHIFT (0u) +#define ADC_intClock_CMD_PA_DIV_SHIFT (8u) +#define ADC_intClock_CMD_DISABLE_SHIFT (30u) +#define ADC_intClock_CMD_ENABLE_SHIFT (31u) + +#define ADC_intClock_CMD_DISABLE_MASK ((uint32)((uint32)1u << ADC_intClock_CMD_DISABLE_SHIFT)) +#define ADC_intClock_CMD_ENABLE_MASK ((uint32)((uint32)1u << ADC_intClock_CMD_ENABLE_SHIFT)) + +#define ADC_intClock_DIV_FRAC_MASK (0x000000F8u) +#define ADC_intClock_DIV_FRAC_SHIFT (3u) +#define ADC_intClock_DIV_INT_MASK (0xFFFFFF00u) +#define ADC_intClock_DIV_INT_SHIFT (8u) + +#else + +#define ADC_intClock_DIV_REG (*(reg32 *)ADC_intClock__REGISTER) +#define ADC_intClock_ENABLE_REG ADC_intClock_DIV_REG +#define ADC_intClock_DIV_FRAC_MASK ADC_intClock__FRAC_MASK +#define ADC_intClock_DIV_FRAC_SHIFT (16u) +#define ADC_intClock_DIV_INT_MASK ADC_intClock__DIVIDER_MASK +#define ADC_intClock_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_ADC_intClock_H) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0Iar.icf b/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0Iar.icf new file mode 100644 index 0000000..f45b65d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0Iar.icf @@ -0,0 +1,226 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 32768 - 1; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + 4096 - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0100; +/**** End of ICF editor section. ###ICF###*/ + + +/******** Definitions ********/ +define symbol CY_FLASH_SIZE = 32768; +define symbol CY_APPL_ORIGIN = 0; +define symbol CY_FLASH_ROW_SIZE = 128; +define symbol CY_APPL_LOADABLE = 0; +define symbol CY_APPL_LOADER = 0; +define symbol CY_APPL_NUM = 1; +define symbol CY_METADATA_SIZE = 64; +define symbol CY_APPL_MAX = 1; +define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0; +define symbol CY_APPL_FOR_STACK_AND_COPIER = 0; +define symbol CY_FIRST_AVAILABLE_META_ROW = 0; + +define symbol CYDEV_IS_IMPORTING_CODE = 0; +define symbol CYDEV_IS_EXPORTING_CODE = 0; + + + +if (!CY_APPL_LOADABLE) { + define symbol CYDEV_BTLDR_SIZE = 0; + + /* The first 0x100 Flash bytes become unavailable right after remapping of the vector table to RAM. + * This space should be used for .romvectors section. + */ + define block ROMVEC with size = 0x100 {readonly section .romvectors}; + + define block APPL with fixed order {block ROMVEC, section .psocinit, readonly}; +} else { + define block APPL with fixed order {readonly section .romvectors, section .psocinit, readonly}; +} + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, last block CSTACK}; + +define block RAMVEC with fixed order {readwrite section .ramvectors, readwrite section .bootloaderruntype}; + +if (CY_APPL_LOADABLE) +{ + define block LOADER { readonly section .cybootloader }; +} + +/* The address of the Flash row next after the Bootloader image */ +define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? + (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); + +/* The start address of Standard/Loader/Loadable#1 image */ +define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; + +/* The number of metadata records located at the end of Flash */ +define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); + +/* The application area size measured in rows */ +define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; + +/* The start address of Loadable#2 image if any */ +define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; + +/* The current image (Standard/Loader/Loadable) start address */ +define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; + +/* Define APPL region that will limit application size */ +define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; + + +/****** Initializations ******/ +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { readwrite section .ramvectors, readwrite section .bootloaderruntype }; + +/******** Placements *********/ +if (CY_APPL_LOADABLE) +{ +".cybootloader" : place at start of ROM_region {block LOADER}; +} + +"APPL" : place at start of APPL_region {block APPL}; + +"RAMVEC" : place at start of RAM_region { block RAMVEC }; +"readwrite" : place in RAM_region { readwrite }; +"HSTACK" : place at end of RAM_region { block HSTACK}; + +keep { section .cybootloader, + section .cyloadermeta, + section .cyloadablemeta, + section .cy_checksum_exclude, + section .cyflashprotect, + section .cymeta, + section .cychipprotect }; + + +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if ((CY_APPL_LOADER)&&!(CY_APPL_LOADABLE)) +{ + ".cyloadermeta" : place at address mem : (CY_FLASH_SIZE - CY_METADATA_SIZE) { readonly section .cyloadermeta }; +} +else +{ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + ".cyloadermeta" : place at address mem : (CY_FLASH_SIZE - CY_METADATA_SIZE) { readonly section .cyloadermeta }; + } + else + { + /* Must be part of the image, but beyond rom memory. */ + ".cyloadermeta" : place at address mem : 0x90700000 { readonly section .cyloadermeta }; + } +} + + + +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* General case */ + if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (CY_APPL_NUM - 1); + } + + /* Stack Project (SP) */ + if (CYDEV_IS_EXPORTING_CODE == 1) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (0); + } + + /* App for SP+L */ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (1); + } + + define symbol CYLOADABLEMETA_START_ADDR = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_METADATA_SLOT_NUM - CY_METADATA_SIZE); + + + ".cyloadablemeta" : place at address mem : CYLOADABLEMETA_START_ADDR { readonly section .cyloadablemeta }; +} + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* Align size to the flash row size */ + define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0); + + if (CY_CHECKSUM_EXCLUDE_SIZE != 0) + { + + /* General case */ + if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + { + if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + else + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + } + + + if (CY_APPL_MAX == 1) + { + /* Stack Project (SP) */ + if (CYDEV_IS_EXPORTING_CODE == 1) + { + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; + } + + /* App for SP+L */ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * 2) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + } + } + + } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */ +} +else +{ + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; +} + + +".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; +".cychipprotect" : place at address mem : 0x90600000 { readonly section .cychipprotect }; + + +/* EOF */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0RealView.scat b/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0RealView.scat new file mode 100644 index 0000000..732f8a4 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0RealView.scat @@ -0,0 +1,245 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************** +;* \file Cm0RealView.scat +;* \version 5.70 +;* +;* \brief This Linker Descriptor file describes the memory layout of the PSOC4 +;* device family. The memory layout of the final binary and hex images as well +;* as the placement in the PSOC4 memory is described. +;* +;* romvectors: Cypress default Interrupt service routine vector table. +;* +;* This is the ISR vector table at bootup. Used only for the reset vector. +;* +;* +;* ramvectors: Cypress ram interrupt service routine vector table. +;* +;* This is the ISR vector table used by the application. +;* +;******************************************************************************** +;* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;********************************************************************************/ +#include "cyfitter.h" +#include "cycodeshareimport.scat" + +#define CY_FLASH_SIZE 32768 +#define CY_APPL_ORIGIN 0 +#define CY_FLASH_ROW_SIZE 128 +#define CY_METADATA_SIZE 64 + +#define CY_APPL_FOR_STACK_AND_COPIER 0 +#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE) +#define CY_APPL_NUM 1 +#define CY_APPL_MAX 1 + + +; Define application base address +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + #if CY_APPL_ORIGIN + #define APPL1_START CY_APPL_ORIGIN + #else + #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) + #endif + + #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) + +#else + + #define APPL_START 0 + +#endif + + +; Place Bootloader at the beginning of Flash +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + CYBOOTLOADER 0 + { + .cybootloader +0 + { + * (.cybootloader) + } + } + + #if CY_APPL_ORIGIN + ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER)) + #endif + +#endif + + +APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) +{ + VECTORS +0 + { + * (.romvectors) + } + + RELOCATION +0 + { + * (.psocinit) + } + + CODE ((ImageLimit(RELOCATION) < 0x100) ? 0x100 : ImageLimit(RELOCATION)) FIXED + { + * (+RO) + } + + ISRVECTORS (0x20000000) UNINIT + { + * (.ramvectors, +FIRST) + } + + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + BTLDR_RUN +0 UNINIT + { + * (.bootloaderruntype) + } + #endif + + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + DATA +0 + { + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP (0x20000000 + 4096 - 0x0100 - 0x0400) EMPTY 0x0100 + { + } + + ARM_LIB_STACK (0x20000000 + 4096) EMPTY -0x0400 + { + } +} + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + + #if (0 != 0) + + /* General case */ + #if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + #define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #else + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + #endif + + #if (CY_APPL_MAX == 1) + + /* Stack Project (SP) */ + #if (CYDEV_IS_EXPORTING_CODE == 1) + #define CY_CHECKSUM_EXCLUDE_START (+0) + #endif + + /* App for SP+L */ + #if ((CYDEV_IS_IMPORTING_CODE == 1) && (0 == 2)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * 2) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + #endif + + CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START) + { + .cy_checksum_exclude +0 + { + * (.cy_checksum_exclude) + } + } + + #endif /* (0 != 0) */ + +#endif + + +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER || \ + CY_APPL_FOR_STACK_AND_COPIER) + + CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif + + +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* General case */ + #if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + #define CY_APPL_METADATA_SLOT_NUM (CY_APPL_NUM - 1) + #endif + + /* Stack Project (SP) */ + #if (CYDEV_IS_EXPORTING_CODE == 1) + #define CY_APPL_METADATA_SLOT_NUM (0) + #endif + + /* App for SP+L */ + #if ((CYDEV_IS_IMPORTING_CODE == 1) && (0 == 2)) + #define CY_APPL_METADATA_SLOT_NUM (1) + #endif + + #define CYLOADABLEMETA_START_ADDR (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_METADATA_SLOT_NUM - CY_METADATA_SIZE) + + CYLOADABLEMETA (CYLOADABLEMETA_START_ADDR) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } +#endif + +CYFLASHPROTECT 0x90400000 +{ + .cyflashprotect +0 { * (.cyflashprotect) } +} + +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +CYCHIPPROTECT 0x90600000 +{ + .cychipprotect +0 { * (.cychipprotect) } +} + + +/******************************************************************************* +* Bootloader Metadata Section. Must be part of the image, but beyond rom memory. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) && \ + !(CY_APPL_FOR_STACK_AND_COPIER)) + + CYLOADERMETA +0 + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0Start.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0Start.c new file mode 100644 index 0000000..e3d9780 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/Cm0Start.c @@ -0,0 +1,545 @@ +/***************************************************************************//** +* \file Cm0Start.c +* \version 5.70 +* +* \brief Startup code for the ARM CM0. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "cyfitter.h" +#include "cyapicallbacks.h" + +#define CY_NUM_VECTORS (CY_INT_IRQ_BASE + CY_NUM_INTERRUPTS) + +#if (CY_IP_CPUSS_CM0) + #define CY_CPUSS_CONFIG_VECT_IN_RAM (( uint32 ) 0x01) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#if (CY_IP_CPUSS_CM0) + /* CPUSS Configuration register */ + #define CY_CPUSS_CONFIG_REG (*(reg32 *) CYREG_CPUSS_CONFIG) + #define CY_CPUSS_CONFIG_PTR ( (reg32 *) CYREG_CPUSS_CONFIG) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#if defined (__ICCARM__) + #define CY_NUM_ROM_VECTORS (CY_NUM_VECTORS) +#else + #define CY_NUM_ROM_VECTORS (4u) +#endif /* defined (__ICCARM__) */ + +/* Vector table address in SRAM */ +#define CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM (0x20000000u) + +#ifndef CY_SYS_INITIAL_STACK_POINTER + + #if defined(__ARMCC_VERSION) + #define CY_SYS_INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) + #elif defined (__GNUC__) + #define CY_SYS_INITIAL_STACK_POINTER (&__cy_stack) + #elif defined (__ICCARM__) + #pragma language=extended + #pragma segment="CSTACK" + #define CY_SYS_INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + + extern void __iar_program_start( void ); + extern void __iar_data_init3 (void); + #endif /* (__ARMCC_VERSION) */ + +#endif /* CY_SYS_INITIAL_STACK_POINTER */ + + +#if defined(__GNUC__) + #include + extern int end; +#endif /* defined(__GNUC__) */ + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +#if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + + /******************************************************************************* + This variable is used by the Bootloader/Bootloadable components to schedule + what application will be started after a software reset. + *******************************************************************************/ + #if (__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* (__ARMCC_VERSION) */ + volatile uint32 cyBtldrRunType; + +#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + + +/******************************************************************************* +* Function Name: IntDefaultHandler +****************************************************************************//** +* +* This function is called for all interrupts, other than a reset that is called +* before the system is setup. +* +*******************************************************************************/ +CY_NORETURN +CY_ISR(IntDefaultHandler) +{ + /*************************************************************************** + * We must not get here. If we do, a serious problem occurs, so go into + * an infinite loop. + ***************************************************************************/ + + #if defined(__GNUC__) + if (errno == ENOMEM) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK + CyBoot_IntDefaultHandler_Enomem_Exception_Callback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */ + + while(1) + { + /* Out Of Heap Space + * This can be increased in the System tab of the Design Wide Resources. + */ + } + } + else + #endif + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + + } + } +} + +#if defined(__ARMCC_VERSION) + +/* Local function for device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +/* Linker-generated Stack Base addresses, Two Region and One Region */ +extern unsigned long Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the MDK toolchains. +* This is the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + /* The bootloadable application image is started at Reset() handler + * as a result of a branch instruction execution from the bootloader. + * So, the stack pointer needs to be reset to be sure that + * there is no garbage in the stack. + */ + register uint32_t msp __asm("msp"); + msp = (uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit; + #endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + __main(); +} + +/******************************************************************************* +* Function Name: $Sub$$main +****************************************************************************//** +* +* This function is called immediately before the users main +* +*******************************************************************************/ +__attribute__ ((noreturn, __noinline__)) +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* The static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* System Calls of the Red Hat newlib C Library +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: _exit +****************************************************************************//** +* +* Exit a program without cleaning up files. If your system doesn't provide +* this, it is best to avoid linking with subroutines that require it (exit, +* system). +* +* \param status: Status caused program exit. +* +*******************************************************************************/ +__attribute__((weak)) +void _exit(int status) +{ + CyHalt((uint8) status); + + while(1) + { + + } +} + + +/******************************************************************************* +* Function Name: _sbrk +****************************************************************************//** +* +* Increase program data space. As malloc and related functions depend on this, +* it is useful to have a working implementation. The following suffices for a +* standalone system; it exploits the symbol end automatically defined by the +* GNU linker. +* +* \param nbytes: The number of bytes requested (if the parameter value is positive) +* from the heap or returned back to the heap (if the parameter value is +* negative). +* +*******************************************************************************/ +__attribute__((weak)) +void * _sbrk (int nbytes) +{ + extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */ + void * returnValue; + + /* The statically held previous end of the heap, with its initialization. */ + static uint8 *heapPointer = (uint8 *) &end; /* Previous end */ + + if (((heapPointer + nbytes) - (uint8 *) &end) <= CYDEV_HEAP_SIZE) + { + returnValue = (void *) heapPointer; + heapPointer += nbytes; + } + else + { + errno = ENOMEM; + returnValue = (void *) -1; + } + + return (returnValue); +} + + +/******************************************************************************* +* Function Name: Start_c +****************************************************************************//** +* +* This function handles initializing the .data and .bss sections in +* preparation for running the standard c code. Once initialization is complete +* it will call main(). This function will never return. +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn, noinline)); +void Start_c(void) +{ + #ifdef CY_BOOT_START_C_CALLBACK + CyBoot_Start_c_Callback(); + #else + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num; regions != 0u; regions--) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = *src; + dst++; + src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = 0u; + dst++; + } + + rptr++; + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } + + #endif /* CY_BOOT_START_C_CALLBACK */ +} + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the GCC toolchain. This is +* the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* The bootloadable application image is started at Reset() handler + * as a result of a branch instruction execution from the bootloader. + * So, the stack pointer needs to be reset to be sure that + * there is no garbage in the stack. + */ + __asm volatile ("MSR msp, %0\n" : : "r" ((uint32)&__cy_stack) : "sp"); + #endif /* CYDEV_PROJ_TYPE_LOADABLE */ + + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + Start_c(); +} + +#elif defined (__ICCARM__) + + +/******************************************************************************* +* Function Name: __low_level_init +****************************************************************************//** +* +* This function performs early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of reset interrupt handler +* before the data sections are initialized. +* +* \return The value that determines whether or not data sections should be +* initialized by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +#pragma inline = never +int __low_level_init(void) +{ + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + +#if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); +#endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* Ram Interrupt Vector table storage area. Must be placed at 0x20000000. +*******************************************************************************/ + +#if defined (__ICCARM__) + #pragma location=".ramvectors" +#elif defined (__ARMCC_VERSION) + #ifndef CY_SYS_RAM_VECTOR_SECTION + #define CY_SYS_RAM_VECTOR_SECTION __attribute__((section(".ramvectors"), zero_init)) + #endif /* CY_SYS_RAM_VECTOR_SECTION */ + CY_SYS_RAM_VECTOR_SECTION +#else + #ifndef CY_SYS_RAM_VECTOR_SECTION + #define CY_SYS_RAM_VECTOR_SECTION CY_SECTION(".ramvectors") + #endif /* CY_SYS_RAM_VECTOR_SECTION */ + CY_SYS_RAM_VECTOR_SECTION +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Rom Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ + +#if defined(__ARMCC_VERSION) + /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + #pragma diag_suppress 1296 +#endif /* defined(__ARMCC_VERSION) */ + +#if defined (__ICCARM__) + #pragma location=".romvectors" + const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = +#else + #ifndef CY_SYS_ROM_VECTOR_SECTION + #define CY_SYS_ROM_VECTOR_SECTION CY_SECTION(".romvectors") + #endif /* CY_SYS_ROM_VECTOR_SECTION */ + CY_SYS_ROM_VECTOR_SECTION + const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = +#endif /* defined (__ICCARM__) */ +{ + CY_SYS_INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #if defined (__ICCARM__) /* The reset handler 1 */ + __iar_program_start, + #else + (cyisraddress)&Reset, + #endif /* defined (__ICCARM__) */ + &IntDefaultHandler, /* The NMI handler 2 */ + &IntDefaultHandler, /* The hard fault handler 3 */ +}; + +#if defined(__ARMCC_VERSION) + #pragma diag_default 1296 +#endif /* defined(__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: initialize_psoc +****************************************************************************//** +* +* This function is used to initialize the PSoC chip before calling main. +* +*******************************************************************************/ +#if(defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif /* (defined(__GNUC__) && !defined(__ARMCC_VERSION)) */ +void initialize_psoc(void) +{ + uint32 indexInit; + + #if(CY_IP_CPUSSV2) + #if (CY_IP_CPUSS_CM0) + /*********************************************************************** + * Make sure that Vector Table is located at 0000_0000 in Flash, before + * accessing RomVectors or calling functions that may be placed in + * .psocinit (cyfitter_cfg and ClockSetup). Note The CY_CPUSS_CONFIG_REG + * register is retention for the specified device family. + ***********************************************************************/ + CY_CPUSS_CONFIG_REG &= (uint32) ~CY_CPUSS_CONFIG_VECT_IN_RAM; + #endif /* (CY_IP_CPUSS_CM0) */ + #endif /* (CY_IP_CPUSSV2) */ + + /* Set Ram interrupt vectors to default functions. */ + for (indexInit = 0u; indexInit < CY_NUM_VECTORS; indexInit++) + { + CyRamVectors[indexInit] = (indexInit < CY_NUM_ROM_VECTORS) ? + #if defined (__ICCARM__) + __vector_table[indexInit].__fun : &IntDefaultHandler; + #else + RomVectors[indexInit] : &IntDefaultHandler; + #endif /* defined (__ICCARM__) */ + } + + /* Initialize configuration registers. */ + cyfitter_cfg(); + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ + + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + + /* Need to make sure that this variable will not be optimized out */ + if (0u == cyBtldrRunType) + { + cyBtldrRunType = 0u; + } + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + + #if (CY_IP_CPUSS_CM0) + /* Vector Table is located at 0x2000:0000 in SRAM */ + CY_CPUSS_CONFIG_REG |= CY_CPUSS_CONFIG_VECT_IN_RAM; + #else + (*(uint32 *)CYREG_CM0P_VTOR) = CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM; + #endif /* (CY_IP_CPUSS_CM0) */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmGnu.s b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmGnu.s new file mode 100644 index 0000000..b4dd111 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmGnu.s @@ -0,0 +1,140 @@ +/***************************************************************************//** +* \file CyBootAsmGnu.s +* \version 5.70 +* +* \brief Assembly routines for GNU as. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.syntax unified +.text +.thumb +.include "cyfittergnu.inc" + + +/******************************************************************************* +* Function Name: CyDelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32 cycles: number of cycles to delay. +* +* \return +* None +* +*******************************************************************************/ +/* void CyDelayCycles(uint32 cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global CyDelayCycles +.func CyDelayCycles, CyDelayCycles +.type CyDelayCycles, %function +.thumb_func +CyDelayCycles: /* cycles bytes */ + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ +.IFDEF CYIPBLOCK_m0s8cpuss_VERSION + NOP /* 1 2 Loop alignment padding */ +.ELSE + .IFDEF CYIPBLOCK_s8srsslt_VERSION + .IFDEF CYIPBLOCK_m0s8cpussv2_VERSION + .IFDEF CYIPBLOCK_mxusbpd_VERSION + /* Do nothing */ + .ELSE + .IFDEF CYIPBLOCK_m0s8usbpd_VERSION + /* Do nothing */ + .ELSE + NOP /* 1 2 Loop alignment padding */ + .ENDIF + .ENDIF + .ENDIF + .ENDIF + /* Leave loop unaligned */ +.ENDIF +CyDelayCycles_loop: +/* For CM0+ branch instruction takes 2 CPU cycles, for CM0 it takes 3 cycles */ +.IFDEF CYDEV_CM0P_BASE + ADDS r0, r0, #1 /* 1 2 Increment counter */ + SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + BNE CyDelayCycles_loop /* 2 2 2 CPU cycles (if branche is taken)*/ + NOP /* 1 2 Loop alignment padding */ +.ELSE + SUBS r0, r0, #1 /* 1 2 Decrement counter */ + BNE CyDelayCycles_loop /* 3 2 3 CPU cycles (if branche is taken)*/ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ +.ENDIF +CyDelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ +.endfunc + + +/******************************************************************************* +* Function Name: CyEnterCriticalSection +****************************************************************************//** +* +* CyEnterCriticalSection disables interrupts and returns a value indicating +* whether interrupts were previously enabled (the actual value depends on +* whether the device is PSoC 3 or PSoC 5). +* +* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +* with interrupts still enabled. The test and set of the interrupt bits is not +* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +* corrupting processor state, it must be the policy that all interrupt routines +* restore the interrupt enable bits as they were found on entry. +* +* \return +* uint8 +* Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8 CyEnterCriticalSection(void) */ +.global CyEnterCriticalSection +.func CyEnterCriticalSection, CyEnterCriticalSection +.type CyEnterCriticalSection, %function +.thumb_func +CyEnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: CyExitCriticalSection +****************************************************************************//** +* +* CyExitCriticalSection re-enables interrupts if they were enabled before +* CyEnterCriticalSection was called. The argument should be the value returned +* from CyEnterCriticalSection. +* +* \param uint8 savedIntrStatus: +* Saved interrupt status returned by the CyEnterCriticalSection function. +* +* \return +* None +* +*******************************************************************************/ +/* void CyExitCriticalSection(uint8 savedIntrStatus) */ +.global CyExitCriticalSection +.func CyExitCriticalSection, CyExitCriticalSection +.type CyExitCriticalSection, %function +.thumb_func +CyExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmIar.s b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmIar.s new file mode 100644 index 0000000..81aa2af --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmIar.s @@ -0,0 +1,132 @@ +;------------------------------------------------------------------------------- +; \file CyBootAsmIar.s +; \version 5.70 +; +; \brief Assembly routines for IAR Embedded Workbench IDE. +; +;------------------------------------------------------------------------------- +; Copyright 2013-2018, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + SECTION .text:CODE:ROOT(4) + PUBLIC CyDelayCycles + PUBLIC CyEnterCriticalSection + PUBLIC CyExitCriticalSection + THUMB + INCLUDE cyfitter.h + + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + +CyDelayCycles: + ADDS r0, r0, #2 + LSRS r0, r0, #2 + BEQ CyDelayCycles_done + #ifdef CYIPBLOCK_m0s8cpuss_VERSION + NOP ; 1 2 Loop alignment padding + #else + #ifdef CYIPBLOCK_s8srsslt_VERSION + #ifdef CYIPBLOCK_m0s8cpussv2_VERSION + #ifdef CYIPBLOCK_mxusbpd_VERSION + /* Do nothing */ + #else + #ifdef CYIPBLOCK_m0s8usbpd_VERSION + /* Do nothing */ + #else + NOP ; 1 2 Loop alignment padding + #endif + #endif + #endif + #endif + ;Leave loop unaligned + #endif +CyDelayCycles_loop: + #ifdef CYDEV_CM0P_BASE + ADDS r0, r0, #1 + SUBS r0, r0, #2 + BNE CyDelayCycles_loop + NOP + #else + SUBS r0, r0, #1 + BNE CyDelayCycles_loop + NOP + NOP + #endif +CyDelayCycles_done: + BX lr + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled. +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic. Therefore, to avoid corrupting processor state, it must be the policy +; that all interrupt routines restore the interrupt enable bits as they were +; found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) + +CyEnterCriticalSection: + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) + +CyExitCriticalSection: + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + + END + +;Undefine temporary defines +#undef CYIPBLOCK_m0s8cpussv2_VERSION +#undef CYIPBLOCK_m0s8srssv2_VERSION diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmRv.s b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmRv.s new file mode 100644 index 0000000..a1396f0 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyBootAsmRv.s @@ -0,0 +1,136 @@ +;------------------------------------------------------------------------------- +; \file CyBootAsmRv.s +; \version 5.70 +; +; \brief Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + INCLUDE cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + IF :DEF: CYIPBLOCK_m0s8cpuss_VERSION + NOP ; 1 2 Loop alignment padding + ELSE + IF :DEF: CYIPBLOCK_s8srsslt_VERSION + IF :DEF: CYIPBLOCK_m0s8cpussv2_VERSION + IF :DEF: CYIPBLOCK_mxusbpd_VERSION + ; Do nothing + ELSE + IF :DEF: CYIPBLOCK_m0s8usbpd_VERSION + ; Do nothing + ELSE + NOP ; 1 2 Loop alignment padding + ENDIF + ENDIF + ENDIF + ENDIF + ;Leave loop unaligned + ENDIF +CyDelayCycles_loop + ; For CM0+ branch instruction takes 2 CPU cycles, for CM0 it takes 3 cycles + IF :DEF: CYDEV_CM0P_BASE + ADDS r0, r0, #1 ; 1 2 Increment counter + SUBS r0, r0, #2 ; 1 2 Decrement counter by 2 + BNE CyDelayCycles_loop ; 2 2 2 CPU cycles (if branche is taken) + NOP ; 1 2 Loop alignment padding + ELSE + SUBS r0, r0, #1 ; 1 2 Decrement counter + BNE CyDelayCycles_loop ; 3 2 3 CPU cycles (if branche is taken) + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + ENDIF +CyDelayCycles_done + BX lr ; 3 2 + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyFlash.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyFlash.c new file mode 100644 index 0000000..2a1f2ad --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyFlash.c @@ -0,0 +1,803 @@ +/***************************************************************************//** +* \file CyFlash.c +* \version 5.70 +* +* \brief Provides an API for the FLASH. +* +* \note This code is endian agnostic. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + + +/******************************************************************************* +* Cypress identified a defect with the Flash write functionality of the +* PSoC 4000, PSoC 4000U, PSoC 4100, and PSoC 4200 devices. The +* CySysFlashWriteRow() function now checks the data to be written and, if +* necessary, modifies it to have a non-zero checksum. After writing to Flash, +* the modified data is replaced (Flash program) with +* the correct (original) data. +*******************************************************************************/ +#define CY_FLASH_CHECKSUM_WORKAROUND (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + +#if (CY_IP_FM || ((!CY_PSOC4_4000) && CY_IP_SPCIF_SYNCHRONOUS) || (!CY_IP_FM) && CY_PSOC4_4000) + static CY_SYS_FLASH_CLOCK_BACKUP_STRUCT cySysFlashBackup; +#endif /* (CY_IP_FM || ((!CY_PSOC4_4000) && CY_IP_SPCIF_SYNCHRONOUS) || (!CY_IP_FM) && CY_PSOC4_4000) */ + +static cystatus CySysFlashClockBackup(void); +static cystatus CySysFlashClockRestore(void); +#if(CY_IP_SPCIF_SYNCHRONOUS) + static cystatus CySysFlashClockConfig(void); +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + +/******************************************************************************* +* Function Name: CySysFlashWriteRow +****************************************************************************//** +* +* Erases a row of Flash and programs it with the new data. +* +* The IMO must be enabled before calling this function. The operation of the +* flash writing hardware is dependent on the IMO. +* +* For PSoC 4000, PSoC 4100 BLE and PSoC 4200 BLE devices (PSoC 4100 BLE and +* PSoC 4200 BLE devices with 256K of Flash memory are not affected), this API +* will automatically modify the clock settings for the device. Writing to +* flash requires that changes be made to the IMO and HFCLK settings. The +* configuration is restored before returning. This will impact the operation +* of most of the hardware in the device. +* +* For PSoC 4000 devices this API will automatically modify the clock settings +* for the device. Writing to flash requires that changes be made to the IMO +* and HFCLK settings. The configuration is restored before returning. HFCLK +* will have several frequency changes during the operation of this API between +* a minimum frequency of the current IMO frequency divided by 8 and a maximum +* frequency of 12 MHz. This will impact the operation of most of the hardware +* in the device. +* +* \param rowNum The flash row number. The number of the flash rows is defined by +* the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. Refer to the +* device datasheet for the details. +* \note The target flash array is calculated based on the specified flash row. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_FLASH_SIZEOF_ROW macro. Refer to the device datasheet for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashWriteRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA) / sizeof(uint32)]; + uint8 interruptState; + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + uint32 needChecksumWorkaround = 0u; + uint32 savedIndex = 0u; + uint32 savedValue = 0u; + uint32 checksum = 0u; + uint32 bits = 0u; + uint32 i; + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + if ((rowNum < CY_FLASH_NUMBER_ROWS) && (rowData != 0u)) + { + /* Copy data to be written into internal variable */ + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + + for (i = 2u; i < ((CY_FLASH_SIZEOF_ROW / sizeof(uint32)) + 2u); i++) + { + uint32 tmp = parameters[i]; + if (tmp != 0u) + { + checksum += tmp; + bits |= tmp; + savedIndex = i; + } + } + + needChecksumWorkaround = ((checksum == 0u) && (bits != 0u)) ? 1u : 0u; + if (needChecksumWorkaround != 0u) + { + savedValue = parameters[savedIndex]; + parameters[savedIndex] = 0u; + } + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + clkCnfRetValue = CySysFlashClockBackup(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Write Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_WRITE_ROW) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_WRITE_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + + if ((retValue == CYRET_SUCCESS) && (needChecksumWorkaround != 0u)) + { + (void)memset((void *)¶meters[2u], 0, CY_FLASH_SIZEOF_ROW); + parameters[savedIndex] = savedValue; + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Program Row */ + parameters[0u] = + (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_PROGRAM_ROW) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_PROGRAM_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + } + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + clkCnfRetValue = CySysFlashClockRestore(); + + if(clkCnfRetValue != CY_SYS_FLASH_SUCCESS) + { + retValue = clkCnfRetValue; + } + } + + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} + + + +#if (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) +/******************************************************************************* +* Function Name: CySysFlashStartWriteRow +****************************************************************************//** +* +* Initiates a write to a row of Flash. A call to this API is non-blocking. +* Use CySysFlashResumeWriteRow() to resume flash writes and +* CySysFlashGetWriteRowStatus() to ascertain status of the write operation. +* +* The devices require HFCLK to be sourced by 48 MHz IMO during flash write. +* This API will modify IMO configuration; it can be later restored to original +* configuration by calling \ref CySysFlashGetWriteRowStatus(). +* +* \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API +* is complete. The CPUSS_SYSARG register will be reflecting the SRAM address +* during an ongoing non-blocking operation. +* +* \param rowNum The flash row number. The number of the flash rows is defined by +* the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. Refer to the +* device datasheet for the details. +* \note The target flash array is calculated based on the specified flash row. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_FLASH_SIZEOF_ROW macro. Refer to the device datasheet for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashStartWriteRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA) / sizeof(uint32)]; + uint8 interruptState; + +#if(CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if ((rowNum < CY_FLASH_NUMBER_ROWS) && (rowData != 0u)) + { + /* Copy data to be written into internal variable */ + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + clkCnfRetValue = CySysFlashClockBackup(); + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #else + (void)CySysFlashClockBackup(); + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Non-blocking Write Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} + + +/******************************************************************************* +* Function Name: CySysFlashGetWriteRowStatus +****************************************************************************//** +* +* Returns the current status of the flash write operation. +* +** \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API +* is complete. The CPUSS_SYSARG register will be reflecting the SRAM address +* during an ongoing non-blocking operation. +* Calling this API before starting a non-blocking write row operation +* using the \ref CySysFlashStartWriteRow() API will cause improper operation. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashGetWriteRowStatus(void) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + (void) CySysFlashClockRestore(); + + return (retValue); +} + + +/******************************************************************************* +* Function Name: CySysFlashResumeWriteRow +****************************************************************************//** +* +* This API must be called, once the SPC interrupt is triggered to complete the +* non-blocking operation. It is advised not to prolong calling this API for +* more than 25 ms. +* +* The non-blocking write row API \ref CySysFlashStartWriteRow() requires that +* this API be called 3 times to complete the write. This can be done by +* configuring SPCIF interrupt and placing a call to this API. +* +* For CM0 based device, a non-blocking call to program a row of macro 0 +* requires the user to set the CPUSS_CONFIG.VECS_IN_RAM bit so that the +* interrupt vector for the SPC is fetched from the SRAM rather than the FLASH. +* +* For CM0+ based device, if the user wants to keep the vector table in flash +* when performing non-blocking flash write then they need to make sure the +* vector table is placed in the flash macro which is not getting programmed by +* configuring the VTOR register. +* +* \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last Resume API is complete. +* The CPUSS_SYSARG register will be reflecting the SRAM address during an +* ongoing non-blocking operation. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashResumeWriteRow(void) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + static volatile uint32 parameters[1u]; + + /* Resume */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING; + + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + return (retValue); +} + +#endif /* (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) */ + + +/******************************************************************************* +* Function Name: CySysFlashSetWaitCycles +****************************************************************************//** +* +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from Flash. This function must be called before increasing the +* SYSCLK clock frequency. It can optionally be called after lowering SYSCLK +* clock frequency in order to improve the CPU performance. +* +* \param freq The System clock frequency in MHz. +* +* \note Invalid frequency will be ignored in Release mode and the CPU will be +* halted if project is compiled in Debug mode. +* +*******************************************************************************/ +void CySysFlashSetWaitCycles(uint32 freq) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_CPUSS) + + if ( freq <= CY_FLASH_SYSCLK_BOUNDARY_MHZ ) + { + CY_SYS_CLK_SELECT_REG &= (uint32)(~CY_FLASH_WAIT_STATE_EN); + } + else + { + CY_SYS_CLK_SELECT_REG |= CY_FLASH_WAIT_STATE_EN; + } + #else + #if (CY_IP_CPUSS_FLASHC_PRESENT) + /* CY_IP_FM and CY_IP_FS */ + if (freq <= CY_FLASH_CTL_WS_0_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_0_VALUE; + } else + if (freq <= CY_FLASH_CTL_WS_1_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_1_VALUE; + } else + #if (CY_IP_FMLT || CY_IP_FSLT) + if (freq <= CY_FLASH_CTL_WS_2_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_2_VALUE; + } + else + #endif /* (CY_IP_FMLT || CY_IP_FSLT) */ + #endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + { + /* Halt CPU in debug mode if frequency is invalid */ + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_CPUSS) */ + + CyExitCriticalSection(interruptState); +} + + +#if (CY_SFLASH_XTRA_ROWS) +/******************************************************************************* +* Function Name: CySysSFlashWriteUserRow +****************************************************************************//** +* +* Writes data to a row of SFlash user configurable area. +* +* This API is applicable for PSoC 4100 BLE, PSoC 4200 BLE, PSoC 4100M, +* PSoC 4200M, and PSoC 4200L family of devices. +* +* \param rowNum The flash row number. The flash row number. The number of the +* flash rows is defined by the CY_SFLASH_NUMBER_USERROWS macro for the selected +* device. Valid range is 0-3. Refer to the device TRM for details. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_SFLASH_SIZEOF_USERROW macro. Refer to the device TRM for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysSFlashWriteUserRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA)/4u]; + uint8 interruptState; + + + if ((rowNum < CY_SFLASH_NUMBER_USERROWS) && (rowData != 0u)) + { + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + clkCnfRetValue = CySysFlashClockBackup(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Write User Sflash Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) rowNum; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + clkCnfRetValue = CySysFlashClockRestore(); + } + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} +#endif /* (CY_SFLASH_XTRA_ROWS) */ + + +/******************************************************************************* +* Function Name: CySysFlashClockBackup +****************************************************************************//** +* +* Backups the device clock configuration. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockBackup(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; +#if(!CY_IP_FM) + #if !(CY_PSOC4_4000) + #if (CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 parameters[2u]; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + #endif /* !(CY_PSOC4_4000) */ +#endif /* (!CY_IP_FM) */ + +#if(CY_IP_FM) + + /*************************************************************** + * Preserve IMO configuration that could be changed during + * system call execution (Cypress ID #150448). + ***************************************************************/ + cySysFlashBackup.imoConfigReg = CY_SYS_CLK_IMO_CONFIG_REG; + +#else /* (CY_IP_FMLT) */ + + #if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings backup for the PSOC4 4000 devices (the + * corresponding system call is not available). + ***************************************************************************/ + + /*************************************************************************** + * The registers listed below are modified by CySysFlashClockConfig(). + * + * The registers to be saved: + * - CY_SYS_CLK_IMO_CONFIG_REG - IMO enable state. + * - CY_SYS_CLK_SELECT_REG - HFCLK source, divider, pump source. Save + * entire register as it can be directly + * written on restore (no special + * requirements). + * - CY_SYS_CLK_IMO_SELECT_REG - Save IMO frequency. + * + * The registers not to be saved: + * - CY_SYS_CLK_IMO_TRIM1_REG - No need to save. Function of frequency. + * Restored by CySysClkWriteImoFreq(). + * - CY_SYS_CLK_IMO_TRIM3_REG - No need to save. Function of frequency. + * Restored by CySysClkWriteImoFreq(). + * - REG_CPUSS_FLASH_CTL - Flash wait cycles. Unmodified due to system + * clock 16 MHz limit. + ***************************************************************************/ + + cySysFlashBackup.clkSelectReg = CY_SYS_CLK_SELECT_REG; + cySysFlashBackup.clkImoEna = CY_SYS_CLK_IMO_CONFIG_REG & CY_SYS_CLK_IMO_CONFIG_ENABLE; + cySysFlashBackup.clkImoFreq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ + (CY_SYS_CLK_IMO_SELECT_REG << 2u); + + #else + + #if (CY_IP_SPCIF_SYNCHRONOUS) + /* FM-Lite Clock Backup System Call */ + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_BACKUP) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_BACKUP; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ + + return (retValue); +} + + +#if(CY_IP_SPCIF_SYNCHRONOUS) +/******************************************************************************* +* Function Name: CySysFlashClockConfig +****************************************************************************//** +* +* Configures the device clocks for the flash writing. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockConfig(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; + + /*************************************************************************** + * The FM-Lite IP uses the IMO at 48MHz for the pump clock and SPC timer + * clock. The PUMP_SEL and HF clock must be set to IMO before calling Flash + * write or erase operation. + ***************************************************************************/ +#if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings setup for the PSOC4 4000 devices (the + * corresponding system call is not reliable): + * - The IMO frequency should be 48 MHz + * - The IMO should be source for the HFCLK + * - The IMO should be the source for the charge pump clock + * + * Note The structure members used below are initialized by + * the CySysFlashClockBackup() function. + ***************************************************************************/ + if ((cySysFlashBackup.clkImoFreq != 48u) || + ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCLK_IMO) || + (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELECT_PUMP_SEL_MASK) != + CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + { + /*********************************************************************** + Set HFCLK divider to divide-by-4 to ensure that System clock frequency + * is within the valid limit (16 MHz for the PSoC4 4000). + ***********************************************************************/ + CySysClkWriteHfclkDiv(CY_SYS_CLK_HFCLK_DIV_4); + + /* The IMO frequency should be 48 MHz */ + if (cySysFlashBackup.clkImoFreq != 48u) + { + CySysClkWriteImoFreq(48u); + } + CySysClkImoStart(); + + /* The IMO should be source for the HFCLK */ + CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO); + + /* The IMO should be the source for the charge pump clock */ + CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & + ((uint32)~(uint32)(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT))) | + ((uint32)((uint32)1u << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT)); + } + +#else + + /* FM-Lite Clock Configuration */ + CY_FLASH_CPUSS_SYSARG_REG = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_CONFIG) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_CONFIG; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + +#endif /* (CY_PSOC4_4000) */ + + return (retValue); +} +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + +/******************************************************************************* +* Function Name: CySysFlashClockRestore +****************************************************************************//** +* +* Restores the device clock configuration. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockRestore(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; +#if(!CY_IP_FM) + #if !(CY_PSOC4_4000) + #if (CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 parameters[2u]; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + #endif /* !(CY_PSOC4_4000) */ +#endif /* (!CY_IP_FM) */ + +#if(CY_IP_FM) + + /*************************************************************** + * Restore IMO configuration that could be changed during + * system call execution (Cypress ID #150448). + ***************************************************************/ + CY_SYS_CLK_IMO_CONFIG_REG = cySysFlashBackup.imoConfigReg; + +#else + + #if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings restore for the PSOC4 4000 devices (the + * corresponding system call is not available). + ***************************************************************************/ + + /* Restore clock settings */ + if ((cySysFlashBackup.clkImoFreq != 48u) || + ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCLK_IMO) || + (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELECT_PUMP_SEL_MASK) != + CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + { + /* Restore IMO frequency if needed */ + if (cySysFlashBackup.clkImoFreq != 48u) + { + CySysClkWriteImoFreq(cySysFlashBackup.clkImoFreq); + } + + /* Restore HFCLK clock source */ + CySysClkWriteHfclkDirect(cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + + /* Restore HFCLK divider and source for pump */ + CY_SYS_CLK_SELECT_REG = cySysFlashBackup.clkSelectReg; + + /* Stop IMO if needed */ + if (0u == cySysFlashBackup.clkImoEna) + { + CySysClkImoStop(); + } + } + + #else + + #if (CY_IP_SPCIF_SYNCHRONOUS) + /* FM-Lite Clock Restore */ + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ + + return (retValue); +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyFlash.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyFlash.h new file mode 100644 index 0000000..0ea8ecf --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyFlash.h @@ -0,0 +1,293 @@ +/***************************************************************************//** +* \file CyFlash.h +* \version 5.70 +* +* \brief Provides the function definitions for the FLASH. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "CyLib.h" + +/** +* \addtogroup group_flash + +\brief Flash memory in PSoC devices provides nonvolatile storage for user +firmware, user configuration data, and bulk data storage. See the device +datasheet and TRM for more information on Flash architecture. + +\section section_flash_protection Flash Protection +PSoC devices include a flexible flash-protection model that prevents access +and visibility to on-chip flash memory. The device offers the ability to +assign one of two protection levels to each row of flash: unprotected and +full protection. The required protection level can be selected using the Flash +Security tab of the PSoC Creator DWR file. Flash protection levels can only be +changed by performing a complete flash erase. The Flash programming APIs will +fail to write a row with Full Protection level. For more information on +protection model, refer to the Flash Security Editor section in the PSoC +Creator Help. + +\section section_flash_working_with Working with Flash +Flash programming operations are implemented as system calls. System calls are +executed out of SROM in the privileged mode of operation. Users have no access +to read or modify the SROM code. The CPU requests the system call by writing +the function opcode and parameters to the System Performance Controller (SPC) +input registers, and then requesting the SROM to execute the function. Based +on the function opcode, the SPC executes the corresponding system call from +SROM and updates the SPC status register. The CPU should read this status +register for the pass/fail result of the function execution. As part of +function execution, the code in SROM interacts with the SPC interface to do +the actual flash programming operations. + +It can take as many as 20 milliseconds to write to flash. During this time, +the device should not be reset, or unexpected changes may be made to portions +of the flash. Reset sources include XRES pin, software reset, and watchdog. +Make sure that these are not inadvertently activated. Also, the low voltage +detect circuits should be configured to generate an interrupt instead of a +reset. + +The flash can be read either by the cache controller or the SPC. Flash write +can be performed only by the SPC. Both the SPC and cache cannot simultaneously +access flash memory. If the cache controller tries to access flash at the same +time as the SPC, then it must wait until the SPC completes its flash access +operation. The CPU, which accesses the flash memory through the cache +controller, is therefore also stalled in this circumstance. If a CPU code +fetch has to be done from flash memory due to a cache miss condition, then the +cache would have to wait until the SPC completes the flash write operation. +Thus the CPU code execution will also be halted till the flash write is +complete. Flash is directly mapped into memory space and can be read directly. + +\note Flash write operations on PSoC 4000 devices modify the clock settings of +the device during the period of the write operation. +Refer to the \ref CySysFlashWriteRow() API documentation for details. + +* @{ +*/ + +uint32 CySysFlashWriteRow (uint32 rowNum, const uint8 rowData[]); +#if (CY_SFLASH_XTRA_ROWS) + uint32 CySysSFlashWriteUserRow (uint32 rowNum, const uint8 rowData[]); +#endif /* (CY_SFLASH_XTRA_ROWS) */ +void CySysFlashSetWaitCycles (uint32 freq); + +#if (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) + uint32 CySysFlashStartWriteRow(uint32 rowNum, const uint8 rowData[]); + uint32 CySysFlashGetWriteRowStatus(void); + uint32 CySysFlashResumeWriteRow(void); +#endif /* (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) */ + +/** @} group_flash */ + + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) /**< The base pointer of the Flash memory.*/ +#define CY_FLASH_SIZE (CYDEV_FLASH_SIZE) /**< The size of the Flash memory. */ +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE) /**< The size of Flash array. */ +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) /**< The size of the Flash row. */ +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) /**< The number of Flash row. */ +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) /**< The number of Flash arrays. */ + +#if (CY_SFLASH_XTRA_ROWS) + #define CY_SFLASH_USERBASE (CYREG_SFLASH_MACRO_0_FREE_SFLASH0) /**< The base pointer of the user SFlash memory. */ + #define CY_SFLASH_SIZE (CYDEV_SFLASH_SIZE) /**< The size of the SFlash memory. */ + #define CY_SFLASH_SIZEOF_USERROW (CYDEV_FLS_ROW_SIZE) /**< The size of the SFlash row. */ + #define CY_SFLASH_NUMBER_USERROWS (4u) /**< The number of SFlash row. */ +#endif /* (CY_SFLASH_XTRA_ROWS) */ + + +/** +* \addtogroup group_flash_status_codes Flash API status codes +* \ingroup group_flash +* @{ +*/ + +/** Completed successfully. */ +#define CY_SYS_FLASH_SUCCESS (0x00u) +/** Specified flash row address is invalid. The row id or byte address provided is outside of the available memory. */ +#define CY_SYS_FLASH_INVALID_ADDR (0x04u) +/** Specified flash row is protected. */ +#define CY_SYS_FLASH_PROTECTED (0x05u) +/** Resume Completed. All non-blocking calls have completed. The resume/abort function cannot be called until the +next non-blocking. */ +#define CY_SYS_FLASH_RESUME_COMPLETED (0x07u) +/** \brief Pending Resume. A non-blocking was initiated and must be completed by calling the resume API, before any other +function may be called. */ +#define CY_SYS_FLASH_PENDING_RESUME (0x08u) +/** System Call Still In Progress. A resume or non-blocking is still in progress. The SPC ISR must fire before +attempting the next resume. */ +#define CY_SYS_FLASH_CALL_IN_PROGRESS (0x09u) +/** Invalid Flash Clock. Products using CY_IP_SRSSLT must set the IMO to 48MHz and the HF clock source to the IMO clock +before Write/Erase operations. */ +#define CY_SYS_FLASH_INVALID_CLOCK (0x12u) +/** @} group_flash_status_codes */ + +#define CY_SYS_SFLASH_SUCCESS (CY_SYS_FLASH_SUCCESS) +#define CY_SYS_SFLASH_INVALID_ADDR (CY_SYS_FLASH_INVALID_ADDR) +#define CY_SYS_SFLASH_PROTECTED (CY_SYS_FLASH_PROTECTED) + +/* CySysFlashSetWaitCycles() - implementation definitions */ +#define CY_FLASH_WAIT_STATE_EN (( uint32 )(( uint32 )0x01u << 18u)) +#define CY_FLASH_SYSCLK_BOUNDARY_MHZ (24u) +#if (CY_IP_CPUSS_FLASHC_PRESENT) + /* CySysFlashSetWaitCycles() */ + #if(CY_IP_FM || CY_IP_FS) + #define CY_FLASH_CTL_WS_0_FREQ_MIN (0u) + #define CY_FLASH_CTL_WS_0_FREQ_MAX (24u) + + #define CY_FLASH_CTL_WS_1_FREQ_MIN (24u) + #define CY_FLASH_CTL_WS_1_FREQ_MAX (48u) + #else /* (CY_IP_FMLT || CY_IP_FSLT) */ + #define CY_FLASH_CTL_WS_0_FREQ_MIN (0u) + #define CY_FLASH_CTL_WS_0_FREQ_MAX (16u) + + #define CY_FLASH_CTL_WS_1_FREQ_MIN (16u) + #define CY_FLASH_CTL_WS_1_FREQ_MAX (32u) + + #define CY_FLASH_CTL_WS_2_FREQ_MIN (32u) + #define CY_FLASH_CTL_WS_2_FREQ_MAX (48u) + #endif /* (CY_IP_FM || CY_IP_FS) */ + + #define CY_FLASH_CTL_WS_MASK ((uint32) 0x03u) + #define CY_FLASH_CTL_WS_0_VALUE (0x00u) + #define CY_FLASH_CTL_WS_1_VALUE (0x01u) + #if(CY_IP_FMLT || CY_IP_FSLT) + #define CY_FLASH_CTL_WS_2_VALUE (0x02u) + #endif /* (CY_IP_FMLT || CY_IP_FSLT) */ +#endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + + +#define CY_FLASH_KEY_ONE (0xB6u) +#define CY_FLASH_KEY_TWO(x) ((uint32) (((uint16) 0xD3u) + ((uint16) (x)))) + +#define CY_FLASH_PAGE_LATCH_START_ADDR ((uint32) (0x00u)) +#define CY_FLASH_ROW_NUM_MASK (0x100u) +#define CY_FLASH_CPUSS_REQ_START (( uint32 )(( uint32 )0x1u << 31u)) + +/* Opcodes */ +#define CY_FLASH_API_OPCODE_LOAD (0x04u) +#define CY_FLASH_API_OPCODE_WRITE_ROW (0x05u) +#define CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW (0x07u) +#define CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING (0x09u) + +#define CY_FLASH_API_OPCODE_PROGRAM_ROW (0x06u) +#define CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW (0x18u) + +#define CY_FLASH_API_OPCODE_CLK_CONFIG (0x15u) +#define CY_FLASH_API_OPCODE_CLK_BACKUP (0x16u) +#define CY_FLASH_API_OPCODE_CLK_RESTORE (0x17u) + +/* SROM API parameters offsets */ +#define CY_FLASH_PARAM_KEY_TWO_OFFSET (8u) +#define CY_FLASH_PARAM_ADDR_OFFSET (16u) +#define CY_FLASH_PARAM_MACRO_SEL_OFFSET (24u) + +#if (CY_IP_FLASH_MACROS == 2u) + /* Macro #0: rows 0x00-0x1ff, Macro #1: rows 0x200-0x3ff */ + #define CY_FLASH_GET_MACRO_FROM_ROW(row) ((uint32)(((row) > 0x1ffu) ? 1u : 0u)) +#else + /* Only macro # 0 is available */ + #define CY_FLASH_GET_MACRO_FROM_ROW(row) ((uint32)(((row) != 0u) ? 0u : 0u)) +#endif /* (CY_IP_FLASH_MACROS == 2u) */ + +#if(CY_IP_FMLT) + /* SROM size greater than 4k */ + #define CY_FLASH_IS_BACKUP_RESTORE (CYDEV_SROM_SIZE > 0x00001000u) +#endif /* (CY_IP_FMLT) */ + + +#if(CY_IP_SRSSV2) + #define CY_FLASH_CLOCK_BACKUP_SIZE (4u) +#else /* CY_IP_SRSSLT */ + #define CY_FLASH_CLOCK_BACKUP_SIZE (6u) +#endif /* (CY_IP_SRSSV2) */ + + +typedef struct cySysFlashClockBackupStruct +{ +#if(CY_IP_FM) + uint32 imoConfigReg; +#else /* (CY_IP_FMLT) */ + #if (CY_PSOC4_4000) + uint32 clkSelectReg; + uint32 clkImoEna; + uint32 clkImoFreq; + #else + + #if(CY_IP_SRSSV2) + uint32 clkImoPump; + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_SPCIF_SYNCHRONOUS) + uint32 clockSettings[CY_FLASH_CLOCK_BACKUP_SIZE]; /* FM-Lite Clock Backup */ + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ +} CY_SYS_FLASH_CLOCK_BACKUP_STRUCT; + + +/* SYSARG control register */ +#define CY_FLASH_CPUSS_SYSARG_REG (*(reg32 *) CYREG_CPUSS_SYSARG) +#define CY_FLASH_CPUSS_SYSARG_PTR ( (reg32 *) CYREG_CPUSS_SYSARG) + +/* SYSCALL control register */ +#define CY_FLASH_CPUSS_SYSREQ_REG (*(reg32 *) CYREG_CPUSS_SYSREQ) +#define CY_FLASH_CPUSS_SYSREQ_PTR ( (reg32 *) CYREG_CPUSS_SYSREQ) + +#if (CY_IP_CPUSS_FLASHC_PRESENT) + /* SYSARG control register */ + #define CY_FLASH_CTL_REG (*(reg32 *) CYREG_CPUSS_FLASH_CTL) + #define CY_FLASH_CTL_PTR ( (reg32 *) CYREG_CPUSS_FLASH_CTL) +#endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + + +#define CY_FLASH_API_RETURN (((CY_FLASH_CPUSS_SYSARG_REG & 0xF0000000u) == 0xF0000000u) ? \ + (CY_FLASH_CPUSS_SYSARG_REG & 0x000000FFu) : \ + (((CY_FLASH_CPUSS_SYSARG_REG & 0xF0000000u) == 0xA0000000u) ? \ + CYRET_SUCCESS : (CY_FLASH_CPUSS_SYSARG_REG & 0x000000FFu))) + + +/******************************************************************************* +* Thne following code is OBSOLETE and must not be used starting with cy_boot +* 4.20. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_FLASH_SRAM_ROM_KEY1 (( uint32 )0x00u) +#define CY_FLASH_SRAM_ROM_PARAM2 (CY_FLASH_SRAM_ROM_KEY1 + 0x04u) +#define CY_FLASH_SRAM_ROM_DATA (CY_FLASH_SRAM_ROM_KEY1 + 0x08u) + +#define CY_FLASH_SROM_CMD_RETURN_MASK (0xF0000000u) +#define CY_FLASH_SROM_CMD_RETURN_SUCC (0xA0000000u) +#define CY_FLASH_SROM_KEY1 (( uint32 )0xB6u) +#define CY_FLASH_SROM_KEY2_LOAD (( uint32 )0xD7u) +#define CY_FLASH_SROM_KEY2_WRITE (( uint32 )0xD8u) +#define CY_FLASH_SROM_LOAD_CMD ((CY_FLASH_SROM_KEY2_LOAD << 8u) | CY_FLASH_SROM_KEY1) +#define CY_FLASH_LOAD_BYTE_OPCODE (( uint32 )0x04u) +#define CY_FLASH_WRITE_ROW_OPCODE (( uint32 )0x05u) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLFClk.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLFClk.c new file mode 100644 index 0000000..acd01f7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLFClk.c @@ -0,0 +1,3230 @@ +/***************************************************************************//** +* \file .c +* \version 1.20 +* +* \brief +* This file provides the source code for configuring watchdog timers WDTs, +* low frequency clocks (LFCLK) and the Real-time Clock (RTC) component in +* PSoC Creator for the PSoC 4 families. +* +******************************************************************************** +* \copyright +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "CyLFClk.h" +#include "CyLib.h" + +#if (CY_IP_WCO && CY_IP_SRSSV2) + static uint32 CySysClkGetLfclkSource(void); +#endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + /* Default Ilo Trim Register value for ILO trimming*/ + static volatile uint16 defaultIloTrimRegValue = CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE; +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + +#if(CY_IP_SRSSV2) + /* CySysClkLfclkPosedgeCatch() / CySysClkLfclkPosedgeRestore() */ + static uint32 lfclkPosedgeWdtCounter0Enabled = 0u; + static uint32 lfclkPosedgeWdtCounter0Mode = CY_SYS_WDT_MODE_NONE; + + static volatile uint32 disableServicedIsr = 0uL; + static volatile uint32 wdtIsrMask = CY_SYS_WDT_COUNTER0_INT |\ + CY_SYS_WDT_COUNTER1_INT |\ + CY_SYS_WDT_COUNTER2_INT; + + static const uint32 counterIntMaskTbl[CY_WDT_NUM_OF_WDT] = {CY_SYS_WDT_COUNTER0_INT, + CY_SYS_WDT_COUNTER1_INT, + CY_SYS_WDT_COUNTER2_INT}; + + static void CySysClkLfclkPosedgeCatch(void); + static void CySysClkLfclkPosedgeRestore(void); + + static uint32 CySysWdtLocked(void); + static uint32 CySysClkIloEnabled(void); +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + static uint32 CySysClkGetTimerSource(void); + static volatile uint32 disableTimerServicedIsr = 0uL; + static volatile uint32 timerIsrMask = CY_SYS_TIMER0_INT |\ + CY_SYS_TIMER1_INT |\ + CY_SYS_TIMER2_INT; + + static const uint32 counterTimerIntMaskTbl[CY_SYS_NUM_OF_TIMERS] = {CY_SYS_TIMER0_INT, + CY_SYS_TIMER1_INT, + CY_SYS_TIMER2_INT}; + + static cyTimerCallback cySysTimerCallback[CY_SYS_NUM_OF_TIMERS] = {(void *)0, (void *)0, (void *)0}; +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_DWT_EN) */ + +#if(CY_IP_SRSSV2) + static cyWdtCallback cySysWdtCallback[CY_WDT_NUM_OF_WDT] = {(void *)0, (void *)0, (void *)0}; +#else + static cyWdtCallback cySysWdtCallback = (void *)0; +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Function Name: CySysClkIloStart +****************************************************************************//** +* \brief +* Enables ILO. +* +* Refer to the device datasheet for the ILO startup time. +* +*******************************************************************************/ +void CySysClkIloStart(void) +{ + CY_SYS_CLK_ILO_CONFIG_REG |= CY_SYS_CLK_ILO_CONFIG_ENABLE; +} + + +/******************************************************************************* +* Function Name: CySysClkIloStop +****************************************************************************//** +* \brief +* Disables the ILO. +* +* This function has no effect if WDT is locked (CySysWdtLock() is +* called). Call CySysWdtUnlock() to unlock WDT and stop ILO. +* +* PSoC 4100 / PSoC 4200: Note that ILO is required for WDT's operation. +* +* PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / +* PSoC 4200M: +* Stopping ILO affects the peripheral clocked by LFCLK, if +* LFCLK is configured to be sourced by ILO. +* +* If the ILO is disabled, all blocks run by ILO will stop functioning. +* +*******************************************************************************/ +void CySysClkIloStop(void) +{ + #if(CY_IP_SRSSV2) + uint8 interruptState; + + /* Do nothing if WDT is locked or ILO is disabled */ + if (0u == CySysWdtLocked()) + { + if (0u != CySysClkIloEnabled()) + { + + #if (CY_IP_WCO) + if (CY_SYS_CLK_LFCLK_SRC_ILO == CySysClkGetLfclkSource()) + { + #endif /* (CY_IP_WCO) */ + + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + + #if (CY_IP_WCO) + } + else /* Safe to disable - shortened pulse does not impact peripheral */ + { + CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + } + #endif /* (CY_IP_WCO) */ + + } + } + #else + CY_SYS_CLK_ILO_CONFIG_REG &= ( uint32 ) ( ~( uint32 )CY_SYS_CLK_ILO_CONFIG_ENABLE); + #endif /* (CY_IP_SRSSV2) */ +} + + +/****************************************************************************** +* Function Name: CySysClkIloStartMeasurement +***************************************************************************//** +* \brief +* Starts the ILO accuracy measurement. +* +* This function is non-blocking and needs to be called before using the +* CySysClkIloTrim() and CySysClkIloCompensate() API. +* +* This API configures measurement counters to be sourced by SysClk (Counter 1) +* and ILO (Counter 2). +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* In addition, this API stores the factory ILO trim settings on the first call +* after reset. This stored factory setting is used by the +* CySysClkIloRestoreFactoryTrim() API to restore the ILO factory trim. +* Hence, it is important to call this API before restoring the ILO +* factory trim settings. +* +******************************************************************************/ +void CySysClkIloStartMeasurement(void) +{ +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + static uint8 iloTrimTrig = 0u; + + /* Write default ILO trim value while ILO starting ( Cypress ID 225244 )*/ + if (0u == iloTrimTrig) + { + defaultIloTrimRegValue = ((uint8)(CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK)); + iloTrimTrig = 1u; + } +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + + /* Configure measurement counters to source by SysClk (Counter 1) and ILO (Counter 2)*/ + CY_SYS_CLK_DFT_REG = (CY_SYS_CLK_DFT_REG & (uint32) ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK) | + CY_SYS_CLK_SEL_ILO_DFT_SOURCE; + + CY_SYS_TST_DDFT_CTRL_REG = (CY_SYS_TST_DDFT_CTRL_REG & (uint32) ~ CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK) | + CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1; +} + + +/****************************************************************************** +* Function Name: CySysClkIloStopMeasurement +***************************************************************************//** +* \brief +* Stops the ILO accuracy measurement. +* +* Calling this function immediately stops the the ILO frequency measurement. +* This function should be called before placing the device to deepsleep, if +* CySysClkIloStartMeasurement() API was called before. +* +******************************************************************************/ +void CySysClkIloStopMeasurement(void) +{ + /* Set default configurations in 11...8 DFT register bits to zero */ + CY_SYS_CLK_DFT_REG &= ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK; + #if(CY_IP_SRSSLT) + CY_SYS_TST_DDFT_CTRL_REG &= ((uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + #endif /* (CY_IP_SRSSLT) */ +} + + +/****************************************************************************** +* Function Name: CySysClkIloCompensate +***************************************************************************//** +* \brief +* This API measures the current ILO accuracy. +* +* Basing on the measured frequency the required number of ILO cycles for a +* given delay (in microseconds) is obtained. The desired delay that needs to +* be compensated is passed through the desiredDelay parameter. The compensated +* cycle count is returned through the compesatedCycles pointer. +* The compensated ILO cycles can then be used to define the WDT period value, +* effectively compensating for the ILO inaccuracy and allowing a more +* accurate WDT interrupt generation. +* +* CySysClkIloStartMeasurement() API should be called prior to calling this API. +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* \note If the System clock frequency is changed in runtime, the CyDelayFreq() +* with the appropriate parameter (Frequency of bus clock in Hertz) should be +* called before calling a next CySysClkIloCompensate(). +* +* \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS. +* +* \param desiredDelay Required delay in microseconds. +* +* \param *compensatedCycles The pointer to the variable in which the required +* number of ILO cycles for the given delay will be returned. +* +* \details +* The value returned in *compensatedCycles pointer is not valid until the +* function returns CYRET_SUCCESS. +* +* The desiredDelay parameter value should be in next range:
From 100 to +* 2 000 000 microseconds for PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog +* Coprocessor devices.
From 100 to 4 000 000 000 microseconds for +* PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / +* PSoC 4200L / PSoC 4100M /PSoC 4200M devices. +* +* \return CYRET_SUCCESS - The compensation process is complete and the +* compensated cycles value is returned in the compensatedCycles pointer. +* +* \return CYRET_STARTED - Indicates measurement is in progress. It is +* strongly recommended to do not make pauses between API calling. The +* function should be called repeatedly until the API returns CYRET_SUCCESS. +* +* \return CYRET_INVALID_STATE - Indicates that measurement not started. +* The user should call CySysClkIloStartMeasurement() API before calling +* this API. +* +* \note For a correct WDT or DeepSleep Timers functioning with ILO compensating +* the CySysClkIloCompensate() should be called before WDT or DeepSleep Timers +* enabling. +* +*******************************************************************************/ +cystatus CySysClkIloCompensate(uint32 desiredDelay , uint32* compensatedCycles) +{ + uint32 iloCompensatedCycles; + uint32 desiredDelayInCounts; + static uint32 compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + uint32 checkStatus; + cystatus returnStatus; + + checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + + /* Check if CySysStartMeasurement was called before */ + if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + (CY_SYS_CLK_MAX_DELAY_US >= desiredDelay) && + (CY_SYS_CLK_MIN_DELAY_US <= desiredDelay) && + (compensatedCycles != NULL)) + { + if(CY_SYS_CLK_TRIM_OR_COMP_FINISHED != compensateRunningStatus) + { + /* Wait until counter 1 stopped counting and after it calculate compensated cycles */ + if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + if (0u != CY_SYS_CNT_REG2_REG) + { + /* Calculate required number of ILO cycles for given delay */ + #if(CY_IP_SRSSV2) + if (CY_SYS_CLK_DELAY_COUNTS_LIMIT < desiredDelay) + { + desiredDelayInCounts = (desiredDelay / CY_SYS_CLK_ILO_PERIOD); + iloCompensatedCycles = + (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) >> + CY_SYS_CLK_ILO_FREQ_2MSB) * (desiredDelayInCounts / CY_SYS_CLK_ILO_FREQ_3LSB); + } + else + { + desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + + CY_SYS_CLK_HALF_OF_CLOCK) / CY_SYS_CLK_ILO_PERIOD_PPH; + + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) * + desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED_FREQ_HZ; + } + #else /* (CY_IP_SRSSLT) */ + desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + CY_SYS_CLK_HALF_OF_CLOCK) / + CY_SYS_CLK_ILO_PERIOD_PPH; + if(CY_SYS_CLK_MAX_LITE_NUMBER < desiredDelayInCounts) + { + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> + CY_SYS_CLK_SYS_CLK_DEVIDER)) / CY_SYS_CLK_ILO_FREQ_2MSB) * + (desiredDelayInCounts / CY_SYS_CLK_ILO_FREQ_3LSB); + } + else + { + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) * + desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED_FREQ_HZ; + } + #endif /* (CY_IP_SRSSV2) */ + + *compensatedCycles = iloCompensatedCycles; + compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + returnStatus = CYRET_SUCCESS; + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + } + else + { + returnStatus = CYRET_STARTED; + } + } + else + { + /* Reload CNTR 1 count value for next measurement cycle*/ + CY_SYS_CNT_REG1_REG = (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER); + compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + returnStatus = CYRET_STARTED; + } + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + + return (returnStatus); +} + + +#if(CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysClkIloEnabled + ****************************************************************************//** + * + * \internal + * Reports the ILO enable state. + * + * \return + * 1 if ILO is enabled, and 0 if ILO is disabled. + * + * \endinternal + ********************************************************************************/ + static uint32 CySysClkIloEnabled(void) + { + /* Prohibits writing to WDT registers and ILO/WCO registers when not equal to 0 */ + return ((0u != (CY_SYS_CLK_ILO_CONFIG_REG & (uint32)(CY_SYS_CLK_ILO_CONFIG_ENABLE))) ? + (uint32) 1u : + (uint32) 0u); + } +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) +/******************************************************************************** +* Function Name: CySysClkIloTrim +*****************************************************************************//** +* \brief +* The API trims the ILO frequency to +/- 10% accuracy range using accurate +* SysClk. +* +* The API can be blocking or non-blocking depending on the value of the mode +* parameter passed. The accuracy of ILO after trimming in parts per thousand +* is returned through the iloAccuracyInPPT pointer. A positive number indicates +* that the ILO is running fast and a negative number indicates that the ILO is +* running slowly. This error is relative to the error in the reference clock +* (SysClk), so the absolute error will be higher and depends on the accuracy +* of the reference. +* +* The CySysClkIloStartMeasurement() API should be called prior to calling this +* API. Otherwise it will return CYRET_INVALID_STATE as the measurement was not +* started. +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* \note If System clock frequency is changed in runtime, the CyDelayFreq() +* with the appropriate parameter (Frequency of bus clock in Hertz) should be +* called before next CySysClkIloCompensate() usage. +* +* \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS +* or CYRET_TIMEOUT. +* +* Available for all PSoC 4 devices with ILO trim capability. This excludes +* PSoC 4000 / PSoC 4100 / PSoC 4200 / PSoC 4000S / PSoC 4100S / PSoC +* Analog Coprocessor devices. +* +* \param mode +* CY_SYS_CLK_BLOCKING - The function does not return until the ILO is +* within +/-10% accuracy range or time out has occurred.
+* CY_SYS_CLK_NON_BLOCKING - The function returns immediately after +* performing a single iteration of the trim process. The function should be +* called repeatedly until the trimming is completed successfully. +* +* \param *iloAccuracyInPPT Pointer to an integer in which the trimmed ILO +* accuracy will be returned. +* +* \details The value returned in *iloAccuracyInPPT pointer is not valid +* until the function returns CYRET_SUCCESS. ILO accuracy in PPT is given by: +* +* IloAccuracyInPPT = ((MeasuredIloFreq - DesiredIloFreq) * +* CY_SYS_CLK_PERTHOUSAND) / DesiredIloFreq); +* +* DesiredIloFreq = 32000, CY_SYS_CLK_PERTHOUSAND = 1000; +* +* \return CYRET_SUCCESS - Indicates trimming is complete. This value indicates +* trimming is successful and iloAccuracyInPPT is within +/- 10%. +* +* \return CYRET_STARTED - Indicates measurement is in progress. This is applicable +* only for non-blocking mode. +* +* \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. You should +* call CySysClkIloStartMeasurement() before calling this API. +* +* \return CYRET_TIMEOUT - Indicates trimming was unsuccessful. This is applicable +* only for blocking mode. Timeout means the trimming was tried 5 times without +* success (i.e. ILO accuracy > +/- 10%). The user can call the API again for +* another try or wait for some time before calling it again (to let the system +* to settle to another operating point change in temperature etc.) and continue +* using the previous trim value till the next call. +* +**********************************************************************************/ +cystatus CySysClkIloTrim(uint32 mode, int32* iloAccuracyInPPT) +{ + uint32 timeOutClocks = CY_SYS_CLK_TIMEOUT; + uint32 waitUntilCntr1Stops; + static uint32 trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + uint32 checkStatus; + cystatus returnStatus; + + checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + + /* Check if DFT and CTRL registers were configures in CySysStartMeasurement*/ + if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + (iloAccuracyInPPT != NULL)) + { + if(CY_SYS_CLK_BLOCKING == mode) + { + waitUntilCntr1Stops = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + do + { + /* Reload CNTR 1 count value for measuring cycle*/ + CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + + /* Wait until counter CNTR 1 will finish down-counting */ + while (0u == (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + waitUntilCntr1Stops--; + if (0u == waitUntilCntr1Stops) + { + break; + } + } + trimRunningStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + timeOutClocks--; + + /* Untill ILO accuracy will be in range less than +/- 10% or timeout occurs*/ + } while((CYRET_SUCCESS != trimRunningStatus) && + (CYRET_INVALID_STATE != trimRunningStatus) && + (0u != timeOutClocks)); + + if (CYRET_SUCCESS == trimRunningStatus) + { + returnStatus = CYRET_SUCCESS; + } + else + { + if(0u == timeOutClocks) + { + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + returnStatus = CYRET_TIMEOUT; + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + } + } + /* Non - blocking mode */ + else + { + if (CY_SYS_CLK_TRIM_OR_COMP_FINISHED != trimRunningStatus) + { + /* Checking if the counter CNTR 1 finished down-counting */ + if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + returnStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + } + else + { + returnStatus = CYRET_STARTED; + } + } + else + { + /* Reload CNTR 1 count value for next measuring */ + CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + returnStatus = CYRET_STARTED; + } + } + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + + return (returnStatus); +} + + +/******************************************************************************** +* Function Name: CySysClkIloUpdateTrimReg +********************************************************************************* +* +* \internal +* Function calculates ILO accuracy and check is error range is higher than +* +/- 10%. If Measured frequency is higher than +/- 10% function updates +* ILO Trim register. +* +* \param +* iloAccuracyInPPT Pointer to an integer in which the trimmed ILO +* accuracy will be returned. The value returned in this pointer is not valid +* until the function returns CYRET_SUCCESS. If ILO frequency error is lower +* than +/- 10% then the value returned in this pointer will be updated. +* +* \return CYRET_SUCCESS - Indicates that ILO frequency error is lower than +* +/- 10% and no actions are required. +* +* \return CYRET_STARTED - Indicates that ILO frequency error is higher than +* +/- 10% and ILO Trim register was updated. +* +* \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. +* +* Post #1 - To obtain 10% ILO accuracy the calculated accuracy should be equal +* CY_SYS_CLK_ERROR_RANGE = 5.6%. Error value should take to account IMO error of +* +/-2% (+/-0.64kHz), trim step of 2.36kHz (+/-1.18kHz) and error while ILO +* frequency measuring. +* +* \endinternal +* +**********************************************************************************/ +cystatus CySysClkIloUpdateTrimReg(int32* iloAccuracyInPPT) +{ + uint32 measuredIloFreq; + uint32 currentIloTrimValue; + int32 iloAccuracyValue; + int32 trimStep; + cystatus errorRangeStatus; + + if(0u != CY_SYS_CNT_REG2_REG) + { + measuredIloFreq = (CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER); + + /* Calculate value of error in PPT according to formula - + * ((measuredIlofrequency - iloDesired frequency) * 1000 / iloDesired frequency) */ + iloAccuracyValue = (((int32) measuredIloFreq - (int32) CY_SYS_CLK_ILO_DESIRED_FREQ_HZ) * \ + ((int32) CY_SYS_CLK_PERTHOUSAND)) / ((int32) CY_SYS_CLK_ILO_DESIRED_FREQ_HZ); + + /* Check if ILO accuracy is more than +/- CY_SYS_CLK_ERROR_RANGE. See post #1 of API description.*/ + if(CY_SYS_CLK_ERROR_RANGE < (uint32) (CY_SYS_CLK_ABS_MACRO(iloAccuracyValue))) + { + if (0 < iloAccuracyValue) + { + trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) + + CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + } + else + { + trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) - + CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + } + currentIloTrimValue = (CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK); + trimStep = (int32) currentIloTrimValue - trimStep; + + if(trimStep > CY_SYS_CLK_FOURBITS_MAX) + { + trimStep = CY_SYS_CLK_FOURBITS_MAX; + } + if(trimStep < 0) + { + trimStep = 0; + } + CY_SYS_CLK_ILO_TRIM_REG = (CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MASK)) | + ((uint32) trimStep); + errorRangeStatus = CYRET_STARTED; + } /* Else return success because error is in +/- 10% range*/ + else + { + /* Write trimmed ILO accuracy through pointer. */ + *iloAccuracyInPPT = iloAccuracyValue; + errorRangeStatus = CYRET_SUCCESS; + } + } + else + { + errorRangeStatus = CYRET_INVALID_STATE; + } +return (errorRangeStatus); +} + + +/******************************************************************************* +* Function Name: CySysClkIloRestoreFactoryTrim +****************************************************************************//** +* \brief +* Restores the ILO Trim Register to factory value. +* +* The CySysClkIloStartMeasurement() API should be called prior to +* calling this API. Otherwise CYRET_UNKNOWN will be returned. +* +* Available for all PSoC 4 devices except for PSoC 4000 / PSoC 4100 / PSoC 4200 +* / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. +* +* \return CYRET_SUCCESS - Operation was successful. +* \return CYRET_UNKNOWN - CySysClkIloStartMeasurement() was not called +* before this API. Hence the trim value cannot be updated. +* +******************************************************************************/ +cystatus CySysClkIloRestoreFactoryTrim(void) +{ + cystatus returnStatus = CYRET_SUCCESS; + + /* Check was defaultIloTrimRegValue modified in CySysClkIloStartMeasurement */ + if(CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE != defaultIloTrimRegValue) + { + CY_SYS_CLK_ILO_TRIM_REG = ((CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MASK)) | + (defaultIloTrimRegValue & CY_SYS_CLK_ILO_TRIM_MASK)); + } + else + { + returnStatus = CYRET_UNKNOWN; + } + + return (returnStatus); +} +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + + +#if (CY_IP_WCO && CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysClkGetLfclkSource + ******************************************************************************** + * + * \internal + * Gets the clock source for the LFCLK clock. + * The function is applicable only for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L. + * + * \return The LFCLK source: + * CY_SYS_CLK_LFCLK_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) + * CY_SYS_CLK_LFCLK_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) + * + * \endinternal + * + *******************************************************************************/ + static uint32 CySysClkGetLfclkSource(void) + { + uint32 lfclkSource; + lfclkSource = CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK; + return (lfclkSource); + } + + + /******************************************************************************* + * Function Name: CySysClkSetLfclkSource + ****************************************************************************//** + * \brief + * Sets the clock source for the LFCLK clock. + * + * The switch between LFCLK sources must be done between the positive edges of + * LFCLK, because the glitch risk is around the LFCLK positive edge. To ensure + * that the switch can be done safely, the WDT counter value is read until it + * changes. + * + * That means that the positive edge just finished and the switch is performed. + * The enabled WDT counter is used for that purpose. If no counters are enabled, + * counter 0 is enabled. And after the LFCLK source is switched, counter 0 + * configuration is restored. + * + * The function is applicable only for devices with more than one source for + * LFCLK - PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L. + * + * \note For PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices LFCLK can + * only be sourced from ILO even though WCO is available. + * + * \param + * source + * CY_SYS_CLK_LFCLK_SRC_ILO - Internal Low Frequency (32 kHz) + * Oscillator (ILO).
+ * CY_SYS_CLK_LFCLK_SRC_WCO - Low Frequency Watch Crystal Oscillator (WCO). + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is called). + * Call CySysWdtUnlock() to unlock WDT. + * + * Both the current source and the new source must be running and stable before + * calling this function. + * + * Changing the LFCLK clock source may change the LFCLK clock frequency and + * affect the functionality that uses this clock. For example, watchdog timer + * "uses this clock" or "this clock uses" (WDT) is clocked by LFCLK. + * + *******************************************************************************/ + void CySysClkSetLfclkSource(uint32 source) + { + uint8 interruptState; + + if (CySysClkGetLfclkSource() != source) + { + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_WDT_CONFIG_REG = (CY_SYS_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_LFCLK_SEL_MASK)) | + (source & CY_SYS_CLK_LFCLK_SEL_MASK); + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + } + } +#endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + + +#if (CY_IP_WCO) + /******************************************************************************* + * Function Name: CySysClkWcoStart + ****************************************************************************//** + * \brief + * Enables Watch Crystal Oscillator (WCO). + * + * This API enables WCO which is used as a source for LFCLK. Similar to ILO, + * WCO is also available in all modes except Hibernate and Stop modes. + * \note In PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices + * WCO cannot be a source for the LFCLK. + * + * WCO is always enabled in High Power Mode (HPM). Refer to the device + * datasheet for the WCO startup time. Once WCO becomes stable it can be + * switched to Low Power Mode (LPM). Note that oscillator can be unstable + * during a switch and hence its output should not be used at that moment. + * + * The CySysClkWcoSetPowerMode() function configures the WCO power mode. + * + *******************************************************************************/ + void CySysClkWcoStart(void) + { + CySysClkWcoSetHighPowerMode(); + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + } + + + /******************************************************************************* + * Function Name: CySysClkWcoStop + ****************************************************************************//** + * \brief + * Disables the 32 KHz Crystal Oscillator. + * + * API switch of WCO. + * \note PSoC 4100S / PSoC Analog Coprocessor: WCO is required for DeepSleep + * Timer's operation. + * + *******************************************************************************/ + void CySysClkWcoStop(void) + { + #if (CY_IP_SRSSV2) + uint8 interruptState; + #endif /* (CY_IP_SRSSV2) */ + + if (0u != CySysClkWcoEnabled()) + { + #if (CY_IP_SRSSV2) + if (CY_SYS_CLK_LFCLK_SRC_WCO == CySysClkGetLfclkSource()) + { + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + } + else /* Safe to disable - shortened pulse does not impact peripheral */ + #endif /* (CY_IP_SRSSV2) */ + { + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + } + } /* Otherwise do nothing. WCO configuration cannot be changed. */ + } + + + /******************************************************************************* + * Function Name: CySysClkWcoEnabled + ****************************************************************************//** + * \internal Reports the WCO enable state. + * + * \return 1 if WCO is enabled + * \return 0 if WCO is disabled. + * \endinternal + *******************************************************************************/ + uint32 CySysClkWcoEnabled(void) + { + return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE))) ? + (uint32) 1u : + (uint32) 0u); + } + + + /******************************************************************************* + * Function Name: CySysClkWcoSetPowerMode + ****************************************************************************//** + * \brief + * Sets the power mode for the 32 KHz WCO. + * + * By default (if this function is not called), the WCO is in High power mode + * during Active and device's low power modes + * + * \param mode + * CY_SYS_CLK_WCO_HPM - The High Power mode.
+ * CY_SYS_CLK_WCO_LPM - The Low Power mode. + * + * \return A previous power mode. The same as the parameters. + * + * \note + * The WCO Low Power mode is applicable for PSoC 4100 BLE / PSoC 4200 BLE devices. + * + *******************************************************************************/ + uint32 CySysClkWcoSetPowerMode(uint32 mode) + { + uint32 powerModeStatus; + + powerModeStatus = CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_LPM_EN; + + switch(mode) + { + case CY_SYS_CLK_WCO_HPM: + CySysClkWcoSetHighPowerMode(); + break; + + #if(CY_IP_BLESS) + case CY_SYS_CLK_WCO_LPM: + CySysClkWcoSetLowPowerMode(); + break; + #endif /* (CY_IP_BLESS) */ + + default: + CYASSERT(0u != 0u); + break; + } + + return (powerModeStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkWcoClockOutSelect + ****************************************************************************//** + * \brief + * Selects the WCO block output source. + * + * In addition to generating 32.768 kHz clock from external crystals, WCO + * can be sourced by external clock source using wco_out pin. The API help to + * lets you select between the sources: External crystal or external pin. + * + * If you want to use external pin to drive WCO the next procedure is required: + *
1) Disable the WCO. + *
2) Drive the wco_out pin to an external signal source. + *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_PIN). + *
4) Enable the WCO and wait for 15 us before clocking the XO pad at the high + * potential. Let's assume you are using the 1.6v clock amplitude, then the + * sequence would start at 1.6v, then 0v, then 1.6v etc at a chosen frequency. + * + * If you want to use WCO after using an external pin source: + *
1) Disable the WCO. + *
2) Drive off wco_out pin with external signal source. + *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_CRYSTAL). + *
4) Enable the WCO. + * + * \warning + * Do not use the oscillator output clock prior to a 15uS delay in your system. + * There are no limitations on the external clock frequency. + * \warning + * When external clock source was selected to drive WCO block the IMO can be + * trimmed only when external clock source period is equal to WCO external + * crystal period. Also external clock source accuracy should be higher + * or equal to WCO external crystal accuracy. + * + * \param clockSel + * CY_SYS_CLK_WCO_SEL_CRYSTAL - Selects External crystal as clock + * source of WCO.
+ * CY_SYS_CLK_WCO_SEL_PIN - Selects External clock input on wco_in pin as + * clock source of WCO. + * + *******************************************************************************/ + void CySysClkWcoClockOutSelect(uint32 clockSel) + { + if (0u != CySysClkWcoEnabled()) + { + if (1u >= clockSel) + { + CY_SYS_CLK_WCO_CONFIG_REG = (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(~CY_SYS_CLK_WCO_SELECT_PIN_MASK)) | + (clockSel << CY_SYS_CLK_WCO_SELECT_PIN_OFFSET); + } + else + { + CYASSERT(0u != 0u); + } + } + } +#endif /* (CY_IP_WCO) */ + + +#if(CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysWdtLock + ****************************************************************************//** + * \brief + * Locks out configuration changes to the Watchdog timer registers and ILO + * configuration register. + * + * After this function is called, ILO clock can't be disabled until + * CySysWdtUnlock() is called. + * + *******************************************************************************/ + void CySysWdtLock(void) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BITS_MASK; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtLocked + ****************************************************************************//** + * \internal + * Reports the WDT lock state. + * + * \return 1 - WDT is locked, and 0 - WDT is unlocked. + * \endinternal + *******************************************************************************/ + static uint32 CySysWdtLocked(void) + { + /* Prohibits writing to WDT registers and ILO/WCO registers when not equal 0 */ + return ((0u != (CY_SYS_CLK_SELECT_REG & (uint32)(CY_SYS_WDT_CLK_LOCK_BITS_MASK))) ? (uint32) 1u : (uint32) 0u); + } + + + /******************************************************************************* + * Function Name: CySysWdtUnlock + ****************************************************************************//** + * \brief + * Unlocks the Watchdog Timer configuration register. + * + *******************************************************************************/ + void CySysWdtUnlock(void) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + /* Removing WDT lock requires two writes */ + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BIT0); + + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BIT1); + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetEnabledStatus + ****************************************************************************//** + * \brief + * Reads the enabled status of one of the three WDT counters. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \return The status of the WDT counter: + * \return 0 - If the counter is disabled. + * \return 1 - If the counter is enabled. + * + * \details + * This function returns an actual WDT counter status from the status register. It may + * take up to 3 LFCLK cycles for the WDT status register to contain actual data + * after the WDT counter is enabled. + * + *******************************************************************************/ + uint32 CySysWdtGetEnabledStatus(uint32 counterNum) + { + CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + return ((CY_SYS_WDT_CONTROL_REG >> ((CY_SYS_WDT_CNT_SHIFT * counterNum) + CY_SYS_WDT_CNT_STTS_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMode + ****************************************************************************//** + * \brief + * Writes the mode of one of the three WDT counters. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \param mode + * CY_SYS_WDT_MODE_NONE - Free running.
+ * CY_SYS_WDT_MODE_INT - The interrupt generated on match for counter 0 + * and 1, and on bit toggle for counter 2.
+ * CY_SYS_WDT_MODE_RESET - Reset on match (valid for counter 0 and 1 only).
+ * CY_SYS_WDT_MODE_INT_RESET - Generate an interrupt. Generate a reset on + * the 3rd non-handled interrupt (valid for counter 0 and counter 1 only). + * + * \details + * WDT counter counterNum should be disabled to set a mode. Otherwise, this + * function call has no effect. If the specified counter is enabled, + * call the CySysWdtDisable() function with the corresponding parameter to + * disable the specified counter and wait for it to stop. + * + *******************************************************************************/ + void CySysWdtSetMode(uint32 counterNum, uint32 mode) + { + uint32 configRegValue; + + CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + + if(0u == CySysWdtGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG & + (uint32)~((uint32)(CY_SYS_WDT_MODE_MASK << (counterNum * CY_SYS_WDT_CNT_SHIFT))); + configRegValue |= (uint32)((mode & CY_SYS_WDT_MODE_MASK) << (counterNum * CY_SYS_WDT_CNT_SHIFT)); + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMode + ****************************************************************************//** + * + * \brief Reads the mode of one of the three WDT counters. + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + * \return The mode of the counter. The same enumerated values as the mode + * parameter used in CySysWdtSetMode(). + * + *******************************************************************************/ + uint32 CySysWdtGetMode(uint32 counterNum) + { + return ((CY_SYS_WDT_CONFIG_REG >> (counterNum * CY_SYS_WDT_CNT_SHIFT)) & CY_SYS_WDT_MODE_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetClearOnMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter "clear on match" setting. + * + * If configured to "clear on match", the counter counts from 0 to MatchValue + * giving it a period of (MatchValue + 1). + * + * \param counterNum + * Valid range [0-1]. The number of the WDT counter. The match values are not + * supported by counter 2. + * + * \param enable 0 to disable appropriate counter
+ * 1 to enable appropriate counter + * + * \details + * WDT counter counterNum should be disabled. Otherwise this function call + * has no effect. If the specified counter is enabled, call the CySysWdtDisable() + * function with the corresponding parameter to disable the specified counter and + * wait for it to stop. This may take up to three LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetClearOnMatch(uint32 counterNum, uint32 enable) + { + uint32 configRegValue; + + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + if(0u == CySysWdtGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << + ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT))); + + configRegValue + |= (uint32)(enable << ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)); + + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetClearOnMatch + ****************************************************************************//** + * \brief + * Reads the "clear on match" setting for the specified counter. + * + * \param + * counterNum Valid range [0-1]. The number of the WDT counter. The match values + * are not supported by counter 2. + * + * \return The "clear on match" status:
1 if enabled
0 if disabled + * + *******************************************************************************/ + uint32 CySysWdtGetClearOnMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + return (uint32)((CY_SYS_WDT_CONFIG_REG >> + ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnable + ****************************************************************************//** + * + * \brief Enables the specified WDT counters. + * + * All the counters specified in the mask are enabled. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to enable.
+ * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to enable.
+ * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to enable. + * + * \details + * Enabling or disabling WDT requires 3 LFCLK cycles to come into effect. + * Therefore, the WDT enable state must not be changed more than once in + * that period. + * + * After WDT is enabled, it is illegal to write WDT configuration (WDT_CONFIG) + * and control (WDT_CONTROL) registers. This means that all WDT functions that + * contain 'write' in the name (with the exception of CySysWdtSetMatch() + * function) are illegal to call if WDT is enabled. + * + * PSoC 4100 / PSoC 4200: This function enables ILO. + * + * PSoC 4100 BLE / PSoC 4200 BLE / PSoC4200L / PSoC 4100M + * / PSoC 4200M: + * LFLCK should be configured before calling this function. The desired + * source should be enabled and configured to be the source for LFCLK. + * + *******************************************************************************/ + void CySysWdtEnable(uint32 counterMask) + { + #if (!CY_IP_WCO) + CySysClkIloStart(); + #endif /* (!CY_IP_WCO) */ + + CY_SYS_WDT_CONTROL_REG |= counterMask; + + if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + /* Wait for changes to come into effect */ + } + } + } + + + /******************************************************************************* + * Function Name: CySysWdtDisable + ****************************************************************************//** + * + * \brief Disables the specified WDT counters. + * All the counters specified in the mask are disabled. The function waits for + * the changes to come into effect. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to disable.
+ * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to disable.
+ * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to disable. + * + *******************************************************************************/ + void CySysWdtDisable(uint32 counterMask) + { + if (0uL == CySysWdtLocked()) + { + CY_SYS_WDT_CONTROL_REG &= ~counterMask; + + if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + /* Wait for changes to come into effect */ + } + } + } + } + + + /******************************************************************************* + * Function Name: CySysWdtSetCascade + ****************************************************************************//** + * \brief + * Writes the two WDT cascade values based on the combination of mask values + * specified. + * + * \param cascadeMask The mask value used to set or clear the cascade values: + * CY_SYS_WDT_CASCADE_NONE - Neither
+ * CY_SYS_WDT_CASCADE_01 - Cascade 01
+ * CY_SYS_WDT_CASCADE_12 - Cascade 12 + * + * If only one cascade mask is specified, the second cascade is disabled. + * To set both cascade modes, two defines should be ORed: + * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). + * \note If CySysWdtSetCascade() was called with ORed defines it is necessary + * to call CySysWdtSetClearOnMatch(1,1). It is needed to make sure that + * Counter 2 will be updated in the expected way. + * + * WDT counters that are part of the specified cascade should be disabled. + * Otherwise this function call has no effect. If the specified + * counter is enabled, call CySysWdtDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. This may + * take up to 3 LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetCascade(uint32 cascadeMask) + { + uint32 configRegValue; + uint32 countersEnableStatus; + + countersEnableStatus = CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0) | + CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1) | + CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2); + + if (0u == countersEnableStatus) + { + configRegValue = CY_SYS_WDT_CONFIG_REG; + configRegValue &= ((uint32)(~(CY_SYS_WDT_CASCADE_01|CY_SYS_WDT_CASCADE_12))); + configRegValue |= cascadeMask; + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCascade + ****************************************************************************//** + * + * \brief Reads the two WDT cascade values returning a mask of the bits set. + * + * \return The mask of the cascade values set. + * \return CY_SYS_WDT_CASCADE_NONE - Neither + * \return CY_SYS_WDT_CASCADE_01 - Cascade 01 + * \return CY_SYS_WDT_CASCADE_12 - Cascade 12 + * + *******************************************************************************/ + uint32 CySysWdtGetCascade(void) + { + return (CY_SYS_WDT_CONFIG_REG & (CY_SYS_WDT_CASCADE_01 | CY_SYS_WDT_CASCADE_12)); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter match comparison value. + * + * \param counterNum + * Valid range [0-1]. The number of the WDT counter. The match values are not + * supported by counter 2. + * + * \param match + * Valid range [0-65535]. The value to be used to match against the counter. + * + *******************************************************************************/ + void CySysWdtSetMatch(uint32 counterNum, uint32 match) + { + uint32 regValue; + + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + /* Wait for previous changes to come into effect */ + CyDelayUs(CY_SYS_WDT_3LFCLK_DELAY_US); + + regValue = CY_SYS_WDT_MATCH_REG; + regValue &= (uint32)~((uint32)(CY_SYS_WDT_LOWER_16BITS_MASK << (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT))); + CY_SYS_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT))); + + /* Make sure match synchronization has started */ + CyDelayUs(CY_SYS_WDT_1LFCLK_DELAY_US); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetToggleBit + ****************************************************************************//** + * \brief + * Configures which bit in WDT counter 2 to monitor for a toggle. + * + * When that bit toggles, an interrupt is generated if the mode for counter 2 has + * enabled interrupts. + * + * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. + * + * \details + * WDT Counter 2 should be disabled. Otherwise this function call has no + * effect. + * + * If the specified counter is enabled, call the CySysWdtDisable() function with + * the corresponding parameter to disable the specified counter and wait for it to + * stop. This may take up to 3 LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetToggleBit(uint32 bits) + { + uint32 configRegValue; + + if (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG; + configRegValue &= (uint32)(~((uint32)(CY_SYS_WDT_CONFIG_BITS2_MASK << CY_SYS_WDT_CONFIG_BITS2_POS))); + configRegValue |= ((bits & CY_SYS_WDT_CONFIG_BITS2_MASK) << CY_SYS_WDT_CONFIG_BITS2_POS); + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetToggleBit + ****************************************************************************//** + * \brief + * Reads which bit in WDT counter 2 is monitored for a toggle. + * + * \return The bit that is monitored (range of 0 to 31) + * + *******************************************************************************/ + uint32 CySysWdtGetToggleBit(void) + { + return ((CY_SYS_WDT_CONFIG_REG >> CY_SYS_WDT_CONFIG_BITS2_POS) & CY_SYS_WDT_CONFIG_BITS2_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMatch + ****************************************************************************//** + * + * \brief Reads the WDT counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the WDT counter. The match + * values are not supported by counter 2. + * + * \return A 16-bit match value. + * + *******************************************************************************/ + uint32 CySysWdtGetMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + return ((uint32)(CY_SYS_WDT_MATCH_REG >> + (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT)) & CY_SYS_WDT_LOWER_16BITS_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCount + ****************************************************************************//** + * + * \brief Reads the current WDT counter value. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters + * and counter 2 is a 32 bit counter. + * + *******************************************************************************/ + uint32 CySysWdtGetCount(uint32 counterNum) + { + uint32 regValue = 0u; + + switch(counterNum) + { + /* WDT Counter 0 */ + case 0u: + regValue = CY_SYS_WDT_CTRLOW_REG & CY_SYS_WDT_LOWER_16BITS_MASK; + break; + + /* WDT Counter 1 */ + case 1u: + regValue = (CY_SYS_WDT_CTRLOW_REG >> CY_SYS_WDT_CNT_MATCH_SHIFT) & CY_SYS_WDT_LOWER_16BITS_MASK; + break; + + /* WDT Counter 2 */ + case 2u: + regValue = CY_SYS_WDT_CTRHIGH_REG; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + return (regValue); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetInterruptSource + ****************************************************************************//** + * \brief + * Reads a mask containing all the WDT counters interrupts that are currently + * set by the hardware, if a corresponding mode is selected. + * + * \return The mask of interrupts set + * \return CY_SYS_WDT_COUNTER0_INT - Counter 0 + * \return CY_SYS_WDT_COUNTER1_INT - Counter 1 + * \return CY_SYS_WDT_COUNTER2_INT - Counter 2 + * + *******************************************************************************/ + uint32 CySysWdtGetInterruptSource(void) + { + return (CY_SYS_WDT_CONTROL_REG & (CY_SYS_WDT_COUNTER0_INT | CY_SYS_WDT_COUNTER1_INT | CY_SYS_WDT_COUNTER2_INT)); + } + + + /******************************************************************************* + * Function Name: CySysWdtClearInterrupt + ****************************************************************************//** + * \brief + * Clears all the WDT counter interrupts set in the mask. + * + * Calling this function also prevents from Reset when the counter mode is set + * to generate 3 interrupts and then the device resets. + * + * All the WDT interrupts are to be cleared by the firmware, otherwise + * interrupts are generated continuously. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_INT - Clears counter 0 interrupts
+ * CY_SYS_WDT_COUNTER1_INT - Clears counter 1 interrupts
+ * CY_SYS_WDT_COUNTER2_INT - Clears counter 2 interrupts + * + * \details + * This function temporary removes the watchdog lock, if it was set, and + * restores the lock state after cleaning the WDT interrupts that are set in + * a mask. + * + *******************************************************************************/ + void CySysWdtClearInterrupt(uint32 counterMask) + { + uint8 interruptState; + uint32 wdtLockState; + + interruptState = CyEnterCriticalSection(); + + if (0u != CySysWdtLocked()) + { + wdtLockState = 1u; + CySysWdtUnlock(); + } + else + { + wdtLockState = 0u; + } + + /* Set new WDT control register value */ + counterMask &= (CY_SYS_WDT_COUNTER0_INT | + CY_SYS_WDT_COUNTER1_INT | + CY_SYS_WDT_COUNTER2_INT); + + CY_SYS_WDT_CONTROL_REG = counterMask | (CY_SYS_WDT_CONTROL_REG & ~(CY_SYS_WDT_COUNTER0_INT | + CY_SYS_WDT_COUNTER1_INT | + CY_SYS_WDT_COUNTER2_INT)); + + /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. + * Cypress ID #207093, #206231 + */ + (void)CY_SYS_WDT_CONTROL_REG; + + if (1u == wdtLockState) + { + CySysWdtLock(); + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtResetCounters + ****************************************************************************//** + * \brief + * Resets all the WDT counters set in the mask. + * + * \param countersMask + * CY_SYS_WDT_COUNTER0_RESET - Reset counter 0
+ * CY_SYS_WDT_COUNTER1_RESET - Reset counter 1
+ * CY_SYS_WDT_COUNTER2_RESET - Reset counter 2 + * + * \details + * This function does not reset counter values if the Watchdog is locked. + * This function waits while corresponding counters will be reset. This may + * take up to 3 LFCLK cycles. + * The LFCLK source must be enabled. Otherwise, the function will never exit. + * + *******************************************************************************/ + void CySysWdtResetCounters(uint32 countersMask) + { + /* Set new WDT reset value */ + CY_SYS_WDT_CONTROL_REG |= (countersMask & CY_SYS_WDT_COUNTERS_RESET); + + while (0uL != (CY_SYS_WDT_CONTROL_REG & CY_SYS_WDT_COUNTERS_RESET)) + { + /* Wait for reset to come into effect */ + } + } + + + /******************************************************************************* + * Function Name: CySysWdtSetInterruptCallback + ****************************************************************************//** + * \brief + * Sets the ISR callback function for the particular WDT counter. + * These functions are called on the WDT interrupt. + * + * \param counterNum The number of the WDT counter. + * \param function The pointer to the callback function. + * + * \return The pointer to the previous callback function. + * \return NULL is returned if the specified address is not set. + * + *******************************************************************************/ + cyWdtCallback CySysWdtSetInterruptCallback(uint32 counterNum, cyWdtCallback function) + { + cyWdtCallback prevCallback = (void *)0; + + if(counterNum < CY_WDT_NUM_OF_WDT) + { + prevCallback = cySysWdtCallback[counterNum]; + cySysWdtCallback[counterNum] = function; + } + else + { + CYASSERT(0u != 0u); + } + + return((cyWdtCallback)prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetInterruptCallback + ****************************************************************************//** + * \brief + * Gets the ISR callback function for the particular WDT counter. + * + * \param counterNum The number of the WDT counter. + * + * \return The pointer to the callback function registered for a particular WDT by + * a particular address that are passed through arguments. + * + *******************************************************************************/ + cyWdtCallback CySysWdtGetInterruptCallback(uint32 counterNum) + { + cyWdtCallback retCallback = (void *)0; + + if(counterNum < CY_WDT_NUM_OF_WDT) + { + retCallback = (cyWdtCallback)cySysWdtCallback[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + + return(retCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnableCounterIsr + ****************************************************************************//** + * \brief + * Enables the ISR callback servicing for the particular WDT counter + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + * Value corresponds to appropriate WDT counter. For example value 1 + * corresponds to second WDT counter. + * + *******************************************************************************/ + void CySysWdtEnableCounterIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_WDT_COUNTER2) + { + disableServicedIsr &= ~counterIntMaskTbl[counterNum]; + wdtIsrMask |= counterIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysWdtDisableCounterIsr + ****************************************************************************//** + * \brief + * Disables the ISR callback servicing for the particular WDT counter + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + *******************************************************************************/ + void CySysWdtDisableCounterIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_WDT_COUNTER2) + { + wdtIsrMask &= ~counterIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysWdtIsr + ****************************************************************************//** + * \brief + * This is the handler of the WDT interrupt in CPU NVIC. + * + * The handler checks which WDT triggered in the interrupt and calls the + * respective callback functions configured by the user by using + * CySysWdtSetIsrCallback() API. + * + * The order of the callback execution is incremental. Callback-0 is + * run as the first one and callback-2 is called as the last one. + * + * \details + * This function clears the WDT interrupt every time when it is called. + * Reset after the 3rd interrupt does not happen if this function is registered + * as the interrupt handler even if the "Watchdog with Interrupt" mode is + * selected on the "Low Frequency Clocks" tab. + * + *******************************************************************************/ + void CySysWdtIsr(void) + { + if(0u != (CY_SYS_WDT_COUNTER0_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER0_INT & wdtIsrMask)) + { + wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER0_INT); + disableServicedIsr &= ~CY_SYS_WDT_COUNTER0_INT; + if(cySysWdtCallback[CY_SYS_WDT_COUNTER0] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER0])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + + if(0u != (CY_SYS_WDT_COUNTER1_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER1_INT & wdtIsrMask)) + { + wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER1_INT); + disableServicedIsr &= ~CY_SYS_WDT_COUNTER1_INT; + if(cySysWdtCallback[CY_SYS_WDT_COUNTER1] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER1])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + + if(0u != (CY_SYS_WDT_COUNTER2_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER2_INT & wdtIsrMask)) + { + if(cySysWdtCallback[CY_SYS_WDT_COUNTER2] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER2])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER2_INT); + } + } + + + /******************************************************************************* + * Function Name: CySysWatchdogFeed + ****************************************************************************//** + * \brief + * Feeds the corresponded Watchdog Counter before it causes the device reset. + * + * Supported only for first WDT0 and second WDT1 counters in the "Watchdog" or + * "Watchdog w/ Interrupts" modes. + * + * \param counterNum + * CY_SYS_WDT_COUNTER0 - Feeds the Counter 0
+ * CY_SYS_WDT_COUNTER1 - Feeds the Counter 1 + * + * Value of counterNum corresponds to appropriate counter. For example value 1 + * corresponds to second WDT1 Counter. + * + * \details + * Clears the WDT counter in the "Watchdog" mode or clears the WDT interrupt in + * "Watchdog w/ Interrupts" mode. Does nothing in other modes. + * + *******************************************************************************/ + void CySysWatchdogFeed(uint32 counterNum) + { + if(counterNum == CY_SYS_WDT_COUNTER0) + { + if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtResetCounters(CY_SYS_WDT_COUNTER0_RESET); + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + else + { + /* Do nothing. */ + } + } + else if(counterNum == CY_SYS_WDT_COUNTER1) + { + if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtResetCounters(CY_SYS_WDT_COUNTER1_RESET); + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + else + { + /* Do nothing. */ + } + } + else + { + /* Do nothing. */ + } + } + + + /******************************************************************************* + * Function Name: CySysClkLfclkPosedgeCatch + ****************************************************************************//** + * \internal + * Returns once the LFCLK positive edge occurred. + * + * CySysClkLfclkPosedgeRestore() should be called after this function + * to restore the WDT configuration. + * + * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() + * functions is expected to be called inside a critical section. + * + * To ensure that the WDT counter value is read until it changes, the enabled + * WDT counter is used. If no counter is enabled, counter 0 is enabled. + * And after the LFCLK source is switched, the counter 0 configuration + * is restored. + * + * Not applicable for the PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog + * Coprocessor devices. + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is + * called). Call CySysWdtUnlock() to unlock WDT. + * \endinternal + *******************************************************************************/ + static void CySysClkLfclkPosedgeCatch(void) + { + uint32 firstCount; + static uint32 lfclkPosedgeEnabledWdtCounter = 0u; + + if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + } + else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER1; + } + else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER2; + } + else /* All WDT counters are disabled */ + { + /* Configure WDT counter # 0 */ + lfclkPosedgeWdtCounter0Enabled = 1u; + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + + lfclkPosedgeWdtCounter0Mode = CySysWdtGetMode(CY_SYS_WDT_COUNTER0); + CySysWdtSetMode(CY_SYS_WDT_COUNTER0, CY_SYS_WDT_MODE_NONE); + CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK); + } + + firstCount = CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter); + while (CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter) == firstCount) + { + /* Wait for counter to increment */ + } + } + + + /******************************************************************************* + * Function Name: CySysClkLfclkPosedgeRestore + ****************************************************************************//** + * \internal + * Restores the WDT configuration after a CySysClkLfclkPosedgeCatch() call. + * + * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() + * functions is expected to be called inside a critical section. + * + * Not applicable for the PSoC 4000/PSoC 4000S / PSoC 4100S / PSoC Analog + * Coprocessor devices. + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is + * called). Call CySysWdtUnlock() to unlock WDT. + * + * \endinternal + *******************************************************************************/ + static void CySysClkLfclkPosedgeRestore(void) + { + if (lfclkPosedgeWdtCounter0Enabled != 0u) + { + /* Restore counter # 0 configuration and force its shutdown */ + CY_SYS_WDT_CONTROL_REG &= (uint32)(~CY_SYS_WDT_COUNTER0_MASK); + CySysWdtSetMode(CY_SYS_WDT_COUNTER0, lfclkPosedgeWdtCounter0Mode); + lfclkPosedgeWdtCounter0Enabled = 0u; + } + } + +#else + + /******************************************************************************* + * Function Name: CySysWdtGetEnabledStatus + ****************************************************************************//** + * + * \brief Reads the enabled status of the WDT counter. + * + * \return The status of the WDT counter: + * \return 0 - Counter is disabled + * \return 1 - Counter is enabled + * + *******************************************************************************/ + uint32 CySysWdtGetEnabledStatus(void) + { + return ((CY_SYS_WDT_DISABLE_KEY_REG == CY_SYS_WDT_KEY) ? (uint32) 0u : (uint32) 1u); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnable + ****************************************************************************//** + * + * \brief + * Enables watchdog timer reset generation. + * + * CySysWdtClearInterrupt() feeds the watchdog. Two unserviced interrupts lead + * to a system reset (i.e. at the third match). + * + * ILO is enabled by the hardware once WDT is started. + * + *******************************************************************************/ + void CySysWdtEnable(void) + { + CY_SYS_WDT_DISABLE_KEY_REG = 0u; + } + + + /******************************************************************************* + * Function Name: CySysWdtDisable + ****************************************************************************//** + * + * \brief Disables the WDT reset generation. + * + * This function unlocks the ENABLE bit in the CLK_ILO_CONFIG registers and + * enables the user to disable ILO. + * + *******************************************************************************/ + void CySysWdtDisable(void) + { + CY_SYS_WDT_DISABLE_KEY_REG = CY_SYS_WDT_KEY; + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter match comparison value. + * + * \param match Valid range [0-65535]. The value to be used to match against + * the counter. + * + *******************************************************************************/ + void CySysWdtSetMatch(uint32 match) + { + match &= CY_SYS_WDT_MATCH_MASK; + CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_MATCH_MASK)) | match; + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMatch + ****************************************************************************//** + * + * \brief Reads the WDT counter match comparison value. + * + * \return The counter match value. + * + *******************************************************************************/ + uint32 CySysWdtGetMatch(void) + { + return (CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_MATCH_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCount + ****************************************************************************//** + * + * \brief Reads the current WDT counter value. + * + * \return A live counter value. + * + *******************************************************************************/ + uint32 CySysWdtGetCount(void) + { + return ((uint32)CY_SYS_WDT_COUNTER_REG); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetIgnoreBits + ****************************************************************************//** + * + * \brief + * Configures the number of the MSB bits of the watchdog timer that are not + * checked against the match. + * + * \param bitsNum Valid range [0-15]. The number of the MSB bits. + * + * \details The value of bitsNum controls the time-to-reset of the watchdog + * (which happens after 3 successive matches). + * + *******************************************************************************/ + void CySysWdtSetIgnoreBits(uint32 bitsNum) + { + bitsNum = ((uint32)(bitsNum << CY_SYS_WDT_IGNORE_BITS_SHIFT) & CY_SYS_WDT_IGNORE_BITS_MASK); + CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_IGNORE_BITS_MASK)) | bitsNum; + } + + + /******************************************************************************* + * Function Name: CySysWdtGetIgnoreBits + ****************************************************************************//** + * + * \brief + * Reads the number of the MSB bits of the watchdog timer that are not + * checked against the match. + * + * \return The number of the MSB bits. + * + *******************************************************************************/ + uint32 CySysWdtGetIgnoreBits(void) + { + return((uint32)((CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_IGNORE_BITS_MASK) >> CY_SYS_WDT_IGNORE_BITS_SHIFT)); + } + + + /******************************************************************************* + * Function Name: CySysWdtClearInterrupt + ****************************************************************************//** + * + * \brief + * Feeds the watchdog. + * Cleans the WDT match flag which is set every time the WDT counter reaches a + * WDT match value. Two unserviced interrupts lead to a system reset + * (i.e. at the third match). + * + *******************************************************************************/ + void CySysWdtClearInterrupt(void) + { + CY_SYS_SRSS_INTR_REG |= CY_SYS_WDT_LOWER_BIT_MASK; + } + + + /******************************************************************************* + * Function Name: CySysWdtMaskInterrupt + ****************************************************************************//** + * + * \brief + * After masking interrupts from WDT, they are not passed to CPU. + * This function does not disable WDT reset generation. + * + *******************************************************************************/ + void CySysWdtMaskInterrupt(void) + { + CY_SYS_SRSS_INTR_MASK_REG &= (uint32)(~ (uint32)CY_SYS_WDT_LOWER_BIT_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtUnmaskInterrupt + ****************************************************************************//** + * + * \brief + * After unmasking interrupts from WDT, they are passed to CPU. + * This function does not impact the reset generation. + * + *******************************************************************************/ + void CySysWdtUnmaskInterrupt(void) + { + CY_SYS_SRSS_INTR_MASK_REG |= CY_SYS_WDT_LOWER_BIT_MASK; + } + + + /******************************************************************************* + * Function Name: CySysWdtSetIsrCallback + ****************************************************************************//** + * + * \brief + * Sets the ISR callback function for the WDT counter + * + * \param function The pointer to the callback function. + * + * \return The pointer to a previous callback function. + * + *******************************************************************************/ + cyWdtCallback CySysWdtSetInterruptCallback(cyWdtCallback function) + { + cyWdtCallback prevCallback = (void *)0; + + prevCallback = cySysWdtCallback; + cySysWdtCallback = function; + + return(prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetIsrCallback + ****************************************************************************//** + * + * \brief + * Gets the ISR callback function for the WDT counter + * + * \return The pointer to the callback function registered for WDT. + * + *******************************************************************************/ + cyWdtCallback CySysWdtGetInterruptCallback(void) + { + return(cySysWdtCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtIsr + ****************************************************************************//** + * + * \brief + * This is the handler of the WDT interrupt in CPU NVIC. + * + * The handler calls the respective callback functions configured by the user + * by using CySysWdtSetIsrCallback() API. + * + * + * \details + * This function clears the WDT interrupt every time when it is called. + * Reset after the 3rd interrupt does not happen if this function is registered + * as the interrupt handler even if the "Watchdog with Interrupt" mode is + * selected on the "Low Frequency Clocks" tab. + * + *******************************************************************************/ + void CySysWdtIsr(void) + { + if(cySysWdtCallback != (void *) 0) + { + (void)(cySysWdtCallback)(); + } + + CySysWdtClearInterrupt(); + } + +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + +/******************************************************************************* +* Function Name: CySysClkGetTimerSource +******************************************************************************** +* +* \brief Gets the clock source for the DeepSleep Timers. +* +* The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor. +* +* \return The DeepSleep Timer source +* CY_SYS_CLK_TIMER_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) +* CY_SYS_CLK_TIMER_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) +* +*******************************************************************************/ + static uint32 CySysClkGetTimerSource(void) + { + uint32 timerSource; + timerSource = CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK; + return (timerSource); + } + + +/******************************************************************************* +* Function Name: CySysClkSetTimerSource +****************************************************************************//** +* +* \brief Sets the clock source for the DeepSleep Timers. +* +* The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor +* devices. +* +* \param source +* CY_SYS_CLK_TIMER_SRC_ILO - Internal Low Frequency (32 kHz) Oscillator +* (ILO).
+* CY_SYS_CLK_TIMER_SRC_WCO - Low Frequency Watch Crystal Oscillator +* (WCO). +* +* \details Both the current source and the new source must be running and stable +* before calling this function. +* +* \warning DeepSleep Timer reset is required if Timer source was switched while +* DeepSleep Timers were running. Call CySysTimerResetCounters() API after +* Timer source switching. +* It is highly recommended to disable DeepSleep Timers before Timer source +* switching. Changing the Timer source may change the functionality that uses +* this Timers as clock source. +*******************************************************************************/ + void CySysClkSetTimerSource(uint32 source) + { + uint8 interruptState; + + if (CySysClkGetTimerSource() != source) + { + + /* Reset both _EN bits in WCO_WDT_CLKEN register */ + CY_SYS_WCO_WDT_CLKEN_REG &= ~CY_SYS_WCO_WDT_CLKEN_RESET_MASK; + + /* Wait 4 new clock source-cycles for change to come into effect */ + CyDelayUs(CY_SYS_4TIMER_DELAY_US); + + interruptState = CyEnterCriticalSection(); + CY_SYS_WCO_WDT_CONFIG_REG = (CY_SYS_WCO_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_TIMER_SEL_MASK)) | + (source & CY_SYS_CLK_TIMER_SEL_MASK); + CyExitCriticalSection(interruptState); + } + + CY_SYS_WCO_WDT_CLKEN_REG = (CY_SYS_WCO_WDT_CLKEN_REG & (uint32)(~CY_SYS_WCO_WDT_CLKEN_RESET_MASK)) | + CY_SYS_SET_CURRENT_TIMER_SOURCE_BIT; + } + + + /******************************************************************************* + * Function Name: CySysTimerGetEnabledStatus + ****************************************************************************//** + * + * \brief Reads the enabled status of one of the three DeepSleep Timer + * counters. + * + * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer + * counter. + * + * \return The status of the Timers counter: + * \return 0 - If the Counter is disabled. + * \return 1 - If the Counter is enabled. + * + * \details + * This function returns an actual DeepSleep Timer counter status from the + * status register. It may take up to 3 LFCLK cycles for the Timer status + * register to contain actual data after the Timer counter is enabled. + * + *******************************************************************************/ + uint32 CySysTimerGetEnabledStatus(uint32 counterNum) + { + CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); + return ((CY_SYS_WCO_WDT_CONTROL_REG >> ((CY_SYS_TIMER_CNT_SHIFT * counterNum) + + CY_SYS_TIMER_CNT_STTS_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetMode + ****************************************************************************//** + * + * \brief Writes the mode of one of the three DeepSleep Timer counters. + * + * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer + * counter. + * + * \param mode + * CY_SYS_TIMER_MODE_NONE - Free running.
+ * CY_SYS_TIMER_MODE_INT - The interrupt generated on match for counter 0 + * and 1, and on bit toggle for counter 2. + * + * \details + * DeepSleep Timer counter counterNum should be disabled to set a mode. + * Otherwise, this function call has no effect. If the specified counter is + * enabled, call the CySysTimerDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. + * + *******************************************************************************/ + void CySysTimerSetMode(uint32 counterNum, uint32 mode) + { + uint32 configRegValue; + + CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); + + CYASSERT(mode <= CY_SYS_TIMER_MODE_MASK); + + if(0u == CySysTimerGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & + (uint32)~((uint32)(CY_SYS_TIMER_MODE_MASK << (counterNum * CY_SYS_TIMER_CNT_SHIFT))); + configRegValue |= (uint32)((mode & CY_SYS_TIMER_MODE_MASK) << (counterNum * CY_SYS_TIMER_CNT_SHIFT)); + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetMode + ****************************************************************************//** + * + * \brief Reads the mode of one of the three DeepSleep Timer counters. + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * \return The mode of the counter. The same enumerated values as the mode + * parameter used in CySysTimerSetMode(). + * + *******************************************************************************/ + uint32 CySysTimerGetMode(uint32 counterNum) + { + return ((CY_SYS_WCO_WDT_CONFIG_REG >> (counterNum * CY_SYS_TIMER_CNT_SHIFT)) & CY_SYS_TIMER_MODE_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetClearOnMatch + ****************************************************************************//** + * + * \brief Configures the DeepSleep Timer counter "clear on match" setting. + * + * If configured to "clear on match", the counter counts from 0 to MatchValue + * giving it a period of (MatchValue + 1). + * + * \param counterNum + * Valid range [0-1]. The number of the Timer counter. The match values are not + * supported by counter 2. + * \param enable 0 to disable appropriate counter
+ * 1 to enable appropriate counter + * + * \details + * Timer counter counterNum should be disabled. Otherwise this function call + * has no effect. If the specified counter is enabled, call the CySysTimerDisable() + * function with the corresponding parameter to disable the specified counter and + * wait for it to stop. This may take up to three Timer source-cycles. + * + *******************************************************************************/ + void CySysTimerSetClearOnMatch(uint32 counterNum, uint32 enable) + { + uint32 configRegValue; + + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + if(0u == CySysTimerGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << + ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT))); + + configRegValue + |= (uint32)(enable << ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT)); + + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetClearOnMatch + ****************************************************************************//** + * + * \brief Reads the "clear on match" setting for the specified DeepSleep Timer + * counter. + * + * \param counterNum Valid range [0-1]. The number of the Timer counter. The + * match values are not supported by counter 2. + * + * \return The "clear on match" status:
1 if enabled
0 if disabled + * + *******************************************************************************/ + uint32 CySysTimerGetClearOnMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + return (uint32)((CY_SYS_WCO_WDT_CONFIG_REG >> + ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTimerEnable + ****************************************************************************//** + * + * \brief Enables the specified DeepSleep Timer counters. All the counters + * specified in the mask are enabled. + * + * \param counterMask CY_SYS_TIMER0_MASK - The mask for counter 0 to enable.
+ * CY_SYS_TIMER1_MASK - The mask for counter 1 to enable.
+ * CY_SYS_TIMER2_MASK - The mask for counter 2 to enable. + * + * \details + * Enabling or disabling Timer requires 3 Timer source-cycles to come into effect. + * Therefore, the Timer enable state must not be changed more than once in + * that period. + * + * After Timer is enabled, it is illegal to write Timer configuration + * (WCO_WDT_CONFIG) and control (WCO_WDT_CONTROL) registers. This means that all + * Timer functions that contain 'write' in the name (with the exception of + * CySysTimerSetMatch() function) are illegal to call once Timer enabled. + * + * Timer current source must be running and stable before calling this + * function. + * + *******************************************************************************/ + void CySysTimerEnable(uint32 counterMask) + { + CY_SYS_WCO_WDT_CONTROL_REG |= counterMask; + + if(0u != (counterMask & CY_SYS_TIMER0_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER1_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER2_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + /* Wait for changes to come into effect */ + } + } + } + + + /******************************************************************************* + * Function Name: CySysTimerDisable + ****************************************************************************//** + * + * \brief Disables the specified DeepSleep Timer counters. + * + * All the counters specified in the mask are disabled. The function waits for + * the changes to come into effect. + * + * \param counterMask + * CY_SYS_TIMER0_MASK - The mask for Counter 0 to disable.
+ * CY_SYS_TIMER1_MASK - The mask for Counter 1 to disable.
+ * CY_SYS_TIMER2_MASK - The mask for Counter 2 to disable. + * + *******************************************************************************/ + void CySysTimerDisable(uint32 counterMask) + { + + CY_SYS_WCO_WDT_CONTROL_REG &= ~counterMask; + + if(0u != (counterMask & CY_SYS_TIMER0_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER1_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER2_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + /* Wait for changes to come into effect */ + } + } + + } + + + /******************************************************************************* + * Function Name: CySysTimerSetCascade + ****************************************************************************//** + * + * \brief + * Writes the two DeepSleep Timers cascade values based on the combination of + * mask values specified. + * + * \param cascadeMask The mask value used to set or clear the cascade values: + * CY_SYS_TIMER_CASCADE_NONE - Neither
+ * CY_SYS_TIMER_CASCADE_01 - Cascade 01
+ * CY_SYS_TIMER_CASCADE_12 - Cascade 12 + * + * If only one cascade mask is specified, the second cascade is disabled. + * To set both cascade modes, two defines should be ORed: + * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). + * \note If CySysTimerSetCascade() was called with ORed defines it is necessary + * to call CySysTimeSetClearOnMatch(1,1). It is needed to make sure that + * Counter 2 will be updated in the expected way. + * + * Timer counters that are part of the specified cascade should be disabled. + * Otherwise this function call has no effect. If the specified + * counter is enabled, call CySysTimerDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. This may + * take up to 3 Timers source-cycles. + * + *******************************************************************************/ + void CySysTimerSetCascade(uint32 cascadeMask) + { + uint32 configRegValue; + uint32 countersEnableStatus; + + countersEnableStatus = CySysTimerGetEnabledStatus(CY_SYS_TIMER0) | + CySysTimerGetEnabledStatus(CY_SYS_TIMER1) | + CySysTimerGetEnabledStatus(CY_SYS_TIMER2); + + if (0u == countersEnableStatus) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; + configRegValue &= ((uint32)(~(CY_SYS_TIMER_CASCADE_01|CY_SYS_TIMER_CASCADE_12))); + configRegValue |= cascadeMask; + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetCascade + ****************************************************************************//** + * + * \brief Reads the two DeepSleep Timer cascade values returning a mask of the + * bits set. + * + * \return The mask of the cascade values set. + * \return CY_SYS_TIMER_CASCADE_NONE - Neither + * \return CY_SYS_TIMER_CASCADE_01 - Cascade 01 + * \return CY_SYS_TIMER_CASCADE_12 - Cascade 12 + * + *******************************************************************************/ + uint32 CySysTimerGetCascade(void) + { + return (CY_SYS_WCO_WDT_CONFIG_REG & (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12)); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetMatch + ****************************************************************************//** + * + * \brief Configures the Timer counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the Timer counter. The + * match values are not supported by counter 2. + * + * \param match Valid range [0-65535]. The value to be used to match against + * the counter. + * + *******************************************************************************/ + void CySysTimerSetMatch(uint32 counterNum, uint32 match) + { + uint32 regValue; + + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + /* Wait for previous changes to come into effect */ + CyDelayUs(CY_SYS_3TIMER_DELAY_US); + + regValue = CY_SYS_WCO_WDT_MATCH_REG; + regValue &= (uint32)~((uint32)(CY_SYS_TIMER_LOWER_16BITS_MASK << (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT))); + CY_SYS_WCO_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT))); + + /* Make sure match synchronization has started */ + CyDelayUs(CY_SYS_1TIMER_DELAY_US); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetToggleBit + ****************************************************************************//** + * + * \brief Configures which bit in Timer counter 2 to monitor for a toggle. + * + * When that bit toggles, an interrupt is generated if mode for counter 2 has + * enabled interrupts. + * + * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. + * + * \details Timer counter 2 should be disabled. Otherwise this function call has + * no effect. + * + * If the specified counter is enabled, call the CySysTimerDisable() function with + * the corresponding parameter to disable the specified counter and wait for it to + * stop. This may take up to three Timer source-cycles. + * + *******************************************************************************/ + void CySysTimerSetToggleBit(uint32 bits) + { + uint32 configRegValue; + + if (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; + configRegValue &= (uint32)(~((uint32)(CY_SYS_TIMER_CONFIG_BITS2_MASK << CY_SYS_TIMER_CONFIG_BITS2_POS))); + configRegValue |= ((bits & CY_SYS_TIMER_CONFIG_BITS2_MASK) << CY_SYS_TIMER_CONFIG_BITS2_POS); + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetToggleBit + ****************************************************************************//** + * + * \brief Reads which bit in Timer counter 2 is monitored for a toggle. + * + * \return The bit that is monitored (range of 0 to 31) + * + *******************************************************************************/ + uint32 CySysTimerGetToggleBit(void) + { + return ((CY_SYS_WCO_WDT_CONFIG_REG >> CY_SYS_TIMER_CONFIG_BITS2_POS) & CY_SYS_TIMER_CONFIG_BITS2_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetMatch + ****************************************************************************//** + * + * \brief Reads the Timer counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the DeepSleep Timer + * counter. The match values are not supported by counter 2. + * + * \return A 16-bit match value. + * + *******************************************************************************/ + uint32 CySysTimerGetMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + return ((uint32)(CY_SYS_WCO_WDT_MATCH_REG >> (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT)) & + CY_SYS_TIMER_LOWER_16BITS_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetCount + ****************************************************************************//** + * + * \brief Reads the current DeepSleep Timer counter value. + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters + * and counter 2 is a 32 bit counter. + * + *******************************************************************************/ + uint32 CySysTimerGetCount(uint32 counterNum) + { + uint32 regValue = 0u; + + switch(counterNum) + { + /* Timer Counter 0 */ + case 0u: + regValue = CY_SYS_WCO_WDT_CTRLOW_REG & CY_SYS_TIMER_LOWER_16BITS_MASK; + break; + + /* Timer Counter 1 */ + case 1u: + regValue = (CY_SYS_WCO_WDT_CTRLOW_REG >> CY_SYS_TIMER_CNT_MATCH_SHIFT) & CY_SYS_TIMER_LOWER_16BITS_MASK; + break; + + /* Timer Counter 2 */ + case 2u: + regValue = CY_SYS_WCO_WDT_CTRHIGH_REG; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + return (regValue); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetInterruptSource + ****************************************************************************//** + * + * \brief + * Reads a mask containing all the DeepSleep Timer counters interrupts that are + * currently set by the hardware, if a corresponding mode is selected. + * + * \return The mask of interrupts set + * \return CY_SYS_TIMER0_INT - Set interrupt for Counter 0 + * \return CY_SYS_TIMER1_INT - Set interrupt for Counter 1 + * \return CY_SYS_TIMER2_INT - Set interrupt for Counter 2 + * + *******************************************************************************/ + uint32 CySysTimerGetInterruptSource(void) + { + return (CY_SYS_WCO_WDT_CONTROL_REG & (CY_SYS_TIMER0_INT | CY_SYS_TIMER1_INT | CY_SYS_TIMER2_INT)); + } + + + /******************************************************************************* + * Function Name: CySysTimerClearInterrupt + ****************************************************************************//** + * + * \brief Clears all the DeepSleep Timer counter interrupts set in the mask. + * + * All the Timer interrupts are to be cleared by the firmware, otherwise + * interrupts are generated continuously. + * + * \param counterMask + * CY_SYS_TIMER0_INT - Clear counter 0
+ * CY_SYS_TIMER1_INT - Clear counter 1
+ * CY_SYS_TIMER2_INT - Clear counter 2 + * + *******************************************************************************/ + void CySysTimerClearInterrupt(uint32 counterMask) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + /* Set new WCO_TIMER control register value */ + counterMask &= (CY_SYS_TIMER0_INT | + CY_SYS_TIMER1_INT | + CY_SYS_TIMER2_INT); + + CY_SYS_WCO_WDT_CONTROL_REG = counterMask | (CY_SYS_WCO_WDT_CONTROL_REG & ~(CY_SYS_TIMER0_INT | + CY_SYS_TIMER1_INT | + CY_SYS_TIMER2_INT)); + + /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. + * Cypress ID #207093, #206231 + */ + (void)CY_SYS_WCO_WDT_CONTROL_REG; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetInterruptCallback + ****************************************************************************//** + * + * \brief + * Sets the ISR callback function for the particular DeepSleep Timer counter. + * + * These functions are called on the Timer interrupt. + * + * \param counterNum The number of the Timer counter. + * \param function The pointer to the callback function. + * + * \return The pointer to the previous callback function. + * \return NULL is returned if the specified address is not set. + * + *******************************************************************************/ + cyTimerCallback CySysTimerSetInterruptCallback(uint32 counterNum, cyTimerCallback function) + { + cyTimerCallback prevCallback = (void *)0; + + if(counterNum < CY_SYS_NUM_OF_TIMERS) + { + prevCallback = cySysTimerCallback[counterNum]; + cySysTimerCallback[counterNum] = function; + } + else + { + CYASSERT(0u != 0u); + } + + return((cyTimerCallback)prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetInterruptCallback + ****************************************************************************//** + * + * \brief Gets the ISR callback function for the particular DeepSleep Timer + * counter. + * + * \param counterNum The number of the Timer counter. + * + * \return + * The pointer to the callback function registered for a particular Timer by + * a particular address that are passed through arguments. + * + *******************************************************************************/ + cyTimerCallback CySysTimerGetInterruptCallback(uint32 counterNum) + { + cyTimerCallback retCallback = (void *)0; + + if(counterNum < CY_SYS_NUM_OF_TIMERS) + { + retCallback = (cyTimerCallback)cySysTimerCallback[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + + return(retCallback); + } + + + /******************************************************************************* + * Function Name: CySysTimerEnableIsr + ****************************************************************************//** + * + * \brief Enables the ISR callback servicing for the particular Timer counter + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * Value corresponds to appropriate Timer counter. For example value 1 + * corresponds to second Timer counter. + * + *******************************************************************************/ + void CySysTimerEnableIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_TIMER2) + { + disableTimerServicedIsr &= ~counterTimerIntMaskTbl[counterNum]; + timerIsrMask |= counterTimerIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerDisableIsr + ****************************************************************************//** + * + * \brief Disables the ISR callback servicing for the particular Timer counter + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + *******************************************************************************/ + void CySysTimerDisableIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_TIMER2) + { + timerIsrMask &= ~counterTimerIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerIsr + ****************************************************************************//** + * + * \brief This is the handler of the DeepSleep Timer interrupt in CPU NVIC. + * + * The handler checks which Timer triggered in the interrupt and calls the + * respective callback functions configured by the user by using + * CySysTimerSetIsrCallback() API. + * + * The order of the callback execution is incremental. Callback-0 is + * run as the first one and callback-2 is called as the last one. + * + * \details This function clears the DeepSleep Timer interrupt every time when + * it is called. + * + *******************************************************************************/ + void CySysTimerIsr(void) + { + if(0u != (CY_SYS_TIMER0_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER0_INT & timerIsrMask)) + { + timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER0_INT); + disableTimerServicedIsr &= ~CY_SYS_TIMER0_INT; + if(cySysTimerCallback[CY_SYS_TIMER0] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER0])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER0_INT); + } + + if(0u != (CY_SYS_TIMER1_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER1_INT & timerIsrMask)) + { + timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER1_INT); + disableTimerServicedIsr &= ~CY_SYS_TIMER1_INT; + if(cySysTimerCallback[CY_SYS_TIMER1] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER1])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER1_INT); + } + + if(0u != (CY_SYS_TIMER2_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER2_INT & timerIsrMask)) + { + if(cySysTimerCallback[CY_SYS_TIMER2] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER2])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER2_INT); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerResetCounters + ****************************************************************************//** + * + * \brief Resets all the Timer counters set in the mask. + * + * \param countersMask + * CY_SYS_TIMER0_RESET - Reset the Counter 0
+ * CY_SYS_TIMER1_RESET - Reset the Counter 1
+ * CY_SYS_TIMER2_RESET - Reset the Counter 2 + * + * \details + * This function waits while corresponding counters will be reset. This may + * take up to 3 DeepSleep Timer source-cycles. DeepSleep Timer source must be + * enabled. Otherwise, the function will never exit. + * + *******************************************************************************/ + void CySysTimerResetCounters(uint32 countersMask) + { + /* Set new Timer reset value */ + CY_SYS_WCO_WDT_CONTROL_REG |= (countersMask & CY_SYS_TIMER_RESET); + + while (0uL != (CY_SYS_WCO_WDT_CONTROL_REG & CY_SYS_TIMER_RESET)) + { + /* Wait for reset to come into effect */ + } + } +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + + +#if(CY_IP_SRSSV2 || (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT)) + /******************************************************************************* + * Function Name: CySysTimerDelay + ****************************************************************************//** + * + * \brief + * The function implements the delay specified in the LFCLK clock ticks. + * + * This API is applicable for PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / + * PSoC 4200 BLE / PRoC BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to + * use WDT. Also this API is available to use for PSoC4100S and / PSoC Analog + * Coprocessor devices to use DeepSleep Timers. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The specified WDT counter should be configured as described below and started. + * + * For PSoC 4100S / PSoC Analog Coprocessor devices: + * The specified DeepSleep Timer counter should be configured as described below + * and started. + * + * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In + * the "WAIT" mode, the function waits for the specified number of ticks. In the + * "INTERRUPT" mode, the interrupt is generated after the specified number of + * ticks. + * + * For the correct function operation, the "Clear On Match" option should be + * disabled for the specified WDT or DeepSleep Timer counter. Use + * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep + * Timer function with the "enable" parameter equal to zero for the used WDT + * counter or DeepSleep Timer counter. + * + * The corresponding WDT counter should be configured to match the selected + * mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. + * + * Or the corresponding DeepSleep Timer counter should be configured to match the + * selected mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" for the "INTERRUPT" mode. + * + * This can be configured in two ways: + * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." + * button, in the "Configure System Clocks" window click on the + * "Low Frequency Clocks" tab and choose the appropriate option for the used + * WDT or DeepSleep Timer counter. + * + * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep + * Timer function. Call it with the appropriate "mode" parameter for the + * used WDT or DeepSleep Timer counter. + * + * For the "INTERRUPT" mode, the recommended sequence is the following: + * - Call the CySysWdtDisableCounterIsr() for WDT or + * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing + * interrupts of the specified WDT or DeepSleep Timer counter. + * + * - Call the CySysWdtSetInterruptCallback() for WDT or + * CySysTimerSetIsrCallback() for DeepSleep Timer function to register + * the callback function for the corresponding WDT or DeepSleep Timer counter. + * + * - Call the CySysTimerDelay() function. + * + * \param counterNum Valid range [0-1]. The number of the counter + * (Timer0 or Timer1). + * \param delayType + * CY_SYS_TIMER_WAIT - "WAIT" mode.
+ * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. + * \param delay The delay value in the LFCLK ticks + * (allowable range - 16-bit value). + * + * \details + * In the "INTERRUPT" mode, this function enables ISR callback servicing + * from the corresponding WDT or DeepSleep Timer counter. Servicing of this ISR + * callback will be disabled after the expiration of the delay time. + * + *******************************************************************************/ + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay) + { + uint32 regValue; + uint32 matchValue; + + #if(CY_IP_SRSSV2) + if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) && + (delay <= CY_SYS_UINT16_MAX_VAL)) + { + regValue = CySysWdtGetCount(counterNum); + matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; + + CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) + if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && + (delay <= CY_SYS_UINT16_MAX_VAL)) + { + regValue = CySysTimerGetCount(counterNum); + matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; + + CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_WCO_WDT_EN) */ + } + + + /******************************************************************************* + * Function Name: CySysTimerDelayUntilMatch + ****************************************************************************//** + * + * \brief + * The function implements the delay specified as the number of WDT or DeepSleep + * Timer clock source ticks between WDT or DeepSleep Timer current value and + * match" value. + * + * This API is applicable for PSoC 4100 / PSoC 4200 / PRoC BLE / PSoC 4100 BLE / + * PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to use WDT. + * Also this API is available to use for PSoC4100S / Analog Coprocessor devices + * to use DeepSleep Timers. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The function implements the delay specified as the number of LFCLK ticks + * between the specified WDT counter's current value and the "match" + * passed as the parameter to this function. The current WDT counter value can + * be obtained using the CySysWdtGetCount() function. + * + * For PSoC4100 S and Analog Coprocessor devices: + * The function implements the delay specified as the number of DeepSleep Timer + * input clock ticks for Timer0/Timer1 counter's current value and the "match" + * passed as the parameter to this function. The current DeepSleep Timer counter + * value can be obtained using the CySysWdtGetCount() function. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The specified WDT counter should be configured as described below and started. + * + * For PSoC PSoC 4100S / PSoC Analog Coprocessor devices: + * The specified DeepSleep Timer counter should be configured as described below + * and started. + * + * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In + * the "WAIT" mode, the function waits for the specified number of ticks. In the + * "INTERRUPT" mode, the interrupt is generated after the specified number of + * ticks. + * + * For the correct function operation, the "Clear On Match" option should be + * disabled for the specified WDT or DeepSleep Timer counter. Use + * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep + * Timer function with the "enable" parameter equal to zero for the used WDT + * or DeepSleep Timer counter. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M/PSoC 4200M devices: + * The corresponding WDT counter should be configured to match the selected + * mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. + * + * For PSoC 4100S / PSoC Analog Coprocessor devices: + * Corresponding DeepSleep Timer counter should be configured to match the + * selected mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" for the "INTERRUPT" mode. + * + * This can be configured in two ways: + * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." + * button, in the "Configure System Clocks" window click on the + * "Low Frequency Clocks" tab and choose the appropriate option for the used + * WDT or DeepSleep Timer counter. + * + * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep + * Timer function. Call it with the appropriate "mode" parameter for the + * used WDT or DeepSleep Timer counter. + * + * For the "INTERRUPT" mode, the recommended sequence is the following: + * - Call the CySysWdtDisableCounterIsr() for WDT or + * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing + * interrupts of the specified WDT or DeepSleep Timer counter. + * + * - Call the CySysWdtSetInterruptCallback() for WDT or + * CySysTimerSetInterruptCallback() for DeepSleep Timer function to register + * the callback function for the corresponding WDT or DeepSleep Timer counter. + * + * - Call the CySysTimerDelay() function. + * + * \param counterNum Valid range [0-1]. The number of the WDT or DeepSleep + * Timer. + * counter (Timer0 or Timer1). + * \param delayType CY_SYS_TIMER_WAIT - "WAIT" mode.
+ * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. + * \param delay The delay value in the LFCLK ticks + * (allowable range - 16-bit value). + * + * \details + * In the "INTERRUPT" mode, this function enables ISR callback servicing + * from the corresponding WDT counter. Servicing of this ISR callback will be + * disabled after the expiration of the delay time. + * + *******************************************************************************/ + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match) + { + uint32 tmpValue; + + #if(CY_IP_SRSSV2) + if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) && + (match <= CY_SYS_UINT16_MAX_VAL)) + { + if(delayType == CY_SYS_TIMER_WAIT) + { + do + { + tmpValue = CySysWdtGetCount(counterNum); + }while(tmpValue > match); + + do + { + tmpValue = CySysWdtGetCount(counterNum); + }while(tmpValue < match); + } + else + { + tmpValue = counterIntMaskTbl[counterNum]; + CySysWdtSetMatch(counterNum, match); + + disableServicedIsr |= tmpValue; + wdtIsrMask |= tmpValue; + } + } + else + { + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) + if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && + (match <= CY_SYS_UINT16_MAX_VAL)) + { + if(delayType == CY_SYS_TIMER_WAIT) + { + do + { + tmpValue = CySysTimerGetCount(counterNum); + }while(tmpValue > match); + + do + { + tmpValue = CySysTimerGetCount(counterNum); + }while(tmpValue < match); + } + else + { + tmpValue = counterTimerIntMaskTbl[counterNum]; + CySysTimerSetMatch(counterNum, match); + + disableTimerServicedIsr |= tmpValue; + timerIsrMask |= tmpValue; + } + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) */ + } + +#endif /* (CY_IP_SRSSV2 || (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLFClk.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLFClk.h new file mode 100644 index 0000000..c3bf4f7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLFClk.h @@ -0,0 +1,724 @@ +/***************************************************************************//** +* \file .h +* \version 1.20 +* +* \brief +* This file provides the source code to API for the lfclk and wdt. +* +******************************************************************************** +* \copyright +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_LFCLK_CYLIB_H) +#define CY_LFCLK_CYLIB_H + +#include "cytypes.h" +#include "cydevice_trm.h" + +#define CY_IP_WCO_WDT_EN (-1 == 1) + +typedef enum +{ + CY_SYS_TIMER_WAIT = 0u, + CY_SYS_TIMER_INTERRUPT = 1u +} cy_sys_timer_delaytype_enum; + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +/* Clocks API */ +void CySysClkIloStart(void); +void CySysClkIloStop(void); +/** @} general */ + +/** +* \addtogroup group_compensate +* @{ +*/ +cystatus CySysClkIloCompensate(uint32 desiredDelay, uint32 *compensatedCycles); +void CySysClkIloStartMeasurement(void); +void CySysClkIloStopMeasurement(void); +/** @} compensate */ + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + /** + * \addtogroup group_compensate + * @{ + */ + cystatus CySysClkIloTrim(uint32 mode, int32 *iloAccuracyInPPT); + cystatus CySysClkIloRestoreFactoryTrim(void); + /** @} compensate */ + cystatus CySysClkIloUpdateTrimReg(int32* iloAccuracyInPPT); +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + +#if(CY_IP_SRSSV2 && CY_IP_WCO) + /** + * \addtogroup group_general + * @{ + */ + void CySysClkSetLfclkSource(uint32 source); + /** @} group_general */ +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + +#if (CY_IP_WCO) + /** + * \addtogroup group_wco + * @{ + */ + void CySysClkWcoStart(void); + void CySysClkWcoStop(void); + uint32 CySysClkWcoSetPowerMode(uint32 mode); + void CySysClkWcoClockOutSelect(uint32 clockSel); + /** @} wco */ + + uint32 CySysClkWcoEnabled(void); + +#endif /* (CY_IP_WCO) */ + +typedef void (*cyWdtCallback)(void); + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + typedef void (*cyTimerCallback)(void); +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +#if(CY_IP_SRSSV2) + /** + * \addtogroup group_wdtsrssv2 + * @{ + */ + /* WDT API */ + void CySysWdtLock(void); + void CySysWdtUnlock(void); + void CySysWdtSetMode(uint32 counterNum, uint32 mode); + uint32 CySysWdtGetMode(uint32 counterNum); + uint32 CySysWdtGetEnabledStatus(uint32 counterNum); + void CySysWdtSetClearOnMatch(uint32 counterNum, uint32 enable); + uint32 CySysWdtGetClearOnMatch(uint32 counterNum); + void CySysWdtEnable(uint32 counterMask); + void CySysWdtDisable(uint32 counterMask); + void CySysWdtSetCascade(uint32 cascadeMask); + uint32 CySysWdtGetCascade(void); + void CySysWdtSetMatch(uint32 counterNum, uint32 match); + void CySysWdtSetToggleBit(uint32 bits); + uint32 CySysWdtGetToggleBit(void); + uint32 CySysWdtGetMatch(uint32 counterNum); + uint32 CySysWdtGetCount(uint32 counterNum); + uint32 CySysWdtGetInterruptSource(void); + void CySysWdtClearInterrupt(uint32 counterMask); + void CySysWdtResetCounters(uint32 countersMask); + cyWdtCallback CySysWdtSetInterruptCallback(uint32 counterNum, cyWdtCallback function); + cyWdtCallback CySysWdtGetInterruptCallback(uint32 counterNum); + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay); + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match); + void CySysWatchdogFeed(uint32 counterNum); + void CySysWdtEnableCounterIsr(uint32 counterNum); + void CySysWdtDisableCounterIsr(uint32 counterNum); + void CySysWdtIsr(void); + /** @} wdtsrssv2 */ +#else + /** + * \addtogroup group_wdtsrsslite + * @{ + */ + /* WDT API */ + uint32 CySysWdtGetEnabledStatus(void); + void CySysWdtEnable(void); + void CySysWdtDisable(void); + void CySysWdtSetMatch(uint32 match); + uint32 CySysWdtGetMatch(void); + uint32 CySysWdtGetCount(void); + void CySysWdtSetIgnoreBits(uint32 bitsNum); + uint32 CySysWdtGetIgnoreBits(void); + void CySysWdtClearInterrupt(void); + void CySysWdtMaskInterrupt(void); + void CySysWdtUnmaskInterrupt(void); + cyWdtCallback CySysWdtSetInterruptCallback(cyWdtCallback function); + cyWdtCallback CySysWdtGetInterruptCallback(void); + void CySysWdtIsr(void); + /** @} wdtsrsslite*/ +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + /** + * \addtogroup group_deepsleepwdt + * @{ + */ + /* WCO WDT APIs */ + void CySysClkSetTimerSource(uint32 source); + void CySysTimerSetMode(uint32 counterNum, uint32 mode); + uint32 CySysTimerGetMode(uint32 counterNum); + uint32 CySysTimerGetEnabledStatus(uint32 counterNum); + void CySysTimerSetClearOnMatch(uint32 counterNum, uint32 enable); + uint32 CySysTimerGetClearOnMatch(uint32 counterNum); + void CySysTimerEnable(uint32 counterMask); + void CySysTimerDisable(uint32 counterMask); + void CySysTimerSetCascade(uint32 cascadeMask); + uint32 CySysTimerGetCascade(void); + void CySysTimerSetMatch(uint32 counterNum, uint32 match); + void CySysTimerSetToggleBit(uint32 bits); + uint32 CySysTimerGetToggleBit(void); + uint32 CySysTimerGetMatch(uint32 counterNum); + uint32 CySysTimerGetCount(uint32 counterNum); + uint32 CySysTimerGetInterruptSource(void); + void CySysTimerClearInterrupt(uint32 counterMask); + cyTimerCallback CySysTimerSetInterruptCallback(uint32 counterNum, cyTimerCallback function); + cyTimerCallback CySysTimerGetInterruptCallback(uint32 counterNum); + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay); + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match); + void CySysTimerResetCounters(uint32 countersMask); + void CySysTimerEnableIsr(uint32 counterNum); + void CySysTimerDisableIsr(uint32 counterNum); + void CySysTimerIsr(void); + /** @} deepsleepwdt */ +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + + +/******************************************************************************* +* API Constants +*******************************************************************************/ +#define CY_SYS_UINT16_MAX_VAL (0xFFFFu) + + +/******************************************************************************* +* Clock API Constants +*******************************************************************************/ + +/* CySysClkIloStart()/CySysClkIloStop() - implementation definitions */ +#define CY_SYS_CLK_ILO_CONFIG_ENABLE ((uint32)(( uint32 )0x01u << 31u)) +#define CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK ((uint32)(( uint32 )0x0fu << 8u )) + +/* CySysClkIloCompensate() - one ILO clock in uS multiplied on thousand */ +#if (CY_IP_SRSSV2) + #define CY_SYS_CLK_ILO_PERIOD_PPH ((uint32) (0x0C35u)) +#else + #define CY_SYS_CLK_ILO_PERIOD_PPH ((uint32) (0x09C4u)) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkIloCompensate() - implementation definitions */ +#define CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK ((uint32)(( uint32 )0x01u << 31u)) +#define CY_SYS_CLK_ILO_DFT_LSB_MASK ((uint32)(0x00000FFFu)) +#define CY_SYS_CLK_TRIM_OR_COMP_STARTED (1u) +#define CY_SYS_CLK_TRIM_OR_COMP_FINISHED (0u) +#define CY_SYS_CLK_COEF_PHUNDRED ((uint32) (0x64u)) +#define CY_SYS_CLK_HALF_OF_CLOCK ((uint32) ((uint32) CY_SYS_CLK_ILO_PERIOD_PPH >> 2u)) + +/* CySysClkIloCompensate() - maximum value of desiredDelay argument */ +#if (CY_IP_SRSSV2) + #define CY_SYS_CLK_MAX_DELAY_US ((uint32) (0xEE6B2800u)) + #define CY_SYS_CLK_ILO_PERIOD ((uint32) (0x1Fu)) + #define CY_SYS_CLK_ILO_FREQ_2MSB ((uint32) 5u) +#else + #define CY_SYS_CLK_MAX_DELAY_US ((uint32) (0x1E8480u)) + #define CY_SYS_CLK_ILO_FREQ_2MSB ((uint32) (0x28u )) + + /********************************************************************************** + * CySysClkIloCompensate() - value to walk over oversamling in calculations with + * srsslite. The oversample can be obtained when ilo frequency in equal 80 KHz and + * desired clocks are 80 000 clocks. + **********************************************************************************/ + #define CY_SYS_CLK_MAX_LITE_NUMBER ((uint32) 53600u) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_CLK_ILO_FREQ_3LSB ((uint32) (0x3E8u)) +#define CY_SYS_CLK_DELAY_COUNTS_LIMIT ((uint32) (0xD160u)) +#define CY_SYS_CLK_MIN_DELAY_US ((uint32) (0x64u)) + +/* CySysClkSetLfclkSource() - parameter definitions */ +#if (CY_IP_SRSSV2 && CY_IP_WCO) + + /** Internal Low Frequency (32 kHz) Oscillator (ILO) */ + #define CY_SYS_CLK_LFCLK_SRC_ILO (0u) + + /** Low Frequency Watch Crystal Oscillator (WCO) */ + #define CY_SYS_CLK_LFCLK_SRC_WCO ((uint32)(( uint32 )0x01u << 30u)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + + +#if (CY_IP_WCO) + + /* CySysClkSetLfclkSource() - implementation definitions */ + #define CY_SYS_CLK_LFCLK_SEL_MASK ((uint32)(( uint32 )0x03u << 30u)) +#endif /* (CY_IP_WCO) */ + +/* CySysClkSetTimerSource() - implementation definitions */ +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + #define CY_SYS_CLK_TIMER_SEL_MASK ((uint32)(( uint32 )0x03u << 30u)) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkSetTimerSource() - parameter definitions */ +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + /** Internal Low Frequency (32 kHz) Oscillator (ILO) */ + #define CY_SYS_CLK_TIMER_SRC_ILO (0u) + + /** Low Frequency Watch Crystal Oscillator (WCO) */ + #define CY_SYS_CLK_TIMER_SRC_WCO ((uint32)(( uint32 )0x01u << 30u)) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkWcoClockOutSelect() - parameter definitions */ +#if (CY_IP_WCO) + + /** Selects External crystal as WCO’s clock source */ + #define CY_SYS_CLK_WCO_SEL_CRYSTAL (1u) + + /** Selects External clock input on wco_in pin as WCO’s clock source */ + #define CY_SYS_CLK_WCO_SEL_PIN (0u) +#endif /* (CY_IP_WCO) */ + +/* CySysClkWcoClockOutSelect() - implementation definitions */ +#if (CY_IP_WCO) + #define CY_SYS_CLK_WCO_SELECT_PIN_MASK ((uint32)(( uint32 )0x01u << 2u)) + #define CY_SYS_CLK_WCO_SELECT_PIN_OFFSET ((uint32) 0x02u) +#endif /* (CY_IP_WCO) */ + +/* CySysClkIloRestoreFactoryTrim() - implementation definitions */ +#if (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) + #define CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE ((uint8 )(0xF0u)) + #define CY_SYS_CLK_ILO_TRIM_DEFAULT_MASK ((uint32)((uint32)0x01u << 3u)) + #define CY_SYS_CLK_ILO_TRIM_MASK ((uint32)(0x0Fu)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) */ + +/* CySysIloTrim() - parameter definitions and macros*/ +#if (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) + #define CY_SYS_CLK_BLOCKING (0u) + #define CY_SYS_CLK_NON_BLOCKING (1u) + #define CY_SYS_CLK_PERTHOUSAND ((uint32) 0x000003E8u ) + #define CY_SYS_CLK_ABS_MACRO(x) ((0 > (x)) ? (-(x)) : (x)) + #define CY_SYS_CLK_ERROR_RANGE ((uint32) 0x38u) + #define CY_SYS_CLK_TIMEOUT ((uint8 ) 0x05u) + + /* ILO error step is 7,37 % error range */ + #define CY_SYS_CLK_ERROR_STEP (( int32) 0x02E1u) + #define CY_SYS_CLK_ERROR_COEF ((uint32) 0x0Au) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) */ + +#if (CY_IP_WCO) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_LPM_EN (( uint32 )(( uint32 )0x01u << 0u)) + #define CY_SYS_CLK_WCO_CONFIG_LPM_AUTO (( uint32 )(( uint32 )0x01u << 1u)) + #define CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE (( uint32 )(( uint32 )0x01u << 31u)) + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_OUT_BLNK_A (( uint32 )(( uint32 )0x01u << 0u)) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_XGM_MASK (( uint32 ) 0x07u) + #define CY_SYS_CLK_WCO_TRIM_XGM_SHIFT (( uint32 ) 0x00u) + + #define CY_SYS_CLK_WCO_TRIM_XGM_3370NA (( uint32 ) 0x00u) + #define CY_SYS_CLK_WCO_TRIM_XGM_2620NA (( uint32 ) 0x01u) + #define CY_SYS_CLK_WCO_TRIM_XGM_2250NA (( uint32 ) 0x02u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1500NA (( uint32 ) 0x03u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1870NA (( uint32 ) 0x04u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1120NA (( uint32 ) 0x05u) + #define CY_SYS_CLK_WCO_TRIM_XGM_750NA (( uint32 ) 0x06u) + #define CY_SYS_CLK_WCO_TRIM_XGM_0NA (( uint32 ) 0x07u) + + #define CY_SYS_CLK_WCO_TRIM_GM_MASK (( uint32 )(( uint32 )0x03u << 4u)) + #define CY_SYS_CLK_WCO_TRIM_GM_SHIFT (( uint32 ) 0x04u) + #define CY_SYS_CLK_WCO_TRIM_GM_HPM (( uint32 ) 0x01u) + #define CY_SYS_CLK_WCO_TRIM_GM_LPM (( uint32 ) 0x02u) +#endif /* (CY_IP_WCO) */ + + +/******************************************************************************* +* WDT API Constants +*******************************************************************************/ +#if(CY_IP_SRSSV2) + + #define CY_SYS_WDT_MODE_NONE (0u) + #define CY_SYS_WDT_MODE_INT (1u) + #define CY_SYS_WDT_MODE_RESET (2u) + #define CY_SYS_WDT_MODE_INT_RESET (3u) + + #define CY_SYS_WDT_COUNTER0_MASK ((uint32)((uint32)0x01u)) /**< Counter 0 */ + #define CY_SYS_WDT_COUNTER1_MASK ((uint32)((uint32)0x01u << 8u)) /**< Counter 1 */ + #define CY_SYS_WDT_COUNTER2_MASK ((uint32)((uint32)0x01u << 16u)) /**< Counter 2 */ + + #define CY_SYS_WDT_CASCADE_NONE ((uint32)0x00u) /**< Neither */ + #define CY_SYS_WDT_CASCADE_01 ((uint32)0x01u << 3u) /**< Cascade 01 */ + #define CY_SYS_WDT_CASCADE_12 ((uint32)0x01u << 11u) /**< Cascade 12 */ + + #define CY_SYS_WDT_COUNTER0_INT ((uint32)0x01u << 2u) + #define CY_SYS_WDT_COUNTER1_INT ((uint32)0x01u << 10u) + #define CY_SYS_WDT_COUNTER2_INT ((uint32)0x01u << 18u) + + #define CY_SYS_WDT_COUNTER0_RESET ((uint32)0x01u << 3u) /**< Counter 0 */ + #define CY_SYS_WDT_COUNTER1_RESET ((uint32)0x01u << 11u) /**< Counter 1 */ + #define CY_SYS_WDT_COUNTER2_RESET ((uint32)0x01u << 19u) /**< Counter 2 */ + + #define CY_SYS_WDT_COUNTERS_RESET (CY_SYS_WDT_COUNTER0_RESET |\ + CY_SYS_WDT_COUNTER1_RESET |\ + CY_SYS_WDT_COUNTER2_RESET) + + #define CY_SYS_WDT_COUNTER0 (0x00u) + #define CY_SYS_WDT_COUNTER1 (0x01u) + #define CY_SYS_WDT_COUNTER2 (0x02u) + + #define CY_SYS_WDT_COUNTER0_OFFSET (0x00u) + #define CY_SYS_WDT_COUNTER1_OFFSET (0x02u) + #define CY_SYS_WDT_COUNTER2_OFFSET (0x04u) + + #define CY_SYS_WDT_MODE_MASK ((uint32)(0x03u)) + + #define CY_SYS_WDT_CONFIG_BITS2_MASK (uint32)(0x1Fu) + #define CY_SYS_WDT_CONFIG_BITS2_POS (uint32)(24u) + #define CY_SYS_WDT_LOWER_16BITS_MASK (uint32)(0x0000FFFFu) + #define CY_SYS_WDT_HIGHER_16BITS_MASK (uint32)(0xFFFF0000u) + #define CY_SYS_WDT_COUNTERS_MAX (0x03u) + #define CY_SYS_WDT_CNT_SHIFT (0x08u) + #define CY_SYS_WDT_CNT_MATCH_CLR_SHIFT (0x02u) + #define CY_SYS_WDT_CNT_STTS_SHIFT (0x01u) + #define CY_SYS_WDT_CNT_MATCH_SHIFT (0x10u) + + #define CY_SYS_WDT_CLK_LOCK_BITS_MASK ((uint32)0x03u << 14u) + #define CY_SYS_WDT_CLK_LOCK_BIT0 ((uint32)0x01u << 14u) + #define CY_SYS_WDT_CLK_LOCK_BIT1 ((uint32)0x01u << 15u) + + #define CY_WDT_NUM_OF_WDT (3u) + #define CY_WDT_NUM_OF_CALLBACKS (3u) + + #else + #define CY_WDT_NUM_OF_WDT (1u) + #define CY_WDT_NUM_OF_CALLBACKS (3u) + #define CY_SYS_WDT_KEY ((uint32)(0xACED8865u)) + #define CY_SYS_WDT_MATCH_MASK ((uint32)(0x0000FFFFu)) + #define CY_SYS_WDT_IGNORE_BITS_MASK ((uint32)(0x000F0000u)) + #define CY_SYS_WDT_IGNORE_BITS_SHIFT ((uint32)(16u)) + #define CY_SYS_WDT_LOWER_BIT_MASK ((uint32)(0x00000001u)) + + #define CY_SYS_WDT_COUNTER0 (0x00u) + +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSV2 && CY_IP_WCO) + #define CY_SYS_WDT_1LFCLK_ILO_DELAY_US ((uint16)( 67u)) + #define CY_SYS_WDT_3LFCLK_ILO_DELAY_US ((uint16)(201u)) + #define CY_SYS_WDT_1LFCLK_WCO_DELAY_US ((uint16)( 31u)) + #define CY_SYS_WDT_3LFCLK_WCO_DELAY_US ((uint16)( 93u)) + + #define CY_SYS_WDT_1LFCLK_DELAY_US \ + ((CY_SYS_CLK_LFCLK_SRC_ILO == (CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK)) ? \ + (CY_SYS_WDT_1LFCLK_ILO_DELAY_US) : \ + (CY_SYS_WDT_1LFCLK_WCO_DELAY_US)) + + #define CY_SYS_WDT_3LFCLK_DELAY_US \ + ((CY_SYS_CLK_LFCLK_SRC_ILO == (CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK)) ? \ + (CY_SYS_WDT_3LFCLK_ILO_DELAY_US) : \ + (CY_SYS_WDT_3LFCLK_WCO_DELAY_US)) + #else + #define CY_SYS_WDT_1LFCLK_DELAY_US ((uint16) (67u)) + #define CY_SYS_WDT_3LFCLK_DELAY_US ((uint16) (201u)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + #define CY_SYS_TIMER_MODE_NONE (0u) + #define CY_SYS_TIMER_MODE_INT (1u) + + #define CY_SYS_TIMER0_MASK ((uint32)((uint32)0x01u)) /**< Counter 0 */ + #define CY_SYS_TIMER1_MASK ((uint32)((uint32)0x01u << 8u)) /**< Counter 1 */ + #define CY_SYS_TIMER2_MASK ((uint32)((uint32)0x01u << 16u)) /**< Counter 2 */ + + #define CY_SYS_TIMER0_RESET ((uint32)0x01u << 3u) /**< Counter 0 */ + #define CY_SYS_TIMER1_RESET ((uint32)0x01u << 11u) /**< Counter 1 */ + #define CY_SYS_TIMER2_RESET ((uint32)0x01u << 19u) /**< Counter 2 */ + + #define CY_SYS_TIMER_RESET (CY_SYS_TIMER0_RESET |\ + CY_SYS_TIMER1_RESET |\ + CY_SYS_TIMER2_RESET) + + #define CY_SYS_TIMER_CASCADE_NONE ((uint32)0x00u) /**< Neither */ + #define CY_SYS_TIMER_CASCADE_01 ((uint32)0x01u << 3u) /**< Cascade 01 */ + #define CY_SYS_TIMER_CASCADE_12 ((uint32)0x01u << 11u) /**< Cascade 12 */ + + #define CY_SYS_TIMER0_INT ((uint32)0x01u << 2u) + #define CY_SYS_TIMER1_INT ((uint32)0x01u << 10u) + #define CY_SYS_TIMER2_INT ((uint32)0x01u << 18u) + + #define CY_SYS_TIMER0 (0x00u) + #define CY_SYS_TIMER1 (0x01u) + #define CY_SYS_TIMER2 (0x02u) + + #define CY_SYS_TIMER_MODE_MASK ((uint32)(0x01u)) + + #define CY_SYS_TIMER_CONFIG_BITS2_MASK (uint32)(0x1Fu) + #define CY_SYS_TIMER_CONFIG_BITS2_POS (uint32)(24u) + #define CY_SYS_TIMER_LOWER_16BITS_MASK (uint32)(0x0000FFFFu) + #define CY_SYS_TIMER_HIGHER_16BITS_MASK (uint32)(0xFFFF0000u) + #define CY_SYS_TIMER_COUNTERS_MAX (0x03u) + #define CY_SYS_TIMER_CNT_SHIFT (0x08u) + #define CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT (0x02u) + #define CY_SYS_TIMER_CNT_STTS_SHIFT (0x01u) + #define CY_SYS_TIMER_CNT_MATCH_SHIFT (0x10u) + + #define CY_SYS_NUM_OF_TIMERS (3u) + + #define CY_SYS_SET_NEW_TIMER_SOURCE_ILO ((uint16)(0x02u)) + #define CY_SYS_SET_NEW_TIMER_SOURCE_WCO ((uint16)(0x01u)) + #define CY_SYS_WCO_WDT_CLKEN_RESET_MASK ((uint32)(0x03u)) + + #define CY_SYS_TIMER_1ILO_DELAY_US ((uint16)( 67u)) + #define CY_SYS_TIMER_4ILO_DELAY_US ((uint16)(268u)) + #define CY_SYS_TIMER_3ILO_DELAY_US ((uint16)(201u)) + + #define CY_SYS_TIMER_1WCO_DELAY_US ((uint16)( 31u)) + #define CY_SYS_TIMER_4WCO_DELAY_US ((uint16)(124u)) + #define CY_SYS_TIMER_3WCO_DELAY_US ((uint16)( 93u)) + + #define CY_SYS_1TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_1ILO_DELAY_US) : \ + (CY_SYS_TIMER_1WCO_DELAY_US)) + + #define CY_SYS_4TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_4WCO_DELAY_US) : \ + (CY_SYS_TIMER_4ILO_DELAY_US)) + + #define CY_SYS_3TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_3ILO_DELAY_US) : \ + (CY_SYS_TIMER_3WCO_DELAY_US)) + + #define CY_SYS_SET_CURRENT_TIMER_SOURCE_BIT \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_SET_NEW_TIMER_SOURCE_ILO) : \ + (CY_SYS_SET_NEW_TIMER_SOURCE_WCO)) + +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkWcoSetPowerMode() */ +#define CY_SYS_CLK_WCO_HPM (0x0u) /**< WCO High power mode */ + +#if(CY_IP_BLESS) + #define CY_SYS_CLK_WCO_LPM (0x1u) /**< WCO Low power mode */ +#endif /* (CY_IP_BLESS) */ + + +/******************************************************************************* +* Trim Registers Constants +********************************************************************************/ +#define CY_SYS_CLK_SYS_CLK_DEVIDER ((uint32)0x0Au) +#define CY_SYS_CLK_SEL_ILO_DFT_SOURCE ((uint32)0x00000100u) +#define CY_SYS_CLK_FOURBITS_MAX (( int32)0x0f) +#define CY_SYS_CLK_HALF_OF_STEP (( int32)((uint32) CY_SYS_CLK_ERROR_STEP >> 1u)) + +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_ILO_DESIRED_FREQ_HZ (32000u) + #define CY_SYS_CLK_DFT_SELSIZE ((uint32) 0x3F) +#else + #define CY_SYS_CLK_ILO_DESIRED_FREQ_HZ (40000u) + #define CY_SYS_CLK_DFT_SELSIZE ((uint32) 0x0F) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK ((uint32)((CY_SYS_CLK_DFT_SELSIZE << 8u) | (CY_SYS_CLK_DFT_SELSIZE ))) +#define CY_SYS_TST_DDFT_SELECT_CLK1 ((uint32) ((uint32) CYDEV_DFT_SELECT_CLK1 << 8u)) +#define CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1 ((uint32) (CY_SYS_TST_DDFT_SELECT_CLK1 | CYDEV_DFT_SELECT_CLK0)) + + +/******************************************************************************* +* Trim Registers +********************************************************************************/ +/* DFT TST Control Register*/ +#define CY_SYS_TST_DDFT_CTRL_REG (*(reg32*) CYREG_TST_DDFT_CTRL) +#define CY_SYS_CNT_CTRL_PTR ( (reg32*) CYREG_TST_DDFT_CTRL) + +/* DFT TST Counter 1 Register*/ +#define CY_SYS_CNT_REG1_REG (*(reg32*) CYREG_TST_TRIM_CNTR1) +#define CY_SYS_CNT_REG1_PTR ( (reg32*) CYREG_TST_TRIM_CNTR1) + +/* DFT TST Counter 2 Register*/ +#define CY_SYS_CNT_REG2_REG (*(reg32*) CYREG_TST_TRIM_CNTR2) +#define CY_SYS_CNT_REG2_PTR ( (reg32*) CYREG_TST_TRIM_CNTR2) + +/* DFT Muxes Configuration Register*/ +#define CY_SYS_CLK_DFT_REG (*(reg32*) CYREG_CLK_DFT_SELECT) +#define CY_SYS_CLK_DFT_PTR ( (reg32*) CYREG_CLK_DFT_SELECT) + +/* ILO Configuration Register*/ +#define CY_SYS_CLK_ILO_CONFIG_REG (*(reg32 *) CYREG_CLK_ILO_CONFIG) +#define CY_SYS_CLK_ILO_CONFIG_PTR ( (reg32 *) CYREG_CLK_ILO_CONFIG) + +/* ILO Trim Register*/ +#if(CY_IP_SRSSV2 && CY_IP_WCO) + #define CY_SYS_CLK_ILO_TRIM_REG (*(reg32 *) CYREG_CLK_ILO_TRIM) + #define CY_SYS_CLK_ILO_TRIM_PTR ( (reg32 *) CYREG_CLK_ILO_TRIM) +#endif /* (CY_IP_SRSSV2) && CY_IP_WCO*/ + +#if (CY_IP_WCO) + #if (CY_IP_BLESS) + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_STATUS) + #define CY_SYS_CLK_WCO_STATUS_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_STATUS) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_CONFIG) + #define CY_SYS_CLK_WCO_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_CONFIG) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_TRIM) + #define CY_SYS_CLK_WCO_TRIM_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_TRIM) + #else + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_REG (*(reg32 *) CYREG_WCO_STATUS) + #define CY_SYS_CLK_WCO_STATUS_PTR ( (reg32 *) CYREG_WCO_STATUS) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_REG (*(reg32 *) CYREG_WCO_CONFIG) + #define CY_SYS_CLK_WCO_CONFIG_PTR ( (reg32 *) CYREG_WCO_CONFIG) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_REG (*(reg32 *) CYREG_WCO_TRIM) + #define CY_SYS_CLK_WCO_TRIM_PTR ( (reg32 *) CYREG_WCO_TRIM) + #endif /* (CY_IP_BLESS) */ +#endif /* (CY_IP_WCO) */ + + +/******************************************************************************* +* WDT API Registers +*******************************************************************************/ +#if(CY_IP_SRSSV2) + #define CY_SYS_WDT_CTRLOW_REG (*(reg32 *) CYREG_WDT_CTRLOW) + #define CY_SYS_WDT_CTRLOW_PTR ( (reg32 *) CYREG_WDT_CTRLOW) + + #define CY_SYS_WDT_CTRHIGH_REG (*(reg32 *) CYREG_WDT_CTRHIGH) + #define CY_SYS_WDT_CTRHIGH_PTR ( (reg32 *) CYREG_WDT_CTRHIGH) + + #define CY_SYS_WDT_MATCH_REG (*(reg32 *) CYREG_WDT_MATCH) + #define CY_SYS_WDT_MATCH_PTR ( (reg32 *) CYREG_WDT_MATCH) + + #define CY_SYS_WDT_CONFIG_REG (*(reg32 *) CYREG_WDT_CONFIG) + #define CY_SYS_WDT_CONFIG_PTR ( (reg32 *) CYREG_WDT_CONFIG) + + #define CY_SYS_WDT_CONTROL_REG (*(reg32 *) CYREG_WDT_CONTROL) + #define CY_SYS_WDT_CONTROL_PTR ( (reg32 *) CYREG_WDT_CONTROL) +#else + #define CY_SYS_WDT_DISABLE_KEY_REG (*(reg32 *) CYREG_WDT_DISABLE_KEY) + #define CY_SYS_WDT_DISABLE_KEY_PTR ( (reg32 *) CYREG_WDT_DISABLE_KEY) + + #define CY_SYS_WDT_MATCH_REG (*(reg32 *) CYREG_WDT_MATCH) + #define CY_SYS_WDT_MATCH_PTR ( (reg32 *) CYREG_WDT_MATCH) + + #define CY_SYS_WDT_COUNTER_REG (*(reg32 *) CYREG_WDT_COUNTER) + #define CY_SYS_WDT_COUNTER_PTR ( (reg32 *) CYREG_WDT_COUNTER) + + #define CY_SYS_SRSS_INTR_REG (*(reg32 *) CYREG_SRSS_INTR) + #define CY_SYS_SRSS_INTR_PTR ( (reg32 *) CYREG_SRSS_INTR) + + #define CY_SYS_SRSS_INTR_MASK_REG (*(reg32 *) CYREG_SRSS_INTR_MASK) + #define CY_SYS_SRSS_INTR_MASK_PTR ( (reg32 *) CYREG_SRSS_INTR_MASK) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + #define CY_SYS_WCO_WDT_CTRLOW_REG (*(reg32 *) CYREG_WCO_WDT_CTRLOW) + #define CY_SYS_WCO_WDT_CTRLOW_PTR ( (reg32 *) CYREG_WCO_WDT_CTRLOW) + + #define CY_SYS_WCO_WDT_CTRHIGH_REG (*(reg32 *) CYREG_WCO_WDT_CTRHIGH) + #define CY_SYS_WCO_WDT_CTRHIGH_PTR ( (reg32 *) CYREG_WCO_WDT_CTRHIGH) + + #define CY_SYS_WCO_WDT_MATCH_REG (*(reg32 *) CYREG_WCO_WDT_MATCH) + #define CY_SYS_WCO_WDT_MATCH_PTR ( (reg32 *) CYREG_WCO_WDT_MATCH) + + #define CY_SYS_WCO_WDT_CONFIG_REG (*(reg32 *) CYREG_WCO_WDT_CONFIG) + #define CY_SYS_WCO_WDT_CONFIG_PTR ( (reg32 *) CYREG_WCO_WDT_CONFIG) + + #define CY_SYS_WCO_WDT_CONTROL_REG (*(reg32 *) CYREG_WCO_WDT_CONTROL) + #define CY_SYS_WCO_WDT_CONTROL_PTR ( (reg32 *) CYREG_WCO_WDT_CONTROL) + + #define CY_SYS_WCO_WDT_CLKEN_REG (*(reg32 *) CYREG_WCO_WDT_CLKEN) + #define CY_SYS_WCO_WDT_CLKEN_PTR ( (reg32 *) CYREG_WCO_WDT_CLKEN) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +#if (CY_IP_WCO) + + /******************************************************************************* + * Function Name: CySysClkWcoSetHighPowerMode + ******************************************************************************** + * + * Summary: + * Sets the high power mode for the 32 KHz WCO. + * + *******************************************************************************/ + static CY_INLINE void CySysClkWcoSetHighPowerMode(void) + { + /* Switch off low power mode for WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_EN; + + /* Switch off auto low power mode in WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= ((uint32)~CY_SYS_CLK_WCO_CONFIG_LPM_AUTO); + + /* Restore WCO trim register HPM settings */ + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_GM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_GM_HPM << CY_SYS_CLK_WCO_TRIM_GM_SHIFT); + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_XGM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_XGM_2620NA << CY_SYS_CLK_WCO_TRIM_XGM_SHIFT); + } + + #if(CY_IP_BLESS) + /******************************************************************************* + * Function Name: CySysClkWcoSetLowPowerMode + ******************************************************************************** + * + * Summary: + * Sets the low power mode for the 32 KHz WCO. + * + * Note LPM available only for PSoC 4100 BLE / PSoC4 4200 BLE + *******************************************************************************/ + static CY_INLINE void CySysClkWcoSetLowPowerMode(void) + { + /* Switch off auto low power mode in WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= ((uint32)~CY_SYS_CLK_WCO_CONFIG_LPM_AUTO); + + /* Change WCO trim register settings to LPM */ + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_XGM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_XGM_2250NA << CY_SYS_CLK_WCO_TRIM_XGM_SHIFT); + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_GM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_GM_LPM << CY_SYS_CLK_WCO_TRIM_GM_SHIFT); + + /* Switch on low power mode for WCO */ + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_LPM_EN; + } + #endif /* (CY_IP_BLESS) */ + +#endif /* (CY_IP_WCO) */ + + +/* These defines are intended to maintain the backward compatibility for + * projects which use cy_boot_v4_20 or earlier. +*/ +#define CySysWdtWriteMode CySysWdtSetMode +#define CySysWdtReadMode CySysWdtGetMode +#define CySysWdtWriteClearOnMatch CySysWdtSetClearOnMatch +#define CySysWdtReadClearOnMatch CySysWdtGetClearOnMatch +#define CySysWdtReadEnabledStatus CySysWdtGetEnabledStatus +#define CySysWdtWriteCascade CySysWdtSetCascade +#define CySysWdtReadCascade CySysWdtGetCascade +#define CySysWdtWriteMatch CySysWdtSetMatch +#define CySysWdtWriteToggleBit CySysWdtSetToggleBit +#define CySysWdtReadToggleBit CySysWdtGetToggleBit +#define CySysWdtReadMatch CySysWdtGetMatch +#define CySysWdtReadCount CySysWdtGetCount +#define CySysWdtWriteIgnoreBits CySysWdtSetIgnoreBits +#define CySysWdtReadIgnoreBits CySysWdtGetIgnoreBits +#define CySysWdtSetIsrCallback CySysWdtSetInterruptCallback +#define CySysWdtGetIsrCallback CySysWdtGetInterruptCallback + +#endif /* (CY_LFCLK_CYLIB_H) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLib.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLib.c new file mode 100644 index 0000000..75d5292 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLib.c @@ -0,0 +1,3504 @@ +/***************************************************************************//** +* \file CyLib.c +* \version 5.70 +* +* \brief Provides a system API for the Clocking, Interrupts, SysTick, and +* Voltage Detect. +* +* \note Documentation of the API's in this file is located in the PSoC 4 System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + +/* CySysClkWriteImoFreq() || CySysClkImoEnableWcoLock() */ +#if ((CY_IP_SRSSV2 && CY_IP_FMLT) || CY_IP_IMO_TRIMMABLE_BY_WCO) + #include "CyFlash.h" +#endif /* (CY_IP_SRSSV2 && CY_IP_FMLT) */ + +/* Do not use these definitions directly in your application */ +uint32 cydelayFreqHz = CYDEV_BCLK__SYSCLK__HZ; +uint32 cydelayFreqKhz = (CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; +uint8 cydelayFreqMhz = (uint8)((CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); +uint32 cydelay32kMs = CY_DELAY_MS_OVERFLOW * ((CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD); + + +static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; +static void CySysTickServiceCallbacks(void); + +#if (CY_IP_PLL) + static uint32 CySysClkPllGetBypassMode(uint32 pll); + static cystatus CySysClkPllConfigChangeAllowed(uint32 pll); +#endif /* (CY_IP_PLL) */ + + +/***************************************************************************//** +* Indicates whether or not the SysTick has been initialized. The variable is +* initialized to 0 and set to 1 the first time CySysTickStart() is called. +* +* This allows the component to restart without reinitialization after the first +* call to the CySysTickStart() routine. +* +* If reinitialization of the SysTick is required, call CySysTickInit() before +* calling CySysTickStart(). Alternatively, the SysTick can be reinitialized by +* calling the CySysTickInit() and CySysTickEnable() functions. +*******************************************************************************/ +uint32 CySysTickInitVar = 0u; + + +#if(CY_IP_SRSSV2) + /* Conversion between CySysClkWriteImoFreq() parameter and register's value */ + const uint8 cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_FREQ_TABLE_SIZE] = { + /* 3 MHz */ 0x03u, /* 4 MHz */ 0x04u, /* 5 MHz */ 0x05u, /* 6 MHz */ 0x06u, + /* 7 MHz */ 0x07u, /* 8 MHz */ 0x08u, /* 9 MHz */ 0x09u, /* 10 MHz */ 0x0Au, + /* 11 MHz */ 0x0Bu, /* 12 MHz */ 0x0Cu, /* 13 MHz */ 0x0Eu, /* 14 MHz */ 0x0Fu, + /* 15 MHz */ 0x10u, /* 16 MHz */ 0x11u, /* 17 MHz */ 0x12u, /* 18 MHz */ 0x13u, + /* 19 MHz */ 0x14u, /* 20 MHz */ 0x15u, /* 21 MHz */ 0x16u, /* 22 MHz */ 0x17u, + /* 23 MHz */ 0x18u, /* 24 MHz */ 0x19u, /* 25 MHz */ 0x1Bu, /* 26 MHz */ 0x1Cu, + /* 27 MHz */ 0x1Du, /* 28 MHz */ 0x1Eu, /* 29 MHz */ 0x1Fu, /* 30 MHz */ 0x20u, + /* 31 MHz */ 0x21u, /* 32 MHz */ 0x22u, /* 33 MHz */ 0x23u, /* 34 MHz */ 0x25u, + /* 35 MHz */ 0x26u, /* 36 MHz */ 0x27u, /* 37 MHz */ 0x28u, /* 38 MHz */ 0x29u, + /* 39 MHz */ 0x2Au, /* 40 MHz */ 0x2Bu, /* 41 MHz */ 0x2Eu, /* 42 MHz */ 0x2Fu, + /* 43 MHz */ 0x30u, /* 44 MHz */ 0x31u, /* 45 MHz */ 0x32u, /* 46 MHz */ 0x33u, + /* 47 MHz */ 0x34u, /* 48 MHz */ 0x35u }; +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* Conversion between IMO frequency and WCO DPLL max offset steps */ + const uint8 cyImoFreqMhz2DpllOffset[CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE] = { + /* 26 MHz */ 238u, /* 27 MHz */ 219u, /* 28 MHz */ 201u, /* 29 MHz */ 185u, + /* 30 MHz */ 170u, /* 31 MHz */ 155u, /* 32 MHz */ 142u, /* 33 MHz */ 130u, + /* 34 MHz */ 118u, /* 35 MHz */ 107u, /* 36 MHz */ 96u, /* 37 MHz */ 86u, + /* 38 MHz */ 77u, /* 39 MHz */ 68u, /* 40 MHz */ 59u, /* 41 MHz */ 51u, + /* 42 MHz */ 44u, /* 43 MHz */ 36u, /* 44 MHz */ 29u, /* 45 MHz */ 23u, + /* 46 MHz */ 16u, /* 47 MHz */ 10u, /* 48 MHz */ 4u }; +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + +/* Stored CY_SYS_CLK_IMO_TRIM4_REG when modified for USB lock */ +#if (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSV2) + uint32 CySysClkImoTrim4 = 0u; + uint32 CySysClkImoTrim5 = 0u; +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSV2) */ + +/* Stored PUMP_SEL configuration during disable (IMO output by default) */ +uint32 CySysClkPumpConfig = CY_SYS_CLK_PUMP_ENABLE; + +/******************************************************************************* +* Function Name: CySysClkImoStart +****************************************************************************//** +* +* Enables the IMO. +* +* For PSoC 4100M / PSoC 4200M / PSoC 4000S / PSoC 4100S / PSoC Analog +* Coprocessor devices, this function will also enable WCO lock if selected in +* the Design Wide Resources tab. +* +* For PSoC 4200L devices, this function will also enable USB lock if selected +* in the Design Wide Resources tab. +* +*******************************************************************************/ +void CySysClkImoStart(void) +{ + CY_SYS_CLK_IMO_CONFIG_REG |= CY_SYS_CLK_IMO_CONFIG_ENABLE; + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + #if (CYDEV_IMO_TRIMMED_BY_WCO == 1u) + CySysClkImoEnableWcoLock(); + #endif /* (CYDEV_IMO_TRIMMED_BY_WCO == 1u) */ + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + #if (CYDEV_IMO_TRIMMED_BY_USB == 1u) + CySysClkImoEnableUsbLock(); + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 1u) */ + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +} + + +/******************************************************************************* +* Function Name: CySysClkImoStop +****************************************************************************//** +* +* Disables the IMO. +* +* For PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / +* PSoC Analog Coprocessor devices, this function will also disable WCO lock. +* +* For PSoC PSoC 4200L devices, this function will also disable USB lock. +* +*******************************************************************************/ +void CySysClkImoStop(void) +{ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + CySysClkImoDisableWcoLock(); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + CySysClkImoDisableUsbLock(); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CY_SYS_CLK_IMO_CONFIG_REG &= ( uint32 ) ( ~( uint32 )CY_SYS_CLK_IMO_CONFIG_ENABLE); +} + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + + /******************************************************************************* + * Function Name: CySysClkImoEnableWcoLock + ****************************************************************************//** + * + * Enables the IMO to WCO lock feature. This function works only if the WCO is + * already enabled. If the WCO is not enabled then this function returns + * without enabling the lock feature. + * + * It takes up to 20 ms for the IMO to stabilize. The delay is implemented with + * CyDelay() function. The delay interval is measured based on the system + * frequency defined by PSoC Creator at build time. If System clock frequency + * is changed in runtime, the CyDelayFreq() with the appropriate parameter + * should be called. + * + * For PSoC 4200L devices, note that the IMO can lock to either WCO or USB + * but not both. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + *******************************************************************************/ + void CySysClkImoEnableWcoLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + #endif /* (CY_IP_SRSSV2) */ + + uint32 freq; + uint8 interruptState; + uint32 regTmp; + uint32 lfLimit = 0u; + volatile uint32 flashCtlReg; + + if (0u != CySysClkWcoEnabled()) + { + interruptState = CyEnterCriticalSection(); + + /* Set oscillator interface control port to WCO */ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + CY_SYS_CLK_OSCINTF_CTL_REG = + (CY_SYS_CLK_OSCINTF_CTL_REG & (uint32) ~CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK) | + CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_WCO; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + /* Get current IMO frequency based on the register value */ + #if(CY_IP_SRSSV2) + freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #else + /* Calculate frequency by shifting register field value and adding constant. */ + #if(CY_IP_SRSSLT) + freq = (((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> + ((CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT) & + (uint32) CY_SYS_CLK_SELECT_HFCLK_DIV_MASK)); + #else + freq = ((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #endif /* (CY_IP_SRSSLT) */ + + #endif /* (CY_IP_SRSSV2) */ + + /* For the WCO locking mode, the IMO gain needs to be CY_SYS_CLK_IMO_TRIM4_GAIN */ + #if(CY_IP_SRSSV2) + if ((CY_SYS_CLK_IMO_TRIM4_REG & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) == 0u) + { + CY_SYS_CLK_IMO_TRIM4_REG = (CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SYS_CLK_IMO_TRIM4_WCO_GAIN; + } + #endif /* (CY_IP_SRSSV2) */ + + regTmp = CY_SYS_CLK_WCO_DPLL_REG & ~(CY_SYS_CLK_WCO_DPLL_MULT_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK); + + /* Set multiplier to determine IMO frequency in multiples of the WCO frequency */ + regTmp |= (CY_SYS_CLK_WCO_DPLL_MULT_VALUE(freq) & CY_SYS_CLK_WCO_DPLL_MULT_MASK); + + /* Set DPLL Loop Filter Integral and Proportional Gains Setting */ + regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN | CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN); + + /* Set maximum allowed IMO offset */ + if (freq < CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT) + { + regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); + } + else + { + lfLimit = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + + cyImoFreqMhz2DpllOffset[freq - CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET]; + + lfLimit = (lfLimit > CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX) ? + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX : lfLimit; + + regTmp |= (lfLimit << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); + } + + CY_SYS_CLK_WCO_DPLL_REG = regTmp; + + flashCtlReg = CY_FLASH_CTL_REG; + CySysFlashSetWaitCycles(CY_SYS_CLK_IMO_MAX_FREQ_MHZ); + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + CyDelay(CY_SYS_CLK_WCO_IMO_TIMEOUT_MS); + CY_FLASH_CTL_REG = flashCtlReg; + + CyExitCriticalSection(interruptState); + } + } + + + /******************************************************************************* + * Function Name: CySysClkImoDisableWcoLock + ****************************************************************************//** + * + * Disables the IMO to WCO lock feature. + * + * For PSoC 4200L devices, note that the IMO can lock to either WCO or USB + * but not both. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + *******************************************************************************/ + void CySysClkImoDisableWcoLock(void) + { + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + } + + + /******************************************************************************* + * Function Name: CySysClkImoGetWcoLock + ****************************************************************************//** + * + * Reports the IMO to WCO lock enable state. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + * \return 1 if IMO to WCO lock is enabled. + * \return 0 if IMO to WCO lock is disabled. + * + *******************************************************************************/ + uint32 CySysClkImoGetWcoLock(void) + { + return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE)) ? + (uint32) 1u : + (uint32) 0u); + } + +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +#if (CY_IP_IMO_TRIMMABLE_BY_USB) + + /******************************************************************************* + * Function Name: CySysClkImoEnableUsbLock + ****************************************************************************//** + * + * Enables the IMO to USB lock feature. + * + * This function must be called before CySysClkWriteImoFreq(). + * + * This function is called from CySysClkImoStart() function if USB lock + * selected in the Design Wide Resources tab. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + *******************************************************************************/ + void CySysClkImoEnableUsbLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + + /* Check for new trim algorithm */ + uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_REV_REG & + CY_SFLASH_S1_TESTPGM_REV_MASK)) ? 1u : 0u); + + /* Get current IMO frequency based on the register value */ + uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #endif /* (CY_IP_SRSSV2) */ + + /* Set oscillator interface control port to USB */ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + CY_SYS_CLK_OSCINTF_CTL_REG = (CY_SYS_CLK_OSCINTF_CTL_REG & (uint32) ~CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK) | + CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_USB; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + #if(CY_IP_SRSSV2) + + /* Save CY_SYS_CLK_IMO_TRIM4_REG and set IMO gain for USB lock */ + CySysClkImoTrim4 = CY_SYS_CLK_IMO_TRIM4_REG; + + if(0u != CySysClkUsbCuSortTrim) + { + CySysClkImoTrim5 = CY_PWR_BG_TRIM5_REG; + + CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG; + CY_PWR_BG_TRIM5_REG = CY_SFLASH_USBMODE_IMO_TEMPCO_REG; + + } + else + { + CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SYS_CLK_IMO_TRIM4_USB_GAIN; + + } + + if (48u == freq) + { + CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_48_REG : + (uint32)CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + } + else if (24u == freq) + { + CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_24_REG : + (uint32)CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + } + else + { + /* Do nothing */ + } + + #endif /* (CY_IP_SRSSV2) */ + + CY_SYS_CLK_USBDEVv2_CR1_REG |= CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + } + + + /******************************************************************************* + * Function Name: CySysClkImoDisableUsbLock + ****************************************************************************//** + * + * Disables the IMO to USB lock feature. + * + * This function is called from CySysClkImoStop() function if USB lock selected + * in the Design Wide Resources tab. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + *******************************************************************************/ + void CySysClkImoDisableUsbLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + + /* Check for new trim algorithm */ + uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_REV_REG & + CY_SFLASH_S1_TESTPGM_REV_MASK)) ? 1u : 0u); + + /* Get current IMO frequency based on the register value */ + uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ;; + + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #endif /* (CY_IP_SRSSV2) */ + + CY_SYS_CLK_USBDEVv2_CR1_REG &= (uint32) ~CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + + #if(CY_IP_SRSSV2) + /* Restore CY_SYS_CLK_IMO_TRIM4_REG */ + CY_SYS_CLK_IMO_TRIM4_REG = ((CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + (CySysClkImoTrim4 & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK)); + + if(0u != CySysClkUsbCuSortTrim) + { + CY_PWR_BG_TRIM5_REG = CySysClkImoTrim5; + } + + CY_SYS_CLK_IMO_TRIM1_REG = CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET); + + #endif /* (CY_IP_SRSSV2) */ + } + + + /******************************************************************************* + * Function Name: CySysClkImoGetUsbLock + ****************************************************************************//** + * + * Reports the IMO to USB lock enable state. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + * \return 1 if IMO to USB lock is enabled. + * \return 0 if IMO to USB lock is disabled. + * + *******************************************************************************/ + uint32 CySysClkImoGetUsbLock(void) + { + return ((0u != (CY_SYS_CLK_USBDEVv2_CR1_REG & CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK)) ? + (uint32) 1u : + (uint32) 0u); + } +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + + +/******************************************************************************* +* Function Name: CySysClkWriteHfclkDirect +****************************************************************************//** +* +* Selects the direct source for the HFCLK. +* +* The new source must be running and stable before calling this function. +* +* PSoC 4000: +* The SYSCLK has a maximum speed of 16 MHz, so HFCLK and SYSCLK dividers should +* be selected in a way to not to exceed 16 MHz for the System clock. +* +* If the SYSCLK clock frequency increases during device operation, call +* CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number +* of clock cycles the cache will wait before sampling data comes back from +* Flash. If the SYSCLK clock frequency decreases, you can call +* CySysFlashSetWaitCycles() to improve the CPU performance. See +* CySysFlashSetWaitCycles() description for more information. +* +* Do not select PLL as the source for HFCLK if PLL output frequency exceeds +* maximum permissible value for HFCLK. +* +* \param clkSelect One of the available HFCLK direct sources. +* CY_SYS_CLK_HFCLK_IMO IMO. +* CY_SYS_CLK_HFCLK_EXTCLK External clock pin. +* CY_SYS_CLK_HFCLK_ECO External crystal oscillator. Applicable for +* PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / +* 4100S with ECO. +* CY_SYS_CLK_HFCLK_PLL0 PLL#0. Applicable for PSoC 4200L / +* 4100S with PLL. +* CY_SYS_CLK_HFCLK_PLL1 PLL#1. Applicable for PSoC 4200L. +* +*******************************************************************************/ +void CySysClkWriteHfclkDirect(uint32 clkSelect) +{ + uint8 interruptState; + uint32 tmpReg; + + #if (CY_IP_SRSSLT && CY_IP_PLL) + uint8 i = 0u; + #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + interruptState = CyEnterCriticalSection(); + +#if (CY_IP_SRSSLT && CY_IP_PLL) + if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_ECO == clkSelect)) + { + tmpReg = CY_SYS_CLK_SELECT_REG & ~CY_SYS_CLK_SELECT_DIRECT_SEL_MASK; + tmpReg |= CY_SYS_CLK_HFCLK_IMO; + CY_SYS_CLK_SELECT_REG = tmpReg; + + /* SRSSLT block does not have registers to select PLL. It is part of EXCO */ + tmpReg = CY_SYS_ECO_CLK_SELECT_REG & ~CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK; + tmpReg |= ((clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_PLL_MASK) >> CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT); + CY_SYS_ECO_CLK_SELECT_REG = tmpReg; + + /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) + { + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + } + + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + } +#endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + tmpReg = CY_SYS_CLK_SELECT_REG & ~(CY_SYS_CLK_SELECT_DIRECT_SEL_MASK | + CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + +#if (CY_IP_SRSSV2 && CY_IP_PLL) + if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_PLL1 == clkSelect)) + { + tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + } + else +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + { + tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + } + + CY_SYS_CLK_SELECT_REG = tmpReg; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysEnablePumpClock +****************************************************************************//** +* +* Enables / disables the pump clock. +* +* \param enable +* CY_SYS_CLK_PUMP_DISABLE - Disables the pump clock +* CY_SYS_CLK_PUMP_ENABLE - Enables and restores the operating source of +* the pump clock. +* +* \sideeffect +* Enabling/disabling the pump clock does not guarantee glitch free operation +* when changing the IMO parameters or clock divider settings. +* +*******************************************************************************/ +void CySysEnablePumpClock(uint32 enable) +{ + #if(CY_IP_SRSSV2) + if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + { + CY_SYS_CLK_IMO_CONFIG_REG |= (CySysClkPumpConfig << CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT); + } + else + { + CySysClkPumpConfig = (CY_SYS_CLK_IMO_CONFIG_REG >> CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT) & + CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK; + CY_SYS_CLK_IMO_CONFIG_REG &= ~(CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK << CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT); + } + #else /* CY_IP_SRSSLT */ + if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + { + CY_SYS_CLK_SELECT_REG |= (CySysClkPumpConfig << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT); + } + else + { + CySysClkPumpConfig = (CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & + CY_SYS_CLK_SELECT_PUMP_SEL_MASK; + CY_SYS_CLK_SELECT_REG &= ~(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT); + } + #endif /* (CY_IP_SRSSV2) */ +} + + +/******************************************************************************* +* Function Name: CySysClkGetSysclkSource +****************************************************************************//** +* +* Returns the source of the System clock. +* +* \return The same as \ref CySysClkWriteHfclkDirect() function parameters. +* +*******************************************************************************/ +uint32 CySysClkGetSysclkSource(void) +{ + uint8 interruptState; + uint32 sysclkSource; + + interruptState = CyEnterCriticalSection(); + +#if (CY_IP_SRSSV2 && CY_IP_PLL) + if ((CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK) != 0u) + { + sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + } + else +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + { + sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + + #if (CY_IP_SRSSLT && CY_IP_PLL) + sysclkSource |= (((uint32)(CY_SYS_ECO_CLK_SELECT_REG & CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK)) << + CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT); + #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + } + + CyExitCriticalSection(interruptState); + + return (sysclkSource); +} + + +/******************************************************************************* +* Function Name: CySysClkWriteSysclkDiv +****************************************************************************//** +* +* Selects the prescaler divide amount for SYSCLK from HFCLK. +* +* PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers +* should be selected in a way, not to exceed 16 MHz for SYSCLK. +* +* PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, +* so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz +* for SYSCLK. +* +* If the SYSCLK clock frequency increases during the device operation, call +* \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the +* number of clock cycles the cache will wait before sampling data comes back +* from Flash. If the SYSCLK clock frequency decreases, you can call +* \ref CySysFlashSetWaitCycles() to improve the CPU performance. See +* \ref CySysFlashSetWaitCycles() description for more information. +* +* \param divider Power of 2 prescaler selection +* CY_SYS_CLK_SYSCLK_DIV1 SYSCLK = HFCLK / 1 +* CY_SYS_CLK_SYSCLK_DIV2 SYSCLK = HFCLK / 2 +* CY_SYS_CLK_SYSCLK_DIV4 SYSCLK = HFCLK / 4 +* CY_SYS_CLK_SYSCLK_DIV8 SYSCLK = HFCLK / 8 +* CY_SYS_CLK_SYSCLK_DIV16 SYSCLK = HFCLK / 16 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV32 SYSCLK = HFCLK / 32 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV64 SYSCLK = HFCLK / 64 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV128 SYSCLK = HFCLK / 128 (N/A for 4000 Family) +* +*******************************************************************************/ +void CySysClkWriteSysclkDiv(uint32 divider) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = ((uint32)(((uint32)divider & CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK) << + CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)) | + (CY_SYS_CLK_SELECT_REG & ((uint32)(~(uint32)(CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK << + CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)))); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysClkWriteImoFreq +****************************************************************************//** +* +* Sets the frequency of the IMO. +* +* PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers +* should be selected in a way, not to exceed 16 MHz for SYSCLK. +* +* PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, +* so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz +* for SYSCLK. +* +* For PSoC 4200M and PSoC 4200L device families, if WCO lock feature is enabled +* then this API will disable the lock, write the new IMO frequency and then +* re-enable the lock. +* +* For PSoC 4200L device families, this function enables the USB lock when 24 or +* 48 MHz passed as a parameter if the USB lock option is enabled in Design Wide +* Resources tab or CySysClkImoEnableUsbLock() was called before. Note the USB +* lock is disabled during IMO frequency change. +* +* The CPU is halted if new frequency is invalid and project is compiled +* in debug mode. +* +* If the SYSCLK clock frequency increases during the device operation, call +* \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the +* number of clock cycles the cache will wait before sampling data comes back +* from Flash. If the SYSCLK clock frequency decreases, you can call +* \ref CySysFlashSetWaitCycles() to improve the CPU performance. See +* \ref CySysFlashSetWaitCycles() description for more information. +* +* PSoC 4000: The System Clock (SYSCLK) has maximum speed of 16 MHz, so HFCLK +* and SYSCLK dividers should be selected in a way, to not to exceed 16 MHz for +* the System clock. +* +* \param freq All PSoC 4 families excluding the following: Valid range [3-48] +* with step size equals 1. PSoC 4000: Valid values are 24, 32, and 48. +* PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor: Valid range [24-48] with +* step size equals 4. +* +*******************************************************************************/ +#if(CY_IP_SRSSV2) + void CySysClkWriteImoFreq(uint32 freq) + { + #if (CY_IP_FMLT) + volatile uint32 parameters[2u]; + volatile uint32 regValues[4u]; + #else + uint8 bgTrim4; + uint8 bgTrim5; + uint8 newImoTrim2Value; + uint8 currentImoTrim2Value; + #endif /* (CY_IP_FM) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + uint32 wcoLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + uint32 usbLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + uint8 interruptState; + + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if(0u != CySysClkImoGetWcoLock()) + { + wcoLock = 1u; + CySysClkImoDisableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + if(0u != CySysClkImoGetUsbLock()) + { + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + if ((24u == freq) || (48u == freq)) + { + usbLock = 1u; + CySysClkImoDisableUsbLock(); + } + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + } + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + + #if (CY_IP_FMLT) + + /* FM-Lite Clock Restore */ + regValues[0u] = CY_SYS_CLK_IMO_CONFIG_REG; + regValues[1u] = CY_SYS_CLK_SELECT_REG; + regValues[2u] = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + regValues[3u] = CY_FLASH_CTL_REG; + + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) ®Values[0u]; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + (void) CY_FLASH_CPUSS_SYSARG_REG; + + #else /* (CY_IP_FM) */ + + if ((freq >= CY_SYS_CLK_IMO_MIN_FREQ_MHZ) && (freq <= CY_SYS_CLK_IMO_MAX_FREQ_MHZ)) + { + if(freq <= CY_SFLASH_IMO_MAXF0_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS0_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO0_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF1_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS1_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO1_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF2_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS2_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO2_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF3_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS3_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO3_REG; + } + else + { + bgTrim4 = CY_SFLASH_IMO_ABS4_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO4_REG; + } + + /* Get IMO_TRIM2 value for the new frequency */ + newImoTrim2Value = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + + + /**************************************************************************** + * The IMO can have a different trim per frequency. To avoid possible corner + * cases where a trim change can exceed the maximum frequency, the trim must + * be applied at a frequency that is low enough. + * + * Comparing IMO_TRIM2 values for the current and new frequencies, since + * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + * function and is time-invariant. + ***************************************************************************/ + if ((newImoTrim2Value >= CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2) && (freq >= CY_SYS_CLK_IMO_BOUNDARY_FREQ_MHZ)) + { + /* Set boundary IMO frequency: safe for IMO above 48 MHZ trimming */ + CY_SYS_CLK_IMO_TRIM2_REG = (uint32) cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_TEMP_FREQ_MHZ - + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + + currentImoTrim2Value = CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2; + } + else + { + currentImoTrim2Value = (uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK); + } + + + /*************************************************************************** + * A trim change needs to be allowed to settle (within 5us) before the Freq + * can be changed to a new frequency. + * + * Comparing IMO_TRIM2 values for the current and new frequencies, since + * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + * function and is time-invariant. + ***************************************************************************/ + if (newImoTrim2Value < currentImoTrim2Value) + { + /* Set new IMO frequency */ + CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + } + + /* Set trims for the new IMO frequency */ + CY_SYS_CLK_IMO_TRIM1_REG = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET); + CY_PWR_BG_TRIM4_REG = bgTrim4; + CY_PWR_BG_TRIM5_REG = bgTrim5; + CyDelayUs(CY_SYS_CLK_IMO_TRIM_TIMEOUT_US); + + if (newImoTrim2Value > currentImoTrim2Value) + { + /* Set new IMO frequency */ + CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + } + } + else + { + /* Halt CPU in debug mode if new frequency is invalid */ + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_FMLT) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (1u == wcoLock) + { + CySysClkImoEnableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if (1u == usbLock) + { + CySysClkImoEnableUsbLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CyExitCriticalSection(interruptState); + } + +#else + + void CySysClkWriteImoFreq(uint32 freq) + { + uint8 interruptState; + uint8 imoTrim1Value; + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + uint32 wcoLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + uint32 usbLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + #if (CY_PSOC4_4000) + if ((freq == 24u) || (freq == 32u) || (freq == 48u)) + #elif (CY_CCG3) + if ((freq == 24u) || (freq == 36u) || (freq == 48u)) + #else + if ((freq == 24u) || (freq == 28u) || (freq == 32u) || + (freq == 36u) || (freq == 40u) || (freq == 44u) || + (freq == 48u)) + #endif /* (CY_PSOC4_4000) */ + { + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if(0u != CySysClkImoGetWcoLock()) + { + wcoLock = 1u; + CySysClkImoDisableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + if(0u != CySysClkImoGetUsbLock()) + { + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + if (48u == freq) + { + usbLock = 1u; + CySysClkImoDisableUsbLock(); + } + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + } + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + + /* Set IMO to 24 MHz - CLK_IMO_SELECT.FREQ = 0 */ + CY_SYS_CLK_IMO_SELECT_REG &= ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + + + /* Apply coarse trim */ + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if ((1u == usbLock) && (48u == freq)) + { + imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + } + else if ((1u == usbLock) && (24u == freq)) + { + imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + } + else + { + imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + } + #else + imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + CY_SYS_CLK_IMO_TRIM1_REG = (uint32) imoTrim1Value; + + /* Zero out fine trim */ + CY_SYS_CLK_IMO_TRIM2_REG = CY_SYS_CLK_IMO_TRIM2_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM2_FSOFFSET_MASK); + + /* Apply TC trim */ + CY_SYS_CLK_IMO_TRIM3_REG = (CY_SYS_CLK_IMO_TRIM3_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM3_VALUES_MASK)) | + (CY_SFLASH_IMO_TCTRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) & CY_SYS_CLK_IMO_TRIM3_VALUES_MASK); + + CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); + + if (freq > CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + { + /* Select nearby intermediate frequency */ + CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) | + (((freq - 4u - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + + CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); + + /* Make small step to final frequency */ + /* Select nearby intermediate frequency */ + CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) | + (((freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + } + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (1u == wcoLock) + { + CySysClkImoEnableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if (1u == usbLock) + { + CySysClkImoEnableUsbLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CyExitCriticalSection(interruptState); + } + else + { + /* Halt CPU in debug mode if new frequency is invalid */ + CYASSERT(0u != 0u); + } + } + +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT) + /******************************************************************************* + * Function Name: CySysClkWriteHfclkDiv + ****************************************************************************//** + * + * Selects the pre-scaler divider value for HFCLK from IMO. + * + * The HFCLK predivider allows the device to divide the HFCLK selection mux + * input before use as HFCLK. The predivider is capable of dividing the HFCLK by + * powers of 2 between 1 and 8. + * + * PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers + * should be selected in a way, not to exceed 16 MHz for SYSCLK. + * + * If the SYSCLK clock frequency increases during the device operation, call + * \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the + * number of clock cycles the cache will wait before sampling data comes back + * from Flash. If the SYSCLK clock frequency decreases, you can call + * \ref CySysFlashSetWaitCycles() to improve the CPU performance. See + * \ref CySysFlashSetWaitCycles() description for more information. + * + * \param \ref CY_SYS_CLK_HFCLK_DIV_NODIV Transparent mode (w/o dividing) + * \param \ref CY_SYS_CLK_HFCLK_DIV_2 Divide selected clock source by 2 + * \param \ref CY_SYS_CLK_HFCLK_DIV_4 Divide selected clock source by 4 + * \param \ref CY_SYS_CLK_HFCLK_DIV_8 Divide selected clock source by 8 + * + *******************************************************************************/ + void CySysClkWriteHfclkDiv(uint32 divider) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & ((uint32) (~(CY_SYS_CLK_SELECT_HFCLK_DIV_MASK << + CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT)))) | + ((uint32)((divider & CY_SYS_CLK_SELECT_HFCLK_DIV_MASK) << CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT))); + + CyExitCriticalSection(interruptState); + } +#endif /* (CY_IP_SRSSLT) */ + + +#if (CY_IP_ECO) + + /******************************************************************************* + * Function Name: CySysClkEcoStart + ****************************************************************************//** + * + * Starts the External Crystal Oscillator (ECO). Refer to the device datasheet + * for the ECO startup time. + * + * The timeout interval is measured based on the system frequency defined by + * PSoC Creator at build time. If System clock frequency is changed in + * runtime, the \ref CyDelayFreq() with the appropriate parameter should be + * called. + * + * PSoC 4100 BLE / PSoC 4200 BLE: The WCO must be enabled prior to enabling ECO. + * + * \param timeoutUs Timeout in microseconds. + * + * If zero is specified, the function does not wait for timeout and returns + * CYRET_SUCCESS. If non-zero is specified, the function waits for the timeout. + * + * \return \ref CYRET_SUCCESS Completed successfully. The ECO is oscillating and + * amplitude reached 60% and it does not mean 24 MHz crystal is within 50 ppm. + * + * \return \ref CYRET_TIMEOUT Timeout occurred. If the crystal is not oscillating + * or amplitude didn't reach 60% after specified amount of time, CYRET_TIMEOUT + * is returned. + * + * \return \ref CYRET_BAD_PARAM One or more invalid parameters. + * + *******************************************************************************/ + cystatus CySysClkEcoStart(uint32 timeoutUs) + { + cystatus returnStatus = CYRET_SUCCESS; + + #if (CY_IP_ECO_BLESS) + /* Enable the RF oscillator band gap */ + CY_SYS_XTAL_BLESS_RF_CONFIG_REG |= CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; + + /* Update trimming register */ + CY_SYS_XTAL_BLERD_BB_XO_REG = CY_SYS_XTAL_BLERD_BB_XO_TRIM; + + /* Enable the Crystal */ + CY_SYS_XTAL_BLERD_DBUS_REG |= CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; + + #elif (CY_IP_ECO_BLESSV3) + uint32 regConfig; + uint32 intrRegMaskStore = 0u; + + if (0u != (CY_SYS_BLESS_MT_CFG_REG & (CY_SYS_BLESS_MT_CFG_ENABLE_BLERD << CYFLD_BLE_BLESS_ENABLE_BLERD__OFFSET))) + { + CY_SYS_BLESS_MT_CFG_REG |= (CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET); + } + else + { + /* Init BLE core */ + CY_SYS_BLESS_MT_DELAY_CFG_REG = CY_SYS_BLESS_MT_DELAY_CFG_INIT; + CY_SYS_BLESS_MT_DELAY_CFG2_REG = CY_SYS_BLESS_MT_DELAY_CFG2_INIT; + CY_SYS_BLESS_MT_DELAY_CFG3_REG = CY_SYS_BLESS_MT_DELAY_CFG3_INIT; + + /* RCB init */ + regConfig = CY_SYS_RCB_CTRL_REG; + regConfig &= CY_SYS_RCB_CTRL_CLEAR; + regConfig |= CY_SYS_RCB_CTRL_INIT; + CY_SYS_RCB_CTRL_REG = regConfig; + + intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; + if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG &= ~CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; + } + + /* Enable BLE core */ + regConfig = CY_SYS_BLESS_MT_CFG_REG; + regConfig &= CY_SYS_BLESS_MT_CFG_CLEAR; + regConfig |= CY_SYS_BLESS_MT_CFG_INIT; + CY_SYS_BLESS_MT_CFG_REG = regConfig; + + while(0u == ((CY_SYS_BLESS_BLERD_ACTIVE_INTR_STAT & CY_SYS_BLESS_INTR_STAT_REG))) + { + /* Wait until BLERD55 moves to active state */ + } + + if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG |= CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; + } + + /* Send write commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_NRST_SET; + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_DIG_CLK_SET; + + #if (CY_SYS_BLE_CLK_ECO_FREQ_32MHZ == CYDEV_ECO_CLK_MHZ) + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_DIV_SET; + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | CY_SYS_RCB_RBUS_IB_VAL); + #else + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_NODIV_SET; + #endif + + intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; + if(0u != (CY_SYS_RCB_INTR_RCB_DONE & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG &= ~(CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY); + } + + /* Send read commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RD_CMD | + (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET & ~CY_SYS_RCB_RBUS_VAL_MASK)); + + while (0u == (CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY & CY_SYS_RCB_INTR_REG)) + { + /* Wait until RX_FIFO_NOT_EMPTY state */ + } + + CY_SYS_RCB_INTR_REG |= CY_SYS_RCB_INTR_RCB_DONE; + + regConfig = CY_SYS_RCB_RX_FIFO_RD_REG & CY_SYS_RCB_RBUS_TRIM_MASK; + + /* Send write commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | regConfig | CY_SYS_RCB_RBUS_TRIM_VAL); + + while (0u == (CY_SYS_RCB_INTR_RCB_DONE & CY_SYS_RCB_INTR_REG)) + { + /* Wait until RCB_DONE state */ + } + + /* Clear Interrupt */ + CY_SYS_RCB_INTR_REG = CY_SYS_RCB_INTR_CLEAR; + + if(0u != ((CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY) & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG |= intrRegMaskStore; + } + + } + #else /* CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT */ + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_ENABLE; + CyDelayUs(CY_SYS_CLK_ECO_CONFIG_CLK_EN_TIMEOUT_US); + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_CLK_EN; + #endif /* (CY_IP_ECO_BLESS) */ + + if(timeoutUs > 0u) + { + returnStatus = CYRET_TIMEOUT; + + for( ; timeoutUs > 0u; timeoutUs--) + { + CyDelayUs(1u); + + if(0u != CySysClkEcoReadStatus()) + { + returnStatus = CYRET_SUCCESS; + break; + } + } + + } + + return(returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkEcoStop + ****************************************************************************//** + * + * Stops the megahertz crystal. + * + * If ECO is disabled when it is sourcing HFCLK, the CPU will halt. In addition, + * for PSoC 4100 BLE / PSoC 4200 BLE devices, the BLE sub-system will stop + * functioning. + * + *******************************************************************************/ + void CySysClkEcoStop(void) + { + #if (CY_IP_WCO_BLESS) + /* Disable the RF oscillator band gap */ + CY_SYS_XTAL_BLESS_RF_CONFIG_REG &= (uint32) ~CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; + + /* Disable the Crystal */ + CY_SYS_XTAL_BLERD_DBUS_REG &= (uint32) ~CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; + #elif (CY_IP_ECO_BLESSV3) + CY_SYS_BLESS_MT_CFG_REG &= ~(CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET); + #else + CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~(CY_SYS_CLK_ECO_CONFIG_ENABLE | CY_SYS_CLK_ECO_CONFIG_CLK_EN); + #endif /* (CY_IP_WCO_BLESS) */ + } + + + /******************************************************************************* + * Function Name: CySysClkEcoReadStatus + ****************************************************************************//** + * + * Reads the status bit for the megahertz crystal. + * + * For PSoC 4100 BLE / PSoC 4200 BLE devices, the status bit is the + * XO_AMP_DETECT bit in FSM register. + * + * For PSoC 4200L / 4100S with ECO devices, the error status bit is the + * WATCHDOG_ERROR bit in ECO_STATUS register. + * + * \return PSoC 4100 BLE/PSoC 4200 BLE: Non-zero indicates that ECO output + * reached 50 ppm and is oscillating in valid range. + * + * \return PSoC 4200L / 4100S with ECO: Non-zero indicates that ECO is running. + * + *******************************************************************************/ + uint32 CySysClkEcoReadStatus(void) + { + uint32 returnValue; + + #if (CY_IP_WCO_BLESS) + returnValue = CY_SYS_XTAL_BLERD_FSM_REG & CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT; + #elif (CY_IP_ECO_BLESSV3) + returnValue = (CY_SYS_BLESS_MT_STATUS_REG & CY_SYS_BLESS_MT_STATUS_CURR_STATE_MASK) >> CYFLD_BLE_BLESS_MT_CURR_STATE__OFFSET; + + returnValue = ((CY_SYS_BLESS_MT_STATUS_BLERD_IDLE == returnValue) || + (CY_SYS_BLESS_MT_STATUS_SWITCH_EN == returnValue) || + (CY_SYS_BLESS_MT_STATUS_ACTIVE == returnValue) || + (CY_SYS_BLESS_MT_STATUS_ISOLATE == returnValue)); + #else + returnValue = (0u != (CY_SYS_CLK_ECO_STATUS_REG & CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR)) ? 0u : 1u; + #endif /* (CY_IP_WCO_BLESS) */ + + return (returnValue); + } + + #if (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) + /******************************************************************************* + * Function Name: CySysClkWriteEcoDiv + ****************************************************************************//** + * + * Selects value for the ECO divider. + * + * The ECO must not be the HFCLK clock source when this function is called. + * The HFCLK source can be changed to the other clock source by call to the + * CySysClkWriteHfclkDirect() function. If the ECO sources the HFCLK this + * function will not have any effect if compiler in release mode, and halt the + * CPU when compiler in debug mode. + * + * If the SYSCLK clock frequency increases during the device operation, call + * CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number + * of clock cycles the cache will wait before sampling data comes back from + * Flash. If the SYSCLK clock frequency decreases, you can call + * CySysFlashSetWaitCycles() to improve the CPU performance. See + * CySysFlashSetWaitCycles() description for more information. + * + * \param divider Power of 2 divider selection. + * - \ref CY_SYS_CLK_ECO_DIV1 + * - \ref CY_SYS_CLK_ECO_DIV2 + * - \ref CY_SYS_CLK_ECO_DIV4 + * - \ref CY_SYS_CLK_ECO_DIV8 + * + *******************************************************************************/ + void CySysClkWriteEcoDiv(uint32 divider) + { + uint8 interruptState; + + if (CY_SYS_CLK_HFCLK_ECO != (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK)) + { + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG = (divider & CY_SYS_CLK_XTAL_CLK_DIV_MASK) | + (CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG & ((uint32) ~CY_SYS_CLK_XTAL_CLK_DIV_MASK)); + + CyExitCriticalSection(interruptState); + } + else + { + /* Halt CPU in debug mode if ECO sources HFCLK */ + CYASSERT(0u != 0u); + } + } + + #else + + /******************************************************************************* + * Function Name: CySysClkConfigureEcoTrim + ****************************************************************************//** + * + * Selects trim setting values for ECO. This API is available only for PSoC + * 4200L / 4100S with ECO devices only. + * + * The following parameters can be trimmed for ECO. The affected registers are + * ECO_TRIM0 and ECO_TRIM1. + * + * Watchdog trim - This bit field sets the error threshold below the steady + * state amplitude level. + * + * Amplitude trim - This bit field is to set the crystal drive level when + * ECO_CONFIG.AGC_EN = 1. WARNING: use care when setting this field because + * driving a crystal beyond its rated limit can permanently damage the crystal. + * + * Filter frequency trim - This bit field sets LPF frequency trim and affects + * the 3rd harmonic content. + * + * Feedback resistor trim - This bit field sets the feedback resistor trim and + * impacts the oscillation amplitude. + * + * Amplifier gain trim - This bit field sets the amplifier gain trim and affects + * the startup time of the crystal. + * + * Use care when setting the amplitude trim field because driving a crystal + * beyond its rated limit can permanently damage the crystal. + * + * \param wDTrim: Watchdog trim + * - \ref CY_SYS_CLK_ECO_WDTRIM0 Error threshold is 0.05 V + * - \ref CY_SYS_CLK_ECO_WDTRIM1 Error threshold is 0.10 V + * - \ref CY_SYS_CLK_ECO_WDTRIM2 Error threshold is 0.15 V + * - \ref CY_SYS_CLK_ECO_WDTRIM3 Error threshold is 0.20 V + * + * \param aTrim: Amplitude trim + * - \ref CY_SYS_CLK_ECO_ATRIM0 Amplitude is 0.3 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM1 Amplitude is 0.4 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM2 Amplitude is 0.5 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM3 Amplitude is 0.6 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM4 Amplitude is 0.7 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM5 Amplitude is 0.8 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM6 Amplitude is 0.9 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM7 Amplitude is 1.0 Vpp + * + * \param fTrim: Filter frequency trim + * - \ref CY_SYS_CLK_ECO_FTRIM0 Crystal frequency > 30 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM1 24 MHz < Crystal frequency <= 30 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM2 17 MHz < Crystal frequency <= 24 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM3 Crystal frequency <= 17 MHz + * + * \param rTrim: Feedback resistor trim + * - \ref CY_SYS_CLK_ECO_RTRIM0 Crystal frequency > 30 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM1 24 MHz < Crystal frequency <= 30 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM2 17 MHz < Crystal frequency <= 24 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM3 Crystal frequency <= 17 MHz + * + * \param gTrim: Amplifier gain trim. Calculate the minimum required gm + * (trans-conductance value). Divide the calculated gm value by 4.5 to + * obtain an integer value 'result'. For more information please refer + * to the device TRM. + * - \ref CY_SYS_CLK_ECO_GTRIM0 If result = 1 + * - \ref CY_SYS_CLK_ECO_GTRIM1 If result = 0 + * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 2 + * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 3 + * + *******************************************************************************/ + void CySysClkConfigureEcoTrim(uint32 wDTrim, uint32 aTrim, uint32 fTrim, uint32 rTrim, uint32 gTrim) + { + uint8 interruptState; + uint32 regTmp; + + interruptState = CyEnterCriticalSection(); + + regTmp = CY_SYS_CLK_ECO_TRIM0_REG & ~(CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK | CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK); + regTmp |= ((uint32) (wDTrim << CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK); + regTmp |= ((uint32) (aTrim << CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK); + CY_SYS_CLK_ECO_TRIM0_REG = regTmp; + + regTmp = CY_SYS_CLK_ECO_TRIM1_REG & ~(CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK | + CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK | + CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK); + regTmp |= ((uint32) (fTrim << CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK); + regTmp |= ((uint32) (rTrim << CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK); + regTmp |= ((uint32) (gTrim << CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK); + + CY_SYS_CLK_ECO_TRIM1_REG = regTmp; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkConfigureEcoDrive + ****************************************************************************//** + * + * Selects trim setting values for ECO based on crystal parameters. Use care + * when setting the driveLevel parameter because driving a crystal beyond its + * rated limit can permanently damage the crystal. + * + * This API is available only for PSoC 4200L / 4100S with ECO devices only. + * + * \param freq Frequency of the crystal in kHz. + * \param cLoad Crystal load capacitance in pF. + * \param esr Equivalent series resistance of the crystal in ohm. + * maxAmplitude: maximum amplitude level in mV. Calculate as + * ((sqrt(driveLevel in uW / 2 / esr))/(3.14 * freq * cLoad)) * 10^9. + * + * The Automatic Gain Control (AGC) is disabled when the specified maximum + * amplitude level equals or above 2. In this case the amplitude is not + * explicitly controlled and will grow until it saturates to the supply rail + * (1.8V nom). WARNING: use care when disabling AGC because driving a crystal + * beyond its rated limit can permanently damage the crystal. + * + * \return \ref CYRET_SUCCESS ECO configuration completed successfully. + * \return \ref CYRET_BAD_PARAM One or more invalid parameters. + * + *******************************************************************************/ + cystatus CySysClkConfigureEcoDrive(uint32 freq, uint32 cLoad, uint32 esr, uint32 maxAmplitude) + { + cystatus returnStatus = CYRET_SUCCESS; + + uint32 wDTrim; + uint32 aTrim; + uint32 fTrim; + uint32 rTrim; + uint32 gTrim; + + uint32 gmMin; + + + if ((maxAmplitude < CY_SYS_CLK_ECO_MAX_AMPL_MIN_mV) || + (freq < CY_SYS_CLK_ECO_FREQ_KHZ_MIN) || (freq > CY_SYS_CLK_ECO_FREQ_KHZ_MAX)) + { + returnStatus = CYRET_BAD_PARAM; + } + else + { + /* Calculate amplitude trim */ + aTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/100u) - 4u) : 7u; + + if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM0) + { + aTrim = CY_SYS_CLK_ECO_ATRIM0; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM1) + { + aTrim = CY_SYS_CLK_ECO_ATRIM1; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM2) + { + aTrim = CY_SYS_CLK_ECO_ATRIM2; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM3) + { + aTrim = CY_SYS_CLK_ECO_ATRIM3; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM4) + { + aTrim = CY_SYS_CLK_ECO_ATRIM4; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM5) + { + aTrim = CY_SYS_CLK_ECO_ATRIM5; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM6) + { + aTrim = CY_SYS_CLK_ECO_ATRIM6; + } + else + { + aTrim = CY_SYS_CLK_ECO_ATRIM7; + } + + /* Calculate Watchdog trim. */ + wDTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/200u) - 2u) : 3u; + + /* Calculate amplifier gain trim. */ + gmMin = (uint32) (((((CY_SYS_CLK_ECO_GMMIN_COEFFICIENT * freq * cLoad) / 1000) * ((freq * cLoad * esr) / 1000)) / 100u) / 4500000u); + if (gmMin > 3u) + { + returnStatus = CYRET_BAD_PARAM; + gTrim = 0u; + } + else if (gmMin > 1u) + { + gTrim = gmMin; + } + else + { + gTrim = (gmMin == 1u) ? 0u : 1u; + } + + /* Calculate feedback resistor trim */ + if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM0) + { + rTrim = CY_SYS_CLK_ECO_FTRIM0; + } + else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM1) + { + rTrim = CY_SYS_CLK_ECO_FTRIM1; + } + else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM2) + { + rTrim = CY_SYS_CLK_ECO_FTRIM2; + } + else + { + rTrim = CY_SYS_CLK_ECO_FTRIM3; + } + + /* Calculate filter frequency trim */ + fTrim = rTrim; + + CySysClkConfigureEcoTrim(wDTrim, aTrim, fTrim, rTrim, gTrim); + + /* Automatic Gain Control (AGC) enable */ + if (maxAmplitude < 2u) + { + /* The oscillation amplitude is controlled to the level selected by amplitude trim */ + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_AGC_EN; + } + else + { + /* The amplitude is not explicitly controlled and will grow until it saturates to the + * supply rail (1.8V nom). + */ + CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_ECO_CONFIG_AGC_EN; + } + } + + return (returnStatus); + } + + #endif /* CY_IP_ECO_BLESS */ + +#endif /* (CY_IP_ECO) */ + + +#if (CY_IP_PLL) + /******************************************************************************* + * Function Name: CySysClkPllStart + ****************************************************************************//** + * + * Enables the PLL. Optionally waits for it to become stable. Waits at least + * 250 us or until it is detected that the PLL is stable. + * + * Clears the unlock occurred status bit by calling CySysClkPllGetUnlockStatus(), + * once the PLL is locked if the wait parameter is 1). + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param wait: + * 0 - Return immediately after configuration. + * 1 - Wait for PLL lock or timeout. This API shall use the CyDelayUs() to + * implement the timeout feature. + * + * \return CYRET_SUCCESS Completed successfully. + * \return CYRET_TIMEOUT The timeout occurred without detecting a stable clock. + * If the input source of the clock is jittery, then the lock indication may + * not occur. However, after the timeout has expired, the generated PLL clock can + * still be used. + * \return CYRET_BAD_PARAM - Either the PLL or wait parameter is invalid. + * + *******************************************************************************/ + cystatus CySysClkPllStart(uint32 pll, uint32 wait) + { + uint32 counts = CY_SYS_CLK_PLL_MAX_STARTUP_US; + uint8 interruptState; + cystatus returnStatus = CYRET_SUCCESS; + + if((pll < CY_IP_PLL_NR) && (wait <= 1u)) + { + interruptState = CyEnterCriticalSection(); + + /* Isolate PLL outputs */ + CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~CY_SYS_CLK_PLL_CONFIG_ISOLATE; + + /* Enable PLL */ + CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ENABLE; + + CyExitCriticalSection(interruptState); + + /* De-isolate >= CY_SYS_CLK_PLL_MIN_STARTUP_US after PLL enabled */ + CyDelayUs(CY_SYS_CLK_PLL_MIN_STARTUP_US); + interruptState = CyEnterCriticalSection(); + CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ISOLATE; + CyExitCriticalSection(interruptState); + + if(wait != 0u) + { + returnStatus = CYRET_TIMEOUT; + + while(0u != counts) + { + + if(0u != CySysClkPllGetLockStatus(pll)) + { + returnStatus = CYRET_SUCCESS; + (void) CySysClkPllGetUnlockStatus(pll); + break; + } + + CyDelayUs(1u); + counts--; + } + } + } + else + { + returnStatus = CYRET_BAD_PARAM; + } + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetLockStatus + ****************************************************************************//** + * + * Returns non-zero if the output of the specified PLL output is locked. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return A non-zero value when the specified PLL is locked. + * + *******************************************************************************/ + uint32 CySysClkPllGetLockStatus(uint32 pll) + { + uint8 interruptState; + uint32 returnStatus; + + CYASSERT(pll < CY_IP_PLL_NR); + + interruptState = CyEnterCriticalSection(); + + /* PLL is locked if reported so for two consecutive read. */ + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; + if(0u != returnStatus) + { + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + /******************************************************************************* + * Function Name: CySysClkPllStop + ****************************************************************************//** + * + * Disables the PLL. + * + * Ensures that either PLL is not the source of HFCLK before it is disabled, + * otherwise, the CPU will halt. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + *******************************************************************************/ + void CySysClkPllStop(uint32 pll) + { + uint8 interruptState; + + if (pll < CY_IP_PLL_NR) + { + interruptState = CyEnterCriticalSection(); + CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~(CY_SYS_CLK_PLL_CONFIG_ISOLATE | CY_SYS_CLK_PLL_CONFIG_ENABLE); + CyExitCriticalSection(interruptState); + } + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetPQ + ****************************************************************************//** + * + * Sets feedback (P) and reference the (Q) divider value. This API also sets the + * programmable charge pump current value. Note that the PLL has to be disabled + * before calling this API. If this function is called while any PLL is sourcing, + * the SYSCLK will return an error. + * + * The PLL must not be the system clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param feedback The P divider. Range 4 - 259. Control bits for the feedback + * divider. + * + * \param reference The Q divider. Range 1 - 64. Divide by the reference. + * + * \param current Charge the pump current in uA. The 2 uA for output frequencies + * of 67 MHz or less, and 3 uA for higher output frequencies. The default + * value is 2 uA. + * + * \return CYRET_SUCCESS Completed successfully. + * \return CYRET_BAD_PARAM The parameters are out of range or the specified PLL + * sources the system clock. + * + *******************************************************************************/ + cystatus CySysClkPllSetPQ(uint32 pll, uint32 feedback, uint32 reference, uint32 current) + { + uint32 regTmp; + cystatus tmp; + uint8 interruptState; + cystatus returnStatus = CYRET_BAD_PARAM; + + interruptState = CyEnterCriticalSection(); + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && + (feedback >= CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MIN) && (feedback <= CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MAX) && + (reference >= CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MIN) && (reference <= CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MAX) && + (current >= CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MIN ) && (current <= CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MAX) && + (CYRET_SUCCESS == tmp)) + { + /* Set new feedback, reference and current values */ + regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK | + CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK | + CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK); + + regTmp |= ((feedback << CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK); + regTmp |= (((reference - 1u) << CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK); + regTmp |= ((current << CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT) & CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK); + + CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; + + returnStatus = CYRET_SUCCESS; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetBypassMode + ****************************************************************************//** + * + * Sets the bypass mode for the specified PLL. + * + * The PLL must not be the system clock source when calling this function. + * The PLL output will glitch during this function call. + * + * When the PLL's reference input is higher than HFCLK frequency the device may + * lock due to incorrect flash wait cycle configuration and bypass switches from + * PLL output to the reference input. See description of + * CySysFlashSetWaitCycles() for more information. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param bypass: The bypass mode. + * CY_SYS_PLL_BYPASS_AUTO - Automatic usage of the lock indicator. When unlocked, + * automatically selects PLL the reference input (bypass mode). When locked, + * automatically selects the PLL output. + * + * CY_SYS_PLL_BYPASS_PLL_REF - Selects the PLL reference input (bypass mode). + * Ignores the lock indicator. + * + * CY_SYS_PLL_BYPASS_PLL_OUT - Selects the PLL output. Ignores the lock indicator. + * + *******************************************************************************/ + void CySysClkPllSetBypassMode(uint32 pll, uint32 bypass) + { + uint32 regTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + if ((pll < CY_IP_PLL_NR) && (bypass <= CY_SYS_PLL_BYPASS_PLL_OUT)) + { + regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK; + regTmp |= (uint32)(bypass << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT); + CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetBypassMode + ****************************************************************************//** + * + * Gets the bypass mode for the specified PLL. + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param bypass: Bypass mode. + * The same as the parameter of the CySysClkPllSetBypassMode(). + * + *******************************************************************************/ + static uint32 CySysClkPllGetBypassMode(uint32 pll) + { + uint32 returnValue; + uint8 interruptState; + + CYASSERT(pll < CY_IP_PLL_NR); + + interruptState = CyEnterCriticalSection(); + + returnValue = CY_SYS_CLK_PLL_BASE.pll[pll].config & CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK; + returnValue = returnValue >> CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT; + + CyExitCriticalSection(interruptState); + + return (returnValue); + } + + + /******************************************************************************* + * Function Name: CySysClkPllConfigChangeAllowed + ****************************************************************************//** + * + * The function returns non-zero value if the specified PLL sources the System + * clock and the PLL is not in the bypass mode. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return Non-zero value when the specified PLL sources the System clock and + * the PLL is not in the bypass mode. + * + *******************************************************************************/ + static cystatus CySysClkPllConfigChangeAllowed(uint32 pll) + { + uint32 pllBypassMode; + uint32 sysclkSource; + cystatus returnValue = CYRET_INVALID_STATE; + + sysclkSource = CySysClkGetSysclkSource(); + pllBypassMode = CySysClkPllGetBypassMode(pll); + + if ((CY_SYS_PLL_BYPASS_PLL_REF == pllBypassMode) || + ((CY_SYS_CLK_HFCLK_PLL0 != sysclkSource) && (0u == pll)) + #if (CY_IP_SRSSV2) + || ((CY_SYS_CLK_HFCLK_PLL1 != sysclkSource) && (1u == pll)) + #endif /* (CY_IP_SRSSV2) */ + ) + { + returnValue = CYRET_SUCCESS; + } + + return (returnValue); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetUnlockStatus + ****************************************************************************//** + * + * Returns a non-zero value if the specified PLL output was unlocked. + * The unlock status is an indicator that the PLL has lost a lock at least once + * during its operation. The unlock status is cleared once it is read using + * this API. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return Non-zero value when the specified PLL was unlocked. + * + *******************************************************************************/ + uint32 CySysClkPllGetUnlockStatus(uint32 pll) + { + uint32 returnStatus = 0u; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].test & CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK; + CY_SYS_CLK_PLL_BASE.pll[pll].test |= CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK; + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetFrequency + ****************************************************************************//** + * + * Configures either PLL#0 or PLL#1 for the requested input/output frequencies. + * The input frequency is the frequency of the source to the PLL. The source is + * set using the CySysClkPllSetSource() function. + * + * The PLL must not be the system clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param pll: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param inputFreq The reference frequency in KHz. The valid range is from 1000 to 49152 KHz. + * + * \param pllFreq The target frequency in KHz. The valid range is from 22500 to 49152 KHz. + * + * \param divider The output clock divider for the PLL: + * CY_SYS_PLL_OUTPUT_DIVPASS Pass Through + * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 + * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 + * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 + * + * \param freqTol The tolerance in ppm, 10 ppm is equal to 0.001%. + * + * \return CYRET_SUCCESS The PLL was successfully configured for the requested + * frequency. + * + * \return CYRET_BAD_PARAM The PLL was not able to successfully configure for the + * requested frequency. + * + *******************************************************************************/ + cystatus CySysClkPllSetFrequency(uint32 pll, uint32 inputFreq, uint32 pllFreq, uint32 divider, uint32 freqTol) + { + uint32 qMin; + uint32 qMax; + + uint32 qVal = CY_SYS_CLK_PLL_INVALID; + uint32 pVal = CY_SYS_CLK_PLL_INVALID; + + uint32 q; + uint32 p; + + uint32 fvco; + int32 ferr; + + cystatus tmp; + cystatus returnStatus = CYRET_BAD_PARAM; + + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && + (inputFreq >= CY_SYS_CLK_PLL_INPUT_FREQ_MIN ) && (inputFreq <= CY_SYS_CLK_PLL_INPUT_FREQ_MAX) && + (pllFreq >= CY_SYS_CLK_PLL_OUTPUT_FREQ_MIN ) && (pllFreq <= CY_SYS_CLK_PLL_OUTPUT_FREQ_MAX) && + (divider <= CY_SYS_PLL_OUTPUT_DIV8) && + (CYRET_SUCCESS == tmp)) + { + + /* Minimum feed forward loop divisor */ + qMin = (inputFreq + (CY_SYS_CLK_PLL_FPFDMAX - 1u)) / CY_SYS_CLK_PLL_FPFDMAX; + qMin = (qMin < CY_SYS_CLK_PLL_QMINIP) ? CY_SYS_CLK_PLL_QMINIP : qMin; + + /* Maximum feed forward loop divisor */ + qMax = inputFreq / CY_SYS_CLK_PLL_FPFDMIN; + qMax = (qMax > CY_SYS_CLK_PLL_QMAXIP) ? CY_SYS_CLK_PLL_QMAXIP : qMax; + + if (qMin <= qMax) + { + for(q = qMin; q <= qMax; q++) + { + /* Solve for the feedback divisor value */ + + /* INT((pllFreq * q ) / inputFreq), where INT is normal rounding */ + p = ((pllFreq * q) + (inputFreq / 2u)) / inputFreq; + + /* Calculate the actual VCO frequency (FVCO) */ + fvco = ((inputFreq * p) / q); + + /* Calculate the frequency error (FERR) */ + ferr = ((1000000 * ((int32) fvco - (int32) pllFreq))/ (int32) pllFreq); + + /* Bound check the frequency error and decide next action */ + if ((( -1 * (int32) freqTol) <= ferr) && (ferr <= (int32) freqTol)) + { + qVal = q; + pVal = p; + break; + } + } + + + if ((pVal != CY_SYS_CLK_PLL_INVALID) && (qVal != CY_SYS_CLK_PLL_INVALID)) + { + if (CySysClkPllSetPQ(pll, pVal, qVal, CY_SYS_CLK_PLL_CURRENT_DEFAULT) == CYRET_SUCCESS) + { + returnStatus = CySysClkPllSetOutputDivider(pll, divider); + } + } + } + + } + + return (returnStatus); + } + + /******************************************************************************* + * Function Name: CySysClkPllSetSource + ****************************************************************************//** + * + * Sets the input clock source to the PLL. The PLL must be disabled before + * calling this function. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param source: + * CY_SYS_PLL_SOURCE_IMO IMO + * CY_SYS_PLL_SOURCE_EXTCLK External Clock (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_ECO ECO + * CY_SYS_PLL_SOURCE_DSI0 DSI_OUT[0] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI1 DSI_OUT[1] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI2 DSI_OUT[2] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI3 DSI_OUT[3] (available only for PSoC 4200L) + * + *******************************************************************************/ + void CySysClkPllSetSource(uint32 pll, uint32 source) + { + uint32 regTmp; + uint8 interruptState; + + #if (CY_IP_SRSSLT) + uint8 i = 0u; + #endif /* (CY_IP_SRSSLT) */ + + interruptState = CyEnterCriticalSection(); + + if (pll < CY_IP_PLL_NR) + { + #if(CY_IP_SRSSV2) + regTmp = CY_SYS_CLK_SELECT_REG & (uint32) ~CY_SYS_CLK_SELECT_PLL_MASK(pll); + regTmp |= ((source << CY_SYS_CLK_SELECT_PLL_SHIFT(pll)) & CY_SYS_CLK_SELECT_PLL_MASK(pll)); + CY_SYS_CLK_SELECT_REG = regTmp; + #else + regTmp = CY_SYS_ECO_CLK_SELECT_REG & (uint32) ~CY_SYS_ECO_CLK_SELECT_PLL0_MASK; + regTmp |= ((source << CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT) & CY_SYS_ECO_CLK_SELECT_PLL0_MASK); + CY_SYS_ECO_CLK_SELECT_REG = regTmp; + + /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) + { + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + } + + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + #endif /* (CY_IP_SRSSV2) */ + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetOutputDivider + ****************************************************************************//** + * + * Sets the output clock divider for the PLL. + * + * The PLL must not be the System Clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param divider: + * CY_SYS_PLL_OUTPUT_DIVPASS Pass through + * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 + * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 + * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 + * + * \return \ref CYRET_SUCCESS Completed successfully. + * \return \ref CYRET_BAD_PARAM The parameters are out of range or the + * specified PLL sources the System clock. + * + *******************************************************************************/ + cystatus CySysClkPllSetOutputDivider(uint32 pll, uint32 divider) + { + uint32 tmpReg; + uint8 interruptState; + cystatus returnStatus = CYRET_BAD_PARAM; + cystatus tmp; + + + interruptState = CyEnterCriticalSection(); + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && (CYRET_SUCCESS == tmp) && (divider <= CY_SYS_PLL_OUTPUT_DIV8)) + { + tmpReg = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK); + tmpReg |= ((divider << CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK); + + CY_SYS_CLK_PLL_BASE.pll[pll].config = tmpReg; + + returnStatus = CYRET_SUCCESS; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } +#endif /* (CY_IP_PLL) */ + + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Function Name: CySysLvdEnable + ****************************************************************************//** + * + * Enables the output of the low-voltage monitor when Vddd is at or below the + * trip point, configures the device to generate an interrupt, and sets the + * voltage trip level. + * + * \param threshold: Threshold selection for Low Voltage Detect circuit. + * Threshold variation is +/- 2.5% from these typical voltage choices. + * Define Voltage threshold + * CY_LVD_THRESHOLD_1_75_V 1.7500 V + * CY_LVD_THRESHOLD_1_80_V 1.8000 V + * CY_LVD_THRESHOLD_1_90_V 1.9000 V + * CY_LVD_THRESHOLD_2_00_V 2.0000 V + * CY_LVD_THRESHOLD_2_10_V 2.1000 V + * CY_LVD_THRESHOLD_2_20_V 2.2000 V + * CY_LVD_THRESHOLD_2_30_V 2.3000 V + * CY_LVD_THRESHOLD_2_40_V 2.4000 V + * CY_LVD_THRESHOLD_2_50_V 2.5000 V + * CY_LVD_THRESHOLD_2_60_V 2.6000 V + * CY_LVD_THRESHOLD_2_70_V 2.7000 V + * CY_LVD_THRESHOLD_2_80_V 2.8000 V + * CY_LVD_THRESHOLD_2_90_V 2.9000 V + * CY_LVD_THRESHOLD_3_00_V 3.0000 V + * CY_LVD_THRESHOLD_3_20_V 3.2000 V + * CY_LVD_THRESHOLD_4_50_V 4.5000 V + * + *******************************************************************************/ + void CySysLvdEnable(uint32 threshold) + { + /* Prevent propagating a false interrupt */ + CY_LVD_PWR_INTR_MASK_REG &= (uint32) ~CY_LVD_PROPAGATE_INT_TO_CPU; + + /* Set specified threshold */ + CY_LVD_PWR_VMON_CONFIG_REG = (CY_LVD_PWR_VMON_CONFIG_REG & ~CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK) | + ((threshold << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT) & CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK); + + /* Enable the LVD. This may cause a false LVD event. */ + CY_LVD_PWR_VMON_CONFIG_REG |= CY_LVD_PWR_VMON_CONFIG_LVD_EN; + + /* Wait for the circuit to stabilize */ + CyDelayUs(CY_LVD_STABILIZE_TIMEOUT_US); + + /* Clear the false event */ + CySysLvdClearInterrupt(); + + /* Unmask the interrupt */ + CY_LVD_PWR_INTR_MASK_REG |= CY_LVD_PROPAGATE_INT_TO_CPU; + } + + + /******************************************************************************* + * Function Name: CySysLvdDisable + ****************************************************************************//** + * + * Disables the low voltage detection. A low voltage interrupt is disabled. + * + *******************************************************************************/ + void CySysLvdDisable(void) + { + CY_LVD_PWR_INTR_MASK_REG &= ~CY_LVD_PROPAGATE_INT_TO_CPU; + CY_LVD_PWR_VMON_CONFIG_REG &= ~CY_LVD_PWR_VMON_CONFIG_LVD_EN; + } + + + /******************************************************************************* + * Function Name: CySysLvdGetInterruptSource + ****************************************************************************//** + * + * Gets the low voltage detection interrupt status (without clearing). + * + * \return + * Interrupt request value: + * CY_SYS_LVD_INT - Indicates an Low Voltage Detect interrupt + * + *******************************************************************************/ + uint32 CySysLvdGetInterruptSource(void) + { + return (CY_LVD_PWR_INTR_REG & CY_SYS_LVD_INT); + } + + + /******************************************************************************* + * Function Name: CySysLvdClearInterrupt + ****************************************************************************//** + * + * Clears the low voltage detection interrupt status. + * + * \return + * None + * + *******************************************************************************/ + void CySysLvdClearInterrupt(void) + { + CY_LVD_PWR_INTR_REG = CY_SYS_LVD_INT; + } + +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Function Name: CySysGetResetReason +****************************************************************************//** +* +* Reports the cause for the latest reset(s) that occurred in the system. All +* the bits in the RES_CAUSE register assert when the corresponding reset cause +* occurs and must be cleared by the firmware. These bits are cleared by the +* hardware only during XRES, POR, or a detected brown-out. +* +* \param reason: bits in the RES_CAUSE register to clear. +* CY_SYS_RESET_WDT - WDT caused a reset +* CY_SYS_RESET_PROTFAULT - Occured protection violation that requires reset +* CY_SYS_RESET_SW - Cortex-M0 requested a system reset. +* +* \return +* Status. Same enumerated bit values as used for the reason parameter. +* +*******************************************************************************/ +uint32 CySysGetResetReason(uint32 reason) +{ + uint32 returnStatus; + + reason &= (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); + returnStatus = CY_SYS_RES_CAUSE_REG & + (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); + CY_SYS_RES_CAUSE_REG = reason; + + return (returnStatus); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +****************************************************************************//** +* +* Disables all interrupts. +* +* \return +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + + /* Get current interrupt state. */ + intState = CY_INT_CLEAR_REG; + + /* Disable all interrupts. */ + CY_INT_CLEAR_REG = CY_INT_CLEAR_DISABLE_ALL; + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +****************************************************************************//** +* +* Enables interrupts to a given state. +* +* \param mask The 32 bit mask of interrupts to enable. +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + CY_INT_ENABLE_REG = mask; +} + + +/******************************************************************************* +* Function Name: CyIntSetSysVector +****************************************************************************//** +* +* Sets the interrupt vector of the specified system interrupt number. These +* interrupts are for SysTick, PendSV and others. +* +* \param number: System interrupt number: +* CY_INT_NMI_IRQN - Non Maskable Interrupt +* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +* CY_INT_SVCALL_IRQN - SV Call Interrupt +* CY_INT_PEND_SV_IRQN - Pend SV Interrupt +* CY_INT_SYSTICK_IRQN - System Tick Interrupt +* +* \param address Pointer to an interrupt service routine. +* +* \return The old ISR vector at this location. +* +*******************************************************************************/ +cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) +{ + cyisraddress oldIsr; + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_INT_IRQ_BASE); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number] = address; + + return(oldIsr); +} + + +/******************************************************************************* +* Function Name: CyIntGetSysVector +****************************************************************************//** +* +* Gets the interrupt vector of the specified system interrupt number. These +* interrupts are for SysTick, PendSV and others. +* +* \param number: System interrupt number: +* CY_INT_NMI_IRQN - Non Maskable Interrupt +* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +* CY_INT_SVCALL_IRQN - SV Call Interrupt +* CY_INT_PEND_SV_IRQN - Pend SV Interrupt +* CY_INT_SYSTICK_IRQN - System Tick Interrupt +* +* \return Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress CyIntGetSysVector(uint8 number) +{ + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_INT_IRQ_BASE); + + return(ramVectorTable[number]); +} + + +/******************************************************************************* +* Function Name: CyIntSetVector +****************************************************************************//** +* +* Sets the interrupt vector of the specified interrupt number. +* +* \param number Valid range [0-31]. Interrupt number +* \param address Pointer to an interrupt service routine +* +* \return Previous interrupt vector value. +* +*******************************************************************************/ +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) +{ + cyisraddress oldIsr; + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + number]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + number] = address; + + return(oldIsr); +} + + +/******************************************************************************* +* Function Name: CyIntGetVector +****************************************************************************//** +* +* Gets the interrupt vector of the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number +* +* \return Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress CyIntGetVector(uint8 number) +{ + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + return (ramVectorTable[CY_INT_IRQ_BASE + number]); +} + +/******************************************************************************* +* Function Name: CyIntSetPriority +****************************************************************************//** +* +* Sets the priority of the interrupt. +* +* \param priority: Priority of the interrupt. 0 - 3, 0 being the highest. +* \param number: The number of the interrupt, 0 - 31. +* +*******************************************************************************/ +void CyIntSetPriority(uint8 number, uint8 priority) +{ + uint8 interruptState; + uint32 shift; + uint32 value; + + CYASSERT(priority <= CY_MIN_PRIORITY); + CYASSERT(number < CY_NUM_INTERRUPTS); + + shift = CY_INT_PRIORITY_SHIFT(number); + + interruptState = CyEnterCriticalSection(); + + value = CY_INT_PRIORITY_REG(number); + value &= (uint32)(~((uint32)(CY_INT_PRIORITY_MASK << shift))); + value |= ((uint32)priority << shift); + CY_INT_PRIORITY_REG(number) = value; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyIntGetPriority +****************************************************************************//** +* +* Gets the priority of the interrupt. +* +* \param number: The number of the interrupt, 0 - 31. +* +* \return +* Priority of the interrupt. 0 - 3, 0 being the highest. +* +*******************************************************************************/ +uint8 CyIntGetPriority(uint8 number) +{ + uint8 priority; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + priority = (uint8) (CY_INT_PRIORITY_REG(number) >> CY_INT_PRIORITY_SHIFT(number)); + + return (priority & (uint8) CY_INT_PRIORITY_MASK); +} + + +/******************************************************************************* +* Function Name: CyIntEnable +****************************************************************************//** +* +* Enables the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number +* +*******************************************************************************/ +void CyIntEnable(uint8 number) +{ + CY_INT_ENABLE_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyIntGetState +****************************************************************************//** +* +* Gets the enable state of the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +* \return +* Enable status: 1 if enabled, 0 if disabled +* +*******************************************************************************/ +uint8 CyIntGetState(uint8 number) +{ + /* Get state of interrupt. */ + return ((0u != (CY_INT_ENABLE_REG & ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)))) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyIntDisable +****************************************************************************//** +* +* Disables the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntDisable(uint8 number) +{ + CY_INT_CLEAR_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + +/******************************************************************************* +* Function Name: CyIntSetPending +****************************************************************************//** +* +* Forces the specified interrupt number to be pending. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntSetPending(uint8 number) +{ + CY_INT_SET_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyIntClearPending +****************************************************************************//** +* +* Clears any pending interrupt for the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntClearPending(uint8 number) +{ + CY_INT_CLR_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyHalt +****************************************************************************//** +* +* Halts the CPU. +* +* \param reason: Value to be used during debugging. +* +*******************************************************************************/ +void CyHalt(uint8 reason) +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +****************************************************************************//** +* +* Forces a software reset of the device. +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + /*************************************************************************** + * Setting the system reset request bit. The vector key value must be written + * to the register, otherwise the register write is unpredictable. + ***************************************************************************/ + CY_SYS_AIRCR_REG = (CY_SYS_AIRCR_REG & (uint32)(~CY_SYS_AIRCR_VECTKEY_MASK)) | + CY_SYS_AIRCR_VECTKEY | CY_SYS_AIRCR_SYSRESETREQ; +} + + +/******************************************************************************* +* Function Name: CyDelay +****************************************************************************//** +* +* Blocks for milliseconds. +* +* \param milliseconds: number of milliseconds to delay. +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) +{ + while (milliseconds > CY_DELAY_MS_OVERFLOW) + { + /* This loop prevents overflow. + * At 100MHz, milliseconds * cydelayFreqKhz overflows at about 42 seconds + */ + CyDelayCycles(cydelay32kMs); + milliseconds -= CY_DELAY_MS_OVERFLOW; + } + + CyDelayCycles(milliseconds * cydelayFreqKhz); +} + + +/******************************************************************************* +* Function Name: CyDelayUs +****************************************************************************//** +* Blocks for microseconds. +* +* \param microseconds: number of microseconds to delay. +* +*******************************************************************************/ +void CyDelayUs(uint16 microseconds) +{ + CyDelayCycles((uint32)microseconds * cydelayFreqMhz); +} + + +/******************************************************************************* +* Function Name: CyDelayFreq +****************************************************************************//** +* Sets clock frequency for CyDelay. +* +* \param freq: Frequency of bus clock in Hertz. +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) +{ + if (freq != 0u) + { + cydelayFreqHz = freq; + } + else + { + cydelayFreqHz = CYDEV_BCLK__SYSCLK__HZ; + } + + cydelayFreqMhz = (uint8)((cydelayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cydelayFreqKhz = (cydelayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cydelay32kMs = CY_DELAY_MS_OVERFLOW * cydelayFreqKhz; +} + + +/******************************************************************************* +* Function Name: CySysTick_Start +****************************************************************************//** +* +* Starts the system timer (SysTick): configures SysTick to generate interrupt +* every 1 ms and enables the interrupt. +* +* There are components (LIN, CapSense Gesture) that relies on the default +* interval (1 ms). And that changing the interval will negatively impact +* their functionality. +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +void CySysTickStart(void) +{ + if (0u == CySysTickInitVar) + { + CySysTickInit(); + CySysTickInitVar = 1u; + } + + CySysTickEnable(); +} + + +/******************************************************************************* +* Function Name: CySysTickInit +****************************************************************************//** +* +* Initializes the callback addresses with pointers to NULL, associates the +* SysTick system vector with the function that is responsible for calling +* registered callback functions, configures SysTick timer to generate interrupt +* every 1 ms. +* +* The 1 ms interrupt interval is configured based on the frequency determined +* by PSoC Creator at build time. If System clock frequency is changed in +* runtime, the CyDelayFreq() with the appropriate parameter should be called. +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +void CySysTickInit(void) +{ + uint32 i; + + for (i = 0u; i> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ); + } + +#endif /* (CY_SYSTICK_LFCLK_SOURCE) */ + + +/******************************************************************************* +* Function Name: CySysTickGetCountFlag +****************************************************************************//** +* +* The count flag is set once SysTick counter reaches zero. +* The flag cleared on read. +* +* \return + * Returns non-zero value if flag is set, otherwise zero is returned. +* +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +uint32 CySysTickGetCountFlag(void) +{ + return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); +} + + +/******************************************************************************* +* Function Name: CySysTickClear +****************************************************************************//** +* +* Clears the SysTick counter for well-defined startup. +* +*******************************************************************************/ +void CySysTickClear(void) +{ + CY_SYS_SYST_CVR_REG = 0u; +} + + +/******************************************************************************* +* Function Name: CySysTickSetCallback +****************************************************************************//** +* +* This function allows up to five user-defined interrupt service routine +* functions to be associated with the SysTick interrupt. These are specified +* through the use of pointers to the function. +* +* To set a custom callback function without the overhead of the system provided +* one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress
), +* where
is address of the custom defined interrupt service routine. +* Note: a custom callback function overrides the system defined callback +* functions. +* +* \param number: The number of the callback function addresses to be set. The valid +* range is from 0 to 4. +* +* void(*CallbackFunction(void): A pointer to the function that will be +* associated with the SysTick ISR for the +* specified number. +* +* \return +* Returns the address of the previous callback function. +* The NULL is returned if the specified address in not set. +* +* \sideeffect +* The registered callback functions will be executed in the interrupt. +* +*******************************************************************************/ +cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) +{ + cySysTickCallback retVal; + + retVal = CySysTickCallbacks[number]; + CySysTickCallbacks[number] = function; + return (retVal); +} + + +/******************************************************************************* +* Function Name: CySysTickGetCallback +****************************************************************************//** +* +* The function get the specified callback pointer. +* +* \param number: The number of callback function address to get. The valid +* range is from 0 to 4. +* +* \return +* Returns the address of the specified callback function. +* The NULL is returned if the specified address in not initialized. +* +*******************************************************************************/ +cySysTickCallback CySysTickGetCallback(uint32 number) +{ + return ((cySysTickCallback) CySysTickCallbacks[number]); +} + + +/******************************************************************************* +* Function Name: CySysTickServiceCallbacks +****************************************************************************//** +* +* System Tick timer interrupt routine +* +*******************************************************************************/ +static void CySysTickServiceCallbacks(void) +{ + uint32 i; + + /* Verify that tick timer flag was set */ + if (1u == CySysTickGetCountFlag()) + { + for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + { + if (CySysTickCallbacks[i] != (void *) 0) + { + (void)(CySysTickCallbacks[i])(); + } + } + } +} + + +/******************************************************************************* +* Function Name: CyGetUniqueId +****************************************************************************//** +* +* Returns the 64-bit unique ID of the device. The uniqueness of the number is +* guaranteed for 10 years due to the die lot number having a cycle life of 10 +* years and even after 10 years, the probability of getting two identical +* numbers is very small. +* +* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns +* the 64-bit unique ID of the device by loading them into the integer array +* pointed to by uniqueId. +* +*******************************************************************************/ +void CyGetUniqueId(uint32* uniqueId) +{ +#if(CY_PSOC4) + uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 ); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u); + + uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X ); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u); +#else + uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB )); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u); + + uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC )); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u); +#endif /* (CY_PSOC4) */ +} + + +#if (CY_IP_DMAC_PRESENT) + /******************************************************************************* + * Function Name: CySysSetRamAccessArbPriority + ****************************************************************************//** + * + * Sets RAM access priority between CPU and DMA. The RAM_CTL register is + * configured to set the priority. Please refer to the device TRM for more + * details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetRamAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_RAM_CTL_REG & ~CY_SYS_CPUSS_RAM_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT) & CY_SYS_CPUSS_RAM_CTL_ARB_MASK); + CY_SYS_CPUSS_RAM_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetFlashAccessArbPriority + ****************************************************************************//** + * + * Sets flash access priority between CPU and DMA. The FLASH_CTL register is + * configured to set the priority. Please refer to the device TRM for more + * details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetFlashAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_FLASH_CTL_REG & ~CY_SYS_CPUSS_FLASH_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT) & CY_SYS_CPUSS_FLASH_CTL_ARB_MASK); + CY_SYS_CPUSS_FLASH_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetDmacAccessArbPriority + ****************************************************************************//** + * + * Sets DMAC slave interface access priority between CPU and DMA. The DMAC_CTL + * register is configured to set the priority. Please refer to the device TRM + * for more details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetDmacAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_DMAC_CTL_REG & ~CY_SYS_CPUSS_DMAC_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT) & CY_SYS_CPUSS_DMAC_CTL_ARB_MASK); + CY_SYS_CPUSS_DMAC_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetPeripheralAccessArbPriority + ****************************************************************************//** + * + * Sets slave peripheral interface access priority between CPU and DMA. + * The SL_CTL register is configured to set the priority. Please refer to the + * device TRM for more details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param interfaceNumber: the slave interface number. Please refer to the + * device TRM for more details. + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetPeripheralAccessArbPriority(uint32 interfaceNumber, uint32 source) + { + uint32 regTmp; + + if (interfaceNumber == 0u) + { + regTmp = CY_SYS_CPUSS_SL_CTL0_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL0_REG = regTmp; + } else + #if (CY_IP_SL_NR >= 2) + if (interfaceNumber == 1u) + { + regTmp = CY_SYS_CPUSS_SL_CTL1_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL1_REG = regTmp; + } else + #endif /* (CY_IP_SL_NR >= 1) */ + #if (CY_IP_SL_NR >= 3) + if (interfaceNumber == 2u) + { + regTmp = CY_SYS_CPUSS_SL_CTL2_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL2_REG = regTmp; + } else + #endif /* (CY_IP_SL_NR >= 1) */ + { + /* Halt CPU in debug mode if interface is invalid */ + CYASSERT(0u != 0u); + } + } + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +#if (CY_IP_PASS) + /******************************************************************************* + * Function Name: CySysPrbSetGlobalVrefSource + ****************************************************************************//** + * + * Selects the source of the global voltage reference. + * + * \note The global voltage reference uses one of the available programmable + * voltage reference lines. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * This API affects the voltage values available in + * \ref CySysPrbSetGlobalVrefVoltage(). + * + * This API is applicable for PSoC 4200M, PSoC 4200L and PSoC Analog + * Coprocessor devices only. + * + * \param source: + * CY_SYS_VREF_SOURCE_BG Sets bandgap as the source of the global voltage + * reference. + * CY_SYS_VREF_SOURCE_VDDA Sets VDDA as the source of the global voltage + * reference. + * + *******************************************************************************/ + #ifdef CyDesignWideVoltageReference_PRB_REF + void CySysPrbSetGlobalVrefSource(uint32 source) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_REF, CYFLD_PASS_VREF_SUP_SEL, source); + } + #endif + + /******************************************************************************* + * Function Name: CySysPrbSetBgGain + ****************************************************************************//** + * + * Selects the gain of bandgap reference buffer. Note that this API is effective + * only when the bandgap is set as the source of global voltage reference. + * + * \note This API affects the voltage values available in \ref + * CySysPrbSetGlobalVrefVoltage() API. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * \param gain: + * CY_SYS_VREF_BG_GAINx1 Gain is 1. + * CY_SYS_VREF_BG_GAINx2 Gain is 2. + * + *******************************************************************************/ + void CySysPrbSetBgGain(uint32 gain) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VBGR_BUF_GAIN, gain); + } + + + /******************************************************************************* + * Function Name: CySysPrbSetGlobalVrefVoltage + ****************************************************************************//** + * + * Selects the value of global voltage reference. Set the source of the global + * voltage reference and bandgap buffer gain (if applicable) before calling this + * API. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * \param voltageTap The range is from 1 to 16 that corresponds to: + * Source is bandgap (x1): 0.08 V to 1.20 V in steps of 0.07 V approximately. + * Source is bandgap (x2): 0.16 V to 2.40 V in steps of 0.14 V approximately. + * Source is Vdda: 0.21 V to 3.30 in steps of 0.21 V approximately. The Vdda + * is equal to 3.3 V. Voltage value will change according to value of Vdda. + * + * voltageTap | If bandgap (x1), V| If bandgap (x2), V| If Vdda + * ------------|-------------------|-------------------|------------------- + * 1 | 0.08 | 0.16 | 0.21 + * 2 | 0.15 | 0.30 | 0.41 + * 3 | 0.23 | 0.46 | 0.62 + * 4 | 0.30 | 0.60 | 0.83 + * 5 | 0.38 | 0.76 | 1.03 + * 6 | 0.45 | 0.90 | 1.24 + * 7 | 0.53 | 1.06 | 1.44 + * 8 | 0.60 | 1.20 | 1.65 + * 9 | 0.68 | 1.36 | 1.86 + * 10 | 0.75 | 1.50 | 2.06 + * 11 | 0.83 | 1.66 | 2.27 + * 12 | 0.90 | 1.80 | 2.48 + * 13 | 0.98 | 1.96 | 2.68 + * 14 | 1.05 | 2.10 | 2.89 + * 15 | 1.13 | 2.26 | 3.09 + * 16 | 1.20 | 2.40 | 3.30 + * + *******************************************************************************/ + #ifdef CyDesignWideVoltageReference_PRB_REF + void CySysPrbSetGlobalVrefVoltage(uint32 voltageTap) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_REF, CYFLD_PASS_VREF_SEL, voltageTap); + } + #endif + + + /******************************************************************************* + * Function Name: CySysPrbEnableDeepsleepVddaRef + ****************************************************************************//** + * + * Enables the Vdda reference in deep sleep mode. The Vdda reference is by + * default disabled when entering deep sleep mode. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbEnableDeepsleepVddaRef(void) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_DEEPSLEEP_ON, 1u); + } + + + /******************************************************************************* + * Function Name: CySysPrbDisableDeepsleepVddaRef + ****************************************************************************//** + * + * Disables the Vdda reference in deep sleep mode. The Vdda reference is by + * default disabled when entering deep sleep mode. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbDisableDeepsleepVddaRef(void) + { + CY_CLEAR_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_DEEPSLEEP_ON); + } + + + /******************************************************************************* + * Function Name: CySysPrbEnableVddaRef + ****************************************************************************//** + * + * Enables the Vdda reference. The Vdda reference is by default not enabled. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbEnableVddaRef(void) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VDDA_ENABLE, 1u); + } + + + /******************************************************************************* + * Function Name: CySysPrbDisableVddaRef + ****************************************************************************//** + * + * Disables the Vdda reference. The Vdda reference is by default not enabled. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbDisableVddaRef(void) + { + CY_CLEAR_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VDDA_ENABLE); + } + + + /******************************************************************************* + * Function Name: CySysPrbSetBgBufferTrim + ****************************************************************************//** + * + * Sets the trim for the bandgap reference buffer. + * + * \note Affects all bandgap sourced references. + * + * \param bgTrim The trim value from -32 to 31. Step size is approximately 1 mV. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbSetBgBufferTrim(int32 bgTrim) + { + uint8 tmp = 0u; + + if (bgTrim >= 0) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM, (uint32) bgTrim); + } + else + { + tmp = (uint8)((int32) bgTrim * (int8) (-1)); /* Make positive */ + tmp = (uint8) ~tmp + 1u; /* Two's complement */ + tmp |= (uint8) CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT; + + CY_SET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM, tmp); + } + } + + + /******************************************************************************* + * Function Name: CySysPrbGetBgBufferTrim + ****************************************************************************//** + * + * Returns the current trim of the bandgap reference buffer. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + int32 CySysPrbGetBgBufferTrim(void) + { + uint8 tmp; + int32 returnValue; + + tmp = (uint8) CY_GET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM); + if ((tmp & CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT) != 0u) + { + tmp = ((uint8) ~tmp) + 1u; /* Make positive */ + returnValue = (int32) tmp * (-1); /* Make negative */ + } + else + { + returnValue = (int32) tmp; + } + + return (returnValue); + } + + +#endif /* (CY_IP_PASS) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLib.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLib.h new file mode 100644 index 0000000..c818cc1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/CyLib.h @@ -0,0 +1,1576 @@ +/***************************************************************************//** +* \file CyLib.h +* \version 5.70 +* +* \brief Provides a system API for the clocking, and interrupts. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include "cytypes.h" +#include "cydevice_trm.h" +#include "CyLFClk.h" + +#include +#include +#include + + +/** +* \addtogroup group_clocking + +PSoC devices supported by PSoC Creator have flexible clocking capabilities. These clocking capabilities are +controlled in PSoC Creator by selections within the Design-Wide Resources settings, connectivity of clocking signals on +the design schematic, and API calls that can modify the clocking at runtime. The clocking API is provided in the CyLib.c +and CyLib.h files. + +This section describes how PSoC Creator maps clocks onto the device and provides guidance on clocking methodologies that +are optimized for the PSoC architecture. + + +\section section_clocking_modes Power Modes +The IMO is available in Active and Sleep modes. It is automatically disabled/enabled for the proper Deep Sleep and +Hibernate mode entry/exit. The IMO is disabled during Deep Sleep and Hibernate modes. + +The EXTCLK is available in Active and Sleep modes. The system will enter/exit Deep Sleep and Hibernate using external +clock. The device will re-enable the IMO if it was enabled before entering Deep Sleep or Hibernate, but it does not wait +for the IMO before starting the CPU. After entering Active mode, the IMO may take an additional 2 us to begin toggling. +The IMO will startup cleanly without glitches, but any dependency should account for this extra startup time. If +desired, firmware may increase wakeup hold-off using \ref CySysPmSetWakeupHoldoff() function to include this 2 us and +ensure the IMO is toggling by the time Active mode is reached. + +The ILO is available in all modes except Hibernate and Stop. + + + +\section section_clocking_connectivity Clock Connectivity +The PSoC architecture includes flexible clock generation logic. Refer to the Technical Reference Manual for a detailed +description of all the clocking sources available in a particular device. The usage of these various clocking sources +can be categorized by how those clocks are connected to elements of a design. + +\section section_clocking_runtime_changing Changing Clocks in Run-time + +\subsection section_clocking_runtime_changing_impact Impact on Components Operation +The components with internal clocks are directly impacted by the change of the system clock frequencies or sources. The +components clock frequencies obtained using design-time dividers. The run-time change of components clock source will +correspondingly change the internal component clock. Refer to the component datasheet for the details. + +\subsection section_clocking_runtime_adjust CyDelay APIs +The CyDelay APIs implement simple software-based delay loops. The loops compensate for system clock frequency. The +\ref CyDelayFreq() function must be called in order to adjust \ref CyDelay(), \ref CyDelayUs() and \ref CyDelayCycles() +functions to the new system clock value. + +\subsection section_clocking_runtime_cache Cache Configuration +If the CPU clock frequency increases during device operation, the number of clock cycles cache will wait before sampling +data coming back from Flash should be adjusted. If the CPU clock frequency decreases, the number of clock cycles can be +also adjusted to improve CPU performance. See “CySysFlashSetWaitCycles()” for PSoC 4 for more information. + +*/ + + +/** +* \addtogroup group_clocking_hfclk High-Frequency Clocking API +* \ingroup group_clocking +* @{ +*/ +void CySysClkImoStart(void); +void CySysClkImoStop(void); +void CySysClkWriteHfclkDirect(uint32 clkSelect); + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + void CySysClkImoEnableWcoLock(void); + void CySysClkImoDisableWcoLock(void); + uint32 CySysClkImoGetWcoLock(void); +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_USB) + void CySysClkImoEnableUsbLock(void); + void CySysClkImoDisableUsbLock(void); + uint32 CySysClkImoGetUsbLock(void); +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#if (CY_IP_SRSSLT) + void CySysClkWriteHfclkDiv(uint32 divider); +#endif /* (CY_IP_SRSSLT) */ + +void CySysClkWriteSysclkDiv(uint32 divider); +void CySysClkWriteImoFreq(uint32 freq); +uint32 CySysClkGetSysclkSource(void); +void CySysEnablePumpClock(uint32 enable); + +/** @} group_clocking_hfclk */ + + +/** +* \addtogroup group_clocking_lfclk Low-Frequency Clocking API +* \ingroup group_clocking +* \detailed For PSoC 4 devices, the CyLFClk (low-frequency clock) APIs are located in separate files +* (CyLFClk.h/CyLFClk.c). See the CyLFClk Component Datasheet available from the System Reference Guides item of the +* PSoC Creator Help menu. +* @{ +*/ +/** @} group_clocking_lfclk */ + + +/** +* \addtogroup group_clocking_eco External Crystal Oscillator (ECO) API +* \ingroup group_clocking +* @{ +*/ +#if (CY_IP_ECO) + cystatus CySysClkEcoStart(uint32 timeoutUs); + void CySysClkEcoStop(void); + uint32 CySysClkEcoReadStatus(void); + + #if (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) + void CySysClkWriteEcoDiv(uint32 divider); + #endif /* (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) */ + + #if (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) + void CySysClkConfigureEcoTrim(uint32 wDTrim, uint32 aTrim, uint32 fTrim, uint32 rTrim, uint32 gTrim); + cystatus CySysClkConfigureEcoDrive(uint32 freq, uint32 cLoad, uint32 esr, uint32 maxAmplitude); + #endif /* (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) */ +#endif /* (CY_IP_ECO) */ +/** @} group_clocking_eco */ + + +/** +* \addtogroup group_clocking_pll Phase-Locked Loop (PLL) API +* \ingroup group_clocking +* @{ +*/ +#if (CY_IP_PLL) + cystatus CySysClkPllStart(uint32 pll, uint32 wait); + void CySysClkPllStop(uint32 pll); + cystatus CySysClkPllSetPQ(uint32 pll, uint32 feedback, uint32 reference, uint32 current); + cystatus CySysClkPllSetFrequency(uint32 pll, uint32 inputFreq, uint32 pllFreq, uint32 divider, uint32 freqTol); + void CySysClkPllSetSource(uint32 pll, uint32 source); + cystatus CySysClkPllSetOutputDivider(uint32 pll, uint32 divider); + void CySysClkPllSetBypassMode(uint32 pll, uint32 bypass); + uint32 CySysClkPllGetUnlockStatus(uint32 pll); + uint32 CySysClkPllGetLockStatus(uint32 pll); +#endif /* (CY_IP_PLL) */ +/** @} group_clocking_pll */ + + +/** +* \addtogroup group_api_lvd_functions Low Voltage Detection API +* @{ +*/ +#if(CY_IP_SRSSV2) + void CySysLvdEnable(uint32 threshold); + void CySysLvdDisable(void); + uint32 CySysLvdGetInterruptSource(void); + void CySysLvdClearInterrupt(void); +#endif /* (CY_IP_SRSSV2) */ +/** @} group_api_lvd_functions */ + + +/** +* \addtogroup group_interrupts Interrupt API +* \brief The APIs in this chapter apply to all architectures except as noted. The Interrupts API is provided in the +* CyLib.c and CyLib.h files. Refer also to the Interrupt component datasheet for more information about interrupts. +* @{ +*/ +cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address); +cyisraddress CyIntGetSysVector(uint8 number); + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address); +cyisraddress CyIntGetVector(uint8 number); + +void CyIntSetPriority(uint8 number, uint8 priority); +uint8 CyIntGetPriority(uint8 number); + +void CyIntEnable(uint8 number); +uint8 CyIntGetState(uint8 number); +void CyIntDisable(uint8 number); + +void CyIntSetPending(uint8 number); +void CyIntClearPending(uint8 number); + +uint32 CyDisableInts(void); +void CyEnableInts(uint32 mask); +/** @} group_interrupts */ + + +/** +* \addtogroup group_api_delay_functions Delay API +* @{ +*/ +/* Do not use these definitions directly in your application */ +extern uint32 cydelayFreqHz; +extern uint32 cydelayFreqKhz; +extern uint8 cydelayFreqMhz; +extern uint32 cydelay32kMs; + +void CyDelay(uint32 milliseconds); +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq); +void CyDelayCycles(uint32 cycles); +/** @} group_api_delay_functions */ + + +/** +* \addtogroup group_api_system_functions System API +* @{ +*/ +void CySoftwareReset(void); +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason); +uint32 CySysGetResetReason(uint32 reason); +void CyGetUniqueId(uint32* uniqueId); + +/* Default interrupt handler */ +CY_ISR_PROTO(IntDefaultHandler); +/** @} group_api_system_functions */ + + +/** +* \addtogroup group_api_systick_functions System Timer (SysTick) API +* @{ +*/ + +typedef void (*cySysTickCallback)(void); + +void CySysTickStart(void); +void CySysTickInit(void); +void CySysTickEnable(void); +void CySysTickStop(void); +void CySysTickEnableInterrupt(void); +void CySysTickDisableInterrupt(void); +void CySysTickSetReload(uint32 value); +uint32 CySysTickGetReload(void); +uint32 CySysTickGetValue(void); +cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function); +cySysTickCallback CySysTickGetCallback(uint32 number); + +#if(CY_SYSTICK_LFCLK_SOURCE) + void CySysTickSetClockSource(uint32 clockSource); + uint32 CySysTickGetClockSource(void); +#endif /* (CY_SYSTICK_LFCLK_SOURCE) */ + +uint32 CySysTickGetCountFlag(void); +void CySysTickClear(void); +extern uint32 CySysTickInitVar; +/** @} group_api_systick_functions */ + + +#if (CY_IP_DMAC_PRESENT) + void CySysSetRamAccessArbPriority(uint32 source); + void CySysSetFlashAccessArbPriority(uint32 source); + void CySysSetDmacAccessArbPriority(uint32 source); + void CySysSetPeripheralAccessArbPriority(uint32 interfaceNumber, uint32 source); +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/** +* \addtogroup group_api_pvb_functions Programmable Voltage Block (PVB) API +* @{ +*/ +#if (CY_IP_PASS) + void CySysPrbSetGlobalVrefSource(uint32 source); + void CySysPrbSetBgGain(uint32 gain); + void CySysPrbSetGlobalVrefVoltage(uint32 voltageTap); + void CySysPrbEnableDeepsleepVddaRef(void); + void CySysPrbDisableDeepsleepVddaRef(void); + void CySysPrbEnableVddaRef(void); + void CySysPrbDisableVddaRef(void); + void CySysPrbSetBgBufferTrim(int32 bgTrim); + int32 CySysPrbGetBgBufferTrim(void); +#endif /* (CY_IP_PASS) */ +/** @} group_api_pvb_functions */ + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* Clock API Constants +*******************************************************************************/ + +/* CySysClkWriteHfclkDirect() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x07u) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (( uint32 ) 0x07u) + + #define CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT (( uint32 ) 16u) + + #if (CY_IP_PLL) + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 3u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT) + #else + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 0u ) + #endif /* (CY_IP_PLL) */ + +#else + #if (CY_IP_PLL && CY_IP_SRSSLT) + #define CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK (( uint32 ) 0x01u ) + #define CY_SYS_CLK_SELECT_HFCLK_SEL_PLL_MASK (( uint32 ) 0x04u ) + #define CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT (( uint32 ) 2u) + + #define CY_SYS_EXCO_PGM_CLK_ENABLE_MASK (( uint32 ) 0x80000000u) + #define CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK (( uint32 ) 0x2u) + #define CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR (( uint8 ) 0x5u) + #endif /* (CY_IP_PLL && CY_IP_SRSSLT) */ + + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 0u ) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x03u) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkWriteHfclkDirect() - parameter definitions */ +#define CY_SYS_CLK_HFCLK_IMO (0u) +#define CY_SYS_CLK_HFCLK_EXTCLK (1u) +#if (CY_IP_ECO) + #define CY_SYS_CLK_HFCLK_ECO (2u) +#endif /* (CY_IP_ECO) */ + +#if (CY_IP_PLL) + #if (CY_IP_SRSSV2) + #define CY_SYS_CLK_HFCLK_PLL0 ((uint32) ((uint32) 2u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT)) + #define CY_SYS_CLK_HFCLK_PLL1 ((uint32) ((uint32) 1u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT)) + #else + #define CY_SYS_CLK_HFCLK_PLL0 (6u) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkWriteSysclkDiv() - parameter definitions */ +#define CY_SYS_CLK_SYSCLK_DIV1 (0u) +#define CY_SYS_CLK_SYSCLK_DIV2 (1u) +#define CY_SYS_CLK_SYSCLK_DIV4 (2u) +#define CY_SYS_CLK_SYSCLK_DIV8 (3u) +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SYSCLK_DIV16 (4u) + #define CY_SYS_CLK_SYSCLK_DIV32 (5u) + #define CY_SYS_CLK_SYSCLK_DIV64 (6u) + #define CY_SYS_CLK_SYSCLK_DIV128 (7u) +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkWriteSysclkDiv() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (19u) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x07u) +#else + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (6u) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x03u) +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkPllSetSource() - implementation definitions */ +#if (CY_IP_PLL) + #if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_PLL_SHIFT(x) (3u + (3u * (x))) + #define CY_SYS_CLK_SELECT_PLL_MASK(x) ((uint32) ((uint32) 0x07u << CY_SYS_CLK_SELECT_PLL_SHIFT((x)))) + #else + #define CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT (1u) + #define CY_SYS_ECO_CLK_SELECT_PLL0_MASK ((uint32) ((uint32) 0x01u << CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT)) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkPllSetSource() - parameter definitions */ +#if (CY_IP_PLL) + #if(CY_IP_SRSSV2) + #define CY_SYS_PLL_SOURCE_IMO (0u) + #define CY_SYS_PLL_SOURCE_EXTCLK (1u) + #define CY_SYS_PLL_SOURCE_ECO (2u) + #define CY_SYS_PLL_SOURCE_DSI0 (4u) + #define CY_SYS_PLL_SOURCE_DSI1 (5u) + #define CY_SYS_PLL_SOURCE_DSI2 (6u) + #define CY_SYS_PLL_SOURCE_DSI3 (7u) + #else + #define CY_SYS_PLL_SOURCE_ECO (0u) + #define CY_SYS_PLL_SOURCE_IMO (1u) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkPllSetBypassMode() - parameter definitions */ +#if(CY_IP_SRSSV2 || CY_IP_SRSSLT) + #if (CY_IP_PLL) + #define CY_SYS_PLL_BYPASS_AUTO (0u) + #define CY_SYS_PLL_BYPASS_PLL_REF (2u) + #define CY_SYS_PLL_BYPASS_PLL_OUT (3u) + #endif /* (CY_IP_PLL) */ +#endif /* (CY_IP_SRSSV2 || CY_IP_SRSSLT)) */ + +/* CySysClkPllSetOutputDivider()/CySysClkPllSetFrequency() - parameters */ +#if(CY_IP_SRSSV2 || CY_IP_SRSSLT) + #if (CY_IP_PLL) + #define CY_SYS_PLL_OUTPUT_DIVPASS (0u) + #define CY_SYS_PLL_OUTPUT_DIV2 (1u) + #define CY_SYS_PLL_OUTPUT_DIV4 (2u) + #define CY_SYS_PLL_OUTPUT_DIV8 (3u) + #endif /* (CY_IP_PLL) */ +#endif /* (CY_IP_SRSSV2 || CY_IP_SRSSLT) */ + +/* CySysPumpClock() */ +#define CY_SYS_CLK_PUMP_DISABLE ((uint32) 0u) +#define CY_SYS_CLK_PUMP_ENABLE ((uint32) 1u) + +#if (CY_IP_PLL) + + /* Set of the PLL registers */ + typedef struct + { + uint32 config; + uint32 status; + uint32 test; + } cy_sys_clk_pll_regs_struct; + + /* Array of the PLL registers */ + typedef struct + { + cy_sys_clk_pll_regs_struct pll[2u]; + } cy_sys_clk_pll_struct; + + + /* CySysClkPllSetPQ() - implementation definitions */ + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT (0u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT (8u) + #define CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT (14u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT (16u) + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT (20u) + + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK ((uint32) ((uint32) 0xFFu << CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK ((uint32) ((uint32) 0x3Fu << CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK ((uint32) ((uint32) 0x03u << CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK ((uint32) ((uint32) 0x07u << CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK ((uint32) ((uint32) 0x03u << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT)) + + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_PLL_REF ((uint32) ((uint32) 2u << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT)) + + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MIN (4u) + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MAX (259u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MIN (2u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MAX (3u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MIN (1u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MAX (64u) + + /* CySysClkPllGetUnlockStatus() - implementation definitions */ + #define CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_SHIFT (4u) + #define CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK (( uint32 )(( uint32 )0x01u << CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_SHIFT)) + + /* CySysClkPllSetFrequency() - implementation definitions */ + #define CY_SYS_CLK_PLL_QMINIP (1u) + #define CY_SYS_CLK_PLL_FPFDMAX (3000u) + + #define CY_SYS_CLK_PLL_QMAXIP (64u) + #define CY_SYS_CLK_PLL_FPFDMIN (1000u) + + #define CY_SYS_CLK_PLL_INVALID (0u) + #define CY_SYS_CLK_PLL_CURRENT_DEFAULT (2u) + + #define CY_SYS_CLK_PLL_INPUT_FREQ_MIN (1000u) + #define CY_SYS_CLK_PLL_INPUT_FREQ_MAX (49152u) + + #define CY_SYS_CLK_PLL_OUTPUT_FREQ_MIN (22500u) + #define CY_SYS_CLK_PLL_OUTPUT_FREQ_MAX (49152u) + + /* CySysClkPllStart() / CySysClkPllStop() - implementation definitions */ + #define CY_SYS_CLK_PLL_STATUS_LOCKED (1u) + #define CY_SYS_CLK_PLL_MIN_STARTUP_US (5u) + #define CY_SYS_CLK_PLL_MAX_STARTUP_US (255u) + + #define CY_SYS_CLK_PLL_CONFIG_ENABLE ((uint32) ((uint32) 1u << 31u)) + #define CY_SYS_CLK_PLL_CONFIG_ISOLATE ((uint32) ((uint32) 1u << 30u)) + +#endif /* (CY_IP_PLL) */ + +/* CySysClkWriteImoFreq() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u) + #define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (3u) + + #define CY_SYS_CLK_IMO_TEMP_FREQ_MHZ (24u) + #define CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2 (0x19u) /* Corresponds to 24 MHz */ + + #define CY_SYS_CLK_IMO_BOUNDARY_FREQ_MHZ (43u) + #define CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2 (0x30u) /* Corresponds to 43 MHz */ + + #define CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES (5u) + #define CY_SYS_CLK_IMO_TRIM_TIMEOUT_US (5u) + #define CY_SYS_CLK_IMO_FREQ_TABLE_SIZE (46u) + #define CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET (3u) + #define CY_SYS_CLK_IMO_FREQ_BITS_MASK (( uint32 )0x3Fu) + #define CY_SYS_CLK_IMO_FREQ_CLEAR (( uint32 )(CY_SYS_CLK_IMO_FREQ_BITS_MASK << 8u)) + #define CY_SYS_CLK_IMO_TRIM4_GAIN_MASK (( uint32 )0x1Fu) + #define CY_SYS_CLK_IMO_TRIM4_WCO_GAIN (( uint32 ) 12u) + #define CY_SYS_CLK_IMO_TRIM4_USB_GAIN (( uint32 ) 8u) + + #if(CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK (( uint32 )0x02u) + #define CY_SFLASH_S1_TESTPGM_REV_MASK (( uint32 )0x3Fu) + #define CY_SFLASH_S1_TESTPGM_OLD_REV (( uint32 )4u) + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#else + #define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (24u) + #define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u) + #define CY_SYS_CLK_IMO_STEP_SIZE_MASK (0x03u) + #define CY_SYS_CLK_IMO_TRIM1_OFFSET_MASK (( uint32 )(0xFFu)) + #define CY_SYS_CLK_IMO_TRIM2_FSOFFSET_MASK (( uint32 )(0x07u)) + #define CY_SYS_CLK_IMO_TRIM3_VALUES_MASK (( uint32 )(0x7Fu)) + #define CY_SYS_CLK_IMO_SELECT_FREQ_MASK (( uint32 )(0x07u)) + #define CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT (( uint32 )(0x02u)) + #define CY_SYS_CLK_IMO_SELECT_24MHZ (( uint32 )(0x00u)) + + #define CY_SYS_CLK_IMO_TRIM_DELAY_US (( uint32 )(50u)) + #define CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES (( uint32 )(50u)) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkImoEnableUsbLock(void) - - implementation definitions */ +#if(CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK (( uint32 )0x02u) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK (( uint32 )0x01u) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_USB (( uint32 )0x00u) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_WCO (( uint32 )0x01u) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +#if(CY_IP_SRSSV2) + /* Conversion between CySysClkWriteImoFreq() parameter and register's value */ + extern const uint8 cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_FREQ_TABLE_SIZE]; +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkImoStart()/CySysClkImoStop() - implementation definitions */ +#define CY_SYS_CLK_IMO_CONFIG_ENABLE (( uint32 )(( uint32 )0x01u << 31u)) + + +#if(CY_IP_SRSSLT) + /* CySysClkWriteHfclkDiv() - parameter definitions */ + #define CY_SYS_CLK_HFCLK_DIV_NODIV (0u) + #define CY_SYS_CLK_HFCLK_DIV_2 (1u) + #define CY_SYS_CLK_HFCLK_DIV_4 (2u) + #define CY_SYS_CLK_HFCLK_DIV_8 (3u) + + /* CySysClkWriteHfclkDiv() - implementation definitions */ + #define CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT (2u) + #define CY_SYS_CLK_SELECT_HFCLK_DIV_MASK (( uint32 )0x03u) +#endif /* (CY_IP_SRSSLT) */ + + +/* Operating source for Pump clock */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT (25u) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK ((uint32) 0x07u) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_IMO (1u) + + #define CY_SYS_CLK_IMO_CONFIG_PUMP_OSC (( uint32 )(( uint32 )0x01u << 22u)) +#else /* CY_IP_SRSSLT */ + #define CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT (4u) + #define CY_SYS_CLK_SELECT_PUMP_SEL_MASK ((uint32) 0x03u) + #define CY_SYS_CLK_SELECT_PUMP_SEL_IMO (1u) +#endif /* (CY_IP_SRSSLT) */ + + +#if (CY_IP_ECO_BLESS) + /* Radio configuration register */ + #define CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE (( uint32 )0x01u) + + /* RFCTRL mode transition control */ + #define CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE (( uint32 )(( uint32 )0x01u << 15u)) + + /* XO is oscillating status */ + #define CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT (( uint32 )0x01u) + + /* BB bump configuration 2 */ + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_MASK (( uint32 )(( uint32 )0x7Fu << 8u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_MASK (( uint32 )(( uint32 )0x7Fu << 0u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_ADD_CAP (( uint32 )(( uint32 )0x01u << 15u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_ADD_CAP (( uint32 )(( uint32 )0x01u << 7u)) + + /* BB bump configuration 1 */ + #define CY_SYS_XTAL_BLERD_BB_XO_TRIM ((uint32) 0x2002u) + + + /** + * \addtogroup group_api_eco + * @{ + */ + #define CY_SYS_CLK_ECO_DIV1 ((uint32) 0x00) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_DIV2 ((uint32) 0x01) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 2 */ + #define CY_SYS_CLK_ECO_DIV4 ((uint32) 0x02) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 4 */ + #define CY_SYS_CLK_ECO_DIV8 ((uint32) 0x03) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 8 */ + /** @} group_api_eco */ + + /* CySysClkWriteEcoDiv() - implementation definitions */ + #define CY_SYS_CLK_XTAL_CLK_DIV_MASK ((uint32) 0x03) +#endif /* (CY_IP_ECO_BLESS) */ + +#if (CY_IP_ECO_BLESSV3) + #define CY_SYS_CLK_ECO_DIV1 ((uint32) 0x00) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_DIV2 ((uint32) 0x01) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 2 */ + #define CY_SYS_CLK_ECO_DIV4 ((uint32) 0x02) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 4 */ + #define CY_SYS_CLK_ECO_DIV8 ((uint32) 0x03) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 8 */ + /** @} group_api_eco */ + + #define CY_SYS_BLESS_HVLDO_STARTUP_DELAY ((uint32) 2u) + #define CY_SYS_BLESS_ISOLATE_DEASSERT_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_ACT_TO_SWITCH_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_HVLDO_DISABLE_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_OSC_STARTUP_DELAY_LF ((uint32) 80u) + #define CY_SYS_BLESS_DSM_OFFSET_TO_WAKEUP_INST_LF ((uint32) 4u) + #define CY_SYS_BLESS_ACT_STARTUP_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_DIG_LDO_STARTUP_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_XTAL_DISABLE_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_DIG_LDO_DISABLE_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_MT_CFG_ACT_LDO ((uint32) 1u) + #define CY_SYS_BLESS_MT_CFG_ENABLE_BLERD ((uint32) 1u) + #define CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON ((uint32) 1u) + + #define CY_SYS_BLESS_MT_STATUS_BLERD_IDLE ((uint32) 4u) + #define CY_SYS_BLESS_MT_STATUS_SWITCH_EN ((uint32) 5u) + #define CY_SYS_BLESS_MT_STATUS_ACTIVE ((uint32) 6u) + #define CY_SYS_BLESS_MT_STATUS_ISOLATE ((uint32) 7u) + + #define CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK ((uint32) 0x20u) + #define CY_SYS_BLESS_BLERD_ACTIVE_INTR_STAT ((uint32) 0x8u) + + #define CY_SYS_BLESS_MT_STATUS_CURR_STATE_MASK ((uint32) 0x1Eu) + + #define CY_SYS_RCB_CTRL_ENABLED ((uint32) 1u) + #define CY_SYS_RCB_CTRL_DIV_ENABLED ((uint32) 1u) + #define CY_SYS_RCB_CTRL_DIV ((uint32) 2u) + #define CY_SYS_RCB_CTRL_LEAD ((uint32) 3u) + #define CY_SYS_RCB_CTRL_LAG ((uint32) 3u) + + #define CY_SYS_RCB_INTR_RCB_DONE ((uint32) 1u) + #define CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY ((uint32) ((uint32)0x1u << 17u)) + #define CY_SYS_RCB_INTR_CLEAR ((uint32) 0xFFFFFFFFu) + #define CY_SYS_RCB_RBUS_RD_CMD ((uint32) ((uint32)0x1u << 31u)) + #define CY_SYS_RCB_RBUS_DIG_CLK_SET ((uint32) 0x1e030400u) + #define CY_SYS_RCB_RBUS_FREQ_NRST_SET ((uint32) 0x1e021800u) + #define CY_SYS_RCB_RBUS_FREQ_XTAL_DIV_SET ((uint32) 0x1e090040u) + #define CY_SYS_RCB_RBUS_FREQ_XTAL_NODIV_SET ((uint32) 0x1e090000u) + #define CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET ((uint32) 0x1e080000u) + #define CY_SYS_RCB_RBUS_IB_VAL ((uint32) ((uint32)0x1u << 9u)) + #define CY_SYS_RCB_RBUS_IB_MASK ((uint32) ((uint32)0x3u << 9u)) + #define CY_SYS_RCB_RBUS_TRIM_VAL ((uint32) (CYDEV_RCB_RBUS_RF_DCXO_CAP_TRIM << 1u)) + #define CY_SYS_RCB_RBUS_TRIM_MASK ((uint32) ((uint32)0xFFu << 1u)) + #define CY_SYS_RCB_RBUS_VAL_MASK ((uint32) 0xFFFFu) + + #define CY_SYS_RCBLL_CPU_ACCESS ((uint32) 0u) + #define CY_SYS_RCBLL_BLELL_ACCESS ((uint32) 1u) + + #define CY_SYS_BLELL_CMD_ENTER_DSM ((uint32) 0x50u) + + #define CY_SYS_BLESS_MT_DELAY_CFG_INIT \ + ((CY_SYS_BLESS_HVLDO_STARTUP_DELAY << CYFLD_BLE_BLESS_HVLDO_STARTUP_DELAY__OFFSET) | \ + (CY_SYS_BLESS_ISOLATE_DEASSERT_DELAY << CYFLD_BLE_BLESS_ISOLATE_DEASSERT_DELAY__OFFSET) | \ + (CY_SYS_BLESS_ACT_TO_SWITCH_DELAY << CYFLD_BLE_BLESS_ACT_TO_SWITCH_DELAY__OFFSET) | \ + (CY_SYS_BLESS_HVLDO_DISABLE_DELAY << CYFLD_BLE_BLESS_HVLDO_DISABLE_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_DELAY_CFG2_INIT \ + ((CY_SYS_BLESS_OSC_STARTUP_DELAY_LF << CYFLD_BLE_BLESS_OSC_STARTUP_DELAY_LF__OFFSET) | \ + (CY_SYS_BLESS_DSM_OFFSET_TO_WAKEUP_INST_LF << CYFLD_BLE_BLESS_DSM_OFFSET_TO_WAKEUP_INSTANT_LF__OFFSET) | \ + (CY_SYS_BLESS_ACT_STARTUP_DELAY << CYFLD_BLE_BLESS_ACT_STARTUP_DELAY__OFFSET) | \ + (CY_SYS_BLESS_DIG_LDO_STARTUP_DELAY << CYFLD_BLE_BLESS_DIG_LDO_STARTUP_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_DELAY_CFG3_INIT \ + ((CY_SYS_BLESS_XTAL_DISABLE_DELAY << CYFLD_BLE_BLESS_XTAL_DISABLE_DELAY__OFFSET) | \ + (CY_SYS_BLESS_DIG_LDO_DISABLE_DELAY << CYFLD_BLE_BLESS_DIG_LDO_DISABLE_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_CFG_CLEAR \ + ~(CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_ENABLE_BLERD) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_DPSLP_ECO_ON) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_ACT_LDO_NOT_BUCK)) + + #define CY_SYS_BLESS_MT_CFG_INIT \ + ((CY_SYS_BLESS_MT_CFG_ENABLE_BLERD << CYFLD_BLE_BLESS_ENABLE_BLERD__OFFSET) | \ + (CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET) | \ + (CY_SYS_BLESS_MT_CFG_ACT_LDO << CYFLD_BLE_BLESS_ACT_LDO_NOT_BUCK__OFFSET)) + + #define CY_SYS_RCB_CTRL_CLEAR \ + ~(CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_ENABLED) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_DIV_ENABLED) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_DIV) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_LEAD) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_LAG)) + + #define CY_SYS_RCB_CTRL_INIT \ + ((CY_SYS_RCB_CTRL_ENABLED << CYFLD_BLE_RCB_ENABLED__OFFSET) | \ + (CY_SYS_RCB_CTRL_DIV_ENABLED << CYFLD_BLE_RCB_DIV_ENABLED__OFFSET) | \ + (CY_SYS_RCB_CTRL_DIV << CYFLD_BLE_RCB_DIV__OFFSET) | \ + (CY_SYS_RCB_CTRL_LEAD << CYFLD_BLE_RCB_LEAD__OFFSET) | \ + (CY_SYS_RCB_CTRL_LAG << CYFLD_BLE_RCB_LAG__OFFSET)) + + /* CySysClkWriteEcoDiv() - implementation definitions */ + #define CY_SYS_CLK_XTAL_CLK_DIV_MASK ((uint32) 0x03) + + #define CY_SYS_BLE_CLK_ECO_FREQ_32MHZ (32) + +#endif /* (CY_IP_ECO_BLESSV3) */ + + +/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() constants */ +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* Fimo = DPLL_MULT * Fwco */ + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE (( uint32 )(( uint32 )0x01u << 30u)) + + /* Rounding integer division: DPLL_MULT = (Fimo_in_khz + Fwco_in_khz / 2) / Fwco_in_khz */ + #define CY_SYS_CLK_WCO_DPLL_MULT_VALUE(frequencyMhz) ((uint32) (((((frequencyMhz) * 1000000u) + 16384u) / 32768u) - 1u)) + #define CY_SYS_CLK_WCO_DPLL_MULT_MASK ((uint32) 0x7FFu) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT (16u) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT (19u) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT (22u) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK (( uint32 )(( uint32 )0xFFu << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT)) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN (( uint32 )(( uint32 ) 4u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN (( uint32 )(( uint32 ) 2u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT)) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX ((uint32) 0xFFu) + #define CY_SYS_CLK_WCO_IMO_TIMEOUT_MS ((uint32) 20u) + + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT (26u) + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE (23u) + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET (26u) + +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +/******************************************************************************* +* System API Constants +*******************************************************************************/ + +/* CySysGetResetReason() */ +#define CY_SYS_RESET_WDT_SHIFT (0u) +#define CY_SYS_RESET_PROTFAULT_SHIFT (3u) +#define CY_SYS_RESET_SW_SHIFT (4u) + +#define CY_SYS_RESET_WDT ((uint32)1u << CY_SYS_RESET_WDT_SHIFT ) +#define CY_SYS_RESET_PROTFAULT ((uint32)1u << CY_SYS_RESET_PROTFAULT_SHIFT) +#define CY_SYS_RESET_SW ((uint32)1u << CY_SYS_RESET_SW_SHIFT ) + + +/* CySoftwareReset() - implementation definitions */ + +/* Vector Key */ +#define CY_SYS_AIRCR_VECTKEY_SHIFT (16u) +#define CY_SYS_AIRCR_VECTKEY ((uint32)((uint32)0x05FAu << CY_SYS_AIRCR_VECTKEY_SHIFT)) +#define CY_SYS_AIRCR_VECTKEY_MASK ((uint32)((uint32)0xFFFFu << CY_SYS_AIRCR_VECTKEY_SHIFT)) + +/* System Reset Request */ +#define CY_SYS_AIRCR_SYSRESETREQ_SHIFT (2u) +#define CY_SYS_AIRCR_SYSRESETREQ ((uint32)((uint32)1u << CY_SYS_AIRCR_SYSRESETREQ_SHIFT)) + + +#if defined(__ARMCC_VERSION) + + #define CyGlobalIntEnable do \ + { \ + __enable_irq(); \ + } while ( 0 ) + + #define CyGlobalIntDisable do \ + { \ + __disable_irq(); \ + } while ( 0 ) + +#elif defined(__GNUC__) || defined (__ICCARM__) + + #define CyGlobalIntEnable do \ + { \ + __asm("CPSIE i"); \ + } while ( 0 ) + + #define CyGlobalIntDisable do \ + { \ + __asm("CPSID i"); \ + } while ( 0 ) + +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + +/* System tick timer */ +#define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u)) +#define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u)) +#define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT (0x02u) +#define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT (16u) +#define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u)) +#define CY_SYS_SYST_CSR_CLK_SRC_LFCLK (0u) +#define CY_SYS_SYST_RVR_CNT_MASK (0x00FFFFFFu) +#define CY_SYS_SYST_CVR_CNT_MASK (0x00FFFFFFu) +#define CY_SYS_SYST_NUM_OF_CALLBACKS (5u) + + +/******************************************************************************* +* Macro Name: CyAssert +******************************************************************************** +* Summary: +* Macro that evaluates the expression and, if it is false (evaluates to 0), +* the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* If NDEBUG is defined, then no code is generated for this macro. +* NDEBUG is defined by default for a Release build setting and not defined for +* a Debug build setting. +* +* Parameters: +* expr: Logical expression. Asserts if false. +* +* Return: +* None +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) do \ + { \ + if(0u == (uint32)(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } while ( 0u ) +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/******************************************************************************* +* Interrupt API Constants +*******************************************************************************/ +#define CY_NUM_INTERRUPTS (CY_IP_INT_NR) + +#define CY_MIN_PRIORITY (3u) + +#define CY_INT_IRQ_BASE (16u) +#define CY_INT_CLEAR_DISABLE_ALL (0xFFFFFFFFu) +#define CY_INT_ENABLE_RANGE_MASK (0x1Fu) + +/* Register n contains priorities for interrupts N=4n .. 4n+3 */ +#define CY_INT_PRIORITY_SHIFT(number) (( uint32 )6u + (8u * (( uint32 )(number) % 4u))) + +/* Mask to get valid range of system priority 0-3 */ +#define CY_INT_PRIORITY_MASK (( uint32 ) 0x03u) + +/* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */ +#define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */ +#define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */ +#define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */ +#define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */ +#define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */ + + +#if(CY_IP_SRSSV2) + + + /******************************************************************************* + * Low Voltage Detection API Constants + *******************************************************************************/ + + /* CySysLvdEnable() - parameter definitions */ + #define CY_LVD_THRESHOLD_1_75_V (( uint32 ) 0u) + #define CY_LVD_THRESHOLD_1_80_V (( uint32 ) 1u) + #define CY_LVD_THRESHOLD_1_90_V (( uint32 ) 2u) + #define CY_LVD_THRESHOLD_2_00_V (( uint32 ) 3u) + #define CY_LVD_THRESHOLD_2_10_V (( uint32 ) 4u) + #define CY_LVD_THRESHOLD_2_20_V (( uint32 ) 5u) + #define CY_LVD_THRESHOLD_2_30_V (( uint32 ) 6u) + #define CY_LVD_THRESHOLD_2_40_V (( uint32 ) 7u) + #define CY_LVD_THRESHOLD_2_50_V (( uint32 ) 8u) + #define CY_LVD_THRESHOLD_2_60_V (( uint32 ) 9u) + #define CY_LVD_THRESHOLD_2_70_V (( uint32 ) 10u) + #define CY_LVD_THRESHOLD_2_80_V (( uint32 ) 11u) + #define CY_LVD_THRESHOLD_2_90_V (( uint32 ) 12u) + #define CY_LVD_THRESHOLD_3_00_V (( uint32 ) 13u) + #define CY_LVD_THRESHOLD_3_20_V (( uint32 ) 14u) + #define CY_LVD_THRESHOLD_4_50_V (( uint32 ) 15u) + + /* CySysLvdEnable() - implementation definitions */ + #define CY_LVD_PWR_VMON_CONFIG_LVD_EN (( uint32 ) 0x01u) + #define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT (1u) + #define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK (( uint32 ) (0x0F << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT)) + #define CY_LVD_PROPAGATE_INT_TO_CPU (( uint32 ) 0x02u) + #define CY_LVD_STABILIZE_TIMEOUT_US (1000u) + + /* CySysLvdGetInterruptSource()/ CySysLvdClearInterrupt() - parameter definitions */ + #define CY_SYS_LVD_INT (( uint32 ) 0x02u) +#endif /* (CY_IP_SRSSV2) */ + +/* CyDelay()/CyDelayFreq() - implementation definitions */ +#define CY_DELAY_MS_OVERFLOW (0x8000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (999999u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (999u) + + +/******************************************************************************* +* ECO +*******************************************************************************/ +#if (CY_IP_ECO) + #if (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) + + /* CySysClkEcoStart() - implementation definitions */ + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN_SHIFT (0u) + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_CLK_EN_SHIFT)) + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN_TIMEOUT_US (10u) + + #define CY_SYS_CLK_ECO_CONFIG_ENABLE_SHIFT (31u) + #define CY_SYS_CLK_ECO_CONFIG_ENABLE ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_ENABLE_SHIFT)) + + #define CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR_SHIFT (0u) + #define CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR_SHIFT)) + + #define CY_SYS_CLK_ECO_CONFIG_AGC_EN_SHIFT (1u) + #define CY_SYS_CLK_ECO_CONFIG_AGC_EN ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_AGC_EN_SHIFT)) + + + /** + * \addtogroup group_api_eco + * @{ + */ + #define CY_SYS_CLK_ECO_WDTRIM0 (0u) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_WDTRIM1 (1u) + #define CY_SYS_CLK_ECO_WDTRIM2 (2u) + #define CY_SYS_CLK_ECO_WDTRIM3 (3u) + + #define CY_SYS_CLK_ECO_ATRIM0 (0u) + #define CY_SYS_CLK_ECO_ATRIM1 (1u) + #define CY_SYS_CLK_ECO_ATRIM2 (2u) + #define CY_SYS_CLK_ECO_ATRIM3 (3u) + #define CY_SYS_CLK_ECO_ATRIM4 (4u) + #define CY_SYS_CLK_ECO_ATRIM5 (5u) + #define CY_SYS_CLK_ECO_ATRIM6 (6u) + #define CY_SYS_CLK_ECO_ATRIM7 (7u) + + #define CY_SYS_CLK_ECO_FTRIM0 (0u) + #define CY_SYS_CLK_ECO_FTRIM1 (1u) + #define CY_SYS_CLK_ECO_FTRIM2 (2u) + #define CY_SYS_CLK_ECO_FTRIM3 (3u) + + #define CY_SYS_CLK_ECO_RTRIM0 (0u) + #define CY_SYS_CLK_ECO_RTRIM1 (1u) + #define CY_SYS_CLK_ECO_RTRIM2 (2u) + #define CY_SYS_CLK_ECO_RTRIM3 (3u) + + #define CY_SYS_CLK_ECO_GTRIM0 (0u) + #define CY_SYS_CLK_ECO_GTRIM1 (1u) + #define CY_SYS_CLK_ECO_GTRIM2 (2u) + #define CY_SYS_CLK_ECO_GTRIM3 (3u) + /** @} group_api_eco */ + + + /* CySysClkConfigureEcoTrim() - implementation definitions */ + #define CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT (0u) + #define CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT (2u) + #define CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK ((uint32) ((uint32) 7u << CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT (0u) + #define CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT (2u) + #define CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT (4u) + #define CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT)) + + + /* CySysClkConfigureEcoDrive() - implementation definitions */ + #define CY_SYS_CLK_ECO_FREQ_KHZ_MIN (4000u) + #define CY_SYS_CLK_ECO_FREQ_KHZ_MAX (33333u) + + #define CY_SYS_CLK_ECO_MAX_AMPL_MIN_mV (500u) + #define CY_SYS_CLK_ECO_TRIM_BOUNDARY (1200u) + + /* Constant coefficient: 5u * 4u * CY_M_PI * CY_M_PI * 4 / 10 */ + #define CY_SYS_CLK_ECO_GMMIN_COEFFICIENT (79u) + + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM0 (30000u) + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM1 (24000u) + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM2 (17000u) + + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM0 (600u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM1 (700u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM2 (800u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM3 (900u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM4 (1025u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM5 (1150u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM6 (1275u) + + #endif /* (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) */ +#endif /* (CY_IP_ECO) */ + + +/******************************************************************************* +* Access Arbitration API Constants +*******************************************************************************/ +#if (CY_IP_DMAC_PRESENT) + #define CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_RAM_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_FLASH_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_DMAC_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_SL_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_SL_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT)) + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +#if (CY_IP_DMAC_PRESENT) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_CPU (0u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_DMA (1u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_ROUND (2u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_ROUND_STICKY (3u) +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/******************************************************************************* +* Programmable Voltage Reference API +*******************************************************************************/ +#if (CY_IP_PASS) + + #define CYFLD_PASS_VREF_ENABLE__OFFSET (CYFLD_PASS_VREF0_ENABLE__OFFSET ) + #define CYFLD_PASS_VREF_ENABLE__SIZE (CYFLD_PASS_VREF0_ENABLE__SIZE ) + #define CYFLD_PASS_VREF_SUP_SEL__OFFSET (CYFLD_PASS_VREF0_SUP_SEL__OFFSET) + #define CYFLD_PASS_VREF_SUP_SEL__SIZE (CYFLD_PASS_VREF0_SUP_SEL__SIZE ) + #define CYFLD_PASS_VREF_SEL__OFFSET (CYFLD_PASS_VREF0_SEL__OFFSET ) + #define CYFLD_PASS_VREF_SEL__SIZE (CYFLD_PASS_VREF0_SEL__SIZE ) + + /* CySysSetGlobalVrefSource() */ + #define CY_SYS_VREF_SOURCE_BG (0u) + #define CY_SYS_VREF_SOURCE_VDDA (1u) + + /* CySysSetGlobalVrefBgGain() */ + #define CY_SYS_VREF_BG_GAINx1 (1u) + #define CY_SYS_VREF_BG_GAINx2 (2u) + + #ifdef CyDesignWideVoltageReference_PRB_REF + #define CYREG_PASS_PRB_REF (CyDesignWideVoltageReference_PRB_REF) + #endif + + #define CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT (0x20u) + +#endif /* (CY_IP_PASS) */ + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* Clocks API Registers +*******************************************************************************/ +#define CY_SYS_CLK_IMO_TRIM1_REG (*(reg32 *) CYREG_CLK_IMO_TRIM1) +#define CY_SYS_CLK_IMO_TRIM1_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM1) + +#define CY_SYS_CLK_IMO_TRIM2_REG (*(reg32 *) CYREG_CLK_IMO_TRIM2) +#define CY_SYS_CLK_IMO_TRIM2_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM2) + +#define CY_SYS_CLK_IMO_TRIM3_REG (*(reg32 *) CYREG_CLK_IMO_TRIM3) +#define CY_SYS_CLK_IMO_TRIM3_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM3) + +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_TRIM4_REG (*(reg32 *) CYREG_CLK_IMO_TRIM4) + #define CY_SYS_CLK_IMO_TRIM4_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM4) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_CLK_IMO_CONFIG_REG (*(reg32 *) CYREG_CLK_IMO_CONFIG) +#define CY_SYS_CLK_IMO_CONFIG_PTR ( (reg32 *) CYREG_CLK_IMO_CONFIG) + + +#define CY_SYS_CLK_SELECT_REG (*(reg32 *) CYREG_CLK_SELECT) +#define CY_SYS_CLK_SELECT_PTR ( (reg32 *) CYREG_CLK_SELECT) + +#if(CY_IP_SRSSV2) + + #if(CY_IP_HOBTO_DEVICE) + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number]) + #else + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number]) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG (*(reg8 *) CYREG_SFLASH_USBMODE_IMO_GAIN_TRIM) + #define CY_SFLASH_USBMODE_IMO_GAIN_TRIM_PTR ( (reg8 *) CYREG_SFLASH_USBMODE_IMO_GAIN_TRIM) + + #define CY_SFLASH_USBMODE_IMO_TEMPCO_REG (*(reg8 *) CYREG_SFLASH_USBMODE_IMO_TEMPCO) + #define CY_SFLASH_USBMODE_IMO_TEMPCO_PTR ( (reg8 *) CYREG_SFLASH_USBMODE_IMO_TEMPCO) + + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_48) + + #define CY_SFLASH_S1_TESTPGM_REV_REG (*(reg8 *) CYSFLASH_S1_testpgm_rev) + #define CY_SFLASH_S1_TESTPGM_REV_PTR ( (reg8 *) CYSFLASH_S1_testpgm_rev) + + #define CY_SFLASH_IMO_MAXF0_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF0) + #define CY_SFLASH_IMO_MAXF0_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF0) + + #define CY_SFLASH_IMO_ABS0_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS0) + #define CY_SFLASH_IMO_ABS0_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS0) + + #define CY_SFLASH_IMO_TMPCO0_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO0) + #define CY_SFLASH_IMO_TMPCO0_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO0) + + #define CY_SFLASH_IMO_MAXF1_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF1) + #define CY_SFLASH_IMO_MAXF1_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF1) + + #define CY_SFLASH_IMO_ABS1_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS1) + #define CY_SFLASH_IMO_ABS1_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS1) + + #define CY_SFLASH_IMO_TMPCO1_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO1) + #define CY_SFLASH_IMO_TMPCO1_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO1) + + #define CY_SFLASH_IMO_MAXF2_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF2) + #define CY_SFLASH_IMO_MAXF2_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF2) + + #define CY_SFLASH_IMO_ABS2_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS2) + #define CY_SFLASH_IMO_ABS2_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS2) + + #define CY_SFLASH_IMO_TMPCO2_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO2) + #define CY_SFLASH_IMO_TMPCO2_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO2) + + #define CY_SFLASH_IMO_MAXF3_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF3) + #define CY_SFLASH_IMO_MAXF3_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF3) + + #define CY_SFLASH_IMO_ABS3_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS3) + #define CY_SFLASH_IMO_ABS3_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS3) + + #define CY_SFLASH_IMO_TMPCO3_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO3) + #define CY_SFLASH_IMO_TMPCO3_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO3) + + #define CY_SFLASH_IMO_ABS4_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS4) + #define CY_SFLASH_IMO_ABS4_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS4) + + #define CY_SFLASH_IMO_TMPCO4_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO4) + #define CY_SFLASH_IMO_TMPCO4_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO4) + + #define CY_PWR_BG_TRIM4_REG (*(reg32 *) CYREG_PWR_BG_TRIM4) + #define CY_PWR_BG_TRIM4_PTR ( (reg32 *) CYREG_PWR_BG_TRIM4) + + #define CY_PWR_BG_TRIM5_REG (*(reg32 *) CYREG_PWR_BG_TRIM5) + #define CY_PWR_BG_TRIM5_PTR ( (reg32 *) CYREG_PWR_BG_TRIM5) + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #define CY_SFLASH_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#else + + #define CY_SYS_CLK_IMO_SELECT_REG (*(reg32 *) CYREG_CLK_IMO_SELECT) + #define CY_SYS_CLK_IMO_SELECT_PTR ( (reg32 *) CYREG_CLK_IMO_SELECT) + + #define CY_SFLASH_IMO_TCTRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number]) + #define CY_SFLASH_IMO_TCTRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number]) + + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number]) + + #if (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSLT) + + #define CY_SFLASH_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSLT) */ + +#endif /* (CY_IP_SRSSV2) */ + +#if(CY_IP_IMO_TRIMMABLE_BY_USB) + /* USB control 0 Register */ + #define CY_SYS_CLK_USBDEVv2_CR1_REG (*(reg32 *) CYREG_USBDEVv2_CR1) + #define CY_SYS_CLK_USBDEVv2_CR1_PTR ( (reg32 *) CYREG_USBDEVv2_CR1) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +/******************************************************************************* +* ECO +*******************************************************************************/ +#if (CY_IP_ECO) + #if (CY_IP_ECO_BLESS) + + /* Radio configuration register */ + #define CY_SYS_XTAL_BLESS_RF_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_RF_CONFIG) + #define CY_SYS_XTAL_BLESS_RF_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_RF_CONFIG) + + /* RFCTRL mode transition control */ + #define CY_SYS_XTAL_BLERD_DBUS_REG (*(reg32 *) CYREG_BLE_BLERD_DBUS) + #define CY_SYS_XTAL_BLERD_DBUS_PTR ( (reg32 *) CYREG_BLE_BLERD_DBUS) + + /* RFCTRL state information */ + #define CY_SYS_XTAL_BLERD_FSM_REG (*(reg32 *) CYREG_BLE_BLERD_FSM) + #define CY_SYS_XTAL_BLERD_FSM_PTR ( (reg32 *) CYREG_BLE_BLERD_FSM) + + /* BB bump configuration 1 */ + #define CY_SYS_XTAL_BLERD_BB_XO_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO) + #define CY_SYS_XTAL_BLERD_BB_XO_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO) + + /* BB bump configuration 2 */ + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM) + + /* Crystal clock divider configuration register */ + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + + #elif (CY_IP_ECO_BLESSV3) + /* Crystal clock divider configuration register */ + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + + /* RCB registers */ + #define CY_SYS_RCB_CTRL_REG (*(reg32 *) CYREG_BLE_RCB_CTRL) + #define CY_SYS_RCB_CTRL_PTR ( (reg32 *) CYREG_BLE_RCB_CTRL) + #define CY_SYS_RCB_TX_FIFO_WR_REG (*(reg32 *) CYREG_BLE_RCB_TX_FIFO_WR) + #define CY_SYS_RCB_TX_FIFO_WR_PTR ( (reg32 *) CYREG_BLE_RCB_TX_FIFO_WR) + #define CY_SYS_RCB_RX_FIFO_RD_REG (*(reg32 *) CYREG_BLE_RCB_RX_FIFO_RD) + #define CY_SYS_RCB_RX_FIFO_RD_PTR ( (reg32 *) CYREG_BLE_RCB_RX_FIFO_RD) + #define CY_SYS_RCB_INTR_REG (*(reg32 *) CYREG_BLE_RCB_INTR) + #define CY_SYS_RCB_INTR_PTR ( (reg32 *) CYREG_BLE_RCB_INTR) + #define CY_SYS_RCB_INTR_MASK_REG (*(reg32 *) CYREG_BLE_RCB_INTR_MASK) + #define CY_SYS_RCB_INTR_MASK_PTR ( (reg32 *) CYREG_BLE_RCB_INTR_MASK) + + + /* BLESS registers */ + #define CY_SYS_BLESS_MT_CFG_REG (*(reg32 *) CYREG_BLE_BLESS_MT_CFG) + #define CY_SYS_BLESS_MT_CFG_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_CFG) + #define CY_SYS_BLESS_MT_STATUS_REG (*(reg32 *) CYREG_BLE_BLESS_MT_STATUS) + #define CY_SYS_BLESS_MT_STATUS_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_STATUS) + #define CY_SYS_BLESS_INTR_STAT_REG (*(reg32 *) CYREG_BLE_BLESS_INTR_STAT) + #define CY_SYS_BLESS_INTR_STAT_PTR ( (reg32 *) CYREG_BLE_BLESS_INTR_STAT) + #define CY_SYS_BLESS_INTR_MASK_REG (*(reg32 *) CYREG_BLE_BLESS_INTR_MASK) + #define CY_SYS_BLESS_INTR_MASK_PTR ( (reg32 *) CYREG_BLE_BLESS_INTR_MASK) + #define CY_SYS_BLESS_MT_DELAY_CFG_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG) + #define CY_SYS_BLESS_MT_DELAY_CFG_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG) + #define CY_SYS_BLESS_MT_DELAY_CFG2_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG2) + #define CY_SYS_BLESS_MT_DELAY_CFG2_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG2) + #define CY_SYS_BLESS_MT_DELAY_CFG3_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG3) + #define CY_SYS_BLESS_MT_DELAY_CFG3_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG3) + + /* BLELL registers */ + #define CY_SYS_BLELL_COMMAND_REG (*(reg32 *) CYREG_BLE_BLELL_COMMAND_REGISTER) + #define CY_SYS_BLELL_COMMAND_PTR ( (reg32 *) CYREG_BLE_BLELL_COMMAND_REGISTER) + + #elif (CY_IP_ECO_SRSSLT) + + /* ECO Clock Select Register */ + #define CY_SYS_ECO_CLK_SELECT_REG (*(reg32 *) CYREG_EXCO_CLK_SELECT) + #define CY_SYS_ECO_CLK_SELECT_PTR ( (reg32 *) CYREG_EXCO_CLK_SELECT) + + /* ECO Configuration Register */ + #define CY_SYS_CLK_ECO_CONFIG_REG (*(reg32 *) CYREG_EXCO_ECO_CONFIG) + #define CY_SYS_CLK_ECO_CONFIG_PTR ( (reg32 *) CYREG_EXCO_ECO_CONFIG) + + /* ECO Status Register */ + #define CY_SYS_CLK_ECO_STATUS_REG (*(reg32 *) CYREG_EXCO_ECO_STATUS) + #define CY_SYS_CLK_ECO_STATUS_PTR ( (reg32 *) CYREG_EXCO_ECO_STATUS) + + /* PLL Configuration Register */ + #define CY_SYS_CLK_PLL0_CONFIG_REG (*(reg32 *) CYREG_EXCO_PLL_CONFIG) + #define CY_SYS_CLK_PLL0_CONFIG_PTR ( (reg32 *) CYREG_EXCO_PLL_CONFIG) + + /* PLL Status Register */ + #define CY_SYS_CLK_PLL_STATUS_REG (*(reg32 *) CYREG_EXCO_PLL_STATUS) + #define CY_SYS_CLK_PLL_STATUS_PTR ( (reg32 *) CYREG_EXCO_PLL_STATUS) + + #define CY_SYS_CLK_PLL_BASE (*(volatile cy_sys_clk_pll_struct *) CYREG_EXCO_PLL_CONFIG) + + /* ECO Trim0 Register */ + #define CY_SYS_CLK_ECO_TRIM0_REG (*(reg32 *) CYREG_EXCO_ECO_TRIM0) + #define CY_SYS_CLK_ECO_TRIM0_PTR ( (reg32 *) CYREG_EXCO_ECO_TRIM0) + + /* ECO Trim1 Register */ + #define CY_SYS_CLK_ECO_TRIM1_REG (*(reg32 *) CYREG_EXCO_ECO_TRIM1) + #define CY_SYS_CLK_ECO_TRIM1_PTR ( (reg32 *) CYREG_EXCO_ECO_TRIM1) + + /* PLL Trim Register */ + #define CY_SYS_CLK_PLL_TRIM_REG (*(reg32 *) CYREG_EXCO_PLL_TRIM) + #define CY_SYS_CLK_PLL_TRIM_PTR ( (reg32 *) CYREG_EXCO_PLL_TRIM) + + #define CY_SYS_EXCO_PGM_CLK_REG (*(reg32 *) CYREG_EXCO_EXCO_PGM_CLK) + #define CY_SYS_EXCO_PGM_CLK_PTR ( (reg32 *) CYREG_EXCO_EXCO_PGM_CLK) + + #else + /* ECO Configuration Register */ + #define CY_SYS_CLK_ECO_CONFIG_REG (*(reg32 *) CYREG_CLK_ECO_CONFIG) + #define CY_SYS_CLK_ECO_CONFIG_PTR ( (reg32 *) CYREG_CLK_ECO_CONFIG) + + /* ECO Status Register */ + #define CY_SYS_CLK_ECO_STATUS_REG (*(reg32 *) CYREG_CLK_ECO_STATUS) + #define CY_SYS_CLK_ECO_STATUS_PTR ( (reg32 *) CYREG_CLK_ECO_STATUS) + + /* ECO Trim0 Register */ + #define CY_SYS_CLK_ECO_TRIM0_REG (*(reg32 *) CYREG_CLK_ECO_TRIM0) + #define CY_SYS_CLK_ECO_TRIM0_PTR ( (reg32 *) CYREG_CLK_ECO_TRIM0) + + /* ECO Trim1 Register */ + #define CY_SYS_CLK_ECO_TRIM1_REG (*(reg32 *) CYREG_CLK_ECO_TRIM1) + #define CY_SYS_CLK_ECO_TRIM1_PTR ( (reg32 *) CYREG_CLK_ECO_TRIM1) + #endif /* (CY_IP_ECO_BLESS) */ +#endif /* (CY_IP_ECO) */ + + +/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() registers */ +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* WCO DPLL Register */ + #define CY_SYS_CLK_WCO_DPLL_REG (*(reg32 *) CYREG_WCO_DPLL) + #define CY_SYS_CLK_WCO_DPLL_PTR ( (reg32 *) CYREG_WCO_DPLL) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + /* Oscillator Interface Control */ + #define CY_SYS_CLK_OSCINTF_CTL_REG (*(reg32 *) CYREG_CLK_OSCINTF_CTL) + #define CY_SYS_CLK_OSCINTF_CTL_PTR ( (reg32 *) CYREG_CLK_OSCINTF_CTL) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +/******************************************************************************* +* PLL +*******************************************************************************/ +#if (CY_IP_SRSSV2 && CY_IP_PLL) + + /* PLL #0 Configuration Register */ + #define CY_SYS_CLK_PLL0_CONFIG_REG (*(reg32 *) CYREG_CLK_PLL0_CONFIG) + #define CY_SYS_CLK_PLL0_CONFIG_PTR ( (reg32 *) CYREG_CLK_PLL0_CONFIG) + + /* PLL #0 Status Register */ + #define CY_SYS_CLK_PLL0_STATUS_REG (*(reg32 *) CYREG_CLK_PLL0_STATUS) + #define CY_SYS_CLK_PLL0_STATUS_PTR ( (reg32 *) CYREG_CLK_PLL0_STATUS) + + + /* PLL #1 Configuration Register */ + #define CY_SYS_CLK_PLL1_CONFIG_REG (*(reg32 *) CYREG_CLK_PLL1_CONFIG) + #define CY_SYS_CLK_PLL1_CONFIG_PTR ( (reg32 *) CYREG_CLK_PLL1_CONFIG) + + /* PLL #1 Status Register */ + #define CY_SYS_CLK_PLL1_STATUS_REG (*(reg32 *) CYREG_CLK_PLL1_STATUS) + #define CY_SYS_CLK_PLL1_STATUS_PTR ( (reg32 *) CYREG_CLK_PLL1_STATUS) + + #define CY_SYS_CLK_PLL_BASE (*(volatile cy_sys_clk_pll_struct *) CYREG_CLK_PLL0_CONFIG) + +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + + +/******************************************************************************* +* System API Registers +*******************************************************************************/ +#if (CY_IP_CPUSS_CM0) + #define CY_SYS_AIRCR_REG (*(reg32 *) CYREG_CM0_AIRCR) + #define CY_SYS_AIRCR_PTR ( (reg32 *) CYREG_CM0_AIRCR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_SYS_AIRCR_REG (*(reg32 *) CYREG_CM0P_AIRCR) + #define CY_SYS_AIRCR_PTR ( (reg32 *) CYREG_CM0P_AIRCR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/* Reset Cause Observation Register */ +#define CY_SYS_RES_CAUSE_REG (*(reg32 *) CYREG_RES_CAUSE) +#define CY_SYS_RES_CAUSE_PTR ( (reg32 *) CYREG_RES_CAUSE) + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Low Voltage Detection + *******************************************************************************/ + + /* Voltage Monitoring Trim and Configuration */ + #define CY_LVD_PWR_VMON_CONFIG_REG (*(reg32 *) CYREG_PWR_VMON_CONFIG) + #define CY_LVD_PWR_VMON_CONFIG_PTR ( (reg32 *) CYREG_PWR_VMON_CONFIG) + + /* Power System Interrupt Mask Register */ + #define CY_LVD_PWR_INTR_MASK_REG (*(reg32 *) CYREG_PWR_INTR_MASK) + #define CY_LVD_PWR_INTR_MASK_PTR ( (reg32 *) CYREG_PWR_INTR_MASK) + + /* Power System Interrupt Register */ + #define CY_LVD_PWR_INTR_REG (*(reg32 *) CYREG_PWR_INTR) + #define CY_LVD_PWR_INTR_PTR ( (reg32 *) CYREG_PWR_INTR) + +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Interrupt API Registers +*******************************************************************************/ +#define CY_INT_VECT_TABLE ( (cyisraddress **) CYDEV_SRAM_BASE) + +#if (CY_IP_CPUSS_CM0) + #define CY_INT_PRIORITY_REG(number) ( ((reg32 *) CYREG_CM0_IPR0)[(number)/4u]) + #define CY_INT_PRIORITY_PTR(number) (&((reg32 *) CYREG_CM0_IPR0)[(number)/4u]) + + #define CY_INT_ENABLE_REG (*(reg32 *) CYREG_CM0_ISER) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_CM0_ISER) + + #define CY_INT_CLEAR_REG (*(reg32 *) CYREG_CM0_ICER) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_CM0_ICER) + + #define CY_INT_SET_PEND_REG (*(reg32 *) CYREG_CM0_ISPR) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_CM0_ISPR) + + #define CY_INT_CLR_PEND_REG (*(reg32 *) CYREG_CM0_ICPR) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_CM0_ICPR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_INT_PRIORITY_REG(number) ( ((reg32 *) CYREG_CM0P_IPR0)[(number)/4u]) + #define CY_INT_PRIORITY_PTR(number) (&((reg32 *) CYREG_CM0P_IPR0)[(number)/4u]) + + #define CY_INT_ENABLE_REG (*(reg32 *) CYREG_CM0P_ISER) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_CM0P_ISER) + + #define CY_INT_CLEAR_REG (*(reg32 *) CYREG_CM0P_ICER) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_CM0P_ICER) + + #define CY_INT_SET_PEND_REG (*(reg32 *) CYREG_CM0P_ISPR) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_CM0P_ISPR) + + #define CY_INT_CLR_PEND_REG (*(reg32 *) CYREG_CM0P_ICPR) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_CM0P_ICPR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/******************************************************************************* +* System tick API Registers +*******************************************************************************/ +#if (CY_IP_CPUSS_CM0) + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_CM0_SYST_CSR) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_CM0_SYST_CSR) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_CM0_SYST_RVR) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_CM0_SYST_RVR) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_CM0_SYST_CVR) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_CM0_SYST_CVR) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_CM0_SYST_CALIB) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_CM0_SYST_CALIB) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_CM0P_SYST_CSR) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_CM0P_SYST_CSR) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_CM0P_SYST_RVR) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_CM0P_SYST_RVR) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_CM0P_SYST_CVR) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_CM0P_SYST_CVR) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_CM0P_SYST_CALIB) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_CM0P_SYST_CALIB) +#endif /* (CY_IP_CPUSS_CM0) */ + + +/******************************************************************************* +* Access Arbitration API Registers +*******************************************************************************/ +#if (CY_IP_DMAC_PRESENT) + /* RAM control register */ + #define CY_SYS_CPUSS_RAM_CTL_REG (*(reg32 *) CYREG_CPUSS_RAM_CTL) + #define CY_SYS_CPUSS_RAM_CTL_PTR ( (reg32 *) CYREG_CPUSS_RAM_CTL) + + /* FLASH control register */ + #define CY_SYS_CPUSS_FLASH_CTL_REG (*(reg32 *) CYREG_CPUSS_FLASH_CTL) + #define CY_SYS_CPUSS_FLASH_CTL_PTR ( (reg32 *) CYREG_CPUSS_FLASH_CTL) + + /* DMAC control register */ + #define CY_SYS_CPUSS_DMAC_CTL_REG (*(reg32 *) CYREG_CPUSS_DMAC_CTL) + #define CY_SYS_CPUSS_DMAC_CTL_PTR ( (reg32 *) CYREG_CPUSS_DMAC_CTL) + + #if (CY_IP_SL_NR >= 1) + /* Slave control register # 0 */ + #if (CY_IP_SL_NR == 1) + #define CY_SYS_CPUSS_SL_CTL0_REG (*(reg32 *) CYREG_CPUSS_SL_CTL) + #define CY_SYS_CPUSS_SL_CTL0_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL) + #else + #define CY_SYS_CPUSS_SL_CTL0_REG (*(reg32 *) CYREG_CPUSS_SL_CTL0) + #define CY_SYS_CPUSS_SL_CTL0_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL0) + #endif /* (CY_IP_SL_NR == 1) */ + #endif /* (CY_IP_SL_NR > 0) */ + + #if (CY_IP_SL_NR >= 2) + /* Slave control register # 1 */ + #define CY_SYS_CPUSS_SL_CTL1_REG (*(reg32 *) CYREG_CPUSS_SL_CTL1) + #define CY_SYS_CPUSS_SL_CTL1_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL1) + #endif /* (CY_IP_SL_NR >= 1) */ + + #if (CY_IP_SL_NR >= 3) + /* Slave control register # 2 */ + #define CY_SYS_CPUSS_SL_CTL2_REG (*(reg32 *) CYREG_CPUSS_SL_CTL2) + #define CY_SYS_CPUSS_SL_CTL2_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL2) + #endif /* (CY_IP_SL_NR >= 2) */ + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions are intended for use in the application, +* use the following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) +#define CY_SYS_CLK_IMO_TRIM4_GAIN (CY_SYS_CLK_IMO_TRIM4_USB_GAIN) + +/* SFLASH0 block has been renamed to SFLASH */ +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + #if !defined(CYREG_SFLASH_IMO_TRIM21) + #define CYREG_SFLASH_IMO_TRIM21 (CYREG_SFLASH0_IMO_TRIM21) + #endif /* !defined(CYREG_SFLASH_IMO_TRIM21) */ +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + +#if (CY_IP_CPUSS_CM0) + + #define CY_SYS_CM0_AIRCR_REG (CY_SYS_AIRCR_REG) + #define CY_SYS_CM0_AIRCR_PTR (CY_SYS_AIRCR_PTR) + + #define CY_SYS_CM0_AIRCR_VECTKEY_SHIFT (CY_SYS_AIRCR_VECTKEY_SHIFT ) + #define CY_SYS_CM0_AIRCR_VECTKEY (CY_SYS_AIRCR_VECTKEY ) + #define CY_SYS_CM0_AIRCR_VECTKEY_MASK (CY_SYS_AIRCR_VECTKEY_MASK ) + #define CY_SYS_CM0_AIRCR_SYSRESETREQ_SHIFT (CY_SYS_AIRCR_SYSRESETREQ_SHIFT) + #define CY_SYS_CM0_AIRCR_SYSRESETREQ (CY_SYS_AIRCR_SYSRESETREQ ) + +#endif /* (CY_IP_CPUSS_CM0) */ + +#endif /* CY_BOOT_CYLIB_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1.c new file mode 100644 index 0000000..9bee24a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: Input_1.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "Input_1.h" + + +#if defined(Input_1__PC) + #define Input_1_SetP4PinDriveMode(shift, mode) \ + do { \ + Input_1_PC = (Input_1_PC & \ + (uint32)(~(uint32)(Input_1_DRIVE_MODE_IND_MASK << \ + (Input_1_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (Input_1_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define Input_1_SetP4PinDriveMode(shift, mode) \ + do { \ + Input_1_USBIO_CTRL_REG = (Input_1_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(Input_1_DRIVE_MODE_IND_MASK << \ + (Input_1_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (Input_1_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(Input_1__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: Input_1_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet Input_1_SUT.c usage_Input_1_SetDriveMode + *******************************************************************************/ + void Input_1_SetDriveMode(uint8 mode) + { + Input_1_SetP4PinDriveMode(Input_1__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: Input_1_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_Write +*******************************************************************************/ +void Input_1_Write(uint8 value) +{ + uint8 drVal = (uint8)(Input_1_DR & (uint8)(~Input_1_MASK)); + drVal = (drVal | ((uint8)(value << Input_1_SHIFT) & Input_1_MASK)); + Input_1_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: Input_1_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_Read +*******************************************************************************/ +uint8 Input_1_Read(void) +{ + return (uint8)((Input_1_PS & Input_1_MASK) >> Input_1_SHIFT); +} + + +/******************************************************************************* +* Function Name: Input_1_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred Input_1_Read() API because the +* Input_1_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_ReadDataReg +*******************************************************************************/ +uint8 Input_1_ReadDataReg(void) +{ + return (uint8)((Input_1_DR & Input_1_MASK) >> Input_1_SHIFT); +} + + +/******************************************************************************* +* Function Name: Input_1_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use Input_1_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - Input_1_0_INTR (First pin in the list) +* - Input_1_1_INTR (Second pin in the list) +* - ... +* - Input_1_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_SetInterruptMode +*******************************************************************************/ +void Input_1_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = Input_1_INTCFG & (uint32)(~(uint32)position); + Input_1_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: Input_1_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_ClearInterrupt +*******************************************************************************/ +uint8 Input_1_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(Input_1_INTSTAT & Input_1_MASK); + Input_1_INTSTAT = maskedStatus; + return maskedStatus >> Input_1_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1.h new file mode 100644 index 0000000..a02adc3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: Input_1.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_Input_1_H) /* Pins Input_1_H */ +#define CY_PINS_Input_1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "Input_1_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} Input_1_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 Input_1_Read(void); +void Input_1_Write(uint8 value); +uint8 Input_1_ReadDataReg(void); +#if defined(Input_1__PC) || (CY_PSOC4_4200L) + void Input_1_SetDriveMode(uint8 mode); +#endif +void Input_1_SetInterruptMode(uint16 position, uint16 mode); +uint8 Input_1_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void Input_1_Sleep(void); +void Input_1_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(Input_1__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define Input_1_DRIVE_MODE_BITS (3) + #define Input_1_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - Input_1_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the Input_1_SetDriveMode() function. + * @{ + */ + #define Input_1_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define Input_1_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define Input_1_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define Input_1_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define Input_1_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define Input_1_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define Input_1_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define Input_1_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define Input_1_MASK Input_1__MASK +#define Input_1_SHIFT Input_1__SHIFT +#define Input_1_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in Input_1_SetInterruptMode() function. + * @{ + */ + #define Input_1_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define Input_1_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define Input_1_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define Input_1_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(Input_1__SIO) + #define Input_1_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(Input_1__PC) && (CY_PSOC4_4200L) + #define Input_1_USBIO_ENABLE ((uint32)0x80000000u) + #define Input_1_USBIO_DISABLE ((uint32)(~Input_1_USBIO_ENABLE)) + #define Input_1_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define Input_1_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define Input_1_USBIO_ENTER_SLEEP ((uint32)((1u << Input_1_USBIO_SUSPEND_SHIFT) \ + | (1u << Input_1_USBIO_SUSPEND_DEL_SHIFT))) + #define Input_1_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << Input_1_USBIO_SUSPEND_SHIFT))) + #define Input_1_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << Input_1_USBIO_SUSPEND_DEL_SHIFT))) + #define Input_1_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(Input_1__PC) + /* Port Configuration */ + #define Input_1_PC (* (reg32 *) Input_1__PC) +#endif +/* Pin State */ +#define Input_1_PS (* (reg32 *) Input_1__PS) +/* Data Register */ +#define Input_1_DR (* (reg32 *) Input_1__DR) +/* Input Buffer Disable Override */ +#define Input_1_INP_DIS (* (reg32 *) Input_1__PC2) + +/* Interrupt configuration Registers */ +#define Input_1_INTCFG (* (reg32 *) Input_1__INTCFG) +#define Input_1_INTSTAT (* (reg32 *) Input_1__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define Input_1_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(Input_1__SIO) + #define Input_1_SIO_REG (* (reg32 *) Input_1__SIO) +#endif /* (Input_1__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(Input_1__PC) && (CY_PSOC4_4200L) + #define Input_1_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define Input_1_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define Input_1_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define Input_1_DRIVE_MODE_SHIFT (0x00u) +#define Input_1_DRIVE_MODE_MASK (0x07u << Input_1_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins Input_1_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1_PM.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1_PM.c new file mode 100644 index 0000000..de3c500 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: Input_1.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "Input_1.h" + +static Input_1_BACKUP_STRUCT Input_1_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: Input_1_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet Input_1_SUT.c usage_Input_1_Sleep_Wakeup +*******************************************************************************/ +void Input_1_Sleep(void) +{ + #if defined(Input_1__PC) + Input_1_backup.pcState = Input_1_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + Input_1_backup.usbState = Input_1_CR1_REG; + Input_1_USB_POWER_REG |= Input_1_USBIO_ENTER_SLEEP; + Input_1_CR1_REG &= Input_1_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(Input_1__SIO) + Input_1_backup.sioState = Input_1_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + Input_1_SIO_REG &= (uint32)(~Input_1_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: Input_1_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to Input_1_Sleep() for an example usage. +*******************************************************************************/ +void Input_1_Wakeup(void) +{ + #if defined(Input_1__PC) + Input_1_PC = Input_1_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + Input_1_USB_POWER_REG &= Input_1_USBIO_EXIT_SLEEP_PH1; + Input_1_CR1_REG = Input_1_backup.usbState; + Input_1_USB_POWER_REG &= Input_1_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(Input_1__SIO) + Input_1_SIO_REG = Input_1_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1_aliases.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1_aliases.h new file mode 100644 index 0000000..ad275f1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/Input_1_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: Input_1.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_Input_1_ALIASES_H) /* Pins Input_1_ALIASES_H */ +#define CY_PINS_Input_1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define Input_1_0 (Input_1__0__PC) +#define Input_1_0_PS (Input_1__0__PS) +#define Input_1_0_PC (Input_1__0__PC) +#define Input_1_0_DR (Input_1__0__DR) +#define Input_1_0_SHIFT (Input_1__0__SHIFT) +#define Input_1_0_INTR ((uint16)((uint16)0x0003u << (Input_1__0__SHIFT*2u))) + +#define Input_1_INTR_ALL ((uint16)(Input_1_0_INTR)) + + +#endif /* End Pins Input_1_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/LED.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED.c new file mode 100644 index 0000000..f6a2fdf --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: LED.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED.h" + + +#if defined(LED__PC) + #define LED_SetP4PinDriveMode(shift, mode) \ + do { \ + LED_PC = (LED_PC & \ + (uint32)(~(uint32)(LED_DRIVE_MODE_IND_MASK << \ + (LED_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (LED_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define LED_SetP4PinDriveMode(shift, mode) \ + do { \ + LED_USBIO_CTRL_REG = (LED_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(LED_DRIVE_MODE_IND_MASK << \ + (LED_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (LED_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(LED__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: LED_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet LED_SUT.c usage_LED_SetDriveMode + *******************************************************************************/ + void LED_SetDriveMode(uint8 mode) + { + LED_SetP4PinDriveMode(LED__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: LED_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Write +*******************************************************************************/ +void LED_Write(uint8 value) +{ + uint8 drVal = (uint8)(LED_DR & (uint8)(~LED_MASK)); + drVal = (drVal | ((uint8)(value << LED_SHIFT) & LED_MASK)); + LED_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: LED_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Read +*******************************************************************************/ +uint8 LED_Read(void) +{ + return (uint8)((LED_PS & LED_MASK) >> LED_SHIFT); +} + + +/******************************************************************************* +* Function Name: LED_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED_Read() API because the +* LED_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_ReadDataReg +*******************************************************************************/ +uint8 LED_ReadDataReg(void) +{ + return (uint8)((LED_DR & LED_MASK) >> LED_SHIFT); +} + + +/******************************************************************************* +* Function Name: LED_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use LED_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - LED_0_INTR (First pin in the list) +* - LED_1_INTR (Second pin in the list) +* - ... +* - LED_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_SetInterruptMode +*******************************************************************************/ +void LED_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = LED_INTCFG & (uint32)(~(uint32)position); + LED_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: LED_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_ClearInterrupt +*******************************************************************************/ +uint8 LED_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(LED_INTSTAT & LED_MASK); + LED_INTSTAT = maskedStatus; + return maskedStatus >> LED_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/LED.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED.h new file mode 100644 index 0000000..900f52f --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: LED.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_H) /* Pins LED_H */ +#define CY_PINS_LED_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "LED_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} LED_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 LED_Read(void); +void LED_Write(uint8 value); +uint8 LED_ReadDataReg(void); +#if defined(LED__PC) || (CY_PSOC4_4200L) + void LED_SetDriveMode(uint8 mode); +#endif +void LED_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void LED_Sleep(void); +void LED_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(LED__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define LED_DRIVE_MODE_BITS (3) + #define LED_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - LED_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED_SetDriveMode() function. + * @{ + */ + #define LED_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define LED_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define LED_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define LED_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define LED_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define LED_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define LED_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define LED_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define LED_MASK LED__MASK +#define LED_SHIFT LED__SHIFT +#define LED_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED_SetInterruptMode() function. + * @{ + */ + #define LED_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define LED_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define LED_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define LED_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(LED__SIO) + #define LED_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(LED__PC) && (CY_PSOC4_4200L) + #define LED_USBIO_ENABLE ((uint32)0x80000000u) + #define LED_USBIO_DISABLE ((uint32)(~LED_USBIO_ENABLE)) + #define LED_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define LED_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define LED_USBIO_ENTER_SLEEP ((uint32)((1u << LED_USBIO_SUSPEND_SHIFT) \ + | (1u << LED_USBIO_SUSPEND_DEL_SHIFT))) + #define LED_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << LED_USBIO_SUSPEND_SHIFT))) + #define LED_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << LED_USBIO_SUSPEND_DEL_SHIFT))) + #define LED_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(LED__PC) + /* Port Configuration */ + #define LED_PC (* (reg32 *) LED__PC) +#endif +/* Pin State */ +#define LED_PS (* (reg32 *) LED__PS) +/* Data Register */ +#define LED_DR (* (reg32 *) LED__DR) +/* Input Buffer Disable Override */ +#define LED_INP_DIS (* (reg32 *) LED__PC2) + +/* Interrupt configuration Registers */ +#define LED_INTCFG (* (reg32 *) LED__INTCFG) +#define LED_INTSTAT (* (reg32 *) LED__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define LED_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(LED__SIO) + #define LED_SIO_REG (* (reg32 *) LED__SIO) +#endif /* (LED__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(LED__PC) && (CY_PSOC4_4200L) + #define LED_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define LED_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define LED_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define LED_DRIVE_MODE_SHIFT (0x00u) +#define LED_DRIVE_MODE_MASK (0x07u << LED_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins LED_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/LED_PM.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED_PM.c new file mode 100644 index 0000000..7d143dd --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: LED.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED.h" + +static LED_BACKUP_STRUCT LED_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: LED_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Sleep_Wakeup +*******************************************************************************/ +void LED_Sleep(void) +{ + #if defined(LED__PC) + LED_backup.pcState = LED_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + LED_backup.usbState = LED_CR1_REG; + LED_USB_POWER_REG |= LED_USBIO_ENTER_SLEEP; + LED_CR1_REG &= LED_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(LED__SIO) + LED_backup.sioState = LED_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + LED_SIO_REG &= (uint32)(~LED_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: LED_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to LED_Sleep() for an example usage. +*******************************************************************************/ +void LED_Wakeup(void) +{ + #if defined(LED__PC) + LED_PC = LED_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + LED_USB_POWER_REG &= LED_USBIO_EXIT_SLEEP_PH1; + LED_CR1_REG = LED_backup.usbState; + LED_USB_POWER_REG &= LED_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(LED__SIO) + LED_SIO_REG = LED_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/LED_aliases.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED_aliases.h new file mode 100644 index 0000000..056ce76 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/LED_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: LED.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_ALIASES_H) /* Pins LED_ALIASES_H */ +#define CY_PINS_LED_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define LED_0 (LED__0__PC) +#define LED_0_PS (LED__0__PS) +#define LED_0_PC (LED__0__PC) +#define LED_0_DR (LED__0__DR) +#define LED_0_SHIFT (LED__0__SHIFT) +#define LED_0_INTR ((uint16)((uint16)0x0003u << (LED__0__SHIFT*2u))) + +#define LED_INTR_ALL ((uint16)(LED_0_INTR)) + + +#endif /* End Pins LED_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART.c new file mode 100644 index 0000000..7e83645 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART.c @@ -0,0 +1,818 @@ +/***************************************************************************//** +* \file UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" + +#if (UART_SCB_MODE_I2C_INC) + #include "UART_I2C_PVT.h" +#endif /* (UART_SCB_MODE_I2C_INC) */ + +#if (UART_SCB_MODE_EZI2C_INC) + #include "UART_EZI2C_PVT.h" +#endif /* (UART_SCB_MODE_EZI2C_INC) */ + +#if (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) + #include "UART_SPI_UART_PVT.h" +#endif /* (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) */ + + +/*************************************** +* Run Time Configuration Vars +***************************************/ + +/* Stores internal component configuration for Unconfigured mode */ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + uint8 UART_scbMode = UART_SCB_MODE_UNCONFIG; + uint8 UART_scbEnableWake; + uint8 UART_scbEnableIntr; + + /* I2C configuration variables */ + uint8 UART_mode; + uint8 UART_acceptAddr; + + /* SPI/UART configuration variables */ + volatile uint8 * UART_rxBuffer; + uint8 UART_rxDataBits; + uint32 UART_rxBufferSize; + + volatile uint8 * UART_txBuffer; + uint8 UART_txDataBits; + uint32 UART_txBufferSize; + + /* EZI2C configuration variables */ + uint8 UART_numberOfAddr; + uint8 UART_subAddrSize; +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Common SCB Vars +***************************************/ +/** +* \addtogroup group_general +* \{ +*/ + +/** UART_initVar indicates whether the UART +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the UART_Start() routine. +* +* If re-initialization of the component is required, then the +* UART_Init() function can be called before the +* UART_Start() or UART_Enable() function. +*/ +uint8 UART_initVar = 0u; + + +#if (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) + /** This global variable stores TX interrupt sources after + * UART_Stop() is called. Only these TX interrupt sources + * will be restored on a subsequent UART_Enable() call. + */ + uint16 UART_IntrTxMask = 0u; +#endif /* (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) */ +/** \} globals */ + +#if (UART_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + void (*UART_customIntrHandler)(void) = NULL; +#endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +static void UART_ScbEnableIntr(void); +static void UART_ScbModeStop(void); +static void UART_ScbModePostEnable(void); + + +/******************************************************************************* +* Function Name: UART_Init +****************************************************************************//** +* +* Initializes the UART component to operate in one of the selected +* configurations: I2C, SPI, UART or EZI2C. +* When the configuration is set to "Unconfigured SCB", this function does +* not do any initialization. Use mode-specific initialization APIs instead: +* UART_I2CInit, UART_SpiInit, +* UART_UartInit or UART_EzI2CInit. +* +*******************************************************************************/ +void UART_Init(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + if (UART_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + UART_initVar = 0u; + } + else + { + /* Initialization was done before this function call */ + } + +#elif (UART_SCB_MODE_I2C_CONST_CFG) + UART_I2CInit(); + +#elif (UART_SCB_MODE_SPI_CONST_CFG) + UART_SpiInit(); + +#elif (UART_SCB_MODE_UART_CONST_CFG) + UART_UartInit(); + +#elif (UART_SCB_MODE_EZI2C_CONST_CFG) + UART_EzI2CInit(); + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_Enable +****************************************************************************//** +* +* Enables UART component operation: activates the hardware and +* internal interrupt. It also restores TX interrupt sources disabled after the +* UART_Stop() function was called (note that level-triggered TX +* interrupt sources remain disabled to not cause code lock-up). +* For I2C and EZI2C modes the interrupt is internal and mandatory for +* operation. For SPI and UART modes the interrupt can be configured as none, +* internal or external. +* The UART configuration should be not changed when the component +* is enabled. Any configuration changes should be made after disabling the +* component. +* When configuration is set to “Unconfigured UART”, the component +* must first be initialized to operate in one of the following configurations: +* I2C, SPI, UART or EZ I2C, using the mode-specific initialization API. +* Otherwise this function does not enable the component. +* +*******************************************************************************/ +void UART_Enable(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Enable SCB block, only if it is already configured */ + if (!UART_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + UART_CTRL_REG |= UART_CTRL_ENABLED; + + UART_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + UART_ScbModePostEnable(); + } +#else + UART_CTRL_REG |= UART_CTRL_ENABLED; + + UART_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + UART_ScbModePostEnable(); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_Start +****************************************************************************//** +* +* Invokes UART_Init() and UART_Enable(). +* After this function call, the component is enabled and ready for operation. +* When configuration is set to "Unconfigured SCB", the component must first be +* initialized to operate in one of the following configurations: I2C, SPI, UART +* or EZI2C. Otherwise this function does not enable the component. +* +* \globalvars +* UART_initVar - used to check initial configuration, modified +* on first function call. +* +*******************************************************************************/ +void UART_Start(void) +{ + if (0u == UART_initVar) + { + UART_Init(); + UART_initVar = 1u; /* Component was initialized */ + } + + UART_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_Stop +****************************************************************************//** +* +* Disables the UART component: disable the hardware and internal +* interrupt. It also disables all TX interrupt sources so as not to cause an +* unexpected interrupt trigger because after the component is enabled, the +* TX FIFO is empty. +* Refer to the function UART_Enable() for the interrupt +* configuration details. +* This function disables the SCB component without checking to see if +* communication is in progress. Before calling this function it may be +* necessary to check the status of communication to make sure communication +* is complete. If this is not done then communication could be stopped mid +* byte and corrupted data could result. +* +*******************************************************************************/ +void UART_Stop(void) +{ +#if (UART_SCB_IRQ_INTERNAL) + UART_DisableInt(); +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + /* Call Stop function specific to current operation mode */ + UART_ScbModeStop(); + + /* Disable SCB IP */ + UART_CTRL_REG &= (uint32) ~UART_CTRL_ENABLED; + + /* Disable all TX interrupt sources so as not to cause an unexpected + * interrupt trigger after the component will be enabled because the + * TX FIFO is empty. + * For SCB IP v0, it is critical as it does not mask-out interrupt + * sources when it is disabled. This can cause a code lock-up in the + * interrupt handler because TX FIFO cannot be loaded after the block + * is disabled. + */ + UART_SetTxInterruptMode(UART_NO_INTR_SOURCES); + +#if (UART_SCB_IRQ_INTERNAL) + UART_ClearPendingInt(); +#endif /* (UART_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: UART_SetRxFifoLevel +****************************************************************************//** +* +* Sets level in the RX FIFO to generate a RX level interrupt. +* When the RX FIFO has more entries than the RX FIFO level an RX level +* interrupt request is generated. +* +* \param level: Level in the RX FIFO to generate RX level interrupt. +* The range of valid level values is between 0 and RX FIFO depth - 1. +* +*******************************************************************************/ +void UART_SetRxFifoLevel(uint32 level) +{ + uint32 rxFifoCtrl; + + rxFifoCtrl = UART_RX_FIFO_CTRL_REG; + + rxFifoCtrl &= ((uint32) ~UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + rxFifoCtrl |= ((uint32) (UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_RX_FIFO_CTRL_REG = rxFifoCtrl; +} + + +/******************************************************************************* +* Function Name: UART_SetTxFifoLevel +****************************************************************************//** +* +* Sets level in the TX FIFO to generate a TX level interrupt. +* When the TX FIFO has less entries than the TX FIFO level an TX level +* interrupt request is generated. +* +* \param level: Level in the TX FIFO to generate TX level interrupt. +* The range of valid level values is between 0 and TX FIFO depth - 1. +* +*******************************************************************************/ +void UART_SetTxFifoLevel(uint32 level) +{ + uint32 txFifoCtrl; + + txFifoCtrl = UART_TX_FIFO_CTRL_REG; + + txFifoCtrl &= ((uint32) ~UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + txFifoCtrl |= ((uint32) (UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_TX_FIFO_CTRL_REG = txFifoCtrl; +} + + +#if (UART_SCB_IRQ_INTERNAL) + /******************************************************************************* + * Function Name: UART_SetCustomInterruptHandler + ****************************************************************************//** + * + * Registers a function to be called by the internal interrupt handler. + * First the function that is registered is called, then the internal interrupt + * handler performs any operation such as software buffer management functions + * before the interrupt returns. It is the user's responsibility not to break + * the software buffer operations. Only one custom handler is supported, which + * is the function provided by the most recent call. + * At the initialization time no custom handler is registered. + * + * \param func: Pointer to the function to register. + * The value NULL indicates to remove the current custom interrupt + * handler. + * + *******************************************************************************/ + void UART_SetCustomInterruptHandler(void (*func)(void)) + { + #if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + UART_customIntrHandler = func; /* Register interrupt handler */ + #else + if (NULL != func) + { + /* Suppress compiler warning */ + } + #endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ + } +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + +/******************************************************************************* +* Function Name: UART_ScbModeEnableIntr +****************************************************************************//** +* +* Enables an interrupt for a specific mode. +* +*******************************************************************************/ +static void UART_ScbEnableIntr(void) +{ +#if (UART_SCB_IRQ_INTERNAL) + /* Enable interrupt in NVIC */ + #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + if (0u != UART_scbEnableIntr) + { + UART_EnableInt(); + } + + #else + UART_EnableInt(); + + #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +#endif /* (UART_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: UART_ScbModePostEnable +****************************************************************************//** +* +* Calls the PostEnable function for a specific operation mode. +* +*******************************************************************************/ +static void UART_ScbModePostEnable(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) +#if (!UART_CY_SCBIP_V1) + if (UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiPostEnable(); + } + else if (UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartPostEnable(); + } + else + { + /* Unknown mode: do nothing */ + } +#endif /* (!UART_CY_SCBIP_V1) */ + +#elif (UART_SCB_MODE_SPI_CONST_CFG) + UART_SpiPostEnable(); + +#elif (UART_SCB_MODE_UART_CONST_CFG) + UART_UartPostEnable(); + +#else + /* Unknown mode: do nothing */ +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_ScbModeStop +****************************************************************************//** +* +* Calls the Stop function for a specific operation mode. +* +*******************************************************************************/ +static void UART_ScbModeStop(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + if (UART_SCB_MODE_I2C_RUNTM_CFG) + { + UART_I2CStop(); + } + else if (UART_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_EzI2CStop(); + } +#if (!UART_CY_SCBIP_V1) + else if (UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiStop(); + } + else if (UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartStop(); + } +#endif /* (!UART_CY_SCBIP_V1) */ + else + { + /* Unknown mode: do nothing */ + } +#elif (UART_SCB_MODE_I2C_CONST_CFG) + UART_I2CStop(); + +#elif (UART_SCB_MODE_EZI2C_CONST_CFG) + UART_EzI2CStop(); + +#elif (UART_SCB_MODE_SPI_CONST_CFG) + UART_SpiStop(); + +#elif (UART_SCB_MODE_UART_CONST_CFG) + UART_UartStop(); + +#else + /* Unknown mode: do nothing */ +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: UART_SetPins + ****************************************************************************//** + * + * Sets the pins settings accordingly to the selected operation mode. + * Only available in the Unconfigured operation mode. The mode specific + * initialization function calls it. + * Pins configuration is set by PSoC Creator when a specific mode of operation + * is selected in design time. + * + * \param mode: Mode of SCB operation. + * \param subMode: Sub-mode of SCB operation. It is only required for SPI and UART + * modes. + * \param uartEnableMask: enables TX or RX direction and RTS and CTS signals. + * + *******************************************************************************/ + void UART_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask) + { + uint32 pinsDm[UART_SCB_PINS_NUMBER]; + uint32 i; + + #if (!UART_CY_SCBIP_V1) + uint32 pinsInBuf = 0u; + #endif /* (!UART_CY_SCBIP_V1) */ + + uint32 hsiomSel[UART_SCB_PINS_NUMBER] = + { + UART_RX_SCL_MOSI_HSIOM_SEL_GPIO, + UART_TX_SDA_MISO_HSIOM_SEL_GPIO, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + + #if (UART_CY_SCBIP_V1) + /* Supress compiler warning. */ + if ((0u == subMode) || (0u == uartEnableMask)) + { + } + #endif /* (UART_CY_SCBIP_V1) */ + + /* Set default HSIOM to GPIO and Drive Mode to Analog Hi-Z */ + for (i = 0u; i < UART_SCB_PINS_NUMBER; i++) + { + pinsDm[i] = UART_PIN_DM_ALG_HIZ; + } + + if ((UART_SCB_MODE_I2C == mode) || + (UART_SCB_MODE_EZI2C == mode)) + { + #if (UART_RX_SCL_MOSI_PIN) + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_I2C; + pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + #if (!UART_CY_SCBIP_V1) + else if (UART_SCB_MODE_SPI == mode) + { + #if (UART_RX_SCL_MOSI_PIN) + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_SPI; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_SPI; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_SPI; + #endif /* (UART_TX_SDA_MISO_PIN) */ + + #if (UART_SCLK_PIN) + hsiomSel[UART_SCLK_PIN_INDEX] = UART_SCLK_HSIOM_SEL_SPI; + #endif /* (UART_SCLK_PIN) */ + + if (UART_SPI_SLAVE == subMode) + { + /* Slave */ + pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + + #if (UART_SS0_PIN) + /* Only SS0 is valid choice for Slave */ + hsiomSel[UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_SPI; + pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #endif /* (UART_SS0_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + /* Disable input buffer */ + pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + else + { + /* (Master) */ + pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_STRONG; + + #if (UART_SS0_PIN) + hsiomSel [UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_SPI; + pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS0_PIN_MASK; + #endif /* (UART_SS0_PIN) */ + + #if (UART_SS1_PIN) + hsiomSel [UART_SS1_PIN_INDEX] = UART_SS1_HSIOM_SEL_SPI; + pinsDm [UART_SS1_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS1_PIN_MASK; + #endif /* (UART_SS1_PIN) */ + + #if (UART_SS2_PIN) + hsiomSel [UART_SS2_PIN_INDEX] = UART_SS2_HSIOM_SEL_SPI; + pinsDm [UART_SS2_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS2_PIN_MASK; + #endif /* (UART_SS2_PIN) */ + + #if (UART_SS3_PIN) + hsiomSel [UART_SS3_PIN_INDEX] = UART_SS3_HSIOM_SEL_SPI; + pinsDm [UART_SS3_PIN_INDEX] = UART_PIN_DM_STRONG; + pinsInBuf |= UART_SS3_PIN_MASK; + #endif /* (UART_SS3_PIN) */ + + /* Disable input buffers */ + #if (UART_RX_SCL_MOSI_PIN) + pinsInBuf |= UART_RX_SCL_MOSI_PIN_MASK; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + pinsInBuf |= UART_RX_WAKE_SCL_MOSI_PIN_MASK; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_SCLK_PIN) + pinsInBuf |= UART_SCLK_PIN_MASK; + #endif /* (UART_SCLK_PIN) */ + } + } + else /* UART */ + { + if (UART_UART_MODE_SMARTCARD == subMode) + { + /* SmartCard */ + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + else /* Standard or IrDA */ + { + if (0u != (UART_UART_RX_PIN_ENABLE & uartEnableMask)) + { + #if (UART_RX_SCL_MOSI_PIN) + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #else + #endif /* (UART_RX_SCL_MOSI_PIN) */ + } + + if (0u != (UART_UART_TX_PIN_ENABLE & uartEnableMask)) + { + #if (UART_TX_SDA_MISO_PIN) + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; + #endif /* (UART_TX_SDA_MISO_PIN) */ + } + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + if (UART_UART_MODE_STD == subMode) + { + if (0u != (UART_UART_CTS_PIN_ENABLE & uartEnableMask)) + { + /* CTS input is multiplexed with SCLK */ + #if (UART_SCLK_PIN) + hsiomSel[UART_SCLK_PIN_INDEX] = UART_SCLK_HSIOM_SEL_UART; + pinsDm [UART_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + #endif /* (UART_SCLK_PIN) */ + } + + if (0u != (UART_UART_RTS_PIN_ENABLE & uartEnableMask)) + { + /* RTS output is multiplexed with SS0 */ + #if (UART_SS0_PIN) + hsiomSel[UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_UART; + pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= UART_SS0_PIN_MASK; + #endif /* (UART_SS0_PIN) */ + } + } + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + } + } + #endif /* (!UART_CY_SCBIP_V1) */ + + /* Configure pins: set HSIOM, DM and InputBufEnable */ + /* Note: the DR register settings do not effect the pin output if HSIOM is other than GPIO */ + + #if (UART_RX_SCL_MOSI_PIN) + UART_SET_HSIOM_SEL(UART_RX_SCL_MOSI_HSIOM_REG, + UART_RX_SCL_MOSI_HSIOM_MASK, + UART_RX_SCL_MOSI_HSIOM_POS, + hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX]); + + UART_uart_rx_i2c_scl_spi_mosi_SetDriveMode((uint8) pinsDm[UART_RX_SCL_MOSI_PIN_INDEX]); + + #if (!UART_CY_SCBIP_V1) + UART_SET_INP_DIS(UART_uart_rx_i2c_scl_spi_mosi_INP_DIS, + UART_uart_rx_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & UART_RX_SCL_MOSI_PIN_MASK))); + #endif /* (!UART_CY_SCBIP_V1) */ + + #elif (UART_RX_WAKE_SCL_MOSI_PIN) + UART_SET_HSIOM_SEL(UART_RX_WAKE_SCL_MOSI_HSIOM_REG, + UART_RX_WAKE_SCL_MOSI_HSIOM_MASK, + UART_RX_WAKE_SCL_MOSI_HSIOM_POS, + hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + UART_uart_rx_wake_i2c_scl_spi_mosi_SetDriveMode((uint8) + pinsDm[UART_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + UART_SET_INP_DIS(UART_uart_rx_wake_i2c_scl_spi_mosi_INP_DIS, + UART_uart_rx_wake_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & UART_RX_WAKE_SCL_MOSI_PIN_MASK))); + + /* Set interrupt on falling edge */ + UART_SET_INCFG_TYPE(UART_RX_WAKE_SCL_MOSI_INTCFG_REG, + UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_MASK, + UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_POS, + UART_INTCFG_TYPE_FALLING_EDGE); + #else + #endif /* (UART_RX_WAKE_SCL_MOSI_PIN) */ + + #if (UART_TX_SDA_MISO_PIN) + UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, + UART_TX_SDA_MISO_HSIOM_MASK, + UART_TX_SDA_MISO_HSIOM_POS, + hsiomSel[UART_TX_SDA_MISO_PIN_INDEX]); + + UART_uart_tx_i2c_sda_spi_miso_SetDriveMode((uint8) pinsDm[UART_TX_SDA_MISO_PIN_INDEX]); + + #if (!UART_CY_SCBIP_V1) + UART_SET_INP_DIS(UART_uart_tx_i2c_sda_spi_miso_INP_DIS, + UART_uart_tx_i2c_sda_spi_miso_MASK, + (0u != (pinsInBuf & UART_TX_SDA_MISO_PIN_MASK))); + #endif /* (!UART_CY_SCBIP_V1) */ + #endif /* (UART_RX_SCL_MOSI_PIN) */ + + #if (UART_SCLK_PIN) + UART_SET_HSIOM_SEL(UART_SCLK_HSIOM_REG, + UART_SCLK_HSIOM_MASK, + UART_SCLK_HSIOM_POS, + hsiomSel[UART_SCLK_PIN_INDEX]); + + UART_spi_sclk_SetDriveMode((uint8) pinsDm[UART_SCLK_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_sclk_INP_DIS, + UART_spi_sclk_MASK, + (0u != (pinsInBuf & UART_SCLK_PIN_MASK))); + #endif /* (UART_SCLK_PIN) */ + + #if (UART_SS0_PIN) + UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, + UART_SS0_HSIOM_MASK, + UART_SS0_HSIOM_POS, + hsiomSel[UART_SS0_PIN_INDEX]); + + UART_spi_ss0_SetDriveMode((uint8) pinsDm[UART_SS0_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss0_INP_DIS, + UART_spi_ss0_MASK, + (0u != (pinsInBuf & UART_SS0_PIN_MASK))); + #endif /* (UART_SS0_PIN) */ + + #if (UART_SS1_PIN) + UART_SET_HSIOM_SEL(UART_SS1_HSIOM_REG, + UART_SS1_HSIOM_MASK, + UART_SS1_HSIOM_POS, + hsiomSel[UART_SS1_PIN_INDEX]); + + UART_spi_ss1_SetDriveMode((uint8) pinsDm[UART_SS1_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss1_INP_DIS, + UART_spi_ss1_MASK, + (0u != (pinsInBuf & UART_SS1_PIN_MASK))); + #endif /* (UART_SS1_PIN) */ + + #if (UART_SS2_PIN) + UART_SET_HSIOM_SEL(UART_SS2_HSIOM_REG, + UART_SS2_HSIOM_MASK, + UART_SS2_HSIOM_POS, + hsiomSel[UART_SS2_PIN_INDEX]); + + UART_spi_ss2_SetDriveMode((uint8) pinsDm[UART_SS2_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss2_INP_DIS, + UART_spi_ss2_MASK, + (0u != (pinsInBuf & UART_SS2_PIN_MASK))); + #endif /* (UART_SS2_PIN) */ + + #if (UART_SS3_PIN) + UART_SET_HSIOM_SEL(UART_SS3_HSIOM_REG, + UART_SS3_HSIOM_MASK, + UART_SS3_HSIOM_POS, + hsiomSel[UART_SS3_PIN_INDEX]); + + UART_spi_ss3_SetDriveMode((uint8) pinsDm[UART_SS3_PIN_INDEX]); + + UART_SET_INP_DIS(UART_spi_ss3_INP_DIS, + UART_spi_ss3_MASK, + (0u != (pinsInBuf & UART_SS3_PIN_MASK))); + #endif /* (UART_SS3_PIN) */ + } + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UART_I2CSlaveNackGeneration + ****************************************************************************//** + * + * Sets command to generate NACK to the address or data. + * + *******************************************************************************/ + void UART_I2CSlaveNackGeneration(void) + { + /* Check for EC_AM toggle condition: EC_AM and clock stretching for address are enabled */ + if ((0u != (UART_CTRL_REG & UART_CTRL_EC_AM_MODE)) && + (0u == (UART_I2C_CTRL_REG & UART_I2C_CTRL_S_NOT_READY_ADDR_NACK))) + { + /* Toggle EC_AM before NACK generation */ + UART_CTRL_REG &= ~UART_CTRL_EC_AM_MODE; + UART_CTRL_REG |= UART_CTRL_EC_AM_MODE; + } + + UART_I2C_SLAVE_CMD_REG = UART_I2C_SLAVE_CMD_S_NACK; + } +#endif /* (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART.h new file mode 100644 index 0000000..ae88815 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART.h @@ -0,0 +1,2126 @@ +/***************************************************************************//** +* \file UART.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_UART_H) +#define CY_SCB_UART_H + +#include +#include +#include +#include + +/* SCB IP block v0 is available in PSoC 4100/PSoC 4200 */ +#define UART_CY_SCBIP_V0 (CYIPBLOCK_m0s8scb_VERSION == 0u) +/* SCB IP block v1 is available in PSoC 4000 */ +#define UART_CY_SCBIP_V1 (CYIPBLOCK_m0s8scb_VERSION == 1u) +/* SCB IP block v2 is available in all other devices */ +#define UART_CY_SCBIP_V2 (CYIPBLOCK_m0s8scb_VERSION >= 2u) + +/** Component version major.minor */ +#define UART_COMP_VERSION_MAJOR (4) +#define UART_COMP_VERSION_MINOR (0) + +#define UART_SCB_MODE (4u) + +/* SCB modes enum */ +#define UART_SCB_MODE_I2C (0x01u) +#define UART_SCB_MODE_SPI (0x02u) +#define UART_SCB_MODE_UART (0x04u) +#define UART_SCB_MODE_EZI2C (0x08u) +#define UART_SCB_MODE_UNCONFIG (0xFFu) + +/* Condition compilation depends on operation mode: Unconfigured implies apply to all modes */ +#define UART_SCB_MODE_I2C_CONST_CFG (UART_SCB_MODE_I2C == UART_SCB_MODE) +#define UART_SCB_MODE_SPI_CONST_CFG (UART_SCB_MODE_SPI == UART_SCB_MODE) +#define UART_SCB_MODE_UART_CONST_CFG (UART_SCB_MODE_UART == UART_SCB_MODE) +#define UART_SCB_MODE_EZI2C_CONST_CFG (UART_SCB_MODE_EZI2C == UART_SCB_MODE) +#define UART_SCB_MODE_UNCONFIG_CONST_CFG (UART_SCB_MODE_UNCONFIG == UART_SCB_MODE) + +/* Condition compilation for includes */ +#define UART_SCB_MODE_I2C_INC (0u !=(UART_SCB_MODE_I2C & UART_SCB_MODE)) +#define UART_SCB_MODE_EZI2C_INC (0u !=(UART_SCB_MODE_EZI2C & UART_SCB_MODE)) +#if (!UART_CY_SCBIP_V1) + #define UART_SCB_MODE_SPI_INC (0u !=(UART_SCB_MODE_SPI & UART_SCB_MODE)) + #define UART_SCB_MODE_UART_INC (0u !=(UART_SCB_MODE_UART & UART_SCB_MODE)) +#else + #define UART_SCB_MODE_SPI_INC (0u) + #define UART_SCB_MODE_UART_INC (0u) +#endif /* (!UART_CY_SCBIP_V1) */ + +/* Interrupts remove options */ +#define UART_REMOVE_SCB_IRQ (1u) +#define UART_SCB_IRQ_INTERNAL (0u == UART_REMOVE_SCB_IRQ) + +#define UART_REMOVE_UART_RX_WAKEUP_IRQ (1u) +#define UART_UART_RX_WAKEUP_IRQ (0u == UART_REMOVE_UART_RX_WAKEUP_IRQ) + +/* SCB interrupt enum */ +#define UART_SCB_INTR_MODE_NONE (0u) +#define UART_SCB_INTR_MODE_INTERNAL (1u) +#define UART_SCB_INTR_MODE_EXTERNAL (2u) + +/* Internal clock remove option */ +#define UART_REMOVE_SCB_CLK (0u) +#define UART_SCB_CLK_INTERNAL (0u == UART_REMOVE_SCB_CLK) + + +/*************************************** +* Includes +****************************************/ + +#include "UART_PINS.h" + +#if (UART_SCB_CLK_INTERNAL) + #include "UART_SCBCLK.h" +#endif /* (UART_SCB_CLK_INTERNAL) */ + + +/*************************************** +* Type Definitions +***************************************/ + +typedef struct +{ + uint8 enableState; +} UART_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ + +/* Start and Stop APIs */ +void UART_Init(void); +void UART_Enable(void); +void UART_Start(void); +void UART_Stop(void); + +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +/* Sleep and Wakeup APis */ +void UART_Sleep(void); +void UART_Wakeup(void); +/** @} power */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +#if (UART_SCB_IRQ_INTERNAL) + /* Custom interrupt handler */ + void UART_SetCustomInterruptHandler(void (*func)(void)); +#endif /* (UART_SCB_IRQ_INTERNAL) */ +/** @} interrupt */ + +/* Interface to internal interrupt component */ +#if (UART_SCB_IRQ_INTERNAL) + /** + * \addtogroup group_interrupt + * @{ + */ + /******************************************************************************* + * Function Name: UART_EnableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this enables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to enable the interrupt. + * + *******************************************************************************/ + #define UART_EnableInt() CyIntEnable(UART_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_DisableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this disables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to disable the interrupt. + * + *******************************************************************************/ + #define UART_DisableInt() CyIntDisable(UART_ISR_NUMBER) + /** @} interrupt */ + + /******************************************************************************* + * Function Name: UART_ClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt pending status in the NVIC. + * + *******************************************************************************/ + #define UART_ClearPendingInt() CyIntClearPending(UART_ISR_NUMBER) +#endif /* (UART_SCB_IRQ_INTERNAL) */ + +#if (UART_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: UART_RxWakeEnableInt + ****************************************************************************//** + * + * This function enables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_RxWakeEnableInt() CyIntEnable(UART_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_RxWakeDisableInt + ****************************************************************************//** + * + * This function disables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_RxWakeDisableInt() CyIntDisable(UART_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_RxWakeClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_RxWakeClearPendingInt() CyIntClearPending(UART_RX_WAKE_ISR_NUMBER) +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +/* Get interrupt cause */ +/******************************************************************************* +* Function Name: UART_GetInterruptCause +****************************************************************************//** +* +* Returns a mask of bits showing the source of the current triggered interrupt. +* This is useful for modes of operation where an interrupt can be generated by +* conditions in multiple interrupt source registers. +* +* \return +* Mask with the OR of the following conditions that have been triggered. +* - UART_INTR_CAUSE_MASTER - Interrupt from Master +* - UART_INTR_CAUSE_SLAVE - Interrupt from Slave +* - UART_INTR_CAUSE_TX - Interrupt from TX +* - UART_INTR_CAUSE_RX - Interrupt from RX +* +*******************************************************************************/ +#define UART_GetInterruptCause() (UART_INTR_CAUSE_REG) + + +/* APIs to service INTR_RX register */ +/******************************************************************************* +* Function Name: UART_GetRxInterruptSource +****************************************************************************//** +* +* Returns RX interrupt request register. This register contains current status +* of RX interrupt sources. +* +* \return +* Current status of RX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_RX_FIFO_LEVEL - The number of data elements in the + RX FIFO is greater than the value of RX FIFO level. +* - UART_INTR_RX_NOT_EMPTY - Receiver FIFO is not empty. +* - UART_INTR_RX_FULL - Receiver FIFO is full. +* - UART_INTR_RX_OVERFLOW - Attempt to write to a full +* receiver FIFO. +* - UART_INTR_RX_UNDERFLOW - Attempt to read from an empty +* receiver FIFO. +* - UART_INTR_RX_FRAME_ERROR - UART framing error detected. +* - UART_INTR_RX_PARITY_ERROR - UART parity error detected. +* +*******************************************************************************/ +#define UART_GetRxInterruptSource() (UART_INTR_RX_REG) + + +/******************************************************************************* +* Function Name: UART_SetRxInterruptMode +****************************************************************************//** +* +* Writes RX interrupt mask register. This register configures which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: RX interrupt sources to be enabled (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_SetRxInterruptMode(interruptMask) UART_WRITE_INTR_RX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: UART_GetRxInterruptMode +****************************************************************************//** +* +* Returns RX interrupt mask register This register specifies which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \return +* RX interrupt sources to be enabled (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_GetRxInterruptMode() (UART_INTR_RX_MASK_REG) + + +/******************************************************************************* +* Function Name: UART_GetRxInterruptSourceMasked +****************************************************************************//** +* +* Returns RX interrupt masked request register. This register contains logical +* AND of corresponding bits from RX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled RX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled RX interrupt sources (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_GetRxInterruptSourceMasked() (UART_INTR_RX_MASKED_REG) + + +/******************************************************************************* +* Function Name: UART_ClearRxInterruptSource +****************************************************************************//** +* +* Clears RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to be cleared (refer to +* UART_GetRxInterruptSource() function for bit fields values). +* +* \sideeffects +* The side effects are listed in the table below for each +* affected interrupt source. Refer to section RX FIFO interrupt sources for +* detailed description. +* - UART_INTR_RX_FIFO_LEVEL Interrupt source is not cleared when +* the receiver FIFO has more entries than level. +* - UART_INTR_RX_NOT_EMPTY Interrupt source is not cleared when +* receiver FIFO is not empty. +* - UART_INTR_RX_FULL Interrupt source is not cleared when +* receiver FIFO is full. +* +*******************************************************************************/ +#define UART_ClearRxInterruptSource(interruptMask) UART_CLEAR_INTR_RX(interruptMask) + + +/******************************************************************************* +* Function Name: UART_SetRxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to UART_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define UART_SetRxInterrupt(interruptMask) UART_SET_INTR_RX(interruptMask) + +void UART_SetRxFifoLevel(uint32 level); + + +/* APIs to service INTR_TX register */ +/******************************************************************************* +* Function Name: UART_GetTxInterruptSource +****************************************************************************//** +* +* Returns TX interrupt request register. This register contains current status +* of TX interrupt sources. +* +* \return +* Current status of TX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_TX_FIFO_LEVEL - The number of data elements in the +* TX FIFO is less than the value of TX FIFO level. +* - UART_INTR_TX_NOT_FULL - Transmitter FIFO is not full. +* - UART_INTR_TX_EMPTY - Transmitter FIFO is empty. +* - UART_INTR_TX_OVERFLOW - Attempt to write to a full +* transmitter FIFO. +* - UART_INTR_TX_UNDERFLOW - Attempt to read from an empty +* transmitter FIFO. +* - UART_INTR_TX_UART_NACK - UART received a NACK in SmartCard +* mode. +* - UART_INTR_TX_UART_DONE - UART transfer is complete. +* All data elements from the TX FIFO are sent. +* - UART_INTR_TX_UART_ARB_LOST - Value on the TX line of the UART +* does not match the value on the RX line. +* +*******************************************************************************/ +#define UART_GetTxInterruptSource() (UART_INTR_TX_REG) + + +/******************************************************************************* +* Function Name: UART_SetTxInterruptMode +****************************************************************************//** +* +* Writes TX interrupt mask register. This register configures which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: TX interrupt sources to be enabled (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_SetTxInterruptMode(interruptMask) UART_WRITE_INTR_TX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: UART_GetTxInterruptMode +****************************************************************************//** +* +* Returns TX interrupt mask register This register specifies which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \return +* Enabled TX interrupt sources (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_GetTxInterruptMode() (UART_INTR_TX_MASK_REG) + + +/******************************************************************************* +* Function Name: UART_GetTxInterruptSourceMasked +****************************************************************************//** +* +* Returns TX interrupt masked request register. This register contains logical +* AND of corresponding bits from TX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to identify +* which of enabled TX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled TX interrupt sources (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_GetTxInterruptSourceMasked() (UART_INTR_TX_MASKED_REG) + + +/******************************************************************************* +* Function Name: UART_ClearTxInterruptSource +****************************************************************************//** +* +* Clears TX interrupt sources in the interrupt request register. +* +* \param interruptMask: TX interrupt sources to be cleared (refer to +* UART_GetTxInterruptSource() function for bit field values). +* +* \sideeffects +* The side effects are listed in the table below for each affected interrupt +* source. Refer to section TX FIFO interrupt sources for detailed description. +* - UART_INTR_TX_FIFO_LEVEL - Interrupt source is not cleared when +* transmitter FIFO has less entries than level. +* - UART_INTR_TX_NOT_FULL - Interrupt source is not cleared when +* transmitter FIFO has empty entries. +* - UART_INTR_TX_EMPTY - Interrupt source is not cleared when +* transmitter FIFO is empty. +* - UART_INTR_TX_UNDERFLOW - Interrupt source is not cleared when +* transmitter FIFO is empty and I2C mode with clock stretching is selected. +* Put data into the transmitter FIFO before clearing it. This behavior only +* applicable for PSoC 4100/PSoC 4200 devices. +* +*******************************************************************************/ +#define UART_ClearTxInterruptSource(interruptMask) UART_CLEAR_INTR_TX(interruptMask) + + +/******************************************************************************* +* Function Name: UART_SetTxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to UART_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define UART_SetTxInterrupt(interruptMask) UART_SET_INTR_TX(interruptMask) + +void UART_SetTxFifoLevel(uint32 level); + + +/* APIs to service INTR_MASTER register */ +/******************************************************************************* +* Function Name: UART_GetMasterInterruptSource +****************************************************************************//** +* +* Returns Master interrupt request register. This register contains current +* status of Master interrupt sources. +* +* \return +* Current status of Master interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_MASTER_SPI_DONE - SPI master transfer is complete. +* Refer to Interrupt sources section for detailed description. +* - UART_INTR_MASTER_I2C_ARB_LOST - I2C master lost arbitration. +* - UART_INTR_MASTER_I2C_NACK - I2C master received negative +* acknowledgement (NAK). +* - UART_INTR_MASTER_I2C_ACK - I2C master received acknowledgement. +* - UART_INTR_MASTER_I2C_STOP - I2C master generated STOP. +* - UART_INTR_MASTER_I2C_BUS_ERROR - I2C master bus error +* (detection of unexpected START or STOP condition). +* +*******************************************************************************/ +#define UART_GetMasterInterruptSource() (UART_INTR_MASTER_REG) + +/******************************************************************************* +* Function Name: UART_SetMasterInterruptMode +****************************************************************************//** +* +* Writes Master interrupt mask register. This register configures which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \param interruptMask: Master interrupt sources to be enabled (refer to +* UART_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_SetMasterInterruptMode(interruptMask) UART_WRITE_INTR_MASTER_MASK(interruptMask) + +/******************************************************************************* +* Function Name: UART_GetMasterInterruptMode +****************************************************************************//** +* +* Returns Master interrupt mask register This register specifies which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \return +* Enabled Master interrupt sources (refer to +* UART_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_GetMasterInterruptMode() (UART_INTR_MASTER_MASK_REG) + +/******************************************************************************* +* Function Name: UART_GetMasterInterruptSourceMasked +****************************************************************************//** +* +* Returns Master interrupt masked request register. This register contains +* logical AND of corresponding bits from Master interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Master interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Master interrupt sources (refer to +* UART_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_GetMasterInterruptSourceMasked() (UART_INTR_MASTER_MASKED_REG) + +/******************************************************************************* +* Function Name: UART_ClearMasterInterruptSource +****************************************************************************//** +* +* Clears Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to be cleared (refer to +* UART_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_ClearMasterInterruptSource(interruptMask) UART_CLEAR_INTR_MASTER(interruptMask) + +/******************************************************************************* +* Function Name: UART_SetMasterInterrupt +****************************************************************************//** +* +* Sets Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to set in the Master interrupt +* request register (refer to UART_GetMasterInterruptSource() +* function for bit field values). +* +*******************************************************************************/ +#define UART_SetMasterInterrupt(interruptMask) UART_SET_INTR_MASTER(interruptMask) + + +/* APIs to service INTR_SLAVE register */ +/******************************************************************************* +* Function Name: UART_GetSlaveInterruptSource +****************************************************************************//** +* +* Returns Slave interrupt request register. This register contains current +* status of Slave interrupt sources. +* +* \return +* Current status of Slave interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_INTR_SLAVE_I2C_ARB_LOST - I2C slave lost arbitration: +* the value driven on the SDA line is not the same as the value observed +* on the SDA line. +* - UART_INTR_SLAVE_I2C_NACK - I2C slave received negative +* acknowledgement (NAK). +* - UART_INTR_SLAVE_I2C_ACK - I2C slave received +* acknowledgement (ACK). +* - UART_INTR_SLAVE_I2C_WRITE_STOP - Stop or Repeated Start +* event for write transfer intended for this slave (address matching +* is performed). +* - UART_INTR_SLAVE_I2C_STOP - Stop or Repeated Start event +* for (read or write) transfer intended for this slave (address matching +* is performed). +* - UART_INTR_SLAVE_I2C_START - I2C slave received Start +* condition. +* - UART_INTR_SLAVE_I2C_ADDR_MATCH - I2C slave received matching +* address. +* - UART_INTR_SLAVE_I2C_GENERAL - I2C Slave received general +* call address. +* - UART_INTR_SLAVE_I2C_BUS_ERROR - I2C slave bus error (detection +* of unexpected Start or Stop condition). +* - UART_INTR_SLAVE_SPI_BUS_ERROR - SPI slave select line is +* deselected at an expected time while the SPI transfer. +* +*******************************************************************************/ +#define UART_GetSlaveInterruptSource() (UART_INTR_SLAVE_REG) + +/******************************************************************************* +* Function Name: UART_SetSlaveInterruptMode +****************************************************************************//** +* +* Writes Slave interrupt mask register. +* This register configures which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \param interruptMask: Slave interrupt sources to be enabled (refer to +* UART_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_SetSlaveInterruptMode(interruptMask) UART_WRITE_INTR_SLAVE_MASK(interruptMask) + +/******************************************************************************* +* Function Name: UART_GetSlaveInterruptMode +****************************************************************************//** +* +* Returns Slave interrupt mask register. +* This register specifies which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \return +* Enabled Slave interrupt sources(refer to +* UART_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_GetSlaveInterruptMode() (UART_INTR_SLAVE_MASK_REG) + +/******************************************************************************* +* Function Name: UART_GetSlaveInterruptSourceMasked +****************************************************************************//** +* +* Returns Slave interrupt masked request register. This register contains +* logical AND of corresponding bits from Slave interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Slave interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Slave interrupt sources (refer to +* UART_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_GetSlaveInterruptSourceMasked() (UART_INTR_SLAVE_MASKED_REG) + +/******************************************************************************* +* Function Name: UART_ClearSlaveInterruptSource +****************************************************************************//** +* +* Clears Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to be cleared (refer to +* UART_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_ClearSlaveInterruptSource(interruptMask) UART_CLEAR_INTR_SLAVE(interruptMask) + +/******************************************************************************* +* Function Name: UART_SetSlaveInterrupt +****************************************************************************//** +* +* Sets Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to set in the Slave interrupt +* request register (refer to UART_GetSlaveInterruptSource() +* function for return values). +* +*******************************************************************************/ +#define UART_SetSlaveInterrupt(interruptMask) UART_SET_INTR_SLAVE(interruptMask) + +/** @} interrupt */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +/** +* \addtogroup group_globals +* @{ +*/ + +/** UART_initVar indicates whether the UART +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the UART_Start() routine. +* +* If re-initialization of the component is required, then the +* UART_Init() function can be called before the +* UART_Start() or UART_Enable() function. +*/ +extern uint8 UART_initVar; +/** @} globals */ + +/*************************************** +* Registers +***************************************/ + +#define UART_CTRL_REG (*(reg32 *) UART_SCB__CTRL) +#define UART_CTRL_PTR ( (reg32 *) UART_SCB__CTRL) + +#define UART_STATUS_REG (*(reg32 *) UART_SCB__STATUS) +#define UART_STATUS_PTR ( (reg32 *) UART_SCB__STATUS) + +#if (!UART_CY_SCBIP_V1) + #define UART_SPI_CTRL_REG (*(reg32 *) UART_SCB__SPI_CTRL) + #define UART_SPI_CTRL_PTR ( (reg32 *) UART_SCB__SPI_CTRL) + + #define UART_SPI_STATUS_REG (*(reg32 *) UART_SCB__SPI_STATUS) + #define UART_SPI_STATUS_PTR ( (reg32 *) UART_SCB__SPI_STATUS) + + #define UART_UART_CTRL_REG (*(reg32 *) UART_SCB__UART_CTRL) + #define UART_UART_CTRL_PTR ( (reg32 *) UART_SCB__UART_CTRL) + + #define UART_UART_TX_CTRL_REG (*(reg32 *) UART_SCB__UART_TX_CTRL) + #define UART_UART_TX_CTRL_PTR ( (reg32 *) UART_SCB__UART_TX_CTRL) + + #define UART_UART_RX_CTRL_REG (*(reg32 *) UART_SCB__UART_RX_CTRL) + #define UART_UART_RX_CTRL_PTR ( (reg32 *) UART_SCB__UART_RX_CTRL) + + #define UART_UART_RX_STATUS_REG (*(reg32 *) UART_SCB__UART_RX_STATUS) + #define UART_UART_RX_STATUS_PTR ( (reg32 *) UART_SCB__UART_RX_STATUS) +#endif /* (!UART_CY_SCBIP_V1) */ + +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_UART_FLOW_CTRL_REG (*(reg32 *) UART_SCB__UART_FLOW_CTRL) + #define UART_UART_FLOW_CTRL_PTR ( (reg32 *) UART_SCB__UART_FLOW_CTRL) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#define UART_I2C_CTRL_REG (*(reg32 *) UART_SCB__I2C_CTRL) +#define UART_I2C_CTRL_PTR ( (reg32 *) UART_SCB__I2C_CTRL) + +#define UART_I2C_STATUS_REG (*(reg32 *) UART_SCB__I2C_STATUS) +#define UART_I2C_STATUS_PTR ( (reg32 *) UART_SCB__I2C_STATUS) + +#define UART_I2C_MASTER_CMD_REG (*(reg32 *) UART_SCB__I2C_M_CMD) +#define UART_I2C_MASTER_CMD_PTR ( (reg32 *) UART_SCB__I2C_M_CMD) + +#define UART_I2C_SLAVE_CMD_REG (*(reg32 *) UART_SCB__I2C_S_CMD) +#define UART_I2C_SLAVE_CMD_PTR ( (reg32 *) UART_SCB__I2C_S_CMD) + +#define UART_I2C_CFG_REG (*(reg32 *) UART_SCB__I2C_CFG) +#define UART_I2C_CFG_PTR ( (reg32 *) UART_SCB__I2C_CFG) + +#define UART_TX_CTRL_REG (*(reg32 *) UART_SCB__TX_CTRL) +#define UART_TX_CTRL_PTR ( (reg32 *) UART_SCB__TX_CTRL) + +#define UART_TX_FIFO_CTRL_REG (*(reg32 *) UART_SCB__TX_FIFO_CTRL) +#define UART_TX_FIFO_CTRL_PTR ( (reg32 *) UART_SCB__TX_FIFO_CTRL) + +#define UART_TX_FIFO_STATUS_REG (*(reg32 *) UART_SCB__TX_FIFO_STATUS) +#define UART_TX_FIFO_STATUS_PTR ( (reg32 *) UART_SCB__TX_FIFO_STATUS) + +#define UART_TX_FIFO_WR_REG (*(reg32 *) UART_SCB__TX_FIFO_WR) +#define UART_TX_FIFO_WR_PTR ( (reg32 *) UART_SCB__TX_FIFO_WR) + +#define UART_RX_CTRL_REG (*(reg32 *) UART_SCB__RX_CTRL) +#define UART_RX_CTRL_PTR ( (reg32 *) UART_SCB__RX_CTRL) + +#define UART_RX_FIFO_CTRL_REG (*(reg32 *) UART_SCB__RX_FIFO_CTRL) +#define UART_RX_FIFO_CTRL_PTR ( (reg32 *) UART_SCB__RX_FIFO_CTRL) + +#define UART_RX_FIFO_STATUS_REG (*(reg32 *) UART_SCB__RX_FIFO_STATUS) +#define UART_RX_FIFO_STATUS_PTR ( (reg32 *) UART_SCB__RX_FIFO_STATUS) + +#define UART_RX_MATCH_REG (*(reg32 *) UART_SCB__RX_MATCH) +#define UART_RX_MATCH_PTR ( (reg32 *) UART_SCB__RX_MATCH) + +#define UART_RX_FIFO_RD_REG (*(reg32 *) UART_SCB__RX_FIFO_RD) +#define UART_RX_FIFO_RD_PTR ( (reg32 *) UART_SCB__RX_FIFO_RD) + +#define UART_RX_FIFO_RD_SILENT_REG (*(reg32 *) UART_SCB__RX_FIFO_RD_SILENT) +#define UART_RX_FIFO_RD_SILENT_PTR ( (reg32 *) UART_SCB__RX_FIFO_RD_SILENT) + +#ifdef UART_SCB__EZ_DATA0 + #define UART_EZBUF_DATA0_REG (*(reg32 *) UART_SCB__EZ_DATA0) + #define UART_EZBUF_DATA0_PTR ( (reg32 *) UART_SCB__EZ_DATA0) +#else + #define UART_EZBUF_DATA0_REG (*(reg32 *) UART_SCB__EZ_DATA00) + #define UART_EZBUF_DATA0_PTR ( (reg32 *) UART_SCB__EZ_DATA00) +#endif /* UART_SCB__EZ_DATA00 */ + +#define UART_INTR_CAUSE_REG (*(reg32 *) UART_SCB__INTR_CAUSE) +#define UART_INTR_CAUSE_PTR ( (reg32 *) UART_SCB__INTR_CAUSE) + +#define UART_INTR_I2C_EC_REG (*(reg32 *) UART_SCB__INTR_I2C_EC) +#define UART_INTR_I2C_EC_PTR ( (reg32 *) UART_SCB__INTR_I2C_EC) + +#define UART_INTR_I2C_EC_MASK_REG (*(reg32 *) UART_SCB__INTR_I2C_EC_MASK) +#define UART_INTR_I2C_EC_MASK_PTR ( (reg32 *) UART_SCB__INTR_I2C_EC_MASK) + +#define UART_INTR_I2C_EC_MASKED_REG (*(reg32 *) UART_SCB__INTR_I2C_EC_MASKED) +#define UART_INTR_I2C_EC_MASKED_PTR ( (reg32 *) UART_SCB__INTR_I2C_EC_MASKED) + +#if (!UART_CY_SCBIP_V1) + #define UART_INTR_SPI_EC_REG (*(reg32 *) UART_SCB__INTR_SPI_EC) + #define UART_INTR_SPI_EC_PTR ( (reg32 *) UART_SCB__INTR_SPI_EC) + + #define UART_INTR_SPI_EC_MASK_REG (*(reg32 *) UART_SCB__INTR_SPI_EC_MASK) + #define UART_INTR_SPI_EC_MASK_PTR ( (reg32 *) UART_SCB__INTR_SPI_EC_MASK) + + #define UART_INTR_SPI_EC_MASKED_REG (*(reg32 *) UART_SCB__INTR_SPI_EC_MASKED) + #define UART_INTR_SPI_EC_MASKED_PTR ( (reg32 *) UART_SCB__INTR_SPI_EC_MASKED) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_INTR_MASTER_REG (*(reg32 *) UART_SCB__INTR_M) +#define UART_INTR_MASTER_PTR ( (reg32 *) UART_SCB__INTR_M) + +#define UART_INTR_MASTER_SET_REG (*(reg32 *) UART_SCB__INTR_M_SET) +#define UART_INTR_MASTER_SET_PTR ( (reg32 *) UART_SCB__INTR_M_SET) + +#define UART_INTR_MASTER_MASK_REG (*(reg32 *) UART_SCB__INTR_M_MASK) +#define UART_INTR_MASTER_MASK_PTR ( (reg32 *) UART_SCB__INTR_M_MASK) + +#define UART_INTR_MASTER_MASKED_REG (*(reg32 *) UART_SCB__INTR_M_MASKED) +#define UART_INTR_MASTER_MASKED_PTR ( (reg32 *) UART_SCB__INTR_M_MASKED) + +#define UART_INTR_SLAVE_REG (*(reg32 *) UART_SCB__INTR_S) +#define UART_INTR_SLAVE_PTR ( (reg32 *) UART_SCB__INTR_S) + +#define UART_INTR_SLAVE_SET_REG (*(reg32 *) UART_SCB__INTR_S_SET) +#define UART_INTR_SLAVE_SET_PTR ( (reg32 *) UART_SCB__INTR_S_SET) + +#define UART_INTR_SLAVE_MASK_REG (*(reg32 *) UART_SCB__INTR_S_MASK) +#define UART_INTR_SLAVE_MASK_PTR ( (reg32 *) UART_SCB__INTR_S_MASK) + +#define UART_INTR_SLAVE_MASKED_REG (*(reg32 *) UART_SCB__INTR_S_MASKED) +#define UART_INTR_SLAVE_MASKED_PTR ( (reg32 *) UART_SCB__INTR_S_MASKED) + +#define UART_INTR_TX_REG (*(reg32 *) UART_SCB__INTR_TX) +#define UART_INTR_TX_PTR ( (reg32 *) UART_SCB__INTR_TX) + +#define UART_INTR_TX_SET_REG (*(reg32 *) UART_SCB__INTR_TX_SET) +#define UART_INTR_TX_SET_PTR ( (reg32 *) UART_SCB__INTR_TX_SET) + +#define UART_INTR_TX_MASK_REG (*(reg32 *) UART_SCB__INTR_TX_MASK) +#define UART_INTR_TX_MASK_PTR ( (reg32 *) UART_SCB__INTR_TX_MASK) + +#define UART_INTR_TX_MASKED_REG (*(reg32 *) UART_SCB__INTR_TX_MASKED) +#define UART_INTR_TX_MASKED_PTR ( (reg32 *) UART_SCB__INTR_TX_MASKED) + +#define UART_INTR_RX_REG (*(reg32 *) UART_SCB__INTR_RX) +#define UART_INTR_RX_PTR ( (reg32 *) UART_SCB__INTR_RX) + +#define UART_INTR_RX_SET_REG (*(reg32 *) UART_SCB__INTR_RX_SET) +#define UART_INTR_RX_SET_PTR ( (reg32 *) UART_SCB__INTR_RX_SET) + +#define UART_INTR_RX_MASK_REG (*(reg32 *) UART_SCB__INTR_RX_MASK) +#define UART_INTR_RX_MASK_PTR ( (reg32 *) UART_SCB__INTR_RX_MASK) + +#define UART_INTR_RX_MASKED_REG (*(reg32 *) UART_SCB__INTR_RX_MASKED) +#define UART_INTR_RX_MASKED_PTR ( (reg32 *) UART_SCB__INTR_RX_MASKED) + +/* Defines get from SCB IP parameters. */ +#define UART_FIFO_SIZE (8u) /* TX or RX FIFO size. */ +#define UART_EZ_DATA_NR (32u) /* Number of words in EZ memory. */ +#define UART_ONE_BYTE_WIDTH (8u) /* Number of bits in one byte. */ +#define UART_FF_DATA_NR_LOG2_MASK (0x07u) /* Number of bits to represent a FIFO address. */ +#define UART_FF_DATA_NR_LOG2_PLUS1_MASK (0x0Fu) /* Number of bits to represent #bytes in FIFO. */ + + +/*************************************** +* Registers Constants +***************************************/ + +#if (UART_SCB_IRQ_INTERNAL) + #define UART_ISR_NUMBER ((uint8) UART_SCB_IRQ__INTC_NUMBER) + #define UART_ISR_PRIORITY ((uint8) UART_SCB_IRQ__INTC_PRIOR_NUM) +#endif /* (UART_SCB_IRQ_INTERNAL) */ + +#if (UART_UART_RX_WAKEUP_IRQ) + #define UART_RX_WAKE_ISR_NUMBER ((uint8) UART_RX_WAKEUP_IRQ__INTC_NUMBER) + #define UART_RX_WAKE_ISR_PRIORITY ((uint8) UART_RX_WAKEUP_IRQ__INTC_PRIOR_NUM) +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + +/* UART_CTRL_REG */ +#define UART_CTRL_OVS_POS (0u) /* [3:0] Oversampling factor */ +#define UART_CTRL_EC_AM_MODE_POS (8u) /* [8] Externally clocked address match */ +#define UART_CTRL_EC_OP_MODE_POS (9u) /* [9] Externally clocked operation mode */ +#define UART_CTRL_EZBUF_MODE_POS (10u) /* [10] EZ buffer is enabled */ +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_CTRL_BYTE_MODE_POS (11u) /* [11] Determines the number of bits per FIFO data element */ +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#define UART_CTRL_ADDR_ACCEPT_POS (16u) /* [16] Put matched address in RX FIFO */ +#define UART_CTRL_BLOCK_POS (17u) /* [17] Ext and Int logic to resolve collide */ +#define UART_CTRL_MODE_POS (24u) /* [25:24] Operation mode */ +#define UART_CTRL_ENABLED_POS (31u) /* [31] Enable SCB block */ +#define UART_CTRL_OVS_MASK ((uint32) 0x0Fu) +#define UART_CTRL_EC_AM_MODE ((uint32) 0x01u << UART_CTRL_EC_AM_MODE_POS) +#define UART_CTRL_EC_OP_MODE ((uint32) 0x01u << UART_CTRL_EC_OP_MODE_POS) +#define UART_CTRL_EZBUF_MODE ((uint32) 0x01u << UART_CTRL_EZBUF_MODE_POS) +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_CTRL_BYTE_MODE ((uint32) 0x01u << UART_CTRL_BYTE_MODE_POS) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#define UART_CTRL_ADDR_ACCEPT ((uint32) 0x01u << UART_CTRL_ADDR_ACCEPT_POS) +#define UART_CTRL_BLOCK ((uint32) 0x01u << UART_CTRL_BLOCK_POS) +#define UART_CTRL_MODE_MASK ((uint32) 0x03u << UART_CTRL_MODE_POS) +#define UART_CTRL_MODE_I2C ((uint32) 0x00u) +#define UART_CTRL_MODE_SPI ((uint32) 0x01u << UART_CTRL_MODE_POS) +#define UART_CTRL_MODE_UART ((uint32) 0x02u << UART_CTRL_MODE_POS) +#define UART_CTRL_ENABLED ((uint32) 0x01u << UART_CTRL_ENABLED_POS) + +/* UART_STATUS_REG */ +#define UART_STATUS_EC_BUSY_POS (0u) /* [0] Bus busy. Externally clocked logic access to EZ memory */ +#define UART_STATUS_EC_BUSY ((uint32) 0x0Fu) + +/* UART_SPI_CTRL_REG */ +#define UART_SPI_CTRL_CONTINUOUS_POS (0u) /* [0] Continuous or Separated SPI data transfers */ +#define UART_SPI_CTRL_SELECT_PRECEDE_POS (1u) /* [1] Precedes or coincides start of data frame */ +#define UART_SPI_CTRL_CPHA_POS (2u) /* [2] SCLK phase */ +#define UART_SPI_CTRL_CPOL_POS (3u) /* [3] SCLK polarity */ +#define UART_SPI_CTRL_LATE_MISO_SAMPLE_POS (4u) /* [4] Late MISO sample enabled */ +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_SPI_CTRL_SCLK_CONTINUOUS_POS (5u) /* [5] Enable continuous SCLK generation */ + #define UART_SPI_CTRL_SSEL0_POLARITY_POS (8u) /* [8] SS0 polarity */ + #define UART_SPI_CTRL_SSEL1_POLARITY_POS (9u) /* [9] SS1 polarity */ + #define UART_SPI_CTRL_SSEL2_POLARITY_POS (10u) /* [10] SS2 polarity */ + #define UART_SPI_CTRL_SSEL3_POLARITY_POS (11u) /* [11] SS3 polarity */ +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#define UART_SPI_CTRL_LOOPBACK_POS (16u) /* [16] Local loop-back control enabled */ +#define UART_SPI_CTRL_MODE_POS (24u) /* [25:24] Submode of SPI operation */ +#define UART_SPI_CTRL_SLAVE_SELECT_POS (26u) /* [27:26] Selects SPI SS signal */ +#define UART_SPI_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define UART_SPI_CTRL_CONTINUOUS ((uint32) 0x01u) +#define UART_SPI_CTRL_SELECT_PRECEDE ((uint32) 0x01u << UART_SPI_CTRL_SELECT_PRECEDE_POS) +#define UART_SPI_CTRL_SCLK_MODE_MASK ((uint32) 0x03u << UART_SPI_CTRL_CPHA_POS) +#define UART_SPI_CTRL_CPHA ((uint32) 0x01u << UART_SPI_CTRL_CPHA_POS) +#define UART_SPI_CTRL_CPOL ((uint32) 0x01u << UART_SPI_CTRL_CPOL_POS) +#define UART_SPI_CTRL_LATE_MISO_SAMPLE ((uint32) 0x01u << \ + UART_SPI_CTRL_LATE_MISO_SAMPLE_POS) +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_SPI_CTRL_SCLK_CONTINUOUS ((uint32) 0x01u << UART_SPI_CTRL_SCLK_CONTINUOUS_POS) + #define UART_SPI_CTRL_SSEL0_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL0_POLARITY_POS) + #define UART_SPI_CTRL_SSEL1_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL1_POLARITY_POS) + #define UART_SPI_CTRL_SSEL2_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL2_POLARITY_POS) + #define UART_SPI_CTRL_SSEL3_POLARITY ((uint32) 0x01u << UART_SPI_CTRL_SSEL3_POLARITY_POS) + #define UART_SPI_CTRL_SSEL_POLARITY_MASK ((uint32)0x0Fu << UART_SPI_CTRL_SSEL0_POLARITY_POS) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#define UART_SPI_CTRL_LOOPBACK ((uint32) 0x01u << UART_SPI_CTRL_LOOPBACK_POS) +#define UART_SPI_CTRL_MODE_MASK ((uint32) 0x03u << UART_SPI_CTRL_MODE_POS) +#define UART_SPI_CTRL_MODE_MOTOROLA ((uint32) 0x00u) +#define UART_SPI_CTRL_MODE_TI ((uint32) 0x01u << UART_CTRL_MODE_POS) +#define UART_SPI_CTRL_MODE_NS ((uint32) 0x02u << UART_CTRL_MODE_POS) +#define UART_SPI_CTRL_SLAVE_SELECT_MASK ((uint32) 0x03u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_SLAVE_SELECT0 ((uint32) 0x00u) +#define UART_SPI_CTRL_SLAVE_SELECT1 ((uint32) 0x01u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_SLAVE_SELECT2 ((uint32) 0x02u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_SLAVE_SELECT3 ((uint32) 0x03u << UART_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_SPI_CTRL_MASTER ((uint32) 0x01u << UART_SPI_CTRL_MASTER_MODE_POS) +#define UART_SPI_CTRL_SLAVE ((uint32) 0x00u) + +/* UART_SPI_STATUS_REG */ +#define UART_SPI_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy - slave selected */ +#define UART_SPI_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EzAddress */ +#define UART_SPI_STATUS_BUS_BUSY ((uint32) 0x01u) +#define UART_SPI_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << UART_I2C_STATUS_EZBUF_ADDR_POS) + +/* UART_UART_CTRL */ +#define UART_UART_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define UART_UART_CTRL_MODE_POS (24u) /* [24] UART subMode */ +#define UART_UART_CTRL_LOOPBACK ((uint32) 0x01u << UART_UART_CTRL_LOOPBACK_POS) +#define UART_UART_CTRL_MODE_UART_STD ((uint32) 0x00u) +#define UART_UART_CTRL_MODE_UART_SMARTCARD ((uint32) 0x01u << UART_UART_CTRL_MODE_POS) +#define UART_UART_CTRL_MODE_UART_IRDA ((uint32) 0x02u << UART_UART_CTRL_MODE_POS) +#define UART_UART_CTRL_MODE_MASK ((uint32) 0x03u << UART_UART_CTRL_MODE_POS) + +/* UART_UART_TX_CTRL */ +#define UART_UART_TX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period */ +#define UART_UART_TX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define UART_UART_TX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define UART_UART_TX_CTRL_RETRY_ON_NACK_POS (8u) /* [8] Smart Card: re-send frame on NACK */ +#define UART_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define UART_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define UART_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define UART_UART_TX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define UART_UART_TX_CTRL_PARITY ((uint32) 0x01u << \ + UART_UART_TX_CTRL_PARITY_POS) +#define UART_UART_TX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + UART_UART_TX_CTRL_PARITY_ENABLED_POS) +#define UART_UART_TX_CTRL_RETRY_ON_NACK ((uint32) 0x01u << \ + UART_UART_TX_CTRL_RETRY_ON_NACK_POS) + +/* UART_UART_RX_CTRL */ +#define UART_UART_RX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period*/ +#define UART_UART_RX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define UART_UART_RX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define UART_UART_RX_CTRL_POLARITY_POS (6u) /* [6] IrDA: inverts polarity of RX signal */ +#define UART_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS (8u) /* [8] Drop and lost RX FIFO on parity error */ +#define UART_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS (9u) /* [9] Drop and lost RX FIFO on frame error */ +#define UART_UART_RX_CTRL_MP_MODE_POS (10u) /* [10] Multi-processor mode */ +#define UART_UART_RX_CTRL_LIN_MODE_POS (12u) /* [12] Lin mode: applicable for UART Standard */ +#define UART_UART_RX_CTRL_SKIP_START_POS (13u) /* [13] Skip start not: only for UART Standard */ +#define UART_UART_RX_CTRL_BREAK_WIDTH_POS (16u) /* [19:16] Break width: (Break width + 1) */ +#define UART_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define UART_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define UART_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define UART_UART_RX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define UART_UART_RX_CTRL_PARITY ((uint32) 0x01u << \ + UART_UART_RX_CTRL_PARITY_POS) +#define UART_UART_RX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + UART_UART_RX_CTRL_PARITY_ENABLED_POS) +#define UART_UART_RX_CTRL_POLARITY ((uint32) 0x01u << \ + UART_UART_RX_CTRL_POLARITY_POS) +#define UART_UART_RX_CTRL_DROP_ON_PARITY_ERR ((uint32) 0x01u << \ + UART_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS) +#define UART_UART_RX_CTRL_DROP_ON_FRAME_ERR ((uint32) 0x01u << \ + UART_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS) +#define UART_UART_RX_CTRL_MP_MODE ((uint32) 0x01u << \ + UART_UART_RX_CTRL_MP_MODE_POS) +#define UART_UART_RX_CTRL_LIN_MODE ((uint32) 0x01u << \ + UART_UART_RX_CTRL_LIN_MODE_POS) +#define UART_UART_RX_CTRL_SKIP_START ((uint32) 0x01u << \ + UART_UART_RX_CTRL_SKIP_START_POS) +#define UART_UART_RX_CTRL_BREAK_WIDTH_MASK ((uint32) 0x0Fu << \ + UART_UART_RX_CTRL_BREAK_WIDTH_POS) +/* UART_UART_RX_STATUS_REG */ +#define UART_UART_RX_STATUS_BR_COUNTER_POS (0u) /* [11:0] Baud Rate counter */ +#define UART_UART_RX_STATUS_BR_COUNTER_MASK ((uint32) 0xFFFu) + +#if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* UART_UART_FLOW_CTRL_REG */ + #define UART_UART_FLOW_CTRL_TRIGGER_LEVEL_POS (0u) /* [7:0] RTS RX FIFO trigger level */ + #define UART_UART_FLOW_CTRL_RTS_POLARITY_POS (16u) /* [16] Polarity of the RTS output signal */ + #define UART_UART_FLOW_CTRL_CTS_POLARITY_POS (24u) /* [24] Polarity of the CTS input signal */ + #define UART_UART_FLOW_CTRL_CTS_ENABLED_POS (25u) /* [25] Enable CTS signal */ + #define UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK) + #define UART_UART_FLOW_CTRL_RTS_POLARITY ((uint32) 0x01u << \ + UART_UART_FLOW_CTRL_RTS_POLARITY_POS) + #define UART_UART_FLOW_CTRL_CTS_POLARITY ((uint32) 0x01u << \ + UART_UART_FLOW_CTRL_CTS_POLARITY_POS) + #define UART_UART_FLOW_CTRL_CTS_ENABLE ((uint32) 0x01u << \ + UART_UART_FLOW_CTRL_CTS_ENABLED_POS) +#endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +/* UART_I2C_CTRL */ +#define UART_I2C_CTRL_HIGH_PHASE_OVS_POS (0u) /* [3:0] Oversampling factor high: master only */ +#define UART_I2C_CTRL_LOW_PHASE_OVS_POS (4u) /* [7:4] Oversampling factor low: master only */ +#define UART_I2C_CTRL_M_READY_DATA_ACK_POS (8u) /* [8] Master ACKs data while RX FIFO != FULL*/ +#define UART_I2C_CTRL_M_NOT_READY_DATA_NACK_POS (9u) /* [9] Master NACKs data if RX FIFO == FULL */ +#define UART_I2C_CTRL_S_GENERAL_IGNORE_POS (11u) /* [11] Slave ignores General call */ +#define UART_I2C_CTRL_S_READY_ADDR_ACK_POS (12u) /* [12] Slave ACKs Address if RX FIFO != FULL */ +#define UART_I2C_CTRL_S_READY_DATA_ACK_POS (13u) /* [13] Slave ACKs data while RX FIFO == FULL */ +#define UART_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS (14u) /* [14] Slave NACKs address if RX FIFO == FULL*/ +#define UART_I2C_CTRL_S_NOT_READY_DATA_NACK_POS (15u) /* [15] Slave NACKs data if RX FIFO is FULL */ +#define UART_I2C_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define UART_I2C_CTRL_SLAVE_MODE_POS (30u) /* [30] Slave mode enabled */ +#define UART_I2C_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define UART_I2C_CTRL_HIGH_PHASE_OVS_MASK ((uint32) 0x0Fu) +#define UART_I2C_CTRL_LOW_PHASE_OVS_MASK ((uint32) 0x0Fu << \ + UART_I2C_CTRL_LOW_PHASE_OVS_POS) +#define UART_I2C_CTRL_M_READY_DATA_ACK ((uint32) 0x01u << \ + UART_I2C_CTRL_M_READY_DATA_ACK_POS) +#define UART_I2C_CTRL_M_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + UART_I2C_CTRL_M_NOT_READY_DATA_NACK_POS) +#define UART_I2C_CTRL_S_GENERAL_IGNORE ((uint32) 0x01u << \ + UART_I2C_CTRL_S_GENERAL_IGNORE_POS) +#define UART_I2C_CTRL_S_READY_ADDR_ACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_READY_ADDR_ACK_POS) +#define UART_I2C_CTRL_S_READY_DATA_ACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_READY_DATA_ACK_POS) +#define UART_I2C_CTRL_S_NOT_READY_ADDR_NACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS) +#define UART_I2C_CTRL_S_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK_POS) +#define UART_I2C_CTRL_LOOPBACK ((uint32) 0x01u << \ + UART_I2C_CTRL_LOOPBACK_POS) +#define UART_I2C_CTRL_SLAVE_MODE ((uint32) 0x01u << \ + UART_I2C_CTRL_SLAVE_MODE_POS) +#define UART_I2C_CTRL_MASTER_MODE ((uint32) 0x01u << \ + UART_I2C_CTRL_MASTER_MODE_POS) +#define UART_I2C_CTRL_SLAVE_MASTER_MODE_MASK ((uint32) 0x03u << \ + UART_I2C_CTRL_SLAVE_MODE_POS) + +/* UART_I2C_STATUS_REG */ +#define UART_I2C_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy: internally clocked */ +#define UART_I2C_STATUS_S_READ_POS (4u) /* [4] Slave is read by master */ +#define UART_I2C_STATUS_M_READ_POS (5u) /* [5] Master reads Slave */ +#define UART_I2C_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EZAddress */ +#define UART_I2C_STATUS_BUS_BUSY ((uint32) 0x01u) +#define UART_I2C_STATUS_S_READ ((uint32) 0x01u << UART_I2C_STATUS_S_READ_POS) +#define UART_I2C_STATUS_M_READ ((uint32) 0x01u << UART_I2C_STATUS_M_READ_POS) +#define UART_I2C_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << UART_I2C_STATUS_EZBUF_ADDR_POS) + +/* UART_I2C_MASTER_CMD_REG */ +#define UART_I2C_MASTER_CMD_M_START_POS (0u) /* [0] Master generate Start */ +#define UART_I2C_MASTER_CMD_M_START_ON_IDLE_POS (1u) /* [1] Master generate Start if bus is free */ +#define UART_I2C_MASTER_CMD_M_ACK_POS (2u) /* [2] Master generate ACK */ +#define UART_I2C_MASTER_CMD_M_NACK_POS (3u) /* [3] Master generate NACK */ +#define UART_I2C_MASTER_CMD_M_STOP_POS (4u) /* [4] Master generate Stop */ +#define UART_I2C_MASTER_CMD_M_START ((uint32) 0x01u) +#define UART_I2C_MASTER_CMD_M_START_ON_IDLE ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_START_ON_IDLE_POS) +#define UART_I2C_MASTER_CMD_M_ACK ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_ACK_POS) +#define UART_I2C_MASTER_CMD_M_NACK ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_NACK_POS) +#define UART_I2C_MASTER_CMD_M_STOP ((uint32) 0x01u << \ + UART_I2C_MASTER_CMD_M_STOP_POS) + +/* UART_I2C_SLAVE_CMD_REG */ +#define UART_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define UART_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define UART_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define UART_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << UART_I2C_SLAVE_CMD_S_NACK_POS) + +#define UART_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define UART_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define UART_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define UART_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << UART_I2C_SLAVE_CMD_S_NACK_POS) + +/* UART_I2C_CFG_REG */ +#if (UART_CY_SCBIP_V0) +#define UART_I2C_CFG_SDA_FILT_HYS_POS (0u) /* [1:0] Trim bits for the I2C SDA filter */ +#define UART_I2C_CFG_SDA_FILT_TRIM_POS (2u) /* [3:2] Trim bits for the I2C SDA filter */ +#define UART_I2C_CFG_SCL_FILT_HYS_POS (4u) /* [5:4] Trim bits for the I2C SCL filter */ +#define UART_I2C_CFG_SCL_FILT_TRIM_POS (6u) /* [7:6] Trim bits for the I2C SCL filter */ +#define UART_I2C_CFG_SDA_FILT_OUT_HYS_POS (8u) /* [9:8] Trim bits for I2C SDA filter output path */ +#define UART_I2C_CFG_SDA_FILT_OUT_TRIM_POS (10u) /* [11:10] Trim bits for I2C SDA filter output path */ +#define UART_I2C_CFG_SDA_FILT_HS_POS (16u) /* [16] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_I2C_CFG_SDA_FILT_ENABLED_POS (17u) /* [17] I2C SDA filter enabled */ +#define UART_I2C_CFG_SCL_FILT_HS_POS (24u) /* [24] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_I2C_CFG_SCL_FILT_ENABLED_POS (25u) /* [25] I2C SCL filter enabled */ +#define UART_I2C_CFG_SDA_FILT_OUT_HS_POS (26u) /* [26] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_I2C_CFG_SDA_FILT_OUT_ENABLED_POS (27u) /* [27] I2C SDA output delay filter enabled */ +#define UART_I2C_CFG_SDA_FILT_HYS_MASK ((uint32) 0x03u) +#define UART_I2C_CFG_SDA_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_FILT_TRIM_POS) +#define UART_I2C_CFG_SCL_FILT_HYS_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SCL_FILT_HYS_POS) +#define UART_I2C_CFG_SCL_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SCL_FILT_TRIM_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_HYS_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_FILT_OUT_HYS_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_FILT_OUT_TRIM_POS) +#define UART_I2C_CFG_SDA_FILT_HS ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_HS_POS) +#define UART_I2C_CFG_SDA_FILT_ENABLED ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_ENABLED_POS) +#define UART_I2C_CFG_SCL_FILT_HS ((uint32) 0x01u << \ + UART_I2C_CFG_SCL_FILT_HS_POS) +#define UART_I2C_CFG_SCL_FILT_ENABLED ((uint32) 0x01u << \ + UART_I2C_CFG_SCL_FILT_ENABLED_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_HS ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_OUT_HS_POS) +#define UART_I2C_CFG_SDA_FILT_OUT_ENABLED ((uint32) 0x01u << \ + UART_I2C_CFG_SDA_FILT_OUT_ENABLED_POS) +#else +#define UART_I2C_CFG_SDA_IN_FILT_TRIM_POS (0u) /* [1:0] Trim bits for "i2c_sda_in" 50 ns filter */ +#define UART_I2C_CFG_SDA_IN_FILT_SEL_POS (4u) /* [4] "i2c_sda_in" filter delay: 0 ns and 50 ns */ +#define UART_I2C_CFG_SCL_IN_FILT_TRIM_POS (8u) /* [9:8] Trim bits for "i2c_scl_in" 50 ns filter */ +#define UART_I2C_CFG_SCL_IN_FILT_SEL_POS (12u) /* [12] "i2c_scl_in" filter delay: 0 ns and 50 ns */ +#define UART_I2C_CFG_SDA_OUT_FILT0_TRIM_POS (16u) /* [17:16] Trim bits for "i2c_sda_out" 50 ns filter 0 */ +#define UART_I2C_CFG_SDA_OUT_FILT1_TRIM_POS (18u) /* [19:18] Trim bits for "i2c_sda_out" 50 ns filter 1 */ +#define UART_I2C_CFG_SDA_OUT_FILT2_TRIM_POS (20u) /* [21:20] Trim bits for "i2c_sda_out" 50 ns filter 2 */ +#define UART_I2C_CFG_SDA_OUT_FILT_SEL_POS (28u) /* [29:28] Cumulative "i2c_sda_out" filter delay: */ + +#define UART_I2C_CFG_SDA_IN_FILT_TRIM_MASK ((uint32) 0x03u) +#define UART_I2C_CFG_SDA_IN_FILT_SEL ((uint32) 0x01u << UART_I2C_CFG_SDA_IN_FILT_SEL_POS) +#define UART_I2C_CFG_SCL_IN_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SCL_IN_FILT_TRIM_POS) +#define UART_I2C_CFG_SCL_IN_FILT_SEL ((uint32) 0x01u << UART_I2C_CFG_SCL_IN_FILT_SEL_POS) +#define UART_I2C_CFG_SDA_OUT_FILT0_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT0_TRIM_POS) +#define UART_I2C_CFG_SDA_OUT_FILT1_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT1_TRIM_POS) +#define UART_I2C_CFG_SDA_OUT_FILT2_TRIM_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT2_TRIM_POS) +#define UART_I2C_CFG_SDA_OUT_FILT_SEL_MASK ((uint32) 0x03u << \ + UART_I2C_CFG_SDA_OUT_FILT_SEL_POS) +#endif /* (UART_CY_SCBIP_V0) */ + + +/* UART_TX_CTRL_REG */ +#define UART_TX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define UART_TX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define UART_TX_CTRL_ENABLED_POS (31u) /* [31] Transmitter enabled */ +#define UART_TX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define UART_TX_CTRL_MSB_FIRST ((uint32) 0x01u << UART_TX_CTRL_MSB_FIRST_POS) +#define UART_TX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define UART_TX_CTRL_ENABLED ((uint32) 0x01u << UART_TX_CTRL_ENABLED_POS) + +/* UART_TX_CTRL_FIFO_REG */ +#define UART_TX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define UART_TX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear TX FIFO: cleared after set */ +#define UART_TX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze TX FIFO: HW do not inc read pointer */ +#define UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK) +#define UART_TX_FIFO_CTRL_CLEAR ((uint32) 0x01u << UART_TX_FIFO_CTRL_CLEAR_POS) +#define UART_TX_FIFO_CTRL_FREEZE ((uint32) 0x01u << UART_TX_FIFO_CTRL_FREEZE_POS) + +/* UART_TX_FIFO_STATUS_REG */ +#define UART_TX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in TX FIFO */ +#define UART_TX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of TX FIFO */ +#define UART_TX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] TX FIFO read pointer */ +#define UART_TX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] TX FIFO write pointer */ +#define UART_TX_FIFO_STATUS_USED_MASK ((uint32) UART_FF_DATA_NR_LOG2_PLUS1_MASK) +#define UART_TX_FIFO_SR_VALID ((uint32) 0x01u << UART_TX_FIFO_SR_VALID_POS) +#define UART_TX_FIFO_STATUS_RD_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_TX_FIFO_STATUS_RD_PTR_POS) +#define UART_TX_FIFO_STATUS_WR_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_TX_FIFO_STATUS_WR_PTR_POS) + +/* UART_TX_FIFO_WR_REG */ +#define UART_TX_FIFO_WR_POS (0u) /* [15:0] Data written into TX FIFO */ +#define UART_TX_FIFO_WR_MASK ((uint32) 0xFFu) + +/* UART_RX_CTRL_REG */ +#define UART_RX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define UART_RX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define UART_RX_CTRL_MEDIAN_POS (9u) /* [9] Median filter */ +#define UART_RX_CTRL_ENABLED_POS (31u) /* [31] Receiver enabled */ +#define UART_RX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define UART_RX_CTRL_MSB_FIRST ((uint32) 0x01u << UART_RX_CTRL_MSB_FIRST_POS) +#define UART_RX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define UART_RX_CTRL_MEDIAN ((uint32) 0x01u << UART_RX_CTRL_MEDIAN_POS) +#define UART_RX_CTRL_ENABLED ((uint32) 0x01u << UART_RX_CTRL_ENABLED_POS) + + +/* UART_RX_FIFO_CTRL_REG */ +#define UART_RX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define UART_RX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear RX FIFO: clear after set */ +#define UART_RX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze RX FIFO: HW writes has not effect */ +#define UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK) +#define UART_RX_FIFO_CTRL_CLEAR ((uint32) 0x01u << UART_RX_FIFO_CTRL_CLEAR_POS) +#define UART_RX_FIFO_CTRL_FREEZE ((uint32) 0x01u << UART_RX_FIFO_CTRL_FREEZE_POS) + +/* UART_RX_FIFO_STATUS_REG */ +#define UART_RX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in RX FIFO */ +#define UART_RX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of RX FIFO */ +#define UART_RX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] RX FIFO read pointer */ +#define UART_RX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] RX FIFO write pointer */ +#define UART_RX_FIFO_STATUS_USED_MASK ((uint32) UART_FF_DATA_NR_LOG2_PLUS1_MASK) +#define UART_RX_FIFO_SR_VALID ((uint32) 0x01u << UART_RX_FIFO_SR_VALID_POS) +#define UART_RX_FIFO_STATUS_RD_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_RX_FIFO_STATUS_RD_PTR_POS) +#define UART_RX_FIFO_STATUS_WR_PTR_MASK ((uint32) UART_FF_DATA_NR_LOG2_MASK << \ + UART_RX_FIFO_STATUS_WR_PTR_POS) + +/* UART_RX_MATCH_REG */ +#define UART_RX_MATCH_ADDR_POS (0u) /* [7:0] Slave address */ +#define UART_RX_MATCH_MASK_POS (16u) /* [23:16] Slave address mask: 0 - doesn't care */ +#define UART_RX_MATCH_ADDR_MASK ((uint32) 0xFFu) +#define UART_RX_MATCH_MASK_MASK ((uint32) 0xFFu << UART_RX_MATCH_MASK_POS) + +/* UART_RX_FIFO_WR_REG */ +#define UART_RX_FIFO_RD_POS (0u) /* [15:0] Data read from RX FIFO */ +#define UART_RX_FIFO_RD_MASK ((uint32) 0xFFu) + +/* UART_RX_FIFO_RD_SILENT_REG */ +#define UART_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define UART_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* UART_RX_FIFO_RD_SILENT_REG */ +#define UART_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define UART_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* UART_EZBUF_DATA_REG */ +#define UART_EZBUF_DATA_POS (0u) /* [7:0] Data from EZ Memory */ +#define UART_EZBUF_DATA_MASK ((uint32) 0xFFu) + +/* UART_INTR_CAUSE_REG */ +#define UART_INTR_CAUSE_MASTER_POS (0u) /* [0] Master interrupt active */ +#define UART_INTR_CAUSE_SLAVE_POS (1u) /* [1] Slave interrupt active */ +#define UART_INTR_CAUSE_TX_POS (2u) /* [2] Transmitter interrupt active */ +#define UART_INTR_CAUSE_RX_POS (3u) /* [3] Receiver interrupt active */ +#define UART_INTR_CAUSE_I2C_EC_POS (4u) /* [4] Externally clock I2C interrupt active */ +#define UART_INTR_CAUSE_SPI_EC_POS (5u) /* [5] Externally clocked SPI interrupt active */ +#define UART_INTR_CAUSE_MASTER ((uint32) 0x01u) +#define UART_INTR_CAUSE_SLAVE ((uint32) 0x01u << UART_INTR_CAUSE_SLAVE_POS) +#define UART_INTR_CAUSE_TX ((uint32) 0x01u << UART_INTR_CAUSE_TX_POS) +#define UART_INTR_CAUSE_RX ((uint32) 0x01u << UART_INTR_CAUSE_RX_POS) +#define UART_INTR_CAUSE_I2C_EC ((uint32) 0x01u << UART_INTR_CAUSE_I2C_EC_POS) +#define UART_INTR_CAUSE_SPI_EC ((uint32) 0x01u << UART_INTR_CAUSE_SPI_EC_POS) + +/* UART_INTR_SPI_EC_REG, UART_INTR_SPI_EC_MASK_REG, UART_INTR_SPI_EC_MASKED_REG */ +#define UART_INTR_SPI_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define UART_INTR_SPI_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define UART_INTR_SPI_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define UART_INTR_SPI_EC_WAKE_UP ((uint32) 0x01u) +#define UART_INTR_SPI_EC_EZBUF_STOP ((uint32) 0x01u << \ + UART_INTR_SPI_EC_EZBUF_STOP_POS) +#define UART_INTR_SPI_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_SPI_EC_EZBUF_WRITE_STOP_POS) + +/* UART_INTR_I2C_EC, UART_INTR_I2C_EC_MASK, UART_INTR_I2C_EC_MASKED */ +#define UART_INTR_I2C_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define UART_INTR_I2C_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define UART_INTR_I2C_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define UART_INTR_I2C_EC_WAKE_UP ((uint32) 0x01u) +#define UART_INTR_I2C_EC_EZBUF_STOP ((uint32) 0x01u << \ + UART_INTR_I2C_EC_EZBUF_STOP_POS) +#define UART_INTR_I2C_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_I2C_EC_EZBUF_WRITE_STOP_POS) + +/* UART_INTR_MASTER, UART_INTR_MASTER_SET, + UART_INTR_MASTER_MASK, UART_INTR_MASTER_MASKED */ +#define UART_INTR_MASTER_I2C_ARB_LOST_POS (0u) /* [0] Master lost arbitration */ +#define UART_INTR_MASTER_I2C_NACK_POS (1u) /* [1] Master receives NACK: address or write to slave */ +#define UART_INTR_MASTER_I2C_ACK_POS (2u) /* [2] Master receives NACK: address or write to slave */ +#define UART_INTR_MASTER_I2C_STOP_POS (4u) /* [4] Master detects the Stop: only self generated Stop*/ +#define UART_INTR_MASTER_I2C_BUS_ERROR_POS (8u) /* [8] Master detects bus error: misplaced Start or Stop*/ +#define UART_INTR_MASTER_SPI_DONE_POS (9u) /* [9] Master complete transfer: Only for SPI */ +#define UART_INTR_MASTER_I2C_ARB_LOST ((uint32) 0x01u) +#define UART_INTR_MASTER_I2C_NACK ((uint32) 0x01u << UART_INTR_MASTER_I2C_NACK_POS) +#define UART_INTR_MASTER_I2C_ACK ((uint32) 0x01u << UART_INTR_MASTER_I2C_ACK_POS) +#define UART_INTR_MASTER_I2C_STOP ((uint32) 0x01u << UART_INTR_MASTER_I2C_STOP_POS) +#define UART_INTR_MASTER_I2C_BUS_ERROR ((uint32) 0x01u << \ + UART_INTR_MASTER_I2C_BUS_ERROR_POS) +#define UART_INTR_MASTER_SPI_DONE ((uint32) 0x01u << UART_INTR_MASTER_SPI_DONE_POS) + +/* +* UART_INTR_SLAVE, UART_INTR_SLAVE_SET, +* UART_INTR_SLAVE_MASK, UART_INTR_SLAVE_MASKED +*/ +#define UART_INTR_SLAVE_I2C_ARB_LOST_POS (0u) /* [0] Slave lost arbitration */ +#define UART_INTR_SLAVE_I2C_NACK_POS (1u) /* [1] Slave receives NACK: master reads data */ +#define UART_INTR_SLAVE_I2C_ACK_POS (2u) /* [2] Slave receives ACK: master reads data */ +#define UART_INTR_SLAVE_I2C_WRITE_STOP_POS (3u) /* [3] Slave detects end of write transaction */ +#define UART_INTR_SLAVE_I2C_STOP_POS (4u) /* [4] Slave detects end of transaction intended */ +#define UART_INTR_SLAVE_I2C_START_POS (5u) /* [5] Slave detects Start */ +#define UART_INTR_SLAVE_I2C_ADDR_MATCH_POS (6u) /* [6] Slave address matches */ +#define UART_INTR_SLAVE_I2C_GENERAL_POS (7u) /* [7] General call received */ +#define UART_INTR_SLAVE_I2C_BUS_ERROR_POS (8u) /* [8] Slave detects bus error */ +#define UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS (9u) /* [9] Slave write complete: Only for SPI */ +#define UART_INTR_SLAVE_SPI_EZBUF_STOP_POS (10u) /* [10] Slave end of transaction: Only for SPI */ +#define UART_INTR_SLAVE_SPI_BUS_ERROR_POS (11u) /* [11] Slave detects bus error: Only for SPI */ +#define UART_INTR_SLAVE_I2C_ARB_LOST ((uint32) 0x01u) +#define UART_INTR_SLAVE_I2C_NACK ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_NACK_POS) +#define UART_INTR_SLAVE_I2C_ACK ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_ACK_POS) +#define UART_INTR_SLAVE_I2C_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_WRITE_STOP_POS) +#define UART_INTR_SLAVE_I2C_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_STOP_POS) +#define UART_INTR_SLAVE_I2C_START ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_START_POS) +#define UART_INTR_SLAVE_I2C_ADDR_MATCH ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_ADDR_MATCH_POS) +#define UART_INTR_SLAVE_I2C_GENERAL ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_GENERAL_POS) +#define UART_INTR_SLAVE_I2C_BUS_ERROR ((uint32) 0x01u << \ + UART_INTR_SLAVE_I2C_BUS_ERROR_POS) +#define UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS) +#define UART_INTR_SLAVE_SPI_EZBUF_STOP ((uint32) 0x01u << \ + UART_INTR_SLAVE_SPI_EZBUF_STOP_POS) +#define UART_INTR_SLAVE_SPI_BUS_ERROR ((uint32) 0x01u << \ + UART_INTR_SLAVE_SPI_BUS_ERROR_POS) + +/* +* UART_INTR_TX, UART_INTR_TX_SET, +* UART_INTR_TX_MASK, UART_INTR_TX_MASKED +*/ +#define UART_INTR_TX_TRIGGER_POS (0u) /* [0] Trigger on TX FIFO entires */ +#define UART_INTR_TX_NOT_FULL_POS (1u) /* [1] TX FIFO is not full */ +#define UART_INTR_TX_EMPTY_POS (4u) /* [4] TX FIFO is empty */ +#define UART_INTR_TX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full TX FIFO */ +#define UART_INTR_TX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty TX FIFO */ +#define UART_INTR_TX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define UART_INTR_TX_UART_NACK_POS (8u) /* [8] UART transmitter received a NACK: SmartCard mode */ +#define UART_INTR_TX_UART_DONE_POS (9u) /* [9] UART transmitter done even */ +#define UART_INTR_TX_UART_ARB_LOST_POS (10u) /* [10] UART lost arbitration: LIN or SmartCard */ +#define UART_INTR_TX_TRIGGER ((uint32) 0x01u) +#define UART_INTR_TX_FIFO_LEVEL (UART_INTR_TX_TRIGGER) +#define UART_INTR_TX_NOT_FULL ((uint32) 0x01u << UART_INTR_TX_NOT_FULL_POS) +#define UART_INTR_TX_EMPTY ((uint32) 0x01u << UART_INTR_TX_EMPTY_POS) +#define UART_INTR_TX_OVERFLOW ((uint32) 0x01u << UART_INTR_TX_OVERFLOW_POS) +#define UART_INTR_TX_UNDERFLOW ((uint32) 0x01u << UART_INTR_TX_UNDERFLOW_POS) +#define UART_INTR_TX_BLOCKED ((uint32) 0x01u << UART_INTR_TX_BLOCKED_POS) +#define UART_INTR_TX_UART_NACK ((uint32) 0x01u << UART_INTR_TX_UART_NACK_POS) +#define UART_INTR_TX_UART_DONE ((uint32) 0x01u << UART_INTR_TX_UART_DONE_POS) +#define UART_INTR_TX_UART_ARB_LOST ((uint32) 0x01u << UART_INTR_TX_UART_ARB_LOST_POS) + +/* +* UART_INTR_RX, UART_INTR_RX_SET, +* UART_INTR_RX_MASK, UART_INTR_RX_MASKED +*/ +#define UART_INTR_RX_TRIGGER_POS (0u) /* [0] Trigger on RX FIFO entires */ +#define UART_INTR_RX_NOT_EMPTY_POS (2u) /* [2] RX FIFO is not empty */ +#define UART_INTR_RX_FULL_POS (3u) /* [3] RX FIFO is full */ +#define UART_INTR_RX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full RX FIFO */ +#define UART_INTR_RX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty RX FIFO */ +#define UART_INTR_RX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define UART_INTR_RX_FRAME_ERROR_POS (8u) /* [8] Frame error in received data frame */ +#define UART_INTR_RX_PARITY_ERROR_POS (9u) /* [9] Parity error in received data frame */ +#define UART_INTR_RX_BAUD_DETECT_POS (10u) /* [10] LIN baud rate detection is completed */ +#define UART_INTR_RX_BREAK_DETECT_POS (11u) /* [11] Break detection is successful */ +#define UART_INTR_RX_TRIGGER ((uint32) 0x01u) +#define UART_INTR_RX_FIFO_LEVEL (UART_INTR_RX_TRIGGER) +#define UART_INTR_RX_NOT_EMPTY ((uint32) 0x01u << UART_INTR_RX_NOT_EMPTY_POS) +#define UART_INTR_RX_FULL ((uint32) 0x01u << UART_INTR_RX_FULL_POS) +#define UART_INTR_RX_OVERFLOW ((uint32) 0x01u << UART_INTR_RX_OVERFLOW_POS) +#define UART_INTR_RX_UNDERFLOW ((uint32) 0x01u << UART_INTR_RX_UNDERFLOW_POS) +#define UART_INTR_RX_BLOCKED ((uint32) 0x01u << UART_INTR_RX_BLOCKED_POS) +#define UART_INTR_RX_FRAME_ERROR ((uint32) 0x01u << UART_INTR_RX_FRAME_ERROR_POS) +#define UART_INTR_RX_PARITY_ERROR ((uint32) 0x01u << UART_INTR_RX_PARITY_ERROR_POS) +#define UART_INTR_RX_BAUD_DETECT ((uint32) 0x01u << UART_INTR_RX_BAUD_DETECT_POS) +#define UART_INTR_RX_BREAK_DETECT ((uint32) 0x01u << UART_INTR_RX_BREAK_DETECT_POS) + +/* Define all interrupt sources */ +#define UART_INTR_I2C_EC_ALL (UART_INTR_I2C_EC_WAKE_UP | \ + UART_INTR_I2C_EC_EZBUF_STOP | \ + UART_INTR_I2C_EC_EZBUF_WRITE_STOP) + +#define UART_INTR_SPI_EC_ALL (UART_INTR_SPI_EC_WAKE_UP | \ + UART_INTR_SPI_EC_EZBUF_STOP | \ + UART_INTR_SPI_EC_EZBUF_WRITE_STOP) + +#define UART_INTR_MASTER_ALL (UART_INTR_MASTER_I2C_ARB_LOST | \ + UART_INTR_MASTER_I2C_NACK | \ + UART_INTR_MASTER_I2C_ACK | \ + UART_INTR_MASTER_I2C_STOP | \ + UART_INTR_MASTER_I2C_BUS_ERROR | \ + UART_INTR_MASTER_SPI_DONE) + +#define UART_INTR_SLAVE_ALL (UART_INTR_SLAVE_I2C_ARB_LOST | \ + UART_INTR_SLAVE_I2C_NACK | \ + UART_INTR_SLAVE_I2C_ACK | \ + UART_INTR_SLAVE_I2C_WRITE_STOP | \ + UART_INTR_SLAVE_I2C_STOP | \ + UART_INTR_SLAVE_I2C_START | \ + UART_INTR_SLAVE_I2C_ADDR_MATCH | \ + UART_INTR_SLAVE_I2C_GENERAL | \ + UART_INTR_SLAVE_I2C_BUS_ERROR | \ + UART_INTR_SLAVE_SPI_EZBUF_WRITE_STOP | \ + UART_INTR_SLAVE_SPI_EZBUF_STOP | \ + UART_INTR_SLAVE_SPI_BUS_ERROR) + +#define UART_INTR_TX_ALL (UART_INTR_TX_TRIGGER | \ + UART_INTR_TX_NOT_FULL | \ + UART_INTR_TX_EMPTY | \ + UART_INTR_TX_OVERFLOW | \ + UART_INTR_TX_UNDERFLOW | \ + UART_INTR_TX_BLOCKED | \ + UART_INTR_TX_UART_NACK | \ + UART_INTR_TX_UART_DONE | \ + UART_INTR_TX_UART_ARB_LOST) + +#define UART_INTR_RX_ALL (UART_INTR_RX_TRIGGER | \ + UART_INTR_RX_NOT_EMPTY | \ + UART_INTR_RX_FULL | \ + UART_INTR_RX_OVERFLOW | \ + UART_INTR_RX_UNDERFLOW | \ + UART_INTR_RX_BLOCKED | \ + UART_INTR_RX_FRAME_ERROR | \ + UART_INTR_RX_PARITY_ERROR | \ + UART_INTR_RX_BAUD_DETECT | \ + UART_INTR_RX_BREAK_DETECT) + +/* I2C and EZI2C slave address defines */ +#define UART_I2C_SLAVE_ADDR_POS (0x01u) /* 7-bit address shift */ +#define UART_I2C_SLAVE_ADDR_MASK (0xFEu) /* 8-bit address mask */ + +/* OVS constants for IrDA Low Power operation */ +#define UART_CTRL_OVS_IRDA_LP_OVS16 (0x00u) +#define UART_CTRL_OVS_IRDA_LP_OVS32 (0x01u) +#define UART_CTRL_OVS_IRDA_LP_OVS48 (0x02u) +#define UART_CTRL_OVS_IRDA_LP_OVS96 (0x03u) +#define UART_CTRL_OVS_IRDA_LP_OVS192 (0x04u) +#define UART_CTRL_OVS_IRDA_LP_OVS768 (0x05u) +#define UART_CTRL_OVS_IRDA_LP_OVS1536 (0x06u) + +/* OVS constant for IrDA */ +#define UART_CTRL_OVS_IRDA_OVS16 (UART_UART_IRDA_LP_OVS16) + + +/*************************************** +* Common Macro Definitions +***************************************/ + +/* Re-enables the SCB IP. A clear enable bit has a different effect +* on the scb IP depending on the version: +* CY_SCBIP_V0: resets state, status, TX and RX FIFOs. +* CY_SCBIP_V1 or later: resets state, status, TX and RX FIFOs and interrupt sources. +* Clear I2C command registers are because they are not impacted by re-enable. +*/ +#define UART_SCB_SW_RESET UART_I2CFwBlockReset() + +/* TX FIFO macro */ +#define UART_CLEAR_TX_FIFO \ + do{ \ + UART_TX_FIFO_CTRL_REG |= ((uint32) UART_TX_FIFO_CTRL_CLEAR); \ + UART_TX_FIFO_CTRL_REG &= ((uint32) ~UART_TX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define UART_GET_TX_FIFO_ENTRIES (UART_TX_FIFO_STATUS_REG & \ + UART_TX_FIFO_STATUS_USED_MASK) + +#define UART_GET_TX_FIFO_SR_VALID ((0u != (UART_TX_FIFO_STATUS_REG & \ + UART_TX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* RX FIFO macro */ +#define UART_CLEAR_RX_FIFO \ + do{ \ + UART_RX_FIFO_CTRL_REG |= ((uint32) UART_RX_FIFO_CTRL_CLEAR); \ + UART_RX_FIFO_CTRL_REG &= ((uint32) ~UART_RX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define UART_GET_RX_FIFO_ENTRIES (UART_RX_FIFO_STATUS_REG & \ + UART_RX_FIFO_STATUS_USED_MASK) + +#define UART_GET_RX_FIFO_SR_VALID ((0u != (UART_RX_FIFO_STATUS_REG & \ + UART_RX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* Write interrupt source: set sourceMask bits in UART_INTR_X_MASK_REG */ +#define UART_WRITE_INTR_I2C_EC_MASK(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!UART_CY_SCBIP_V1) + #define UART_WRITE_INTR_SPI_EC_MASK(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_WRITE_INTR_MASTER_MASK(sourceMask) \ + do{ \ + UART_INTR_MASTER_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_WRITE_INTR_SLAVE_MASK(sourceMask) \ + do{ \ + UART_INTR_SLAVE_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_WRITE_INTR_TX_MASK(sourceMask) \ + do{ \ + UART_INTR_TX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_WRITE_INTR_RX_MASK(sourceMask) \ + do{ \ + UART_INTR_RX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +/* Enable interrupt source: set sourceMask bits in UART_INTR_X_MASK_REG */ +#define UART_ENABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#if (!UART_CY_SCBIP_V1) + #define UART_ENABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_ENABLE_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_ENABLE_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_ENABLE_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_ENABLE_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +/* Disable interrupt source: clear sourceMask bits in UART_INTR_X_MASK_REG */ +#define UART_DISABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#if (!UART_CY_SCBIP_V1) + #define UART_DISABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_DISABLE_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_DISABLE_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_DISABLE_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_DISABLE_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +/* Set interrupt sources: write sourceMask bits in UART_INTR_X_SET_REG */ +#define UART_SET_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_SET_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_SET_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_SET_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +/* Clear interrupt sources: write sourceMask bits in UART_INTR_X_REG */ +#define UART_CLEAR_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_INTR_I2C_EC_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!UART_CY_SCBIP_V1) + #define UART_CLEAR_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_INTR_SPI_EC_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_CY_SCBIP_V1) */ + +#define UART_CLEAR_INTR_MASTER(sourceMask) \ + do{ \ + UART_INTR_MASTER_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_CLEAR_INTR_SLAVE(sourceMask) \ + do{ \ + UART_INTR_SLAVE_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_CLEAR_INTR_TX(sourceMask) \ + do{ \ + UART_INTR_TX_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_CLEAR_INTR_RX(sourceMask) \ + do{ \ + UART_INTR_RX_REG = (uint32) (sourceMask); \ + }while(0) + +/* Return true if sourceMask is set in UART_INTR_CAUSE_REG */ +#define UART_CHECK_CAUSE_INTR(sourceMask) (0u != (UART_INTR_CAUSE_REG & (sourceMask))) + +/* Return true if sourceMask is set in INTR_X_MASKED_REG */ +#define UART_CHECK_INTR_I2C_EC(sourceMask) (0u != (UART_INTR_I2C_EC_REG & (sourceMask))) +#if (!UART_CY_SCBIP_V1) + #define UART_CHECK_INTR_SPI_EC(sourceMask) (0u != (UART_INTR_SPI_EC_REG & (sourceMask))) +#endif /* (!UART_CY_SCBIP_V1) */ +#define UART_CHECK_INTR_MASTER(sourceMask) (0u != (UART_INTR_MASTER_REG & (sourceMask))) +#define UART_CHECK_INTR_SLAVE(sourceMask) (0u != (UART_INTR_SLAVE_REG & (sourceMask))) +#define UART_CHECK_INTR_TX(sourceMask) (0u != (UART_INTR_TX_REG & (sourceMask))) +#define UART_CHECK_INTR_RX(sourceMask) (0u != (UART_INTR_RX_REG & (sourceMask))) + +/* Return true if sourceMask is set in UART_INTR_X_MASKED_REG */ +#define UART_CHECK_INTR_I2C_EC_MASKED(sourceMask) (0u != (UART_INTR_I2C_EC_MASKED_REG & \ + (sourceMask))) +#if (!UART_CY_SCBIP_V1) + #define UART_CHECK_INTR_SPI_EC_MASKED(sourceMask) (0u != (UART_INTR_SPI_EC_MASKED_REG & \ + (sourceMask))) +#endif /* (!UART_CY_SCBIP_V1) */ +#define UART_CHECK_INTR_MASTER_MASKED(sourceMask) (0u != (UART_INTR_MASTER_MASKED_REG & \ + (sourceMask))) +#define UART_CHECK_INTR_SLAVE_MASKED(sourceMask) (0u != (UART_INTR_SLAVE_MASKED_REG & \ + (sourceMask))) +#define UART_CHECK_INTR_TX_MASKED(sourceMask) (0u != (UART_INTR_TX_MASKED_REG & \ + (sourceMask))) +#define UART_CHECK_INTR_RX_MASKED(sourceMask) (0u != (UART_INTR_RX_MASKED_REG & \ + (sourceMask))) + +/* Return true if sourceMask is set in UART_CTRL_REG: generally is used to check enable bit */ +#define UART_GET_CTRL_ENABLED (0u != (UART_CTRL_REG & UART_CTRL_ENABLED)) + +#define UART_CHECK_SLAVE_AUTO_ADDR_NACK (0u != (UART_I2C_CTRL_REG & \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK)) + + +/*************************************** +* I2C Macro Definitions +***************************************/ + +/* Enable auto ACK/NACK */ +#define UART_ENABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_ENABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define UART_ENABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_ENABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define UART_ENABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG |= UART_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Disable auto ACK/NACK */ +#define UART_DISABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_DISABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define UART_DISABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_DISABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define UART_DISABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + UART_I2C_CTRL_REG &= ~UART_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Enable Slave autoACK/NACK Data */ +#define UART_ENABLE_SLAVE_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG |= (UART_I2C_CTRL_S_READY_DATA_ACK | \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK); \ + }while(0) + +/* Disable Slave autoACK/NACK Data */ +#define UART_DISABLE_SLAVE_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG &= ((uint32) \ + ~(UART_I2C_CTRL_S_READY_DATA_ACK | \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Disable Master autoACK/NACK Data */ +#define UART_DISABLE_MASTER_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG &= ((uint32) \ + ~(UART_I2C_CTRL_M_READY_DATA_ACK | \ + UART_I2C_CTRL_M_NOT_READY_DATA_NACK)); \ + }while(0) +/* Disables auto data ACK/NACK bits */ +#define UART_DISABLE_AUTO_DATA \ + do{ \ + UART_I2C_CTRL_REG &= ((uint32) ~(UART_I2C_CTRL_M_READY_DATA_ACK | \ + UART_I2C_CTRL_M_NOT_READY_DATA_NACK | \ + UART_I2C_CTRL_S_READY_DATA_ACK | \ + UART_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Master commands */ +#define UART_I2C_MASTER_GENERATE_START \ + do{ \ + UART_I2C_MASTER_CMD_REG = UART_I2C_MASTER_CMD_M_START_ON_IDLE; \ + }while(0) + +#define UART_I2C_MASTER_CLEAR_START \ + do{ \ + UART_I2C_MASTER_CMD_REG = ((uint32) 0u); \ + }while(0) + +#define UART_I2C_MASTER_GENERATE_RESTART UART_I2CReStartGeneration() + +#define UART_I2C_MASTER_GENERATE_STOP \ + do{ \ + UART_I2C_MASTER_CMD_REG = \ + (UART_I2C_MASTER_CMD_M_STOP | \ + (UART_CHECK_I2C_STATUS(UART_I2C_STATUS_M_READ) ? \ + (UART_I2C_MASTER_CMD_M_NACK) : (0u))); \ + }while(0) + +#define UART_I2C_MASTER_GENERATE_ACK \ + do{ \ + UART_I2C_MASTER_CMD_REG = UART_I2C_MASTER_CMD_M_ACK; \ + }while(0) + +#define UART_I2C_MASTER_GENERATE_NACK \ + do{ \ + UART_I2C_MASTER_CMD_REG = UART_I2C_MASTER_CMD_M_NACK; \ + }while(0) + +/* Slave commands */ +#define UART_I2C_SLAVE_GENERATE_ACK \ + do{ \ + UART_I2C_SLAVE_CMD_REG = UART_I2C_SLAVE_CMD_S_ACK; \ + }while(0) + +#if (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* Slave NACK generation for EC_AM logic on address phase. Ticket ID #183902 */ + void UART_I2CSlaveNackGeneration(void); + #define UART_I2C_SLAVE_GENERATE_NACK UART_I2CSlaveNackGeneration() + +#else + #define UART_I2C_SLAVE_GENERATE_NACK \ + do{ \ + UART_I2C_SLAVE_CMD_REG = UART_I2C_SLAVE_CMD_S_NACK; \ + }while(0) +#endif /* (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#define UART_I2C_SLAVE_CLEAR_NACK \ + do{ \ + UART_I2C_SLAVE_CMD_REG = 0u; \ + }while(0) + +/* Return 8-bit address. The input address should be 7-bits */ +#define UART_GET_I2C_8BIT_ADDRESS(addr) (((uint32) ((uint32) (addr) << \ + UART_I2C_SLAVE_ADDR_POS)) & \ + UART_I2C_SLAVE_ADDR_MASK) + +#define UART_GET_I2C_7BIT_ADDRESS(addr) ((uint32) (addr) >> UART_I2C_SLAVE_ADDR_POS) + +/* Adjust SDA filter Trim settings */ +#define UART_DEFAULT_I2C_CFG_SDA_FILT_TRIM (0x02u) +#define UART_EC_AM_I2C_CFG_SDA_FILT_TRIM (0x03u) + +#if (UART_CY_SCBIP_V0) + #define UART_SET_I2C_CFG_SDA_FILT_TRIM(sdaTrim) \ + do{ \ + UART_I2C_CFG_REG = \ + ((UART_I2C_CFG_REG & (uint32) ~UART_I2C_CFG_SDA_FILT_TRIM_MASK) | \ + ((uint32) ((uint32) (sdaTrim) <> \ + (UART_DM_SIZE * (pos)) ) + +#if (UART_TX_SDA_MISO_PIN) + #define UART_CHECK_TX_SDA_MISO_PIN_USED \ + (UART_PIN_DM_ALG_HIZ != \ + UART_GET_P4_PIN_DM(UART_uart_tx_i2c_sda_spi_miso_PC, \ + UART_uart_tx_i2c_sda_spi_miso_SHIFT)) +#endif /* (UART_TX_SDA_MISO_PIN) */ + +#if (UART_SS0_PIN) + #define UART_CHECK_SS0_PIN_USED \ + (UART_PIN_DM_ALG_HIZ != \ + UART_GET_P4_PIN_DM(UART_spi_ss0_PC, \ + UART_spi_ss0_SHIFT)) +#endif /* (UART_SS0_PIN) */ + +/* Set bits-mask in register */ +#define UART_SET_REGISTER_BITS(reg, mask, pos, mode) \ + do \ + { \ + (reg) = (((reg) & ((uint32) ~(uint32) (mask))) | ((uint32) ((uint32) (mode) << (pos)))); \ + }while(0) + +/* Set bit in the register */ +#define UART_SET_REGISTER_BIT(reg, mask, val) \ + ((val) ? ((reg) |= (mask)) : ((reg) &= ((uint32) ~((uint32) (mask))))) + +#define UART_SET_HSIOM_SEL(reg, mask, pos, sel) UART_SET_REGISTER_BITS(reg, mask, pos, sel) +#define UART_SET_INCFG_TYPE(reg, mask, pos, intType) \ + UART_SET_REGISTER_BITS(reg, mask, pos, intType) +#define UART_SET_INP_DIS(reg, mask, val) UART_SET_REGISTER_BIT(reg, mask, val) + +/* UART_SET_I2C_SCL_DR(val) - Sets I2C SCL DR register. +* UART_SET_I2C_SCL_HSIOM_SEL(sel) - Sets I2C SCL HSIOM settings. +*/ +/* SCB I2C: scl signal */ +#if (UART_CY_SCBIP_V0) +#if (UART_I2C_PINS) + #define UART_SET_I2C_SCL_DR(val) UART_scl_Write(val) + + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_SET_HSIOM_SEL(UART_SCL_HSIOM_REG, \ + UART_SCL_HSIOM_MASK, \ + UART_SCL_HSIOM_POS, \ + (sel)) + #define UART_WAIT_SCL_SET_HIGH (0u == UART_scl_Read()) + +/* Unconfigured SCB: scl signal */ +#elif (UART_RX_WAKE_SCL_MOSI_PIN) + #define UART_SET_I2C_SCL_DR(val) \ + UART_uart_rx_wake_i2c_scl_spi_mosi_Write(val) + + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_SET_HSIOM_SEL(UART_RX_WAKE_SCL_MOSI_HSIOM_REG, \ + UART_RX_WAKE_SCL_MOSI_HSIOM_MASK, \ + UART_RX_WAKE_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define UART_WAIT_SCL_SET_HIGH (0u == UART_uart_rx_wake_i2c_scl_spi_mosi_Read()) + +#elif (UART_RX_SCL_MOSI_PIN) + #define UART_SET_I2C_SCL_DR(val) \ + UART_uart_rx_i2c_scl_spi_mosi_Write(val) + + + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_SET_HSIOM_SEL(UART_RX_SCL_MOSI_HSIOM_REG, \ + UART_RX_SCL_MOSI_HSIOM_MASK, \ + UART_RX_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define UART_WAIT_SCL_SET_HIGH (0u == UART_uart_rx_i2c_scl_spi_mosi_Read()) + +#else + #define UART_SET_I2C_SCL_DR(val) do{ /* Does nothing */ }while(0) + #define UART_SET_I2C_SCL_HSIOM_SEL(sel) do{ /* Does nothing */ }while(0) + + #define UART_WAIT_SCL_SET_HIGH (0u) +#endif /* (UART_I2C_PINS) */ + +/* SCB I2C: sda signal */ +#if (UART_I2C_PINS) + #define UART_WAIT_SDA_SET_HIGH (0u == UART_sda_Read()) +/* Unconfigured SCB: sda signal */ +#elif (UART_TX_SDA_MISO_PIN) + #define UART_WAIT_SDA_SET_HIGH (0u == UART_uart_tx_i2c_sda_spi_miso_Read()) +#else + #define UART_WAIT_SDA_SET_HIGH (0u) +#endif /* (UART_MOSI_SCL_RX_PIN) */ +#endif /* (UART_CY_SCBIP_V0) */ + +/* Clear UART wakeup source */ +#if (UART_RX_SCL_MOSI_PIN) + #define UART_CLEAR_UART_RX_WAKE_INTR do{ /* Does nothing */ }while(0) + +#elif (UART_RX_WAKE_SCL_MOSI_PIN) + #define UART_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) UART_uart_rx_wake_i2c_scl_spi_mosi_ClearInterrupt(); \ + }while(0) + +#elif(UART_UART_RX_WAKE_PIN) + #define UART_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) UART_rx_wake_ClearInterrupt(); \ + }while(0) +#else +#endif /* (UART_RX_SCL_MOSI_PIN) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Unconfigured pins */ +#define UART_REMOVE_MOSI_SCL_RX_WAKE_PIN UART_REMOVE_RX_WAKE_SCL_MOSI_PIN +#define UART_REMOVE_MOSI_SCL_RX_PIN UART_REMOVE_RX_SCL_MOSI_PIN +#define UART_REMOVE_MISO_SDA_TX_PIN UART_REMOVE_TX_SDA_MISO_PIN +#ifndef UART_REMOVE_SCLK_PIN +#define UART_REMOVE_SCLK_PIN UART_REMOVE_SCLK_PIN +#endif /* UART_REMOVE_SCLK_PIN */ +#ifndef UART_REMOVE_SS0_PIN +#define UART_REMOVE_SS0_PIN UART_REMOVE_SS0_PIN +#endif /* UART_REMOVE_SS0_PIN */ + +/* Unconfigured pins */ +#define UART_MOSI_SCL_RX_WAKE_PIN UART_RX_WAKE_SCL_MOSI_PIN +#define UART_MOSI_SCL_RX_PIN UART_RX_SCL_MOSI_PIN +#define UART_MISO_SDA_TX_PIN UART_TX_SDA_MISO_PIN +#ifndef UART_SCLK_PIN +#define UART_SCLK_PIN UART_SCLK_PIN +#endif /* UART_SCLK_PIN */ +#ifndef UART_SS0_PIN +#define UART_SS0_PIN UART_SS0_PIN +#endif /* UART_SS0_PIN */ + +#if (UART_MOSI_SCL_RX_WAKE_PIN) + #define UART_MOSI_SCL_RX_WAKE_HSIOM_REG UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_HSIOM_PTR UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_HSIOM_MASK UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_HSIOM_POS UART_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define UART_MOSI_SCL_RX_WAKE_INTCFG_REG UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_INTCFG_PTR UART_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define UART_MOSI_SCL_RX_WAKE_INTCFG_TYPE_POS UART_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_WAKE_INTCFG_TYPE_MASK UART_RX_WAKE_SCL_MOSI_HSIOM_REG +#endif /* (UART_RX_WAKE_SCL_MOSI_PIN) */ + +#if (UART_MOSI_SCL_RX_PIN) + #define UART_MOSI_SCL_RX_HSIOM_REG UART_RX_SCL_MOSI_HSIOM_REG + #define UART_MOSI_SCL_RX_HSIOM_PTR UART_RX_SCL_MOSI_HSIOM_PTR + #define UART_MOSI_SCL_RX_HSIOM_MASK UART_RX_SCL_MOSI_HSIOM_MASK + #define UART_MOSI_SCL_RX_HSIOM_POS UART_RX_SCL_MOSI_HSIOM_POS +#endif /* (UART_MOSI_SCL_RX_PIN) */ + +#if (UART_MISO_SDA_TX_PIN) + #define UART_MISO_SDA_TX_HSIOM_REG UART_TX_SDA_MISO_HSIOM_REG + #define UART_MISO_SDA_TX_HSIOM_PTR UART_TX_SDA_MISO_HSIOM_REG + #define UART_MISO_SDA_TX_HSIOM_MASK UART_TX_SDA_MISO_HSIOM_REG + #define UART_MISO_SDA_TX_HSIOM_POS UART_TX_SDA_MISO_HSIOM_REG +#endif /* (UART_MISO_SDA_TX_PIN_PIN) */ + +#if (UART_SCLK_PIN) + #ifndef UART_SCLK_HSIOM_REG + #define UART_SCLK_HSIOM_REG UART_SCLK_HSIOM_REG + #define UART_SCLK_HSIOM_PTR UART_SCLK_HSIOM_PTR + #define UART_SCLK_HSIOM_MASK UART_SCLK_HSIOM_MASK + #define UART_SCLK_HSIOM_POS UART_SCLK_HSIOM_POS + #endif /* UART_SCLK_HSIOM_REG */ +#endif /* (UART_SCLK_PIN) */ + +#if (UART_SS0_PIN) + #ifndef UART_SS0_HSIOM_REG + #define UART_SS0_HSIOM_REG UART_SS0_HSIOM_REG + #define UART_SS0_HSIOM_PTR UART_SS0_HSIOM_PTR + #define UART_SS0_HSIOM_MASK UART_SS0_HSIOM_MASK + #define UART_SS0_HSIOM_POS UART_SS0_HSIOM_POS + #endif /* UART_SS0_HSIOM_REG */ +#endif /* (UART_SS0_PIN) */ + +#define UART_MOSI_SCL_RX_WAKE_PIN_INDEX UART_RX_WAKE_SCL_MOSI_PIN_INDEX +#define UART_MOSI_SCL_RX_PIN_INDEX UART_RX_SCL_MOSI_PIN_INDEX +#define UART_MISO_SDA_TX_PIN_INDEX UART_TX_SDA_MISO_PIN_INDEX +#ifndef UART_SCLK_PIN_INDEX +#define UART_SCLK_PIN_INDEX UART_SCLK_PIN_INDEX +#endif /* UART_SCLK_PIN_INDEX */ +#ifndef UART_SS0_PIN_INDEX +#define UART_SS0_PIN_INDEX UART_SS0_PIN_INDEX +#endif /* UART_SS0_PIN_INDEX */ + +#define UART_MOSI_SCL_RX_WAKE_PIN_MASK UART_RX_WAKE_SCL_MOSI_PIN_MASK +#define UART_MOSI_SCL_RX_PIN_MASK UART_RX_SCL_MOSI_PIN_MASK +#define UART_MISO_SDA_TX_PIN_MASK UART_TX_SDA_MISO_PIN_MASK +#ifndef UART_SCLK_PIN_MASK +#define UART_SCLK_PIN_MASK UART_SCLK_PIN_MASK +#endif /* UART_SCLK_PIN_MASK */ +#ifndef UART_SS0_PIN_MASK +#define UART_SS0_PIN_MASK UART_SS0_PIN_MASK +#endif /* UART_SS0_PIN_MASK */ + +#endif /* (CY_SCB_PINS_UART_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_PM.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_PM.c new file mode 100644 index 0000000..000a1be --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_PM.c @@ -0,0 +1,223 @@ +/***************************************************************************//** +* \file UART_PM.c +* \version 4.0 +* +* \brief +* This file provides the source code to the Power Management support for +* the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART.h" +#include "UART_PVT.h" + +#if(UART_SCB_MODE_I2C_INC) + #include "UART_I2C_PVT.h" +#endif /* (UART_SCB_MODE_I2C_INC) */ + +#if(UART_SCB_MODE_EZI2C_INC) + #include "UART_EZI2C_PVT.h" +#endif /* (UART_SCB_MODE_EZI2C_INC) */ + +#if(UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) + #include "UART_SPI_UART_PVT.h" +#endif /* (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) */ + + +/*************************************** +* Backup Structure declaration +***************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG || \ + (UART_SCB_MODE_I2C_CONST_CFG && (!UART_I2C_WAKE_ENABLE_CONST)) || \ + (UART_SCB_MODE_EZI2C_CONST_CFG && (!UART_EZI2C_WAKE_ENABLE_CONST)) || \ + (UART_SCB_MODE_SPI_CONST_CFG && (!UART_SPI_WAKE_ENABLE_CONST)) || \ + (UART_SCB_MODE_UART_CONST_CFG && (!UART_UART_WAKE_ENABLE_CONST))) + + UART_BACKUP_STRUCT UART_backup = + { + 0u, /* enableState */ + }; +#endif + + +/******************************************************************************* +* Function Name: UART_Sleep +****************************************************************************//** +* +* Prepares the UART component to enter Deep Sleep. +* The “Enable wakeup from Deep Sleep Mode” selection has an influence on this +* function implementation: +* - Checked: configures the component to be wakeup source from Deep Sleep. +* - Unchecked: stores the current component state (enabled or disabled) and +* disables the component. See SCB_Stop() function for details about component +* disabling. +* +* Call the UART_Sleep() function before calling the +* CyPmSysDeepSleep() function. +* Refer to the PSoC Creator System Reference Guide for more information about +* power management functions and Low power section of this document for the +* selected mode. +* +* This function should not be called before entering Sleep. +* +*******************************************************************************/ +void UART_Sleep(void) +{ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + if(UART_SCB_WAKE_ENABLE_CHECK) + { + if(UART_SCB_MODE_I2C_RUNTM_CFG) + { + UART_I2CSaveConfig(); + } + else if(UART_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_EzI2CSaveConfig(); + } + #if(!UART_CY_SCBIP_V1) + else if(UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiSaveConfig(); + } + else if(UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartSaveConfig(); + } + #endif /* (!UART_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + UART_backup.enableState = (uint8) UART_GET_CTRL_ENABLED; + + if(0u != UART_backup.enableState) + { + UART_Stop(); + } + } + +#else + + #if (UART_SCB_MODE_I2C_CONST_CFG && UART_I2C_WAKE_ENABLE_CONST) + UART_I2CSaveConfig(); + + #elif (UART_SCB_MODE_EZI2C_CONST_CFG && UART_EZI2C_WAKE_ENABLE_CONST) + UART_EzI2CSaveConfig(); + + #elif (UART_SCB_MODE_SPI_CONST_CFG && UART_SPI_WAKE_ENABLE_CONST) + UART_SpiSaveConfig(); + + #elif (UART_SCB_MODE_UART_CONST_CFG && UART_UART_WAKE_ENABLE_CONST) + UART_UartSaveConfig(); + + #else + + UART_backup.enableState = (uint8) UART_GET_CTRL_ENABLED; + + if(0u != UART_backup.enableState) + { + UART_Stop(); + } + + #endif /* defined (UART_SCB_MODE_I2C_CONST_CFG) && (UART_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_Wakeup +****************************************************************************//** +* +* Prepares the UART component for Active mode operation after +* Deep Sleep. +* The “Enable wakeup from Deep Sleep Mode” selection has influence on this +* function implementation: +* - Checked: restores the component Active mode configuration. +* - Unchecked: enables the component if it was enabled before enter Deep Sleep. +* +* This function should not be called after exiting Sleep. +* +* \sideeffect +* Calling the UART_Wakeup() function without first calling the +* UART_Sleep() function may produce unexpected behavior. +* +*******************************************************************************/ +void UART_Wakeup(void) +{ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + if(UART_SCB_WAKE_ENABLE_CHECK) + { + if(UART_SCB_MODE_I2C_RUNTM_CFG) + { + UART_I2CRestoreConfig(); + } + else if(UART_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_EzI2CRestoreConfig(); + } + #if(!UART_CY_SCBIP_V1) + else if(UART_SCB_MODE_SPI_RUNTM_CFG) + { + UART_SpiRestoreConfig(); + } + else if(UART_SCB_MODE_UART_RUNTM_CFG) + { + UART_UartRestoreConfig(); + } + #endif /* (!UART_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + if(0u != UART_backup.enableState) + { + UART_Enable(); + } + } + +#else + + #if (UART_SCB_MODE_I2C_CONST_CFG && UART_I2C_WAKE_ENABLE_CONST) + UART_I2CRestoreConfig(); + + #elif (UART_SCB_MODE_EZI2C_CONST_CFG && UART_EZI2C_WAKE_ENABLE_CONST) + UART_EzI2CRestoreConfig(); + + #elif (UART_SCB_MODE_SPI_CONST_CFG && UART_SPI_WAKE_ENABLE_CONST) + UART_SpiRestoreConfig(); + + #elif (UART_SCB_MODE_UART_CONST_CFG && UART_UART_WAKE_ENABLE_CONST) + UART_UartRestoreConfig(); + + #else + + if(0u != UART_backup.enableState) + { + UART_Enable(); + } + + #endif /* (UART_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_PVT.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_PVT.h new file mode 100644 index 0000000..aa1d516 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_PVT.h @@ -0,0 +1,123 @@ +/***************************************************************************//** +* \file .h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_PVT_UART_H) +#define CY_SCB_PVT_UART_H + +#include "UART.h" + + +/*************************************** +* Private Function Prototypes +***************************************/ + +/* APIs to service INTR_I2C_EC register */ +#define UART_SetI2CExtClkInterruptMode(interruptMask) UART_WRITE_INTR_I2C_EC_MASK(interruptMask) +#define UART_ClearI2CExtClkInterruptSource(interruptMask) UART_CLEAR_INTR_I2C_EC(interruptMask) +#define UART_GetI2CExtClkInterruptSource() (UART_INTR_I2C_EC_REG) +#define UART_GetI2CExtClkInterruptMode() (UART_INTR_I2C_EC_MASK_REG) +#define UART_GetI2CExtClkInterruptSourceMasked() (UART_INTR_I2C_EC_MASKED_REG) + +#if (!UART_CY_SCBIP_V1) + /* APIs to service INTR_SPI_EC register */ + #define UART_SetSpiExtClkInterruptMode(interruptMask) \ + UART_WRITE_INTR_SPI_EC_MASK(interruptMask) + #define UART_ClearSpiExtClkInterruptSource(interruptMask) \ + UART_CLEAR_INTR_SPI_EC(interruptMask) + #define UART_GetExtSpiClkInterruptSource() (UART_INTR_SPI_EC_REG) + #define UART_GetExtSpiClkInterruptMode() (UART_INTR_SPI_EC_MASK_REG) + #define UART_GetExtSpiClkInterruptSourceMasked() (UART_INTR_SPI_EC_MASKED_REG) +#endif /* (!UART_CY_SCBIP_V1) */ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + extern void UART_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if (UART_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + extern cyisraddress UART_customIntrHandler; +#endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ +#endif /* (UART_SCB_IRQ_INTERNAL) */ + +extern UART_BACKUP_STRUCT UART_backup; + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + extern uint8 UART_scbMode; + extern uint8 UART_scbEnableWake; + extern uint8 UART_scbEnableIntr; + + /* I2C configuration variables */ + extern uint8 UART_mode; + extern uint8 UART_acceptAddr; + + /* SPI/UART configuration variables */ + extern volatile uint8 * UART_rxBuffer; + extern uint8 UART_rxDataBits; + extern uint32 UART_rxBufferSize; + + extern volatile uint8 * UART_txBuffer; + extern uint8 UART_txDataBits; + extern uint32 UART_txBufferSize; + + /* EZI2C configuration variables */ + extern uint8 UART_numberOfAddr; + extern uint8 UART_subAddrSize; +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) + extern uint16 UART_IntrTxMask; +#endif /* (! (UART_SCB_MODE_I2C_CONST_CFG || \ + UART_SCB_MODE_EZI2C_CONST_CFG)) */ + + +/*************************************** +* Conditional Macro +****************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* Defines run time operation mode */ + #define UART_SCB_MODE_I2C_RUNTM_CFG (UART_SCB_MODE_I2C == UART_scbMode) + #define UART_SCB_MODE_SPI_RUNTM_CFG (UART_SCB_MODE_SPI == UART_scbMode) + #define UART_SCB_MODE_UART_RUNTM_CFG (UART_SCB_MODE_UART == UART_scbMode) + #define UART_SCB_MODE_EZI2C_RUNTM_CFG (UART_SCB_MODE_EZI2C == UART_scbMode) + #define UART_SCB_MODE_UNCONFIG_RUNTM_CFG \ + (UART_SCB_MODE_UNCONFIG == UART_scbMode) + + /* Defines wakeup enable */ + #define UART_SCB_WAKE_ENABLE_CHECK (0u != UART_scbEnableWake) +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +/* Defines maximum number of SCB pins */ +#if (!UART_CY_SCBIP_V1) + #define UART_SCB_PINS_NUMBER (7u) +#else + #define UART_SCB_PINS_NUMBER (2u) +#endif /* (!UART_CY_SCBIP_V1) */ + +#endif /* (CY_SCB_PVT_UART_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SCBCLK.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SCBCLK.c new file mode 100644 index 0000000..4205404 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SCBCLK.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: UART_SCBCLK.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "UART_SCBCLK.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: UART_SCBCLK_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void UART_SCBCLK_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((UART_SCBCLK_CMD_REG & UART_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + UART_SCBCLK_CMD_REG = + ((uint32)UART_SCBCLK__DIV_ID << UART_SCBCLK_CMD_DIV_SHIFT)| + (alignClkDiv << UART_SCBCLK_CMD_PA_DIV_SHIFT) | + (uint32)UART_SCBCLK_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: UART_SCBCLK_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void UART_SCBCLK_Start(void) +{ + /* Set the bit to enable the clock. */ + UART_SCBCLK_ENABLE_REG |= UART_SCBCLK__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: UART_SCBCLK_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void UART_SCBCLK_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((UART_SCBCLK_CMD_REG & UART_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + UART_SCBCLK_CMD_REG = + ((uint32)UART_SCBCLK__DIV_ID << UART_SCBCLK_CMD_DIV_SHIFT)| + ((uint32)UART_SCBCLK_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + UART_SCBCLK_ENABLE_REG &= (uint32)(~UART_SCBCLK__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: UART_SCBCLK_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void UART_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (UART_SCBCLK__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = UART_SCBCLK_DIV_REG & + (uint32)(~(uint32)(UART_SCBCLK_DIV_INT_MASK | UART_SCBCLK_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << UART_SCBCLK_DIV_INT_SHIFT) & UART_SCBCLK_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << UART_SCBCLK_DIV_FRAC_SHIFT) & UART_SCBCLK_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = UART_SCBCLK_DIV_REG & (uint32)(~(uint32)UART_SCBCLK__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* UART_SCBCLK__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + UART_SCBCLK_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: UART_SCBCLK_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 UART_SCBCLK_GetDividerRegister(void) +{ + return (uint16)((UART_SCBCLK_DIV_REG & UART_SCBCLK_DIV_INT_MASK) + >> UART_SCBCLK_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_SCBCLK_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 UART_SCBCLK_GetFractionalDividerRegister(void) +{ +#if defined (UART_SCBCLK__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((UART_SCBCLK_DIV_REG & UART_SCBCLK_DIV_FRAC_MASK) + >> UART_SCBCLK_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* UART_SCBCLK__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SCBCLK.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SCBCLK.h new file mode 100644 index 0000000..65b74d1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SCBCLK.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* File Name: UART_SCBCLK.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_UART_SCBCLK_H) +#define CY_CLOCK_UART_SCBCLK_H + +#include +#include + + +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void UART_SCBCLK_StartEx(uint32 alignClkDiv); +#define UART_SCBCLK_Start() \ + UART_SCBCLK_StartEx(UART_SCBCLK__PA_DIV_ID) + +#else + +void UART_SCBCLK_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void UART_SCBCLK_Stop(void); + +void UART_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 UART_SCBCLK_GetDividerRegister(void); +uint8 UART_SCBCLK_GetFractionalDividerRegister(void); + +#define UART_SCBCLK_Enable() UART_SCBCLK_Start() +#define UART_SCBCLK_Disable() UART_SCBCLK_Stop() +#define UART_SCBCLK_SetDividerRegister(clkDivider, reset) \ + UART_SCBCLK_SetFractionalDividerRegister((clkDivider), 0u) +#define UART_SCBCLK_SetDivider(clkDivider) UART_SCBCLK_SetDividerRegister((clkDivider), 1u) +#define UART_SCBCLK_SetDividerValue(clkDivider) UART_SCBCLK_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define UART_SCBCLK_DIV_ID UART_SCBCLK__DIV_ID + +#define UART_SCBCLK_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define UART_SCBCLK_CTRL_REG (*(reg32 *)UART_SCBCLK__CTRL_REGISTER) +#define UART_SCBCLK_DIV_REG (*(reg32 *)UART_SCBCLK__DIV_REGISTER) + +#define UART_SCBCLK_CMD_DIV_SHIFT (0u) +#define UART_SCBCLK_CMD_PA_DIV_SHIFT (8u) +#define UART_SCBCLK_CMD_DISABLE_SHIFT (30u) +#define UART_SCBCLK_CMD_ENABLE_SHIFT (31u) + +#define UART_SCBCLK_CMD_DISABLE_MASK ((uint32)((uint32)1u << UART_SCBCLK_CMD_DISABLE_SHIFT)) +#define UART_SCBCLK_CMD_ENABLE_MASK ((uint32)((uint32)1u << UART_SCBCLK_CMD_ENABLE_SHIFT)) + +#define UART_SCBCLK_DIV_FRAC_MASK (0x000000F8u) +#define UART_SCBCLK_DIV_FRAC_SHIFT (3u) +#define UART_SCBCLK_DIV_INT_MASK (0xFFFFFF00u) +#define UART_SCBCLK_DIV_INT_SHIFT (8u) + +#else + +#define UART_SCBCLK_DIV_REG (*(reg32 *)UART_SCBCLK__REGISTER) +#define UART_SCBCLK_ENABLE_REG UART_SCBCLK_DIV_REG +#define UART_SCBCLK_DIV_FRAC_MASK UART_SCBCLK__FRAC_MASK +#define UART_SCBCLK_DIV_FRAC_SHIFT (16u) +#define UART_SCBCLK_DIV_INT_MASK UART_SCBCLK__DIVIDER_MASK +#define UART_SCBCLK_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_UART_SCBCLK_H) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART.c new file mode 100644 index 0000000..4db5689 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART.c @@ -0,0 +1,603 @@ +/***************************************************************************//** +* \file UART_SPI_UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" +#include "UART_SPI_UART_PVT.h" + +/*************************************** +* SPI/UART Private Vars +***************************************/ + +#if(UART_INTERNAL_RX_SW_BUFFER_CONST) + /* Start index to put data into the software receive buffer.*/ + volatile uint32 UART_rxBufferHead; + /* Start index to get data from the software receive buffer.*/ + volatile uint32 UART_rxBufferTail; + /** + * \addtogroup group_globals + * \{ + */ + /** Sets when internal software receive buffer overflow + * was occurred. + */ + volatile uint8 UART_rxBufferOverflow; + /** \} globals */ +#endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if(UART_INTERNAL_TX_SW_BUFFER_CONST) + /* Start index to put data into the software transmit buffer.*/ + volatile uint32 UART_txBufferHead; + /* Start index to get data from the software transmit buffer.*/ + volatile uint32 UART_txBufferTail; +#endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if(UART_INTERNAL_RX_SW_BUFFER) + /* Add one element to the buffer to receive full packet. One byte in receive buffer is always empty */ + volatile uint8 UART_rxBufferInternal[UART_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_RX_SW_BUFFER) */ + +#if(UART_INTERNAL_TX_SW_BUFFER) + volatile uint8 UART_txBufferInternal[UART_TX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_TX_SW_BUFFER) */ + + +#if(UART_RX_DIRECTION) + /******************************************************************************* + * Function Name: UART_SpiUartReadRxData + ****************************************************************************//** + * + * Retrieves the next data element from the receive buffer. + * - RX software buffer is disabled: Returns data element retrieved from + * RX FIFO. Undefined data will be returned if the RX FIFO is empty. + * - RX software buffer is enabled: Returns data element from the software + * receive buffer. Zero value is returned if the software receive buffer + * is empty. + * + * \return + * Next data element from the receive buffer. + * The amount of data bits to be received depends on RX data bits selection + * (the data bit counting starts from LSB of return value). + * + * \globalvars + * UART_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 UART_SpiUartReadRxData(void) + { + uint32 rxData = 0u; + + #if (UART_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_RX_SW_BUFFER) + { + if (UART_rxBufferHead != UART_rxBufferTail) + { + /* There is data in RX software buffer */ + + /* Calculate index to read from */ + locTail = (UART_rxBufferTail + 1u); + + if (UART_INTERNAL_RX_BUFFER_SIZE == locTail) + { + locTail = 0u; + } + + /* Get data from RX software buffer */ + rxData = UART_GetWordFromRxBuffer(locTail); + + /* Change index in the buffer */ + UART_rxBufferTail = locTail; + + #if (UART_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Check if RX Not Empty is disabled in the interrupt */ + if (0u == (UART_INTR_RX_MASK_REG & UART_INTR_RX_NOT_EMPTY)) + { + /* Enable RX Not Empty interrupt source to continue + * receiving data into software buffer. + */ + UART_INTR_RX_MASK_REG |= UART_INTR_RX_NOT_EMPTY; + } + } + #endif + + } + } + #else + { + /* Read data from RX FIFO */ + rxData = UART_RX_FIFO_RD_REG; + } + #endif + + return (rxData); + } + + + /******************************************************************************* + * Function Name: UART_SpiUartGetRxBufferSize + ****************************************************************************//** + * + * Returns the number of received data elements in the receive buffer. + * - RX software buffer disabled: returns the number of used entries in + * RX FIFO. + * - RX software buffer enabled: returns the number of elements which were + * placed in the receive buffer. This does not include the hardware RX FIFO. + * + * \return + * Number of received data elements. + * + * \globalvars + * UART_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 UART_SpiUartGetRxBufferSize(void) + { + uint32 size; + #if (UART_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_RX_SW_BUFFER) + { + locHead = UART_rxBufferHead; + + if(locHead >= UART_rxBufferTail) + { + size = (locHead - UART_rxBufferTail); + } + else + { + size = (locHead + (UART_INTERNAL_RX_BUFFER_SIZE - UART_rxBufferTail)); + } + } + #else + { + size = UART_GET_RX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: UART_SpiUartClearRxBuffer + ****************************************************************************//** + * + * Clears the receive buffer and RX FIFO. + * + * \globalvars + * UART_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + void UART_SpiUartClearRxBuffer(void) + { + #if (UART_CHECK_RX_SW_BUFFER) + { + /* Lock from component interruption */ + UART_DisableInt(); + + /* Flush RX software buffer */ + UART_rxBufferHead = UART_rxBufferTail; + UART_rxBufferOverflow = 0u; + + UART_CLEAR_RX_FIFO; + UART_ClearRxInterruptSource(UART_INTR_RX_ALL); + + #if (UART_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Enable RX Not Empty interrupt source to continue receiving + * data into software buffer. + */ + UART_INTR_RX_MASK_REG |= UART_INTR_RX_NOT_EMPTY; + } + #endif + + /* Release lock */ + UART_EnableInt(); + } + #else + { + UART_CLEAR_RX_FIFO; + } + #endif + } + +#endif /* (UART_RX_DIRECTION) */ + + +#if(UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_SpiUartWriteTxData + ****************************************************************************//** + * + * Places a data entry into the transmit buffer to be sent at the next available + * bus time. + * This function is blocking and waits until there is space available to put the + * requested data in the transmit buffer. + * + * \param txDataByte: the data to be transmitted. + * The amount of data bits to be transmitted depends on TX data bits selection + * (the data bit counting starts from LSB of txDataByte). + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_SpiUartWriteTxData(uint32 txData) + { + #if (UART_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_TX_SW_BUFFER) + { + /* Put data directly into the TX FIFO */ + if ((UART_txBufferHead == UART_txBufferTail) && + (UART_SPI_UART_FIFO_SIZE != UART_GET_TX_FIFO_ENTRIES)) + { + /* TX software buffer is empty: put data directly in TX FIFO */ + UART_TX_FIFO_WR_REG = txData; + } + /* Put data into TX software buffer */ + else + { + /* Head index to put data */ + locHead = (UART_txBufferHead + 1u); + + /* Adjust TX software buffer index */ + if (UART_TX_BUFFER_SIZE == locHead) + { + locHead = 0u; + } + + /* Wait for space in TX software buffer */ + while (locHead == UART_txBufferTail) + { + } + + /* TX software buffer has at least one room */ + + /* Clear old status of INTR_TX_NOT_FULL. It sets at the end of transfer when TX FIFO is empty. */ + UART_ClearTxInterruptSource(UART_INTR_TX_NOT_FULL); + + UART_PutWordInTxBuffer(locHead, txData); + + UART_txBufferHead = locHead; + + /* Check if TX Not Full is disabled in interrupt */ + if (0u == (UART_INTR_TX_MASK_REG & UART_INTR_TX_NOT_FULL)) + { + /* Enable TX Not Full interrupt source to transmit from software buffer */ + UART_INTR_TX_MASK_REG |= (uint32) UART_INTR_TX_NOT_FULL; + } + } + } + #else + { + /* Wait until TX FIFO has space to put data element */ + while (UART_SPI_UART_FIFO_SIZE == UART_GET_TX_FIFO_ENTRIES) + { + } + + UART_TX_FIFO_WR_REG = txData; + } + #endif + } + + + /******************************************************************************* + * Function Name: UART_SpiUartPutArray + ****************************************************************************//** + * + * Places an array of data into the transmit buffer to be sent. + * This function is blocking and waits until there is a space available to put + * all the requested data in the transmit buffer. The array size can be greater + * than transmit buffer size. + * + * \param wrBuf: pointer to an array of data to be placed in transmit buffer. + * The width of the data to be transmitted depends on TX data width selection + * (the data bit counting starts from LSB for each array element). + * \param count: number of data elements to be placed in the transmit buffer. + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_SpiUartPutArray(const uint8 wrBuf[], uint32 count) + { + uint32 i; + + for (i=0u; i < count; i++) + { + UART_SpiUartWriteTxData((uint32) wrBuf[i]); + } + } + + + /******************************************************************************* + * Function Name: UART_SpiUartGetTxBufferSize + ****************************************************************************//** + * + * Returns the number of elements currently in the transmit buffer. + * - TX software buffer is disabled: returns the number of used entries in + * TX FIFO. + * - TX software buffer is enabled: returns the number of elements currently + * used in the transmit buffer. This number does not include used entries in + * the TX FIFO. The transmit buffer size is zero until the TX FIFO is + * not full. + * + * \return + * Number of data elements ready to transmit. + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + uint32 UART_SpiUartGetTxBufferSize(void) + { + uint32 size; + #if (UART_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (UART_CHECK_TX_SW_BUFFER) + { + /* Get current Tail index */ + locTail = UART_txBufferTail; + + if (UART_txBufferHead >= locTail) + { + size = (UART_txBufferHead - locTail); + } + else + { + size = (UART_txBufferHead + (UART_TX_BUFFER_SIZE - locTail)); + } + } + #else + { + size = UART_GET_TX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: UART_SpiUartClearTxBuffer + ****************************************************************************//** + * + * Clears the transmit buffer and TX FIFO. + * + * \globalvars + * UART_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_SpiUartClearTxBuffer(void) + { + #if (UART_CHECK_TX_SW_BUFFER) + { + /* Lock from component interruption */ + UART_DisableInt(); + + /* Flush TX software buffer */ + UART_txBufferHead = UART_txBufferTail; + + UART_INTR_TX_MASK_REG &= (uint32) ~UART_INTR_TX_NOT_FULL; + UART_CLEAR_TX_FIFO; + UART_ClearTxInterruptSource(UART_INTR_TX_ALL); + + /* Release lock */ + UART_EnableInt(); + } + #else + { + UART_CLEAR_TX_FIFO; + } + #endif + } + +#endif /* (UART_TX_DIRECTION) */ + + +/******************************************************************************* +* Function Name: UART_SpiUartDisableIntRx +****************************************************************************//** +* +* Disables the RX interrupt sources. +* +* \return +* Returns the RX interrupt sources enabled before the function call. +* +*******************************************************************************/ +uint32 UART_SpiUartDisableIntRx(void) +{ + uint32 intSource; + + intSource = UART_GetRxInterruptMode(); + + UART_SetRxInterruptMode(UART_NO_INTR_SOURCES); + + return (intSource); +} + + +/******************************************************************************* +* Function Name: UART_SpiUartDisableIntTx +****************************************************************************//** +* +* Disables TX interrupt sources. +* +* \return +* Returns TX interrupt sources enabled before function call. +* +*******************************************************************************/ +uint32 UART_SpiUartDisableIntTx(void) +{ + uint32 intSourceMask; + + intSourceMask = UART_GetTxInterruptMode(); + + UART_SetTxInterruptMode(UART_NO_INTR_SOURCES); + + return (intSourceMask); +} + + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: UART_PutWordInRxBuffer + ****************************************************************************//** + * + * Stores a byte/word into the RX buffer. + * Only available in the Unconfigured operation mode. + * + * \param index: index to store data byte/word in the RX buffer. + * \param rxDataByte: byte/word to store. + * + *******************************************************************************/ + void UART_PutWordInRxBuffer(uint32 idx, uint32 rxDataByte) + { + /* Put data in buffer */ + if (UART_ONE_BYTE_WIDTH == UART_rxDataBits) + { + UART_rxBuffer[idx] = ((uint8) rxDataByte); + } + else + { + UART_rxBuffer[(uint32)(idx << 1u)] = LO8(LO16(rxDataByte)); + UART_rxBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(rxDataByte)); + } + } + + + /******************************************************************************* + * Function Name: UART_GetWordFromRxBuffer + ****************************************************************************//** + * + * Reads byte/word from RX buffer. + * Only available in the Unconfigured operation mode. + * + * \return + * Returns byte/word read from RX buffer. + * + *******************************************************************************/ + uint32 UART_GetWordFromRxBuffer(uint32 idx) + { + uint32 value; + + if (UART_ONE_BYTE_WIDTH == UART_rxDataBits) + { + value = UART_rxBuffer[idx]; + } + else + { + value = (uint32) UART_rxBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32)UART_rxBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + + + /******************************************************************************* + * Function Name: UART_PutWordInTxBuffer + ****************************************************************************//** + * + * Stores byte/word into the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to store data byte/word in the TX buffer. + * \param txDataByte: byte/word to store. + * + *******************************************************************************/ + void UART_PutWordInTxBuffer(uint32 idx, uint32 txDataByte) + { + /* Put data in buffer */ + if (UART_ONE_BYTE_WIDTH == UART_txDataBits) + { + UART_txBuffer[idx] = ((uint8) txDataByte); + } + else + { + UART_txBuffer[(uint32)(idx << 1u)] = LO8(LO16(txDataByte)); + UART_txBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(txDataByte)); + } + } + + + /******************************************************************************* + * Function Name: UART_GetWordFromTxBuffer + ****************************************************************************//** + * + * Reads byte/word from the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to get data byte/word from the TX buffer. + * + * \return + * Returns byte/word read from the TX buffer. + * + *******************************************************************************/ + uint32 UART_GetWordFromTxBuffer(uint32 idx) + { + uint32 value; + + if (UART_ONE_BYTE_WIDTH == UART_txDataBits) + { + value = (uint32) UART_txBuffer[idx]; + } + else + { + value = (uint32) UART_txBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32) UART_txBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART.h new file mode 100644 index 0000000..3e2b602 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART.h @@ -0,0 +1,1231 @@ +/***************************************************************************//** +* \file UART_SPI_UART.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_SPI_UART_UART_H) +#define CY_SCB_SPI_UART_UART_H + +#include "UART.h" + + +/*************************************** +* SPI Initial Parameter Constants +****************************************/ + +#define UART_SPI_MODE (0u) +#define UART_SPI_SUB_MODE (0u) +#define UART_SPI_CLOCK_MODE (0u) +#define UART_SPI_OVS_FACTOR (16u) +#define UART_SPI_MEDIAN_FILTER_ENABLE (0u) +#define UART_SPI_LATE_MISO_SAMPLE_ENABLE (0u) +#define UART_SPI_RX_DATA_BITS_NUM (8u) +#define UART_SPI_TX_DATA_BITS_NUM (8u) +#define UART_SPI_WAKE_ENABLE (0u) +#define UART_SPI_BITS_ORDER (1u) +#define UART_SPI_TRANSFER_SEPARATION (1u) +#define UART_SPI_NUMBER_OF_SS_LINES (1u) +#define UART_SPI_RX_BUFFER_SIZE (8u) +#define UART_SPI_TX_BUFFER_SIZE (8u) + +#define UART_SPI_INTERRUPT_MODE (1u) + +#define UART_SPI_INTR_RX_MASK (0x0u) +#define UART_SPI_INTR_TX_MASK (0x0u) + +#define UART_SPI_RX_TRIGGER_LEVEL (7u) +#define UART_SPI_TX_TRIGGER_LEVEL (0u) + +#define UART_SPI_BYTE_MODE_ENABLE (0u) +#define UART_SPI_FREE_RUN_SCLK_ENABLE (0u) +#define UART_SPI_SS0_POLARITY (0u) +#define UART_SPI_SS1_POLARITY (0u) +#define UART_SPI_SS2_POLARITY (0u) +#define UART_SPI_SS3_POLARITY (0u) + + +/*************************************** +* UART Initial Parameter Constants +****************************************/ + +#define UART_UART_SUB_MODE (0u) +#define UART_UART_DIRECTION (2u) +#define UART_UART_DATA_BITS_NUM (8u) +#define UART_UART_PARITY_TYPE (2u) +#define UART_UART_STOP_BITS_NUM (2u) +#define UART_UART_OVS_FACTOR (8u) +#define UART_UART_IRDA_LOW_POWER (0u) +#define UART_UART_MEDIAN_FILTER_ENABLE (0u) +#define UART_UART_RETRY_ON_NACK (0u) +#define UART_UART_IRDA_POLARITY (0u) +#define UART_UART_DROP_ON_FRAME_ERR (0u) +#define UART_UART_DROP_ON_PARITY_ERR (0u) +#define UART_UART_WAKE_ENABLE (0u) +#define UART_UART_RX_BUFFER_SIZE (8u) +#define UART_UART_TX_BUFFER_SIZE (8u) +#define UART_UART_MP_MODE_ENABLE (0u) +#define UART_UART_MP_ACCEPT_ADDRESS (0u) +#define UART_UART_MP_RX_ADDRESS (0x2u) +#define UART_UART_MP_RX_ADDRESS_MASK (0xFFu) + +#define UART_UART_INTERRUPT_MODE (0u) + +#define UART_UART_INTR_RX_MASK (0x0u) +#define UART_UART_INTR_TX_MASK (0x0u) + +#define UART_UART_RX_TRIGGER_LEVEL (7u) +#define UART_UART_TX_TRIGGER_LEVEL (0u) + +#define UART_UART_BYTE_MODE_ENABLE (0u) +#define UART_UART_CTS_ENABLE (0u) +#define UART_UART_CTS_POLARITY (0u) +#define UART_UART_RTS_ENABLE (0u) +#define UART_UART_RTS_POLARITY (0u) +#define UART_UART_RTS_FIFO_LEVEL (4u) + +#define UART_UART_RX_BREAK_WIDTH (11u) + +/* SPI mode enum */ +#define UART_SPI_SLAVE (0u) +#define UART_SPI_MASTER (1u) + +/* UART direction enum */ +#define UART_UART_RX (1u) +#define UART_UART_TX (2u) +#define UART_UART_TX_RX (3u) + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + /* Mode */ + #define UART_SPI_SLAVE_CONST (1u) + #define UART_SPI_MASTER_CONST (1u) + + /* Direction */ + #define UART_RX_DIRECTION (1u) + #define UART_TX_DIRECTION (1u) + #define UART_UART_RX_DIRECTION (1u) + #define UART_UART_TX_DIRECTION (1u) + + /* Only external RX and TX buffer for Uncofigured mode */ + #define UART_INTERNAL_RX_SW_BUFFER (0u) + #define UART_INTERNAL_TX_SW_BUFFER (0u) + + /* Get RX and TX buffer size */ + #define UART_INTERNAL_RX_BUFFER_SIZE (UART_rxBufferSize + 1u) + #define UART_RX_BUFFER_SIZE (UART_rxBufferSize) + #define UART_TX_BUFFER_SIZE (UART_txBufferSize) + + /* Return true if buffer is provided */ + #define UART_CHECK_RX_SW_BUFFER (NULL != UART_rxBuffer) + #define UART_CHECK_TX_SW_BUFFER (NULL != UART_txBuffer) + + /* Always provide global variables to support RX and TX buffers */ + #define UART_INTERNAL_RX_SW_BUFFER_CONST (1u) + #define UART_INTERNAL_TX_SW_BUFFER_CONST (1u) + + /* Get wakeup enable option */ + #define UART_SPI_WAKE_ENABLE_CONST (1u) + #define UART_UART_WAKE_ENABLE_CONST (1u) + #define UART_CHECK_SPI_WAKE_ENABLE ((0u != UART_scbEnableWake) && UART_SCB_MODE_SPI_RUNTM_CFG) + #define UART_CHECK_UART_WAKE_ENABLE ((0u != UART_scbEnableWake) && UART_SCB_MODE_UART_RUNTM_CFG) + + /* SPI/UART: TX or RX FIFO size */ + #if (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #define UART_SPI_UART_FIFO_SIZE (UART_FIFO_SIZE) + #define UART_CHECK_UART_RTS_CONTROL_FLOW (0u) + #else + #define UART_SPI_UART_FIFO_SIZE (UART_GET_FIFO_SIZE(UART_CTRL_REG & \ + UART_CTRL_BYTE_MODE)) + + #define UART_CHECK_UART_RTS_CONTROL_FLOW \ + ((UART_SCB_MODE_UART_RUNTM_CFG) && \ + (0u != UART_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(UART_UART_FLOW_CTRL_REG))) + #endif /* (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#else + + /* Internal RX and TX buffer: for SPI or UART */ + #if (UART_SCB_MODE_SPI_CONST_CFG) + + /* SPI Direction */ + #define UART_SPI_RX_DIRECTION (1u) + #define UART_SPI_TX_DIRECTION (1u) + + /* Get FIFO size */ + #define UART_SPI_UART_FIFO_SIZE UART_GET_FIFO_SIZE(UART_SPI_BYTE_MODE_ENABLE) + + /* SPI internal RX and TX buffers */ + #define UART_INTERNAL_SPI_RX_SW_BUFFER (UART_SPI_RX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + #define UART_INTERNAL_SPI_TX_SW_BUFFER (UART_SPI_TX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + + /* Internal SPI RX and TX buffer */ + #define UART_INTERNAL_RX_SW_BUFFER (UART_INTERNAL_SPI_RX_SW_BUFFER) + #define UART_INTERNAL_TX_SW_BUFFER (UART_INTERNAL_SPI_TX_SW_BUFFER) + + /* Internal SPI RX and TX buffer size */ + #define UART_INTERNAL_RX_BUFFER_SIZE (UART_SPI_RX_BUFFER_SIZE + 1u) + #define UART_RX_BUFFER_SIZE (UART_SPI_RX_BUFFER_SIZE) + #define UART_TX_BUFFER_SIZE (UART_SPI_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define UART_SPI_WAKE_ENABLE_CONST (0u != UART_SPI_WAKE_ENABLE) + #define UART_UART_WAKE_ENABLE_CONST (0u) + + #else + + /* UART Direction */ + #define UART_UART_RX_DIRECTION (0u != (UART_UART_DIRECTION & UART_UART_RX)) + #define UART_UART_TX_DIRECTION (0u != (UART_UART_DIRECTION & UART_UART_TX)) + + /* Get FIFO size */ + #define UART_SPI_UART_FIFO_SIZE UART_GET_FIFO_SIZE(UART_UART_BYTE_MODE_ENABLE) + + /* UART internal RX and TX buffers */ + #define UART_INTERNAL_UART_RX_SW_BUFFER (UART_UART_RX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + #define UART_INTERNAL_UART_TX_SW_BUFFER (UART_UART_TX_BUFFER_SIZE > \ + UART_SPI_UART_FIFO_SIZE) + + /* Internal UART RX and TX buffer */ + #define UART_INTERNAL_RX_SW_BUFFER (UART_INTERNAL_UART_RX_SW_BUFFER) + #define UART_INTERNAL_TX_SW_BUFFER (UART_INTERNAL_UART_TX_SW_BUFFER) + + /* Internal UART RX and TX buffer size */ + #define UART_INTERNAL_RX_BUFFER_SIZE (UART_UART_RX_BUFFER_SIZE + 1u) + #define UART_RX_BUFFER_SIZE (UART_UART_RX_BUFFER_SIZE) + #define UART_TX_BUFFER_SIZE (UART_UART_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define UART_SPI_WAKE_ENABLE_CONST (0u) + #define UART_UART_WAKE_ENABLE_CONST (0u != UART_UART_WAKE_ENABLE) + + #endif /* (UART_SCB_MODE_SPI_CONST_CFG) */ + + /* Mode */ + #define UART_SPI_SLAVE_CONST (UART_SPI_MODE == UART_SPI_SLAVE) + #define UART_SPI_MASTER_CONST (UART_SPI_MODE == UART_SPI_MASTER) + + /* Direction */ + #define UART_RX_DIRECTION ((UART_SCB_MODE_SPI_CONST_CFG) ? \ + (UART_SPI_RX_DIRECTION) : (UART_UART_RX_DIRECTION)) + + #define UART_TX_DIRECTION ((UART_SCB_MODE_SPI_CONST_CFG) ? \ + (UART_SPI_TX_DIRECTION) : (UART_UART_TX_DIRECTION)) + + /* Internal RX and TX buffer: for SPI or UART. Used in conditional compilation check */ + #define UART_CHECK_RX_SW_BUFFER (UART_INTERNAL_RX_SW_BUFFER) + #define UART_CHECK_TX_SW_BUFFER (UART_INTERNAL_TX_SW_BUFFER) + + /* Provide global variables to support RX and TX buffers */ + #define UART_INTERNAL_RX_SW_BUFFER_CONST (UART_INTERNAL_RX_SW_BUFFER) + #define UART_INTERNAL_TX_SW_BUFFER_CONST (UART_INTERNAL_TX_SW_BUFFER) + + /* Wake up enable */ + #define UART_CHECK_SPI_WAKE_ENABLE (UART_SPI_WAKE_ENABLE_CONST) + #define UART_CHECK_UART_WAKE_ENABLE (UART_UART_WAKE_ENABLE_CONST) + + /* UART flow control: not applicable for CY_SCBIP_V0 || CY_SCBIP_V1 */ + #define UART_CHECK_UART_RTS_CONTROL_FLOW (UART_SCB_MODE_UART_CONST_CFG && \ + UART_UART_RTS_ENABLE) + +#endif /* End (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* UART_SPI_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for SPI. The following defines are available choices: + * - UART_SPI_SLAVE + * - UART_SPI_MASTE + */ + uint32 mode; + + /** Submode of operation for SPI. The following defines are available + * choices: + * - UART_SPI_MODE_MOTOROLA + * - UART_SPI_MODE_TI_COINCIDES + * - UART_SPI_MODE_TI_PRECEDES + * - UART_SPI_MODE_NATIONAL + */ + uint32 submode; + + /** Determines the sclk relationship for Motorola submode. Ignored + * for other submodes. The following defines are available choices: + * - UART_SPI_SCLK_CPHA0_CPOL0 + * - UART_SPI_SCLK_CPHA0_CPOL1 + * - UART_SPI_SCLK_CPHA1_CPOL0 + * - UART_SPI_SCLK_CPHA1_CPOL1 + */ + uint32 sclkMode; + + /** Oversampling factor for the SPI clock. Ignored for Slave mode operation. + */ + uint32 oversample; + + /** Applies median filter on the input lines: 0 – not applied, 1 – applied. + */ + uint32 enableMedianFilter; + + /** Applies late sampling of MISO line: 0 – not applied, 1 – applied. + * Ignored for slave mode. + */ + uint32 enableLateSampling; + + /** Enables wakeup from low power mode: 0 – disable, 1 – enable. + * Ignored for master mode. + */ + uint32 enableWake; + + /** Number of data bits for RX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 rxDataBits; + + /** Number of data bits for TX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 txDataBits; + + /** Determines the bit ordering. The following defines are available + * choices: + * - UART_BITS_ORDER_LSB_FIRST + * - UART_BITS_ORDER_MSB_FIRST + */ + uint32 bitOrder; + + /** Determines whether transfers are back to back or have SS disabled + * between words. Ignored for slave mode. The following defines are + * available choices: + * - UART_SPI_TRANSFER_CONTINUOUS + * - UART_SPI_TRANSFER_SEPARATED + */ + uint32 transferSeperation; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The UART_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables component interrupt: 0 – disable, 1 – enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of enabled interrupt sources for the RX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_RX_FIFO_LEVEL + * - UART_INTR_RX_NOT_EMPTY + * - UART_INTR_RX_FULL + * - UART_INTR_RX_OVERFLOW + * - UART_INTR_RX_UNDERFLOW + * - UART_INTR_SLAVE_SPI_BUS_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of enabled interrupt sources for the TX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_TX_FIFO_LEVEL + * - UART_INTR_TX_NOT_FULL + * - UART_INTR_TX_EMPTY + * - UART_INTR_TX_OVERFLOW + * - UART_INTR_TX_UNDERFLOW + * - UART_INTR_MASTER_SPI_DONE + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 – disable, 1 – enable. This implies that number of + * TX and RX data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables continuous SCLK generation by the SPI master: 0 – disable, + * 1 – enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableFreeRunSclk; + + /** Active polarity of slave select lines 0-3. This is bit mask where bit + * UART_SPI_SLAVE_SELECT0 corresponds to slave select 0 + * polarity, bit UART_SPI_SLAVE_SELECT1 – slave select 1 + * polarity and so on. Polarity constants are: + * - UART_SPI_SS_ACTIVE_LOW + * - UART_SPI_SS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 polaritySs; +} UART_SPI_INIT_STRUCT; + + +/* UART_UART_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for the UART. The following defines are available + * choices: + * - UART_UART_MODE_STD + * - UART_UART_MODE_SMARTCARD + * - UART_UART_MODE_IRDA + */ + uint32 mode; + + /** Direction of operation for the UART. The following defines are available + * choices: + * - UART_UART_TX_RX + * - UART_UART_RX + * - UART_UART_TX + */ + uint32 direction; + + /** Number of data bits. + */ + uint32 dataBits; + + /** Determines the parity. The following defines are available choices: + * - UART_UART_PARITY_EVEN + * - UART_UART_PARITY_ODD + * - UART_UART_PARITY_NONE + */ + uint32 parity; + + /** Determines the number of stop bits. The following defines are available + * choices: + * - UART_UART_STOP_BITS_1 + * - UART_UART_STOP_BITS_1_5 + * - UART_UART_STOP_BITS_2 + */ + uint32 stopBits; + + /** Oversampling factor for the UART. + * + * Note The oversampling factor values are changed when enableIrdaLowPower + * is enabled: + * - UART_UART_IRDA_LP_OVS16 + * - UART_UART_IRDA_LP_OVS32 + * - UART_UART_IRDA_LP_OVS48 + * - UART_UART_IRDA_LP_OVS96 + * - UART_UART_IRDA_LP_OVS192 + * - UART_UART_IRDA_LP_OVS768 + * - UART_UART_IRDA_LP_OVS1536 + */ + uint32 oversample; + + /** Enables IrDA low power RX mode operation: 0 – disable, 1 – enable. + * The TX functionality does not work when enabled. + */ + uint32 enableIrdaLowPower; + + /** Applies median filter on the input lines: 0 – not applied, 1 – applied. + */ + uint32 enableMedianFilter; + + /** Enables retry when NACK response was received: 0 – disable, 1 – enable. + * Only current content of TX FIFO is re-sent. + * Ignored for modes other than SmartCard. + */ + uint32 enableRetryNack; + + /** Inverts polarity of RX line: 0 – non-inverting, 1 – inverting. + * Ignored for modes other than IrDA. + */ + uint32 enableInvertedRx; + + /** Drop data from RX FIFO if parity error is detected: 0 – disable, + * 1 – enable. + */ + uint32 dropOnParityErr; + + /** Drop data from RX FIFO if a frame error is detected: 0 – disable, + * 1 – enable. + */ + uint32 dropOnFrameErr; + + /** Enables wakeup from low power mode: 0 – disable, 1 – enable. + * Ignored for modes other than standard UART. The RX functionality + * has to be enabled. + */ + uint32 enableWake; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The UART_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables multiprocessor mode: 0 – disable, 1 – enable. + */ + uint32 enableMultiproc; + + /** Enables matched address to be accepted: 0 – disable, 1 – enable. + */ + uint32 multiprocAcceptAddr; + + /** 8 bit address to match in Multiprocessor mode. Ignored for other modes. + */ + uint32 multiprocAddr; + + /** 8 bit mask of address bits that are compared for a Multiprocessor + * address match. Ignored for other modes. + * - Bit value 0 – excludes bit from address comparison. + * - Bit value 1 – the bit needs to match with the corresponding bit + * of the device address. + */ + uint32 multiprocAddrMask; + + /** Enables component interrupt: 0 – disable, 1 – enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of interrupt sources to enable in the RX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_RX_FIFO_LEVEL + * - UART_INTR_RX_NOT_EMPTY + * - UART_INTR_RX_FULL + * - UART_INTR_RX_OVERFLOW + * - UART_INTR_RX_UNDERFLOW + * - UART_INTR_RX_FRAME_ERROR + * - UART_INTR_RX_PARITY_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of interrupt sources to enable in the TX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_INTR_TX_FIFO_LEVEL + * - UART_INTR_TX_NOT_FULL + * - UART_INTR_TX_EMPTY + * - UART_INTR_TX_OVERFLOW + * - UART_INTR_TX_UNDERFLOW + * - UART_INTR_TX_UART_DONE + * - UART_INTR_TX_UART_NACK + * - UART_INTR_TX_UART_ARB_LOST + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 – disable, 1 – enable. This implies that number of + * Data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables usage of CTS input signal by the UART transmitter : 0 – disable, + * 1 – enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableCts; + + /** Sets active polarity of CTS input signal: + * - UART_UART_CTS_ACTIVE_LOW + * - UART_UART_CTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 ctsPolarity; + + /** RX FIFO level for RTS signal activation. While the RX FIFO has fewer + * entries than the RTS FIFO level value the RTS signal remains active, + * otherwise the RTS signal becomes inactive. By setting this field to 0, + * RTS signal activation is disabled. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsRxFifoLevel; + + /** Sets active polarity of RTS output signal: + * - UART_UART_RTS_ ACTIVE_LOW + * - UART_UART_RTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsPolarity; + + /** Configures the width of a break signal in that triggers the break + * detection interrupt source. A Break is a low level on the RX line. + * Valid range is 1-16 UART bits times. + */ + uint8 breakWidth; +} UART_UART_INIT_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_spi +* @{ +*/ +/* SPI specific functions */ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + void UART_SpiInit(const UART_SPI_INIT_STRUCT *config); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if(UART_SCB_MODE_SPI_INC) + /******************************************************************************* + * Function Name: UART_SpiIsBusBusy + ****************************************************************************//** + * + * Returns the current status on the bus. The bus status is determined using + * the slave select signal. + * - Motorola and National Semiconductor sub-modes: The bus is busy after + * the slave select line is activated and lasts until the slave select line + * is deactivated. + * - Texas Instrument sub-modes: The bus is busy at the moment of the initial + * pulse on the slave select line and lasts until the transfer is complete. + * If SPI Master is configured to use "Separated transfers" + * (see Continuous versus Separated Transfer Separation), the bus is busy + * during each element transfer and is free between each element transfer. + * The Master does not activate SS line immediately after data has been + * written into the TX FIFO. + * + * \return slaveSelect: Current status on the bus. + * If the returned value is nonzero, the bus is busy. + * If zero is returned, the bus is free. The bus status is determined using + * the slave select signal. + * + *******************************************************************************/ + #define UART_SpiIsBusBusy() ((uint32) (0u != (UART_SPI_STATUS_REG & \ + UART_SPI_STATUS_BUS_BUSY))) + + #if (UART_SPI_MASTER_CONST) + void UART_SpiSetActiveSlaveSelect(uint32 slaveSelect); + #endif /*(UART_SPI_MASTER_CONST) */ + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + void UART_SpiSetSlaveSelectPolarity(uint32 slaveSelect, uint32 polarity); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ +#endif /* (UART_SCB_MODE_SPI_INC) */ +/** @} spi */ + +/** +* \addtogroup group_uart +* @{ +*/ +/* UART specific functions */ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + void UART_UartInit(const UART_UART_INIT_STRUCT *config); +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if(UART_SCB_MODE_UART_INC) + void UART_UartSetRxAddress(uint32 address); + void UART_UartSetRxAddressMask(uint32 addressMask); + + + /* UART RX direction APIs */ + #if(UART_UART_RX_DIRECTION) + uint32 UART_UartGetChar(void); + uint32 UART_UartGetByte(void); + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void UART_UartSetRtsPolarity(uint32 polarity); + void UART_UartSetRtsFifoLevel(uint32 level); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + #endif /* (UART_UART_RX_DIRECTION) */ + + /* UART TX direction APIs */ + #if(UART_UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_UartPutChar + ****************************************************************************//** + * + * Places a byte of data in the transmit buffer to be sent at the next available + * bus time. This function is blocking and waits until there is a space + * available to put requested data in the transmit buffer. + * For UART Multi Processor mode this function can send 9-bits data as well. + * Use UART_UART_MP_MARK to add a mark to create an address byte. + * + * \param txDataByte: the data to be transmitted. + * + *******************************************************************************/ + #define UART_UartPutChar(ch) UART_SpiUartWriteTxData((uint32)(ch)) + + void UART_UartPutString(const char8 string[]); + void UART_UartPutCRLF(uint32 txDataByte); + void UART_UartSendBreakBlocking(uint32 breakWidth); + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void UART_UartEnableCts(void); + void UART_UartDisableCts(void); + void UART_UartSetCtsPolarity(uint32 polarity); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + #endif /* (UART_UART_TX_DIRECTION) */ +#endif /* (UART_SCB_MODE_UART_INC) */ +/** @} uart */ + +/** +* \addtogroup group_spi_uart +* @{ +*/ +#if(UART_RX_DIRECTION) + uint32 UART_SpiUartReadRxData(void); + uint32 UART_SpiUartGetRxBufferSize(void); + void UART_SpiUartClearRxBuffer(void); +#endif /* (UART_RX_DIRECTION) */ + +/* Common APIs TX direction */ +#if(UART_TX_DIRECTION) + void UART_SpiUartWriteTxData(uint32 txData); + void UART_SpiUartPutArray(const uint8 wrBuf[], uint32 count); + uint32 UART_SpiUartGetTxBufferSize(void); + void UART_SpiUartClearTxBuffer(void); +#endif /* (UART_TX_DIRECTION) */ +/** @} spi_uart */ + +CY_ISR_PROTO(UART_SPI_UART_ISR); + +#if(UART_UART_RX_WAKEUP_IRQ) + CY_ISR_PROTO(UART_UART_WAKEUP_ISR); +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Buffer Access Macro Definitions +***************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + /* RX direction */ + void UART_PutWordInRxBuffer (uint32 idx, uint32 rxDataByte); + uint32 UART_GetWordFromRxBuffer(uint32 idx); + + /* TX direction */ + void UART_PutWordInTxBuffer (uint32 idx, uint32 txDataByte); + uint32 UART_GetWordFromTxBuffer(uint32 idx); + +#else + /* RX direction */ + #if(UART_INTERNAL_RX_SW_BUFFER_CONST) + #define UART_PutWordInRxBuffer(idx, rxDataByte) \ + do{ \ + UART_rxBufferInternal[(idx)] = ((uint8) (rxDataByte)); \ + }while(0) + + #define UART_GetWordFromRxBuffer(idx) UART_rxBufferInternal[(idx)] + + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + /* TX direction */ + #if(UART_INTERNAL_TX_SW_BUFFER_CONST) + #define UART_PutWordInTxBuffer(idx, txDataByte) \ + do{ \ + UART_txBufferInternal[(idx)] = ((uint8) (txDataByte)); \ + }while(0) + + #define UART_GetWordFromTxBuffer(idx) UART_txBufferInternal[(idx)] + + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#endif /* (UART_TX_SW_BUFFER_ENABLE) */ + + +/*************************************** +* SPI API Constants +***************************************/ + +/* SPI sub mode enum */ +#define UART_SPI_MODE_MOTOROLA (0x00u) +#define UART_SPI_MODE_TI_COINCIDES (0x01u) +#define UART_SPI_MODE_TI_PRECEDES (0x11u) +#define UART_SPI_MODE_NATIONAL (0x02u) +#define UART_SPI_MODE_MASK (0x03u) +#define UART_SPI_MODE_TI_PRECEDES_MASK (0x10u) +#define UART_SPI_MODE_NS_MICROWIRE (UART_SPI_MODE_NATIONAL) + +/* SPI phase and polarity mode enum */ +#define UART_SPI_SCLK_CPHA0_CPOL0 (0x00u) +#define UART_SPI_SCLK_CPHA0_CPOL1 (0x02u) +#define UART_SPI_SCLK_CPHA1_CPOL0 (0x01u) +#define UART_SPI_SCLK_CPHA1_CPOL1 (0x03u) + +/* SPI bits order enum */ +#define UART_BITS_ORDER_LSB_FIRST (0u) +#define UART_BITS_ORDER_MSB_FIRST (1u) + +/* SPI transfer separation enum */ +#define UART_SPI_TRANSFER_SEPARATED (0u) +#define UART_SPI_TRANSFER_CONTINUOUS (1u) + +/* SPI slave select constants */ +#define UART_SPI_SLAVE_SELECT0 (UART_SCB__SS0_POSISTION) +#define UART_SPI_SLAVE_SELECT1 (UART_SCB__SS1_POSISTION) +#define UART_SPI_SLAVE_SELECT2 (UART_SCB__SS2_POSISTION) +#define UART_SPI_SLAVE_SELECT3 (UART_SCB__SS3_POSISTION) + +/* SPI slave select polarity settings */ +#define UART_SPI_SS_ACTIVE_LOW (0u) +#define UART_SPI_SS_ACTIVE_HIGH (1u) + +#define UART_INTR_SPIM_TX_RESTORE (UART_INTR_TX_OVERFLOW) + +#define UART_INTR_SPIS_TX_RESTORE (UART_INTR_TX_OVERFLOW | \ + UART_INTR_TX_UNDERFLOW) + +/*************************************** +* UART API Constants +***************************************/ + +/* UART sub-modes enum */ +#define UART_UART_MODE_STD (0u) +#define UART_UART_MODE_SMARTCARD (1u) +#define UART_UART_MODE_IRDA (2u) + +/* UART direction enum */ +#define UART_UART_RX (1u) +#define UART_UART_TX (2u) +#define UART_UART_TX_RX (3u) + +/* UART parity enum */ +#define UART_UART_PARITY_EVEN (0u) +#define UART_UART_PARITY_ODD (1u) +#define UART_UART_PARITY_NONE (2u) + +/* UART stop bits enum */ +#define UART_UART_STOP_BITS_1 (2u) +#define UART_UART_STOP_BITS_1_5 (3u) +#define UART_UART_STOP_BITS_2 (4u) + +/* UART IrDA low power OVS enum */ +#define UART_UART_IRDA_LP_OVS16 (16u) +#define UART_UART_IRDA_LP_OVS32 (32u) +#define UART_UART_IRDA_LP_OVS48 (48u) +#define UART_UART_IRDA_LP_OVS96 (96u) +#define UART_UART_IRDA_LP_OVS192 (192u) +#define UART_UART_IRDA_LP_OVS768 (768u) +#define UART_UART_IRDA_LP_OVS1536 (1536u) + +/* Uart MP: mark (address) and space (data) bit definitions */ +#define UART_UART_MP_MARK (0x100u) +#define UART_UART_MP_SPACE (0x000u) + +/* UART CTS/RTS polarity settings */ +#define UART_UART_CTS_ACTIVE_LOW (0u) +#define UART_UART_CTS_ACTIVE_HIGH (1u) +#define UART_UART_RTS_ACTIVE_LOW (0u) +#define UART_UART_RTS_ACTIVE_HIGH (1u) + +/* Sources of RX errors */ +#define UART_INTR_RX_ERR (UART_INTR_RX_OVERFLOW | \ + UART_INTR_RX_UNDERFLOW | \ + UART_INTR_RX_FRAME_ERROR | \ + UART_INTR_RX_PARITY_ERROR) + +/* Shifted INTR_RX_ERR defines ONLY for UART_UartGetByte() */ +#define UART_UART_RX_OVERFLOW (UART_INTR_RX_OVERFLOW << 8u) +#define UART_UART_RX_UNDERFLOW (UART_INTR_RX_UNDERFLOW << 8u) +#define UART_UART_RX_FRAME_ERROR (UART_INTR_RX_FRAME_ERROR << 8u) +#define UART_UART_RX_PARITY_ERROR (UART_INTR_RX_PARITY_ERROR << 8u) +#define UART_UART_RX_ERROR_MASK (UART_UART_RX_OVERFLOW | \ + UART_UART_RX_UNDERFLOW | \ + UART_UART_RX_FRAME_ERROR | \ + UART_UART_RX_PARITY_ERROR) + +#define UART_INTR_UART_TX_RESTORE (UART_INTR_TX_OVERFLOW | \ + UART_INTR_TX_UART_NACK | \ + UART_INTR_TX_UART_DONE | \ + UART_INTR_TX_UART_ARB_LOST) + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + extern const UART_SPI_INIT_STRUCT UART_configSpi; + extern const UART_UART_INIT_STRUCT UART_configUart; +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) + extern uint8 UART_skipStart; +#endif /* (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Specific SPI Macro Definitions +***************************************/ + +#define UART_GET_SPI_INTR_SLAVE_MASK(sourceMask) ((sourceMask) & UART_INTR_SLAVE_SPI_BUS_ERROR) +#define UART_GET_SPI_INTR_MASTER_MASK(sourceMask) ((sourceMask) & UART_INTR_MASTER_SPI_DONE) +#define UART_GET_SPI_INTR_RX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~UART_INTR_SLAVE_SPI_BUS_ERROR) + +#define UART_GET_SPI_INTR_TX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~UART_INTR_MASTER_SPI_DONE) + + +/*************************************** +* Specific UART Macro Definitions +***************************************/ + +#define UART_UART_GET_CTRL_OVS_IRDA_LP(oversample) \ + ((UART_UART_IRDA_LP_OVS16 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS16 : \ + ((UART_UART_IRDA_LP_OVS32 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS32 : \ + ((UART_UART_IRDA_LP_OVS48 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS48 : \ + ((UART_UART_IRDA_LP_OVS96 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS96 : \ + ((UART_UART_IRDA_LP_OVS192 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS192 : \ + ((UART_UART_IRDA_LP_OVS768 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS768 : \ + ((UART_UART_IRDA_LP_OVS1536 == (oversample)) ? UART_CTRL_OVS_IRDA_LP_OVS1536 : \ + UART_CTRL_OVS_IRDA_LP_OVS16))))))) + +#define UART_GET_UART_RX_CTRL_ENABLED(direction) ((0u != (UART_UART_RX & (direction))) ? \ + (UART_RX_CTRL_ENABLED) : (0u)) + +#define UART_GET_UART_TX_CTRL_ENABLED(direction) ((0u != (UART_UART_TX & (direction))) ? \ + (UART_TX_CTRL_ENABLED) : (0u)) + + +/*************************************** +* SPI Register Settings +***************************************/ + +#define UART_CTRL_SPI (UART_CTRL_MODE_SPI) +#define UART_SPI_RX_CTRL (UART_RX_CTRL_ENABLED) +#define UART_SPI_TX_CTRL (UART_TX_CTRL_ENABLED) + + +/*************************************** +* SPI Init Register Settings +***************************************/ + +#define UART_SPI_SS_POLARITY \ + (((uint32) UART_SPI_SS0_POLARITY << UART_SPI_SLAVE_SELECT0) | \ + ((uint32) UART_SPI_SS1_POLARITY << UART_SPI_SLAVE_SELECT1) | \ + ((uint32) UART_SPI_SS2_POLARITY << UART_SPI_SLAVE_SELECT2) | \ + ((uint32) UART_SPI_SS3_POLARITY << UART_SPI_SLAVE_SELECT3)) + +#if(UART_SCB_MODE_SPI_CONST_CFG) + + /* SPI Configuration */ + #define UART_SPI_DEFAULT_CTRL \ + (UART_GET_CTRL_OVS(UART_SPI_OVS_FACTOR) | \ + UART_GET_CTRL_BYTE_MODE (UART_SPI_BYTE_MODE_ENABLE) | \ + UART_GET_CTRL_EC_AM_MODE(UART_SPI_WAKE_ENABLE) | \ + UART_CTRL_SPI) + + #define UART_SPI_DEFAULT_SPI_CTRL \ + (UART_GET_SPI_CTRL_CONTINUOUS (UART_SPI_TRANSFER_SEPARATION) | \ + UART_GET_SPI_CTRL_SELECT_PRECEDE(UART_SPI_SUB_MODE & \ + UART_SPI_MODE_TI_PRECEDES_MASK) | \ + UART_GET_SPI_CTRL_SCLK_MODE (UART_SPI_CLOCK_MODE) | \ + UART_GET_SPI_CTRL_LATE_MISO_SAMPLE(UART_SPI_LATE_MISO_SAMPLE_ENABLE) | \ + UART_GET_SPI_CTRL_SCLK_CONTINUOUS(UART_SPI_FREE_RUN_SCLK_ENABLE) | \ + UART_GET_SPI_CTRL_SSEL_POLARITY (UART_SPI_SS_POLARITY) | \ + UART_GET_SPI_CTRL_SUB_MODE (UART_SPI_SUB_MODE) | \ + UART_GET_SPI_CTRL_MASTER_MODE (UART_SPI_MODE)) + + /* RX direction */ + #define UART_SPI_DEFAULT_RX_CTRL \ + (UART_GET_RX_CTRL_DATA_WIDTH(UART_SPI_RX_DATA_BITS_NUM) | \ + UART_GET_RX_CTRL_BIT_ORDER (UART_SPI_BITS_ORDER) | \ + UART_GET_RX_CTRL_MEDIAN (UART_SPI_MEDIAN_FILTER_ENABLE) | \ + UART_SPI_RX_CTRL) + + #define UART_SPI_DEFAULT_RX_FIFO_CTRL \ + UART_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(UART_SPI_RX_TRIGGER_LEVEL) + + /* TX direction */ + #define UART_SPI_DEFAULT_TX_CTRL \ + (UART_GET_TX_CTRL_DATA_WIDTH(UART_SPI_TX_DATA_BITS_NUM) | \ + UART_GET_TX_CTRL_BIT_ORDER (UART_SPI_BITS_ORDER) | \ + UART_SPI_TX_CTRL) + + #define UART_SPI_DEFAULT_TX_FIFO_CTRL \ + UART_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(UART_SPI_TX_TRIGGER_LEVEL) + + /* Interrupt sources */ + #define UART_SPI_DEFAULT_INTR_SPI_EC_MASK (UART_NO_INTR_SOURCES) + + #define UART_SPI_DEFAULT_INTR_I2C_EC_MASK (UART_NO_INTR_SOURCES) + #define UART_SPI_DEFAULT_INTR_SLAVE_MASK \ + (UART_SPI_INTR_RX_MASK & UART_INTR_SLAVE_SPI_BUS_ERROR) + + #define UART_SPI_DEFAULT_INTR_MASTER_MASK \ + (UART_SPI_INTR_TX_MASK & UART_INTR_MASTER_SPI_DONE) + + #define UART_SPI_DEFAULT_INTR_RX_MASK \ + (UART_SPI_INTR_RX_MASK & (uint32) ~UART_INTR_SLAVE_SPI_BUS_ERROR) + + #define UART_SPI_DEFAULT_INTR_TX_MASK \ + (UART_SPI_INTR_TX_MASK & (uint32) ~UART_INTR_MASTER_SPI_DONE) + +#endif /* (UART_SCB_MODE_SPI_CONST_CFG) */ + + +/*************************************** +* UART Register Settings +***************************************/ + +#define UART_CTRL_UART (UART_CTRL_MODE_UART) +#define UART_UART_RX_CTRL (UART_RX_CTRL_LSB_FIRST) /* LSB for UART goes first */ +#define UART_UART_TX_CTRL (UART_TX_CTRL_LSB_FIRST) /* LSB for UART goes first */ + + +/*************************************** +* UART Init Register Settings +***************************************/ + +#if(UART_SCB_MODE_UART_CONST_CFG) + + /* UART configuration */ + #if(UART_UART_MODE_IRDA == UART_UART_SUB_MODE) + + #define UART_DEFAULT_CTRL_OVS ((0u != UART_UART_IRDA_LOW_POWER) ? \ + (UART_UART_GET_CTRL_OVS_IRDA_LP(UART_UART_OVS_FACTOR)) : \ + (UART_CTRL_OVS_IRDA_OVS16)) + + #else + + #define UART_DEFAULT_CTRL_OVS UART_GET_CTRL_OVS(UART_UART_OVS_FACTOR) + + #endif /* (UART_UART_MODE_IRDA == UART_UART_SUB_MODE) */ + + #define UART_UART_DEFAULT_CTRL \ + (UART_GET_CTRL_BYTE_MODE (UART_UART_BYTE_MODE_ENABLE) | \ + UART_GET_CTRL_ADDR_ACCEPT(UART_UART_MP_ACCEPT_ADDRESS) | \ + UART_DEFAULT_CTRL_OVS | \ + UART_CTRL_UART) + + #define UART_UART_DEFAULT_UART_CTRL \ + (UART_GET_UART_CTRL_MODE(UART_UART_SUB_MODE)) + + /* RX direction */ + #define UART_UART_DEFAULT_RX_CTRL_PARITY \ + ((UART_UART_PARITY_NONE != UART_UART_PARITY_TYPE) ? \ + (UART_GET_UART_RX_CTRL_PARITY(UART_UART_PARITY_TYPE) | \ + UART_UART_RX_CTRL_PARITY_ENABLED) : (0u)) + + #define UART_UART_DEFAULT_UART_RX_CTRL \ + (UART_GET_UART_RX_CTRL_MODE(UART_UART_STOP_BITS_NUM) | \ + UART_GET_UART_RX_CTRL_POLARITY(UART_UART_IRDA_POLARITY) | \ + UART_GET_UART_RX_CTRL_MP_MODE(UART_UART_MP_MODE_ENABLE) | \ + UART_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(UART_UART_DROP_ON_PARITY_ERR) | \ + UART_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(UART_UART_DROP_ON_FRAME_ERR) | \ + UART_GET_UART_RX_CTRL_BREAK_WIDTH(UART_UART_RX_BREAK_WIDTH) | \ + UART_UART_DEFAULT_RX_CTRL_PARITY) + + + #define UART_UART_DEFAULT_RX_CTRL \ + (UART_GET_RX_CTRL_DATA_WIDTH(UART_UART_DATA_BITS_NUM) | \ + UART_GET_RX_CTRL_MEDIAN (UART_UART_MEDIAN_FILTER_ENABLE) | \ + UART_GET_UART_RX_CTRL_ENABLED(UART_UART_DIRECTION)) + + #define UART_UART_DEFAULT_RX_FIFO_CTRL \ + UART_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(UART_UART_RX_TRIGGER_LEVEL) + + #define UART_UART_DEFAULT_RX_MATCH_REG ((0u != UART_UART_MP_MODE_ENABLE) ? \ + (UART_GET_RX_MATCH_ADDR(UART_UART_MP_RX_ADDRESS) | \ + UART_GET_RX_MATCH_MASK(UART_UART_MP_RX_ADDRESS_MASK)) : (0u)) + + /* TX direction */ + #define UART_UART_DEFAULT_TX_CTRL_PARITY (UART_UART_DEFAULT_RX_CTRL_PARITY) + + #define UART_UART_DEFAULT_UART_TX_CTRL \ + (UART_GET_UART_TX_CTRL_MODE(UART_UART_STOP_BITS_NUM) | \ + UART_GET_UART_TX_CTRL_RETRY_NACK(UART_UART_RETRY_ON_NACK) | \ + UART_UART_DEFAULT_TX_CTRL_PARITY) + + #define UART_UART_DEFAULT_TX_CTRL \ + (UART_GET_TX_CTRL_DATA_WIDTH(UART_UART_DATA_BITS_NUM) | \ + UART_GET_UART_TX_CTRL_ENABLED(UART_UART_DIRECTION)) + + #define UART_UART_DEFAULT_TX_FIFO_CTRL \ + UART_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(UART_UART_TX_TRIGGER_LEVEL) + + #define UART_UART_DEFAULT_FLOW_CTRL \ + (UART_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(UART_UART_RTS_FIFO_LEVEL) | \ + UART_GET_UART_FLOW_CTRL_RTS_POLARITY (UART_UART_RTS_POLARITY) | \ + UART_GET_UART_FLOW_CTRL_CTS_POLARITY (UART_UART_CTS_POLARITY) | \ + UART_GET_UART_FLOW_CTRL_CTS_ENABLE (UART_UART_CTS_ENABLE)) + + /* Interrupt sources */ + #define UART_UART_DEFAULT_INTR_I2C_EC_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_SPI_EC_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_SLAVE_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_MASTER_MASK (UART_NO_INTR_SOURCES) + #define UART_UART_DEFAULT_INTR_RX_MASK (UART_UART_INTR_RX_MASK) + #define UART_UART_DEFAULT_INTR_TX_MASK (UART_UART_INTR_TX_MASK) + +#endif /* (UART_SCB_MODE_UART_CONST_CFG) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +#define UART_SPIM_ACTIVE_SS0 (UART_SPI_SLAVE_SELECT0) +#define UART_SPIM_ACTIVE_SS1 (UART_SPI_SLAVE_SELECT1) +#define UART_SPIM_ACTIVE_SS2 (UART_SPI_SLAVE_SELECT2) +#define UART_SPIM_ACTIVE_SS3 (UART_SPI_SLAVE_SELECT3) + +#endif /* CY_SCB_SPI_UART_UART_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART_INT.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART_INT.c new file mode 100644 index 0000000..c7809b2 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART_INT.c @@ -0,0 +1,158 @@ +/***************************************************************************//** +* \file UART_SPI_UART_INT.c +* \version 4.0 +* +* \brief +* This file provides the source code to the Interrupt Service Routine for +* the SCB Component in SPI and UART modes. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" +#include "UART_SPI_UART_PVT.h" +#include "cyapicallbacks.h" + +#if (UART_SCB_IRQ_INTERNAL) +/******************************************************************************* +* Function Name: UART_SPI_UART_ISR +****************************************************************************//** +* +* Handles the Interrupt Service Routine for the SCB SPI or UART modes. +* +*******************************************************************************/ +CY_ISR(UART_SPI_UART_ISR) +{ +#if (UART_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locHead; +#endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if (UART_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locTail; +#endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#ifdef UART_SPI_UART_ISR_ENTRY_CALLBACK + UART_SPI_UART_ISR_EntryCallback(); +#endif /* UART_SPI_UART_ISR_ENTRY_CALLBACK */ + + if (NULL != UART_customIntrHandler) + { + UART_customIntrHandler(); + } + + #if(UART_CHECK_SPI_WAKE_ENABLE) + { + /* Clear SPI wakeup source */ + UART_ClearSpiExtClkInterruptSource(UART_INTR_SPI_EC_WAKE_UP); + } + #endif + + #if (UART_CHECK_RX_SW_BUFFER) + { + if (UART_CHECK_INTR_RX_MASKED(UART_INTR_RX_NOT_EMPTY)) + { + do + { + /* Move local head index */ + locHead = (UART_rxBufferHead + 1u); + + /* Adjust local head index */ + if (UART_INTERNAL_RX_BUFFER_SIZE == locHead) + { + locHead = 0u; + } + + if (locHead == UART_rxBufferTail) + { + #if (UART_CHECK_UART_RTS_CONTROL_FLOW) + { + /* There is no space in the software buffer - disable the + * RX Not Empty interrupt source. The data elements are + * still being received into the RX FIFO until the RTS signal + * stops the transmitter. After the data element is read from the + * buffer, the RX Not Empty interrupt source is enabled to + * move the next data element in the software buffer. + */ + UART_INTR_RX_MASK_REG &= ~UART_INTR_RX_NOT_EMPTY; + break; + } + #else + { + /* Overflow: through away received data element */ + (void) UART_RX_FIFO_RD_REG; + UART_rxBufferOverflow = (uint8) UART_INTR_RX_OVERFLOW; + } + #endif + } + else + { + /* Store received data */ + UART_PutWordInRxBuffer(locHead, UART_RX_FIFO_RD_REG); + + /* Move head index */ + UART_rxBufferHead = locHead; + } + } + while(0u != UART_GET_RX_FIFO_ENTRIES); + + UART_ClearRxInterruptSource(UART_INTR_RX_NOT_EMPTY); + } + } + #endif + + + #if (UART_CHECK_TX_SW_BUFFER) + { + if (UART_CHECK_INTR_TX_MASKED(UART_INTR_TX_NOT_FULL)) + { + do + { + /* Check for room in TX software buffer */ + if (UART_txBufferHead != UART_txBufferTail) + { + /* Move local tail index */ + locTail = (UART_txBufferTail + 1u); + + /* Adjust local tail index */ + if (UART_TX_BUFFER_SIZE == locTail) + { + locTail = 0u; + } + + /* Put data into TX FIFO */ + UART_TX_FIFO_WR_REG = UART_GetWordFromTxBuffer(locTail); + + /* Move tail index */ + UART_txBufferTail = locTail; + } + else + { + /* TX software buffer is empty: complete transfer */ + UART_DISABLE_INTR_TX(UART_INTR_TX_NOT_FULL); + break; + } + } + while (UART_SPI_UART_FIFO_SIZE != UART_GET_TX_FIFO_ENTRIES); + + UART_ClearTxInterruptSource(UART_INTR_TX_NOT_FULL); + } + } + #endif + +#ifdef UART_SPI_UART_ISR_EXIT_CALLBACK + UART_SPI_UART_ISR_ExitCallback(); +#endif /* UART_SPI_UART_ISR_EXIT_CALLBACK */ + +} + +#endif /* (UART_SCB_IRQ_INTERNAL) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART_PVT.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART_PVT.h new file mode 100644 index 0000000..5d656ee --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_SPI_UART_PVT.h @@ -0,0 +1,117 @@ +/***************************************************************************//** +* \file UART_SPI_UART_PVT.h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component in SPI and UART modes. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_SPI_UART_PVT_UART_H) +#define CY_SCB_SPI_UART_PVT_UART_H + +#include "UART_SPI_UART.h" + + +/*************************************** +* Internal Global Vars +***************************************/ + +#if (UART_INTERNAL_RX_SW_BUFFER_CONST) + extern volatile uint32 UART_rxBufferHead; + extern volatile uint32 UART_rxBufferTail; + + /** + * \addtogroup group_globals + * @{ + */ + + /** Sets when internal software receive buffer overflow + * was occurred. + */ + extern volatile uint8 UART_rxBufferOverflow; + /** @} globals */ +#endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if (UART_INTERNAL_TX_SW_BUFFER_CONST) + extern volatile uint32 UART_txBufferHead; + extern volatile uint32 UART_txBufferTail; +#endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if (UART_INTERNAL_RX_SW_BUFFER) + extern volatile uint8 UART_rxBufferInternal[UART_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_RX_SW_BUFFER) */ + +#if (UART_INTERNAL_TX_SW_BUFFER) + extern volatile uint8 UART_txBufferInternal[UART_TX_BUFFER_SIZE]; +#endif /* (UART_INTERNAL_TX_SW_BUFFER) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +void UART_SpiPostEnable(void); +void UART_SpiStop(void); + +#if (UART_SCB_MODE_SPI_CONST_CFG) + void UART_SpiInit(void); +#endif /* (UART_SCB_MODE_SPI_CONST_CFG) */ + +#if (UART_SPI_WAKE_ENABLE_CONST) + void UART_SpiSaveConfig(void); + void UART_SpiRestoreConfig(void); +#endif /* (UART_SPI_WAKE_ENABLE_CONST) */ + +void UART_UartPostEnable(void); +void UART_UartStop(void); + +#if (UART_SCB_MODE_UART_CONST_CFG) + void UART_UartInit(void); +#endif /* (UART_SCB_MODE_UART_CONST_CFG) */ + +#if (UART_UART_WAKE_ENABLE_CONST) + void UART_UartSaveConfig(void); + void UART_UartRestoreConfig(void); +#endif /* (UART_UART_WAKE_ENABLE_CONST) */ + + +/*************************************** +* UART API Constants +***************************************/ + +/* UART RX and TX position to be used in UART_SetPins() */ +#define UART_UART_RX_PIN_ENABLE (UART_UART_RX) +#define UART_UART_TX_PIN_ENABLE (UART_UART_TX) + +/* UART RTS and CTS position to be used in UART_SetPins() */ +#define UART_UART_RTS_PIN_ENABLE (0x10u) +#define UART_UART_CTS_PIN_ENABLE (0x20u) + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Interrupt processing */ +#define UART_SpiUartEnableIntRx(intSourceMask) UART_SetRxInterruptMode(intSourceMask) +#define UART_SpiUartEnableIntTx(intSourceMask) UART_SetTxInterruptMode(intSourceMask) +uint32 UART_SpiUartDisableIntRx(void); +uint32 UART_SpiUartDisableIntTx(void); + + +#endif /* (CY_SCB_SPI_UART_PVT_UART_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_UART.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_UART.c new file mode 100644 index 0000000..0b7318e --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_UART.c @@ -0,0 +1,905 @@ +/***************************************************************************//** +* \file UART_UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* UART mode. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_PVT.h" +#include "UART_SPI_UART_PVT.h" +#include "cyapicallbacks.h" + +#if (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) + /** + * \addtogroup group_globals + * \{ + */ + /** This global variable determines whether to enable Skip Start + * functionality when UART_Sleep() function is called: + * 0 – disable, other values – enable. Default value is 1. + * It is only available when Enable wakeup from Deep Sleep Mode is enabled. + */ + uint8 UART_skipStart = 1u; + /** \} globals */ +#endif /* (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) */ + +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + + /*************************************** + * Configuration Structure Initialization + ***************************************/ + + const UART_UART_INIT_STRUCT UART_configUart = + { + UART_UART_SUB_MODE, + UART_UART_DIRECTION, + UART_UART_DATA_BITS_NUM, + UART_UART_PARITY_TYPE, + UART_UART_STOP_BITS_NUM, + UART_UART_OVS_FACTOR, + UART_UART_IRDA_LOW_POWER, + UART_UART_MEDIAN_FILTER_ENABLE, + UART_UART_RETRY_ON_NACK, + UART_UART_IRDA_POLARITY, + UART_UART_DROP_ON_PARITY_ERR, + UART_UART_DROP_ON_FRAME_ERR, + UART_UART_WAKE_ENABLE, + 0u, + NULL, + 0u, + NULL, + UART_UART_MP_MODE_ENABLE, + UART_UART_MP_ACCEPT_ADDRESS, + UART_UART_MP_RX_ADDRESS, + UART_UART_MP_RX_ADDRESS_MASK, + (uint32) UART_SCB_IRQ_INTERNAL, + UART_UART_INTR_RX_MASK, + UART_UART_RX_TRIGGER_LEVEL, + UART_UART_INTR_TX_MASK, + UART_UART_TX_TRIGGER_LEVEL, + (uint8) UART_UART_BYTE_MODE_ENABLE, + (uint8) UART_UART_CTS_ENABLE, + (uint8) UART_UART_CTS_POLARITY, + (uint8) UART_UART_RTS_POLARITY, + (uint8) UART_UART_RTS_FIFO_LEVEL, + (uint8) UART_UART_RX_BREAK_WIDTH + }; + + + /******************************************************************************* + * Function Name: UART_UartInit + ****************************************************************************//** + * + * Configures the UART for UART operation. + * + * This function is intended specifically to be used when the UART + * configuration is set to “Unconfigured UART” in the customizer. + * After initializing the UART in UART mode using this function, + * the component can be enabled using the UART_Start() or + * UART_Enable() function. + * This function uses a pointer to a structure that provides the configuration + * settings. This structure contains the same information that would otherwise + * be provided by the customizer settings. + * + * \param config: pointer to a structure that contains the following list of + * fields. These fields match the selections available in the customizer. + * Refer to the customizer for further description of the settings. + * + *******************************************************************************/ + void UART_UartInit(const UART_UART_INIT_STRUCT *config) + { + uint32 pinsConfig; + + if (NULL == config) + { + CYASSERT(0u != 0u); /* Halt execution due to bad function parameter */ + } + else + { + /* Get direction to configure UART pins: TX, RX or TX+RX */ + pinsConfig = config->direction; + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /* Add RTS and CTS pins to configure */ + pinsConfig |= (0u != config->rtsRxFifoLevel) ? (UART_UART_RTS_PIN_ENABLE) : (0u); + pinsConfig |= (0u != config->enableCts) ? (UART_UART_CTS_PIN_ENABLE) : (0u); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + /* Configure pins */ + UART_SetPins(UART_SCB_MODE_UART, config->mode, pinsConfig); + + /* Store internal configuration */ + UART_scbMode = (uint8) UART_SCB_MODE_UART; + UART_scbEnableWake = (uint8) config->enableWake; + UART_scbEnableIntr = (uint8) config->enableInterrupt; + + /* Set RX direction internal variables */ + UART_rxBuffer = config->rxBuffer; + UART_rxDataBits = (uint8) config->dataBits; + UART_rxBufferSize = config->rxBufferSize; + + /* Set TX direction internal variables */ + UART_txBuffer = config->txBuffer; + UART_txDataBits = (uint8) config->dataBits; + UART_txBufferSize = config->txBufferSize; + + /* Configure UART interface */ + if(UART_UART_MODE_IRDA == config->mode) + { + /* OVS settings: IrDA */ + UART_CTRL_REG = ((0u != config->enableIrdaLowPower) ? + (UART_UART_GET_CTRL_OVS_IRDA_LP(config->oversample)) : + (UART_CTRL_OVS_IRDA_OVS16)); + } + else + { + /* OVS settings: UART and SmartCard */ + UART_CTRL_REG = UART_GET_CTRL_OVS(config->oversample); + } + + UART_CTRL_REG |= UART_GET_CTRL_BYTE_MODE (config->enableByteMode) | + UART_GET_CTRL_ADDR_ACCEPT(config->multiprocAcceptAddr) | + UART_CTRL_UART; + + /* Configure sub-mode: UART, SmartCard or IrDA */ + UART_UART_CTRL_REG = UART_GET_UART_CTRL_MODE(config->mode); + + /* Configure RX direction */ + UART_UART_RX_CTRL_REG = UART_GET_UART_RX_CTRL_MODE(config->stopBits) | + UART_GET_UART_RX_CTRL_POLARITY(config->enableInvertedRx) | + UART_GET_UART_RX_CTRL_MP_MODE(config->enableMultiproc) | + UART_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(config->dropOnParityErr) | + UART_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(config->dropOnFrameErr) | + UART_GET_UART_RX_CTRL_BREAK_WIDTH(config->breakWidth); + + if(UART_UART_PARITY_NONE != config->parity) + { + UART_UART_RX_CTRL_REG |= UART_GET_UART_RX_CTRL_PARITY(config->parity) | + UART_UART_RX_CTRL_PARITY_ENABLED; + } + + UART_RX_CTRL_REG = UART_GET_RX_CTRL_DATA_WIDTH(config->dataBits) | + UART_GET_RX_CTRL_MEDIAN(config->enableMedianFilter) | + UART_GET_UART_RX_CTRL_ENABLED(config->direction); + + UART_RX_FIFO_CTRL_REG = UART_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(config->rxTriggerLevel); + + /* Configure MP address */ + UART_RX_MATCH_REG = UART_GET_RX_MATCH_ADDR(config->multiprocAddr) | + UART_GET_RX_MATCH_MASK(config->multiprocAddrMask); + + /* Configure RX direction */ + UART_UART_TX_CTRL_REG = UART_GET_UART_TX_CTRL_MODE(config->stopBits) | + UART_GET_UART_TX_CTRL_RETRY_NACK(config->enableRetryNack); + + if(UART_UART_PARITY_NONE != config->parity) + { + UART_UART_TX_CTRL_REG |= UART_GET_UART_TX_CTRL_PARITY(config->parity) | + UART_UART_TX_CTRL_PARITY_ENABLED; + } + + UART_TX_CTRL_REG = UART_GET_TX_CTRL_DATA_WIDTH(config->dataBits) | + UART_GET_UART_TX_CTRL_ENABLED(config->direction); + + UART_TX_FIFO_CTRL_REG = UART_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(config->txTriggerLevel); + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + UART_UART_FLOW_CTRL_REG = UART_GET_UART_FLOW_CTRL_CTS_ENABLE(config->enableCts) | \ + UART_GET_UART_FLOW_CTRL_CTS_POLARITY (config->ctsPolarity) | \ + UART_GET_UART_FLOW_CTRL_RTS_POLARITY (config->rtsPolarity) | \ + UART_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(config->rtsRxFifoLevel); + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + /* Configure interrupt with UART handler but do not enable it */ + CyIntDisable (UART_ISR_NUMBER); + CyIntSetPriority(UART_ISR_NUMBER, UART_ISR_PRIORITY); + (void) CyIntSetVector(UART_ISR_NUMBER, &UART_SPI_UART_ISR); + + /* Configure WAKE interrupt */ + #if(UART_UART_RX_WAKEUP_IRQ) + CyIntDisable (UART_RX_WAKE_ISR_NUMBER); + CyIntSetPriority(UART_RX_WAKE_ISR_NUMBER, UART_RX_WAKE_ISR_PRIORITY); + (void) CyIntSetVector(UART_RX_WAKE_ISR_NUMBER, &UART_UART_WAKEUP_ISR); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + /* Configure interrupt sources */ + UART_INTR_I2C_EC_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_SPI_EC_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_SLAVE_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_MASTER_MASK_REG = UART_NO_INTR_SOURCES; + UART_INTR_RX_MASK_REG = config->rxInterruptMask; + UART_INTR_TX_MASK_REG = config->txInterruptMask; + + /* Configure TX interrupt sources to restore. */ + UART_IntrTxMask = LO16(UART_INTR_TX_MASK_REG); + + /* Clear RX buffer indexes */ + UART_rxBufferHead = 0u; + UART_rxBufferTail = 0u; + UART_rxBufferOverflow = 0u; + + /* Clear TX buffer indexes */ + UART_txBufferHead = 0u; + UART_txBufferTail = 0u; + } + } + +#else + + /******************************************************************************* + * Function Name: UART_UartInit + ****************************************************************************//** + * + * Configures the SCB for the UART operation. + * + *******************************************************************************/ + void UART_UartInit(void) + { + /* Configure UART interface */ + UART_CTRL_REG = UART_UART_DEFAULT_CTRL; + + /* Configure sub-mode: UART, SmartCard or IrDA */ + UART_UART_CTRL_REG = UART_UART_DEFAULT_UART_CTRL; + + /* Configure RX direction */ + UART_UART_RX_CTRL_REG = UART_UART_DEFAULT_UART_RX_CTRL; + UART_RX_CTRL_REG = UART_UART_DEFAULT_RX_CTRL; + UART_RX_FIFO_CTRL_REG = UART_UART_DEFAULT_RX_FIFO_CTRL; + UART_RX_MATCH_REG = UART_UART_DEFAULT_RX_MATCH_REG; + + /* Configure TX direction */ + UART_UART_TX_CTRL_REG = UART_UART_DEFAULT_UART_TX_CTRL; + UART_TX_CTRL_REG = UART_UART_DEFAULT_TX_CTRL; + UART_TX_FIFO_CTRL_REG = UART_UART_DEFAULT_TX_FIFO_CTRL; + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + UART_UART_FLOW_CTRL_REG = UART_UART_DEFAULT_FLOW_CTRL; + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + /* Configure interrupt with UART handler but do not enable it */ + #if(UART_SCB_IRQ_INTERNAL) + CyIntDisable (UART_ISR_NUMBER); + CyIntSetPriority(UART_ISR_NUMBER, UART_ISR_PRIORITY); + (void) CyIntSetVector(UART_ISR_NUMBER, &UART_SPI_UART_ISR); + #endif /* (UART_SCB_IRQ_INTERNAL) */ + + /* Configure WAKE interrupt */ + #if(UART_UART_RX_WAKEUP_IRQ) + CyIntDisable (UART_RX_WAKE_ISR_NUMBER); + CyIntSetPriority(UART_RX_WAKE_ISR_NUMBER, UART_RX_WAKE_ISR_PRIORITY); + (void) CyIntSetVector(UART_RX_WAKE_ISR_NUMBER, &UART_UART_WAKEUP_ISR); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + /* Configure interrupt sources */ + UART_INTR_I2C_EC_MASK_REG = UART_UART_DEFAULT_INTR_I2C_EC_MASK; + UART_INTR_SPI_EC_MASK_REG = UART_UART_DEFAULT_INTR_SPI_EC_MASK; + UART_INTR_SLAVE_MASK_REG = UART_UART_DEFAULT_INTR_SLAVE_MASK; + UART_INTR_MASTER_MASK_REG = UART_UART_DEFAULT_INTR_MASTER_MASK; + UART_INTR_RX_MASK_REG = UART_UART_DEFAULT_INTR_RX_MASK; + UART_INTR_TX_MASK_REG = UART_UART_DEFAULT_INTR_TX_MASK; + + /* Configure TX interrupt sources to restore. */ + UART_IntrTxMask = LO16(UART_INTR_TX_MASK_REG); + + #if(UART_INTERNAL_RX_SW_BUFFER_CONST) + UART_rxBufferHead = 0u; + UART_rxBufferTail = 0u; + UART_rxBufferOverflow = 0u; + #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if(UART_INTERNAL_TX_SW_BUFFER_CONST) + UART_txBufferHead = 0u; + UART_txBufferTail = 0u; + #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + } +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/******************************************************************************* +* Function Name: UART_UartPostEnable +****************************************************************************//** +* +* Restores HSIOM settings for the UART output pins (TX and/or RTS) to be +* controlled by the SCB UART. +* +*******************************************************************************/ +void UART_UartPostEnable(void) +{ +#if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + #if (UART_TX_SDA_MISO_PIN) + if (UART_CHECK_TX_SDA_MISO_PIN_USED) + { + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, UART_TX_SDA_MISO_HSIOM_MASK, + UART_TX_SDA_MISO_HSIOM_POS, UART_TX_SDA_MISO_HSIOM_SEL_UART); + } + #endif /* (UART_TX_SDA_MISO_PIN_PIN) */ + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #if (UART_SS0_PIN) + if (UART_CHECK_SS0_PIN_USED) + { + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, UART_SS0_HSIOM_MASK, + UART_SS0_HSIOM_POS, UART_SS0_HSIOM_SEL_UART); + } + #endif /* (UART_SS0_PIN) */ + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#else + #if (UART_UART_TX_PIN) + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_TX_HSIOM_REG, UART_TX_HSIOM_MASK, + UART_TX_HSIOM_POS, UART_TX_HSIOM_SEL_UART); + #endif /* (UART_UART_TX_PIN) */ + + #if (UART_UART_RTS_PIN) + /* Set SCB UART to drive the output pin */ + UART_SET_HSIOM_SEL(UART_RTS_HSIOM_REG, UART_RTS_HSIOM_MASK, + UART_RTS_HSIOM_POS, UART_RTS_HSIOM_SEL_UART); + #endif /* (UART_UART_RTS_PIN) */ +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + + /* Restore TX interrupt sources. */ + UART_SetTxInterruptMode(UART_IntrTxMask); +} + + +/******************************************************************************* +* Function Name: UART_UartStop +****************************************************************************//** +* +* Changes the HSIOM settings for the UART output pins (TX and/or RTS) to keep +* them inactive after the block is disabled. The output pins are controlled by +* the GPIO data register. Also, the function disables the skip start feature +* to not cause it to trigger after the component is enabled. +* +*******************************************************************************/ +void UART_UartStop(void) +{ +#if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + #if (UART_TX_SDA_MISO_PIN) + if (UART_CHECK_TX_SDA_MISO_PIN_USED) + { + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, UART_TX_SDA_MISO_HSIOM_MASK, + UART_TX_SDA_MISO_HSIOM_POS, UART_TX_SDA_MISO_HSIOM_SEL_GPIO); + } + #endif /* (UART_TX_SDA_MISO_PIN_PIN) */ + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + #if (UART_SS0_PIN) + if (UART_CHECK_SS0_PIN_USED) + { + /* Set output pin state after block is disabled */ + UART_spi_ss0_Write(UART_GET_UART_RTS_INACTIVE); + + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, UART_SS0_HSIOM_MASK, + UART_SS0_HSIOM_POS, UART_SS0_HSIOM_SEL_GPIO); + } + #endif /* (UART_SS0_PIN) */ + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#else + #if (UART_UART_TX_PIN) + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_TX_HSIOM_REG, UART_TX_HSIOM_MASK, + UART_TX_HSIOM_POS, UART_TX_HSIOM_SEL_GPIO); + #endif /* (UART_UART_TX_PIN) */ + + #if (UART_UART_RTS_PIN) + /* Set output pin state after block is disabled */ + UART_rts_Write(UART_GET_UART_RTS_INACTIVE); + + /* Set GPIO to drive output pin */ + UART_SET_HSIOM_SEL(UART_RTS_HSIOM_REG, UART_RTS_HSIOM_MASK, + UART_RTS_HSIOM_POS, UART_RTS_HSIOM_SEL_GPIO); + #endif /* (UART_UART_RTS_PIN) */ + +#endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (UART_UART_WAKE_ENABLE_CONST) + /* Disable skip start feature used for wakeup */ + UART_UART_RX_CTRL_REG &= (uint32) ~UART_UART_RX_CTRL_SKIP_START; +#endif /* (UART_UART_WAKE_ENABLE_CONST) */ + + /* Store TX interrupt sources (exclude level triggered). */ + UART_IntrTxMask = LO16(UART_GetTxInterruptMode() & UART_INTR_UART_TX_RESTORE); +} + + +/******************************************************************************* +* Function Name: UART_UartSetRxAddress +****************************************************************************//** +* +* Sets the hardware detectable receiver address for the UART in the +* Multiprocessor mode. +* +* \param address: Address for hardware address detection. +* +*******************************************************************************/ +void UART_UartSetRxAddress(uint32 address) +{ + uint32 matchReg; + + matchReg = UART_RX_MATCH_REG; + + matchReg &= ((uint32) ~UART_RX_MATCH_ADDR_MASK); /* Clear address bits */ + matchReg |= ((uint32) (address & UART_RX_MATCH_ADDR_MASK)); /* Set address */ + + UART_RX_MATCH_REG = matchReg; +} + + +/******************************************************************************* +* Function Name: UART_UartSetRxAddressMask +****************************************************************************//** +* +* Sets the hardware address mask for the UART in the Multiprocessor mode. +* +* \param addressMask: Address mask. +* - Bit value 0 – excludes bit from address comparison. +* - Bit value 1 – the bit needs to match with the corresponding bit +* of the address. +* +*******************************************************************************/ +void UART_UartSetRxAddressMask(uint32 addressMask) +{ + uint32 matchReg; + + matchReg = UART_RX_MATCH_REG; + + matchReg &= ((uint32) ~UART_RX_MATCH_MASK_MASK); /* Clear address mask bits */ + matchReg |= ((uint32) (addressMask << UART_RX_MATCH_MASK_POS)); + + UART_RX_MATCH_REG = matchReg; +} + + +#if(UART_UART_RX_DIRECTION) + /******************************************************************************* + * Function Name: UART_UartGetChar + ****************************************************************************//** + * + * Retrieves next data element from receive buffer. + * This function is designed for ASCII characters and returns a char where + * 1 to 255 are valid characters and 0 indicates an error occurred or no data + * is present. + * - RX software buffer is disabled: Returns data element retrieved from RX + * FIFO. + * - RX software buffer is enabled: Returns data element from the software + * receive buffer. + * + * \return + * Next data element from the receive buffer. ASCII character values from + * 1 to 255 are valid. A returned zero signifies an error condition or no + * data available. + * + * \sideeffect + * The errors bits may not correspond with reading characters due to + * RX FIFO and software buffer usage. + * RX software buffer is enabled: The internal software buffer overflow + * is not treated as an error condition. + * Check UART_rxBufferOverflow to capture that error condition. + * + *******************************************************************************/ + uint32 UART_UartGetChar(void) + { + uint32 rxData = 0u; + + /* Reads data only if there is data to read */ + if (0u != UART_SpiUartGetRxBufferSize()) + { + rxData = UART_SpiUartReadRxData(); + } + + if (UART_CHECK_INTR_RX(UART_INTR_RX_ERR)) + { + rxData = 0u; /* Error occurred: returns zero */ + UART_ClearRxInterruptSource(UART_INTR_RX_ERR); + } + + return (rxData); + } + + + /******************************************************************************* + * Function Name: UART_UartGetByte + ****************************************************************************//** + * + * Retrieves the next data element from the receive buffer, returns the + * received byte and error condition. + * - The RX software buffer is disabled: returns the data element retrieved + * from the RX FIFO. Undefined data will be returned if the RX FIFO is + * empty. + * - The RX software buffer is enabled: returns data element from the + * software receive buffer. + * + * \return + * Bits 7-0 contain the next data element from the receive buffer and + * other bits contain the error condition. + * - UART_UART_RX_OVERFLOW - Attempt to write to a full + * receiver FIFO. + * - UART_UART_RX_UNDERFLOW Attempt to read from an empty + * receiver FIFO. + * - UART_UART_RX_FRAME_ERROR - UART framing error detected. + * - UART_UART_RX_PARITY_ERROR - UART parity error detected. + * + * \sideeffect + * The errors bits may not correspond with reading characters due to + * RX FIFO and software buffer usage. + * RX software buffer is enabled: The internal software buffer overflow + * is not treated as an error condition. + * Check UART_rxBufferOverflow to capture that error condition. + * + *******************************************************************************/ + uint32 UART_UartGetByte(void) + { + uint32 rxData; + uint32 tmpStatus; + + #if (UART_CHECK_RX_SW_BUFFER) + { + UART_DisableInt(); + } + #endif + + if (0u != UART_SpiUartGetRxBufferSize()) + { + /* Enables interrupt to receive more bytes: at least one byte is in + * buffer. + */ + #if (UART_CHECK_RX_SW_BUFFER) + { + UART_EnableInt(); + } + #endif + + /* Get received byte */ + rxData = UART_SpiUartReadRxData(); + } + else + { + /* Reads a byte directly from RX FIFO: underflow is raised in the + * case of empty. Otherwise the first received byte will be read. + */ + rxData = UART_RX_FIFO_RD_REG; + + + /* Enables interrupt to receive more bytes. */ + #if (UART_CHECK_RX_SW_BUFFER) + { + + /* The byte has been read from RX FIFO. Clear RX interrupt to + * not involve interrupt handler when RX FIFO is empty. + */ + UART_ClearRxInterruptSource(UART_INTR_RX_NOT_EMPTY); + + UART_EnableInt(); + } + #endif + } + + /* Get and clear RX error mask */ + tmpStatus = (UART_GetRxInterruptSource() & UART_INTR_RX_ERR); + UART_ClearRxInterruptSource(UART_INTR_RX_ERR); + + /* Puts together data and error status: + * MP mode and accept address: 9th bit is set to notify mark. + */ + rxData |= ((uint32) (tmpStatus << 8u)); + + return (rxData); + } + + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UART_UartSetRtsPolarity + ****************************************************************************//** + * + * Sets active polarity of RTS output signal. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param polarity: Active polarity of RTS output signal. + * - UART_UART_RTS_ACTIVE_LOW - RTS signal is active low. + * - UART_UART_RTS_ACTIVE_HIGH - RTS signal is active high. + * + *******************************************************************************/ + void UART_UartSetRtsPolarity(uint32 polarity) + { + if(0u != polarity) + { + UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_RTS_POLARITY; + } + else + { + UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_RTS_POLARITY; + } + } + + + /******************************************************************************* + * Function Name: UART_UartSetRtsFifoLevel + ****************************************************************************//** + * + * Sets level in the RX FIFO for RTS signal activation. + * While the RX FIFO has fewer entries than the RX FIFO level the RTS signal + * remains active, otherwise the RTS signal becomes inactive. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param level: Level in the RX FIFO for RTS signal activation. + * The range of valid level values is between 0 and RX FIFO depth - 1. + * Setting level value to 0 disables RTS signal activation. + * + *******************************************************************************/ + void UART_UartSetRtsFifoLevel(uint32 level) + { + uint32 uartFlowCtrl; + + uartFlowCtrl = UART_UART_FLOW_CTRL_REG; + + uartFlowCtrl &= ((uint32) ~UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + uartFlowCtrl |= ((uint32) (UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_UART_FLOW_CTRL_REG = uartFlowCtrl; + } + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + +#endif /* (UART_UART_RX_DIRECTION) */ + + +#if(UART_UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_UartPutString + ****************************************************************************//** + * + * Places a NULL terminated string in the transmit buffer to be sent at the + * next available bus time. + * This function is blocking and waits until there is a space available to put + * requested data in transmit buffer. + * + * \param string: pointer to the null terminated string array to be placed in the + * transmit buffer. + * + *******************************************************************************/ + void UART_UartPutString(const char8 string[]) + { + uint32 bufIndex; + + bufIndex = 0u; + + /* Blocks the control flow until all data has been sent */ + while(string[bufIndex] != ((char8) 0)) + { + UART_UartPutChar((uint32) string[bufIndex]); + bufIndex++; + } + } + + + /******************************************************************************* + * Function Name: UART_UartPutCRLF + ****************************************************************************//** + * + * Places byte of data followed by a carriage return (0x0D) and line feed + * (0x0A) in the transmit buffer. + * This function is blocking and waits until there is a space available to put + * all requested data in transmit buffer. + * + * \param txDataByte: the data to be transmitted. + * + *******************************************************************************/ + void UART_UartPutCRLF(uint32 txDataByte) + { + UART_UartPutChar(txDataByte); /* Blocks control flow until all data has been sent */ + UART_UartPutChar(0x0Du); /* Blocks control flow until all data has been sent */ + UART_UartPutChar(0x0Au); /* Blocks control flow until all data has been sent */ + } + + + #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UARTSCB_UartEnableCts + ****************************************************************************//** + * + * Enables usage of CTS input signal by the UART transmitter. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + *******************************************************************************/ + void UART_UartEnableCts(void) + { + UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_CTS_ENABLE; + } + + + /******************************************************************************* + * Function Name: UART_UartDisableCts + ****************************************************************************//** + * + * Disables usage of CTS input signal by the UART transmitter. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + *******************************************************************************/ + void UART_UartDisableCts(void) + { + UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_CTS_ENABLE; + } + + + /******************************************************************************* + * Function Name: UART_UartSetCtsPolarity + ****************************************************************************//** + * + * Sets active polarity of CTS input signal. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param + * polarity: Active polarity of CTS output signal. + * - UART_UART_CTS_ACTIVE_LOW - CTS signal is active low. + * - UART_UART_CTS_ACTIVE_HIGH - CTS signal is active high. + * + *******************************************************************************/ + void UART_UartSetCtsPolarity(uint32 polarity) + { + if (0u != polarity) + { + UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_CTS_POLARITY; + } + else + { + UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_CTS_POLARITY; + } + } + #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + + + /******************************************************************************* + * Function Name: UART_UartSendBreakBlocking + ****************************************************************************//** + * + * Sends a break condition (logic low) of specified width on UART TX line. + * Blocks until break is completed. Only call this function when UART TX FIFO + * and shifter are empty. + * + * \param breakWidth + * Width of break condition. Valid range is 4 to 16 bits. + * + * \note + * Before sending break all UART TX interrupt sources are disabled. The state + * of UART TX interrupt sources is restored before function returns. + * + * \sideeffect + * If this function is called while there is data in the TX FIFO or shifter that + * data will be shifted out in packets the size of breakWidth. + * + *******************************************************************************/ + void UART_UartSendBreakBlocking(uint32 breakWidth) + { + uint32 txCtrlReg; + uint32 txIntrReg; + + /* Disable all UART TX interrupt source and clear UART TX Done history */ + txIntrReg = UART_GetTxInterruptMode(); + UART_SetTxInterruptMode(0u); + UART_ClearTxInterruptSource(UART_INTR_TX_UART_DONE); + + /* Store TX CTRL configuration */ + txCtrlReg = UART_TX_CTRL_REG; + + /* Set break width */ + UART_TX_CTRL_REG = (UART_TX_CTRL_REG & (uint32) ~UART_TX_CTRL_DATA_WIDTH_MASK) | + UART_GET_TX_CTRL_DATA_WIDTH(breakWidth); + + /* Generate break */ + UART_TX_FIFO_WR_REG = 0u; + + /* Wait for break completion */ + while (0u == (UART_GetTxInterruptSource() & UART_INTR_TX_UART_DONE)) + { + } + + /* Clear all UART TX interrupt sources to */ + UART_ClearTxInterruptSource(UART_INTR_TX_ALL); + + /* Restore TX interrupt sources and data width */ + UART_TX_CTRL_REG = txCtrlReg; + UART_SetTxInterruptMode(txIntrReg); + } +#endif /* (UART_UART_TX_DIRECTION) */ + + +#if (UART_UART_WAKE_ENABLE_CONST) + /******************************************************************************* + * Function Name: UART_UartSaveConfig + ****************************************************************************//** + * + * Clears and enables an interrupt on a falling edge of the Rx input. The GPIO + * interrupt does not track in the active mode, therefore requires to be + * cleared by this API. + * + *******************************************************************************/ + void UART_UartSaveConfig(void) + { + #if (UART_UART_RX_WAKEUP_IRQ) + /* Set SKIP_START if requested (set by default). */ + if (0u != UART_skipStart) + { + UART_UART_RX_CTRL_REG |= (uint32) UART_UART_RX_CTRL_SKIP_START; + } + else + { + UART_UART_RX_CTRL_REG &= (uint32) ~UART_UART_RX_CTRL_SKIP_START; + } + + /* Clear RX GPIO interrupt status and pending interrupt in NVIC because + * falling edge on RX line occurs while UART communication in active mode. + * Enable interrupt: next interrupt trigger should wakeup device. + */ + UART_CLEAR_UART_RX_WAKE_INTR; + UART_RxWakeClearPendingInt(); + UART_RxWakeEnableInt(); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + } + + + /******************************************************************************* + * Function Name: UART_UartRestoreConfig + ****************************************************************************//** + * + * Disables the RX GPIO interrupt. Until this function is called the interrupt + * remains active and triggers on every falling edge of the UART RX line. + * + *******************************************************************************/ + void UART_UartRestoreConfig(void) + { + #if (UART_UART_RX_WAKEUP_IRQ) + /* Disable interrupt: no more triggers in active mode */ + UART_RxWakeDisableInt(); + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + } + + + #if (UART_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: UART_UART_WAKEUP_ISR + ****************************************************************************//** + * + * Handles the Interrupt Service Routine for the SCB UART mode GPIO wakeup + * event. This event is configured to trigger on a falling edge of the RX line. + * + *******************************************************************************/ + CY_ISR(UART_UART_WAKEUP_ISR) + { + #ifdef UART_UART_WAKEUP_ISR_ENTRY_CALLBACK + UART_UART_WAKEUP_ISR_EntryCallback(); + #endif /* UART_UART_WAKEUP_ISR_ENTRY_CALLBACK */ + + UART_CLEAR_UART_RX_WAKE_INTR; + + #ifdef UART_UART_WAKEUP_ISR_EXIT_CALLBACK + UART_UART_WAKEUP_ISR_ExitCallback(); + #endif /* UART_UART_WAKEUP_ISR_EXIT_CALLBACK */ + } + #endif /* (UART_UART_RX_WAKEUP_IRQ) */ +#endif /* (UART_UART_RX_WAKEUP_IRQ) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_UART_BOOT.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_UART_BOOT.c new file mode 100644 index 0000000..cd16e78 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_UART_BOOT.c @@ -0,0 +1,189 @@ +/***************************************************************************//** +* \file UART_UART_BOOT.c +* \version 4.0 +* +* \brief +* This file provides the source code of the bootloader communication APIs +* for the SCB Component UART mode. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_BOOT.h" +#include "UART_SPI_UART.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && (UART_UART_BTLDR_COMM_ENABLED) + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommStart +****************************************************************************//** +* +* Starts the UART component. +* +*******************************************************************************/ +void UART_UartCyBtldrCommStart(void) +{ + UART_Start(); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommStop +****************************************************************************//** +* +* Disables the UART component. +* +*******************************************************************************/ +void UART_UartCyBtldrCommStop(void) +{ + UART_Stop(); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommReset +****************************************************************************//** +* +* Resets the receive and transmit communication buffers. +* +*******************************************************************************/ +void UART_UartCyBtldrCommReset(void) +{ + /* Clear RX and TX buffers */ + UART_SpiUartClearRxBuffer(); + UART_SpiUartClearTxBuffer(); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommRead +****************************************************************************//** +* +* Allows the caller to read data from the bootloader host (the host writes the +* data). The function handles polling to allow a block of data to be completely +* received from the host device. +* +* \param pData: Pointer to storage for the block of data to be read from the +* bootloader host +* \param size: Number of bytes to be read. +* \param count: Pointer to the variable to write the number of bytes actually +* read. +* \param timeOut Number of units in 10 ms to wait before returning +* because of a timeout. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus UART_UartCyBtldrCommRead(uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + uint32 byteCount; + uint32 timeoutMs; + uint32 i; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + status = CYRET_TIMEOUT; + timeoutMs = ((uint32) 10u * timeOut); /* Convert from 10mS check to 1mS checks */ + + /* Wait with timeout 1mS for packet end */ + byteCount = 0u; + do + { + /* Check packet start */ + if (0u != UART_SpiUartGetRxBufferSize()) + { + /* Wait for end of packet */ + do + { + byteCount = UART_SpiUartGetRxBufferSize(); + CyDelayUs(UART_UART_BYTE_TO_BYTE); + } + while (byteCount != UART_SpiUartGetRxBufferSize()); + + byteCount = UART_BYTES_TO_COPY(byteCount, size); + *count = (uint16) byteCount; + status = CYRET_SUCCESS; + + break; + } + + CyDelay(UART_WAIT_1_MS); + --timeoutMs; + } + while (0u != timeoutMs); + + /* Get data from RX buffer into bootloader buffer */ + for (i = 0u; i < byteCount; ++i) + { + pData[i] = (uint8) UART_SpiUartReadRxData(); + } + } + + return (status); +} + + +/******************************************************************************* +* Function Name: UART_UartCyBtldrCommWrite +****************************************************************************//** +* +* Allows the caller to write data to the bootloader host (the host reads the +* data). The function does not use timeout and returns after data has been +* copied into the transmit buffer. The data transmission starts immediately +* after the first data element is written into the buffer and lasts until all +* data elements from the buffer are sent. +* +* \param pData: Pointer to the block of data to be written to the bootloader +* host. +* \param size: Number of bytes to be written. +* \param count: Pointer to the variable to write the number of bytes actually +* written. +* \param timeOut: The timeout is not used by this function. +* The function returns as soon as data is copied into the transmit buffer. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus UART_UartCyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + /* Transmit data. This function does not wait until data is sent. */ + UART_SpiUartPutArray(pData, (uint32) size); + + *count = size; + status = CYRET_SUCCESS; + + if (0u != timeOut) + { + /* Suppress compiler warning */ + } + } + + return (status); +} + +#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (UART_UART_BTLDR_COMM_ENABLED) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx.c new file mode 100644 index 0000000..2a025d1 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: UART_tx.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_tx.h" + + +#if defined(UART_tx__PC) + #define UART_tx_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_tx_PC = (UART_tx_PC & \ + (uint32)(~(uint32)(UART_tx_DRIVE_MODE_IND_MASK << \ + (UART_tx_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_tx_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define UART_tx_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_tx_USBIO_CTRL_REG = (UART_tx_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(UART_tx_DRIVE_MODE_IND_MASK << \ + (UART_tx_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_tx_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(UART_tx__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: UART_tx_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet UART_tx_SUT.c usage_UART_tx_SetDriveMode + *******************************************************************************/ + void UART_tx_SetDriveMode(uint8 mode) + { + UART_tx_SetP4PinDriveMode(UART_tx__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: UART_tx_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_Write +*******************************************************************************/ +void UART_tx_Write(uint8 value) +{ + uint8 drVal = (uint8)(UART_tx_DR & (uint8)(~UART_tx_MASK)); + drVal = (drVal | ((uint8)(value << UART_tx_SHIFT) & UART_tx_MASK)); + UART_tx_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: UART_tx_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_Read +*******************************************************************************/ +uint8 UART_tx_Read(void) +{ + return (uint8)((UART_tx_PS & UART_tx_MASK) >> UART_tx_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_tx_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred UART_tx_Read() API because the +* UART_tx_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_ReadDataReg +*******************************************************************************/ +uint8 UART_tx_ReadDataReg(void) +{ + return (uint8)((UART_tx_DR & UART_tx_MASK) >> UART_tx_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_tx_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use UART_tx_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - UART_tx_0_INTR (First pin in the list) +* - UART_tx_1_INTR (Second pin in the list) +* - ... +* - UART_tx_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_SetInterruptMode +*******************************************************************************/ +void UART_tx_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = UART_tx_INTCFG & (uint32)(~(uint32)position); + UART_tx_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: UART_tx_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_ClearInterrupt +*******************************************************************************/ +uint8 UART_tx_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(UART_tx_INTSTAT & UART_tx_MASK); + UART_tx_INTSTAT = maskedStatus; + return maskedStatus >> UART_tx_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx.h new file mode 100644 index 0000000..bdcfe1c --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: UART_tx.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_tx_H) /* Pins UART_tx_H */ +#define CY_PINS_UART_tx_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "UART_tx_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} UART_tx_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 UART_tx_Read(void); +void UART_tx_Write(uint8 value); +uint8 UART_tx_ReadDataReg(void); +#if defined(UART_tx__PC) || (CY_PSOC4_4200L) + void UART_tx_SetDriveMode(uint8 mode); +#endif +void UART_tx_SetInterruptMode(uint16 position, uint16 mode); +uint8 UART_tx_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void UART_tx_Sleep(void); +void UART_tx_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(UART_tx__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define UART_tx_DRIVE_MODE_BITS (3) + #define UART_tx_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - UART_tx_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the UART_tx_SetDriveMode() function. + * @{ + */ + #define UART_tx_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define UART_tx_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define UART_tx_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define UART_tx_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define UART_tx_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define UART_tx_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define UART_tx_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define UART_tx_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define UART_tx_MASK UART_tx__MASK +#define UART_tx_SHIFT UART_tx__SHIFT +#define UART_tx_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in UART_tx_SetInterruptMode() function. + * @{ + */ + #define UART_tx_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define UART_tx_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define UART_tx_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define UART_tx_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(UART_tx__SIO) + #define UART_tx_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(UART_tx__PC) && (CY_PSOC4_4200L) + #define UART_tx_USBIO_ENABLE ((uint32)0x80000000u) + #define UART_tx_USBIO_DISABLE ((uint32)(~UART_tx_USBIO_ENABLE)) + #define UART_tx_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define UART_tx_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define UART_tx_USBIO_ENTER_SLEEP ((uint32)((1u << UART_tx_USBIO_SUSPEND_SHIFT) \ + | (1u << UART_tx_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_tx_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << UART_tx_USBIO_SUSPEND_SHIFT))) + #define UART_tx_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << UART_tx_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_tx_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(UART_tx__PC) + /* Port Configuration */ + #define UART_tx_PC (* (reg32 *) UART_tx__PC) +#endif +/* Pin State */ +#define UART_tx_PS (* (reg32 *) UART_tx__PS) +/* Data Register */ +#define UART_tx_DR (* (reg32 *) UART_tx__DR) +/* Input Buffer Disable Override */ +#define UART_tx_INP_DIS (* (reg32 *) UART_tx__PC2) + +/* Interrupt configuration Registers */ +#define UART_tx_INTCFG (* (reg32 *) UART_tx__INTCFG) +#define UART_tx_INTSTAT (* (reg32 *) UART_tx__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define UART_tx_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(UART_tx__SIO) + #define UART_tx_SIO_REG (* (reg32 *) UART_tx__SIO) +#endif /* (UART_tx__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(UART_tx__PC) && (CY_PSOC4_4200L) + #define UART_tx_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define UART_tx_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define UART_tx_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define UART_tx_DRIVE_MODE_SHIFT (0x00u) +#define UART_tx_DRIVE_MODE_MASK (0x07u << UART_tx_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins UART_tx_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx_PM.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx_PM.c new file mode 100644 index 0000000..d72f2ee --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: UART_tx.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_tx.h" + +static UART_tx_BACKUP_STRUCT UART_tx_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: UART_tx_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet UART_tx_SUT.c usage_UART_tx_Sleep_Wakeup +*******************************************************************************/ +void UART_tx_Sleep(void) +{ + #if defined(UART_tx__PC) + UART_tx_backup.pcState = UART_tx_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + UART_tx_backup.usbState = UART_tx_CR1_REG; + UART_tx_USB_POWER_REG |= UART_tx_USBIO_ENTER_SLEEP; + UART_tx_CR1_REG &= UART_tx_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_tx__SIO) + UART_tx_backup.sioState = UART_tx_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + UART_tx_SIO_REG &= (uint32)(~UART_tx_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: UART_tx_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to UART_tx_Sleep() for an example usage. +*******************************************************************************/ +void UART_tx_Wakeup(void) +{ + #if defined(UART_tx__PC) + UART_tx_PC = UART_tx_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + UART_tx_USB_POWER_REG &= UART_tx_USBIO_EXIT_SLEEP_PH1; + UART_tx_CR1_REG = UART_tx_backup.usbState; + UART_tx_USB_POWER_REG &= UART_tx_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_tx__SIO) + UART_tx_SIO_REG = UART_tx_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx_aliases.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx_aliases.h new file mode 100644 index 0000000..14254ae --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/UART_tx_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: UART_tx.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_tx_ALIASES_H) /* Pins UART_tx_ALIASES_H */ +#define CY_PINS_UART_tx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define UART_tx_0 (UART_tx__0__PC) +#define UART_tx_0_PS (UART_tx__0__PS) +#define UART_tx_0_PC (UART_tx__0__PC) +#define UART_tx_0_DR (UART_tx__0__DR) +#define UART_tx_0_SHIFT (UART_tx__0__SHIFT) +#define UART_tx_0_INTR ((uint16)((uint16)0x0003u << (UART_tx__0__SHIFT*2u))) + +#define UART_tx_INTR_ALL ((uint16)(UART_tx_0_INTR)) + + +#endif /* End Pins UART_tx_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/bitstream.txt b/TrainingProjects/ADC-UART.cydsn/codegentemp/bitstream.txt new file mode 100644 index 0000000..06d03bd --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/bitstream.txt @@ -0,0 +1,498 @@ +===========Generating Bitstream=========== +# IOPINS0_0 (count=28) +00000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000010: 00 00 00 00 00 00 00 00 00 00 00 00 +# UDB_PA_0 (count=15) +0000001c: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +# UDB_PA_1 (count=15) +0000002b: 00 00 99 00 00 00 00 00 00 00 00 00 00 00 00 +# IOPINS0_1 (count=28) +0000003a: 40 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 +0000004a: 00 00 00 00 00 00 00 00 00 00 00 00 +# UDB_PA_2 (count=15) +00000056: 00 00 99 00 00 00 00 00 00 00 00 00 00 00 00 +# IOPINS0_2 (count=28) +00000065: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000075: 00 00 00 00 00 00 00 00 08 00 00 00 +# UDB_PA_3 (count=15) +00000081: 00 00 99 00 00 00 00 00 00 00 00 00 00 00 00 +# IOPINS0_3 (count=28) +00000090: 00 00 00 00 00 00 00 00 80 0d 00 00 00 00 00 00 +000000a0: 00 00 00 00 00 00 00 00 00 00 00 00 +# IOPINS0_4 (count=28) +000000ac: 02 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 +000000bc: 00 00 00 00 00 00 00 00 02 00 00 00 +# INT_SELECT (count=4) +000000c8: 00 00 00 00 +# INT_CONFIG (count=4) +000000cc: 00 00 00 00 +# CYDEV_CLK_SELECT00 (count=64) +000000d0: 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 +000000e0: 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 +000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# CYDEV_CLK_IMO_CONFIG (count=4) +00000110: 00 00 00 82 +# CYDEV_CLK_ILO_CONFIG (count=4) +00000114: 06 00 00 80 +# CYDEV_CLK_SELECT (count=4) +00000118: 00 00 00 00 +# CYDEV_WDT_CONFIG (count=4) +0000011c: 00 00 00 00 +# CYDEV_CLK_DIVIDER_A00 (count=4) +00000120: 17 00 00 80 +# CYDEV_CLK_DIVIDER_B00 (count=4) +00000124: 38 01 00 80 +# CYDEV_CLK_DIVIDER_C00 (count=4) +00000128: 00 00 00 00 +# CYDEV_CLK_DIVIDER_A01 (count=4) +0000012c: 00 00 00 00 +# CYDEV_CLK_DIVIDER_B01 (count=4) +00000130: 00 00 00 00 +# CYDEV_CLK_DIVIDER_C01 (count=4) +00000134: 00 00 00 00 +# CYDEV_CLK_DIVIDER_A02 (count=4) +00000138: 00 00 00 00 +# CYDEV_CLK_DIVIDER_B02 (count=4) +0000013c: 00 00 00 00 +# CYDEV_CLK_DIVIDER_C02 (count=4) +00000140: 00 00 00 00 +# CYDEV_CLK_DIVIDER_FRAC_A00 (count=4) +00000144: 00 00 00 00 +# CYDEV_CLK_DIVIDER_FRAC_B00 (count=4) +00000148: 00 00 00 00 +# CYDEV_CLK_DIVIDER_FRAC_C00 (count=4) +0000014c: 00 00 00 00 +# UDB_0_1_0_CONFIG (count=128) +00000150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDB_0_1_1_CONFIG (count=128) +000001d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDB_0_0_1_CONFIG (count=128) +00000250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDB_0_0_0_CONFIG (count=128) +000002d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000310: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UWRK_B0_WRK_DP_BITS (count=64) +00000350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UWRK_B0_WRK_STATCTL_BITS + 0x00000070 (count=32) +00000390: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000003a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDB_BCTL0_DRV (count=3) +000003b0: 00 00 00 +# UDB_BCTL0_BOTSEL_L (count=12) +000003b3: 00 00 00 00 00 00 00 00 00 00 00 00 +# DSISWITCH_0_0 (count=128) +000003bf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000003cf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000003df: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000003ef: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000003ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000040f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000041f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000042f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# DSI0_0_HV_ROUTING + 0x00000080 (count=128) +0000043f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000044f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000045f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000046f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000047f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000048f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000049f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000004af: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# DSISWITCH_0_1 (count=128) +000004bf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000004cf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000004df: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000004ef: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000004ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000050f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000051f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000052f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# DSI0_1_HV_ROUTING + 0x00000080 (count=128) +0000053f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000054f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000055f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000056f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000057f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000058f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000059f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000005af: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDBSWITCH_0_0 (count=128) +000005bf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000005cf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000005df: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000005ef: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000005ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000060f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000061f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000062f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDB_1_0_HV_ROUTING + 0x00000080 (count=128) +0000063f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000064f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000065f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000066f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000067f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000068f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000069f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000006af: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDBSWITCH_0_1 (count=128) +000006bf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000006cf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000006df: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000006ef: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000006ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000070f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000071f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000072f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# UDB_1_1_HV_ROUTING + 0x00000080 (count=128) +0000073f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000074f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000075f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000076f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000077f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000078f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000079f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000007af: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# DSISWITCH_1_0 (count=128) +000007bf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000007cf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000007df: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000007ef: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000007ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000080f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000081f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000082f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# DSI2_0_HV_ROUTING + 0x00000080 (count=128) +0000083f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000084f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000085f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000086f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000087f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000088f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000089f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000008af: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# DSISWITCH_1_1 (count=128) +000008bf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000008cf: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000008df: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000008ef: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000008ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000090f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000091f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000092f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# DSI2_1_HV_ROUTING + 0x00000080 (count=128) +0000093f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000094f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000095f: 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000194f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000195f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000196f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000197f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000198f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000199f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000019af: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cm0gcc.ld b/TrainingProjects/ADC-UART.cydsn/codegentemp/cm0gcc.ld new file mode 100644 index 0000000..b2b139d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cm0gcc.ld @@ -0,0 +1,475 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(Reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + + +/* Code sharing support */ +INCLUDE cycodeshareexport.ld +INCLUDE cycodeshareimport.ld + + +MEMORY +{ + rom (rx) : ORIGIN = 0x0, LENGTH = 32768 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4096 +} + + +CY_APPL_ORIGIN = 0; +CY_FLASH_ROW_SIZE = 128; +CY_APPL_NUM = 1; +CY_APPL_MAX = 1; +CY_METADATA_SIZE = 64; +CY_APPL_LOADABLE = 0; +CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(0, CY_FLASH_ROW_SIZE); +CY_APP_FOR_STACK_AND_COPIER = 0; + + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(Reset) + +/* Bring in the interrupt routines & vector */ +EXTERN(main) + +/* Bring in the romvector */ +EXTERN(RomVectors) + +/* Bring in the ramvector */ +EXTERN(CyRamVectors) + +/* Bring in the meta data */ +EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) +EXTERN(cy_meta_flashprotect cy_metadata cy_meta_chipprotect) +EXTERN(cy_heap) + +/* Provide fall-back values */ +PROVIDE(__cy_heap_start = _end); +PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); + +/* Set stack top to end of RAM, and stack limit move down by + * size of .stack section. + */ +PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); + +PROVIDE(__cy_heap_end = __cy_stack - 0x0400); + + +SECTIONS +{ + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + + + cy_project_type_bootloader = (appl_start == 0) ? 1 : 0; + cy_project_type_app_for_stack_and_copier = (CY_APP_FOR_STACK_AND_COPIER == 1) ? 1 : 0; + + + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); + + KEEP(*(.romvectors)) + + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + + PROVIDE(__cy_reset = Reset); + + *(.text.Reset) + + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); + + *(.psocinit) + + /* The first 0x100 Flash bytes become unavailable right after remapping of the vector table to RAM. */ + . = MAX(., 0x100); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + + __exidx_end = .; + + + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + + /*************************************************************************** + * Checksum Exclude Section for non-bootloadable projects. See below. + ***************************************************************************/ + .cy_checksum_exclude : { KEEP(*(.cy_checksum_exclude)) } >rom + + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + + + + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x0100; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x0400) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x0400; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + + /*************************************************************************** + * Checksum Exclude Section + *************************************************************************** + * + * For the normal and bootloader projects this section is placed at any + * place. For the Bootloadable applications, it is placed at the specific + * address. + * + * Case # 1. Bootloadable application + * + * _______________________________ + * | Metadata (BTLDBL) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | | + * | | + * | BTLDBL | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDR | + * |_______________________________| + * + * + * Case # 2. Bootloadable application for Dual-Application Bootloader + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 2 | + * |_______________________________|____BTLDBL # 2 Start address___ + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + * + * + * Case # 3. OTA updatable stack + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * | | + * |-------------------------------| + * |_______________________________|____Temporary location for BTLDBL # 1 update(Former BTLDBL # 2 start)___ + * | | + * | BTLDBL # 2 | + * | | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + */ + + + + /* Bootloadable applications only: verify that size of the data in the section is within the specified limit. */ + cy_checksum_exclude_size = (CY_APPL_LOADABLE == 1) ? SIZEOF(.cy_checksum_exclude) : 0; + ASSERT(cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE, "CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.") + + + /*************************************************************************** + * Bootloader Metadata Section + *************************************************************************** + * + * Case # 1. Bootloader project + * + * _______________________________ + * | BTLDR Metadata | + * |-------------------------------| + * | | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | Bootloader (BTLDR) | + * |_______________________________| + * + * + * Case # 2. Code sharing + * + * _______________________________ + * | SP/L Metadata | CY_APPL_METADATA_SLOT_NUM == 0 + * |-------------------------------| + * | App for SP+L Metadata | CY_APPL_METADATA_SLOT_NUM == 1 + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | App for SP+L | ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + * | | + * |-------------------------------| + * | | + * | Stack Project (SP) | (CYDEV_IS_EXPORTING_CODE == 1) + * | | + * |-------------------------------| + * | | + * | Launcher (L) | + * |_______________________________| + * + * Notes: + * - App for SP+L start just after the SP + * - SP treated as a single bootloadable application + * - App for SP+L treats SP+L as a bootloader + */ + + /* For the bootloader project, place bootloader metadata at the last flash row, otherwise place beyond map */ + cyloadermeta_start = (cy_project_type_bootloader || cy_project_type_app_for_stack_and_copier) ? + (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000; + .cyloadermeta (cyloadermeta_start) : + { + KEEP(*(.cyloadermeta)) + } : NONE + + + cyloadablemeta_start = (cy_project_type_app_for_stack_and_copier) ? + (LENGTH(rom) - CY_FLASH_ROW_SIZE - CY_METADATA_SIZE) : (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE); + .cyloadablemeta (cyloadablemeta_start) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + .cychipprotect 0x90600000 : { KEEP(*(.cychipprotect)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_armcc.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_armcc.h new file mode 100644 index 0000000..234ea5e --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_armcc.h @@ -0,0 +1,791 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 27. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_compiler.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_compiler.h new file mode 100644 index 0000000..658bd96 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_compiler.h @@ -0,0 +1,210 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V5.00 + * @date 09. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include + + #ifndef __NO_RETURN + #define __NO_RETURN __noreturn + #endif + #ifndef __USED + #define __USED __root + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + __packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_gcc.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_gcc.h new file mode 100644 index 0000000..1b85b91 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cmsis_gcc.h @@ -0,0 +1,1894 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 28. October 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef _WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1U)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1U)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cm0.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cm0.h new file mode 100644 index 0000000..41b07f5 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cm0.h @@ -0,0 +1,820 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.00 + * @date 13. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cm0_psoc4.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cm0_psoc4.h new file mode 100644 index 0000000..51de779 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cm0_psoc4.h @@ -0,0 +1,43 @@ +/******************************************************************************* +* \file core_cm0_psoc4.h +* \version 5.70 +* +* \brief Provides important type information for the PSOC4 device family. +* This includes types necessary for core_cm0.h. +* +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_BOOT_CORE_CM0_PSOC4_H) +#define CY_BOOT_CORE_CM0_PSOC4_H + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M0 System Tick Interrupt */ +/****** PSOC4 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#define __CHECK_DEVICE_DEFINES + +#define __CM0_REV 0x0000 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +#include + +#endif /* CY_BOOT_CORE_CM0_PSOC4_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cmFunc.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cmFunc.h new file mode 100644 index 0000000..652a48a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cmInstr.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cmInstr.h new file mode 100644 index 0000000..f474b0e --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyPm.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyPm.c new file mode 100644 index 0000000..3181e33 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyPm.c @@ -0,0 +1,435 @@ +/***************************************************************************//** +* \file cyPm.c +* \version 5.70 +* +* \brief Provides an API for the power management. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2011-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" +#include "CyLib.h" +#include "CyFlash.h" + + +/******************************************************************************* +* Function Name: CySysPmSleep +****************************************************************************//** +* +* Puts the part into the Sleep state. This is a CPU-centric power mode. +* It means that the CPU has indicated that it is in the sleep mode and +* its main clock can be removed. It is identical to Active from a peripheral +* point of view. Any enabled interrupts can cause wakeup from the Sleep mode. +* +*******************************************************************************/ +void CySysPmSleep(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* CPU enters Sleep mode upon execution of WFI */ + CY_PM_CPU_SCR_REG &= (uint32) (~CY_PM_CPU_SCR_SLEEPDEEP); + + /* Sleep and wait for interrupt */ + CY_PM_WFI; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysPmDeepSleep +****************************************************************************//** +* +* Puts the part into the Deep Sleep state. If the firmware attempts to enter +* this mode before the system is ready (that is, when +* PWR_CONTROL.LPM_READY = 0), then the device will go into the Sleep mode +* instead and automatically enter the originally intended mode when the +* holdoff expires. +* +* The wakeup occurs when an interrupt is received from a DeepSleep or +* Hibernate peripheral. For more details, see a corresponding +* peripheral's datasheet. +* +*******************************************************************************/ +void CySysPmDeepSleep(void) +{ + uint8 interruptState; + #if(CY_IP_SRSSV2) + volatile uint32 clkSelectReg; + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_ECO_SRSSLT) + volatile uint32 pllResoreFlag = 0u; + #endif /* (CY_IP_ECO_SRSSLT) */ + + interruptState = CyEnterCriticalSection(); + + #if(CY_IP_ECO_SRSSLT) + if(0u != (CY_SYS_ECO_CLK_SELECT_REG & CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK)) + { + pllResoreFlag = 1u; + + /* Set default state = IMO for HFCLK_SEL bit mask */ + CY_SYS_CLK_SELECT_REG &= (uint32)(~CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + } + #endif /* (CY_IP_ECO_SRSSLT) */ + + #if(CY_IP_SRSSV2) + /* Device enters DeepSleep mode when CPU asserts SLEEPDEEP signal */ + CY_PM_PWR_CONTROL_REG &= (uint32) (~CY_PM_PWR_CONTROL_HIBERNATE); + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_CPUSS && CY_IP_SRSSV2) + CY_PM_CPUSS_CONFIG_REG |= CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS; + #endif /* (CY_IP_CPUSS && CY_IP_SRSSV2) */ + + /* Adjust delay to wait for references to settle on wakeup from Deep Sleep */ + CY_PM_PWR_KEY_DELAY_REG = CY_SFLASH_DPSLP_KEY_DELAY_REG; + + /* CPU enters DeepSleep/Hibernate mode upon execution of WFI */ + CY_PM_CPU_SCR_REG |= CY_PM_CPU_SCR_SLEEPDEEP; + + #if(CY_IP_SRSSV2) + /* Preserve system clock configuration and + * reduce sysclk to <=12 MHz (Cypress ID #158710, #179888). + */ + clkSelectReg = CY_SYS_CLK_SELECT_REG; + CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV4); + #endif /* (CY_IP_SRSSV2) */ + + /* Sleep and wait for interrupt */ + CY_PM_WFI; + + #if(CY_IP_SRSSV2) + /* Restore system clock configuration */ + CY_SYS_CLK_SELECT_REG = clkSelectReg; + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_CPUSS && CY_IP_SRSSV2) + CY_PM_CPUSS_CONFIG_REG &= (uint32) (~CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS); + #endif /* (CY_IP_CPUSS && CY_IP_SRSSV2) */ + + #if(CY_IP_ECO_SRSSLT) + if(0u != pllResoreFlag) + { + CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_PLL0); + } + #endif /* (CY_IP_ECO_SRSSLT) */ + + CyExitCriticalSection(interruptState); +} + + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Function Name: CySysPmHibernate + ****************************************************************************//** + * + * Puts the part into the Hibernate state. Only SRAM and UDBs are retained; + * most internal supplies are off. Wakeup is possible from a pin or a hibernate + * comparator only. + * + * It is expected that the firmware has already frozen the IO-Cells using + * CySysPmFreezeIo() function before the call to this function. If this is + * omitted, the IO-cells will be frozen in the same way as they are + * in the Active to Deep Sleep transition, but will lose their state on wake up + * (because of the reset occurring at that time). + * + * Because all the CPU state is lost, the CPU will start up at the reset vector. + * To save the firmware state through the Hibernate low power mode, a + * corresponding variable should be defined with CY_NOINIT attribute. It + * prevents data from being initialized to zero on startup. The interrupt + * cause of the hibernate peripheral is retained, such that it can be either + * read by the firmware or cause an interrupt after the firmware has booted and + * enabled the corresponding interrupt. To distinguish the wakeup from + * the Hibernate mode and the general Reset event, the + * \ref CySysPmGetResetReason() function could be used. + * + *******************************************************************************/ + void CySysPmHibernate(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_HOBTO_DEVICE) + /* Disable input buffers for all ports */ + CySysPmHibPinsDisableInputBuf(); + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Device enters Hibernate mode when CPU asserts SLEEPDEEP signal */ + CY_PM_PWR_CONTROL_REG |= CY_PM_PWR_CONTROL_HIBERNATE; + + /* Adjust delay to wait for references to settle on wakeup from hibernate */ + CY_PM_PWR_KEY_DELAY_REG = CY_SFLASH_HIB_KEY_DELAY_REG; + + /* CPU enters DeepSleep/Hibernate mode upon execution of WFI */ + CY_PM_CPU_SCR_REG |= CY_PM_CPU_SCR_SLEEPDEEP; + + /* Save token that will retain through a STOP/WAKEUP sequence + * thus could be used by CySysPmGetResetReason() to differentiate + * WAKEUP from a general RESET event. + */ + CY_PM_PWR_STOP_REG = (CY_PM_PWR_STOP_REG & (uint32)(~CY_PM_PWR_STOP_TOKEN_MASK)) | CY_PM_PWR_STOP_TOKEN_HIB; + + /* Sleep and wait for interrupt. Wakeup from Hibernate is performed + * through RESET state, causing a normal Boot procedure to occur. + * The WFI instruction doesn't put the core to sleep if its wake condition + * is true when the instruction is executed. + */ + CY_PM_WFI; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmStop + ****************************************************************************//** + * + * Puts the part into the Stop state. All internal supplies are off; + * no state is retained. + * + * Wakeup from Stop is performed by toggling the wakeup pin, causing + * a normal boot procedure to occur. To configure the wakeup pin, + * the Digital Input Pin component should be placed on the schematic, + * assigned to the wakeup pin, and resistively pulled up or down to the inverse + * state of the wakeup polarity. To distinguish the wakeup from the Stop mode + * and the general Reset event, \ref CySysPmGetResetReason() function could be + * used. The wakeup pin is active low by default. The wakeup pin polarity + * could be changed with the \ref CySysPmSetWakeupPolarity() function. + * + * This function freezes IO cells implicitly. It is not possible to enter + * the STOP mode before freezing the IO cells. The IO cells remain frozen after + * awake from the Stop mode until the firmware unfreezes them after booting + * explicitly with \ref CySysPmUnfreezeIo() function call. + * + *******************************************************************************/ + void CySysPmStop(void) + { + (void) CyEnterCriticalSection(); + + /* Update token to indicate Stop mode transition. Preserve only polarity. */ + CY_PM_PWR_STOP_REG = (CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_POLARITY) | CY_PM_PWR_STOP_TOKEN_STOP; + + /* Freeze IO-Cells to save IO-Cell state */ + CySysPmFreezeIo(); + + /* Initiates transition to Stop state */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_REG | CY_PM_PWR_STOP_STOP; + + /* Depending on the clock frequency and internal timing delays, + * the final AHB transaction may or may not complete. To guard against + * accidentally executing an unintended instruction, it is recommended + * to add 2 NOP cycles after the final write to the STOP register. + */ + CY_NOP; + CY_NOP; + + /* Should never get to this WFI instruction */ + CY_PM_WFI; + + /* Wakeup from Stop is performed by toggling of Wakeup pin, + * causing a normal Boot procedure to occur. No need to exit + * from the critical section. + */ + } + + + /******************************************************************************* + * Function Name: CySysPmSetWakeupPolarity + ****************************************************************************//** + * + * Wake up from the stop mode is performed by toggling the wakeup pin, + * causing a normal boot procedure to occur. This function assigns + * the wakeup pin active level. Setting the wakeup pin to this level will cause + * the wakeup from stop mode. The wakeup pin is active low by default. + * + * \param polarity + * - \ref CY_PM_STOP_WAKEUP_ACTIVE_LOW Logical zero will wakeup the chip + * - \ref CY_PM_STOP_WAKEUP_ACTIVE_HIGH Logical one will wakeup the chip + * + *******************************************************************************/ + void CySysPmSetWakeupPolarity(uint32 polarity) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_PM_PWR_STOP_REG = (CY_PM_STOP_WAKEUP_ACTIVE_LOW != polarity) ? + (CY_PM_PWR_STOP_REG | CY_PM_PWR_STOP_POLARITY) : + (CY_PM_PWR_STOP_REG & (uint32) (~CY_PM_PWR_STOP_POLARITY)); + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmGetResetReason + ****************************************************************************//** + * + * Retrieves the last reset reason - transition from OFF/XRES/STOP/HIBERNATE to + * the RESET state. Note that waking up from STOP using XRES will be perceived + * as a general RESET. + * + * \return CY_PM_RESET_REASON_UNKN Unknown reset reason. + * \return CY_PM_RESET_REASON_XRES Transition from OFF/XRES to RESET + * \return CY_PM_RESET_REASON_WAKEUP_HIB Transition/wakeup from HIBERNATE to RESET + * \return CY_PM_RESET_REASON_WAKEUP_STOP Transition/wakeup from STOP to RESET + * + *******************************************************************************/ + uint32 CySysPmGetResetReason(void) + { + uint32 reason = CY_PM_RESET_REASON_UNKN; + + switch(CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_TOKEN_MASK) + { + /* Power up, XRES */ + case CY_PM_PWR_STOP_TOKEN_XRES: + reason = CY_PM_RESET_REASON_XRES; + break; + + /* Wakeup from Hibernate */ + case CY_PM_PWR_STOP_TOKEN_HIB: + reason = CY_PM_RESET_REASON_WAKEUP_HIB; + break; + + /* Wakeup from Stop (through WAKEUP pin assert) */ + case CY_PM_PWR_STOP_TOKEN_STOP: + reason = CY_PM_RESET_REASON_WAKEUP_STOP; + break; + + /* Unknown reason */ + default: + break; + } + + return (reason); + } + + + /******************************************************************************* + * Function Name: CySysPmFreezeIo + ****************************************************************************//** + * + * Freezes IO-Cells directly to save the IO-Cell state on wake up from the + * Hibernate or Stop state. It is not required to call this function before + * entering the Stop mode, since \ref CySysPmStop() function freezes IO-Cells + * implicitly. + * + * This API is not available for PSoC 4000 family of devices. + * + *******************************************************************************/ + void CySysPmFreezeIo(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Check FREEZE state to avoid recurrent IO-Cells freeze attempt, + * since the second call to this function will cause accidental switch + * to the STOP mode (the system will enter STOP mode immediately after + * writing to STOP bit since both UNLOCK and FREEZE have been set correctly + * in a previous call to this function). + */ + if (0u == (CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_FREEZE)) + { + /* Preserve last reset reason and disable overrides the next freeze command by peripherals */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_STOP | CY_PM_PWR_STOP_FREEZE | CY_PM_PWR_STOP_UNLOCK | + (CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY)); + + /* If reading after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) CY_PM_PWR_STOP_REG; + (void) CY_PM_PWR_STOP_REG; + + /* Second write causes the freeze of IO-Cells to save IO-Cell state */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_REG; + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmUnfreezeIo + ****************************************************************************//** + * + * The IO-Cells remain frozen after awake from Hibernate or Stop mode until + * the firmware unfreezes them after booting. The call of this function + * unfreezes IO-Cells explicitly. + * + * If the firmware intent is to retain the data value on the port, then the + * value must be read and re-written to the data register before calling this + * API. Furthermore, the drive mode must be re-programmed. If this is not done, + * the pin state will change to default state the moment the freeze is removed. + * + * This API is not available for PSoC 4000 family of devices. + * + *******************************************************************************/ + void CySysPmUnfreezeIo(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Preserve last reset reason and wakeup polarity. Then, unfreeze I/O: + * write PWR_STOP.FREEZE=0, .UNLOCK=0x3A, .STOP=0, .TOKEN + */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_UNLOCK | + (CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY)); + + /* If reading after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) CY_PM_PWR_STOP_REG; + (void) CY_PM_PWR_STOP_REG; + + /* Lock STOP mode: write PWR_STOP.FREEZE=0, UNLOCK=0x00, STOP=0, .TOKEN */ + CY_PM_PWR_STOP_REG &= (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY); + + CyExitCriticalSection(interruptState); + } + +#else + + /******************************************************************************* + * Function Name: CySysPmSetWakeupHoldoff + ****************************************************************************//** + * + * Sets the Deep Sleep wakeup time by scaling the hold-off to the HFCLK + * frequency. + * + * This function must be called before increasing HFCLK clock frequency. It can + * optionally be called after lowering HFCLK clock frequency in order to improve + * Deep Sleep wakeup time. + * + * It is functionally acceptable to leave the default hold-off setting, but + * Deep Sleep wakeup time may exceed the specification. + * + * This function is applicable only for the 4000 device family. + * + * \param hfclkFrequencyMhz The HFCLK frequency in MHz. + * + *******************************************************************************/ + void CySysPmSetWakeupHoldoff(uint32 hfclkFrequencyMhz) + { + CY_PM_PWR_KEY_DELAY_REG = ((((uint32)(CY_PM_PWR_KEY_DELAY_REG_DEFAULT << 16u) / + CY_PM_PWR_KEY_DELAY_FREQ_DEFAULT) * hfclkFrequencyMhz) >> 16u) + 1u; + } + +#endif /* (CY_IP_SRSSV2) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyPm.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyPm.h new file mode 100644 index 0000000..7b0641a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyPm.h @@ -0,0 +1,302 @@ +/***************************************************************************//** +* \file cyPm.h +* \version 5.70 +* +* \brief Provides the function definitions for the power management API. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2011-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" +#include "cypins.h" + + +/** +* \addtogroup group_power_management Power Management API +* @{ + +\brief PSoC 4 devices support the following power modes (in order of high to low power consumption): Active, Sleep, +Deep Sleep, Hibernate, and Stop. Active, Sleep and Deep-Sleep are standard ARM defined power modes, supported by the +ARM CPUs. Hibernate/Stop are even lower power modes that are entered from firmware just like Deep-Sleep, but on wakeup +the CPU (and all peripherals) goes through a full reset. + +There is a full range of power modes supported by PSoC devices to control power consumption and the amount of available +resources. See the following table for the supported power modes. + +Mode | PSoC 4000 | Rest Devices | +----------- | ---------------------- | ---------------------- | +Active | Y | Y | +Sleep | Y | Y | +Deep Sleep | Y | Y | +Hibernate | Y | Y | +Stop | | Y | + +For the ARM-based devices (PSoC 4), an interrupt is required for the CPU to wake up. The Power Management implementation +assumes that wakeup time is configured with a separate component (component-based wakeup time configuration) for an +interrupt to be issued on terminal count. + +All pending interrupts should be cleared before the device is put into low power mode, even if they are masked. + +The Power Management API is provided in the CyPm.c and CyPm.h files. + + +\section group_power_management_implementation Implementation +For PSoC 4100, PSoC 4000U and PSoC 4200 devices, the software should set EXT_VCCD bit in the PWR_CONTROL register when +Vccd is shorted to Vddd on the board. This impacts the chip internal state transitions where it is necessary to know +whether Vccd is connected or floating to achieve minimum current in low power modes. Note Setting this bit turns off +the active regulator and will lead to a system reset unless both Vddd and Vccd pins are supplied externally. Refer to +the device TRM for more information. + +It is safe to call PM APIs from the ISR. The wakeup conditions for Sleep and DeepSleep low power modes are illustrated +in the following table. + +Interrupts State | Condition | Wakeup | ISR Execution | +------------------|---------------------------------|-----------|------------------ | +Unmasked | IRQ priority > current level | Yes | Yes | +Unmasked | IRQ priority ≤ current level | No | No | +Masked | IRQ priority > current level | Yes | No | +Masked | IRQ priority ≤ current level | No | No | + + +\section group_power_management_clocks Clock Configuration +For PSoC 4100 BLE and PSoC 4200 BLE devices, the HFCLK source should be set to IMO before switching the device into low +power mode. The IMO should be enabled (by calling CySysClkImoStart(), if it is not) and HFCLK source should be changed +to IMO by calling CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO). + +If the System clock frequency is increased by switching to the IMO, the CySysFlashSetWaitCycles() function with an +appropriate parameter should be called beforehand. Also, it can optionally be called after lowering the System clock +frequency in order to improve CPU performance. See CySysFlashSetWaitCycles() description for the details. + + + + + +*/ +void CySysPmSleep(void); +void CySysPmDeepSleep(void); + +#if(CY_IP_SRSSV2) + void CySysPmHibernate(void); + void CySysPmFreezeIo(void); + void CySysPmUnfreezeIo(void); + uint32 CySysPmGetResetReason(void); + void CySysPmStop(void); + void CySysPmSetWakeupPolarity(uint32 polarity); +#else + void CySysPmSetWakeupHoldoff(uint32 hfclkFrequencyMhz); +#endif /* (CY_IP_SRSSV2) */ + +/** @} group_power_management */ + + +/******************************************************************************* +* The ARM compilers have the __wfi() intrinsic that inserts a WFI instruction +* into the instruction stream generated by the compiler. The GCC compiler has to +* execute assembly language instruction. +*******************************************************************************/ +#if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() +#else /* ASM for GCC & IAR */ + #define CY_PM_WFI __asm volatile ("WFI \n") +#endif /* __ARMCC_VERSION */ + +#if(CY_IP_SRSSV2) + + /* CySysPmSetWakeupPolarity() */ + #define CY_PM_STOP_WAKEUP_ACTIVE_LOW ((uint32)(0x0u)) /**< Logical zero will wakeup the chip */ + #define CY_PM_STOP_WAKEUP_ACTIVE_HIGH ((uint32)(0x1u)) /**< Logical one will wakeup the chip */ + #define CY_PM_STOP_WAKEUP_POLARITY (CY_PM_STOP_WAKEUP_ACTIVE_LOW) + + /* CySysPmGetResetReason() */ + #define CY_PM_RESET_REASON_UNKN (0u) /**< Unknown reset reason. */ + #define CY_PM_RESET_REASON_XRES (1u) /**< Transition from OFF/XRES to RESET */ + #define CY_PM_RESET_REASON_WAKEUP_HIB (2u) /**< Transition/wakeup from HIBERNATE to RESET */ + #define CY_PM_RESET_REASON_WAKEUP_STOP (3u) /**< Transition/wakeup from STOP to RESET */ + +#endif /* (CY_IP_SRSSV2) */ + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Control */ +#define CY_PM_PWR_CONTROL_REG (*(reg32 *) CYREG_PWR_CONTROL) +#define CY_PM_PWR_CONTROL_PTR ( (reg32 *) CYREG_PWR_CONTROL) + +/* CPU System Control Register */ +#if (CY_IP_CPUSS_CM0) + #define CY_PM_CPU_SCR_REG (*(reg32 *) CYREG_CM0_SCR) + #define CY_PM_CPU_SCR_PTR ( (reg32 *) CYREG_CM0_SCR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_PM_CPU_SCR_REG (*(reg32 *) CYREG_CM0P_SCR) + #define CY_PM_CPU_SCR_PTR ( (reg32 *) CYREG_CM0P_SCR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/* Power System Key & Delay Register */ +#define CY_PM_PWR_KEY_DELAY_REG (*(reg32 *) CYREG_PWR_KEY_DELAY) +#define CY_PM_PWR_KEY_DELAY_PTR ( (reg32 *) CYREG_PWR_KEY_DELAY) + + +#if(CY_IP_SRSSV2) + /* Hibernate wakeup value for PWR_KEY_DELAY */ + #define CY_SFLASH_HIB_KEY_DELAY_REG (*(reg16 *) CYREG_SFLASH_HIB_KEY_DELAY) + #define CY_SFLASH_HIB_KEY_DELAY_PTR ( (reg16 *) CYREG_SFLASH_HIB_KEY_DELAY) +#endif /* (CY_IP_SRSSV2) */ + +/* Deep Sleep wakeup value for PWR_KEY_DELAY */ +#define CY_SFLASH_DPSLP_KEY_DELAY_REG (*(reg16 *) CYREG_SFLASH_DPSLP_KEY_DELAY) +#define CY_SFLASH_DPSLP_KEY_DELAY_PTR ( (reg16 *) CYREG_SFLASH_DPSLP_KEY_DELAY) + +/* Power Stop Mode Register */ +#if(CY_IP_SRSSV2) + #define CY_PM_PWR_STOP_REG (*(reg32 *) CYREG_PWR_STOP) + #define CY_PM_PWR_STOP_PTR ( (reg32 *) CYREG_PWR_STOP) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + /* CPU Subsystem Configuration */ + #define CY_PM_CPUSS_CONFIG_REG (*(reg32 *) CYREG_CPUSS_CONFIG) + #define CY_PM_CPUSS_CONFIG_PTR ( (reg32 *) CYREG_CPUSS_CONFIG) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* CM0 System Control Register Constants */ +#define CY_PM_CPU_SCR_SLEEPDEEP ((uint32)(0x04u)) + +#if(CY_IP_SRSSV2) + /* Power Mode Control Constants */ + #define CY_PM_PWR_CONTROL_HIBERNATE (0x80000000u) + + /* Power Mode Stop Constants */ + #define CY_PM_PWR_STOP_POLARITY_SHIFT (16u) + #define CY_PM_PWR_STOP_POLARITY ((uint32)((uint32)1u << CY_PM_PWR_STOP_POLARITY_SHIFT)) + #define CY_PM_PWR_STOP_FREEZE_SHIFT (17u) + #define CY_PM_PWR_STOP_FREEZE ((uint32)((uint32)1u << CY_PM_PWR_STOP_FREEZE_SHIFT)) + #define CY_PM_PWR_STOP_UNLOCK_SHIFT (8u) + #define CY_PM_PWR_STOP_UNLOCK_MASK ((uint32)((uint32)0xFFu << CY_PM_PWR_STOP_UNLOCK_SHIFT)) + #define CY_PM_PWR_STOP_UNLOCK ((uint32)((uint32)0x3Au << CY_PM_PWR_STOP_UNLOCK_SHIFT)) + #define CY_PM_PWR_STOP_STOP_SHIFT (31u) + #define CY_PM_PWR_STOP_STOP ((uint32)((uint32)1u << CY_PM_PWR_STOP_STOP_SHIFT)) + #define CY_PM_PWR_STOP_TOKEN_MASK ((uint32)(0xFFu)) + #define CY_PM_PWR_STOP_TOKEN_XRES ((uint32)(0x00u)) + #define CY_PM_PWR_STOP_TOKEN_HIB ((uint32)(0xF1u)) + #define CY_PM_PWR_STOP_TOKEN_STOP ((uint32)(0xF2u)) +#else + #define CY_PM_PWR_KEY_DELAY_REG_DEFAULT ((uint32) 248u) + #define CY_PM_PWR_KEY_DELAY_FREQ_DEFAULT (48u) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + /* 0 - normal operation, 1 - Flash Accelerator in bypass mode */ + #define CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS ((uint32) 0x02u) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + + +#if (CY_IP_SRSSV2) + #if (CY_IP_HOBTO_DEVICE) + /******************************************************************************* + * Function Name: CySysPmHibPinsDisableInputBuf + ****************************************************************************//** + * + * Disable the input buffer for all the port. This is required before Hibernate + * mode entry as the operation of the input buffer is not guaranteed if VCCD + * drops down to 1.0 V. + * + *******************************************************************************/ + static CY_INLINE void CySysPmHibPinsDisableInputBuf(void) + { + #ifdef CYREG_GPIO_PRT0_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT0_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT0_PC */ + + #ifdef CYREG_GPIO_PRT1_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT1_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT1_PC */ + + #ifdef CYREG_GPIO_PRT2_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT2_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT2_PC */ + + #ifdef CYREG_GPIO_PRT3_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT3_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT3_PC */ + + #ifdef CYREG_GPIO_PRT4_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT4_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT4_PC */ + + #ifdef CYREG_GPIO_PRT5_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT5_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT5_PC */ + + #ifdef CYREG_GPIO_PRT6_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT6_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT6_PC */ + + #ifdef CYREG_GPIO_PRT7_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT7_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT7_PC */ + + #ifdef CYREG_GPIO_PRT8_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT8_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT8_PC */ + + #ifdef CYREG_GPIO_PRT9_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT9_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT9_PC */ + + #ifdef CYREG_GPIO_PRT10_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT10_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT10_PC */ + + #ifdef CYREG_GPIO_PRT11_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT11_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT11_PC */ + + #ifdef CYREG_GPIO_PRT12_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT12_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT12_PC */ + + #ifdef CYREG_GPIO_PRT13_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT13_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT13_PC */ + + #ifdef CYREG_GPIO_PRT14_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT14_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT14_PC */ + + #ifdef CYREG_GPIO_PRT15_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT15_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT15_PC */ + } + #endif /* (CY_IP_HOBTO_DEVICE) */ +#endif /* (CY_IP_SRSSV2) */ + + +#if (CY_IP_CPUSS_CM0) + #define CY_PM_CM0_SCR_REG (CY_PM_CPU_SCR_REG) + #define CY_PM_CM0_SCR_PTR (CY_PM_CPU_SCR_PTR) + #define CY_PM_CM0_SCR_SLEEPDEEP (CY_PM_CPU_SCR_SLEEPDEEP) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#endif /* CY_BOOT_CYPM_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cy_em_eeprom.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/cy_em_eeprom.c new file mode 100644 index 0000000..ce94d9c --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cy_em_eeprom.c @@ -0,0 +1,1416 @@ +/***************************************************************************//** +* \file cy_em_eeprom.c +* \version 2.0 +* +* \brief +* This file provides source code of the API for the Emulated EEPROM library. +* The Emulated EEPROM API allows creating of an emulated EEPROM in flash that +* has the ability to do wear leveling and restore corrupted data from a +* redundant copy. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "cytypes.h" +#include + +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include "em_eeprom/cy_em_eeprom.h" +#else + #include "cy_em_eeprom.h" +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Private Function Prototypes +***************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context); +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context); +static uint8 CalcChecksum(uint8 rowData[], uint32 len); +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config); +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context); +static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint32 addr, uint32 len); +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context); + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Init +****************************************************************************//** +* +* Initializes the Emulated EEPROM library by filling the context structure. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \param context +* The pointer to the EEPROM context structure to be filled by the function. +* \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* The context structure should not be modified by the user after it is filled +* with this function. Modification of context structure may cause the +* unexpected behavior of the Cy_Em_EEPROM API functions which rely on it. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* If the "Redundant Copy" option is used, the function performs a number of +* write operations to the EEPROM to initialize flash rows checksums. Therefore, +* Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(), +* will return a non-zero value that identifies the number of writes performed +* by Cy_Em_EEPROM_Init(). +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) && + (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSize != 0u)) + { + ret = CheckRanges(config); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Copy the user config structure fields into context */ + context->eepromSize = config->eepromSize; + context->wearLevelingFactor = config->wearLevelingFactor; + context->redundantCopy = config->redundantCopy; + context->blockingWrite = config->blockingWrite; + context->userFlashStartAddr = config->userFlashStartAddr; + /* Store frequently used data for internal use */ + context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize); + context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->wearLevelingFactor) + + config->userFlashStartAddr); + /* Find last written EEPROM row and store it for quick access */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + + if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundantCopy)) + { + /* Call the function only after device reprogramming in case + * if redundant copy is enabled. + */ + ret = FillChecksum(context); + + /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Read +****************************************************************************//** +* +* This function takes the logical EEPROM address, converts it to the actual +* physical address where the data is stored and returns the data to the user. +* +* \param addr +* The logical start address in EEPROM to start reading data from. +* +* \param eepromData +* The pointer to a user array to write data to. +* +* \param size +* The amount of data to read. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \note +* In case if redundant copy option is enabled the function may perform writes +* to EEPROM. This is done in case if the data in the EEPPROM is corrupted and +* the data in redundant copy is valid based on CRC-8 data integrity check. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 numBytesToRead; + uint32 curEepromBaseAddr; + uint32 curRowOffset; + uint32 startRowAddr; + uint32 actEepromRowNum; + uint32 curRdEepromRowNum = 0u; + uint32 dataStartEepromRowNum = 0u; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Validate input parameters */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 rdAddr = addr; + uint32 rdSize = size; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr); + uint32 updateAddrFlag = 0u; + + /* Calculate the number of the row read operations. Currently this only concerns + * the reads from the EEPROM data locations. + */ + uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) - + (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + + /* Get the address of the first row of the currently active EEPROM sector. If + * no wear leveling is used - the EEPROM has only one sector, so use the base + * addr stored in "context->userFlashStartAddr". + */ + curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) / + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) + + context->userFlashStartAddr; + + /* Find the number of the row that contains the start address of the data */ + for(i = 0u; i < context->numberOfRows; i++) + { + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i)) + { + dataStartEepromRowNum = i; + curRdEepromRowNum = dataStartEepromRowNum; + break; + } + } + + /* Find the row number of the last written row */ + actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + /* Check if wear leveling is used */ + if(context->wearLevelingFactor > 1u) + { + uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u); + + /* Check if the future validation of the read address is required. */ + updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u : + ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u); + } + + /* Copy data from the EEPROM data locations to the user buffer */ + for(i = 0u; i < numRowReads; i++) + { + startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Check if there are more reads pending and update the number of the + * remaining bytes to read respectively. + */ + if((i + 1u) < numRowReads) + { + numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + } + else + { + numBytesToRead = rdSize; + } + + /* Check if the read address needs to be updated to point to the correct + * EEPROM sector. + */ + if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum)) + { + startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if(startRowAddr < context->userFlashStartAddr) + { + startRowAddr = context->wlEndAddr - + ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + + if(0u != context->redundantCopy) + { + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + * the corresponding row in redundant copy, otherwise return failure. + */ + ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + /* Copy the data to the user buffer */ + (void)memcpy((void *)(eeData), + (void *)(startRowAddr + curRowOffset), + numBytesToRead); + + /* Indicate success to be able to execute next code block */ + ret = CY_EM_EEPROM_SUCCESS; + } + + /* Update variables anticipated in the read operation */ + rdAddr += numBytesToRead; + rdSize -= numBytesToRead; + eeData += numBytesToRead; + curRdEepromRowNum++; + } + + /* This code block will copy the latest data from the EEPROM headers into the + * user buffer. The data previously copied into the user buffer may be updated + * as the EEPROM headers contain more recent data. + * The code block is executed when two following conditions are true: + * 1) The reads from "historic" data locations were successful; + * 2) The user performed at least one write operation to Em_EEPROM (0u != + * seqNum). + */ + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum)) + { + numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum); + numRowReads--; + + for(i = (seqNum - numRowReads); i <= seqNum; i++) + { + startRowAddr = GetRowAddrBySeqNum(i, context); + + if (0u != startRowAddr) + { + /* The following variables are introduced to increase code readability. */ + uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET); + uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + + /* Check if the current row EEPROM header contains the data requested for read */ + if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + size)) + { + uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr); + uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u); + rdAddr = (startAddr > addr) ? (startAddr) : (addr); + + srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET; + + /* Calculate the number of bytes to be read from the current row's EEPROM header */ + numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rdAddr; + + /* Calculate the offset in the user buffer from which the data will be updated. */ + eeData = ((uint32)eepromData) + dstOffset; + + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in the + * corresponding row in redundant copy, otherwise return failure. Copy the data + * from the recent EEPROM headers to the user buffer. This will overwrite the + * data copied form EEPROM data locations as the data in EEPROM headers is newer. + */ + if(0u != context->redundantCopy) + { + ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numBytesToRead); + } + } + } + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Write +****************************************************************************//** +* +* This function takes the logical EEPROM address and converts it to the actual +* physical address and writes data there. If wear leveling is implemented, the +* writing process will use the wear leveling techniques. This is a blocking +* function and it does not return until the write operation is completed. The +* user firmware should not enter Hibernate mode until write is completed. The +* write operation is allowed in Sleep and Deep-Sleep modes. During the flash +* operation, the device should not be reset, including the XRES pin, a software +* reset, and watchdog reset sources. Also, low-voltage detect circuits should +* be configured to generate an interrupt instead of a reset. Otherwise, portions +* of flash may undergo unexpected changes. +* +* \param addr +* The logical start address in EEPROM to start writing data from. +* +* \param eepromData +* Data to write to EEPROM. +* +* \param size +* The amount of data to write to EEPROM. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform write +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM write is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 wrCnt; + uint32 actEmEepromRowNum; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 startAddr = 0u; + uint32 endAddr = 0u; + uint32 tmpRowAddr; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + void * tmpData; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Check if the EEPROM data does not exceed the EEPROM capacity */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u; + uint32 eeHeaderDataOffset = 0u; + + for(wrCnt = 0u; wrCnt < numWrites; wrCnt++) + { + uint32 skipOperation = 0u; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* Get the address of the row to be written. The "emEepromRowAddr" may be + * updated with the proper address (if wear leveling is used). The + * "emEepromRowRdAddr" will point to the row address from which the historic + * data will be read into the RAM buffer. + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + + /* Clear the RAM buffer so to not put junk into flash */ + (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Fill the EM_EEPROM header info for the row in the RAM buffer */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr; + tmpData = (void *) eeData; + + /* Check if this is the last row to write */ + if(wrCnt == (numWrites - 1u)) + { + /* Fill in the remaining size value to the EEPROM header. */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size; + } + else + { + /* This is not the last row to write in the current EEPROM write operation. + * Write the maximum possible data size to the EEPROM header. Update the + * size, eeData and addr respectively. + */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN; + size -= CY_EM_EEPROM_HEADER_DATA_LEN; + addr += CY_EM_EEPROM_HEADER_DATA_LEN; + eeData += CY_EM_EEPROM_HEADER_DATA_LEN; + } + + /* Write the data to the EEPROM header */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32], + tmpData, + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]); + + if(emEepromRowRdAddr != 0UL) + { + /* Copy the EEPROM historic data for this row from flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + /* Check if there is data for this location in other EEPROM headers: + * find out the row with the lowest possible sequence number which + * may contain the data for the current row. + */ + i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u; + + for(; i <= seqNum; i++) + { + if(i == seqNum) + { + /* The code reached the row that is about to be written. Analyze the recently + * created EEPROM header (stored in the RAM buffer currently): if it contains + * the data for EEPROM data locations in the row that is about to be written. + */ + tmpRowAddr = (uint32) writeRamBuffer; + } + else + { + /* Retrieve the address of the previously written row by its sequence number. + * The pointer will be used to get data from the respective EEPROM header. + */ + tmpRowAddr = GetRowAddrBySeqNum(i, context); + } + + actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr, + context->numberOfRows, + context->userFlashStartAddr); + if(0UL != tmpRowAddr) + { + /* Calculate the required addressed for the later EEPROM historic data update */ + skipOperation = GetAddresses( + &startAddr, + &endAddr, + &eeHeaderDataOffset, + actEmEepromRowNum, + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET), + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + } + else + { + /* Skip writes to the RAM buffer */ + skipOperation++; + } + + /* Write data to the RAM buffer */ + if(0u == skipOperation) + { + uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr; + + /* Update the address to point to the EEPROM header data and not to + * the start of the row. + */ + tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset; + (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr); + } + + /* Calculate the checksum if redundant copy is enabled */ + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + } + + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, writeRamBuffer, context); + tmpRowAddr = emEepromRowAddr; + + /* Check if redundant copy is used */ + if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret)) + { + /* Update the row address to point to the row in the redundant EEPROM's copy */ + tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Store last written row address only when EEPROM and redundant + * copy writes were successful. + */ + context->lastWrRowAddr = emEepromRowAddr; + } + else + { + break; + } + } + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Erase +****************************************************************************//** +* +* This function erases the entire contents of the EEPROM. Erased values are all +* zeros. This is a blocking function and it does not return until the write +* operation is completed. The user firmware should not enter Hibernate mode until +* erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage +* detect circuits should be configured to generate an interrupt instead of a +* reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* For all non PSoC 6 devices the erase operation is performed by clearing +* the EEPROM data using flash write. This affects the flash durability. +* So it is recommended to use this function in utmost case to prolongate +* flash life. +* +* \note +* This function uses a buffer of the flash row size to perform erase +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM erase is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 seqNum; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u}; +#if (CY_PSOC6) + uint32 emEepromStoredRowAddr = context->lastWrRowAddr; + uint32 storedSeqNum; +#endif /* (!CY_PSOC6) */ + + /* Get the sequence number of the last written row */ + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* If there were no writes to EEPROM - nothing to erase */ + if(0u != seqNum) + { + /* Calculate the number of row erase operations required */ + uint32 numWrites = context->numberOfRows * context->wearLevelingFactor; + + #if (CY_PSOC6) + GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context); + storedSeqNum = seqNum + 1u; + #endif /* (CY_PSOC6) */ + + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + for(i = 0u; i < numWrites; i++) + { + #if (CY_PSOC6) + /* For PSoC 6 the erase operation moves backwards. From last written row + * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr" + * is zero this means that the row identified by "seqNum" was previously + * erased. + */ + if(0u != emEepromRowAddr) + { + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + } + + seqNum--; + + if(0u == seqNum) + { + /* Exit the loop as there is no more row is EEPROM to be erased */ + break; + } + emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context); + #else + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + /* Get the address of the row to be erased. "emEepromRowAddr" may be updated + * with the proper address (if wear leveling is used). + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + seqNum++; + writeRamBuffer[0u] = seqNum; + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + #endif /* (CY_PSOC6) */ + } + + #if (CY_PSOC6) + if(CY_EM_EEPROM_SUCCESS == ret) + { + writeRamBuffer[0u] = storedSeqNum; + + /* Write the previously stored sequence number to the flash row which would be + * written next if the erase wouldn't happen. In this case the write to + * redundant copy can be skipped as it does not add any value. + */ + ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = emEepromStoredRowAddr; + } + } + #endif /* (CY_PSOC6) */ + + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_NumWrites +****************************************************************************//** +* +* Returns the number of the EEPROM writes completed so far. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* The number of writes performed to the EEPROM. +* +*******************************************************************************/ +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context) +{ + return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)); +} + +/** \} */ + +/** \cond INTERNAL */ + + +/******************************************************************************* +* Function Name: FindLastWrittenRow +****************************************************************************//** +* +* Performs a search of the last written row address of the EEPROM associated +* with the context structure. If there were no writes to the EEPROM the +* function returns the start address of the EEPROM. The row address is returned +* in the input parameter. +* +* \param lastWrRowPtr +* The pointer to a memory where the last written row will be returned. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context) +{ + uint32 seqNum = 0u; + uint32 prevSeqNum = 0u; + uint32 numRows; + uint32 emEepromAddr = context->userFlashStartAddr; + + *lastWrRowPtr = emEepromAddr; + + for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++) + { + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr); + if((0u != seqNum) && (seqNum > prevSeqNum)) + { + /* Some record in EEPROM was found. Store found sequence + * number and row address. + */ + prevSeqNum = seqNum; + *lastWrRowPtr = emEepromAddr; + } + + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } +} + + +/******************************************************************************* +* Function Name: GetRowAddrBySeqNum +****************************************************************************//** +* +* Returns the address of the row in EEPROM using its sequence number. +* +* \param seqNum +* The sequence number of the row. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* The address of the row or zero if the row with the sequence number was not +* found. +* +*******************************************************************************/ +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context) +{ + uint32 emEepromAddr = context->userFlashStartAddr; + + while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum) + { + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if (CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + { + emEepromAddr = 0u; + /* Exit the loop as we reached the end of EEPROM */ + break; + } + } + + return (emEepromAddr); +} + + +/******************************************************************************* +* Function Name: GetNextRowToWrite +****************************************************************************//** +* +* Performs a range check of the row that should be written and updates the +* address to the row respectively. The similar actions are done for the read +* address. +* +* \param seqNum +* The sequence number of the last written row. +* +* \param rowToWrPtr +* The address of the last written row (input). The address of the row to be +* written (output). +* +* \param rowToRdPtr +* The address of the row from which the data should be read into the RAM buffer +* in a later write operation. Out parameter. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context) +{ + /* Switch to the next row to be written if the current sequence number is + * not zero. + */ + if(0u != seqNum) + { + *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + + /* If the resulting row address is out of EEPROM, then switch to the base + * EEPROM address (Row#0). + */ + if(CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + { + *rowToWrPtr = context->userFlashStartAddr; + } + + *rowToRdPtr = 0u; + + /* Check if the sequence number is larger than the number of rows in the EEPROM. + * If not, do not update the row read address because there is no historic + * data to be read. + */ + if(context->numberOfRows <= seqNum) + { + /* Check if wear leveling is used in EEPROM */ + if(context->wearLevelingFactor > 1u) + { + /* The read row address should be taken from an EEPROM copy that became + * inactive recently. This condition check handles that. + */ + if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) < + context->userFlashStartAddr) + { + *rowToRdPtr = context->userFlashStartAddr + + (context->numberOfRows * (context->wearLevelingFactor - 1u) * + CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr); + } + else + { + *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + else + { + /* If no wear leveling, always read from the same flash row that + * should be written. + */ + *rowToRdPtr = *rowToWrPtr; + } + } +} + + +/******************************************************************************* +* Function Name: CalcChecksum +****************************************************************************//** +* +* Implements CRC-8 that is used in checksum calculation for the redundant copy +* algorithm. +* +* \param rowData +* The row data to be used to calculate the checksum. +* +* \param len +* The length of rowData. +* +* \return +* The calculated value of CRC-8. +* +*******************************************************************************/ +static uint8 CalcChecksum(uint8 rowData[], uint32 len) +{ + uint8 crc = CY_EM_EEPROM_CRC8_SEED; + uint8 i; + uint16 cnt = 0u; + + while(cnt != len) + { + crc ^= rowData[cnt]; + for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + { + crc = CY_EM_EEPROM_CALCULATE_CRC8(crc); + } + cnt++; + } + + return (crc); +} + + +/******************************************************************************* +* Function Name: CheckRanges +****************************************************************************//** +* +* Checks if the EEPROM of the requested size can be placed in flash. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA; + uint32 startAddr = config->userFlashStartAddr; + uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize, + config->wearLevelingFactor, config->redundantCopy); + + /* Range check if there is enough flash for EEPROM */ + if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + return (ret); +} + + +/******************************************************************************* +* Function Name: WriteRow +****************************************************************************//** +* +* Writes one flash row starting from the specified row address. +* +* \param rowAdd +* The address of the flash row. +* +* \param rowData +* The pointer to the data to be written to the row. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, + uint32 *rowData, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (!CY_PSOC6) + cystatus rc; + uint32 rowId; + #if ((CY_PSOC3) || (CY_PSOC5)) + uint32 arrayId; + #endif /* (CY_PSOC3) */ + + #if (CY_PSOC3) + rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK; + context = context; /* To avoid compiler warning generation */ + #else + (void)context; /* To avoid compiler warning generation */ + #endif /* ((CY_PSOC3) */ + + /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */ + rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY; + + /* Write the flash row */ + #if (CY_PSOC4) + rc = CySysFlashWriteRow(rowId, (uint8 *)rowData); + #else + + #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT + (void)CySetTemp(); + #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */ + + arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY; + rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData); + + #if (CY_PSOC5) + CyFlushCache(); + #endif /* (CY_PSOC5) */ + #endif /* (CY_PSOC4) */ + + if(CYRET_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } +#else /* PSoC 6 */ + if(0u != context->blockingWrite) + { + /* Do blocking write */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate write */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } +#endif /* (CY_PSOC6) */ + + return (ret); +} + + +/******************************************************************************* +* Function Name: EraseRow +****************************************************************************//** +* +* Erases one flash row starting from the specified row address. If the redundant +* copy option is enabled the corresponding row in the redundant copy will also +* be erased. +* +* \param rowAdd +* The address of the flash row. +* +* \param ramBuffAddr +* The address of the RAM buffer that contains zeroed data (used only for +* non-PSoC 6 devices). +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, + uint32 ramBuffAddr, + cy_stc_eeprom_context_t * context) +{ + uint32 emEepromRowAddr = rowAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (CY_PSOC6) + uint32 i = 1u; + + (void)ramBuffAddr; /* To avoid compiler warning */ + + if(0u != context->redundantCopy) + { + i++; + } + + do + { + if(0u != context->blockingWrite) + { + /* Erase the flash row */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate erase */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + } + else + { + break; + } + i--; + } while (0u != i); +#else + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy)) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = rowAddr; + } +#endif /* (CY_PSOC6) */ + + return(ret); +} + + +/******************************************************************************* +* Function Name: CheckCrcAndCopy +****************************************************************************//** +* +* Checks the checksum of the specific row in EEPROM. If the CRC matches - copies +* the data to the "datAddr" from EEPROM. f the CRC does not match checks the +* CRC of the corresponding row in the EEPROM's redundant copy. If the CRC +* matches - copies the data to the "datAddr" from EEPROM redundant copy. If the +* CRC of the redundant copy does not match - returns bad checksum. +* +* \param startAddr +* The address that points to the start of the specified row. +* +* \param datAddr +* The start address of where the row data will be copied if the CRC check +* will succeed. +* +* \param rowOffset +* The offset in the row from which the data should be copied. +* +* \param numBytes +* The number of bytes to be copied. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + + /* Calculate the row address in the EEPROM's redundant copy */ + uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Check the row data CRC in the EEPROM */ + if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes); + + ret = CY_EM_EEPROM_SUCCESS; + } + /* Check the row data CRC in the EEPROM's redundant copy */ + else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW) + * flash exception. The RWW occurs while trying to write and read the data from + * same flash macro. + */ + (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Restore bad row data from the RAM buffer */ + ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes); + } + } + else + { + ret = CY_EM_EEPROM_BAD_CHECKSUM; + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: GetAddresses +****************************************************************************//** +* +* Calculates the start and end address of the row's EEPROM data to be updated. +* The start and end are not absolute addresses but a relative addresses in a +* flash row. +* +* \param startAddr +* The pointer the address where the EEPROM data start address will be returned. +* +* \param endAddr +* The pointer the address where the EEPROM data end address will be returned. +* +* \param offset +* The pointer the address where the calculated offset of the EEPROM header data +* will be returned. +* +* \param rowNum +* The row number that is about to be written. +* +* \param addr +* The address of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \param len +* The length of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \return +* Zero indicates that the currently analyzed row has the data to be written to +* the active EEPROM row data locations. Non zero value indicates that there is +* no data to be written +* +*******************************************************************************/ +static uint32 GetAddresses(uint32 *startAddr, + uint32 *endAddr, + uint32 *offset, + uint32 rowNum, + uint32 addr, + uint32 len) +{ + uint32 skip = 0u; + + *offset =0u; + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *endAddr = *startAddr + len; + } + else + { + *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } + } + else + { + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN; + *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN)); + *offset = len - (*endAddr - *startAddr); + } + else + { + skip++; + } + } + + return (skip); +} + + +/******************************************************************************* +* Function Name: FillChecksum +****************************************************************************//** +* +* Performs calculation of the checksum on each row in the Em_EEPROM and fills +* the Em_EEPROM headers checksum field with the calculated checksums. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \theory +* In case if redundant copy option is used the Em_EEPROM would return bad +* checksum while trying to read the EEPROM rows which were not yet written by +* the user. E.g. any read after device reprogramming without previous Write() +* operation to the EEPROM would fail. This would happen because the Em_EEPROM +* headers checksum field values (which is zero at the moment) would not be +* equal to the actual data checksum. This function allows to avoid read failure +* after device reprogramming. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 rdAddr; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 wrAddr = context->lastWrRowAddr; + uint32 tmpRowAddr; + /* Get the sequence number (number of writes) */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr); + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++) + { + /* Copy the EEPROM row from Flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Increment the sequence number */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + + /* Calculate and fill the checksum to the Em_EEPROM header */ + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Write the data to the specified flash row */ + ret = WriteRow(wrAddr, writeRamBuffer, context); + + /* Update the row address to point to the relevant row in the redundant + * EEPROM's copy. + */ + tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + + /* Get the address of the next row to be written. + * "rdAddr" is not used in this function but provided to prevent NULL + * pointer exception in GetNextRowToWrite(). + */ + GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context); + } + + return(ret); +} + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cy_em_eeprom.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cy_em_eeprom.h new file mode 100644 index 0000000..4aef67b --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cy_em_eeprom.h @@ -0,0 +1,556 @@ +/******************************************************************************* +* \file cy_em_eeprom.h +* \version 2.0 +* +* \brief +* This file provides the function prototypes and constants for the Emulated +* EEPROM middleware library. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** + * \mainpage Cypress Em_EEPROM Middleware Library + * + * The Emulated EEPROM provides an API that allows creating an emulated + * EEPROM in flash that has the ability to do wear leveling and restore + * corrupted data from a redundant copy. The Emulated EEPROM library is designed + * to be used with the Em_EEPROM component. + * + * The Cy_Em_EEPROM API is described in the following sections: + * - \ref group_em_eeprom_macros + * - \ref group_em_eeprom_data_structures + * - \ref group_em_eeprom_enums + * - \ref group_em_eeprom_functions + * + * Features: + * * EEPROM-Like Non-Volatile Storage + * * Easy to use Read and Write API + * * Optional Wear Leveling + * * Optional Redundant Data storage + * + * \section group_em_eeprom_configuration Configuration Considerations + * + * The Em_EEPROM operates on the top of the flash driver. The flash driver has + * some prerequisites for proper operation. Refer to the "Flash System + * Routine (Flash)" section of the PDL API Reference Manual. + * + * Initializing Emulated EEPROM in User flash + * + * To initialize an Emulated EEPROM in the User flash, the EEPROM storage should + * be declared by the user. For the proper operation, the EEPROM storage should + * be aligned to the size of the flash row. An example of the EEPROM storage + * declaration is below (applicable for GCC and MDK compilers): + * + * CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * Note that the name "emEeprom" is shown for reference. Any other name can be + * used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is + * generated by the PSoC Creator Em_EEPROM component and so it is instance name + * dependent and its prefix should be changed when the name of the component + * changes. If the The Cy_Em_EEPROM middleware library is used without the + * Em_EEPROM component, the user has to provide a proper size for the EEPROM + * storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage + * can be calculated using the following equation: + * + * Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy) + * + * where, + * "EEPROM data size" - the size of data the user wants to store in the + * EEPROM. The data size must divide evenly to the half of the flash row size. + * "wear leveling" - the wear leveling factor (1-10). + * "redundant copy" - "zero" if a redundant copy is not used, and "one" + * otherwise. + * + * The start address of the storage should be filled to the Emulated EEPROM + * configuration structure and then passed to the Cy_Em_EEPROM_Init(). + * If the Em_EEPROM component is used, the config (Em_EEPROM_config) and + * context structures (Em_EEPROM_context) are defined by the component, so the + * user may just use that structures otherwise both of the structures need to + * be provided by the user. Note that if the "Config Data in Flash" + * option is selected in the component, then the configuration structure should + * be copied to RAM to allow EEPROM storage start address update. The following + * code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context" + * Em_EEPROM component structures for Cy_Em_EEPROM middleware library + * initialization: + * + * cy_en_em_eeprom_status_t retValue; + * cy_stc_eeprom_config_t config; + * + * memcpy((void *)&config, + (void *)&Em_EEPROM_config, + sizeof(cy_stc_eeprom_config_t)); + * config.userFlashStartAddr = (uint32)emEeprom; + * retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context); + * + * Initializing EEPROM in Emulated EEPROM flash area + * + * Initializing of the EEPROM storage in the Emulated EEPROM flash area is + * identical to initializing of the EEPROM storage in the User flash with one + * difference. The location of the Emulated EEPROM storage should be specified + * somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is + * utilized in the project, then the respective storage + * (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component + * if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to + * fill the start address of the storage to the config structure. If the + * Em_EEPROM component is not used, the user needs to declare the storage + * in the Emulated EEPROM flash area. An example of such declaration is + * following (applicable for GCC and MDK compilers): + * + * CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma location = ".cy_em_eeprom" + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * where, + * Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM + * component when the component is utilized in the project or it should be + * provided by the user. The equation for the calculation of the constant is + * shown above. + * + * Note that the size of the Emulated EEPROM flash area is limited. Refer to the + * specific device datasheet for the value of the available EEPROM Emulation + * area. + * + * \section group_em_eeprom_more_information More Information + * See the Em_EEPROM Component datasheet. + * + * + * \section group_em_eeprom_MISRA MISRA-C Compliance + * + * The Cy_Em_EEPROM library has the following specific deviations: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AThe cast should not be performed between a pointer to the object type + * and a different pointer to the object type.The cast from the object type and a different pointer to the object + * was used intentionally because of the performance reasons.
14.2RAll non-null statements shall either have at least one side-effect, + * however executed, or cause control flow to change.To maintain common codebase, some variables, unused for a specific + * device, are casted to void to prevent generation of an unused variable + * compiler warning.
16.7AThe object addressed by the pointer parameter is not modified and so + * the pointer could be of type 'pointer to const'.The warning is generated because of the pointer dereferencing to + * address which makes the MISRA checker think the data is not + * modified.
17.4RThe array indexing shall be the only allowed form of pointer + * arithmetic.The pointer arithmetic used in several places on the Cy_Em_EEPROM + * implementation is safe and preferred because it increases the code + * flexibility.
19.7AA function shall be used in preference to a function-like macro.Macro is used because of performance reasons.
+ * + * \section group_em_eeprom_changelog Changelog + * + * + * + * + * + * + * + *
VersionChangesReason for Change
1.0Initial Version
+ * + * \defgroup group_em_eeprom_macros Macros + * \brief + * This section describes the Emulated EEPROM Macros. + * + * \defgroup group_em_eeprom_functions Functions + * \brief + * This section describes the Emulated EEPROM Function Prototypes. + * + * \defgroup group_em_eeprom_data_structures Data Structures + * \brief + * Describes the data structures defined by the Emulated EEPROM. + * + * \defgroup group_em_eeprom_enums Enumerated types + * \brief + * Describes the enumeration types defined by the Emulated EEPROM. + * + */ + + +#if !defined(CY_EM_EEPROM_H) +#define CY_EM_EEPROM_H + +#include "cytypes.h" +#include +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include + #include "syslib/cy_syslib.h" + #include "flash/cy_flash.h" +#else + #include "CyFlash.h" + #include +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + +/* The C binding of definitions if building with the C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + + +/*************************************** +* Data Structure definitions +***************************************/ +/** +* \addtogroup group_em_eeprom_data_structures +* \{ +*/ + +/** EEPROM configuration structure */ +typedef struct +{ + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_config_t; + +/** \} group_em_eeprom_data_structures */ + +/** The EEPROM context data structure. It is used to store the specific +* EEPROM context data. +*/ +typedef struct +{ + /** The pointer to the end address of EEPROM including wear leveling overhead + * and excluding redundant copy overhead. + */ + uint32 wlEndAddr; + + /** The number of flash rows allocated for the EEPROM excluding the number of + * rows allocated for wear leveling and redundant copy overhead. + */ + uint32 numberOfRows; + + /** The address of the last written EEPROM row */ + uint32 lastWrRowAddr; + + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_context_t; + +#if (CY_PSOC6) + + #define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */ + /** + * \addtogroup group_em_eeprom_enums + * \{ + * Specifies return values meaning. + */ + /** A prefix for EEPROM function error return-values */ + #define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR) + +#else + + /** A prefix for EEPROM function status codes. For non-PSoC6 devices, + * prefix is zero. + */ + #define CY_EM_EEPROM_ID_ERROR (0uL) + +#endif /* (CY_PSOC6) */ + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/** EEPROM return enumeration type */ +typedef enum +{ + CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */ + CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */ + CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */ + CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */ + CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */ +} cy_en_em_eeprom_status_t; + +/** \} group_em_eeprom_enums */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context); +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context); +/** \} group_em_eeprom_functions */ + + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ +/** Library major version */ +#define CY_EM_EEPROM_VERSION_MAJOR (2) + +/** Library minor version */ +#define CY_EM_EEPROM_VERSION_MINOR (0) + +/** Defines the maximum data length that can be stored in one flash row */ +#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) + +/** \} group_em_eeprom_macros */ + + +/*************************************** +* Macro definitions +***************************************/ +/** \cond INTERNAL */ + +/* Defines the size of flash row */ +#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW) + +/* Device specific flash constants */ +#if (!CY_PSOC6) + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE) + #define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW) + #if (CY_PSOC3) + #define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL) + #define CY_EM_EEPROM_CODE_ADDR_END \ + (CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u)) + #define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu) + /* Checks if the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \ + ((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END)) + #else + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) + #endif /* (CY_PSOC3) */ +#else + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE) + #define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE) + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \ + (((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \ + ((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR)))) +#endif /* (!CY_PSOC6) */ + +#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE) + +/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */ +#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u) + +#define CY_EM_EEPROM_ADDR_IN_RANGE (1u) + +/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of +* EEPROM. The wear leveling overhead is included in the range but redundant copy +* is excluded. +*/ +#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \ + (((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE)) + +/* Check to see if the specified address is present in the EEPROM */ +#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \ + (((addr) > (startEepromAddr)) ? \ + (((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u)) + +/* Check if the EEPROM address locations from startAddr1 to endAddr1 +* are crossed with EEPROM address locations from startAddr2 to endAddr2. +*/ +#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \ + (((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \ + (((startAddr2) >= (endAddr1)) ? (0u) : (1u))) + +/* Return the pointer to the start of the redundant copy of the EEPROM */ +#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \ + ((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr)) + +/* Return the number of the row in EM_EEPROM which contains an address defined by +* rowAddr. + */ +#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \ + ((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows)) + + +/** Returns the size allocated for the EEPROM excluding wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) + +/* Check if the given address belongs to the EEPROM address of the row +* specified by rowNum. +*/ +#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \ + (((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \ + (((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \ + (0u) : (1u))) + +/* CRC-8 constants */ +#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u)) +#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u) +#define CY_EM_EEPROM_CRC8_SEED (0xFFu) +#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u)) + +#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \ + ((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \ + ((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u))) + +#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr)) + +/** \endcond */ + +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ + +/** Calculate the number of flash rows required to create an Em_EEPROM of +* dataSize. +*/ +#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \ + (((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \ + ((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U)) + +/** Returns the size of flash allocated for EEPROM including wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \ + (((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \ + CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \ + (wearLeveling)) * (1uL + (redundantCopy))) + +/** \} group_em_eeprom_macros */ + + +/****************************************************************************** +* Local definitions +*******************************************************************************/ +/** \cond INTERNAL */ + +/* Offsets for 32-bit RAM buffer addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u) +#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u) + +/* The same offsets as above used for direct memory addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u) + +#define CY_EM_EEPROM_U32_DIV (4u) + +/* Maximum wear leveling value */ +#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u) + +/* Maximum allowed flash row write/erase operation duration */ +#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u) + +/** \endcond */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* CY_EM_EEPROM_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cycodeshareexport.ld b/TrainingProjects/ADC-UART.cydsn/codegentemp/cycodeshareexport.ld new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cycodeshareimport.ld b/TrainingProjects/ADC-UART.cydsn/codegentemp/cycodeshareimport.ld new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cycodeshareimport.scat b/TrainingProjects/ADC-UART.cydsn/codegentemp/cycodeshareimport.scat new file mode 100644 index 0000000..e69de29 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevice_trm.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevice_trm.h new file mode 100644 index 0000000..47bacde --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevice_trm.h @@ -0,0 +1,6497 @@ +/******************************************************************************* +* File Name: cydevice_trm.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00008000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00008000u +#define CYDEV_SFLASH_BASE 0x0ffff000u +#define CYDEV_SFLASH_SIZE 0x00000200u +#define CYREG_SFLASH_PROT_ROW00 0x0ffff000u +#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000u +#define CYFLD_SFLASH_DATA8__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_ROW01 0x0ffff001u +#define CYREG_SFLASH_PROT_ROW02 0x0ffff002u +#define CYREG_SFLASH_PROT_ROW03 0x0ffff003u +#define CYREG_SFLASH_PROT_ROW04 0x0ffff004u +#define CYREG_SFLASH_PROT_ROW05 0x0ffff005u +#define CYREG_SFLASH_PROT_ROW06 0x0ffff006u +#define CYREG_SFLASH_PROT_ROW07 0x0ffff007u +#define CYREG_SFLASH_PROT_ROW08 0x0ffff008u +#define CYREG_SFLASH_PROT_ROW09 0x0ffff009u +#define CYREG_SFLASH_PROT_ROW10 0x0ffff00au +#define CYREG_SFLASH_PROT_ROW11 0x0ffff00bu +#define CYREG_SFLASH_PROT_ROW12 0x0ffff00cu +#define CYREG_SFLASH_PROT_ROW13 0x0ffff00du +#define CYREG_SFLASH_PROT_ROW14 0x0ffff00eu +#define CYREG_SFLASH_PROT_ROW15 0x0ffff00fu +#define CYREG_SFLASH_PROT_ROW16 0x0ffff010u +#define CYREG_SFLASH_PROT_ROW17 0x0ffff011u +#define CYREG_SFLASH_PROT_ROW18 0x0ffff012u +#define CYREG_SFLASH_PROT_ROW19 0x0ffff013u +#define CYREG_SFLASH_PROT_ROW20 0x0ffff014u +#define CYREG_SFLASH_PROT_ROW21 0x0ffff015u +#define CYREG_SFLASH_PROT_ROW22 0x0ffff016u +#define CYREG_SFLASH_PROT_ROW23 0x0ffff017u +#define CYREG_SFLASH_PROT_ROW24 0x0ffff018u +#define CYREG_SFLASH_PROT_ROW25 0x0ffff019u +#define CYREG_SFLASH_PROT_ROW26 0x0ffff01au +#define CYREG_SFLASH_PROT_ROW27 0x0ffff01bu +#define CYREG_SFLASH_PROT_ROW28 0x0ffff01cu +#define CYREG_SFLASH_PROT_ROW29 0x0ffff01du +#define CYREG_SFLASH_PROT_ROW30 0x0ffff01eu +#define CYREG_SFLASH_PROT_ROW31 0x0ffff01fu +#define CYREG_SFLASH_PROT_ROW32 0x0ffff020u +#define CYREG_SFLASH_PROT_ROW33 0x0ffff021u +#define CYREG_SFLASH_PROT_ROW34 0x0ffff022u +#define CYREG_SFLASH_PROT_ROW35 0x0ffff023u +#define CYREG_SFLASH_PROT_ROW36 0x0ffff024u +#define CYREG_SFLASH_PROT_ROW37 0x0ffff025u +#define CYREG_SFLASH_PROT_ROW38 0x0ffff026u +#define CYREG_SFLASH_PROT_ROW39 0x0ffff027u +#define CYREG_SFLASH_PROT_ROW40 0x0ffff028u +#define CYREG_SFLASH_PROT_ROW41 0x0ffff029u +#define CYREG_SFLASH_PROT_ROW42 0x0ffff02au +#define CYREG_SFLASH_PROT_ROW43 0x0ffff02bu +#define CYREG_SFLASH_PROT_ROW44 0x0ffff02cu +#define CYREG_SFLASH_PROT_ROW45 0x0ffff02du +#define CYREG_SFLASH_PROT_ROW46 0x0ffff02eu +#define CYREG_SFLASH_PROT_ROW47 0x0ffff02fu +#define CYREG_SFLASH_PROT_ROW48 0x0ffff030u +#define CYREG_SFLASH_PROT_ROW49 0x0ffff031u +#define CYREG_SFLASH_PROT_ROW50 0x0ffff032u +#define CYREG_SFLASH_PROT_ROW51 0x0ffff033u +#define CYREG_SFLASH_PROT_ROW52 0x0ffff034u +#define CYREG_SFLASH_PROT_ROW53 0x0ffff035u +#define CYREG_SFLASH_PROT_ROW54 0x0ffff036u +#define CYREG_SFLASH_PROT_ROW55 0x0ffff037u +#define CYREG_SFLASH_PROT_ROW56 0x0ffff038u +#define CYREG_SFLASH_PROT_ROW57 0x0ffff039u +#define CYREG_SFLASH_PROT_ROW58 0x0ffff03au +#define CYREG_SFLASH_PROT_ROW59 0x0ffff03bu +#define CYREG_SFLASH_PROT_ROW60 0x0ffff03cu +#define CYREG_SFLASH_PROT_ROW61 0x0ffff03du +#define CYREG_SFLASH_PROT_ROW62 0x0ffff03eu +#define CYREG_SFLASH_PROT_ROW63 0x0ffff03fu +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07fu +#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000u +#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002u +#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001u +#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000u +#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002u +#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003u +#define CYREG_SFLASH_AV_PAIRS_8B000 0x0ffff080u +#define CYREG_SFLASH_AV_PAIRS_8B001 0x0ffff081u +#define CYREG_SFLASH_AV_PAIRS_8B002 0x0ffff082u +#define CYREG_SFLASH_AV_PAIRS_8B003 0x0ffff083u +#define CYREG_SFLASH_AV_PAIRS_8B004 0x0ffff084u +#define CYREG_SFLASH_AV_PAIRS_8B005 0x0ffff085u +#define CYREG_SFLASH_AV_PAIRS_8B006 0x0ffff086u +#define CYREG_SFLASH_AV_PAIRS_8B007 0x0ffff087u +#define CYREG_SFLASH_AV_PAIRS_8B008 0x0ffff088u +#define CYREG_SFLASH_AV_PAIRS_8B009 0x0ffff089u +#define CYREG_SFLASH_AV_PAIRS_8B010 0x0ffff08au +#define CYREG_SFLASH_AV_PAIRS_8B011 0x0ffff08bu +#define CYREG_SFLASH_AV_PAIRS_8B012 0x0ffff08cu +#define CYREG_SFLASH_AV_PAIRS_8B013 0x0ffff08du +#define CYREG_SFLASH_AV_PAIRS_8B014 0x0ffff08eu +#define CYREG_SFLASH_AV_PAIRS_8B015 0x0ffff08fu +#define CYREG_SFLASH_AV_PAIRS_8B016 0x0ffff090u +#define CYREG_SFLASH_AV_PAIRS_8B017 0x0ffff091u +#define CYREG_SFLASH_AV_PAIRS_8B018 0x0ffff092u +#define CYREG_SFLASH_AV_PAIRS_8B019 0x0ffff093u +#define CYREG_SFLASH_AV_PAIRS_8B020 0x0ffff094u +#define CYREG_SFLASH_AV_PAIRS_8B021 0x0ffff095u +#define CYREG_SFLASH_AV_PAIRS_8B022 0x0ffff096u +#define CYREG_SFLASH_AV_PAIRS_8B023 0x0ffff097u +#define CYREG_SFLASH_AV_PAIRS_8B024 0x0ffff098u +#define CYREG_SFLASH_AV_PAIRS_8B025 0x0ffff099u +#define CYREG_SFLASH_AV_PAIRS_8B026 0x0ffff09au +#define CYREG_SFLASH_AV_PAIRS_8B027 0x0ffff09bu +#define CYREG_SFLASH_AV_PAIRS_8B028 0x0ffff09cu +#define CYREG_SFLASH_AV_PAIRS_8B029 0x0ffff09du +#define CYREG_SFLASH_AV_PAIRS_8B030 0x0ffff09eu +#define CYREG_SFLASH_AV_PAIRS_8B031 0x0ffff09fu +#define CYREG_SFLASH_AV_PAIRS_8B032 0x0ffff0a0u +#define CYREG_SFLASH_AV_PAIRS_8B033 0x0ffff0a1u +#define CYREG_SFLASH_AV_PAIRS_8B034 0x0ffff0a2u +#define CYREG_SFLASH_AV_PAIRS_8B035 0x0ffff0a3u +#define CYREG_SFLASH_AV_PAIRS_8B036 0x0ffff0a4u +#define CYREG_SFLASH_AV_PAIRS_8B037 0x0ffff0a5u +#define CYREG_SFLASH_AV_PAIRS_8B038 0x0ffff0a6u +#define CYREG_SFLASH_AV_PAIRS_8B039 0x0ffff0a7u +#define CYREG_SFLASH_AV_PAIRS_8B040 0x0ffff0a8u +#define CYREG_SFLASH_AV_PAIRS_8B041 0x0ffff0a9u +#define CYREG_SFLASH_AV_PAIRS_8B042 0x0ffff0aau +#define CYREG_SFLASH_AV_PAIRS_8B043 0x0ffff0abu +#define CYREG_SFLASH_AV_PAIRS_8B044 0x0ffff0acu +#define CYREG_SFLASH_AV_PAIRS_8B045 0x0ffff0adu +#define CYREG_SFLASH_AV_PAIRS_8B046 0x0ffff0aeu +#define CYREG_SFLASH_AV_PAIRS_8B047 0x0ffff0afu +#define CYREG_SFLASH_AV_PAIRS_8B048 0x0ffff0b0u +#define CYREG_SFLASH_AV_PAIRS_8B049 0x0ffff0b1u +#define CYREG_SFLASH_AV_PAIRS_8B050 0x0ffff0b2u +#define CYREG_SFLASH_AV_PAIRS_8B051 0x0ffff0b3u +#define CYREG_SFLASH_AV_PAIRS_8B052 0x0ffff0b4u +#define CYREG_SFLASH_AV_PAIRS_8B053 0x0ffff0b5u +#define CYREG_SFLASH_AV_PAIRS_8B054 0x0ffff0b6u +#define CYREG_SFLASH_AV_PAIRS_8B055 0x0ffff0b7u +#define CYREG_SFLASH_AV_PAIRS_8B056 0x0ffff0b8u +#define CYREG_SFLASH_AV_PAIRS_8B057 0x0ffff0b9u +#define CYREG_SFLASH_AV_PAIRS_8B058 0x0ffff0bau +#define CYREG_SFLASH_AV_PAIRS_8B059 0x0ffff0bbu +#define CYREG_SFLASH_AV_PAIRS_8B060 0x0ffff0bcu +#define CYREG_SFLASH_AV_PAIRS_8B061 0x0ffff0bdu +#define CYREG_SFLASH_AV_PAIRS_8B062 0x0ffff0beu +#define CYREG_SFLASH_AV_PAIRS_8B063 0x0ffff0bfu +#define CYREG_SFLASH_AV_PAIRS_8B064 0x0ffff0c0u +#define CYREG_SFLASH_AV_PAIRS_8B065 0x0ffff0c1u +#define CYREG_SFLASH_AV_PAIRS_8B066 0x0ffff0c2u +#define CYREG_SFLASH_AV_PAIRS_8B067 0x0ffff0c3u +#define CYREG_SFLASH_AV_PAIRS_8B068 0x0ffff0c4u +#define CYREG_SFLASH_AV_PAIRS_8B069 0x0ffff0c5u +#define CYREG_SFLASH_AV_PAIRS_8B070 0x0ffff0c6u +#define CYREG_SFLASH_AV_PAIRS_8B071 0x0ffff0c7u +#define CYREG_SFLASH_AV_PAIRS_8B072 0x0ffff0c8u +#define CYREG_SFLASH_AV_PAIRS_8B073 0x0ffff0c9u +#define CYREG_SFLASH_AV_PAIRS_8B074 0x0ffff0cau +#define CYREG_SFLASH_AV_PAIRS_8B075 0x0ffff0cbu +#define CYREG_SFLASH_AV_PAIRS_8B076 0x0ffff0ccu +#define CYREG_SFLASH_AV_PAIRS_8B077 0x0ffff0cdu +#define CYREG_SFLASH_AV_PAIRS_8B078 0x0ffff0ceu +#define CYREG_SFLASH_AV_PAIRS_8B079 0x0ffff0cfu +#define CYREG_SFLASH_AV_PAIRS_8B080 0x0ffff0d0u +#define CYREG_SFLASH_AV_PAIRS_8B081 0x0ffff0d1u +#define CYREG_SFLASH_AV_PAIRS_8B082 0x0ffff0d2u +#define CYREG_SFLASH_AV_PAIRS_8B083 0x0ffff0d3u +#define CYREG_SFLASH_AV_PAIRS_8B084 0x0ffff0d4u +#define CYREG_SFLASH_AV_PAIRS_8B085 0x0ffff0d5u +#define CYREG_SFLASH_AV_PAIRS_8B086 0x0ffff0d6u +#define CYREG_SFLASH_AV_PAIRS_8B087 0x0ffff0d7u +#define CYREG_SFLASH_AV_PAIRS_8B088 0x0ffff0d8u +#define CYREG_SFLASH_AV_PAIRS_8B089 0x0ffff0d9u +#define CYREG_SFLASH_AV_PAIRS_8B090 0x0ffff0dau +#define CYREG_SFLASH_AV_PAIRS_8B091 0x0ffff0dbu +#define CYREG_SFLASH_AV_PAIRS_8B092 0x0ffff0dcu +#define CYREG_SFLASH_AV_PAIRS_8B093 0x0ffff0ddu +#define CYREG_SFLASH_AV_PAIRS_8B094 0x0ffff0deu +#define CYREG_SFLASH_AV_PAIRS_8B095 0x0ffff0dfu +#define CYREG_SFLASH_AV_PAIRS_8B096 0x0ffff0e0u +#define CYREG_SFLASH_AV_PAIRS_8B097 0x0ffff0e1u +#define CYREG_SFLASH_AV_PAIRS_8B098 0x0ffff0e2u +#define CYREG_SFLASH_AV_PAIRS_8B099 0x0ffff0e3u +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4u +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5u +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6u +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7u +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8u +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9u +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0eau +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0ebu +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ecu +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0edu +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0eeu +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0efu +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0u +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1u +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2u +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3u +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4u +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5u +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6u +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7u +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8u +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9u +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fau +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fbu +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fcu +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fdu +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0feu +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ffu +#define CYREG_SFLASH_AV_PAIRS_32B00 0x0ffff100u +#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000u +#define CYFLD_SFLASH_DATA32__SIZE 0x00000020u +#define CYREG_SFLASH_AV_PAIRS_32B01 0x0ffff104u +#define CYREG_SFLASH_AV_PAIRS_32B02 0x0ffff108u +#define CYREG_SFLASH_AV_PAIRS_32B03 0x0ffff10cu +#define CYREG_SFLASH_AV_PAIRS_32B04 0x0ffff110u +#define CYREG_SFLASH_AV_PAIRS_32B05 0x0ffff114u +#define CYREG_SFLASH_AV_PAIRS_32B06 0x0ffff118u +#define CYREG_SFLASH_AV_PAIRS_32B07 0x0ffff11cu +#define CYREG_SFLASH_AV_PAIRS_32B08 0x0ffff120u +#define CYREG_SFLASH_AV_PAIRS_32B09 0x0ffff124u +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128u +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12cu +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130u +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134u +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138u +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13cu +#define CYREG_SFLASH_CPUSS_WOUNDING 0x0ffff140u +#define CYREG_SFLASH_SILICON_ID 0x0ffff144u +#define CYFLD_SFLASH_ID__OFFSET 0x00000000u +#define CYFLD_SFLASH_ID__SIZE 0x00000010u +#define CYREG_SFLASH_CPUSS_PRIV_RAM 0x0ffff148u +#define CYREG_SFLASH_CPUSS_PRIV_FLASH 0x0ffff14cu +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150u +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152u +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154u +#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u +#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158u +#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u +#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u +#define CYREG_SFLASH_FLASH_START 0x0ffff15cu +#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u +#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u +#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160u +#define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000u +#define CYFLD_SFLASH_TRIM8__SIZE 0x00000008u +#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161u +#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162u +#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163u +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164u +#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000u +#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010u +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166u +#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000u +#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010u +#define CYREG_SFLASH_SKIP_CHECKSUM 0x0ffff169u +#define CYFLD_SFLASH_SKIP__OFFSET 0x00000000u +#define CYFLD_SFLASH_SKIP__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170u +#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000u +#define CYFLD_SFLASH_KEY8__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171u +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172u +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173u +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174u +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175u +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176u +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177u +#define CYREG_SFLASH_DIE_LOT0 0x0ffff178u +#define CYFLD_SFLASH_LOT__OFFSET 0x00000000u +#define CYFLD_SFLASH_LOT__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_LOT1 0x0ffff179u +#define CYREG_SFLASH_DIE_LOT2 0x0ffff17au +#define CYREG_SFLASH_DIE_WAFER 0x0ffff17bu +#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u +#define CYFLD_SFLASH_WAFER__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_X 0x0ffff17cu +#define CYFLD_SFLASH_X__OFFSET 0x00000000u +#define CYFLD_SFLASH_X__SIZE 0x00000006u +#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000006u +#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000002u +#define CYREG_SFLASH_DIE_Y 0x0ffff17du +#define CYFLD_SFLASH_Y__OFFSET 0x00000000u +#define CYFLD_SFLASH_Y__SIZE 0x00000006u +#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000006u +#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000002u +#define CYREG_SFLASH_DIE_SORT 0x0ffff17eu +#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u +#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000002u +#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000002u +#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000002u +#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000004u +#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000002u +#define CYREG_SFLASH_DIE_MINOR 0x0ffff17fu +#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u +#define CYFLD_SFLASH_MINOR__SIZE 0x00000008u +#define CYREG_SFLASH_PE_TE_DATA00 0x0ffff180u +#define CYREG_SFLASH_PE_TE_DATA01 0x0ffff181u +#define CYREG_SFLASH_PE_TE_DATA02 0x0ffff182u +#define CYREG_SFLASH_PE_TE_DATA03 0x0ffff183u +#define CYREG_SFLASH_PE_TE_DATA04 0x0ffff184u +#define CYREG_SFLASH_PE_TE_DATA05 0x0ffff185u +#define CYREG_SFLASH_PE_TE_DATA06 0x0ffff186u +#define CYREG_SFLASH_PE_TE_DATA07 0x0ffff187u +#define CYREG_SFLASH_PE_TE_DATA08 0x0ffff188u +#define CYREG_SFLASH_PE_TE_DATA09 0x0ffff189u +#define CYREG_SFLASH_PE_TE_DATA10 0x0ffff18au +#define CYREG_SFLASH_PE_TE_DATA11 0x0ffff18bu +#define CYREG_SFLASH_PE_TE_DATA12 0x0ffff18cu +#define CYREG_SFLASH_PE_TE_DATA13 0x0ffff18du +#define CYREG_SFLASH_PE_TE_DATA14 0x0ffff18eu +#define CYREG_SFLASH_PE_TE_DATA15 0x0ffff18fu +#define CYREG_SFLASH_PE_TE_DATA16 0x0ffff190u +#define CYREG_SFLASH_PE_TE_DATA17 0x0ffff191u +#define CYREG_SFLASH_PE_TE_DATA18 0x0ffff192u +#define CYREG_SFLASH_PE_TE_DATA19 0x0ffff193u +#define CYREG_SFLASH_PE_TE_DATA20 0x0ffff194u +#define CYREG_SFLASH_PE_TE_DATA21 0x0ffff195u +#define CYREG_SFLASH_PE_TE_DATA22 0x0ffff196u +#define CYREG_SFLASH_PE_TE_DATA23 0x0ffff197u +#define CYREG_SFLASH_PE_TE_DATA24 0x0ffff198u +#define CYREG_SFLASH_PE_TE_DATA25 0x0ffff199u +#define CYREG_SFLASH_PE_TE_DATA26 0x0ffff19au +#define CYREG_SFLASH_PE_TE_DATA27 0x0ffff19bu +#define CYREG_SFLASH_PE_TE_DATA28 0x0ffff19cu +#define CYREG_SFLASH_PE_TE_DATA29 0x0ffff19du +#define CYREG_SFLASH_PE_TE_DATA30 0x0ffff19eu +#define CYREG_SFLASH_PE_TE_DATA31 0x0ffff19fu +#define CYREG_SFLASH_PP 0x0ffff1a0u +#define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000u +#define CYFLD_SFLASH_PERIOD__SIZE 0x00000018u +#define CYFLD_SFLASH_PDAC__OFFSET 0x00000018u +#define CYFLD_SFLASH_PDAC__SIZE 0x00000004u +#define CYFLD_SFLASH_NDAC__OFFSET 0x0000001cu +#define CYFLD_SFLASH_NDAC__SIZE 0x00000004u +#define CYREG_SFLASH_E 0x0ffff1a4u +#define CYREG_SFLASH_P 0x0ffff1a8u +#define CYREG_SFLASH_EA_E 0x0ffff1acu +#define CYREG_SFLASH_EA_P 0x0ffff1b0u +#define CYREG_SFLASH_ES_E 0x0ffff1b4u +#define CYREG_SFLASH_ES_P_EO 0x0ffff1b8u +#define CYREG_SFLASH_E_VCTAT 0x0ffff1bcu +#define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000u +#define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004u +#define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004u +#define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002u +#define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006u +#define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001u +#define CYREG_SFLASH_P_VCTAT 0x0ffff1bdu +#define CYREG_SFLASH_MARGIN 0x0ffff1beu +#define CYFLD_SFLASH_MDAC__OFFSET 0x00000000u +#define CYFLD_SFLASH_MDAC__SIZE 0x00000008u +#define CYREG_SFLASH_SPCIF_TRIM1 0x0ffff1bfu +#define CYFLD_SFLASH_BDAC__OFFSET 0x00000000u +#define CYFLD_SFLASH_BDAC__SIZE 0x00000004u +#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0u +#define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000u +#define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006u +#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1u +#define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006u +#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2u +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006u +#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3u +#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4u +#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5u +#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6u +#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7u +#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8u +#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9u +#define CYREG_SFLASH_IMO_ABS3 0x0ffff1cau +#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cbu +#define CYREG_SFLASH_IMO_ABS4 0x0ffff1ccu +#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cdu +#define CYREG_SFLASH_IMO_TRIM00 0x0ffff1d0u +#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u +#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u +#define CYREG_SFLASH_IMO_TRIM01 0x0ffff1d1u +#define CYREG_SFLASH_IMO_TRIM02 0x0ffff1d2u +#define CYREG_SFLASH_IMO_TRIM03 0x0ffff1d3u +#define CYREG_SFLASH_IMO_TRIM04 0x0ffff1d4u +#define CYREG_SFLASH_IMO_TRIM05 0x0ffff1d5u +#define CYREG_SFLASH_IMO_TRIM06 0x0ffff1d6u +#define CYREG_SFLASH_IMO_TRIM07 0x0ffff1d7u +#define CYREG_SFLASH_IMO_TRIM08 0x0ffff1d8u +#define CYREG_SFLASH_IMO_TRIM09 0x0ffff1d9u +#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1dau +#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1dbu +#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dcu +#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1ddu +#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1deu +#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1dfu +#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0u +#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1u +#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2u +#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3u +#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4u +#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5u +#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6u +#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7u +#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8u +#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9u +#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1eau +#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1ebu +#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ecu +#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1edu +#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1eeu +#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1efu +#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0u +#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1u +#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2u +#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3u +#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4u +#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5u +#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6u +#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7u +#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8u +#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9u +#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fau +#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fbu +#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fcu +#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fdu +#define CYREG_SFLASH_CHECKSUM 0x0ffff1feu +#define CYFLD_SFLASH_CHECKSUM__OFFSET 0x00000000u +#define CYFLD_SFLASH_CHECKSUM__SIZE 0x00000010u +#define CYDEV_SROM_BASE 0x10000000u +#define CYDEV_SROM_SIZE 0x00001000u +#define CYREG_SROM_DATA_MBASE 0x10000000u +#define CYREG_SROM_DATA_MSIZE 0x00001000u +#define CYDEV_SRAM_BASE 0x20000000u +#define CYDEV_SRAM_SIZE 0x00001000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00001000u +#define CYDEV_CPUSS_BASE 0x40000000u +#define CYDEV_CPUSS_SIZE 0x00010000u +#define CYREG_CPUSS_CONFIG 0x40000000u +#define CYFLD_CPUSS_VECS_IN_RAM__OFFSET 0x00000000u +#define CYFLD_CPUSS_VECS_IN_RAM__SIZE 0x00000001u +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET 0x00000001u +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE 0x00000001u +#define CYREG_CPUSS_SYSREQ 0x40000004u +#define CYFLD_CPUSS_COMMAND__OFFSET 0x00000000u +#define CYFLD_CPUSS_COMMAND__SIZE 0x00000010u +#define CYFLD_CPUSS_NO_RST_OVR__OFFSET 0x0000001bu +#define CYFLD_CPUSS_NO_RST_OVR__SIZE 0x00000001u +#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001cu +#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001u +#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001du +#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001u +#define CYFLD_CPUSS_HMASTER__OFFSET 0x0000001eu +#define CYFLD_CPUSS_HMASTER__SIZE 0x00000001u +#define CYFLD_CPUSS_SYSREQ__OFFSET 0x0000001fu +#define CYFLD_CPUSS_SYSREQ__SIZE 0x00000001u +#define CYREG_CPUSS_SYSARG 0x40000008u +#define CYFLD_CPUSS_ARG32__OFFSET 0x00000000u +#define CYFLD_CPUSS_ARG32__SIZE 0x00000020u +#define CYREG_CPUSS_PROTECTION 0x4000000cu +#define CYFLD_CPUSS_PROT__OFFSET 0x00000000u +#define CYFLD_CPUSS_PROT__SIZE 0x00000004u +#define CYVAL_CPUSS_PROT_VIRGIN 0x00000000u +#define CYVAL_CPUSS_PROT_OPEN 0x00000001u +#define CYVAL_CPUSS_PROT_PROTECTED 0x00000002u +#define CYVAL_CPUSS_PROT_KILL 0x00000004u +#define CYVAL_CPUSS_PROT_BOOT 0x00000008u +#define CYFLD_CPUSS_PROT_LOCK__OFFSET 0x0000001fu +#define CYFLD_CPUSS_PROT_LOCK__SIZE 0x00000001u +#define CYREG_CPUSS_PRIV_ROM 0x40000010u +#define CYFLD_CPUSS_ROM_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_ROM_LIMIT__SIZE 0x00000008u +#define CYREG_CPUSS_PRIV_RAM 0x40000014u +#define CYFLD_CPUSS_RAM_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_RAM_LIMIT__SIZE 0x00000009u +#define CYREG_CPUSS_PRIV_FLASH 0x40000018u +#define CYFLD_CPUSS_FLASH_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_FLASH_LIMIT__SIZE 0x0000000bu +#define CYREG_CPUSS_WOUNDING 0x4000001cu +#define CYFLD_CPUSS_RAM_SIZE__OFFSET 0x00000000u +#define CYFLD_CPUSS_RAM_SIZE__SIZE 0x00000009u +#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010u +#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003u +#define CYVAL_CPUSS_RAM_WOUND_FULL 0x00000000u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 0x00000001u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 0x00000002u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 0x00000003u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 0x00000004u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 0x00000005u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 0x00000006u +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 0x00000007u +#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014u +#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003u +#define CYVAL_CPUSS_FLASH_WOUND_FULL 0x00000000u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 0x00000001u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 0x00000002u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 0x00000003u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 0x00000004u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 0x00000005u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 0x00000006u +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 0x00000007u +#define CYREG_CPUSS_INTR_SELECT 0x40000020u +#define CYFLD_CPUSS_SELECT32__OFFSET 0x00000000u +#define CYFLD_CPUSS_SELECT32__SIZE 0x00000020u +#define CYDEV_HSIOM_BASE 0x40010000u +#define CYDEV_HSIOM_SIZE 0x00001000u +#define CYREG_HSIOM_PORT_SEL0 0x40010000u +#define CYFLD_HSIOM_SEL0__OFFSET 0x00000000u +#define CYFLD_HSIOM_SEL0__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL0_GPIO 0x00000000u +#define CYVAL_HSIOM_SEL0_GPIO_DSI 0x00000001u +#define CYVAL_HSIOM_SEL0_DSI_DSI 0x00000002u +#define CYVAL_HSIOM_SEL0_DSI_GPIO 0x00000003u +#define CYVAL_HSIOM_SEL0_CSD_SENSE 0x00000004u +#define CYVAL_HSIOM_SEL0_CSD_SHIELD 0x00000005u +#define CYVAL_HSIOM_SEL0_AMUXA 0x00000006u +#define CYVAL_HSIOM_SEL0_AMUXB 0x00000007u +#define CYVAL_HSIOM_SEL0_ACT_0 0x00000008u +#define CYVAL_HSIOM_SEL0_ACT_1 0x00000009u +#define CYVAL_HSIOM_SEL0_ACT_2 0x0000000au +#define CYVAL_HSIOM_SEL0_ACT_3 0x0000000bu +#define CYVAL_HSIOM_SEL0_LCD_COM 0x0000000cu +#define CYVAL_HSIOM_SEL0_LCD_SEG 0x0000000du +#define CYVAL_HSIOM_SEL0_DPSLP_0 0x0000000eu +#define CYVAL_HSIOM_SEL0_DPSLP_1 0x0000000fu +#define CYVAL_HSIOM_SEL0_COMP1_INP 0x00000000u +#define CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 0x0000000fu +#define CYFLD_HSIOM_SEL1__OFFSET 0x00000004u +#define CYFLD_HSIOM_SEL1__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL1_COMP1_INN 0x00000000u +#define CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 0x0000000fu +#define CYFLD_HSIOM_SEL2__OFFSET 0x00000008u +#define CYFLD_HSIOM_SEL2__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL2_COMP2_INP 0x00000000u +#define CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 0x0000000fu +#define CYFLD_HSIOM_SEL3__OFFSET 0x0000000cu +#define CYFLD_HSIOM_SEL3__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL3_COMP2_INN 0x00000000u +#define CYFLD_HSIOM_SEL4__OFFSET 0x00000010u +#define CYFLD_HSIOM_SEL4__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL4_SCB1_UART_RX 0x00000009u +#define CYVAL_HSIOM_SEL4_SCB1_I2C_SCL 0x0000000eu +#define CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI 0x0000000fu +#define CYFLD_HSIOM_SEL5__OFFSET 0x00000014u +#define CYFLD_HSIOM_SEL5__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL5_SCB1_UART_TX 0x00000009u +#define CYVAL_HSIOM_SEL5_SCB1_I2C_SDA 0x0000000eu +#define CYVAL_HSIOM_SEL5_SCB1_SPI_MISO 0x0000000fu +#define CYFLD_HSIOM_SEL6__OFFSET 0x00000018u +#define CYFLD_HSIOM_SEL6__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL6_EXT_CLK 0x00000008u +#define CYVAL_HSIOM_SEL6_SCB1_SPI_CLK 0x0000000fu +#define CYFLD_HSIOM_SEL7__OFFSET 0x0000001cu +#define CYFLD_HSIOM_SEL7__SIZE 0x00000004u +#define CYVAL_HSIOM_SEL7_WAKEUP 0x0000000eu +#define CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 0x0000000fu +#define CYREG_HSIOM_PORT_SEL1 0x40010004u +#define CYREG_HSIOM_PORT_SEL2 0x40010008u +#define CYREG_HSIOM_PORT_SEL3 0x4001000cu +#define CYREG_HSIOM_PORT_SEL4 0x40010010u +#define CYDEV_CLK_BASE 0x40020000u +#define CYDEV_CLK_SIZE 0x00010000u +#define CYREG_CLK_DIVIDER_A00 0x40020000u +#define CYFLD_CLK_DIVIDER_A__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_A__SIZE 0x00000010u +#define CYFLD_CLK_ENABLE_A__OFFSET 0x0000001fu +#define CYFLD_CLK_ENABLE_A__SIZE 0x00000001u +#define CYREG_CLK_DIVIDER_A01 0x40020004u +#define CYREG_CLK_DIVIDER_A02 0x40020008u +#define CYREG_CLK_DIVIDER_B00 0x40020040u +#define CYFLD_CLK_DIVIDER_B__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_B__SIZE 0x00000010u +#define CYFLD_CLK_CASCADE_A_B__OFFSET 0x0000001eu +#define CYFLD_CLK_CASCADE_A_B__SIZE 0x00000001u +#define CYFLD_CLK_ENABLE_B__OFFSET 0x0000001fu +#define CYFLD_CLK_ENABLE_B__SIZE 0x00000001u +#define CYREG_CLK_DIVIDER_B01 0x40020044u +#define CYREG_CLK_DIVIDER_B02 0x40020048u +#define CYREG_CLK_DIVIDER_C00 0x40020080u +#define CYFLD_CLK_DIVIDER_C__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_C__SIZE 0x00000010u +#define CYFLD_CLK_CASCADE_B_C__OFFSET 0x0000001eu +#define CYFLD_CLK_CASCADE_B_C__SIZE 0x00000001u +#define CYFLD_CLK_ENABLE_C__OFFSET 0x0000001fu +#define CYFLD_CLK_ENABLE_C__SIZE 0x00000001u +#define CYREG_CLK_DIVIDER_C01 0x40020084u +#define CYREG_CLK_DIVIDER_C02 0x40020088u +#define CYREG_CLK_DIVIDER_FRAC_A00 0x40020100u +#define CYFLD_CLK_FRAC_A__OFFSET 0x00000010u +#define CYFLD_CLK_FRAC_A__SIZE 0x00000005u +#define CYREG_CLK_DIVIDER_FRAC_B00 0x40020140u +#define CYFLD_CLK_FRAC_B__OFFSET 0x00000010u +#define CYFLD_CLK_FRAC_B__SIZE 0x00000005u +#define CYREG_CLK_DIVIDER_FRAC_C00 0x40020180u +#define CYFLD_CLK_FRAC_C__OFFSET 0x00000010u +#define CYFLD_CLK_FRAC_C__SIZE 0x00000005u +#define CYREG_CLK_SELECT00 0x40020200u +#define CYFLD_CLK_DIVIDER_N__OFFSET 0x00000000u +#define CYFLD_CLK_DIVIDER_N__SIZE 0x00000004u +#define CYFLD_CLK_DIVIDER_ABC__OFFSET 0x00000004u +#define CYFLD_CLK_DIVIDER_ABC__SIZE 0x00000002u +#define CYVAL_CLK_DIVIDER_ABC_OFF 0x00000000u +#define CYVAL_CLK_DIVIDER_ABC_A 0x00000001u +#define CYVAL_CLK_DIVIDER_ABC_B 0x00000002u +#define CYVAL_CLK_DIVIDER_ABC_C 0x00000003u +#define CYREG_CLK_SELECT01 0x40020204u +#define CYREG_CLK_SELECT02 0x40020208u +#define CYREG_CLK_SELECT03 0x4002020cu +#define CYREG_CLK_SELECT04 0x40020210u +#define CYREG_CLK_SELECT05 0x40020214u +#define CYREG_CLK_SELECT06 0x40020218u +#define CYREG_CLK_SELECT07 0x4002021cu +#define CYREG_CLK_SELECT08 0x40020220u +#define CYREG_CLK_SELECT09 0x40020224u +#define CYREG_CLK_SELECT10 0x40020228u +#define CYREG_CLK_SELECT11 0x4002022cu +#define CYREG_CLK_SELECT12 0x40020230u +#define CYREG_CLK_SELECT13 0x40020234u +#define CYREG_CLK_SELECT14 0x40020238u +#define CYREG_CLK_SELECT15 0x4002023cu +#define CYDEV_TST_BASE 0x40030000u +#define CYDEV_TST_SIZE 0x00010000u +#define CYREG_TST_CTRL 0x40030000u +#define CYFLD_TST_DAP_NO_ACCESS__OFFSET 0x00000000u +#define CYFLD_TST_DAP_NO_ACCESS__SIZE 0x00000001u +#define CYFLD_TST_DAP_NO_DEBUG__OFFSET 0x00000001u +#define CYFLD_TST_DAP_NO_DEBUG__SIZE 0x00000001u +#define CYFLD_TST_SWD_CONNECTED__OFFSET 0x00000002u +#define CYFLD_TST_SWD_CONNECTED__SIZE 0x00000001u +#define CYFLD_TST_TEST_RESET_EN_N__OFFSET 0x00000008u +#define CYFLD_TST_TEST_RESET_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_SET_EN_N__OFFSET 0x00000009u +#define CYFLD_TST_TEST_SET_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_ICG_EN_N__OFFSET 0x0000000au +#define CYFLD_TST_TEST_ICG_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET 0x0000000bu +#define CYFLD_TST_TEST_OCC0_1_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET 0x0000000cu +#define CYFLD_TST_TEST_OCC0_2_EN_N__SIZE 0x00000001u +#define CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET 0x0000000du +#define CYFLD_TST_TEST_SLPISOLATE_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET 0x0000000eu +#define CYFLD_TST_TEST_SYSISOLATE_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET 0x0000000fu +#define CYFLD_TST_TEST_SLPRETAIN_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET 0x00000010u +#define CYFLD_TST_TEST_SYSRETAIN_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SPARE1_EN__OFFSET 0x00000011u +#define CYFLD_TST_TEST_SPARE1_EN__SIZE 0x00000001u +#define CYFLD_TST_TEST_SPARE2_EN__OFFSET 0x00000012u +#define CYFLD_TST_TEST_SPARE2_EN__SIZE 0x00000001u +#define CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET 0x00000018u +#define CYFLD_TST_SCAN_OCC_OBSERVE__SIZE 0x00000001u +#define CYFLD_TST_SCAN_TRF1__OFFSET 0x00000019u +#define CYFLD_TST_SCAN_TRF1__SIZE 0x00000001u +#define CYFLD_TST_SCAN_TRF__OFFSET 0x0000001au +#define CYFLD_TST_SCAN_TRF__SIZE 0x00000001u +#define CYFLD_TST_SCAN_IDDQ__OFFSET 0x0000001bu +#define CYFLD_TST_SCAN_IDDQ__SIZE 0x00000001u +#define CYFLD_TST_SCAN_COMPRESS__OFFSET 0x0000001cu +#define CYFLD_TST_SCAN_COMPRESS__SIZE 0x00000001u +#define CYFLD_TST_SCAN_MODE__OFFSET 0x0000001du +#define CYFLD_TST_SCAN_MODE__SIZE 0x00000001u +#define CYFLD_TST_PTM_MODE_EN__OFFSET 0x0000001eu +#define CYFLD_TST_PTM_MODE_EN__SIZE 0x00000001u +#define CYREG_TST_ADFT_CTRL 0x40030004u +#define CYFLD_TST_ENABLE__OFFSET 0x0000001fu +#define CYFLD_TST_ENABLE__SIZE 0x00000001u +#define CYREG_TST_DDFT_CTRL 0x40030008u +#define CYFLD_TST_DFT_SEL1__OFFSET 0x00000000u +#define CYFLD_TST_DFT_SEL1__SIZE 0x00000006u +#define CYVAL_TST_DFT_SEL1_VSS 0x00000000u +#define CYVAL_TST_DFT_SEL1_CLK1 0x00000001u +#define CYVAL_TST_DFT_SEL1_CLK2 0x00000002u +#define CYVAL_TST_DFT_SEL1_PWR1 0x00000003u +#define CYVAL_TST_DFT_SEL1_PWR2 0x00000004u +#define CYVAL_TST_DFT_SEL1_VMON 0x00000005u +#define CYVAL_TST_DFT_SEL1_TSS_VDDA_OK 0x00000006u +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP1 0x00000007u +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP2 0x00000008u +#define CYVAL_TST_DFT_SEL1_TSS1 0x00000009u +#define CYVAL_TST_DFT_SEL1_TSS2 0x0000000au +#define CYVAL_TST_DFT_SEL1_TSS3 0x0000000bu +#define CYVAL_TST_DFT_SEL1_TSS4 0x0000000cu +#define CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS 0x0000000du +#define CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI 0x0000000eu +#define CYFLD_TST_DFT_SEL2__OFFSET 0x00000008u +#define CYFLD_TST_DFT_SEL2__SIZE 0x00000006u +#define CYVAL_TST_DFT_SEL2_VSS 0x00000000u +#define CYVAL_TST_DFT_SEL2_CLK1 0x00000001u +#define CYVAL_TST_DFT_SEL2_CLK2 0x00000002u +#define CYVAL_TST_DFT_SEL2_PWR1 0x00000003u +#define CYVAL_TST_DFT_SEL2_PWR2 0x00000004u +#define CYVAL_TST_DFT_SEL2_VMON 0x00000005u +#define CYVAL_TST_DFT_SEL2_TSS_VDDA_OK 0x00000006u +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP1 0x00000007u +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP2 0x00000008u +#define CYVAL_TST_DFT_SEL2_TSS1 0x00000009u +#define CYVAL_TST_DFT_SEL2_TSS2 0x0000000au +#define CYVAL_TST_DFT_SEL2_TSS3 0x0000000bu +#define CYVAL_TST_DFT_SEL2_TSS4 0x0000000cu +#define CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS 0x0000000du +#define CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI 0x0000000eu +#define CYFLD_TST_EDGE__OFFSET 0x0000001cu +#define CYFLD_TST_EDGE__SIZE 0x00000001u +#define CYVAL_TST_EDGE_POSEDGE 0x00000000u +#define CYVAL_TST_EDGE_NEGEDGE 0x00000001u +#define CYFLD_TST_DIVIDE__OFFSET 0x0000001du +#define CYFLD_TST_DIVIDE__SIZE 0x00000002u +#define CYVAL_TST_DIVIDE_DIRECT 0x00000000u +#define CYVAL_TST_DIVIDE_DIV_BY_2 0x00000001u +#define CYVAL_TST_DIVIDE_DIV_BY_4 0x00000002u +#define CYVAL_TST_DIVIDE_DIV_BY_8 0x00000003u +#define CYREG_TST_MODE 0x40030014u +#define CYFLD_TST_TEST_MODE__OFFSET 0x0000001fu +#define CYFLD_TST_TEST_MODE__SIZE 0x00000001u +#define CYREG_TST_TRIM_CNTR1 0x40030018u +#define CYFLD_TST_COUNTER__OFFSET 0x00000000u +#define CYFLD_TST_COUNTER__SIZE 0x00000010u +#define CYFLD_TST_COUNTER_DONE__OFFSET 0x0000001fu +#define CYFLD_TST_COUNTER_DONE__SIZE 0x00000001u +#define CYREG_TST_TRIM_CNTR2 0x4003001cu +#define CYDEV_PRT0_BASE 0x40040000u +#define CYDEV_PRT0_SIZE 0x00000100u +#define CYREG_PRT0_DR 0x40040000u +#define CYFLD_PRT_DATAREG__OFFSET 0x00000000u +#define CYFLD_PRT_DATAREG__SIZE 0x00000008u +#define CYREG_PRT0_PS 0x40040004u +#define CYFLD_PRT_PINSTATE__OFFSET 0x00000000u +#define CYFLD_PRT_PINSTATE__SIZE 0x00000008u +#define CYFLD_PRT_PINSTATE_FLT__OFFSET 0x00000008u +#define CYFLD_PRT_PINSTATE_FLT__SIZE 0x00000001u +#define CYREG_PRT0_PC 0x40040008u +#define CYFLD_PRT_DM__OFFSET 0x00000000u +#define CYFLD_PRT_DM__SIZE 0x00000018u +#define CYVAL_PRT_DM_OFF 0x00000000u +#define CYVAL_PRT_DM_INPUT 0x00000001u +#define CYVAL_PRT_DM_0_PU 0x00000002u +#define CYVAL_PRT_DM_PD_1 0x00000003u +#define CYVAL_PRT_DM_0_Z 0x00000004u +#define CYVAL_PRT_DM_Z_1 0x00000005u +#define CYVAL_PRT_DM_0_1 0x00000006u +#define CYVAL_PRT_DM_PD_PU 0x00000007u +#define CYFLD_PRT_VTRIP_SEL__OFFSET 0x00000018u +#define CYFLD_PRT_VTRIP_SEL__SIZE 0x00000001u +#define CYFLD_PRT_SLOW__OFFSET 0x00000019u +#define CYFLD_PRT_SLOW__SIZE 0x00000001u +#define CYREG_PRT0_INTCFG 0x4004000cu +#define CYFLD_PRT_INTTYPE__OFFSET 0x00000000u +#define CYFLD_PRT_INTTYPE__SIZE 0x00000010u +#define CYVAL_PRT_INTTYPE_DISABLE 0x00000000u +#define CYVAL_PRT_INTTYPE_RISING 0x00000001u +#define CYVAL_PRT_INTTYPE_FALLING 0x00000002u +#define CYVAL_PRT_INTTYPE_BOTH 0x00000003u +#define CYFLD_PRT_INTTYPE_FLT__OFFSET 0x00000010u +#define CYFLD_PRT_INTTYPE_FLT__SIZE 0x00000002u +#define CYVAL_PRT_INTTYPE_FLT_DISABLE 0x00000000u +#define CYVAL_PRT_INTTYPE_FLT_RISING 0x00000001u +#define CYVAL_PRT_INTTYPE_FLT_FALLING 0x00000002u +#define CYVAL_PRT_INTTYPE_FLT_BOTH 0x00000003u +#define CYFLD_PRT_FLT_SELECT__OFFSET 0x00000012u +#define CYFLD_PRT_FLT_SELECT__SIZE 0x00000003u +#define CYREG_PRT0_INTSTAT 0x40040010u +#define CYFLD_PRT_INTSTAT__OFFSET 0x00000000u +#define CYFLD_PRT_INTSTAT__SIZE 0x00000008u +#define CYFLD_PRT_INTSTAT_FLT__OFFSET 0x00000008u +#define CYFLD_PRT_INTSTAT_FLT__SIZE 0x00000001u +#define CYFLD_PRT_PS__OFFSET 0x00000010u +#define CYFLD_PRT_PS__SIZE 0x00000008u +#define CYFLD_PRT_PS_FLT__OFFSET 0x00000018u +#define CYFLD_PRT_PS_FLT__SIZE 0x00000001u +#define CYREG_PRT0_PC2 0x40040018u +#define CYFLD_PRT_INP_DIS__OFFSET 0x00000000u +#define CYFLD_PRT_INP_DIS__SIZE 0x00000008u +#define CYDEV_PRT1_BASE 0x40040100u +#define CYDEV_PRT1_SIZE 0x00000100u +#define CYREG_PRT1_DR 0x40040100u +#define CYREG_PRT1_PS 0x40040104u +#define CYREG_PRT1_PC 0x40040108u +#define CYREG_PRT1_INTCFG 0x4004010cu +#define CYREG_PRT1_INTSTAT 0x40040110u +#define CYREG_PRT1_PC2 0x40040118u +#define CYDEV_PRT2_BASE 0x40040200u +#define CYDEV_PRT2_SIZE 0x00000100u +#define CYREG_PRT2_DR 0x40040200u +#define CYREG_PRT2_PS 0x40040204u +#define CYREG_PRT2_PC 0x40040208u +#define CYREG_PRT2_INTCFG 0x4004020cu +#define CYREG_PRT2_INTSTAT 0x40040210u +#define CYREG_PRT2_PC2 0x40040218u +#define CYDEV_PRT3_BASE 0x40040300u +#define CYDEV_PRT3_SIZE 0x00000100u +#define CYREG_PRT3_DR 0x40040300u +#define CYREG_PRT3_PS 0x40040304u +#define CYREG_PRT3_PC 0x40040308u +#define CYREG_PRT3_INTCFG 0x4004030cu +#define CYREG_PRT3_INTSTAT 0x40040310u +#define CYREG_PRT3_PC2 0x40040318u +#define CYDEV_PRT4_BASE 0x40040400u +#define CYDEV_PRT4_SIZE 0x00000100u +#define CYREG_PRT4_DR 0x40040400u +#define CYREG_PRT4_PS 0x40040404u +#define CYREG_PRT4_PC 0x40040408u +#define CYREG_PRT4_INTCFG 0x4004040cu +#define CYREG_PRT4_INTSTAT 0x40040410u +#define CYREG_PRT4_PC2 0x40040418u +#define CYDEV_TCPWM_BASE 0x40050000u +#define CYDEV_TCPWM_SIZE 0x00001000u +#define CYREG_TCPWM_CTRL 0x40050000u +#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008u +#define CYREG_TCPWM_CMD 0x40050008u +#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008u +#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010u +#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018u +#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008u +#define CYREG_TCPWM_INTR_CAUSE 0x4005000cu +#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008u +#define CYDEV_TCPWM_CNT0_BASE 0x40050100u +#define CYDEV_TCPWM_CNT0_SIZE 0x00000040u +#define CYREG_TCPWM_CNT0_CTRL 0x40050100u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003u +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007u +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010u +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003u +#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012u +#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014u +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002u +#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018u +#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003u +#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000u +#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002u +#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003u +#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004u +#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005u +#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006u +#define CYREG_TCPWM_CNT0_STATUS 0x40050104u +#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001fu +#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001u +#define CYREG_TCPWM_CNT0_COUNTER 0x40050108u +#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_CC 0x4005010cu +#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_CC_BUFF 0x40050110u +#define CYREG_TCPWM_CNT0_PERIOD 0x40050114u +#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40050118u +#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40050120u +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000cu +#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010u +#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004u +#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40050124u +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006u +#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003u +#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40050128u +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003u +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003u +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003u +#define CYREG_TCPWM_CNT0_INTR 0x40050130u +#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001u +#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001u +#define CYREG_TCPWM_CNT0_INTR_SET 0x40050134u +#define CYREG_TCPWM_CNT0_INTR_MASK 0x40050138u +#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4005013cu +#define CYDEV_TCPWM_CNT1_BASE 0x40050140u +#define CYDEV_TCPWM_CNT1_SIZE 0x00000040u +#define CYREG_TCPWM_CNT1_CTRL 0x40050140u +#define CYREG_TCPWM_CNT1_STATUS 0x40050144u +#define CYREG_TCPWM_CNT1_COUNTER 0x40050148u +#define CYREG_TCPWM_CNT1_CC 0x4005014cu +#define CYREG_TCPWM_CNT1_CC_BUFF 0x40050150u +#define CYREG_TCPWM_CNT1_PERIOD 0x40050154u +#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40050158u +#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40050160u +#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40050164u +#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40050168u +#define CYREG_TCPWM_CNT1_INTR 0x40050170u +#define CYREG_TCPWM_CNT1_INTR_SET 0x40050174u +#define CYREG_TCPWM_CNT1_INTR_MASK 0x40050178u +#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4005017cu +#define CYDEV_TCPWM_CNT2_BASE 0x40050180u +#define CYDEV_TCPWM_CNT2_SIZE 0x00000040u +#define CYREG_TCPWM_CNT2_CTRL 0x40050180u +#define CYREG_TCPWM_CNT2_STATUS 0x40050184u +#define CYREG_TCPWM_CNT2_COUNTER 0x40050188u +#define CYREG_TCPWM_CNT2_CC 0x4005018cu +#define CYREG_TCPWM_CNT2_CC_BUFF 0x40050190u +#define CYREG_TCPWM_CNT2_PERIOD 0x40050194u +#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40050198u +#define CYREG_TCPWM_CNT2_TR_CTRL0 0x400501a0u +#define CYREG_TCPWM_CNT2_TR_CTRL1 0x400501a4u +#define CYREG_TCPWM_CNT2_TR_CTRL2 0x400501a8u +#define CYREG_TCPWM_CNT2_INTR 0x400501b0u +#define CYREG_TCPWM_CNT2_INTR_SET 0x400501b4u +#define CYREG_TCPWM_CNT2_INTR_MASK 0x400501b8u +#define CYREG_TCPWM_CNT2_INTR_MASKED 0x400501bcu +#define CYDEV_TCPWM_CNT3_BASE 0x400501c0u +#define CYDEV_TCPWM_CNT3_SIZE 0x00000040u +#define CYREG_TCPWM_CNT3_CTRL 0x400501c0u +#define CYREG_TCPWM_CNT3_STATUS 0x400501c4u +#define CYREG_TCPWM_CNT3_COUNTER 0x400501c8u +#define CYREG_TCPWM_CNT3_CC 0x400501ccu +#define CYREG_TCPWM_CNT3_CC_BUFF 0x400501d0u +#define CYREG_TCPWM_CNT3_PERIOD 0x400501d4u +#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x400501d8u +#define CYREG_TCPWM_CNT3_TR_CTRL0 0x400501e0u +#define CYREG_TCPWM_CNT3_TR_CTRL1 0x400501e4u +#define CYREG_TCPWM_CNT3_TR_CTRL2 0x400501e8u +#define CYREG_TCPWM_CNT3_INTR 0x400501f0u +#define CYREG_TCPWM_CNT3_INTR_SET 0x400501f4u +#define CYREG_TCPWM_CNT3_INTR_MASK 0x400501f8u +#define CYREG_TCPWM_CNT3_INTR_MASKED 0x400501fcu +#define CYDEV_SCB0_BASE 0x40060000u +#define CYDEV_SCB0_SIZE 0x00010000u +#define CYREG_SCB0_CTRL 0x40060000u +#define CYFLD_SCB_OVS__OFFSET 0x00000000u +#define CYFLD_SCB_OVS__SIZE 0x00000004u +#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008u +#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001u +#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009u +#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001u +#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000au +#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001u +#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010u +#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001u +#define CYFLD_SCB_BLOCK__OFFSET 0x00000011u +#define CYFLD_SCB_BLOCK__SIZE 0x00000001u +#define CYFLD_SCB_MODE__OFFSET 0x00000018u +#define CYFLD_SCB_MODE__SIZE 0x00000002u +#define CYVAL_SCB_MODE_I2C 0x00000000u +#define CYVAL_SCB_MODE_SPI 0x00000001u +#define CYVAL_SCB_MODE_UART 0x00000002u +#define CYFLD_SCB_ENABLED__OFFSET 0x0000001fu +#define CYFLD_SCB_ENABLED__SIZE 0x00000001u +#define CYREG_SCB0_STATUS 0x40060004u +#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000u +#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001u +#define CYREG_SCB0_SPI_CTRL 0x40060020u +#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000u +#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001u +#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001u +#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001u +#define CYFLD_SCB_CPHA__OFFSET 0x00000002u +#define CYFLD_SCB_CPHA__SIZE 0x00000001u +#define CYFLD_SCB_CPOL__OFFSET 0x00000003u +#define CYFLD_SCB_CPOL__SIZE 0x00000001u +#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004u +#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001u +#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010u +#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001u +#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001au +#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002u +#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001fu +#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001u +#define CYREG_SCB0_SPI_STATUS 0x40060024u +#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000u +#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001u +#define CYFLD_SCB_EZ_ADDR__OFFSET 0x00000008u +#define CYFLD_SCB_EZ_ADDR__SIZE 0x00000008u +#define CYREG_SCB0_UART_CTRL 0x40060040u +#define CYREG_SCB0_UART_TX_CTRL 0x40060044u +#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000u +#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003u +#define CYFLD_SCB_PARITY__OFFSET 0x00000004u +#define CYFLD_SCB_PARITY__SIZE 0x00000001u +#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005u +#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001u +#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008u +#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001u +#define CYREG_SCB0_UART_RX_CTRL 0x40060048u +#define CYFLD_SCB_POLARITY__OFFSET 0x00000006u +#define CYFLD_SCB_POLARITY__SIZE 0x00000001u +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009u +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000au +#define CYFLD_SCB_MP_MODE__SIZE 0x00000001u +#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000cu +#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001u +#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000du +#define CYFLD_SCB_SKIP_START__SIZE 0x00000001u +#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010u +#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004u +#define CYREG_SCB0_UART_RX_STATUS 0x4006004cu +#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000u +#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000cu +#define CYREG_SCB0_I2C_CTRL 0x40060060u +#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000u +#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004u +#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004u +#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004u +#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008u +#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001u +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009u +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001u +#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000bu +#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001u +#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000cu +#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000du +#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000eu +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000fu +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001u +#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001eu +#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001u +#define CYREG_SCB0_I2C_STATUS 0x40060064u +#define CYFLD_SCB_S_READ__OFFSET 0x00000004u +#define CYFLD_SCB_S_READ__SIZE 0x00000001u +#define CYFLD_SCB_M_READ__OFFSET 0x00000005u +#define CYFLD_SCB_M_READ__SIZE 0x00000001u +#define CYREG_SCB0_I2C_M_CMD 0x40060068u +#define CYFLD_SCB_M_START__OFFSET 0x00000000u +#define CYFLD_SCB_M_START__SIZE 0x00000001u +#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001u +#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001u +#define CYFLD_SCB_M_ACK__OFFSET 0x00000002u +#define CYFLD_SCB_M_ACK__SIZE 0x00000001u +#define CYFLD_SCB_M_NACK__OFFSET 0x00000003u +#define CYFLD_SCB_M_NACK__SIZE 0x00000001u +#define CYFLD_SCB_M_STOP__OFFSET 0x00000004u +#define CYFLD_SCB_M_STOP__SIZE 0x00000001u +#define CYREG_SCB0_I2C_S_CMD 0x4006006cu +#define CYFLD_SCB_S_ACK__OFFSET 0x00000000u +#define CYFLD_SCB_S_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NACK__OFFSET 0x00000001u +#define CYFLD_SCB_S_NACK__SIZE 0x00000001u +#define CYREG_SCB0_I2C_CFG 0x40060070u +#define CYFLD_SCB_SDA_FILT_HYS__OFFSET 0x00000000u +#define CYFLD_SCB_SDA_FILT_HYS__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_TRIM__OFFSET 0x00000002u +#define CYFLD_SCB_SDA_FILT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SCL_FILT_HYS__OFFSET 0x00000004u +#define CYFLD_SCB_SCL_FILT_HYS__SIZE 0x00000002u +#define CYFLD_SCB_SCL_FILT_TRIM__OFFSET 0x00000006u +#define CYFLD_SCB_SCL_FILT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET 0x00000008u +#define CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET 0x0000000au +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_FILT_HS__OFFSET 0x00000010u +#define CYFLD_SCB_SDA_FILT_HS__SIZE 0x00000001u +#define CYFLD_SCB_SDA_FILT_ENABLED__OFFSET 0x00000011u +#define CYFLD_SCB_SDA_FILT_ENABLED__SIZE 0x00000001u +#define CYFLD_SCB_SCL_FILT_HS__OFFSET 0x00000018u +#define CYFLD_SCB_SCL_FILT_HS__SIZE 0x00000001u +#define CYFLD_SCB_SCL_FILT_ENABLED__OFFSET 0x00000019u +#define CYFLD_SCB_SCL_FILT_ENABLED__SIZE 0x00000001u +#define CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET 0x0000001au +#define CYFLD_SCB_SDA_FILT_OUT_HS__SIZE 0x00000001u +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET 0x0000001bu +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE 0x00000001u +#define CYREG_SCB0_BIST_CONTROL 0x40060100u +#define CYFLD_SCB_RAM_ADDR__OFFSET 0x00000000u +#define CYFLD_SCB_RAM_ADDR__SIZE 0x00000005u +#define CYFLD_SCB_RAM_OP1__OFFSET 0x00000010u +#define CYFLD_SCB_RAM_OP1__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OP2__OFFSET 0x00000012u +#define CYFLD_SCB_RAM_OP2__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OP3__OFFSET 0x00000014u +#define CYFLD_SCB_RAM_OP3__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OP4__OFFSET 0x00000016u +#define CYFLD_SCB_RAM_OP4__SIZE 0x00000002u +#define CYFLD_SCB_RAM_OPCNT__OFFSET 0x00000018u +#define CYFLD_SCB_RAM_OPCNT__SIZE 0x00000002u +#define CYFLD_SCB_RAM_PREADR__OFFSET 0x0000001au +#define CYFLD_SCB_RAM_PREADR__SIZE 0x00000001u +#define CYFLD_SCB_RAM_WORD__OFFSET 0x0000001bu +#define CYFLD_SCB_RAM_WORD__SIZE 0x00000001u +#define CYFLD_SCB_RAM_FAIL__OFFSET 0x0000001cu +#define CYFLD_SCB_RAM_FAIL__SIZE 0x00000001u +#define CYFLD_SCB_RAM_GO__OFFSET 0x0000001du +#define CYFLD_SCB_RAM_GO__SIZE 0x00000001u +#define CYREG_SCB0_BIST_DATA 0x40060104u +#define CYFLD_SCB_RAM_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_RAM_DATA__SIZE 0x00000010u +#define CYREG_SCB0_TX_CTRL 0x40060200u +#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000u +#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004u +#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008u +#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001u +#define CYREG_SCB0_TX_FIFO_CTRL 0x40060204u +#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000u +#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000003u +#define CYFLD_SCB_CLEAR__OFFSET 0x00000010u +#define CYFLD_SCB_CLEAR__SIZE 0x00000001u +#define CYFLD_SCB_FREEZE__OFFSET 0x00000011u +#define CYFLD_SCB_FREEZE__SIZE 0x00000001u +#define CYREG_SCB0_TX_FIFO_STATUS 0x40060208u +#define CYFLD_SCB_USED__OFFSET 0x00000000u +#define CYFLD_SCB_USED__SIZE 0x00000004u +#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000fu +#define CYFLD_SCB_SR_VALID__SIZE 0x00000001u +#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010u +#define CYFLD_SCB_RD_PTR__SIZE 0x00000003u +#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018u +#define CYFLD_SCB_WR_PTR__SIZE 0x00000003u +#define CYREG_SCB0_TX_FIFO_WR 0x40060240u +#define CYFLD_SCB_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_DATA__SIZE 0x00000010u +#define CYREG_SCB0_RX_CTRL 0x40060300u +#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009u +#define CYFLD_SCB_MEDIAN__SIZE 0x00000001u +#define CYREG_SCB0_RX_FIFO_CTRL 0x40060304u +#define CYREG_SCB0_RX_FIFO_STATUS 0x40060308u +#define CYREG_SCB0_RX_MATCH 0x40060310u +#define CYFLD_SCB_ADDR__OFFSET 0x00000000u +#define CYFLD_SCB_ADDR__SIZE 0x00000008u +#define CYFLD_SCB_MASK__OFFSET 0x00000010u +#define CYFLD_SCB_MASK__SIZE 0x00000008u +#define CYREG_SCB0_RX_FIFO_RD 0x40060340u +#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40060344u +#define CYREG_SCB0_EZ_DATA00 0x40060400u +#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008u +#define CYREG_SCB0_EZ_DATA01 0x40060404u +#define CYREG_SCB0_EZ_DATA02 0x40060408u +#define CYREG_SCB0_EZ_DATA03 0x4006040cu +#define CYREG_SCB0_EZ_DATA04 0x40060410u +#define CYREG_SCB0_EZ_DATA05 0x40060414u +#define CYREG_SCB0_EZ_DATA06 0x40060418u +#define CYREG_SCB0_EZ_DATA07 0x4006041cu +#define CYREG_SCB0_EZ_DATA08 0x40060420u +#define CYREG_SCB0_EZ_DATA09 0x40060424u +#define CYREG_SCB0_EZ_DATA10 0x40060428u +#define CYREG_SCB0_EZ_DATA11 0x4006042cu +#define CYREG_SCB0_EZ_DATA12 0x40060430u +#define CYREG_SCB0_EZ_DATA13 0x40060434u +#define CYREG_SCB0_EZ_DATA14 0x40060438u +#define CYREG_SCB0_EZ_DATA15 0x4006043cu +#define CYREG_SCB0_EZ_DATA16 0x40060440u +#define CYREG_SCB0_EZ_DATA17 0x40060444u +#define CYREG_SCB0_EZ_DATA18 0x40060448u +#define CYREG_SCB0_EZ_DATA19 0x4006044cu +#define CYREG_SCB0_EZ_DATA20 0x40060450u +#define CYREG_SCB0_EZ_DATA21 0x40060454u +#define CYREG_SCB0_EZ_DATA22 0x40060458u +#define CYREG_SCB0_EZ_DATA23 0x4006045cu +#define CYREG_SCB0_EZ_DATA24 0x40060460u +#define CYREG_SCB0_EZ_DATA25 0x40060464u +#define CYREG_SCB0_EZ_DATA26 0x40060468u +#define CYREG_SCB0_EZ_DATA27 0x4006046cu +#define CYREG_SCB0_EZ_DATA28 0x40060470u +#define CYREG_SCB0_EZ_DATA29 0x40060474u +#define CYREG_SCB0_EZ_DATA30 0x40060478u +#define CYREG_SCB0_EZ_DATA31 0x4006047cu +#define CYREG_SCB0_INTR_CAUSE 0x40060e00u +#define CYFLD_SCB_M__OFFSET 0x00000000u +#define CYFLD_SCB_M__SIZE 0x00000001u +#define CYFLD_SCB_S__OFFSET 0x00000001u +#define CYFLD_SCB_S__SIZE 0x00000001u +#define CYFLD_SCB_TX__OFFSET 0x00000002u +#define CYFLD_SCB_TX__SIZE 0x00000001u +#define CYFLD_SCB_RX__OFFSET 0x00000003u +#define CYFLD_SCB_RX__SIZE 0x00000001u +#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004u +#define CYFLD_SCB_I2C_EC__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005u +#define CYFLD_SCB_SPI_EC__SIZE 0x00000001u +#define CYREG_SCB0_INTR_I2C_EC 0x40060e80u +#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000u +#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001u +#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001u +#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001u +#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002u +#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001u +#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40060e88u +#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40060e8cu +#define CYREG_SCB0_INTR_SPI_EC 0x40060ec0u +#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40060ec8u +#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40060eccu +#define CYREG_SCB0_INTR_M 0x40060f00u +#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000u +#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001u +#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001u +#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001u +#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002u +#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001u +#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004u +#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001u +#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009u +#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001u +#define CYREG_SCB0_INTR_M_SET 0x40060f04u +#define CYREG_SCB0_INTR_M_MASK 0x40060f08u +#define CYREG_SCB0_INTR_M_MASKED 0x40060f0cu +#define CYREG_SCB0_INTR_S 0x40060f40u +#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003u +#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001u +#define CYFLD_SCB_I2C_START__OFFSET 0x00000005u +#define CYFLD_SCB_I2C_START__SIZE 0x00000001u +#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006u +#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001u +#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007u +#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009u +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000au +#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001u +#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000bu +#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001u +#define CYREG_SCB0_INTR_S_SET 0x40060f44u +#define CYREG_SCB0_INTR_S_MASK 0x40060f48u +#define CYREG_SCB0_INTR_S_MASKED 0x40060f4cu +#define CYREG_SCB0_INTR_TX 0x40060f80u +#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000u +#define CYFLD_SCB_TRIGGER__SIZE 0x00000001u +#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001u +#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001u +#define CYFLD_SCB_EMPTY__OFFSET 0x00000004u +#define CYFLD_SCB_EMPTY__SIZE 0x00000001u +#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005u +#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001u +#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006u +#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001u +#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007u +#define CYFLD_SCB_BLOCKED__SIZE 0x00000001u +#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008u +#define CYFLD_SCB_UART_NACK__SIZE 0x00000001u +#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009u +#define CYFLD_SCB_UART_DONE__SIZE 0x00000001u +#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000au +#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001u +#define CYREG_SCB0_INTR_TX_SET 0x40060f84u +#define CYREG_SCB0_INTR_TX_MASK 0x40060f88u +#define CYREG_SCB0_INTR_TX_MASKED 0x40060f8cu +#define CYREG_SCB0_INTR_RX 0x40060fc0u +#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002u +#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001u +#define CYFLD_SCB_FULL__OFFSET 0x00000003u +#define CYFLD_SCB_FULL__SIZE 0x00000001u +#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009u +#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000au +#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001u +#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000bu +#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001u +#define CYREG_SCB0_INTR_RX_SET 0x40060fc4u +#define CYREG_SCB0_INTR_RX_MASK 0x40060fc8u +#define CYREG_SCB0_INTR_RX_MASKED 0x40060fccu +#define CYDEV_SCB1_BASE 0x40070000u +#define CYDEV_SCB1_SIZE 0x00010000u +#define CYREG_SCB1_CTRL 0x40070000u +#define CYREG_SCB1_STATUS 0x40070004u +#define CYREG_SCB1_SPI_CTRL 0x40070020u +#define CYREG_SCB1_SPI_STATUS 0x40070024u +#define CYREG_SCB1_UART_CTRL 0x40070040u +#define CYREG_SCB1_UART_TX_CTRL 0x40070044u +#define CYREG_SCB1_UART_RX_CTRL 0x40070048u +#define CYREG_SCB1_UART_RX_STATUS 0x4007004cu +#define CYREG_SCB1_I2C_CTRL 0x40070060u +#define CYREG_SCB1_I2C_STATUS 0x40070064u +#define CYREG_SCB1_I2C_M_CMD 0x40070068u +#define CYREG_SCB1_I2C_S_CMD 0x4007006cu +#define CYREG_SCB1_I2C_CFG 0x40070070u +#define CYREG_SCB1_BIST_CONTROL 0x40070100u +#define CYREG_SCB1_BIST_DATA 0x40070104u +#define CYREG_SCB1_TX_CTRL 0x40070200u +#define CYREG_SCB1_TX_FIFO_CTRL 0x40070204u +#define CYREG_SCB1_TX_FIFO_STATUS 0x40070208u +#define CYREG_SCB1_TX_FIFO_WR 0x40070240u +#define CYREG_SCB1_RX_CTRL 0x40070300u +#define CYREG_SCB1_RX_FIFO_CTRL 0x40070304u +#define CYREG_SCB1_RX_FIFO_STATUS 0x40070308u +#define CYREG_SCB1_RX_MATCH 0x40070310u +#define CYREG_SCB1_RX_FIFO_RD 0x40070340u +#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40070344u +#define CYREG_SCB1_EZ_DATA00 0x40070400u +#define CYREG_SCB1_EZ_DATA01 0x40070404u +#define CYREG_SCB1_EZ_DATA02 0x40070408u +#define CYREG_SCB1_EZ_DATA03 0x4007040cu +#define CYREG_SCB1_EZ_DATA04 0x40070410u +#define CYREG_SCB1_EZ_DATA05 0x40070414u +#define CYREG_SCB1_EZ_DATA06 0x40070418u +#define CYREG_SCB1_EZ_DATA07 0x4007041cu +#define CYREG_SCB1_EZ_DATA08 0x40070420u +#define CYREG_SCB1_EZ_DATA09 0x40070424u +#define CYREG_SCB1_EZ_DATA10 0x40070428u +#define CYREG_SCB1_EZ_DATA11 0x4007042cu +#define CYREG_SCB1_EZ_DATA12 0x40070430u +#define CYREG_SCB1_EZ_DATA13 0x40070434u +#define CYREG_SCB1_EZ_DATA14 0x40070438u +#define CYREG_SCB1_EZ_DATA15 0x4007043cu +#define CYREG_SCB1_EZ_DATA16 0x40070440u +#define CYREG_SCB1_EZ_DATA17 0x40070444u +#define CYREG_SCB1_EZ_DATA18 0x40070448u +#define CYREG_SCB1_EZ_DATA19 0x4007044cu +#define CYREG_SCB1_EZ_DATA20 0x40070450u +#define CYREG_SCB1_EZ_DATA21 0x40070454u +#define CYREG_SCB1_EZ_DATA22 0x40070458u +#define CYREG_SCB1_EZ_DATA23 0x4007045cu +#define CYREG_SCB1_EZ_DATA24 0x40070460u +#define CYREG_SCB1_EZ_DATA25 0x40070464u +#define CYREG_SCB1_EZ_DATA26 0x40070468u +#define CYREG_SCB1_EZ_DATA27 0x4007046cu +#define CYREG_SCB1_EZ_DATA28 0x40070470u +#define CYREG_SCB1_EZ_DATA29 0x40070474u +#define CYREG_SCB1_EZ_DATA30 0x40070478u +#define CYREG_SCB1_EZ_DATA31 0x4007047cu +#define CYREG_SCB1_INTR_CAUSE 0x40070e00u +#define CYREG_SCB1_INTR_I2C_EC 0x40070e80u +#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40070e88u +#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40070e8cu +#define CYREG_SCB1_INTR_SPI_EC 0x40070ec0u +#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40070ec8u +#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40070eccu +#define CYREG_SCB1_INTR_M 0x40070f00u +#define CYREG_SCB1_INTR_M_SET 0x40070f04u +#define CYREG_SCB1_INTR_M_MASK 0x40070f08u +#define CYREG_SCB1_INTR_M_MASKED 0x40070f0cu +#define CYREG_SCB1_INTR_S 0x40070f40u +#define CYREG_SCB1_INTR_S_SET 0x40070f44u +#define CYREG_SCB1_INTR_S_MASK 0x40070f48u +#define CYREG_SCB1_INTR_S_MASKED 0x40070f4cu +#define CYREG_SCB1_INTR_TX 0x40070f80u +#define CYREG_SCB1_INTR_TX_SET 0x40070f84u +#define CYREG_SCB1_INTR_TX_MASK 0x40070f88u +#define CYREG_SCB1_INTR_TX_MASKED 0x40070f8cu +#define CYREG_SCB1_INTR_RX 0x40070fc0u +#define CYREG_SCB1_INTR_RX_SET 0x40070fc4u +#define CYREG_SCB1_INTR_RX_MASK 0x40070fc8u +#define CYREG_SCB1_INTR_RX_MASKED 0x40070fccu +#define CYDEV_CSD_BASE 0x40080000u +#define CYDEV_CSD_SIZE 0x00010000u +#define CYREG_CSD_ID 0x40080000u +#define CYFLD_CSD_ID__OFFSET 0x00000000u +#define CYFLD_CSD_ID__SIZE 0x00000010u +#define CYFLD_CSD_REVISION__OFFSET 0x00000010u +#define CYFLD_CSD_REVISION__SIZE 0x00000010u +#define CYREG_CSD_CONFIG 0x40080004u +#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000000u +#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001u +#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x00000001u +#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001u +#define CYFLD_CSD_PRS_CLEAR__OFFSET 0x00000005u +#define CYFLD_CSD_PRS_CLEAR__SIZE 0x00000001u +#define CYFLD_CSD_PRS_SELECT__OFFSET 0x00000006u +#define CYFLD_CSD_PRS_SELECT__SIZE 0x00000001u +#define CYVAL_CSD_PRS_SELECT_DIV2 0x00000000u +#define CYVAL_CSD_PRS_SELECT_PRS 0x00000001u +#define CYFLD_CSD_PRS_12_8__OFFSET 0x00000007u +#define CYFLD_CSD_PRS_12_8__SIZE 0x00000001u +#define CYVAL_CSD_PRS_12_8_8B 0x00000000u +#define CYVAL_CSD_PRS_12_8_12B 0x00000001u +#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x00000008u +#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001u +#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000009u +#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002u +#define CYFLD_CSD_SENSE_COMP_BW__OFFSET 0x0000000bu +#define CYFLD_CSD_SENSE_COMP_BW__SIZE 0x00000001u +#define CYVAL_CSD_SENSE_COMP_BW_LOW 0x00000000u +#define CYVAL_CSD_SENSE_COMP_BW_HIGH 0x00000001u +#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000cu +#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001u +#define CYFLD_CSD_REFBUF_EN__OFFSET 0x0000000du +#define CYFLD_CSD_REFBUF_EN__SIZE 0x00000001u +#define CYFLD_CSD_COMP_MODE__OFFSET 0x0000000eu +#define CYFLD_CSD_COMP_MODE__SIZE 0x00000001u +#define CYVAL_CSD_COMP_MODE_CHARGE_BUF 0x00000000u +#define CYVAL_CSD_COMP_MODE_CHARGE_IO 0x00000001u +#define CYFLD_CSD_COMP_PIN__OFFSET 0x0000000fu +#define CYFLD_CSD_COMP_PIN__SIZE 0x00000001u +#define CYVAL_CSD_COMP_PIN_CHANNEL1 0x00000000u +#define CYVAL_CSD_COMP_PIN_CHANNEL2 0x00000001u +#define CYFLD_CSD_POLARITY__OFFSET 0x00000010u +#define CYFLD_CSD_POLARITY__SIZE 0x00000001u +#define CYVAL_CSD_POLARITY_VSSIO 0x00000000u +#define CYVAL_CSD_POLARITY_VDDIO 0x00000001u +#define CYFLD_CSD_POLARITY2__OFFSET 0x00000011u +#define CYFLD_CSD_POLARITY2__SIZE 0x00000001u +#define CYVAL_CSD_POLARITY2_VSSIO 0x00000000u +#define CYVAL_CSD_POLARITY2_VDDIO 0x00000001u +#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012u +#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001u +#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000u +#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001u +#define CYFLD_CSD_SENSE_COMP_EN__OFFSET 0x00000013u +#define CYFLD_CSD_SENSE_COMP_EN__SIZE 0x00000001u +#define CYFLD_CSD_REBUF_OUTSEL__OFFSET 0x00000015u +#define CYFLD_CSD_REBUF_OUTSEL__SIZE 0x00000001u +#define CYVAL_CSD_REBUF_OUTSEL_AMUXA 0x00000000u +#define CYVAL_CSD_REBUF_OUTSEL_AMUXB 0x00000001u +#define CYFLD_CSD_SENSE_INSEL__OFFSET 0x00000016u +#define CYFLD_CSD_SENSE_INSEL__SIZE 0x00000001u +#define CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 0x00000000u +#define CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA 0x00000001u +#define CYFLD_CSD_REFBUF_DRV__OFFSET 0x00000017u +#define CYFLD_CSD_REFBUF_DRV__SIZE 0x00000002u +#define CYVAL_CSD_REFBUF_DRV_OFF 0x00000000u +#define CYVAL_CSD_REFBUF_DRV_DRV_1 0x00000001u +#define CYVAL_CSD_REFBUF_DRV_DRV_2 0x00000002u +#define CYVAL_CSD_REFBUF_DRV_DRV_3 0x00000003u +#define CYFLD_CSD_DDFTSEL__OFFSET 0x0000001au +#define CYFLD_CSD_DDFTSEL__SIZE 0x00000003u +#define CYVAL_CSD_DDFTSEL_NORMAL 0x00000000u +#define CYVAL_CSD_DDFTSEL_CSD_SENSE 0x00000001u +#define CYVAL_CSD_DDFTSEL_CSD_SHIELD 0x00000002u +#define CYVAL_CSD_DDFTSEL_CLK_SAMPLE 0x00000003u +#define CYVAL_CSD_DDFTSEL_COMP_OUT 0x00000004u +#define CYFLD_CSD_ADFTEN__OFFSET 0x0000001du +#define CYFLD_CSD_ADFTEN__SIZE 0x00000001u +#define CYFLD_CSD_DDFTCOMP__OFFSET 0x0000001eu +#define CYFLD_CSD_DDFTCOMP__SIZE 0x00000001u +#define CYVAL_CSD_DDFTCOMP_REFBUFCOMP 0x00000000u +#define CYVAL_CSD_DDFTCOMP_SENSECOMP 0x00000001u +#define CYFLD_CSD_ENABLE__OFFSET 0x0000001fu +#define CYFLD_CSD_ENABLE__SIZE 0x00000001u +#define CYREG_CSD_IDAC 0x40080008u +#define CYFLD_CSD_IDAC1__OFFSET 0x00000000u +#define CYFLD_CSD_IDAC1__SIZE 0x00000008u +#define CYFLD_CSD_IDAC1_MODE__OFFSET 0x00000008u +#define CYFLD_CSD_IDAC1_MODE__SIZE 0x00000002u +#define CYVAL_CSD_IDAC1_MODE_OFF 0x00000000u +#define CYVAL_CSD_IDAC1_MODE_FIXED 0x00000001u +#define CYVAL_CSD_IDAC1_MODE_VARIABLE 0x00000002u +#define CYVAL_CSD_IDAC1_MODE_DSI 0x00000003u +#define CYFLD_CSD_IDAC1_RANGE__OFFSET 0x0000000au +#define CYFLD_CSD_IDAC1_RANGE__SIZE 0x00000001u +#define CYVAL_CSD_IDAC1_RANGE_4X 0x00000000u +#define CYVAL_CSD_IDAC1_RANGE_8X 0x00000001u +#define CYFLD_CSD_IDAC2__OFFSET 0x00000010u +#define CYFLD_CSD_IDAC2__SIZE 0x00000007u +#define CYFLD_CSD_IDAC2_MODE__OFFSET 0x00000018u +#define CYFLD_CSD_IDAC2_MODE__SIZE 0x00000002u +#define CYVAL_CSD_IDAC2_MODE_OFF 0x00000000u +#define CYVAL_CSD_IDAC2_MODE_FIXED 0x00000001u +#define CYVAL_CSD_IDAC2_MODE_VARIABLE 0x00000002u +#define CYVAL_CSD_IDAC2_MODE_DSI 0x00000003u +#define CYFLD_CSD_IDAC2_RANGE__OFFSET 0x0000001au +#define CYFLD_CSD_IDAC2_RANGE__SIZE 0x00000001u +#define CYVAL_CSD_IDAC2_RANGE_4X 0x00000000u +#define CYVAL_CSD_IDAC2_RANGE_8X 0x00000001u +#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001eu +#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001u +#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000u +#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001u +#define CYREG_CSD_COUNTER 0x4008000cu +#define CYFLD_CSD_COUNTER__OFFSET 0x00000000u +#define CYFLD_CSD_COUNTER__SIZE 0x00000010u +#define CYFLD_CSD_PERIOD__OFFSET 0x00000010u +#define CYFLD_CSD_PERIOD__SIZE 0x00000010u +#define CYREG_CSD_STATUS 0x40080010u +#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000u +#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001u +#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001u +#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001u +#define CYFLD_CSD_COMP_OUT__OFFSET 0x00000002u +#define CYFLD_CSD_COMP_OUT__SIZE 0x00000001u +#define CYVAL_CSD_COMP_OUT_C_LT_VREF 0x00000000u +#define CYVAL_CSD_COMP_OUT_C_GT_VREF 0x00000001u +#define CYFLD_CSD_SAMPLE__OFFSET 0x00000003u +#define CYFLD_CSD_SAMPLE__SIZE 0x00000001u +#define CYREG_CSD_INTR 0x40080014u +#define CYFLD_CSD_CSD__OFFSET 0x00000000u +#define CYFLD_CSD_CSD__SIZE 0x00000001u +#define CYREG_CSD_INTR_SET 0x40080018u +#define CYREG_CSD_TRIM1 0x4008ff00u +#define CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET 0x00000000u +#define CYFLD_CSD_IDAC1_SRC_TRIM__SIZE 0x00000004u +#define CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET 0x00000004u +#define CYFLD_CSD_IDAC2_SRC_TRIM__SIZE 0x00000004u +#define CYREG_CSD_TRIM2 0x4008ff04u +#define CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET 0x00000000u +#define CYFLD_CSD_IDAC1_SNK_TRIM__SIZE 0x00000004u +#define CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET 0x00000004u +#define CYFLD_CSD_IDAC2_SNK_TRIM__SIZE 0x00000004u +#define CYDEV_LCD_BASE 0x40090000u +#define CYDEV_LCD_SIZE 0x00010000u +#define CYREG_LCD_ID 0x40090000u +#define CYFLD_LCD_ID__OFFSET 0x00000000u +#define CYFLD_LCD_ID__SIZE 0x00000010u +#define CYFLD_LCD_REVISION__OFFSET 0x00000010u +#define CYFLD_LCD_REVISION__SIZE 0x00000010u +#define CYREG_LCD_DIVIDER 0x40090004u +#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000u +#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010u +#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010u +#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010u +#define CYREG_LCD_CONTROL 0x40090008u +#define CYFLD_LCD_LS_EN__OFFSET 0x00000000u +#define CYFLD_LCD_LS_EN__SIZE 0x00000001u +#define CYFLD_LCD_HS_EN__OFFSET 0x00000001u +#define CYFLD_LCD_HS_EN__SIZE 0x00000001u +#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002u +#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001u +#define CYVAL_LCD_LCD_MODE_LS 0x00000000u +#define CYVAL_LCD_LCD_MODE_HS 0x00000001u +#define CYFLD_LCD_TYPE__OFFSET 0x00000003u +#define CYFLD_LCD_TYPE__SIZE 0x00000001u +#define CYVAL_LCD_TYPE_A 0x00000000u +#define CYVAL_LCD_TYPE_B 0x00000001u +#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004u +#define CYFLD_LCD_OP_MODE__SIZE 0x00000001u +#define CYVAL_LCD_OP_MODE_PWM 0x00000000u +#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001u +#define CYFLD_LCD_BIAS__OFFSET 0x00000005u +#define CYFLD_LCD_BIAS__SIZE 0x00000002u +#define CYVAL_LCD_BIAS_HALF 0x00000000u +#define CYVAL_LCD_BIAS_THIRD 0x00000001u +#define CYVAL_LCD_BIAS_FOURTH 0x00000002u +#define CYVAL_LCD_BIAS_FIFTH 0x00000003u +#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008u +#define CYFLD_LCD_COM_NUM__SIZE 0x00000004u +#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001fu +#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001u +#define CYREG_LCD_DATA00 0x40090100u +#define CYFLD_LCD_DATA__OFFSET 0x00000000u +#define CYFLD_LCD_DATA__SIZE 0x00000020u +#define CYREG_LCD_DATA01 0x40090104u +#define CYREG_LCD_DATA02 0x40090108u +#define CYREG_LCD_DATA03 0x4009010cu +#define CYREG_LCD_DATA04 0x40090110u +#define CYDEV_LPCOMP_BASE 0x400a0000u +#define CYDEV_LPCOMP_SIZE 0x00010000u +#define CYREG_LPCOMP_ID 0x400a0000u +#define CYFLD_LPCOMP_ID__OFFSET 0x00000000u +#define CYFLD_LPCOMP_ID__SIZE 0x00000010u +#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010u +#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010u +#define CYREG_LPCOMP_CONFIG 0x400a0004u +#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000u +#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002u +#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000u +#define CYVAL_LPCOMP_MODE1_FAST 0x00000001u +#define CYVAL_LPCOMP_MODE1_ULP 0x00000002u +#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002u +#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001u +#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003u +#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001u +#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004u +#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002u +#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000u +#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001u +#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002u +#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003u +#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006u +#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001u +#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007u +#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001u +#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008u +#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002u +#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000u +#define CYVAL_LPCOMP_MODE2_FAST 0x00000001u +#define CYVAL_LPCOMP_MODE2_ULP 0x00000002u +#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000au +#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001u +#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000bu +#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001u +#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000cu +#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002u +#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000u +#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001u +#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002u +#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003u +#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000eu +#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001u +#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000fu +#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001u +#define CYREG_LPCOMP_DFT 0x400a0008u +#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000u +#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001u +#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001u +#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001u +#define CYREG_LPCOMP_INTR 0x400a000cu +#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001u +#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001u +#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001u +#define CYREG_LPCOMP_INTR_SET 0x400a0010u +#define CYREG_LPCOMP_TRIM1 0x400aff00u +#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM2 0x400aff04u +#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM3 0x400aff08u +#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM4 0x400aff0cu +#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005u +#define CYREG_PWR_CONTROL 0x400b0000u +#define CYFLD__POWER_MODE__OFFSET 0x00000000u +#define CYFLD__POWER_MODE__SIZE 0x00000004u +#define CYVAL__POWER_MODE_RESET 0x00000000u +#define CYVAL__POWER_MODE_ACTIVE 0x00000001u +#define CYVAL__POWER_MODE_SLEEP 0x00000002u +#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003u +#define CYVAL__POWER_MODE_HIBERNATE 0x00000004u +#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004u +#define CYFLD__DEBUG_SESSION__SIZE 0x00000001u +#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000u +#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001u +#define CYFLD__LPM_READY__OFFSET 0x00000005u +#define CYFLD__LPM_READY__SIZE 0x00000001u +#define CYFLD__EXT_VCCD__OFFSET 0x00000017u +#define CYFLD__EXT_VCCD__SIZE 0x00000001u +#define CYFLD__HVMON_ENABLE__OFFSET 0x00000018u +#define CYFLD__HVMON_ENABLE__SIZE 0x00000001u +#define CYFLD__HVMON_RELOAD__OFFSET 0x00000019u +#define CYFLD__HVMON_RELOAD__SIZE 0x00000001u +#define CYFLD__FIMO_DISABLE__OFFSET 0x0000001bu +#define CYFLD__FIMO_DISABLE__SIZE 0x00000001u +#define CYFLD__HIBERNATE_DISABLE__OFFSET 0x0000001cu +#define CYFLD__HIBERNATE_DISABLE__SIZE 0x00000001u +#define CYFLD__LFCLK_SHORT__OFFSET 0x0000001du +#define CYFLD__LFCLK_SHORT__SIZE 0x00000001u +#define CYFLD__HIBERNATE__OFFSET 0x0000001fu +#define CYFLD__HIBERNATE__SIZE 0x00000001u +#define CYVAL__HIBERNATE_DEEP_SLEEP 0x00000000u +#define CYVAL__HIBERNATE_HIBERNATE 0x00000001u +#define CYREG_PWR_INTR 0x400b0004u +#define CYFLD__LVD__OFFSET 0x00000001u +#define CYFLD__LVD__SIZE 0x00000001u +#define CYREG_PWR_INTR_MASK 0x400b0008u +#define CYREG_PWR_KEY_DELAY 0x400b000cu +#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000u +#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000au +#define CYREG_PWR_PWRSYS_CONFIG 0x400b0010u +#define CYFLD__HIB_TEST_EN__OFFSET 0x00000008u +#define CYFLD__HIB_TEST_EN__SIZE 0x00000001u +#define CYFLD__HIB_TEST_REP__OFFSET 0x00000009u +#define CYFLD__HIB_TEST_REP__SIZE 0x00000001u +#define CYREG_PWR_BG_CONFIG 0x400b0014u +#define CYFLD__BG_DFT_EN__OFFSET 0x00000000u +#define CYFLD__BG_DFT_EN__SIZE 0x00000001u +#define CYFLD__BG_DFT_VREF_SEL__OFFSET 0x00000001u +#define CYFLD__BG_DFT_VREF_SEL__SIZE 0x00000004u +#define CYFLD__BG_DFT_CORE_SEL__OFFSET 0x00000005u +#define CYFLD__BG_DFT_CORE_SEL__SIZE 0x00000001u +#define CYFLD__BG_DFT_ICORE_SEL__OFFSET 0x00000006u +#define CYFLD__BG_DFT_ICORE_SEL__SIZE 0x00000002u +#define CYFLD__BG_DFT_VCORE_SEL__OFFSET 0x00000008u +#define CYFLD__BG_DFT_VCORE_SEL__SIZE 0x00000001u +#define CYFLD__VREF_EN__OFFSET 0x00000010u +#define CYFLD__VREF_EN__SIZE 0x00000003u +#define CYREG_PWR_VMON_CONFIG 0x400b0018u +#define CYFLD__LVD_EN__OFFSET 0x00000000u +#define CYFLD__LVD_EN__SIZE 0x00000001u +#define CYFLD__LVD_SEL__OFFSET 0x00000001u +#define CYFLD__LVD_SEL__SIZE 0x00000004u +#define CYFLD__VMON_DDFT_SEL__OFFSET 0x00000005u +#define CYFLD__VMON_DDFT_SEL__SIZE 0x00000003u +#define CYFLD__VMON_ADFT_SEL__OFFSET 0x00000008u +#define CYFLD__VMON_ADFT_SEL__SIZE 0x00000002u +#define CYREG_PWR_DFT_SELECT 0x400b001cu +#define CYFLD__TVMON1_SEL__OFFSET 0x00000000u +#define CYFLD__TVMON1_SEL__SIZE 0x00000003u +#define CYFLD__TVMON2_SEL__OFFSET 0x00000003u +#define CYFLD__TVMON2_SEL__SIZE 0x00000003u +#define CYFLD__BYPASS__OFFSET 0x00000006u +#define CYFLD__BYPASS__SIZE 0x00000001u +#define CYFLD__ACTIVE_EN__OFFSET 0x00000007u +#define CYFLD__ACTIVE_EN__SIZE 0x00000001u +#define CYFLD__ACTIVE_INRUSH_DIS__OFFSET 0x00000008u +#define CYFLD__ACTIVE_INRUSH_DIS__SIZE 0x00000001u +#define CYFLD__LPCOMP_DIS__OFFSET 0x00000009u +#define CYFLD__LPCOMP_DIS__SIZE 0x00000001u +#define CYFLD__BLEED_EN__OFFSET 0x0000000au +#define CYFLD__BLEED_EN__SIZE 0x00000001u +#define CYFLD__IPOR_EN__OFFSET 0x0000000bu +#define CYFLD__IPOR_EN__SIZE 0x00000001u +#define CYFLD__POWER_UP_RAW_BYP__OFFSET 0x0000000cu +#define CYFLD__POWER_UP_RAW_BYP__SIZE 0x00000001u +#define CYFLD__POWER_UP_RAW_CTL__OFFSET 0x0000000du +#define CYFLD__POWER_UP_RAW_CTL__SIZE 0x00000001u +#define CYFLD__DEEPSLEEP_EN__OFFSET 0x0000000eu +#define CYFLD__DEEPSLEEP_EN__SIZE 0x00000001u +#define CYFLD__RSVD_BYPASS__OFFSET 0x0000000fu +#define CYFLD__RSVD_BYPASS__SIZE 0x00000001u +#define CYFLD__NWELL_OPEN__OFFSET 0x00000010u +#define CYFLD__NWELL_OPEN__SIZE 0x00000001u +#define CYFLD__HIBERNATE_OPEN__OFFSET 0x00000011u +#define CYFLD__HIBERNATE_OPEN__SIZE 0x00000001u +#define CYFLD__DEEPSLEEP_OPEN__OFFSET 0x00000012u +#define CYFLD__DEEPSLEEP_OPEN__SIZE 0x00000001u +#define CYFLD__QUIET_OPEN__OFFSET 0x00000013u +#define CYFLD__QUIET_OPEN__SIZE 0x00000001u +#define CYFLD__LFCLK_OPEN__OFFSET 0x00000014u +#define CYFLD__LFCLK_OPEN__SIZE 0x00000001u +#define CYFLD__QUIET_EN__OFFSET 0x00000016u +#define CYFLD__QUIET_EN__SIZE 0x00000001u +#define CYFLD__BREF_EN__OFFSET 0x00000017u +#define CYFLD__BREF_EN__SIZE 0x00000001u +#define CYFLD__BREF_OUTEN__OFFSET 0x00000018u +#define CYFLD__BREF_OUTEN__SIZE 0x00000001u +#define CYFLD__BREF_REFSW__OFFSET 0x00000019u +#define CYFLD__BREF_REFSW__SIZE 0x00000001u +#define CYFLD__BREF_TESTMODE__OFFSET 0x0000001au +#define CYFLD__BREF_TESTMODE__SIZE 0x00000001u +#define CYFLD__NWELL_DIS__OFFSET 0x0000001bu +#define CYFLD__NWELL_DIS__SIZE 0x00000001u +#define CYFLD__HVMON_DFT_OVR__OFFSET 0x0000001cu +#define CYFLD__HVMON_DFT_OVR__SIZE 0x00000001u +#define CYFLD__IMO_REFGEN_DIS__OFFSET 0x0000001du +#define CYFLD__IMO_REFGEN_DIS__SIZE 0x00000001u +#define CYFLD__POWER_UP_ACTIVE__OFFSET 0x0000001eu +#define CYFLD__POWER_UP_ACTIVE__SIZE 0x00000001u +#define CYFLD__POWER_UP_HIBDPSLP__OFFSET 0x0000001fu +#define CYFLD__POWER_UP_HIBDPSLP__SIZE 0x00000001u +#define CYREG_PWR_DDFT_SELECT 0x400b0020u +#define CYFLD__DDFT1_SEL__OFFSET 0x00000000u +#define CYFLD__DDFT1_SEL__SIZE 0x00000004u +#define CYFLD__DDFT2_SEL__OFFSET 0x00000004u +#define CYFLD__DDFT2_SEL__SIZE 0x00000004u +#define CYREG_PWR_DFT_KEY 0x400b0024u +#define CYFLD__KEY16__OFFSET 0x00000000u +#define CYFLD__KEY16__SIZE 0x00000010u +#define CYFLD__HBOD_OFF_AWAKE__OFFSET 0x00000010u +#define CYFLD__HBOD_OFF_AWAKE__SIZE 0x00000001u +#define CYFLD__BODS_OFF__OFFSET 0x00000011u +#define CYFLD__BODS_OFF__SIZE 0x00000001u +#define CYFLD__DFT_MODE__OFFSET 0x00000012u +#define CYFLD__DFT_MODE__SIZE 0x00000001u +#define CYFLD__IO_DISABLE_BYPASS__OFFSET 0x00000013u +#define CYFLD__IO_DISABLE_BYPASS__SIZE 0x00000001u +#define CYFLD__VMON_PD__OFFSET 0x00000014u +#define CYFLD__VMON_PD__SIZE 0x00000001u +#define CYREG_PWR_BOD_KEY 0x400b0028u +#define CYREG_PWR_STOP 0x400b002cu +#define CYFLD__TOKEN__OFFSET 0x00000000u +#define CYFLD__TOKEN__SIZE 0x00000008u +#define CYFLD__UNLOCK__OFFSET 0x00000008u +#define CYFLD__UNLOCK__SIZE 0x00000008u +#define CYFLD__POLARITY__OFFSET 0x00000010u +#define CYFLD__POLARITY__SIZE 0x00000001u +#define CYFLD__FREEZE__OFFSET 0x00000011u +#define CYFLD__FREEZE__SIZE 0x00000001u +#define CYFLD__STOP__OFFSET 0x0000001fu +#define CYFLD__STOP__SIZE 0x00000001u +#define CYREG_CLK_SELECT 0x400b0100u +#define CYFLD__DIRECT_SEL__OFFSET 0x00000000u +#define CYFLD__DIRECT_SEL__SIZE 0x00000003u +#define CYVAL__DIRECT_SEL_IMO 0x00000000u +#define CYVAL__DIRECT_SEL_EXTCLK 0x00000001u +#define CYVAL__DIRECT_SEL_ECO 0x00000002u +#define CYVAL__DIRECT_SEL_DSI0 0x00000004u +#define CYVAL__DIRECT_SEL_DSI1 0x00000005u +#define CYVAL__DIRECT_SEL_DSI2 0x00000006u +#define CYVAL__DIRECT_SEL_DSI3 0x00000007u +#define CYFLD__DBL_SEL__OFFSET 0x00000003u +#define CYFLD__DBL_SEL__SIZE 0x00000003u +#define CYVAL__DBL_SEL_IMO 0x00000000u +#define CYVAL__DBL_SEL_EXTCLK 0x00000001u +#define CYVAL__DBL_SEL_ECO 0x00000002u +#define CYVAL__DBL_SEL_DSI0 0x00000004u +#define CYVAL__DBL_SEL_DSI1 0x00000005u +#define CYVAL__DBL_SEL_DSI2 0x00000006u +#define CYVAL__DBL_SEL_DSI3 0x00000007u +#define CYFLD__PLL_SEL__OFFSET 0x00000006u +#define CYFLD__PLL_SEL__SIZE 0x00000003u +#define CYVAL__PLL_SEL_IMO 0x00000000u +#define CYVAL__PLL_SEL_EXTCLK 0x00000001u +#define CYVAL__PLL_SEL_ECO 0x00000002u +#define CYVAL__PLL_SEL_DPLL 0x00000003u +#define CYVAL__PLL_SEL_DSI0 0x00000004u +#define CYVAL__PLL_SEL_DSI1 0x00000005u +#define CYVAL__PLL_SEL_DSI2 0x00000006u +#define CYVAL__PLL_SEL_DSI3 0x00000007u +#define CYFLD__DPLLIN_SEL__OFFSET 0x00000009u +#define CYFLD__DPLLIN_SEL__SIZE 0x00000003u +#define CYVAL__DPLLIN_SEL_IMO 0x00000000u +#define CYVAL__DPLLIN_SEL_EXTCLK 0x00000001u +#define CYVAL__DPLLIN_SEL_ECO 0x00000002u +#define CYVAL__DPLLIN_SEL_DSI0 0x00000004u +#define CYVAL__DPLLIN_SEL_DSI1 0x00000005u +#define CYVAL__DPLLIN_SEL_DSI2 0x00000006u +#define CYVAL__DPLLIN_SEL_DSI3 0x00000007u +#define CYFLD__DPLLREF_SEL__OFFSET 0x0000000cu +#define CYFLD__DPLLREF_SEL__SIZE 0x00000002u +#define CYVAL__DPLLREF_SEL_DSI0 0x00000000u +#define CYVAL__DPLLREF_SEL_DSI1 0x00000001u +#define CYVAL__DPLLREF_SEL_DSI2 0x00000002u +#define CYVAL__DPLLREF_SEL_DSI3 0x00000003u +#define CYFLD__WDT_LOCK__OFFSET 0x0000000eu +#define CYFLD__WDT_LOCK__SIZE 0x00000002u +#define CYVAL__WDT_LOCK_NO_CHG 0x00000000u +#define CYVAL__WDT_LOCK_CLR0 0x00000001u +#define CYVAL__WDT_LOCK_CLR1 0x00000002u +#define CYVAL__WDT_LOCK_SET01 0x00000003u +#define CYFLD__HFCLK_SEL__OFFSET 0x00000010u +#define CYFLD__HFCLK_SEL__SIZE 0x00000002u +#define CYVAL__HFCLK_SEL_DIRECT_SEL 0x00000000u +#define CYVAL__HFCLK_SEL_DBL 0x00000001u +#define CYVAL__HFCLK_SEL_PLL 0x00000002u +#define CYFLD__HALF_EN__OFFSET 0x00000012u +#define CYFLD__HALF_EN__SIZE 0x00000001u +#define CYFLD__SYSCLK_DIV__OFFSET 0x00000013u +#define CYFLD__SYSCLK_DIV__SIZE 0x00000003u +#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000u +#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001u +#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002u +#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003u +#define CYVAL__SYSCLK_DIV_DIV_BY_16 0x00000004u +#define CYVAL__SYSCLK_DIV_DIV_BY_32 0x00000005u +#define CYVAL__SYSCLK_DIV_DIV_BY_64 0x00000006u +#define CYVAL__SYSCLK_DIV_DIV_BY_128 0x00000007u +#define CYREG_CLK_ILO_CONFIG 0x400b0104u +#define CYFLD__PD_MODE__OFFSET 0x00000000u +#define CYFLD__PD_MODE__SIZE 0x00000001u +#define CYVAL__PD_MODE_SLEEP 0x00000000u +#define CYVAL__PD_MODE_COMA 0x00000001u +#define CYFLD__TURBO__OFFSET 0x00000001u +#define CYFLD__TURBO__SIZE 0x00000001u +#define CYFLD__SATBIAS__OFFSET 0x00000002u +#define CYFLD__SATBIAS__SIZE 0x00000001u +#define CYVAL__SATBIAS_SATURATED 0x00000000u +#define CYVAL__SATBIAS_SUBTHRESHOLD 0x00000001u +#define CYFLD__ENABLE__OFFSET 0x0000001fu +#define CYFLD__ENABLE__SIZE 0x00000001u +#define CYREG_CLK_IMO_CONFIG 0x400b0108u +#define CYFLD__FLASHPUMP_SEL__OFFSET 0x00000016u +#define CYFLD__FLASHPUMP_SEL__SIZE 0x00000001u +#define CYVAL__FLASHPUMP_SEL_GND 0x00000000u +#define CYVAL__FLASHPUMP_SEL_CLK36 0x00000001u +#define CYFLD__EN_FASTBIAS__OFFSET 0x00000017u +#define CYFLD__EN_FASTBIAS__SIZE 0x00000001u +#define CYFLD__TEST_FASTBIAS__OFFSET 0x00000018u +#define CYFLD__TEST_FASTBIAS__SIZE 0x00000001u +#define CYFLD__PUMP_SEL__OFFSET 0x00000019u +#define CYFLD__PUMP_SEL__SIZE 0x00000003u +#define CYVAL__PUMP_SEL_GND 0x00000000u +#define CYVAL__PUMP_SEL_IMO 0x00000001u +#define CYVAL__PUMP_SEL_DBL 0x00000002u +#define CYVAL__PUMP_SEL_CLK36 0x00000003u +#define CYVAL__PUMP_SEL_FF1 0x00000004u +#define CYFLD__TEST_USB_MODE__OFFSET 0x0000001cu +#define CYFLD__TEST_USB_MODE__SIZE 0x00000001u +#define CYFLD__EN_CLK36__OFFSET 0x0000001du +#define CYFLD__EN_CLK36__SIZE 0x00000001u +#define CYFLD__EN_CLK2X__OFFSET 0x0000001eu +#define CYFLD__EN_CLK2X__SIZE 0x00000001u +#define CYREG_CLK_IMO_SPREAD 0x400b010cu +#define CYFLD__SS_VALUE__OFFSET 0x00000000u +#define CYFLD__SS_VALUE__SIZE 0x00000005u +#define CYFLD__SS_MAX__OFFSET 0x00000008u +#define CYFLD__SS_MAX__SIZE 0x00000005u +#define CYFLD__SS_RANGE__OFFSET 0x0000001cu +#define CYFLD__SS_RANGE__SIZE 0x00000002u +#define CYVAL__SS_RANGE_M1 0x00000000u +#define CYVAL__SS_RANGE_M2 0x00000001u +#define CYVAL__SS_RANGE_M4 0x00000002u +#define CYFLD__SS_MODE__OFFSET 0x0000001eu +#define CYFLD__SS_MODE__SIZE 0x00000002u +#define CYVAL__SS_MODE_OFF 0x00000000u +#define CYVAL__SS_MODE_TRIANGLE 0x00000001u +#define CYVAL__SS_MODE_LFSR 0x00000002u +#define CYVAL__SS_MODE_DSI 0x00000003u +#define CYREG_CLK_DFT_SELECT 0x400b0110u +#define CYFLD__DFT_SEL1__OFFSET 0x00000000u +#define CYFLD__DFT_SEL1__SIZE 0x00000004u +#define CYVAL__DFT_SEL1_NC 0x00000000u +#define CYVAL__DFT_SEL1_ILO 0x00000001u +#define CYVAL__DFT_SEL1_WCO 0x00000002u +#define CYVAL__DFT_SEL1_IMO 0x00000003u +#define CYVAL__DFT_SEL1_ECO 0x00000004u +#define CYVAL__DFT_SEL1_PLL 0x00000005u +#define CYVAL__DFT_SEL1_DPLL_OUT 0x00000006u +#define CYVAL__DFT_SEL1_DPLL_REF 0x00000007u +#define CYVAL__DFT_SEL1_DBL 0x00000008u +#define CYVAL__DFT_SEL1_IMO2X 0x00000009u +#define CYVAL__DFT_SEL1_IMO36 0x0000000au +#define CYVAL__DFT_SEL1_HFCLK 0x0000000bu +#define CYVAL__DFT_SEL1_LFCLK 0x0000000cu +#define CYVAL__DFT_SEL1_SYSCLK 0x0000000du +#define CYVAL__DFT_SEL1_EXTCLK 0x0000000eu +#define CYVAL__DFT_SEL1_HALFSYSCLK 0x0000000fu +#define CYFLD__DFT_DIV1__OFFSET 0x00000004u +#define CYFLD__DFT_DIV1__SIZE 0x00000002u +#define CYVAL__DFT_DIV1_NO_DIV 0x00000000u +#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001u +#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002u +#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003u +#define CYFLD__DFT_SEL2__OFFSET 0x00000008u +#define CYFLD__DFT_SEL2__SIZE 0x00000004u +#define CYVAL__DFT_SEL2_NC 0x00000000u +#define CYVAL__DFT_SEL2_ILO 0x00000001u +#define CYVAL__DFT_SEL2_WCO 0x00000002u +#define CYVAL__DFT_SEL2_IMO 0x00000003u +#define CYVAL__DFT_SEL2_ECO 0x00000004u +#define CYVAL__DFT_SEL2_PLL 0x00000005u +#define CYVAL__DFT_SEL2_DPLL_OUT 0x00000006u +#define CYVAL__DFT_SEL2_DPLL_REF 0x00000007u +#define CYVAL__DFT_SEL2_DBL 0x00000008u +#define CYVAL__DFT_SEL2_IMO2X 0x00000009u +#define CYVAL__DFT_SEL2_IMO36 0x0000000au +#define CYVAL__DFT_SEL2_HFCLK 0x0000000bu +#define CYVAL__DFT_SEL2_LFCLK 0x0000000cu +#define CYVAL__DFT_SEL2_SYSCLK 0x0000000du +#define CYVAL__DFT_SEL2_EXTCLK 0x0000000eu +#define CYVAL__DFT_SEL2_HALFSYSCLK 0x0000000fu +#define CYFLD__DFT_DIV2__OFFSET 0x0000000cu +#define CYFLD__DFT_DIV2__SIZE 0x00000002u +#define CYVAL__DFT_DIV2_NO_DIV 0x00000000u +#define CYVAL__DFT_DIV2_DIV_BY_2 0x00000001u +#define CYVAL__DFT_DIV2_DIV_BY_4 0x00000002u +#define CYVAL__DFT_DIV2_DIV_BY_8 0x00000003u +#define CYREG_WDT_CTRLOW 0x400b0200u +#define CYFLD__WDT_CTR0__OFFSET 0x00000000u +#define CYFLD__WDT_CTR0__SIZE 0x00000010u +#define CYFLD__WDT_CTR1__OFFSET 0x00000010u +#define CYFLD__WDT_CTR1__SIZE 0x00000010u +#define CYREG_WDT_CTRHIGH 0x400b0204u +#define CYFLD__WDT_CTR2__OFFSET 0x00000000u +#define CYFLD__WDT_CTR2__SIZE 0x00000020u +#define CYREG_WDT_MATCH 0x400b0208u +#define CYFLD__WDT_MATCH0__OFFSET 0x00000000u +#define CYFLD__WDT_MATCH0__SIZE 0x00000010u +#define CYFLD__WDT_MATCH1__OFFSET 0x00000010u +#define CYFLD__WDT_MATCH1__SIZE 0x00000010u +#define CYREG_WDT_CONFIG 0x400b020cu +#define CYFLD__WDT_MODE0__OFFSET 0x00000000u +#define CYFLD__WDT_MODE0__SIZE 0x00000002u +#define CYVAL__WDT_MODE0_NOTHING 0x00000000u +#define CYVAL__WDT_MODE0_INT 0x00000001u +#define CYVAL__WDT_MODE0_RESET 0x00000002u +#define CYVAL__WDT_MODE0_INT_THEN_RESET 0x00000003u +#define CYFLD__WDT_CLEAR0__OFFSET 0x00000002u +#define CYFLD__WDT_CLEAR0__SIZE 0x00000001u +#define CYFLD__WDT_CASCADE0_1__OFFSET 0x00000003u +#define CYFLD__WDT_CASCADE0_1__SIZE 0x00000001u +#define CYFLD__WDT_MODE1__OFFSET 0x00000008u +#define CYFLD__WDT_MODE1__SIZE 0x00000002u +#define CYVAL__WDT_MODE1_NOTHING 0x00000000u +#define CYVAL__WDT_MODE1_INT 0x00000001u +#define CYVAL__WDT_MODE1_RESET 0x00000002u +#define CYVAL__WDT_MODE1_INT_THEN_RESET 0x00000003u +#define CYFLD__WDT_CLEAR1__OFFSET 0x0000000au +#define CYFLD__WDT_CLEAR1__SIZE 0x00000001u +#define CYFLD__WDT_CASCADE1_2__OFFSET 0x0000000bu +#define CYFLD__WDT_CASCADE1_2__SIZE 0x00000001u +#define CYFLD__WDT_MODE2__OFFSET 0x00000010u +#define CYFLD__WDT_MODE2__SIZE 0x00000001u +#define CYVAL__WDT_MODE2_NOTHING 0x00000000u +#define CYVAL__WDT_MODE2_INT 0x00000001u +#define CYFLD__WDT_BITS2__OFFSET 0x00000018u +#define CYFLD__WDT_BITS2__SIZE 0x00000005u +#define CYFLD__LFCLK_SEL__OFFSET 0x0000001eu +#define CYFLD__LFCLK_SEL__SIZE 0x00000002u +#define CYREG_WDT_CONTROL 0x400b0210u +#define CYFLD__WDT_ENABLE0__OFFSET 0x00000000u +#define CYFLD__WDT_ENABLE0__SIZE 0x00000001u +#define CYFLD__WDT_ENABLED0__OFFSET 0x00000001u +#define CYFLD__WDT_ENABLED0__SIZE 0x00000001u +#define CYFLD__WDT_INT0__OFFSET 0x00000002u +#define CYFLD__WDT_INT0__SIZE 0x00000001u +#define CYFLD__WDT_RESET0__OFFSET 0x00000003u +#define CYFLD__WDT_RESET0__SIZE 0x00000001u +#define CYFLD__WDT_ENABLE1__OFFSET 0x00000008u +#define CYFLD__WDT_ENABLE1__SIZE 0x00000001u +#define CYFLD__WDT_ENABLED1__OFFSET 0x00000009u +#define CYFLD__WDT_ENABLED1__SIZE 0x00000001u +#define CYFLD__WDT_INT1__OFFSET 0x0000000au +#define CYFLD__WDT_INT1__SIZE 0x00000001u +#define CYFLD__WDT_RESET1__OFFSET 0x0000000bu +#define CYFLD__WDT_RESET1__SIZE 0x00000001u +#define CYFLD__WDT_ENABLE2__OFFSET 0x00000010u +#define CYFLD__WDT_ENABLE2__SIZE 0x00000001u +#define CYFLD__WDT_ENABLED2__OFFSET 0x00000011u +#define CYFLD__WDT_ENABLED2__SIZE 0x00000001u +#define CYFLD__WDT_INT2__OFFSET 0x00000012u +#define CYFLD__WDT_INT2__SIZE 0x00000001u +#define CYFLD__WDT_RESET2__OFFSET 0x00000013u +#define CYFLD__WDT_RESET2__SIZE 0x00000001u +#define CYREG_RES_CAUSE 0x400b0300u +#define CYFLD__RESET_WDT__OFFSET 0x00000000u +#define CYFLD__RESET_WDT__SIZE 0x00000001u +#define CYFLD__RESET_DSBOD__OFFSET 0x00000001u +#define CYFLD__RESET_DSBOD__SIZE 0x00000001u +#define CYFLD__RESET_LOCKUP__OFFSET 0x00000002u +#define CYFLD__RESET_LOCKUP__SIZE 0x00000001u +#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003u +#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001u +#define CYFLD__RESET_SOFT__OFFSET 0x00000004u +#define CYFLD__RESET_SOFT__SIZE 0x00000001u +#define CYFLD__RESET_HVBOD__OFFSET 0x00000005u +#define CYFLD__RESET_HVBOD__SIZE 0x00000001u +#define CYFLD__RESET_PBOD__OFFSET 0x00000006u +#define CYFLD__RESET_PBOD__SIZE 0x00000001u +#define CYFLD__RESET_XRES__OFFSET 0x00000007u +#define CYFLD__RESET_XRES__SIZE 0x00000001u +#define CYREG_PWR_PWRSYS_TRIM1 0x400bff00u +#define CYFLD__HIB_BIAS_TRIM__OFFSET 0x00000000u +#define CYFLD__HIB_BIAS_TRIM__SIZE 0x00000003u +#define CYFLD__BOD_TURBO_THRESH__OFFSET 0x00000003u +#define CYFLD__BOD_TURBO_THRESH__SIZE 0x00000001u +#define CYFLD__BOD_TRIM_TRIP__OFFSET 0x00000004u +#define CYFLD__BOD_TRIM_TRIP__SIZE 0x00000004u +#define CYREG_PWR_PWRSYS_TRIM2 0x400bff04u +#define CYFLD__LFCLK_TRIM_LOAD__OFFSET 0x00000000u +#define CYFLD__LFCLK_TRIM_LOAD__SIZE 0x00000002u +#define CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET 0x00000002u +#define CYFLD__LFCLK_TRIM_VOLTAGE__SIZE 0x00000002u +#define CYFLD__DPSLP_TRIM_LOAD__OFFSET 0x00000004u +#define CYFLD__DPSLP_TRIM_LOAD__SIZE 0x00000002u +#define CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET 0x00000006u +#define CYFLD__DPSLP_TRIM_LEAKAGE__SIZE 0x00000001u +#define CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET 0x00000007u +#define CYFLD__DPSLP_TRIM_VOLTAGE__SIZE 0x00000001u +#define CYREG_PWR_PWRSYS_TRIM3 0x400bff08u +#define CYFLD__NWELL_TRIM__OFFSET 0x00000000u +#define CYFLD__NWELL_TRIM__SIZE 0x00000003u +#define CYFLD__QUIET_TRIM__OFFSET 0x00000003u +#define CYFLD__QUIET_TRIM__SIZE 0x00000005u +#define CYREG_PWR_PWRSYS_TRIM4 0x400bff0cu +#define CYFLD__HIB_TRIM_NWELL__OFFSET 0x00000000u +#define CYFLD__HIB_TRIM_NWELL__SIZE 0x00000002u +#define CYFLD__HIB_TRIM_LEAKAGE__OFFSET 0x00000002u +#define CYFLD__HIB_TRIM_LEAKAGE__SIZE 0x00000001u +#define CYFLD__HIB_TRIM_VOLTAGE__OFFSET 0x00000003u +#define CYFLD__HIB_TRIM_VOLTAGE__SIZE 0x00000001u +#define CYFLD__HIB_TRIM_REFERENCE__OFFSET 0x00000004u +#define CYFLD__HIB_TRIM_REFERENCE__SIZE 0x00000002u +#define CYREG_PWR_BG_TRIM1 0x400bff10u +#define CYFLD__INL_TRIM_MAIN__OFFSET 0x00000000u +#define CYFLD__INL_TRIM_MAIN__SIZE 0x00000003u +#define CYFLD__INL_CROSS_MAIN__OFFSET 0x00000003u +#define CYFLD__INL_CROSS_MAIN__SIZE 0x00000004u +#define CYREG_PWR_BG_TRIM2 0x400bff14u +#define CYFLD__VCTAT_SLOPE__OFFSET 0x00000000u +#define CYFLD__VCTAT_SLOPE__SIZE 0x00000004u +#define CYFLD__VCTAT_VOLTAGE__OFFSET 0x00000004u +#define CYFLD__VCTAT_VOLTAGE__SIZE 0x00000002u +#define CYFLD__VCTAT_ENABLE__OFFSET 0x00000006u +#define CYFLD__VCTAT_ENABLE__SIZE 0x00000001u +#define CYFLD__VCTAT_VOLTAGE_MSB__OFFSET 0x00000007u +#define CYFLD__VCTAT_VOLTAGE_MSB__SIZE 0x00000001u +#define CYREG_PWR_BG_TRIM3 0x400bff18u +#define CYFLD__INL_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD__INL_TRIM_IMO__SIZE 0x00000003u +#define CYFLD__INL_CROSS_IMO__OFFSET 0x00000003u +#define CYFLD__INL_CROSS_IMO__SIZE 0x00000004u +#define CYREG_PWR_BG_TRIM4 0x400bff1cu +#define CYFLD__ABS_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD__ABS_TRIM_IMO__SIZE 0x00000006u +#define CYREG_PWR_BG_TRIM5 0x400bff20u +#define CYFLD__TMPCO_TRIM_IMO__OFFSET 0x00000000u +#define CYFLD__TMPCO_TRIM_IMO__SIZE 0x00000006u +#define CYREG_CLK_ILO_TRIM 0x400bff24u +#define CYFLD__TRIM__OFFSET 0x00000000u +#define CYFLD__TRIM__SIZE 0x00000004u +#define CYFLD__COARSE_TRIM__OFFSET 0x00000004u +#define CYFLD__COARSE_TRIM__SIZE 0x00000004u +#define CYREG_CLK_IMO_TRIM1 0x400bff28u +#define CYFLD__OFFSET__OFFSET 0x00000000u +#define CYFLD__OFFSET__SIZE 0x00000008u +#define CYREG_CLK_IMO_TRIM2 0x400bff2cu +#define CYFLD__FREQ__OFFSET 0x00000000u +#define CYFLD__FREQ__SIZE 0x00000006u +#define CYREG_CLK_IMO_TRIM3 0x400bff30u +#define CYFLD__TRIM_CLK36__OFFSET 0x00000000u +#define CYFLD__TRIM_CLK36__SIZE 0x00000004u +#define CYREG_CLK_IMO_TRIM4 0x400bff34u +#define CYFLD__GAIN__OFFSET 0x00000000u +#define CYFLD__GAIN__SIZE 0x00000005u +#define CYFLD__FSOFFSET__OFFSET 0x00000005u +#define CYFLD__FSOFFSET__SIZE 0x00000003u +#define CYREG_PWR_RSVD_TRIM 0x400bff38u +#define CYFLD__RSVD_TRIM__OFFSET 0x00000000u +#define CYFLD__RSVD_TRIM__SIZE 0x00000004u +#define CYDEV_SPCIF_BASE 0x400e0000u +#define CYDEV_SPCIF_SIZE 0x00010000u +#define CYREG_SPCIF_GEOMETRY 0x400e0000u +#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000u +#define CYFLD_SPCIF_FLASH__SIZE 0x00000010u +#define CYFLD_SPCIF_SFLASH__OFFSET 0x00000010u +#define CYFLD_SPCIF_SFLASH__SIZE 0x00000004u +#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014u +#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002u +#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016u +#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002u +#define CYFLD_SPCIF_NVL__OFFSET 0x00000018u +#define CYFLD_SPCIF_NVL__SIZE 0x00000007u +#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001fu +#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001u +#define CYREG_SPCIF_NVL_WR_DATA 0x400e001cu +#define CYFLD_SPCIF_DATA__OFFSET 0x00000000u +#define CYFLD_SPCIF_DATA__SIZE 0x00000008u +#define CYDEV_UDB_BASE 0x400f0000u +#define CYDEV_UDB_SIZE 0x00010000u +#define CYDEV_UDB_W8_BASE 0x400f0000u +#define CYDEV_UDB_W8_SIZE 0x00001000u +#define CYREG_UDB_W8_A0_00 0x400f0000u +#define CYFLD_UDB_W8_A0__OFFSET 0x00000000u +#define CYFLD_UDB_W8_A0__SIZE 0x00000008u +#define CYREG_UDB_W8_A0_01 0x400f0001u +#define CYREG_UDB_W8_A0_02 0x400f0002u +#define CYREG_UDB_W8_A0_03 0x400f0003u +#define CYREG_UDB_W8_A1_00 0x400f0010u +#define CYFLD_UDB_W8_A1__OFFSET 0x00000000u +#define CYFLD_UDB_W8_A1__SIZE 0x00000008u +#define CYREG_UDB_W8_A1_01 0x400f0011u +#define CYREG_UDB_W8_A1_02 0x400f0012u +#define CYREG_UDB_W8_A1_03 0x400f0013u +#define CYREG_UDB_W8_D0_00 0x400f0020u +#define CYFLD_UDB_W8_D0__OFFSET 0x00000000u +#define CYFLD_UDB_W8_D0__SIZE 0x00000008u +#define CYREG_UDB_W8_D0_01 0x400f0021u +#define CYREG_UDB_W8_D0_02 0x400f0022u +#define CYREG_UDB_W8_D0_03 0x400f0023u +#define CYREG_UDB_W8_D1_00 0x400f0030u +#define CYFLD_UDB_W8_D1__OFFSET 0x00000000u +#define CYFLD_UDB_W8_D1__SIZE 0x00000008u +#define CYREG_UDB_W8_D1_01 0x400f0031u +#define CYREG_UDB_W8_D1_02 0x400f0032u +#define CYREG_UDB_W8_D1_03 0x400f0033u +#define CYREG_UDB_W8_F0_00 0x400f0040u +#define CYFLD_UDB_W8_F0__OFFSET 0x00000000u +#define CYFLD_UDB_W8_F0__SIZE 0x00000008u +#define CYREG_UDB_W8_F0_01 0x400f0041u +#define CYREG_UDB_W8_F0_02 0x400f0042u +#define CYREG_UDB_W8_F0_03 0x400f0043u +#define CYREG_UDB_W8_F1_00 0x400f0050u +#define CYFLD_UDB_W8_F1__OFFSET 0x00000000u +#define CYFLD_UDB_W8_F1__SIZE 0x00000008u +#define CYREG_UDB_W8_F1_01 0x400f0051u +#define CYREG_UDB_W8_F1_02 0x400f0052u +#define CYREG_UDB_W8_F1_03 0x400f0053u +#define CYREG_UDB_W8_ST_00 0x400f0060u +#define CYFLD_UDB_W8_ST__OFFSET 0x00000000u +#define CYFLD_UDB_W8_ST__SIZE 0x00000008u +#define CYREG_UDB_W8_ST_01 0x400f0061u +#define CYREG_UDB_W8_ST_02 0x400f0062u +#define CYREG_UDB_W8_ST_03 0x400f0063u +#define CYREG_UDB_W8_CTL_00 0x400f0070u +#define CYFLD_UDB_W8_CTL__OFFSET 0x00000000u +#define CYFLD_UDB_W8_CTL__SIZE 0x00000008u +#define CYREG_UDB_W8_CTL_01 0x400f0071u +#define CYREG_UDB_W8_CTL_02 0x400f0072u +#define CYREG_UDB_W8_CTL_03 0x400f0073u +#define CYREG_UDB_W8_MSK_00 0x400f0080u +#define CYFLD_UDB_W8_MSK__OFFSET 0x00000000u +#define CYFLD_UDB_W8_MSK__SIZE 0x00000007u +#define CYREG_UDB_W8_MSK_01 0x400f0081u +#define CYREG_UDB_W8_MSK_02 0x400f0082u +#define CYREG_UDB_W8_MSK_03 0x400f0083u +#define CYREG_UDB_W8_ACTL_00 0x400f0090u +#define CYFLD_UDB_W8_FIFO0_CLR__OFFSET 0x00000000u +#define CYFLD_UDB_W8_FIFO0_CLR__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO0_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO0_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_W8_FIFO1_CLR__OFFSET 0x00000001u +#define CYFLD_UDB_W8_FIFO1_CLR__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO1_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO1_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_W8_FIFO0_LVL__OFFSET 0x00000002u +#define CYFLD_UDB_W8_FIFO0_LVL__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO0_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO0_LVL_MID 0x00000001u +#define CYFLD_UDB_W8_FIFO1_LVL__OFFSET 0x00000003u +#define CYFLD_UDB_W8_FIFO1_LVL__SIZE 0x00000001u +#define CYVAL_UDB_W8_FIFO1_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_W8_FIFO1_LVL_MID 0x00000001u +#define CYFLD_UDB_W8_INT_EN__OFFSET 0x00000004u +#define CYFLD_UDB_W8_INT_EN__SIZE 0x00000001u +#define CYVAL_UDB_W8_INT_EN_DISABLE 0x00000000u +#define CYVAL_UDB_W8_INT_EN_ENABLE 0x00000001u +#define CYFLD_UDB_W8_CNT_START__OFFSET 0x00000005u +#define CYFLD_UDB_W8_CNT_START__SIZE 0x00000001u +#define CYVAL_UDB_W8_CNT_START_DISABLE 0x00000000u +#define CYVAL_UDB_W8_CNT_START_ENABLE 0x00000001u +#define CYREG_UDB_W8_ACTL_01 0x400f0091u +#define CYREG_UDB_W8_ACTL_02 0x400f0092u +#define CYREG_UDB_W8_ACTL_03 0x400f0093u +#define CYREG_UDB_W8_MC_00 0x400f00a0u +#define CYFLD_UDB_W8_PLD0_MC__OFFSET 0x00000000u +#define CYFLD_UDB_W8_PLD0_MC__SIZE 0x00000004u +#define CYFLD_UDB_W8_PLD1_MC__OFFSET 0x00000004u +#define CYFLD_UDB_W8_PLD1_MC__SIZE 0x00000004u +#define CYREG_UDB_W8_MC_01 0x400f00a1u +#define CYREG_UDB_W8_MC_02 0x400f00a2u +#define CYREG_UDB_W8_MC_03 0x400f00a3u +#define CYDEV_UDB_CAT16_BASE 0x400f1000u +#define CYDEV_UDB_CAT16_SIZE 0x00001000u +#define CYREG_UDB_CAT16_A_00 0x400f1000u +#define CYFLD_UDB_CAT16_A0__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_A0__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_A1__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_A1__SIZE 0x00000008u +#define CYREG_UDB_CAT16_A_01 0x400f1002u +#define CYREG_UDB_CAT16_A_02 0x400f1004u +#define CYREG_UDB_CAT16_A_03 0x400f1006u +#define CYREG_UDB_CAT16_D_00 0x400f1040u +#define CYFLD_UDB_CAT16_D0__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_D0__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_D1__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_D1__SIZE 0x00000008u +#define CYREG_UDB_CAT16_D_01 0x400f1042u +#define CYREG_UDB_CAT16_D_02 0x400f1044u +#define CYREG_UDB_CAT16_D_03 0x400f1046u +#define CYREG_UDB_CAT16_F_00 0x400f1080u +#define CYFLD_UDB_CAT16_F0__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_F0__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_F1__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_F1__SIZE 0x00000008u +#define CYREG_UDB_CAT16_F_01 0x400f1082u +#define CYREG_UDB_CAT16_F_02 0x400f1084u +#define CYREG_UDB_CAT16_F_03 0x400f1086u +#define CYREG_UDB_CAT16_CTL_ST_00 0x400f10c0u +#define CYFLD_UDB_CAT16_ST__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_ST__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_CTL__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_CTL__SIZE 0x00000008u +#define CYREG_UDB_CAT16_CTL_ST_01 0x400f10c2u +#define CYREG_UDB_CAT16_CTL_ST_02 0x400f10c4u +#define CYREG_UDB_CAT16_CTL_ST_03 0x400f10c6u +#define CYREG_UDB_CAT16_ACTL_MSK_00 0x400f1100u +#define CYFLD_UDB_CAT16_MSK__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_MSK__SIZE 0x00000008u +#define CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET 0x00000008u +#define CYFLD_UDB_CAT16_FIFO0_CLR__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET 0x00000009u +#define CYFLD_UDB_CAT16_FIFO1_CLR__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR 0x00000001u +#define CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET 0x0000000au +#define CYFLD_UDB_CAT16_FIFO0_LVL__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO0_LVL_MID 0x00000001u +#define CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET 0x0000000bu +#define CYFLD_UDB_CAT16_FIFO1_LVL__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL 0x00000000u +#define CYVAL_UDB_CAT16_FIFO1_LVL_MID 0x00000001u +#define CYFLD_UDB_CAT16_INT_EN__OFFSET 0x0000000cu +#define CYFLD_UDB_CAT16_INT_EN__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_INT_EN_DISABLE 0x00000000u +#define CYVAL_UDB_CAT16_INT_EN_ENABLE 0x00000001u +#define CYFLD_UDB_CAT16_CNT_START__OFFSET 0x0000000du +#define CYFLD_UDB_CAT16_CNT_START__SIZE 0x00000001u +#define CYVAL_UDB_CAT16_CNT_START_DISABLE 0x00000000u +#define CYVAL_UDB_CAT16_CNT_START_ENABLE 0x00000001u +#define CYREG_UDB_CAT16_ACTL_MSK_01 0x400f1102u +#define CYREG_UDB_CAT16_ACTL_MSK_02 0x400f1104u +#define CYREG_UDB_CAT16_ACTL_MSK_03 0x400f1106u +#define CYREG_UDB_CAT16_MC_00 0x400f1140u +#define CYFLD_UDB_CAT16_PLD0_MC__OFFSET 0x00000000u +#define CYFLD_UDB_CAT16_PLD0_MC__SIZE 0x00000004u +#define CYFLD_UDB_CAT16_PLD1_MC__OFFSET 0x00000004u +#define CYFLD_UDB_CAT16_PLD1_MC__SIZE 0x00000004u +#define CYREG_UDB_CAT16_MC_01 0x400f1142u +#define CYREG_UDB_CAT16_MC_02 0x400f1144u +#define CYREG_UDB_CAT16_MC_03 0x400f1146u +#define CYDEV_UDB_W16_BASE 0x400f1000u +#define CYDEV_UDB_W16_SIZE 0x00001000u +#define CYREG_UDB_W16_A0_00 0x400f1000u +#define CYFLD_UDB_W16_A0_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_A0_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_A0_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_A0_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_A0_01 0x400f1002u +#define CYREG_UDB_W16_A0_02 0x400f1004u +#define CYREG_UDB_W16_A1_00 0x400f1020u +#define CYFLD_UDB_W16_A1_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_A1_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_A1_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_A1_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_A1_01 0x400f1022u +#define CYREG_UDB_W16_A1_02 0x400f1024u +#define CYREG_UDB_W16_D0_00 0x400f1040u +#define CYFLD_UDB_W16_D0_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_D0_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_D0_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_D0_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_D0_01 0x400f1042u +#define CYREG_UDB_W16_D0_02 0x400f1044u +#define CYREG_UDB_W16_D1_00 0x400f1060u +#define CYFLD_UDB_W16_D1_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_D1_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_D1_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_D1_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_D1_01 0x400f1062u +#define CYREG_UDB_W16_D1_02 0x400f1064u +#define CYREG_UDB_W16_F0_00 0x400f1080u +#define CYFLD_UDB_W16_F0_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_F0_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_F0_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_F0_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_F0_01 0x400f1082u +#define CYREG_UDB_W16_F0_02 0x400f1084u +#define CYREG_UDB_W16_F1_00 0x400f10a0u +#define CYFLD_UDB_W16_F1_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_F1_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_F1_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_F1_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_F1_01 0x400f10a2u +#define CYREG_UDB_W16_F1_02 0x400f10a4u +#define CYREG_UDB_W16_ST_00 0x400f10c0u +#define CYFLD_UDB_W16_ST_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_ST_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_ST_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_ST_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_ST_01 0x400f10c2u +#define CYREG_UDB_W16_ST_02 0x400f10c4u +#define CYREG_UDB_W16_CTL_00 0x400f10e0u +#define CYFLD_UDB_W16_CTL_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_CTL_LS__SIZE 0x00000008u +#define CYFLD_UDB_W16_CTL_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_CTL_MS__SIZE 0x00000008u +#define CYREG_UDB_W16_CTL_01 0x400f10e2u +#define CYREG_UDB_W16_CTL_02 0x400f10e4u +#define CYREG_UDB_W16_MSK_00 0x400f1100u +#define CYFLD_UDB_W16_MSK_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_MSK_LS__SIZE 0x00000007u +#define CYFLD_UDB_W16_MSK_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_MSK_MS__SIZE 0x00000007u +#define CYREG_UDB_W16_MSK_01 0x400f1102u +#define CYREG_UDB_W16_MSK_02 0x400f1104u +#define CYREG_UDB_W16_ACTL_00 0x400f1120u +#define CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET 0x00000001u +#define CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET 0x00000002u +#define CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_LVL_LS_MID 0x00000001u +#define CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET 0x00000003u +#define CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_LVL_LS_MID 0x00000001u +#define CYFLD_UDB_W16_INT_EN_LS__OFFSET 0x00000004u +#define CYFLD_UDB_W16_INT_EN_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_INT_EN_LS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_INT_EN_LS_ENABLE 0x00000001u +#define CYFLD_UDB_W16_CNT_START_LS__OFFSET 0x00000005u +#define CYFLD_UDB_W16_CNT_START_LS__SIZE 0x00000001u +#define CYVAL_UDB_W16_CNT_START_LS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_CNT_START_LS_ENABLE 0x00000001u +#define CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET 0x00000009u +#define CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR 0x00000001u +#define CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET 0x0000000au +#define CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO0_LVL_MS_MID 0x00000001u +#define CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET 0x0000000bu +#define CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL 0x00000000u +#define CYVAL_UDB_W16_FIFO1_LVL_MS_MID 0x00000001u +#define CYFLD_UDB_W16_INT_EN_MS__OFFSET 0x0000000cu +#define CYFLD_UDB_W16_INT_EN_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_INT_EN_MS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_INT_EN_MS_ENABLE 0x00000001u +#define CYFLD_UDB_W16_CNT_START_MS__OFFSET 0x0000000du +#define CYFLD_UDB_W16_CNT_START_MS__SIZE 0x00000001u +#define CYVAL_UDB_W16_CNT_START_MS_DISABLE 0x00000000u +#define CYVAL_UDB_W16_CNT_START_MS_ENABLE 0x00000001u +#define CYREG_UDB_W16_ACTL_01 0x400f1122u +#define CYREG_UDB_W16_ACTL_02 0x400f1124u +#define CYREG_UDB_W16_MC_00 0x400f1140u +#define CYFLD_UDB_W16_PLD0_MC_LS__OFFSET 0x00000000u +#define CYFLD_UDB_W16_PLD0_MC_LS__SIZE 0x00000004u +#define CYFLD_UDB_W16_PLD1_MC_LS__OFFSET 0x00000004u +#define CYFLD_UDB_W16_PLD1_MC_LS__SIZE 0x00000004u +#define CYFLD_UDB_W16_PLD0_MC_MS__OFFSET 0x00000008u +#define CYFLD_UDB_W16_PLD0_MC_MS__SIZE 0x00000004u +#define CYFLD_UDB_W16_PLD1_MC_MS__OFFSET 0x0000000cu +#define CYFLD_UDB_W16_PLD1_MC_MS__SIZE 0x00000004u +#define CYREG_UDB_W16_MC_01 0x400f1142u +#define CYREG_UDB_W16_MC_02 0x400f1144u +#define CYDEV_UDB_W32_BASE 0x400f2000u +#define CYDEV_UDB_W32_SIZE 0x00001000u +#define CYREG_UDB_W32_A0_00 0x400f2000u +#define CYFLD_UDB_W32_A0_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_A0_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_A0_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_A0_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_A0_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_A0_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_A0_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_A0_3__SIZE 0x00000008u +#define CYREG_UDB_W32_A1_00 0x400f2040u +#define CYFLD_UDB_W32_A1_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_A1_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_A1_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_A1_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_A1_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_A1_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_A1_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_A1_3__SIZE 0x00000008u +#define CYREG_UDB_W32_D0_00 0x400f2080u +#define CYFLD_UDB_W32_D0_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_D0_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_D0_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_D0_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_D0_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_D0_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_D0_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_D0_3__SIZE 0x00000008u +#define CYREG_UDB_W32_D1_00 0x400f20c0u +#define CYFLD_UDB_W32_D1_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_D1_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_D1_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_D1_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_D1_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_D1_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_D1_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_D1_3__SIZE 0x00000008u +#define CYREG_UDB_W32_F0_00 0x400f2100u +#define CYFLD_UDB_W32_F0_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_F0_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_F0_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_F0_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_F0_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_F0_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_F0_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_F0_3__SIZE 0x00000008u +#define CYREG_UDB_W32_F1_00 0x400f2140u +#define CYFLD_UDB_W32_F1_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_F1_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_F1_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_F1_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_F1_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_F1_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_F1_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_F1_3__SIZE 0x00000008u +#define CYREG_UDB_W32_ST_00 0x400f2180u +#define CYFLD_UDB_W32_ST_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_ST_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_ST_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_ST_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_ST_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_ST_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_ST_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_ST_3__SIZE 0x00000008u +#define CYREG_UDB_W32_CTL_00 0x400f21c0u +#define CYFLD_UDB_W32_CTL_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_CTL_0__SIZE 0x00000008u +#define CYFLD_UDB_W32_CTL_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_CTL_1__SIZE 0x00000008u +#define CYFLD_UDB_W32_CTL_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_CTL_2__SIZE 0x00000008u +#define CYFLD_UDB_W32_CTL_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_CTL_3__SIZE 0x00000008u +#define CYREG_UDB_W32_MSK_00 0x400f2200u +#define CYFLD_UDB_W32_MSK_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_MSK_0__SIZE 0x00000007u +#define CYFLD_UDB_W32_MSK_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_MSK_1__SIZE 0x00000007u +#define CYFLD_UDB_W32_MSK_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_MSK_2__SIZE 0x00000007u +#define CYFLD_UDB_W32_MSK_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_MSK_3__SIZE 0x00000007u +#define CYREG_UDB_W32_ACTL_00 0x400f2240u +#define CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_FIFO0_CLR_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET 0x00000002u +#define CYFLD_UDB_W32_FIFO0_LVL_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_0_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET 0x00000003u +#define CYFLD_UDB_W32_FIFO1_LVL_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_0_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_0__OFFSET 0x00000004u +#define CYFLD_UDB_W32_INT_EN_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_0_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_0_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_0__OFFSET 0x00000005u +#define CYFLD_UDB_W32_CNT_START_0__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_0_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_0_ENABLE 0x00000001u +#define CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_FIFO0_CLR_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET 0x00000009u +#define CYFLD_UDB_W32_FIFO1_CLR_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET 0x0000000au +#define CYFLD_UDB_W32_FIFO0_LVL_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_1_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET 0x0000000bu +#define CYFLD_UDB_W32_FIFO1_LVL_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_1_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_1__OFFSET 0x0000000cu +#define CYFLD_UDB_W32_INT_EN_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_1_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_1_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_1__OFFSET 0x0000000du +#define CYFLD_UDB_W32_CNT_START_1__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_1_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_1_ENABLE 0x00000001u +#define CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_FIFO0_CLR_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET 0x00000011u +#define CYFLD_UDB_W32_FIFO1_CLR_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET 0x00000012u +#define CYFLD_UDB_W32_FIFO0_LVL_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_2_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET 0x00000013u +#define CYFLD_UDB_W32_FIFO1_LVL_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_2_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_2__OFFSET 0x00000014u +#define CYFLD_UDB_W32_INT_EN_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_2_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_2_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_2__OFFSET 0x00000015u +#define CYFLD_UDB_W32_CNT_START_2__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_2_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_2_ENABLE 0x00000001u +#define CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_FIFO0_CLR_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET 0x00000019u +#define CYFLD_UDB_W32_FIFO1_CLR_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR 0x00000001u +#define CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET 0x0000001au +#define CYFLD_UDB_W32_FIFO0_LVL_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO0_LVL_3_MID 0x00000001u +#define CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET 0x0000001bu +#define CYFLD_UDB_W32_FIFO1_LVL_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL 0x00000000u +#define CYVAL_UDB_W32_FIFO1_LVL_3_MID 0x00000001u +#define CYFLD_UDB_W32_INT_EN_3__OFFSET 0x0000001cu +#define CYFLD_UDB_W32_INT_EN_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_INT_EN_3_DISABLE 0x00000000u +#define CYVAL_UDB_W32_INT_EN_3_ENABLE 0x00000001u +#define CYFLD_UDB_W32_CNT_START_3__OFFSET 0x0000001du +#define CYFLD_UDB_W32_CNT_START_3__SIZE 0x00000001u +#define CYVAL_UDB_W32_CNT_START_3_DISABLE 0x00000000u +#define CYVAL_UDB_W32_CNT_START_3_ENABLE 0x00000001u +#define CYREG_UDB_W32_MC_00 0x400f2280u +#define CYFLD_UDB_W32_PLD0_MC_0__OFFSET 0x00000000u +#define CYFLD_UDB_W32_PLD0_MC_0__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_0__OFFSET 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_0__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD0_MC_1__OFFSET 0x00000008u +#define CYFLD_UDB_W32_PLD0_MC_1__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_1__OFFSET 0x0000000cu +#define CYFLD_UDB_W32_PLD1_MC_1__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD0_MC_2__OFFSET 0x00000010u +#define CYFLD_UDB_W32_PLD0_MC_2__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_2__OFFSET 0x00000014u +#define CYFLD_UDB_W32_PLD1_MC_2__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD0_MC_3__OFFSET 0x00000018u +#define CYFLD_UDB_W32_PLD0_MC_3__SIZE 0x00000004u +#define CYFLD_UDB_W32_PLD1_MC_3__OFFSET 0x0000001cu +#define CYFLD_UDB_W32_PLD1_MC_3__SIZE 0x00000004u +#define CYDEV_UDB_P0_BASE 0x400f3000u +#define CYDEV_UDB_P0_SIZE 0x00000200u +#define CYDEV_UDB_P0_U0_BASE 0x400f3000u +#define CYDEV_UDB_P0_U0_SIZE 0x00000080u +#define CYREG_UDB_P0_U0_PLD_IT0 0x400f3000u +#define CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET 0x00000010u +#define CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET 0x00000011u +#define CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET 0x00000012u +#define CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET 0x00000013u +#define CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET 0x00000014u +#define CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET 0x00000015u +#define CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET 0x00000016u +#define CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET 0x00000017u +#define CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET 0x00000018u +#define CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET 0x00000019u +#define CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET 0x0000001au +#define CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET 0x0000001bu +#define CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET 0x0000001cu +#define CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET 0x0000001du +#define CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET 0x0000001eu +#define CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET 0x0000001fu +#define CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_PLD_IT1 0x400f3004u +#define CYREG_UDB_P0_U0_PLD_IT2 0x400f3008u +#define CYREG_UDB_P0_U0_PLD_IT3 0x400f300cu +#define CYREG_UDB_P0_U0_PLD_IT4 0x400f3010u +#define CYREG_UDB_P0_U0_PLD_IT5 0x400f3014u +#define CYREG_UDB_P0_U0_PLD_IT6 0x400f3018u +#define CYREG_UDB_P0_U0_PLD_IT7 0x400f301cu +#define CYREG_UDB_P0_U0_PLD_IT8 0x400f3020u +#define CYREG_UDB_P0_U0_PLD_IT9 0x400f3024u +#define CYREG_UDB_P0_U0_PLD_IT10 0x400f3028u +#define CYREG_UDB_P0_U0_PLD_IT11 0x400f302cu +#define CYREG_UDB_P0_U0_PLD_ORT0 0x400f3030u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_PLD_ORT1 0x400f3032u +#define CYREG_UDB_P0_U0_PLD_ORT2 0x400f3034u +#define CYREG_UDB_P0_U0_PLD_ORT3 0x400f3036u +#define CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST 0x400f3038u +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED 0x00000001u +#define CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB 0x400f303au +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L 0x00000003u +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H 0x00000002u +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L 0x00000003u +#define CYREG_UDB_P0_U0_PLD_MC_SET_RESET 0x400f303cu +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS 0x400f303eu +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_NC1__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC3__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_NC3__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC5__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_NC5__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC7__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_NC7__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC9__OFFSET 0x00000009u +#define CYFLD_UDB_P_U_NC9__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC11__OFFSET 0x0000000bu +#define CYFLD_UDB_P_U_NC11__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC13__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_NC13__SIZE 0x00000001u +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET 0x0000000eu +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER 0x00000000u +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC15__OFFSET 0x0000000fu +#define CYFLD_UDB_P_U_NC15__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG0 0x400f3040u +#define CYFLD_UDB_P_U_RAD0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RAD0__SIZE 0x00000003u +#define CYVAL_UDB_P_U_RAD0_OFF 0x00000000u +#define CYVAL_UDB_P_U_RAD0_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_RAD0_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_RAD0_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_RAD0_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_RAD0_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_RAD0_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_RAD0_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_RAD1__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_RAD1__SIZE 0x00000003u +#define CYVAL_UDB_P_U_RAD1_OFF 0x00000000u +#define CYVAL_UDB_P_U_RAD1_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_RAD1_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_RAD1_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_RAD1_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_RAD1_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_RAD1_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_RAD1_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG1 0x400f3041u +#define CYFLD_UDB_P_U_RAD2__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RAD2__SIZE 0x00000003u +#define CYVAL_UDB_P_U_RAD2_OFF 0x00000000u +#define CYVAL_UDB_P_U_RAD2_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_RAD2_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_RAD2_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_RAD2_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_RAD2_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_RAD2_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_RAD2_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS 0x00000001u +#define CYREG_UDB_P0_U0_CFG2 0x400f3042u +#define CYFLD_UDB_P_U_F0_LD__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_F0_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_F0_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_F0_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_F0_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_F0_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_F0_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_F0_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_F0_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_F0_LD_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE 0x00000000u +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS 0x00000001u +#define CYFLD_UDB_P_U_F1_LD__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_F1_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_F1_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_F1_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_F1_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_F1_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_F1_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_F1_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_F1_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_F1_LD_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG3 0x400f3043u +#define CYFLD_UDB_P_U_D0_LD__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_D0_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_D0_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_D0_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_D0_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_D0_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_D0_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_D0_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_D0_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_D0_LD_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_D1_LD__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_D1_LD__SIZE 0x00000003u +#define CYVAL_UDB_P_U_D1_LD_OFF 0x00000000u +#define CYVAL_UDB_P_U_D1_LD_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_D1_LD_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_D1_LD_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_D1_LD_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_D1_LD_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_D1_LD_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_D1_LD_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG4 0x400f3044u +#define CYFLD_UDB_P_U_SI_MUX__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_SI_MUX__SIZE 0x00000003u +#define CYVAL_UDB_P_U_SI_MUX_OFF 0x00000000u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_SI_MUX_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_SI_MUX_RESERVED 0x00000007u +#define CYFLD_UDB_P_U_CI_MUX__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_CI_MUX__SIZE 0x00000003u +#define CYVAL_UDB_P_U_CI_MUX_OFF 0x00000000u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN0 0x00000001u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN1 0x00000002u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN2 0x00000003u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN3 0x00000004u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN4 0x00000005u +#define CYVAL_UDB_P_U_CI_MUX_DP_IN5 0x00000006u +#define CYVAL_UDB_P_U_CI_MUX_RESERVED 0x00000007u +#define CYREG_UDB_P0_U0_CFG5 0x400f3045u +#define CYFLD_UDB_P_U_OUT0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT0__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT0_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT0_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT0_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT0_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT0_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT0_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT0_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT0_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT0_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT0_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT0_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT0_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT0_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT0_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT0_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT0_F1_BUS_STAT 0x0000000fu +#define CYFLD_UDB_P_U_OUT1__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_OUT1__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT1_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT1_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT1_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT1_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT1_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT1_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT1_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT1_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT1_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT1_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT1_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT1_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT1_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT1_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT1_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT1_F1_BUS_STAT 0x0000000fu +#define CYREG_UDB_P0_U0_CFG6 0x400f3046u +#define CYFLD_UDB_P_U_OUT2__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT2__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT2_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT2_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT2_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT2_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT2_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT2_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT2_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT2_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT2_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT2_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT2_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT2_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT2_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT2_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT2_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT2_F1_BUS_STAT 0x0000000fu +#define CYFLD_UDB_P_U_OUT3__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_OUT3__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT3_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT3_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT3_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT3_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT3_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT3_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT3_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT3_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT3_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT3_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT3_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT3_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT3_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT3_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT3_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT3_F1_BUS_STAT 0x0000000fu +#define CYREG_UDB_P0_U0_CFG7 0x400f3047u +#define CYFLD_UDB_P_U_OUT4__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT4__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT4_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT4_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT4_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT4_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT4_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT4_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT4_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT4_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT4_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT4_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT4_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT4_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT4_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT4_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT4_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT4_F1_BUS_STAT 0x0000000fu +#define CYFLD_UDB_P_U_OUT5__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_OUT5__SIZE 0x00000004u +#define CYVAL_UDB_P_U_OUT5_CE0 0x00000000u +#define CYVAL_UDB_P_U_OUT5_CL0 0x00000001u +#define CYVAL_UDB_P_U_OUT5_Z0 0x00000002u +#define CYVAL_UDB_P_U_OUT5_FF0 0x00000003u +#define CYVAL_UDB_P_U_OUT5_CE1 0x00000004u +#define CYVAL_UDB_P_U_OUT5_CL1 0x00000005u +#define CYVAL_UDB_P_U_OUT5_Z1 0x00000006u +#define CYVAL_UDB_P_U_OUT5_FF1 0x00000007u +#define CYVAL_UDB_P_U_OUT5_OV_MSB 0x00000008u +#define CYVAL_UDB_P_U_OUT5_CO_MSB 0x00000009u +#define CYVAL_UDB_P_U_OUT5_CMSBO 0x0000000au +#define CYVAL_UDB_P_U_OUT5_SO 0x0000000bu +#define CYVAL_UDB_P_U_OUT5_F0_BLK_STAT 0x0000000cu +#define CYVAL_UDB_P_U_OUT5_F1_BLK_STAT 0x0000000du +#define CYVAL_UDB_P_U_OUT5_F0_BUS_STAT 0x0000000eu +#define CYVAL_UDB_P_U_OUT5_F1_BUS_STAT 0x0000000fu +#define CYREG_UDB_P0_U0_CFG8 0x400f3048u +#define CYFLD_UDB_P_U_OUT_SYNC__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_OUT_SYNC__SIZE 0x00000006u +#define CYVAL_UDB_P_U_OUT_SYNC_REGISTERED 0x00000000u +#define CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL 0x00000001u +#define CYFLD_UDB_P_U_NC6__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_NC6__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG9 0x400f3049u +#define CYFLD_UDB_P_U_AMASK__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_AMASK__SIZE 0x00000008u +#define CYREG_UDB_P0_U0_CFG10 0x400f304au +#define CYFLD_UDB_P_U_CMASK0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CMASK0__SIZE 0x00000008u +#define CYREG_UDB_P0_U0_CFG11 0x400f304bu +#define CYREG_UDB_P0_U0_CFG12 0x400f304cu +#define CYFLD_UDB_P_U_SI_SELA__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_SI_SELA__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELA_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_SI_SELA_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_SI_SELA_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELA_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_SI_SELB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_SI_SELB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELB_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_SI_SELB_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_SI_SELB_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_SI_SELB_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_DEF_SI__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_DEF_SI__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 0x00000000u +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 0x00000001u +#define CYFLD_UDB_P_U_AMASK_EN__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_AMASK_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_AMASK_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_AMASK_EN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CMASK0_EN__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_CMASK0_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CMASK0_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CMASK0_EN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CMASK1_EN__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_CMASK1_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CMASK1_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CMASK1_EN_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_CFG13 0x400f304du +#define CYFLD_UDB_P_U_CI_SELA__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CI_SELA__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELA_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_CI_SELA_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_CI_SELA_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELA_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_CI_SELB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CI_SELB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELB_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_CI_SELB_REGISTERED 0x00000001u +#define CYVAL_UDB_P_U_CI_SELB_ROUTE 0x00000002u +#define CYVAL_UDB_P_U_CI_SELB_CHAIN 0x00000003u +#define CYFLD_UDB_P_U_CMP_SELA__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_CMP_SELA__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELA_A1_D1 0x00000000u +#define CYVAL_UDB_P_U_CMP_SELA_A1_A0 0x00000001u +#define CYVAL_UDB_P_U_CMP_SELA_A0_D1 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELA_A0_A0 0x00000003u +#define CYFLD_UDB_P_U_CMP_SELB__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_CMP_SELB__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELB_A1_D1 0x00000000u +#define CYVAL_UDB_P_U_CMP_SELB_A1_A0 0x00000001u +#define CYVAL_UDB_P_U_CMP_SELB_A0_D1 0x00000002u +#define CYVAL_UDB_P_U_CMP_SELB_A0_A0 0x00000003u +#define CYREG_UDB_P0_U0_CFG14 0x400f304eu +#define CYFLD_UDB_P_U_CHAIN0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CHAIN0__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN0_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN0_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CHAIN1__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_CHAIN1__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN1_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN1_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CHAIN_FB__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CHAIN_FB__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN_FB_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN_FB_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_CHAIN_CMSB__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_MSB_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_MSB_SEL__SIZE 0x00000003u +#define CYVAL_UDB_P_U_MSB_SEL_BIT0 0x00000000u +#define CYVAL_UDB_P_U_MSB_SEL_BIT1 0x00000001u +#define CYVAL_UDB_P_U_MSB_SEL_BIT2 0x00000002u +#define CYVAL_UDB_P_U_MSB_SEL_BIT3 0x00000003u +#define CYVAL_UDB_P_U_MSB_SEL_BIT4 0x00000004u +#define CYVAL_UDB_P_U_MSB_SEL_BIT5 0x00000005u +#define CYVAL_UDB_P_U_MSB_SEL_BIT6 0x00000006u +#define CYVAL_UDB_P_U_MSB_SEL_BIT7 0x00000007u +#define CYFLD_UDB_P_U_MSB_EN__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_MSB_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_MSB_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_MSB_EN_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_CFG15 0x400f304fu +#define CYFLD_UDB_P_U_F0_INSEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_F0_INSEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_F0_INSEL_INPUT 0x00000000u +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 0x00000001u +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 0x00000002u +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU 0x00000003u +#define CYFLD_UDB_P_U_F1_INSEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_F1_INSEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_F1_INSEL_INPUT 0x00000000u +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 0x00000001u +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 0x00000002u +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU 0x00000003u +#define CYFLD_UDB_P_U_MSB_SI__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_MSB_SI__SIZE 0x00000001u +#define CYVAL_UDB_P_U_MSB_SI_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_MSB_SI_MSB 0x00000001u +#define CYFLD_UDB_P_U_PI_DYN__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_PI_DYN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PI_DYN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_PI_DYN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_SHIFT_SEL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_SHIFT_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB 0x00000000u +#define CYVAL_UDB_P_U_SHIFT_SEL_SOR 0x00000001u +#define CYFLD_UDB_P_U_PI_SEL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PI_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PI_SEL_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_PI_SEL_PARALLEL 0x00000001u +#define CYREG_UDB_P0_U0_CFG16 0x400f3050u +#define CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_WRK16_CONCAT__SIZE 0x00000001u +#define CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT 0x00000000u +#define CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE 0x00000001u +#define CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_EXT_CRCPRS__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL 0x00000000u +#define CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL 0x00000001u +#define CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_FIFO_ASYNC__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_EDGE__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_FIFO_EDGE__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_EDGE_LEVEL 0x00000000u +#define CYVAL_UDB_P_U_FIFO_EDGE_EDGE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_CAP__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_FIFO_CAP__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_CAP_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_CAP_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_FAST__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_FIFO_FAST__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_FAST_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_FAST_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_F0_CK_INV__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_F0_CK_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F0_CK_INV_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_F0_CK_INV_INVERT 0x00000001u +#define CYFLD_UDB_P_U_F1_CK_INV__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_F1_CK_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F1_CK_INV_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_F1_CK_INV_INVERT 0x00000001u +#define CYREG_UDB_P0_U0_CFG17 0x400f3051u +#define CYFLD_UDB_P_U_F0_DYN__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_F0_DYN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F0_DYN_STATIC 0x00000000u +#define CYVAL_UDB_P_U_F0_DYN_DYNAMIC 0x00000001u +#define CYFLD_UDB_P_U_F1_DYN__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_F1_DYN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_F1_DYN_STATIC 0x00000000u +#define CYVAL_UDB_P_U_F1_DYN_DYNAMIC 0x00000001u +#define CYFLD_UDB_P_U_NC2__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_NC2__SIZE 0x00000001u +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE 0x00000001u +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE 0x00000001u +#define CYREG_UDB_P0_U0_CFG18 0x400f3052u +#define CYFLD_UDB_P_U_CTL_MD0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CTL_MD0__SIZE 0x00000008u +#define CYVAL_UDB_P_U_CTL_MD0_DIRECT 0x00000000u +#define CYVAL_UDB_P_U_CTL_MD0_SYNC 0x00000001u +#define CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC 0x00000002u +#define CYVAL_UDB_P_U_CTL_MD0_PULSE 0x00000003u +#define CYREG_UDB_P0_U0_CFG19 0x400f3053u +#define CYFLD_UDB_P_U_CTL_MD1__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CTL_MD1__SIZE 0x00000008u +#define CYVAL_UDB_P_U_CTL_MD1_DIRECT 0x00000000u +#define CYVAL_UDB_P_U_CTL_MD1_SYNC 0x00000001u +#define CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC 0x00000002u +#define CYVAL_UDB_P_U_CTL_MD1_PULSE 0x00000003u +#define CYREG_UDB_P0_U0_CFG20 0x400f3054u +#define CYFLD_UDB_P_U_STAT_MD__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_STAT_MD__SIZE 0x00000008u +#define CYREG_UDB_P0_U0_CFG21 0x400f3055u +#define CYFLD_UDB_P_U_NC0__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_NC0__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG22 0x400f3056u +#define CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_SC_OUT_CTL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL 0x00000000u +#define CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL 0x00000001u +#define CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER 0x00000002u +#define CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED 0x00000003u +#define CYFLD_UDB_P_U_SC_INT_MD__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_SC_INT_MD__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_INT_MD_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_SC_INT_MD_INT_MODE 0x00000001u +#define CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_SC_SYNC_MD__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL 0x00000000u +#define CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE 0x00000001u +#define CYFLD_UDB_P_U_SC_EXT_RES__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_SC_EXT_RES__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_EXT_RES_DISABLED 0x00000000u +#define CYVAL_UDB_P_U_SC_EXT_RES_ENABLED 0x00000001u +#define CYREG_UDB_P0_U0_CFG23 0x400f3057u +#define CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CNT_LD_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 0x00000000u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 0x00000001u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 0x00000002u +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 0x00000003u +#define CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CNT_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 0x00000000u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 0x00000001u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 0x00000002u +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO 0x00000003u +#define CYFLD_UDB_P_U_ROUTE_LD__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_ROUTE_LD__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ROUTE_LD_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_ROUTE_LD_ROUTED 0x00000001u +#define CYFLD_UDB_P_U_ROUTE_EN__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_ROUTE_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ROUTE_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_ROUTE_EN_ROUTED 0x00000001u +#define CYFLD_UDB_P_U_ALT_CNT__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_ALT_CNT__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE 0x00000000u +#define CYVAL_UDB_P_U_ALT_CNT_ALT_MODE 0x00000001u +#define CYREG_UDB_P0_U0_CFG24 0x400f3058u +#define CYFLD_UDB_P_U_RC_EN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RC_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 0x00000000u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 0x00000001u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 0x00000003u +#define CYFLD_UDB_P_U_RC_EN_MODE__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_RC_EN_MODE__SIZE 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_MODE_OFF 0x00000000u +#define CYVAL_UDB_P_U_RC_EN_MODE_ON 0x00000001u +#define CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE 0x00000002u +#define CYVAL_UDB_P_U_RC_EN_MODE_LEVEL 0x00000003u +#define CYFLD_UDB_P_U_RC_EN_INV__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_RC_EN_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_RC_EN_INV_NOINV 0x00000000u +#define CYVAL_UDB_P_U_RC_EN_INV_INVERT 0x00000001u +#define CYFLD_UDB_P_U_RC_INV__OFFSET 0x00000005u +#define CYFLD_UDB_P_U_RC_INV__SIZE 0x00000001u +#define CYVAL_UDB_P_U_RC_INV_NOINV 0x00000000u +#define CYVAL_UDB_P_U_RC_INV_INVERT 0x00000001u +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE 0x00000001u +#define CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_RC_RES_SEL1__SIZE 0x00000001u +#define CYREG_UDB_P0_U0_CFG25 0x400f3059u +#define CYREG_UDB_P0_U0_CFG26 0x400f305au +#define CYREG_UDB_P0_U0_CFG27 0x400f305bu +#define CYREG_UDB_P0_U0_CFG28 0x400f305cu +#define CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK 0x00000009u +#define CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK 0x00000009u +#define CYREG_UDB_P0_U0_CFG29 0x400f305du +#define CYFLD_UDB_P_U_DP_CK_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_DP_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK 0x00000009u +#define CYFLD_UDB_P_U_SC_CK_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_SC_CK_SEL__SIZE 0x00000004u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK 0x00000008u +#define CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK 0x00000009u +#define CYREG_UDB_P0_U0_CFG30 0x400f305eu +#define CYFLD_UDB_P_U_RES_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_RES_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN0 0x00000000u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN1 0x00000001u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN2 0x00000002u +#define CYVAL_UDB_P_U_RES_SEL_RC_IN3 0x00000003u +#define CYFLD_UDB_P_U_RES_POL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_RES_POL_NEGATED 0x00000000u +#define CYVAL_UDB_P_U_RES_POL_ASSERTED 0x00000001u +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_GUDB_WR__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_GUDB_WR__SIZE 0x00000001u +#define CYVAL_UDB_P_U_GUDB_WR_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_GUDB_WR_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_DP_RES_POL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_DP_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_DP_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_DP_RES_POL_INVERT 0x00000001u +#define CYFLD_UDB_P_U_SC_RES_POL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_SC_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SC_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_SC_RES_POL_INVERT 0x00000001u +#define CYREG_UDB_P0_U0_CFG31 0x400f305fu +#define CYFLD_UDB_P_U_ALT_RES__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_ALT_RES__SIZE 0x00000001u +#define CYVAL_UDB_P_U_ALT_RES_COMPATIBLE 0x00000000u +#define CYVAL_UDB_P_U_ALT_RES_ALTERNATE 0x00000001u +#define CYFLD_UDB_P_U_EXT_SYNC__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_EXT_SYNC__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EXT_SYNC_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_EXT_SYNC_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_EN_RES_STAT__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_EN_RES_STAT__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EN_RES_STAT_NEGATED 0x00000000u +#define CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED 0x00000001u +#define CYFLD_UDB_P_U_EN_RES_DP__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_EN_RES_DP__SIZE 0x00000001u +#define CYVAL_UDB_P_U_EN_RES_DP_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_EN_RES_DP_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_EXT_CK_SEL__SIZE 0x00000002u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 0x00000000u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 0x00000001u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 0x00000002u +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 0x00000003u +#define CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_PLD0_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD0_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD0_RES_POL_INVERT 0x00000001u +#define CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET 0x00000007u +#define CYFLD_UDB_P_U_PLD1_RES_POL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_PLD1_RES_POL_NOINV 0x00000000u +#define CYVAL_UDB_P_U_PLD1_RES_POL_INVERT 0x00000001u +#define CYREG_UDB_P0_U0_DCFG0 0x400f3060u +#define CYFLD_UDB_P_U_CMP_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_P_U_CMP_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CMP_SEL_CFG_A 0x00000000u +#define CYVAL_UDB_P_U_CMP_SEL_CFG_B 0x00000001u +#define CYFLD_UDB_P_U_SI_SEL__OFFSET 0x00000001u +#define CYFLD_UDB_P_U_SI_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SI_SEL_CFG_A 0x00000000u +#define CYVAL_UDB_P_U_SI_SEL_CFG_B 0x00000001u +#define CYFLD_UDB_P_U_CI_SEL__OFFSET 0x00000002u +#define CYFLD_UDB_P_U_CI_SEL__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CI_SEL_CFG_A 0x00000000u +#define CYVAL_UDB_P_U_CI_SEL_CFG_B 0x00000001u +#define CYFLD_UDB_P_U_CFB_EN__OFFSET 0x00000003u +#define CYFLD_UDB_P_U_CFB_EN__SIZE 0x00000001u +#define CYVAL_UDB_P_U_CFB_EN_DISABLE 0x00000000u +#define CYVAL_UDB_P_U_CFB_EN_ENABLE 0x00000001u +#define CYFLD_UDB_P_U_A1_WR_SRC__OFFSET 0x00000004u +#define CYFLD_UDB_P_U_A1_WR_SRC__SIZE 0x00000002u +#define CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE 0x00000000u +#define CYVAL_UDB_P_U_A1_WR_SRC_ALU 0x00000001u +#define CYVAL_UDB_P_U_A1_WR_SRC_D1 0x00000002u +#define CYVAL_UDB_P_U_A1_WR_SRC_F1 0x00000003u +#define CYFLD_UDB_P_U_A0_WR_SRC__OFFSET 0x00000006u +#define CYFLD_UDB_P_U_A0_WR_SRC__SIZE 0x00000002u +#define CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE 0x00000000u +#define CYVAL_UDB_P_U_A0_WR_SRC_ALU 0x00000001u +#define CYVAL_UDB_P_U_A0_WR_SRC_D0 0x00000002u +#define CYVAL_UDB_P_U_A0_WR_SRC_F0 0x00000003u +#define CYFLD_UDB_P_U_SHIFT__OFFSET 0x00000008u +#define CYFLD_UDB_P_U_SHIFT__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SHIFT_NOSHIFT 0x00000000u +#define CYVAL_UDB_P_U_SHIFT_LEFT 0x00000001u +#define CYVAL_UDB_P_U_SHIFT_RIGHT 0x00000002u +#define CYVAL_UDB_P_U_SHIFT_SWAP 0x00000003u +#define CYFLD_UDB_P_U_SRC_B__OFFSET 0x0000000au +#define CYFLD_UDB_P_U_SRC_B__SIZE 0x00000002u +#define CYVAL_UDB_P_U_SRC_B_D0 0x00000000u +#define CYVAL_UDB_P_U_SRC_B_D1 0x00000001u +#define CYVAL_UDB_P_U_SRC_B_A0 0x00000002u +#define CYVAL_UDB_P_U_SRC_B_A1 0x00000003u +#define CYFLD_UDB_P_U_SRC_A__OFFSET 0x0000000cu +#define CYFLD_UDB_P_U_SRC_A__SIZE 0x00000001u +#define CYVAL_UDB_P_U_SRC_A_A0 0x00000000u +#define CYVAL_UDB_P_U_SRC_A_A1 0x00000001u +#define CYFLD_UDB_P_U_FUNC__OFFSET 0x0000000du +#define CYFLD_UDB_P_U_FUNC__SIZE 0x00000003u +#define CYVAL_UDB_P_U_FUNC_PASS 0x00000000u +#define CYVAL_UDB_P_U_FUNC_INC_A 0x00000001u +#define CYVAL_UDB_P_U_FUNC_DEC_A 0x00000002u +#define CYVAL_UDB_P_U_FUNC_ADD 0x00000003u +#define CYVAL_UDB_P_U_FUNC_SUB 0x00000004u +#define CYVAL_UDB_P_U_FUNC_XOR 0x00000005u +#define CYVAL_UDB_P_U_FUNC_AND 0x00000006u +#define CYVAL_UDB_P_U_FUNC_OR 0x00000007u +#define CYREG_UDB_P0_U0_DCFG1 0x400f3062u +#define CYREG_UDB_P0_U0_DCFG2 0x400f3064u +#define CYREG_UDB_P0_U0_DCFG3 0x400f3066u +#define CYREG_UDB_P0_U0_DCFG4 0x400f3068u +#define CYREG_UDB_P0_U0_DCFG5 0x400f306au +#define CYREG_UDB_P0_U0_DCFG6 0x400f306cu +#define CYREG_UDB_P0_U0_DCFG7 0x400f306eu +#define CYDEV_UDB_P0_U1_BASE 0x400f3080u +#define CYDEV_UDB_P0_U1_SIZE 0x00000080u +#define CYREG_UDB_P0_U1_PLD_IT0 0x400f3080u +#define CYREG_UDB_P0_U1_PLD_IT1 0x400f3084u +#define CYREG_UDB_P0_U1_PLD_IT2 0x400f3088u +#define CYREG_UDB_P0_U1_PLD_IT3 0x400f308cu +#define CYREG_UDB_P0_U1_PLD_IT4 0x400f3090u +#define CYREG_UDB_P0_U1_PLD_IT5 0x400f3094u +#define CYREG_UDB_P0_U1_PLD_IT6 0x400f3098u +#define CYREG_UDB_P0_U1_PLD_IT7 0x400f309cu +#define CYREG_UDB_P0_U1_PLD_IT8 0x400f30a0u +#define CYREG_UDB_P0_U1_PLD_IT9 0x400f30a4u +#define CYREG_UDB_P0_U1_PLD_IT10 0x400f30a8u +#define CYREG_UDB_P0_U1_PLD_IT11 0x400f30acu +#define CYREG_UDB_P0_U1_PLD_ORT0 0x400f30b0u +#define CYREG_UDB_P0_U1_PLD_ORT1 0x400f30b2u +#define CYREG_UDB_P0_U1_PLD_ORT2 0x400f30b4u +#define CYREG_UDB_P0_U1_PLD_ORT3 0x400f30b6u +#define CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST 0x400f30b8u +#define CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB 0x400f30bau +#define CYREG_UDB_P0_U1_PLD_MC_SET_RESET 0x400f30bcu +#define CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS 0x400f30beu +#define CYREG_UDB_P0_U1_CFG0 0x400f30c0u +#define CYREG_UDB_P0_U1_CFG1 0x400f30c1u +#define CYREG_UDB_P0_U1_CFG2 0x400f30c2u +#define CYREG_UDB_P0_U1_CFG3 0x400f30c3u +#define CYREG_UDB_P0_U1_CFG4 0x400f30c4u +#define CYREG_UDB_P0_U1_CFG5 0x400f30c5u +#define CYREG_UDB_P0_U1_CFG6 0x400f30c6u +#define CYREG_UDB_P0_U1_CFG7 0x400f30c7u +#define CYREG_UDB_P0_U1_CFG8 0x400f30c8u +#define CYREG_UDB_P0_U1_CFG9 0x400f30c9u +#define CYREG_UDB_P0_U1_CFG10 0x400f30cau +#define CYREG_UDB_P0_U1_CFG11 0x400f30cbu +#define CYREG_UDB_P0_U1_CFG12 0x400f30ccu +#define CYREG_UDB_P0_U1_CFG13 0x400f30cdu +#define CYREG_UDB_P0_U1_CFG14 0x400f30ceu +#define CYREG_UDB_P0_U1_CFG15 0x400f30cfu +#define CYREG_UDB_P0_U1_CFG16 0x400f30d0u +#define CYREG_UDB_P0_U1_CFG17 0x400f30d1u +#define CYREG_UDB_P0_U1_CFG18 0x400f30d2u +#define CYREG_UDB_P0_U1_CFG19 0x400f30d3u +#define CYREG_UDB_P0_U1_CFG20 0x400f30d4u +#define CYREG_UDB_P0_U1_CFG21 0x400f30d5u +#define CYREG_UDB_P0_U1_CFG22 0x400f30d6u +#define CYREG_UDB_P0_U1_CFG23 0x400f30d7u +#define CYREG_UDB_P0_U1_CFG24 0x400f30d8u +#define CYREG_UDB_P0_U1_CFG25 0x400f30d9u +#define CYREG_UDB_P0_U1_CFG26 0x400f30dau +#define CYREG_UDB_P0_U1_CFG27 0x400f30dbu +#define CYREG_UDB_P0_U1_CFG28 0x400f30dcu +#define CYREG_UDB_P0_U1_CFG29 0x400f30ddu +#define CYREG_UDB_P0_U1_CFG30 0x400f30deu +#define CYREG_UDB_P0_U1_CFG31 0x400f30dfu +#define CYREG_UDB_P0_U1_DCFG0 0x400f30e0u +#define CYREG_UDB_P0_U1_DCFG1 0x400f30e2u +#define CYREG_UDB_P0_U1_DCFG2 0x400f30e4u +#define CYREG_UDB_P0_U1_DCFG3 0x400f30e6u +#define CYREG_UDB_P0_U1_DCFG4 0x400f30e8u +#define CYREG_UDB_P0_U1_DCFG5 0x400f30eau +#define CYREG_UDB_P0_U1_DCFG6 0x400f30ecu +#define CYREG_UDB_P0_U1_DCFG7 0x400f30eeu +#define CYDEV_UDB_P0_ROUTE_BASE 0x400f3100u +#define CYDEV_UDB_P0_ROUTE_SIZE 0x00000100u +#define CYREG_UDB_P0_ROUTE_HC0 0x400f3100u +#define CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE 0x00000008u +#define CYREG_UDB_P0_ROUTE_HC1 0x400f3101u +#define CYREG_UDB_P0_ROUTE_HC2 0x400f3102u +#define CYREG_UDB_P0_ROUTE_HC3 0x400f3103u +#define CYREG_UDB_P0_ROUTE_HC4 0x400f3104u +#define CYREG_UDB_P0_ROUTE_HC5 0x400f3105u +#define CYREG_UDB_P0_ROUTE_HC6 0x400f3106u +#define CYREG_UDB_P0_ROUTE_HC7 0x400f3107u +#define CYREG_UDB_P0_ROUTE_HC8 0x400f3108u +#define CYREG_UDB_P0_ROUTE_HC9 0x400f3109u +#define CYREG_UDB_P0_ROUTE_HC10 0x400f310au +#define CYREG_UDB_P0_ROUTE_HC11 0x400f310bu +#define CYREG_UDB_P0_ROUTE_HC12 0x400f310cu +#define CYREG_UDB_P0_ROUTE_HC13 0x400f310du +#define CYREG_UDB_P0_ROUTE_HC14 0x400f310eu +#define CYREG_UDB_P0_ROUTE_HC15 0x400f310fu +#define CYREG_UDB_P0_ROUTE_HC16 0x400f3110u +#define CYREG_UDB_P0_ROUTE_HC17 0x400f3111u +#define CYREG_UDB_P0_ROUTE_HC18 0x400f3112u +#define CYREG_UDB_P0_ROUTE_HC19 0x400f3113u +#define CYREG_UDB_P0_ROUTE_HC20 0x400f3114u +#define CYREG_UDB_P0_ROUTE_HC21 0x400f3115u +#define CYREG_UDB_P0_ROUTE_HC22 0x400f3116u +#define CYREG_UDB_P0_ROUTE_HC23 0x400f3117u +#define CYREG_UDB_P0_ROUTE_HC24 0x400f3118u +#define CYREG_UDB_P0_ROUTE_HC25 0x400f3119u +#define CYREG_UDB_P0_ROUTE_HC26 0x400f311au +#define CYREG_UDB_P0_ROUTE_HC27 0x400f311bu +#define CYREG_UDB_P0_ROUTE_HC28 0x400f311cu +#define CYREG_UDB_P0_ROUTE_HC29 0x400f311du +#define CYREG_UDB_P0_ROUTE_HC30 0x400f311eu +#define CYREG_UDB_P0_ROUTE_HC31 0x400f311fu +#define CYREG_UDB_P0_ROUTE_HC32 0x400f3120u +#define CYREG_UDB_P0_ROUTE_HC33 0x400f3121u +#define CYREG_UDB_P0_ROUTE_HC34 0x400f3122u +#define CYREG_UDB_P0_ROUTE_HC35 0x400f3123u +#define CYREG_UDB_P0_ROUTE_HC36 0x400f3124u +#define CYREG_UDB_P0_ROUTE_HC37 0x400f3125u +#define CYREG_UDB_P0_ROUTE_HC38 0x400f3126u +#define CYREG_UDB_P0_ROUTE_HC39 0x400f3127u +#define CYREG_UDB_P0_ROUTE_HC40 0x400f3128u +#define CYREG_UDB_P0_ROUTE_HC41 0x400f3129u +#define CYREG_UDB_P0_ROUTE_HC42 0x400f312au +#define CYREG_UDB_P0_ROUTE_HC43 0x400f312bu +#define CYREG_UDB_P0_ROUTE_HC44 0x400f312cu +#define CYREG_UDB_P0_ROUTE_HC45 0x400f312du +#define CYREG_UDB_P0_ROUTE_HC46 0x400f312eu +#define CYREG_UDB_P0_ROUTE_HC47 0x400f312fu +#define CYREG_UDB_P0_ROUTE_HC48 0x400f3130u +#define CYREG_UDB_P0_ROUTE_HC49 0x400f3131u +#define CYREG_UDB_P0_ROUTE_HC50 0x400f3132u +#define CYREG_UDB_P0_ROUTE_HC51 0x400f3133u +#define CYREG_UDB_P0_ROUTE_HC52 0x400f3134u +#define CYREG_UDB_P0_ROUTE_HC53 0x400f3135u +#define CYREG_UDB_P0_ROUTE_HC54 0x400f3136u +#define CYREG_UDB_P0_ROUTE_HC55 0x400f3137u +#define CYREG_UDB_P0_ROUTE_HC56 0x400f3138u +#define CYREG_UDB_P0_ROUTE_HC57 0x400f3139u +#define CYREG_UDB_P0_ROUTE_HC58 0x400f313au +#define CYREG_UDB_P0_ROUTE_HC59 0x400f313bu +#define CYREG_UDB_P0_ROUTE_HC60 0x400f313cu +#define CYREG_UDB_P0_ROUTE_HC61 0x400f313du +#define CYREG_UDB_P0_ROUTE_HC62 0x400f313eu +#define CYREG_UDB_P0_ROUTE_HC63 0x400f313fu +#define CYREG_UDB_P0_ROUTE_HC64 0x400f3140u +#define CYREG_UDB_P0_ROUTE_HC65 0x400f3141u +#define CYREG_UDB_P0_ROUTE_HC66 0x400f3142u +#define CYREG_UDB_P0_ROUTE_HC67 0x400f3143u +#define CYREG_UDB_P0_ROUTE_HC68 0x400f3144u +#define CYREG_UDB_P0_ROUTE_HC69 0x400f3145u +#define CYREG_UDB_P0_ROUTE_HC70 0x400f3146u +#define CYREG_UDB_P0_ROUTE_HC71 0x400f3147u +#define CYREG_UDB_P0_ROUTE_HC72 0x400f3148u +#define CYREG_UDB_P0_ROUTE_HC73 0x400f3149u +#define CYREG_UDB_P0_ROUTE_HC74 0x400f314au +#define CYREG_UDB_P0_ROUTE_HC75 0x400f314bu +#define CYREG_UDB_P0_ROUTE_HC76 0x400f314cu +#define CYREG_UDB_P0_ROUTE_HC77 0x400f314du +#define CYREG_UDB_P0_ROUTE_HC78 0x400f314eu +#define CYREG_UDB_P0_ROUTE_HC79 0x400f314fu +#define CYREG_UDB_P0_ROUTE_HC80 0x400f3150u +#define CYREG_UDB_P0_ROUTE_HC81 0x400f3151u +#define CYREG_UDB_P0_ROUTE_HC82 0x400f3152u +#define CYREG_UDB_P0_ROUTE_HC83 0x400f3153u +#define CYREG_UDB_P0_ROUTE_HC84 0x400f3154u +#define CYREG_UDB_P0_ROUTE_HC85 0x400f3155u +#define CYREG_UDB_P0_ROUTE_HC86 0x400f3156u +#define CYREG_UDB_P0_ROUTE_HC87 0x400f3157u +#define CYREG_UDB_P0_ROUTE_HC88 0x400f3158u +#define CYREG_UDB_P0_ROUTE_HC89 0x400f3159u +#define CYREG_UDB_P0_ROUTE_HC90 0x400f315au +#define CYREG_UDB_P0_ROUTE_HC91 0x400f315bu +#define CYREG_UDB_P0_ROUTE_HC92 0x400f315cu +#define CYREG_UDB_P0_ROUTE_HC93 0x400f315du +#define CYREG_UDB_P0_ROUTE_HC94 0x400f315eu +#define CYREG_UDB_P0_ROUTE_HC95 0x400f315fu +#define CYREG_UDB_P0_ROUTE_HC96 0x400f3160u +#define CYREG_UDB_P0_ROUTE_HC97 0x400f3161u +#define CYREG_UDB_P0_ROUTE_HC98 0x400f3162u +#define CYREG_UDB_P0_ROUTE_HC99 0x400f3163u +#define CYREG_UDB_P0_ROUTE_HC100 0x400f3164u +#define CYREG_UDB_P0_ROUTE_HC101 0x400f3165u +#define CYREG_UDB_P0_ROUTE_HC102 0x400f3166u +#define CYREG_UDB_P0_ROUTE_HC103 0x400f3167u +#define CYREG_UDB_P0_ROUTE_HC104 0x400f3168u +#define CYREG_UDB_P0_ROUTE_HC105 0x400f3169u +#define CYREG_UDB_P0_ROUTE_HC106 0x400f316au +#define CYREG_UDB_P0_ROUTE_HC107 0x400f316bu +#define CYREG_UDB_P0_ROUTE_HC108 0x400f316cu +#define CYREG_UDB_P0_ROUTE_HC109 0x400f316du +#define CYREG_UDB_P0_ROUTE_HC110 0x400f316eu +#define CYREG_UDB_P0_ROUTE_HC111 0x400f316fu +#define CYREG_UDB_P0_ROUTE_HC112 0x400f3170u +#define CYREG_UDB_P0_ROUTE_HC113 0x400f3171u +#define CYREG_UDB_P0_ROUTE_HC114 0x400f3172u +#define CYREG_UDB_P0_ROUTE_HC115 0x400f3173u +#define CYREG_UDB_P0_ROUTE_HC116 0x400f3174u +#define CYREG_UDB_P0_ROUTE_HC117 0x400f3175u +#define CYREG_UDB_P0_ROUTE_HC118 0x400f3176u +#define CYREG_UDB_P0_ROUTE_HC119 0x400f3177u +#define CYREG_UDB_P0_ROUTE_HC120 0x400f3178u +#define CYREG_UDB_P0_ROUTE_HC121 0x400f3179u +#define CYREG_UDB_P0_ROUTE_HC122 0x400f317au +#define CYREG_UDB_P0_ROUTE_HC123 0x400f317bu +#define CYREG_UDB_P0_ROUTE_HC124 0x400f317cu +#define CYREG_UDB_P0_ROUTE_HC125 0x400f317du +#define CYREG_UDB_P0_ROUTE_HC126 0x400f317eu +#define CYREG_UDB_P0_ROUTE_HC127 0x400f317fu +#define CYREG_UDB_P0_ROUTE_HV_L0 0x400f3180u +#define CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE 0x00000008u +#define CYREG_UDB_P0_ROUTE_HV_L1 0x400f3181u +#define CYREG_UDB_P0_ROUTE_HV_L2 0x400f3182u +#define CYREG_UDB_P0_ROUTE_HV_L3 0x400f3183u +#define CYREG_UDB_P0_ROUTE_HV_L4 0x400f3184u +#define CYREG_UDB_P0_ROUTE_HV_L5 0x400f3185u +#define CYREG_UDB_P0_ROUTE_HV_L6 0x400f3186u +#define CYREG_UDB_P0_ROUTE_HV_L7 0x400f3187u +#define CYREG_UDB_P0_ROUTE_HV_L8 0x400f3188u +#define CYREG_UDB_P0_ROUTE_HV_L9 0x400f3189u +#define CYREG_UDB_P0_ROUTE_HV_L10 0x400f318au +#define CYREG_UDB_P0_ROUTE_HV_L11 0x400f318bu +#define CYREG_UDB_P0_ROUTE_HV_L12 0x400f318cu +#define CYREG_UDB_P0_ROUTE_HV_L13 0x400f318du +#define CYREG_UDB_P0_ROUTE_HV_L14 0x400f318eu +#define CYREG_UDB_P0_ROUTE_HV_L15 0x400f318fu +#define CYREG_UDB_P0_ROUTE_HS0 0x400f3190u +#define CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE 0x00000008u +#define CYREG_UDB_P0_ROUTE_HS1 0x400f3191u +#define CYREG_UDB_P0_ROUTE_HS2 0x400f3192u +#define CYREG_UDB_P0_ROUTE_HS3 0x400f3193u +#define CYREG_UDB_P0_ROUTE_HS4 0x400f3194u +#define CYREG_UDB_P0_ROUTE_HS5 0x400f3195u +#define CYREG_UDB_P0_ROUTE_HS6 0x400f3196u +#define CYREG_UDB_P0_ROUTE_HS7 0x400f3197u +#define CYREG_UDB_P0_ROUTE_HS8 0x400f3198u +#define CYREG_UDB_P0_ROUTE_HS9 0x400f3199u +#define CYREG_UDB_P0_ROUTE_HS10 0x400f319au +#define CYREG_UDB_P0_ROUTE_HS11 0x400f319bu +#define CYREG_UDB_P0_ROUTE_HS12 0x400f319cu +#define CYREG_UDB_P0_ROUTE_HS13 0x400f319du +#define CYREG_UDB_P0_ROUTE_HS14 0x400f319eu +#define CYREG_UDB_P0_ROUTE_HS15 0x400f319fu +#define CYREG_UDB_P0_ROUTE_HS16 0x400f31a0u +#define CYREG_UDB_P0_ROUTE_HS17 0x400f31a1u +#define CYREG_UDB_P0_ROUTE_HS18 0x400f31a2u +#define CYREG_UDB_P0_ROUTE_HS19 0x400f31a3u +#define CYREG_UDB_P0_ROUTE_HS20 0x400f31a4u +#define CYREG_UDB_P0_ROUTE_HS21 0x400f31a5u +#define CYREG_UDB_P0_ROUTE_HS22 0x400f31a6u +#define CYREG_UDB_P0_ROUTE_HS23 0x400f31a7u +#define CYREG_UDB_P0_ROUTE_HV_R0 0x400f31a8u +#define CYREG_UDB_P0_ROUTE_HV_R1 0x400f31a9u +#define CYREG_UDB_P0_ROUTE_HV_R2 0x400f31aau +#define CYREG_UDB_P0_ROUTE_HV_R3 0x400f31abu +#define CYREG_UDB_P0_ROUTE_HV_R4 0x400f31acu +#define CYREG_UDB_P0_ROUTE_HV_R5 0x400f31adu +#define CYREG_UDB_P0_ROUTE_HV_R6 0x400f31aeu +#define CYREG_UDB_P0_ROUTE_HV_R7 0x400f31afu +#define CYREG_UDB_P0_ROUTE_HV_R8 0x400f31b0u +#define CYREG_UDB_P0_ROUTE_HV_R9 0x400f31b1u +#define CYREG_UDB_P0_ROUTE_HV_R10 0x400f31b2u +#define CYREG_UDB_P0_ROUTE_HV_R11 0x400f31b3u +#define CYREG_UDB_P0_ROUTE_HV_R12 0x400f31b4u +#define CYREG_UDB_P0_ROUTE_HV_R13 0x400f31b5u +#define CYREG_UDB_P0_ROUTE_HV_R14 0x400f31b6u +#define CYREG_UDB_P0_ROUTE_HV_R15 0x400f31b7u +#define CYREG_UDB_P0_ROUTE_PLD0IN0 0x400f31c0u +#define CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_PI_TOP__SIZE 0x00000004u +#define CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_P_ROUTE_PI_BOT__SIZE 0x00000004u +#define CYREG_UDB_P0_ROUTE_PLD0IN1 0x400f31c2u +#define CYREG_UDB_P0_ROUTE_PLD0IN2 0x400f31c4u +#define CYREG_UDB_P0_ROUTE_PLD1IN0 0x400f31cau +#define CYREG_UDB_P0_ROUTE_PLD1IN1 0x400f31ccu +#define CYREG_UDB_P0_ROUTE_PLD1IN2 0x400f31ceu +#define CYREG_UDB_P0_ROUTE_DPIN0 0x400f31d0u +#define CYREG_UDB_P0_ROUTE_DPIN1 0x400f31d2u +#define CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET 0x00000002u +#define CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE 0x00000002u +#define CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET 0x00000004u +#define CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE 0x00000002u +#define CYREG_UDB_P0_ROUTE_SCIN 0x400f31d6u +#define CYREG_UDB_P0_ROUTE_SCIOIN 0x400f31d8u +#define CYREG_UDB_P0_ROUTE_RCIN 0x400f31deu +#define CYREG_UDB_P0_ROUTE_VS0 0x400f31e0u +#define CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_P_ROUTE_VS_TOP__SIZE 0x00000004u +#define CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_P_ROUTE_VS_BOT__SIZE 0x00000004u +#define CYREG_UDB_P0_ROUTE_VS1 0x400f31e2u +#define CYREG_UDB_P0_ROUTE_VS2 0x400f31e4u +#define CYREG_UDB_P0_ROUTE_VS3 0x400f31e6u +#define CYREG_UDB_P0_ROUTE_VS4 0x400f31e8u +#define CYREG_UDB_P0_ROUTE_VS5 0x400f31eau +#define CYREG_UDB_P0_ROUTE_VS6 0x400f31ecu +#define CYREG_UDB_P0_ROUTE_VS7 0x400f31eeu +#define CYDEV_UDB_P1_BASE 0x400f3200u +#define CYDEV_UDB_P1_SIZE 0x00000200u +#define CYDEV_UDB_P1_U0_BASE 0x400f3200u +#define CYDEV_UDB_P1_U0_SIZE 0x00000080u +#define CYREG_UDB_P1_U0_PLD_IT0 0x400f3200u +#define CYREG_UDB_P1_U0_PLD_IT1 0x400f3204u +#define CYREG_UDB_P1_U0_PLD_IT2 0x400f3208u +#define CYREG_UDB_P1_U0_PLD_IT3 0x400f320cu +#define CYREG_UDB_P1_U0_PLD_IT4 0x400f3210u +#define CYREG_UDB_P1_U0_PLD_IT5 0x400f3214u +#define CYREG_UDB_P1_U0_PLD_IT6 0x400f3218u +#define CYREG_UDB_P1_U0_PLD_IT7 0x400f321cu +#define CYREG_UDB_P1_U0_PLD_IT8 0x400f3220u +#define CYREG_UDB_P1_U0_PLD_IT9 0x400f3224u +#define CYREG_UDB_P1_U0_PLD_IT10 0x400f3228u +#define CYREG_UDB_P1_U0_PLD_IT11 0x400f322cu +#define CYREG_UDB_P1_U0_PLD_ORT0 0x400f3230u +#define CYREG_UDB_P1_U0_PLD_ORT1 0x400f3232u +#define CYREG_UDB_P1_U0_PLD_ORT2 0x400f3234u +#define CYREG_UDB_P1_U0_PLD_ORT3 0x400f3236u +#define CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST 0x400f3238u +#define CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB 0x400f323au +#define CYREG_UDB_P1_U0_PLD_MC_SET_RESET 0x400f323cu +#define CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS 0x400f323eu +#define CYREG_UDB_P1_U0_CFG0 0x400f3240u +#define CYREG_UDB_P1_U0_CFG1 0x400f3241u +#define CYREG_UDB_P1_U0_CFG2 0x400f3242u +#define CYREG_UDB_P1_U0_CFG3 0x400f3243u +#define CYREG_UDB_P1_U0_CFG4 0x400f3244u +#define CYREG_UDB_P1_U0_CFG5 0x400f3245u +#define CYREG_UDB_P1_U0_CFG6 0x400f3246u +#define CYREG_UDB_P1_U0_CFG7 0x400f3247u +#define CYREG_UDB_P1_U0_CFG8 0x400f3248u +#define CYREG_UDB_P1_U0_CFG9 0x400f3249u +#define CYREG_UDB_P1_U0_CFG10 0x400f324au +#define CYREG_UDB_P1_U0_CFG11 0x400f324bu +#define CYREG_UDB_P1_U0_CFG12 0x400f324cu +#define CYREG_UDB_P1_U0_CFG13 0x400f324du +#define CYREG_UDB_P1_U0_CFG14 0x400f324eu +#define CYREG_UDB_P1_U0_CFG15 0x400f324fu +#define CYREG_UDB_P1_U0_CFG16 0x400f3250u +#define CYREG_UDB_P1_U0_CFG17 0x400f3251u +#define CYREG_UDB_P1_U0_CFG18 0x400f3252u +#define CYREG_UDB_P1_U0_CFG19 0x400f3253u +#define CYREG_UDB_P1_U0_CFG20 0x400f3254u +#define CYREG_UDB_P1_U0_CFG21 0x400f3255u +#define CYREG_UDB_P1_U0_CFG22 0x400f3256u +#define CYREG_UDB_P1_U0_CFG23 0x400f3257u +#define CYREG_UDB_P1_U0_CFG24 0x400f3258u +#define CYREG_UDB_P1_U0_CFG25 0x400f3259u +#define CYREG_UDB_P1_U0_CFG26 0x400f325au +#define CYREG_UDB_P1_U0_CFG27 0x400f325bu +#define CYREG_UDB_P1_U0_CFG28 0x400f325cu +#define CYREG_UDB_P1_U0_CFG29 0x400f325du +#define CYREG_UDB_P1_U0_CFG30 0x400f325eu +#define CYREG_UDB_P1_U0_CFG31 0x400f325fu +#define CYREG_UDB_P1_U0_DCFG0 0x400f3260u +#define CYREG_UDB_P1_U0_DCFG1 0x400f3262u +#define CYREG_UDB_P1_U0_DCFG2 0x400f3264u +#define CYREG_UDB_P1_U0_DCFG3 0x400f3266u +#define CYREG_UDB_P1_U0_DCFG4 0x400f3268u +#define CYREG_UDB_P1_U0_DCFG5 0x400f326au +#define CYREG_UDB_P1_U0_DCFG6 0x400f326cu +#define CYREG_UDB_P1_U0_DCFG7 0x400f326eu +#define CYDEV_UDB_P1_U1_BASE 0x400f3280u +#define CYDEV_UDB_P1_U1_SIZE 0x00000080u +#define CYREG_UDB_P1_U1_PLD_IT0 0x400f3280u +#define CYREG_UDB_P1_U1_PLD_IT1 0x400f3284u +#define CYREG_UDB_P1_U1_PLD_IT2 0x400f3288u +#define CYREG_UDB_P1_U1_PLD_IT3 0x400f328cu +#define CYREG_UDB_P1_U1_PLD_IT4 0x400f3290u +#define CYREG_UDB_P1_U1_PLD_IT5 0x400f3294u +#define CYREG_UDB_P1_U1_PLD_IT6 0x400f3298u +#define CYREG_UDB_P1_U1_PLD_IT7 0x400f329cu +#define CYREG_UDB_P1_U1_PLD_IT8 0x400f32a0u +#define CYREG_UDB_P1_U1_PLD_IT9 0x400f32a4u +#define CYREG_UDB_P1_U1_PLD_IT10 0x400f32a8u +#define CYREG_UDB_P1_U1_PLD_IT11 0x400f32acu +#define CYREG_UDB_P1_U1_PLD_ORT0 0x400f32b0u +#define CYREG_UDB_P1_U1_PLD_ORT1 0x400f32b2u +#define CYREG_UDB_P1_U1_PLD_ORT2 0x400f32b4u +#define CYREG_UDB_P1_U1_PLD_ORT3 0x400f32b6u +#define CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST 0x400f32b8u +#define CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB 0x400f32bau +#define CYREG_UDB_P1_U1_PLD_MC_SET_RESET 0x400f32bcu +#define CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS 0x400f32beu +#define CYREG_UDB_P1_U1_CFG0 0x400f32c0u +#define CYREG_UDB_P1_U1_CFG1 0x400f32c1u +#define CYREG_UDB_P1_U1_CFG2 0x400f32c2u +#define CYREG_UDB_P1_U1_CFG3 0x400f32c3u +#define CYREG_UDB_P1_U1_CFG4 0x400f32c4u +#define CYREG_UDB_P1_U1_CFG5 0x400f32c5u +#define CYREG_UDB_P1_U1_CFG6 0x400f32c6u +#define CYREG_UDB_P1_U1_CFG7 0x400f32c7u +#define CYREG_UDB_P1_U1_CFG8 0x400f32c8u +#define CYREG_UDB_P1_U1_CFG9 0x400f32c9u +#define CYREG_UDB_P1_U1_CFG10 0x400f32cau +#define CYREG_UDB_P1_U1_CFG11 0x400f32cbu +#define CYREG_UDB_P1_U1_CFG12 0x400f32ccu +#define CYREG_UDB_P1_U1_CFG13 0x400f32cdu +#define CYREG_UDB_P1_U1_CFG14 0x400f32ceu +#define CYREG_UDB_P1_U1_CFG15 0x400f32cfu +#define CYREG_UDB_P1_U1_CFG16 0x400f32d0u +#define CYREG_UDB_P1_U1_CFG17 0x400f32d1u +#define CYREG_UDB_P1_U1_CFG18 0x400f32d2u +#define CYREG_UDB_P1_U1_CFG19 0x400f32d3u +#define CYREG_UDB_P1_U1_CFG20 0x400f32d4u +#define CYREG_UDB_P1_U1_CFG21 0x400f32d5u +#define CYREG_UDB_P1_U1_CFG22 0x400f32d6u +#define CYREG_UDB_P1_U1_CFG23 0x400f32d7u +#define CYREG_UDB_P1_U1_CFG24 0x400f32d8u +#define CYREG_UDB_P1_U1_CFG25 0x400f32d9u +#define CYREG_UDB_P1_U1_CFG26 0x400f32dau +#define CYREG_UDB_P1_U1_CFG27 0x400f32dbu +#define CYREG_UDB_P1_U1_CFG28 0x400f32dcu +#define CYREG_UDB_P1_U1_CFG29 0x400f32ddu +#define CYREG_UDB_P1_U1_CFG30 0x400f32deu +#define CYREG_UDB_P1_U1_CFG31 0x400f32dfu +#define CYREG_UDB_P1_U1_DCFG0 0x400f32e0u +#define CYREG_UDB_P1_U1_DCFG1 0x400f32e2u +#define CYREG_UDB_P1_U1_DCFG2 0x400f32e4u +#define CYREG_UDB_P1_U1_DCFG3 0x400f32e6u +#define CYREG_UDB_P1_U1_DCFG4 0x400f32e8u +#define CYREG_UDB_P1_U1_DCFG5 0x400f32eau +#define CYREG_UDB_P1_U1_DCFG6 0x400f32ecu +#define CYREG_UDB_P1_U1_DCFG7 0x400f32eeu +#define CYDEV_UDB_P1_ROUTE_BASE 0x400f3300u +#define CYDEV_UDB_P1_ROUTE_SIZE 0x00000100u +#define CYREG_UDB_P1_ROUTE_HC0 0x400f3300u +#define CYREG_UDB_P1_ROUTE_HC1 0x400f3301u +#define CYREG_UDB_P1_ROUTE_HC2 0x400f3302u +#define CYREG_UDB_P1_ROUTE_HC3 0x400f3303u +#define CYREG_UDB_P1_ROUTE_HC4 0x400f3304u +#define CYREG_UDB_P1_ROUTE_HC5 0x400f3305u +#define CYREG_UDB_P1_ROUTE_HC6 0x400f3306u +#define CYREG_UDB_P1_ROUTE_HC7 0x400f3307u +#define CYREG_UDB_P1_ROUTE_HC8 0x400f3308u +#define CYREG_UDB_P1_ROUTE_HC9 0x400f3309u +#define CYREG_UDB_P1_ROUTE_HC10 0x400f330au +#define CYREG_UDB_P1_ROUTE_HC11 0x400f330bu +#define CYREG_UDB_P1_ROUTE_HC12 0x400f330cu +#define CYREG_UDB_P1_ROUTE_HC13 0x400f330du +#define CYREG_UDB_P1_ROUTE_HC14 0x400f330eu +#define CYREG_UDB_P1_ROUTE_HC15 0x400f330fu +#define CYREG_UDB_P1_ROUTE_HC16 0x400f3310u +#define CYREG_UDB_P1_ROUTE_HC17 0x400f3311u +#define CYREG_UDB_P1_ROUTE_HC18 0x400f3312u +#define CYREG_UDB_P1_ROUTE_HC19 0x400f3313u +#define CYREG_UDB_P1_ROUTE_HC20 0x400f3314u +#define CYREG_UDB_P1_ROUTE_HC21 0x400f3315u +#define CYREG_UDB_P1_ROUTE_HC22 0x400f3316u +#define CYREG_UDB_P1_ROUTE_HC23 0x400f3317u +#define CYREG_UDB_P1_ROUTE_HC24 0x400f3318u +#define CYREG_UDB_P1_ROUTE_HC25 0x400f3319u +#define CYREG_UDB_P1_ROUTE_HC26 0x400f331au +#define CYREG_UDB_P1_ROUTE_HC27 0x400f331bu +#define CYREG_UDB_P1_ROUTE_HC28 0x400f331cu +#define CYREG_UDB_P1_ROUTE_HC29 0x400f331du +#define CYREG_UDB_P1_ROUTE_HC30 0x400f331eu +#define CYREG_UDB_P1_ROUTE_HC31 0x400f331fu +#define CYREG_UDB_P1_ROUTE_HC32 0x400f3320u +#define CYREG_UDB_P1_ROUTE_HC33 0x400f3321u +#define CYREG_UDB_P1_ROUTE_HC34 0x400f3322u +#define CYREG_UDB_P1_ROUTE_HC35 0x400f3323u +#define CYREG_UDB_P1_ROUTE_HC36 0x400f3324u +#define CYREG_UDB_P1_ROUTE_HC37 0x400f3325u +#define CYREG_UDB_P1_ROUTE_HC38 0x400f3326u +#define CYREG_UDB_P1_ROUTE_HC39 0x400f3327u +#define CYREG_UDB_P1_ROUTE_HC40 0x400f3328u +#define CYREG_UDB_P1_ROUTE_HC41 0x400f3329u +#define CYREG_UDB_P1_ROUTE_HC42 0x400f332au +#define CYREG_UDB_P1_ROUTE_HC43 0x400f332bu +#define CYREG_UDB_P1_ROUTE_HC44 0x400f332cu +#define CYREG_UDB_P1_ROUTE_HC45 0x400f332du +#define CYREG_UDB_P1_ROUTE_HC46 0x400f332eu +#define CYREG_UDB_P1_ROUTE_HC47 0x400f332fu +#define CYREG_UDB_P1_ROUTE_HC48 0x400f3330u +#define CYREG_UDB_P1_ROUTE_HC49 0x400f3331u +#define CYREG_UDB_P1_ROUTE_HC50 0x400f3332u +#define CYREG_UDB_P1_ROUTE_HC51 0x400f3333u +#define CYREG_UDB_P1_ROUTE_HC52 0x400f3334u +#define CYREG_UDB_P1_ROUTE_HC53 0x400f3335u +#define CYREG_UDB_P1_ROUTE_HC54 0x400f3336u +#define CYREG_UDB_P1_ROUTE_HC55 0x400f3337u +#define CYREG_UDB_P1_ROUTE_HC56 0x400f3338u +#define CYREG_UDB_P1_ROUTE_HC57 0x400f3339u +#define CYREG_UDB_P1_ROUTE_HC58 0x400f333au +#define CYREG_UDB_P1_ROUTE_HC59 0x400f333bu +#define CYREG_UDB_P1_ROUTE_HC60 0x400f333cu +#define CYREG_UDB_P1_ROUTE_HC61 0x400f333du +#define CYREG_UDB_P1_ROUTE_HC62 0x400f333eu +#define CYREG_UDB_P1_ROUTE_HC63 0x400f333fu +#define CYREG_UDB_P1_ROUTE_HC64 0x400f3340u +#define CYREG_UDB_P1_ROUTE_HC65 0x400f3341u +#define CYREG_UDB_P1_ROUTE_HC66 0x400f3342u +#define CYREG_UDB_P1_ROUTE_HC67 0x400f3343u +#define CYREG_UDB_P1_ROUTE_HC68 0x400f3344u +#define CYREG_UDB_P1_ROUTE_HC69 0x400f3345u +#define CYREG_UDB_P1_ROUTE_HC70 0x400f3346u +#define CYREG_UDB_P1_ROUTE_HC71 0x400f3347u +#define CYREG_UDB_P1_ROUTE_HC72 0x400f3348u +#define CYREG_UDB_P1_ROUTE_HC73 0x400f3349u +#define CYREG_UDB_P1_ROUTE_HC74 0x400f334au +#define CYREG_UDB_P1_ROUTE_HC75 0x400f334bu +#define CYREG_UDB_P1_ROUTE_HC76 0x400f334cu +#define CYREG_UDB_P1_ROUTE_HC77 0x400f334du +#define CYREG_UDB_P1_ROUTE_HC78 0x400f334eu +#define CYREG_UDB_P1_ROUTE_HC79 0x400f334fu +#define CYREG_UDB_P1_ROUTE_HC80 0x400f3350u +#define CYREG_UDB_P1_ROUTE_HC81 0x400f3351u +#define CYREG_UDB_P1_ROUTE_HC82 0x400f3352u +#define CYREG_UDB_P1_ROUTE_HC83 0x400f3353u +#define CYREG_UDB_P1_ROUTE_HC84 0x400f3354u +#define CYREG_UDB_P1_ROUTE_HC85 0x400f3355u +#define CYREG_UDB_P1_ROUTE_HC86 0x400f3356u +#define CYREG_UDB_P1_ROUTE_HC87 0x400f3357u +#define CYREG_UDB_P1_ROUTE_HC88 0x400f3358u +#define CYREG_UDB_P1_ROUTE_HC89 0x400f3359u +#define CYREG_UDB_P1_ROUTE_HC90 0x400f335au +#define CYREG_UDB_P1_ROUTE_HC91 0x400f335bu +#define CYREG_UDB_P1_ROUTE_HC92 0x400f335cu +#define CYREG_UDB_P1_ROUTE_HC93 0x400f335du +#define CYREG_UDB_P1_ROUTE_HC94 0x400f335eu +#define CYREG_UDB_P1_ROUTE_HC95 0x400f335fu +#define CYREG_UDB_P1_ROUTE_HC96 0x400f3360u +#define CYREG_UDB_P1_ROUTE_HC97 0x400f3361u +#define CYREG_UDB_P1_ROUTE_HC98 0x400f3362u +#define CYREG_UDB_P1_ROUTE_HC99 0x400f3363u +#define CYREG_UDB_P1_ROUTE_HC100 0x400f3364u +#define CYREG_UDB_P1_ROUTE_HC101 0x400f3365u +#define CYREG_UDB_P1_ROUTE_HC102 0x400f3366u +#define CYREG_UDB_P1_ROUTE_HC103 0x400f3367u +#define CYREG_UDB_P1_ROUTE_HC104 0x400f3368u +#define CYREG_UDB_P1_ROUTE_HC105 0x400f3369u +#define CYREG_UDB_P1_ROUTE_HC106 0x400f336au +#define CYREG_UDB_P1_ROUTE_HC107 0x400f336bu +#define CYREG_UDB_P1_ROUTE_HC108 0x400f336cu +#define CYREG_UDB_P1_ROUTE_HC109 0x400f336du +#define CYREG_UDB_P1_ROUTE_HC110 0x400f336eu +#define CYREG_UDB_P1_ROUTE_HC111 0x400f336fu +#define CYREG_UDB_P1_ROUTE_HC112 0x400f3370u +#define CYREG_UDB_P1_ROUTE_HC113 0x400f3371u +#define CYREG_UDB_P1_ROUTE_HC114 0x400f3372u +#define CYREG_UDB_P1_ROUTE_HC115 0x400f3373u +#define CYREG_UDB_P1_ROUTE_HC116 0x400f3374u +#define CYREG_UDB_P1_ROUTE_HC117 0x400f3375u +#define CYREG_UDB_P1_ROUTE_HC118 0x400f3376u +#define CYREG_UDB_P1_ROUTE_HC119 0x400f3377u +#define CYREG_UDB_P1_ROUTE_HC120 0x400f3378u +#define CYREG_UDB_P1_ROUTE_HC121 0x400f3379u +#define CYREG_UDB_P1_ROUTE_HC122 0x400f337au +#define CYREG_UDB_P1_ROUTE_HC123 0x400f337bu +#define CYREG_UDB_P1_ROUTE_HC124 0x400f337cu +#define CYREG_UDB_P1_ROUTE_HC125 0x400f337du +#define CYREG_UDB_P1_ROUTE_HC126 0x400f337eu +#define CYREG_UDB_P1_ROUTE_HC127 0x400f337fu +#define CYREG_UDB_P1_ROUTE_HV_L0 0x400f3380u +#define CYREG_UDB_P1_ROUTE_HV_L1 0x400f3381u +#define CYREG_UDB_P1_ROUTE_HV_L2 0x400f3382u +#define CYREG_UDB_P1_ROUTE_HV_L3 0x400f3383u +#define CYREG_UDB_P1_ROUTE_HV_L4 0x400f3384u +#define CYREG_UDB_P1_ROUTE_HV_L5 0x400f3385u +#define CYREG_UDB_P1_ROUTE_HV_L6 0x400f3386u +#define CYREG_UDB_P1_ROUTE_HV_L7 0x400f3387u +#define CYREG_UDB_P1_ROUTE_HV_L8 0x400f3388u +#define CYREG_UDB_P1_ROUTE_HV_L9 0x400f3389u +#define CYREG_UDB_P1_ROUTE_HV_L10 0x400f338au +#define CYREG_UDB_P1_ROUTE_HV_L11 0x400f338bu +#define CYREG_UDB_P1_ROUTE_HV_L12 0x400f338cu +#define CYREG_UDB_P1_ROUTE_HV_L13 0x400f338du +#define CYREG_UDB_P1_ROUTE_HV_L14 0x400f338eu +#define CYREG_UDB_P1_ROUTE_HV_L15 0x400f338fu +#define CYREG_UDB_P1_ROUTE_HS0 0x400f3390u +#define CYREG_UDB_P1_ROUTE_HS1 0x400f3391u +#define CYREG_UDB_P1_ROUTE_HS2 0x400f3392u +#define CYREG_UDB_P1_ROUTE_HS3 0x400f3393u +#define CYREG_UDB_P1_ROUTE_HS4 0x400f3394u +#define CYREG_UDB_P1_ROUTE_HS5 0x400f3395u +#define CYREG_UDB_P1_ROUTE_HS6 0x400f3396u +#define CYREG_UDB_P1_ROUTE_HS7 0x400f3397u +#define CYREG_UDB_P1_ROUTE_HS8 0x400f3398u +#define CYREG_UDB_P1_ROUTE_HS9 0x400f3399u +#define CYREG_UDB_P1_ROUTE_HS10 0x400f339au +#define CYREG_UDB_P1_ROUTE_HS11 0x400f339bu +#define CYREG_UDB_P1_ROUTE_HS12 0x400f339cu +#define CYREG_UDB_P1_ROUTE_HS13 0x400f339du +#define CYREG_UDB_P1_ROUTE_HS14 0x400f339eu +#define CYREG_UDB_P1_ROUTE_HS15 0x400f339fu +#define CYREG_UDB_P1_ROUTE_HS16 0x400f33a0u +#define CYREG_UDB_P1_ROUTE_HS17 0x400f33a1u +#define CYREG_UDB_P1_ROUTE_HS18 0x400f33a2u +#define CYREG_UDB_P1_ROUTE_HS19 0x400f33a3u +#define CYREG_UDB_P1_ROUTE_HS20 0x400f33a4u +#define CYREG_UDB_P1_ROUTE_HS21 0x400f33a5u +#define CYREG_UDB_P1_ROUTE_HS22 0x400f33a6u +#define CYREG_UDB_P1_ROUTE_HS23 0x400f33a7u +#define CYREG_UDB_P1_ROUTE_HV_R0 0x400f33a8u +#define CYREG_UDB_P1_ROUTE_HV_R1 0x400f33a9u +#define CYREG_UDB_P1_ROUTE_HV_R2 0x400f33aau +#define CYREG_UDB_P1_ROUTE_HV_R3 0x400f33abu +#define CYREG_UDB_P1_ROUTE_HV_R4 0x400f33acu +#define CYREG_UDB_P1_ROUTE_HV_R5 0x400f33adu +#define CYREG_UDB_P1_ROUTE_HV_R6 0x400f33aeu +#define CYREG_UDB_P1_ROUTE_HV_R7 0x400f33afu +#define CYREG_UDB_P1_ROUTE_HV_R8 0x400f33b0u +#define CYREG_UDB_P1_ROUTE_HV_R9 0x400f33b1u +#define CYREG_UDB_P1_ROUTE_HV_R10 0x400f33b2u +#define CYREG_UDB_P1_ROUTE_HV_R11 0x400f33b3u +#define CYREG_UDB_P1_ROUTE_HV_R12 0x400f33b4u +#define CYREG_UDB_P1_ROUTE_HV_R13 0x400f33b5u +#define CYREG_UDB_P1_ROUTE_HV_R14 0x400f33b6u +#define CYREG_UDB_P1_ROUTE_HV_R15 0x400f33b7u +#define CYREG_UDB_P1_ROUTE_PLD0IN0 0x400f33c0u +#define CYREG_UDB_P1_ROUTE_PLD0IN1 0x400f33c2u +#define CYREG_UDB_P1_ROUTE_PLD0IN2 0x400f33c4u +#define CYREG_UDB_P1_ROUTE_PLD1IN0 0x400f33cau +#define CYREG_UDB_P1_ROUTE_PLD1IN1 0x400f33ccu +#define CYREG_UDB_P1_ROUTE_PLD1IN2 0x400f33ceu +#define CYREG_UDB_P1_ROUTE_DPIN0 0x400f33d0u +#define CYREG_UDB_P1_ROUTE_DPIN1 0x400f33d2u +#define CYREG_UDB_P1_ROUTE_SCIN 0x400f33d6u +#define CYREG_UDB_P1_ROUTE_SCIOIN 0x400f33d8u +#define CYREG_UDB_P1_ROUTE_RCIN 0x400f33deu +#define CYREG_UDB_P1_ROUTE_VS0 0x400f33e0u +#define CYREG_UDB_P1_ROUTE_VS1 0x400f33e2u +#define CYREG_UDB_P1_ROUTE_VS2 0x400f33e4u +#define CYREG_UDB_P1_ROUTE_VS3 0x400f33e6u +#define CYREG_UDB_P1_ROUTE_VS4 0x400f33e8u +#define CYREG_UDB_P1_ROUTE_VS5 0x400f33eau +#define CYREG_UDB_P1_ROUTE_VS6 0x400f33ecu +#define CYREG_UDB_P1_ROUTE_VS7 0x400f33eeu +#define CYDEV_UDB_DSI0_BASE 0x400f4000u +#define CYDEV_UDB_DSI0_SIZE 0x00000100u +#define CYREG_UDB_DSI0_HC0 0x400f4000u +#define CYFLD_UDB_DSI_HC_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_HC_BYTE__SIZE 0x00000008u +#define CYREG_UDB_DSI0_HC1 0x400f4001u +#define CYREG_UDB_DSI0_HC2 0x400f4002u +#define CYREG_UDB_DSI0_HC3 0x400f4003u +#define CYREG_UDB_DSI0_HC4 0x400f4004u +#define CYREG_UDB_DSI0_HC5 0x400f4005u +#define CYREG_UDB_DSI0_HC6 0x400f4006u +#define CYREG_UDB_DSI0_HC7 0x400f4007u +#define CYREG_UDB_DSI0_HC8 0x400f4008u +#define CYREG_UDB_DSI0_HC9 0x400f4009u +#define CYREG_UDB_DSI0_HC10 0x400f400au +#define CYREG_UDB_DSI0_HC11 0x400f400bu +#define CYREG_UDB_DSI0_HC12 0x400f400cu +#define CYREG_UDB_DSI0_HC13 0x400f400du +#define CYREG_UDB_DSI0_HC14 0x400f400eu +#define CYREG_UDB_DSI0_HC15 0x400f400fu +#define CYREG_UDB_DSI0_HC16 0x400f4010u +#define CYREG_UDB_DSI0_HC17 0x400f4011u +#define CYREG_UDB_DSI0_HC18 0x400f4012u +#define CYREG_UDB_DSI0_HC19 0x400f4013u +#define CYREG_UDB_DSI0_HC20 0x400f4014u +#define CYREG_UDB_DSI0_HC21 0x400f4015u +#define CYREG_UDB_DSI0_HC22 0x400f4016u +#define CYREG_UDB_DSI0_HC23 0x400f4017u +#define CYREG_UDB_DSI0_HC24 0x400f4018u +#define CYREG_UDB_DSI0_HC25 0x400f4019u +#define CYREG_UDB_DSI0_HC26 0x400f401au +#define CYREG_UDB_DSI0_HC27 0x400f401bu +#define CYREG_UDB_DSI0_HC28 0x400f401cu +#define CYREG_UDB_DSI0_HC29 0x400f401du +#define CYREG_UDB_DSI0_HC30 0x400f401eu +#define CYREG_UDB_DSI0_HC31 0x400f401fu +#define CYREG_UDB_DSI0_HC32 0x400f4020u +#define CYREG_UDB_DSI0_HC33 0x400f4021u +#define CYREG_UDB_DSI0_HC34 0x400f4022u +#define CYREG_UDB_DSI0_HC35 0x400f4023u +#define CYREG_UDB_DSI0_HC36 0x400f4024u +#define CYREG_UDB_DSI0_HC37 0x400f4025u +#define CYREG_UDB_DSI0_HC38 0x400f4026u +#define CYREG_UDB_DSI0_HC39 0x400f4027u +#define CYREG_UDB_DSI0_HC40 0x400f4028u +#define CYREG_UDB_DSI0_HC41 0x400f4029u +#define CYREG_UDB_DSI0_HC42 0x400f402au +#define CYREG_UDB_DSI0_HC43 0x400f402bu +#define CYREG_UDB_DSI0_HC44 0x400f402cu +#define CYREG_UDB_DSI0_HC45 0x400f402du +#define CYREG_UDB_DSI0_HC46 0x400f402eu +#define CYREG_UDB_DSI0_HC47 0x400f402fu +#define CYREG_UDB_DSI0_HC48 0x400f4030u +#define CYREG_UDB_DSI0_HC49 0x400f4031u +#define CYREG_UDB_DSI0_HC50 0x400f4032u +#define CYREG_UDB_DSI0_HC51 0x400f4033u +#define CYREG_UDB_DSI0_HC52 0x400f4034u +#define CYREG_UDB_DSI0_HC53 0x400f4035u +#define CYREG_UDB_DSI0_HC54 0x400f4036u +#define CYREG_UDB_DSI0_HC55 0x400f4037u +#define CYREG_UDB_DSI0_HC56 0x400f4038u +#define CYREG_UDB_DSI0_HC57 0x400f4039u +#define CYREG_UDB_DSI0_HC58 0x400f403au +#define CYREG_UDB_DSI0_HC59 0x400f403bu +#define CYREG_UDB_DSI0_HC60 0x400f403cu +#define CYREG_UDB_DSI0_HC61 0x400f403du +#define CYREG_UDB_DSI0_HC62 0x400f403eu +#define CYREG_UDB_DSI0_HC63 0x400f403fu +#define CYREG_UDB_DSI0_HC64 0x400f4040u +#define CYREG_UDB_DSI0_HC65 0x400f4041u +#define CYREG_UDB_DSI0_HC66 0x400f4042u +#define CYREG_UDB_DSI0_HC67 0x400f4043u +#define CYREG_UDB_DSI0_HC68 0x400f4044u +#define CYREG_UDB_DSI0_HC69 0x400f4045u +#define CYREG_UDB_DSI0_HC70 0x400f4046u +#define CYREG_UDB_DSI0_HC71 0x400f4047u +#define CYREG_UDB_DSI0_HC72 0x400f4048u +#define CYREG_UDB_DSI0_HC73 0x400f4049u +#define CYREG_UDB_DSI0_HC74 0x400f404au +#define CYREG_UDB_DSI0_HC75 0x400f404bu +#define CYREG_UDB_DSI0_HC76 0x400f404cu +#define CYREG_UDB_DSI0_HC77 0x400f404du +#define CYREG_UDB_DSI0_HC78 0x400f404eu +#define CYREG_UDB_DSI0_HC79 0x400f404fu +#define CYREG_UDB_DSI0_HC80 0x400f4050u +#define CYREG_UDB_DSI0_HC81 0x400f4051u +#define CYREG_UDB_DSI0_HC82 0x400f4052u +#define CYREG_UDB_DSI0_HC83 0x400f4053u +#define CYREG_UDB_DSI0_HC84 0x400f4054u +#define CYREG_UDB_DSI0_HC85 0x400f4055u +#define CYREG_UDB_DSI0_HC86 0x400f4056u +#define CYREG_UDB_DSI0_HC87 0x400f4057u +#define CYREG_UDB_DSI0_HC88 0x400f4058u +#define CYREG_UDB_DSI0_HC89 0x400f4059u +#define CYREG_UDB_DSI0_HC90 0x400f405au +#define CYREG_UDB_DSI0_HC91 0x400f405bu +#define CYREG_UDB_DSI0_HC92 0x400f405cu +#define CYREG_UDB_DSI0_HC93 0x400f405du +#define CYREG_UDB_DSI0_HC94 0x400f405eu +#define CYREG_UDB_DSI0_HC95 0x400f405fu +#define CYREG_UDB_DSI0_HC96 0x400f4060u +#define CYREG_UDB_DSI0_HC97 0x400f4061u +#define CYREG_UDB_DSI0_HC98 0x400f4062u +#define CYREG_UDB_DSI0_HC99 0x400f4063u +#define CYREG_UDB_DSI0_HC100 0x400f4064u +#define CYREG_UDB_DSI0_HC101 0x400f4065u +#define CYREG_UDB_DSI0_HC102 0x400f4066u +#define CYREG_UDB_DSI0_HC103 0x400f4067u +#define CYREG_UDB_DSI0_HC104 0x400f4068u +#define CYREG_UDB_DSI0_HC105 0x400f4069u +#define CYREG_UDB_DSI0_HC106 0x400f406au +#define CYREG_UDB_DSI0_HC107 0x400f406bu +#define CYREG_UDB_DSI0_HC108 0x400f406cu +#define CYREG_UDB_DSI0_HC109 0x400f406du +#define CYREG_UDB_DSI0_HC110 0x400f406eu +#define CYREG_UDB_DSI0_HC111 0x400f406fu +#define CYREG_UDB_DSI0_HC112 0x400f4070u +#define CYREG_UDB_DSI0_HC113 0x400f4071u +#define CYREG_UDB_DSI0_HC114 0x400f4072u +#define CYREG_UDB_DSI0_HC115 0x400f4073u +#define CYREG_UDB_DSI0_HC116 0x400f4074u +#define CYREG_UDB_DSI0_HC117 0x400f4075u +#define CYREG_UDB_DSI0_HC118 0x400f4076u +#define CYREG_UDB_DSI0_HC119 0x400f4077u +#define CYREG_UDB_DSI0_HC120 0x400f4078u +#define CYREG_UDB_DSI0_HC121 0x400f4079u +#define CYREG_UDB_DSI0_HC122 0x400f407au +#define CYREG_UDB_DSI0_HC123 0x400f407bu +#define CYREG_UDB_DSI0_HC124 0x400f407cu +#define CYREG_UDB_DSI0_HC125 0x400f407du +#define CYREG_UDB_DSI0_HC126 0x400f407eu +#define CYREG_UDB_DSI0_HC127 0x400f407fu +#define CYREG_UDB_DSI0_HV_L0 0x400f4080u +#define CYFLD_UDB_DSI_HV_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_HV_BYTE__SIZE 0x00000008u +#define CYREG_UDB_DSI0_HV_L1 0x400f4081u +#define CYREG_UDB_DSI0_HV_L2 0x400f4082u +#define CYREG_UDB_DSI0_HV_L3 0x400f4083u +#define CYREG_UDB_DSI0_HV_L4 0x400f4084u +#define CYREG_UDB_DSI0_HV_L5 0x400f4085u +#define CYREG_UDB_DSI0_HV_L6 0x400f4086u +#define CYREG_UDB_DSI0_HV_L7 0x400f4087u +#define CYREG_UDB_DSI0_HV_L8 0x400f4088u +#define CYREG_UDB_DSI0_HV_L9 0x400f4089u +#define CYREG_UDB_DSI0_HV_L10 0x400f408au +#define CYREG_UDB_DSI0_HV_L11 0x400f408bu +#define CYREG_UDB_DSI0_HV_L12 0x400f408cu +#define CYREG_UDB_DSI0_HV_L13 0x400f408du +#define CYREG_UDB_DSI0_HV_L14 0x400f408eu +#define CYREG_UDB_DSI0_HV_L15 0x400f408fu +#define CYREG_UDB_DSI0_HS0 0x400f4090u +#define CYFLD_UDB_DSI_HS_BYTE__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_HS_BYTE__SIZE 0x00000008u +#define CYREG_UDB_DSI0_HS1 0x400f4091u +#define CYREG_UDB_DSI0_HS2 0x400f4092u +#define CYREG_UDB_DSI0_HS3 0x400f4093u +#define CYREG_UDB_DSI0_HS4 0x400f4094u +#define CYREG_UDB_DSI0_HS5 0x400f4095u +#define CYREG_UDB_DSI0_HS6 0x400f4096u +#define CYREG_UDB_DSI0_HS7 0x400f4097u +#define CYREG_UDB_DSI0_HS8 0x400f4098u +#define CYREG_UDB_DSI0_HS9 0x400f4099u +#define CYREG_UDB_DSI0_HS10 0x400f409au +#define CYREG_UDB_DSI0_HS11 0x400f409bu +#define CYREG_UDB_DSI0_HS12 0x400f409cu +#define CYREG_UDB_DSI0_HS13 0x400f409du +#define CYREG_UDB_DSI0_HS14 0x400f409eu +#define CYREG_UDB_DSI0_HS15 0x400f409fu +#define CYREG_UDB_DSI0_HS16 0x400f40a0u +#define CYREG_UDB_DSI0_HS17 0x400f40a1u +#define CYREG_UDB_DSI0_HS18 0x400f40a2u +#define CYREG_UDB_DSI0_HS19 0x400f40a3u +#define CYREG_UDB_DSI0_HS20 0x400f40a4u +#define CYREG_UDB_DSI0_HS21 0x400f40a5u +#define CYREG_UDB_DSI0_HS22 0x400f40a6u +#define CYREG_UDB_DSI0_HS23 0x400f40a7u +#define CYREG_UDB_DSI0_HV_R0 0x400f40a8u +#define CYREG_UDB_DSI0_HV_R1 0x400f40a9u +#define CYREG_UDB_DSI0_HV_R2 0x400f40aau +#define CYREG_UDB_DSI0_HV_R3 0x400f40abu +#define CYREG_UDB_DSI0_HV_R4 0x400f40acu +#define CYREG_UDB_DSI0_HV_R5 0x400f40adu +#define CYREG_UDB_DSI0_HV_R6 0x400f40aeu +#define CYREG_UDB_DSI0_HV_R7 0x400f40afu +#define CYREG_UDB_DSI0_HV_R8 0x400f40b0u +#define CYREG_UDB_DSI0_HV_R9 0x400f40b1u +#define CYREG_UDB_DSI0_HV_R10 0x400f40b2u +#define CYREG_UDB_DSI0_HV_R11 0x400f40b3u +#define CYREG_UDB_DSI0_HV_R12 0x400f40b4u +#define CYREG_UDB_DSI0_HV_R13 0x400f40b5u +#define CYREG_UDB_DSI0_HV_R14 0x400f40b6u +#define CYREG_UDB_DSI0_HV_R15 0x400f40b7u +#define CYREG_UDB_DSI0_DSIINP0 0x400f40c0u +#define CYFLD_UDB_DSI_PI_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_PI_TOP__SIZE 0x00000004u +#define CYFLD_UDB_DSI_PI_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_DSI_PI_BOT__SIZE 0x00000004u +#define CYREG_UDB_DSI0_DSIINP1 0x400f40c2u +#define CYREG_UDB_DSI0_DSIINP2 0x400f40c4u +#define CYREG_UDB_DSI0_DSIINP3 0x400f40c6u +#define CYREG_UDB_DSI0_DSIINP4 0x400f40c8u +#define CYREG_UDB_DSI0_DSIINP5 0x400f40cau +#define CYREG_UDB_DSI0_DSIOUTP0 0x400f40ccu +#define CYREG_UDB_DSI0_DSIOUTP1 0x400f40ceu +#define CYREG_UDB_DSI0_DSIOUTP2 0x400f40d0u +#define CYREG_UDB_DSI0_DSIOUTP3 0x400f40d2u +#define CYREG_UDB_DSI0_DSIOUTT0 0x400f40d4u +#define CYREG_UDB_DSI0_DSIOUTT1 0x400f40d6u +#define CYREG_UDB_DSI0_DSIOUTT2 0x400f40d8u +#define CYREG_UDB_DSI0_DSIOUTT3 0x400f40dau +#define CYREG_UDB_DSI0_DSIOUTT4 0x400f40dcu +#define CYREG_UDB_DSI0_DSIOUTT5 0x400f40deu +#define CYREG_UDB_DSI0_VS0 0x400f40e0u +#define CYFLD_UDB_DSI_VS_TOP__OFFSET 0x00000000u +#define CYFLD_UDB_DSI_VS_TOP__SIZE 0x00000004u +#define CYFLD_UDB_DSI_VS_BOT__OFFSET 0x00000004u +#define CYFLD_UDB_DSI_VS_BOT__SIZE 0x00000004u +#define CYREG_UDB_DSI0_VS1 0x400f40e2u +#define CYREG_UDB_DSI0_VS2 0x400f40e4u +#define CYREG_UDB_DSI0_VS3 0x400f40e6u +#define CYREG_UDB_DSI0_VS4 0x400f40e8u +#define CYREG_UDB_DSI0_VS5 0x400f40eau +#define CYREG_UDB_DSI0_VS6 0x400f40ecu +#define CYREG_UDB_DSI0_VS7 0x400f40eeu +#define CYDEV_UDB_DSI1_BASE 0x400f4100u +#define CYDEV_UDB_DSI1_SIZE 0x00000100u +#define CYREG_UDB_DSI1_HC0 0x400f4100u +#define CYREG_UDB_DSI1_HC1 0x400f4101u +#define CYREG_UDB_DSI1_HC2 0x400f4102u +#define CYREG_UDB_DSI1_HC3 0x400f4103u +#define CYREG_UDB_DSI1_HC4 0x400f4104u +#define CYREG_UDB_DSI1_HC5 0x400f4105u +#define CYREG_UDB_DSI1_HC6 0x400f4106u +#define CYREG_UDB_DSI1_HC7 0x400f4107u +#define CYREG_UDB_DSI1_HC8 0x400f4108u +#define CYREG_UDB_DSI1_HC9 0x400f4109u +#define CYREG_UDB_DSI1_HC10 0x400f410au +#define CYREG_UDB_DSI1_HC11 0x400f410bu +#define CYREG_UDB_DSI1_HC12 0x400f410cu +#define CYREG_UDB_DSI1_HC13 0x400f410du +#define CYREG_UDB_DSI1_HC14 0x400f410eu +#define CYREG_UDB_DSI1_HC15 0x400f410fu +#define CYREG_UDB_DSI1_HC16 0x400f4110u +#define CYREG_UDB_DSI1_HC17 0x400f4111u +#define CYREG_UDB_DSI1_HC18 0x400f4112u +#define CYREG_UDB_DSI1_HC19 0x400f4113u +#define CYREG_UDB_DSI1_HC20 0x400f4114u +#define CYREG_UDB_DSI1_HC21 0x400f4115u +#define CYREG_UDB_DSI1_HC22 0x400f4116u +#define CYREG_UDB_DSI1_HC23 0x400f4117u +#define CYREG_UDB_DSI1_HC24 0x400f4118u +#define CYREG_UDB_DSI1_HC25 0x400f4119u +#define CYREG_UDB_DSI1_HC26 0x400f411au +#define CYREG_UDB_DSI1_HC27 0x400f411bu +#define CYREG_UDB_DSI1_HC28 0x400f411cu +#define CYREG_UDB_DSI1_HC29 0x400f411du +#define CYREG_UDB_DSI1_HC30 0x400f411eu +#define CYREG_UDB_DSI1_HC31 0x400f411fu +#define CYREG_UDB_DSI1_HC32 0x400f4120u +#define CYREG_UDB_DSI1_HC33 0x400f4121u +#define CYREG_UDB_DSI1_HC34 0x400f4122u +#define CYREG_UDB_DSI1_HC35 0x400f4123u +#define CYREG_UDB_DSI1_HC36 0x400f4124u +#define CYREG_UDB_DSI1_HC37 0x400f4125u +#define CYREG_UDB_DSI1_HC38 0x400f4126u +#define CYREG_UDB_DSI1_HC39 0x400f4127u +#define CYREG_UDB_DSI1_HC40 0x400f4128u +#define CYREG_UDB_DSI1_HC41 0x400f4129u +#define CYREG_UDB_DSI1_HC42 0x400f412au +#define CYREG_UDB_DSI1_HC43 0x400f412bu +#define CYREG_UDB_DSI1_HC44 0x400f412cu +#define CYREG_UDB_DSI1_HC45 0x400f412du +#define CYREG_UDB_DSI1_HC46 0x400f412eu +#define CYREG_UDB_DSI1_HC47 0x400f412fu +#define CYREG_UDB_DSI1_HC48 0x400f4130u +#define CYREG_UDB_DSI1_HC49 0x400f4131u +#define CYREG_UDB_DSI1_HC50 0x400f4132u +#define CYREG_UDB_DSI1_HC51 0x400f4133u +#define CYREG_UDB_DSI1_HC52 0x400f4134u +#define CYREG_UDB_DSI1_HC53 0x400f4135u +#define CYREG_UDB_DSI1_HC54 0x400f4136u +#define CYREG_UDB_DSI1_HC55 0x400f4137u +#define CYREG_UDB_DSI1_HC56 0x400f4138u +#define CYREG_UDB_DSI1_HC57 0x400f4139u +#define CYREG_UDB_DSI1_HC58 0x400f413au +#define CYREG_UDB_DSI1_HC59 0x400f413bu +#define CYREG_UDB_DSI1_HC60 0x400f413cu +#define CYREG_UDB_DSI1_HC61 0x400f413du +#define CYREG_UDB_DSI1_HC62 0x400f413eu +#define CYREG_UDB_DSI1_HC63 0x400f413fu +#define CYREG_UDB_DSI1_HC64 0x400f4140u +#define CYREG_UDB_DSI1_HC65 0x400f4141u +#define CYREG_UDB_DSI1_HC66 0x400f4142u +#define CYREG_UDB_DSI1_HC67 0x400f4143u +#define CYREG_UDB_DSI1_HC68 0x400f4144u +#define CYREG_UDB_DSI1_HC69 0x400f4145u +#define CYREG_UDB_DSI1_HC70 0x400f4146u +#define CYREG_UDB_DSI1_HC71 0x400f4147u +#define CYREG_UDB_DSI1_HC72 0x400f4148u +#define CYREG_UDB_DSI1_HC73 0x400f4149u +#define CYREG_UDB_DSI1_HC74 0x400f414au +#define CYREG_UDB_DSI1_HC75 0x400f414bu +#define CYREG_UDB_DSI1_HC76 0x400f414cu +#define CYREG_UDB_DSI1_HC77 0x400f414du +#define CYREG_UDB_DSI1_HC78 0x400f414eu +#define CYREG_UDB_DSI1_HC79 0x400f414fu +#define CYREG_UDB_DSI1_HC80 0x400f4150u +#define CYREG_UDB_DSI1_HC81 0x400f4151u +#define CYREG_UDB_DSI1_HC82 0x400f4152u +#define CYREG_UDB_DSI1_HC83 0x400f4153u +#define CYREG_UDB_DSI1_HC84 0x400f4154u +#define CYREG_UDB_DSI1_HC85 0x400f4155u +#define CYREG_UDB_DSI1_HC86 0x400f4156u +#define CYREG_UDB_DSI1_HC87 0x400f4157u +#define CYREG_UDB_DSI1_HC88 0x400f4158u +#define CYREG_UDB_DSI1_HC89 0x400f4159u +#define CYREG_UDB_DSI1_HC90 0x400f415au +#define CYREG_UDB_DSI1_HC91 0x400f415bu +#define CYREG_UDB_DSI1_HC92 0x400f415cu +#define CYREG_UDB_DSI1_HC93 0x400f415du +#define CYREG_UDB_DSI1_HC94 0x400f415eu +#define CYREG_UDB_DSI1_HC95 0x400f415fu +#define CYREG_UDB_DSI1_HC96 0x400f4160u +#define CYREG_UDB_DSI1_HC97 0x400f4161u +#define CYREG_UDB_DSI1_HC98 0x400f4162u +#define CYREG_UDB_DSI1_HC99 0x400f4163u +#define CYREG_UDB_DSI1_HC100 0x400f4164u +#define CYREG_UDB_DSI1_HC101 0x400f4165u +#define CYREG_UDB_DSI1_HC102 0x400f4166u +#define CYREG_UDB_DSI1_HC103 0x400f4167u +#define CYREG_UDB_DSI1_HC104 0x400f4168u +#define CYREG_UDB_DSI1_HC105 0x400f4169u +#define CYREG_UDB_DSI1_HC106 0x400f416au +#define CYREG_UDB_DSI1_HC107 0x400f416bu +#define CYREG_UDB_DSI1_HC108 0x400f416cu +#define CYREG_UDB_DSI1_HC109 0x400f416du +#define CYREG_UDB_DSI1_HC110 0x400f416eu +#define CYREG_UDB_DSI1_HC111 0x400f416fu +#define CYREG_UDB_DSI1_HC112 0x400f4170u +#define CYREG_UDB_DSI1_HC113 0x400f4171u +#define CYREG_UDB_DSI1_HC114 0x400f4172u +#define CYREG_UDB_DSI1_HC115 0x400f4173u +#define CYREG_UDB_DSI1_HC116 0x400f4174u +#define CYREG_UDB_DSI1_HC117 0x400f4175u +#define CYREG_UDB_DSI1_HC118 0x400f4176u +#define CYREG_UDB_DSI1_HC119 0x400f4177u +#define CYREG_UDB_DSI1_HC120 0x400f4178u +#define CYREG_UDB_DSI1_HC121 0x400f4179u +#define CYREG_UDB_DSI1_HC122 0x400f417au +#define CYREG_UDB_DSI1_HC123 0x400f417bu +#define CYREG_UDB_DSI1_HC124 0x400f417cu +#define CYREG_UDB_DSI1_HC125 0x400f417du +#define CYREG_UDB_DSI1_HC126 0x400f417eu +#define CYREG_UDB_DSI1_HC127 0x400f417fu +#define CYREG_UDB_DSI1_HV_L0 0x400f4180u +#define CYREG_UDB_DSI1_HV_L1 0x400f4181u +#define CYREG_UDB_DSI1_HV_L2 0x400f4182u +#define CYREG_UDB_DSI1_HV_L3 0x400f4183u +#define CYREG_UDB_DSI1_HV_L4 0x400f4184u +#define CYREG_UDB_DSI1_HV_L5 0x400f4185u +#define CYREG_UDB_DSI1_HV_L6 0x400f4186u +#define CYREG_UDB_DSI1_HV_L7 0x400f4187u +#define CYREG_UDB_DSI1_HV_L8 0x400f4188u +#define CYREG_UDB_DSI1_HV_L9 0x400f4189u +#define CYREG_UDB_DSI1_HV_L10 0x400f418au +#define CYREG_UDB_DSI1_HV_L11 0x400f418bu +#define CYREG_UDB_DSI1_HV_L12 0x400f418cu +#define CYREG_UDB_DSI1_HV_L13 0x400f418du +#define CYREG_UDB_DSI1_HV_L14 0x400f418eu +#define CYREG_UDB_DSI1_HV_L15 0x400f418fu +#define CYREG_UDB_DSI1_HS0 0x400f4190u +#define CYREG_UDB_DSI1_HS1 0x400f4191u +#define CYREG_UDB_DSI1_HS2 0x400f4192u +#define CYREG_UDB_DSI1_HS3 0x400f4193u +#define CYREG_UDB_DSI1_HS4 0x400f4194u +#define CYREG_UDB_DSI1_HS5 0x400f4195u +#define CYREG_UDB_DSI1_HS6 0x400f4196u +#define CYREG_UDB_DSI1_HS7 0x400f4197u +#define CYREG_UDB_DSI1_HS8 0x400f4198u +#define CYREG_UDB_DSI1_HS9 0x400f4199u +#define CYREG_UDB_DSI1_HS10 0x400f419au +#define CYREG_UDB_DSI1_HS11 0x400f419bu +#define CYREG_UDB_DSI1_HS12 0x400f419cu +#define CYREG_UDB_DSI1_HS13 0x400f419du +#define CYREG_UDB_DSI1_HS14 0x400f419eu +#define CYREG_UDB_DSI1_HS15 0x400f419fu +#define CYREG_UDB_DSI1_HS16 0x400f41a0u +#define CYREG_UDB_DSI1_HS17 0x400f41a1u +#define CYREG_UDB_DSI1_HS18 0x400f41a2u +#define CYREG_UDB_DSI1_HS19 0x400f41a3u +#define CYREG_UDB_DSI1_HS20 0x400f41a4u +#define CYREG_UDB_DSI1_HS21 0x400f41a5u +#define CYREG_UDB_DSI1_HS22 0x400f41a6u +#define CYREG_UDB_DSI1_HS23 0x400f41a7u +#define CYREG_UDB_DSI1_HV_R0 0x400f41a8u +#define CYREG_UDB_DSI1_HV_R1 0x400f41a9u +#define CYREG_UDB_DSI1_HV_R2 0x400f41aau +#define CYREG_UDB_DSI1_HV_R3 0x400f41abu +#define CYREG_UDB_DSI1_HV_R4 0x400f41acu +#define CYREG_UDB_DSI1_HV_R5 0x400f41adu +#define CYREG_UDB_DSI1_HV_R6 0x400f41aeu +#define CYREG_UDB_DSI1_HV_R7 0x400f41afu +#define CYREG_UDB_DSI1_HV_R8 0x400f41b0u +#define CYREG_UDB_DSI1_HV_R9 0x400f41b1u +#define CYREG_UDB_DSI1_HV_R10 0x400f41b2u +#define CYREG_UDB_DSI1_HV_R11 0x400f41b3u +#define CYREG_UDB_DSI1_HV_R12 0x400f41b4u +#define CYREG_UDB_DSI1_HV_R13 0x400f41b5u +#define CYREG_UDB_DSI1_HV_R14 0x400f41b6u +#define CYREG_UDB_DSI1_HV_R15 0x400f41b7u +#define CYREG_UDB_DSI1_DSIINP0 0x400f41c0u +#define CYREG_UDB_DSI1_DSIINP1 0x400f41c2u +#define CYREG_UDB_DSI1_DSIINP2 0x400f41c4u +#define CYREG_UDB_DSI1_DSIINP3 0x400f41c6u +#define CYREG_UDB_DSI1_DSIINP4 0x400f41c8u +#define CYREG_UDB_DSI1_DSIINP5 0x400f41cau +#define CYREG_UDB_DSI1_DSIOUTP0 0x400f41ccu +#define CYREG_UDB_DSI1_DSIOUTP1 0x400f41ceu +#define CYREG_UDB_DSI1_DSIOUTP2 0x400f41d0u +#define CYREG_UDB_DSI1_DSIOUTP3 0x400f41d2u +#define CYREG_UDB_DSI1_DSIOUTT0 0x400f41d4u +#define CYREG_UDB_DSI1_DSIOUTT1 0x400f41d6u +#define CYREG_UDB_DSI1_DSIOUTT2 0x400f41d8u +#define CYREG_UDB_DSI1_DSIOUTT3 0x400f41dau +#define CYREG_UDB_DSI1_DSIOUTT4 0x400f41dcu +#define CYREG_UDB_DSI1_DSIOUTT5 0x400f41deu +#define CYREG_UDB_DSI1_VS0 0x400f41e0u +#define CYREG_UDB_DSI1_VS1 0x400f41e2u +#define CYREG_UDB_DSI1_VS2 0x400f41e4u +#define CYREG_UDB_DSI1_VS3 0x400f41e6u +#define CYREG_UDB_DSI1_VS4 0x400f41e8u +#define CYREG_UDB_DSI1_VS5 0x400f41eau +#define CYREG_UDB_DSI1_VS6 0x400f41ecu +#define CYREG_UDB_DSI1_VS7 0x400f41eeu +#define CYDEV_UDB_DSI2_BASE 0x400f4200u +#define CYDEV_UDB_DSI2_SIZE 0x00000100u +#define CYREG_UDB_DSI2_HC0 0x400f4200u +#define CYREG_UDB_DSI2_HC1 0x400f4201u +#define CYREG_UDB_DSI2_HC2 0x400f4202u +#define CYREG_UDB_DSI2_HC3 0x400f4203u +#define CYREG_UDB_DSI2_HC4 0x400f4204u +#define CYREG_UDB_DSI2_HC5 0x400f4205u +#define CYREG_UDB_DSI2_HC6 0x400f4206u +#define CYREG_UDB_DSI2_HC7 0x400f4207u +#define CYREG_UDB_DSI2_HC8 0x400f4208u +#define CYREG_UDB_DSI2_HC9 0x400f4209u +#define CYREG_UDB_DSI2_HC10 0x400f420au +#define CYREG_UDB_DSI2_HC11 0x400f420bu +#define CYREG_UDB_DSI2_HC12 0x400f420cu +#define CYREG_UDB_DSI2_HC13 0x400f420du +#define CYREG_UDB_DSI2_HC14 0x400f420eu +#define CYREG_UDB_DSI2_HC15 0x400f420fu +#define CYREG_UDB_DSI2_HC16 0x400f4210u +#define CYREG_UDB_DSI2_HC17 0x400f4211u +#define CYREG_UDB_DSI2_HC18 0x400f4212u +#define CYREG_UDB_DSI2_HC19 0x400f4213u +#define CYREG_UDB_DSI2_HC20 0x400f4214u +#define CYREG_UDB_DSI2_HC21 0x400f4215u +#define CYREG_UDB_DSI2_HC22 0x400f4216u +#define CYREG_UDB_DSI2_HC23 0x400f4217u +#define CYREG_UDB_DSI2_HC24 0x400f4218u +#define CYREG_UDB_DSI2_HC25 0x400f4219u +#define CYREG_UDB_DSI2_HC26 0x400f421au +#define CYREG_UDB_DSI2_HC27 0x400f421bu +#define CYREG_UDB_DSI2_HC28 0x400f421cu +#define CYREG_UDB_DSI2_HC29 0x400f421du +#define CYREG_UDB_DSI2_HC30 0x400f421eu +#define CYREG_UDB_DSI2_HC31 0x400f421fu +#define CYREG_UDB_DSI2_HC32 0x400f4220u +#define CYREG_UDB_DSI2_HC33 0x400f4221u +#define CYREG_UDB_DSI2_HC34 0x400f4222u +#define CYREG_UDB_DSI2_HC35 0x400f4223u +#define CYREG_UDB_DSI2_HC36 0x400f4224u +#define CYREG_UDB_DSI2_HC37 0x400f4225u +#define CYREG_UDB_DSI2_HC38 0x400f4226u +#define CYREG_UDB_DSI2_HC39 0x400f4227u +#define CYREG_UDB_DSI2_HC40 0x400f4228u +#define CYREG_UDB_DSI2_HC41 0x400f4229u +#define CYREG_UDB_DSI2_HC42 0x400f422au +#define CYREG_UDB_DSI2_HC43 0x400f422bu +#define CYREG_UDB_DSI2_HC44 0x400f422cu +#define CYREG_UDB_DSI2_HC45 0x400f422du +#define CYREG_UDB_DSI2_HC46 0x400f422eu +#define CYREG_UDB_DSI2_HC47 0x400f422fu +#define CYREG_UDB_DSI2_HC48 0x400f4230u +#define CYREG_UDB_DSI2_HC49 0x400f4231u +#define CYREG_UDB_DSI2_HC50 0x400f4232u +#define CYREG_UDB_DSI2_HC51 0x400f4233u +#define CYREG_UDB_DSI2_HC52 0x400f4234u +#define CYREG_UDB_DSI2_HC53 0x400f4235u +#define CYREG_UDB_DSI2_HC54 0x400f4236u +#define CYREG_UDB_DSI2_HC55 0x400f4237u +#define CYREG_UDB_DSI2_HC56 0x400f4238u +#define CYREG_UDB_DSI2_HC57 0x400f4239u +#define CYREG_UDB_DSI2_HC58 0x400f423au +#define CYREG_UDB_DSI2_HC59 0x400f423bu +#define CYREG_UDB_DSI2_HC60 0x400f423cu +#define CYREG_UDB_DSI2_HC61 0x400f423du +#define CYREG_UDB_DSI2_HC62 0x400f423eu +#define CYREG_UDB_DSI2_HC63 0x400f423fu +#define CYREG_UDB_DSI2_HC64 0x400f4240u +#define CYREG_UDB_DSI2_HC65 0x400f4241u +#define CYREG_UDB_DSI2_HC66 0x400f4242u +#define CYREG_UDB_DSI2_HC67 0x400f4243u +#define CYREG_UDB_DSI2_HC68 0x400f4244u +#define CYREG_UDB_DSI2_HC69 0x400f4245u +#define CYREG_UDB_DSI2_HC70 0x400f4246u +#define CYREG_UDB_DSI2_HC71 0x400f4247u +#define CYREG_UDB_DSI2_HC72 0x400f4248u +#define CYREG_UDB_DSI2_HC73 0x400f4249u +#define CYREG_UDB_DSI2_HC74 0x400f424au +#define CYREG_UDB_DSI2_HC75 0x400f424bu +#define CYREG_UDB_DSI2_HC76 0x400f424cu +#define CYREG_UDB_DSI2_HC77 0x400f424du +#define CYREG_UDB_DSI2_HC78 0x400f424eu +#define CYREG_UDB_DSI2_HC79 0x400f424fu +#define CYREG_UDB_DSI2_HC80 0x400f4250u +#define CYREG_UDB_DSI2_HC81 0x400f4251u +#define CYREG_UDB_DSI2_HC82 0x400f4252u +#define CYREG_UDB_DSI2_HC83 0x400f4253u +#define CYREG_UDB_DSI2_HC84 0x400f4254u +#define CYREG_UDB_DSI2_HC85 0x400f4255u +#define CYREG_UDB_DSI2_HC86 0x400f4256u +#define CYREG_UDB_DSI2_HC87 0x400f4257u +#define CYREG_UDB_DSI2_HC88 0x400f4258u +#define CYREG_UDB_DSI2_HC89 0x400f4259u +#define CYREG_UDB_DSI2_HC90 0x400f425au +#define CYREG_UDB_DSI2_HC91 0x400f425bu +#define CYREG_UDB_DSI2_HC92 0x400f425cu +#define CYREG_UDB_DSI2_HC93 0x400f425du +#define CYREG_UDB_DSI2_HC94 0x400f425eu +#define CYREG_UDB_DSI2_HC95 0x400f425fu +#define CYREG_UDB_DSI2_HC96 0x400f4260u +#define CYREG_UDB_DSI2_HC97 0x400f4261u +#define CYREG_UDB_DSI2_HC98 0x400f4262u +#define CYREG_UDB_DSI2_HC99 0x400f4263u +#define CYREG_UDB_DSI2_HC100 0x400f4264u +#define CYREG_UDB_DSI2_HC101 0x400f4265u +#define CYREG_UDB_DSI2_HC102 0x400f4266u +#define CYREG_UDB_DSI2_HC103 0x400f4267u +#define CYREG_UDB_DSI2_HC104 0x400f4268u +#define CYREG_UDB_DSI2_HC105 0x400f4269u +#define CYREG_UDB_DSI2_HC106 0x400f426au +#define CYREG_UDB_DSI2_HC107 0x400f426bu +#define CYREG_UDB_DSI2_HC108 0x400f426cu +#define CYREG_UDB_DSI2_HC109 0x400f426du +#define CYREG_UDB_DSI2_HC110 0x400f426eu +#define CYREG_UDB_DSI2_HC111 0x400f426fu +#define CYREG_UDB_DSI2_HC112 0x400f4270u +#define CYREG_UDB_DSI2_HC113 0x400f4271u +#define CYREG_UDB_DSI2_HC114 0x400f4272u +#define CYREG_UDB_DSI2_HC115 0x400f4273u +#define CYREG_UDB_DSI2_HC116 0x400f4274u +#define CYREG_UDB_DSI2_HC117 0x400f4275u +#define CYREG_UDB_DSI2_HC118 0x400f4276u +#define CYREG_UDB_DSI2_HC119 0x400f4277u +#define CYREG_UDB_DSI2_HC120 0x400f4278u +#define CYREG_UDB_DSI2_HC121 0x400f4279u +#define CYREG_UDB_DSI2_HC122 0x400f427au +#define CYREG_UDB_DSI2_HC123 0x400f427bu +#define CYREG_UDB_DSI2_HC124 0x400f427cu +#define CYREG_UDB_DSI2_HC125 0x400f427du +#define CYREG_UDB_DSI2_HC126 0x400f427eu +#define CYREG_UDB_DSI2_HC127 0x400f427fu +#define CYREG_UDB_DSI2_HV_L0 0x400f4280u +#define CYREG_UDB_DSI2_HV_L1 0x400f4281u +#define CYREG_UDB_DSI2_HV_L2 0x400f4282u +#define CYREG_UDB_DSI2_HV_L3 0x400f4283u +#define CYREG_UDB_DSI2_HV_L4 0x400f4284u +#define CYREG_UDB_DSI2_HV_L5 0x400f4285u +#define CYREG_UDB_DSI2_HV_L6 0x400f4286u +#define CYREG_UDB_DSI2_HV_L7 0x400f4287u +#define CYREG_UDB_DSI2_HV_L8 0x400f4288u +#define CYREG_UDB_DSI2_HV_L9 0x400f4289u +#define CYREG_UDB_DSI2_HV_L10 0x400f428au +#define CYREG_UDB_DSI2_HV_L11 0x400f428bu +#define CYREG_UDB_DSI2_HV_L12 0x400f428cu +#define CYREG_UDB_DSI2_HV_L13 0x400f428du +#define CYREG_UDB_DSI2_HV_L14 0x400f428eu +#define CYREG_UDB_DSI2_HV_L15 0x400f428fu +#define CYREG_UDB_DSI2_HS0 0x400f4290u +#define CYREG_UDB_DSI2_HS1 0x400f4291u +#define CYREG_UDB_DSI2_HS2 0x400f4292u +#define CYREG_UDB_DSI2_HS3 0x400f4293u +#define CYREG_UDB_DSI2_HS4 0x400f4294u +#define CYREG_UDB_DSI2_HS5 0x400f4295u +#define CYREG_UDB_DSI2_HS6 0x400f4296u +#define CYREG_UDB_DSI2_HS7 0x400f4297u +#define CYREG_UDB_DSI2_HS8 0x400f4298u +#define CYREG_UDB_DSI2_HS9 0x400f4299u +#define CYREG_UDB_DSI2_HS10 0x400f429au +#define CYREG_UDB_DSI2_HS11 0x400f429bu +#define CYREG_UDB_DSI2_HS12 0x400f429cu +#define CYREG_UDB_DSI2_HS13 0x400f429du +#define CYREG_UDB_DSI2_HS14 0x400f429eu +#define CYREG_UDB_DSI2_HS15 0x400f429fu +#define CYREG_UDB_DSI2_HS16 0x400f42a0u +#define CYREG_UDB_DSI2_HS17 0x400f42a1u +#define CYREG_UDB_DSI2_HS18 0x400f42a2u +#define CYREG_UDB_DSI2_HS19 0x400f42a3u +#define CYREG_UDB_DSI2_HS20 0x400f42a4u +#define CYREG_UDB_DSI2_HS21 0x400f42a5u +#define CYREG_UDB_DSI2_HS22 0x400f42a6u +#define CYREG_UDB_DSI2_HS23 0x400f42a7u +#define CYREG_UDB_DSI2_HV_R0 0x400f42a8u +#define CYREG_UDB_DSI2_HV_R1 0x400f42a9u +#define CYREG_UDB_DSI2_HV_R2 0x400f42aau +#define CYREG_UDB_DSI2_HV_R3 0x400f42abu +#define CYREG_UDB_DSI2_HV_R4 0x400f42acu +#define CYREG_UDB_DSI2_HV_R5 0x400f42adu +#define CYREG_UDB_DSI2_HV_R6 0x400f42aeu +#define CYREG_UDB_DSI2_HV_R7 0x400f42afu +#define CYREG_UDB_DSI2_HV_R8 0x400f42b0u +#define CYREG_UDB_DSI2_HV_R9 0x400f42b1u +#define CYREG_UDB_DSI2_HV_R10 0x400f42b2u +#define CYREG_UDB_DSI2_HV_R11 0x400f42b3u +#define CYREG_UDB_DSI2_HV_R12 0x400f42b4u +#define CYREG_UDB_DSI2_HV_R13 0x400f42b5u +#define CYREG_UDB_DSI2_HV_R14 0x400f42b6u +#define CYREG_UDB_DSI2_HV_R15 0x400f42b7u +#define CYREG_UDB_DSI2_DSIINP0 0x400f42c0u +#define CYREG_UDB_DSI2_DSIINP1 0x400f42c2u +#define CYREG_UDB_DSI2_DSIINP2 0x400f42c4u +#define CYREG_UDB_DSI2_DSIINP3 0x400f42c6u +#define CYREG_UDB_DSI2_DSIINP4 0x400f42c8u +#define CYREG_UDB_DSI2_DSIINP5 0x400f42cau +#define CYREG_UDB_DSI2_DSIOUTP0 0x400f42ccu +#define CYREG_UDB_DSI2_DSIOUTP1 0x400f42ceu +#define CYREG_UDB_DSI2_DSIOUTP2 0x400f42d0u +#define CYREG_UDB_DSI2_DSIOUTP3 0x400f42d2u +#define CYREG_UDB_DSI2_DSIOUTT0 0x400f42d4u +#define CYREG_UDB_DSI2_DSIOUTT1 0x400f42d6u +#define CYREG_UDB_DSI2_DSIOUTT2 0x400f42d8u +#define CYREG_UDB_DSI2_DSIOUTT3 0x400f42dau +#define CYREG_UDB_DSI2_DSIOUTT4 0x400f42dcu +#define CYREG_UDB_DSI2_DSIOUTT5 0x400f42deu +#define CYREG_UDB_DSI2_VS0 0x400f42e0u +#define CYREG_UDB_DSI2_VS1 0x400f42e2u +#define CYREG_UDB_DSI2_VS2 0x400f42e4u +#define CYREG_UDB_DSI2_VS3 0x400f42e6u +#define CYREG_UDB_DSI2_VS4 0x400f42e8u +#define CYREG_UDB_DSI2_VS5 0x400f42eau +#define CYREG_UDB_DSI2_VS6 0x400f42ecu +#define CYREG_UDB_DSI2_VS7 0x400f42eeu +#define CYDEV_UDB_DSI3_BASE 0x400f4300u +#define CYDEV_UDB_DSI3_SIZE 0x00000100u +#define CYREG_UDB_DSI3_HC0 0x400f4300u +#define CYREG_UDB_DSI3_HC1 0x400f4301u +#define CYREG_UDB_DSI3_HC2 0x400f4302u +#define CYREG_UDB_DSI3_HC3 0x400f4303u +#define CYREG_UDB_DSI3_HC4 0x400f4304u +#define CYREG_UDB_DSI3_HC5 0x400f4305u +#define CYREG_UDB_DSI3_HC6 0x400f4306u +#define CYREG_UDB_DSI3_HC7 0x400f4307u +#define CYREG_UDB_DSI3_HC8 0x400f4308u +#define CYREG_UDB_DSI3_HC9 0x400f4309u +#define CYREG_UDB_DSI3_HC10 0x400f430au +#define CYREG_UDB_DSI3_HC11 0x400f430bu +#define CYREG_UDB_DSI3_HC12 0x400f430cu +#define CYREG_UDB_DSI3_HC13 0x400f430du +#define CYREG_UDB_DSI3_HC14 0x400f430eu +#define CYREG_UDB_DSI3_HC15 0x400f430fu +#define CYREG_UDB_DSI3_HC16 0x400f4310u +#define CYREG_UDB_DSI3_HC17 0x400f4311u +#define CYREG_UDB_DSI3_HC18 0x400f4312u +#define CYREG_UDB_DSI3_HC19 0x400f4313u +#define CYREG_UDB_DSI3_HC20 0x400f4314u +#define CYREG_UDB_DSI3_HC21 0x400f4315u +#define CYREG_UDB_DSI3_HC22 0x400f4316u +#define CYREG_UDB_DSI3_HC23 0x400f4317u +#define CYREG_UDB_DSI3_HC24 0x400f4318u +#define CYREG_UDB_DSI3_HC25 0x400f4319u +#define CYREG_UDB_DSI3_HC26 0x400f431au +#define CYREG_UDB_DSI3_HC27 0x400f431bu +#define CYREG_UDB_DSI3_HC28 0x400f431cu +#define CYREG_UDB_DSI3_HC29 0x400f431du +#define CYREG_UDB_DSI3_HC30 0x400f431eu +#define CYREG_UDB_DSI3_HC31 0x400f431fu +#define CYREG_UDB_DSI3_HC32 0x400f4320u +#define CYREG_UDB_DSI3_HC33 0x400f4321u +#define CYREG_UDB_DSI3_HC34 0x400f4322u +#define CYREG_UDB_DSI3_HC35 0x400f4323u +#define CYREG_UDB_DSI3_HC36 0x400f4324u +#define CYREG_UDB_DSI3_HC37 0x400f4325u +#define CYREG_UDB_DSI3_HC38 0x400f4326u +#define CYREG_UDB_DSI3_HC39 0x400f4327u +#define CYREG_UDB_DSI3_HC40 0x400f4328u +#define CYREG_UDB_DSI3_HC41 0x400f4329u +#define CYREG_UDB_DSI3_HC42 0x400f432au +#define CYREG_UDB_DSI3_HC43 0x400f432bu +#define CYREG_UDB_DSI3_HC44 0x400f432cu +#define CYREG_UDB_DSI3_HC45 0x400f432du +#define CYREG_UDB_DSI3_HC46 0x400f432eu +#define CYREG_UDB_DSI3_HC47 0x400f432fu +#define CYREG_UDB_DSI3_HC48 0x400f4330u +#define CYREG_UDB_DSI3_HC49 0x400f4331u +#define CYREG_UDB_DSI3_HC50 0x400f4332u +#define CYREG_UDB_DSI3_HC51 0x400f4333u +#define CYREG_UDB_DSI3_HC52 0x400f4334u +#define CYREG_UDB_DSI3_HC53 0x400f4335u +#define CYREG_UDB_DSI3_HC54 0x400f4336u +#define CYREG_UDB_DSI3_HC55 0x400f4337u +#define CYREG_UDB_DSI3_HC56 0x400f4338u +#define CYREG_UDB_DSI3_HC57 0x400f4339u +#define CYREG_UDB_DSI3_HC58 0x400f433au +#define CYREG_UDB_DSI3_HC59 0x400f433bu +#define CYREG_UDB_DSI3_HC60 0x400f433cu +#define CYREG_UDB_DSI3_HC61 0x400f433du +#define CYREG_UDB_DSI3_HC62 0x400f433eu +#define CYREG_UDB_DSI3_HC63 0x400f433fu +#define CYREG_UDB_DSI3_HC64 0x400f4340u +#define CYREG_UDB_DSI3_HC65 0x400f4341u +#define CYREG_UDB_DSI3_HC66 0x400f4342u +#define CYREG_UDB_DSI3_HC67 0x400f4343u +#define CYREG_UDB_DSI3_HC68 0x400f4344u +#define CYREG_UDB_DSI3_HC69 0x400f4345u +#define CYREG_UDB_DSI3_HC70 0x400f4346u +#define CYREG_UDB_DSI3_HC71 0x400f4347u +#define CYREG_UDB_DSI3_HC72 0x400f4348u +#define CYREG_UDB_DSI3_HC73 0x400f4349u +#define CYREG_UDB_DSI3_HC74 0x400f434au +#define CYREG_UDB_DSI3_HC75 0x400f434bu +#define CYREG_UDB_DSI3_HC76 0x400f434cu +#define CYREG_UDB_DSI3_HC77 0x400f434du +#define CYREG_UDB_DSI3_HC78 0x400f434eu +#define CYREG_UDB_DSI3_HC79 0x400f434fu +#define CYREG_UDB_DSI3_HC80 0x400f4350u +#define CYREG_UDB_DSI3_HC81 0x400f4351u +#define CYREG_UDB_DSI3_HC82 0x400f4352u +#define CYREG_UDB_DSI3_HC83 0x400f4353u +#define CYREG_UDB_DSI3_HC84 0x400f4354u +#define CYREG_UDB_DSI3_HC85 0x400f4355u +#define CYREG_UDB_DSI3_HC86 0x400f4356u +#define CYREG_UDB_DSI3_HC87 0x400f4357u +#define CYREG_UDB_DSI3_HC88 0x400f4358u +#define CYREG_UDB_DSI3_HC89 0x400f4359u +#define CYREG_UDB_DSI3_HC90 0x400f435au +#define CYREG_UDB_DSI3_HC91 0x400f435bu +#define CYREG_UDB_DSI3_HC92 0x400f435cu +#define CYREG_UDB_DSI3_HC93 0x400f435du +#define CYREG_UDB_DSI3_HC94 0x400f435eu +#define CYREG_UDB_DSI3_HC95 0x400f435fu +#define CYREG_UDB_DSI3_HC96 0x400f4360u +#define CYREG_UDB_DSI3_HC97 0x400f4361u +#define CYREG_UDB_DSI3_HC98 0x400f4362u +#define CYREG_UDB_DSI3_HC99 0x400f4363u +#define CYREG_UDB_DSI3_HC100 0x400f4364u +#define CYREG_UDB_DSI3_HC101 0x400f4365u +#define CYREG_UDB_DSI3_HC102 0x400f4366u +#define CYREG_UDB_DSI3_HC103 0x400f4367u +#define CYREG_UDB_DSI3_HC104 0x400f4368u +#define CYREG_UDB_DSI3_HC105 0x400f4369u +#define CYREG_UDB_DSI3_HC106 0x400f436au +#define CYREG_UDB_DSI3_HC107 0x400f436bu +#define CYREG_UDB_DSI3_HC108 0x400f436cu +#define CYREG_UDB_DSI3_HC109 0x400f436du +#define CYREG_UDB_DSI3_HC110 0x400f436eu +#define CYREG_UDB_DSI3_HC111 0x400f436fu +#define CYREG_UDB_DSI3_HC112 0x400f4370u +#define CYREG_UDB_DSI3_HC113 0x400f4371u +#define CYREG_UDB_DSI3_HC114 0x400f4372u +#define CYREG_UDB_DSI3_HC115 0x400f4373u +#define CYREG_UDB_DSI3_HC116 0x400f4374u +#define CYREG_UDB_DSI3_HC117 0x400f4375u +#define CYREG_UDB_DSI3_HC118 0x400f4376u +#define CYREG_UDB_DSI3_HC119 0x400f4377u +#define CYREG_UDB_DSI3_HC120 0x400f4378u +#define CYREG_UDB_DSI3_HC121 0x400f4379u +#define CYREG_UDB_DSI3_HC122 0x400f437au +#define CYREG_UDB_DSI3_HC123 0x400f437bu +#define CYREG_UDB_DSI3_HC124 0x400f437cu +#define CYREG_UDB_DSI3_HC125 0x400f437du +#define CYREG_UDB_DSI3_HC126 0x400f437eu +#define CYREG_UDB_DSI3_HC127 0x400f437fu +#define CYREG_UDB_DSI3_HV_L0 0x400f4380u +#define CYREG_UDB_DSI3_HV_L1 0x400f4381u +#define CYREG_UDB_DSI3_HV_L2 0x400f4382u +#define CYREG_UDB_DSI3_HV_L3 0x400f4383u +#define CYREG_UDB_DSI3_HV_L4 0x400f4384u +#define CYREG_UDB_DSI3_HV_L5 0x400f4385u +#define CYREG_UDB_DSI3_HV_L6 0x400f4386u +#define CYREG_UDB_DSI3_HV_L7 0x400f4387u +#define CYREG_UDB_DSI3_HV_L8 0x400f4388u +#define CYREG_UDB_DSI3_HV_L9 0x400f4389u +#define CYREG_UDB_DSI3_HV_L10 0x400f438au +#define CYREG_UDB_DSI3_HV_L11 0x400f438bu +#define CYREG_UDB_DSI3_HV_L12 0x400f438cu +#define CYREG_UDB_DSI3_HV_L13 0x400f438du +#define CYREG_UDB_DSI3_HV_L14 0x400f438eu +#define CYREG_UDB_DSI3_HV_L15 0x400f438fu +#define CYREG_UDB_DSI3_HS0 0x400f4390u +#define CYREG_UDB_DSI3_HS1 0x400f4391u +#define CYREG_UDB_DSI3_HS2 0x400f4392u +#define CYREG_UDB_DSI3_HS3 0x400f4393u +#define CYREG_UDB_DSI3_HS4 0x400f4394u +#define CYREG_UDB_DSI3_HS5 0x400f4395u +#define CYREG_UDB_DSI3_HS6 0x400f4396u +#define CYREG_UDB_DSI3_HS7 0x400f4397u +#define CYREG_UDB_DSI3_HS8 0x400f4398u +#define CYREG_UDB_DSI3_HS9 0x400f4399u +#define CYREG_UDB_DSI3_HS10 0x400f439au +#define CYREG_UDB_DSI3_HS11 0x400f439bu +#define CYREG_UDB_DSI3_HS12 0x400f439cu +#define CYREG_UDB_DSI3_HS13 0x400f439du +#define CYREG_UDB_DSI3_HS14 0x400f439eu +#define CYREG_UDB_DSI3_HS15 0x400f439fu +#define CYREG_UDB_DSI3_HS16 0x400f43a0u +#define CYREG_UDB_DSI3_HS17 0x400f43a1u +#define CYREG_UDB_DSI3_HS18 0x400f43a2u +#define CYREG_UDB_DSI3_HS19 0x400f43a3u +#define CYREG_UDB_DSI3_HS20 0x400f43a4u +#define CYREG_UDB_DSI3_HS21 0x400f43a5u +#define CYREG_UDB_DSI3_HS22 0x400f43a6u +#define CYREG_UDB_DSI3_HS23 0x400f43a7u +#define CYREG_UDB_DSI3_HV_R0 0x400f43a8u +#define CYREG_UDB_DSI3_HV_R1 0x400f43a9u +#define CYREG_UDB_DSI3_HV_R2 0x400f43aau +#define CYREG_UDB_DSI3_HV_R3 0x400f43abu +#define CYREG_UDB_DSI3_HV_R4 0x400f43acu +#define CYREG_UDB_DSI3_HV_R5 0x400f43adu +#define CYREG_UDB_DSI3_HV_R6 0x400f43aeu +#define CYREG_UDB_DSI3_HV_R7 0x400f43afu +#define CYREG_UDB_DSI3_HV_R8 0x400f43b0u +#define CYREG_UDB_DSI3_HV_R9 0x400f43b1u +#define CYREG_UDB_DSI3_HV_R10 0x400f43b2u +#define CYREG_UDB_DSI3_HV_R11 0x400f43b3u +#define CYREG_UDB_DSI3_HV_R12 0x400f43b4u +#define CYREG_UDB_DSI3_HV_R13 0x400f43b5u +#define CYREG_UDB_DSI3_HV_R14 0x400f43b6u +#define CYREG_UDB_DSI3_HV_R15 0x400f43b7u +#define CYREG_UDB_DSI3_DSIINP0 0x400f43c0u +#define CYREG_UDB_DSI3_DSIINP1 0x400f43c2u +#define CYREG_UDB_DSI3_DSIINP2 0x400f43c4u +#define CYREG_UDB_DSI3_DSIINP3 0x400f43c6u +#define CYREG_UDB_DSI3_DSIINP4 0x400f43c8u +#define CYREG_UDB_DSI3_DSIINP5 0x400f43cau +#define CYREG_UDB_DSI3_DSIOUTP0 0x400f43ccu +#define CYREG_UDB_DSI3_DSIOUTP1 0x400f43ceu +#define CYREG_UDB_DSI3_DSIOUTP2 0x400f43d0u +#define CYREG_UDB_DSI3_DSIOUTP3 0x400f43d2u +#define CYREG_UDB_DSI3_DSIOUTT0 0x400f43d4u +#define CYREG_UDB_DSI3_DSIOUTT1 0x400f43d6u +#define CYREG_UDB_DSI3_DSIOUTT2 0x400f43d8u +#define CYREG_UDB_DSI3_DSIOUTT3 0x400f43dau +#define CYREG_UDB_DSI3_DSIOUTT4 0x400f43dcu +#define CYREG_UDB_DSI3_DSIOUTT5 0x400f43deu +#define CYREG_UDB_DSI3_VS0 0x400f43e0u +#define CYREG_UDB_DSI3_VS1 0x400f43e2u +#define CYREG_UDB_DSI3_VS2 0x400f43e4u +#define CYREG_UDB_DSI3_VS3 0x400f43e6u +#define CYREG_UDB_DSI3_VS4 0x400f43e8u +#define CYREG_UDB_DSI3_VS5 0x400f43eau +#define CYREG_UDB_DSI3_VS6 0x400f43ecu +#define CYREG_UDB_DSI3_VS7 0x400f43eeu +#define CYDEV_UDB_PA0_BASE 0x400f5000u +#define CYDEV_UDB_PA0_SIZE 0x00000010u +#define CYREG_UDB_PA0_CFG0 0x400f5000u +#define CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET 0x00000002u +#define CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_OFF 0x00000000u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_ON 0x00000001u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE 0x00000002u +#define CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL 0x00000003u +#define CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET 0x00000004u +#define CYFLD_UDB_PA_CLKIN_EN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKIN_EN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKIN_EN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_CLKIN_INV__OFFSET 0x00000005u +#define CYFLD_UDB_PA_CLKIN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKIN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKIN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_NC__OFFSET 0x00000006u +#define CYFLD_UDB_PA_NC__SIZE 0x00000002u +#define CYREG_UDB_PA0_CFG1 0x400f5001u +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET 0x00000002u +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_ON 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL 0x00000003u +#define CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET 0x00000004u +#define CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_EN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_CLKOUT_INV__OFFSET 0x00000005u +#define CYFLD_UDB_PA_CLKOUT_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_INV_INV 0x00000001u +#define CYREG_UDB_PA0_CFG2 0x400f5002u +#define CYFLD_UDB_PA_CLKIN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_CLKIN_SEL__SIZE 0x00000004u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP 0x00000009u +#define CYVAL_UDB_PA_CLKIN_SEL_PIN_RC 0x0000000cu +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 0x0000000du +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 0x0000000eu +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 0x0000000fu +#define CYFLD_UDB_PA_CLKOUT_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_PA_CLKOUT_SEL__SIZE 0x00000004u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 0x00000000u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 0x00000001u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 0x00000002u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 0x00000003u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 0x00000004u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 0x00000005u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 0x00000006u +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 0x00000007u +#define CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP 0x00000009u +#define CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC 0x0000000cu +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 0x0000000du +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 0x0000000eu +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 0x0000000fu +#define CYREG_UDB_PA0_CFG3 0x400f5003u +#define CYFLD_UDB_PA_RES_IN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_RES_IN_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_RES_IN_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_RES_IN_INV__OFFSET 0x00000002u +#define CYFLD_UDB_PA_RES_IN_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_IN_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_RES_IN_INV_INV 0x00000001u +#define CYFLD_UDB_PA_NC0__OFFSET 0x00000003u +#define CYFLD_UDB_PA_NC0__SIZE 0x00000001u +#define CYFLD_UDB_PA_RES_OUT_SEL__OFFSET 0x00000004u +#define CYFLD_UDB_PA_RES_OUT_SEL__SIZE 0x00000002u +#define CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC 0x00000000u +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 0x00000001u +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 0x00000002u +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 0x00000003u +#define CYFLD_UDB_PA_RES_OUT_INV__OFFSET 0x00000006u +#define CYFLD_UDB_PA_RES_OUT_INV__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_OUT_INV_NOINV 0x00000000u +#define CYVAL_UDB_PA_RES_OUT_INV_INV 0x00000001u +#define CYFLD_UDB_PA_NC7__OFFSET 0x00000007u +#define CYFLD_UDB_PA_NC7__SIZE 0x00000001u +#define CYREG_UDB_PA0_CFG4 0x400f5004u +#define CYFLD_UDB_PA_RES_IN_EN__OFFSET 0x00000000u +#define CYFLD_UDB_PA_RES_IN_EN__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_IN_EN_DISABLE 0x00000000u +#define CYVAL_UDB_PA_RES_IN_EN_ENABLE 0x00000001u +#define CYFLD_UDB_PA_RES_OUT_EN__OFFSET 0x00000001u +#define CYFLD_UDB_PA_RES_OUT_EN__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_OUT_EN_DISABLE 0x00000000u +#define CYVAL_UDB_PA_RES_OUT_EN_ENABLE 0x00000001u +#define CYFLD_UDB_PA_RES_OE_EN__OFFSET 0x00000002u +#define CYFLD_UDB_PA_RES_OE_EN__SIZE 0x00000001u +#define CYVAL_UDB_PA_RES_OE_EN_DISABLE 0x00000000u +#define CYVAL_UDB_PA_RES_OE_EN_ENABLE 0x00000001u +#define CYFLD_UDB_PA_NC7654__OFFSET 0x00000003u +#define CYFLD_UDB_PA_NC7654__SIZE 0x00000005u +#define CYREG_UDB_PA0_CFG5 0x400f5005u +#define CYFLD_UDB_PA_PIN_SEL__OFFSET 0x00000000u +#define CYFLD_UDB_PA_PIN_SEL__SIZE 0x00000001u +#define CYVAL_UDB_PA_PIN_SEL_PIN0 0x00000000u +#define CYVAL_UDB_PA_PIN_SEL_PIN1 0x00000001u +#define CYVAL_UDB_PA_PIN_SEL_PIN2 0x00000002u +#define CYVAL_UDB_PA_PIN_SEL_PIN3 0x00000003u +#define CYVAL_UDB_PA_PIN_SEL_PIN4 0x00000004u +#define CYVAL_UDB_PA_PIN_SEL_PIN5 0x00000005u +#define CYVAL_UDB_PA_PIN_SEL_PIN6 0x00000006u +#define CYVAL_UDB_PA_PIN_SEL_PIN7 0x00000007u +#define CYREG_UDB_PA0_CFG6 0x400f5006u +#define CYFLD_UDB_PA_IN_SYNC0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_IN_SYNC0__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC0_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_IN_SYNC1__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC1_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_IN_SYNC2__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC2_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_IN_SYNC3__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC3_RSVD 0x00000003u +#define CYREG_UDB_PA0_CFG7 0x400f5007u +#define CYFLD_UDB_PA_IN_SYNC4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_IN_SYNC4__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC4_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_IN_SYNC5__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC5_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_IN_SYNC6__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC6_RSVD 0x00000003u +#define CYFLD_UDB_PA_IN_SYNC7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_IN_SYNC7__SIZE 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC 0x00000002u +#define CYVAL_UDB_PA_IN_SYNC7_RSVD 0x00000003u +#define CYREG_UDB_PA0_CFG8 0x400f5008u +#define CYFLD_UDB_PA_OUT_SYNC0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OUT_SYNC0__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OUT_SYNC1__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OUT_SYNC2__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OUT_SYNC3__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV 0x00000003u +#define CYREG_UDB_PA0_CFG9 0x400f5009u +#define CYFLD_UDB_PA_OUT_SYNC4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OUT_SYNC4__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OUT_SYNC5__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OUT_SYNC6__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV 0x00000003u +#define CYFLD_UDB_PA_OUT_SYNC7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OUT_SYNC7__SIZE 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCK 0x00000002u +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV 0x00000003u +#define CYREG_UDB_PA0_CFG10 0x400f500au +#define CYFLD_UDB_PA_DATA_SEL0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_DATA_SEL0__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_DATA_SEL1__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_DATA_SEL2__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_DATA_SEL3__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 0x00000003u +#define CYREG_UDB_PA0_CFG11 0x400f500bu +#define CYFLD_UDB_PA_DATA_SEL4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_DATA_SEL4__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_DATA_SEL5__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_DATA_SEL6__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 0x00000003u +#define CYFLD_UDB_PA_DATA_SEL7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_DATA_SEL7__SIZE 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 0x00000000u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 0x00000001u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 0x00000002u +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 0x00000003u +#define CYREG_UDB_PA0_CFG12 0x400f500cu +#define CYFLD_UDB_PA_OE_SEL0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OE_SEL0__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OE_SEL1__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OE_SEL2__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OE_SEL3__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 0x00000003u +#define CYREG_UDB_PA0_CFG13 0x400f500du +#define CYFLD_UDB_PA_OE_SEL4__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OE_SEL4__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL5__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OE_SEL5__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL6__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OE_SEL6__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 0x00000003u +#define CYFLD_UDB_PA_OE_SEL7__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OE_SEL7__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 0x00000000u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 0x00000001u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 0x00000002u +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 0x00000003u +#define CYREG_UDB_PA0_CFG14 0x400f500eu +#define CYFLD_UDB_PA_OE_SYNC0__OFFSET 0x00000000u +#define CYFLD_UDB_PA_OE_SYNC0__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 0x00000003u +#define CYFLD_UDB_PA_OE_SYNC1__OFFSET 0x00000002u +#define CYFLD_UDB_PA_OE_SYNC1__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 0x00000003u +#define CYFLD_UDB_PA_OE_SYNC2__OFFSET 0x00000004u +#define CYFLD_UDB_PA_OE_SYNC2__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 0x00000003u +#define CYFLD_UDB_PA_OE_SYNC3__OFFSET 0x00000006u +#define CYFLD_UDB_PA_OE_SYNC3__SIZE 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT 0x00000000u +#define CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC 0x00000001u +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 0x00000002u +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 0x00000003u +#define CYDEV_UDB_PA1_BASE 0x400f5010u +#define CYDEV_UDB_PA1_SIZE 0x00000010u +#define CYREG_UDB_PA1_CFG0 0x400f5010u +#define CYREG_UDB_PA1_CFG1 0x400f5011u +#define CYREG_UDB_PA1_CFG2 0x400f5012u +#define CYREG_UDB_PA1_CFG3 0x400f5013u +#define CYREG_UDB_PA1_CFG4 0x400f5014u +#define CYREG_UDB_PA1_CFG5 0x400f5015u +#define CYREG_UDB_PA1_CFG6 0x400f5016u +#define CYREG_UDB_PA1_CFG7 0x400f5017u +#define CYREG_UDB_PA1_CFG8 0x400f5018u +#define CYREG_UDB_PA1_CFG9 0x400f5019u +#define CYREG_UDB_PA1_CFG10 0x400f501au +#define CYREG_UDB_PA1_CFG11 0x400f501bu +#define CYREG_UDB_PA1_CFG12 0x400f501cu +#define CYREG_UDB_PA1_CFG13 0x400f501du +#define CYREG_UDB_PA1_CFG14 0x400f501eu +#define CYDEV_UDB_PA2_BASE 0x400f5020u +#define CYDEV_UDB_PA2_SIZE 0x00000010u +#define CYREG_UDB_PA2_CFG0 0x400f5020u +#define CYREG_UDB_PA2_CFG1 0x400f5021u +#define CYREG_UDB_PA2_CFG2 0x400f5022u +#define CYREG_UDB_PA2_CFG3 0x400f5023u +#define CYREG_UDB_PA2_CFG4 0x400f5024u +#define CYREG_UDB_PA2_CFG5 0x400f5025u +#define CYREG_UDB_PA2_CFG6 0x400f5026u +#define CYREG_UDB_PA2_CFG7 0x400f5027u +#define CYREG_UDB_PA2_CFG8 0x400f5028u +#define CYREG_UDB_PA2_CFG9 0x400f5029u +#define CYREG_UDB_PA2_CFG10 0x400f502au +#define CYREG_UDB_PA2_CFG11 0x400f502bu +#define CYREG_UDB_PA2_CFG12 0x400f502cu +#define CYREG_UDB_PA2_CFG13 0x400f502du +#define CYREG_UDB_PA2_CFG14 0x400f502eu +#define CYDEV_UDB_PA3_BASE 0x400f5030u +#define CYDEV_UDB_PA3_SIZE 0x00000010u +#define CYREG_UDB_PA3_CFG0 0x400f5030u +#define CYREG_UDB_PA3_CFG1 0x400f5031u +#define CYREG_UDB_PA3_CFG2 0x400f5032u +#define CYREG_UDB_PA3_CFG3 0x400f5033u +#define CYREG_UDB_PA3_CFG4 0x400f5034u +#define CYREG_UDB_PA3_CFG5 0x400f5035u +#define CYREG_UDB_PA3_CFG6 0x400f5036u +#define CYREG_UDB_PA3_CFG7 0x400f5037u +#define CYREG_UDB_PA3_CFG8 0x400f5038u +#define CYREG_UDB_PA3_CFG9 0x400f5039u +#define CYREG_UDB_PA3_CFG10 0x400f503au +#define CYREG_UDB_PA3_CFG11 0x400f503bu +#define CYREG_UDB_PA3_CFG12 0x400f503cu +#define CYREG_UDB_PA3_CFG13 0x400f503du +#define CYREG_UDB_PA3_CFG14 0x400f503eu +#define CYDEV_UDB_BCTL0_BASE 0x400f6000u +#define CYDEV_UDB_BCTL0_SIZE 0x00001000u +#define CYREG_UDB_BCTL0_DRV 0x400f6000u +#define CYFLD_UDB_BCTL0_DRV__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_DRV__SIZE 0x00000008u +#define CYVAL_UDB_BCTL0_DRV_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DRV_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_MDCLK_EN 0x400f6001u +#define CYFLD_UDB_BCTL0_DCEN__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_DCEN__SIZE 0x00000008u +#define CYVAL_UDB_BCTL0_DCEN_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DCEN_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_MBCLK_EN 0x400f6002u +#define CYFLD_UDB_BCTL0_BCEN__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_BCEN__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_BCEN_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_BCEN_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_BOTSEL_L 0x400f6008u +#define CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_CLK_SEL0__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET 0x00000002u +#define CYFLD_UDB_BCTL0_CLK_SEL1__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET 0x00000004u +#define CYFLD_UDB_BCTL0_CLK_SEL2__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET 0x00000006u +#define CYFLD_UDB_BCTL0_CLK_SEL3__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT 0x00000003u +#define CYREG_UDB_BCTL0_BOTSEL_U 0x400f6009u +#define CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_CLK_SEL4__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET 0x00000002u +#define CYFLD_UDB_BCTL0_CLK_SEL5__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET 0x00000004u +#define CYFLD_UDB_BCTL0_CLK_SEL6__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT 0x00000003u +#define CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET 0x00000006u +#define CYFLD_UDB_BCTL0_CLK_SEL7__SIZE 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES 0x00000000u +#define CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT 0x00000001u +#define CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT 0x00000002u +#define CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT 0x00000003u +#define CYREG_UDB_BCTL0_TOPSEL_L 0x400f600au +#define CYREG_UDB_BCTL0_TOPSEL_U 0x400f600bu +#define CYREG_UDB_BCTL0_QCLK_EN0 0x400f6010u +#define CYFLD_UDB_BCTL0_DCEN_Q__OFFSET 0x00000000u +#define CYFLD_UDB_BCTL0_DCEN_Q__SIZE 0x00000008u +#define CYVAL_UDB_BCTL0_DCEN_Q_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DCEN_Q_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_BCEN_Q__OFFSET 0x00000008u +#define CYFLD_UDB_BCTL0_BCEN_Q__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_BCEN_Q_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_BCEN_Q_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET 0x00000009u +#define CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET 0x0000000au +#define CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET 0x0000000bu +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET 0x0000000cu +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE 0x00000001u +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET 0x0000000du +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB 0x00000000u +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB 0x00000001u +#define CYFLD_UDB_BCTL0_NC0__OFFSET 0x0000000eu +#define CYFLD_UDB_BCTL0_NC0__SIZE 0x00000001u +#define CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET 0x0000000fu +#define CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE 0x00000001u +#define CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE 0x00000000u +#define CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE 0x00000001u +#define CYREG_UDB_BCTL0_QCLK_EN1 0x400f6012u +#define CYDEV_UDB_UDBIF_BASE 0x400f7000u +#define CYDEV_UDB_UDBIF_SIZE 0x00001000u +#define CYREG_UDB_UDBIF_BANK_CTL 0x400f7000u +#define CYFLD_UDB_UDBIF_DIS_COR__OFFSET 0x00000000u +#define CYFLD_UDB_UDBIF_DIS_COR__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_DIS_COR_NORMAL 0x00000000u +#define CYVAL_UDB_UDBIF_DIS_COR_DISABLE 0x00000001u +#define CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET 0x00000001u +#define CYFLD_UDB_UDBIF_ROUTE_EN__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE 0x00000000u +#define CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE 0x00000001u +#define CYFLD_UDB_UDBIF_BANK_EN__OFFSET 0x00000002u +#define CYFLD_UDB_UDBIF_BANK_EN__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_BANK_EN_DISABLE 0x00000000u +#define CYVAL_UDB_UDBIF_BANK_EN_ENABLE 0x00000001u +#define CYFLD_UDB_UDBIF_LOCK__OFFSET 0x00000003u +#define CYFLD_UDB_UDBIF_LOCK__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_LOCK_MUTABLE 0x00000000u +#define CYVAL_UDB_UDBIF_LOCK_LOCKED 0x00000001u +#define CYFLD_UDB_UDBIF_PIPE__OFFSET 0x00000004u +#define CYFLD_UDB_UDBIF_PIPE__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_PIPE_BYPASS 0x00000000u +#define CYVAL_UDB_UDBIF_PIPE_PIPELINED 0x00000001u +#define CYFLD_UDB_UDBIF_GLBL_WR__OFFSET 0x00000007u +#define CYFLD_UDB_UDBIF_GLBL_WR__SIZE 0x00000001u +#define CYVAL_UDB_UDBIF_GLBL_WR_DISABLE 0x00000000u +#define CYVAL_UDB_UDBIF_GLBL_WR_ENABLE 0x00000001u +#define CYREG_UDB_UDBIF_WAIT_CFG 0x400f7001u +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET 0x00000000u +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS 0x00000000u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT 0x00000003u +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET 0x00000002u +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT 0x00000000u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS 0x00000003u +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET 0x00000004u +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT 0x00000000u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS 0x00000003u +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET 0x00000006u +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE 0x00000002u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT 0x00000000u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS 0x00000001u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS 0x00000002u +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS 0x00000003u +#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x400f701cu +#define CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET 0x00000000u +#define CYFLD_UDB_UDBIF_EN_HFCLK__SIZE 0x00000001u +#define CYREG_UDB_INT_CFG 0x400f8000u +#define CYFLD_UDB_INT_MODE_CFG__OFFSET 0x00000000u +#define CYFLD_UDB_INT_MODE_CFG__SIZE 0x00000020u +#define CYVAL_UDB_INT_MODE_CFG_LEVEL 0x00000000u +#define CYVAL_UDB_INT_MODE_CFG_PULSE 0x00000001u +#define CYDEV_CTBM_BASE 0x40100000u +#define CYDEV_CTBM_SIZE 0x00010000u +#define CYREG_CTBM_CTB_CTRL 0x40100000u +#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001fu +#define CYFLD_CTBM_ENABLED__SIZE 0x00000001u +#define CYREG_CTBM_OA_RES0_CTRL 0x40100004u +#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002u +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002u +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004u +#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005u +#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006u +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008u +#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002u +#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000u +#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001u +#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002u +#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003u +#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000bu +#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001u +#define CYREG_CTBM_OA_RES1_CTRL 0x40100008u +#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002u +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002u +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004u +#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005u +#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006u +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008u +#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002u +#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000u +#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001u +#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002u +#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003u +#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000bu +#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001u +#define CYREG_CTBM_COMP_STAT 0x4010000cu +#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010u +#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001u +#define CYREG_CTBM_INTR 0x40100020u +#define CYFLD_CTBM_COMP0__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1__SIZE 0x00000001u +#define CYREG_CTBM_INTR_SET 0x40100024u +#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001u +#define CYREG_CTBM_INTR_MASK 0x40100028u +#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001u +#define CYREG_CTBM_INTR_MASKED 0x4010002cu +#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001u +#define CYREG_CTBM_DFT_CTRL 0x40100030u +#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003u +#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001fu +#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001u +#define CYREG_CTBM_OA0_SW 0x40100080u +#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001u +#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002u +#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001u +#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003u +#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001u +#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008u +#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001u +#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000eu +#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001u +#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012u +#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001u +#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015u +#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001u +#define CYREG_CTBM_OA0_SW_CLEAR 0x40100084u +#define CYREG_CTBM_OA1_SW 0x40100088u +#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001u +#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001u +#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001u +#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004u +#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001u +#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008u +#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001u +#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000eu +#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012u +#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013u +#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015u +#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001u +#define CYREG_CTBM_OA1_SW_CLEAR 0x4010008cu +#define CYREG_CTBM_CTB_SW_HW_CTRL 0x401000c0u +#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002u +#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001u +#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003u +#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001u +#define CYREG_CTBM_CTB_SW_STATUS 0x401000c4u +#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001cu +#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001du +#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001eu +#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001u +#define CYREG_CTBM_OA0_OFFSET_TRIM 0x40100f00u +#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM 0x40100f04u +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA0_COMP_TRIM 0x40100f08u +#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002u +#define CYREG_CTBM_OA1_OFFSET_TRIM 0x40100f0cu +#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM 0x40100f10u +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM_OA1_COMP_TRIM 0x40100f14u +#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002u +#define CYDEV_SAR_BASE 0x401a0000u +#define CYDEV_SAR_SIZE 0x00010000u +#define CYREG_SAR_CTRL 0x401a0000u +#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004u +#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003u +#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000u +#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001u +#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002u +#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003u +#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004u +#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005u +#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006u +#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007u +#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007u +#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001u +#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009u +#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003u +#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000u +#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001u +#define CYVAL_SAR_NEG_SEL_P1 0x00000002u +#define CYVAL_SAR_NEG_SEL_P3 0x00000003u +#define CYVAL_SAR_NEG_SEL_P5 0x00000004u +#define CYVAL_SAR_NEG_SEL_P7 0x00000005u +#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006u +#define CYVAL_SAR_NEG_SEL_VREF 0x00000007u +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000du +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001u +#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000eu +#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002u +#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000u +#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001u +#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002u +#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003u +#define CYFLD_SAR_SPARE__OFFSET 0x00000010u +#define CYFLD_SAR_SPARE__SIZE 0x00000004u +#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018u +#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002u +#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000u +#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001u +#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002u +#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003u +#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001cu +#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001u +#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001du +#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001u +#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001eu +#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001u +#define CYFLD_SAR_ENABLED__OFFSET 0x0000001fu +#define CYFLD_SAR_ENABLED__SIZE 0x00000001u +#define CYREG_SAR_SAMPLE_CTRL 0x401a0004u +#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000u +#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000u +#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001u +#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001u +#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001u +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002u +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001u +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000u +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001u +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003u +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001u +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000u +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001u +#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004u +#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003u +#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007u +#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001u +#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010u +#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001u +#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011u +#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001u +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012u +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001u +#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013u +#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001u +#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001u +#define CYREG_SAR_SAMPLE_TIME01 0x401a0010u +#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000u +#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000au +#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010u +#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000au +#define CYREG_SAR_SAMPLE_TIME23 0x401a0014u +#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000u +#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000au +#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010u +#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000au +#define CYREG_SAR_RANGE_THRES 0x401a0018u +#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010u +#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010u +#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010u +#define CYREG_SAR_RANGE_COND 0x401a001cu +#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001eu +#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002u +#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000u +#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001u +#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002u +#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003u +#define CYREG_SAR_CHAN_EN 0x401a0020u +#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010u +#define CYREG_SAR_START_CTRL 0x401a0024u +#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000u +#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001u +#define CYREG_SAR_DFT_CTRL 0x401a0030u +#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000u +#define CYFLD_SAR_DLY_INC__SIZE 0x00000001u +#define CYFLD_SAR_HIZ__OFFSET 0x00000001u +#define CYFLD_SAR_HIZ__SIZE 0x00000001u +#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010u +#define CYFLD_SAR_DFT_INC__SIZE 0x00000004u +#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014u +#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003u +#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018u +#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004u +#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001cu +#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001u +#define CYFLD_SAR_DCEN__OFFSET 0x0000001du +#define CYFLD_SAR_DCEN__SIZE 0x00000001u +#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001fu +#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001u +#define CYREG_SAR_CHAN_CONFIG00 0x401a0080u +#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000u +#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003u +#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004u +#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003u +#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000u +#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001u +#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002u +#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003u +#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004u +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT 0x00000006u +#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007u +#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008u +#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001u +#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009u +#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_RESOLUTION_12B 0x00000000u +#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001u +#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000au +#define CYFLD_SAR_AVG_EN__SIZE 0x00000001u +#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000cu +#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002u +#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001u +#define CYREG_SAR_CHAN_CONFIG01 0x401a0084u +#define CYREG_SAR_CHAN_CONFIG02 0x401a0088u +#define CYREG_SAR_CHAN_CONFIG03 0x401a008cu +#define CYREG_SAR_CHAN_CONFIG04 0x401a0090u +#define CYREG_SAR_CHAN_CONFIG05 0x401a0094u +#define CYREG_SAR_CHAN_CONFIG06 0x401a0098u +#define CYREG_SAR_CHAN_CONFIG07 0x401a009cu +#define CYREG_SAR_CHAN_WORK00 0x401a0100u +#define CYFLD_SAR_WORK__OFFSET 0x00000000u +#define CYFLD_SAR_WORK__SIZE 0x00000010u +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001u +#define CYREG_SAR_CHAN_WORK01 0x401a0104u +#define CYREG_SAR_CHAN_WORK02 0x401a0108u +#define CYREG_SAR_CHAN_WORK03 0x401a010cu +#define CYREG_SAR_CHAN_WORK04 0x401a0110u +#define CYREG_SAR_CHAN_WORK05 0x401a0114u +#define CYREG_SAR_CHAN_WORK06 0x401a0118u +#define CYREG_SAR_CHAN_WORK07 0x401a011cu +#define CYREG_SAR_CHAN_RESULT00 0x401a0180u +#define CYFLD_SAR_RESULT__OFFSET 0x00000000u +#define CYFLD_SAR_RESULT__SIZE 0x00000010u +#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001du +#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001eu +#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001u +#define CYREG_SAR_CHAN_RESULT01 0x401a0184u +#define CYREG_SAR_CHAN_RESULT02 0x401a0188u +#define CYREG_SAR_CHAN_RESULT03 0x401a018cu +#define CYREG_SAR_CHAN_RESULT04 0x401a0190u +#define CYREG_SAR_CHAN_RESULT05 0x401a0194u +#define CYREG_SAR_CHAN_RESULT06 0x401a0198u +#define CYREG_SAR_CHAN_RESULT07 0x401a019cu +#define CYREG_SAR_CHAN_WORK_VALID 0x401a0200u +#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010u +#define CYREG_SAR_CHAN_RESULT_VALID 0x401a0204u +#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010u +#define CYREG_SAR_STATUS 0x401a0208u +#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000u +#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005u +#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001eu +#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001u +#define CYFLD_SAR_BUSY__OFFSET 0x0000001fu +#define CYFLD_SAR_BUSY__SIZE 0x00000001u +#define CYREG_SAR_AVG_STAT 0x401a020cu +#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000u +#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014u +#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018u +#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008u +#define CYREG_SAR_INTR 0x401a0210u +#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001u +#define CYREG_SAR_INTR_SET 0x401a0214u +#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_SET__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001u +#define CYREG_SAR_INTR_MASK 0x401a0218u +#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001u +#define CYREG_SAR_INTR_MASKED 0x401a021cu +#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001u +#define CYREG_SAR_SATURATE_INTR 0x401a0220u +#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_SET 0x401a0224u +#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_MASK 0x401a0228u +#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_MASKED 0x401a022cu +#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR 0x401a0230u +#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_SET 0x401a0234u +#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_MASK 0x401a0238u +#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_MASKED 0x401a023cu +#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010u +#define CYREG_SAR_INTR_CAUSE 0x401a0240u +#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001eu +#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001u +#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001fu +#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001u +#define CYREG_SAR_INJ_CHAN_CONFIG 0x401a0280u +#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000u +#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003u +#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003u +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004u +#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006u +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007u +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008u +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009u +#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000u +#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001u +#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000au +#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000cu +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002u +#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001eu +#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001u +#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001u +#define CYREG_SAR_INJ_RESULT 0x401a0290u +#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000u +#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010u +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001cu +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001du +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001eu +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH0 0x401a0300u +#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004u +#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005u +#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006u +#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007u +#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008u +#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009u +#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000au +#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000bu +#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000cu +#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000du +#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000eu +#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000fu +#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010u +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011u +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016u +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017u +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018u +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019u +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001au +#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001bu +#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001cu +#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001du +#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x401a0304u +#define CYREG_SAR_MUX_SWITCH1 0x401a0308u +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x401a030cu +#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x401a0340u +#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004u +#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005u +#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006u +#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007u +#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010u +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011u +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_STATUS 0x401a0348u +#define CYREG_SAR_PUMP_CTRL 0x401a0380u +#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000u +#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001u +#define CYREG_SAR_ANA_TRIM 0x401a0f00u +#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000u +#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003u +#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003u +#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001u +#define CYREG_SAR_WOUNDING 0x401a0f04u +#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000u +#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002u +#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000u +#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001u +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002u +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003u +#define CYDEV_CM0_BASE 0xe0000000u +#define CYDEV_CM0_SIZE 0x00100000u +#define CYREG_CM0_DWT_PID4 0xe0001fd0u +#define CYFLD_CM0_VALUE__OFFSET 0x00000000u +#define CYFLD_CM0_VALUE__SIZE 0x00000020u +#define CYREG_CM0_DWT_PID0 0xe0001fe0u +#define CYREG_CM0_DWT_PID1 0xe0001fe4u +#define CYREG_CM0_DWT_PID2 0xe0001fe8u +#define CYREG_CM0_DWT_PID3 0xe0001fecu +#define CYREG_CM0_DWT_CID0 0xe0001ff0u +#define CYREG_CM0_DWT_CID1 0xe0001ff4u +#define CYREG_CM0_DWT_CID2 0xe0001ff8u +#define CYREG_CM0_DWT_CID3 0xe0001ffcu +#define CYREG_CM0_BP_PID4 0xe0002fd0u +#define CYREG_CM0_BP_PID0 0xe0002fe0u +#define CYREG_CM0_BP_PID1 0xe0002fe4u +#define CYREG_CM0_BP_PID2 0xe0002fe8u +#define CYREG_CM0_BP_PID3 0xe0002fecu +#define CYREG_CM0_BP_CID0 0xe0002ff0u +#define CYREG_CM0_BP_CID1 0xe0002ff4u +#define CYREG_CM0_BP_CID2 0xe0002ff8u +#define CYREG_CM0_BP_CID3 0xe0002ffcu +#define CYREG_CM0_SYST_CSR 0xe000e010u +#define CYFLD_CM0_ENABLE__OFFSET 0x00000000u +#define CYFLD_CM0_ENABLE__SIZE 0x00000001u +#define CYFLD_CM0_TICKINT__OFFSET 0x00000001u +#define CYFLD_CM0_TICKINT__SIZE 0x00000001u +#define CYFLD_CM0_CLKSOURCE__OFFSET 0x00000002u +#define CYFLD_CM0_CLKSOURCE__SIZE 0x00000001u +#define CYFLD_CM0_COUNTFLAG__OFFSET 0x00000010u +#define CYFLD_CM0_COUNTFLAG__SIZE 0x00000001u +#define CYREG_CM0_SYST_RVR 0xe000e014u +#define CYFLD_CM0_RELOAD__OFFSET 0x00000000u +#define CYFLD_CM0_RELOAD__SIZE 0x00000018u +#define CYREG_CM0_SYST_CVR 0xe000e018u +#define CYFLD_CM0_CURRENT__OFFSET 0x00000000u +#define CYFLD_CM0_CURRENT__SIZE 0x00000018u +#define CYREG_CM0_SYST_CALIB 0xe000e01cu +#define CYFLD_CM0_TENMS__OFFSET 0x00000000u +#define CYFLD_CM0_TENMS__SIZE 0x00000018u +#define CYFLD_CM0_SKEW__OFFSET 0x0000001eu +#define CYFLD_CM0_SKEW__SIZE 0x00000001u +#define CYFLD_CM0_NOREF__OFFSET 0x0000001fu +#define CYFLD_CM0_NOREF__SIZE 0x00000001u +#define CYREG_CM0_ISER 0xe000e100u +#define CYFLD_CM0_SETENA__OFFSET 0x00000000u +#define CYFLD_CM0_SETENA__SIZE 0x00000020u +#define CYREG_CM0_ICER 0xe000e180u +#define CYFLD_CM0_CLRENA__OFFSET 0x00000000u +#define CYFLD_CM0_CLRENA__SIZE 0x00000020u +#define CYREG_CM0_ISPR 0xe000e200u +#define CYFLD_CM0_SETPEND__OFFSET 0x00000000u +#define CYFLD_CM0_SETPEND__SIZE 0x00000020u +#define CYREG_CM0_ICPR 0xe000e280u +#define CYFLD_CM0_CLRPEND__OFFSET 0x00000000u +#define CYFLD_CM0_CLRPEND__SIZE 0x00000020u +#define CYREG_CM0_IPR0 0xe000e400u +#define CYFLD_CM0_PRI_N0__OFFSET 0x00000006u +#define CYFLD_CM0_PRI_N0__SIZE 0x00000002u +#define CYFLD_CM0_PRI_N1__OFFSET 0x0000000eu +#define CYFLD_CM0_PRI_N1__SIZE 0x00000002u +#define CYFLD_CM0_PRI_N2__OFFSET 0x00000016u +#define CYFLD_CM0_PRI_N2__SIZE 0x00000002u +#define CYFLD_CM0_PRI_N3__OFFSET 0x0000001eu +#define CYFLD_CM0_PRI_N3__SIZE 0x00000002u +#define CYREG_CM0_IPR1 0xe000e404u +#define CYREG_CM0_IPR2 0xe000e408u +#define CYREG_CM0_IPR3 0xe000e40cu +#define CYREG_CM0_IPR4 0xe000e410u +#define CYREG_CM0_IPR5 0xe000e414u +#define CYREG_CM0_IPR6 0xe000e418u +#define CYREG_CM0_IPR7 0xe000e41cu +#define CYREG_CM0_CPUID 0xe000ed00u +#define CYFLD_CM0_REVISION__OFFSET 0x00000000u +#define CYFLD_CM0_REVISION__SIZE 0x00000004u +#define CYFLD_CM0_PARTNO__OFFSET 0x00000004u +#define CYFLD_CM0_PARTNO__SIZE 0x0000000cu +#define CYFLD_CM0_CONSTANT__OFFSET 0x00000010u +#define CYFLD_CM0_CONSTANT__SIZE 0x00000004u +#define CYFLD_CM0_VARIANT__OFFSET 0x00000014u +#define CYFLD_CM0_VARIANT__SIZE 0x00000004u +#define CYFLD_CM0_IMPLEMENTER__OFFSET 0x00000018u +#define CYFLD_CM0_IMPLEMENTER__SIZE 0x00000008u +#define CYREG_CM0_ICSR 0xe000ed04u +#define CYFLD_CM0_VECTACTIVE__OFFSET 0x00000000u +#define CYFLD_CM0_VECTACTIVE__SIZE 0x00000009u +#define CYFLD_CM0_VECTPENDING__OFFSET 0x0000000cu +#define CYFLD_CM0_VECTPENDING__SIZE 0x00000009u +#define CYFLD_CM0_ISRPENDING__OFFSET 0x00000016u +#define CYFLD_CM0_ISRPENDING__SIZE 0x00000001u +#define CYFLD_CM0_ISRPREEMPT__OFFSET 0x00000017u +#define CYFLD_CM0_ISRPREEMPT__SIZE 0x00000001u +#define CYFLD_CM0_PENDSTCLR__OFFSET 0x00000019u +#define CYFLD_CM0_PENDSTCLR__SIZE 0x00000001u +#define CYFLD_CM0_PENDSTSETb__OFFSET 0x0000001au +#define CYFLD_CM0_PENDSTSETb__SIZE 0x00000001u +#define CYFLD_CM0_PENDSVCLR__OFFSET 0x0000001bu +#define CYFLD_CM0_PENDSVCLR__SIZE 0x00000001u +#define CYFLD_CM0_PENDSVSET__OFFSET 0x0000001cu +#define CYFLD_CM0_PENDSVSET__SIZE 0x00000001u +#define CYFLD_CM0_NMIPENDSET__OFFSET 0x0000001fu +#define CYFLD_CM0_NMIPENDSET__SIZE 0x00000001u +#define CYREG_CM0_AIRCR 0xe000ed0cu +#define CYFLD_CM0_VECTCLRACTIVE__OFFSET 0x00000001u +#define CYFLD_CM0_VECTCLRACTIVE__SIZE 0x00000001u +#define CYFLD_CM0_SYSRESETREQ__OFFSET 0x00000002u +#define CYFLD_CM0_SYSRESETREQ__SIZE 0x00000001u +#define CYFLD_CM0_ENDIANNESS__OFFSET 0x0000000fu +#define CYFLD_CM0_ENDIANNESS__SIZE 0x00000001u +#define CYFLD_CM0_VECTKEY__OFFSET 0x00000010u +#define CYFLD_CM0_VECTKEY__SIZE 0x00000010u +#define CYREG_CM0_SCR 0xe000ed10u +#define CYFLD_CM0_SLEEPONEXIT__OFFSET 0x00000001u +#define CYFLD_CM0_SLEEPONEXIT__SIZE 0x00000001u +#define CYFLD_CM0_SLEEPDEEP__OFFSET 0x00000002u +#define CYFLD_CM0_SLEEPDEEP__SIZE 0x00000001u +#define CYFLD_CM0_SEVONPEND__OFFSET 0x00000004u +#define CYFLD_CM0_SEVONPEND__SIZE 0x00000001u +#define CYREG_CM0_CCR 0xe000ed14u +#define CYFLD_CM0_UNALIGN_TRP__OFFSET 0x00000003u +#define CYFLD_CM0_UNALIGN_TRP__SIZE 0x00000001u +#define CYFLD_CM0_STKALIGN__OFFSET 0x00000009u +#define CYFLD_CM0_STKALIGN__SIZE 0x00000001u +#define CYREG_CM0_SHPR2 0xe000ed1cu +#define CYFLD_CM0_PRI_11__OFFSET 0x0000001eu +#define CYFLD_CM0_PRI_11__SIZE 0x00000002u +#define CYREG_CM0_SHPR3 0xe000ed20u +#define CYFLD_CM0_PRI_14__OFFSET 0x00000016u +#define CYFLD_CM0_PRI_14__SIZE 0x00000002u +#define CYFLD_CM0_PRI_15__OFFSET 0x0000001eu +#define CYFLD_CM0_PRI_15__SIZE 0x00000002u +#define CYREG_CM0_SHCSR 0xe000ed24u +#define CYFLD_CM0_SVCALLPENDED__OFFSET 0x0000000fu +#define CYFLD_CM0_SVCALLPENDED__SIZE 0x00000001u +#define CYREG_CM0_SCS_PID4 0xe000efd0u +#define CYREG_CM0_SCS_PID0 0xe000efe0u +#define CYREG_CM0_SCS_PID1 0xe000efe4u +#define CYREG_CM0_SCS_PID2 0xe000efe8u +#define CYREG_CM0_SCS_PID3 0xe000efecu +#define CYREG_CM0_SCS_CID0 0xe000eff0u +#define CYREG_CM0_SCS_CID1 0xe000eff4u +#define CYREG_CM0_SCS_CID2 0xe000eff8u +#define CYREG_CM0_SCS_CID3 0xe000effcu +#define CYREG_CM0_ROM_SCS 0xe00ff000u +#define CYREG_CM0_ROM_DWT 0xe00ff004u +#define CYREG_CM0_ROM_BPU 0xe00ff008u +#define CYREG_CM0_ROM_END 0xe00ff00cu +#define CYREG_CM0_ROM_CSMT 0xe00fffccu +#define CYREG_CM0_ROM_PID4 0xe00fffd0u +#define CYREG_CM0_ROM_PID0 0xe00fffe0u +#define CYREG_CM0_ROM_PID1 0xe00fffe4u +#define CYREG_CM0_ROM_PID2 0xe00fffe8u +#define CYREG_CM0_ROM_PID3 0xe00fffecu +#define CYREG_CM0_ROM_CID0 0xe00ffff0u +#define CYREG_CM0_ROM_CID1 0xe00ffff4u +#define CYREG_CM0_ROM_CID2 0xe00ffff8u +#define CYREG_CM0_ROM_CID3 0xe00ffffcu +#define CYDEV_CoreSightTable_BASE 0xf0000000u +#define CYDEV_CoreSightTable_SIZE 0x00001000u +#define CYREG_CoreSightTable_DATA_MBASE 0xf0000000u +#define CYREG_CoreSightTable_DATA_MSIZE 0x00001000u +#define CYDEV_FLS_SECTOR_SIZE 0x00008000u +#define CYDEV_FLS_ROW_SIZE 0x00000080u +#endif /* CYDEVICE_TRM_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevicegnu_trm.inc b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevicegnu_trm.inc new file mode 100644 index 0000000..62bbcb7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevicegnu_trm.inc @@ -0,0 +1,6494 @@ +/******************************************************************************* +* File Name: cydevicegnu_trm.inc +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00008000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00008000 +.set CYDEV_SFLASH_BASE, 0x0ffff000 +.set CYDEV_SFLASH_SIZE, 0x00000200 +.set CYREG_SFLASH_PROT_ROW00, 0x0ffff000 +.set CYFLD_SFLASH_DATA8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_DATA8__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_ROW01, 0x0ffff001 +.set CYREG_SFLASH_PROT_ROW02, 0x0ffff002 +.set CYREG_SFLASH_PROT_ROW03, 0x0ffff003 +.set CYREG_SFLASH_PROT_ROW04, 0x0ffff004 +.set CYREG_SFLASH_PROT_ROW05, 0x0ffff005 +.set CYREG_SFLASH_PROT_ROW06, 0x0ffff006 +.set CYREG_SFLASH_PROT_ROW07, 0x0ffff007 +.set CYREG_SFLASH_PROT_ROW08, 0x0ffff008 +.set CYREG_SFLASH_PROT_ROW09, 0x0ffff009 +.set CYREG_SFLASH_PROT_ROW10, 0x0ffff00a +.set CYREG_SFLASH_PROT_ROW11, 0x0ffff00b +.set CYREG_SFLASH_PROT_ROW12, 0x0ffff00c +.set CYREG_SFLASH_PROT_ROW13, 0x0ffff00d +.set CYREG_SFLASH_PROT_ROW14, 0x0ffff00e +.set CYREG_SFLASH_PROT_ROW15, 0x0ffff00f +.set CYREG_SFLASH_PROT_ROW16, 0x0ffff010 +.set CYREG_SFLASH_PROT_ROW17, 0x0ffff011 +.set CYREG_SFLASH_PROT_ROW18, 0x0ffff012 +.set CYREG_SFLASH_PROT_ROW19, 0x0ffff013 +.set CYREG_SFLASH_PROT_ROW20, 0x0ffff014 +.set CYREG_SFLASH_PROT_ROW21, 0x0ffff015 +.set CYREG_SFLASH_PROT_ROW22, 0x0ffff016 +.set CYREG_SFLASH_PROT_ROW23, 0x0ffff017 +.set CYREG_SFLASH_PROT_ROW24, 0x0ffff018 +.set CYREG_SFLASH_PROT_ROW25, 0x0ffff019 +.set CYREG_SFLASH_PROT_ROW26, 0x0ffff01a +.set CYREG_SFLASH_PROT_ROW27, 0x0ffff01b +.set CYREG_SFLASH_PROT_ROW28, 0x0ffff01c +.set CYREG_SFLASH_PROT_ROW29, 0x0ffff01d +.set CYREG_SFLASH_PROT_ROW30, 0x0ffff01e +.set CYREG_SFLASH_PROT_ROW31, 0x0ffff01f +.set CYREG_SFLASH_PROT_ROW32, 0x0ffff020 +.set CYREG_SFLASH_PROT_ROW33, 0x0ffff021 +.set CYREG_SFLASH_PROT_ROW34, 0x0ffff022 +.set CYREG_SFLASH_PROT_ROW35, 0x0ffff023 +.set CYREG_SFLASH_PROT_ROW36, 0x0ffff024 +.set CYREG_SFLASH_PROT_ROW37, 0x0ffff025 +.set CYREG_SFLASH_PROT_ROW38, 0x0ffff026 +.set CYREG_SFLASH_PROT_ROW39, 0x0ffff027 +.set CYREG_SFLASH_PROT_ROW40, 0x0ffff028 +.set CYREG_SFLASH_PROT_ROW41, 0x0ffff029 +.set CYREG_SFLASH_PROT_ROW42, 0x0ffff02a +.set CYREG_SFLASH_PROT_ROW43, 0x0ffff02b +.set CYREG_SFLASH_PROT_ROW44, 0x0ffff02c +.set CYREG_SFLASH_PROT_ROW45, 0x0ffff02d +.set CYREG_SFLASH_PROT_ROW46, 0x0ffff02e +.set CYREG_SFLASH_PROT_ROW47, 0x0ffff02f +.set CYREG_SFLASH_PROT_ROW48, 0x0ffff030 +.set CYREG_SFLASH_PROT_ROW49, 0x0ffff031 +.set CYREG_SFLASH_PROT_ROW50, 0x0ffff032 +.set CYREG_SFLASH_PROT_ROW51, 0x0ffff033 +.set CYREG_SFLASH_PROT_ROW52, 0x0ffff034 +.set CYREG_SFLASH_PROT_ROW53, 0x0ffff035 +.set CYREG_SFLASH_PROT_ROW54, 0x0ffff036 +.set CYREG_SFLASH_PROT_ROW55, 0x0ffff037 +.set CYREG_SFLASH_PROT_ROW56, 0x0ffff038 +.set CYREG_SFLASH_PROT_ROW57, 0x0ffff039 +.set CYREG_SFLASH_PROT_ROW58, 0x0ffff03a +.set CYREG_SFLASH_PROT_ROW59, 0x0ffff03b +.set CYREG_SFLASH_PROT_ROW60, 0x0ffff03c +.set CYREG_SFLASH_PROT_ROW61, 0x0ffff03d +.set CYREG_SFLASH_PROT_ROW62, 0x0ffff03e +.set CYREG_SFLASH_PROT_ROW63, 0x0ffff03f +.set CYREG_SFLASH_PROT_PROTECTION, 0x0ffff07f +.set CYFLD_SFLASH_PROT_LEVEL__OFFSET, 0x00000000 +.set CYFLD_SFLASH_PROT_LEVEL__SIZE, 0x00000002 +.set CYVAL_SFLASH_PROT_LEVEL_VIRGIN, 0x00000001 +.set CYVAL_SFLASH_PROT_LEVEL_OPEN, 0x00000000 +.set CYVAL_SFLASH_PROT_LEVEL_PROTECTED, 0x00000002 +.set CYVAL_SFLASH_PROT_LEVEL_KILL, 0x00000003 +.set CYREG_SFLASH_AV_PAIRS_8B000, 0x0ffff080 +.set CYREG_SFLASH_AV_PAIRS_8B001, 0x0ffff081 +.set CYREG_SFLASH_AV_PAIRS_8B002, 0x0ffff082 +.set CYREG_SFLASH_AV_PAIRS_8B003, 0x0ffff083 +.set CYREG_SFLASH_AV_PAIRS_8B004, 0x0ffff084 +.set CYREG_SFLASH_AV_PAIRS_8B005, 0x0ffff085 +.set CYREG_SFLASH_AV_PAIRS_8B006, 0x0ffff086 +.set CYREG_SFLASH_AV_PAIRS_8B007, 0x0ffff087 +.set CYREG_SFLASH_AV_PAIRS_8B008, 0x0ffff088 +.set CYREG_SFLASH_AV_PAIRS_8B009, 0x0ffff089 +.set CYREG_SFLASH_AV_PAIRS_8B010, 0x0ffff08a +.set CYREG_SFLASH_AV_PAIRS_8B011, 0x0ffff08b +.set CYREG_SFLASH_AV_PAIRS_8B012, 0x0ffff08c +.set CYREG_SFLASH_AV_PAIRS_8B013, 0x0ffff08d +.set CYREG_SFLASH_AV_PAIRS_8B014, 0x0ffff08e +.set CYREG_SFLASH_AV_PAIRS_8B015, 0x0ffff08f +.set CYREG_SFLASH_AV_PAIRS_8B016, 0x0ffff090 +.set CYREG_SFLASH_AV_PAIRS_8B017, 0x0ffff091 +.set CYREG_SFLASH_AV_PAIRS_8B018, 0x0ffff092 +.set CYREG_SFLASH_AV_PAIRS_8B019, 0x0ffff093 +.set CYREG_SFLASH_AV_PAIRS_8B020, 0x0ffff094 +.set CYREG_SFLASH_AV_PAIRS_8B021, 0x0ffff095 +.set CYREG_SFLASH_AV_PAIRS_8B022, 0x0ffff096 +.set CYREG_SFLASH_AV_PAIRS_8B023, 0x0ffff097 +.set CYREG_SFLASH_AV_PAIRS_8B024, 0x0ffff098 +.set CYREG_SFLASH_AV_PAIRS_8B025, 0x0ffff099 +.set CYREG_SFLASH_AV_PAIRS_8B026, 0x0ffff09a +.set CYREG_SFLASH_AV_PAIRS_8B027, 0x0ffff09b +.set CYREG_SFLASH_AV_PAIRS_8B028, 0x0ffff09c +.set CYREG_SFLASH_AV_PAIRS_8B029, 0x0ffff09d +.set CYREG_SFLASH_AV_PAIRS_8B030, 0x0ffff09e +.set CYREG_SFLASH_AV_PAIRS_8B031, 0x0ffff09f +.set CYREG_SFLASH_AV_PAIRS_8B032, 0x0ffff0a0 +.set CYREG_SFLASH_AV_PAIRS_8B033, 0x0ffff0a1 +.set CYREG_SFLASH_AV_PAIRS_8B034, 0x0ffff0a2 +.set CYREG_SFLASH_AV_PAIRS_8B035, 0x0ffff0a3 +.set CYREG_SFLASH_AV_PAIRS_8B036, 0x0ffff0a4 +.set CYREG_SFLASH_AV_PAIRS_8B037, 0x0ffff0a5 +.set CYREG_SFLASH_AV_PAIRS_8B038, 0x0ffff0a6 +.set CYREG_SFLASH_AV_PAIRS_8B039, 0x0ffff0a7 +.set CYREG_SFLASH_AV_PAIRS_8B040, 0x0ffff0a8 +.set CYREG_SFLASH_AV_PAIRS_8B041, 0x0ffff0a9 +.set CYREG_SFLASH_AV_PAIRS_8B042, 0x0ffff0aa +.set CYREG_SFLASH_AV_PAIRS_8B043, 0x0ffff0ab +.set CYREG_SFLASH_AV_PAIRS_8B044, 0x0ffff0ac +.set CYREG_SFLASH_AV_PAIRS_8B045, 0x0ffff0ad +.set CYREG_SFLASH_AV_PAIRS_8B046, 0x0ffff0ae +.set CYREG_SFLASH_AV_PAIRS_8B047, 0x0ffff0af +.set CYREG_SFLASH_AV_PAIRS_8B048, 0x0ffff0b0 +.set CYREG_SFLASH_AV_PAIRS_8B049, 0x0ffff0b1 +.set CYREG_SFLASH_AV_PAIRS_8B050, 0x0ffff0b2 +.set CYREG_SFLASH_AV_PAIRS_8B051, 0x0ffff0b3 +.set CYREG_SFLASH_AV_PAIRS_8B052, 0x0ffff0b4 +.set CYREG_SFLASH_AV_PAIRS_8B053, 0x0ffff0b5 +.set CYREG_SFLASH_AV_PAIRS_8B054, 0x0ffff0b6 +.set CYREG_SFLASH_AV_PAIRS_8B055, 0x0ffff0b7 +.set CYREG_SFLASH_AV_PAIRS_8B056, 0x0ffff0b8 +.set CYREG_SFLASH_AV_PAIRS_8B057, 0x0ffff0b9 +.set CYREG_SFLASH_AV_PAIRS_8B058, 0x0ffff0ba +.set CYREG_SFLASH_AV_PAIRS_8B059, 0x0ffff0bb +.set CYREG_SFLASH_AV_PAIRS_8B060, 0x0ffff0bc +.set CYREG_SFLASH_AV_PAIRS_8B061, 0x0ffff0bd +.set CYREG_SFLASH_AV_PAIRS_8B062, 0x0ffff0be +.set CYREG_SFLASH_AV_PAIRS_8B063, 0x0ffff0bf +.set CYREG_SFLASH_AV_PAIRS_8B064, 0x0ffff0c0 +.set CYREG_SFLASH_AV_PAIRS_8B065, 0x0ffff0c1 +.set CYREG_SFLASH_AV_PAIRS_8B066, 0x0ffff0c2 +.set CYREG_SFLASH_AV_PAIRS_8B067, 0x0ffff0c3 +.set CYREG_SFLASH_AV_PAIRS_8B068, 0x0ffff0c4 +.set CYREG_SFLASH_AV_PAIRS_8B069, 0x0ffff0c5 +.set CYREG_SFLASH_AV_PAIRS_8B070, 0x0ffff0c6 +.set CYREG_SFLASH_AV_PAIRS_8B071, 0x0ffff0c7 +.set CYREG_SFLASH_AV_PAIRS_8B072, 0x0ffff0c8 +.set CYREG_SFLASH_AV_PAIRS_8B073, 0x0ffff0c9 +.set CYREG_SFLASH_AV_PAIRS_8B074, 0x0ffff0ca +.set CYREG_SFLASH_AV_PAIRS_8B075, 0x0ffff0cb +.set CYREG_SFLASH_AV_PAIRS_8B076, 0x0ffff0cc +.set CYREG_SFLASH_AV_PAIRS_8B077, 0x0ffff0cd +.set CYREG_SFLASH_AV_PAIRS_8B078, 0x0ffff0ce +.set CYREG_SFLASH_AV_PAIRS_8B079, 0x0ffff0cf +.set CYREG_SFLASH_AV_PAIRS_8B080, 0x0ffff0d0 +.set CYREG_SFLASH_AV_PAIRS_8B081, 0x0ffff0d1 +.set CYREG_SFLASH_AV_PAIRS_8B082, 0x0ffff0d2 +.set CYREG_SFLASH_AV_PAIRS_8B083, 0x0ffff0d3 +.set CYREG_SFLASH_AV_PAIRS_8B084, 0x0ffff0d4 +.set CYREG_SFLASH_AV_PAIRS_8B085, 0x0ffff0d5 +.set CYREG_SFLASH_AV_PAIRS_8B086, 0x0ffff0d6 +.set CYREG_SFLASH_AV_PAIRS_8B087, 0x0ffff0d7 +.set CYREG_SFLASH_AV_PAIRS_8B088, 0x0ffff0d8 +.set CYREG_SFLASH_AV_PAIRS_8B089, 0x0ffff0d9 +.set CYREG_SFLASH_AV_PAIRS_8B090, 0x0ffff0da +.set CYREG_SFLASH_AV_PAIRS_8B091, 0x0ffff0db +.set CYREG_SFLASH_AV_PAIRS_8B092, 0x0ffff0dc +.set CYREG_SFLASH_AV_PAIRS_8B093, 0x0ffff0dd +.set CYREG_SFLASH_AV_PAIRS_8B094, 0x0ffff0de +.set CYREG_SFLASH_AV_PAIRS_8B095, 0x0ffff0df +.set CYREG_SFLASH_AV_PAIRS_8B096, 0x0ffff0e0 +.set CYREG_SFLASH_AV_PAIRS_8B097, 0x0ffff0e1 +.set CYREG_SFLASH_AV_PAIRS_8B098, 0x0ffff0e2 +.set CYREG_SFLASH_AV_PAIRS_8B099, 0x0ffff0e3 +.set CYREG_SFLASH_AV_PAIRS_8B100, 0x0ffff0e4 +.set CYREG_SFLASH_AV_PAIRS_8B101, 0x0ffff0e5 +.set CYREG_SFLASH_AV_PAIRS_8B102, 0x0ffff0e6 +.set CYREG_SFLASH_AV_PAIRS_8B103, 0x0ffff0e7 +.set CYREG_SFLASH_AV_PAIRS_8B104, 0x0ffff0e8 +.set CYREG_SFLASH_AV_PAIRS_8B105, 0x0ffff0e9 +.set CYREG_SFLASH_AV_PAIRS_8B106, 0x0ffff0ea +.set CYREG_SFLASH_AV_PAIRS_8B107, 0x0ffff0eb +.set CYREG_SFLASH_AV_PAIRS_8B108, 0x0ffff0ec +.set CYREG_SFLASH_AV_PAIRS_8B109, 0x0ffff0ed +.set CYREG_SFLASH_AV_PAIRS_8B110, 0x0ffff0ee +.set CYREG_SFLASH_AV_PAIRS_8B111, 0x0ffff0ef +.set CYREG_SFLASH_AV_PAIRS_8B112, 0x0ffff0f0 +.set CYREG_SFLASH_AV_PAIRS_8B113, 0x0ffff0f1 +.set CYREG_SFLASH_AV_PAIRS_8B114, 0x0ffff0f2 +.set CYREG_SFLASH_AV_PAIRS_8B115, 0x0ffff0f3 +.set CYREG_SFLASH_AV_PAIRS_8B116, 0x0ffff0f4 +.set CYREG_SFLASH_AV_PAIRS_8B117, 0x0ffff0f5 +.set CYREG_SFLASH_AV_PAIRS_8B118, 0x0ffff0f6 +.set CYREG_SFLASH_AV_PAIRS_8B119, 0x0ffff0f7 +.set CYREG_SFLASH_AV_PAIRS_8B120, 0x0ffff0f8 +.set CYREG_SFLASH_AV_PAIRS_8B121, 0x0ffff0f9 +.set CYREG_SFLASH_AV_PAIRS_8B122, 0x0ffff0fa +.set CYREG_SFLASH_AV_PAIRS_8B123, 0x0ffff0fb +.set CYREG_SFLASH_AV_PAIRS_8B124, 0x0ffff0fc +.set CYREG_SFLASH_AV_PAIRS_8B125, 0x0ffff0fd +.set CYREG_SFLASH_AV_PAIRS_8B126, 0x0ffff0fe +.set CYREG_SFLASH_AV_PAIRS_8B127, 0x0ffff0ff +.set CYREG_SFLASH_AV_PAIRS_32B00, 0x0ffff100 +.set CYFLD_SFLASH_DATA32__OFFSET, 0x00000000 +.set CYFLD_SFLASH_DATA32__SIZE, 0x00000020 +.set CYREG_SFLASH_AV_PAIRS_32B01, 0x0ffff104 +.set CYREG_SFLASH_AV_PAIRS_32B02, 0x0ffff108 +.set CYREG_SFLASH_AV_PAIRS_32B03, 0x0ffff10c +.set CYREG_SFLASH_AV_PAIRS_32B04, 0x0ffff110 +.set CYREG_SFLASH_AV_PAIRS_32B05, 0x0ffff114 +.set CYREG_SFLASH_AV_PAIRS_32B06, 0x0ffff118 +.set CYREG_SFLASH_AV_PAIRS_32B07, 0x0ffff11c +.set CYREG_SFLASH_AV_PAIRS_32B08, 0x0ffff120 +.set CYREG_SFLASH_AV_PAIRS_32B09, 0x0ffff124 +.set CYREG_SFLASH_AV_PAIRS_32B10, 0x0ffff128 +.set CYREG_SFLASH_AV_PAIRS_32B11, 0x0ffff12c +.set CYREG_SFLASH_AV_PAIRS_32B12, 0x0ffff130 +.set CYREG_SFLASH_AV_PAIRS_32B13, 0x0ffff134 +.set CYREG_SFLASH_AV_PAIRS_32B14, 0x0ffff138 +.set CYREG_SFLASH_AV_PAIRS_32B15, 0x0ffff13c +.set CYREG_SFLASH_CPUSS_WOUNDING, 0x0ffff140 +.set CYREG_SFLASH_SILICON_ID, 0x0ffff144 +.set CYFLD_SFLASH_ID__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ID__SIZE, 0x00000010 +.set CYREG_SFLASH_CPUSS_PRIV_RAM, 0x0ffff148 +.set CYREG_SFLASH_CPUSS_PRIV_FLASH, 0x0ffff14c +.set CYREG_SFLASH_HIB_KEY_DELAY, 0x0ffff150 +.set CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET, 0x00000000 +.set CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE, 0x0000000a +.set CYREG_SFLASH_DPSLP_KEY_DELAY, 0x0ffff152 +.set CYREG_SFLASH_SWD_CONFIG, 0x0ffff154 +.set CYFLD_SFLASH_SWD_SELECT__OFFSET, 0x00000000 +.set CYFLD_SFLASH_SWD_SELECT__SIZE, 0x00000001 +.set CYREG_SFLASH_SWD_LISTEN, 0x0ffff158 +.set CYFLD_SFLASH_CYCLES__OFFSET, 0x00000000 +.set CYFLD_SFLASH_CYCLES__SIZE, 0x00000020 +.set CYREG_SFLASH_FLASH_START, 0x0ffff15c +.set CYFLD_SFLASH_ADDRESS__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ADDRESS__SIZE, 0x00000020 +.set CYREG_SFLASH_CSD_TRIM1_HVIDAC, 0x0ffff160 +.set CYFLD_SFLASH_TRIM8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TRIM8__SIZE, 0x00000008 +.set CYREG_SFLASH_CSD_TRIM2_HVIDAC, 0x0ffff161 +.set CYREG_SFLASH_CSD_TRIM1_CSD, 0x0ffff162 +.set CYREG_SFLASH_CSD_TRIM2_CSD, 0x0ffff163 +.set CYREG_SFLASH_SAR_TEMP_MULTIPLIER, 0x0ffff164 +.set CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE, 0x00000010 +.set CYREG_SFLASH_SAR_TEMP_OFFSET, 0x0ffff166 +.set CYFLD_SFLASH_TEMP_OFFSET__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TEMP_OFFSET__SIZE, 0x00000010 +.set CYREG_SFLASH_SKIP_CHECKSUM, 0x0ffff169 +.set CYFLD_SFLASH_SKIP__OFFSET, 0x00000000 +.set CYFLD_SFLASH_SKIP__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_VIRGINKEY0, 0x0ffff170 +.set CYFLD_SFLASH_KEY8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_KEY8__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_VIRGINKEY1, 0x0ffff171 +.set CYREG_SFLASH_PROT_VIRGINKEY2, 0x0ffff172 +.set CYREG_SFLASH_PROT_VIRGINKEY3, 0x0ffff173 +.set CYREG_SFLASH_PROT_VIRGINKEY4, 0x0ffff174 +.set CYREG_SFLASH_PROT_VIRGINKEY5, 0x0ffff175 +.set CYREG_SFLASH_PROT_VIRGINKEY6, 0x0ffff176 +.set CYREG_SFLASH_PROT_VIRGINKEY7, 0x0ffff177 +.set CYREG_SFLASH_DIE_LOT0, 0x0ffff178 +.set CYFLD_SFLASH_LOT__OFFSET, 0x00000000 +.set CYFLD_SFLASH_LOT__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_LOT1, 0x0ffff179 +.set CYREG_SFLASH_DIE_LOT2, 0x0ffff17a +.set CYREG_SFLASH_DIE_WAFER, 0x0ffff17b +.set CYFLD_SFLASH_WAFER__OFFSET, 0x00000000 +.set CYFLD_SFLASH_WAFER__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_X, 0x0ffff17c +.set CYFLD_SFLASH_X__OFFSET, 0x00000000 +.set CYFLD_SFLASH_X__SIZE, 0x00000006 +.set CYFLD_SFLASH_CRI_PASS__OFFSET, 0x00000006 +.set CYFLD_SFLASH_CRI_PASS__SIZE, 0x00000002 +.set CYREG_SFLASH_DIE_Y, 0x0ffff17d +.set CYFLD_SFLASH_Y__OFFSET, 0x00000000 +.set CYFLD_SFLASH_Y__SIZE, 0x00000006 +.set CYFLD_SFLASH_CHI_PASS__OFFSET, 0x00000006 +.set CYFLD_SFLASH_CHI_PASS__SIZE, 0x00000002 +.set CYREG_SFLASH_DIE_SORT, 0x0ffff17e +.set CYFLD_SFLASH_S1_PASS__OFFSET, 0x00000000 +.set CYFLD_SFLASH_S1_PASS__SIZE, 0x00000002 +.set CYFLD_SFLASH_S2_PASS__OFFSET, 0x00000002 +.set CYFLD_SFLASH_S2_PASS__SIZE, 0x00000002 +.set CYFLD_SFLASH_S3_PASS__OFFSET, 0x00000004 +.set CYFLD_SFLASH_S3_PASS__SIZE, 0x00000002 +.set CYREG_SFLASH_DIE_MINOR, 0x0ffff17f +.set CYFLD_SFLASH_MINOR__OFFSET, 0x00000000 +.set CYFLD_SFLASH_MINOR__SIZE, 0x00000008 +.set CYREG_SFLASH_PE_TE_DATA00, 0x0ffff180 +.set CYREG_SFLASH_PE_TE_DATA01, 0x0ffff181 +.set CYREG_SFLASH_PE_TE_DATA02, 0x0ffff182 +.set CYREG_SFLASH_PE_TE_DATA03, 0x0ffff183 +.set CYREG_SFLASH_PE_TE_DATA04, 0x0ffff184 +.set CYREG_SFLASH_PE_TE_DATA05, 0x0ffff185 +.set CYREG_SFLASH_PE_TE_DATA06, 0x0ffff186 +.set CYREG_SFLASH_PE_TE_DATA07, 0x0ffff187 +.set CYREG_SFLASH_PE_TE_DATA08, 0x0ffff188 +.set CYREG_SFLASH_PE_TE_DATA09, 0x0ffff189 +.set CYREG_SFLASH_PE_TE_DATA10, 0x0ffff18a +.set CYREG_SFLASH_PE_TE_DATA11, 0x0ffff18b +.set CYREG_SFLASH_PE_TE_DATA12, 0x0ffff18c +.set CYREG_SFLASH_PE_TE_DATA13, 0x0ffff18d +.set CYREG_SFLASH_PE_TE_DATA14, 0x0ffff18e +.set CYREG_SFLASH_PE_TE_DATA15, 0x0ffff18f +.set CYREG_SFLASH_PE_TE_DATA16, 0x0ffff190 +.set CYREG_SFLASH_PE_TE_DATA17, 0x0ffff191 +.set CYREG_SFLASH_PE_TE_DATA18, 0x0ffff192 +.set CYREG_SFLASH_PE_TE_DATA19, 0x0ffff193 +.set CYREG_SFLASH_PE_TE_DATA20, 0x0ffff194 +.set CYREG_SFLASH_PE_TE_DATA21, 0x0ffff195 +.set CYREG_SFLASH_PE_TE_DATA22, 0x0ffff196 +.set CYREG_SFLASH_PE_TE_DATA23, 0x0ffff197 +.set CYREG_SFLASH_PE_TE_DATA24, 0x0ffff198 +.set CYREG_SFLASH_PE_TE_DATA25, 0x0ffff199 +.set CYREG_SFLASH_PE_TE_DATA26, 0x0ffff19a +.set CYREG_SFLASH_PE_TE_DATA27, 0x0ffff19b +.set CYREG_SFLASH_PE_TE_DATA28, 0x0ffff19c +.set CYREG_SFLASH_PE_TE_DATA29, 0x0ffff19d +.set CYREG_SFLASH_PE_TE_DATA30, 0x0ffff19e +.set CYREG_SFLASH_PE_TE_DATA31, 0x0ffff19f +.set CYREG_SFLASH_PP, 0x0ffff1a0 +.set CYFLD_SFLASH_PERIOD__OFFSET, 0x00000000 +.set CYFLD_SFLASH_PERIOD__SIZE, 0x00000018 +.set CYFLD_SFLASH_PDAC__OFFSET, 0x00000018 +.set CYFLD_SFLASH_PDAC__SIZE, 0x00000004 +.set CYFLD_SFLASH_NDAC__OFFSET, 0x0000001c +.set CYFLD_SFLASH_NDAC__SIZE, 0x00000004 +.set CYREG_SFLASH_E, 0x0ffff1a4 +.set CYREG_SFLASH_P, 0x0ffff1a8 +.set CYREG_SFLASH_EA_E, 0x0ffff1ac +.set CYREG_SFLASH_EA_P, 0x0ffff1b0 +.set CYREG_SFLASH_ES_E, 0x0ffff1b4 +.set CYREG_SFLASH_ES_P_EO, 0x0ffff1b8 +.set CYREG_SFLASH_E_VCTAT, 0x0ffff1bc +.set CYFLD_SFLASH_VCTAT_SLOPE__OFFSET, 0x00000000 +.set CYFLD_SFLASH_VCTAT_SLOPE__SIZE, 0x00000004 +.set CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET, 0x00000004 +.set CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE, 0x00000002 +.set CYFLD_SFLASH_VCTAT_ENABLE__OFFSET, 0x00000006 +.set CYFLD_SFLASH_VCTAT_ENABLE__SIZE, 0x00000001 +.set CYREG_SFLASH_P_VCTAT, 0x0ffff1bd +.set CYREG_SFLASH_MARGIN, 0x0ffff1be +.set CYFLD_SFLASH_MDAC__OFFSET, 0x00000000 +.set CYFLD_SFLASH_MDAC__SIZE, 0x00000008 +.set CYREG_SFLASH_SPCIF_TRIM1, 0x0ffff1bf +.set CYFLD_SFLASH_BDAC__OFFSET, 0x00000000 +.set CYFLD_SFLASH_BDAC__SIZE, 0x00000004 +.set CYREG_SFLASH_IMO_MAXF0, 0x0ffff1c0 +.set CYFLD_SFLASH_MAXFREQ__OFFSET, 0x00000000 +.set CYFLD_SFLASH_MAXFREQ__SIZE, 0x00000006 +.set CYREG_SFLASH_IMO_ABS0, 0x0ffff1c1 +.set CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ABS_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_SFLASH_IMO_TMPCO0, 0x0ffff1c2 +.set CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_SFLASH_IMO_MAXF1, 0x0ffff1c3 +.set CYREG_SFLASH_IMO_ABS1, 0x0ffff1c4 +.set CYREG_SFLASH_IMO_TMPCO1, 0x0ffff1c5 +.set CYREG_SFLASH_IMO_MAXF2, 0x0ffff1c6 +.set CYREG_SFLASH_IMO_ABS2, 0x0ffff1c7 +.set CYREG_SFLASH_IMO_TMPCO2, 0x0ffff1c8 +.set CYREG_SFLASH_IMO_MAXF3, 0x0ffff1c9 +.set CYREG_SFLASH_IMO_ABS3, 0x0ffff1ca +.set CYREG_SFLASH_IMO_TMPCO3, 0x0ffff1cb +.set CYREG_SFLASH_IMO_ABS4, 0x0ffff1cc +.set CYREG_SFLASH_IMO_TMPCO4, 0x0ffff1cd +.set CYREG_SFLASH_IMO_TRIM00, 0x0ffff1d0 +.set CYFLD_SFLASH_OFFSET__OFFSET, 0x00000000 +.set CYFLD_SFLASH_OFFSET__SIZE, 0x00000008 +.set CYREG_SFLASH_IMO_TRIM01, 0x0ffff1d1 +.set CYREG_SFLASH_IMO_TRIM02, 0x0ffff1d2 +.set CYREG_SFLASH_IMO_TRIM03, 0x0ffff1d3 +.set CYREG_SFLASH_IMO_TRIM04, 0x0ffff1d4 +.set CYREG_SFLASH_IMO_TRIM05, 0x0ffff1d5 +.set CYREG_SFLASH_IMO_TRIM06, 0x0ffff1d6 +.set CYREG_SFLASH_IMO_TRIM07, 0x0ffff1d7 +.set CYREG_SFLASH_IMO_TRIM08, 0x0ffff1d8 +.set CYREG_SFLASH_IMO_TRIM09, 0x0ffff1d9 +.set CYREG_SFLASH_IMO_TRIM10, 0x0ffff1da +.set CYREG_SFLASH_IMO_TRIM11, 0x0ffff1db +.set CYREG_SFLASH_IMO_TRIM12, 0x0ffff1dc +.set CYREG_SFLASH_IMO_TRIM13, 0x0ffff1dd +.set CYREG_SFLASH_IMO_TRIM14, 0x0ffff1de +.set CYREG_SFLASH_IMO_TRIM15, 0x0ffff1df +.set CYREG_SFLASH_IMO_TRIM16, 0x0ffff1e0 +.set CYREG_SFLASH_IMO_TRIM17, 0x0ffff1e1 +.set CYREG_SFLASH_IMO_TRIM18, 0x0ffff1e2 +.set CYREG_SFLASH_IMO_TRIM19, 0x0ffff1e3 +.set CYREG_SFLASH_IMO_TRIM20, 0x0ffff1e4 +.set CYREG_SFLASH_IMO_TRIM21, 0x0ffff1e5 +.set CYREG_SFLASH_IMO_TRIM22, 0x0ffff1e6 +.set CYREG_SFLASH_IMO_TRIM23, 0x0ffff1e7 +.set CYREG_SFLASH_IMO_TRIM24, 0x0ffff1e8 +.set CYREG_SFLASH_IMO_TRIM25, 0x0ffff1e9 +.set CYREG_SFLASH_IMO_TRIM26, 0x0ffff1ea +.set CYREG_SFLASH_IMO_TRIM27, 0x0ffff1eb +.set CYREG_SFLASH_IMO_TRIM28, 0x0ffff1ec +.set CYREG_SFLASH_IMO_TRIM29, 0x0ffff1ed +.set CYREG_SFLASH_IMO_TRIM30, 0x0ffff1ee +.set CYREG_SFLASH_IMO_TRIM31, 0x0ffff1ef +.set CYREG_SFLASH_IMO_TRIM32, 0x0ffff1f0 +.set CYREG_SFLASH_IMO_TRIM33, 0x0ffff1f1 +.set CYREG_SFLASH_IMO_TRIM34, 0x0ffff1f2 +.set CYREG_SFLASH_IMO_TRIM35, 0x0ffff1f3 +.set CYREG_SFLASH_IMO_TRIM36, 0x0ffff1f4 +.set CYREG_SFLASH_IMO_TRIM37, 0x0ffff1f5 +.set CYREG_SFLASH_IMO_TRIM38, 0x0ffff1f6 +.set CYREG_SFLASH_IMO_TRIM39, 0x0ffff1f7 +.set CYREG_SFLASH_IMO_TRIM40, 0x0ffff1f8 +.set CYREG_SFLASH_IMO_TRIM41, 0x0ffff1f9 +.set CYREG_SFLASH_IMO_TRIM42, 0x0ffff1fa +.set CYREG_SFLASH_IMO_TRIM43, 0x0ffff1fb +.set CYREG_SFLASH_IMO_TRIM44, 0x0ffff1fc +.set CYREG_SFLASH_IMO_TRIM45, 0x0ffff1fd +.set CYREG_SFLASH_CHECKSUM, 0x0ffff1fe +.set CYFLD_SFLASH_CHECKSUM__OFFSET, 0x00000000 +.set CYFLD_SFLASH_CHECKSUM__SIZE, 0x00000010 +.set CYDEV_SROM_BASE, 0x10000000 +.set CYDEV_SROM_SIZE, 0x00001000 +.set CYREG_SROM_DATA_MBASE, 0x10000000 +.set CYREG_SROM_DATA_MSIZE, 0x00001000 +.set CYDEV_SRAM_BASE, 0x20000000 +.set CYDEV_SRAM_SIZE, 0x00001000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00001000 +.set CYDEV_CPUSS_BASE, 0x40000000 +.set CYDEV_CPUSS_SIZE, 0x00010000 +.set CYREG_CPUSS_CONFIG, 0x40000000 +.set CYFLD_CPUSS_VECS_IN_RAM__OFFSET, 0x00000000 +.set CYFLD_CPUSS_VECS_IN_RAM__SIZE, 0x00000001 +.set CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET, 0x00000001 +.set CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE, 0x00000001 +.set CYREG_CPUSS_SYSREQ, 0x40000004 +.set CYFLD_CPUSS_COMMAND__OFFSET, 0x00000000 +.set CYFLD_CPUSS_COMMAND__SIZE, 0x00000010 +.set CYFLD_CPUSS_NO_RST_OVR__OFFSET, 0x0000001b +.set CYFLD_CPUSS_NO_RST_OVR__SIZE, 0x00000001 +.set CYFLD_CPUSS_PRIVILEGED__OFFSET, 0x0000001c +.set CYFLD_CPUSS_PRIVILEGED__SIZE, 0x00000001 +.set CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET, 0x0000001d +.set CYFLD_CPUSS_ROM_ACCESS_EN__SIZE, 0x00000001 +.set CYFLD_CPUSS_HMASTER__OFFSET, 0x0000001e +.set CYFLD_CPUSS_HMASTER__SIZE, 0x00000001 +.set CYFLD_CPUSS_SYSREQ__OFFSET, 0x0000001f +.set CYFLD_CPUSS_SYSREQ__SIZE, 0x00000001 +.set CYREG_CPUSS_SYSARG, 0x40000008 +.set CYFLD_CPUSS_ARG32__OFFSET, 0x00000000 +.set CYFLD_CPUSS_ARG32__SIZE, 0x00000020 +.set CYREG_CPUSS_PROTECTION, 0x4000000c +.set CYFLD_CPUSS_PROT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_PROT__SIZE, 0x00000004 +.set CYVAL_CPUSS_PROT_VIRGIN, 0x00000000 +.set CYVAL_CPUSS_PROT_OPEN, 0x00000001 +.set CYVAL_CPUSS_PROT_PROTECTED, 0x00000002 +.set CYVAL_CPUSS_PROT_KILL, 0x00000004 +.set CYVAL_CPUSS_PROT_BOOT, 0x00000008 +.set CYFLD_CPUSS_PROT_LOCK__OFFSET, 0x0000001f +.set CYFLD_CPUSS_PROT_LOCK__SIZE, 0x00000001 +.set CYREG_CPUSS_PRIV_ROM, 0x40000010 +.set CYFLD_CPUSS_ROM_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_ROM_LIMIT__SIZE, 0x00000008 +.set CYREG_CPUSS_PRIV_RAM, 0x40000014 +.set CYFLD_CPUSS_RAM_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_RAM_LIMIT__SIZE, 0x00000009 +.set CYREG_CPUSS_PRIV_FLASH, 0x40000018 +.set CYFLD_CPUSS_FLASH_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_FLASH_LIMIT__SIZE, 0x0000000b +.set CYREG_CPUSS_WOUNDING, 0x4000001c +.set CYFLD_CPUSS_RAM_SIZE__OFFSET, 0x00000000 +.set CYFLD_CPUSS_RAM_SIZE__SIZE, 0x00000009 +.set CYFLD_CPUSS_RAM_WOUND__OFFSET, 0x00000010 +.set CYFLD_CPUSS_RAM_WOUND__SIZE, 0x00000003 +.set CYVAL_CPUSS_RAM_WOUND_FULL, 0x00000000 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_2, 0x00000001 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_4, 0x00000002 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_8, 0x00000003 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_16, 0x00000004 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_32, 0x00000005 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_64, 0x00000006 +.set CYVAL_CPUSS_RAM_WOUND_DIV_BY_128, 0x00000007 +.set CYFLD_CPUSS_FLASH_WOUND__OFFSET, 0x00000014 +.set CYFLD_CPUSS_FLASH_WOUND__SIZE, 0x00000003 +.set CYVAL_CPUSS_FLASH_WOUND_FULL, 0x00000000 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2, 0x00000001 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4, 0x00000002 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8, 0x00000003 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16, 0x00000004 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32, 0x00000005 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64, 0x00000006 +.set CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128, 0x00000007 +.set CYREG_CPUSS_INTR_SELECT, 0x40000020 +.set CYFLD_CPUSS_SELECT32__OFFSET, 0x00000000 +.set CYFLD_CPUSS_SELECT32__SIZE, 0x00000020 +.set CYDEV_HSIOM_BASE, 0x40010000 +.set CYDEV_HSIOM_SIZE, 0x00001000 +.set CYREG_HSIOM_PORT_SEL0, 0x40010000 +.set CYFLD_HSIOM_SEL0__OFFSET, 0x00000000 +.set CYFLD_HSIOM_SEL0__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL0_GPIO, 0x00000000 +.set CYVAL_HSIOM_SEL0_GPIO_DSI, 0x00000001 +.set CYVAL_HSIOM_SEL0_DSI_DSI, 0x00000002 +.set CYVAL_HSIOM_SEL0_DSI_GPIO, 0x00000003 +.set CYVAL_HSIOM_SEL0_CSD_SENSE, 0x00000004 +.set CYVAL_HSIOM_SEL0_CSD_SHIELD, 0x00000005 +.set CYVAL_HSIOM_SEL0_AMUXA, 0x00000006 +.set CYVAL_HSIOM_SEL0_AMUXB, 0x00000007 +.set CYVAL_HSIOM_SEL0_ACT_0, 0x00000008 +.set CYVAL_HSIOM_SEL0_ACT_1, 0x00000009 +.set CYVAL_HSIOM_SEL0_ACT_2, 0x0000000a +.set CYVAL_HSIOM_SEL0_ACT_3, 0x0000000b +.set CYVAL_HSIOM_SEL0_LCD_COM, 0x0000000c +.set CYVAL_HSIOM_SEL0_LCD_SEG, 0x0000000d +.set CYVAL_HSIOM_SEL0_DPSLP_0, 0x0000000e +.set CYVAL_HSIOM_SEL0_DPSLP_1, 0x0000000f +.set CYVAL_HSIOM_SEL0_COMP1_INP, 0x00000000 +.set CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1, 0x0000000f +.set CYFLD_HSIOM_SEL1__OFFSET, 0x00000004 +.set CYFLD_HSIOM_SEL1__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL1_COMP1_INN, 0x00000000 +.set CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2, 0x0000000f +.set CYFLD_HSIOM_SEL2__OFFSET, 0x00000008 +.set CYFLD_HSIOM_SEL2__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL2_COMP2_INP, 0x00000000 +.set CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3, 0x0000000f +.set CYFLD_HSIOM_SEL3__OFFSET, 0x0000000c +.set CYFLD_HSIOM_SEL3__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL3_COMP2_INN, 0x00000000 +.set CYFLD_HSIOM_SEL4__OFFSET, 0x00000010 +.set CYFLD_HSIOM_SEL4__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL4_SCB1_UART_RX, 0x00000009 +.set CYVAL_HSIOM_SEL4_SCB1_I2C_SCL, 0x0000000e +.set CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI, 0x0000000f +.set CYFLD_HSIOM_SEL5__OFFSET, 0x00000014 +.set CYFLD_HSIOM_SEL5__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL5_SCB1_UART_TX, 0x00000009 +.set CYVAL_HSIOM_SEL5_SCB1_I2C_SDA, 0x0000000e +.set CYVAL_HSIOM_SEL5_SCB1_SPI_MISO, 0x0000000f +.set CYFLD_HSIOM_SEL6__OFFSET, 0x00000018 +.set CYFLD_HSIOM_SEL6__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL6_EXT_CLK, 0x00000008 +.set CYVAL_HSIOM_SEL6_SCB1_SPI_CLK, 0x0000000f +.set CYFLD_HSIOM_SEL7__OFFSET, 0x0000001c +.set CYFLD_HSIOM_SEL7__SIZE, 0x00000004 +.set CYVAL_HSIOM_SEL7_WAKEUP, 0x0000000e +.set CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0, 0x0000000f +.set CYREG_HSIOM_PORT_SEL1, 0x40010004 +.set CYREG_HSIOM_PORT_SEL2, 0x40010008 +.set CYREG_HSIOM_PORT_SEL3, 0x4001000c +.set CYREG_HSIOM_PORT_SEL4, 0x40010010 +.set CYDEV_CLK_BASE, 0x40020000 +.set CYDEV_CLK_SIZE, 0x00010000 +.set CYREG_CLK_DIVIDER_A00, 0x40020000 +.set CYFLD_CLK_DIVIDER_A__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_A__SIZE, 0x00000010 +.set CYFLD_CLK_ENABLE_A__OFFSET, 0x0000001f +.set CYFLD_CLK_ENABLE_A__SIZE, 0x00000001 +.set CYREG_CLK_DIVIDER_A01, 0x40020004 +.set CYREG_CLK_DIVIDER_A02, 0x40020008 +.set CYREG_CLK_DIVIDER_B00, 0x40020040 +.set CYFLD_CLK_DIVIDER_B__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_B__SIZE, 0x00000010 +.set CYFLD_CLK_CASCADE_A_B__OFFSET, 0x0000001e +.set CYFLD_CLK_CASCADE_A_B__SIZE, 0x00000001 +.set CYFLD_CLK_ENABLE_B__OFFSET, 0x0000001f +.set CYFLD_CLK_ENABLE_B__SIZE, 0x00000001 +.set CYREG_CLK_DIVIDER_B01, 0x40020044 +.set CYREG_CLK_DIVIDER_B02, 0x40020048 +.set CYREG_CLK_DIVIDER_C00, 0x40020080 +.set CYFLD_CLK_DIVIDER_C__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_C__SIZE, 0x00000010 +.set CYFLD_CLK_CASCADE_B_C__OFFSET, 0x0000001e +.set CYFLD_CLK_CASCADE_B_C__SIZE, 0x00000001 +.set CYFLD_CLK_ENABLE_C__OFFSET, 0x0000001f +.set CYFLD_CLK_ENABLE_C__SIZE, 0x00000001 +.set CYREG_CLK_DIVIDER_C01, 0x40020084 +.set CYREG_CLK_DIVIDER_C02, 0x40020088 +.set CYREG_CLK_DIVIDER_FRAC_A00, 0x40020100 +.set CYFLD_CLK_FRAC_A__OFFSET, 0x00000010 +.set CYFLD_CLK_FRAC_A__SIZE, 0x00000005 +.set CYREG_CLK_DIVIDER_FRAC_B00, 0x40020140 +.set CYFLD_CLK_FRAC_B__OFFSET, 0x00000010 +.set CYFLD_CLK_FRAC_B__SIZE, 0x00000005 +.set CYREG_CLK_DIVIDER_FRAC_C00, 0x40020180 +.set CYFLD_CLK_FRAC_C__OFFSET, 0x00000010 +.set CYFLD_CLK_FRAC_C__SIZE, 0x00000005 +.set CYREG_CLK_SELECT00, 0x40020200 +.set CYFLD_CLK_DIVIDER_N__OFFSET, 0x00000000 +.set CYFLD_CLK_DIVIDER_N__SIZE, 0x00000004 +.set CYFLD_CLK_DIVIDER_ABC__OFFSET, 0x00000004 +.set CYFLD_CLK_DIVIDER_ABC__SIZE, 0x00000002 +.set CYVAL_CLK_DIVIDER_ABC_OFF, 0x00000000 +.set CYVAL_CLK_DIVIDER_ABC_A, 0x00000001 +.set CYVAL_CLK_DIVIDER_ABC_B, 0x00000002 +.set CYVAL_CLK_DIVIDER_ABC_C, 0x00000003 +.set CYREG_CLK_SELECT01, 0x40020204 +.set CYREG_CLK_SELECT02, 0x40020208 +.set CYREG_CLK_SELECT03, 0x4002020c +.set CYREG_CLK_SELECT04, 0x40020210 +.set CYREG_CLK_SELECT05, 0x40020214 +.set CYREG_CLK_SELECT06, 0x40020218 +.set CYREG_CLK_SELECT07, 0x4002021c +.set CYREG_CLK_SELECT08, 0x40020220 +.set CYREG_CLK_SELECT09, 0x40020224 +.set CYREG_CLK_SELECT10, 0x40020228 +.set CYREG_CLK_SELECT11, 0x4002022c +.set CYREG_CLK_SELECT12, 0x40020230 +.set CYREG_CLK_SELECT13, 0x40020234 +.set CYREG_CLK_SELECT14, 0x40020238 +.set CYREG_CLK_SELECT15, 0x4002023c +.set CYDEV_TST_BASE, 0x40030000 +.set CYDEV_TST_SIZE, 0x00010000 +.set CYREG_TST_CTRL, 0x40030000 +.set CYFLD_TST_DAP_NO_ACCESS__OFFSET, 0x00000000 +.set CYFLD_TST_DAP_NO_ACCESS__SIZE, 0x00000001 +.set CYFLD_TST_DAP_NO_DEBUG__OFFSET, 0x00000001 +.set CYFLD_TST_DAP_NO_DEBUG__SIZE, 0x00000001 +.set CYFLD_TST_SWD_CONNECTED__OFFSET, 0x00000002 +.set CYFLD_TST_SWD_CONNECTED__SIZE, 0x00000001 +.set CYFLD_TST_TEST_RESET_EN_N__OFFSET, 0x00000008 +.set CYFLD_TST_TEST_RESET_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SET_EN_N__OFFSET, 0x00000009 +.set CYFLD_TST_TEST_SET_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_ICG_EN_N__OFFSET, 0x0000000a +.set CYFLD_TST_TEST_ICG_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET, 0x0000000b +.set CYFLD_TST_TEST_OCC0_1_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET, 0x0000000c +.set CYFLD_TST_TEST_OCC0_2_EN_N__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET, 0x0000000d +.set CYFLD_TST_TEST_SLPISOLATE_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET, 0x0000000e +.set CYFLD_TST_TEST_SYSISOLATE_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET, 0x0000000f +.set CYFLD_TST_TEST_SLPRETAIN_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET, 0x00000010 +.set CYFLD_TST_TEST_SYSRETAIN_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SPARE1_EN__OFFSET, 0x00000011 +.set CYFLD_TST_TEST_SPARE1_EN__SIZE, 0x00000001 +.set CYFLD_TST_TEST_SPARE2_EN__OFFSET, 0x00000012 +.set CYFLD_TST_TEST_SPARE2_EN__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET, 0x00000018 +.set CYFLD_TST_SCAN_OCC_OBSERVE__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_TRF1__OFFSET, 0x00000019 +.set CYFLD_TST_SCAN_TRF1__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_TRF__OFFSET, 0x0000001a +.set CYFLD_TST_SCAN_TRF__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_IDDQ__OFFSET, 0x0000001b +.set CYFLD_TST_SCAN_IDDQ__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_COMPRESS__OFFSET, 0x0000001c +.set CYFLD_TST_SCAN_COMPRESS__SIZE, 0x00000001 +.set CYFLD_TST_SCAN_MODE__OFFSET, 0x0000001d +.set CYFLD_TST_SCAN_MODE__SIZE, 0x00000001 +.set CYFLD_TST_PTM_MODE_EN__OFFSET, 0x0000001e +.set CYFLD_TST_PTM_MODE_EN__SIZE, 0x00000001 +.set CYREG_TST_ADFT_CTRL, 0x40030004 +.set CYFLD_TST_ENABLE__OFFSET, 0x0000001f +.set CYFLD_TST_ENABLE__SIZE, 0x00000001 +.set CYREG_TST_DDFT_CTRL, 0x40030008 +.set CYFLD_TST_DFT_SEL1__OFFSET, 0x00000000 +.set CYFLD_TST_DFT_SEL1__SIZE, 0x00000006 +.set CYVAL_TST_DFT_SEL1_VSS, 0x00000000 +.set CYVAL_TST_DFT_SEL1_CLK1, 0x00000001 +.set CYVAL_TST_DFT_SEL1_CLK2, 0x00000002 +.set CYVAL_TST_DFT_SEL1_PWR1, 0x00000003 +.set CYVAL_TST_DFT_SEL1_PWR2, 0x00000004 +.set CYVAL_TST_DFT_SEL1_VMON, 0x00000005 +.set CYVAL_TST_DFT_SEL1_TSS_VDDA_OK, 0x00000006 +.set CYVAL_TST_DFT_SEL1_ADFT_TRIP1, 0x00000007 +.set CYVAL_TST_DFT_SEL1_ADFT_TRIP2, 0x00000008 +.set CYVAL_TST_DFT_SEL1_TSS1, 0x00000009 +.set CYVAL_TST_DFT_SEL1_TSS2, 0x0000000a +.set CYVAL_TST_DFT_SEL1_TSS3, 0x0000000b +.set CYVAL_TST_DFT_SEL1_TSS4, 0x0000000c +.set CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS, 0x0000000d +.set CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI, 0x0000000e +.set CYFLD_TST_DFT_SEL2__OFFSET, 0x00000008 +.set CYFLD_TST_DFT_SEL2__SIZE, 0x00000006 +.set CYVAL_TST_DFT_SEL2_VSS, 0x00000000 +.set CYVAL_TST_DFT_SEL2_CLK1, 0x00000001 +.set CYVAL_TST_DFT_SEL2_CLK2, 0x00000002 +.set CYVAL_TST_DFT_SEL2_PWR1, 0x00000003 +.set CYVAL_TST_DFT_SEL2_PWR2, 0x00000004 +.set CYVAL_TST_DFT_SEL2_VMON, 0x00000005 +.set CYVAL_TST_DFT_SEL2_TSS_VDDA_OK, 0x00000006 +.set CYVAL_TST_DFT_SEL2_ADFT_TRIP1, 0x00000007 +.set CYVAL_TST_DFT_SEL2_ADFT_TRIP2, 0x00000008 +.set CYVAL_TST_DFT_SEL2_TSS1, 0x00000009 +.set CYVAL_TST_DFT_SEL2_TSS2, 0x0000000a +.set CYVAL_TST_DFT_SEL2_TSS3, 0x0000000b +.set CYVAL_TST_DFT_SEL2_TSS4, 0x0000000c +.set CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS, 0x0000000d +.set CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI, 0x0000000e +.set CYFLD_TST_EDGE__OFFSET, 0x0000001c +.set CYFLD_TST_EDGE__SIZE, 0x00000001 +.set CYVAL_TST_EDGE_POSEDGE, 0x00000000 +.set CYVAL_TST_EDGE_NEGEDGE, 0x00000001 +.set CYFLD_TST_DIVIDE__OFFSET, 0x0000001d +.set CYFLD_TST_DIVIDE__SIZE, 0x00000002 +.set CYVAL_TST_DIVIDE_DIRECT, 0x00000000 +.set CYVAL_TST_DIVIDE_DIV_BY_2, 0x00000001 +.set CYVAL_TST_DIVIDE_DIV_BY_4, 0x00000002 +.set CYVAL_TST_DIVIDE_DIV_BY_8, 0x00000003 +.set CYREG_TST_MODE, 0x40030014 +.set CYFLD_TST_TEST_MODE__OFFSET, 0x0000001f +.set CYFLD_TST_TEST_MODE__SIZE, 0x00000001 +.set CYREG_TST_TRIM_CNTR1, 0x40030018 +.set CYFLD_TST_COUNTER__OFFSET, 0x00000000 +.set CYFLD_TST_COUNTER__SIZE, 0x00000010 +.set CYFLD_TST_COUNTER_DONE__OFFSET, 0x0000001f +.set CYFLD_TST_COUNTER_DONE__SIZE, 0x00000001 +.set CYREG_TST_TRIM_CNTR2, 0x4003001c +.set CYDEV_PRT0_BASE, 0x40040000 +.set CYDEV_PRT0_SIZE, 0x00000100 +.set CYREG_PRT0_DR, 0x40040000 +.set CYFLD_PRT_DATAREG__OFFSET, 0x00000000 +.set CYFLD_PRT_DATAREG__SIZE, 0x00000008 +.set CYREG_PRT0_PS, 0x40040004 +.set CYFLD_PRT_PINSTATE__OFFSET, 0x00000000 +.set CYFLD_PRT_PINSTATE__SIZE, 0x00000008 +.set CYFLD_PRT_PINSTATE_FLT__OFFSET, 0x00000008 +.set CYFLD_PRT_PINSTATE_FLT__SIZE, 0x00000001 +.set CYREG_PRT0_PC, 0x40040008 +.set CYFLD_PRT_DM__OFFSET, 0x00000000 +.set CYFLD_PRT_DM__SIZE, 0x00000018 +.set CYVAL_PRT_DM_OFF, 0x00000000 +.set CYVAL_PRT_DM_INPUT, 0x00000001 +.set CYVAL_PRT_DM_0_PU, 0x00000002 +.set CYVAL_PRT_DM_PD_1, 0x00000003 +.set CYVAL_PRT_DM_0_Z, 0x00000004 +.set CYVAL_PRT_DM_Z_1, 0x00000005 +.set CYVAL_PRT_DM_0_1, 0x00000006 +.set CYVAL_PRT_DM_PD_PU, 0x00000007 +.set CYFLD_PRT_VTRIP_SEL__OFFSET, 0x00000018 +.set CYFLD_PRT_VTRIP_SEL__SIZE, 0x00000001 +.set CYFLD_PRT_SLOW__OFFSET, 0x00000019 +.set CYFLD_PRT_SLOW__SIZE, 0x00000001 +.set CYREG_PRT0_INTCFG, 0x4004000c +.set CYFLD_PRT_INTTYPE__OFFSET, 0x00000000 +.set CYFLD_PRT_INTTYPE__SIZE, 0x00000010 +.set CYVAL_PRT_INTTYPE_DISABLE, 0x00000000 +.set CYVAL_PRT_INTTYPE_RISING, 0x00000001 +.set CYVAL_PRT_INTTYPE_FALLING, 0x00000002 +.set CYVAL_PRT_INTTYPE_BOTH, 0x00000003 +.set CYFLD_PRT_INTTYPE_FLT__OFFSET, 0x00000010 +.set CYFLD_PRT_INTTYPE_FLT__SIZE, 0x00000002 +.set CYVAL_PRT_INTTYPE_FLT_DISABLE, 0x00000000 +.set CYVAL_PRT_INTTYPE_FLT_RISING, 0x00000001 +.set CYVAL_PRT_INTTYPE_FLT_FALLING, 0x00000002 +.set CYVAL_PRT_INTTYPE_FLT_BOTH, 0x00000003 +.set CYFLD_PRT_FLT_SELECT__OFFSET, 0x00000012 +.set CYFLD_PRT_FLT_SELECT__SIZE, 0x00000003 +.set CYREG_PRT0_INTSTAT, 0x40040010 +.set CYFLD_PRT_INTSTAT__OFFSET, 0x00000000 +.set CYFLD_PRT_INTSTAT__SIZE, 0x00000008 +.set CYFLD_PRT_INTSTAT_FLT__OFFSET, 0x00000008 +.set CYFLD_PRT_INTSTAT_FLT__SIZE, 0x00000001 +.set CYFLD_PRT_PS__OFFSET, 0x00000010 +.set CYFLD_PRT_PS__SIZE, 0x00000008 +.set CYFLD_PRT_PS_FLT__OFFSET, 0x00000018 +.set CYFLD_PRT_PS_FLT__SIZE, 0x00000001 +.set CYREG_PRT0_PC2, 0x40040018 +.set CYFLD_PRT_INP_DIS__OFFSET, 0x00000000 +.set CYFLD_PRT_INP_DIS__SIZE, 0x00000008 +.set CYDEV_PRT1_BASE, 0x40040100 +.set CYDEV_PRT1_SIZE, 0x00000100 +.set CYREG_PRT1_DR, 0x40040100 +.set CYREG_PRT1_PS, 0x40040104 +.set CYREG_PRT1_PC, 0x40040108 +.set CYREG_PRT1_INTCFG, 0x4004010c +.set CYREG_PRT1_INTSTAT, 0x40040110 +.set CYREG_PRT1_PC2, 0x40040118 +.set CYDEV_PRT2_BASE, 0x40040200 +.set CYDEV_PRT2_SIZE, 0x00000100 +.set CYREG_PRT2_DR, 0x40040200 +.set CYREG_PRT2_PS, 0x40040204 +.set CYREG_PRT2_PC, 0x40040208 +.set CYREG_PRT2_INTCFG, 0x4004020c +.set CYREG_PRT2_INTSTAT, 0x40040210 +.set CYREG_PRT2_PC2, 0x40040218 +.set CYDEV_PRT3_BASE, 0x40040300 +.set CYDEV_PRT3_SIZE, 0x00000100 +.set CYREG_PRT3_DR, 0x40040300 +.set CYREG_PRT3_PS, 0x40040304 +.set CYREG_PRT3_PC, 0x40040308 +.set CYREG_PRT3_INTCFG, 0x4004030c +.set CYREG_PRT3_INTSTAT, 0x40040310 +.set CYREG_PRT3_PC2, 0x40040318 +.set CYDEV_PRT4_BASE, 0x40040400 +.set CYDEV_PRT4_SIZE, 0x00000100 +.set CYREG_PRT4_DR, 0x40040400 +.set CYREG_PRT4_PS, 0x40040404 +.set CYREG_PRT4_PC, 0x40040408 +.set CYREG_PRT4_INTCFG, 0x4004040c +.set CYREG_PRT4_INTSTAT, 0x40040410 +.set CYREG_PRT4_PC2, 0x40040418 +.set CYDEV_TCPWM_BASE, 0x40050000 +.set CYDEV_TCPWM_SIZE, 0x00001000 +.set CYREG_TCPWM_CTRL, 0x40050000 +.set CYFLD_TCPWM_COUNTER_ENABLED__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_ENABLED__SIZE, 0x00000008 +.set CYREG_TCPWM_CMD, 0x40050008 +.set CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_CAPTURE__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_RELOAD__OFFSET, 0x00000008 +.set CYFLD_TCPWM_COUNTER_RELOAD__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_STOP__OFFSET, 0x00000010 +.set CYFLD_TCPWM_COUNTER_STOP__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_START__OFFSET, 0x00000018 +.set CYFLD_TCPWM_COUNTER_START__SIZE, 0x00000008 +.set CYREG_TCPWM_INTR_CAUSE, 0x4005000c +.set CYFLD_TCPWM_COUNTER_INT__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_INT__SIZE, 0x00000008 +.set CYDEV_TCPWM_CNT0_BASE, 0x40050100 +.set CYDEV_TCPWM_CNT0_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT0_CTRL, 0x40050100 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET, 0x00000001 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET, 0x00000003 +.set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_GENERIC__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_GENERIC__SIZE, 0x00000008 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY1, 0x00000000 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY2, 0x00000001 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY4, 0x00000002 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY8, 0x00000003 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY16, 0x00000004 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY32, 0x00000005 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY64, 0x00000006 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY128, 0x00000007 +.set CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET, 0x00000010 +.set CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP, 0x00000000 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN, 0x00000001 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1, 0x00000002 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2, 0x00000003 +.set CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET, 0x00000012 +.set CYFLD_TCPWM_CNT_ONE_SHOT__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET, 0x00000014 +.set CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1, 0x00000000 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2, 0x00000001 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4, 0x00000002 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT, 0x00000001 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT, 0x00000002 +.set CYFLD_TCPWM_CNT_MODE__OFFSET, 0x00000018 +.set CYFLD_TCPWM_CNT_MODE__SIZE, 0x00000003 +.set CYVAL_TCPWM_CNT_MODE_TIMER, 0x00000000 +.set CYVAL_TCPWM_CNT_MODE_CAPTURE, 0x00000002 +.set CYVAL_TCPWM_CNT_MODE_QUAD, 0x00000003 +.set CYVAL_TCPWM_CNT_MODE_PWM, 0x00000004 +.set CYVAL_TCPWM_CNT_MODE_PWM_DT, 0x00000005 +.set CYVAL_TCPWM_CNT_MODE_PWM_PR, 0x00000006 +.set CYREG_TCPWM_CNT0_STATUS, 0x40050104 +.set CYFLD_TCPWM_CNT_DOWN__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_DOWN__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_RUNNING__OFFSET, 0x0000001f +.set CYFLD_TCPWM_CNT_RUNNING__SIZE, 0x00000001 +.set CYREG_TCPWM_CNT0_COUNTER, 0x40050108 +.set CYFLD_TCPWM_CNT_COUNTER__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_COUNTER__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_CC, 0x4005010c +.set CYFLD_TCPWM_CNT_CC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CC__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_CC_BUFF, 0x40050110 +.set CYREG_TCPWM_CNT0_PERIOD, 0x40050114 +.set CYFLD_TCPWM_CNT_PERIOD__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_PERIOD__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_PERIOD_BUFF, 0x40050118 +.set CYREG_TCPWM_CNT0_TR_CTRL0, 0x40050120 +.set CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_COUNT_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_STOP_SEL__OFFSET, 0x0000000c +.set CYFLD_TCPWM_CNT_STOP_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_START_SEL__OFFSET, 0x00000010 +.set CYFLD_TCPWM_CNT_START_SEL__SIZE, 0x00000004 +.set CYREG_TCPWM_CNT0_TR_CTRL1, 0x40050124 +.set CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET, 0x00000006 +.set CYFLD_TCPWM_CNT_STOP_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_START_EDGE__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_START_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET, 0x00000003 +.set CYREG_TCPWM_CNT0_TR_CTRL2, 0x40050128 +.set CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE, 0x00000003 +.set CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE, 0x00000003 +.set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE, 0x00000003 +.set CYREG_TCPWM_CNT0_INTR, 0x40050130 +.set CYFLD_TCPWM_CNT_TC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_TC__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_CC_MATCH__OFFSET, 0x00000001 +.set CYFLD_TCPWM_CNT_CC_MATCH__SIZE, 0x00000001 +.set CYREG_TCPWM_CNT0_INTR_SET, 0x40050134 +.set CYREG_TCPWM_CNT0_INTR_MASK, 0x40050138 +.set CYREG_TCPWM_CNT0_INTR_MASKED, 0x4005013c +.set CYDEV_TCPWM_CNT1_BASE, 0x40050140 +.set CYDEV_TCPWM_CNT1_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT1_CTRL, 0x40050140 +.set CYREG_TCPWM_CNT1_STATUS, 0x40050144 +.set CYREG_TCPWM_CNT1_COUNTER, 0x40050148 +.set CYREG_TCPWM_CNT1_CC, 0x4005014c +.set CYREG_TCPWM_CNT1_CC_BUFF, 0x40050150 +.set CYREG_TCPWM_CNT1_PERIOD, 0x40050154 +.set CYREG_TCPWM_CNT1_PERIOD_BUFF, 0x40050158 +.set CYREG_TCPWM_CNT1_TR_CTRL0, 0x40050160 +.set CYREG_TCPWM_CNT1_TR_CTRL1, 0x40050164 +.set CYREG_TCPWM_CNT1_TR_CTRL2, 0x40050168 +.set CYREG_TCPWM_CNT1_INTR, 0x40050170 +.set CYREG_TCPWM_CNT1_INTR_SET, 0x40050174 +.set CYREG_TCPWM_CNT1_INTR_MASK, 0x40050178 +.set CYREG_TCPWM_CNT1_INTR_MASKED, 0x4005017c +.set CYDEV_TCPWM_CNT2_BASE, 0x40050180 +.set CYDEV_TCPWM_CNT2_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT2_CTRL, 0x40050180 +.set CYREG_TCPWM_CNT2_STATUS, 0x40050184 +.set CYREG_TCPWM_CNT2_COUNTER, 0x40050188 +.set CYREG_TCPWM_CNT2_CC, 0x4005018c +.set CYREG_TCPWM_CNT2_CC_BUFF, 0x40050190 +.set CYREG_TCPWM_CNT2_PERIOD, 0x40050194 +.set CYREG_TCPWM_CNT2_PERIOD_BUFF, 0x40050198 +.set CYREG_TCPWM_CNT2_TR_CTRL0, 0x400501a0 +.set CYREG_TCPWM_CNT2_TR_CTRL1, 0x400501a4 +.set CYREG_TCPWM_CNT2_TR_CTRL2, 0x400501a8 +.set CYREG_TCPWM_CNT2_INTR, 0x400501b0 +.set CYREG_TCPWM_CNT2_INTR_SET, 0x400501b4 +.set CYREG_TCPWM_CNT2_INTR_MASK, 0x400501b8 +.set CYREG_TCPWM_CNT2_INTR_MASKED, 0x400501bc +.set CYDEV_TCPWM_CNT3_BASE, 0x400501c0 +.set CYDEV_TCPWM_CNT3_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT3_CTRL, 0x400501c0 +.set CYREG_TCPWM_CNT3_STATUS, 0x400501c4 +.set CYREG_TCPWM_CNT3_COUNTER, 0x400501c8 +.set CYREG_TCPWM_CNT3_CC, 0x400501cc +.set CYREG_TCPWM_CNT3_CC_BUFF, 0x400501d0 +.set CYREG_TCPWM_CNT3_PERIOD, 0x400501d4 +.set CYREG_TCPWM_CNT3_PERIOD_BUFF, 0x400501d8 +.set CYREG_TCPWM_CNT3_TR_CTRL0, 0x400501e0 +.set CYREG_TCPWM_CNT3_TR_CTRL1, 0x400501e4 +.set CYREG_TCPWM_CNT3_TR_CTRL2, 0x400501e8 +.set CYREG_TCPWM_CNT3_INTR, 0x400501f0 +.set CYREG_TCPWM_CNT3_INTR_SET, 0x400501f4 +.set CYREG_TCPWM_CNT3_INTR_MASK, 0x400501f8 +.set CYREG_TCPWM_CNT3_INTR_MASKED, 0x400501fc +.set CYDEV_SCB0_BASE, 0x40060000 +.set CYDEV_SCB0_SIZE, 0x00010000 +.set CYREG_SCB0_CTRL, 0x40060000 +.set CYFLD_SCB_OVS__OFFSET, 0x00000000 +.set CYFLD_SCB_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_EC_AM_MODE__OFFSET, 0x00000008 +.set CYFLD_SCB_EC_AM_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_EC_OP_MODE__OFFSET, 0x00000009 +.set CYFLD_SCB_EC_OP_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_MODE__OFFSET, 0x0000000a +.set CYFLD_SCB_EZ_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_ADDR_ACCEPT__OFFSET, 0x00000010 +.set CYFLD_SCB_ADDR_ACCEPT__SIZE, 0x00000001 +.set CYFLD_SCB_BLOCK__OFFSET, 0x00000011 +.set CYFLD_SCB_BLOCK__SIZE, 0x00000001 +.set CYFLD_SCB_MODE__OFFSET, 0x00000018 +.set CYFLD_SCB_MODE__SIZE, 0x00000002 +.set CYVAL_SCB_MODE_I2C, 0x00000000 +.set CYVAL_SCB_MODE_SPI, 0x00000001 +.set CYVAL_SCB_MODE_UART, 0x00000002 +.set CYFLD_SCB_ENABLED__OFFSET, 0x0000001f +.set CYFLD_SCB_ENABLED__SIZE, 0x00000001 +.set CYREG_SCB0_STATUS, 0x40060004 +.set CYFLD_SCB_EC_BUSY__OFFSET, 0x00000000 +.set CYFLD_SCB_EC_BUSY__SIZE, 0x00000001 +.set CYREG_SCB0_SPI_CTRL, 0x40060020 +.set CYFLD_SCB_CONTINUOUS__OFFSET, 0x00000000 +.set CYFLD_SCB_CONTINUOUS__SIZE, 0x00000001 +.set CYFLD_SCB_SELECT_PRECEDE__OFFSET, 0x00000001 +.set CYFLD_SCB_SELECT_PRECEDE__SIZE, 0x00000001 +.set CYFLD_SCB_CPHA__OFFSET, 0x00000002 +.set CYFLD_SCB_CPHA__SIZE, 0x00000001 +.set CYFLD_SCB_CPOL__OFFSET, 0x00000003 +.set CYFLD_SCB_CPOL__SIZE, 0x00000001 +.set CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET, 0x00000004 +.set CYFLD_SCB_LATE_MISO_SAMPLE__SIZE, 0x00000001 +.set CYFLD_SCB_LOOPBACK__OFFSET, 0x00000010 +.set CYFLD_SCB_LOOPBACK__SIZE, 0x00000001 +.set CYFLD_SCB_SLAVE_SELECT__OFFSET, 0x0000001a +.set CYFLD_SCB_SLAVE_SELECT__SIZE, 0x00000002 +.set CYFLD_SCB_MASTER_MODE__OFFSET, 0x0000001f +.set CYFLD_SCB_MASTER_MODE__SIZE, 0x00000001 +.set CYREG_SCB0_SPI_STATUS, 0x40060024 +.set CYFLD_SCB_BUS_BUSY__OFFSET, 0x00000000 +.set CYFLD_SCB_BUS_BUSY__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_ADDR__OFFSET, 0x00000008 +.set CYFLD_SCB_EZ_ADDR__SIZE, 0x00000008 +.set CYREG_SCB0_UART_CTRL, 0x40060040 +.set CYREG_SCB0_UART_TX_CTRL, 0x40060044 +.set CYFLD_SCB_STOP_BITS__OFFSET, 0x00000000 +.set CYFLD_SCB_STOP_BITS__SIZE, 0x00000003 +.set CYFLD_SCB_PARITY__OFFSET, 0x00000004 +.set CYFLD_SCB_PARITY__SIZE, 0x00000001 +.set CYFLD_SCB_PARITY_ENABLED__OFFSET, 0x00000005 +.set CYFLD_SCB_PARITY_ENABLED__SIZE, 0x00000001 +.set CYFLD_SCB_RETRY_ON_NACK__OFFSET, 0x00000008 +.set CYFLD_SCB_RETRY_ON_NACK__SIZE, 0x00000001 +.set CYREG_SCB0_UART_RX_CTRL, 0x40060048 +.set CYFLD_SCB_POLARITY__OFFSET, 0x00000006 +.set CYFLD_SCB_POLARITY__SIZE, 0x00000001 +.set CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET, 0x00000009 +.set CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_MP_MODE__OFFSET, 0x0000000a +.set CYFLD_SCB_MP_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_LIN_MODE__OFFSET, 0x0000000c +.set CYFLD_SCB_LIN_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_SKIP_START__OFFSET, 0x0000000d +.set CYFLD_SCB_SKIP_START__SIZE, 0x00000001 +.set CYFLD_SCB_BREAK_WIDTH__OFFSET, 0x00000010 +.set CYFLD_SCB_BREAK_WIDTH__SIZE, 0x00000004 +.set CYREG_SCB0_UART_RX_STATUS, 0x4006004c +.set CYFLD_SCB_BR_COUNTER__OFFSET, 0x00000000 +.set CYFLD_SCB_BR_COUNTER__SIZE, 0x0000000c +.set CYREG_SCB0_I2C_CTRL, 0x40060060 +.set CYFLD_SCB_HIGH_PHASE_OVS__OFFSET, 0x00000000 +.set CYFLD_SCB_HIGH_PHASE_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_LOW_PHASE_OVS__OFFSET, 0x00000004 +.set CYFLD_SCB_LOW_PHASE_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_M_READY_DATA_ACK__OFFSET, 0x00000008 +.set CYFLD_SCB_M_READY_DATA_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET, 0x00000009 +.set CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_GENERAL_IGNORE__OFFSET, 0x0000000b +.set CYFLD_SCB_S_GENERAL_IGNORE__SIZE, 0x00000001 +.set CYFLD_SCB_S_READY_ADDR_ACK__OFFSET, 0x0000000c +.set CYFLD_SCB_S_READY_ADDR_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_READY_DATA_ACK__OFFSET, 0x0000000d +.set CYFLD_SCB_S_READY_DATA_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET, 0x0000000e +.set CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET, 0x0000000f +.set CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_SLAVE_MODE__OFFSET, 0x0000001e +.set CYFLD_SCB_SLAVE_MODE__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_STATUS, 0x40060064 +.set CYFLD_SCB_S_READ__OFFSET, 0x00000004 +.set CYFLD_SCB_S_READ__SIZE, 0x00000001 +.set CYFLD_SCB_M_READ__OFFSET, 0x00000005 +.set CYFLD_SCB_M_READ__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_M_CMD, 0x40060068 +.set CYFLD_SCB_M_START__OFFSET, 0x00000000 +.set CYFLD_SCB_M_START__SIZE, 0x00000001 +.set CYFLD_SCB_M_START_ON_IDLE__OFFSET, 0x00000001 +.set CYFLD_SCB_M_START_ON_IDLE__SIZE, 0x00000001 +.set CYFLD_SCB_M_ACK__OFFSET, 0x00000002 +.set CYFLD_SCB_M_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_NACK__OFFSET, 0x00000003 +.set CYFLD_SCB_M_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_STOP__OFFSET, 0x00000004 +.set CYFLD_SCB_M_STOP__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_S_CMD, 0x4006006c +.set CYFLD_SCB_S_ACK__OFFSET, 0x00000000 +.set CYFLD_SCB_S_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NACK__OFFSET, 0x00000001 +.set CYFLD_SCB_S_NACK__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_CFG, 0x40060070 +.set CYFLD_SCB_SDA_FILT_HYS__OFFSET, 0x00000000 +.set CYFLD_SCB_SDA_FILT_HYS__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_TRIM__OFFSET, 0x00000002 +.set CYFLD_SCB_SDA_FILT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SCL_FILT_HYS__OFFSET, 0x00000004 +.set CYFLD_SCB_SCL_FILT_HYS__SIZE, 0x00000002 +.set CYFLD_SCB_SCL_FILT_TRIM__OFFSET, 0x00000006 +.set CYFLD_SCB_SCL_FILT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET, 0x00000008 +.set CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET, 0x0000000a +.set CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_FILT_HS__OFFSET, 0x00000010 +.set CYFLD_SCB_SDA_FILT_HS__SIZE, 0x00000001 +.set CYFLD_SCB_SDA_FILT_ENABLED__OFFSET, 0x00000011 +.set CYFLD_SCB_SDA_FILT_ENABLED__SIZE, 0x00000001 +.set CYFLD_SCB_SCL_FILT_HS__OFFSET, 0x00000018 +.set CYFLD_SCB_SCL_FILT_HS__SIZE, 0x00000001 +.set CYFLD_SCB_SCL_FILT_ENABLED__OFFSET, 0x00000019 +.set CYFLD_SCB_SCL_FILT_ENABLED__SIZE, 0x00000001 +.set CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET, 0x0000001a +.set CYFLD_SCB_SDA_FILT_OUT_HS__SIZE, 0x00000001 +.set CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET, 0x0000001b +.set CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE, 0x00000001 +.set CYREG_SCB0_BIST_CONTROL, 0x40060100 +.set CYFLD_SCB_RAM_ADDR__OFFSET, 0x00000000 +.set CYFLD_SCB_RAM_ADDR__SIZE, 0x00000005 +.set CYFLD_SCB_RAM_OP1__OFFSET, 0x00000010 +.set CYFLD_SCB_RAM_OP1__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OP2__OFFSET, 0x00000012 +.set CYFLD_SCB_RAM_OP2__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OP3__OFFSET, 0x00000014 +.set CYFLD_SCB_RAM_OP3__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OP4__OFFSET, 0x00000016 +.set CYFLD_SCB_RAM_OP4__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_OPCNT__OFFSET, 0x00000018 +.set CYFLD_SCB_RAM_OPCNT__SIZE, 0x00000002 +.set CYFLD_SCB_RAM_PREADR__OFFSET, 0x0000001a +.set CYFLD_SCB_RAM_PREADR__SIZE, 0x00000001 +.set CYFLD_SCB_RAM_WORD__OFFSET, 0x0000001b +.set CYFLD_SCB_RAM_WORD__SIZE, 0x00000001 +.set CYFLD_SCB_RAM_FAIL__OFFSET, 0x0000001c +.set CYFLD_SCB_RAM_FAIL__SIZE, 0x00000001 +.set CYFLD_SCB_RAM_GO__OFFSET, 0x0000001d +.set CYFLD_SCB_RAM_GO__SIZE, 0x00000001 +.set CYREG_SCB0_BIST_DATA, 0x40060104 +.set CYFLD_SCB_RAM_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_RAM_DATA__SIZE, 0x00000010 +.set CYREG_SCB0_TX_CTRL, 0x40060200 +.set CYFLD_SCB_DATA_WIDTH__OFFSET, 0x00000000 +.set CYFLD_SCB_DATA_WIDTH__SIZE, 0x00000004 +.set CYFLD_SCB_MSB_FIRST__OFFSET, 0x00000008 +.set CYFLD_SCB_MSB_FIRST__SIZE, 0x00000001 +.set CYREG_SCB0_TX_FIFO_CTRL, 0x40060204 +.set CYFLD_SCB_TRIGGER_LEVEL__OFFSET, 0x00000000 +.set CYFLD_SCB_TRIGGER_LEVEL__SIZE, 0x00000003 +.set CYFLD_SCB_CLEAR__OFFSET, 0x00000010 +.set CYFLD_SCB_CLEAR__SIZE, 0x00000001 +.set CYFLD_SCB_FREEZE__OFFSET, 0x00000011 +.set CYFLD_SCB_FREEZE__SIZE, 0x00000001 +.set CYREG_SCB0_TX_FIFO_STATUS, 0x40060208 +.set CYFLD_SCB_USED__OFFSET, 0x00000000 +.set CYFLD_SCB_USED__SIZE, 0x00000004 +.set CYFLD_SCB_SR_VALID__OFFSET, 0x0000000f +.set CYFLD_SCB_SR_VALID__SIZE, 0x00000001 +.set CYFLD_SCB_RD_PTR__OFFSET, 0x00000010 +.set CYFLD_SCB_RD_PTR__SIZE, 0x00000003 +.set CYFLD_SCB_WR_PTR__OFFSET, 0x00000018 +.set CYFLD_SCB_WR_PTR__SIZE, 0x00000003 +.set CYREG_SCB0_TX_FIFO_WR, 0x40060240 +.set CYFLD_SCB_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_DATA__SIZE, 0x00000010 +.set CYREG_SCB0_RX_CTRL, 0x40060300 +.set CYFLD_SCB_MEDIAN__OFFSET, 0x00000009 +.set CYFLD_SCB_MEDIAN__SIZE, 0x00000001 +.set CYREG_SCB0_RX_FIFO_CTRL, 0x40060304 +.set CYREG_SCB0_RX_FIFO_STATUS, 0x40060308 +.set CYREG_SCB0_RX_MATCH, 0x40060310 +.set CYFLD_SCB_ADDR__OFFSET, 0x00000000 +.set CYFLD_SCB_ADDR__SIZE, 0x00000008 +.set CYFLD_SCB_MASK__OFFSET, 0x00000010 +.set CYFLD_SCB_MASK__SIZE, 0x00000008 +.set CYREG_SCB0_RX_FIFO_RD, 0x40060340 +.set CYREG_SCB0_RX_FIFO_RD_SILENT, 0x40060344 +.set CYREG_SCB0_EZ_DATA00, 0x40060400 +.set CYFLD_SCB_EZ_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_EZ_DATA__SIZE, 0x00000008 +.set CYREG_SCB0_EZ_DATA01, 0x40060404 +.set CYREG_SCB0_EZ_DATA02, 0x40060408 +.set CYREG_SCB0_EZ_DATA03, 0x4006040c +.set CYREG_SCB0_EZ_DATA04, 0x40060410 +.set CYREG_SCB0_EZ_DATA05, 0x40060414 +.set CYREG_SCB0_EZ_DATA06, 0x40060418 +.set CYREG_SCB0_EZ_DATA07, 0x4006041c +.set CYREG_SCB0_EZ_DATA08, 0x40060420 +.set CYREG_SCB0_EZ_DATA09, 0x40060424 +.set CYREG_SCB0_EZ_DATA10, 0x40060428 +.set CYREG_SCB0_EZ_DATA11, 0x4006042c +.set CYREG_SCB0_EZ_DATA12, 0x40060430 +.set CYREG_SCB0_EZ_DATA13, 0x40060434 +.set CYREG_SCB0_EZ_DATA14, 0x40060438 +.set CYREG_SCB0_EZ_DATA15, 0x4006043c +.set CYREG_SCB0_EZ_DATA16, 0x40060440 +.set CYREG_SCB0_EZ_DATA17, 0x40060444 +.set CYREG_SCB0_EZ_DATA18, 0x40060448 +.set CYREG_SCB0_EZ_DATA19, 0x4006044c +.set CYREG_SCB0_EZ_DATA20, 0x40060450 +.set CYREG_SCB0_EZ_DATA21, 0x40060454 +.set CYREG_SCB0_EZ_DATA22, 0x40060458 +.set CYREG_SCB0_EZ_DATA23, 0x4006045c +.set CYREG_SCB0_EZ_DATA24, 0x40060460 +.set CYREG_SCB0_EZ_DATA25, 0x40060464 +.set CYREG_SCB0_EZ_DATA26, 0x40060468 +.set CYREG_SCB0_EZ_DATA27, 0x4006046c +.set CYREG_SCB0_EZ_DATA28, 0x40060470 +.set CYREG_SCB0_EZ_DATA29, 0x40060474 +.set CYREG_SCB0_EZ_DATA30, 0x40060478 +.set CYREG_SCB0_EZ_DATA31, 0x4006047c +.set CYREG_SCB0_INTR_CAUSE, 0x40060e00 +.set CYFLD_SCB_M__OFFSET, 0x00000000 +.set CYFLD_SCB_M__SIZE, 0x00000001 +.set CYFLD_SCB_S__OFFSET, 0x00000001 +.set CYFLD_SCB_S__SIZE, 0x00000001 +.set CYFLD_SCB_TX__OFFSET, 0x00000002 +.set CYFLD_SCB_TX__SIZE, 0x00000001 +.set CYFLD_SCB_RX__OFFSET, 0x00000003 +.set CYFLD_SCB_RX__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_EC__OFFSET, 0x00000004 +.set CYFLD_SCB_I2C_EC__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EC__OFFSET, 0x00000005 +.set CYFLD_SCB_SPI_EC__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_I2C_EC, 0x40060e80 +.set CYFLD_SCB_WAKE_UP__OFFSET, 0x00000000 +.set CYFLD_SCB_WAKE_UP__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_STOP__OFFSET, 0x00000001 +.set CYFLD_SCB_EZ_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_WRITE_STOP__OFFSET, 0x00000002 +.set CYFLD_SCB_EZ_WRITE_STOP__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_I2C_EC_MASK, 0x40060e88 +.set CYREG_SCB0_INTR_I2C_EC_MASKED, 0x40060e8c +.set CYREG_SCB0_INTR_SPI_EC, 0x40060ec0 +.set CYREG_SCB0_INTR_SPI_EC_MASK, 0x40060ec8 +.set CYREG_SCB0_INTR_SPI_EC_MASKED, 0x40060ecc +.set CYREG_SCB0_INTR_M, 0x40060f00 +.set CYFLD_SCB_I2C_ARB_LOST__OFFSET, 0x00000000 +.set CYFLD_SCB_I2C_ARB_LOST__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_NACK__OFFSET, 0x00000001 +.set CYFLD_SCB_I2C_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_ACK__OFFSET, 0x00000002 +.set CYFLD_SCB_I2C_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_STOP__OFFSET, 0x00000004 +.set CYFLD_SCB_I2C_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_BUS_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_I2C_BUS_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_DONE__OFFSET, 0x00000009 +.set CYFLD_SCB_SPI_DONE__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_M_SET, 0x40060f04 +.set CYREG_SCB0_INTR_M_MASK, 0x40060f08 +.set CYREG_SCB0_INTR_M_MASKED, 0x40060f0c +.set CYREG_SCB0_INTR_S, 0x40060f40 +.set CYFLD_SCB_I2C_WRITE_STOP__OFFSET, 0x00000003 +.set CYFLD_SCB_I2C_WRITE_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_START__OFFSET, 0x00000005 +.set CYFLD_SCB_I2C_START__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_ADDR_MATCH__OFFSET, 0x00000006 +.set CYFLD_SCB_I2C_ADDR_MATCH__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_GENERAL__OFFSET, 0x00000007 +.set CYFLD_SCB_I2C_GENERAL__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET, 0x00000009 +.set CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EZ_STOP__OFFSET, 0x0000000a +.set CYFLD_SCB_SPI_EZ_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_BUS_ERROR__OFFSET, 0x0000000b +.set CYFLD_SCB_SPI_BUS_ERROR__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_S_SET, 0x40060f44 +.set CYREG_SCB0_INTR_S_MASK, 0x40060f48 +.set CYREG_SCB0_INTR_S_MASKED, 0x40060f4c +.set CYREG_SCB0_INTR_TX, 0x40060f80 +.set CYFLD_SCB_TRIGGER__OFFSET, 0x00000000 +.set CYFLD_SCB_TRIGGER__SIZE, 0x00000001 +.set CYFLD_SCB_NOT_FULL__OFFSET, 0x00000001 +.set CYFLD_SCB_NOT_FULL__SIZE, 0x00000001 +.set CYFLD_SCB_EMPTY__OFFSET, 0x00000004 +.set CYFLD_SCB_EMPTY__SIZE, 0x00000001 +.set CYFLD_SCB_OVERFLOW__OFFSET, 0x00000005 +.set CYFLD_SCB_OVERFLOW__SIZE, 0x00000001 +.set CYFLD_SCB_UNDERFLOW__OFFSET, 0x00000006 +.set CYFLD_SCB_UNDERFLOW__SIZE, 0x00000001 +.set CYFLD_SCB_BLOCKED__OFFSET, 0x00000007 +.set CYFLD_SCB_BLOCKED__SIZE, 0x00000001 +.set CYFLD_SCB_UART_NACK__OFFSET, 0x00000008 +.set CYFLD_SCB_UART_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_UART_DONE__OFFSET, 0x00000009 +.set CYFLD_SCB_UART_DONE__SIZE, 0x00000001 +.set CYFLD_SCB_UART_ARB_LOST__OFFSET, 0x0000000a +.set CYFLD_SCB_UART_ARB_LOST__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_TX_SET, 0x40060f84 +.set CYREG_SCB0_INTR_TX_MASK, 0x40060f88 +.set CYREG_SCB0_INTR_TX_MASKED, 0x40060f8c +.set CYREG_SCB0_INTR_RX, 0x40060fc0 +.set CYFLD_SCB_NOT_EMPTY__OFFSET, 0x00000002 +.set CYFLD_SCB_NOT_EMPTY__SIZE, 0x00000001 +.set CYFLD_SCB_FULL__OFFSET, 0x00000003 +.set CYFLD_SCB_FULL__SIZE, 0x00000001 +.set CYFLD_SCB_FRAME_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_FRAME_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_PARITY_ERROR__OFFSET, 0x00000009 +.set CYFLD_SCB_PARITY_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_BAUD_DETECT__OFFSET, 0x0000000a +.set CYFLD_SCB_BAUD_DETECT__SIZE, 0x00000001 +.set CYFLD_SCB_BREAK_DETECT__OFFSET, 0x0000000b +.set CYFLD_SCB_BREAK_DETECT__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_RX_SET, 0x40060fc4 +.set CYREG_SCB0_INTR_RX_MASK, 0x40060fc8 +.set CYREG_SCB0_INTR_RX_MASKED, 0x40060fcc +.set CYDEV_SCB1_BASE, 0x40070000 +.set CYDEV_SCB1_SIZE, 0x00010000 +.set CYREG_SCB1_CTRL, 0x40070000 +.set CYREG_SCB1_STATUS, 0x40070004 +.set CYREG_SCB1_SPI_CTRL, 0x40070020 +.set CYREG_SCB1_SPI_STATUS, 0x40070024 +.set CYREG_SCB1_UART_CTRL, 0x40070040 +.set CYREG_SCB1_UART_TX_CTRL, 0x40070044 +.set CYREG_SCB1_UART_RX_CTRL, 0x40070048 +.set CYREG_SCB1_UART_RX_STATUS, 0x4007004c +.set CYREG_SCB1_I2C_CTRL, 0x40070060 +.set CYREG_SCB1_I2C_STATUS, 0x40070064 +.set CYREG_SCB1_I2C_M_CMD, 0x40070068 +.set CYREG_SCB1_I2C_S_CMD, 0x4007006c +.set CYREG_SCB1_I2C_CFG, 0x40070070 +.set CYREG_SCB1_BIST_CONTROL, 0x40070100 +.set CYREG_SCB1_BIST_DATA, 0x40070104 +.set CYREG_SCB1_TX_CTRL, 0x40070200 +.set CYREG_SCB1_TX_FIFO_CTRL, 0x40070204 +.set CYREG_SCB1_TX_FIFO_STATUS, 0x40070208 +.set CYREG_SCB1_TX_FIFO_WR, 0x40070240 +.set CYREG_SCB1_RX_CTRL, 0x40070300 +.set CYREG_SCB1_RX_FIFO_CTRL, 0x40070304 +.set CYREG_SCB1_RX_FIFO_STATUS, 0x40070308 +.set CYREG_SCB1_RX_MATCH, 0x40070310 +.set CYREG_SCB1_RX_FIFO_RD, 0x40070340 +.set CYREG_SCB1_RX_FIFO_RD_SILENT, 0x40070344 +.set CYREG_SCB1_EZ_DATA00, 0x40070400 +.set CYREG_SCB1_EZ_DATA01, 0x40070404 +.set CYREG_SCB1_EZ_DATA02, 0x40070408 +.set CYREG_SCB1_EZ_DATA03, 0x4007040c +.set CYREG_SCB1_EZ_DATA04, 0x40070410 +.set CYREG_SCB1_EZ_DATA05, 0x40070414 +.set CYREG_SCB1_EZ_DATA06, 0x40070418 +.set CYREG_SCB1_EZ_DATA07, 0x4007041c +.set CYREG_SCB1_EZ_DATA08, 0x40070420 +.set CYREG_SCB1_EZ_DATA09, 0x40070424 +.set CYREG_SCB1_EZ_DATA10, 0x40070428 +.set CYREG_SCB1_EZ_DATA11, 0x4007042c +.set CYREG_SCB1_EZ_DATA12, 0x40070430 +.set CYREG_SCB1_EZ_DATA13, 0x40070434 +.set CYREG_SCB1_EZ_DATA14, 0x40070438 +.set CYREG_SCB1_EZ_DATA15, 0x4007043c +.set CYREG_SCB1_EZ_DATA16, 0x40070440 +.set CYREG_SCB1_EZ_DATA17, 0x40070444 +.set CYREG_SCB1_EZ_DATA18, 0x40070448 +.set CYREG_SCB1_EZ_DATA19, 0x4007044c +.set CYREG_SCB1_EZ_DATA20, 0x40070450 +.set CYREG_SCB1_EZ_DATA21, 0x40070454 +.set CYREG_SCB1_EZ_DATA22, 0x40070458 +.set CYREG_SCB1_EZ_DATA23, 0x4007045c +.set CYREG_SCB1_EZ_DATA24, 0x40070460 +.set CYREG_SCB1_EZ_DATA25, 0x40070464 +.set CYREG_SCB1_EZ_DATA26, 0x40070468 +.set CYREG_SCB1_EZ_DATA27, 0x4007046c +.set CYREG_SCB1_EZ_DATA28, 0x40070470 +.set CYREG_SCB1_EZ_DATA29, 0x40070474 +.set CYREG_SCB1_EZ_DATA30, 0x40070478 +.set CYREG_SCB1_EZ_DATA31, 0x4007047c +.set CYREG_SCB1_INTR_CAUSE, 0x40070e00 +.set CYREG_SCB1_INTR_I2C_EC, 0x40070e80 +.set CYREG_SCB1_INTR_I2C_EC_MASK, 0x40070e88 +.set CYREG_SCB1_INTR_I2C_EC_MASKED, 0x40070e8c +.set CYREG_SCB1_INTR_SPI_EC, 0x40070ec0 +.set CYREG_SCB1_INTR_SPI_EC_MASK, 0x40070ec8 +.set CYREG_SCB1_INTR_SPI_EC_MASKED, 0x40070ecc +.set CYREG_SCB1_INTR_M, 0x40070f00 +.set CYREG_SCB1_INTR_M_SET, 0x40070f04 +.set CYREG_SCB1_INTR_M_MASK, 0x40070f08 +.set CYREG_SCB1_INTR_M_MASKED, 0x40070f0c +.set CYREG_SCB1_INTR_S, 0x40070f40 +.set CYREG_SCB1_INTR_S_SET, 0x40070f44 +.set CYREG_SCB1_INTR_S_MASK, 0x40070f48 +.set CYREG_SCB1_INTR_S_MASKED, 0x40070f4c +.set CYREG_SCB1_INTR_TX, 0x40070f80 +.set CYREG_SCB1_INTR_TX_SET, 0x40070f84 +.set CYREG_SCB1_INTR_TX_MASK, 0x40070f88 +.set CYREG_SCB1_INTR_TX_MASKED, 0x40070f8c +.set CYREG_SCB1_INTR_RX, 0x40070fc0 +.set CYREG_SCB1_INTR_RX_SET, 0x40070fc4 +.set CYREG_SCB1_INTR_RX_MASK, 0x40070fc8 +.set CYREG_SCB1_INTR_RX_MASKED, 0x40070fcc +.set CYDEV_CSD_BASE, 0x40080000 +.set CYDEV_CSD_SIZE, 0x00010000 +.set CYREG_CSD_ID, 0x40080000 +.set CYFLD_CSD_ID__OFFSET, 0x00000000 +.set CYFLD_CSD_ID__SIZE, 0x00000010 +.set CYFLD_CSD_REVISION__OFFSET, 0x00000010 +.set CYFLD_CSD_REVISION__SIZE, 0x00000010 +.set CYREG_CSD_CONFIG, 0x40080004 +.set CYFLD_CSD_DSI_SAMPLE_EN__OFFSET, 0x00000000 +.set CYFLD_CSD_DSI_SAMPLE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_SAMPLE_SYNC__OFFSET, 0x00000001 +.set CYFLD_CSD_SAMPLE_SYNC__SIZE, 0x00000001 +.set CYFLD_CSD_PRS_CLEAR__OFFSET, 0x00000005 +.set CYFLD_CSD_PRS_CLEAR__SIZE, 0x00000001 +.set CYFLD_CSD_PRS_SELECT__OFFSET, 0x00000006 +.set CYFLD_CSD_PRS_SELECT__SIZE, 0x00000001 +.set CYVAL_CSD_PRS_SELECT_DIV2, 0x00000000 +.set CYVAL_CSD_PRS_SELECT_PRS, 0x00000001 +.set CYFLD_CSD_PRS_12_8__OFFSET, 0x00000007 +.set CYFLD_CSD_PRS_12_8__SIZE, 0x00000001 +.set CYVAL_CSD_PRS_12_8_8B, 0x00000000 +.set CYVAL_CSD_PRS_12_8_12B, 0x00000001 +.set CYFLD_CSD_DSI_SENSE_EN__OFFSET, 0x00000008 +.set CYFLD_CSD_DSI_SENSE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_SHIELD_DELAY__OFFSET, 0x00000009 +.set CYFLD_CSD_SHIELD_DELAY__SIZE, 0x00000002 +.set CYFLD_CSD_SENSE_COMP_BW__OFFSET, 0x0000000b +.set CYFLD_CSD_SENSE_COMP_BW__SIZE, 0x00000001 +.set CYVAL_CSD_SENSE_COMP_BW_LOW, 0x00000000 +.set CYVAL_CSD_SENSE_COMP_BW_HIGH, 0x00000001 +.set CYFLD_CSD_SENSE_EN__OFFSET, 0x0000000c +.set CYFLD_CSD_SENSE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_REFBUF_EN__OFFSET, 0x0000000d +.set CYFLD_CSD_REFBUF_EN__SIZE, 0x00000001 +.set CYFLD_CSD_COMP_MODE__OFFSET, 0x0000000e +.set CYFLD_CSD_COMP_MODE__SIZE, 0x00000001 +.set CYVAL_CSD_COMP_MODE_CHARGE_BUF, 0x00000000 +.set CYVAL_CSD_COMP_MODE_CHARGE_IO, 0x00000001 +.set CYFLD_CSD_COMP_PIN__OFFSET, 0x0000000f +.set CYFLD_CSD_COMP_PIN__SIZE, 0x00000001 +.set CYVAL_CSD_COMP_PIN_CHANNEL1, 0x00000000 +.set CYVAL_CSD_COMP_PIN_CHANNEL2, 0x00000001 +.set CYFLD_CSD_POLARITY__OFFSET, 0x00000010 +.set CYFLD_CSD_POLARITY__SIZE, 0x00000001 +.set CYVAL_CSD_POLARITY_VSSIO, 0x00000000 +.set CYVAL_CSD_POLARITY_VDDIO, 0x00000001 +.set CYFLD_CSD_POLARITY2__OFFSET, 0x00000011 +.set CYFLD_CSD_POLARITY2__SIZE, 0x00000001 +.set CYVAL_CSD_POLARITY2_VSSIO, 0x00000000 +.set CYVAL_CSD_POLARITY2_VDDIO, 0x00000001 +.set CYFLD_CSD_MUTUAL_CAP__OFFSET, 0x00000012 +.set CYFLD_CSD_MUTUAL_CAP__SIZE, 0x00000001 +.set CYVAL_CSD_MUTUAL_CAP_SELFCAP, 0x00000000 +.set CYVAL_CSD_MUTUAL_CAP_MUTUALCAP, 0x00000001 +.set CYFLD_CSD_SENSE_COMP_EN__OFFSET, 0x00000013 +.set CYFLD_CSD_SENSE_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CSD_REBUF_OUTSEL__OFFSET, 0x00000015 +.set CYFLD_CSD_REBUF_OUTSEL__SIZE, 0x00000001 +.set CYVAL_CSD_REBUF_OUTSEL_AMUXA, 0x00000000 +.set CYVAL_CSD_REBUF_OUTSEL_AMUXB, 0x00000001 +.set CYFLD_CSD_SENSE_INSEL__OFFSET, 0x00000016 +.set CYFLD_CSD_SENSE_INSEL__SIZE, 0x00000001 +.set CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1, 0x00000000 +.set CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA, 0x00000001 +.set CYFLD_CSD_REFBUF_DRV__OFFSET, 0x00000017 +.set CYFLD_CSD_REFBUF_DRV__SIZE, 0x00000002 +.set CYVAL_CSD_REFBUF_DRV_OFF, 0x00000000 +.set CYVAL_CSD_REFBUF_DRV_DRV_1, 0x00000001 +.set CYVAL_CSD_REFBUF_DRV_DRV_2, 0x00000002 +.set CYVAL_CSD_REFBUF_DRV_DRV_3, 0x00000003 +.set CYFLD_CSD_DDFTSEL__OFFSET, 0x0000001a +.set CYFLD_CSD_DDFTSEL__SIZE, 0x00000003 +.set CYVAL_CSD_DDFTSEL_NORMAL, 0x00000000 +.set CYVAL_CSD_DDFTSEL_CSD_SENSE, 0x00000001 +.set CYVAL_CSD_DDFTSEL_CSD_SHIELD, 0x00000002 +.set CYVAL_CSD_DDFTSEL_CLK_SAMPLE, 0x00000003 +.set CYVAL_CSD_DDFTSEL_COMP_OUT, 0x00000004 +.set CYFLD_CSD_ADFTEN__OFFSET, 0x0000001d +.set CYFLD_CSD_ADFTEN__SIZE, 0x00000001 +.set CYFLD_CSD_DDFTCOMP__OFFSET, 0x0000001e +.set CYFLD_CSD_DDFTCOMP__SIZE, 0x00000001 +.set CYVAL_CSD_DDFTCOMP_REFBUFCOMP, 0x00000000 +.set CYVAL_CSD_DDFTCOMP_SENSECOMP, 0x00000001 +.set CYFLD_CSD_ENABLE__OFFSET, 0x0000001f +.set CYFLD_CSD_ENABLE__SIZE, 0x00000001 +.set CYREG_CSD_IDAC, 0x40080008 +.set CYFLD_CSD_IDAC1__OFFSET, 0x00000000 +.set CYFLD_CSD_IDAC1__SIZE, 0x00000008 +.set CYFLD_CSD_IDAC1_MODE__OFFSET, 0x00000008 +.set CYFLD_CSD_IDAC1_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_IDAC1_MODE_OFF, 0x00000000 +.set CYVAL_CSD_IDAC1_MODE_FIXED, 0x00000001 +.set CYVAL_CSD_IDAC1_MODE_VARIABLE, 0x00000002 +.set CYVAL_CSD_IDAC1_MODE_DSI, 0x00000003 +.set CYFLD_CSD_IDAC1_RANGE__OFFSET, 0x0000000a +.set CYFLD_CSD_IDAC1_RANGE__SIZE, 0x00000001 +.set CYVAL_CSD_IDAC1_RANGE_4X, 0x00000000 +.set CYVAL_CSD_IDAC1_RANGE_8X, 0x00000001 +.set CYFLD_CSD_IDAC2__OFFSET, 0x00000010 +.set CYFLD_CSD_IDAC2__SIZE, 0x00000007 +.set CYFLD_CSD_IDAC2_MODE__OFFSET, 0x00000018 +.set CYFLD_CSD_IDAC2_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_IDAC2_MODE_OFF, 0x00000000 +.set CYVAL_CSD_IDAC2_MODE_FIXED, 0x00000001 +.set CYVAL_CSD_IDAC2_MODE_VARIABLE, 0x00000002 +.set CYVAL_CSD_IDAC2_MODE_DSI, 0x00000003 +.set CYFLD_CSD_IDAC2_RANGE__OFFSET, 0x0000001a +.set CYFLD_CSD_IDAC2_RANGE__SIZE, 0x00000001 +.set CYVAL_CSD_IDAC2_RANGE_4X, 0x00000000 +.set CYVAL_CSD_IDAC2_RANGE_8X, 0x00000001 +.set CYFLD_CSD_FEEDBACK_MODE__OFFSET, 0x0000001e +.set CYFLD_CSD_FEEDBACK_MODE__SIZE, 0x00000001 +.set CYVAL_CSD_FEEDBACK_MODE_FLOP, 0x00000000 +.set CYVAL_CSD_FEEDBACK_MODE_COMP, 0x00000001 +.set CYREG_CSD_COUNTER, 0x4008000c +.set CYFLD_CSD_COUNTER__OFFSET, 0x00000000 +.set CYFLD_CSD_COUNTER__SIZE, 0x00000010 +.set CYFLD_CSD_PERIOD__OFFSET, 0x00000010 +.set CYFLD_CSD_PERIOD__SIZE, 0x00000010 +.set CYREG_CSD_STATUS, 0x40080010 +.set CYFLD_CSD_CSD_CHARGE__OFFSET, 0x00000000 +.set CYFLD_CSD_CSD_CHARGE__SIZE, 0x00000001 +.set CYFLD_CSD_CSD_SENSE__OFFSET, 0x00000001 +.set CYFLD_CSD_CSD_SENSE__SIZE, 0x00000001 +.set CYFLD_CSD_COMP_OUT__OFFSET, 0x00000002 +.set CYFLD_CSD_COMP_OUT__SIZE, 0x00000001 +.set CYVAL_CSD_COMP_OUT_C_LT_VREF, 0x00000000 +.set CYVAL_CSD_COMP_OUT_C_GT_VREF, 0x00000001 +.set CYFLD_CSD_SAMPLE__OFFSET, 0x00000003 +.set CYFLD_CSD_SAMPLE__SIZE, 0x00000001 +.set CYREG_CSD_INTR, 0x40080014 +.set CYFLD_CSD_CSD__OFFSET, 0x00000000 +.set CYFLD_CSD_CSD__SIZE, 0x00000001 +.set CYREG_CSD_INTR_SET, 0x40080018 +.set CYREG_CSD_TRIM1, 0x4008ff00 +.set CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET, 0x00000000 +.set CYFLD_CSD_IDAC1_SRC_TRIM__SIZE, 0x00000004 +.set CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET, 0x00000004 +.set CYFLD_CSD_IDAC2_SRC_TRIM__SIZE, 0x00000004 +.set CYREG_CSD_TRIM2, 0x4008ff04 +.set CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET, 0x00000000 +.set CYFLD_CSD_IDAC1_SNK_TRIM__SIZE, 0x00000004 +.set CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET, 0x00000004 +.set CYFLD_CSD_IDAC2_SNK_TRIM__SIZE, 0x00000004 +.set CYDEV_LCD_BASE, 0x40090000 +.set CYDEV_LCD_SIZE, 0x00010000 +.set CYREG_LCD_ID, 0x40090000 +.set CYFLD_LCD_ID__OFFSET, 0x00000000 +.set CYFLD_LCD_ID__SIZE, 0x00000010 +.set CYFLD_LCD_REVISION__OFFSET, 0x00000010 +.set CYFLD_LCD_REVISION__SIZE, 0x00000010 +.set CYREG_LCD_DIVIDER, 0x40090004 +.set CYFLD_LCD_SUBFR_DIV__OFFSET, 0x00000000 +.set CYFLD_LCD_SUBFR_DIV__SIZE, 0x00000010 +.set CYFLD_LCD_DEAD_DIV__OFFSET, 0x00000010 +.set CYFLD_LCD_DEAD_DIV__SIZE, 0x00000010 +.set CYREG_LCD_CONTROL, 0x40090008 +.set CYFLD_LCD_LS_EN__OFFSET, 0x00000000 +.set CYFLD_LCD_LS_EN__SIZE, 0x00000001 +.set CYFLD_LCD_HS_EN__OFFSET, 0x00000001 +.set CYFLD_LCD_HS_EN__SIZE, 0x00000001 +.set CYFLD_LCD_LCD_MODE__OFFSET, 0x00000002 +.set CYFLD_LCD_LCD_MODE__SIZE, 0x00000001 +.set CYVAL_LCD_LCD_MODE_LS, 0x00000000 +.set CYVAL_LCD_LCD_MODE_HS, 0x00000001 +.set CYFLD_LCD_TYPE__OFFSET, 0x00000003 +.set CYFLD_LCD_TYPE__SIZE, 0x00000001 +.set CYVAL_LCD_TYPE_A, 0x00000000 +.set CYVAL_LCD_TYPE_B, 0x00000001 +.set CYFLD_LCD_OP_MODE__OFFSET, 0x00000004 +.set CYFLD_LCD_OP_MODE__SIZE, 0x00000001 +.set CYVAL_LCD_OP_MODE_PWM, 0x00000000 +.set CYVAL_LCD_OP_MODE_CORRELATION, 0x00000001 +.set CYFLD_LCD_BIAS__OFFSET, 0x00000005 +.set CYFLD_LCD_BIAS__SIZE, 0x00000002 +.set CYVAL_LCD_BIAS_HALF, 0x00000000 +.set CYVAL_LCD_BIAS_THIRD, 0x00000001 +.set CYVAL_LCD_BIAS_FOURTH, 0x00000002 +.set CYVAL_LCD_BIAS_FIFTH, 0x00000003 +.set CYFLD_LCD_COM_NUM__OFFSET, 0x00000008 +.set CYFLD_LCD_COM_NUM__SIZE, 0x00000004 +.set CYFLD_LCD_LS_EN_STAT__OFFSET, 0x0000001f +.set CYFLD_LCD_LS_EN_STAT__SIZE, 0x00000001 +.set CYREG_LCD_DATA00, 0x40090100 +.set CYFLD_LCD_DATA__OFFSET, 0x00000000 +.set CYFLD_LCD_DATA__SIZE, 0x00000020 +.set CYREG_LCD_DATA01, 0x40090104 +.set CYREG_LCD_DATA02, 0x40090108 +.set CYREG_LCD_DATA03, 0x4009010c +.set CYREG_LCD_DATA04, 0x40090110 +.set CYDEV_LPCOMP_BASE, 0x400a0000 +.set CYDEV_LPCOMP_SIZE, 0x00010000 +.set CYREG_LPCOMP_ID, 0x400a0000 +.set CYFLD_LPCOMP_ID__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_ID__SIZE, 0x00000010 +.set CYFLD_LPCOMP_REVISION__OFFSET, 0x00000010 +.set CYFLD_LPCOMP_REVISION__SIZE, 0x00000010 +.set CYREG_LPCOMP_CONFIG, 0x400a0004 +.set CYFLD_LPCOMP_MODE1__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_MODE1__SIZE, 0x00000002 +.set CYVAL_LPCOMP_MODE1_SLOW, 0x00000000 +.set CYVAL_LPCOMP_MODE1_FAST, 0x00000001 +.set CYVAL_LPCOMP_MODE1_ULP, 0x00000002 +.set CYFLD_LPCOMP_HYST1__OFFSET, 0x00000002 +.set CYFLD_LPCOMP_HYST1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_FILTER1__OFFSET, 0x00000003 +.set CYFLD_LPCOMP_FILTER1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_INTTYPE1__OFFSET, 0x00000004 +.set CYFLD_LPCOMP_INTTYPE1__SIZE, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE1_DISABLE, 0x00000000 +.set CYVAL_LPCOMP_INTTYPE1_RISING, 0x00000001 +.set CYVAL_LPCOMP_INTTYPE1_FALLING, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE1_BOTH, 0x00000003 +.set CYFLD_LPCOMP_OUT1__OFFSET, 0x00000006 +.set CYFLD_LPCOMP_OUT1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_ENABLE1__OFFSET, 0x00000007 +.set CYFLD_LPCOMP_ENABLE1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_MODE2__OFFSET, 0x00000008 +.set CYFLD_LPCOMP_MODE2__SIZE, 0x00000002 +.set CYVAL_LPCOMP_MODE2_SLOW, 0x00000000 +.set CYVAL_LPCOMP_MODE2_FAST, 0x00000001 +.set CYVAL_LPCOMP_MODE2_ULP, 0x00000002 +.set CYFLD_LPCOMP_HYST2__OFFSET, 0x0000000a +.set CYFLD_LPCOMP_HYST2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_FILTER2__OFFSET, 0x0000000b +.set CYFLD_LPCOMP_FILTER2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_INTTYPE2__OFFSET, 0x0000000c +.set CYFLD_LPCOMP_INTTYPE2__SIZE, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE2_DISABLE, 0x00000000 +.set CYVAL_LPCOMP_INTTYPE2_RISING, 0x00000001 +.set CYVAL_LPCOMP_INTTYPE2_FALLING, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE2_BOTH, 0x00000003 +.set CYFLD_LPCOMP_OUT2__OFFSET, 0x0000000e +.set CYFLD_LPCOMP_OUT2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_ENABLE2__OFFSET, 0x0000000f +.set CYFLD_LPCOMP_ENABLE2__SIZE, 0x00000001 +.set CYREG_LPCOMP_DFT, 0x400a0008 +.set CYFLD_LPCOMP_CAL_EN__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_CAL_EN__SIZE, 0x00000001 +.set CYFLD_LPCOMP_BYPASS__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_BYPASS__SIZE, 0x00000001 +.set CYREG_LPCOMP_INTR, 0x400a000c +.set CYFLD_LPCOMP_COMP1__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_COMP2__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_COMP2__SIZE, 0x00000001 +.set CYREG_LPCOMP_INTR_SET, 0x400a0010 +.set CYREG_LPCOMP_TRIM1, 0x400aff00 +.set CYFLD_LPCOMP_COMP1_TRIMA__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_TRIMA__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM2, 0x400aff04 +.set CYFLD_LPCOMP_COMP1_TRIMB__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_TRIMB__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM3, 0x400aff08 +.set CYFLD_LPCOMP_COMP2_TRIMA__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP2_TRIMA__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM4, 0x400aff0c +.set CYFLD_LPCOMP_COMP2_TRIMB__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP2_TRIMB__SIZE, 0x00000005 +.set CYREG_PWR_CONTROL, 0x400b0000 +.set CYFLD__POWER_MODE__OFFSET, 0x00000000 +.set CYFLD__POWER_MODE__SIZE, 0x00000004 +.set CYVAL__POWER_MODE_RESET, 0x00000000 +.set CYVAL__POWER_MODE_ACTIVE, 0x00000001 +.set CYVAL__POWER_MODE_SLEEP, 0x00000002 +.set CYVAL__POWER_MODE_DEEP_SLEEP, 0x00000003 +.set CYVAL__POWER_MODE_HIBERNATE, 0x00000004 +.set CYFLD__DEBUG_SESSION__OFFSET, 0x00000004 +.set CYFLD__DEBUG_SESSION__SIZE, 0x00000001 +.set CYVAL__DEBUG_SESSION_NO_SESSION, 0x00000000 +.set CYVAL__DEBUG_SESSION_SESSION_ACTIVE, 0x00000001 +.set CYFLD__LPM_READY__OFFSET, 0x00000005 +.set CYFLD__LPM_READY__SIZE, 0x00000001 +.set CYFLD__EXT_VCCD__OFFSET, 0x00000017 +.set CYFLD__EXT_VCCD__SIZE, 0x00000001 +.set CYFLD__HVMON_ENABLE__OFFSET, 0x00000018 +.set CYFLD__HVMON_ENABLE__SIZE, 0x00000001 +.set CYFLD__HVMON_RELOAD__OFFSET, 0x00000019 +.set CYFLD__HVMON_RELOAD__SIZE, 0x00000001 +.set CYFLD__FIMO_DISABLE__OFFSET, 0x0000001b +.set CYFLD__FIMO_DISABLE__SIZE, 0x00000001 +.set CYFLD__HIBERNATE_DISABLE__OFFSET, 0x0000001c +.set CYFLD__HIBERNATE_DISABLE__SIZE, 0x00000001 +.set CYFLD__LFCLK_SHORT__OFFSET, 0x0000001d +.set CYFLD__LFCLK_SHORT__SIZE, 0x00000001 +.set CYFLD__HIBERNATE__OFFSET, 0x0000001f +.set CYFLD__HIBERNATE__SIZE, 0x00000001 +.set CYVAL__HIBERNATE_DEEP_SLEEP, 0x00000000 +.set CYVAL__HIBERNATE_HIBERNATE, 0x00000001 +.set CYREG_PWR_INTR, 0x400b0004 +.set CYFLD__LVD__OFFSET, 0x00000001 +.set CYFLD__LVD__SIZE, 0x00000001 +.set CYREG_PWR_INTR_MASK, 0x400b0008 +.set CYREG_PWR_KEY_DELAY, 0x400b000c +.set CYFLD__WAKEUP_HOLDOFF__OFFSET, 0x00000000 +.set CYFLD__WAKEUP_HOLDOFF__SIZE, 0x0000000a +.set CYREG_PWR_PWRSYS_CONFIG, 0x400b0010 +.set CYFLD__HIB_TEST_EN__OFFSET, 0x00000008 +.set CYFLD__HIB_TEST_EN__SIZE, 0x00000001 +.set CYFLD__HIB_TEST_REP__OFFSET, 0x00000009 +.set CYFLD__HIB_TEST_REP__SIZE, 0x00000001 +.set CYREG_PWR_BG_CONFIG, 0x400b0014 +.set CYFLD__BG_DFT_EN__OFFSET, 0x00000000 +.set CYFLD__BG_DFT_EN__SIZE, 0x00000001 +.set CYFLD__BG_DFT_VREF_SEL__OFFSET, 0x00000001 +.set CYFLD__BG_DFT_VREF_SEL__SIZE, 0x00000004 +.set CYFLD__BG_DFT_CORE_SEL__OFFSET, 0x00000005 +.set CYFLD__BG_DFT_CORE_SEL__SIZE, 0x00000001 +.set CYFLD__BG_DFT_ICORE_SEL__OFFSET, 0x00000006 +.set CYFLD__BG_DFT_ICORE_SEL__SIZE, 0x00000002 +.set CYFLD__BG_DFT_VCORE_SEL__OFFSET, 0x00000008 +.set CYFLD__BG_DFT_VCORE_SEL__SIZE, 0x00000001 +.set CYFLD__VREF_EN__OFFSET, 0x00000010 +.set CYFLD__VREF_EN__SIZE, 0x00000003 +.set CYREG_PWR_VMON_CONFIG, 0x400b0018 +.set CYFLD__LVD_EN__OFFSET, 0x00000000 +.set CYFLD__LVD_EN__SIZE, 0x00000001 +.set CYFLD__LVD_SEL__OFFSET, 0x00000001 +.set CYFLD__LVD_SEL__SIZE, 0x00000004 +.set CYFLD__VMON_DDFT_SEL__OFFSET, 0x00000005 +.set CYFLD__VMON_DDFT_SEL__SIZE, 0x00000003 +.set CYFLD__VMON_ADFT_SEL__OFFSET, 0x00000008 +.set CYFLD__VMON_ADFT_SEL__SIZE, 0x00000002 +.set CYREG_PWR_DFT_SELECT, 0x400b001c +.set CYFLD__TVMON1_SEL__OFFSET, 0x00000000 +.set CYFLD__TVMON1_SEL__SIZE, 0x00000003 +.set CYFLD__TVMON2_SEL__OFFSET, 0x00000003 +.set CYFLD__TVMON2_SEL__SIZE, 0x00000003 +.set CYFLD__BYPASS__OFFSET, 0x00000006 +.set CYFLD__BYPASS__SIZE, 0x00000001 +.set CYFLD__ACTIVE_EN__OFFSET, 0x00000007 +.set CYFLD__ACTIVE_EN__SIZE, 0x00000001 +.set CYFLD__ACTIVE_INRUSH_DIS__OFFSET, 0x00000008 +.set CYFLD__ACTIVE_INRUSH_DIS__SIZE, 0x00000001 +.set CYFLD__LPCOMP_DIS__OFFSET, 0x00000009 +.set CYFLD__LPCOMP_DIS__SIZE, 0x00000001 +.set CYFLD__BLEED_EN__OFFSET, 0x0000000a +.set CYFLD__BLEED_EN__SIZE, 0x00000001 +.set CYFLD__IPOR_EN__OFFSET, 0x0000000b +.set CYFLD__IPOR_EN__SIZE, 0x00000001 +.set CYFLD__POWER_UP_RAW_BYP__OFFSET, 0x0000000c +.set CYFLD__POWER_UP_RAW_BYP__SIZE, 0x00000001 +.set CYFLD__POWER_UP_RAW_CTL__OFFSET, 0x0000000d +.set CYFLD__POWER_UP_RAW_CTL__SIZE, 0x00000001 +.set CYFLD__DEEPSLEEP_EN__OFFSET, 0x0000000e +.set CYFLD__DEEPSLEEP_EN__SIZE, 0x00000001 +.set CYFLD__RSVD_BYPASS__OFFSET, 0x0000000f +.set CYFLD__RSVD_BYPASS__SIZE, 0x00000001 +.set CYFLD__NWELL_OPEN__OFFSET, 0x00000010 +.set CYFLD__NWELL_OPEN__SIZE, 0x00000001 +.set CYFLD__HIBERNATE_OPEN__OFFSET, 0x00000011 +.set CYFLD__HIBERNATE_OPEN__SIZE, 0x00000001 +.set CYFLD__DEEPSLEEP_OPEN__OFFSET, 0x00000012 +.set CYFLD__DEEPSLEEP_OPEN__SIZE, 0x00000001 +.set CYFLD__QUIET_OPEN__OFFSET, 0x00000013 +.set CYFLD__QUIET_OPEN__SIZE, 0x00000001 +.set CYFLD__LFCLK_OPEN__OFFSET, 0x00000014 +.set CYFLD__LFCLK_OPEN__SIZE, 0x00000001 +.set CYFLD__QUIET_EN__OFFSET, 0x00000016 +.set CYFLD__QUIET_EN__SIZE, 0x00000001 +.set CYFLD__BREF_EN__OFFSET, 0x00000017 +.set CYFLD__BREF_EN__SIZE, 0x00000001 +.set CYFLD__BREF_OUTEN__OFFSET, 0x00000018 +.set CYFLD__BREF_OUTEN__SIZE, 0x00000001 +.set CYFLD__BREF_REFSW__OFFSET, 0x00000019 +.set CYFLD__BREF_REFSW__SIZE, 0x00000001 +.set CYFLD__BREF_TESTMODE__OFFSET, 0x0000001a +.set CYFLD__BREF_TESTMODE__SIZE, 0x00000001 +.set CYFLD__NWELL_DIS__OFFSET, 0x0000001b +.set CYFLD__NWELL_DIS__SIZE, 0x00000001 +.set CYFLD__HVMON_DFT_OVR__OFFSET, 0x0000001c +.set CYFLD__HVMON_DFT_OVR__SIZE, 0x00000001 +.set CYFLD__IMO_REFGEN_DIS__OFFSET, 0x0000001d +.set CYFLD__IMO_REFGEN_DIS__SIZE, 0x00000001 +.set CYFLD__POWER_UP_ACTIVE__OFFSET, 0x0000001e +.set CYFLD__POWER_UP_ACTIVE__SIZE, 0x00000001 +.set CYFLD__POWER_UP_HIBDPSLP__OFFSET, 0x0000001f +.set CYFLD__POWER_UP_HIBDPSLP__SIZE, 0x00000001 +.set CYREG_PWR_DDFT_SELECT, 0x400b0020 +.set CYFLD__DDFT1_SEL__OFFSET, 0x00000000 +.set CYFLD__DDFT1_SEL__SIZE, 0x00000004 +.set CYFLD__DDFT2_SEL__OFFSET, 0x00000004 +.set CYFLD__DDFT2_SEL__SIZE, 0x00000004 +.set CYREG_PWR_DFT_KEY, 0x400b0024 +.set CYFLD__KEY16__OFFSET, 0x00000000 +.set CYFLD__KEY16__SIZE, 0x00000010 +.set CYFLD__HBOD_OFF_AWAKE__OFFSET, 0x00000010 +.set CYFLD__HBOD_OFF_AWAKE__SIZE, 0x00000001 +.set CYFLD__BODS_OFF__OFFSET, 0x00000011 +.set CYFLD__BODS_OFF__SIZE, 0x00000001 +.set CYFLD__DFT_MODE__OFFSET, 0x00000012 +.set CYFLD__DFT_MODE__SIZE, 0x00000001 +.set CYFLD__IO_DISABLE_BYPASS__OFFSET, 0x00000013 +.set CYFLD__IO_DISABLE_BYPASS__SIZE, 0x00000001 +.set CYFLD__VMON_PD__OFFSET, 0x00000014 +.set CYFLD__VMON_PD__SIZE, 0x00000001 +.set CYREG_PWR_BOD_KEY, 0x400b0028 +.set CYREG_PWR_STOP, 0x400b002c +.set CYFLD__TOKEN__OFFSET, 0x00000000 +.set CYFLD__TOKEN__SIZE, 0x00000008 +.set CYFLD__UNLOCK__OFFSET, 0x00000008 +.set CYFLD__UNLOCK__SIZE, 0x00000008 +.set CYFLD__POLARITY__OFFSET, 0x00000010 +.set CYFLD__POLARITY__SIZE, 0x00000001 +.set CYFLD__FREEZE__OFFSET, 0x00000011 +.set CYFLD__FREEZE__SIZE, 0x00000001 +.set CYFLD__STOP__OFFSET, 0x0000001f +.set CYFLD__STOP__SIZE, 0x00000001 +.set CYREG_CLK_SELECT, 0x400b0100 +.set CYFLD__DIRECT_SEL__OFFSET, 0x00000000 +.set CYFLD__DIRECT_SEL__SIZE, 0x00000003 +.set CYVAL__DIRECT_SEL_IMO, 0x00000000 +.set CYVAL__DIRECT_SEL_EXTCLK, 0x00000001 +.set CYVAL__DIRECT_SEL_ECO, 0x00000002 +.set CYVAL__DIRECT_SEL_DSI0, 0x00000004 +.set CYVAL__DIRECT_SEL_DSI1, 0x00000005 +.set CYVAL__DIRECT_SEL_DSI2, 0x00000006 +.set CYVAL__DIRECT_SEL_DSI3, 0x00000007 +.set CYFLD__DBL_SEL__OFFSET, 0x00000003 +.set CYFLD__DBL_SEL__SIZE, 0x00000003 +.set CYVAL__DBL_SEL_IMO, 0x00000000 +.set CYVAL__DBL_SEL_EXTCLK, 0x00000001 +.set CYVAL__DBL_SEL_ECO, 0x00000002 +.set CYVAL__DBL_SEL_DSI0, 0x00000004 +.set CYVAL__DBL_SEL_DSI1, 0x00000005 +.set CYVAL__DBL_SEL_DSI2, 0x00000006 +.set CYVAL__DBL_SEL_DSI3, 0x00000007 +.set CYFLD__PLL_SEL__OFFSET, 0x00000006 +.set CYFLD__PLL_SEL__SIZE, 0x00000003 +.set CYVAL__PLL_SEL_IMO, 0x00000000 +.set CYVAL__PLL_SEL_EXTCLK, 0x00000001 +.set CYVAL__PLL_SEL_ECO, 0x00000002 +.set CYVAL__PLL_SEL_DPLL, 0x00000003 +.set CYVAL__PLL_SEL_DSI0, 0x00000004 +.set CYVAL__PLL_SEL_DSI1, 0x00000005 +.set CYVAL__PLL_SEL_DSI2, 0x00000006 +.set CYVAL__PLL_SEL_DSI3, 0x00000007 +.set CYFLD__DPLLIN_SEL__OFFSET, 0x00000009 +.set CYFLD__DPLLIN_SEL__SIZE, 0x00000003 +.set CYVAL__DPLLIN_SEL_IMO, 0x00000000 +.set CYVAL__DPLLIN_SEL_EXTCLK, 0x00000001 +.set CYVAL__DPLLIN_SEL_ECO, 0x00000002 +.set CYVAL__DPLLIN_SEL_DSI0, 0x00000004 +.set CYVAL__DPLLIN_SEL_DSI1, 0x00000005 +.set CYVAL__DPLLIN_SEL_DSI2, 0x00000006 +.set CYVAL__DPLLIN_SEL_DSI3, 0x00000007 +.set CYFLD__DPLLREF_SEL__OFFSET, 0x0000000c +.set CYFLD__DPLLREF_SEL__SIZE, 0x00000002 +.set CYVAL__DPLLREF_SEL_DSI0, 0x00000000 +.set CYVAL__DPLLREF_SEL_DSI1, 0x00000001 +.set CYVAL__DPLLREF_SEL_DSI2, 0x00000002 +.set CYVAL__DPLLREF_SEL_DSI3, 0x00000003 +.set CYFLD__WDT_LOCK__OFFSET, 0x0000000e +.set CYFLD__WDT_LOCK__SIZE, 0x00000002 +.set CYVAL__WDT_LOCK_NO_CHG, 0x00000000 +.set CYVAL__WDT_LOCK_CLR0, 0x00000001 +.set CYVAL__WDT_LOCK_CLR1, 0x00000002 +.set CYVAL__WDT_LOCK_SET01, 0x00000003 +.set CYFLD__HFCLK_SEL__OFFSET, 0x00000010 +.set CYFLD__HFCLK_SEL__SIZE, 0x00000002 +.set CYVAL__HFCLK_SEL_DIRECT_SEL, 0x00000000 +.set CYVAL__HFCLK_SEL_DBL, 0x00000001 +.set CYVAL__HFCLK_SEL_PLL, 0x00000002 +.set CYFLD__HALF_EN__OFFSET, 0x00000012 +.set CYFLD__HALF_EN__SIZE, 0x00000001 +.set CYFLD__SYSCLK_DIV__OFFSET, 0x00000013 +.set CYFLD__SYSCLK_DIV__SIZE, 0x00000003 +.set CYVAL__SYSCLK_DIV_NO_DIV, 0x00000000 +.set CYVAL__SYSCLK_DIV_DIV_BY_2, 0x00000001 +.set CYVAL__SYSCLK_DIV_DIV_BY_4, 0x00000002 +.set CYVAL__SYSCLK_DIV_DIV_BY_8, 0x00000003 +.set CYVAL__SYSCLK_DIV_DIV_BY_16, 0x00000004 +.set CYVAL__SYSCLK_DIV_DIV_BY_32, 0x00000005 +.set CYVAL__SYSCLK_DIV_DIV_BY_64, 0x00000006 +.set CYVAL__SYSCLK_DIV_DIV_BY_128, 0x00000007 +.set CYREG_CLK_ILO_CONFIG, 0x400b0104 +.set CYFLD__PD_MODE__OFFSET, 0x00000000 +.set CYFLD__PD_MODE__SIZE, 0x00000001 +.set CYVAL__PD_MODE_SLEEP, 0x00000000 +.set CYVAL__PD_MODE_COMA, 0x00000001 +.set CYFLD__TURBO__OFFSET, 0x00000001 +.set CYFLD__TURBO__SIZE, 0x00000001 +.set CYFLD__SATBIAS__OFFSET, 0x00000002 +.set CYFLD__SATBIAS__SIZE, 0x00000001 +.set CYVAL__SATBIAS_SATURATED, 0x00000000 +.set CYVAL__SATBIAS_SUBTHRESHOLD, 0x00000001 +.set CYFLD__ENABLE__OFFSET, 0x0000001f +.set CYFLD__ENABLE__SIZE, 0x00000001 +.set CYREG_CLK_IMO_CONFIG, 0x400b0108 +.set CYFLD__FLASHPUMP_SEL__OFFSET, 0x00000016 +.set CYFLD__FLASHPUMP_SEL__SIZE, 0x00000001 +.set CYVAL__FLASHPUMP_SEL_GND, 0x00000000 +.set CYVAL__FLASHPUMP_SEL_CLK36, 0x00000001 +.set CYFLD__EN_FASTBIAS__OFFSET, 0x00000017 +.set CYFLD__EN_FASTBIAS__SIZE, 0x00000001 +.set CYFLD__TEST_FASTBIAS__OFFSET, 0x00000018 +.set CYFLD__TEST_FASTBIAS__SIZE, 0x00000001 +.set CYFLD__PUMP_SEL__OFFSET, 0x00000019 +.set CYFLD__PUMP_SEL__SIZE, 0x00000003 +.set CYVAL__PUMP_SEL_GND, 0x00000000 +.set CYVAL__PUMP_SEL_IMO, 0x00000001 +.set CYVAL__PUMP_SEL_DBL, 0x00000002 +.set CYVAL__PUMP_SEL_CLK36, 0x00000003 +.set CYVAL__PUMP_SEL_FF1, 0x00000004 +.set CYFLD__TEST_USB_MODE__OFFSET, 0x0000001c +.set CYFLD__TEST_USB_MODE__SIZE, 0x00000001 +.set CYFLD__EN_CLK36__OFFSET, 0x0000001d +.set CYFLD__EN_CLK36__SIZE, 0x00000001 +.set CYFLD__EN_CLK2X__OFFSET, 0x0000001e +.set CYFLD__EN_CLK2X__SIZE, 0x00000001 +.set CYREG_CLK_IMO_SPREAD, 0x400b010c +.set CYFLD__SS_VALUE__OFFSET, 0x00000000 +.set CYFLD__SS_VALUE__SIZE, 0x00000005 +.set CYFLD__SS_MAX__OFFSET, 0x00000008 +.set CYFLD__SS_MAX__SIZE, 0x00000005 +.set CYFLD__SS_RANGE__OFFSET, 0x0000001c +.set CYFLD__SS_RANGE__SIZE, 0x00000002 +.set CYVAL__SS_RANGE_M1, 0x00000000 +.set CYVAL__SS_RANGE_M2, 0x00000001 +.set CYVAL__SS_RANGE_M4, 0x00000002 +.set CYFLD__SS_MODE__OFFSET, 0x0000001e +.set CYFLD__SS_MODE__SIZE, 0x00000002 +.set CYVAL__SS_MODE_OFF, 0x00000000 +.set CYVAL__SS_MODE_TRIANGLE, 0x00000001 +.set CYVAL__SS_MODE_LFSR, 0x00000002 +.set CYVAL__SS_MODE_DSI, 0x00000003 +.set CYREG_CLK_DFT_SELECT, 0x400b0110 +.set CYFLD__DFT_SEL1__OFFSET, 0x00000000 +.set CYFLD__DFT_SEL1__SIZE, 0x00000004 +.set CYVAL__DFT_SEL1_NC, 0x00000000 +.set CYVAL__DFT_SEL1_ILO, 0x00000001 +.set CYVAL__DFT_SEL1_WCO, 0x00000002 +.set CYVAL__DFT_SEL1_IMO, 0x00000003 +.set CYVAL__DFT_SEL1_ECO, 0x00000004 +.set CYVAL__DFT_SEL1_PLL, 0x00000005 +.set CYVAL__DFT_SEL1_DPLL_OUT, 0x00000006 +.set CYVAL__DFT_SEL1_DPLL_REF, 0x00000007 +.set CYVAL__DFT_SEL1_DBL, 0x00000008 +.set CYVAL__DFT_SEL1_IMO2X, 0x00000009 +.set CYVAL__DFT_SEL1_IMO36, 0x0000000a +.set CYVAL__DFT_SEL1_HFCLK, 0x0000000b +.set CYVAL__DFT_SEL1_LFCLK, 0x0000000c +.set CYVAL__DFT_SEL1_SYSCLK, 0x0000000d +.set CYVAL__DFT_SEL1_EXTCLK, 0x0000000e +.set CYVAL__DFT_SEL1_HALFSYSCLK, 0x0000000f +.set CYFLD__DFT_DIV1__OFFSET, 0x00000004 +.set CYFLD__DFT_DIV1__SIZE, 0x00000002 +.set CYVAL__DFT_DIV1_NO_DIV, 0x00000000 +.set CYVAL__DFT_DIV1_DIV_BY_2, 0x00000001 +.set CYVAL__DFT_DIV1_DIV_BY_4, 0x00000002 +.set CYVAL__DFT_DIV1_DIV_BY_8, 0x00000003 +.set CYFLD__DFT_SEL2__OFFSET, 0x00000008 +.set CYFLD__DFT_SEL2__SIZE, 0x00000004 +.set CYVAL__DFT_SEL2_NC, 0x00000000 +.set CYVAL__DFT_SEL2_ILO, 0x00000001 +.set CYVAL__DFT_SEL2_WCO, 0x00000002 +.set CYVAL__DFT_SEL2_IMO, 0x00000003 +.set CYVAL__DFT_SEL2_ECO, 0x00000004 +.set CYVAL__DFT_SEL2_PLL, 0x00000005 +.set CYVAL__DFT_SEL2_DPLL_OUT, 0x00000006 +.set CYVAL__DFT_SEL2_DPLL_REF, 0x00000007 +.set CYVAL__DFT_SEL2_DBL, 0x00000008 +.set CYVAL__DFT_SEL2_IMO2X, 0x00000009 +.set CYVAL__DFT_SEL2_IMO36, 0x0000000a +.set CYVAL__DFT_SEL2_HFCLK, 0x0000000b +.set CYVAL__DFT_SEL2_LFCLK, 0x0000000c +.set CYVAL__DFT_SEL2_SYSCLK, 0x0000000d +.set CYVAL__DFT_SEL2_EXTCLK, 0x0000000e +.set CYVAL__DFT_SEL2_HALFSYSCLK, 0x0000000f +.set CYFLD__DFT_DIV2__OFFSET, 0x0000000c +.set CYFLD__DFT_DIV2__SIZE, 0x00000002 +.set CYVAL__DFT_DIV2_NO_DIV, 0x00000000 +.set CYVAL__DFT_DIV2_DIV_BY_2, 0x00000001 +.set CYVAL__DFT_DIV2_DIV_BY_4, 0x00000002 +.set CYVAL__DFT_DIV2_DIV_BY_8, 0x00000003 +.set CYREG_WDT_CTRLOW, 0x400b0200 +.set CYFLD__WDT_CTR0__OFFSET, 0x00000000 +.set CYFLD__WDT_CTR0__SIZE, 0x00000010 +.set CYFLD__WDT_CTR1__OFFSET, 0x00000010 +.set CYFLD__WDT_CTR1__SIZE, 0x00000010 +.set CYREG_WDT_CTRHIGH, 0x400b0204 +.set CYFLD__WDT_CTR2__OFFSET, 0x00000000 +.set CYFLD__WDT_CTR2__SIZE, 0x00000020 +.set CYREG_WDT_MATCH, 0x400b0208 +.set CYFLD__WDT_MATCH0__OFFSET, 0x00000000 +.set CYFLD__WDT_MATCH0__SIZE, 0x00000010 +.set CYFLD__WDT_MATCH1__OFFSET, 0x00000010 +.set CYFLD__WDT_MATCH1__SIZE, 0x00000010 +.set CYREG_WDT_CONFIG, 0x400b020c +.set CYFLD__WDT_MODE0__OFFSET, 0x00000000 +.set CYFLD__WDT_MODE0__SIZE, 0x00000002 +.set CYVAL__WDT_MODE0_NOTHING, 0x00000000 +.set CYVAL__WDT_MODE0_INT, 0x00000001 +.set CYVAL__WDT_MODE0_RESET, 0x00000002 +.set CYVAL__WDT_MODE0_INT_THEN_RESET, 0x00000003 +.set CYFLD__WDT_CLEAR0__OFFSET, 0x00000002 +.set CYFLD__WDT_CLEAR0__SIZE, 0x00000001 +.set CYFLD__WDT_CASCADE0_1__OFFSET, 0x00000003 +.set CYFLD__WDT_CASCADE0_1__SIZE, 0x00000001 +.set CYFLD__WDT_MODE1__OFFSET, 0x00000008 +.set CYFLD__WDT_MODE1__SIZE, 0x00000002 +.set CYVAL__WDT_MODE1_NOTHING, 0x00000000 +.set CYVAL__WDT_MODE1_INT, 0x00000001 +.set CYVAL__WDT_MODE1_RESET, 0x00000002 +.set CYVAL__WDT_MODE1_INT_THEN_RESET, 0x00000003 +.set CYFLD__WDT_CLEAR1__OFFSET, 0x0000000a +.set CYFLD__WDT_CLEAR1__SIZE, 0x00000001 +.set CYFLD__WDT_CASCADE1_2__OFFSET, 0x0000000b +.set CYFLD__WDT_CASCADE1_2__SIZE, 0x00000001 +.set CYFLD__WDT_MODE2__OFFSET, 0x00000010 +.set CYFLD__WDT_MODE2__SIZE, 0x00000001 +.set CYVAL__WDT_MODE2_NOTHING, 0x00000000 +.set CYVAL__WDT_MODE2_INT, 0x00000001 +.set CYFLD__WDT_BITS2__OFFSET, 0x00000018 +.set CYFLD__WDT_BITS2__SIZE, 0x00000005 +.set CYFLD__LFCLK_SEL__OFFSET, 0x0000001e +.set CYFLD__LFCLK_SEL__SIZE, 0x00000002 +.set CYREG_WDT_CONTROL, 0x400b0210 +.set CYFLD__WDT_ENABLE0__OFFSET, 0x00000000 +.set CYFLD__WDT_ENABLE0__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLED0__OFFSET, 0x00000001 +.set CYFLD__WDT_ENABLED0__SIZE, 0x00000001 +.set CYFLD__WDT_INT0__OFFSET, 0x00000002 +.set CYFLD__WDT_INT0__SIZE, 0x00000001 +.set CYFLD__WDT_RESET0__OFFSET, 0x00000003 +.set CYFLD__WDT_RESET0__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLE1__OFFSET, 0x00000008 +.set CYFLD__WDT_ENABLE1__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLED1__OFFSET, 0x00000009 +.set CYFLD__WDT_ENABLED1__SIZE, 0x00000001 +.set CYFLD__WDT_INT1__OFFSET, 0x0000000a +.set CYFLD__WDT_INT1__SIZE, 0x00000001 +.set CYFLD__WDT_RESET1__OFFSET, 0x0000000b +.set CYFLD__WDT_RESET1__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLE2__OFFSET, 0x00000010 +.set CYFLD__WDT_ENABLE2__SIZE, 0x00000001 +.set CYFLD__WDT_ENABLED2__OFFSET, 0x00000011 +.set CYFLD__WDT_ENABLED2__SIZE, 0x00000001 +.set CYFLD__WDT_INT2__OFFSET, 0x00000012 +.set CYFLD__WDT_INT2__SIZE, 0x00000001 +.set CYFLD__WDT_RESET2__OFFSET, 0x00000013 +.set CYFLD__WDT_RESET2__SIZE, 0x00000001 +.set CYREG_RES_CAUSE, 0x400b0300 +.set CYFLD__RESET_WDT__OFFSET, 0x00000000 +.set CYFLD__RESET_WDT__SIZE, 0x00000001 +.set CYFLD__RESET_DSBOD__OFFSET, 0x00000001 +.set CYFLD__RESET_DSBOD__SIZE, 0x00000001 +.set CYFLD__RESET_LOCKUP__OFFSET, 0x00000002 +.set CYFLD__RESET_LOCKUP__SIZE, 0x00000001 +.set CYFLD__RESET_PROT_FAULT__OFFSET, 0x00000003 +.set CYFLD__RESET_PROT_FAULT__SIZE, 0x00000001 +.set CYFLD__RESET_SOFT__OFFSET, 0x00000004 +.set CYFLD__RESET_SOFT__SIZE, 0x00000001 +.set CYFLD__RESET_HVBOD__OFFSET, 0x00000005 +.set CYFLD__RESET_HVBOD__SIZE, 0x00000001 +.set CYFLD__RESET_PBOD__OFFSET, 0x00000006 +.set CYFLD__RESET_PBOD__SIZE, 0x00000001 +.set CYFLD__RESET_XRES__OFFSET, 0x00000007 +.set CYFLD__RESET_XRES__SIZE, 0x00000001 +.set CYREG_PWR_PWRSYS_TRIM1, 0x400bff00 +.set CYFLD__HIB_BIAS_TRIM__OFFSET, 0x00000000 +.set CYFLD__HIB_BIAS_TRIM__SIZE, 0x00000003 +.set CYFLD__BOD_TURBO_THRESH__OFFSET, 0x00000003 +.set CYFLD__BOD_TURBO_THRESH__SIZE, 0x00000001 +.set CYFLD__BOD_TRIM_TRIP__OFFSET, 0x00000004 +.set CYFLD__BOD_TRIM_TRIP__SIZE, 0x00000004 +.set CYREG_PWR_PWRSYS_TRIM2, 0x400bff04 +.set CYFLD__LFCLK_TRIM_LOAD__OFFSET, 0x00000000 +.set CYFLD__LFCLK_TRIM_LOAD__SIZE, 0x00000002 +.set CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET, 0x00000002 +.set CYFLD__LFCLK_TRIM_VOLTAGE__SIZE, 0x00000002 +.set CYFLD__DPSLP_TRIM_LOAD__OFFSET, 0x00000004 +.set CYFLD__DPSLP_TRIM_LOAD__SIZE, 0x00000002 +.set CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET, 0x00000006 +.set CYFLD__DPSLP_TRIM_LEAKAGE__SIZE, 0x00000001 +.set CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET, 0x00000007 +.set CYFLD__DPSLP_TRIM_VOLTAGE__SIZE, 0x00000001 +.set CYREG_PWR_PWRSYS_TRIM3, 0x400bff08 +.set CYFLD__NWELL_TRIM__OFFSET, 0x00000000 +.set CYFLD__NWELL_TRIM__SIZE, 0x00000003 +.set CYFLD__QUIET_TRIM__OFFSET, 0x00000003 +.set CYFLD__QUIET_TRIM__SIZE, 0x00000005 +.set CYREG_PWR_PWRSYS_TRIM4, 0x400bff0c +.set CYFLD__HIB_TRIM_NWELL__OFFSET, 0x00000000 +.set CYFLD__HIB_TRIM_NWELL__SIZE, 0x00000002 +.set CYFLD__HIB_TRIM_LEAKAGE__OFFSET, 0x00000002 +.set CYFLD__HIB_TRIM_LEAKAGE__SIZE, 0x00000001 +.set CYFLD__HIB_TRIM_VOLTAGE__OFFSET, 0x00000003 +.set CYFLD__HIB_TRIM_VOLTAGE__SIZE, 0x00000001 +.set CYFLD__HIB_TRIM_REFERENCE__OFFSET, 0x00000004 +.set CYFLD__HIB_TRIM_REFERENCE__SIZE, 0x00000002 +.set CYREG_PWR_BG_TRIM1, 0x400bff10 +.set CYFLD__INL_TRIM_MAIN__OFFSET, 0x00000000 +.set CYFLD__INL_TRIM_MAIN__SIZE, 0x00000003 +.set CYFLD__INL_CROSS_MAIN__OFFSET, 0x00000003 +.set CYFLD__INL_CROSS_MAIN__SIZE, 0x00000004 +.set CYREG_PWR_BG_TRIM2, 0x400bff14 +.set CYFLD__VCTAT_SLOPE__OFFSET, 0x00000000 +.set CYFLD__VCTAT_SLOPE__SIZE, 0x00000004 +.set CYFLD__VCTAT_VOLTAGE__OFFSET, 0x00000004 +.set CYFLD__VCTAT_VOLTAGE__SIZE, 0x00000002 +.set CYFLD__VCTAT_ENABLE__OFFSET, 0x00000006 +.set CYFLD__VCTAT_ENABLE__SIZE, 0x00000001 +.set CYFLD__VCTAT_VOLTAGE_MSB__OFFSET, 0x00000007 +.set CYFLD__VCTAT_VOLTAGE_MSB__SIZE, 0x00000001 +.set CYREG_PWR_BG_TRIM3, 0x400bff18 +.set CYFLD__INL_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD__INL_TRIM_IMO__SIZE, 0x00000003 +.set CYFLD__INL_CROSS_IMO__OFFSET, 0x00000003 +.set CYFLD__INL_CROSS_IMO__SIZE, 0x00000004 +.set CYREG_PWR_BG_TRIM4, 0x400bff1c +.set CYFLD__ABS_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD__ABS_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_PWR_BG_TRIM5, 0x400bff20 +.set CYFLD__TMPCO_TRIM_IMO__OFFSET, 0x00000000 +.set CYFLD__TMPCO_TRIM_IMO__SIZE, 0x00000006 +.set CYREG_CLK_ILO_TRIM, 0x400bff24 +.set CYFLD__TRIM__OFFSET, 0x00000000 +.set CYFLD__TRIM__SIZE, 0x00000004 +.set CYFLD__COARSE_TRIM__OFFSET, 0x00000004 +.set CYFLD__COARSE_TRIM__SIZE, 0x00000004 +.set CYREG_CLK_IMO_TRIM1, 0x400bff28 +.set CYFLD__OFFSET__OFFSET, 0x00000000 +.set CYFLD__OFFSET__SIZE, 0x00000008 +.set CYREG_CLK_IMO_TRIM2, 0x400bff2c +.set CYFLD__FREQ__OFFSET, 0x00000000 +.set CYFLD__FREQ__SIZE, 0x00000006 +.set CYREG_CLK_IMO_TRIM3, 0x400bff30 +.set CYFLD__TRIM_CLK36__OFFSET, 0x00000000 +.set CYFLD__TRIM_CLK36__SIZE, 0x00000004 +.set CYREG_CLK_IMO_TRIM4, 0x400bff34 +.set CYFLD__GAIN__OFFSET, 0x00000000 +.set CYFLD__GAIN__SIZE, 0x00000005 +.set CYFLD__FSOFFSET__OFFSET, 0x00000005 +.set CYFLD__FSOFFSET__SIZE, 0x00000003 +.set CYREG_PWR_RSVD_TRIM, 0x400bff38 +.set CYFLD__RSVD_TRIM__OFFSET, 0x00000000 +.set CYFLD__RSVD_TRIM__SIZE, 0x00000004 +.set CYDEV_SPCIF_BASE, 0x400e0000 +.set CYDEV_SPCIF_SIZE, 0x00010000 +.set CYREG_SPCIF_GEOMETRY, 0x400e0000 +.set CYFLD_SPCIF_FLASH__OFFSET, 0x00000000 +.set CYFLD_SPCIF_FLASH__SIZE, 0x00000010 +.set CYFLD_SPCIF_SFLASH__OFFSET, 0x00000010 +.set CYFLD_SPCIF_SFLASH__SIZE, 0x00000004 +.set CYFLD_SPCIF_NUM_FLASH__OFFSET, 0x00000014 +.set CYFLD_SPCIF_NUM_FLASH__SIZE, 0x00000002 +.set CYFLD_SPCIF_FLASH_ROW__OFFSET, 0x00000016 +.set CYFLD_SPCIF_FLASH_ROW__SIZE, 0x00000002 +.set CYFLD_SPCIF_NVL__OFFSET, 0x00000018 +.set CYFLD_SPCIF_NVL__SIZE, 0x00000007 +.set CYFLD_SPCIF_DE_CPD_LP__OFFSET, 0x0000001f +.set CYFLD_SPCIF_DE_CPD_LP__SIZE, 0x00000001 +.set CYREG_SPCIF_NVL_WR_DATA, 0x400e001c +.set CYFLD_SPCIF_DATA__OFFSET, 0x00000000 +.set CYFLD_SPCIF_DATA__SIZE, 0x00000008 +.set CYDEV_UDB_BASE, 0x400f0000 +.set CYDEV_UDB_SIZE, 0x00010000 +.set CYDEV_UDB_W8_BASE, 0x400f0000 +.set CYDEV_UDB_W8_SIZE, 0x00001000 +.set CYREG_UDB_W8_A0_00, 0x400f0000 +.set CYFLD_UDB_W8_A0__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_A0__SIZE, 0x00000008 +.set CYREG_UDB_W8_A0_01, 0x400f0001 +.set CYREG_UDB_W8_A0_02, 0x400f0002 +.set CYREG_UDB_W8_A0_03, 0x400f0003 +.set CYREG_UDB_W8_A1_00, 0x400f0010 +.set CYFLD_UDB_W8_A1__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_A1__SIZE, 0x00000008 +.set CYREG_UDB_W8_A1_01, 0x400f0011 +.set CYREG_UDB_W8_A1_02, 0x400f0012 +.set CYREG_UDB_W8_A1_03, 0x400f0013 +.set CYREG_UDB_W8_D0_00, 0x400f0020 +.set CYFLD_UDB_W8_D0__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_D0__SIZE, 0x00000008 +.set CYREG_UDB_W8_D0_01, 0x400f0021 +.set CYREG_UDB_W8_D0_02, 0x400f0022 +.set CYREG_UDB_W8_D0_03, 0x400f0023 +.set CYREG_UDB_W8_D1_00, 0x400f0030 +.set CYFLD_UDB_W8_D1__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_D1__SIZE, 0x00000008 +.set CYREG_UDB_W8_D1_01, 0x400f0031 +.set CYREG_UDB_W8_D1_02, 0x400f0032 +.set CYREG_UDB_W8_D1_03, 0x400f0033 +.set CYREG_UDB_W8_F0_00, 0x400f0040 +.set CYFLD_UDB_W8_F0__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_F0__SIZE, 0x00000008 +.set CYREG_UDB_W8_F0_01, 0x400f0041 +.set CYREG_UDB_W8_F0_02, 0x400f0042 +.set CYREG_UDB_W8_F0_03, 0x400f0043 +.set CYREG_UDB_W8_F1_00, 0x400f0050 +.set CYFLD_UDB_W8_F1__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_F1__SIZE, 0x00000008 +.set CYREG_UDB_W8_F1_01, 0x400f0051 +.set CYREG_UDB_W8_F1_02, 0x400f0052 +.set CYREG_UDB_W8_F1_03, 0x400f0053 +.set CYREG_UDB_W8_ST_00, 0x400f0060 +.set CYFLD_UDB_W8_ST__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_ST__SIZE, 0x00000008 +.set CYREG_UDB_W8_ST_01, 0x400f0061 +.set CYREG_UDB_W8_ST_02, 0x400f0062 +.set CYREG_UDB_W8_ST_03, 0x400f0063 +.set CYREG_UDB_W8_CTL_00, 0x400f0070 +.set CYFLD_UDB_W8_CTL__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_CTL__SIZE, 0x00000008 +.set CYREG_UDB_W8_CTL_01, 0x400f0071 +.set CYREG_UDB_W8_CTL_02, 0x400f0072 +.set CYREG_UDB_W8_CTL_03, 0x400f0073 +.set CYREG_UDB_W8_MSK_00, 0x400f0080 +.set CYFLD_UDB_W8_MSK__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_MSK__SIZE, 0x00000007 +.set CYREG_UDB_W8_MSK_01, 0x400f0081 +.set CYREG_UDB_W8_MSK_02, 0x400f0082 +.set CYREG_UDB_W8_MSK_03, 0x400f0083 +.set CYREG_UDB_W8_ACTL_00, 0x400f0090 +.set CYFLD_UDB_W8_FIFO0_CLR__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_FIFO0_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO0_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO0_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_W8_FIFO1_CLR__OFFSET, 0x00000001 +.set CYFLD_UDB_W8_FIFO1_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO1_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO1_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_W8_FIFO0_LVL__OFFSET, 0x00000002 +.set CYFLD_UDB_W8_FIFO0_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO0_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO0_LVL_MID, 0x00000001 +.set CYFLD_UDB_W8_FIFO1_LVL__OFFSET, 0x00000003 +.set CYFLD_UDB_W8_FIFO1_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_W8_FIFO1_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_W8_FIFO1_LVL_MID, 0x00000001 +.set CYFLD_UDB_W8_INT_EN__OFFSET, 0x00000004 +.set CYFLD_UDB_W8_INT_EN__SIZE, 0x00000001 +.set CYVAL_UDB_W8_INT_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_W8_INT_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_W8_CNT_START__OFFSET, 0x00000005 +.set CYFLD_UDB_W8_CNT_START__SIZE, 0x00000001 +.set CYVAL_UDB_W8_CNT_START_DISABLE, 0x00000000 +.set CYVAL_UDB_W8_CNT_START_ENABLE, 0x00000001 +.set CYREG_UDB_W8_ACTL_01, 0x400f0091 +.set CYREG_UDB_W8_ACTL_02, 0x400f0092 +.set CYREG_UDB_W8_ACTL_03, 0x400f0093 +.set CYREG_UDB_W8_MC_00, 0x400f00a0 +.set CYFLD_UDB_W8_PLD0_MC__OFFSET, 0x00000000 +.set CYFLD_UDB_W8_PLD0_MC__SIZE, 0x00000004 +.set CYFLD_UDB_W8_PLD1_MC__OFFSET, 0x00000004 +.set CYFLD_UDB_W8_PLD1_MC__SIZE, 0x00000004 +.set CYREG_UDB_W8_MC_01, 0x400f00a1 +.set CYREG_UDB_W8_MC_02, 0x400f00a2 +.set CYREG_UDB_W8_MC_03, 0x400f00a3 +.set CYDEV_UDB_CAT16_BASE, 0x400f1000 +.set CYDEV_UDB_CAT16_SIZE, 0x00001000 +.set CYREG_UDB_CAT16_A_00, 0x400f1000 +.set CYFLD_UDB_CAT16_A0__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_A0__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_A1__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_A1__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_A_01, 0x400f1002 +.set CYREG_UDB_CAT16_A_02, 0x400f1004 +.set CYREG_UDB_CAT16_A_03, 0x400f1006 +.set CYREG_UDB_CAT16_D_00, 0x400f1040 +.set CYFLD_UDB_CAT16_D0__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_D0__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_D1__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_D1__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_D_01, 0x400f1042 +.set CYREG_UDB_CAT16_D_02, 0x400f1044 +.set CYREG_UDB_CAT16_D_03, 0x400f1046 +.set CYREG_UDB_CAT16_F_00, 0x400f1080 +.set CYFLD_UDB_CAT16_F0__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_F0__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_F1__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_F1__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_F_01, 0x400f1082 +.set CYREG_UDB_CAT16_F_02, 0x400f1084 +.set CYREG_UDB_CAT16_F_03, 0x400f1086 +.set CYREG_UDB_CAT16_CTL_ST_00, 0x400f10c0 +.set CYFLD_UDB_CAT16_ST__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_ST__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_CTL__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_CTL__SIZE, 0x00000008 +.set CYREG_UDB_CAT16_CTL_ST_01, 0x400f10c2 +.set CYREG_UDB_CAT16_CTL_ST_02, 0x400f10c4 +.set CYREG_UDB_CAT16_CTL_ST_03, 0x400f10c6 +.set CYREG_UDB_CAT16_ACTL_MSK_00, 0x400f1100 +.set CYFLD_UDB_CAT16_MSK__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_MSK__SIZE, 0x00000008 +.set CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET, 0x00000008 +.set CYFLD_UDB_CAT16_FIFO0_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET, 0x00000009 +.set CYFLD_UDB_CAT16_FIFO1_CLR__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR, 0x00000001 +.set CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET, 0x0000000a +.set CYFLD_UDB_CAT16_FIFO0_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO0_LVL_MID, 0x00000001 +.set CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET, 0x0000000b +.set CYFLD_UDB_CAT16_FIFO1_LVL__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL, 0x00000000 +.set CYVAL_UDB_CAT16_FIFO1_LVL_MID, 0x00000001 +.set CYFLD_UDB_CAT16_INT_EN__OFFSET, 0x0000000c +.set CYFLD_UDB_CAT16_INT_EN__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_INT_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_CAT16_INT_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_CAT16_CNT_START__OFFSET, 0x0000000d +.set CYFLD_UDB_CAT16_CNT_START__SIZE, 0x00000001 +.set CYVAL_UDB_CAT16_CNT_START_DISABLE, 0x00000000 +.set CYVAL_UDB_CAT16_CNT_START_ENABLE, 0x00000001 +.set CYREG_UDB_CAT16_ACTL_MSK_01, 0x400f1102 +.set CYREG_UDB_CAT16_ACTL_MSK_02, 0x400f1104 +.set CYREG_UDB_CAT16_ACTL_MSK_03, 0x400f1106 +.set CYREG_UDB_CAT16_MC_00, 0x400f1140 +.set CYFLD_UDB_CAT16_PLD0_MC__OFFSET, 0x00000000 +.set CYFLD_UDB_CAT16_PLD0_MC__SIZE, 0x00000004 +.set CYFLD_UDB_CAT16_PLD1_MC__OFFSET, 0x00000004 +.set CYFLD_UDB_CAT16_PLD1_MC__SIZE, 0x00000004 +.set CYREG_UDB_CAT16_MC_01, 0x400f1142 +.set CYREG_UDB_CAT16_MC_02, 0x400f1144 +.set CYREG_UDB_CAT16_MC_03, 0x400f1146 +.set CYDEV_UDB_W16_BASE, 0x400f1000 +.set CYDEV_UDB_W16_SIZE, 0x00001000 +.set CYREG_UDB_W16_A0_00, 0x400f1000 +.set CYFLD_UDB_W16_A0_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_A0_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_A0_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_A0_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_A0_01, 0x400f1002 +.set CYREG_UDB_W16_A0_02, 0x400f1004 +.set CYREG_UDB_W16_A1_00, 0x400f1020 +.set CYFLD_UDB_W16_A1_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_A1_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_A1_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_A1_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_A1_01, 0x400f1022 +.set CYREG_UDB_W16_A1_02, 0x400f1024 +.set CYREG_UDB_W16_D0_00, 0x400f1040 +.set CYFLD_UDB_W16_D0_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_D0_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_D0_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_D0_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_D0_01, 0x400f1042 +.set CYREG_UDB_W16_D0_02, 0x400f1044 +.set CYREG_UDB_W16_D1_00, 0x400f1060 +.set CYFLD_UDB_W16_D1_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_D1_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_D1_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_D1_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_D1_01, 0x400f1062 +.set CYREG_UDB_W16_D1_02, 0x400f1064 +.set CYREG_UDB_W16_F0_00, 0x400f1080 +.set CYFLD_UDB_W16_F0_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_F0_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_F0_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_F0_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_F0_01, 0x400f1082 +.set CYREG_UDB_W16_F0_02, 0x400f1084 +.set CYREG_UDB_W16_F1_00, 0x400f10a0 +.set CYFLD_UDB_W16_F1_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_F1_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_F1_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_F1_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_F1_01, 0x400f10a2 +.set CYREG_UDB_W16_F1_02, 0x400f10a4 +.set CYREG_UDB_W16_ST_00, 0x400f10c0 +.set CYFLD_UDB_W16_ST_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_ST_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_ST_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_ST_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_ST_01, 0x400f10c2 +.set CYREG_UDB_W16_ST_02, 0x400f10c4 +.set CYREG_UDB_W16_CTL_00, 0x400f10e0 +.set CYFLD_UDB_W16_CTL_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_CTL_LS__SIZE, 0x00000008 +.set CYFLD_UDB_W16_CTL_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_CTL_MS__SIZE, 0x00000008 +.set CYREG_UDB_W16_CTL_01, 0x400f10e2 +.set CYREG_UDB_W16_CTL_02, 0x400f10e4 +.set CYREG_UDB_W16_MSK_00, 0x400f1100 +.set CYFLD_UDB_W16_MSK_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_MSK_LS__SIZE, 0x00000007 +.set CYFLD_UDB_W16_MSK_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_MSK_MS__SIZE, 0x00000007 +.set CYREG_UDB_W16_MSK_01, 0x400f1102 +.set CYREG_UDB_W16_MSK_02, 0x400f1104 +.set CYREG_UDB_W16_ACTL_00, 0x400f1120 +.set CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET, 0x00000002 +.set CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_LVL_LS_MID, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET, 0x00000003 +.set CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_LVL_LS_MID, 0x00000001 +.set CYFLD_UDB_W16_INT_EN_LS__OFFSET, 0x00000004 +.set CYFLD_UDB_W16_INT_EN_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_INT_EN_LS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_INT_EN_LS_ENABLE, 0x00000001 +.set CYFLD_UDB_W16_CNT_START_LS__OFFSET, 0x00000005 +.set CYFLD_UDB_W16_CNT_START_LS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_CNT_START_LS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_CNT_START_LS_ENABLE, 0x00000001 +.set CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET, 0x00000009 +.set CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR, 0x00000001 +.set CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET, 0x0000000a +.set CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO0_LVL_MS_MID, 0x00000001 +.set CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET, 0x0000000b +.set CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL, 0x00000000 +.set CYVAL_UDB_W16_FIFO1_LVL_MS_MID, 0x00000001 +.set CYFLD_UDB_W16_INT_EN_MS__OFFSET, 0x0000000c +.set CYFLD_UDB_W16_INT_EN_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_INT_EN_MS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_INT_EN_MS_ENABLE, 0x00000001 +.set CYFLD_UDB_W16_CNT_START_MS__OFFSET, 0x0000000d +.set CYFLD_UDB_W16_CNT_START_MS__SIZE, 0x00000001 +.set CYVAL_UDB_W16_CNT_START_MS_DISABLE, 0x00000000 +.set CYVAL_UDB_W16_CNT_START_MS_ENABLE, 0x00000001 +.set CYREG_UDB_W16_ACTL_01, 0x400f1122 +.set CYREG_UDB_W16_ACTL_02, 0x400f1124 +.set CYREG_UDB_W16_MC_00, 0x400f1140 +.set CYFLD_UDB_W16_PLD0_MC_LS__OFFSET, 0x00000000 +.set CYFLD_UDB_W16_PLD0_MC_LS__SIZE, 0x00000004 +.set CYFLD_UDB_W16_PLD1_MC_LS__OFFSET, 0x00000004 +.set CYFLD_UDB_W16_PLD1_MC_LS__SIZE, 0x00000004 +.set CYFLD_UDB_W16_PLD0_MC_MS__OFFSET, 0x00000008 +.set CYFLD_UDB_W16_PLD0_MC_MS__SIZE, 0x00000004 +.set CYFLD_UDB_W16_PLD1_MC_MS__OFFSET, 0x0000000c +.set CYFLD_UDB_W16_PLD1_MC_MS__SIZE, 0x00000004 +.set CYREG_UDB_W16_MC_01, 0x400f1142 +.set CYREG_UDB_W16_MC_02, 0x400f1144 +.set CYDEV_UDB_W32_BASE, 0x400f2000 +.set CYDEV_UDB_W32_SIZE, 0x00001000 +.set CYREG_UDB_W32_A0_00, 0x400f2000 +.set CYFLD_UDB_W32_A0_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_A0_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A0_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_A0_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A0_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_A0_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A0_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_A0_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_A1_00, 0x400f2040 +.set CYFLD_UDB_W32_A1_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_A1_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A1_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_A1_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A1_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_A1_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_A1_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_A1_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_D0_00, 0x400f2080 +.set CYFLD_UDB_W32_D0_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_D0_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D0_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_D0_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D0_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_D0_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D0_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_D0_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_D1_00, 0x400f20c0 +.set CYFLD_UDB_W32_D1_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_D1_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D1_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_D1_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D1_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_D1_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_D1_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_D1_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_F0_00, 0x400f2100 +.set CYFLD_UDB_W32_F0_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_F0_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F0_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_F0_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F0_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_F0_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F0_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_F0_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_F1_00, 0x400f2140 +.set CYFLD_UDB_W32_F1_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_F1_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F1_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_F1_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F1_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_F1_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_F1_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_F1_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_ST_00, 0x400f2180 +.set CYFLD_UDB_W32_ST_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_ST_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_ST_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_ST_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_ST_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_ST_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_ST_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_ST_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_CTL_00, 0x400f21c0 +.set CYFLD_UDB_W32_CTL_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_CTL_0__SIZE, 0x00000008 +.set CYFLD_UDB_W32_CTL_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_CTL_1__SIZE, 0x00000008 +.set CYFLD_UDB_W32_CTL_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_CTL_2__SIZE, 0x00000008 +.set CYFLD_UDB_W32_CTL_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_CTL_3__SIZE, 0x00000008 +.set CYREG_UDB_W32_MSK_00, 0x400f2200 +.set CYFLD_UDB_W32_MSK_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_MSK_0__SIZE, 0x00000007 +.set CYFLD_UDB_W32_MSK_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_MSK_1__SIZE, 0x00000007 +.set CYFLD_UDB_W32_MSK_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_MSK_2__SIZE, 0x00000007 +.set CYFLD_UDB_W32_MSK_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_MSK_3__SIZE, 0x00000007 +.set CYREG_UDB_W32_ACTL_00, 0x400f2240 +.set CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_FIFO0_CLR_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET, 0x00000002 +.set CYFLD_UDB_W32_FIFO0_LVL_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_0_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET, 0x00000003 +.set CYFLD_UDB_W32_FIFO1_LVL_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_0_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_0__OFFSET, 0x00000004 +.set CYFLD_UDB_W32_INT_EN_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_0_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_0_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_0__OFFSET, 0x00000005 +.set CYFLD_UDB_W32_CNT_START_0__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_0_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_0_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_FIFO0_CLR_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET, 0x00000009 +.set CYFLD_UDB_W32_FIFO1_CLR_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET, 0x0000000a +.set CYFLD_UDB_W32_FIFO0_LVL_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_1_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET, 0x0000000b +.set CYFLD_UDB_W32_FIFO1_LVL_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_1_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_1__OFFSET, 0x0000000c +.set CYFLD_UDB_W32_INT_EN_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_1_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_1_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_1__OFFSET, 0x0000000d +.set CYFLD_UDB_W32_CNT_START_1__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_1_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_1_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_FIFO0_CLR_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET, 0x00000011 +.set CYFLD_UDB_W32_FIFO1_CLR_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET, 0x00000012 +.set CYFLD_UDB_W32_FIFO0_LVL_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_2_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET, 0x00000013 +.set CYFLD_UDB_W32_FIFO1_LVL_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_2_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_2__OFFSET, 0x00000014 +.set CYFLD_UDB_W32_INT_EN_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_2_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_2_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_2__OFFSET, 0x00000015 +.set CYFLD_UDB_W32_CNT_START_2__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_2_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_2_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_FIFO0_CLR_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET, 0x00000019 +.set CYFLD_UDB_W32_FIFO1_CLR_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR, 0x00000001 +.set CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET, 0x0000001a +.set CYFLD_UDB_W32_FIFO0_LVL_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO0_LVL_3_MID, 0x00000001 +.set CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET, 0x0000001b +.set CYFLD_UDB_W32_FIFO1_LVL_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL, 0x00000000 +.set CYVAL_UDB_W32_FIFO1_LVL_3_MID, 0x00000001 +.set CYFLD_UDB_W32_INT_EN_3__OFFSET, 0x0000001c +.set CYFLD_UDB_W32_INT_EN_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_INT_EN_3_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_INT_EN_3_ENABLE, 0x00000001 +.set CYFLD_UDB_W32_CNT_START_3__OFFSET, 0x0000001d +.set CYFLD_UDB_W32_CNT_START_3__SIZE, 0x00000001 +.set CYVAL_UDB_W32_CNT_START_3_DISABLE, 0x00000000 +.set CYVAL_UDB_W32_CNT_START_3_ENABLE, 0x00000001 +.set CYREG_UDB_W32_MC_00, 0x400f2280 +.set CYFLD_UDB_W32_PLD0_MC_0__OFFSET, 0x00000000 +.set CYFLD_UDB_W32_PLD0_MC_0__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_0__OFFSET, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_0__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD0_MC_1__OFFSET, 0x00000008 +.set CYFLD_UDB_W32_PLD0_MC_1__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_1__OFFSET, 0x0000000c +.set CYFLD_UDB_W32_PLD1_MC_1__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD0_MC_2__OFFSET, 0x00000010 +.set CYFLD_UDB_W32_PLD0_MC_2__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_2__OFFSET, 0x00000014 +.set CYFLD_UDB_W32_PLD1_MC_2__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD0_MC_3__OFFSET, 0x00000018 +.set CYFLD_UDB_W32_PLD0_MC_3__SIZE, 0x00000004 +.set CYFLD_UDB_W32_PLD1_MC_3__OFFSET, 0x0000001c +.set CYFLD_UDB_W32_PLD1_MC_3__SIZE, 0x00000004 +.set CYDEV_UDB_P0_BASE, 0x400f3000 +.set CYDEV_UDB_P0_SIZE, 0x00000200 +.set CYDEV_UDB_P0_U0_BASE, 0x400f3000 +.set CYDEV_UDB_P0_U0_SIZE, 0x00000080 +.set CYREG_UDB_P0_U0_PLD_IT0, 0x400f3000 +.set CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET, 0x00000010 +.set CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET, 0x00000011 +.set CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET, 0x00000012 +.set CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET, 0x00000013 +.set CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET, 0x00000014 +.set CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET, 0x00000015 +.set CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET, 0x00000016 +.set CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET, 0x00000017 +.set CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET, 0x00000018 +.set CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET, 0x00000019 +.set CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET, 0x0000001a +.set CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET, 0x0000001b +.set CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET, 0x0000001c +.set CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET, 0x0000001d +.set CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET, 0x0000001e +.set CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET, 0x0000001f +.set CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_IT1, 0x400f3004 +.set CYREG_UDB_P0_U0_PLD_IT2, 0x400f3008 +.set CYREG_UDB_P0_U0_PLD_IT3, 0x400f300c +.set CYREG_UDB_P0_U0_PLD_IT4, 0x400f3010 +.set CYREG_UDB_P0_U0_PLD_IT5, 0x400f3014 +.set CYREG_UDB_P0_U0_PLD_IT6, 0x400f3018 +.set CYREG_UDB_P0_U0_PLD_IT7, 0x400f301c +.set CYREG_UDB_P0_U0_PLD_IT8, 0x400f3020 +.set CYREG_UDB_P0_U0_PLD_IT9, 0x400f3024 +.set CYREG_UDB_P0_U0_PLD_IT10, 0x400f3028 +.set CYREG_UDB_P0_U0_PLD_IT11, 0x400f302c +.set CYREG_UDB_P0_U0_PLD_ORT0, 0x400f3030 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_ORT1, 0x400f3032 +.set CYREG_UDB_P0_U0_PLD_ORT2, 0x400f3034 +.set CYREG_UDB_P0_U0_PLD_ORT3, 0x400f3036 +.set CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST, 0x400f3038 +.set CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB, 0x400f303a +.set CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L, 0x00000003 +.set CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L, 0x00000003 +.set CYREG_UDB_P0_U0_PLD_MC_SET_RESET, 0x400f303c +.set CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS, 0x400f303e +.set CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_NC1__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC3__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_NC3__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC5__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_NC5__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC7__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_NC7__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC9__OFFSET, 0x00000009 +.set CYFLD_UDB_P_U_NC9__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC11__OFFSET, 0x0000000b +.set CYFLD_UDB_P_U_NC11__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC13__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_NC13__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET, 0x0000000e +.set CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC15__OFFSET, 0x0000000f +.set CYFLD_UDB_P_U_NC15__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG0, 0x400f3040 +.set CYFLD_UDB_P_U_RAD0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RAD0__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_RAD0_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RAD0_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_RAD0_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_RAD0_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_RAD0_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_RAD0_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_RAD0_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_RAD0_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_RAD1__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_RAD1__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_RAD1_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RAD1_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_RAD1_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_RAD1_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_RAD1_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_RAD1_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_RAD1_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_RAD1_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG1, 0x400f3041 +.set CYFLD_UDB_P_U_RAD2__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RAD2__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_RAD2_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RAD2_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_RAD2_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_RAD2_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_RAD2_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_RAD2_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_RAD2_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_RAD2_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS, 0x00000001 +.set CYREG_UDB_P0_U0_CFG2, 0x400f3042 +.set CYFLD_UDB_P_U_F0_LD__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_F0_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_F0_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_F0_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_F0_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_F0_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_F0_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_F0_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_F0_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_F0_LD_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE, 0x00000000 +.set CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS, 0x00000001 +.set CYFLD_UDB_P_U_F1_LD__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_F1_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_F1_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_F1_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_F1_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_F1_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_F1_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_F1_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_F1_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_F1_LD_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG3, 0x400f3043 +.set CYFLD_UDB_P_U_D0_LD__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_D0_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_D0_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_D0_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_D0_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_D0_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_D0_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_D0_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_D0_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_D0_LD_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_D1_LD__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_D1_LD__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_D1_LD_OFF, 0x00000000 +.set CYVAL_UDB_P_U_D1_LD_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_D1_LD_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_D1_LD_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_D1_LD_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_D1_LD_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_D1_LD_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_D1_LD_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG4, 0x400f3044 +.set CYFLD_UDB_P_U_SI_MUX__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_SI_MUX__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_SI_MUX_OFF, 0x00000000 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_SI_MUX_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_SI_MUX_RESERVED, 0x00000007 +.set CYFLD_UDB_P_U_CI_MUX__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_CI_MUX__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_CI_MUX_OFF, 0x00000000 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN0, 0x00000001 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN1, 0x00000002 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN2, 0x00000003 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN3, 0x00000004 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN4, 0x00000005 +.set CYVAL_UDB_P_U_CI_MUX_DP_IN5, 0x00000006 +.set CYVAL_UDB_P_U_CI_MUX_RESERVED, 0x00000007 +.set CYREG_UDB_P0_U0_CFG5, 0x400f3045 +.set CYFLD_UDB_P_U_OUT0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT0__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT0_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT0_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT0_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT0_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT0_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT0_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT0_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT0_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT0_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT0_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT0_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT0_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT0_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT0_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT0_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT0_F1_BUS_STAT, 0x0000000f +.set CYFLD_UDB_P_U_OUT1__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_OUT1__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT1_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT1_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT1_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT1_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT1_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT1_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT1_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT1_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT1_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT1_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT1_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT1_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT1_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT1_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT1_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT1_F1_BUS_STAT, 0x0000000f +.set CYREG_UDB_P0_U0_CFG6, 0x400f3046 +.set CYFLD_UDB_P_U_OUT2__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT2__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT2_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT2_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT2_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT2_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT2_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT2_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT2_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT2_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT2_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT2_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT2_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT2_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT2_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT2_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT2_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT2_F1_BUS_STAT, 0x0000000f +.set CYFLD_UDB_P_U_OUT3__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_OUT3__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT3_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT3_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT3_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT3_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT3_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT3_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT3_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT3_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT3_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT3_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT3_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT3_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT3_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT3_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT3_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT3_F1_BUS_STAT, 0x0000000f +.set CYREG_UDB_P0_U0_CFG7, 0x400f3047 +.set CYFLD_UDB_P_U_OUT4__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT4__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT4_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT4_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT4_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT4_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT4_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT4_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT4_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT4_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT4_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT4_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT4_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT4_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT4_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT4_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT4_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT4_F1_BUS_STAT, 0x0000000f +.set CYFLD_UDB_P_U_OUT5__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_OUT5__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_OUT5_CE0, 0x00000000 +.set CYVAL_UDB_P_U_OUT5_CL0, 0x00000001 +.set CYVAL_UDB_P_U_OUT5_Z0, 0x00000002 +.set CYVAL_UDB_P_U_OUT5_FF0, 0x00000003 +.set CYVAL_UDB_P_U_OUT5_CE1, 0x00000004 +.set CYVAL_UDB_P_U_OUT5_CL1, 0x00000005 +.set CYVAL_UDB_P_U_OUT5_Z1, 0x00000006 +.set CYVAL_UDB_P_U_OUT5_FF1, 0x00000007 +.set CYVAL_UDB_P_U_OUT5_OV_MSB, 0x00000008 +.set CYVAL_UDB_P_U_OUT5_CO_MSB, 0x00000009 +.set CYVAL_UDB_P_U_OUT5_CMSBO, 0x0000000a +.set CYVAL_UDB_P_U_OUT5_SO, 0x0000000b +.set CYVAL_UDB_P_U_OUT5_F0_BLK_STAT, 0x0000000c +.set CYVAL_UDB_P_U_OUT5_F1_BLK_STAT, 0x0000000d +.set CYVAL_UDB_P_U_OUT5_F0_BUS_STAT, 0x0000000e +.set CYVAL_UDB_P_U_OUT5_F1_BUS_STAT, 0x0000000f +.set CYREG_UDB_P0_U0_CFG8, 0x400f3048 +.set CYFLD_UDB_P_U_OUT_SYNC__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_OUT_SYNC__SIZE, 0x00000006 +.set CYVAL_UDB_P_U_OUT_SYNC_REGISTERED, 0x00000000 +.set CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL, 0x00000001 +.set CYFLD_UDB_P_U_NC6__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_NC6__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG9, 0x400f3049 +.set CYFLD_UDB_P_U_AMASK__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_AMASK__SIZE, 0x00000008 +.set CYREG_UDB_P0_U0_CFG10, 0x400f304a +.set CYFLD_UDB_P_U_CMASK0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CMASK0__SIZE, 0x00000008 +.set CYREG_UDB_P0_U0_CFG11, 0x400f304b +.set CYREG_UDB_P0_U0_CFG12, 0x400f304c +.set CYFLD_UDB_P_U_SI_SELA__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_SI_SELA__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELA_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_SI_SELA_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_SI_SELA_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELA_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_SI_SELB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_SI_SELB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELB_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_SI_SELB_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_SI_SELB_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_SI_SELB_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_DEF_SI__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_DEF_SI__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DEF_SI_DEFAULT_0, 0x00000000 +.set CYVAL_UDB_P_U_DEF_SI_DEFAULT_1, 0x00000001 +.set CYFLD_UDB_P_U_AMASK_EN__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_AMASK_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_AMASK_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_AMASK_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CMASK0_EN__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_CMASK0_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CMASK0_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CMASK0_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CMASK1_EN__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_CMASK1_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CMASK1_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CMASK1_EN_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG13, 0x400f304d +.set CYFLD_UDB_P_U_CI_SELA__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CI_SELA__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELA_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_CI_SELA_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_CI_SELA_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELA_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_CI_SELB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CI_SELB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELB_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_CI_SELB_REGISTERED, 0x00000001 +.set CYVAL_UDB_P_U_CI_SELB_ROUTE, 0x00000002 +.set CYVAL_UDB_P_U_CI_SELB_CHAIN, 0x00000003 +.set CYFLD_UDB_P_U_CMP_SELA__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_CMP_SELA__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELA_A1_D1, 0x00000000 +.set CYVAL_UDB_P_U_CMP_SELA_A1_A0, 0x00000001 +.set CYVAL_UDB_P_U_CMP_SELA_A0_D1, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELA_A0_A0, 0x00000003 +.set CYFLD_UDB_P_U_CMP_SELB__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_CMP_SELB__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELB_A1_D1, 0x00000000 +.set CYVAL_UDB_P_U_CMP_SELB_A1_A0, 0x00000001 +.set CYVAL_UDB_P_U_CMP_SELB_A0_D1, 0x00000002 +.set CYVAL_UDB_P_U_CMP_SELB_A0_A0, 0x00000003 +.set CYREG_UDB_P0_U0_CFG14, 0x400f304e +.set CYFLD_UDB_P_U_CHAIN0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CHAIN0__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN0_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN0_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN1__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN1__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN1_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN1_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN_FB__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CHAIN_FB__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN_FB_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN_FB_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_CHAIN_CMSB__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_MSB_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_MSB_SEL__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_MSB_SEL_BIT0, 0x00000000 +.set CYVAL_UDB_P_U_MSB_SEL_BIT1, 0x00000001 +.set CYVAL_UDB_P_U_MSB_SEL_BIT2, 0x00000002 +.set CYVAL_UDB_P_U_MSB_SEL_BIT3, 0x00000003 +.set CYVAL_UDB_P_U_MSB_SEL_BIT4, 0x00000004 +.set CYVAL_UDB_P_U_MSB_SEL_BIT5, 0x00000005 +.set CYVAL_UDB_P_U_MSB_SEL_BIT6, 0x00000006 +.set CYVAL_UDB_P_U_MSB_SEL_BIT7, 0x00000007 +.set CYFLD_UDB_P_U_MSB_EN__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_MSB_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_MSB_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_MSB_EN_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG15, 0x400f304f +.set CYFLD_UDB_P_U_F0_INSEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_F0_INSEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_F0_INSEL_INPUT, 0x00000000 +.set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0, 0x00000001 +.set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1, 0x00000002 +.set CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU, 0x00000003 +.set CYFLD_UDB_P_U_F1_INSEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_F1_INSEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_F1_INSEL_INPUT, 0x00000000 +.set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0, 0x00000001 +.set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1, 0x00000002 +.set CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU, 0x00000003 +.set CYFLD_UDB_P_U_MSB_SI__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_MSB_SI__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_MSB_SI_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_MSB_SI_MSB, 0x00000001 +.set CYFLD_UDB_P_U_PI_DYN__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_PI_DYN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PI_DYN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_PI_DYN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_SHIFT_SEL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_SHIFT_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB, 0x00000000 +.set CYVAL_UDB_P_U_SHIFT_SEL_SOR, 0x00000001 +.set CYFLD_UDB_P_U_PI_SEL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PI_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PI_SEL_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_PI_SEL_PARALLEL, 0x00000001 +.set CYREG_UDB_P0_U0_CFG16, 0x400f3050 +.set CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_WRK16_CONCAT__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT, 0x00000000 +.set CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE, 0x00000001 +.set CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_EXT_CRCPRS__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL, 0x00000000 +.set CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_FIFO_ASYNC__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_EDGE__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_FIFO_EDGE__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_EDGE_LEVEL, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_EDGE_EDGE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_CAP__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_FIFO_CAP__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_CAP_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_CAP_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_FAST__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_FIFO_FAST__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_FAST_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_FAST_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_F0_CK_INV__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_F0_CK_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F0_CK_INV_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_F0_CK_INV_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_F1_CK_INV__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_F1_CK_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F1_CK_INV_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_F1_CK_INV_INVERT, 0x00000001 +.set CYREG_UDB_P0_U0_CFG17, 0x400f3051 +.set CYFLD_UDB_P_U_F0_DYN__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_F0_DYN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F0_DYN_STATIC, 0x00000000 +.set CYVAL_UDB_P_U_F0_DYN_DYNAMIC, 0x00000001 +.set CYFLD_UDB_P_U_F1_DYN__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_F1_DYN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_F1_DYN_STATIC, 0x00000000 +.set CYVAL_UDB_P_U_F1_DYN_DYNAMIC, 0x00000001 +.set CYFLD_UDB_P_U_NC2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_NC2__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG18, 0x400f3052 +.set CYFLD_UDB_P_U_CTL_MD0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CTL_MD0__SIZE, 0x00000008 +.set CYVAL_UDB_P_U_CTL_MD0_DIRECT, 0x00000000 +.set CYVAL_UDB_P_U_CTL_MD0_SYNC, 0x00000001 +.set CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC, 0x00000002 +.set CYVAL_UDB_P_U_CTL_MD0_PULSE, 0x00000003 +.set CYREG_UDB_P0_U0_CFG19, 0x400f3053 +.set CYFLD_UDB_P_U_CTL_MD1__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CTL_MD1__SIZE, 0x00000008 +.set CYVAL_UDB_P_U_CTL_MD1_DIRECT, 0x00000000 +.set CYVAL_UDB_P_U_CTL_MD1_SYNC, 0x00000001 +.set CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC, 0x00000002 +.set CYVAL_UDB_P_U_CTL_MD1_PULSE, 0x00000003 +.set CYREG_UDB_P0_U0_CFG20, 0x400f3054 +.set CYFLD_UDB_P_U_STAT_MD__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_STAT_MD__SIZE, 0x00000008 +.set CYREG_UDB_P0_U0_CFG21, 0x400f3055 +.set CYFLD_UDB_P_U_NC0__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_NC0__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG22, 0x400f3056 +.set CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_SC_OUT_CTL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL, 0x00000000 +.set CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL, 0x00000001 +.set CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER, 0x00000002 +.set CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED, 0x00000003 +.set CYFLD_UDB_P_U_SC_INT_MD__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_SC_INT_MD__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_INT_MD_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_SC_INT_MD_INT_MODE, 0x00000001 +.set CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_SC_SYNC_MD__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL, 0x00000000 +.set CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE, 0x00000001 +.set CYFLD_UDB_P_U_SC_EXT_RES__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_SC_EXT_RES__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_EXT_RES_DISABLED, 0x00000000 +.set CYVAL_UDB_P_U_SC_EXT_RES_ENABLED, 0x00000001 +.set CYREG_UDB_P0_U0_CFG23, 0x400f3057 +.set CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CNT_LD_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CNT_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4, 0x00000000 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5, 0x00000001 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6, 0x00000002 +.set CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO, 0x00000003 +.set CYFLD_UDB_P_U_ROUTE_LD__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_ROUTE_LD__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ROUTE_LD_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_ROUTE_LD_ROUTED, 0x00000001 +.set CYFLD_UDB_P_U_ROUTE_EN__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_ROUTE_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ROUTE_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_ROUTE_EN_ROUTED, 0x00000001 +.set CYFLD_UDB_P_U_ALT_CNT__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_ALT_CNT__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE, 0x00000000 +.set CYVAL_UDB_P_U_ALT_CNT_ALT_MODE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG24, 0x400f3058 +.set CYFLD_UDB_P_U_RC_EN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RC_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_RC_EN_MODE__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_RC_EN_MODE__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_MODE_OFF, 0x00000000 +.set CYVAL_UDB_P_U_RC_EN_MODE_ON, 0x00000001 +.set CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE, 0x00000002 +.set CYVAL_UDB_P_U_RC_EN_MODE_LEVEL, 0x00000003 +.set CYFLD_UDB_P_U_RC_EN_INV__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_RC_EN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_RC_EN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_RC_EN_INV_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_RC_INV__OFFSET, 0x00000005 +.set CYFLD_UDB_P_U_RC_INV__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_RC_INV_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_RC_INV_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE, 0x00000001 +.set CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_RC_RES_SEL1__SIZE, 0x00000001 +.set CYREG_UDB_P0_U0_CFG25, 0x400f3059 +.set CYREG_UDB_P0_U0_CFG26, 0x400f305a +.set CYREG_UDB_P0_U0_CFG27, 0x400f305b +.set CYREG_UDB_P0_U0_CFG28, 0x400f305c +.set CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK, 0x00000009 +.set CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK, 0x00000009 +.set CYREG_UDB_P0_U0_CFG29, 0x400f305d +.set CYFLD_UDB_P_U_DP_CK_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_DP_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_DP_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK, 0x00000009 +.set CYFLD_UDB_P_U_SC_CK_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_SC_CK_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_P_U_SC_CK_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK, 0x00000008 +.set CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK, 0x00000009 +.set CYREG_UDB_P0_U0_CFG30, 0x400f305e +.set CYFLD_UDB_P_U_RES_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_RES_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_RES_SEL_RC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_RES_POL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_RES_POL_NEGATED, 0x00000000 +.set CYVAL_UDB_P_U_RES_POL_ASSERTED, 0x00000001 +.set CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_GUDB_WR__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_GUDB_WR__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_GUDB_WR_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_GUDB_WR_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_DP_RES_POL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_DP_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_DP_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_DP_RES_POL_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_SC_RES_POL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_SC_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SC_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_SC_RES_POL_INVERT, 0x00000001 +.set CYREG_UDB_P0_U0_CFG31, 0x400f305f +.set CYFLD_UDB_P_U_ALT_RES__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_ALT_RES__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_ALT_RES_COMPATIBLE, 0x00000000 +.set CYVAL_UDB_P_U_ALT_RES_ALTERNATE, 0x00000001 +.set CYFLD_UDB_P_U_EXT_SYNC__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_EXT_SYNC__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EXT_SYNC_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_EXT_SYNC_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_EN_RES_STAT__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_EN_RES_STAT__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EN_RES_STAT_NEGATED, 0x00000000 +.set CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED, 0x00000001 +.set CYFLD_UDB_P_U_EN_RES_DP__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_EN_RES_DP__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_EN_RES_DP_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_EN_RES_DP_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_EXT_CK_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0, 0x00000000 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1, 0x00000001 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2, 0x00000002 +.set CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3, 0x00000003 +.set CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_PLD0_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD0_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD0_RES_POL_INVERT, 0x00000001 +.set CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET, 0x00000007 +.set CYFLD_UDB_P_U_PLD1_RES_POL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_PLD1_RES_POL_NOINV, 0x00000000 +.set CYVAL_UDB_P_U_PLD1_RES_POL_INVERT, 0x00000001 +.set CYREG_UDB_P0_U0_DCFG0, 0x400f3060 +.set CYFLD_UDB_P_U_CMP_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_P_U_CMP_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CMP_SEL_CFG_A, 0x00000000 +.set CYVAL_UDB_P_U_CMP_SEL_CFG_B, 0x00000001 +.set CYFLD_UDB_P_U_SI_SEL__OFFSET, 0x00000001 +.set CYFLD_UDB_P_U_SI_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SI_SEL_CFG_A, 0x00000000 +.set CYVAL_UDB_P_U_SI_SEL_CFG_B, 0x00000001 +.set CYFLD_UDB_P_U_CI_SEL__OFFSET, 0x00000002 +.set CYFLD_UDB_P_U_CI_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CI_SEL_CFG_A, 0x00000000 +.set CYVAL_UDB_P_U_CI_SEL_CFG_B, 0x00000001 +.set CYFLD_UDB_P_U_CFB_EN__OFFSET, 0x00000003 +.set CYFLD_UDB_P_U_CFB_EN__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_CFB_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_P_U_CFB_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_P_U_A1_WR_SRC__OFFSET, 0x00000004 +.set CYFLD_UDB_P_U_A1_WR_SRC__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE, 0x00000000 +.set CYVAL_UDB_P_U_A1_WR_SRC_ALU, 0x00000001 +.set CYVAL_UDB_P_U_A1_WR_SRC_D1, 0x00000002 +.set CYVAL_UDB_P_U_A1_WR_SRC_F1, 0x00000003 +.set CYFLD_UDB_P_U_A0_WR_SRC__OFFSET, 0x00000006 +.set CYFLD_UDB_P_U_A0_WR_SRC__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE, 0x00000000 +.set CYVAL_UDB_P_U_A0_WR_SRC_ALU, 0x00000001 +.set CYVAL_UDB_P_U_A0_WR_SRC_D0, 0x00000002 +.set CYVAL_UDB_P_U_A0_WR_SRC_F0, 0x00000003 +.set CYFLD_UDB_P_U_SHIFT__OFFSET, 0x00000008 +.set CYFLD_UDB_P_U_SHIFT__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SHIFT_NOSHIFT, 0x00000000 +.set CYVAL_UDB_P_U_SHIFT_LEFT, 0x00000001 +.set CYVAL_UDB_P_U_SHIFT_RIGHT, 0x00000002 +.set CYVAL_UDB_P_U_SHIFT_SWAP, 0x00000003 +.set CYFLD_UDB_P_U_SRC_B__OFFSET, 0x0000000a +.set CYFLD_UDB_P_U_SRC_B__SIZE, 0x00000002 +.set CYVAL_UDB_P_U_SRC_B_D0, 0x00000000 +.set CYVAL_UDB_P_U_SRC_B_D1, 0x00000001 +.set CYVAL_UDB_P_U_SRC_B_A0, 0x00000002 +.set CYVAL_UDB_P_U_SRC_B_A1, 0x00000003 +.set CYFLD_UDB_P_U_SRC_A__OFFSET, 0x0000000c +.set CYFLD_UDB_P_U_SRC_A__SIZE, 0x00000001 +.set CYVAL_UDB_P_U_SRC_A_A0, 0x00000000 +.set CYVAL_UDB_P_U_SRC_A_A1, 0x00000001 +.set CYFLD_UDB_P_U_FUNC__OFFSET, 0x0000000d +.set CYFLD_UDB_P_U_FUNC__SIZE, 0x00000003 +.set CYVAL_UDB_P_U_FUNC_PASS, 0x00000000 +.set CYVAL_UDB_P_U_FUNC_INC_A, 0x00000001 +.set CYVAL_UDB_P_U_FUNC_DEC_A, 0x00000002 +.set CYVAL_UDB_P_U_FUNC_ADD, 0x00000003 +.set CYVAL_UDB_P_U_FUNC_SUB, 0x00000004 +.set CYVAL_UDB_P_U_FUNC_XOR, 0x00000005 +.set CYVAL_UDB_P_U_FUNC_AND, 0x00000006 +.set CYVAL_UDB_P_U_FUNC_OR, 0x00000007 +.set CYREG_UDB_P0_U0_DCFG1, 0x400f3062 +.set CYREG_UDB_P0_U0_DCFG2, 0x400f3064 +.set CYREG_UDB_P0_U0_DCFG3, 0x400f3066 +.set CYREG_UDB_P0_U0_DCFG4, 0x400f3068 +.set CYREG_UDB_P0_U0_DCFG5, 0x400f306a +.set CYREG_UDB_P0_U0_DCFG6, 0x400f306c +.set CYREG_UDB_P0_U0_DCFG7, 0x400f306e +.set CYDEV_UDB_P0_U1_BASE, 0x400f3080 +.set CYDEV_UDB_P0_U1_SIZE, 0x00000080 +.set CYREG_UDB_P0_U1_PLD_IT0, 0x400f3080 +.set CYREG_UDB_P0_U1_PLD_IT1, 0x400f3084 +.set CYREG_UDB_P0_U1_PLD_IT2, 0x400f3088 +.set CYREG_UDB_P0_U1_PLD_IT3, 0x400f308c +.set CYREG_UDB_P0_U1_PLD_IT4, 0x400f3090 +.set CYREG_UDB_P0_U1_PLD_IT5, 0x400f3094 +.set CYREG_UDB_P0_U1_PLD_IT6, 0x400f3098 +.set CYREG_UDB_P0_U1_PLD_IT7, 0x400f309c +.set CYREG_UDB_P0_U1_PLD_IT8, 0x400f30a0 +.set CYREG_UDB_P0_U1_PLD_IT9, 0x400f30a4 +.set CYREG_UDB_P0_U1_PLD_IT10, 0x400f30a8 +.set CYREG_UDB_P0_U1_PLD_IT11, 0x400f30ac +.set CYREG_UDB_P0_U1_PLD_ORT0, 0x400f30b0 +.set CYREG_UDB_P0_U1_PLD_ORT1, 0x400f30b2 +.set CYREG_UDB_P0_U1_PLD_ORT2, 0x400f30b4 +.set CYREG_UDB_P0_U1_PLD_ORT3, 0x400f30b6 +.set CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST, 0x400f30b8 +.set CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB, 0x400f30ba +.set CYREG_UDB_P0_U1_PLD_MC_SET_RESET, 0x400f30bc +.set CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS, 0x400f30be +.set CYREG_UDB_P0_U1_CFG0, 0x400f30c0 +.set CYREG_UDB_P0_U1_CFG1, 0x400f30c1 +.set CYREG_UDB_P0_U1_CFG2, 0x400f30c2 +.set CYREG_UDB_P0_U1_CFG3, 0x400f30c3 +.set CYREG_UDB_P0_U1_CFG4, 0x400f30c4 +.set CYREG_UDB_P0_U1_CFG5, 0x400f30c5 +.set CYREG_UDB_P0_U1_CFG6, 0x400f30c6 +.set CYREG_UDB_P0_U1_CFG7, 0x400f30c7 +.set CYREG_UDB_P0_U1_CFG8, 0x400f30c8 +.set CYREG_UDB_P0_U1_CFG9, 0x400f30c9 +.set CYREG_UDB_P0_U1_CFG10, 0x400f30ca +.set CYREG_UDB_P0_U1_CFG11, 0x400f30cb +.set CYREG_UDB_P0_U1_CFG12, 0x400f30cc +.set CYREG_UDB_P0_U1_CFG13, 0x400f30cd +.set CYREG_UDB_P0_U1_CFG14, 0x400f30ce +.set CYREG_UDB_P0_U1_CFG15, 0x400f30cf +.set CYREG_UDB_P0_U1_CFG16, 0x400f30d0 +.set CYREG_UDB_P0_U1_CFG17, 0x400f30d1 +.set CYREG_UDB_P0_U1_CFG18, 0x400f30d2 +.set CYREG_UDB_P0_U1_CFG19, 0x400f30d3 +.set CYREG_UDB_P0_U1_CFG20, 0x400f30d4 +.set CYREG_UDB_P0_U1_CFG21, 0x400f30d5 +.set CYREG_UDB_P0_U1_CFG22, 0x400f30d6 +.set CYREG_UDB_P0_U1_CFG23, 0x400f30d7 +.set CYREG_UDB_P0_U1_CFG24, 0x400f30d8 +.set CYREG_UDB_P0_U1_CFG25, 0x400f30d9 +.set CYREG_UDB_P0_U1_CFG26, 0x400f30da +.set CYREG_UDB_P0_U1_CFG27, 0x400f30db +.set CYREG_UDB_P0_U1_CFG28, 0x400f30dc +.set CYREG_UDB_P0_U1_CFG29, 0x400f30dd +.set CYREG_UDB_P0_U1_CFG30, 0x400f30de +.set CYREG_UDB_P0_U1_CFG31, 0x400f30df +.set CYREG_UDB_P0_U1_DCFG0, 0x400f30e0 +.set CYREG_UDB_P0_U1_DCFG1, 0x400f30e2 +.set CYREG_UDB_P0_U1_DCFG2, 0x400f30e4 +.set CYREG_UDB_P0_U1_DCFG3, 0x400f30e6 +.set CYREG_UDB_P0_U1_DCFG4, 0x400f30e8 +.set CYREG_UDB_P0_U1_DCFG5, 0x400f30ea +.set CYREG_UDB_P0_U1_DCFG6, 0x400f30ec +.set CYREG_UDB_P0_U1_DCFG7, 0x400f30ee +.set CYDEV_UDB_P0_ROUTE_BASE, 0x400f3100 +.set CYDEV_UDB_P0_ROUTE_SIZE, 0x00000100 +.set CYREG_UDB_P0_ROUTE_HC0, 0x400f3100 +.set CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_P0_ROUTE_HC1, 0x400f3101 +.set CYREG_UDB_P0_ROUTE_HC2, 0x400f3102 +.set CYREG_UDB_P0_ROUTE_HC3, 0x400f3103 +.set CYREG_UDB_P0_ROUTE_HC4, 0x400f3104 +.set CYREG_UDB_P0_ROUTE_HC5, 0x400f3105 +.set CYREG_UDB_P0_ROUTE_HC6, 0x400f3106 +.set CYREG_UDB_P0_ROUTE_HC7, 0x400f3107 +.set CYREG_UDB_P0_ROUTE_HC8, 0x400f3108 +.set CYREG_UDB_P0_ROUTE_HC9, 0x400f3109 +.set CYREG_UDB_P0_ROUTE_HC10, 0x400f310a +.set CYREG_UDB_P0_ROUTE_HC11, 0x400f310b +.set CYREG_UDB_P0_ROUTE_HC12, 0x400f310c +.set CYREG_UDB_P0_ROUTE_HC13, 0x400f310d +.set CYREG_UDB_P0_ROUTE_HC14, 0x400f310e +.set CYREG_UDB_P0_ROUTE_HC15, 0x400f310f +.set CYREG_UDB_P0_ROUTE_HC16, 0x400f3110 +.set CYREG_UDB_P0_ROUTE_HC17, 0x400f3111 +.set CYREG_UDB_P0_ROUTE_HC18, 0x400f3112 +.set CYREG_UDB_P0_ROUTE_HC19, 0x400f3113 +.set CYREG_UDB_P0_ROUTE_HC20, 0x400f3114 +.set CYREG_UDB_P0_ROUTE_HC21, 0x400f3115 +.set CYREG_UDB_P0_ROUTE_HC22, 0x400f3116 +.set CYREG_UDB_P0_ROUTE_HC23, 0x400f3117 +.set CYREG_UDB_P0_ROUTE_HC24, 0x400f3118 +.set CYREG_UDB_P0_ROUTE_HC25, 0x400f3119 +.set CYREG_UDB_P0_ROUTE_HC26, 0x400f311a +.set CYREG_UDB_P0_ROUTE_HC27, 0x400f311b +.set CYREG_UDB_P0_ROUTE_HC28, 0x400f311c +.set CYREG_UDB_P0_ROUTE_HC29, 0x400f311d +.set CYREG_UDB_P0_ROUTE_HC30, 0x400f311e +.set CYREG_UDB_P0_ROUTE_HC31, 0x400f311f +.set CYREG_UDB_P0_ROUTE_HC32, 0x400f3120 +.set CYREG_UDB_P0_ROUTE_HC33, 0x400f3121 +.set CYREG_UDB_P0_ROUTE_HC34, 0x400f3122 +.set CYREG_UDB_P0_ROUTE_HC35, 0x400f3123 +.set CYREG_UDB_P0_ROUTE_HC36, 0x400f3124 +.set CYREG_UDB_P0_ROUTE_HC37, 0x400f3125 +.set CYREG_UDB_P0_ROUTE_HC38, 0x400f3126 +.set CYREG_UDB_P0_ROUTE_HC39, 0x400f3127 +.set CYREG_UDB_P0_ROUTE_HC40, 0x400f3128 +.set CYREG_UDB_P0_ROUTE_HC41, 0x400f3129 +.set CYREG_UDB_P0_ROUTE_HC42, 0x400f312a +.set CYREG_UDB_P0_ROUTE_HC43, 0x400f312b +.set CYREG_UDB_P0_ROUTE_HC44, 0x400f312c +.set CYREG_UDB_P0_ROUTE_HC45, 0x400f312d +.set CYREG_UDB_P0_ROUTE_HC46, 0x400f312e +.set CYREG_UDB_P0_ROUTE_HC47, 0x400f312f +.set CYREG_UDB_P0_ROUTE_HC48, 0x400f3130 +.set CYREG_UDB_P0_ROUTE_HC49, 0x400f3131 +.set CYREG_UDB_P0_ROUTE_HC50, 0x400f3132 +.set CYREG_UDB_P0_ROUTE_HC51, 0x400f3133 +.set CYREG_UDB_P0_ROUTE_HC52, 0x400f3134 +.set CYREG_UDB_P0_ROUTE_HC53, 0x400f3135 +.set CYREG_UDB_P0_ROUTE_HC54, 0x400f3136 +.set CYREG_UDB_P0_ROUTE_HC55, 0x400f3137 +.set CYREG_UDB_P0_ROUTE_HC56, 0x400f3138 +.set CYREG_UDB_P0_ROUTE_HC57, 0x400f3139 +.set CYREG_UDB_P0_ROUTE_HC58, 0x400f313a +.set CYREG_UDB_P0_ROUTE_HC59, 0x400f313b +.set CYREG_UDB_P0_ROUTE_HC60, 0x400f313c +.set CYREG_UDB_P0_ROUTE_HC61, 0x400f313d +.set CYREG_UDB_P0_ROUTE_HC62, 0x400f313e +.set CYREG_UDB_P0_ROUTE_HC63, 0x400f313f +.set CYREG_UDB_P0_ROUTE_HC64, 0x400f3140 +.set CYREG_UDB_P0_ROUTE_HC65, 0x400f3141 +.set CYREG_UDB_P0_ROUTE_HC66, 0x400f3142 +.set CYREG_UDB_P0_ROUTE_HC67, 0x400f3143 +.set CYREG_UDB_P0_ROUTE_HC68, 0x400f3144 +.set CYREG_UDB_P0_ROUTE_HC69, 0x400f3145 +.set CYREG_UDB_P0_ROUTE_HC70, 0x400f3146 +.set CYREG_UDB_P0_ROUTE_HC71, 0x400f3147 +.set CYREG_UDB_P0_ROUTE_HC72, 0x400f3148 +.set CYREG_UDB_P0_ROUTE_HC73, 0x400f3149 +.set CYREG_UDB_P0_ROUTE_HC74, 0x400f314a +.set CYREG_UDB_P0_ROUTE_HC75, 0x400f314b +.set CYREG_UDB_P0_ROUTE_HC76, 0x400f314c +.set CYREG_UDB_P0_ROUTE_HC77, 0x400f314d +.set CYREG_UDB_P0_ROUTE_HC78, 0x400f314e +.set CYREG_UDB_P0_ROUTE_HC79, 0x400f314f +.set CYREG_UDB_P0_ROUTE_HC80, 0x400f3150 +.set CYREG_UDB_P0_ROUTE_HC81, 0x400f3151 +.set CYREG_UDB_P0_ROUTE_HC82, 0x400f3152 +.set CYREG_UDB_P0_ROUTE_HC83, 0x400f3153 +.set CYREG_UDB_P0_ROUTE_HC84, 0x400f3154 +.set CYREG_UDB_P0_ROUTE_HC85, 0x400f3155 +.set CYREG_UDB_P0_ROUTE_HC86, 0x400f3156 +.set CYREG_UDB_P0_ROUTE_HC87, 0x400f3157 +.set CYREG_UDB_P0_ROUTE_HC88, 0x400f3158 +.set CYREG_UDB_P0_ROUTE_HC89, 0x400f3159 +.set CYREG_UDB_P0_ROUTE_HC90, 0x400f315a +.set CYREG_UDB_P0_ROUTE_HC91, 0x400f315b +.set CYREG_UDB_P0_ROUTE_HC92, 0x400f315c +.set CYREG_UDB_P0_ROUTE_HC93, 0x400f315d +.set CYREG_UDB_P0_ROUTE_HC94, 0x400f315e +.set CYREG_UDB_P0_ROUTE_HC95, 0x400f315f +.set CYREG_UDB_P0_ROUTE_HC96, 0x400f3160 +.set CYREG_UDB_P0_ROUTE_HC97, 0x400f3161 +.set CYREG_UDB_P0_ROUTE_HC98, 0x400f3162 +.set CYREG_UDB_P0_ROUTE_HC99, 0x400f3163 +.set CYREG_UDB_P0_ROUTE_HC100, 0x400f3164 +.set CYREG_UDB_P0_ROUTE_HC101, 0x400f3165 +.set CYREG_UDB_P0_ROUTE_HC102, 0x400f3166 +.set CYREG_UDB_P0_ROUTE_HC103, 0x400f3167 +.set CYREG_UDB_P0_ROUTE_HC104, 0x400f3168 +.set CYREG_UDB_P0_ROUTE_HC105, 0x400f3169 +.set CYREG_UDB_P0_ROUTE_HC106, 0x400f316a +.set CYREG_UDB_P0_ROUTE_HC107, 0x400f316b +.set CYREG_UDB_P0_ROUTE_HC108, 0x400f316c +.set CYREG_UDB_P0_ROUTE_HC109, 0x400f316d +.set CYREG_UDB_P0_ROUTE_HC110, 0x400f316e +.set CYREG_UDB_P0_ROUTE_HC111, 0x400f316f +.set CYREG_UDB_P0_ROUTE_HC112, 0x400f3170 +.set CYREG_UDB_P0_ROUTE_HC113, 0x400f3171 +.set CYREG_UDB_P0_ROUTE_HC114, 0x400f3172 +.set CYREG_UDB_P0_ROUTE_HC115, 0x400f3173 +.set CYREG_UDB_P0_ROUTE_HC116, 0x400f3174 +.set CYREG_UDB_P0_ROUTE_HC117, 0x400f3175 +.set CYREG_UDB_P0_ROUTE_HC118, 0x400f3176 +.set CYREG_UDB_P0_ROUTE_HC119, 0x400f3177 +.set CYREG_UDB_P0_ROUTE_HC120, 0x400f3178 +.set CYREG_UDB_P0_ROUTE_HC121, 0x400f3179 +.set CYREG_UDB_P0_ROUTE_HC122, 0x400f317a +.set CYREG_UDB_P0_ROUTE_HC123, 0x400f317b +.set CYREG_UDB_P0_ROUTE_HC124, 0x400f317c +.set CYREG_UDB_P0_ROUTE_HC125, 0x400f317d +.set CYREG_UDB_P0_ROUTE_HC126, 0x400f317e +.set CYREG_UDB_P0_ROUTE_HC127, 0x400f317f +.set CYREG_UDB_P0_ROUTE_HV_L0, 0x400f3180 +.set CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_P0_ROUTE_HV_L1, 0x400f3181 +.set CYREG_UDB_P0_ROUTE_HV_L2, 0x400f3182 +.set CYREG_UDB_P0_ROUTE_HV_L3, 0x400f3183 +.set CYREG_UDB_P0_ROUTE_HV_L4, 0x400f3184 +.set CYREG_UDB_P0_ROUTE_HV_L5, 0x400f3185 +.set CYREG_UDB_P0_ROUTE_HV_L6, 0x400f3186 +.set CYREG_UDB_P0_ROUTE_HV_L7, 0x400f3187 +.set CYREG_UDB_P0_ROUTE_HV_L8, 0x400f3188 +.set CYREG_UDB_P0_ROUTE_HV_L9, 0x400f3189 +.set CYREG_UDB_P0_ROUTE_HV_L10, 0x400f318a +.set CYREG_UDB_P0_ROUTE_HV_L11, 0x400f318b +.set CYREG_UDB_P0_ROUTE_HV_L12, 0x400f318c +.set CYREG_UDB_P0_ROUTE_HV_L13, 0x400f318d +.set CYREG_UDB_P0_ROUTE_HV_L14, 0x400f318e +.set CYREG_UDB_P0_ROUTE_HV_L15, 0x400f318f +.set CYREG_UDB_P0_ROUTE_HS0, 0x400f3190 +.set CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_P0_ROUTE_HS1, 0x400f3191 +.set CYREG_UDB_P0_ROUTE_HS2, 0x400f3192 +.set CYREG_UDB_P0_ROUTE_HS3, 0x400f3193 +.set CYREG_UDB_P0_ROUTE_HS4, 0x400f3194 +.set CYREG_UDB_P0_ROUTE_HS5, 0x400f3195 +.set CYREG_UDB_P0_ROUTE_HS6, 0x400f3196 +.set CYREG_UDB_P0_ROUTE_HS7, 0x400f3197 +.set CYREG_UDB_P0_ROUTE_HS8, 0x400f3198 +.set CYREG_UDB_P0_ROUTE_HS9, 0x400f3199 +.set CYREG_UDB_P0_ROUTE_HS10, 0x400f319a +.set CYREG_UDB_P0_ROUTE_HS11, 0x400f319b +.set CYREG_UDB_P0_ROUTE_HS12, 0x400f319c +.set CYREG_UDB_P0_ROUTE_HS13, 0x400f319d +.set CYREG_UDB_P0_ROUTE_HS14, 0x400f319e +.set CYREG_UDB_P0_ROUTE_HS15, 0x400f319f +.set CYREG_UDB_P0_ROUTE_HS16, 0x400f31a0 +.set CYREG_UDB_P0_ROUTE_HS17, 0x400f31a1 +.set CYREG_UDB_P0_ROUTE_HS18, 0x400f31a2 +.set CYREG_UDB_P0_ROUTE_HS19, 0x400f31a3 +.set CYREG_UDB_P0_ROUTE_HS20, 0x400f31a4 +.set CYREG_UDB_P0_ROUTE_HS21, 0x400f31a5 +.set CYREG_UDB_P0_ROUTE_HS22, 0x400f31a6 +.set CYREG_UDB_P0_ROUTE_HS23, 0x400f31a7 +.set CYREG_UDB_P0_ROUTE_HV_R0, 0x400f31a8 +.set CYREG_UDB_P0_ROUTE_HV_R1, 0x400f31a9 +.set CYREG_UDB_P0_ROUTE_HV_R2, 0x400f31aa +.set CYREG_UDB_P0_ROUTE_HV_R3, 0x400f31ab +.set CYREG_UDB_P0_ROUTE_HV_R4, 0x400f31ac +.set CYREG_UDB_P0_ROUTE_HV_R5, 0x400f31ad +.set CYREG_UDB_P0_ROUTE_HV_R6, 0x400f31ae +.set CYREG_UDB_P0_ROUTE_HV_R7, 0x400f31af +.set CYREG_UDB_P0_ROUTE_HV_R8, 0x400f31b0 +.set CYREG_UDB_P0_ROUTE_HV_R9, 0x400f31b1 +.set CYREG_UDB_P0_ROUTE_HV_R10, 0x400f31b2 +.set CYREG_UDB_P0_ROUTE_HV_R11, 0x400f31b3 +.set CYREG_UDB_P0_ROUTE_HV_R12, 0x400f31b4 +.set CYREG_UDB_P0_ROUTE_HV_R13, 0x400f31b5 +.set CYREG_UDB_P0_ROUTE_HV_R14, 0x400f31b6 +.set CYREG_UDB_P0_ROUTE_HV_R15, 0x400f31b7 +.set CYREG_UDB_P0_ROUTE_PLD0IN0, 0x400f31c0 +.set CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_PI_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_P_ROUTE_PI_BOT__SIZE, 0x00000004 +.set CYREG_UDB_P0_ROUTE_PLD0IN1, 0x400f31c2 +.set CYREG_UDB_P0_ROUTE_PLD0IN2, 0x400f31c4 +.set CYREG_UDB_P0_ROUTE_PLD1IN0, 0x400f31ca +.set CYREG_UDB_P0_ROUTE_PLD1IN1, 0x400f31cc +.set CYREG_UDB_P0_ROUTE_PLD1IN2, 0x400f31ce +.set CYREG_UDB_P0_ROUTE_DPIN0, 0x400f31d0 +.set CYREG_UDB_P0_ROUTE_DPIN1, 0x400f31d2 +.set CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET, 0x00000002 +.set CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE, 0x00000002 +.set CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET, 0x00000004 +.set CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE, 0x00000002 +.set CYREG_UDB_P0_ROUTE_SCIN, 0x400f31d6 +.set CYREG_UDB_P0_ROUTE_SCIOIN, 0x400f31d8 +.set CYREG_UDB_P0_ROUTE_RCIN, 0x400f31de +.set CYREG_UDB_P0_ROUTE_VS0, 0x400f31e0 +.set CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_P_ROUTE_VS_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_P_ROUTE_VS_BOT__SIZE, 0x00000004 +.set CYREG_UDB_P0_ROUTE_VS1, 0x400f31e2 +.set CYREG_UDB_P0_ROUTE_VS2, 0x400f31e4 +.set CYREG_UDB_P0_ROUTE_VS3, 0x400f31e6 +.set CYREG_UDB_P0_ROUTE_VS4, 0x400f31e8 +.set CYREG_UDB_P0_ROUTE_VS5, 0x400f31ea +.set CYREG_UDB_P0_ROUTE_VS6, 0x400f31ec +.set CYREG_UDB_P0_ROUTE_VS7, 0x400f31ee +.set CYDEV_UDB_P1_BASE, 0x400f3200 +.set CYDEV_UDB_P1_SIZE, 0x00000200 +.set CYDEV_UDB_P1_U0_BASE, 0x400f3200 +.set CYDEV_UDB_P1_U0_SIZE, 0x00000080 +.set CYREG_UDB_P1_U0_PLD_IT0, 0x400f3200 +.set CYREG_UDB_P1_U0_PLD_IT1, 0x400f3204 +.set CYREG_UDB_P1_U0_PLD_IT2, 0x400f3208 +.set CYREG_UDB_P1_U0_PLD_IT3, 0x400f320c +.set CYREG_UDB_P1_U0_PLD_IT4, 0x400f3210 +.set CYREG_UDB_P1_U0_PLD_IT5, 0x400f3214 +.set CYREG_UDB_P1_U0_PLD_IT6, 0x400f3218 +.set CYREG_UDB_P1_U0_PLD_IT7, 0x400f321c +.set CYREG_UDB_P1_U0_PLD_IT8, 0x400f3220 +.set CYREG_UDB_P1_U0_PLD_IT9, 0x400f3224 +.set CYREG_UDB_P1_U0_PLD_IT10, 0x400f3228 +.set CYREG_UDB_P1_U0_PLD_IT11, 0x400f322c +.set CYREG_UDB_P1_U0_PLD_ORT0, 0x400f3230 +.set CYREG_UDB_P1_U0_PLD_ORT1, 0x400f3232 +.set CYREG_UDB_P1_U0_PLD_ORT2, 0x400f3234 +.set CYREG_UDB_P1_U0_PLD_ORT3, 0x400f3236 +.set CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST, 0x400f3238 +.set CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB, 0x400f323a +.set CYREG_UDB_P1_U0_PLD_MC_SET_RESET, 0x400f323c +.set CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS, 0x400f323e +.set CYREG_UDB_P1_U0_CFG0, 0x400f3240 +.set CYREG_UDB_P1_U0_CFG1, 0x400f3241 +.set CYREG_UDB_P1_U0_CFG2, 0x400f3242 +.set CYREG_UDB_P1_U0_CFG3, 0x400f3243 +.set CYREG_UDB_P1_U0_CFG4, 0x400f3244 +.set CYREG_UDB_P1_U0_CFG5, 0x400f3245 +.set CYREG_UDB_P1_U0_CFG6, 0x400f3246 +.set CYREG_UDB_P1_U0_CFG7, 0x400f3247 +.set CYREG_UDB_P1_U0_CFG8, 0x400f3248 +.set CYREG_UDB_P1_U0_CFG9, 0x400f3249 +.set CYREG_UDB_P1_U0_CFG10, 0x400f324a +.set CYREG_UDB_P1_U0_CFG11, 0x400f324b +.set CYREG_UDB_P1_U0_CFG12, 0x400f324c +.set CYREG_UDB_P1_U0_CFG13, 0x400f324d +.set CYREG_UDB_P1_U0_CFG14, 0x400f324e +.set CYREG_UDB_P1_U0_CFG15, 0x400f324f +.set CYREG_UDB_P1_U0_CFG16, 0x400f3250 +.set CYREG_UDB_P1_U0_CFG17, 0x400f3251 +.set CYREG_UDB_P1_U0_CFG18, 0x400f3252 +.set CYREG_UDB_P1_U0_CFG19, 0x400f3253 +.set CYREG_UDB_P1_U0_CFG20, 0x400f3254 +.set CYREG_UDB_P1_U0_CFG21, 0x400f3255 +.set CYREG_UDB_P1_U0_CFG22, 0x400f3256 +.set CYREG_UDB_P1_U0_CFG23, 0x400f3257 +.set CYREG_UDB_P1_U0_CFG24, 0x400f3258 +.set CYREG_UDB_P1_U0_CFG25, 0x400f3259 +.set CYREG_UDB_P1_U0_CFG26, 0x400f325a +.set CYREG_UDB_P1_U0_CFG27, 0x400f325b +.set CYREG_UDB_P1_U0_CFG28, 0x400f325c +.set CYREG_UDB_P1_U0_CFG29, 0x400f325d +.set CYREG_UDB_P1_U0_CFG30, 0x400f325e +.set CYREG_UDB_P1_U0_CFG31, 0x400f325f +.set CYREG_UDB_P1_U0_DCFG0, 0x400f3260 +.set CYREG_UDB_P1_U0_DCFG1, 0x400f3262 +.set CYREG_UDB_P1_U0_DCFG2, 0x400f3264 +.set CYREG_UDB_P1_U0_DCFG3, 0x400f3266 +.set CYREG_UDB_P1_U0_DCFG4, 0x400f3268 +.set CYREG_UDB_P1_U0_DCFG5, 0x400f326a +.set CYREG_UDB_P1_U0_DCFG6, 0x400f326c +.set CYREG_UDB_P1_U0_DCFG7, 0x400f326e +.set CYDEV_UDB_P1_U1_BASE, 0x400f3280 +.set CYDEV_UDB_P1_U1_SIZE, 0x00000080 +.set CYREG_UDB_P1_U1_PLD_IT0, 0x400f3280 +.set CYREG_UDB_P1_U1_PLD_IT1, 0x400f3284 +.set CYREG_UDB_P1_U1_PLD_IT2, 0x400f3288 +.set CYREG_UDB_P1_U1_PLD_IT3, 0x400f328c +.set CYREG_UDB_P1_U1_PLD_IT4, 0x400f3290 +.set CYREG_UDB_P1_U1_PLD_IT5, 0x400f3294 +.set CYREG_UDB_P1_U1_PLD_IT6, 0x400f3298 +.set CYREG_UDB_P1_U1_PLD_IT7, 0x400f329c +.set CYREG_UDB_P1_U1_PLD_IT8, 0x400f32a0 +.set CYREG_UDB_P1_U1_PLD_IT9, 0x400f32a4 +.set CYREG_UDB_P1_U1_PLD_IT10, 0x400f32a8 +.set CYREG_UDB_P1_U1_PLD_IT11, 0x400f32ac +.set CYREG_UDB_P1_U1_PLD_ORT0, 0x400f32b0 +.set CYREG_UDB_P1_U1_PLD_ORT1, 0x400f32b2 +.set CYREG_UDB_P1_U1_PLD_ORT2, 0x400f32b4 +.set CYREG_UDB_P1_U1_PLD_ORT3, 0x400f32b6 +.set CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST, 0x400f32b8 +.set CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB, 0x400f32ba +.set CYREG_UDB_P1_U1_PLD_MC_SET_RESET, 0x400f32bc +.set CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS, 0x400f32be +.set CYREG_UDB_P1_U1_CFG0, 0x400f32c0 +.set CYREG_UDB_P1_U1_CFG1, 0x400f32c1 +.set CYREG_UDB_P1_U1_CFG2, 0x400f32c2 +.set CYREG_UDB_P1_U1_CFG3, 0x400f32c3 +.set CYREG_UDB_P1_U1_CFG4, 0x400f32c4 +.set CYREG_UDB_P1_U1_CFG5, 0x400f32c5 +.set CYREG_UDB_P1_U1_CFG6, 0x400f32c6 +.set CYREG_UDB_P1_U1_CFG7, 0x400f32c7 +.set CYREG_UDB_P1_U1_CFG8, 0x400f32c8 +.set CYREG_UDB_P1_U1_CFG9, 0x400f32c9 +.set CYREG_UDB_P1_U1_CFG10, 0x400f32ca +.set CYREG_UDB_P1_U1_CFG11, 0x400f32cb +.set CYREG_UDB_P1_U1_CFG12, 0x400f32cc +.set CYREG_UDB_P1_U1_CFG13, 0x400f32cd +.set CYREG_UDB_P1_U1_CFG14, 0x400f32ce +.set CYREG_UDB_P1_U1_CFG15, 0x400f32cf +.set CYREG_UDB_P1_U1_CFG16, 0x400f32d0 +.set CYREG_UDB_P1_U1_CFG17, 0x400f32d1 +.set CYREG_UDB_P1_U1_CFG18, 0x400f32d2 +.set CYREG_UDB_P1_U1_CFG19, 0x400f32d3 +.set CYREG_UDB_P1_U1_CFG20, 0x400f32d4 +.set CYREG_UDB_P1_U1_CFG21, 0x400f32d5 +.set CYREG_UDB_P1_U1_CFG22, 0x400f32d6 +.set CYREG_UDB_P1_U1_CFG23, 0x400f32d7 +.set CYREG_UDB_P1_U1_CFG24, 0x400f32d8 +.set CYREG_UDB_P1_U1_CFG25, 0x400f32d9 +.set CYREG_UDB_P1_U1_CFG26, 0x400f32da +.set CYREG_UDB_P1_U1_CFG27, 0x400f32db +.set CYREG_UDB_P1_U1_CFG28, 0x400f32dc +.set CYREG_UDB_P1_U1_CFG29, 0x400f32dd +.set CYREG_UDB_P1_U1_CFG30, 0x400f32de +.set CYREG_UDB_P1_U1_CFG31, 0x400f32df +.set CYREG_UDB_P1_U1_DCFG0, 0x400f32e0 +.set CYREG_UDB_P1_U1_DCFG1, 0x400f32e2 +.set CYREG_UDB_P1_U1_DCFG2, 0x400f32e4 +.set CYREG_UDB_P1_U1_DCFG3, 0x400f32e6 +.set CYREG_UDB_P1_U1_DCFG4, 0x400f32e8 +.set CYREG_UDB_P1_U1_DCFG5, 0x400f32ea +.set CYREG_UDB_P1_U1_DCFG6, 0x400f32ec +.set CYREG_UDB_P1_U1_DCFG7, 0x400f32ee +.set CYDEV_UDB_P1_ROUTE_BASE, 0x400f3300 +.set CYDEV_UDB_P1_ROUTE_SIZE, 0x00000100 +.set CYREG_UDB_P1_ROUTE_HC0, 0x400f3300 +.set CYREG_UDB_P1_ROUTE_HC1, 0x400f3301 +.set CYREG_UDB_P1_ROUTE_HC2, 0x400f3302 +.set CYREG_UDB_P1_ROUTE_HC3, 0x400f3303 +.set CYREG_UDB_P1_ROUTE_HC4, 0x400f3304 +.set CYREG_UDB_P1_ROUTE_HC5, 0x400f3305 +.set CYREG_UDB_P1_ROUTE_HC6, 0x400f3306 +.set CYREG_UDB_P1_ROUTE_HC7, 0x400f3307 +.set CYREG_UDB_P1_ROUTE_HC8, 0x400f3308 +.set CYREG_UDB_P1_ROUTE_HC9, 0x400f3309 +.set CYREG_UDB_P1_ROUTE_HC10, 0x400f330a +.set CYREG_UDB_P1_ROUTE_HC11, 0x400f330b +.set CYREG_UDB_P1_ROUTE_HC12, 0x400f330c +.set CYREG_UDB_P1_ROUTE_HC13, 0x400f330d +.set CYREG_UDB_P1_ROUTE_HC14, 0x400f330e +.set CYREG_UDB_P1_ROUTE_HC15, 0x400f330f +.set CYREG_UDB_P1_ROUTE_HC16, 0x400f3310 +.set CYREG_UDB_P1_ROUTE_HC17, 0x400f3311 +.set CYREG_UDB_P1_ROUTE_HC18, 0x400f3312 +.set CYREG_UDB_P1_ROUTE_HC19, 0x400f3313 +.set CYREG_UDB_P1_ROUTE_HC20, 0x400f3314 +.set CYREG_UDB_P1_ROUTE_HC21, 0x400f3315 +.set CYREG_UDB_P1_ROUTE_HC22, 0x400f3316 +.set CYREG_UDB_P1_ROUTE_HC23, 0x400f3317 +.set CYREG_UDB_P1_ROUTE_HC24, 0x400f3318 +.set CYREG_UDB_P1_ROUTE_HC25, 0x400f3319 +.set CYREG_UDB_P1_ROUTE_HC26, 0x400f331a +.set CYREG_UDB_P1_ROUTE_HC27, 0x400f331b +.set CYREG_UDB_P1_ROUTE_HC28, 0x400f331c +.set CYREG_UDB_P1_ROUTE_HC29, 0x400f331d +.set CYREG_UDB_P1_ROUTE_HC30, 0x400f331e +.set CYREG_UDB_P1_ROUTE_HC31, 0x400f331f +.set CYREG_UDB_P1_ROUTE_HC32, 0x400f3320 +.set CYREG_UDB_P1_ROUTE_HC33, 0x400f3321 +.set CYREG_UDB_P1_ROUTE_HC34, 0x400f3322 +.set CYREG_UDB_P1_ROUTE_HC35, 0x400f3323 +.set CYREG_UDB_P1_ROUTE_HC36, 0x400f3324 +.set CYREG_UDB_P1_ROUTE_HC37, 0x400f3325 +.set CYREG_UDB_P1_ROUTE_HC38, 0x400f3326 +.set CYREG_UDB_P1_ROUTE_HC39, 0x400f3327 +.set CYREG_UDB_P1_ROUTE_HC40, 0x400f3328 +.set CYREG_UDB_P1_ROUTE_HC41, 0x400f3329 +.set CYREG_UDB_P1_ROUTE_HC42, 0x400f332a +.set CYREG_UDB_P1_ROUTE_HC43, 0x400f332b +.set CYREG_UDB_P1_ROUTE_HC44, 0x400f332c +.set CYREG_UDB_P1_ROUTE_HC45, 0x400f332d +.set CYREG_UDB_P1_ROUTE_HC46, 0x400f332e +.set CYREG_UDB_P1_ROUTE_HC47, 0x400f332f +.set CYREG_UDB_P1_ROUTE_HC48, 0x400f3330 +.set CYREG_UDB_P1_ROUTE_HC49, 0x400f3331 +.set CYREG_UDB_P1_ROUTE_HC50, 0x400f3332 +.set CYREG_UDB_P1_ROUTE_HC51, 0x400f3333 +.set CYREG_UDB_P1_ROUTE_HC52, 0x400f3334 +.set CYREG_UDB_P1_ROUTE_HC53, 0x400f3335 +.set CYREG_UDB_P1_ROUTE_HC54, 0x400f3336 +.set CYREG_UDB_P1_ROUTE_HC55, 0x400f3337 +.set CYREG_UDB_P1_ROUTE_HC56, 0x400f3338 +.set CYREG_UDB_P1_ROUTE_HC57, 0x400f3339 +.set CYREG_UDB_P1_ROUTE_HC58, 0x400f333a +.set CYREG_UDB_P1_ROUTE_HC59, 0x400f333b +.set CYREG_UDB_P1_ROUTE_HC60, 0x400f333c +.set CYREG_UDB_P1_ROUTE_HC61, 0x400f333d +.set CYREG_UDB_P1_ROUTE_HC62, 0x400f333e +.set CYREG_UDB_P1_ROUTE_HC63, 0x400f333f +.set CYREG_UDB_P1_ROUTE_HC64, 0x400f3340 +.set CYREG_UDB_P1_ROUTE_HC65, 0x400f3341 +.set CYREG_UDB_P1_ROUTE_HC66, 0x400f3342 +.set CYREG_UDB_P1_ROUTE_HC67, 0x400f3343 +.set CYREG_UDB_P1_ROUTE_HC68, 0x400f3344 +.set CYREG_UDB_P1_ROUTE_HC69, 0x400f3345 +.set CYREG_UDB_P1_ROUTE_HC70, 0x400f3346 +.set CYREG_UDB_P1_ROUTE_HC71, 0x400f3347 +.set CYREG_UDB_P1_ROUTE_HC72, 0x400f3348 +.set CYREG_UDB_P1_ROUTE_HC73, 0x400f3349 +.set CYREG_UDB_P1_ROUTE_HC74, 0x400f334a +.set CYREG_UDB_P1_ROUTE_HC75, 0x400f334b +.set CYREG_UDB_P1_ROUTE_HC76, 0x400f334c +.set CYREG_UDB_P1_ROUTE_HC77, 0x400f334d +.set CYREG_UDB_P1_ROUTE_HC78, 0x400f334e +.set CYREG_UDB_P1_ROUTE_HC79, 0x400f334f +.set CYREG_UDB_P1_ROUTE_HC80, 0x400f3350 +.set CYREG_UDB_P1_ROUTE_HC81, 0x400f3351 +.set CYREG_UDB_P1_ROUTE_HC82, 0x400f3352 +.set CYREG_UDB_P1_ROUTE_HC83, 0x400f3353 +.set CYREG_UDB_P1_ROUTE_HC84, 0x400f3354 +.set CYREG_UDB_P1_ROUTE_HC85, 0x400f3355 +.set CYREG_UDB_P1_ROUTE_HC86, 0x400f3356 +.set CYREG_UDB_P1_ROUTE_HC87, 0x400f3357 +.set CYREG_UDB_P1_ROUTE_HC88, 0x400f3358 +.set CYREG_UDB_P1_ROUTE_HC89, 0x400f3359 +.set CYREG_UDB_P1_ROUTE_HC90, 0x400f335a +.set CYREG_UDB_P1_ROUTE_HC91, 0x400f335b +.set CYREG_UDB_P1_ROUTE_HC92, 0x400f335c +.set CYREG_UDB_P1_ROUTE_HC93, 0x400f335d +.set CYREG_UDB_P1_ROUTE_HC94, 0x400f335e +.set CYREG_UDB_P1_ROUTE_HC95, 0x400f335f +.set CYREG_UDB_P1_ROUTE_HC96, 0x400f3360 +.set CYREG_UDB_P1_ROUTE_HC97, 0x400f3361 +.set CYREG_UDB_P1_ROUTE_HC98, 0x400f3362 +.set CYREG_UDB_P1_ROUTE_HC99, 0x400f3363 +.set CYREG_UDB_P1_ROUTE_HC100, 0x400f3364 +.set CYREG_UDB_P1_ROUTE_HC101, 0x400f3365 +.set CYREG_UDB_P1_ROUTE_HC102, 0x400f3366 +.set CYREG_UDB_P1_ROUTE_HC103, 0x400f3367 +.set CYREG_UDB_P1_ROUTE_HC104, 0x400f3368 +.set CYREG_UDB_P1_ROUTE_HC105, 0x400f3369 +.set CYREG_UDB_P1_ROUTE_HC106, 0x400f336a +.set CYREG_UDB_P1_ROUTE_HC107, 0x400f336b +.set CYREG_UDB_P1_ROUTE_HC108, 0x400f336c +.set CYREG_UDB_P1_ROUTE_HC109, 0x400f336d +.set CYREG_UDB_P1_ROUTE_HC110, 0x400f336e +.set CYREG_UDB_P1_ROUTE_HC111, 0x400f336f +.set CYREG_UDB_P1_ROUTE_HC112, 0x400f3370 +.set CYREG_UDB_P1_ROUTE_HC113, 0x400f3371 +.set CYREG_UDB_P1_ROUTE_HC114, 0x400f3372 +.set CYREG_UDB_P1_ROUTE_HC115, 0x400f3373 +.set CYREG_UDB_P1_ROUTE_HC116, 0x400f3374 +.set CYREG_UDB_P1_ROUTE_HC117, 0x400f3375 +.set CYREG_UDB_P1_ROUTE_HC118, 0x400f3376 +.set CYREG_UDB_P1_ROUTE_HC119, 0x400f3377 +.set CYREG_UDB_P1_ROUTE_HC120, 0x400f3378 +.set CYREG_UDB_P1_ROUTE_HC121, 0x400f3379 +.set CYREG_UDB_P1_ROUTE_HC122, 0x400f337a +.set CYREG_UDB_P1_ROUTE_HC123, 0x400f337b +.set CYREG_UDB_P1_ROUTE_HC124, 0x400f337c +.set CYREG_UDB_P1_ROUTE_HC125, 0x400f337d +.set CYREG_UDB_P1_ROUTE_HC126, 0x400f337e +.set CYREG_UDB_P1_ROUTE_HC127, 0x400f337f +.set CYREG_UDB_P1_ROUTE_HV_L0, 0x400f3380 +.set CYREG_UDB_P1_ROUTE_HV_L1, 0x400f3381 +.set CYREG_UDB_P1_ROUTE_HV_L2, 0x400f3382 +.set CYREG_UDB_P1_ROUTE_HV_L3, 0x400f3383 +.set CYREG_UDB_P1_ROUTE_HV_L4, 0x400f3384 +.set CYREG_UDB_P1_ROUTE_HV_L5, 0x400f3385 +.set CYREG_UDB_P1_ROUTE_HV_L6, 0x400f3386 +.set CYREG_UDB_P1_ROUTE_HV_L7, 0x400f3387 +.set CYREG_UDB_P1_ROUTE_HV_L8, 0x400f3388 +.set CYREG_UDB_P1_ROUTE_HV_L9, 0x400f3389 +.set CYREG_UDB_P1_ROUTE_HV_L10, 0x400f338a +.set CYREG_UDB_P1_ROUTE_HV_L11, 0x400f338b +.set CYREG_UDB_P1_ROUTE_HV_L12, 0x400f338c +.set CYREG_UDB_P1_ROUTE_HV_L13, 0x400f338d +.set CYREG_UDB_P1_ROUTE_HV_L14, 0x400f338e +.set CYREG_UDB_P1_ROUTE_HV_L15, 0x400f338f +.set CYREG_UDB_P1_ROUTE_HS0, 0x400f3390 +.set CYREG_UDB_P1_ROUTE_HS1, 0x400f3391 +.set CYREG_UDB_P1_ROUTE_HS2, 0x400f3392 +.set CYREG_UDB_P1_ROUTE_HS3, 0x400f3393 +.set CYREG_UDB_P1_ROUTE_HS4, 0x400f3394 +.set CYREG_UDB_P1_ROUTE_HS5, 0x400f3395 +.set CYREG_UDB_P1_ROUTE_HS6, 0x400f3396 +.set CYREG_UDB_P1_ROUTE_HS7, 0x400f3397 +.set CYREG_UDB_P1_ROUTE_HS8, 0x400f3398 +.set CYREG_UDB_P1_ROUTE_HS9, 0x400f3399 +.set CYREG_UDB_P1_ROUTE_HS10, 0x400f339a +.set CYREG_UDB_P1_ROUTE_HS11, 0x400f339b +.set CYREG_UDB_P1_ROUTE_HS12, 0x400f339c +.set CYREG_UDB_P1_ROUTE_HS13, 0x400f339d +.set CYREG_UDB_P1_ROUTE_HS14, 0x400f339e +.set CYREG_UDB_P1_ROUTE_HS15, 0x400f339f +.set CYREG_UDB_P1_ROUTE_HS16, 0x400f33a0 +.set CYREG_UDB_P1_ROUTE_HS17, 0x400f33a1 +.set CYREG_UDB_P1_ROUTE_HS18, 0x400f33a2 +.set CYREG_UDB_P1_ROUTE_HS19, 0x400f33a3 +.set CYREG_UDB_P1_ROUTE_HS20, 0x400f33a4 +.set CYREG_UDB_P1_ROUTE_HS21, 0x400f33a5 +.set CYREG_UDB_P1_ROUTE_HS22, 0x400f33a6 +.set CYREG_UDB_P1_ROUTE_HS23, 0x400f33a7 +.set CYREG_UDB_P1_ROUTE_HV_R0, 0x400f33a8 +.set CYREG_UDB_P1_ROUTE_HV_R1, 0x400f33a9 +.set CYREG_UDB_P1_ROUTE_HV_R2, 0x400f33aa +.set CYREG_UDB_P1_ROUTE_HV_R3, 0x400f33ab +.set CYREG_UDB_P1_ROUTE_HV_R4, 0x400f33ac +.set CYREG_UDB_P1_ROUTE_HV_R5, 0x400f33ad +.set CYREG_UDB_P1_ROUTE_HV_R6, 0x400f33ae +.set CYREG_UDB_P1_ROUTE_HV_R7, 0x400f33af +.set CYREG_UDB_P1_ROUTE_HV_R8, 0x400f33b0 +.set CYREG_UDB_P1_ROUTE_HV_R9, 0x400f33b1 +.set CYREG_UDB_P1_ROUTE_HV_R10, 0x400f33b2 +.set CYREG_UDB_P1_ROUTE_HV_R11, 0x400f33b3 +.set CYREG_UDB_P1_ROUTE_HV_R12, 0x400f33b4 +.set CYREG_UDB_P1_ROUTE_HV_R13, 0x400f33b5 +.set CYREG_UDB_P1_ROUTE_HV_R14, 0x400f33b6 +.set CYREG_UDB_P1_ROUTE_HV_R15, 0x400f33b7 +.set CYREG_UDB_P1_ROUTE_PLD0IN0, 0x400f33c0 +.set CYREG_UDB_P1_ROUTE_PLD0IN1, 0x400f33c2 +.set CYREG_UDB_P1_ROUTE_PLD0IN2, 0x400f33c4 +.set CYREG_UDB_P1_ROUTE_PLD1IN0, 0x400f33ca +.set CYREG_UDB_P1_ROUTE_PLD1IN1, 0x400f33cc +.set CYREG_UDB_P1_ROUTE_PLD1IN2, 0x400f33ce +.set CYREG_UDB_P1_ROUTE_DPIN0, 0x400f33d0 +.set CYREG_UDB_P1_ROUTE_DPIN1, 0x400f33d2 +.set CYREG_UDB_P1_ROUTE_SCIN, 0x400f33d6 +.set CYREG_UDB_P1_ROUTE_SCIOIN, 0x400f33d8 +.set CYREG_UDB_P1_ROUTE_RCIN, 0x400f33de +.set CYREG_UDB_P1_ROUTE_VS0, 0x400f33e0 +.set CYREG_UDB_P1_ROUTE_VS1, 0x400f33e2 +.set CYREG_UDB_P1_ROUTE_VS2, 0x400f33e4 +.set CYREG_UDB_P1_ROUTE_VS3, 0x400f33e6 +.set CYREG_UDB_P1_ROUTE_VS4, 0x400f33e8 +.set CYREG_UDB_P1_ROUTE_VS5, 0x400f33ea +.set CYREG_UDB_P1_ROUTE_VS6, 0x400f33ec +.set CYREG_UDB_P1_ROUTE_VS7, 0x400f33ee +.set CYDEV_UDB_DSI0_BASE, 0x400f4000 +.set CYDEV_UDB_DSI0_SIZE, 0x00000100 +.set CYREG_UDB_DSI0_HC0, 0x400f4000 +.set CYFLD_UDB_DSI_HC_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_HC_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_DSI0_HC1, 0x400f4001 +.set CYREG_UDB_DSI0_HC2, 0x400f4002 +.set CYREG_UDB_DSI0_HC3, 0x400f4003 +.set CYREG_UDB_DSI0_HC4, 0x400f4004 +.set CYREG_UDB_DSI0_HC5, 0x400f4005 +.set CYREG_UDB_DSI0_HC6, 0x400f4006 +.set CYREG_UDB_DSI0_HC7, 0x400f4007 +.set CYREG_UDB_DSI0_HC8, 0x400f4008 +.set CYREG_UDB_DSI0_HC9, 0x400f4009 +.set CYREG_UDB_DSI0_HC10, 0x400f400a +.set CYREG_UDB_DSI0_HC11, 0x400f400b +.set CYREG_UDB_DSI0_HC12, 0x400f400c +.set CYREG_UDB_DSI0_HC13, 0x400f400d +.set CYREG_UDB_DSI0_HC14, 0x400f400e +.set CYREG_UDB_DSI0_HC15, 0x400f400f +.set CYREG_UDB_DSI0_HC16, 0x400f4010 +.set CYREG_UDB_DSI0_HC17, 0x400f4011 +.set CYREG_UDB_DSI0_HC18, 0x400f4012 +.set CYREG_UDB_DSI0_HC19, 0x400f4013 +.set CYREG_UDB_DSI0_HC20, 0x400f4014 +.set CYREG_UDB_DSI0_HC21, 0x400f4015 +.set CYREG_UDB_DSI0_HC22, 0x400f4016 +.set CYREG_UDB_DSI0_HC23, 0x400f4017 +.set CYREG_UDB_DSI0_HC24, 0x400f4018 +.set CYREG_UDB_DSI0_HC25, 0x400f4019 +.set CYREG_UDB_DSI0_HC26, 0x400f401a +.set CYREG_UDB_DSI0_HC27, 0x400f401b +.set CYREG_UDB_DSI0_HC28, 0x400f401c +.set CYREG_UDB_DSI0_HC29, 0x400f401d +.set CYREG_UDB_DSI0_HC30, 0x400f401e +.set CYREG_UDB_DSI0_HC31, 0x400f401f +.set CYREG_UDB_DSI0_HC32, 0x400f4020 +.set CYREG_UDB_DSI0_HC33, 0x400f4021 +.set CYREG_UDB_DSI0_HC34, 0x400f4022 +.set CYREG_UDB_DSI0_HC35, 0x400f4023 +.set CYREG_UDB_DSI0_HC36, 0x400f4024 +.set CYREG_UDB_DSI0_HC37, 0x400f4025 +.set CYREG_UDB_DSI0_HC38, 0x400f4026 +.set CYREG_UDB_DSI0_HC39, 0x400f4027 +.set CYREG_UDB_DSI0_HC40, 0x400f4028 +.set CYREG_UDB_DSI0_HC41, 0x400f4029 +.set CYREG_UDB_DSI0_HC42, 0x400f402a +.set CYREG_UDB_DSI0_HC43, 0x400f402b +.set CYREG_UDB_DSI0_HC44, 0x400f402c +.set CYREG_UDB_DSI0_HC45, 0x400f402d +.set CYREG_UDB_DSI0_HC46, 0x400f402e +.set CYREG_UDB_DSI0_HC47, 0x400f402f +.set CYREG_UDB_DSI0_HC48, 0x400f4030 +.set CYREG_UDB_DSI0_HC49, 0x400f4031 +.set CYREG_UDB_DSI0_HC50, 0x400f4032 +.set CYREG_UDB_DSI0_HC51, 0x400f4033 +.set CYREG_UDB_DSI0_HC52, 0x400f4034 +.set CYREG_UDB_DSI0_HC53, 0x400f4035 +.set CYREG_UDB_DSI0_HC54, 0x400f4036 +.set CYREG_UDB_DSI0_HC55, 0x400f4037 +.set CYREG_UDB_DSI0_HC56, 0x400f4038 +.set CYREG_UDB_DSI0_HC57, 0x400f4039 +.set CYREG_UDB_DSI0_HC58, 0x400f403a +.set CYREG_UDB_DSI0_HC59, 0x400f403b +.set CYREG_UDB_DSI0_HC60, 0x400f403c +.set CYREG_UDB_DSI0_HC61, 0x400f403d +.set CYREG_UDB_DSI0_HC62, 0x400f403e +.set CYREG_UDB_DSI0_HC63, 0x400f403f +.set CYREG_UDB_DSI0_HC64, 0x400f4040 +.set CYREG_UDB_DSI0_HC65, 0x400f4041 +.set CYREG_UDB_DSI0_HC66, 0x400f4042 +.set CYREG_UDB_DSI0_HC67, 0x400f4043 +.set CYREG_UDB_DSI0_HC68, 0x400f4044 +.set CYREG_UDB_DSI0_HC69, 0x400f4045 +.set CYREG_UDB_DSI0_HC70, 0x400f4046 +.set CYREG_UDB_DSI0_HC71, 0x400f4047 +.set CYREG_UDB_DSI0_HC72, 0x400f4048 +.set CYREG_UDB_DSI0_HC73, 0x400f4049 +.set CYREG_UDB_DSI0_HC74, 0x400f404a +.set CYREG_UDB_DSI0_HC75, 0x400f404b +.set CYREG_UDB_DSI0_HC76, 0x400f404c +.set CYREG_UDB_DSI0_HC77, 0x400f404d +.set CYREG_UDB_DSI0_HC78, 0x400f404e +.set CYREG_UDB_DSI0_HC79, 0x400f404f +.set CYREG_UDB_DSI0_HC80, 0x400f4050 +.set CYREG_UDB_DSI0_HC81, 0x400f4051 +.set CYREG_UDB_DSI0_HC82, 0x400f4052 +.set CYREG_UDB_DSI0_HC83, 0x400f4053 +.set CYREG_UDB_DSI0_HC84, 0x400f4054 +.set CYREG_UDB_DSI0_HC85, 0x400f4055 +.set CYREG_UDB_DSI0_HC86, 0x400f4056 +.set CYREG_UDB_DSI0_HC87, 0x400f4057 +.set CYREG_UDB_DSI0_HC88, 0x400f4058 +.set CYREG_UDB_DSI0_HC89, 0x400f4059 +.set CYREG_UDB_DSI0_HC90, 0x400f405a +.set CYREG_UDB_DSI0_HC91, 0x400f405b +.set CYREG_UDB_DSI0_HC92, 0x400f405c +.set CYREG_UDB_DSI0_HC93, 0x400f405d +.set CYREG_UDB_DSI0_HC94, 0x400f405e +.set CYREG_UDB_DSI0_HC95, 0x400f405f +.set CYREG_UDB_DSI0_HC96, 0x400f4060 +.set CYREG_UDB_DSI0_HC97, 0x400f4061 +.set CYREG_UDB_DSI0_HC98, 0x400f4062 +.set CYREG_UDB_DSI0_HC99, 0x400f4063 +.set CYREG_UDB_DSI0_HC100, 0x400f4064 +.set CYREG_UDB_DSI0_HC101, 0x400f4065 +.set CYREG_UDB_DSI0_HC102, 0x400f4066 +.set CYREG_UDB_DSI0_HC103, 0x400f4067 +.set CYREG_UDB_DSI0_HC104, 0x400f4068 +.set CYREG_UDB_DSI0_HC105, 0x400f4069 +.set CYREG_UDB_DSI0_HC106, 0x400f406a +.set CYREG_UDB_DSI0_HC107, 0x400f406b +.set CYREG_UDB_DSI0_HC108, 0x400f406c +.set CYREG_UDB_DSI0_HC109, 0x400f406d +.set CYREG_UDB_DSI0_HC110, 0x400f406e +.set CYREG_UDB_DSI0_HC111, 0x400f406f +.set CYREG_UDB_DSI0_HC112, 0x400f4070 +.set CYREG_UDB_DSI0_HC113, 0x400f4071 +.set CYREG_UDB_DSI0_HC114, 0x400f4072 +.set CYREG_UDB_DSI0_HC115, 0x400f4073 +.set CYREG_UDB_DSI0_HC116, 0x400f4074 +.set CYREG_UDB_DSI0_HC117, 0x400f4075 +.set CYREG_UDB_DSI0_HC118, 0x400f4076 +.set CYREG_UDB_DSI0_HC119, 0x400f4077 +.set CYREG_UDB_DSI0_HC120, 0x400f4078 +.set CYREG_UDB_DSI0_HC121, 0x400f4079 +.set CYREG_UDB_DSI0_HC122, 0x400f407a +.set CYREG_UDB_DSI0_HC123, 0x400f407b +.set CYREG_UDB_DSI0_HC124, 0x400f407c +.set CYREG_UDB_DSI0_HC125, 0x400f407d +.set CYREG_UDB_DSI0_HC126, 0x400f407e +.set CYREG_UDB_DSI0_HC127, 0x400f407f +.set CYREG_UDB_DSI0_HV_L0, 0x400f4080 +.set CYFLD_UDB_DSI_HV_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_HV_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_DSI0_HV_L1, 0x400f4081 +.set CYREG_UDB_DSI0_HV_L2, 0x400f4082 +.set CYREG_UDB_DSI0_HV_L3, 0x400f4083 +.set CYREG_UDB_DSI0_HV_L4, 0x400f4084 +.set CYREG_UDB_DSI0_HV_L5, 0x400f4085 +.set CYREG_UDB_DSI0_HV_L6, 0x400f4086 +.set CYREG_UDB_DSI0_HV_L7, 0x400f4087 +.set CYREG_UDB_DSI0_HV_L8, 0x400f4088 +.set CYREG_UDB_DSI0_HV_L9, 0x400f4089 +.set CYREG_UDB_DSI0_HV_L10, 0x400f408a +.set CYREG_UDB_DSI0_HV_L11, 0x400f408b +.set CYREG_UDB_DSI0_HV_L12, 0x400f408c +.set CYREG_UDB_DSI0_HV_L13, 0x400f408d +.set CYREG_UDB_DSI0_HV_L14, 0x400f408e +.set CYREG_UDB_DSI0_HV_L15, 0x400f408f +.set CYREG_UDB_DSI0_HS0, 0x400f4090 +.set CYFLD_UDB_DSI_HS_BYTE__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_HS_BYTE__SIZE, 0x00000008 +.set CYREG_UDB_DSI0_HS1, 0x400f4091 +.set CYREG_UDB_DSI0_HS2, 0x400f4092 +.set CYREG_UDB_DSI0_HS3, 0x400f4093 +.set CYREG_UDB_DSI0_HS4, 0x400f4094 +.set CYREG_UDB_DSI0_HS5, 0x400f4095 +.set CYREG_UDB_DSI0_HS6, 0x400f4096 +.set CYREG_UDB_DSI0_HS7, 0x400f4097 +.set CYREG_UDB_DSI0_HS8, 0x400f4098 +.set CYREG_UDB_DSI0_HS9, 0x400f4099 +.set CYREG_UDB_DSI0_HS10, 0x400f409a +.set CYREG_UDB_DSI0_HS11, 0x400f409b +.set CYREG_UDB_DSI0_HS12, 0x400f409c +.set CYREG_UDB_DSI0_HS13, 0x400f409d +.set CYREG_UDB_DSI0_HS14, 0x400f409e +.set CYREG_UDB_DSI0_HS15, 0x400f409f +.set CYREG_UDB_DSI0_HS16, 0x400f40a0 +.set CYREG_UDB_DSI0_HS17, 0x400f40a1 +.set CYREG_UDB_DSI0_HS18, 0x400f40a2 +.set CYREG_UDB_DSI0_HS19, 0x400f40a3 +.set CYREG_UDB_DSI0_HS20, 0x400f40a4 +.set CYREG_UDB_DSI0_HS21, 0x400f40a5 +.set CYREG_UDB_DSI0_HS22, 0x400f40a6 +.set CYREG_UDB_DSI0_HS23, 0x400f40a7 +.set CYREG_UDB_DSI0_HV_R0, 0x400f40a8 +.set CYREG_UDB_DSI0_HV_R1, 0x400f40a9 +.set CYREG_UDB_DSI0_HV_R2, 0x400f40aa +.set CYREG_UDB_DSI0_HV_R3, 0x400f40ab +.set CYREG_UDB_DSI0_HV_R4, 0x400f40ac +.set CYREG_UDB_DSI0_HV_R5, 0x400f40ad +.set CYREG_UDB_DSI0_HV_R6, 0x400f40ae +.set CYREG_UDB_DSI0_HV_R7, 0x400f40af +.set CYREG_UDB_DSI0_HV_R8, 0x400f40b0 +.set CYREG_UDB_DSI0_HV_R9, 0x400f40b1 +.set CYREG_UDB_DSI0_HV_R10, 0x400f40b2 +.set CYREG_UDB_DSI0_HV_R11, 0x400f40b3 +.set CYREG_UDB_DSI0_HV_R12, 0x400f40b4 +.set CYREG_UDB_DSI0_HV_R13, 0x400f40b5 +.set CYREG_UDB_DSI0_HV_R14, 0x400f40b6 +.set CYREG_UDB_DSI0_HV_R15, 0x400f40b7 +.set CYREG_UDB_DSI0_DSIINP0, 0x400f40c0 +.set CYFLD_UDB_DSI_PI_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_PI_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_DSI_PI_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_DSI_PI_BOT__SIZE, 0x00000004 +.set CYREG_UDB_DSI0_DSIINP1, 0x400f40c2 +.set CYREG_UDB_DSI0_DSIINP2, 0x400f40c4 +.set CYREG_UDB_DSI0_DSIINP3, 0x400f40c6 +.set CYREG_UDB_DSI0_DSIINP4, 0x400f40c8 +.set CYREG_UDB_DSI0_DSIINP5, 0x400f40ca +.set CYREG_UDB_DSI0_DSIOUTP0, 0x400f40cc +.set CYREG_UDB_DSI0_DSIOUTP1, 0x400f40ce +.set CYREG_UDB_DSI0_DSIOUTP2, 0x400f40d0 +.set CYREG_UDB_DSI0_DSIOUTP3, 0x400f40d2 +.set CYREG_UDB_DSI0_DSIOUTT0, 0x400f40d4 +.set CYREG_UDB_DSI0_DSIOUTT1, 0x400f40d6 +.set CYREG_UDB_DSI0_DSIOUTT2, 0x400f40d8 +.set CYREG_UDB_DSI0_DSIOUTT3, 0x400f40da +.set CYREG_UDB_DSI0_DSIOUTT4, 0x400f40dc +.set CYREG_UDB_DSI0_DSIOUTT5, 0x400f40de +.set CYREG_UDB_DSI0_VS0, 0x400f40e0 +.set CYFLD_UDB_DSI_VS_TOP__OFFSET, 0x00000000 +.set CYFLD_UDB_DSI_VS_TOP__SIZE, 0x00000004 +.set CYFLD_UDB_DSI_VS_BOT__OFFSET, 0x00000004 +.set CYFLD_UDB_DSI_VS_BOT__SIZE, 0x00000004 +.set CYREG_UDB_DSI0_VS1, 0x400f40e2 +.set CYREG_UDB_DSI0_VS2, 0x400f40e4 +.set CYREG_UDB_DSI0_VS3, 0x400f40e6 +.set CYREG_UDB_DSI0_VS4, 0x400f40e8 +.set CYREG_UDB_DSI0_VS5, 0x400f40ea +.set CYREG_UDB_DSI0_VS6, 0x400f40ec +.set CYREG_UDB_DSI0_VS7, 0x400f40ee +.set CYDEV_UDB_DSI1_BASE, 0x400f4100 +.set CYDEV_UDB_DSI1_SIZE, 0x00000100 +.set CYREG_UDB_DSI1_HC0, 0x400f4100 +.set CYREG_UDB_DSI1_HC1, 0x400f4101 +.set CYREG_UDB_DSI1_HC2, 0x400f4102 +.set CYREG_UDB_DSI1_HC3, 0x400f4103 +.set CYREG_UDB_DSI1_HC4, 0x400f4104 +.set CYREG_UDB_DSI1_HC5, 0x400f4105 +.set CYREG_UDB_DSI1_HC6, 0x400f4106 +.set CYREG_UDB_DSI1_HC7, 0x400f4107 +.set CYREG_UDB_DSI1_HC8, 0x400f4108 +.set CYREG_UDB_DSI1_HC9, 0x400f4109 +.set CYREG_UDB_DSI1_HC10, 0x400f410a +.set CYREG_UDB_DSI1_HC11, 0x400f410b +.set CYREG_UDB_DSI1_HC12, 0x400f410c +.set CYREG_UDB_DSI1_HC13, 0x400f410d +.set CYREG_UDB_DSI1_HC14, 0x400f410e +.set CYREG_UDB_DSI1_HC15, 0x400f410f +.set CYREG_UDB_DSI1_HC16, 0x400f4110 +.set CYREG_UDB_DSI1_HC17, 0x400f4111 +.set CYREG_UDB_DSI1_HC18, 0x400f4112 +.set CYREG_UDB_DSI1_HC19, 0x400f4113 +.set CYREG_UDB_DSI1_HC20, 0x400f4114 +.set CYREG_UDB_DSI1_HC21, 0x400f4115 +.set CYREG_UDB_DSI1_HC22, 0x400f4116 +.set CYREG_UDB_DSI1_HC23, 0x400f4117 +.set CYREG_UDB_DSI1_HC24, 0x400f4118 +.set CYREG_UDB_DSI1_HC25, 0x400f4119 +.set CYREG_UDB_DSI1_HC26, 0x400f411a +.set CYREG_UDB_DSI1_HC27, 0x400f411b +.set CYREG_UDB_DSI1_HC28, 0x400f411c +.set CYREG_UDB_DSI1_HC29, 0x400f411d +.set CYREG_UDB_DSI1_HC30, 0x400f411e +.set CYREG_UDB_DSI1_HC31, 0x400f411f +.set CYREG_UDB_DSI1_HC32, 0x400f4120 +.set CYREG_UDB_DSI1_HC33, 0x400f4121 +.set CYREG_UDB_DSI1_HC34, 0x400f4122 +.set CYREG_UDB_DSI1_HC35, 0x400f4123 +.set CYREG_UDB_DSI1_HC36, 0x400f4124 +.set CYREG_UDB_DSI1_HC37, 0x400f4125 +.set CYREG_UDB_DSI1_HC38, 0x400f4126 +.set CYREG_UDB_DSI1_HC39, 0x400f4127 +.set CYREG_UDB_DSI1_HC40, 0x400f4128 +.set CYREG_UDB_DSI1_HC41, 0x400f4129 +.set CYREG_UDB_DSI1_HC42, 0x400f412a +.set CYREG_UDB_DSI1_HC43, 0x400f412b +.set CYREG_UDB_DSI1_HC44, 0x400f412c +.set CYREG_UDB_DSI1_HC45, 0x400f412d +.set CYREG_UDB_DSI1_HC46, 0x400f412e +.set CYREG_UDB_DSI1_HC47, 0x400f412f +.set CYREG_UDB_DSI1_HC48, 0x400f4130 +.set CYREG_UDB_DSI1_HC49, 0x400f4131 +.set CYREG_UDB_DSI1_HC50, 0x400f4132 +.set CYREG_UDB_DSI1_HC51, 0x400f4133 +.set CYREG_UDB_DSI1_HC52, 0x400f4134 +.set CYREG_UDB_DSI1_HC53, 0x400f4135 +.set CYREG_UDB_DSI1_HC54, 0x400f4136 +.set CYREG_UDB_DSI1_HC55, 0x400f4137 +.set CYREG_UDB_DSI1_HC56, 0x400f4138 +.set CYREG_UDB_DSI1_HC57, 0x400f4139 +.set CYREG_UDB_DSI1_HC58, 0x400f413a +.set CYREG_UDB_DSI1_HC59, 0x400f413b +.set CYREG_UDB_DSI1_HC60, 0x400f413c +.set CYREG_UDB_DSI1_HC61, 0x400f413d +.set CYREG_UDB_DSI1_HC62, 0x400f413e +.set CYREG_UDB_DSI1_HC63, 0x400f413f +.set CYREG_UDB_DSI1_HC64, 0x400f4140 +.set CYREG_UDB_DSI1_HC65, 0x400f4141 +.set CYREG_UDB_DSI1_HC66, 0x400f4142 +.set CYREG_UDB_DSI1_HC67, 0x400f4143 +.set CYREG_UDB_DSI1_HC68, 0x400f4144 +.set CYREG_UDB_DSI1_HC69, 0x400f4145 +.set CYREG_UDB_DSI1_HC70, 0x400f4146 +.set CYREG_UDB_DSI1_HC71, 0x400f4147 +.set CYREG_UDB_DSI1_HC72, 0x400f4148 +.set CYREG_UDB_DSI1_HC73, 0x400f4149 +.set CYREG_UDB_DSI1_HC74, 0x400f414a +.set CYREG_UDB_DSI1_HC75, 0x400f414b +.set CYREG_UDB_DSI1_HC76, 0x400f414c +.set CYREG_UDB_DSI1_HC77, 0x400f414d +.set CYREG_UDB_DSI1_HC78, 0x400f414e +.set CYREG_UDB_DSI1_HC79, 0x400f414f +.set CYREG_UDB_DSI1_HC80, 0x400f4150 +.set CYREG_UDB_DSI1_HC81, 0x400f4151 +.set CYREG_UDB_DSI1_HC82, 0x400f4152 +.set CYREG_UDB_DSI1_HC83, 0x400f4153 +.set CYREG_UDB_DSI1_HC84, 0x400f4154 +.set CYREG_UDB_DSI1_HC85, 0x400f4155 +.set CYREG_UDB_DSI1_HC86, 0x400f4156 +.set CYREG_UDB_DSI1_HC87, 0x400f4157 +.set CYREG_UDB_DSI1_HC88, 0x400f4158 +.set CYREG_UDB_DSI1_HC89, 0x400f4159 +.set CYREG_UDB_DSI1_HC90, 0x400f415a +.set CYREG_UDB_DSI1_HC91, 0x400f415b +.set CYREG_UDB_DSI1_HC92, 0x400f415c +.set CYREG_UDB_DSI1_HC93, 0x400f415d +.set CYREG_UDB_DSI1_HC94, 0x400f415e +.set CYREG_UDB_DSI1_HC95, 0x400f415f +.set CYREG_UDB_DSI1_HC96, 0x400f4160 +.set CYREG_UDB_DSI1_HC97, 0x400f4161 +.set CYREG_UDB_DSI1_HC98, 0x400f4162 +.set CYREG_UDB_DSI1_HC99, 0x400f4163 +.set CYREG_UDB_DSI1_HC100, 0x400f4164 +.set CYREG_UDB_DSI1_HC101, 0x400f4165 +.set CYREG_UDB_DSI1_HC102, 0x400f4166 +.set CYREG_UDB_DSI1_HC103, 0x400f4167 +.set CYREG_UDB_DSI1_HC104, 0x400f4168 +.set CYREG_UDB_DSI1_HC105, 0x400f4169 +.set CYREG_UDB_DSI1_HC106, 0x400f416a +.set CYREG_UDB_DSI1_HC107, 0x400f416b +.set CYREG_UDB_DSI1_HC108, 0x400f416c +.set CYREG_UDB_DSI1_HC109, 0x400f416d +.set CYREG_UDB_DSI1_HC110, 0x400f416e +.set CYREG_UDB_DSI1_HC111, 0x400f416f +.set CYREG_UDB_DSI1_HC112, 0x400f4170 +.set CYREG_UDB_DSI1_HC113, 0x400f4171 +.set CYREG_UDB_DSI1_HC114, 0x400f4172 +.set CYREG_UDB_DSI1_HC115, 0x400f4173 +.set CYREG_UDB_DSI1_HC116, 0x400f4174 +.set CYREG_UDB_DSI1_HC117, 0x400f4175 +.set CYREG_UDB_DSI1_HC118, 0x400f4176 +.set CYREG_UDB_DSI1_HC119, 0x400f4177 +.set CYREG_UDB_DSI1_HC120, 0x400f4178 +.set CYREG_UDB_DSI1_HC121, 0x400f4179 +.set CYREG_UDB_DSI1_HC122, 0x400f417a +.set CYREG_UDB_DSI1_HC123, 0x400f417b +.set CYREG_UDB_DSI1_HC124, 0x400f417c +.set CYREG_UDB_DSI1_HC125, 0x400f417d +.set CYREG_UDB_DSI1_HC126, 0x400f417e +.set CYREG_UDB_DSI1_HC127, 0x400f417f +.set CYREG_UDB_DSI1_HV_L0, 0x400f4180 +.set CYREG_UDB_DSI1_HV_L1, 0x400f4181 +.set CYREG_UDB_DSI1_HV_L2, 0x400f4182 +.set CYREG_UDB_DSI1_HV_L3, 0x400f4183 +.set CYREG_UDB_DSI1_HV_L4, 0x400f4184 +.set CYREG_UDB_DSI1_HV_L5, 0x400f4185 +.set CYREG_UDB_DSI1_HV_L6, 0x400f4186 +.set CYREG_UDB_DSI1_HV_L7, 0x400f4187 +.set CYREG_UDB_DSI1_HV_L8, 0x400f4188 +.set CYREG_UDB_DSI1_HV_L9, 0x400f4189 +.set CYREG_UDB_DSI1_HV_L10, 0x400f418a +.set CYREG_UDB_DSI1_HV_L11, 0x400f418b +.set CYREG_UDB_DSI1_HV_L12, 0x400f418c +.set CYREG_UDB_DSI1_HV_L13, 0x400f418d +.set CYREG_UDB_DSI1_HV_L14, 0x400f418e +.set CYREG_UDB_DSI1_HV_L15, 0x400f418f +.set CYREG_UDB_DSI1_HS0, 0x400f4190 +.set CYREG_UDB_DSI1_HS1, 0x400f4191 +.set CYREG_UDB_DSI1_HS2, 0x400f4192 +.set CYREG_UDB_DSI1_HS3, 0x400f4193 +.set CYREG_UDB_DSI1_HS4, 0x400f4194 +.set CYREG_UDB_DSI1_HS5, 0x400f4195 +.set CYREG_UDB_DSI1_HS6, 0x400f4196 +.set CYREG_UDB_DSI1_HS7, 0x400f4197 +.set CYREG_UDB_DSI1_HS8, 0x400f4198 +.set CYREG_UDB_DSI1_HS9, 0x400f4199 +.set CYREG_UDB_DSI1_HS10, 0x400f419a +.set CYREG_UDB_DSI1_HS11, 0x400f419b +.set CYREG_UDB_DSI1_HS12, 0x400f419c +.set CYREG_UDB_DSI1_HS13, 0x400f419d +.set CYREG_UDB_DSI1_HS14, 0x400f419e +.set CYREG_UDB_DSI1_HS15, 0x400f419f +.set CYREG_UDB_DSI1_HS16, 0x400f41a0 +.set CYREG_UDB_DSI1_HS17, 0x400f41a1 +.set CYREG_UDB_DSI1_HS18, 0x400f41a2 +.set CYREG_UDB_DSI1_HS19, 0x400f41a3 +.set CYREG_UDB_DSI1_HS20, 0x400f41a4 +.set CYREG_UDB_DSI1_HS21, 0x400f41a5 +.set CYREG_UDB_DSI1_HS22, 0x400f41a6 +.set CYREG_UDB_DSI1_HS23, 0x400f41a7 +.set CYREG_UDB_DSI1_HV_R0, 0x400f41a8 +.set CYREG_UDB_DSI1_HV_R1, 0x400f41a9 +.set CYREG_UDB_DSI1_HV_R2, 0x400f41aa +.set CYREG_UDB_DSI1_HV_R3, 0x400f41ab +.set CYREG_UDB_DSI1_HV_R4, 0x400f41ac +.set CYREG_UDB_DSI1_HV_R5, 0x400f41ad +.set CYREG_UDB_DSI1_HV_R6, 0x400f41ae +.set CYREG_UDB_DSI1_HV_R7, 0x400f41af +.set CYREG_UDB_DSI1_HV_R8, 0x400f41b0 +.set CYREG_UDB_DSI1_HV_R9, 0x400f41b1 +.set CYREG_UDB_DSI1_HV_R10, 0x400f41b2 +.set CYREG_UDB_DSI1_HV_R11, 0x400f41b3 +.set CYREG_UDB_DSI1_HV_R12, 0x400f41b4 +.set CYREG_UDB_DSI1_HV_R13, 0x400f41b5 +.set CYREG_UDB_DSI1_HV_R14, 0x400f41b6 +.set CYREG_UDB_DSI1_HV_R15, 0x400f41b7 +.set CYREG_UDB_DSI1_DSIINP0, 0x400f41c0 +.set CYREG_UDB_DSI1_DSIINP1, 0x400f41c2 +.set CYREG_UDB_DSI1_DSIINP2, 0x400f41c4 +.set CYREG_UDB_DSI1_DSIINP3, 0x400f41c6 +.set CYREG_UDB_DSI1_DSIINP4, 0x400f41c8 +.set CYREG_UDB_DSI1_DSIINP5, 0x400f41ca +.set CYREG_UDB_DSI1_DSIOUTP0, 0x400f41cc +.set CYREG_UDB_DSI1_DSIOUTP1, 0x400f41ce +.set CYREG_UDB_DSI1_DSIOUTP2, 0x400f41d0 +.set CYREG_UDB_DSI1_DSIOUTP3, 0x400f41d2 +.set CYREG_UDB_DSI1_DSIOUTT0, 0x400f41d4 +.set CYREG_UDB_DSI1_DSIOUTT1, 0x400f41d6 +.set CYREG_UDB_DSI1_DSIOUTT2, 0x400f41d8 +.set CYREG_UDB_DSI1_DSIOUTT3, 0x400f41da +.set CYREG_UDB_DSI1_DSIOUTT4, 0x400f41dc +.set CYREG_UDB_DSI1_DSIOUTT5, 0x400f41de +.set CYREG_UDB_DSI1_VS0, 0x400f41e0 +.set CYREG_UDB_DSI1_VS1, 0x400f41e2 +.set CYREG_UDB_DSI1_VS2, 0x400f41e4 +.set CYREG_UDB_DSI1_VS3, 0x400f41e6 +.set CYREG_UDB_DSI1_VS4, 0x400f41e8 +.set CYREG_UDB_DSI1_VS5, 0x400f41ea +.set CYREG_UDB_DSI1_VS6, 0x400f41ec +.set CYREG_UDB_DSI1_VS7, 0x400f41ee +.set CYDEV_UDB_DSI2_BASE, 0x400f4200 +.set CYDEV_UDB_DSI2_SIZE, 0x00000100 +.set CYREG_UDB_DSI2_HC0, 0x400f4200 +.set CYREG_UDB_DSI2_HC1, 0x400f4201 +.set CYREG_UDB_DSI2_HC2, 0x400f4202 +.set CYREG_UDB_DSI2_HC3, 0x400f4203 +.set CYREG_UDB_DSI2_HC4, 0x400f4204 +.set CYREG_UDB_DSI2_HC5, 0x400f4205 +.set CYREG_UDB_DSI2_HC6, 0x400f4206 +.set CYREG_UDB_DSI2_HC7, 0x400f4207 +.set CYREG_UDB_DSI2_HC8, 0x400f4208 +.set CYREG_UDB_DSI2_HC9, 0x400f4209 +.set CYREG_UDB_DSI2_HC10, 0x400f420a +.set CYREG_UDB_DSI2_HC11, 0x400f420b +.set CYREG_UDB_DSI2_HC12, 0x400f420c +.set CYREG_UDB_DSI2_HC13, 0x400f420d +.set CYREG_UDB_DSI2_HC14, 0x400f420e +.set CYREG_UDB_DSI2_HC15, 0x400f420f +.set CYREG_UDB_DSI2_HC16, 0x400f4210 +.set CYREG_UDB_DSI2_HC17, 0x400f4211 +.set CYREG_UDB_DSI2_HC18, 0x400f4212 +.set CYREG_UDB_DSI2_HC19, 0x400f4213 +.set CYREG_UDB_DSI2_HC20, 0x400f4214 +.set CYREG_UDB_DSI2_HC21, 0x400f4215 +.set CYREG_UDB_DSI2_HC22, 0x400f4216 +.set CYREG_UDB_DSI2_HC23, 0x400f4217 +.set CYREG_UDB_DSI2_HC24, 0x400f4218 +.set CYREG_UDB_DSI2_HC25, 0x400f4219 +.set CYREG_UDB_DSI2_HC26, 0x400f421a +.set CYREG_UDB_DSI2_HC27, 0x400f421b +.set CYREG_UDB_DSI2_HC28, 0x400f421c +.set CYREG_UDB_DSI2_HC29, 0x400f421d +.set CYREG_UDB_DSI2_HC30, 0x400f421e +.set CYREG_UDB_DSI2_HC31, 0x400f421f +.set CYREG_UDB_DSI2_HC32, 0x400f4220 +.set CYREG_UDB_DSI2_HC33, 0x400f4221 +.set CYREG_UDB_DSI2_HC34, 0x400f4222 +.set CYREG_UDB_DSI2_HC35, 0x400f4223 +.set CYREG_UDB_DSI2_HC36, 0x400f4224 +.set CYREG_UDB_DSI2_HC37, 0x400f4225 +.set CYREG_UDB_DSI2_HC38, 0x400f4226 +.set CYREG_UDB_DSI2_HC39, 0x400f4227 +.set CYREG_UDB_DSI2_HC40, 0x400f4228 +.set CYREG_UDB_DSI2_HC41, 0x400f4229 +.set CYREG_UDB_DSI2_HC42, 0x400f422a +.set CYREG_UDB_DSI2_HC43, 0x400f422b +.set CYREG_UDB_DSI2_HC44, 0x400f422c +.set CYREG_UDB_DSI2_HC45, 0x400f422d +.set CYREG_UDB_DSI2_HC46, 0x400f422e +.set CYREG_UDB_DSI2_HC47, 0x400f422f +.set CYREG_UDB_DSI2_HC48, 0x400f4230 +.set CYREG_UDB_DSI2_HC49, 0x400f4231 +.set CYREG_UDB_DSI2_HC50, 0x400f4232 +.set CYREG_UDB_DSI2_HC51, 0x400f4233 +.set CYREG_UDB_DSI2_HC52, 0x400f4234 +.set CYREG_UDB_DSI2_HC53, 0x400f4235 +.set CYREG_UDB_DSI2_HC54, 0x400f4236 +.set CYREG_UDB_DSI2_HC55, 0x400f4237 +.set CYREG_UDB_DSI2_HC56, 0x400f4238 +.set CYREG_UDB_DSI2_HC57, 0x400f4239 +.set CYREG_UDB_DSI2_HC58, 0x400f423a +.set CYREG_UDB_DSI2_HC59, 0x400f423b +.set CYREG_UDB_DSI2_HC60, 0x400f423c +.set CYREG_UDB_DSI2_HC61, 0x400f423d +.set CYREG_UDB_DSI2_HC62, 0x400f423e +.set CYREG_UDB_DSI2_HC63, 0x400f423f +.set CYREG_UDB_DSI2_HC64, 0x400f4240 +.set CYREG_UDB_DSI2_HC65, 0x400f4241 +.set CYREG_UDB_DSI2_HC66, 0x400f4242 +.set CYREG_UDB_DSI2_HC67, 0x400f4243 +.set CYREG_UDB_DSI2_HC68, 0x400f4244 +.set CYREG_UDB_DSI2_HC69, 0x400f4245 +.set CYREG_UDB_DSI2_HC70, 0x400f4246 +.set CYREG_UDB_DSI2_HC71, 0x400f4247 +.set CYREG_UDB_DSI2_HC72, 0x400f4248 +.set CYREG_UDB_DSI2_HC73, 0x400f4249 +.set CYREG_UDB_DSI2_HC74, 0x400f424a +.set CYREG_UDB_DSI2_HC75, 0x400f424b +.set CYREG_UDB_DSI2_HC76, 0x400f424c +.set CYREG_UDB_DSI2_HC77, 0x400f424d +.set CYREG_UDB_DSI2_HC78, 0x400f424e +.set CYREG_UDB_DSI2_HC79, 0x400f424f +.set CYREG_UDB_DSI2_HC80, 0x400f4250 +.set CYREG_UDB_DSI2_HC81, 0x400f4251 +.set CYREG_UDB_DSI2_HC82, 0x400f4252 +.set CYREG_UDB_DSI2_HC83, 0x400f4253 +.set CYREG_UDB_DSI2_HC84, 0x400f4254 +.set CYREG_UDB_DSI2_HC85, 0x400f4255 +.set CYREG_UDB_DSI2_HC86, 0x400f4256 +.set CYREG_UDB_DSI2_HC87, 0x400f4257 +.set CYREG_UDB_DSI2_HC88, 0x400f4258 +.set CYREG_UDB_DSI2_HC89, 0x400f4259 +.set CYREG_UDB_DSI2_HC90, 0x400f425a +.set CYREG_UDB_DSI2_HC91, 0x400f425b +.set CYREG_UDB_DSI2_HC92, 0x400f425c +.set CYREG_UDB_DSI2_HC93, 0x400f425d +.set CYREG_UDB_DSI2_HC94, 0x400f425e +.set CYREG_UDB_DSI2_HC95, 0x400f425f +.set CYREG_UDB_DSI2_HC96, 0x400f4260 +.set CYREG_UDB_DSI2_HC97, 0x400f4261 +.set CYREG_UDB_DSI2_HC98, 0x400f4262 +.set CYREG_UDB_DSI2_HC99, 0x400f4263 +.set CYREG_UDB_DSI2_HC100, 0x400f4264 +.set CYREG_UDB_DSI2_HC101, 0x400f4265 +.set CYREG_UDB_DSI2_HC102, 0x400f4266 +.set CYREG_UDB_DSI2_HC103, 0x400f4267 +.set CYREG_UDB_DSI2_HC104, 0x400f4268 +.set CYREG_UDB_DSI2_HC105, 0x400f4269 +.set CYREG_UDB_DSI2_HC106, 0x400f426a +.set CYREG_UDB_DSI2_HC107, 0x400f426b +.set CYREG_UDB_DSI2_HC108, 0x400f426c +.set CYREG_UDB_DSI2_HC109, 0x400f426d +.set CYREG_UDB_DSI2_HC110, 0x400f426e +.set CYREG_UDB_DSI2_HC111, 0x400f426f +.set CYREG_UDB_DSI2_HC112, 0x400f4270 +.set CYREG_UDB_DSI2_HC113, 0x400f4271 +.set CYREG_UDB_DSI2_HC114, 0x400f4272 +.set CYREG_UDB_DSI2_HC115, 0x400f4273 +.set CYREG_UDB_DSI2_HC116, 0x400f4274 +.set CYREG_UDB_DSI2_HC117, 0x400f4275 +.set CYREG_UDB_DSI2_HC118, 0x400f4276 +.set CYREG_UDB_DSI2_HC119, 0x400f4277 +.set CYREG_UDB_DSI2_HC120, 0x400f4278 +.set CYREG_UDB_DSI2_HC121, 0x400f4279 +.set CYREG_UDB_DSI2_HC122, 0x400f427a +.set CYREG_UDB_DSI2_HC123, 0x400f427b +.set CYREG_UDB_DSI2_HC124, 0x400f427c +.set CYREG_UDB_DSI2_HC125, 0x400f427d +.set CYREG_UDB_DSI2_HC126, 0x400f427e +.set CYREG_UDB_DSI2_HC127, 0x400f427f +.set CYREG_UDB_DSI2_HV_L0, 0x400f4280 +.set CYREG_UDB_DSI2_HV_L1, 0x400f4281 +.set CYREG_UDB_DSI2_HV_L2, 0x400f4282 +.set CYREG_UDB_DSI2_HV_L3, 0x400f4283 +.set CYREG_UDB_DSI2_HV_L4, 0x400f4284 +.set CYREG_UDB_DSI2_HV_L5, 0x400f4285 +.set CYREG_UDB_DSI2_HV_L6, 0x400f4286 +.set CYREG_UDB_DSI2_HV_L7, 0x400f4287 +.set CYREG_UDB_DSI2_HV_L8, 0x400f4288 +.set CYREG_UDB_DSI2_HV_L9, 0x400f4289 +.set CYREG_UDB_DSI2_HV_L10, 0x400f428a +.set CYREG_UDB_DSI2_HV_L11, 0x400f428b +.set CYREG_UDB_DSI2_HV_L12, 0x400f428c +.set CYREG_UDB_DSI2_HV_L13, 0x400f428d +.set CYREG_UDB_DSI2_HV_L14, 0x400f428e +.set CYREG_UDB_DSI2_HV_L15, 0x400f428f +.set CYREG_UDB_DSI2_HS0, 0x400f4290 +.set CYREG_UDB_DSI2_HS1, 0x400f4291 +.set CYREG_UDB_DSI2_HS2, 0x400f4292 +.set CYREG_UDB_DSI2_HS3, 0x400f4293 +.set CYREG_UDB_DSI2_HS4, 0x400f4294 +.set CYREG_UDB_DSI2_HS5, 0x400f4295 +.set CYREG_UDB_DSI2_HS6, 0x400f4296 +.set CYREG_UDB_DSI2_HS7, 0x400f4297 +.set CYREG_UDB_DSI2_HS8, 0x400f4298 +.set CYREG_UDB_DSI2_HS9, 0x400f4299 +.set CYREG_UDB_DSI2_HS10, 0x400f429a +.set CYREG_UDB_DSI2_HS11, 0x400f429b +.set CYREG_UDB_DSI2_HS12, 0x400f429c +.set CYREG_UDB_DSI2_HS13, 0x400f429d +.set CYREG_UDB_DSI2_HS14, 0x400f429e +.set CYREG_UDB_DSI2_HS15, 0x400f429f +.set CYREG_UDB_DSI2_HS16, 0x400f42a0 +.set CYREG_UDB_DSI2_HS17, 0x400f42a1 +.set CYREG_UDB_DSI2_HS18, 0x400f42a2 +.set CYREG_UDB_DSI2_HS19, 0x400f42a3 +.set CYREG_UDB_DSI2_HS20, 0x400f42a4 +.set CYREG_UDB_DSI2_HS21, 0x400f42a5 +.set CYREG_UDB_DSI2_HS22, 0x400f42a6 +.set CYREG_UDB_DSI2_HS23, 0x400f42a7 +.set CYREG_UDB_DSI2_HV_R0, 0x400f42a8 +.set CYREG_UDB_DSI2_HV_R1, 0x400f42a9 +.set CYREG_UDB_DSI2_HV_R2, 0x400f42aa +.set CYREG_UDB_DSI2_HV_R3, 0x400f42ab +.set CYREG_UDB_DSI2_HV_R4, 0x400f42ac +.set CYREG_UDB_DSI2_HV_R5, 0x400f42ad +.set CYREG_UDB_DSI2_HV_R6, 0x400f42ae +.set CYREG_UDB_DSI2_HV_R7, 0x400f42af +.set CYREG_UDB_DSI2_HV_R8, 0x400f42b0 +.set CYREG_UDB_DSI2_HV_R9, 0x400f42b1 +.set CYREG_UDB_DSI2_HV_R10, 0x400f42b2 +.set CYREG_UDB_DSI2_HV_R11, 0x400f42b3 +.set CYREG_UDB_DSI2_HV_R12, 0x400f42b4 +.set CYREG_UDB_DSI2_HV_R13, 0x400f42b5 +.set CYREG_UDB_DSI2_HV_R14, 0x400f42b6 +.set CYREG_UDB_DSI2_HV_R15, 0x400f42b7 +.set CYREG_UDB_DSI2_DSIINP0, 0x400f42c0 +.set CYREG_UDB_DSI2_DSIINP1, 0x400f42c2 +.set CYREG_UDB_DSI2_DSIINP2, 0x400f42c4 +.set CYREG_UDB_DSI2_DSIINP3, 0x400f42c6 +.set CYREG_UDB_DSI2_DSIINP4, 0x400f42c8 +.set CYREG_UDB_DSI2_DSIINP5, 0x400f42ca +.set CYREG_UDB_DSI2_DSIOUTP0, 0x400f42cc +.set CYREG_UDB_DSI2_DSIOUTP1, 0x400f42ce +.set CYREG_UDB_DSI2_DSIOUTP2, 0x400f42d0 +.set CYREG_UDB_DSI2_DSIOUTP3, 0x400f42d2 +.set CYREG_UDB_DSI2_DSIOUTT0, 0x400f42d4 +.set CYREG_UDB_DSI2_DSIOUTT1, 0x400f42d6 +.set CYREG_UDB_DSI2_DSIOUTT2, 0x400f42d8 +.set CYREG_UDB_DSI2_DSIOUTT3, 0x400f42da +.set CYREG_UDB_DSI2_DSIOUTT4, 0x400f42dc +.set CYREG_UDB_DSI2_DSIOUTT5, 0x400f42de +.set CYREG_UDB_DSI2_VS0, 0x400f42e0 +.set CYREG_UDB_DSI2_VS1, 0x400f42e2 +.set CYREG_UDB_DSI2_VS2, 0x400f42e4 +.set CYREG_UDB_DSI2_VS3, 0x400f42e6 +.set CYREG_UDB_DSI2_VS4, 0x400f42e8 +.set CYREG_UDB_DSI2_VS5, 0x400f42ea +.set CYREG_UDB_DSI2_VS6, 0x400f42ec +.set CYREG_UDB_DSI2_VS7, 0x400f42ee +.set CYDEV_UDB_DSI3_BASE, 0x400f4300 +.set CYDEV_UDB_DSI3_SIZE, 0x00000100 +.set CYREG_UDB_DSI3_HC0, 0x400f4300 +.set CYREG_UDB_DSI3_HC1, 0x400f4301 +.set CYREG_UDB_DSI3_HC2, 0x400f4302 +.set CYREG_UDB_DSI3_HC3, 0x400f4303 +.set CYREG_UDB_DSI3_HC4, 0x400f4304 +.set CYREG_UDB_DSI3_HC5, 0x400f4305 +.set CYREG_UDB_DSI3_HC6, 0x400f4306 +.set CYREG_UDB_DSI3_HC7, 0x400f4307 +.set CYREG_UDB_DSI3_HC8, 0x400f4308 +.set CYREG_UDB_DSI3_HC9, 0x400f4309 +.set CYREG_UDB_DSI3_HC10, 0x400f430a +.set CYREG_UDB_DSI3_HC11, 0x400f430b +.set CYREG_UDB_DSI3_HC12, 0x400f430c +.set CYREG_UDB_DSI3_HC13, 0x400f430d +.set CYREG_UDB_DSI3_HC14, 0x400f430e +.set CYREG_UDB_DSI3_HC15, 0x400f430f +.set CYREG_UDB_DSI3_HC16, 0x400f4310 +.set CYREG_UDB_DSI3_HC17, 0x400f4311 +.set CYREG_UDB_DSI3_HC18, 0x400f4312 +.set CYREG_UDB_DSI3_HC19, 0x400f4313 +.set CYREG_UDB_DSI3_HC20, 0x400f4314 +.set CYREG_UDB_DSI3_HC21, 0x400f4315 +.set CYREG_UDB_DSI3_HC22, 0x400f4316 +.set CYREG_UDB_DSI3_HC23, 0x400f4317 +.set CYREG_UDB_DSI3_HC24, 0x400f4318 +.set CYREG_UDB_DSI3_HC25, 0x400f4319 +.set CYREG_UDB_DSI3_HC26, 0x400f431a +.set CYREG_UDB_DSI3_HC27, 0x400f431b +.set CYREG_UDB_DSI3_HC28, 0x400f431c +.set CYREG_UDB_DSI3_HC29, 0x400f431d +.set CYREG_UDB_DSI3_HC30, 0x400f431e +.set CYREG_UDB_DSI3_HC31, 0x400f431f +.set CYREG_UDB_DSI3_HC32, 0x400f4320 +.set CYREG_UDB_DSI3_HC33, 0x400f4321 +.set CYREG_UDB_DSI3_HC34, 0x400f4322 +.set CYREG_UDB_DSI3_HC35, 0x400f4323 +.set CYREG_UDB_DSI3_HC36, 0x400f4324 +.set CYREG_UDB_DSI3_HC37, 0x400f4325 +.set CYREG_UDB_DSI3_HC38, 0x400f4326 +.set CYREG_UDB_DSI3_HC39, 0x400f4327 +.set CYREG_UDB_DSI3_HC40, 0x400f4328 +.set CYREG_UDB_DSI3_HC41, 0x400f4329 +.set CYREG_UDB_DSI3_HC42, 0x400f432a +.set CYREG_UDB_DSI3_HC43, 0x400f432b +.set CYREG_UDB_DSI3_HC44, 0x400f432c +.set CYREG_UDB_DSI3_HC45, 0x400f432d +.set CYREG_UDB_DSI3_HC46, 0x400f432e +.set CYREG_UDB_DSI3_HC47, 0x400f432f +.set CYREG_UDB_DSI3_HC48, 0x400f4330 +.set CYREG_UDB_DSI3_HC49, 0x400f4331 +.set CYREG_UDB_DSI3_HC50, 0x400f4332 +.set CYREG_UDB_DSI3_HC51, 0x400f4333 +.set CYREG_UDB_DSI3_HC52, 0x400f4334 +.set CYREG_UDB_DSI3_HC53, 0x400f4335 +.set CYREG_UDB_DSI3_HC54, 0x400f4336 +.set CYREG_UDB_DSI3_HC55, 0x400f4337 +.set CYREG_UDB_DSI3_HC56, 0x400f4338 +.set CYREG_UDB_DSI3_HC57, 0x400f4339 +.set CYREG_UDB_DSI3_HC58, 0x400f433a +.set CYREG_UDB_DSI3_HC59, 0x400f433b +.set CYREG_UDB_DSI3_HC60, 0x400f433c +.set CYREG_UDB_DSI3_HC61, 0x400f433d +.set CYREG_UDB_DSI3_HC62, 0x400f433e +.set CYREG_UDB_DSI3_HC63, 0x400f433f +.set CYREG_UDB_DSI3_HC64, 0x400f4340 +.set CYREG_UDB_DSI3_HC65, 0x400f4341 +.set CYREG_UDB_DSI3_HC66, 0x400f4342 +.set CYREG_UDB_DSI3_HC67, 0x400f4343 +.set CYREG_UDB_DSI3_HC68, 0x400f4344 +.set CYREG_UDB_DSI3_HC69, 0x400f4345 +.set CYREG_UDB_DSI3_HC70, 0x400f4346 +.set CYREG_UDB_DSI3_HC71, 0x400f4347 +.set CYREG_UDB_DSI3_HC72, 0x400f4348 +.set CYREG_UDB_DSI3_HC73, 0x400f4349 +.set CYREG_UDB_DSI3_HC74, 0x400f434a +.set CYREG_UDB_DSI3_HC75, 0x400f434b +.set CYREG_UDB_DSI3_HC76, 0x400f434c +.set CYREG_UDB_DSI3_HC77, 0x400f434d +.set CYREG_UDB_DSI3_HC78, 0x400f434e +.set CYREG_UDB_DSI3_HC79, 0x400f434f +.set CYREG_UDB_DSI3_HC80, 0x400f4350 +.set CYREG_UDB_DSI3_HC81, 0x400f4351 +.set CYREG_UDB_DSI3_HC82, 0x400f4352 +.set CYREG_UDB_DSI3_HC83, 0x400f4353 +.set CYREG_UDB_DSI3_HC84, 0x400f4354 +.set CYREG_UDB_DSI3_HC85, 0x400f4355 +.set CYREG_UDB_DSI3_HC86, 0x400f4356 +.set CYREG_UDB_DSI3_HC87, 0x400f4357 +.set CYREG_UDB_DSI3_HC88, 0x400f4358 +.set CYREG_UDB_DSI3_HC89, 0x400f4359 +.set CYREG_UDB_DSI3_HC90, 0x400f435a +.set CYREG_UDB_DSI3_HC91, 0x400f435b +.set CYREG_UDB_DSI3_HC92, 0x400f435c +.set CYREG_UDB_DSI3_HC93, 0x400f435d +.set CYREG_UDB_DSI3_HC94, 0x400f435e +.set CYREG_UDB_DSI3_HC95, 0x400f435f +.set CYREG_UDB_DSI3_HC96, 0x400f4360 +.set CYREG_UDB_DSI3_HC97, 0x400f4361 +.set CYREG_UDB_DSI3_HC98, 0x400f4362 +.set CYREG_UDB_DSI3_HC99, 0x400f4363 +.set CYREG_UDB_DSI3_HC100, 0x400f4364 +.set CYREG_UDB_DSI3_HC101, 0x400f4365 +.set CYREG_UDB_DSI3_HC102, 0x400f4366 +.set CYREG_UDB_DSI3_HC103, 0x400f4367 +.set CYREG_UDB_DSI3_HC104, 0x400f4368 +.set CYREG_UDB_DSI3_HC105, 0x400f4369 +.set CYREG_UDB_DSI3_HC106, 0x400f436a +.set CYREG_UDB_DSI3_HC107, 0x400f436b +.set CYREG_UDB_DSI3_HC108, 0x400f436c +.set CYREG_UDB_DSI3_HC109, 0x400f436d +.set CYREG_UDB_DSI3_HC110, 0x400f436e +.set CYREG_UDB_DSI3_HC111, 0x400f436f +.set CYREG_UDB_DSI3_HC112, 0x400f4370 +.set CYREG_UDB_DSI3_HC113, 0x400f4371 +.set CYREG_UDB_DSI3_HC114, 0x400f4372 +.set CYREG_UDB_DSI3_HC115, 0x400f4373 +.set CYREG_UDB_DSI3_HC116, 0x400f4374 +.set CYREG_UDB_DSI3_HC117, 0x400f4375 +.set CYREG_UDB_DSI3_HC118, 0x400f4376 +.set CYREG_UDB_DSI3_HC119, 0x400f4377 +.set CYREG_UDB_DSI3_HC120, 0x400f4378 +.set CYREG_UDB_DSI3_HC121, 0x400f4379 +.set CYREG_UDB_DSI3_HC122, 0x400f437a +.set CYREG_UDB_DSI3_HC123, 0x400f437b +.set CYREG_UDB_DSI3_HC124, 0x400f437c +.set CYREG_UDB_DSI3_HC125, 0x400f437d +.set CYREG_UDB_DSI3_HC126, 0x400f437e +.set CYREG_UDB_DSI3_HC127, 0x400f437f +.set CYREG_UDB_DSI3_HV_L0, 0x400f4380 +.set CYREG_UDB_DSI3_HV_L1, 0x400f4381 +.set CYREG_UDB_DSI3_HV_L2, 0x400f4382 +.set CYREG_UDB_DSI3_HV_L3, 0x400f4383 +.set CYREG_UDB_DSI3_HV_L4, 0x400f4384 +.set CYREG_UDB_DSI3_HV_L5, 0x400f4385 +.set CYREG_UDB_DSI3_HV_L6, 0x400f4386 +.set CYREG_UDB_DSI3_HV_L7, 0x400f4387 +.set CYREG_UDB_DSI3_HV_L8, 0x400f4388 +.set CYREG_UDB_DSI3_HV_L9, 0x400f4389 +.set CYREG_UDB_DSI3_HV_L10, 0x400f438a +.set CYREG_UDB_DSI3_HV_L11, 0x400f438b +.set CYREG_UDB_DSI3_HV_L12, 0x400f438c +.set CYREG_UDB_DSI3_HV_L13, 0x400f438d +.set CYREG_UDB_DSI3_HV_L14, 0x400f438e +.set CYREG_UDB_DSI3_HV_L15, 0x400f438f +.set CYREG_UDB_DSI3_HS0, 0x400f4390 +.set CYREG_UDB_DSI3_HS1, 0x400f4391 +.set CYREG_UDB_DSI3_HS2, 0x400f4392 +.set CYREG_UDB_DSI3_HS3, 0x400f4393 +.set CYREG_UDB_DSI3_HS4, 0x400f4394 +.set CYREG_UDB_DSI3_HS5, 0x400f4395 +.set CYREG_UDB_DSI3_HS6, 0x400f4396 +.set CYREG_UDB_DSI3_HS7, 0x400f4397 +.set CYREG_UDB_DSI3_HS8, 0x400f4398 +.set CYREG_UDB_DSI3_HS9, 0x400f4399 +.set CYREG_UDB_DSI3_HS10, 0x400f439a +.set CYREG_UDB_DSI3_HS11, 0x400f439b +.set CYREG_UDB_DSI3_HS12, 0x400f439c +.set CYREG_UDB_DSI3_HS13, 0x400f439d +.set CYREG_UDB_DSI3_HS14, 0x400f439e +.set CYREG_UDB_DSI3_HS15, 0x400f439f +.set CYREG_UDB_DSI3_HS16, 0x400f43a0 +.set CYREG_UDB_DSI3_HS17, 0x400f43a1 +.set CYREG_UDB_DSI3_HS18, 0x400f43a2 +.set CYREG_UDB_DSI3_HS19, 0x400f43a3 +.set CYREG_UDB_DSI3_HS20, 0x400f43a4 +.set CYREG_UDB_DSI3_HS21, 0x400f43a5 +.set CYREG_UDB_DSI3_HS22, 0x400f43a6 +.set CYREG_UDB_DSI3_HS23, 0x400f43a7 +.set CYREG_UDB_DSI3_HV_R0, 0x400f43a8 +.set CYREG_UDB_DSI3_HV_R1, 0x400f43a9 +.set CYREG_UDB_DSI3_HV_R2, 0x400f43aa +.set CYREG_UDB_DSI3_HV_R3, 0x400f43ab +.set CYREG_UDB_DSI3_HV_R4, 0x400f43ac +.set CYREG_UDB_DSI3_HV_R5, 0x400f43ad +.set CYREG_UDB_DSI3_HV_R6, 0x400f43ae +.set CYREG_UDB_DSI3_HV_R7, 0x400f43af +.set CYREG_UDB_DSI3_HV_R8, 0x400f43b0 +.set CYREG_UDB_DSI3_HV_R9, 0x400f43b1 +.set CYREG_UDB_DSI3_HV_R10, 0x400f43b2 +.set CYREG_UDB_DSI3_HV_R11, 0x400f43b3 +.set CYREG_UDB_DSI3_HV_R12, 0x400f43b4 +.set CYREG_UDB_DSI3_HV_R13, 0x400f43b5 +.set CYREG_UDB_DSI3_HV_R14, 0x400f43b6 +.set CYREG_UDB_DSI3_HV_R15, 0x400f43b7 +.set CYREG_UDB_DSI3_DSIINP0, 0x400f43c0 +.set CYREG_UDB_DSI3_DSIINP1, 0x400f43c2 +.set CYREG_UDB_DSI3_DSIINP2, 0x400f43c4 +.set CYREG_UDB_DSI3_DSIINP3, 0x400f43c6 +.set CYREG_UDB_DSI3_DSIINP4, 0x400f43c8 +.set CYREG_UDB_DSI3_DSIINP5, 0x400f43ca +.set CYREG_UDB_DSI3_DSIOUTP0, 0x400f43cc +.set CYREG_UDB_DSI3_DSIOUTP1, 0x400f43ce +.set CYREG_UDB_DSI3_DSIOUTP2, 0x400f43d0 +.set CYREG_UDB_DSI3_DSIOUTP3, 0x400f43d2 +.set CYREG_UDB_DSI3_DSIOUTT0, 0x400f43d4 +.set CYREG_UDB_DSI3_DSIOUTT1, 0x400f43d6 +.set CYREG_UDB_DSI3_DSIOUTT2, 0x400f43d8 +.set CYREG_UDB_DSI3_DSIOUTT3, 0x400f43da +.set CYREG_UDB_DSI3_DSIOUTT4, 0x400f43dc +.set CYREG_UDB_DSI3_DSIOUTT5, 0x400f43de +.set CYREG_UDB_DSI3_VS0, 0x400f43e0 +.set CYREG_UDB_DSI3_VS1, 0x400f43e2 +.set CYREG_UDB_DSI3_VS2, 0x400f43e4 +.set CYREG_UDB_DSI3_VS3, 0x400f43e6 +.set CYREG_UDB_DSI3_VS4, 0x400f43e8 +.set CYREG_UDB_DSI3_VS5, 0x400f43ea +.set CYREG_UDB_DSI3_VS6, 0x400f43ec +.set CYREG_UDB_DSI3_VS7, 0x400f43ee +.set CYDEV_UDB_PA0_BASE, 0x400f5000 +.set CYDEV_UDB_PA0_SIZE, 0x00000010 +.set CYREG_UDB_PA0_CFG0, 0x400f5000 +.set CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_OFF, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_ON, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL, 0x00000003 +.set CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_CLKIN_EN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_EN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_EN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_CLKIN_INV__OFFSET, 0x00000005 +.set CYFLD_UDB_PA_CLKIN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_NC__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_NC__SIZE, 0x00000002 +.set CYREG_UDB_PA0_CFG1, 0x400f5001 +.set CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_ON, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL, 0x00000003 +.set CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_EN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_CLKOUT_INV__OFFSET, 0x00000005 +.set CYFLD_UDB_PA_CLKOUT_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_INV_INV, 0x00000001 +.set CYREG_UDB_PA0_CFG2, 0x400f5002 +.set CYFLD_UDB_PA_CLKIN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_CLKIN_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_PA_CLKIN_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP, 0x00000009 +.set CYVAL_UDB_PA_CLKIN_SEL_PIN_RC, 0x0000000c +.set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0, 0x0000000d +.set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1, 0x0000000e +.set CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2, 0x0000000f +.set CYFLD_UDB_PA_CLKOUT_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_CLKOUT_SEL__SIZE, 0x00000004 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK0, 0x00000000 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK1, 0x00000001 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK2, 0x00000002 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK3, 0x00000003 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK4, 0x00000004 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK5, 0x00000005 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK6, 0x00000006 +.set CYVAL_UDB_PA_CLKOUT_SEL_GCLK7, 0x00000007 +.set CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP, 0x00000009 +.set CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC, 0x0000000c +.set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0, 0x0000000d +.set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1, 0x0000000e +.set CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2, 0x0000000f +.set CYREG_UDB_PA0_CFG3, 0x400f5003 +.set CYFLD_UDB_PA_RES_IN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_RES_IN_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_RES_IN_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_RES_IN_INV__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_RES_IN_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_IN_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_RES_IN_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_NC0__OFFSET, 0x00000003 +.set CYFLD_UDB_PA_NC0__SIZE, 0x00000001 +.set CYFLD_UDB_PA_RES_OUT_SEL__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_RES_OUT_SEL__SIZE, 0x00000002 +.set CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC, 0x00000000 +.set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0, 0x00000001 +.set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1, 0x00000002 +.set CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2, 0x00000003 +.set CYFLD_UDB_PA_RES_OUT_INV__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_RES_OUT_INV__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_OUT_INV_NOINV, 0x00000000 +.set CYVAL_UDB_PA_RES_OUT_INV_INV, 0x00000001 +.set CYFLD_UDB_PA_NC7__OFFSET, 0x00000007 +.set CYFLD_UDB_PA_NC7__SIZE, 0x00000001 +.set CYREG_UDB_PA0_CFG4, 0x400f5004 +.set CYFLD_UDB_PA_RES_IN_EN__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_RES_IN_EN__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_IN_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_PA_RES_IN_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_PA_RES_OUT_EN__OFFSET, 0x00000001 +.set CYFLD_UDB_PA_RES_OUT_EN__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_OUT_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_PA_RES_OUT_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_PA_RES_OE_EN__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_RES_OE_EN__SIZE, 0x00000001 +.set CYVAL_UDB_PA_RES_OE_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_PA_RES_OE_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_PA_NC7654__OFFSET, 0x00000003 +.set CYFLD_UDB_PA_NC7654__SIZE, 0x00000005 +.set CYREG_UDB_PA0_CFG5, 0x400f5005 +.set CYFLD_UDB_PA_PIN_SEL__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_PIN_SEL__SIZE, 0x00000001 +.set CYVAL_UDB_PA_PIN_SEL_PIN0, 0x00000000 +.set CYVAL_UDB_PA_PIN_SEL_PIN1, 0x00000001 +.set CYVAL_UDB_PA_PIN_SEL_PIN2, 0x00000002 +.set CYVAL_UDB_PA_PIN_SEL_PIN3, 0x00000003 +.set CYVAL_UDB_PA_PIN_SEL_PIN4, 0x00000004 +.set CYVAL_UDB_PA_PIN_SEL_PIN5, 0x00000005 +.set CYVAL_UDB_PA_PIN_SEL_PIN6, 0x00000006 +.set CYVAL_UDB_PA_PIN_SEL_PIN7, 0x00000007 +.set CYREG_UDB_PA0_CFG6, 0x400f5006 +.set CYFLD_UDB_PA_IN_SYNC0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_IN_SYNC0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC0_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_IN_SYNC1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC1_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_IN_SYNC2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC2_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_IN_SYNC3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC3_RSVD, 0x00000003 +.set CYREG_UDB_PA0_CFG7, 0x400f5007 +.set CYFLD_UDB_PA_IN_SYNC4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_IN_SYNC4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC4_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_IN_SYNC5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC5_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_IN_SYNC6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC6_RSVD, 0x00000003 +.set CYFLD_UDB_PA_IN_SYNC7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_IN_SYNC7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC, 0x00000002 +.set CYVAL_UDB_PA_IN_SYNC7_RSVD, 0x00000003 +.set CYREG_UDB_PA0_CFG8, 0x400f5008 +.set CYFLD_UDB_PA_OUT_SYNC0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OUT_SYNC0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC0_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OUT_SYNC1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC1_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OUT_SYNC2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC2_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OUT_SYNC3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC3_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV, 0x00000003 +.set CYREG_UDB_PA0_CFG9, 0x400f5009 +.set CYFLD_UDB_PA_OUT_SYNC4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OUT_SYNC4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC4_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OUT_SYNC5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC5_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OUT_SYNC6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC6_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV, 0x00000003 +.set CYFLD_UDB_PA_OUT_SYNC7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OUT_SYNC7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OUT_SYNC7_CLOCK, 0x00000002 +.set CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV, 0x00000003 +.set CYREG_UDB_PA0_CFG10, 0x400f500a +.set CYFLD_UDB_PA_DATA_SEL0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_DATA_SEL0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_DATA_SEL1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_DATA_SEL2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_DATA_SEL3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG11, 0x400f500b +.set CYFLD_UDB_PA_DATA_SEL4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_DATA_SEL4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_DATA_SEL5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_DATA_SEL6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3, 0x00000003 +.set CYFLD_UDB_PA_DATA_SEL7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_DATA_SEL7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0, 0x00000000 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1, 0x00000001 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2, 0x00000002 +.set CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG12, 0x400f500c +.set CYFLD_UDB_PA_OE_SEL0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OE_SEL0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OE_SEL1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OE_SEL2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OE_SEL3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG13, 0x400f500d +.set CYFLD_UDB_PA_OE_SEL4__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OE_SEL4__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL5__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OE_SEL5__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL6__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OE_SEL6__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3, 0x00000003 +.set CYFLD_UDB_PA_OE_SEL7__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OE_SEL7__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0, 0x00000000 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1, 0x00000001 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2, 0x00000002 +.set CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3, 0x00000003 +.set CYREG_UDB_PA0_CFG14, 0x400f500e +.set CYFLD_UDB_PA_OE_SYNC0__OFFSET, 0x00000000 +.set CYFLD_UDB_PA_OE_SYNC0__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC0_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC0_CONSTANT0, 0x00000003 +.set CYFLD_UDB_PA_OE_SYNC1__OFFSET, 0x00000002 +.set CYFLD_UDB_PA_OE_SYNC1__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC1_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC1_CONSTANT0, 0x00000003 +.set CYFLD_UDB_PA_OE_SYNC2__OFFSET, 0x00000004 +.set CYFLD_UDB_PA_OE_SYNC2__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC2_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC2_CONSTANT0, 0x00000003 +.set CYFLD_UDB_PA_OE_SYNC3__OFFSET, 0x00000006 +.set CYFLD_UDB_PA_OE_SYNC3__SIZE, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT, 0x00000000 +.set CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC, 0x00000001 +.set CYVAL_UDB_PA_OE_SYNC3_CONSTANT1, 0x00000002 +.set CYVAL_UDB_PA_OE_SYNC3_CONSTANT0, 0x00000003 +.set CYDEV_UDB_PA1_BASE, 0x400f5010 +.set CYDEV_UDB_PA1_SIZE, 0x00000010 +.set CYREG_UDB_PA1_CFG0, 0x400f5010 +.set CYREG_UDB_PA1_CFG1, 0x400f5011 +.set CYREG_UDB_PA1_CFG2, 0x400f5012 +.set CYREG_UDB_PA1_CFG3, 0x400f5013 +.set CYREG_UDB_PA1_CFG4, 0x400f5014 +.set CYREG_UDB_PA1_CFG5, 0x400f5015 +.set CYREG_UDB_PA1_CFG6, 0x400f5016 +.set CYREG_UDB_PA1_CFG7, 0x400f5017 +.set CYREG_UDB_PA1_CFG8, 0x400f5018 +.set CYREG_UDB_PA1_CFG9, 0x400f5019 +.set CYREG_UDB_PA1_CFG10, 0x400f501a +.set CYREG_UDB_PA1_CFG11, 0x400f501b +.set CYREG_UDB_PA1_CFG12, 0x400f501c +.set CYREG_UDB_PA1_CFG13, 0x400f501d +.set CYREG_UDB_PA1_CFG14, 0x400f501e +.set CYDEV_UDB_PA2_BASE, 0x400f5020 +.set CYDEV_UDB_PA2_SIZE, 0x00000010 +.set CYREG_UDB_PA2_CFG0, 0x400f5020 +.set CYREG_UDB_PA2_CFG1, 0x400f5021 +.set CYREG_UDB_PA2_CFG2, 0x400f5022 +.set CYREG_UDB_PA2_CFG3, 0x400f5023 +.set CYREG_UDB_PA2_CFG4, 0x400f5024 +.set CYREG_UDB_PA2_CFG5, 0x400f5025 +.set CYREG_UDB_PA2_CFG6, 0x400f5026 +.set CYREG_UDB_PA2_CFG7, 0x400f5027 +.set CYREG_UDB_PA2_CFG8, 0x400f5028 +.set CYREG_UDB_PA2_CFG9, 0x400f5029 +.set CYREG_UDB_PA2_CFG10, 0x400f502a +.set CYREG_UDB_PA2_CFG11, 0x400f502b +.set CYREG_UDB_PA2_CFG12, 0x400f502c +.set CYREG_UDB_PA2_CFG13, 0x400f502d +.set CYREG_UDB_PA2_CFG14, 0x400f502e +.set CYDEV_UDB_PA3_BASE, 0x400f5030 +.set CYDEV_UDB_PA3_SIZE, 0x00000010 +.set CYREG_UDB_PA3_CFG0, 0x400f5030 +.set CYREG_UDB_PA3_CFG1, 0x400f5031 +.set CYREG_UDB_PA3_CFG2, 0x400f5032 +.set CYREG_UDB_PA3_CFG3, 0x400f5033 +.set CYREG_UDB_PA3_CFG4, 0x400f5034 +.set CYREG_UDB_PA3_CFG5, 0x400f5035 +.set CYREG_UDB_PA3_CFG6, 0x400f5036 +.set CYREG_UDB_PA3_CFG7, 0x400f5037 +.set CYREG_UDB_PA3_CFG8, 0x400f5038 +.set CYREG_UDB_PA3_CFG9, 0x400f5039 +.set CYREG_UDB_PA3_CFG10, 0x400f503a +.set CYREG_UDB_PA3_CFG11, 0x400f503b +.set CYREG_UDB_PA3_CFG12, 0x400f503c +.set CYREG_UDB_PA3_CFG13, 0x400f503d +.set CYREG_UDB_PA3_CFG14, 0x400f503e +.set CYDEV_UDB_BCTL0_BASE, 0x400f6000 +.set CYDEV_UDB_BCTL0_SIZE, 0x00001000 +.set CYREG_UDB_BCTL0_DRV, 0x400f6000 +.set CYFLD_UDB_BCTL0_DRV__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_DRV__SIZE, 0x00000008 +.set CYVAL_UDB_BCTL0_DRV_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DRV_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_MDCLK_EN, 0x400f6001 +.set CYFLD_UDB_BCTL0_DCEN__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_DCEN__SIZE, 0x00000008 +.set CYVAL_UDB_BCTL0_DCEN_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DCEN_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_MBCLK_EN, 0x400f6002 +.set CYFLD_UDB_BCTL0_BCEN__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_BCEN__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_BCEN_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_BCEN_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_BOTSEL_L, 0x400f6008 +.set CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_CLK_SEL0__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET, 0x00000002 +.set CYFLD_UDB_BCTL0_CLK_SEL1__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET, 0x00000004 +.set CYFLD_UDB_BCTL0_CLK_SEL2__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET, 0x00000006 +.set CYFLD_UDB_BCTL0_CLK_SEL3__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT, 0x00000003 +.set CYREG_UDB_BCTL0_BOTSEL_U, 0x400f6009 +.set CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_CLK_SEL4__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET, 0x00000002 +.set CYFLD_UDB_BCTL0_CLK_SEL5__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET, 0x00000004 +.set CYFLD_UDB_BCTL0_CLK_SEL6__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT, 0x00000003 +.set CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET, 0x00000006 +.set CYFLD_UDB_BCTL0_CLK_SEL7__SIZE, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES, 0x00000000 +.set CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT, 0x00000001 +.set CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT, 0x00000002 +.set CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT, 0x00000003 +.set CYREG_UDB_BCTL0_TOPSEL_L, 0x400f600a +.set CYREG_UDB_BCTL0_TOPSEL_U, 0x400f600b +.set CYREG_UDB_BCTL0_QCLK_EN0, 0x400f6010 +.set CYFLD_UDB_BCTL0_DCEN_Q__OFFSET, 0x00000000 +.set CYFLD_UDB_BCTL0_DCEN_Q__SIZE, 0x00000008 +.set CYVAL_UDB_BCTL0_DCEN_Q_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DCEN_Q_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_BCEN_Q__OFFSET, 0x00000008 +.set CYFLD_UDB_BCTL0_BCEN_Q__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_BCEN_Q_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_BCEN_Q_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET, 0x00000009 +.set CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET, 0x0000000a +.set CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET, 0x0000000b +.set CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET, 0x0000000c +.set CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE, 0x00000001 +.set CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET, 0x0000000d +.set CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB, 0x00000000 +.set CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB, 0x00000001 +.set CYFLD_UDB_BCTL0_NC0__OFFSET, 0x0000000e +.set CYFLD_UDB_BCTL0_NC0__SIZE, 0x00000001 +.set CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET, 0x0000000f +.set CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE, 0x00000001 +.set CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE, 0x00000000 +.set CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE, 0x00000001 +.set CYREG_UDB_BCTL0_QCLK_EN1, 0x400f6012 +.set CYDEV_UDB_UDBIF_BASE, 0x400f7000 +.set CYDEV_UDB_UDBIF_SIZE, 0x00001000 +.set CYREG_UDB_UDBIF_BANK_CTL, 0x400f7000 +.set CYFLD_UDB_UDBIF_DIS_COR__OFFSET, 0x00000000 +.set CYFLD_UDB_UDBIF_DIS_COR__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_DIS_COR_NORMAL, 0x00000000 +.set CYVAL_UDB_UDBIF_DIS_COR_DISABLE, 0x00000001 +.set CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET, 0x00000001 +.set CYFLD_UDB_UDBIF_ROUTE_EN__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_UDBIF_BANK_EN__OFFSET, 0x00000002 +.set CYFLD_UDB_UDBIF_BANK_EN__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_BANK_EN_DISABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_BANK_EN_ENABLE, 0x00000001 +.set CYFLD_UDB_UDBIF_LOCK__OFFSET, 0x00000003 +.set CYFLD_UDB_UDBIF_LOCK__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_LOCK_MUTABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_LOCK_LOCKED, 0x00000001 +.set CYFLD_UDB_UDBIF_PIPE__OFFSET, 0x00000004 +.set CYFLD_UDB_UDBIF_PIPE__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_PIPE_BYPASS, 0x00000000 +.set CYVAL_UDB_UDBIF_PIPE_PIPELINED, 0x00000001 +.set CYFLD_UDB_UDBIF_GLBL_WR__OFFSET, 0x00000007 +.set CYFLD_UDB_UDBIF_GLBL_WR__SIZE, 0x00000001 +.set CYVAL_UDB_UDBIF_GLBL_WR_DISABLE, 0x00000000 +.set CYVAL_UDB_UDBIF_GLBL_WR_ENABLE, 0x00000001 +.set CYREG_UDB_UDBIF_WAIT_CFG, 0x400f7001 +.set CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET, 0x00000000 +.set CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS, 0x00000000 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT, 0x00000003 +.set CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET, 0x00000002 +.set CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT, 0x00000000 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS, 0x00000003 +.set CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET, 0x00000004 +.set CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT, 0x00000000 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS, 0x00000003 +.set CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET, 0x00000006 +.set CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT, 0x00000000 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS, 0x00000001 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS, 0x00000002 +.set CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS, 0x00000003 +.set CYREG_UDB_UDBIF_INT_CLK_CTL, 0x400f701c +.set CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET, 0x00000000 +.set CYFLD_UDB_UDBIF_EN_HFCLK__SIZE, 0x00000001 +.set CYREG_UDB_INT_CFG, 0x400f8000 +.set CYFLD_UDB_INT_MODE_CFG__OFFSET, 0x00000000 +.set CYFLD_UDB_INT_MODE_CFG__SIZE, 0x00000020 +.set CYVAL_UDB_INT_MODE_CFG_LEVEL, 0x00000000 +.set CYVAL_UDB_INT_MODE_CFG_PULSE, 0x00000001 +.set CYDEV_CTBM_BASE, 0x40100000 +.set CYDEV_CTBM_SIZE, 0x00010000 +.set CYREG_CTBM_CTB_CTRL, 0x40100000 +.set CYFLD_CTBM_ENABLED__OFFSET, 0x0000001f +.set CYFLD_CTBM_ENABLED__SIZE, 0x00000001 +.set CYREG_CTBM_OA_RES0_CTRL, 0x40100004 +.set CYFLD_CTBM_OA0_PWR_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_PWR_MODE__SIZE, 0x00000002 +.set CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_COMP_EN__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA0_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_HYST_EN__OFFSET, 0x00000005 +.set CYFLD_CTBM_OA0_HYST_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET, 0x00000006 +.set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_COMPINT__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA0_COMPINT__SIZE, 0x00000002 +.set CYVAL_CTBM_OA0_COMPINT_DISABLE, 0x00000000 +.set CYVAL_CTBM_OA0_COMPINT_RISING, 0x00000001 +.set CYVAL_CTBM_OA0_COMPINT_FALLING, 0x00000002 +.set CYVAL_CTBM_OA0_COMPINT_BOTH, 0x00000003 +.set CYFLD_CTBM_OA0_PUMP_EN__OFFSET, 0x0000000b +.set CYFLD_CTBM_OA0_PUMP_EN__SIZE, 0x00000001 +.set CYREG_CTBM_OA_RES1_CTRL, 0x40100008 +.set CYFLD_CTBM_OA1_PWR_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_PWR_MODE__SIZE, 0x00000002 +.set CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMP_EN__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA1_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_HYST_EN__OFFSET, 0x00000005 +.set CYFLD_CTBM_OA1_HYST_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET, 0x00000006 +.set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMPINT__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA1_COMPINT__SIZE, 0x00000002 +.set CYVAL_CTBM_OA1_COMPINT_DISABLE, 0x00000000 +.set CYVAL_CTBM_OA1_COMPINT_RISING, 0x00000001 +.set CYVAL_CTBM_OA1_COMPINT_FALLING, 0x00000002 +.set CYVAL_CTBM_OA1_COMPINT_BOTH, 0x00000003 +.set CYFLD_CTBM_OA1_PUMP_EN__OFFSET, 0x0000000b +.set CYFLD_CTBM_OA1_PUMP_EN__SIZE, 0x00000001 +.set CYREG_CTBM_COMP_STAT, 0x4010000c +.set CYFLD_CTBM_OA0_COMP__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_COMP__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMP__OFFSET, 0x00000010 +.set CYFLD_CTBM_OA1_COMP__SIZE, 0x00000001 +.set CYREG_CTBM_INTR, 0x40100020 +.set CYFLD_CTBM_COMP0__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1__SIZE, 0x00000001 +.set CYREG_CTBM_INTR_SET, 0x40100024 +.set CYFLD_CTBM_COMP0_SET__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_SET__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_SET__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_SET__SIZE, 0x00000001 +.set CYREG_CTBM_INTR_MASK, 0x40100028 +.set CYFLD_CTBM_COMP0_MASK__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_MASK__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_MASK__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_MASK__SIZE, 0x00000001 +.set CYREG_CTBM_INTR_MASKED, 0x4010002c +.set CYFLD_CTBM_COMP0_MASKED__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_MASKED__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_MASKED__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_MASKED__SIZE, 0x00000001 +.set CYREG_CTBM_DFT_CTRL, 0x40100030 +.set CYFLD_CTBM_DFT_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_DFT_MODE__SIZE, 0x00000003 +.set CYFLD_CTBM_DFT_EN__OFFSET, 0x0000001f +.set CYFLD_CTBM_DFT_EN__SIZE, 0x00000001 +.set CYREG_CTBM_OA0_SW, 0x40100080 +.set CYFLD_CTBM_OA0P_A00__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0P_A00__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0P_A20__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA0P_A20__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0P_A30__OFFSET, 0x00000003 +.set CYFLD_CTBM_OA0P_A30__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0M_A11__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA0M_A11__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0M_A81__OFFSET, 0x0000000e +.set CYFLD_CTBM_OA0M_A81__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0O_D51__OFFSET, 0x00000012 +.set CYFLD_CTBM_OA0O_D51__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0O_D81__OFFSET, 0x00000015 +.set CYFLD_CTBM_OA0O_D81__SIZE, 0x00000001 +.set CYREG_CTBM_OA0_SW_CLEAR, 0x40100084 +.set CYREG_CTBM_OA1_SW, 0x40100088 +.set CYFLD_CTBM_OA1P_A03__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1P_A03__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1P_A13__OFFSET, 0x00000001 +.set CYFLD_CTBM_OA1P_A13__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1P_A43__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA1P_A43__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1M_A22__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA1M_A22__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1M_A82__OFFSET, 0x0000000e +.set CYFLD_CTBM_OA1M_A82__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D52__OFFSET, 0x00000012 +.set CYFLD_CTBM_OA1O_D52__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D62__OFFSET, 0x00000013 +.set CYFLD_CTBM_OA1O_D62__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D82__OFFSET, 0x00000015 +.set CYFLD_CTBM_OA1O_D82__SIZE, 0x00000001 +.set CYREG_CTBM_OA1_SW_CLEAR, 0x4010008c +.set CYREG_CTBM_CTB_SW_HW_CTRL, 0x401000c0 +.set CYFLD_CTBM_P2_HW_CTRL__OFFSET, 0x00000002 +.set CYFLD_CTBM_P2_HW_CTRL__SIZE, 0x00000001 +.set CYFLD_CTBM_P3_HW_CTRL__OFFSET, 0x00000003 +.set CYFLD_CTBM_P3_HW_CTRL__SIZE, 0x00000001 +.set CYREG_CTBM_CTB_SW_STATUS, 0x401000c4 +.set CYFLD_CTBM_OA0O_D51_STAT__OFFSET, 0x0000001c +.set CYFLD_CTBM_OA0O_D51_STAT__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D52_STAT__OFFSET, 0x0000001d +.set CYFLD_CTBM_OA1O_D52_STAT__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D62_STAT__OFFSET, 0x0000001e +.set CYFLD_CTBM_OA1O_D62_STAT__SIZE, 0x00000001 +.set CYREG_CTBM_OA0_OFFSET_TRIM, 0x40100f00 +.set CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM, 0x40100f04 +.set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA0_COMP_TRIM, 0x40100f08 +.set CYFLD_CTBM_OA0_COMP_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_COMP_TRIM__SIZE, 0x00000002 +.set CYREG_CTBM_OA1_OFFSET_TRIM, 0x40100f0c +.set CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM, 0x40100f10 +.set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM_OA1_COMP_TRIM, 0x40100f14 +.set CYFLD_CTBM_OA1_COMP_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_COMP_TRIM__SIZE, 0x00000002 +.set CYDEV_SAR_BASE, 0x401a0000 +.set CYDEV_SAR_SIZE, 0x00010000 +.set CYREG_SAR_CTRL, 0x401a0000 +.set CYFLD_SAR_VREF_SEL__OFFSET, 0x00000004 +.set CYFLD_SAR_VREF_SEL__SIZE, 0x00000003 +.set CYVAL_SAR_VREF_SEL_VREF0, 0x00000000 +.set CYVAL_SAR_VREF_SEL_VREF1, 0x00000001 +.set CYVAL_SAR_VREF_SEL_VREF2, 0x00000002 +.set CYVAL_SAR_VREF_SEL_VREF_AROUTE, 0x00000003 +.set CYVAL_SAR_VREF_SEL_VBGR, 0x00000004 +.set CYVAL_SAR_VREF_SEL_VREF_EXT, 0x00000005 +.set CYVAL_SAR_VREF_SEL_VDDA_DIV_2, 0x00000006 +.set CYVAL_SAR_VREF_SEL_VDDA, 0x00000007 +.set CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET, 0x00000007 +.set CYFLD_SAR_VREF_BYP_CAP_EN__SIZE, 0x00000001 +.set CYFLD_SAR_NEG_SEL__OFFSET, 0x00000009 +.set CYFLD_SAR_NEG_SEL__SIZE, 0x00000003 +.set CYVAL_SAR_NEG_SEL_VSSA_KELVIN, 0x00000000 +.set CYVAL_SAR_NEG_SEL_ART_VSSA, 0x00000001 +.set CYVAL_SAR_NEG_SEL_P1, 0x00000002 +.set CYVAL_SAR_NEG_SEL_P3, 0x00000003 +.set CYVAL_SAR_NEG_SEL_P5, 0x00000004 +.set CYVAL_SAR_NEG_SEL_P7, 0x00000005 +.set CYVAL_SAR_NEG_SEL_ACORE, 0x00000006 +.set CYVAL_SAR_NEG_SEL_VREF, 0x00000007 +.set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET, 0x0000000d +.set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE, 0x00000001 +.set CYFLD_SAR_PWR_CTRL_VREF__OFFSET, 0x0000000e +.set CYFLD_SAR_PWR_CTRL_VREF__SIZE, 0x00000002 +.set CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR, 0x00000000 +.set CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR, 0x00000001 +.set CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR, 0x00000002 +.set CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR, 0x00000003 +.set CYFLD_SAR_SPARE__OFFSET, 0x00000010 +.set CYFLD_SAR_SPARE__SIZE, 0x00000004 +.set CYFLD_SAR_ICONT_LV__OFFSET, 0x00000018 +.set CYFLD_SAR_ICONT_LV__SIZE, 0x00000002 +.set CYVAL_SAR_ICONT_LV_NORMAL_PWR, 0x00000000 +.set CYVAL_SAR_ICONT_LV_HALF_PWR, 0x00000001 +.set CYVAL_SAR_ICONT_LV_MORE_PWR, 0x00000002 +.set CYVAL_SAR_ICONT_LV_QUARTER_PWR, 0x00000003 +.set CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET, 0x0000001c +.set CYFLD_SAR_DSI_SYNC_CONFIG__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_MODE__OFFSET, 0x0000001d +.set CYFLD_SAR_DSI_MODE__SIZE, 0x00000001 +.set CYFLD_SAR_SWITCH_DISABLE__OFFSET, 0x0000001e +.set CYFLD_SAR_SWITCH_DISABLE__SIZE, 0x00000001 +.set CYFLD_SAR_ENABLED__OFFSET, 0x0000001f +.set CYFLD_SAR_ENABLED__SIZE, 0x00000001 +.set CYREG_SAR_SAMPLE_CTRL, 0x401a0004 +.set CYFLD_SAR_SUB_RESOLUTION__OFFSET, 0x00000000 +.set CYFLD_SAR_SUB_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_SUB_RESOLUTION_8B, 0x00000000 +.set CYVAL_SAR_SUB_RESOLUTION_10B, 0x00000001 +.set CYFLD_SAR_LEFT_ALIGN__OFFSET, 0x00000001 +.set CYFLD_SAR_LEFT_ALIGN__SIZE, 0x00000001 +.set CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET, 0x00000002 +.set CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE, 0x00000001 +.set CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED, 0x00000000 +.set CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED, 0x00000001 +.set CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET, 0x00000003 +.set CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE, 0x00000001 +.set CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED, 0x00000000 +.set CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED, 0x00000001 +.set CYFLD_SAR_AVG_CNT__OFFSET, 0x00000004 +.set CYFLD_SAR_AVG_CNT__SIZE, 0x00000003 +.set CYFLD_SAR_AVG_SHIFT__OFFSET, 0x00000007 +.set CYFLD_SAR_AVG_SHIFT__SIZE, 0x00000001 +.set CYFLD_SAR_CONTINUOUS__OFFSET, 0x00000010 +.set CYFLD_SAR_CONTINUOUS__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_TRIGGER_EN__OFFSET, 0x00000011 +.set CYFLD_SAR_DSI_TRIGGER_EN__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET, 0x00000012 +.set CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET, 0x00000013 +.set CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE, 0x00000001 +.set CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_EOS_DSI_OUT_EN__SIZE, 0x00000001 +.set CYREG_SAR_SAMPLE_TIME01, 0x401a0010 +.set CYFLD_SAR_SAMPLE_TIME0__OFFSET, 0x00000000 +.set CYFLD_SAR_SAMPLE_TIME0__SIZE, 0x0000000a +.set CYFLD_SAR_SAMPLE_TIME1__OFFSET, 0x00000010 +.set CYFLD_SAR_SAMPLE_TIME1__SIZE, 0x0000000a +.set CYREG_SAR_SAMPLE_TIME23, 0x401a0014 +.set CYFLD_SAR_SAMPLE_TIME2__OFFSET, 0x00000000 +.set CYFLD_SAR_SAMPLE_TIME2__SIZE, 0x0000000a +.set CYFLD_SAR_SAMPLE_TIME3__OFFSET, 0x00000010 +.set CYFLD_SAR_SAMPLE_TIME3__SIZE, 0x0000000a +.set CYREG_SAR_RANGE_THRES, 0x401a0018 +.set CYFLD_SAR_RANGE_LOW__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_LOW__SIZE, 0x00000010 +.set CYFLD_SAR_RANGE_HIGH__OFFSET, 0x00000010 +.set CYFLD_SAR_RANGE_HIGH__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_COND, 0x401a001c +.set CYFLD_SAR_RANGE_COND__OFFSET, 0x0000001e +.set CYFLD_SAR_RANGE_COND__SIZE, 0x00000002 +.set CYVAL_SAR_RANGE_COND_BELOW, 0x00000000 +.set CYVAL_SAR_RANGE_COND_INSIDE, 0x00000001 +.set CYVAL_SAR_RANGE_COND_ABOVE, 0x00000002 +.set CYVAL_SAR_RANGE_COND_OUTSIDE, 0x00000003 +.set CYREG_SAR_CHAN_EN, 0x401a0020 +.set CYFLD_SAR_CHAN_EN__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_EN__SIZE, 0x00000010 +.set CYREG_SAR_START_CTRL, 0x401a0024 +.set CYFLD_SAR_FW_TRIGGER__OFFSET, 0x00000000 +.set CYFLD_SAR_FW_TRIGGER__SIZE, 0x00000001 +.set CYREG_SAR_DFT_CTRL, 0x401a0030 +.set CYFLD_SAR_DLY_INC__OFFSET, 0x00000000 +.set CYFLD_SAR_DLY_INC__SIZE, 0x00000001 +.set CYFLD_SAR_HIZ__OFFSET, 0x00000001 +.set CYFLD_SAR_HIZ__SIZE, 0x00000001 +.set CYFLD_SAR_DFT_INC__OFFSET, 0x00000010 +.set CYFLD_SAR_DFT_INC__SIZE, 0x00000004 +.set CYFLD_SAR_DFT_OUTC__OFFSET, 0x00000014 +.set CYFLD_SAR_DFT_OUTC__SIZE, 0x00000003 +.set CYFLD_SAR_SEL_CSEL_DFT__OFFSET, 0x00000018 +.set CYFLD_SAR_SEL_CSEL_DFT__SIZE, 0x00000004 +.set CYFLD_SAR_EN_CSEL_DFT__OFFSET, 0x0000001c +.set CYFLD_SAR_EN_CSEL_DFT__SIZE, 0x00000001 +.set CYFLD_SAR_DCEN__OFFSET, 0x0000001d +.set CYFLD_SAR_DCEN__SIZE, 0x00000001 +.set CYFLD_SAR_ADFT_OVERRIDE__OFFSET, 0x0000001f +.set CYFLD_SAR_ADFT_OVERRIDE__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_CONFIG00, 0x401a0080 +.set CYFLD_SAR_PIN_ADDR__OFFSET, 0x00000000 +.set CYFLD_SAR_PIN_ADDR__SIZE, 0x00000003 +.set CYFLD_SAR_PORT_ADDR__OFFSET, 0x00000004 +.set CYFLD_SAR_PORT_ADDR__SIZE, 0x00000003 +.set CYVAL_SAR_PORT_ADDR_SARMUX, 0x00000000 +.set CYVAL_SAR_PORT_ADDR_CTB0, 0x00000001 +.set CYVAL_SAR_PORT_ADDR_CTB1, 0x00000002 +.set CYVAL_SAR_PORT_ADDR_CTB2, 0x00000003 +.set CYVAL_SAR_PORT_ADDR_CTB3, 0x00000004 +.set CYVAL_SAR_PORT_ADDR_AROUTE_VIRT, 0x00000006 +.set CYVAL_SAR_PORT_ADDR_SARMUX_VIRT, 0x00000007 +.set CYFLD_SAR_DIFFERENTIAL_EN__OFFSET, 0x00000008 +.set CYFLD_SAR_DIFFERENTIAL_EN__SIZE, 0x00000001 +.set CYFLD_SAR_RESOLUTION__OFFSET, 0x00000009 +.set CYFLD_SAR_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_RESOLUTION_12B, 0x00000000 +.set CYVAL_SAR_RESOLUTION_SUBRES, 0x00000001 +.set CYFLD_SAR_AVG_EN__OFFSET, 0x0000000a +.set CYFLD_SAR_AVG_EN__SIZE, 0x00000001 +.set CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET, 0x0000000c +.set CYFLD_SAR_SAMPLE_TIME_SEL__SIZE, 0x00000002 +.set CYFLD_SAR_DSI_OUT_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_DSI_OUT_EN__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_CONFIG01, 0x401a0084 +.set CYREG_SAR_CHAN_CONFIG02, 0x401a0088 +.set CYREG_SAR_CHAN_CONFIG03, 0x401a008c +.set CYREG_SAR_CHAN_CONFIG04, 0x401a0090 +.set CYREG_SAR_CHAN_CONFIG05, 0x401a0094 +.set CYREG_SAR_CHAN_CONFIG06, 0x401a0098 +.set CYREG_SAR_CHAN_CONFIG07, 0x401a009c +.set CYREG_SAR_CHAN_WORK00, 0x401a0100 +.set CYFLD_SAR_WORK__OFFSET, 0x00000000 +.set CYFLD_SAR_WORK__SIZE, 0x00000010 +.set CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_WORK01, 0x401a0104 +.set CYREG_SAR_CHAN_WORK02, 0x401a0108 +.set CYREG_SAR_CHAN_WORK03, 0x401a010c +.set CYREG_SAR_CHAN_WORK04, 0x401a0110 +.set CYREG_SAR_CHAN_WORK05, 0x401a0114 +.set CYREG_SAR_CHAN_WORK06, 0x401a0118 +.set CYREG_SAR_CHAN_WORK07, 0x401a011c +.set CYREG_SAR_CHAN_RESULT00, 0x401a0180 +.set CYFLD_SAR_RESULT__OFFSET, 0x00000000 +.set CYFLD_SAR_RESULT__SIZE, 0x00000010 +.set CYFLD_SAR_SATURATE_INTR_MIR__OFFSET, 0x0000001d +.set CYFLD_SAR_SATURATE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_RANGE_INTR_MIR__OFFSET, 0x0000001e +.set CYFLD_SAR_RANGE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_RESULT01, 0x401a0184 +.set CYREG_SAR_CHAN_RESULT02, 0x401a0188 +.set CYREG_SAR_CHAN_RESULT03, 0x401a018c +.set CYREG_SAR_CHAN_RESULT04, 0x401a0190 +.set CYREG_SAR_CHAN_RESULT05, 0x401a0194 +.set CYREG_SAR_CHAN_RESULT06, 0x401a0198 +.set CYREG_SAR_CHAN_RESULT07, 0x401a019c +.set CYREG_SAR_CHAN_WORK_VALID, 0x401a0200 +.set CYFLD_SAR_CHAN_WORK_VALID__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_WORK_VALID__SIZE, 0x00000010 +.set CYREG_SAR_CHAN_RESULT_VALID, 0x401a0204 +.set CYFLD_SAR_CHAN_RESULT_VALID__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_RESULT_VALID__SIZE, 0x00000010 +.set CYREG_SAR_STATUS, 0x401a0208 +.set CYFLD_SAR_CUR_CHAN__OFFSET, 0x00000000 +.set CYFLD_SAR_CUR_CHAN__SIZE, 0x00000005 +.set CYFLD_SAR_SW_VREF_NEG__OFFSET, 0x0000001e +.set CYFLD_SAR_SW_VREF_NEG__SIZE, 0x00000001 +.set CYFLD_SAR_BUSY__OFFSET, 0x0000001f +.set CYFLD_SAR_BUSY__SIZE, 0x00000001 +.set CYREG_SAR_AVG_STAT, 0x401a020c +.set CYFLD_SAR_CUR_AVG_ACCU__OFFSET, 0x00000000 +.set CYFLD_SAR_CUR_AVG_ACCU__SIZE, 0x00000014 +.set CYFLD_SAR_CUR_AVG_CNT__OFFSET, 0x00000018 +.set CYFLD_SAR_CUR_AVG_CNT__SIZE, 0x00000008 +.set CYREG_SAR_INTR, 0x401a0210 +.set CYFLD_SAR_EOS_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_INTR__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_INTR__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_INTR__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_INTR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_INTR__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_INTR__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_INTR__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_INTR__SIZE, 0x00000001 +.set CYREG_SAR_INTR_SET, 0x401a0214 +.set CYFLD_SAR_EOS_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_SET__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_SET__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_SET__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_SET__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_SET__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_SET__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_SET__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_SET__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_SET__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_SET__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_SET__SIZE, 0x00000001 +.set CYREG_SAR_INTR_MASK, 0x401a0218 +.set CYFLD_SAR_EOS_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASK__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASK__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASK__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASK__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASK__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASK__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASK__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASK__SIZE, 0x00000001 +.set CYREG_SAR_INTR_MASKED, 0x401a021c +.set CYFLD_SAR_EOS_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASKED__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASKED__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASKED__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASKED__SIZE, 0x00000001 +.set CYREG_SAR_SATURATE_INTR, 0x401a0220 +.set CYFLD_SAR_SATURATE_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_INTR__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_SET, 0x401a0224 +.set CYFLD_SAR_SATURATE_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_SET__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_MASK, 0x401a0228 +.set CYFLD_SAR_SATURATE_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_MASK__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_MASKED, 0x401a022c +.set CYFLD_SAR_SATURATE_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_MASKED__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR, 0x401a0230 +.set CYFLD_SAR_RANGE_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_INTR__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_SET, 0x401a0234 +.set CYFLD_SAR_RANGE_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_SET__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_MASK, 0x401a0238 +.set CYFLD_SAR_RANGE_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_MASK__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_MASKED, 0x401a023c +.set CYFLD_SAR_RANGE_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_MASKED__SIZE, 0x00000010 +.set CYREG_SAR_INTR_CAUSE, 0x401a0240 +.set CYFLD_SAR_EOS_MASKED_MIR__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_SATURATE_MASKED_RED__OFFSET, 0x0000001e +.set CYFLD_SAR_SATURATE_MASKED_RED__SIZE, 0x00000001 +.set CYFLD_SAR_RANGE_MASKED_RED__OFFSET, 0x0000001f +.set CYFLD_SAR_RANGE_MASKED_RED__SIZE, 0x00000001 +.set CYREG_SAR_INJ_CHAN_CONFIG, 0x401a0280 +.set CYFLD_SAR_INJ_PIN_ADDR__OFFSET, 0x00000000 +.set CYFLD_SAR_INJ_PIN_ADDR__SIZE, 0x00000003 +.set CYFLD_SAR_INJ_PORT_ADDR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_PORT_ADDR__SIZE, 0x00000003 +.set CYVAL_SAR_INJ_PORT_ADDR_SARMUX, 0x00000000 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB0, 0x00000001 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB1, 0x00000002 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB2, 0x00000003 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB3, 0x00000004 +.set CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT, 0x00000006 +.set CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT, 0x00000007 +.set CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET, 0x00000008 +.set CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RESOLUTION__OFFSET, 0x00000009 +.set CYFLD_SAR_INJ_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_INJ_RESOLUTION_12B, 0x00000000 +.set CYVAL_SAR_INJ_RESOLUTION_SUBRES, 0x00000001 +.set CYFLD_SAR_INJ_AVG_EN__OFFSET, 0x0000000a +.set CYFLD_SAR_INJ_AVG_EN__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET, 0x0000000c +.set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE, 0x00000002 +.set CYFLD_SAR_INJ_TAILGATING__OFFSET, 0x0000001e +.set CYFLD_SAR_INJ_TAILGATING__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_START_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_INJ_START_EN__SIZE, 0x00000001 +.set CYREG_SAR_INJ_RESULT, 0x401a0290 +.set CYFLD_SAR_INJ_RESULT__OFFSET, 0x00000000 +.set CYFLD_SAR_INJ_RESULT__SIZE, 0x00000010 +.set CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET, 0x0000001c +.set CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET, 0x0000001d +.set CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET, 0x0000001e +.set CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH0, 0x401a0300 +.set CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET, 0x00000004 +.set CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET, 0x00000005 +.set CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET, 0x00000006 +.set CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET, 0x00000007 +.set CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET, 0x00000008 +.set CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET, 0x00000009 +.set CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET, 0x0000000a +.set CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET, 0x0000000b +.set CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET, 0x0000000c +.set CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET, 0x0000000d +.set CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET, 0x0000000e +.set CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET, 0x0000000f +.set CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET, 0x00000010 +.set CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET, 0x00000011 +.set CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET, 0x00000012 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET, 0x00000013 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET, 0x00000014 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET, 0x00000015 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET, 0x00000016 +.set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET, 0x00000017 +.set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET, 0x00000018 +.set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET, 0x00000019 +.set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET, 0x0000001a +.set CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET, 0x0000001b +.set CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET, 0x0000001c +.set CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET, 0x0000001d +.set CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_CLEAR0, 0x401a0304 +.set CYREG_SAR_MUX_SWITCH1, 0x401a0308 +.set CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_CLEAR1, 0x401a030c +.set CYREG_SAR_MUX_SWITCH_HW_CTRL, 0x401a0340 +.set CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_HW_CTRL_P0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P1__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_HW_CTRL_P2__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_HW_CTRL_P3__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET, 0x00000004 +.set CYFLD_SAR_MUX_HW_CTRL_P4__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET, 0x00000005 +.set CYFLD_SAR_MUX_HW_CTRL_P5__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET, 0x00000006 +.set CYFLD_SAR_MUX_HW_CTRL_P6__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET, 0x00000007 +.set CYFLD_SAR_MUX_HW_CTRL_P7__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET, 0x00000010 +.set CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET, 0x00000011 +.set CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET, 0x00000012 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET, 0x00000013 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET, 0x00000016 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET, 0x00000017 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_STATUS, 0x401a0348 +.set CYREG_SAR_PUMP_CTRL, 0x401a0380 +.set CYFLD_SAR_CLOCK_SEL__OFFSET, 0x00000000 +.set CYFLD_SAR_CLOCK_SEL__SIZE, 0x00000001 +.set CYREG_SAR_ANA_TRIM, 0x401a0f00 +.set CYFLD_SAR_CAP_TRIM__OFFSET, 0x00000000 +.set CYFLD_SAR_CAP_TRIM__SIZE, 0x00000003 +.set CYFLD_SAR_TRIMUNIT__OFFSET, 0x00000003 +.set CYFLD_SAR_TRIMUNIT__SIZE, 0x00000001 +.set CYREG_SAR_WOUNDING, 0x401a0f04 +.set CYFLD_SAR_WOUND_RESOLUTION__OFFSET, 0x00000000 +.set CYFLD_SAR_WOUND_RESOLUTION__SIZE, 0x00000002 +.set CYVAL_SAR_WOUND_RESOLUTION_12BIT, 0x00000000 +.set CYVAL_SAR_WOUND_RESOLUTION_10BIT, 0x00000001 +.set CYVAL_SAR_WOUND_RESOLUTION_8BIT, 0x00000002 +.set CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO, 0x00000003 +.set CYDEV_CM0_BASE, 0xe0000000 +.set CYDEV_CM0_SIZE, 0x00100000 +.set CYREG_CM0_DWT_PID4, 0xe0001fd0 +.set CYFLD_CM0_VALUE__OFFSET, 0x00000000 +.set CYFLD_CM0_VALUE__SIZE, 0x00000020 +.set CYREG_CM0_DWT_PID0, 0xe0001fe0 +.set CYREG_CM0_DWT_PID1, 0xe0001fe4 +.set CYREG_CM0_DWT_PID2, 0xe0001fe8 +.set CYREG_CM0_DWT_PID3, 0xe0001fec +.set CYREG_CM0_DWT_CID0, 0xe0001ff0 +.set CYREG_CM0_DWT_CID1, 0xe0001ff4 +.set CYREG_CM0_DWT_CID2, 0xe0001ff8 +.set CYREG_CM0_DWT_CID3, 0xe0001ffc +.set CYREG_CM0_BP_PID4, 0xe0002fd0 +.set CYREG_CM0_BP_PID0, 0xe0002fe0 +.set CYREG_CM0_BP_PID1, 0xe0002fe4 +.set CYREG_CM0_BP_PID2, 0xe0002fe8 +.set CYREG_CM0_BP_PID3, 0xe0002fec +.set CYREG_CM0_BP_CID0, 0xe0002ff0 +.set CYREG_CM0_BP_CID1, 0xe0002ff4 +.set CYREG_CM0_BP_CID2, 0xe0002ff8 +.set CYREG_CM0_BP_CID3, 0xe0002ffc +.set CYREG_CM0_SYST_CSR, 0xe000e010 +.set CYFLD_CM0_ENABLE__OFFSET, 0x00000000 +.set CYFLD_CM0_ENABLE__SIZE, 0x00000001 +.set CYFLD_CM0_TICKINT__OFFSET, 0x00000001 +.set CYFLD_CM0_TICKINT__SIZE, 0x00000001 +.set CYFLD_CM0_CLKSOURCE__OFFSET, 0x00000002 +.set CYFLD_CM0_CLKSOURCE__SIZE, 0x00000001 +.set CYFLD_CM0_COUNTFLAG__OFFSET, 0x00000010 +.set CYFLD_CM0_COUNTFLAG__SIZE, 0x00000001 +.set CYREG_CM0_SYST_RVR, 0xe000e014 +.set CYFLD_CM0_RELOAD__OFFSET, 0x00000000 +.set CYFLD_CM0_RELOAD__SIZE, 0x00000018 +.set CYREG_CM0_SYST_CVR, 0xe000e018 +.set CYFLD_CM0_CURRENT__OFFSET, 0x00000000 +.set CYFLD_CM0_CURRENT__SIZE, 0x00000018 +.set CYREG_CM0_SYST_CALIB, 0xe000e01c +.set CYFLD_CM0_TENMS__OFFSET, 0x00000000 +.set CYFLD_CM0_TENMS__SIZE, 0x00000018 +.set CYFLD_CM0_SKEW__OFFSET, 0x0000001e +.set CYFLD_CM0_SKEW__SIZE, 0x00000001 +.set CYFLD_CM0_NOREF__OFFSET, 0x0000001f +.set CYFLD_CM0_NOREF__SIZE, 0x00000001 +.set CYREG_CM0_ISER, 0xe000e100 +.set CYFLD_CM0_SETENA__OFFSET, 0x00000000 +.set CYFLD_CM0_SETENA__SIZE, 0x00000020 +.set CYREG_CM0_ICER, 0xe000e180 +.set CYFLD_CM0_CLRENA__OFFSET, 0x00000000 +.set CYFLD_CM0_CLRENA__SIZE, 0x00000020 +.set CYREG_CM0_ISPR, 0xe000e200 +.set CYFLD_CM0_SETPEND__OFFSET, 0x00000000 +.set CYFLD_CM0_SETPEND__SIZE, 0x00000020 +.set CYREG_CM0_ICPR, 0xe000e280 +.set CYFLD_CM0_CLRPEND__OFFSET, 0x00000000 +.set CYFLD_CM0_CLRPEND__SIZE, 0x00000020 +.set CYREG_CM0_IPR0, 0xe000e400 +.set CYFLD_CM0_PRI_N0__OFFSET, 0x00000006 +.set CYFLD_CM0_PRI_N0__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_N1__OFFSET, 0x0000000e +.set CYFLD_CM0_PRI_N1__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_N2__OFFSET, 0x00000016 +.set CYFLD_CM0_PRI_N2__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_N3__OFFSET, 0x0000001e +.set CYFLD_CM0_PRI_N3__SIZE, 0x00000002 +.set CYREG_CM0_IPR1, 0xe000e404 +.set CYREG_CM0_IPR2, 0xe000e408 +.set CYREG_CM0_IPR3, 0xe000e40c +.set CYREG_CM0_IPR4, 0xe000e410 +.set CYREG_CM0_IPR5, 0xe000e414 +.set CYREG_CM0_IPR6, 0xe000e418 +.set CYREG_CM0_IPR7, 0xe000e41c +.set CYREG_CM0_CPUID, 0xe000ed00 +.set CYFLD_CM0_REVISION__OFFSET, 0x00000000 +.set CYFLD_CM0_REVISION__SIZE, 0x00000004 +.set CYFLD_CM0_PARTNO__OFFSET, 0x00000004 +.set CYFLD_CM0_PARTNO__SIZE, 0x0000000c +.set CYFLD_CM0_CONSTANT__OFFSET, 0x00000010 +.set CYFLD_CM0_CONSTANT__SIZE, 0x00000004 +.set CYFLD_CM0_VARIANT__OFFSET, 0x00000014 +.set CYFLD_CM0_VARIANT__SIZE, 0x00000004 +.set CYFLD_CM0_IMPLEMENTER__OFFSET, 0x00000018 +.set CYFLD_CM0_IMPLEMENTER__SIZE, 0x00000008 +.set CYREG_CM0_ICSR, 0xe000ed04 +.set CYFLD_CM0_VECTACTIVE__OFFSET, 0x00000000 +.set CYFLD_CM0_VECTACTIVE__SIZE, 0x00000009 +.set CYFLD_CM0_VECTPENDING__OFFSET, 0x0000000c +.set CYFLD_CM0_VECTPENDING__SIZE, 0x00000009 +.set CYFLD_CM0_ISRPENDING__OFFSET, 0x00000016 +.set CYFLD_CM0_ISRPENDING__SIZE, 0x00000001 +.set CYFLD_CM0_ISRPREEMPT__OFFSET, 0x00000017 +.set CYFLD_CM0_ISRPREEMPT__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSTCLR__OFFSET, 0x00000019 +.set CYFLD_CM0_PENDSTCLR__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSTSETb__OFFSET, 0x0000001a +.set CYFLD_CM0_PENDSTSETb__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSVCLR__OFFSET, 0x0000001b +.set CYFLD_CM0_PENDSVCLR__SIZE, 0x00000001 +.set CYFLD_CM0_PENDSVSET__OFFSET, 0x0000001c +.set CYFLD_CM0_PENDSVSET__SIZE, 0x00000001 +.set CYFLD_CM0_NMIPENDSET__OFFSET, 0x0000001f +.set CYFLD_CM0_NMIPENDSET__SIZE, 0x00000001 +.set CYREG_CM0_AIRCR, 0xe000ed0c +.set CYFLD_CM0_VECTCLRACTIVE__OFFSET, 0x00000001 +.set CYFLD_CM0_VECTCLRACTIVE__SIZE, 0x00000001 +.set CYFLD_CM0_SYSRESETREQ__OFFSET, 0x00000002 +.set CYFLD_CM0_SYSRESETREQ__SIZE, 0x00000001 +.set CYFLD_CM0_ENDIANNESS__OFFSET, 0x0000000f +.set CYFLD_CM0_ENDIANNESS__SIZE, 0x00000001 +.set CYFLD_CM0_VECTKEY__OFFSET, 0x00000010 +.set CYFLD_CM0_VECTKEY__SIZE, 0x00000010 +.set CYREG_CM0_SCR, 0xe000ed10 +.set CYFLD_CM0_SLEEPONEXIT__OFFSET, 0x00000001 +.set CYFLD_CM0_SLEEPONEXIT__SIZE, 0x00000001 +.set CYFLD_CM0_SLEEPDEEP__OFFSET, 0x00000002 +.set CYFLD_CM0_SLEEPDEEP__SIZE, 0x00000001 +.set CYFLD_CM0_SEVONPEND__OFFSET, 0x00000004 +.set CYFLD_CM0_SEVONPEND__SIZE, 0x00000001 +.set CYREG_CM0_CCR, 0xe000ed14 +.set CYFLD_CM0_UNALIGN_TRP__OFFSET, 0x00000003 +.set CYFLD_CM0_UNALIGN_TRP__SIZE, 0x00000001 +.set CYFLD_CM0_STKALIGN__OFFSET, 0x00000009 +.set CYFLD_CM0_STKALIGN__SIZE, 0x00000001 +.set CYREG_CM0_SHPR2, 0xe000ed1c +.set CYFLD_CM0_PRI_11__OFFSET, 0x0000001e +.set CYFLD_CM0_PRI_11__SIZE, 0x00000002 +.set CYREG_CM0_SHPR3, 0xe000ed20 +.set CYFLD_CM0_PRI_14__OFFSET, 0x00000016 +.set CYFLD_CM0_PRI_14__SIZE, 0x00000002 +.set CYFLD_CM0_PRI_15__OFFSET, 0x0000001e +.set CYFLD_CM0_PRI_15__SIZE, 0x00000002 +.set CYREG_CM0_SHCSR, 0xe000ed24 +.set CYFLD_CM0_SVCALLPENDED__OFFSET, 0x0000000f +.set CYFLD_CM0_SVCALLPENDED__SIZE, 0x00000001 +.set CYREG_CM0_SCS_PID4, 0xe000efd0 +.set CYREG_CM0_SCS_PID0, 0xe000efe0 +.set CYREG_CM0_SCS_PID1, 0xe000efe4 +.set CYREG_CM0_SCS_PID2, 0xe000efe8 +.set CYREG_CM0_SCS_PID3, 0xe000efec +.set CYREG_CM0_SCS_CID0, 0xe000eff0 +.set CYREG_CM0_SCS_CID1, 0xe000eff4 +.set CYREG_CM0_SCS_CID2, 0xe000eff8 +.set CYREG_CM0_SCS_CID3, 0xe000effc +.set CYREG_CM0_ROM_SCS, 0xe00ff000 +.set CYREG_CM0_ROM_DWT, 0xe00ff004 +.set CYREG_CM0_ROM_BPU, 0xe00ff008 +.set CYREG_CM0_ROM_END, 0xe00ff00c +.set CYREG_CM0_ROM_CSMT, 0xe00fffcc +.set CYREG_CM0_ROM_PID4, 0xe00fffd0 +.set CYREG_CM0_ROM_PID0, 0xe00fffe0 +.set CYREG_CM0_ROM_PID1, 0xe00fffe4 +.set CYREG_CM0_ROM_PID2, 0xe00fffe8 +.set CYREG_CM0_ROM_PID3, 0xe00fffec +.set CYREG_CM0_ROM_CID0, 0xe00ffff0 +.set CYREG_CM0_ROM_CID1, 0xe00ffff4 +.set CYREG_CM0_ROM_CID2, 0xe00ffff8 +.set CYREG_CM0_ROM_CID3, 0xe00ffffc +.set CYDEV_CoreSightTable_BASE, 0xf0000000 +.set CYDEV_CoreSightTable_SIZE, 0x00001000 +.set CYREG_CoreSightTable_DATA_MBASE, 0xf0000000 +.set CYREG_CoreSightTable_DATA_MSIZE, 0x00001000 +.set CYDEV_FLS_SECTOR_SIZE, 0x00008000 +.set CYDEV_FLS_ROW_SIZE, 0x00000080 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cydeviceiar_trm.inc b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydeviceiar_trm.inc new file mode 100644 index 0000000..e4eb849 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydeviceiar_trm.inc @@ -0,0 +1,6493 @@ +; +; File Name: cydeviceiar_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00008000 +#define CYREG_FLASH_DATA_MBASE 0x00000000 +#define CYREG_FLASH_DATA_MSIZE 0x00008000 +#define CYDEV_SFLASH_BASE 0x0ffff000 +#define CYDEV_SFLASH_SIZE 0x00000200 +#define CYREG_SFLASH_PROT_ROW00 0x0ffff000 +#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000 +#define CYFLD_SFLASH_DATA8__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_ROW01 0x0ffff001 +#define CYREG_SFLASH_PROT_ROW02 0x0ffff002 +#define CYREG_SFLASH_PROT_ROW03 0x0ffff003 +#define CYREG_SFLASH_PROT_ROW04 0x0ffff004 +#define CYREG_SFLASH_PROT_ROW05 0x0ffff005 +#define CYREG_SFLASH_PROT_ROW06 0x0ffff006 +#define CYREG_SFLASH_PROT_ROW07 0x0ffff007 +#define CYREG_SFLASH_PROT_ROW08 0x0ffff008 +#define CYREG_SFLASH_PROT_ROW09 0x0ffff009 +#define CYREG_SFLASH_PROT_ROW10 0x0ffff00a +#define CYREG_SFLASH_PROT_ROW11 0x0ffff00b +#define CYREG_SFLASH_PROT_ROW12 0x0ffff00c +#define CYREG_SFLASH_PROT_ROW13 0x0ffff00d +#define CYREG_SFLASH_PROT_ROW14 0x0ffff00e +#define CYREG_SFLASH_PROT_ROW15 0x0ffff00f +#define CYREG_SFLASH_PROT_ROW16 0x0ffff010 +#define CYREG_SFLASH_PROT_ROW17 0x0ffff011 +#define CYREG_SFLASH_PROT_ROW18 0x0ffff012 +#define CYREG_SFLASH_PROT_ROW19 0x0ffff013 +#define CYREG_SFLASH_PROT_ROW20 0x0ffff014 +#define CYREG_SFLASH_PROT_ROW21 0x0ffff015 +#define CYREG_SFLASH_PROT_ROW22 0x0ffff016 +#define CYREG_SFLASH_PROT_ROW23 0x0ffff017 +#define CYREG_SFLASH_PROT_ROW24 0x0ffff018 +#define CYREG_SFLASH_PROT_ROW25 0x0ffff019 +#define CYREG_SFLASH_PROT_ROW26 0x0ffff01a +#define CYREG_SFLASH_PROT_ROW27 0x0ffff01b +#define CYREG_SFLASH_PROT_ROW28 0x0ffff01c +#define CYREG_SFLASH_PROT_ROW29 0x0ffff01d +#define CYREG_SFLASH_PROT_ROW30 0x0ffff01e +#define CYREG_SFLASH_PROT_ROW31 0x0ffff01f +#define CYREG_SFLASH_PROT_ROW32 0x0ffff020 +#define CYREG_SFLASH_PROT_ROW33 0x0ffff021 +#define CYREG_SFLASH_PROT_ROW34 0x0ffff022 +#define CYREG_SFLASH_PROT_ROW35 0x0ffff023 +#define CYREG_SFLASH_PROT_ROW36 0x0ffff024 +#define CYREG_SFLASH_PROT_ROW37 0x0ffff025 +#define CYREG_SFLASH_PROT_ROW38 0x0ffff026 +#define CYREG_SFLASH_PROT_ROW39 0x0ffff027 +#define CYREG_SFLASH_PROT_ROW40 0x0ffff028 +#define CYREG_SFLASH_PROT_ROW41 0x0ffff029 +#define CYREG_SFLASH_PROT_ROW42 0x0ffff02a +#define CYREG_SFLASH_PROT_ROW43 0x0ffff02b +#define CYREG_SFLASH_PROT_ROW44 0x0ffff02c +#define CYREG_SFLASH_PROT_ROW45 0x0ffff02d +#define CYREG_SFLASH_PROT_ROW46 0x0ffff02e +#define CYREG_SFLASH_PROT_ROW47 0x0ffff02f +#define CYREG_SFLASH_PROT_ROW48 0x0ffff030 +#define CYREG_SFLASH_PROT_ROW49 0x0ffff031 +#define CYREG_SFLASH_PROT_ROW50 0x0ffff032 +#define CYREG_SFLASH_PROT_ROW51 0x0ffff033 +#define CYREG_SFLASH_PROT_ROW52 0x0ffff034 +#define CYREG_SFLASH_PROT_ROW53 0x0ffff035 +#define CYREG_SFLASH_PROT_ROW54 0x0ffff036 +#define CYREG_SFLASH_PROT_ROW55 0x0ffff037 +#define CYREG_SFLASH_PROT_ROW56 0x0ffff038 +#define CYREG_SFLASH_PROT_ROW57 0x0ffff039 +#define CYREG_SFLASH_PROT_ROW58 0x0ffff03a +#define CYREG_SFLASH_PROT_ROW59 0x0ffff03b +#define CYREG_SFLASH_PROT_ROW60 0x0ffff03c +#define CYREG_SFLASH_PROT_ROW61 0x0ffff03d +#define CYREG_SFLASH_PROT_ROW62 0x0ffff03e +#define CYREG_SFLASH_PROT_ROW63 0x0ffff03f +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07f +#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000 +#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002 +#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001 +#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000 +#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002 +#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003 +#define CYREG_SFLASH_AV_PAIRS_8B000 0x0ffff080 +#define CYREG_SFLASH_AV_PAIRS_8B001 0x0ffff081 +#define CYREG_SFLASH_AV_PAIRS_8B002 0x0ffff082 +#define CYREG_SFLASH_AV_PAIRS_8B003 0x0ffff083 +#define CYREG_SFLASH_AV_PAIRS_8B004 0x0ffff084 +#define CYREG_SFLASH_AV_PAIRS_8B005 0x0ffff085 +#define CYREG_SFLASH_AV_PAIRS_8B006 0x0ffff086 +#define CYREG_SFLASH_AV_PAIRS_8B007 0x0ffff087 +#define CYREG_SFLASH_AV_PAIRS_8B008 0x0ffff088 +#define CYREG_SFLASH_AV_PAIRS_8B009 0x0ffff089 +#define CYREG_SFLASH_AV_PAIRS_8B010 0x0ffff08a +#define CYREG_SFLASH_AV_PAIRS_8B011 0x0ffff08b +#define CYREG_SFLASH_AV_PAIRS_8B012 0x0ffff08c +#define CYREG_SFLASH_AV_PAIRS_8B013 0x0ffff08d +#define CYREG_SFLASH_AV_PAIRS_8B014 0x0ffff08e +#define CYREG_SFLASH_AV_PAIRS_8B015 0x0ffff08f +#define CYREG_SFLASH_AV_PAIRS_8B016 0x0ffff090 +#define CYREG_SFLASH_AV_PAIRS_8B017 0x0ffff091 +#define CYREG_SFLASH_AV_PAIRS_8B018 0x0ffff092 +#define CYREG_SFLASH_AV_PAIRS_8B019 0x0ffff093 +#define CYREG_SFLASH_AV_PAIRS_8B020 0x0ffff094 +#define CYREG_SFLASH_AV_PAIRS_8B021 0x0ffff095 +#define CYREG_SFLASH_AV_PAIRS_8B022 0x0ffff096 +#define CYREG_SFLASH_AV_PAIRS_8B023 0x0ffff097 +#define CYREG_SFLASH_AV_PAIRS_8B024 0x0ffff098 +#define CYREG_SFLASH_AV_PAIRS_8B025 0x0ffff099 +#define CYREG_SFLASH_AV_PAIRS_8B026 0x0ffff09a +#define CYREG_SFLASH_AV_PAIRS_8B027 0x0ffff09b +#define CYREG_SFLASH_AV_PAIRS_8B028 0x0ffff09c +#define CYREG_SFLASH_AV_PAIRS_8B029 0x0ffff09d +#define CYREG_SFLASH_AV_PAIRS_8B030 0x0ffff09e +#define CYREG_SFLASH_AV_PAIRS_8B031 0x0ffff09f +#define CYREG_SFLASH_AV_PAIRS_8B032 0x0ffff0a0 +#define CYREG_SFLASH_AV_PAIRS_8B033 0x0ffff0a1 +#define CYREG_SFLASH_AV_PAIRS_8B034 0x0ffff0a2 +#define CYREG_SFLASH_AV_PAIRS_8B035 0x0ffff0a3 +#define CYREG_SFLASH_AV_PAIRS_8B036 0x0ffff0a4 +#define CYREG_SFLASH_AV_PAIRS_8B037 0x0ffff0a5 +#define CYREG_SFLASH_AV_PAIRS_8B038 0x0ffff0a6 +#define CYREG_SFLASH_AV_PAIRS_8B039 0x0ffff0a7 +#define CYREG_SFLASH_AV_PAIRS_8B040 0x0ffff0a8 +#define CYREG_SFLASH_AV_PAIRS_8B041 0x0ffff0a9 +#define CYREG_SFLASH_AV_PAIRS_8B042 0x0ffff0aa +#define CYREG_SFLASH_AV_PAIRS_8B043 0x0ffff0ab +#define CYREG_SFLASH_AV_PAIRS_8B044 0x0ffff0ac +#define CYREG_SFLASH_AV_PAIRS_8B045 0x0ffff0ad +#define CYREG_SFLASH_AV_PAIRS_8B046 0x0ffff0ae +#define CYREG_SFLASH_AV_PAIRS_8B047 0x0ffff0af +#define CYREG_SFLASH_AV_PAIRS_8B048 0x0ffff0b0 +#define CYREG_SFLASH_AV_PAIRS_8B049 0x0ffff0b1 +#define CYREG_SFLASH_AV_PAIRS_8B050 0x0ffff0b2 +#define CYREG_SFLASH_AV_PAIRS_8B051 0x0ffff0b3 +#define CYREG_SFLASH_AV_PAIRS_8B052 0x0ffff0b4 +#define CYREG_SFLASH_AV_PAIRS_8B053 0x0ffff0b5 +#define CYREG_SFLASH_AV_PAIRS_8B054 0x0ffff0b6 +#define CYREG_SFLASH_AV_PAIRS_8B055 0x0ffff0b7 +#define CYREG_SFLASH_AV_PAIRS_8B056 0x0ffff0b8 +#define CYREG_SFLASH_AV_PAIRS_8B057 0x0ffff0b9 +#define CYREG_SFLASH_AV_PAIRS_8B058 0x0ffff0ba +#define CYREG_SFLASH_AV_PAIRS_8B059 0x0ffff0bb +#define CYREG_SFLASH_AV_PAIRS_8B060 0x0ffff0bc +#define CYREG_SFLASH_AV_PAIRS_8B061 0x0ffff0bd +#define CYREG_SFLASH_AV_PAIRS_8B062 0x0ffff0be +#define CYREG_SFLASH_AV_PAIRS_8B063 0x0ffff0bf +#define CYREG_SFLASH_AV_PAIRS_8B064 0x0ffff0c0 +#define CYREG_SFLASH_AV_PAIRS_8B065 0x0ffff0c1 +#define CYREG_SFLASH_AV_PAIRS_8B066 0x0ffff0c2 +#define CYREG_SFLASH_AV_PAIRS_8B067 0x0ffff0c3 +#define CYREG_SFLASH_AV_PAIRS_8B068 0x0ffff0c4 +#define CYREG_SFLASH_AV_PAIRS_8B069 0x0ffff0c5 +#define CYREG_SFLASH_AV_PAIRS_8B070 0x0ffff0c6 +#define CYREG_SFLASH_AV_PAIRS_8B071 0x0ffff0c7 +#define CYREG_SFLASH_AV_PAIRS_8B072 0x0ffff0c8 +#define CYREG_SFLASH_AV_PAIRS_8B073 0x0ffff0c9 +#define CYREG_SFLASH_AV_PAIRS_8B074 0x0ffff0ca +#define CYREG_SFLASH_AV_PAIRS_8B075 0x0ffff0cb +#define CYREG_SFLASH_AV_PAIRS_8B076 0x0ffff0cc +#define CYREG_SFLASH_AV_PAIRS_8B077 0x0ffff0cd +#define CYREG_SFLASH_AV_PAIRS_8B078 0x0ffff0ce +#define CYREG_SFLASH_AV_PAIRS_8B079 0x0ffff0cf +#define CYREG_SFLASH_AV_PAIRS_8B080 0x0ffff0d0 +#define CYREG_SFLASH_AV_PAIRS_8B081 0x0ffff0d1 +#define CYREG_SFLASH_AV_PAIRS_8B082 0x0ffff0d2 +#define CYREG_SFLASH_AV_PAIRS_8B083 0x0ffff0d3 +#define CYREG_SFLASH_AV_PAIRS_8B084 0x0ffff0d4 +#define CYREG_SFLASH_AV_PAIRS_8B085 0x0ffff0d5 +#define CYREG_SFLASH_AV_PAIRS_8B086 0x0ffff0d6 +#define CYREG_SFLASH_AV_PAIRS_8B087 0x0ffff0d7 +#define CYREG_SFLASH_AV_PAIRS_8B088 0x0ffff0d8 +#define CYREG_SFLASH_AV_PAIRS_8B089 0x0ffff0d9 +#define CYREG_SFLASH_AV_PAIRS_8B090 0x0ffff0da +#define CYREG_SFLASH_AV_PAIRS_8B091 0x0ffff0db +#define CYREG_SFLASH_AV_PAIRS_8B092 0x0ffff0dc +#define CYREG_SFLASH_AV_PAIRS_8B093 0x0ffff0dd +#define CYREG_SFLASH_AV_PAIRS_8B094 0x0ffff0de +#define CYREG_SFLASH_AV_PAIRS_8B095 0x0ffff0df +#define CYREG_SFLASH_AV_PAIRS_8B096 0x0ffff0e0 +#define CYREG_SFLASH_AV_PAIRS_8B097 0x0ffff0e1 +#define CYREG_SFLASH_AV_PAIRS_8B098 0x0ffff0e2 +#define CYREG_SFLASH_AV_PAIRS_8B099 0x0ffff0e3 +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4 +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5 +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6 +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7 +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8 +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9 +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0ea +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0eb +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ec +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0ed +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0ee +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0ef +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0 +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1 +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2 +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3 +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4 +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5 +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6 +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7 +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8 +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9 +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fa +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fb +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fc +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fd +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0fe +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ff +#define CYREG_SFLASH_AV_PAIRS_32B00 0x0ffff100 +#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000 +#define CYFLD_SFLASH_DATA32__SIZE 0x00000020 +#define CYREG_SFLASH_AV_PAIRS_32B01 0x0ffff104 +#define CYREG_SFLASH_AV_PAIRS_32B02 0x0ffff108 +#define CYREG_SFLASH_AV_PAIRS_32B03 0x0ffff10c +#define CYREG_SFLASH_AV_PAIRS_32B04 0x0ffff110 +#define CYREG_SFLASH_AV_PAIRS_32B05 0x0ffff114 +#define CYREG_SFLASH_AV_PAIRS_32B06 0x0ffff118 +#define CYREG_SFLASH_AV_PAIRS_32B07 0x0ffff11c +#define CYREG_SFLASH_AV_PAIRS_32B08 0x0ffff120 +#define CYREG_SFLASH_AV_PAIRS_32B09 0x0ffff124 +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128 +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12c +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130 +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134 +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138 +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13c +#define CYREG_SFLASH_CPUSS_WOUNDING 0x0ffff140 +#define CYREG_SFLASH_SILICON_ID 0x0ffff144 +#define CYFLD_SFLASH_ID__OFFSET 0x00000000 +#define CYFLD_SFLASH_ID__SIZE 0x00000010 +#define CYREG_SFLASH_CPUSS_PRIV_RAM 0x0ffff148 +#define CYREG_SFLASH_CPUSS_PRIV_FLASH 0x0ffff14c +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150 +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000 +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000a +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152 +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154 +#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000 +#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001 +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158 +#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000 +#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020 +#define CYREG_SFLASH_FLASH_START 0x0ffff15c +#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000 +#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020 +#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160 +#define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000 +#define CYFLD_SFLASH_TRIM8__SIZE 0x00000008 +#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161 +#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162 +#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163 +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164 +#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000 +#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010 +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166 +#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000 +#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010 +#define CYREG_SFLASH_SKIP_CHECKSUM 0x0ffff169 +#define CYFLD_SFLASH_SKIP__OFFSET 0x00000000 +#define CYFLD_SFLASH_SKIP__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170 +#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000 +#define CYFLD_SFLASH_KEY8__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171 +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172 +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173 +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174 +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175 +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176 +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177 +#define CYREG_SFLASH_DIE_LOT0 0x0ffff178 +#define CYFLD_SFLASH_LOT__OFFSET 0x00000000 +#define CYFLD_SFLASH_LOT__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_LOT1 0x0ffff179 +#define CYREG_SFLASH_DIE_LOT2 0x0ffff17a +#define CYREG_SFLASH_DIE_WAFER 0x0ffff17b +#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000 +#define CYFLD_SFLASH_WAFER__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_X 0x0ffff17c +#define CYFLD_SFLASH_X__OFFSET 0x00000000 +#define CYFLD_SFLASH_X__SIZE 0x00000006 +#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000006 +#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000002 +#define CYREG_SFLASH_DIE_Y 0x0ffff17d +#define CYFLD_SFLASH_Y__OFFSET 0x00000000 +#define CYFLD_SFLASH_Y__SIZE 0x00000006 +#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000006 +#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000002 +#define CYREG_SFLASH_DIE_SORT 0x0ffff17e +#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000 +#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000002 +#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000002 +#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000002 +#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000004 +#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000002 +#define CYREG_SFLASH_DIE_MINOR 0x0ffff17f +#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000 +#define CYFLD_SFLASH_MINOR__SIZE 0x00000008 +#define CYREG_SFLASH_PE_TE_DATA00 0x0ffff180 +#define CYREG_SFLASH_PE_TE_DATA01 0x0ffff181 +#define CYREG_SFLASH_PE_TE_DATA02 0x0ffff182 +#define CYREG_SFLASH_PE_TE_DATA03 0x0ffff183 +#define CYREG_SFLASH_PE_TE_DATA04 0x0ffff184 +#define CYREG_SFLASH_PE_TE_DATA05 0x0ffff185 +#define CYREG_SFLASH_PE_TE_DATA06 0x0ffff186 +#define CYREG_SFLASH_PE_TE_DATA07 0x0ffff187 +#define CYREG_SFLASH_PE_TE_DATA08 0x0ffff188 +#define CYREG_SFLASH_PE_TE_DATA09 0x0ffff189 +#define CYREG_SFLASH_PE_TE_DATA10 0x0ffff18a +#define CYREG_SFLASH_PE_TE_DATA11 0x0ffff18b +#define CYREG_SFLASH_PE_TE_DATA12 0x0ffff18c +#define CYREG_SFLASH_PE_TE_DATA13 0x0ffff18d +#define CYREG_SFLASH_PE_TE_DATA14 0x0ffff18e +#define CYREG_SFLASH_PE_TE_DATA15 0x0ffff18f +#define CYREG_SFLASH_PE_TE_DATA16 0x0ffff190 +#define CYREG_SFLASH_PE_TE_DATA17 0x0ffff191 +#define CYREG_SFLASH_PE_TE_DATA18 0x0ffff192 +#define CYREG_SFLASH_PE_TE_DATA19 0x0ffff193 +#define CYREG_SFLASH_PE_TE_DATA20 0x0ffff194 +#define CYREG_SFLASH_PE_TE_DATA21 0x0ffff195 +#define CYREG_SFLASH_PE_TE_DATA22 0x0ffff196 +#define CYREG_SFLASH_PE_TE_DATA23 0x0ffff197 +#define CYREG_SFLASH_PE_TE_DATA24 0x0ffff198 +#define CYREG_SFLASH_PE_TE_DATA25 0x0ffff199 +#define CYREG_SFLASH_PE_TE_DATA26 0x0ffff19a +#define CYREG_SFLASH_PE_TE_DATA27 0x0ffff19b +#define CYREG_SFLASH_PE_TE_DATA28 0x0ffff19c +#define CYREG_SFLASH_PE_TE_DATA29 0x0ffff19d +#define CYREG_SFLASH_PE_TE_DATA30 0x0ffff19e +#define CYREG_SFLASH_PE_TE_DATA31 0x0ffff19f +#define CYREG_SFLASH_PP 0x0ffff1a0 +#define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000 +#define CYFLD_SFLASH_PERIOD__SIZE 0x00000018 +#define CYFLD_SFLASH_PDAC__OFFSET 0x00000018 +#define CYFLD_SFLASH_PDAC__SIZE 0x00000004 +#define CYFLD_SFLASH_NDAC__OFFSET 0x0000001c +#define CYFLD_SFLASH_NDAC__SIZE 0x00000004 +#define CYREG_SFLASH_E 0x0ffff1a4 +#define CYREG_SFLASH_P 0x0ffff1a8 +#define CYREG_SFLASH_EA_E 0x0ffff1ac +#define CYREG_SFLASH_EA_P 0x0ffff1b0 +#define CYREG_SFLASH_ES_E 0x0ffff1b4 +#define CYREG_SFLASH_ES_P_EO 0x0ffff1b8 +#define CYREG_SFLASH_E_VCTAT 0x0ffff1bc +#define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000 +#define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004 +#define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004 +#define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002 +#define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006 +#define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001 +#define CYREG_SFLASH_P_VCTAT 0x0ffff1bd +#define CYREG_SFLASH_MARGIN 0x0ffff1be +#define CYFLD_SFLASH_MDAC__OFFSET 0x00000000 +#define CYFLD_SFLASH_MDAC__SIZE 0x00000008 +#define CYREG_SFLASH_SPCIF_TRIM1 0x0ffff1bf +#define CYFLD_SFLASH_BDAC__OFFSET 0x00000000 +#define CYFLD_SFLASH_BDAC__SIZE 0x00000004 +#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0 +#define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000 +#define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006 +#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1 +#define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006 +#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2 +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006 +#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3 +#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4 +#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5 +#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6 +#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7 +#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8 +#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9 +#define CYREG_SFLASH_IMO_ABS3 0x0ffff1ca +#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cb +#define CYREG_SFLASH_IMO_ABS4 0x0ffff1cc +#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cd +#define CYREG_SFLASH_IMO_TRIM00 0x0ffff1d0 +#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000 +#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008 +#define CYREG_SFLASH_IMO_TRIM01 0x0ffff1d1 +#define CYREG_SFLASH_IMO_TRIM02 0x0ffff1d2 +#define CYREG_SFLASH_IMO_TRIM03 0x0ffff1d3 +#define CYREG_SFLASH_IMO_TRIM04 0x0ffff1d4 +#define CYREG_SFLASH_IMO_TRIM05 0x0ffff1d5 +#define CYREG_SFLASH_IMO_TRIM06 0x0ffff1d6 +#define CYREG_SFLASH_IMO_TRIM07 0x0ffff1d7 +#define CYREG_SFLASH_IMO_TRIM08 0x0ffff1d8 +#define CYREG_SFLASH_IMO_TRIM09 0x0ffff1d9 +#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1da +#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1db +#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dc +#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1dd +#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1de +#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1df +#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0 +#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1 +#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2 +#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3 +#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4 +#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5 +#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6 +#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7 +#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8 +#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9 +#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1ea +#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1eb +#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ec +#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1ed +#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1ee +#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1ef +#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0 +#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1 +#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2 +#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3 +#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4 +#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5 +#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6 +#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7 +#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8 +#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9 +#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fa +#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fb +#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fc +#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fd +#define CYREG_SFLASH_CHECKSUM 0x0ffff1fe +#define CYFLD_SFLASH_CHECKSUM__OFFSET 0x00000000 +#define CYFLD_SFLASH_CHECKSUM__SIZE 0x00000010 +#define CYDEV_SROM_BASE 0x10000000 +#define CYDEV_SROM_SIZE 0x00001000 +#define CYREG_SROM_DATA_MBASE 0x10000000 +#define CYREG_SROM_DATA_MSIZE 0x00001000 +#define CYDEV_SRAM_BASE 0x20000000 +#define CYDEV_SRAM_SIZE 0x00001000 +#define CYREG_SRAM_DATA_MBASE 0x20000000 +#define CYREG_SRAM_DATA_MSIZE 0x00001000 +#define CYDEV_CPUSS_BASE 0x40000000 +#define CYDEV_CPUSS_SIZE 0x00010000 +#define CYREG_CPUSS_CONFIG 0x40000000 +#define CYFLD_CPUSS_VECS_IN_RAM__OFFSET 0x00000000 +#define CYFLD_CPUSS_VECS_IN_RAM__SIZE 0x00000001 +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET 0x00000001 +#define CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE 0x00000001 +#define CYREG_CPUSS_SYSREQ 0x40000004 +#define CYFLD_CPUSS_COMMAND__OFFSET 0x00000000 +#define CYFLD_CPUSS_COMMAND__SIZE 0x00000010 +#define CYFLD_CPUSS_NO_RST_OVR__OFFSET 0x0000001b +#define CYFLD_CPUSS_NO_RST_OVR__SIZE 0x00000001 +#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001c +#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001 +#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001d +#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001 +#define CYFLD_CPUSS_HMASTER__OFFSET 0x0000001e +#define CYFLD_CPUSS_HMASTER__SIZE 0x00000001 +#define CYFLD_CPUSS_SYSREQ__OFFSET 0x0000001f +#define CYFLD_CPUSS_SYSREQ__SIZE 0x00000001 +#define CYREG_CPUSS_SYSARG 0x40000008 +#define CYFLD_CPUSS_ARG32__OFFSET 0x00000000 +#define CYFLD_CPUSS_ARG32__SIZE 0x00000020 +#define CYREG_CPUSS_PROTECTION 0x4000000c +#define CYFLD_CPUSS_PROT__OFFSET 0x00000000 +#define CYFLD_CPUSS_PROT__SIZE 0x00000004 +#define CYVAL_CPUSS_PROT_VIRGIN 0x00000000 +#define CYVAL_CPUSS_PROT_OPEN 0x00000001 +#define CYVAL_CPUSS_PROT_PROTECTED 0x00000002 +#define CYVAL_CPUSS_PROT_KILL 0x00000004 +#define CYVAL_CPUSS_PROT_BOOT 0x00000008 +#define CYFLD_CPUSS_PROT_LOCK__OFFSET 0x0000001f +#define CYFLD_CPUSS_PROT_LOCK__SIZE 0x00000001 +#define CYREG_CPUSS_PRIV_ROM 0x40000010 +#define CYFLD_CPUSS_ROM_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_ROM_LIMIT__SIZE 0x00000008 +#define CYREG_CPUSS_PRIV_RAM 0x40000014 +#define CYFLD_CPUSS_RAM_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_RAM_LIMIT__SIZE 0x00000009 +#define CYREG_CPUSS_PRIV_FLASH 0x40000018 +#define CYFLD_CPUSS_FLASH_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_FLASH_LIMIT__SIZE 0x0000000b +#define CYREG_CPUSS_WOUNDING 0x4000001c +#define CYFLD_CPUSS_RAM_SIZE__OFFSET 0x00000000 +#define CYFLD_CPUSS_RAM_SIZE__SIZE 0x00000009 +#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010 +#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003 +#define CYVAL_CPUSS_RAM_WOUND_FULL 0x00000000 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 0x00000001 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 0x00000002 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 0x00000003 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 0x00000004 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 0x00000005 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 0x00000006 +#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 0x00000007 +#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014 +#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003 +#define CYVAL_CPUSS_FLASH_WOUND_FULL 0x00000000 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 0x00000001 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 0x00000002 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 0x00000003 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 0x00000004 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 0x00000005 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 0x00000006 +#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 0x00000007 +#define CYREG_CPUSS_INTR_SELECT 0x40000020 +#define CYFLD_CPUSS_SELECT32__OFFSET 0x00000000 +#define CYFLD_CPUSS_SELECT32__SIZE 0x00000020 +#define CYDEV_HSIOM_BASE 0x40010000 +#define CYDEV_HSIOM_SIZE 0x00001000 +#define CYREG_HSIOM_PORT_SEL0 0x40010000 +#define CYFLD_HSIOM_SEL0__OFFSET 0x00000000 +#define CYFLD_HSIOM_SEL0__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL0_GPIO 0x00000000 +#define CYVAL_HSIOM_SEL0_GPIO_DSI 0x00000001 +#define CYVAL_HSIOM_SEL0_DSI_DSI 0x00000002 +#define CYVAL_HSIOM_SEL0_DSI_GPIO 0x00000003 +#define CYVAL_HSIOM_SEL0_CSD_SENSE 0x00000004 +#define CYVAL_HSIOM_SEL0_CSD_SHIELD 0x00000005 +#define CYVAL_HSIOM_SEL0_AMUXA 0x00000006 +#define CYVAL_HSIOM_SEL0_AMUXB 0x00000007 +#define CYVAL_HSIOM_SEL0_ACT_0 0x00000008 +#define CYVAL_HSIOM_SEL0_ACT_1 0x00000009 +#define CYVAL_HSIOM_SEL0_ACT_2 0x0000000a +#define CYVAL_HSIOM_SEL0_ACT_3 0x0000000b +#define CYVAL_HSIOM_SEL0_LCD_COM 0x0000000c +#define CYVAL_HSIOM_SEL0_LCD_SEG 0x0000000d +#define CYVAL_HSIOM_SEL0_DPSLP_0 0x0000000e +#define CYVAL_HSIOM_SEL0_DPSLP_1 0x0000000f +#define CYVAL_HSIOM_SEL0_COMP1_INP 0x00000000 +#define CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 0x0000000f +#define CYFLD_HSIOM_SEL1__OFFSET 0x00000004 +#define CYFLD_HSIOM_SEL1__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL1_COMP1_INN 0x00000000 +#define CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 0x0000000f +#define CYFLD_HSIOM_SEL2__OFFSET 0x00000008 +#define CYFLD_HSIOM_SEL2__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL2_COMP2_INP 0x00000000 +#define CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 0x0000000f +#define CYFLD_HSIOM_SEL3__OFFSET 0x0000000c +#define CYFLD_HSIOM_SEL3__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL3_COMP2_INN 0x00000000 +#define CYFLD_HSIOM_SEL4__OFFSET 0x00000010 +#define CYFLD_HSIOM_SEL4__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL4_SCB1_UART_RX 0x00000009 +#define CYVAL_HSIOM_SEL4_SCB1_I2C_SCL 0x0000000e +#define CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI 0x0000000f +#define CYFLD_HSIOM_SEL5__OFFSET 0x00000014 +#define CYFLD_HSIOM_SEL5__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL5_SCB1_UART_TX 0x00000009 +#define CYVAL_HSIOM_SEL5_SCB1_I2C_SDA 0x0000000e +#define CYVAL_HSIOM_SEL5_SCB1_SPI_MISO 0x0000000f +#define CYFLD_HSIOM_SEL6__OFFSET 0x00000018 +#define CYFLD_HSIOM_SEL6__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL6_EXT_CLK 0x00000008 +#define CYVAL_HSIOM_SEL6_SCB1_SPI_CLK 0x0000000f +#define CYFLD_HSIOM_SEL7__OFFSET 0x0000001c +#define CYFLD_HSIOM_SEL7__SIZE 0x00000004 +#define CYVAL_HSIOM_SEL7_WAKEUP 0x0000000e +#define CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 0x0000000f +#define CYREG_HSIOM_PORT_SEL1 0x40010004 +#define CYREG_HSIOM_PORT_SEL2 0x40010008 +#define CYREG_HSIOM_PORT_SEL3 0x4001000c +#define CYREG_HSIOM_PORT_SEL4 0x40010010 +#define CYDEV_CLK_BASE 0x40020000 +#define CYDEV_CLK_SIZE 0x00010000 +#define CYREG_CLK_DIVIDER_A00 0x40020000 +#define CYFLD_CLK_DIVIDER_A__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_A__SIZE 0x00000010 +#define CYFLD_CLK_ENABLE_A__OFFSET 0x0000001f +#define CYFLD_CLK_ENABLE_A__SIZE 0x00000001 +#define CYREG_CLK_DIVIDER_A01 0x40020004 +#define CYREG_CLK_DIVIDER_A02 0x40020008 +#define CYREG_CLK_DIVIDER_B00 0x40020040 +#define CYFLD_CLK_DIVIDER_B__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_B__SIZE 0x00000010 +#define CYFLD_CLK_CASCADE_A_B__OFFSET 0x0000001e +#define CYFLD_CLK_CASCADE_A_B__SIZE 0x00000001 +#define CYFLD_CLK_ENABLE_B__OFFSET 0x0000001f +#define CYFLD_CLK_ENABLE_B__SIZE 0x00000001 +#define CYREG_CLK_DIVIDER_B01 0x40020044 +#define CYREG_CLK_DIVIDER_B02 0x40020048 +#define CYREG_CLK_DIVIDER_C00 0x40020080 +#define CYFLD_CLK_DIVIDER_C__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_C__SIZE 0x00000010 +#define CYFLD_CLK_CASCADE_B_C__OFFSET 0x0000001e +#define CYFLD_CLK_CASCADE_B_C__SIZE 0x00000001 +#define CYFLD_CLK_ENABLE_C__OFFSET 0x0000001f +#define CYFLD_CLK_ENABLE_C__SIZE 0x00000001 +#define CYREG_CLK_DIVIDER_C01 0x40020084 +#define CYREG_CLK_DIVIDER_C02 0x40020088 +#define CYREG_CLK_DIVIDER_FRAC_A00 0x40020100 +#define CYFLD_CLK_FRAC_A__OFFSET 0x00000010 +#define CYFLD_CLK_FRAC_A__SIZE 0x00000005 +#define CYREG_CLK_DIVIDER_FRAC_B00 0x40020140 +#define CYFLD_CLK_FRAC_B__OFFSET 0x00000010 +#define CYFLD_CLK_FRAC_B__SIZE 0x00000005 +#define CYREG_CLK_DIVIDER_FRAC_C00 0x40020180 +#define CYFLD_CLK_FRAC_C__OFFSET 0x00000010 +#define CYFLD_CLK_FRAC_C__SIZE 0x00000005 +#define CYREG_CLK_SELECT00 0x40020200 +#define CYFLD_CLK_DIVIDER_N__OFFSET 0x00000000 +#define CYFLD_CLK_DIVIDER_N__SIZE 0x00000004 +#define CYFLD_CLK_DIVIDER_ABC__OFFSET 0x00000004 +#define CYFLD_CLK_DIVIDER_ABC__SIZE 0x00000002 +#define CYVAL_CLK_DIVIDER_ABC_OFF 0x00000000 +#define CYVAL_CLK_DIVIDER_ABC_A 0x00000001 +#define CYVAL_CLK_DIVIDER_ABC_B 0x00000002 +#define CYVAL_CLK_DIVIDER_ABC_C 0x00000003 +#define CYREG_CLK_SELECT01 0x40020204 +#define CYREG_CLK_SELECT02 0x40020208 +#define CYREG_CLK_SELECT03 0x4002020c +#define CYREG_CLK_SELECT04 0x40020210 +#define CYREG_CLK_SELECT05 0x40020214 +#define CYREG_CLK_SELECT06 0x40020218 +#define CYREG_CLK_SELECT07 0x4002021c +#define CYREG_CLK_SELECT08 0x40020220 +#define CYREG_CLK_SELECT09 0x40020224 +#define CYREG_CLK_SELECT10 0x40020228 +#define CYREG_CLK_SELECT11 0x4002022c +#define CYREG_CLK_SELECT12 0x40020230 +#define CYREG_CLK_SELECT13 0x40020234 +#define CYREG_CLK_SELECT14 0x40020238 +#define CYREG_CLK_SELECT15 0x4002023c +#define CYDEV_TST_BASE 0x40030000 +#define CYDEV_TST_SIZE 0x00010000 +#define CYREG_TST_CTRL 0x40030000 +#define CYFLD_TST_DAP_NO_ACCESS__OFFSET 0x00000000 +#define CYFLD_TST_DAP_NO_ACCESS__SIZE 0x00000001 +#define CYFLD_TST_DAP_NO_DEBUG__OFFSET 0x00000001 +#define CYFLD_TST_DAP_NO_DEBUG__SIZE 0x00000001 +#define CYFLD_TST_SWD_CONNECTED__OFFSET 0x00000002 +#define CYFLD_TST_SWD_CONNECTED__SIZE 0x00000001 +#define CYFLD_TST_TEST_RESET_EN_N__OFFSET 0x00000008 +#define CYFLD_TST_TEST_RESET_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_SET_EN_N__OFFSET 0x00000009 +#define CYFLD_TST_TEST_SET_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_ICG_EN_N__OFFSET 0x0000000a +#define CYFLD_TST_TEST_ICG_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET 0x0000000b +#define CYFLD_TST_TEST_OCC0_1_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET 0x0000000c +#define CYFLD_TST_TEST_OCC0_2_EN_N__SIZE 0x00000001 +#define CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET 0x0000000d +#define CYFLD_TST_TEST_SLPISOLATE_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET 0x0000000e +#define CYFLD_TST_TEST_SYSISOLATE_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET 0x0000000f +#define CYFLD_TST_TEST_SLPRETAIN_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET 0x00000010 +#define CYFLD_TST_TEST_SYSRETAIN_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SPARE1_EN__OFFSET 0x00000011 +#define CYFLD_TST_TEST_SPARE1_EN__SIZE 0x00000001 +#define CYFLD_TST_TEST_SPARE2_EN__OFFSET 0x00000012 +#define CYFLD_TST_TEST_SPARE2_EN__SIZE 0x00000001 +#define CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET 0x00000018 +#define CYFLD_TST_SCAN_OCC_OBSERVE__SIZE 0x00000001 +#define CYFLD_TST_SCAN_TRF1__OFFSET 0x00000019 +#define CYFLD_TST_SCAN_TRF1__SIZE 0x00000001 +#define CYFLD_TST_SCAN_TRF__OFFSET 0x0000001a +#define CYFLD_TST_SCAN_TRF__SIZE 0x00000001 +#define CYFLD_TST_SCAN_IDDQ__OFFSET 0x0000001b +#define CYFLD_TST_SCAN_IDDQ__SIZE 0x00000001 +#define CYFLD_TST_SCAN_COMPRESS__OFFSET 0x0000001c +#define CYFLD_TST_SCAN_COMPRESS__SIZE 0x00000001 +#define CYFLD_TST_SCAN_MODE__OFFSET 0x0000001d +#define CYFLD_TST_SCAN_MODE__SIZE 0x00000001 +#define CYFLD_TST_PTM_MODE_EN__OFFSET 0x0000001e +#define CYFLD_TST_PTM_MODE_EN__SIZE 0x00000001 +#define CYREG_TST_ADFT_CTRL 0x40030004 +#define CYFLD_TST_ENABLE__OFFSET 0x0000001f +#define CYFLD_TST_ENABLE__SIZE 0x00000001 +#define CYREG_TST_DDFT_CTRL 0x40030008 +#define CYFLD_TST_DFT_SEL1__OFFSET 0x00000000 +#define CYFLD_TST_DFT_SEL1__SIZE 0x00000006 +#define CYVAL_TST_DFT_SEL1_VSS 0x00000000 +#define CYVAL_TST_DFT_SEL1_CLK1 0x00000001 +#define CYVAL_TST_DFT_SEL1_CLK2 0x00000002 +#define CYVAL_TST_DFT_SEL1_PWR1 0x00000003 +#define CYVAL_TST_DFT_SEL1_PWR2 0x00000004 +#define CYVAL_TST_DFT_SEL1_VMON 0x00000005 +#define CYVAL_TST_DFT_SEL1_TSS_VDDA_OK 0x00000006 +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP1 0x00000007 +#define CYVAL_TST_DFT_SEL1_ADFT_TRIP2 0x00000008 +#define CYVAL_TST_DFT_SEL1_TSS1 0x00000009 +#define CYVAL_TST_DFT_SEL1_TSS2 0x0000000a +#define CYVAL_TST_DFT_SEL1_TSS3 0x0000000b +#define CYVAL_TST_DFT_SEL1_TSS4 0x0000000c +#define CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS 0x0000000d +#define CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI 0x0000000e +#define CYFLD_TST_DFT_SEL2__OFFSET 0x00000008 +#define CYFLD_TST_DFT_SEL2__SIZE 0x00000006 +#define CYVAL_TST_DFT_SEL2_VSS 0x00000000 +#define CYVAL_TST_DFT_SEL2_CLK1 0x00000001 +#define CYVAL_TST_DFT_SEL2_CLK2 0x00000002 +#define CYVAL_TST_DFT_SEL2_PWR1 0x00000003 +#define CYVAL_TST_DFT_SEL2_PWR2 0x00000004 +#define CYVAL_TST_DFT_SEL2_VMON 0x00000005 +#define CYVAL_TST_DFT_SEL2_TSS_VDDA_OK 0x00000006 +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP1 0x00000007 +#define CYVAL_TST_DFT_SEL2_ADFT_TRIP2 0x00000008 +#define CYVAL_TST_DFT_SEL2_TSS1 0x00000009 +#define CYVAL_TST_DFT_SEL2_TSS2 0x0000000a +#define CYVAL_TST_DFT_SEL2_TSS3 0x0000000b +#define CYVAL_TST_DFT_SEL2_TSS4 0x0000000c +#define CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS 0x0000000d +#define CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI 0x0000000e +#define CYFLD_TST_EDGE__OFFSET 0x0000001c +#define CYFLD_TST_EDGE__SIZE 0x00000001 +#define CYVAL_TST_EDGE_POSEDGE 0x00000000 +#define CYVAL_TST_EDGE_NEGEDGE 0x00000001 +#define CYFLD_TST_DIVIDE__OFFSET 0x0000001d +#define CYFLD_TST_DIVIDE__SIZE 0x00000002 +#define CYVAL_TST_DIVIDE_DIRECT 0x00000000 +#define CYVAL_TST_DIVIDE_DIV_BY_2 0x00000001 +#define CYVAL_TST_DIVIDE_DIV_BY_4 0x00000002 +#define CYVAL_TST_DIVIDE_DIV_BY_8 0x00000003 +#define CYREG_TST_MODE 0x40030014 +#define CYFLD_TST_TEST_MODE__OFFSET 0x0000001f +#define CYFLD_TST_TEST_MODE__SIZE 0x00000001 +#define CYREG_TST_TRIM_CNTR1 0x40030018 +#define CYFLD_TST_COUNTER__OFFSET 0x00000000 +#define CYFLD_TST_COUNTER__SIZE 0x00000010 +#define CYFLD_TST_COUNTER_DONE__OFFSET 0x0000001f +#define CYFLD_TST_COUNTER_DONE__SIZE 0x00000001 +#define CYREG_TST_TRIM_CNTR2 0x4003001c +#define CYDEV_PRT0_BASE 0x40040000 +#define CYDEV_PRT0_SIZE 0x00000100 +#define CYREG_PRT0_DR 0x40040000 +#define CYFLD_PRT_DATAREG__OFFSET 0x00000000 +#define CYFLD_PRT_DATAREG__SIZE 0x00000008 +#define CYREG_PRT0_PS 0x40040004 +#define CYFLD_PRT_PINSTATE__OFFSET 0x00000000 +#define CYFLD_PRT_PINSTATE__SIZE 0x00000008 +#define CYFLD_PRT_PINSTATE_FLT__OFFSET 0x00000008 +#define CYFLD_PRT_PINSTATE_FLT__SIZE 0x00000001 +#define CYREG_PRT0_PC 0x40040008 +#define CYFLD_PRT_DM__OFFSET 0x00000000 +#define CYFLD_PRT_DM__SIZE 0x00000018 +#define CYVAL_PRT_DM_OFF 0x00000000 +#define CYVAL_PRT_DM_INPUT 0x00000001 +#define CYVAL_PRT_DM_0_PU 0x00000002 +#define CYVAL_PRT_DM_PD_1 0x00000003 +#define CYVAL_PRT_DM_0_Z 0x00000004 +#define CYVAL_PRT_DM_Z_1 0x00000005 +#define CYVAL_PRT_DM_0_1 0x00000006 +#define CYVAL_PRT_DM_PD_PU 0x00000007 +#define CYFLD_PRT_VTRIP_SEL__OFFSET 0x00000018 +#define CYFLD_PRT_VTRIP_SEL__SIZE 0x00000001 +#define CYFLD_PRT_SLOW__OFFSET 0x00000019 +#define CYFLD_PRT_SLOW__SIZE 0x00000001 +#define CYREG_PRT0_INTCFG 0x4004000c +#define CYFLD_PRT_INTTYPE__OFFSET 0x00000000 +#define CYFLD_PRT_INTTYPE__SIZE 0x00000010 +#define CYVAL_PRT_INTTYPE_DISABLE 0x00000000 +#define CYVAL_PRT_INTTYPE_RISING 0x00000001 +#define CYVAL_PRT_INTTYPE_FALLING 0x00000002 +#define CYVAL_PRT_INTTYPE_BOTH 0x00000003 +#define CYFLD_PRT_INTTYPE_FLT__OFFSET 0x00000010 +#define CYFLD_PRT_INTTYPE_FLT__SIZE 0x00000002 +#define CYVAL_PRT_INTTYPE_FLT_DISABLE 0x00000000 +#define CYVAL_PRT_INTTYPE_FLT_RISING 0x00000001 +#define CYVAL_PRT_INTTYPE_FLT_FALLING 0x00000002 +#define CYVAL_PRT_INTTYPE_FLT_BOTH 0x00000003 +#define CYFLD_PRT_FLT_SELECT__OFFSET 0x00000012 +#define CYFLD_PRT_FLT_SELECT__SIZE 0x00000003 +#define CYREG_PRT0_INTSTAT 0x40040010 +#define CYFLD_PRT_INTSTAT__OFFSET 0x00000000 +#define CYFLD_PRT_INTSTAT__SIZE 0x00000008 +#define CYFLD_PRT_INTSTAT_FLT__OFFSET 0x00000008 +#define CYFLD_PRT_INTSTAT_FLT__SIZE 0x00000001 +#define CYFLD_PRT_PS__OFFSET 0x00000010 +#define CYFLD_PRT_PS__SIZE 0x00000008 +#define CYFLD_PRT_PS_FLT__OFFSET 0x00000018 +#define CYFLD_PRT_PS_FLT__SIZE 0x00000001 +#define CYREG_PRT0_PC2 0x40040018 +#define CYFLD_PRT_INP_DIS__OFFSET 0x00000000 +#define CYFLD_PRT_INP_DIS__SIZE 0x00000008 +#define CYDEV_PRT1_BASE 0x40040100 +#define CYDEV_PRT1_SIZE 0x00000100 +#define CYREG_PRT1_DR 0x40040100 +#define CYREG_PRT1_PS 0x40040104 +#define CYREG_PRT1_PC 0x40040108 +#define CYREG_PRT1_INTCFG 0x4004010c +#define CYREG_PRT1_INTSTAT 0x40040110 +#define CYREG_PRT1_PC2 0x40040118 +#define CYDEV_PRT2_BASE 0x40040200 +#define CYDEV_PRT2_SIZE 0x00000100 +#define CYREG_PRT2_DR 0x40040200 +#define CYREG_PRT2_PS 0x40040204 +#define CYREG_PRT2_PC 0x40040208 +#define CYREG_PRT2_INTCFG 0x4004020c +#define CYREG_PRT2_INTSTAT 0x40040210 +#define CYREG_PRT2_PC2 0x40040218 +#define CYDEV_PRT3_BASE 0x40040300 +#define CYDEV_PRT3_SIZE 0x00000100 +#define CYREG_PRT3_DR 0x40040300 +#define CYREG_PRT3_PS 0x40040304 +#define CYREG_PRT3_PC 0x40040308 +#define CYREG_PRT3_INTCFG 0x4004030c +#define CYREG_PRT3_INTSTAT 0x40040310 +#define CYREG_PRT3_PC2 0x40040318 +#define CYDEV_PRT4_BASE 0x40040400 +#define CYDEV_PRT4_SIZE 0x00000100 +#define CYREG_PRT4_DR 0x40040400 +#define CYREG_PRT4_PS 0x40040404 +#define CYREG_PRT4_PC 0x40040408 +#define CYREG_PRT4_INTCFG 0x4004040c +#define CYREG_PRT4_INTSTAT 0x40040410 +#define CYREG_PRT4_PC2 0x40040418 +#define CYDEV_TCPWM_BASE 0x40050000 +#define CYDEV_TCPWM_SIZE 0x00001000 +#define CYREG_TCPWM_CTRL 0x40050000 +#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008 +#define CYREG_TCPWM_CMD 0x40050008 +#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008 +#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010 +#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018 +#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008 +#define CYREG_TCPWM_INTR_CAUSE 0x4005000c +#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008 +#define CYDEV_TCPWM_CNT0_BASE 0x40050100 +#define CYDEV_TCPWM_CNT0_SIZE 0x00000040 +#define CYREG_TCPWM_CNT0_CTRL 0x40050100 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003 +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007 +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010 +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003 +#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012 +#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014 +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002 +#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018 +#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003 +#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000 +#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002 +#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003 +#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004 +#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005 +#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006 +#define CYREG_TCPWM_CNT0_STATUS 0x40050104 +#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001f +#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001 +#define CYREG_TCPWM_CNT0_COUNTER 0x40050108 +#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_CC 0x4005010c +#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_CC_BUFF 0x40050110 +#define CYREG_TCPWM_CNT0_PERIOD 0x40050114 +#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40050118 +#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40050120 +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000c +#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010 +#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004 +#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40050124 +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006 +#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003 +#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40050128 +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003 +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003 +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003 +#define CYREG_TCPWM_CNT0_INTR 0x40050130 +#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001 +#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001 +#define CYREG_TCPWM_CNT0_INTR_SET 0x40050134 +#define CYREG_TCPWM_CNT0_INTR_MASK 0x40050138 +#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4005013c +#define CYDEV_TCPWM_CNT1_BASE 0x40050140 +#define CYDEV_TCPWM_CNT1_SIZE 0x00000040 +#define CYREG_TCPWM_CNT1_CTRL 0x40050140 +#define CYREG_TCPWM_CNT1_STATUS 0x40050144 +#define CYREG_TCPWM_CNT1_COUNTER 0x40050148 +#define CYREG_TCPWM_CNT1_CC 0x4005014c +#define CYREG_TCPWM_CNT1_CC_BUFF 0x40050150 +#define CYREG_TCPWM_CNT1_PERIOD 0x40050154 +#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40050158 +#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40050160 +#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40050164 +#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40050168 +#define CYREG_TCPWM_CNT1_INTR 0x40050170 +#define CYREG_TCPWM_CNT1_INTR_SET 0x40050174 +#define CYREG_TCPWM_CNT1_INTR_MASK 0x40050178 +#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4005017c +#define CYDEV_TCPWM_CNT2_BASE 0x40050180 +#define CYDEV_TCPWM_CNT2_SIZE 0x00000040 +#define CYREG_TCPWM_CNT2_CTRL 0x40050180 +#define CYREG_TCPWM_CNT2_STATUS 0x40050184 +#define CYREG_TCPWM_CNT2_COUNTER 0x40050188 +#define CYREG_TCPWM_CNT2_CC 0x4005018c +#define CYREG_TCPWM_CNT2_CC_BUFF 0x40050190 +#define CYREG_TCPWM_CNT2_PERIOD 0x40050194 +#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40050198 +#define CYREG_TCPWM_CNT2_TR_CTRL0 0x400501a0 +#define CYREG_TCPWM_CNT2_TR_CTRL1 0x400501a4 +#define CYREG_TCPWM_CNT2_TR_CTRL2 0x400501a8 +#define CYREG_TCPWM_CNT2_INTR 0x400501b0 +#define CYREG_TCPWM_CNT2_INTR_SET 0x400501b4 +#define CYREG_TCPWM_CNT2_INTR_MASK 0x400501b8 +#define CYREG_TCPWM_CNT2_INTR_MASKED 0x400501bc +#define CYDEV_TCPWM_CNT3_BASE 0x400501c0 +#define CYDEV_TCPWM_CNT3_SIZE 0x00000040 +#define CYREG_TCPWM_CNT3_CTRL 0x400501c0 +#define CYREG_TCPWM_CNT3_STATUS 0x400501c4 +#define CYREG_TCPWM_CNT3_COUNTER 0x400501c8 +#define CYREG_TCPWM_CNT3_CC 0x400501cc +#define CYREG_TCPWM_CNT3_CC_BUFF 0x400501d0 +#define CYREG_TCPWM_CNT3_PERIOD 0x400501d4 +#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x400501d8 +#define CYREG_TCPWM_CNT3_TR_CTRL0 0x400501e0 +#define CYREG_TCPWM_CNT3_TR_CTRL1 0x400501e4 +#define CYREG_TCPWM_CNT3_TR_CTRL2 0x400501e8 +#define CYREG_TCPWM_CNT3_INTR 0x400501f0 +#define CYREG_TCPWM_CNT3_INTR_SET 0x400501f4 +#define CYREG_TCPWM_CNT3_INTR_MASK 0x400501f8 +#define CYREG_TCPWM_CNT3_INTR_MASKED 0x400501fc +#define CYDEV_SCB0_BASE 0x40060000 +#define CYDEV_SCB0_SIZE 0x00010000 +#define CYREG_SCB0_CTRL 0x40060000 +#define CYFLD_SCB_OVS__OFFSET 0x00000000 +#define CYFLD_SCB_OVS__SIZE 0x00000004 +#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008 +#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001 +#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009 +#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001 +#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000a +#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001 +#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010 +#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001 +#define CYFLD_SCB_BLOCK__OFFSET 0x00000011 +#define CYFLD_SCB_BLOCK__SIZE 0x00000001 +#define CYFLD_SCB_MODE__OFFSET 0x00000018 +#define CYFLD_SCB_MODE__SIZE 0x00000002 +#define CYVAL_SCB_MODE_I2C 0x00000000 +#define CYVAL_SCB_MODE_SPI 0x00000001 +#define CYVAL_SCB_MODE_UART 0x00000002 +#define CYFLD_SCB_ENABLED__OFFSET 0x0000001f +#define CYFLD_SCB_ENABLED__SIZE 0x00000001 +#define CYREG_SCB0_STATUS 0x40060004 +#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000 +#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001 +#define CYREG_SCB0_SPI_CTRL 0x40060020 +#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000 +#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001 +#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001 +#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001 +#define CYFLD_SCB_CPHA__OFFSET 0x00000002 +#define CYFLD_SCB_CPHA__SIZE 0x00000001 +#define CYFLD_SCB_CPOL__OFFSET 0x00000003 +#define CYFLD_SCB_CPOL__SIZE 0x00000001 +#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004 +#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001 +#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010 +#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001 +#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001a +#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002 +#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001f +#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001 +#define CYREG_SCB0_SPI_STATUS 0x40060024 +#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000 +#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001 +#define CYFLD_SCB_EZ_ADDR__OFFSET 0x00000008 +#define CYFLD_SCB_EZ_ADDR__SIZE 0x00000008 +#define CYREG_SCB0_UART_CTRL 0x40060040 +#define CYREG_SCB0_UART_TX_CTRL 0x40060044 +#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000 +#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003 +#define CYFLD_SCB_PARITY__OFFSET 0x00000004 +#define CYFLD_SCB_PARITY__SIZE 0x00000001 +#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005 +#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001 +#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008 +#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001 +#define CYREG_SCB0_UART_RX_CTRL 0x40060048 +#define CYFLD_SCB_POLARITY__OFFSET 0x00000006 +#define CYFLD_SCB_POLARITY__SIZE 0x00000001 +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009 +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000a +#define CYFLD_SCB_MP_MODE__SIZE 0x00000001 +#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000c +#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001 +#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000d +#define CYFLD_SCB_SKIP_START__SIZE 0x00000001 +#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010 +#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004 +#define CYREG_SCB0_UART_RX_STATUS 0x4006004c +#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000 +#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000c +#define CYREG_SCB0_I2C_CTRL 0x40060060 +#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000 +#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004 +#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004 +#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004 +#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008 +#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001 +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009 +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001 +#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000b +#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001 +#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000c +#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000d +#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000e +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000f +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001 +#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001e +#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001 +#define CYREG_SCB0_I2C_STATUS 0x40060064 +#define CYFLD_SCB_S_READ__OFFSET 0x00000004 +#define CYFLD_SCB_S_READ__SIZE 0x00000001 +#define CYFLD_SCB_M_READ__OFFSET 0x00000005 +#define CYFLD_SCB_M_READ__SIZE 0x00000001 +#define CYREG_SCB0_I2C_M_CMD 0x40060068 +#define CYFLD_SCB_M_START__OFFSET 0x00000000 +#define CYFLD_SCB_M_START__SIZE 0x00000001 +#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001 +#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001 +#define CYFLD_SCB_M_ACK__OFFSET 0x00000002 +#define CYFLD_SCB_M_ACK__SIZE 0x00000001 +#define CYFLD_SCB_M_NACK__OFFSET 0x00000003 +#define CYFLD_SCB_M_NACK__SIZE 0x00000001 +#define CYFLD_SCB_M_STOP__OFFSET 0x00000004 +#define CYFLD_SCB_M_STOP__SIZE 0x00000001 +#define CYREG_SCB0_I2C_S_CMD 0x4006006c +#define CYFLD_SCB_S_ACK__OFFSET 0x00000000 +#define CYFLD_SCB_S_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NACK__OFFSET 0x00000001 +#define CYFLD_SCB_S_NACK__SIZE 0x00000001 +#define CYREG_SCB0_I2C_CFG 0x40060070 +#define CYFLD_SCB_SDA_FILT_HYS__OFFSET 0x00000000 +#define CYFLD_SCB_SDA_FILT_HYS__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_TRIM__OFFSET 0x00000002 +#define CYFLD_SCB_SDA_FILT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SCL_FILT_HYS__OFFSET 0x00000004 +#define CYFLD_SCB_SCL_FILT_HYS__SIZE 0x00000002 +#define CYFLD_SCB_SCL_FILT_TRIM__OFFSET 0x00000006 +#define CYFLD_SCB_SCL_FILT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET 0x00000008 +#define CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET 0x0000000a +#define CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_FILT_HS__OFFSET 0x00000010 +#define CYFLD_SCB_SDA_FILT_HS__SIZE 0x00000001 +#define CYFLD_SCB_SDA_FILT_ENABLED__OFFSET 0x00000011 +#define CYFLD_SCB_SDA_FILT_ENABLED__SIZE 0x00000001 +#define CYFLD_SCB_SCL_FILT_HS__OFFSET 0x00000018 +#define CYFLD_SCB_SCL_FILT_HS__SIZE 0x00000001 +#define CYFLD_SCB_SCL_FILT_ENABLED__OFFSET 0x00000019 +#define CYFLD_SCB_SCL_FILT_ENABLED__SIZE 0x00000001 +#define CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET 0x0000001a +#define CYFLD_SCB_SDA_FILT_OUT_HS__SIZE 0x00000001 +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET 0x0000001b +#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE 0x00000001 +#define CYREG_SCB0_BIST_CONTROL 0x40060100 +#define CYFLD_SCB_RAM_ADDR__OFFSET 0x00000000 +#define CYFLD_SCB_RAM_ADDR__SIZE 0x00000005 +#define CYFLD_SCB_RAM_OP1__OFFSET 0x00000010 +#define CYFLD_SCB_RAM_OP1__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OP2__OFFSET 0x00000012 +#define CYFLD_SCB_RAM_OP2__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OP3__OFFSET 0x00000014 +#define CYFLD_SCB_RAM_OP3__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OP4__OFFSET 0x00000016 +#define CYFLD_SCB_RAM_OP4__SIZE 0x00000002 +#define CYFLD_SCB_RAM_OPCNT__OFFSET 0x00000018 +#define CYFLD_SCB_RAM_OPCNT__SIZE 0x00000002 +#define CYFLD_SCB_RAM_PREADR__OFFSET 0x0000001a +#define CYFLD_SCB_RAM_PREADR__SIZE 0x00000001 +#define CYFLD_SCB_RAM_WORD__OFFSET 0x0000001b +#define CYFLD_SCB_RAM_WORD__SIZE 0x00000001 +#define CYFLD_SCB_RAM_FAIL__OFFSET 0x0000001c +#define CYFLD_SCB_RAM_FAIL__SIZE 0x00000001 +#define CYFLD_SCB_RAM_GO__OFFSET 0x0000001d +#define CYFLD_SCB_RAM_GO__SIZE 0x00000001 +#define CYREG_SCB0_BIST_DATA 0x40060104 +#define CYFLD_SCB_RAM_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_RAM_DATA__SIZE 0x00000010 +#define CYREG_SCB0_TX_CTRL 0x40060200 +#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000 +#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004 +#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008 +#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001 +#define CYREG_SCB0_TX_FIFO_CTRL 0x40060204 +#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000 +#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000003 +#define CYFLD_SCB_CLEAR__OFFSET 0x00000010 +#define CYFLD_SCB_CLEAR__SIZE 0x00000001 +#define CYFLD_SCB_FREEZE__OFFSET 0x00000011 +#define CYFLD_SCB_FREEZE__SIZE 0x00000001 +#define CYREG_SCB0_TX_FIFO_STATUS 0x40060208 +#define CYFLD_SCB_USED__OFFSET 0x00000000 +#define CYFLD_SCB_USED__SIZE 0x00000004 +#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000f +#define CYFLD_SCB_SR_VALID__SIZE 0x00000001 +#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010 +#define CYFLD_SCB_RD_PTR__SIZE 0x00000003 +#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018 +#define CYFLD_SCB_WR_PTR__SIZE 0x00000003 +#define CYREG_SCB0_TX_FIFO_WR 0x40060240 +#define CYFLD_SCB_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_DATA__SIZE 0x00000010 +#define CYREG_SCB0_RX_CTRL 0x40060300 +#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009 +#define CYFLD_SCB_MEDIAN__SIZE 0x00000001 +#define CYREG_SCB0_RX_FIFO_CTRL 0x40060304 +#define CYREG_SCB0_RX_FIFO_STATUS 0x40060308 +#define CYREG_SCB0_RX_MATCH 0x40060310 +#define CYFLD_SCB_ADDR__OFFSET 0x00000000 +#define CYFLD_SCB_ADDR__SIZE 0x00000008 +#define CYFLD_SCB_MASK__OFFSET 0x00000010 +#define CYFLD_SCB_MASK__SIZE 0x00000008 +#define CYREG_SCB0_RX_FIFO_RD 0x40060340 +#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40060344 +#define CYREG_SCB0_EZ_DATA00 0x40060400 +#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008 +#define CYREG_SCB0_EZ_DATA01 0x40060404 +#define CYREG_SCB0_EZ_DATA02 0x40060408 +#define CYREG_SCB0_EZ_DATA03 0x4006040c +#define CYREG_SCB0_EZ_DATA04 0x40060410 +#define CYREG_SCB0_EZ_DATA05 0x40060414 +#define CYREG_SCB0_EZ_DATA06 0x40060418 +#define CYREG_SCB0_EZ_DATA07 0x4006041c +#define CYREG_SCB0_EZ_DATA08 0x40060420 +#define CYREG_SCB0_EZ_DATA09 0x40060424 +#define CYREG_SCB0_EZ_DATA10 0x40060428 +#define CYREG_SCB0_EZ_DATA11 0x4006042c +#define CYREG_SCB0_EZ_DATA12 0x40060430 +#define CYREG_SCB0_EZ_DATA13 0x40060434 +#define CYREG_SCB0_EZ_DATA14 0x40060438 +#define CYREG_SCB0_EZ_DATA15 0x4006043c +#define CYREG_SCB0_EZ_DATA16 0x40060440 +#define CYREG_SCB0_EZ_DATA17 0x40060444 +#define CYREG_SCB0_EZ_DATA18 0x40060448 +#define CYREG_SCB0_EZ_DATA19 0x4006044c +#define CYREG_SCB0_EZ_DATA20 0x40060450 +#define CYREG_SCB0_EZ_DATA21 0x40060454 +#define CYREG_SCB0_EZ_DATA22 0x40060458 +#define CYREG_SCB0_EZ_DATA23 0x4006045c +#define CYREG_SCB0_EZ_DATA24 0x40060460 +#define CYREG_SCB0_EZ_DATA25 0x40060464 +#define CYREG_SCB0_EZ_DATA26 0x40060468 +#define CYREG_SCB0_EZ_DATA27 0x4006046c +#define CYREG_SCB0_EZ_DATA28 0x40060470 +#define CYREG_SCB0_EZ_DATA29 0x40060474 +#define CYREG_SCB0_EZ_DATA30 0x40060478 +#define CYREG_SCB0_EZ_DATA31 0x4006047c +#define CYREG_SCB0_INTR_CAUSE 0x40060e00 +#define CYFLD_SCB_M__OFFSET 0x00000000 +#define CYFLD_SCB_M__SIZE 0x00000001 +#define CYFLD_SCB_S__OFFSET 0x00000001 +#define CYFLD_SCB_S__SIZE 0x00000001 +#define CYFLD_SCB_TX__OFFSET 0x00000002 +#define CYFLD_SCB_TX__SIZE 0x00000001 +#define CYFLD_SCB_RX__OFFSET 0x00000003 +#define CYFLD_SCB_RX__SIZE 0x00000001 +#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004 +#define CYFLD_SCB_I2C_EC__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005 +#define CYFLD_SCB_SPI_EC__SIZE 0x00000001 +#define CYREG_SCB0_INTR_I2C_EC 0x40060e80 +#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000 +#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001 +#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001 +#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001 +#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002 +#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001 +#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40060e88 +#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40060e8c +#define CYREG_SCB0_INTR_SPI_EC 0x40060ec0 +#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40060ec8 +#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40060ecc +#define CYREG_SCB0_INTR_M 0x40060f00 +#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000 +#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001 +#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001 +#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001 +#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002 +#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001 +#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004 +#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001 +#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009 +#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001 +#define CYREG_SCB0_INTR_M_SET 0x40060f04 +#define CYREG_SCB0_INTR_M_MASK 0x40060f08 +#define CYREG_SCB0_INTR_M_MASKED 0x40060f0c +#define CYREG_SCB0_INTR_S 0x40060f40 +#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003 +#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001 +#define CYFLD_SCB_I2C_START__OFFSET 0x00000005 +#define CYFLD_SCB_I2C_START__SIZE 0x00000001 +#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006 +#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001 +#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007 +#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009 +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000a +#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001 +#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000b +#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001 +#define CYREG_SCB0_INTR_S_SET 0x40060f44 +#define CYREG_SCB0_INTR_S_MASK 0x40060f48 +#define CYREG_SCB0_INTR_S_MASKED 0x40060f4c +#define CYREG_SCB0_INTR_TX 0x40060f80 +#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000 +#define CYFLD_SCB_TRIGGER__SIZE 0x00000001 +#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001 +#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001 +#define CYFLD_SCB_EMPTY__OFFSET 0x00000004 +#define CYFLD_SCB_EMPTY__SIZE 0x00000001 +#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005 +#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001 +#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006 +#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001 +#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007 +#define CYFLD_SCB_BLOCKED__SIZE 0x00000001 +#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008 +#define CYFLD_SCB_UART_NACK__SIZE 0x00000001 +#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009 +#define CYFLD_SCB_UART_DONE__SIZE 0x00000001 +#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000a +#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001 +#define CYREG_SCB0_INTR_TX_SET 0x40060f84 +#define CYREG_SCB0_INTR_TX_MASK 0x40060f88 +#define CYREG_SCB0_INTR_TX_MASKED 0x40060f8c +#define CYREG_SCB0_INTR_RX 0x40060fc0 +#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002 +#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001 +#define CYFLD_SCB_FULL__OFFSET 0x00000003 +#define CYFLD_SCB_FULL__SIZE 0x00000001 +#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009 +#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000a +#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001 +#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000b +#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001 +#define CYREG_SCB0_INTR_RX_SET 0x40060fc4 +#define CYREG_SCB0_INTR_RX_MASK 0x40060fc8 +#define CYREG_SCB0_INTR_RX_MASKED 0x40060fcc +#define CYDEV_SCB1_BASE 0x40070000 +#define CYDEV_SCB1_SIZE 0x00010000 +#define CYREG_SCB1_CTRL 0x40070000 +#define CYREG_SCB1_STATUS 0x40070004 +#define CYREG_SCB1_SPI_CTRL 0x40070020 +#define CYREG_SCB1_SPI_STATUS 0x40070024 +#define CYREG_SCB1_UART_CTRL 0x40070040 +#define CYREG_SCB1_UART_TX_CTRL 0x40070044 +#define CYREG_SCB1_UART_RX_CTRL 0x40070048 +#define CYREG_SCB1_UART_RX_STATUS 0x4007004c +#define CYREG_SCB1_I2C_CTRL 0x40070060 +#define CYREG_SCB1_I2C_STATUS 0x40070064 +#define CYREG_SCB1_I2C_M_CMD 0x40070068 +#define CYREG_SCB1_I2C_S_CMD 0x4007006c +#define CYREG_SCB1_I2C_CFG 0x40070070 +#define CYREG_SCB1_BIST_CONTROL 0x40070100 +#define CYREG_SCB1_BIST_DATA 0x40070104 +#define CYREG_SCB1_TX_CTRL 0x40070200 +#define CYREG_SCB1_TX_FIFO_CTRL 0x40070204 +#define CYREG_SCB1_TX_FIFO_STATUS 0x40070208 +#define CYREG_SCB1_TX_FIFO_WR 0x40070240 +#define CYREG_SCB1_RX_CTRL 0x40070300 +#define CYREG_SCB1_RX_FIFO_CTRL 0x40070304 +#define CYREG_SCB1_RX_FIFO_STATUS 0x40070308 +#define CYREG_SCB1_RX_MATCH 0x40070310 +#define CYREG_SCB1_RX_FIFO_RD 0x40070340 +#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40070344 +#define CYREG_SCB1_EZ_DATA00 0x40070400 +#define CYREG_SCB1_EZ_DATA01 0x40070404 +#define CYREG_SCB1_EZ_DATA02 0x40070408 +#define CYREG_SCB1_EZ_DATA03 0x4007040c +#define CYREG_SCB1_EZ_DATA04 0x40070410 +#define CYREG_SCB1_EZ_DATA05 0x40070414 +#define CYREG_SCB1_EZ_DATA06 0x40070418 +#define CYREG_SCB1_EZ_DATA07 0x4007041c +#define CYREG_SCB1_EZ_DATA08 0x40070420 +#define CYREG_SCB1_EZ_DATA09 0x40070424 +#define CYREG_SCB1_EZ_DATA10 0x40070428 +#define CYREG_SCB1_EZ_DATA11 0x4007042c +#define CYREG_SCB1_EZ_DATA12 0x40070430 +#define CYREG_SCB1_EZ_DATA13 0x40070434 +#define CYREG_SCB1_EZ_DATA14 0x40070438 +#define CYREG_SCB1_EZ_DATA15 0x4007043c +#define CYREG_SCB1_EZ_DATA16 0x40070440 +#define CYREG_SCB1_EZ_DATA17 0x40070444 +#define CYREG_SCB1_EZ_DATA18 0x40070448 +#define CYREG_SCB1_EZ_DATA19 0x4007044c +#define CYREG_SCB1_EZ_DATA20 0x40070450 +#define CYREG_SCB1_EZ_DATA21 0x40070454 +#define CYREG_SCB1_EZ_DATA22 0x40070458 +#define CYREG_SCB1_EZ_DATA23 0x4007045c +#define CYREG_SCB1_EZ_DATA24 0x40070460 +#define CYREG_SCB1_EZ_DATA25 0x40070464 +#define CYREG_SCB1_EZ_DATA26 0x40070468 +#define CYREG_SCB1_EZ_DATA27 0x4007046c +#define CYREG_SCB1_EZ_DATA28 0x40070470 +#define CYREG_SCB1_EZ_DATA29 0x40070474 +#define CYREG_SCB1_EZ_DATA30 0x40070478 +#define CYREG_SCB1_EZ_DATA31 0x4007047c +#define CYREG_SCB1_INTR_CAUSE 0x40070e00 +#define CYREG_SCB1_INTR_I2C_EC 0x40070e80 +#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40070e88 +#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40070e8c +#define CYREG_SCB1_INTR_SPI_EC 0x40070ec0 +#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40070ec8 +#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40070ecc +#define CYREG_SCB1_INTR_M 0x40070f00 +#define CYREG_SCB1_INTR_M_SET 0x40070f04 +#define CYREG_SCB1_INTR_M_MASK 0x40070f08 +#define CYREG_SCB1_INTR_M_MASKED 0x40070f0c +#define CYREG_SCB1_INTR_S 0x40070f40 +#define CYREG_SCB1_INTR_S_SET 0x40070f44 +#define CYREG_SCB1_INTR_S_MASK 0x40070f48 +#define CYREG_SCB1_INTR_S_MASKED 0x40070f4c +#define CYREG_SCB1_INTR_TX 0x40070f80 +#define CYREG_SCB1_INTR_TX_SET 0x40070f84 +#define CYREG_SCB1_INTR_TX_MASK 0x40070f88 +#define CYREG_SCB1_INTR_TX_MASKED 0x40070f8c +#define CYREG_SCB1_INTR_RX 0x40070fc0 +#define CYREG_SCB1_INTR_RX_SET 0x40070fc4 +#define CYREG_SCB1_INTR_RX_MASK 0x40070fc8 +#define CYREG_SCB1_INTR_RX_MASKED 0x40070fcc +#define CYDEV_CSD_BASE 0x40080000 +#define CYDEV_CSD_SIZE 0x00010000 +#define CYREG_CSD_ID 0x40080000 +#define CYFLD_CSD_ID__OFFSET 0x00000000 +#define CYFLD_CSD_ID__SIZE 0x00000010 +#define CYFLD_CSD_REVISION__OFFSET 0x00000010 +#define CYFLD_CSD_REVISION__SIZE 0x00000010 +#define CYREG_CSD_CONFIG 0x40080004 +#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000000 +#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001 +#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x00000001 +#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001 +#define CYFLD_CSD_PRS_CLEAR__OFFSET 0x00000005 +#define CYFLD_CSD_PRS_CLEAR__SIZE 0x00000001 +#define CYFLD_CSD_PRS_SELECT__OFFSET 0x00000006 +#define CYFLD_CSD_PRS_SELECT__SIZE 0x00000001 +#define CYVAL_CSD_PRS_SELECT_DIV2 0x00000000 +#define CYVAL_CSD_PRS_SELECT_PRS 0x00000001 +#define CYFLD_CSD_PRS_12_8__OFFSET 0x00000007 +#define CYFLD_CSD_PRS_12_8__SIZE 0x00000001 +#define CYVAL_CSD_PRS_12_8_8B 0x00000000 +#define CYVAL_CSD_PRS_12_8_12B 0x00000001 +#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x00000008 +#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001 +#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000009 +#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002 +#define CYFLD_CSD_SENSE_COMP_BW__OFFSET 0x0000000b +#define CYFLD_CSD_SENSE_COMP_BW__SIZE 0x00000001 +#define CYVAL_CSD_SENSE_COMP_BW_LOW 0x00000000 +#define CYVAL_CSD_SENSE_COMP_BW_HIGH 0x00000001 +#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000c +#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001 +#define CYFLD_CSD_REFBUF_EN__OFFSET 0x0000000d +#define CYFLD_CSD_REFBUF_EN__SIZE 0x00000001 +#define CYFLD_CSD_COMP_MODE__OFFSET 0x0000000e +#define CYFLD_CSD_COMP_MODE__SIZE 0x00000001 +#define CYVAL_CSD_COMP_MODE_CHARGE_BUF 0x00000000 +#define CYVAL_CSD_COMP_MODE_CHARGE_IO 0x00000001 +#define CYFLD_CSD_COMP_PIN__OFFSET 0x0000000f +#define CYFLD_CSD_COMP_PIN__SIZE 0x00000001 +#define CYVAL_CSD_COMP_PIN_CHANNEL1 0x00000000 +#define CYVAL_CSD_COMP_PIN_CHANNEL2 0x00000001 +#define CYFLD_CSD_POLARITY__OFFSET 0x00000010 +#define CYFLD_CSD_POLARITY__SIZE 0x00000001 +#define CYVAL_CSD_POLARITY_VSSIO 0x00000000 +#define CYVAL_CSD_POLARITY_VDDIO 0x00000001 +#define CYFLD_CSD_POLARITY2__OFFSET 0x00000011 +#define CYFLD_CSD_POLARITY2__SIZE 0x00000001 +#define CYVAL_CSD_POLARITY2_VSSIO 0x00000000 +#define CYVAL_CSD_POLARITY2_VDDIO 0x00000001 +#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012 +#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001 +#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000 +#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001 +#define CYFLD_CSD_SENSE_COMP_EN__OFFSET 0x00000013 +#define CYFLD_CSD_SENSE_COMP_EN__SIZE 0x00000001 +#define CYFLD_CSD_REBUF_OUTSEL__OFFSET 0x00000015 +#define CYFLD_CSD_REBUF_OUTSEL__SIZE 0x00000001 +#define CYVAL_CSD_REBUF_OUTSEL_AMUXA 0x00000000 +#define CYVAL_CSD_REBUF_OUTSEL_AMUXB 0x00000001 +#define CYFLD_CSD_SENSE_INSEL__OFFSET 0x00000016 +#define CYFLD_CSD_SENSE_INSEL__SIZE 0x00000001 +#define CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 0x00000000 +#define CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA 0x00000001 +#define CYFLD_CSD_REFBUF_DRV__OFFSET 0x00000017 +#define CYFLD_CSD_REFBUF_DRV__SIZE 0x00000002 +#define CYVAL_CSD_REFBUF_DRV_OFF 0x00000000 +#define CYVAL_CSD_REFBUF_DRV_DRV_1 0x00000001 +#define CYVAL_CSD_REFBUF_DRV_DRV_2 0x00000002 +#define CYVAL_CSD_REFBUF_DRV_DRV_3 0x00000003 +#define CYFLD_CSD_DDFTSEL__OFFSET 0x0000001a +#define CYFLD_CSD_DDFTSEL__SIZE 0x00000003 +#define CYVAL_CSD_DDFTSEL_NORMAL 0x00000000 +#define CYVAL_CSD_DDFTSEL_CSD_SENSE 0x00000001 +#define CYVAL_CSD_DDFTSEL_CSD_SHIELD 0x00000002 +#define CYVAL_CSD_DDFTSEL_CLK_SAMPLE 0x00000003 +#define CYVAL_CSD_DDFTSEL_COMP_OUT 0x00000004 +#define CYFLD_CSD_ADFTEN__OFFSET 0x0000001d +#define CYFLD_CSD_ADFTEN__SIZE 0x00000001 +#define CYFLD_CSD_DDFTCOMP__OFFSET 0x0000001e +#define CYFLD_CSD_DDFTCOMP__SIZE 0x00000001 +#define CYVAL_CSD_DDFTCOMP_REFBUFCOMP 0x00000000 +#define CYVAL_CSD_DDFTCOMP_SENSECOMP 0x00000001 +#define CYFLD_CSD_ENABLE__OFFSET 0x0000001f +#define CYFLD_CSD_ENABLE__SIZE 0x00000001 +#define CYREG_CSD_IDAC 0x40080008 +#define CYFLD_CSD_IDAC1__OFFSET 0x00000000 +#define CYFLD_CSD_IDAC1__SIZE 0x00000008 +#define CYFLD_CSD_IDAC1_MODE__OFFSET 0x00000008 +#define CYFLD_CSD_IDAC1_MODE__SIZE 0x00000002 +#define CYVAL_CSD_IDAC1_MODE_OFF 0x00000000 +#define CYVAL_CSD_IDAC1_MODE_FIXED 0x00000001 +#define CYVAL_CSD_IDAC1_MODE_VARIABLE 0x00000002 +#define CYVAL_CSD_IDAC1_MODE_DSI 0x00000003 +#define CYFLD_CSD_IDAC1_RANGE__OFFSET 0x0000000a +#define CYFLD_CSD_IDAC1_RANGE__SIZE 0x00000001 +#define CYVAL_CSD_IDAC1_RANGE_4X 0x00000000 +#define CYVAL_CSD_IDAC1_RANGE_8X 0x00000001 +#define CYFLD_CSD_IDAC2__OFFSET 0x00000010 +#define CYFLD_CSD_IDAC2__SIZE 0x00000007 +#define CYFLD_CSD_IDAC2_MODE__OFFSET 0x00000018 +#define CYFLD_CSD_IDAC2_MODE__SIZE 0x00000002 +#define CYVAL_CSD_IDAC2_MODE_OFF 0x00000000 +#define CYVAL_CSD_IDAC2_MODE_FIXED 0x00000001 +#define CYVAL_CSD_IDAC2_MODE_VARIABLE 0x00000002 +#define CYVAL_CSD_IDAC2_MODE_DSI 0x00000003 +#define CYFLD_CSD_IDAC2_RANGE__OFFSET 0x0000001a +#define CYFLD_CSD_IDAC2_RANGE__SIZE 0x00000001 +#define CYVAL_CSD_IDAC2_RANGE_4X 0x00000000 +#define CYVAL_CSD_IDAC2_RANGE_8X 0x00000001 +#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001e +#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001 +#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000 +#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001 +#define CYREG_CSD_COUNTER 0x4008000c +#define CYFLD_CSD_COUNTER__OFFSET 0x00000000 +#define CYFLD_CSD_COUNTER__SIZE 0x00000010 +#define CYFLD_CSD_PERIOD__OFFSET 0x00000010 +#define CYFLD_CSD_PERIOD__SIZE 0x00000010 +#define CYREG_CSD_STATUS 0x40080010 +#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000 +#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001 +#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001 +#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001 +#define CYFLD_CSD_COMP_OUT__OFFSET 0x00000002 +#define CYFLD_CSD_COMP_OUT__SIZE 0x00000001 +#define CYVAL_CSD_COMP_OUT_C_LT_VREF 0x00000000 +#define CYVAL_CSD_COMP_OUT_C_GT_VREF 0x00000001 +#define CYFLD_CSD_SAMPLE__OFFSET 0x00000003 +#define CYFLD_CSD_SAMPLE__SIZE 0x00000001 +#define CYREG_CSD_INTR 0x40080014 +#define CYFLD_CSD_CSD__OFFSET 0x00000000 +#define CYFLD_CSD_CSD__SIZE 0x00000001 +#define CYREG_CSD_INTR_SET 0x40080018 +#define CYREG_CSD_TRIM1 0x4008ff00 +#define CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET 0x00000000 +#define CYFLD_CSD_IDAC1_SRC_TRIM__SIZE 0x00000004 +#define CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET 0x00000004 +#define CYFLD_CSD_IDAC2_SRC_TRIM__SIZE 0x00000004 +#define CYREG_CSD_TRIM2 0x4008ff04 +#define CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET 0x00000000 +#define CYFLD_CSD_IDAC1_SNK_TRIM__SIZE 0x00000004 +#define CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET 0x00000004 +#define CYFLD_CSD_IDAC2_SNK_TRIM__SIZE 0x00000004 +#define CYDEV_LCD_BASE 0x40090000 +#define CYDEV_LCD_SIZE 0x00010000 +#define CYREG_LCD_ID 0x40090000 +#define CYFLD_LCD_ID__OFFSET 0x00000000 +#define CYFLD_LCD_ID__SIZE 0x00000010 +#define CYFLD_LCD_REVISION__OFFSET 0x00000010 +#define CYFLD_LCD_REVISION__SIZE 0x00000010 +#define CYREG_LCD_DIVIDER 0x40090004 +#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000 +#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010 +#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010 +#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010 +#define CYREG_LCD_CONTROL 0x40090008 +#define CYFLD_LCD_LS_EN__OFFSET 0x00000000 +#define CYFLD_LCD_LS_EN__SIZE 0x00000001 +#define CYFLD_LCD_HS_EN__OFFSET 0x00000001 +#define CYFLD_LCD_HS_EN__SIZE 0x00000001 +#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002 +#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001 +#define CYVAL_LCD_LCD_MODE_LS 0x00000000 +#define CYVAL_LCD_LCD_MODE_HS 0x00000001 +#define CYFLD_LCD_TYPE__OFFSET 0x00000003 +#define CYFLD_LCD_TYPE__SIZE 0x00000001 +#define CYVAL_LCD_TYPE_A 0x00000000 +#define CYVAL_LCD_TYPE_B 0x00000001 +#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004 +#define CYFLD_LCD_OP_MODE__SIZE 0x00000001 +#define CYVAL_LCD_OP_MODE_PWM 0x00000000 +#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001 +#define CYFLD_LCD_BIAS__OFFSET 0x00000005 +#define CYFLD_LCD_BIAS__SIZE 0x00000002 +#define CYVAL_LCD_BIAS_HALF 0x00000000 +#define CYVAL_LCD_BIAS_THIRD 0x00000001 +#define CYVAL_LCD_BIAS_FOURTH 0x00000002 +#define CYVAL_LCD_BIAS_FIFTH 0x00000003 +#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008 +#define CYFLD_LCD_COM_NUM__SIZE 0x00000004 +#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001f +#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001 +#define CYREG_LCD_DATA00 0x40090100 +#define CYFLD_LCD_DATA__OFFSET 0x00000000 +#define CYFLD_LCD_DATA__SIZE 0x00000020 +#define CYREG_LCD_DATA01 0x40090104 +#define CYREG_LCD_DATA02 0x40090108 +#define CYREG_LCD_DATA03 0x4009010c +#define CYREG_LCD_DATA04 0x40090110 +#define CYDEV_LPCOMP_BASE 0x400a0000 +#define CYDEV_LPCOMP_SIZE 0x00010000 +#define CYREG_LPCOMP_ID 0x400a0000 +#define CYFLD_LPCOMP_ID__OFFSET 0x00000000 +#define CYFLD_LPCOMP_ID__SIZE 0x00000010 +#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010 +#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010 +#define CYREG_LPCOMP_CONFIG 0x400a0004 +#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000 +#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002 +#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000 +#define CYVAL_LPCOMP_MODE1_FAST 0x00000001 +#define CYVAL_LPCOMP_MODE1_ULP 0x00000002 +#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002 +#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001 +#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003 +#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001 +#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004 +#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002 +#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000 +#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001 +#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002 +#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003 +#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006 +#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001 +#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007 +#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001 +#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008 +#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002 +#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000 +#define CYVAL_LPCOMP_MODE2_FAST 0x00000001 +#define CYVAL_LPCOMP_MODE2_ULP 0x00000002 +#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000a +#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001 +#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000b +#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001 +#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000c +#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002 +#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000 +#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001 +#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002 +#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003 +#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000e +#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001 +#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000f +#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001 +#define CYREG_LPCOMP_DFT 0x400a0008 +#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000 +#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001 +#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001 +#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001 +#define CYREG_LPCOMP_INTR 0x400a000c +#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001 +#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001 +#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001 +#define CYREG_LPCOMP_INTR_SET 0x400a0010 +#define CYREG_LPCOMP_TRIM1 0x400aff00 +#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM2 0x400aff04 +#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM3 0x400aff08 +#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM4 0x400aff0c +#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005 +#define CYREG_PWR_CONTROL 0x400b0000 +#define CYFLD__POWER_MODE__OFFSET 0x00000000 +#define CYFLD__POWER_MODE__SIZE 0x00000004 +#define CYVAL__POWER_MODE_RESET 0x00000000 +#define CYVAL__POWER_MODE_ACTIVE 0x00000001 +#define CYVAL__POWER_MODE_SLEEP 0x00000002 +#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003 +#define CYVAL__POWER_MODE_HIBERNATE 0x00000004 +#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004 +#define CYFLD__DEBUG_SESSION__SIZE 0x00000001 +#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000 +#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001 +#define CYFLD__LPM_READY__OFFSET 0x00000005 +#define CYFLD__LPM_READY__SIZE 0x00000001 +#define CYFLD__EXT_VCCD__OFFSET 0x00000017 +#define CYFLD__EXT_VCCD__SIZE 0x00000001 +#define CYFLD__HVMON_ENABLE__OFFSET 0x00000018 +#define CYFLD__HVMON_ENABLE__SIZE 0x00000001 +#define CYFLD__HVMON_RELOAD__OFFSET 0x00000019 +#define CYFLD__HVMON_RELOAD__SIZE 0x00000001 +#define CYFLD__FIMO_DISABLE__OFFSET 0x0000001b +#define CYFLD__FIMO_DISABLE__SIZE 0x00000001 +#define CYFLD__HIBERNATE_DISABLE__OFFSET 0x0000001c +#define CYFLD__HIBERNATE_DISABLE__SIZE 0x00000001 +#define CYFLD__LFCLK_SHORT__OFFSET 0x0000001d +#define CYFLD__LFCLK_SHORT__SIZE 0x00000001 +#define CYFLD__HIBERNATE__OFFSET 0x0000001f +#define CYFLD__HIBERNATE__SIZE 0x00000001 +#define CYVAL__HIBERNATE_DEEP_SLEEP 0x00000000 +#define CYVAL__HIBERNATE_HIBERNATE 0x00000001 +#define CYREG_PWR_INTR 0x400b0004 +#define CYFLD__LVD__OFFSET 0x00000001 +#define CYFLD__LVD__SIZE 0x00000001 +#define CYREG_PWR_INTR_MASK 0x400b0008 +#define CYREG_PWR_KEY_DELAY 0x400b000c +#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000 +#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000a +#define CYREG_PWR_PWRSYS_CONFIG 0x400b0010 +#define CYFLD__HIB_TEST_EN__OFFSET 0x00000008 +#define CYFLD__HIB_TEST_EN__SIZE 0x00000001 +#define CYFLD__HIB_TEST_REP__OFFSET 0x00000009 +#define CYFLD__HIB_TEST_REP__SIZE 0x00000001 +#define CYREG_PWR_BG_CONFIG 0x400b0014 +#define CYFLD__BG_DFT_EN__OFFSET 0x00000000 +#define CYFLD__BG_DFT_EN__SIZE 0x00000001 +#define CYFLD__BG_DFT_VREF_SEL__OFFSET 0x00000001 +#define CYFLD__BG_DFT_VREF_SEL__SIZE 0x00000004 +#define CYFLD__BG_DFT_CORE_SEL__OFFSET 0x00000005 +#define CYFLD__BG_DFT_CORE_SEL__SIZE 0x00000001 +#define CYFLD__BG_DFT_ICORE_SEL__OFFSET 0x00000006 +#define CYFLD__BG_DFT_ICORE_SEL__SIZE 0x00000002 +#define CYFLD__BG_DFT_VCORE_SEL__OFFSET 0x00000008 +#define CYFLD__BG_DFT_VCORE_SEL__SIZE 0x00000001 +#define CYFLD__VREF_EN__OFFSET 0x00000010 +#define CYFLD__VREF_EN__SIZE 0x00000003 +#define CYREG_PWR_VMON_CONFIG 0x400b0018 +#define CYFLD__LVD_EN__OFFSET 0x00000000 +#define CYFLD__LVD_EN__SIZE 0x00000001 +#define CYFLD__LVD_SEL__OFFSET 0x00000001 +#define CYFLD__LVD_SEL__SIZE 0x00000004 +#define CYFLD__VMON_DDFT_SEL__OFFSET 0x00000005 +#define CYFLD__VMON_DDFT_SEL__SIZE 0x00000003 +#define CYFLD__VMON_ADFT_SEL__OFFSET 0x00000008 +#define CYFLD__VMON_ADFT_SEL__SIZE 0x00000002 +#define CYREG_PWR_DFT_SELECT 0x400b001c +#define CYFLD__TVMON1_SEL__OFFSET 0x00000000 +#define CYFLD__TVMON1_SEL__SIZE 0x00000003 +#define CYFLD__TVMON2_SEL__OFFSET 0x00000003 +#define CYFLD__TVMON2_SEL__SIZE 0x00000003 +#define CYFLD__BYPASS__OFFSET 0x00000006 +#define CYFLD__BYPASS__SIZE 0x00000001 +#define CYFLD__ACTIVE_EN__OFFSET 0x00000007 +#define CYFLD__ACTIVE_EN__SIZE 0x00000001 +#define CYFLD__ACTIVE_INRUSH_DIS__OFFSET 0x00000008 +#define CYFLD__ACTIVE_INRUSH_DIS__SIZE 0x00000001 +#define CYFLD__LPCOMP_DIS__OFFSET 0x00000009 +#define CYFLD__LPCOMP_DIS__SIZE 0x00000001 +#define CYFLD__BLEED_EN__OFFSET 0x0000000a +#define CYFLD__BLEED_EN__SIZE 0x00000001 +#define CYFLD__IPOR_EN__OFFSET 0x0000000b +#define CYFLD__IPOR_EN__SIZE 0x00000001 +#define CYFLD__POWER_UP_RAW_BYP__OFFSET 0x0000000c +#define CYFLD__POWER_UP_RAW_BYP__SIZE 0x00000001 +#define CYFLD__POWER_UP_RAW_CTL__OFFSET 0x0000000d +#define CYFLD__POWER_UP_RAW_CTL__SIZE 0x00000001 +#define CYFLD__DEEPSLEEP_EN__OFFSET 0x0000000e +#define CYFLD__DEEPSLEEP_EN__SIZE 0x00000001 +#define CYFLD__RSVD_BYPASS__OFFSET 0x0000000f +#define CYFLD__RSVD_BYPASS__SIZE 0x00000001 +#define CYFLD__NWELL_OPEN__OFFSET 0x00000010 +#define CYFLD__NWELL_OPEN__SIZE 0x00000001 +#define CYFLD__HIBERNATE_OPEN__OFFSET 0x00000011 +#define CYFLD__HIBERNATE_OPEN__SIZE 0x00000001 +#define CYFLD__DEEPSLEEP_OPEN__OFFSET 0x00000012 +#define CYFLD__DEEPSLEEP_OPEN__SIZE 0x00000001 +#define CYFLD__QUIET_OPEN__OFFSET 0x00000013 +#define CYFLD__QUIET_OPEN__SIZE 0x00000001 +#define CYFLD__LFCLK_OPEN__OFFSET 0x00000014 +#define CYFLD__LFCLK_OPEN__SIZE 0x00000001 +#define CYFLD__QUIET_EN__OFFSET 0x00000016 +#define CYFLD__QUIET_EN__SIZE 0x00000001 +#define CYFLD__BREF_EN__OFFSET 0x00000017 +#define CYFLD__BREF_EN__SIZE 0x00000001 +#define CYFLD__BREF_OUTEN__OFFSET 0x00000018 +#define CYFLD__BREF_OUTEN__SIZE 0x00000001 +#define CYFLD__BREF_REFSW__OFFSET 0x00000019 +#define CYFLD__BREF_REFSW__SIZE 0x00000001 +#define CYFLD__BREF_TESTMODE__OFFSET 0x0000001a +#define CYFLD__BREF_TESTMODE__SIZE 0x00000001 +#define CYFLD__NWELL_DIS__OFFSET 0x0000001b +#define CYFLD__NWELL_DIS__SIZE 0x00000001 +#define CYFLD__HVMON_DFT_OVR__OFFSET 0x0000001c +#define CYFLD__HVMON_DFT_OVR__SIZE 0x00000001 +#define CYFLD__IMO_REFGEN_DIS__OFFSET 0x0000001d +#define CYFLD__IMO_REFGEN_DIS__SIZE 0x00000001 +#define CYFLD__POWER_UP_ACTIVE__OFFSET 0x0000001e +#define CYFLD__POWER_UP_ACTIVE__SIZE 0x00000001 +#define CYFLD__POWER_UP_HIBDPSLP__OFFSET 0x0000001f +#define CYFLD__POWER_UP_HIBDPSLP__SIZE 0x00000001 +#define CYREG_PWR_DDFT_SELECT 0x400b0020 +#define CYFLD__DDFT1_SEL__OFFSET 0x00000000 +#define CYFLD__DDFT1_SEL__SIZE 0x00000004 +#define CYFLD__DDFT2_SEL__OFFSET 0x00000004 +#define CYFLD__DDFT2_SEL__SIZE 0x00000004 +#define CYREG_PWR_DFT_KEY 0x400b0024 +#define CYFLD__KEY16__OFFSET 0x00000000 +#define CYFLD__KEY16__SIZE 0x00000010 +#define CYFLD__HBOD_OFF_AWAKE__OFFSET 0x00000010 +#define CYFLD__HBOD_OFF_AWAKE__SIZE 0x00000001 +#define CYFLD__BODS_OFF__OFFSET 0x00000011 +#define CYFLD__BODS_OFF__SIZE 0x00000001 +#define CYFLD__DFT_MODE__OFFSET 0x00000012 +#define CYFLD__DFT_MODE__SIZE 0x00000001 +#define CYFLD__IO_DISABLE_BYPASS__OFFSET 0x00000013 +#define CYFLD__IO_DISABLE_BYPASS__SIZE 0x00000001 +#define CYFLD__VMON_PD__OFFSET 0x00000014 +#define CYFLD__VMON_PD__SIZE 0x00000001 +#define CYREG_PWR_BOD_KEY 0x400b0028 +#define CYREG_PWR_STOP 0x400b002c +#define CYFLD__TOKEN__OFFSET 0x00000000 +#define CYFLD__TOKEN__SIZE 0x00000008 +#define CYFLD__UNLOCK__OFFSET 0x00000008 +#define CYFLD__UNLOCK__SIZE 0x00000008 +#define CYFLD__POLARITY__OFFSET 0x00000010 +#define CYFLD__POLARITY__SIZE 0x00000001 +#define CYFLD__FREEZE__OFFSET 0x00000011 +#define CYFLD__FREEZE__SIZE 0x00000001 +#define CYFLD__STOP__OFFSET 0x0000001f +#define CYFLD__STOP__SIZE 0x00000001 +#define CYREG_CLK_SELECT 0x400b0100 +#define CYFLD__DIRECT_SEL__OFFSET 0x00000000 +#define CYFLD__DIRECT_SEL__SIZE 0x00000003 +#define CYVAL__DIRECT_SEL_IMO 0x00000000 +#define CYVAL__DIRECT_SEL_EXTCLK 0x00000001 +#define CYVAL__DIRECT_SEL_ECO 0x00000002 +#define CYVAL__DIRECT_SEL_DSI0 0x00000004 +#define CYVAL__DIRECT_SEL_DSI1 0x00000005 +#define CYVAL__DIRECT_SEL_DSI2 0x00000006 +#define CYVAL__DIRECT_SEL_DSI3 0x00000007 +#define CYFLD__DBL_SEL__OFFSET 0x00000003 +#define CYFLD__DBL_SEL__SIZE 0x00000003 +#define CYVAL__DBL_SEL_IMO 0x00000000 +#define CYVAL__DBL_SEL_EXTCLK 0x00000001 +#define CYVAL__DBL_SEL_ECO 0x00000002 +#define CYVAL__DBL_SEL_DSI0 0x00000004 +#define CYVAL__DBL_SEL_DSI1 0x00000005 +#define CYVAL__DBL_SEL_DSI2 0x00000006 +#define CYVAL__DBL_SEL_DSI3 0x00000007 +#define CYFLD__PLL_SEL__OFFSET 0x00000006 +#define CYFLD__PLL_SEL__SIZE 0x00000003 +#define CYVAL__PLL_SEL_IMO 0x00000000 +#define CYVAL__PLL_SEL_EXTCLK 0x00000001 +#define CYVAL__PLL_SEL_ECO 0x00000002 +#define CYVAL__PLL_SEL_DPLL 0x00000003 +#define CYVAL__PLL_SEL_DSI0 0x00000004 +#define CYVAL__PLL_SEL_DSI1 0x00000005 +#define CYVAL__PLL_SEL_DSI2 0x00000006 +#define CYVAL__PLL_SEL_DSI3 0x00000007 +#define CYFLD__DPLLIN_SEL__OFFSET 0x00000009 +#define CYFLD__DPLLIN_SEL__SIZE 0x00000003 +#define CYVAL__DPLLIN_SEL_IMO 0x00000000 +#define CYVAL__DPLLIN_SEL_EXTCLK 0x00000001 +#define CYVAL__DPLLIN_SEL_ECO 0x00000002 +#define CYVAL__DPLLIN_SEL_DSI0 0x00000004 +#define CYVAL__DPLLIN_SEL_DSI1 0x00000005 +#define CYVAL__DPLLIN_SEL_DSI2 0x00000006 +#define CYVAL__DPLLIN_SEL_DSI3 0x00000007 +#define CYFLD__DPLLREF_SEL__OFFSET 0x0000000c +#define CYFLD__DPLLREF_SEL__SIZE 0x00000002 +#define CYVAL__DPLLREF_SEL_DSI0 0x00000000 +#define CYVAL__DPLLREF_SEL_DSI1 0x00000001 +#define CYVAL__DPLLREF_SEL_DSI2 0x00000002 +#define CYVAL__DPLLREF_SEL_DSI3 0x00000003 +#define CYFLD__WDT_LOCK__OFFSET 0x0000000e +#define CYFLD__WDT_LOCK__SIZE 0x00000002 +#define CYVAL__WDT_LOCK_NO_CHG 0x00000000 +#define CYVAL__WDT_LOCK_CLR0 0x00000001 +#define CYVAL__WDT_LOCK_CLR1 0x00000002 +#define CYVAL__WDT_LOCK_SET01 0x00000003 +#define CYFLD__HFCLK_SEL__OFFSET 0x00000010 +#define CYFLD__HFCLK_SEL__SIZE 0x00000002 +#define CYVAL__HFCLK_SEL_DIRECT_SEL 0x00000000 +#define CYVAL__HFCLK_SEL_DBL 0x00000001 +#define CYVAL__HFCLK_SEL_PLL 0x00000002 +#define CYFLD__HALF_EN__OFFSET 0x00000012 +#define CYFLD__HALF_EN__SIZE 0x00000001 +#define CYFLD__SYSCLK_DIV__OFFSET 0x00000013 +#define CYFLD__SYSCLK_DIV__SIZE 0x00000003 +#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000 +#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001 +#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002 +#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003 +#define CYVAL__SYSCLK_DIV_DIV_BY_16 0x00000004 +#define CYVAL__SYSCLK_DIV_DIV_BY_32 0x00000005 +#define CYVAL__SYSCLK_DIV_DIV_BY_64 0x00000006 +#define CYVAL__SYSCLK_DIV_DIV_BY_128 0x00000007 +#define CYREG_CLK_ILO_CONFIG 0x400b0104 +#define CYFLD__PD_MODE__OFFSET 0x00000000 +#define CYFLD__PD_MODE__SIZE 0x00000001 +#define CYVAL__PD_MODE_SLEEP 0x00000000 +#define CYVAL__PD_MODE_COMA 0x00000001 +#define CYFLD__TURBO__OFFSET 0x00000001 +#define CYFLD__TURBO__SIZE 0x00000001 +#define CYFLD__SATBIAS__OFFSET 0x00000002 +#define CYFLD__SATBIAS__SIZE 0x00000001 +#define CYVAL__SATBIAS_SATURATED 0x00000000 +#define CYVAL__SATBIAS_SUBTHRESHOLD 0x00000001 +#define CYFLD__ENABLE__OFFSET 0x0000001f +#define CYFLD__ENABLE__SIZE 0x00000001 +#define CYREG_CLK_IMO_CONFIG 0x400b0108 +#define CYFLD__FLASHPUMP_SEL__OFFSET 0x00000016 +#define CYFLD__FLASHPUMP_SEL__SIZE 0x00000001 +#define CYVAL__FLASHPUMP_SEL_GND 0x00000000 +#define CYVAL__FLASHPUMP_SEL_CLK36 0x00000001 +#define CYFLD__EN_FASTBIAS__OFFSET 0x00000017 +#define CYFLD__EN_FASTBIAS__SIZE 0x00000001 +#define CYFLD__TEST_FASTBIAS__OFFSET 0x00000018 +#define CYFLD__TEST_FASTBIAS__SIZE 0x00000001 +#define CYFLD__PUMP_SEL__OFFSET 0x00000019 +#define CYFLD__PUMP_SEL__SIZE 0x00000003 +#define CYVAL__PUMP_SEL_GND 0x00000000 +#define CYVAL__PUMP_SEL_IMO 0x00000001 +#define CYVAL__PUMP_SEL_DBL 0x00000002 +#define CYVAL__PUMP_SEL_CLK36 0x00000003 +#define CYVAL__PUMP_SEL_FF1 0x00000004 +#define CYFLD__TEST_USB_MODE__OFFSET 0x0000001c +#define CYFLD__TEST_USB_MODE__SIZE 0x00000001 +#define CYFLD__EN_CLK36__OFFSET 0x0000001d +#define CYFLD__EN_CLK36__SIZE 0x00000001 +#define CYFLD__EN_CLK2X__OFFSET 0x0000001e +#define CYFLD__EN_CLK2X__SIZE 0x00000001 +#define CYREG_CLK_IMO_SPREAD 0x400b010c +#define CYFLD__SS_VALUE__OFFSET 0x00000000 +#define CYFLD__SS_VALUE__SIZE 0x00000005 +#define CYFLD__SS_MAX__OFFSET 0x00000008 +#define CYFLD__SS_MAX__SIZE 0x00000005 +#define CYFLD__SS_RANGE__OFFSET 0x0000001c +#define CYFLD__SS_RANGE__SIZE 0x00000002 +#define CYVAL__SS_RANGE_M1 0x00000000 +#define CYVAL__SS_RANGE_M2 0x00000001 +#define CYVAL__SS_RANGE_M4 0x00000002 +#define CYFLD__SS_MODE__OFFSET 0x0000001e +#define CYFLD__SS_MODE__SIZE 0x00000002 +#define CYVAL__SS_MODE_OFF 0x00000000 +#define CYVAL__SS_MODE_TRIANGLE 0x00000001 +#define CYVAL__SS_MODE_LFSR 0x00000002 +#define CYVAL__SS_MODE_DSI 0x00000003 +#define CYREG_CLK_DFT_SELECT 0x400b0110 +#define CYFLD__DFT_SEL1__OFFSET 0x00000000 +#define CYFLD__DFT_SEL1__SIZE 0x00000004 +#define CYVAL__DFT_SEL1_NC 0x00000000 +#define CYVAL__DFT_SEL1_ILO 0x00000001 +#define CYVAL__DFT_SEL1_WCO 0x00000002 +#define CYVAL__DFT_SEL1_IMO 0x00000003 +#define CYVAL__DFT_SEL1_ECO 0x00000004 +#define CYVAL__DFT_SEL1_PLL 0x00000005 +#define CYVAL__DFT_SEL1_DPLL_OUT 0x00000006 +#define CYVAL__DFT_SEL1_DPLL_REF 0x00000007 +#define CYVAL__DFT_SEL1_DBL 0x00000008 +#define CYVAL__DFT_SEL1_IMO2X 0x00000009 +#define CYVAL__DFT_SEL1_IMO36 0x0000000a +#define CYVAL__DFT_SEL1_HFCLK 0x0000000b +#define CYVAL__DFT_SEL1_LFCLK 0x0000000c +#define CYVAL__DFT_SEL1_SYSCLK 0x0000000d +#define CYVAL__DFT_SEL1_EXTCLK 0x0000000e +#define CYVAL__DFT_SEL1_HALFSYSCLK 0x0000000f +#define CYFLD__DFT_DIV1__OFFSET 0x00000004 +#define CYFLD__DFT_DIV1__SIZE 0x00000002 +#define CYVAL__DFT_DIV1_NO_DIV 0x00000000 +#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001 +#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002 +#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003 +#define CYFLD__DFT_SEL2__OFFSET 0x00000008 +#define CYFLD__DFT_SEL2__SIZE 0x00000004 +#define CYVAL__DFT_SEL2_NC 0x00000000 +#define CYVAL__DFT_SEL2_ILO 0x00000001 +#define CYVAL__DFT_SEL2_WCO 0x00000002 +#define CYVAL__DFT_SEL2_IMO 0x00000003 +#define CYVAL__DFT_SEL2_ECO 0x00000004 +#define CYVAL__DFT_SEL2_PLL 0x00000005 +#define CYVAL__DFT_SEL2_DPLL_OUT 0x00000006 +#define CYVAL__DFT_SEL2_DPLL_REF 0x00000007 +#define CYVAL__DFT_SEL2_DBL 0x00000008 +#define CYVAL__DFT_SEL2_IMO2X 0x00000009 +#define CYVAL__DFT_SEL2_IMO36 0x0000000a +#define CYVAL__DFT_SEL2_HFCLK 0x0000000b +#define CYVAL__DFT_SEL2_LFCLK 0x0000000c +#define CYVAL__DFT_SEL2_SYSCLK 0x0000000d +#define CYVAL__DFT_SEL2_EXTCLK 0x0000000e +#define CYVAL__DFT_SEL2_HALFSYSCLK 0x0000000f +#define CYFLD__DFT_DIV2__OFFSET 0x0000000c +#define CYFLD__DFT_DIV2__SIZE 0x00000002 +#define CYVAL__DFT_DIV2_NO_DIV 0x00000000 +#define CYVAL__DFT_DIV2_DIV_BY_2 0x00000001 +#define CYVAL__DFT_DIV2_DIV_BY_4 0x00000002 +#define CYVAL__DFT_DIV2_DIV_BY_8 0x00000003 +#define CYREG_WDT_CTRLOW 0x400b0200 +#define CYFLD__WDT_CTR0__OFFSET 0x00000000 +#define CYFLD__WDT_CTR0__SIZE 0x00000010 +#define CYFLD__WDT_CTR1__OFFSET 0x00000010 +#define CYFLD__WDT_CTR1__SIZE 0x00000010 +#define CYREG_WDT_CTRHIGH 0x400b0204 +#define CYFLD__WDT_CTR2__OFFSET 0x00000000 +#define CYFLD__WDT_CTR2__SIZE 0x00000020 +#define CYREG_WDT_MATCH 0x400b0208 +#define CYFLD__WDT_MATCH0__OFFSET 0x00000000 +#define CYFLD__WDT_MATCH0__SIZE 0x00000010 +#define CYFLD__WDT_MATCH1__OFFSET 0x00000010 +#define CYFLD__WDT_MATCH1__SIZE 0x00000010 +#define CYREG_WDT_CONFIG 0x400b020c +#define CYFLD__WDT_MODE0__OFFSET 0x00000000 +#define CYFLD__WDT_MODE0__SIZE 0x00000002 +#define CYVAL__WDT_MODE0_NOTHING 0x00000000 +#define CYVAL__WDT_MODE0_INT 0x00000001 +#define CYVAL__WDT_MODE0_RESET 0x00000002 +#define CYVAL__WDT_MODE0_INT_THEN_RESET 0x00000003 +#define CYFLD__WDT_CLEAR0__OFFSET 0x00000002 +#define CYFLD__WDT_CLEAR0__SIZE 0x00000001 +#define CYFLD__WDT_CASCADE0_1__OFFSET 0x00000003 +#define CYFLD__WDT_CASCADE0_1__SIZE 0x00000001 +#define CYFLD__WDT_MODE1__OFFSET 0x00000008 +#define CYFLD__WDT_MODE1__SIZE 0x00000002 +#define CYVAL__WDT_MODE1_NOTHING 0x00000000 +#define CYVAL__WDT_MODE1_INT 0x00000001 +#define CYVAL__WDT_MODE1_RESET 0x00000002 +#define CYVAL__WDT_MODE1_INT_THEN_RESET 0x00000003 +#define CYFLD__WDT_CLEAR1__OFFSET 0x0000000a +#define CYFLD__WDT_CLEAR1__SIZE 0x00000001 +#define CYFLD__WDT_CASCADE1_2__OFFSET 0x0000000b +#define CYFLD__WDT_CASCADE1_2__SIZE 0x00000001 +#define CYFLD__WDT_MODE2__OFFSET 0x00000010 +#define CYFLD__WDT_MODE2__SIZE 0x00000001 +#define CYVAL__WDT_MODE2_NOTHING 0x00000000 +#define CYVAL__WDT_MODE2_INT 0x00000001 +#define CYFLD__WDT_BITS2__OFFSET 0x00000018 +#define CYFLD__WDT_BITS2__SIZE 0x00000005 +#define CYFLD__LFCLK_SEL__OFFSET 0x0000001e +#define CYFLD__LFCLK_SEL__SIZE 0x00000002 +#define CYREG_WDT_CONTROL 0x400b0210 +#define CYFLD__WDT_ENABLE0__OFFSET 0x00000000 +#define CYFLD__WDT_ENABLE0__SIZE 0x00000001 +#define CYFLD__WDT_ENABLED0__OFFSET 0x00000001 +#define CYFLD__WDT_ENABLED0__SIZE 0x00000001 +#define CYFLD__WDT_INT0__OFFSET 0x00000002 +#define CYFLD__WDT_INT0__SIZE 0x00000001 +#define CYFLD__WDT_RESET0__OFFSET 0x00000003 +#define CYFLD__WDT_RESET0__SIZE 0x00000001 +#define CYFLD__WDT_ENABLE1__OFFSET 0x00000008 +#define CYFLD__WDT_ENABLE1__SIZE 0x00000001 +#define CYFLD__WDT_ENABLED1__OFFSET 0x00000009 +#define CYFLD__WDT_ENABLED1__SIZE 0x00000001 +#define CYFLD__WDT_INT1__OFFSET 0x0000000a +#define CYFLD__WDT_INT1__SIZE 0x00000001 +#define CYFLD__WDT_RESET1__OFFSET 0x0000000b +#define CYFLD__WDT_RESET1__SIZE 0x00000001 +#define CYFLD__WDT_ENABLE2__OFFSET 0x00000010 +#define CYFLD__WDT_ENABLE2__SIZE 0x00000001 +#define CYFLD__WDT_ENABLED2__OFFSET 0x00000011 +#define CYFLD__WDT_ENABLED2__SIZE 0x00000001 +#define CYFLD__WDT_INT2__OFFSET 0x00000012 +#define CYFLD__WDT_INT2__SIZE 0x00000001 +#define CYFLD__WDT_RESET2__OFFSET 0x00000013 +#define CYFLD__WDT_RESET2__SIZE 0x00000001 +#define CYREG_RES_CAUSE 0x400b0300 +#define CYFLD__RESET_WDT__OFFSET 0x00000000 +#define CYFLD__RESET_WDT__SIZE 0x00000001 +#define CYFLD__RESET_DSBOD__OFFSET 0x00000001 +#define CYFLD__RESET_DSBOD__SIZE 0x00000001 +#define CYFLD__RESET_LOCKUP__OFFSET 0x00000002 +#define CYFLD__RESET_LOCKUP__SIZE 0x00000001 +#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003 +#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001 +#define CYFLD__RESET_SOFT__OFFSET 0x00000004 +#define CYFLD__RESET_SOFT__SIZE 0x00000001 +#define CYFLD__RESET_HVBOD__OFFSET 0x00000005 +#define CYFLD__RESET_HVBOD__SIZE 0x00000001 +#define CYFLD__RESET_PBOD__OFFSET 0x00000006 +#define CYFLD__RESET_PBOD__SIZE 0x00000001 +#define CYFLD__RESET_XRES__OFFSET 0x00000007 +#define CYFLD__RESET_XRES__SIZE 0x00000001 +#define CYREG_PWR_PWRSYS_TRIM1 0x400bff00 +#define CYFLD__HIB_BIAS_TRIM__OFFSET 0x00000000 +#define CYFLD__HIB_BIAS_TRIM__SIZE 0x00000003 +#define CYFLD__BOD_TURBO_THRESH__OFFSET 0x00000003 +#define CYFLD__BOD_TURBO_THRESH__SIZE 0x00000001 +#define CYFLD__BOD_TRIM_TRIP__OFFSET 0x00000004 +#define CYFLD__BOD_TRIM_TRIP__SIZE 0x00000004 +#define CYREG_PWR_PWRSYS_TRIM2 0x400bff04 +#define CYFLD__LFCLK_TRIM_LOAD__OFFSET 0x00000000 +#define CYFLD__LFCLK_TRIM_LOAD__SIZE 0x00000002 +#define CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET 0x00000002 +#define CYFLD__LFCLK_TRIM_VOLTAGE__SIZE 0x00000002 +#define CYFLD__DPSLP_TRIM_LOAD__OFFSET 0x00000004 +#define CYFLD__DPSLP_TRIM_LOAD__SIZE 0x00000002 +#define CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET 0x00000006 +#define CYFLD__DPSLP_TRIM_LEAKAGE__SIZE 0x00000001 +#define CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET 0x00000007 +#define CYFLD__DPSLP_TRIM_VOLTAGE__SIZE 0x00000001 +#define CYREG_PWR_PWRSYS_TRIM3 0x400bff08 +#define CYFLD__NWELL_TRIM__OFFSET 0x00000000 +#define CYFLD__NWELL_TRIM__SIZE 0x00000003 +#define CYFLD__QUIET_TRIM__OFFSET 0x00000003 +#define CYFLD__QUIET_TRIM__SIZE 0x00000005 +#define CYREG_PWR_PWRSYS_TRIM4 0x400bff0c +#define CYFLD__HIB_TRIM_NWELL__OFFSET 0x00000000 +#define CYFLD__HIB_TRIM_NWELL__SIZE 0x00000002 +#define CYFLD__HIB_TRIM_LEAKAGE__OFFSET 0x00000002 +#define CYFLD__HIB_TRIM_LEAKAGE__SIZE 0x00000001 +#define CYFLD__HIB_TRIM_VOLTAGE__OFFSET 0x00000003 +#define CYFLD__HIB_TRIM_VOLTAGE__SIZE 0x00000001 +#define CYFLD__HIB_TRIM_REFERENCE__OFFSET 0x00000004 +#define CYFLD__HIB_TRIM_REFERENCE__SIZE 0x00000002 +#define CYREG_PWR_BG_TRIM1 0x400bff10 +#define CYFLD__INL_TRIM_MAIN__OFFSET 0x00000000 +#define CYFLD__INL_TRIM_MAIN__SIZE 0x00000003 +#define CYFLD__INL_CROSS_MAIN__OFFSET 0x00000003 +#define CYFLD__INL_CROSS_MAIN__SIZE 0x00000004 +#define CYREG_PWR_BG_TRIM2 0x400bff14 +#define CYFLD__VCTAT_SLOPE__OFFSET 0x00000000 +#define CYFLD__VCTAT_SLOPE__SIZE 0x00000004 +#define CYFLD__VCTAT_VOLTAGE__OFFSET 0x00000004 +#define CYFLD__VCTAT_VOLTAGE__SIZE 0x00000002 +#define CYFLD__VCTAT_ENABLE__OFFSET 0x00000006 +#define CYFLD__VCTAT_ENABLE__SIZE 0x00000001 +#define CYFLD__VCTAT_VOLTAGE_MSB__OFFSET 0x00000007 +#define CYFLD__VCTAT_VOLTAGE_MSB__SIZE 0x00000001 +#define CYREG_PWR_BG_TRIM3 0x400bff18 +#define CYFLD__INL_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD__INL_TRIM_IMO__SIZE 0x00000003 +#define CYFLD__INL_CROSS_IMO__OFFSET 0x00000003 +#define CYFLD__INL_CROSS_IMO__SIZE 0x00000004 +#define CYREG_PWR_BG_TRIM4 0x400bff1c +#define CYFLD__ABS_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD__ABS_TRIM_IMO__SIZE 0x00000006 +#define CYREG_PWR_BG_TRIM5 0x400bff20 +#define CYFLD__TMPCO_TRIM_IMO__OFFSET 0x00000000 +#define CYFLD__TMPCO_TRIM_IMO__SIZE 0x00000006 +#define CYREG_CLK_ILO_TRIM 0x400bff24 +#define CYFLD__TRIM__OFFSET 0x00000000 +#define CYFLD__TRIM__SIZE 0x00000004 +#define CYFLD__COARSE_TRIM__OFFSET 0x00000004 +#define CYFLD__COARSE_TRIM__SIZE 0x00000004 +#define CYREG_CLK_IMO_TRIM1 0x400bff28 +#define CYFLD__OFFSET__OFFSET 0x00000000 +#define CYFLD__OFFSET__SIZE 0x00000008 +#define CYREG_CLK_IMO_TRIM2 0x400bff2c +#define CYFLD__FREQ__OFFSET 0x00000000 +#define CYFLD__FREQ__SIZE 0x00000006 +#define CYREG_CLK_IMO_TRIM3 0x400bff30 +#define CYFLD__TRIM_CLK36__OFFSET 0x00000000 +#define CYFLD__TRIM_CLK36__SIZE 0x00000004 +#define CYREG_CLK_IMO_TRIM4 0x400bff34 +#define CYFLD__GAIN__OFFSET 0x00000000 +#define CYFLD__GAIN__SIZE 0x00000005 +#define CYFLD__FSOFFSET__OFFSET 0x00000005 +#define CYFLD__FSOFFSET__SIZE 0x00000003 +#define CYREG_PWR_RSVD_TRIM 0x400bff38 +#define CYFLD__RSVD_TRIM__OFFSET 0x00000000 +#define CYFLD__RSVD_TRIM__SIZE 0x00000004 +#define CYDEV_SPCIF_BASE 0x400e0000 +#define CYDEV_SPCIF_SIZE 0x00010000 +#define CYREG_SPCIF_GEOMETRY 0x400e0000 +#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000 +#define CYFLD_SPCIF_FLASH__SIZE 0x00000010 +#define CYFLD_SPCIF_SFLASH__OFFSET 0x00000010 +#define CYFLD_SPCIF_SFLASH__SIZE 0x00000004 +#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014 +#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002 +#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016 +#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002 +#define CYFLD_SPCIF_NVL__OFFSET 0x00000018 +#define CYFLD_SPCIF_NVL__SIZE 0x00000007 +#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001f +#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001 +#define CYREG_SPCIF_NVL_WR_DATA 0x400e001c +#define CYFLD_SPCIF_DATA__OFFSET 0x00000000 +#define CYFLD_SPCIF_DATA__SIZE 0x00000008 +#define CYDEV_UDB_BASE 0x400f0000 +#define CYDEV_UDB_SIZE 0x00010000 +#define CYDEV_UDB_W8_BASE 0x400f0000 +#define CYDEV_UDB_W8_SIZE 0x00001000 +#define CYREG_UDB_W8_A0_00 0x400f0000 +#define CYFLD_UDB_W8_A0__OFFSET 0x00000000 +#define CYFLD_UDB_W8_A0__SIZE 0x00000008 +#define CYREG_UDB_W8_A0_01 0x400f0001 +#define CYREG_UDB_W8_A0_02 0x400f0002 +#define CYREG_UDB_W8_A0_03 0x400f0003 +#define CYREG_UDB_W8_A1_00 0x400f0010 +#define CYFLD_UDB_W8_A1__OFFSET 0x00000000 +#define CYFLD_UDB_W8_A1__SIZE 0x00000008 +#define CYREG_UDB_W8_A1_01 0x400f0011 +#define CYREG_UDB_W8_A1_02 0x400f0012 +#define CYREG_UDB_W8_A1_03 0x400f0013 +#define CYREG_UDB_W8_D0_00 0x400f0020 +#define CYFLD_UDB_W8_D0__OFFSET 0x00000000 +#define CYFLD_UDB_W8_D0__SIZE 0x00000008 +#define CYREG_UDB_W8_D0_01 0x400f0021 +#define CYREG_UDB_W8_D0_02 0x400f0022 +#define CYREG_UDB_W8_D0_03 0x400f0023 +#define CYREG_UDB_W8_D1_00 0x400f0030 +#define CYFLD_UDB_W8_D1__OFFSET 0x00000000 +#define CYFLD_UDB_W8_D1__SIZE 0x00000008 +#define CYREG_UDB_W8_D1_01 0x400f0031 +#define CYREG_UDB_W8_D1_02 0x400f0032 +#define CYREG_UDB_W8_D1_03 0x400f0033 +#define CYREG_UDB_W8_F0_00 0x400f0040 +#define CYFLD_UDB_W8_F0__OFFSET 0x00000000 +#define CYFLD_UDB_W8_F0__SIZE 0x00000008 +#define CYREG_UDB_W8_F0_01 0x400f0041 +#define CYREG_UDB_W8_F0_02 0x400f0042 +#define CYREG_UDB_W8_F0_03 0x400f0043 +#define CYREG_UDB_W8_F1_00 0x400f0050 +#define CYFLD_UDB_W8_F1__OFFSET 0x00000000 +#define CYFLD_UDB_W8_F1__SIZE 0x00000008 +#define CYREG_UDB_W8_F1_01 0x400f0051 +#define CYREG_UDB_W8_F1_02 0x400f0052 +#define CYREG_UDB_W8_F1_03 0x400f0053 +#define CYREG_UDB_W8_ST_00 0x400f0060 +#define CYFLD_UDB_W8_ST__OFFSET 0x00000000 +#define CYFLD_UDB_W8_ST__SIZE 0x00000008 +#define CYREG_UDB_W8_ST_01 0x400f0061 +#define CYREG_UDB_W8_ST_02 0x400f0062 +#define CYREG_UDB_W8_ST_03 0x400f0063 +#define CYREG_UDB_W8_CTL_00 0x400f0070 +#define CYFLD_UDB_W8_CTL__OFFSET 0x00000000 +#define CYFLD_UDB_W8_CTL__SIZE 0x00000008 +#define CYREG_UDB_W8_CTL_01 0x400f0071 +#define CYREG_UDB_W8_CTL_02 0x400f0072 +#define CYREG_UDB_W8_CTL_03 0x400f0073 +#define CYREG_UDB_W8_MSK_00 0x400f0080 +#define CYFLD_UDB_W8_MSK__OFFSET 0x00000000 +#define CYFLD_UDB_W8_MSK__SIZE 0x00000007 +#define CYREG_UDB_W8_MSK_01 0x400f0081 +#define CYREG_UDB_W8_MSK_02 0x400f0082 +#define CYREG_UDB_W8_MSK_03 0x400f0083 +#define CYREG_UDB_W8_ACTL_00 0x400f0090 +#define CYFLD_UDB_W8_FIFO0_CLR__OFFSET 0x00000000 +#define CYFLD_UDB_W8_FIFO0_CLR__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO0_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO0_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_W8_FIFO1_CLR__OFFSET 0x00000001 +#define CYFLD_UDB_W8_FIFO1_CLR__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO1_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO1_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_W8_FIFO0_LVL__OFFSET 0x00000002 +#define CYFLD_UDB_W8_FIFO0_LVL__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO0_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO0_LVL_MID 0x00000001 +#define CYFLD_UDB_W8_FIFO1_LVL__OFFSET 0x00000003 +#define CYFLD_UDB_W8_FIFO1_LVL__SIZE 0x00000001 +#define CYVAL_UDB_W8_FIFO1_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_W8_FIFO1_LVL_MID 0x00000001 +#define CYFLD_UDB_W8_INT_EN__OFFSET 0x00000004 +#define CYFLD_UDB_W8_INT_EN__SIZE 0x00000001 +#define CYVAL_UDB_W8_INT_EN_DISABLE 0x00000000 +#define CYVAL_UDB_W8_INT_EN_ENABLE 0x00000001 +#define CYFLD_UDB_W8_CNT_START__OFFSET 0x00000005 +#define CYFLD_UDB_W8_CNT_START__SIZE 0x00000001 +#define CYVAL_UDB_W8_CNT_START_DISABLE 0x00000000 +#define CYVAL_UDB_W8_CNT_START_ENABLE 0x00000001 +#define CYREG_UDB_W8_ACTL_01 0x400f0091 +#define CYREG_UDB_W8_ACTL_02 0x400f0092 +#define CYREG_UDB_W8_ACTL_03 0x400f0093 +#define CYREG_UDB_W8_MC_00 0x400f00a0 +#define CYFLD_UDB_W8_PLD0_MC__OFFSET 0x00000000 +#define CYFLD_UDB_W8_PLD0_MC__SIZE 0x00000004 +#define CYFLD_UDB_W8_PLD1_MC__OFFSET 0x00000004 +#define CYFLD_UDB_W8_PLD1_MC__SIZE 0x00000004 +#define CYREG_UDB_W8_MC_01 0x400f00a1 +#define CYREG_UDB_W8_MC_02 0x400f00a2 +#define CYREG_UDB_W8_MC_03 0x400f00a3 +#define CYDEV_UDB_CAT16_BASE 0x400f1000 +#define CYDEV_UDB_CAT16_SIZE 0x00001000 +#define CYREG_UDB_CAT16_A_00 0x400f1000 +#define CYFLD_UDB_CAT16_A0__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_A0__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_A1__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_A1__SIZE 0x00000008 +#define CYREG_UDB_CAT16_A_01 0x400f1002 +#define CYREG_UDB_CAT16_A_02 0x400f1004 +#define CYREG_UDB_CAT16_A_03 0x400f1006 +#define CYREG_UDB_CAT16_D_00 0x400f1040 +#define CYFLD_UDB_CAT16_D0__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_D0__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_D1__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_D1__SIZE 0x00000008 +#define CYREG_UDB_CAT16_D_01 0x400f1042 +#define CYREG_UDB_CAT16_D_02 0x400f1044 +#define CYREG_UDB_CAT16_D_03 0x400f1046 +#define CYREG_UDB_CAT16_F_00 0x400f1080 +#define CYFLD_UDB_CAT16_F0__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_F0__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_F1__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_F1__SIZE 0x00000008 +#define CYREG_UDB_CAT16_F_01 0x400f1082 +#define CYREG_UDB_CAT16_F_02 0x400f1084 +#define CYREG_UDB_CAT16_F_03 0x400f1086 +#define CYREG_UDB_CAT16_CTL_ST_00 0x400f10c0 +#define CYFLD_UDB_CAT16_ST__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_ST__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_CTL__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_CTL__SIZE 0x00000008 +#define CYREG_UDB_CAT16_CTL_ST_01 0x400f10c2 +#define CYREG_UDB_CAT16_CTL_ST_02 0x400f10c4 +#define CYREG_UDB_CAT16_CTL_ST_03 0x400f10c6 +#define CYREG_UDB_CAT16_ACTL_MSK_00 0x400f1100 +#define CYFLD_UDB_CAT16_MSK__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_MSK__SIZE 0x00000008 +#define CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET 0x00000008 +#define CYFLD_UDB_CAT16_FIFO0_CLR__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET 0x00000009 +#define CYFLD_UDB_CAT16_FIFO1_CLR__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR 0x00000001 +#define CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET 0x0000000a +#define CYFLD_UDB_CAT16_FIFO0_LVL__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO0_LVL_MID 0x00000001 +#define CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET 0x0000000b +#define CYFLD_UDB_CAT16_FIFO1_LVL__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL 0x00000000 +#define CYVAL_UDB_CAT16_FIFO1_LVL_MID 0x00000001 +#define CYFLD_UDB_CAT16_INT_EN__OFFSET 0x0000000c +#define CYFLD_UDB_CAT16_INT_EN__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_INT_EN_DISABLE 0x00000000 +#define CYVAL_UDB_CAT16_INT_EN_ENABLE 0x00000001 +#define CYFLD_UDB_CAT16_CNT_START__OFFSET 0x0000000d +#define CYFLD_UDB_CAT16_CNT_START__SIZE 0x00000001 +#define CYVAL_UDB_CAT16_CNT_START_DISABLE 0x00000000 +#define CYVAL_UDB_CAT16_CNT_START_ENABLE 0x00000001 +#define CYREG_UDB_CAT16_ACTL_MSK_01 0x400f1102 +#define CYREG_UDB_CAT16_ACTL_MSK_02 0x400f1104 +#define CYREG_UDB_CAT16_ACTL_MSK_03 0x400f1106 +#define CYREG_UDB_CAT16_MC_00 0x400f1140 +#define CYFLD_UDB_CAT16_PLD0_MC__OFFSET 0x00000000 +#define CYFLD_UDB_CAT16_PLD0_MC__SIZE 0x00000004 +#define CYFLD_UDB_CAT16_PLD1_MC__OFFSET 0x00000004 +#define CYFLD_UDB_CAT16_PLD1_MC__SIZE 0x00000004 +#define CYREG_UDB_CAT16_MC_01 0x400f1142 +#define CYREG_UDB_CAT16_MC_02 0x400f1144 +#define CYREG_UDB_CAT16_MC_03 0x400f1146 +#define CYDEV_UDB_W16_BASE 0x400f1000 +#define CYDEV_UDB_W16_SIZE 0x00001000 +#define CYREG_UDB_W16_A0_00 0x400f1000 +#define CYFLD_UDB_W16_A0_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_A0_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_A0_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_A0_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_A0_01 0x400f1002 +#define CYREG_UDB_W16_A0_02 0x400f1004 +#define CYREG_UDB_W16_A1_00 0x400f1020 +#define CYFLD_UDB_W16_A1_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_A1_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_A1_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_A1_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_A1_01 0x400f1022 +#define CYREG_UDB_W16_A1_02 0x400f1024 +#define CYREG_UDB_W16_D0_00 0x400f1040 +#define CYFLD_UDB_W16_D0_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_D0_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_D0_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_D0_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_D0_01 0x400f1042 +#define CYREG_UDB_W16_D0_02 0x400f1044 +#define CYREG_UDB_W16_D1_00 0x400f1060 +#define CYFLD_UDB_W16_D1_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_D1_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_D1_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_D1_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_D1_01 0x400f1062 +#define CYREG_UDB_W16_D1_02 0x400f1064 +#define CYREG_UDB_W16_F0_00 0x400f1080 +#define CYFLD_UDB_W16_F0_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_F0_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_F0_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_F0_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_F0_01 0x400f1082 +#define CYREG_UDB_W16_F0_02 0x400f1084 +#define CYREG_UDB_W16_F1_00 0x400f10a0 +#define CYFLD_UDB_W16_F1_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_F1_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_F1_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_F1_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_F1_01 0x400f10a2 +#define CYREG_UDB_W16_F1_02 0x400f10a4 +#define CYREG_UDB_W16_ST_00 0x400f10c0 +#define CYFLD_UDB_W16_ST_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_ST_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_ST_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_ST_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_ST_01 0x400f10c2 +#define CYREG_UDB_W16_ST_02 0x400f10c4 +#define CYREG_UDB_W16_CTL_00 0x400f10e0 +#define CYFLD_UDB_W16_CTL_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_CTL_LS__SIZE 0x00000008 +#define CYFLD_UDB_W16_CTL_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_CTL_MS__SIZE 0x00000008 +#define CYREG_UDB_W16_CTL_01 0x400f10e2 +#define CYREG_UDB_W16_CTL_02 0x400f10e4 +#define CYREG_UDB_W16_MSK_00 0x400f1100 +#define CYFLD_UDB_W16_MSK_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_MSK_LS__SIZE 0x00000007 +#define CYFLD_UDB_W16_MSK_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_MSK_MS__SIZE 0x00000007 +#define CYREG_UDB_W16_MSK_01 0x400f1102 +#define CYREG_UDB_W16_MSK_02 0x400f1104 +#define CYREG_UDB_W16_ACTL_00 0x400f1120 +#define CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET 0x00000001 +#define CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET 0x00000002 +#define CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_LVL_LS_MID 0x00000001 +#define CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET 0x00000003 +#define CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_LVL_LS_MID 0x00000001 +#define CYFLD_UDB_W16_INT_EN_LS__OFFSET 0x00000004 +#define CYFLD_UDB_W16_INT_EN_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_INT_EN_LS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_INT_EN_LS_ENABLE 0x00000001 +#define CYFLD_UDB_W16_CNT_START_LS__OFFSET 0x00000005 +#define CYFLD_UDB_W16_CNT_START_LS__SIZE 0x00000001 +#define CYVAL_UDB_W16_CNT_START_LS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_CNT_START_LS_ENABLE 0x00000001 +#define CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET 0x00000009 +#define CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR 0x00000001 +#define CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET 0x0000000a +#define CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO0_LVL_MS_MID 0x00000001 +#define CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET 0x0000000b +#define CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL 0x00000000 +#define CYVAL_UDB_W16_FIFO1_LVL_MS_MID 0x00000001 +#define CYFLD_UDB_W16_INT_EN_MS__OFFSET 0x0000000c +#define CYFLD_UDB_W16_INT_EN_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_INT_EN_MS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_INT_EN_MS_ENABLE 0x00000001 +#define CYFLD_UDB_W16_CNT_START_MS__OFFSET 0x0000000d +#define CYFLD_UDB_W16_CNT_START_MS__SIZE 0x00000001 +#define CYVAL_UDB_W16_CNT_START_MS_DISABLE 0x00000000 +#define CYVAL_UDB_W16_CNT_START_MS_ENABLE 0x00000001 +#define CYREG_UDB_W16_ACTL_01 0x400f1122 +#define CYREG_UDB_W16_ACTL_02 0x400f1124 +#define CYREG_UDB_W16_MC_00 0x400f1140 +#define CYFLD_UDB_W16_PLD0_MC_LS__OFFSET 0x00000000 +#define CYFLD_UDB_W16_PLD0_MC_LS__SIZE 0x00000004 +#define CYFLD_UDB_W16_PLD1_MC_LS__OFFSET 0x00000004 +#define CYFLD_UDB_W16_PLD1_MC_LS__SIZE 0x00000004 +#define CYFLD_UDB_W16_PLD0_MC_MS__OFFSET 0x00000008 +#define CYFLD_UDB_W16_PLD0_MC_MS__SIZE 0x00000004 +#define CYFLD_UDB_W16_PLD1_MC_MS__OFFSET 0x0000000c +#define CYFLD_UDB_W16_PLD1_MC_MS__SIZE 0x00000004 +#define CYREG_UDB_W16_MC_01 0x400f1142 +#define CYREG_UDB_W16_MC_02 0x400f1144 +#define CYDEV_UDB_W32_BASE 0x400f2000 +#define CYDEV_UDB_W32_SIZE 0x00001000 +#define CYREG_UDB_W32_A0_00 0x400f2000 +#define CYFLD_UDB_W32_A0_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_A0_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_A0_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_A0_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_A0_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_A0_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_A0_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_A0_3__SIZE 0x00000008 +#define CYREG_UDB_W32_A1_00 0x400f2040 +#define CYFLD_UDB_W32_A1_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_A1_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_A1_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_A1_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_A1_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_A1_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_A1_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_A1_3__SIZE 0x00000008 +#define CYREG_UDB_W32_D0_00 0x400f2080 +#define CYFLD_UDB_W32_D0_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_D0_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_D0_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_D0_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_D0_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_D0_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_D0_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_D0_3__SIZE 0x00000008 +#define CYREG_UDB_W32_D1_00 0x400f20c0 +#define CYFLD_UDB_W32_D1_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_D1_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_D1_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_D1_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_D1_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_D1_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_D1_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_D1_3__SIZE 0x00000008 +#define CYREG_UDB_W32_F0_00 0x400f2100 +#define CYFLD_UDB_W32_F0_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_F0_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_F0_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_F0_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_F0_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_F0_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_F0_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_F0_3__SIZE 0x00000008 +#define CYREG_UDB_W32_F1_00 0x400f2140 +#define CYFLD_UDB_W32_F1_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_F1_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_F1_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_F1_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_F1_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_F1_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_F1_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_F1_3__SIZE 0x00000008 +#define CYREG_UDB_W32_ST_00 0x400f2180 +#define CYFLD_UDB_W32_ST_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_ST_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_ST_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_ST_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_ST_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_ST_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_ST_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_ST_3__SIZE 0x00000008 +#define CYREG_UDB_W32_CTL_00 0x400f21c0 +#define CYFLD_UDB_W32_CTL_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_CTL_0__SIZE 0x00000008 +#define CYFLD_UDB_W32_CTL_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_CTL_1__SIZE 0x00000008 +#define CYFLD_UDB_W32_CTL_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_CTL_2__SIZE 0x00000008 +#define CYFLD_UDB_W32_CTL_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_CTL_3__SIZE 0x00000008 +#define CYREG_UDB_W32_MSK_00 0x400f2200 +#define CYFLD_UDB_W32_MSK_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_MSK_0__SIZE 0x00000007 +#define CYFLD_UDB_W32_MSK_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_MSK_1__SIZE 0x00000007 +#define CYFLD_UDB_W32_MSK_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_MSK_2__SIZE 0x00000007 +#define CYFLD_UDB_W32_MSK_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_MSK_3__SIZE 0x00000007 +#define CYREG_UDB_W32_ACTL_00 0x400f2240 +#define CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_FIFO0_CLR_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET 0x00000002 +#define CYFLD_UDB_W32_FIFO0_LVL_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_0_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET 0x00000003 +#define CYFLD_UDB_W32_FIFO1_LVL_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_0_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_0__OFFSET 0x00000004 +#define CYFLD_UDB_W32_INT_EN_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_0_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_0_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_0__OFFSET 0x00000005 +#define CYFLD_UDB_W32_CNT_START_0__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_0_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_0_ENABLE 0x00000001 +#define CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_FIFO0_CLR_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET 0x00000009 +#define CYFLD_UDB_W32_FIFO1_CLR_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET 0x0000000a +#define CYFLD_UDB_W32_FIFO0_LVL_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_1_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET 0x0000000b +#define CYFLD_UDB_W32_FIFO1_LVL_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_1_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_1__OFFSET 0x0000000c +#define CYFLD_UDB_W32_INT_EN_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_1_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_1_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_1__OFFSET 0x0000000d +#define CYFLD_UDB_W32_CNT_START_1__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_1_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_1_ENABLE 0x00000001 +#define CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_FIFO0_CLR_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET 0x00000011 +#define CYFLD_UDB_W32_FIFO1_CLR_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET 0x00000012 +#define CYFLD_UDB_W32_FIFO0_LVL_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_2_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET 0x00000013 +#define CYFLD_UDB_W32_FIFO1_LVL_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_2_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_2__OFFSET 0x00000014 +#define CYFLD_UDB_W32_INT_EN_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_2_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_2_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_2__OFFSET 0x00000015 +#define CYFLD_UDB_W32_CNT_START_2__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_2_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_2_ENABLE 0x00000001 +#define CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_FIFO0_CLR_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET 0x00000019 +#define CYFLD_UDB_W32_FIFO1_CLR_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR 0x00000001 +#define CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET 0x0000001a +#define CYFLD_UDB_W32_FIFO0_LVL_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO0_LVL_3_MID 0x00000001 +#define CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET 0x0000001b +#define CYFLD_UDB_W32_FIFO1_LVL_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL 0x00000000 +#define CYVAL_UDB_W32_FIFO1_LVL_3_MID 0x00000001 +#define CYFLD_UDB_W32_INT_EN_3__OFFSET 0x0000001c +#define CYFLD_UDB_W32_INT_EN_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_INT_EN_3_DISABLE 0x00000000 +#define CYVAL_UDB_W32_INT_EN_3_ENABLE 0x00000001 +#define CYFLD_UDB_W32_CNT_START_3__OFFSET 0x0000001d +#define CYFLD_UDB_W32_CNT_START_3__SIZE 0x00000001 +#define CYVAL_UDB_W32_CNT_START_3_DISABLE 0x00000000 +#define CYVAL_UDB_W32_CNT_START_3_ENABLE 0x00000001 +#define CYREG_UDB_W32_MC_00 0x400f2280 +#define CYFLD_UDB_W32_PLD0_MC_0__OFFSET 0x00000000 +#define CYFLD_UDB_W32_PLD0_MC_0__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_0__OFFSET 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_0__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD0_MC_1__OFFSET 0x00000008 +#define CYFLD_UDB_W32_PLD0_MC_1__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_1__OFFSET 0x0000000c +#define CYFLD_UDB_W32_PLD1_MC_1__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD0_MC_2__OFFSET 0x00000010 +#define CYFLD_UDB_W32_PLD0_MC_2__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_2__OFFSET 0x00000014 +#define CYFLD_UDB_W32_PLD1_MC_2__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD0_MC_3__OFFSET 0x00000018 +#define CYFLD_UDB_W32_PLD0_MC_3__SIZE 0x00000004 +#define CYFLD_UDB_W32_PLD1_MC_3__OFFSET 0x0000001c +#define CYFLD_UDB_W32_PLD1_MC_3__SIZE 0x00000004 +#define CYDEV_UDB_P0_BASE 0x400f3000 +#define CYDEV_UDB_P0_SIZE 0x00000200 +#define CYDEV_UDB_P0_U0_BASE 0x400f3000 +#define CYDEV_UDB_P0_U0_SIZE 0x00000080 +#define CYREG_UDB_P0_U0_PLD_IT0 0x400f3000 +#define CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET 0x00000010 +#define CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET 0x00000011 +#define CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET 0x00000012 +#define CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET 0x00000013 +#define CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET 0x00000014 +#define CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET 0x00000015 +#define CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET 0x00000016 +#define CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET 0x00000017 +#define CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET 0x00000018 +#define CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET 0x00000019 +#define CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET 0x0000001a +#define CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET 0x0000001b +#define CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET 0x0000001c +#define CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET 0x0000001d +#define CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET 0x0000001e +#define CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET 0x0000001f +#define CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_PLD_IT1 0x400f3004 +#define CYREG_UDB_P0_U0_PLD_IT2 0x400f3008 +#define CYREG_UDB_P0_U0_PLD_IT3 0x400f300c +#define CYREG_UDB_P0_U0_PLD_IT4 0x400f3010 +#define CYREG_UDB_P0_U0_PLD_IT5 0x400f3014 +#define CYREG_UDB_P0_U0_PLD_IT6 0x400f3018 +#define CYREG_UDB_P0_U0_PLD_IT7 0x400f301c +#define CYREG_UDB_P0_U0_PLD_IT8 0x400f3020 +#define CYREG_UDB_P0_U0_PLD_IT9 0x400f3024 +#define CYREG_UDB_P0_U0_PLD_IT10 0x400f3028 +#define CYREG_UDB_P0_U0_PLD_IT11 0x400f302c +#define CYREG_UDB_P0_U0_PLD_ORT0 0x400f3030 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_PLD_ORT1 0x400f3032 +#define CYREG_UDB_P0_U0_PLD_ORT2 0x400f3034 +#define CYREG_UDB_P0_U0_PLD_ORT3 0x400f3036 +#define CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST 0x400f3038 +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED 0x00000001 +#define CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB 0x400f303a +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L 0x00000003 +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H 0x00000002 +#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L 0x00000003 +#define CYREG_UDB_P0_U0_PLD_MC_SET_RESET 0x400f303c +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS 0x400f303e +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_NC1__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC3__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_NC3__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC5__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_NC5__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC7__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_NC7__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC9__OFFSET 0x00000009 +#define CYFLD_UDB_P_U_NC9__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC11__OFFSET 0x0000000b +#define CYFLD_UDB_P_U_NC11__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC13__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_NC13__SIZE 0x00000001 +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET 0x0000000e +#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER 0x00000000 +#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC15__OFFSET 0x0000000f +#define CYFLD_UDB_P_U_NC15__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG0 0x400f3040 +#define CYFLD_UDB_P_U_RAD0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RAD0__SIZE 0x00000003 +#define CYVAL_UDB_P_U_RAD0_OFF 0x00000000 +#define CYVAL_UDB_P_U_RAD0_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_RAD0_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_RAD0_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_RAD0_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_RAD0_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_RAD0_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_RAD0_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_RAD1__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_RAD1__SIZE 0x00000003 +#define CYVAL_UDB_P_U_RAD1_OFF 0x00000000 +#define CYVAL_UDB_P_U_RAD1_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_RAD1_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_RAD1_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_RAD1_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_RAD1_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_RAD1_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_RAD1_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG1 0x400f3041 +#define CYFLD_UDB_P_U_RAD2__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RAD2__SIZE 0x00000003 +#define CYVAL_UDB_P_U_RAD2_OFF 0x00000000 +#define CYVAL_UDB_P_U_RAD2_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_RAD2_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_RAD2_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_RAD2_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_RAD2_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_RAD2_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_RAD2_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS 0x00000001 +#define CYREG_UDB_P0_U0_CFG2 0x400f3042 +#define CYFLD_UDB_P_U_F0_LD__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_F0_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_F0_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_F0_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_F0_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_F0_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_F0_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_F0_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_F0_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_F0_LD_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE 0x00000000 +#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS 0x00000001 +#define CYFLD_UDB_P_U_F1_LD__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_F1_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_F1_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_F1_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_F1_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_F1_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_F1_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_F1_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_F1_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_F1_LD_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG3 0x400f3043 +#define CYFLD_UDB_P_U_D0_LD__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_D0_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_D0_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_D0_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_D0_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_D0_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_D0_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_D0_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_D0_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_D0_LD_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_D1_LD__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_D1_LD__SIZE 0x00000003 +#define CYVAL_UDB_P_U_D1_LD_OFF 0x00000000 +#define CYVAL_UDB_P_U_D1_LD_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_D1_LD_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_D1_LD_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_D1_LD_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_D1_LD_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_D1_LD_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_D1_LD_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG4 0x400f3044 +#define CYFLD_UDB_P_U_SI_MUX__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_SI_MUX__SIZE 0x00000003 +#define CYVAL_UDB_P_U_SI_MUX_OFF 0x00000000 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_SI_MUX_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_SI_MUX_RESERVED 0x00000007 +#define CYFLD_UDB_P_U_CI_MUX__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_CI_MUX__SIZE 0x00000003 +#define CYVAL_UDB_P_U_CI_MUX_OFF 0x00000000 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN0 0x00000001 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN1 0x00000002 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN2 0x00000003 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN3 0x00000004 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN4 0x00000005 +#define CYVAL_UDB_P_U_CI_MUX_DP_IN5 0x00000006 +#define CYVAL_UDB_P_U_CI_MUX_RESERVED 0x00000007 +#define CYREG_UDB_P0_U0_CFG5 0x400f3045 +#define CYFLD_UDB_P_U_OUT0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT0__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT0_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT0_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT0_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT0_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT0_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT0_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT0_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT0_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT0_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT0_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT0_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT0_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT0_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT0_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT0_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT0_F1_BUS_STAT 0x0000000f +#define CYFLD_UDB_P_U_OUT1__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_OUT1__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT1_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT1_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT1_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT1_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT1_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT1_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT1_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT1_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT1_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT1_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT1_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT1_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT1_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT1_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT1_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT1_F1_BUS_STAT 0x0000000f +#define CYREG_UDB_P0_U0_CFG6 0x400f3046 +#define CYFLD_UDB_P_U_OUT2__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT2__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT2_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT2_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT2_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT2_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT2_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT2_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT2_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT2_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT2_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT2_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT2_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT2_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT2_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT2_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT2_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT2_F1_BUS_STAT 0x0000000f +#define CYFLD_UDB_P_U_OUT3__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_OUT3__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT3_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT3_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT3_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT3_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT3_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT3_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT3_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT3_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT3_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT3_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT3_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT3_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT3_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT3_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT3_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT3_F1_BUS_STAT 0x0000000f +#define CYREG_UDB_P0_U0_CFG7 0x400f3047 +#define CYFLD_UDB_P_U_OUT4__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT4__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT4_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT4_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT4_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT4_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT4_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT4_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT4_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT4_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT4_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT4_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT4_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT4_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT4_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT4_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT4_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT4_F1_BUS_STAT 0x0000000f +#define CYFLD_UDB_P_U_OUT5__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_OUT5__SIZE 0x00000004 +#define CYVAL_UDB_P_U_OUT5_CE0 0x00000000 +#define CYVAL_UDB_P_U_OUT5_CL0 0x00000001 +#define CYVAL_UDB_P_U_OUT5_Z0 0x00000002 +#define CYVAL_UDB_P_U_OUT5_FF0 0x00000003 +#define CYVAL_UDB_P_U_OUT5_CE1 0x00000004 +#define CYVAL_UDB_P_U_OUT5_CL1 0x00000005 +#define CYVAL_UDB_P_U_OUT5_Z1 0x00000006 +#define CYVAL_UDB_P_U_OUT5_FF1 0x00000007 +#define CYVAL_UDB_P_U_OUT5_OV_MSB 0x00000008 +#define CYVAL_UDB_P_U_OUT5_CO_MSB 0x00000009 +#define CYVAL_UDB_P_U_OUT5_CMSBO 0x0000000a +#define CYVAL_UDB_P_U_OUT5_SO 0x0000000b +#define CYVAL_UDB_P_U_OUT5_F0_BLK_STAT 0x0000000c +#define CYVAL_UDB_P_U_OUT5_F1_BLK_STAT 0x0000000d +#define CYVAL_UDB_P_U_OUT5_F0_BUS_STAT 0x0000000e +#define CYVAL_UDB_P_U_OUT5_F1_BUS_STAT 0x0000000f +#define CYREG_UDB_P0_U0_CFG8 0x400f3048 +#define CYFLD_UDB_P_U_OUT_SYNC__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_OUT_SYNC__SIZE 0x00000006 +#define CYVAL_UDB_P_U_OUT_SYNC_REGISTERED 0x00000000 +#define CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL 0x00000001 +#define CYFLD_UDB_P_U_NC6__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_NC6__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG9 0x400f3049 +#define CYFLD_UDB_P_U_AMASK__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_AMASK__SIZE 0x00000008 +#define CYREG_UDB_P0_U0_CFG10 0x400f304a +#define CYFLD_UDB_P_U_CMASK0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CMASK0__SIZE 0x00000008 +#define CYREG_UDB_P0_U0_CFG11 0x400f304b +#define CYREG_UDB_P0_U0_CFG12 0x400f304c +#define CYFLD_UDB_P_U_SI_SELA__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_SI_SELA__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELA_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_SI_SELA_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_SI_SELA_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELA_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_SI_SELB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_SI_SELB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELB_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_SI_SELB_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_SI_SELB_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_SI_SELB_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_DEF_SI__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_DEF_SI__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 0x00000000 +#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 0x00000001 +#define CYFLD_UDB_P_U_AMASK_EN__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_AMASK_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_AMASK_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_AMASK_EN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CMASK0_EN__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_CMASK0_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CMASK0_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CMASK0_EN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CMASK1_EN__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_CMASK1_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CMASK1_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CMASK1_EN_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_CFG13 0x400f304d +#define CYFLD_UDB_P_U_CI_SELA__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CI_SELA__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELA_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_CI_SELA_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_CI_SELA_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELA_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_CI_SELB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CI_SELB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELB_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_CI_SELB_REGISTERED 0x00000001 +#define CYVAL_UDB_P_U_CI_SELB_ROUTE 0x00000002 +#define CYVAL_UDB_P_U_CI_SELB_CHAIN 0x00000003 +#define CYFLD_UDB_P_U_CMP_SELA__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_CMP_SELA__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELA_A1_D1 0x00000000 +#define CYVAL_UDB_P_U_CMP_SELA_A1_A0 0x00000001 +#define CYVAL_UDB_P_U_CMP_SELA_A0_D1 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELA_A0_A0 0x00000003 +#define CYFLD_UDB_P_U_CMP_SELB__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_CMP_SELB__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELB_A1_D1 0x00000000 +#define CYVAL_UDB_P_U_CMP_SELB_A1_A0 0x00000001 +#define CYVAL_UDB_P_U_CMP_SELB_A0_D1 0x00000002 +#define CYVAL_UDB_P_U_CMP_SELB_A0_A0 0x00000003 +#define CYREG_UDB_P0_U0_CFG14 0x400f304e +#define CYFLD_UDB_P_U_CHAIN0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CHAIN0__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN0_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN0_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CHAIN1__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_CHAIN1__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN1_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN1_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CHAIN_FB__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CHAIN_FB__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN_FB_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN_FB_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_CHAIN_CMSB__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_MSB_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_MSB_SEL__SIZE 0x00000003 +#define CYVAL_UDB_P_U_MSB_SEL_BIT0 0x00000000 +#define CYVAL_UDB_P_U_MSB_SEL_BIT1 0x00000001 +#define CYVAL_UDB_P_U_MSB_SEL_BIT2 0x00000002 +#define CYVAL_UDB_P_U_MSB_SEL_BIT3 0x00000003 +#define CYVAL_UDB_P_U_MSB_SEL_BIT4 0x00000004 +#define CYVAL_UDB_P_U_MSB_SEL_BIT5 0x00000005 +#define CYVAL_UDB_P_U_MSB_SEL_BIT6 0x00000006 +#define CYVAL_UDB_P_U_MSB_SEL_BIT7 0x00000007 +#define CYFLD_UDB_P_U_MSB_EN__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_MSB_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_MSB_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_MSB_EN_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_CFG15 0x400f304f +#define CYFLD_UDB_P_U_F0_INSEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_F0_INSEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_F0_INSEL_INPUT 0x00000000 +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 0x00000001 +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 0x00000002 +#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU 0x00000003 +#define CYFLD_UDB_P_U_F1_INSEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_F1_INSEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_F1_INSEL_INPUT 0x00000000 +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 0x00000001 +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 0x00000002 +#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU 0x00000003 +#define CYFLD_UDB_P_U_MSB_SI__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_MSB_SI__SIZE 0x00000001 +#define CYVAL_UDB_P_U_MSB_SI_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_MSB_SI_MSB 0x00000001 +#define CYFLD_UDB_P_U_PI_DYN__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_PI_DYN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PI_DYN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_PI_DYN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_SHIFT_SEL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_SHIFT_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB 0x00000000 +#define CYVAL_UDB_P_U_SHIFT_SEL_SOR 0x00000001 +#define CYFLD_UDB_P_U_PI_SEL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PI_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PI_SEL_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_PI_SEL_PARALLEL 0x00000001 +#define CYREG_UDB_P0_U0_CFG16 0x400f3050 +#define CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_WRK16_CONCAT__SIZE 0x00000001 +#define CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT 0x00000000 +#define CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE 0x00000001 +#define CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_EXT_CRCPRS__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL 0x00000000 +#define CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL 0x00000001 +#define CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_FIFO_ASYNC__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_EDGE__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_FIFO_EDGE__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_EDGE_LEVEL 0x00000000 +#define CYVAL_UDB_P_U_FIFO_EDGE_EDGE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_CAP__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_FIFO_CAP__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_CAP_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_CAP_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_FAST__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_FIFO_FAST__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_FAST_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_FAST_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_F0_CK_INV__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_F0_CK_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F0_CK_INV_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_F0_CK_INV_INVERT 0x00000001 +#define CYFLD_UDB_P_U_F1_CK_INV__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_F1_CK_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F1_CK_INV_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_F1_CK_INV_INVERT 0x00000001 +#define CYREG_UDB_P0_U0_CFG17 0x400f3051 +#define CYFLD_UDB_P_U_F0_DYN__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_F0_DYN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F0_DYN_STATIC 0x00000000 +#define CYVAL_UDB_P_U_F0_DYN_DYNAMIC 0x00000001 +#define CYFLD_UDB_P_U_F1_DYN__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_F1_DYN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_F1_DYN_STATIC 0x00000000 +#define CYVAL_UDB_P_U_F1_DYN_DYNAMIC 0x00000001 +#define CYFLD_UDB_P_U_NC2__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_NC2__SIZE 0x00000001 +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE 0x00000001 +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE 0x00000001 +#define CYREG_UDB_P0_U0_CFG18 0x400f3052 +#define CYFLD_UDB_P_U_CTL_MD0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CTL_MD0__SIZE 0x00000008 +#define CYVAL_UDB_P_U_CTL_MD0_DIRECT 0x00000000 +#define CYVAL_UDB_P_U_CTL_MD0_SYNC 0x00000001 +#define CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC 0x00000002 +#define CYVAL_UDB_P_U_CTL_MD0_PULSE 0x00000003 +#define CYREG_UDB_P0_U0_CFG19 0x400f3053 +#define CYFLD_UDB_P_U_CTL_MD1__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CTL_MD1__SIZE 0x00000008 +#define CYVAL_UDB_P_U_CTL_MD1_DIRECT 0x00000000 +#define CYVAL_UDB_P_U_CTL_MD1_SYNC 0x00000001 +#define CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC 0x00000002 +#define CYVAL_UDB_P_U_CTL_MD1_PULSE 0x00000003 +#define CYREG_UDB_P0_U0_CFG20 0x400f3054 +#define CYFLD_UDB_P_U_STAT_MD__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_STAT_MD__SIZE 0x00000008 +#define CYREG_UDB_P0_U0_CFG21 0x400f3055 +#define CYFLD_UDB_P_U_NC0__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_NC0__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG22 0x400f3056 +#define CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_SC_OUT_CTL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL 0x00000000 +#define CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL 0x00000001 +#define CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER 0x00000002 +#define CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED 0x00000003 +#define CYFLD_UDB_P_U_SC_INT_MD__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_SC_INT_MD__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_INT_MD_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_SC_INT_MD_INT_MODE 0x00000001 +#define CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_SC_SYNC_MD__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL 0x00000000 +#define CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE 0x00000001 +#define CYFLD_UDB_P_U_SC_EXT_RES__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_SC_EXT_RES__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_EXT_RES_DISABLED 0x00000000 +#define CYVAL_UDB_P_U_SC_EXT_RES_ENABLED 0x00000001 +#define CYREG_UDB_P0_U0_CFG23 0x400f3057 +#define CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CNT_LD_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 0x00000000 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 0x00000001 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 0x00000002 +#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 0x00000003 +#define CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CNT_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 0x00000000 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 0x00000001 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 0x00000002 +#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO 0x00000003 +#define CYFLD_UDB_P_U_ROUTE_LD__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_ROUTE_LD__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ROUTE_LD_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_ROUTE_LD_ROUTED 0x00000001 +#define CYFLD_UDB_P_U_ROUTE_EN__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_ROUTE_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ROUTE_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_ROUTE_EN_ROUTED 0x00000001 +#define CYFLD_UDB_P_U_ALT_CNT__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_ALT_CNT__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE 0x00000000 +#define CYVAL_UDB_P_U_ALT_CNT_ALT_MODE 0x00000001 +#define CYREG_UDB_P0_U0_CFG24 0x400f3058 +#define CYFLD_UDB_P_U_RC_EN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RC_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 0x00000000 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 0x00000001 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 0x00000003 +#define CYFLD_UDB_P_U_RC_EN_MODE__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_RC_EN_MODE__SIZE 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_MODE_OFF 0x00000000 +#define CYVAL_UDB_P_U_RC_EN_MODE_ON 0x00000001 +#define CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE 0x00000002 +#define CYVAL_UDB_P_U_RC_EN_MODE_LEVEL 0x00000003 +#define CYFLD_UDB_P_U_RC_EN_INV__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_RC_EN_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_RC_EN_INV_NOINV 0x00000000 +#define CYVAL_UDB_P_U_RC_EN_INV_INVERT 0x00000001 +#define CYFLD_UDB_P_U_RC_INV__OFFSET 0x00000005 +#define CYFLD_UDB_P_U_RC_INV__SIZE 0x00000001 +#define CYVAL_UDB_P_U_RC_INV_NOINV 0x00000000 +#define CYVAL_UDB_P_U_RC_INV_INVERT 0x00000001 +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE 0x00000001 +#define CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_RC_RES_SEL1__SIZE 0x00000001 +#define CYREG_UDB_P0_U0_CFG25 0x400f3059 +#define CYREG_UDB_P0_U0_CFG26 0x400f305a +#define CYREG_UDB_P0_U0_CFG27 0x400f305b +#define CYREG_UDB_P0_U0_CFG28 0x400f305c +#define CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK 0x00000009 +#define CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK 0x00000009 +#define CYREG_UDB_P0_U0_CFG29 0x400f305d +#define CYFLD_UDB_P_U_DP_CK_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_DP_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK 0x00000009 +#define CYFLD_UDB_P_U_SC_CK_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_SC_CK_SEL__SIZE 0x00000004 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK 0x00000008 +#define CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK 0x00000009 +#define CYREG_UDB_P0_U0_CFG30 0x400f305e +#define CYFLD_UDB_P_U_RES_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_RES_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN0 0x00000000 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN1 0x00000001 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN2 0x00000002 +#define CYVAL_UDB_P_U_RES_SEL_RC_IN3 0x00000003 +#define CYFLD_UDB_P_U_RES_POL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_RES_POL_NEGATED 0x00000000 +#define CYVAL_UDB_P_U_RES_POL_ASSERTED 0x00000001 +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_GUDB_WR__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_GUDB_WR__SIZE 0x00000001 +#define CYVAL_UDB_P_U_GUDB_WR_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_GUDB_WR_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_DP_RES_POL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_DP_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_DP_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_DP_RES_POL_INVERT 0x00000001 +#define CYFLD_UDB_P_U_SC_RES_POL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_SC_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SC_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_SC_RES_POL_INVERT 0x00000001 +#define CYREG_UDB_P0_U0_CFG31 0x400f305f +#define CYFLD_UDB_P_U_ALT_RES__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_ALT_RES__SIZE 0x00000001 +#define CYVAL_UDB_P_U_ALT_RES_COMPATIBLE 0x00000000 +#define CYVAL_UDB_P_U_ALT_RES_ALTERNATE 0x00000001 +#define CYFLD_UDB_P_U_EXT_SYNC__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_EXT_SYNC__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EXT_SYNC_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_EXT_SYNC_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_EN_RES_STAT__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_EN_RES_STAT__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EN_RES_STAT_NEGATED 0x00000000 +#define CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED 0x00000001 +#define CYFLD_UDB_P_U_EN_RES_DP__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_EN_RES_DP__SIZE 0x00000001 +#define CYVAL_UDB_P_U_EN_RES_DP_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_EN_RES_DP_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_EXT_CK_SEL__SIZE 0x00000002 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 0x00000000 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 0x00000001 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 0x00000002 +#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 0x00000003 +#define CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_PLD0_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD0_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD0_RES_POL_INVERT 0x00000001 +#define CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET 0x00000007 +#define CYFLD_UDB_P_U_PLD1_RES_POL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_PLD1_RES_POL_NOINV 0x00000000 +#define CYVAL_UDB_P_U_PLD1_RES_POL_INVERT 0x00000001 +#define CYREG_UDB_P0_U0_DCFG0 0x400f3060 +#define CYFLD_UDB_P_U_CMP_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_P_U_CMP_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CMP_SEL_CFG_A 0x00000000 +#define CYVAL_UDB_P_U_CMP_SEL_CFG_B 0x00000001 +#define CYFLD_UDB_P_U_SI_SEL__OFFSET 0x00000001 +#define CYFLD_UDB_P_U_SI_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SI_SEL_CFG_A 0x00000000 +#define CYVAL_UDB_P_U_SI_SEL_CFG_B 0x00000001 +#define CYFLD_UDB_P_U_CI_SEL__OFFSET 0x00000002 +#define CYFLD_UDB_P_U_CI_SEL__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CI_SEL_CFG_A 0x00000000 +#define CYVAL_UDB_P_U_CI_SEL_CFG_B 0x00000001 +#define CYFLD_UDB_P_U_CFB_EN__OFFSET 0x00000003 +#define CYFLD_UDB_P_U_CFB_EN__SIZE 0x00000001 +#define CYVAL_UDB_P_U_CFB_EN_DISABLE 0x00000000 +#define CYVAL_UDB_P_U_CFB_EN_ENABLE 0x00000001 +#define CYFLD_UDB_P_U_A1_WR_SRC__OFFSET 0x00000004 +#define CYFLD_UDB_P_U_A1_WR_SRC__SIZE 0x00000002 +#define CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE 0x00000000 +#define CYVAL_UDB_P_U_A1_WR_SRC_ALU 0x00000001 +#define CYVAL_UDB_P_U_A1_WR_SRC_D1 0x00000002 +#define CYVAL_UDB_P_U_A1_WR_SRC_F1 0x00000003 +#define CYFLD_UDB_P_U_A0_WR_SRC__OFFSET 0x00000006 +#define CYFLD_UDB_P_U_A0_WR_SRC__SIZE 0x00000002 +#define CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE 0x00000000 +#define CYVAL_UDB_P_U_A0_WR_SRC_ALU 0x00000001 +#define CYVAL_UDB_P_U_A0_WR_SRC_D0 0x00000002 +#define CYVAL_UDB_P_U_A0_WR_SRC_F0 0x00000003 +#define CYFLD_UDB_P_U_SHIFT__OFFSET 0x00000008 +#define CYFLD_UDB_P_U_SHIFT__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SHIFT_NOSHIFT 0x00000000 +#define CYVAL_UDB_P_U_SHIFT_LEFT 0x00000001 +#define CYVAL_UDB_P_U_SHIFT_RIGHT 0x00000002 +#define CYVAL_UDB_P_U_SHIFT_SWAP 0x00000003 +#define CYFLD_UDB_P_U_SRC_B__OFFSET 0x0000000a +#define CYFLD_UDB_P_U_SRC_B__SIZE 0x00000002 +#define CYVAL_UDB_P_U_SRC_B_D0 0x00000000 +#define CYVAL_UDB_P_U_SRC_B_D1 0x00000001 +#define CYVAL_UDB_P_U_SRC_B_A0 0x00000002 +#define CYVAL_UDB_P_U_SRC_B_A1 0x00000003 +#define CYFLD_UDB_P_U_SRC_A__OFFSET 0x0000000c +#define CYFLD_UDB_P_U_SRC_A__SIZE 0x00000001 +#define CYVAL_UDB_P_U_SRC_A_A0 0x00000000 +#define CYVAL_UDB_P_U_SRC_A_A1 0x00000001 +#define CYFLD_UDB_P_U_FUNC__OFFSET 0x0000000d +#define CYFLD_UDB_P_U_FUNC__SIZE 0x00000003 +#define CYVAL_UDB_P_U_FUNC_PASS 0x00000000 +#define CYVAL_UDB_P_U_FUNC_INC_A 0x00000001 +#define CYVAL_UDB_P_U_FUNC_DEC_A 0x00000002 +#define CYVAL_UDB_P_U_FUNC_ADD 0x00000003 +#define CYVAL_UDB_P_U_FUNC_SUB 0x00000004 +#define CYVAL_UDB_P_U_FUNC_XOR 0x00000005 +#define CYVAL_UDB_P_U_FUNC_AND 0x00000006 +#define CYVAL_UDB_P_U_FUNC_OR 0x00000007 +#define CYREG_UDB_P0_U0_DCFG1 0x400f3062 +#define CYREG_UDB_P0_U0_DCFG2 0x400f3064 +#define CYREG_UDB_P0_U0_DCFG3 0x400f3066 +#define CYREG_UDB_P0_U0_DCFG4 0x400f3068 +#define CYREG_UDB_P0_U0_DCFG5 0x400f306a +#define CYREG_UDB_P0_U0_DCFG6 0x400f306c +#define CYREG_UDB_P0_U0_DCFG7 0x400f306e +#define CYDEV_UDB_P0_U1_BASE 0x400f3080 +#define CYDEV_UDB_P0_U1_SIZE 0x00000080 +#define CYREG_UDB_P0_U1_PLD_IT0 0x400f3080 +#define CYREG_UDB_P0_U1_PLD_IT1 0x400f3084 +#define CYREG_UDB_P0_U1_PLD_IT2 0x400f3088 +#define CYREG_UDB_P0_U1_PLD_IT3 0x400f308c +#define CYREG_UDB_P0_U1_PLD_IT4 0x400f3090 +#define CYREG_UDB_P0_U1_PLD_IT5 0x400f3094 +#define CYREG_UDB_P0_U1_PLD_IT6 0x400f3098 +#define CYREG_UDB_P0_U1_PLD_IT7 0x400f309c +#define CYREG_UDB_P0_U1_PLD_IT8 0x400f30a0 +#define CYREG_UDB_P0_U1_PLD_IT9 0x400f30a4 +#define CYREG_UDB_P0_U1_PLD_IT10 0x400f30a8 +#define CYREG_UDB_P0_U1_PLD_IT11 0x400f30ac +#define CYREG_UDB_P0_U1_PLD_ORT0 0x400f30b0 +#define CYREG_UDB_P0_U1_PLD_ORT1 0x400f30b2 +#define CYREG_UDB_P0_U1_PLD_ORT2 0x400f30b4 +#define CYREG_UDB_P0_U1_PLD_ORT3 0x400f30b6 +#define CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST 0x400f30b8 +#define CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB 0x400f30ba +#define CYREG_UDB_P0_U1_PLD_MC_SET_RESET 0x400f30bc +#define CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS 0x400f30be +#define CYREG_UDB_P0_U1_CFG0 0x400f30c0 +#define CYREG_UDB_P0_U1_CFG1 0x400f30c1 +#define CYREG_UDB_P0_U1_CFG2 0x400f30c2 +#define CYREG_UDB_P0_U1_CFG3 0x400f30c3 +#define CYREG_UDB_P0_U1_CFG4 0x400f30c4 +#define CYREG_UDB_P0_U1_CFG5 0x400f30c5 +#define CYREG_UDB_P0_U1_CFG6 0x400f30c6 +#define CYREG_UDB_P0_U1_CFG7 0x400f30c7 +#define CYREG_UDB_P0_U1_CFG8 0x400f30c8 +#define CYREG_UDB_P0_U1_CFG9 0x400f30c9 +#define CYREG_UDB_P0_U1_CFG10 0x400f30ca +#define CYREG_UDB_P0_U1_CFG11 0x400f30cb +#define CYREG_UDB_P0_U1_CFG12 0x400f30cc +#define CYREG_UDB_P0_U1_CFG13 0x400f30cd +#define CYREG_UDB_P0_U1_CFG14 0x400f30ce +#define CYREG_UDB_P0_U1_CFG15 0x400f30cf +#define CYREG_UDB_P0_U1_CFG16 0x400f30d0 +#define CYREG_UDB_P0_U1_CFG17 0x400f30d1 +#define CYREG_UDB_P0_U1_CFG18 0x400f30d2 +#define CYREG_UDB_P0_U1_CFG19 0x400f30d3 +#define CYREG_UDB_P0_U1_CFG20 0x400f30d4 +#define CYREG_UDB_P0_U1_CFG21 0x400f30d5 +#define CYREG_UDB_P0_U1_CFG22 0x400f30d6 +#define CYREG_UDB_P0_U1_CFG23 0x400f30d7 +#define CYREG_UDB_P0_U1_CFG24 0x400f30d8 +#define CYREG_UDB_P0_U1_CFG25 0x400f30d9 +#define CYREG_UDB_P0_U1_CFG26 0x400f30da +#define CYREG_UDB_P0_U1_CFG27 0x400f30db +#define CYREG_UDB_P0_U1_CFG28 0x400f30dc +#define CYREG_UDB_P0_U1_CFG29 0x400f30dd +#define CYREG_UDB_P0_U1_CFG30 0x400f30de +#define CYREG_UDB_P0_U1_CFG31 0x400f30df +#define CYREG_UDB_P0_U1_DCFG0 0x400f30e0 +#define CYREG_UDB_P0_U1_DCFG1 0x400f30e2 +#define CYREG_UDB_P0_U1_DCFG2 0x400f30e4 +#define CYREG_UDB_P0_U1_DCFG3 0x400f30e6 +#define CYREG_UDB_P0_U1_DCFG4 0x400f30e8 +#define CYREG_UDB_P0_U1_DCFG5 0x400f30ea +#define CYREG_UDB_P0_U1_DCFG6 0x400f30ec +#define CYREG_UDB_P0_U1_DCFG7 0x400f30ee +#define CYDEV_UDB_P0_ROUTE_BASE 0x400f3100 +#define CYDEV_UDB_P0_ROUTE_SIZE 0x00000100 +#define CYREG_UDB_P0_ROUTE_HC0 0x400f3100 +#define CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE 0x00000008 +#define CYREG_UDB_P0_ROUTE_HC1 0x400f3101 +#define CYREG_UDB_P0_ROUTE_HC2 0x400f3102 +#define CYREG_UDB_P0_ROUTE_HC3 0x400f3103 +#define CYREG_UDB_P0_ROUTE_HC4 0x400f3104 +#define CYREG_UDB_P0_ROUTE_HC5 0x400f3105 +#define CYREG_UDB_P0_ROUTE_HC6 0x400f3106 +#define CYREG_UDB_P0_ROUTE_HC7 0x400f3107 +#define CYREG_UDB_P0_ROUTE_HC8 0x400f3108 +#define CYREG_UDB_P0_ROUTE_HC9 0x400f3109 +#define CYREG_UDB_P0_ROUTE_HC10 0x400f310a +#define CYREG_UDB_P0_ROUTE_HC11 0x400f310b +#define CYREG_UDB_P0_ROUTE_HC12 0x400f310c +#define CYREG_UDB_P0_ROUTE_HC13 0x400f310d +#define CYREG_UDB_P0_ROUTE_HC14 0x400f310e +#define CYREG_UDB_P0_ROUTE_HC15 0x400f310f +#define CYREG_UDB_P0_ROUTE_HC16 0x400f3110 +#define CYREG_UDB_P0_ROUTE_HC17 0x400f3111 +#define CYREG_UDB_P0_ROUTE_HC18 0x400f3112 +#define CYREG_UDB_P0_ROUTE_HC19 0x400f3113 +#define CYREG_UDB_P0_ROUTE_HC20 0x400f3114 +#define CYREG_UDB_P0_ROUTE_HC21 0x400f3115 +#define CYREG_UDB_P0_ROUTE_HC22 0x400f3116 +#define CYREG_UDB_P0_ROUTE_HC23 0x400f3117 +#define CYREG_UDB_P0_ROUTE_HC24 0x400f3118 +#define CYREG_UDB_P0_ROUTE_HC25 0x400f3119 +#define CYREG_UDB_P0_ROUTE_HC26 0x400f311a +#define CYREG_UDB_P0_ROUTE_HC27 0x400f311b +#define CYREG_UDB_P0_ROUTE_HC28 0x400f311c +#define CYREG_UDB_P0_ROUTE_HC29 0x400f311d +#define CYREG_UDB_P0_ROUTE_HC30 0x400f311e +#define CYREG_UDB_P0_ROUTE_HC31 0x400f311f +#define CYREG_UDB_P0_ROUTE_HC32 0x400f3120 +#define CYREG_UDB_P0_ROUTE_HC33 0x400f3121 +#define CYREG_UDB_P0_ROUTE_HC34 0x400f3122 +#define CYREG_UDB_P0_ROUTE_HC35 0x400f3123 +#define CYREG_UDB_P0_ROUTE_HC36 0x400f3124 +#define CYREG_UDB_P0_ROUTE_HC37 0x400f3125 +#define CYREG_UDB_P0_ROUTE_HC38 0x400f3126 +#define CYREG_UDB_P0_ROUTE_HC39 0x400f3127 +#define CYREG_UDB_P0_ROUTE_HC40 0x400f3128 +#define CYREG_UDB_P0_ROUTE_HC41 0x400f3129 +#define CYREG_UDB_P0_ROUTE_HC42 0x400f312a +#define CYREG_UDB_P0_ROUTE_HC43 0x400f312b +#define CYREG_UDB_P0_ROUTE_HC44 0x400f312c +#define CYREG_UDB_P0_ROUTE_HC45 0x400f312d +#define CYREG_UDB_P0_ROUTE_HC46 0x400f312e +#define CYREG_UDB_P0_ROUTE_HC47 0x400f312f +#define CYREG_UDB_P0_ROUTE_HC48 0x400f3130 +#define CYREG_UDB_P0_ROUTE_HC49 0x400f3131 +#define CYREG_UDB_P0_ROUTE_HC50 0x400f3132 +#define CYREG_UDB_P0_ROUTE_HC51 0x400f3133 +#define CYREG_UDB_P0_ROUTE_HC52 0x400f3134 +#define CYREG_UDB_P0_ROUTE_HC53 0x400f3135 +#define CYREG_UDB_P0_ROUTE_HC54 0x400f3136 +#define CYREG_UDB_P0_ROUTE_HC55 0x400f3137 +#define CYREG_UDB_P0_ROUTE_HC56 0x400f3138 +#define CYREG_UDB_P0_ROUTE_HC57 0x400f3139 +#define CYREG_UDB_P0_ROUTE_HC58 0x400f313a +#define CYREG_UDB_P0_ROUTE_HC59 0x400f313b +#define CYREG_UDB_P0_ROUTE_HC60 0x400f313c +#define CYREG_UDB_P0_ROUTE_HC61 0x400f313d +#define CYREG_UDB_P0_ROUTE_HC62 0x400f313e +#define CYREG_UDB_P0_ROUTE_HC63 0x400f313f +#define CYREG_UDB_P0_ROUTE_HC64 0x400f3140 +#define CYREG_UDB_P0_ROUTE_HC65 0x400f3141 +#define CYREG_UDB_P0_ROUTE_HC66 0x400f3142 +#define CYREG_UDB_P0_ROUTE_HC67 0x400f3143 +#define CYREG_UDB_P0_ROUTE_HC68 0x400f3144 +#define CYREG_UDB_P0_ROUTE_HC69 0x400f3145 +#define CYREG_UDB_P0_ROUTE_HC70 0x400f3146 +#define CYREG_UDB_P0_ROUTE_HC71 0x400f3147 +#define CYREG_UDB_P0_ROUTE_HC72 0x400f3148 +#define CYREG_UDB_P0_ROUTE_HC73 0x400f3149 +#define CYREG_UDB_P0_ROUTE_HC74 0x400f314a +#define CYREG_UDB_P0_ROUTE_HC75 0x400f314b +#define CYREG_UDB_P0_ROUTE_HC76 0x400f314c +#define CYREG_UDB_P0_ROUTE_HC77 0x400f314d +#define CYREG_UDB_P0_ROUTE_HC78 0x400f314e +#define CYREG_UDB_P0_ROUTE_HC79 0x400f314f +#define CYREG_UDB_P0_ROUTE_HC80 0x400f3150 +#define CYREG_UDB_P0_ROUTE_HC81 0x400f3151 +#define CYREG_UDB_P0_ROUTE_HC82 0x400f3152 +#define CYREG_UDB_P0_ROUTE_HC83 0x400f3153 +#define CYREG_UDB_P0_ROUTE_HC84 0x400f3154 +#define CYREG_UDB_P0_ROUTE_HC85 0x400f3155 +#define CYREG_UDB_P0_ROUTE_HC86 0x400f3156 +#define CYREG_UDB_P0_ROUTE_HC87 0x400f3157 +#define CYREG_UDB_P0_ROUTE_HC88 0x400f3158 +#define CYREG_UDB_P0_ROUTE_HC89 0x400f3159 +#define CYREG_UDB_P0_ROUTE_HC90 0x400f315a +#define CYREG_UDB_P0_ROUTE_HC91 0x400f315b +#define CYREG_UDB_P0_ROUTE_HC92 0x400f315c +#define CYREG_UDB_P0_ROUTE_HC93 0x400f315d +#define CYREG_UDB_P0_ROUTE_HC94 0x400f315e +#define CYREG_UDB_P0_ROUTE_HC95 0x400f315f +#define CYREG_UDB_P0_ROUTE_HC96 0x400f3160 +#define CYREG_UDB_P0_ROUTE_HC97 0x400f3161 +#define CYREG_UDB_P0_ROUTE_HC98 0x400f3162 +#define CYREG_UDB_P0_ROUTE_HC99 0x400f3163 +#define CYREG_UDB_P0_ROUTE_HC100 0x400f3164 +#define CYREG_UDB_P0_ROUTE_HC101 0x400f3165 +#define CYREG_UDB_P0_ROUTE_HC102 0x400f3166 +#define CYREG_UDB_P0_ROUTE_HC103 0x400f3167 +#define CYREG_UDB_P0_ROUTE_HC104 0x400f3168 +#define CYREG_UDB_P0_ROUTE_HC105 0x400f3169 +#define CYREG_UDB_P0_ROUTE_HC106 0x400f316a +#define CYREG_UDB_P0_ROUTE_HC107 0x400f316b +#define CYREG_UDB_P0_ROUTE_HC108 0x400f316c +#define CYREG_UDB_P0_ROUTE_HC109 0x400f316d +#define CYREG_UDB_P0_ROUTE_HC110 0x400f316e +#define CYREG_UDB_P0_ROUTE_HC111 0x400f316f +#define CYREG_UDB_P0_ROUTE_HC112 0x400f3170 +#define CYREG_UDB_P0_ROUTE_HC113 0x400f3171 +#define CYREG_UDB_P0_ROUTE_HC114 0x400f3172 +#define CYREG_UDB_P0_ROUTE_HC115 0x400f3173 +#define CYREG_UDB_P0_ROUTE_HC116 0x400f3174 +#define CYREG_UDB_P0_ROUTE_HC117 0x400f3175 +#define CYREG_UDB_P0_ROUTE_HC118 0x400f3176 +#define CYREG_UDB_P0_ROUTE_HC119 0x400f3177 +#define CYREG_UDB_P0_ROUTE_HC120 0x400f3178 +#define CYREG_UDB_P0_ROUTE_HC121 0x400f3179 +#define CYREG_UDB_P0_ROUTE_HC122 0x400f317a +#define CYREG_UDB_P0_ROUTE_HC123 0x400f317b +#define CYREG_UDB_P0_ROUTE_HC124 0x400f317c +#define CYREG_UDB_P0_ROUTE_HC125 0x400f317d +#define CYREG_UDB_P0_ROUTE_HC126 0x400f317e +#define CYREG_UDB_P0_ROUTE_HC127 0x400f317f +#define CYREG_UDB_P0_ROUTE_HV_L0 0x400f3180 +#define CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE 0x00000008 +#define CYREG_UDB_P0_ROUTE_HV_L1 0x400f3181 +#define CYREG_UDB_P0_ROUTE_HV_L2 0x400f3182 +#define CYREG_UDB_P0_ROUTE_HV_L3 0x400f3183 +#define CYREG_UDB_P0_ROUTE_HV_L4 0x400f3184 +#define CYREG_UDB_P0_ROUTE_HV_L5 0x400f3185 +#define CYREG_UDB_P0_ROUTE_HV_L6 0x400f3186 +#define CYREG_UDB_P0_ROUTE_HV_L7 0x400f3187 +#define CYREG_UDB_P0_ROUTE_HV_L8 0x400f3188 +#define CYREG_UDB_P0_ROUTE_HV_L9 0x400f3189 +#define CYREG_UDB_P0_ROUTE_HV_L10 0x400f318a +#define CYREG_UDB_P0_ROUTE_HV_L11 0x400f318b +#define CYREG_UDB_P0_ROUTE_HV_L12 0x400f318c +#define CYREG_UDB_P0_ROUTE_HV_L13 0x400f318d +#define CYREG_UDB_P0_ROUTE_HV_L14 0x400f318e +#define CYREG_UDB_P0_ROUTE_HV_L15 0x400f318f +#define CYREG_UDB_P0_ROUTE_HS0 0x400f3190 +#define CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE 0x00000008 +#define CYREG_UDB_P0_ROUTE_HS1 0x400f3191 +#define CYREG_UDB_P0_ROUTE_HS2 0x400f3192 +#define CYREG_UDB_P0_ROUTE_HS3 0x400f3193 +#define CYREG_UDB_P0_ROUTE_HS4 0x400f3194 +#define CYREG_UDB_P0_ROUTE_HS5 0x400f3195 +#define CYREG_UDB_P0_ROUTE_HS6 0x400f3196 +#define CYREG_UDB_P0_ROUTE_HS7 0x400f3197 +#define CYREG_UDB_P0_ROUTE_HS8 0x400f3198 +#define CYREG_UDB_P0_ROUTE_HS9 0x400f3199 +#define CYREG_UDB_P0_ROUTE_HS10 0x400f319a +#define CYREG_UDB_P0_ROUTE_HS11 0x400f319b +#define CYREG_UDB_P0_ROUTE_HS12 0x400f319c +#define CYREG_UDB_P0_ROUTE_HS13 0x400f319d +#define CYREG_UDB_P0_ROUTE_HS14 0x400f319e +#define CYREG_UDB_P0_ROUTE_HS15 0x400f319f +#define CYREG_UDB_P0_ROUTE_HS16 0x400f31a0 +#define CYREG_UDB_P0_ROUTE_HS17 0x400f31a1 +#define CYREG_UDB_P0_ROUTE_HS18 0x400f31a2 +#define CYREG_UDB_P0_ROUTE_HS19 0x400f31a3 +#define CYREG_UDB_P0_ROUTE_HS20 0x400f31a4 +#define CYREG_UDB_P0_ROUTE_HS21 0x400f31a5 +#define CYREG_UDB_P0_ROUTE_HS22 0x400f31a6 +#define CYREG_UDB_P0_ROUTE_HS23 0x400f31a7 +#define CYREG_UDB_P0_ROUTE_HV_R0 0x400f31a8 +#define CYREG_UDB_P0_ROUTE_HV_R1 0x400f31a9 +#define CYREG_UDB_P0_ROUTE_HV_R2 0x400f31aa +#define CYREG_UDB_P0_ROUTE_HV_R3 0x400f31ab +#define CYREG_UDB_P0_ROUTE_HV_R4 0x400f31ac +#define CYREG_UDB_P0_ROUTE_HV_R5 0x400f31ad +#define CYREG_UDB_P0_ROUTE_HV_R6 0x400f31ae +#define CYREG_UDB_P0_ROUTE_HV_R7 0x400f31af +#define CYREG_UDB_P0_ROUTE_HV_R8 0x400f31b0 +#define CYREG_UDB_P0_ROUTE_HV_R9 0x400f31b1 +#define CYREG_UDB_P0_ROUTE_HV_R10 0x400f31b2 +#define CYREG_UDB_P0_ROUTE_HV_R11 0x400f31b3 +#define CYREG_UDB_P0_ROUTE_HV_R12 0x400f31b4 +#define CYREG_UDB_P0_ROUTE_HV_R13 0x400f31b5 +#define CYREG_UDB_P0_ROUTE_HV_R14 0x400f31b6 +#define CYREG_UDB_P0_ROUTE_HV_R15 0x400f31b7 +#define CYREG_UDB_P0_ROUTE_PLD0IN0 0x400f31c0 +#define CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_PI_TOP__SIZE 0x00000004 +#define CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_P_ROUTE_PI_BOT__SIZE 0x00000004 +#define CYREG_UDB_P0_ROUTE_PLD0IN1 0x400f31c2 +#define CYREG_UDB_P0_ROUTE_PLD0IN2 0x400f31c4 +#define CYREG_UDB_P0_ROUTE_PLD1IN0 0x400f31ca +#define CYREG_UDB_P0_ROUTE_PLD1IN1 0x400f31cc +#define CYREG_UDB_P0_ROUTE_PLD1IN2 0x400f31ce +#define CYREG_UDB_P0_ROUTE_DPIN0 0x400f31d0 +#define CYREG_UDB_P0_ROUTE_DPIN1 0x400f31d2 +#define CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET 0x00000002 +#define CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE 0x00000002 +#define CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET 0x00000004 +#define CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE 0x00000002 +#define CYREG_UDB_P0_ROUTE_SCIN 0x400f31d6 +#define CYREG_UDB_P0_ROUTE_SCIOIN 0x400f31d8 +#define CYREG_UDB_P0_ROUTE_RCIN 0x400f31de +#define CYREG_UDB_P0_ROUTE_VS0 0x400f31e0 +#define CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_P_ROUTE_VS_TOP__SIZE 0x00000004 +#define CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_P_ROUTE_VS_BOT__SIZE 0x00000004 +#define CYREG_UDB_P0_ROUTE_VS1 0x400f31e2 +#define CYREG_UDB_P0_ROUTE_VS2 0x400f31e4 +#define CYREG_UDB_P0_ROUTE_VS3 0x400f31e6 +#define CYREG_UDB_P0_ROUTE_VS4 0x400f31e8 +#define CYREG_UDB_P0_ROUTE_VS5 0x400f31ea +#define CYREG_UDB_P0_ROUTE_VS6 0x400f31ec +#define CYREG_UDB_P0_ROUTE_VS7 0x400f31ee +#define CYDEV_UDB_P1_BASE 0x400f3200 +#define CYDEV_UDB_P1_SIZE 0x00000200 +#define CYDEV_UDB_P1_U0_BASE 0x400f3200 +#define CYDEV_UDB_P1_U0_SIZE 0x00000080 +#define CYREG_UDB_P1_U0_PLD_IT0 0x400f3200 +#define CYREG_UDB_P1_U0_PLD_IT1 0x400f3204 +#define CYREG_UDB_P1_U0_PLD_IT2 0x400f3208 +#define CYREG_UDB_P1_U0_PLD_IT3 0x400f320c +#define CYREG_UDB_P1_U0_PLD_IT4 0x400f3210 +#define CYREG_UDB_P1_U0_PLD_IT5 0x400f3214 +#define CYREG_UDB_P1_U0_PLD_IT6 0x400f3218 +#define CYREG_UDB_P1_U0_PLD_IT7 0x400f321c +#define CYREG_UDB_P1_U0_PLD_IT8 0x400f3220 +#define CYREG_UDB_P1_U0_PLD_IT9 0x400f3224 +#define CYREG_UDB_P1_U0_PLD_IT10 0x400f3228 +#define CYREG_UDB_P1_U0_PLD_IT11 0x400f322c +#define CYREG_UDB_P1_U0_PLD_ORT0 0x400f3230 +#define CYREG_UDB_P1_U0_PLD_ORT1 0x400f3232 +#define CYREG_UDB_P1_U0_PLD_ORT2 0x400f3234 +#define CYREG_UDB_P1_U0_PLD_ORT3 0x400f3236 +#define CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST 0x400f3238 +#define CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB 0x400f323a +#define CYREG_UDB_P1_U0_PLD_MC_SET_RESET 0x400f323c +#define CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS 0x400f323e +#define CYREG_UDB_P1_U0_CFG0 0x400f3240 +#define CYREG_UDB_P1_U0_CFG1 0x400f3241 +#define CYREG_UDB_P1_U0_CFG2 0x400f3242 +#define CYREG_UDB_P1_U0_CFG3 0x400f3243 +#define CYREG_UDB_P1_U0_CFG4 0x400f3244 +#define CYREG_UDB_P1_U0_CFG5 0x400f3245 +#define CYREG_UDB_P1_U0_CFG6 0x400f3246 +#define CYREG_UDB_P1_U0_CFG7 0x400f3247 +#define CYREG_UDB_P1_U0_CFG8 0x400f3248 +#define CYREG_UDB_P1_U0_CFG9 0x400f3249 +#define CYREG_UDB_P1_U0_CFG10 0x400f324a +#define CYREG_UDB_P1_U0_CFG11 0x400f324b +#define CYREG_UDB_P1_U0_CFG12 0x400f324c +#define CYREG_UDB_P1_U0_CFG13 0x400f324d +#define CYREG_UDB_P1_U0_CFG14 0x400f324e +#define CYREG_UDB_P1_U0_CFG15 0x400f324f +#define CYREG_UDB_P1_U0_CFG16 0x400f3250 +#define CYREG_UDB_P1_U0_CFG17 0x400f3251 +#define CYREG_UDB_P1_U0_CFG18 0x400f3252 +#define CYREG_UDB_P1_U0_CFG19 0x400f3253 +#define CYREG_UDB_P1_U0_CFG20 0x400f3254 +#define CYREG_UDB_P1_U0_CFG21 0x400f3255 +#define CYREG_UDB_P1_U0_CFG22 0x400f3256 +#define CYREG_UDB_P1_U0_CFG23 0x400f3257 +#define CYREG_UDB_P1_U0_CFG24 0x400f3258 +#define CYREG_UDB_P1_U0_CFG25 0x400f3259 +#define CYREG_UDB_P1_U0_CFG26 0x400f325a +#define CYREG_UDB_P1_U0_CFG27 0x400f325b +#define CYREG_UDB_P1_U0_CFG28 0x400f325c +#define CYREG_UDB_P1_U0_CFG29 0x400f325d +#define CYREG_UDB_P1_U0_CFG30 0x400f325e +#define CYREG_UDB_P1_U0_CFG31 0x400f325f +#define CYREG_UDB_P1_U0_DCFG0 0x400f3260 +#define CYREG_UDB_P1_U0_DCFG1 0x400f3262 +#define CYREG_UDB_P1_U0_DCFG2 0x400f3264 +#define CYREG_UDB_P1_U0_DCFG3 0x400f3266 +#define CYREG_UDB_P1_U0_DCFG4 0x400f3268 +#define CYREG_UDB_P1_U0_DCFG5 0x400f326a +#define CYREG_UDB_P1_U0_DCFG6 0x400f326c +#define CYREG_UDB_P1_U0_DCFG7 0x400f326e +#define CYDEV_UDB_P1_U1_BASE 0x400f3280 +#define CYDEV_UDB_P1_U1_SIZE 0x00000080 +#define CYREG_UDB_P1_U1_PLD_IT0 0x400f3280 +#define CYREG_UDB_P1_U1_PLD_IT1 0x400f3284 +#define CYREG_UDB_P1_U1_PLD_IT2 0x400f3288 +#define CYREG_UDB_P1_U1_PLD_IT3 0x400f328c +#define CYREG_UDB_P1_U1_PLD_IT4 0x400f3290 +#define CYREG_UDB_P1_U1_PLD_IT5 0x400f3294 +#define CYREG_UDB_P1_U1_PLD_IT6 0x400f3298 +#define CYREG_UDB_P1_U1_PLD_IT7 0x400f329c +#define CYREG_UDB_P1_U1_PLD_IT8 0x400f32a0 +#define CYREG_UDB_P1_U1_PLD_IT9 0x400f32a4 +#define CYREG_UDB_P1_U1_PLD_IT10 0x400f32a8 +#define CYREG_UDB_P1_U1_PLD_IT11 0x400f32ac +#define CYREG_UDB_P1_U1_PLD_ORT0 0x400f32b0 +#define CYREG_UDB_P1_U1_PLD_ORT1 0x400f32b2 +#define CYREG_UDB_P1_U1_PLD_ORT2 0x400f32b4 +#define CYREG_UDB_P1_U1_PLD_ORT3 0x400f32b6 +#define CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST 0x400f32b8 +#define CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB 0x400f32ba +#define CYREG_UDB_P1_U1_PLD_MC_SET_RESET 0x400f32bc +#define CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS 0x400f32be +#define CYREG_UDB_P1_U1_CFG0 0x400f32c0 +#define CYREG_UDB_P1_U1_CFG1 0x400f32c1 +#define CYREG_UDB_P1_U1_CFG2 0x400f32c2 +#define CYREG_UDB_P1_U1_CFG3 0x400f32c3 +#define CYREG_UDB_P1_U1_CFG4 0x400f32c4 +#define CYREG_UDB_P1_U1_CFG5 0x400f32c5 +#define CYREG_UDB_P1_U1_CFG6 0x400f32c6 +#define CYREG_UDB_P1_U1_CFG7 0x400f32c7 +#define CYREG_UDB_P1_U1_CFG8 0x400f32c8 +#define CYREG_UDB_P1_U1_CFG9 0x400f32c9 +#define CYREG_UDB_P1_U1_CFG10 0x400f32ca +#define CYREG_UDB_P1_U1_CFG11 0x400f32cb +#define CYREG_UDB_P1_U1_CFG12 0x400f32cc +#define CYREG_UDB_P1_U1_CFG13 0x400f32cd +#define CYREG_UDB_P1_U1_CFG14 0x400f32ce +#define CYREG_UDB_P1_U1_CFG15 0x400f32cf +#define CYREG_UDB_P1_U1_CFG16 0x400f32d0 +#define CYREG_UDB_P1_U1_CFG17 0x400f32d1 +#define CYREG_UDB_P1_U1_CFG18 0x400f32d2 +#define CYREG_UDB_P1_U1_CFG19 0x400f32d3 +#define CYREG_UDB_P1_U1_CFG20 0x400f32d4 +#define CYREG_UDB_P1_U1_CFG21 0x400f32d5 +#define CYREG_UDB_P1_U1_CFG22 0x400f32d6 +#define CYREG_UDB_P1_U1_CFG23 0x400f32d7 +#define CYREG_UDB_P1_U1_CFG24 0x400f32d8 +#define CYREG_UDB_P1_U1_CFG25 0x400f32d9 +#define CYREG_UDB_P1_U1_CFG26 0x400f32da +#define CYREG_UDB_P1_U1_CFG27 0x400f32db +#define CYREG_UDB_P1_U1_CFG28 0x400f32dc +#define CYREG_UDB_P1_U1_CFG29 0x400f32dd +#define CYREG_UDB_P1_U1_CFG30 0x400f32de +#define CYREG_UDB_P1_U1_CFG31 0x400f32df +#define CYREG_UDB_P1_U1_DCFG0 0x400f32e0 +#define CYREG_UDB_P1_U1_DCFG1 0x400f32e2 +#define CYREG_UDB_P1_U1_DCFG2 0x400f32e4 +#define CYREG_UDB_P1_U1_DCFG3 0x400f32e6 +#define CYREG_UDB_P1_U1_DCFG4 0x400f32e8 +#define CYREG_UDB_P1_U1_DCFG5 0x400f32ea +#define CYREG_UDB_P1_U1_DCFG6 0x400f32ec +#define CYREG_UDB_P1_U1_DCFG7 0x400f32ee +#define CYDEV_UDB_P1_ROUTE_BASE 0x400f3300 +#define CYDEV_UDB_P1_ROUTE_SIZE 0x00000100 +#define CYREG_UDB_P1_ROUTE_HC0 0x400f3300 +#define CYREG_UDB_P1_ROUTE_HC1 0x400f3301 +#define CYREG_UDB_P1_ROUTE_HC2 0x400f3302 +#define CYREG_UDB_P1_ROUTE_HC3 0x400f3303 +#define CYREG_UDB_P1_ROUTE_HC4 0x400f3304 +#define CYREG_UDB_P1_ROUTE_HC5 0x400f3305 +#define CYREG_UDB_P1_ROUTE_HC6 0x400f3306 +#define CYREG_UDB_P1_ROUTE_HC7 0x400f3307 +#define CYREG_UDB_P1_ROUTE_HC8 0x400f3308 +#define CYREG_UDB_P1_ROUTE_HC9 0x400f3309 +#define CYREG_UDB_P1_ROUTE_HC10 0x400f330a +#define CYREG_UDB_P1_ROUTE_HC11 0x400f330b +#define CYREG_UDB_P1_ROUTE_HC12 0x400f330c +#define CYREG_UDB_P1_ROUTE_HC13 0x400f330d +#define CYREG_UDB_P1_ROUTE_HC14 0x400f330e +#define CYREG_UDB_P1_ROUTE_HC15 0x400f330f +#define CYREG_UDB_P1_ROUTE_HC16 0x400f3310 +#define CYREG_UDB_P1_ROUTE_HC17 0x400f3311 +#define CYREG_UDB_P1_ROUTE_HC18 0x400f3312 +#define CYREG_UDB_P1_ROUTE_HC19 0x400f3313 +#define CYREG_UDB_P1_ROUTE_HC20 0x400f3314 +#define CYREG_UDB_P1_ROUTE_HC21 0x400f3315 +#define CYREG_UDB_P1_ROUTE_HC22 0x400f3316 +#define CYREG_UDB_P1_ROUTE_HC23 0x400f3317 +#define CYREG_UDB_P1_ROUTE_HC24 0x400f3318 +#define CYREG_UDB_P1_ROUTE_HC25 0x400f3319 +#define CYREG_UDB_P1_ROUTE_HC26 0x400f331a +#define CYREG_UDB_P1_ROUTE_HC27 0x400f331b +#define CYREG_UDB_P1_ROUTE_HC28 0x400f331c +#define CYREG_UDB_P1_ROUTE_HC29 0x400f331d +#define CYREG_UDB_P1_ROUTE_HC30 0x400f331e +#define CYREG_UDB_P1_ROUTE_HC31 0x400f331f +#define CYREG_UDB_P1_ROUTE_HC32 0x400f3320 +#define CYREG_UDB_P1_ROUTE_HC33 0x400f3321 +#define CYREG_UDB_P1_ROUTE_HC34 0x400f3322 +#define CYREG_UDB_P1_ROUTE_HC35 0x400f3323 +#define CYREG_UDB_P1_ROUTE_HC36 0x400f3324 +#define CYREG_UDB_P1_ROUTE_HC37 0x400f3325 +#define CYREG_UDB_P1_ROUTE_HC38 0x400f3326 +#define CYREG_UDB_P1_ROUTE_HC39 0x400f3327 +#define CYREG_UDB_P1_ROUTE_HC40 0x400f3328 +#define CYREG_UDB_P1_ROUTE_HC41 0x400f3329 +#define CYREG_UDB_P1_ROUTE_HC42 0x400f332a +#define CYREG_UDB_P1_ROUTE_HC43 0x400f332b +#define CYREG_UDB_P1_ROUTE_HC44 0x400f332c +#define CYREG_UDB_P1_ROUTE_HC45 0x400f332d +#define CYREG_UDB_P1_ROUTE_HC46 0x400f332e +#define CYREG_UDB_P1_ROUTE_HC47 0x400f332f +#define CYREG_UDB_P1_ROUTE_HC48 0x400f3330 +#define CYREG_UDB_P1_ROUTE_HC49 0x400f3331 +#define CYREG_UDB_P1_ROUTE_HC50 0x400f3332 +#define CYREG_UDB_P1_ROUTE_HC51 0x400f3333 +#define CYREG_UDB_P1_ROUTE_HC52 0x400f3334 +#define CYREG_UDB_P1_ROUTE_HC53 0x400f3335 +#define CYREG_UDB_P1_ROUTE_HC54 0x400f3336 +#define CYREG_UDB_P1_ROUTE_HC55 0x400f3337 +#define CYREG_UDB_P1_ROUTE_HC56 0x400f3338 +#define CYREG_UDB_P1_ROUTE_HC57 0x400f3339 +#define CYREG_UDB_P1_ROUTE_HC58 0x400f333a +#define CYREG_UDB_P1_ROUTE_HC59 0x400f333b +#define CYREG_UDB_P1_ROUTE_HC60 0x400f333c +#define CYREG_UDB_P1_ROUTE_HC61 0x400f333d +#define CYREG_UDB_P1_ROUTE_HC62 0x400f333e +#define CYREG_UDB_P1_ROUTE_HC63 0x400f333f +#define CYREG_UDB_P1_ROUTE_HC64 0x400f3340 +#define CYREG_UDB_P1_ROUTE_HC65 0x400f3341 +#define CYREG_UDB_P1_ROUTE_HC66 0x400f3342 +#define CYREG_UDB_P1_ROUTE_HC67 0x400f3343 +#define CYREG_UDB_P1_ROUTE_HC68 0x400f3344 +#define CYREG_UDB_P1_ROUTE_HC69 0x400f3345 +#define CYREG_UDB_P1_ROUTE_HC70 0x400f3346 +#define CYREG_UDB_P1_ROUTE_HC71 0x400f3347 +#define CYREG_UDB_P1_ROUTE_HC72 0x400f3348 +#define CYREG_UDB_P1_ROUTE_HC73 0x400f3349 +#define CYREG_UDB_P1_ROUTE_HC74 0x400f334a +#define CYREG_UDB_P1_ROUTE_HC75 0x400f334b +#define CYREG_UDB_P1_ROUTE_HC76 0x400f334c +#define CYREG_UDB_P1_ROUTE_HC77 0x400f334d +#define CYREG_UDB_P1_ROUTE_HC78 0x400f334e +#define CYREG_UDB_P1_ROUTE_HC79 0x400f334f +#define CYREG_UDB_P1_ROUTE_HC80 0x400f3350 +#define CYREG_UDB_P1_ROUTE_HC81 0x400f3351 +#define CYREG_UDB_P1_ROUTE_HC82 0x400f3352 +#define CYREG_UDB_P1_ROUTE_HC83 0x400f3353 +#define CYREG_UDB_P1_ROUTE_HC84 0x400f3354 +#define CYREG_UDB_P1_ROUTE_HC85 0x400f3355 +#define CYREG_UDB_P1_ROUTE_HC86 0x400f3356 +#define CYREG_UDB_P1_ROUTE_HC87 0x400f3357 +#define CYREG_UDB_P1_ROUTE_HC88 0x400f3358 +#define CYREG_UDB_P1_ROUTE_HC89 0x400f3359 +#define CYREG_UDB_P1_ROUTE_HC90 0x400f335a +#define CYREG_UDB_P1_ROUTE_HC91 0x400f335b +#define CYREG_UDB_P1_ROUTE_HC92 0x400f335c +#define CYREG_UDB_P1_ROUTE_HC93 0x400f335d +#define CYREG_UDB_P1_ROUTE_HC94 0x400f335e +#define CYREG_UDB_P1_ROUTE_HC95 0x400f335f +#define CYREG_UDB_P1_ROUTE_HC96 0x400f3360 +#define CYREG_UDB_P1_ROUTE_HC97 0x400f3361 +#define CYREG_UDB_P1_ROUTE_HC98 0x400f3362 +#define CYREG_UDB_P1_ROUTE_HC99 0x400f3363 +#define CYREG_UDB_P1_ROUTE_HC100 0x400f3364 +#define CYREG_UDB_P1_ROUTE_HC101 0x400f3365 +#define CYREG_UDB_P1_ROUTE_HC102 0x400f3366 +#define CYREG_UDB_P1_ROUTE_HC103 0x400f3367 +#define CYREG_UDB_P1_ROUTE_HC104 0x400f3368 +#define CYREG_UDB_P1_ROUTE_HC105 0x400f3369 +#define CYREG_UDB_P1_ROUTE_HC106 0x400f336a +#define CYREG_UDB_P1_ROUTE_HC107 0x400f336b +#define CYREG_UDB_P1_ROUTE_HC108 0x400f336c +#define CYREG_UDB_P1_ROUTE_HC109 0x400f336d +#define CYREG_UDB_P1_ROUTE_HC110 0x400f336e +#define CYREG_UDB_P1_ROUTE_HC111 0x400f336f +#define CYREG_UDB_P1_ROUTE_HC112 0x400f3370 +#define CYREG_UDB_P1_ROUTE_HC113 0x400f3371 +#define CYREG_UDB_P1_ROUTE_HC114 0x400f3372 +#define CYREG_UDB_P1_ROUTE_HC115 0x400f3373 +#define CYREG_UDB_P1_ROUTE_HC116 0x400f3374 +#define CYREG_UDB_P1_ROUTE_HC117 0x400f3375 +#define CYREG_UDB_P1_ROUTE_HC118 0x400f3376 +#define CYREG_UDB_P1_ROUTE_HC119 0x400f3377 +#define CYREG_UDB_P1_ROUTE_HC120 0x400f3378 +#define CYREG_UDB_P1_ROUTE_HC121 0x400f3379 +#define CYREG_UDB_P1_ROUTE_HC122 0x400f337a +#define CYREG_UDB_P1_ROUTE_HC123 0x400f337b +#define CYREG_UDB_P1_ROUTE_HC124 0x400f337c +#define CYREG_UDB_P1_ROUTE_HC125 0x400f337d +#define CYREG_UDB_P1_ROUTE_HC126 0x400f337e +#define CYREG_UDB_P1_ROUTE_HC127 0x400f337f +#define CYREG_UDB_P1_ROUTE_HV_L0 0x400f3380 +#define CYREG_UDB_P1_ROUTE_HV_L1 0x400f3381 +#define CYREG_UDB_P1_ROUTE_HV_L2 0x400f3382 +#define CYREG_UDB_P1_ROUTE_HV_L3 0x400f3383 +#define CYREG_UDB_P1_ROUTE_HV_L4 0x400f3384 +#define CYREG_UDB_P1_ROUTE_HV_L5 0x400f3385 +#define CYREG_UDB_P1_ROUTE_HV_L6 0x400f3386 +#define CYREG_UDB_P1_ROUTE_HV_L7 0x400f3387 +#define CYREG_UDB_P1_ROUTE_HV_L8 0x400f3388 +#define CYREG_UDB_P1_ROUTE_HV_L9 0x400f3389 +#define CYREG_UDB_P1_ROUTE_HV_L10 0x400f338a +#define CYREG_UDB_P1_ROUTE_HV_L11 0x400f338b +#define CYREG_UDB_P1_ROUTE_HV_L12 0x400f338c +#define CYREG_UDB_P1_ROUTE_HV_L13 0x400f338d +#define CYREG_UDB_P1_ROUTE_HV_L14 0x400f338e +#define CYREG_UDB_P1_ROUTE_HV_L15 0x400f338f +#define CYREG_UDB_P1_ROUTE_HS0 0x400f3390 +#define CYREG_UDB_P1_ROUTE_HS1 0x400f3391 +#define CYREG_UDB_P1_ROUTE_HS2 0x400f3392 +#define CYREG_UDB_P1_ROUTE_HS3 0x400f3393 +#define CYREG_UDB_P1_ROUTE_HS4 0x400f3394 +#define CYREG_UDB_P1_ROUTE_HS5 0x400f3395 +#define CYREG_UDB_P1_ROUTE_HS6 0x400f3396 +#define CYREG_UDB_P1_ROUTE_HS7 0x400f3397 +#define CYREG_UDB_P1_ROUTE_HS8 0x400f3398 +#define CYREG_UDB_P1_ROUTE_HS9 0x400f3399 +#define CYREG_UDB_P1_ROUTE_HS10 0x400f339a +#define CYREG_UDB_P1_ROUTE_HS11 0x400f339b +#define CYREG_UDB_P1_ROUTE_HS12 0x400f339c +#define CYREG_UDB_P1_ROUTE_HS13 0x400f339d +#define CYREG_UDB_P1_ROUTE_HS14 0x400f339e +#define CYREG_UDB_P1_ROUTE_HS15 0x400f339f +#define CYREG_UDB_P1_ROUTE_HS16 0x400f33a0 +#define CYREG_UDB_P1_ROUTE_HS17 0x400f33a1 +#define CYREG_UDB_P1_ROUTE_HS18 0x400f33a2 +#define CYREG_UDB_P1_ROUTE_HS19 0x400f33a3 +#define CYREG_UDB_P1_ROUTE_HS20 0x400f33a4 +#define CYREG_UDB_P1_ROUTE_HS21 0x400f33a5 +#define CYREG_UDB_P1_ROUTE_HS22 0x400f33a6 +#define CYREG_UDB_P1_ROUTE_HS23 0x400f33a7 +#define CYREG_UDB_P1_ROUTE_HV_R0 0x400f33a8 +#define CYREG_UDB_P1_ROUTE_HV_R1 0x400f33a9 +#define CYREG_UDB_P1_ROUTE_HV_R2 0x400f33aa +#define CYREG_UDB_P1_ROUTE_HV_R3 0x400f33ab +#define CYREG_UDB_P1_ROUTE_HV_R4 0x400f33ac +#define CYREG_UDB_P1_ROUTE_HV_R5 0x400f33ad +#define CYREG_UDB_P1_ROUTE_HV_R6 0x400f33ae +#define CYREG_UDB_P1_ROUTE_HV_R7 0x400f33af +#define CYREG_UDB_P1_ROUTE_HV_R8 0x400f33b0 +#define CYREG_UDB_P1_ROUTE_HV_R9 0x400f33b1 +#define CYREG_UDB_P1_ROUTE_HV_R10 0x400f33b2 +#define CYREG_UDB_P1_ROUTE_HV_R11 0x400f33b3 +#define CYREG_UDB_P1_ROUTE_HV_R12 0x400f33b4 +#define CYREG_UDB_P1_ROUTE_HV_R13 0x400f33b5 +#define CYREG_UDB_P1_ROUTE_HV_R14 0x400f33b6 +#define CYREG_UDB_P1_ROUTE_HV_R15 0x400f33b7 +#define CYREG_UDB_P1_ROUTE_PLD0IN0 0x400f33c0 +#define CYREG_UDB_P1_ROUTE_PLD0IN1 0x400f33c2 +#define CYREG_UDB_P1_ROUTE_PLD0IN2 0x400f33c4 +#define CYREG_UDB_P1_ROUTE_PLD1IN0 0x400f33ca +#define CYREG_UDB_P1_ROUTE_PLD1IN1 0x400f33cc +#define CYREG_UDB_P1_ROUTE_PLD1IN2 0x400f33ce +#define CYREG_UDB_P1_ROUTE_DPIN0 0x400f33d0 +#define CYREG_UDB_P1_ROUTE_DPIN1 0x400f33d2 +#define CYREG_UDB_P1_ROUTE_SCIN 0x400f33d6 +#define CYREG_UDB_P1_ROUTE_SCIOIN 0x400f33d8 +#define CYREG_UDB_P1_ROUTE_RCIN 0x400f33de +#define CYREG_UDB_P1_ROUTE_VS0 0x400f33e0 +#define CYREG_UDB_P1_ROUTE_VS1 0x400f33e2 +#define CYREG_UDB_P1_ROUTE_VS2 0x400f33e4 +#define CYREG_UDB_P1_ROUTE_VS3 0x400f33e6 +#define CYREG_UDB_P1_ROUTE_VS4 0x400f33e8 +#define CYREG_UDB_P1_ROUTE_VS5 0x400f33ea +#define CYREG_UDB_P1_ROUTE_VS6 0x400f33ec +#define CYREG_UDB_P1_ROUTE_VS7 0x400f33ee +#define CYDEV_UDB_DSI0_BASE 0x400f4000 +#define CYDEV_UDB_DSI0_SIZE 0x00000100 +#define CYREG_UDB_DSI0_HC0 0x400f4000 +#define CYFLD_UDB_DSI_HC_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_HC_BYTE__SIZE 0x00000008 +#define CYREG_UDB_DSI0_HC1 0x400f4001 +#define CYREG_UDB_DSI0_HC2 0x400f4002 +#define CYREG_UDB_DSI0_HC3 0x400f4003 +#define CYREG_UDB_DSI0_HC4 0x400f4004 +#define CYREG_UDB_DSI0_HC5 0x400f4005 +#define CYREG_UDB_DSI0_HC6 0x400f4006 +#define CYREG_UDB_DSI0_HC7 0x400f4007 +#define CYREG_UDB_DSI0_HC8 0x400f4008 +#define CYREG_UDB_DSI0_HC9 0x400f4009 +#define CYREG_UDB_DSI0_HC10 0x400f400a +#define CYREG_UDB_DSI0_HC11 0x400f400b +#define CYREG_UDB_DSI0_HC12 0x400f400c +#define CYREG_UDB_DSI0_HC13 0x400f400d +#define CYREG_UDB_DSI0_HC14 0x400f400e +#define CYREG_UDB_DSI0_HC15 0x400f400f +#define CYREG_UDB_DSI0_HC16 0x400f4010 +#define CYREG_UDB_DSI0_HC17 0x400f4011 +#define CYREG_UDB_DSI0_HC18 0x400f4012 +#define CYREG_UDB_DSI0_HC19 0x400f4013 +#define CYREG_UDB_DSI0_HC20 0x400f4014 +#define CYREG_UDB_DSI0_HC21 0x400f4015 +#define CYREG_UDB_DSI0_HC22 0x400f4016 +#define CYREG_UDB_DSI0_HC23 0x400f4017 +#define CYREG_UDB_DSI0_HC24 0x400f4018 +#define CYREG_UDB_DSI0_HC25 0x400f4019 +#define CYREG_UDB_DSI0_HC26 0x400f401a +#define CYREG_UDB_DSI0_HC27 0x400f401b +#define CYREG_UDB_DSI0_HC28 0x400f401c +#define CYREG_UDB_DSI0_HC29 0x400f401d +#define CYREG_UDB_DSI0_HC30 0x400f401e +#define CYREG_UDB_DSI0_HC31 0x400f401f +#define CYREG_UDB_DSI0_HC32 0x400f4020 +#define CYREG_UDB_DSI0_HC33 0x400f4021 +#define CYREG_UDB_DSI0_HC34 0x400f4022 +#define CYREG_UDB_DSI0_HC35 0x400f4023 +#define CYREG_UDB_DSI0_HC36 0x400f4024 +#define CYREG_UDB_DSI0_HC37 0x400f4025 +#define CYREG_UDB_DSI0_HC38 0x400f4026 +#define CYREG_UDB_DSI0_HC39 0x400f4027 +#define CYREG_UDB_DSI0_HC40 0x400f4028 +#define CYREG_UDB_DSI0_HC41 0x400f4029 +#define CYREG_UDB_DSI0_HC42 0x400f402a +#define CYREG_UDB_DSI0_HC43 0x400f402b +#define CYREG_UDB_DSI0_HC44 0x400f402c +#define CYREG_UDB_DSI0_HC45 0x400f402d +#define CYREG_UDB_DSI0_HC46 0x400f402e +#define CYREG_UDB_DSI0_HC47 0x400f402f +#define CYREG_UDB_DSI0_HC48 0x400f4030 +#define CYREG_UDB_DSI0_HC49 0x400f4031 +#define CYREG_UDB_DSI0_HC50 0x400f4032 +#define CYREG_UDB_DSI0_HC51 0x400f4033 +#define CYREG_UDB_DSI0_HC52 0x400f4034 +#define CYREG_UDB_DSI0_HC53 0x400f4035 +#define CYREG_UDB_DSI0_HC54 0x400f4036 +#define CYREG_UDB_DSI0_HC55 0x400f4037 +#define CYREG_UDB_DSI0_HC56 0x400f4038 +#define CYREG_UDB_DSI0_HC57 0x400f4039 +#define CYREG_UDB_DSI0_HC58 0x400f403a +#define CYREG_UDB_DSI0_HC59 0x400f403b +#define CYREG_UDB_DSI0_HC60 0x400f403c +#define CYREG_UDB_DSI0_HC61 0x400f403d +#define CYREG_UDB_DSI0_HC62 0x400f403e +#define CYREG_UDB_DSI0_HC63 0x400f403f +#define CYREG_UDB_DSI0_HC64 0x400f4040 +#define CYREG_UDB_DSI0_HC65 0x400f4041 +#define CYREG_UDB_DSI0_HC66 0x400f4042 +#define CYREG_UDB_DSI0_HC67 0x400f4043 +#define CYREG_UDB_DSI0_HC68 0x400f4044 +#define CYREG_UDB_DSI0_HC69 0x400f4045 +#define CYREG_UDB_DSI0_HC70 0x400f4046 +#define CYREG_UDB_DSI0_HC71 0x400f4047 +#define CYREG_UDB_DSI0_HC72 0x400f4048 +#define CYREG_UDB_DSI0_HC73 0x400f4049 +#define CYREG_UDB_DSI0_HC74 0x400f404a +#define CYREG_UDB_DSI0_HC75 0x400f404b +#define CYREG_UDB_DSI0_HC76 0x400f404c +#define CYREG_UDB_DSI0_HC77 0x400f404d +#define CYREG_UDB_DSI0_HC78 0x400f404e +#define CYREG_UDB_DSI0_HC79 0x400f404f +#define CYREG_UDB_DSI0_HC80 0x400f4050 +#define CYREG_UDB_DSI0_HC81 0x400f4051 +#define CYREG_UDB_DSI0_HC82 0x400f4052 +#define CYREG_UDB_DSI0_HC83 0x400f4053 +#define CYREG_UDB_DSI0_HC84 0x400f4054 +#define CYREG_UDB_DSI0_HC85 0x400f4055 +#define CYREG_UDB_DSI0_HC86 0x400f4056 +#define CYREG_UDB_DSI0_HC87 0x400f4057 +#define CYREG_UDB_DSI0_HC88 0x400f4058 +#define CYREG_UDB_DSI0_HC89 0x400f4059 +#define CYREG_UDB_DSI0_HC90 0x400f405a +#define CYREG_UDB_DSI0_HC91 0x400f405b +#define CYREG_UDB_DSI0_HC92 0x400f405c +#define CYREG_UDB_DSI0_HC93 0x400f405d +#define CYREG_UDB_DSI0_HC94 0x400f405e +#define CYREG_UDB_DSI0_HC95 0x400f405f +#define CYREG_UDB_DSI0_HC96 0x400f4060 +#define CYREG_UDB_DSI0_HC97 0x400f4061 +#define CYREG_UDB_DSI0_HC98 0x400f4062 +#define CYREG_UDB_DSI0_HC99 0x400f4063 +#define CYREG_UDB_DSI0_HC100 0x400f4064 +#define CYREG_UDB_DSI0_HC101 0x400f4065 +#define CYREG_UDB_DSI0_HC102 0x400f4066 +#define CYREG_UDB_DSI0_HC103 0x400f4067 +#define CYREG_UDB_DSI0_HC104 0x400f4068 +#define CYREG_UDB_DSI0_HC105 0x400f4069 +#define CYREG_UDB_DSI0_HC106 0x400f406a +#define CYREG_UDB_DSI0_HC107 0x400f406b +#define CYREG_UDB_DSI0_HC108 0x400f406c +#define CYREG_UDB_DSI0_HC109 0x400f406d +#define CYREG_UDB_DSI0_HC110 0x400f406e +#define CYREG_UDB_DSI0_HC111 0x400f406f +#define CYREG_UDB_DSI0_HC112 0x400f4070 +#define CYREG_UDB_DSI0_HC113 0x400f4071 +#define CYREG_UDB_DSI0_HC114 0x400f4072 +#define CYREG_UDB_DSI0_HC115 0x400f4073 +#define CYREG_UDB_DSI0_HC116 0x400f4074 +#define CYREG_UDB_DSI0_HC117 0x400f4075 +#define CYREG_UDB_DSI0_HC118 0x400f4076 +#define CYREG_UDB_DSI0_HC119 0x400f4077 +#define CYREG_UDB_DSI0_HC120 0x400f4078 +#define CYREG_UDB_DSI0_HC121 0x400f4079 +#define CYREG_UDB_DSI0_HC122 0x400f407a +#define CYREG_UDB_DSI0_HC123 0x400f407b +#define CYREG_UDB_DSI0_HC124 0x400f407c +#define CYREG_UDB_DSI0_HC125 0x400f407d +#define CYREG_UDB_DSI0_HC126 0x400f407e +#define CYREG_UDB_DSI0_HC127 0x400f407f +#define CYREG_UDB_DSI0_HV_L0 0x400f4080 +#define CYFLD_UDB_DSI_HV_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_HV_BYTE__SIZE 0x00000008 +#define CYREG_UDB_DSI0_HV_L1 0x400f4081 +#define CYREG_UDB_DSI0_HV_L2 0x400f4082 +#define CYREG_UDB_DSI0_HV_L3 0x400f4083 +#define CYREG_UDB_DSI0_HV_L4 0x400f4084 +#define CYREG_UDB_DSI0_HV_L5 0x400f4085 +#define CYREG_UDB_DSI0_HV_L6 0x400f4086 +#define CYREG_UDB_DSI0_HV_L7 0x400f4087 +#define CYREG_UDB_DSI0_HV_L8 0x400f4088 +#define CYREG_UDB_DSI0_HV_L9 0x400f4089 +#define CYREG_UDB_DSI0_HV_L10 0x400f408a +#define CYREG_UDB_DSI0_HV_L11 0x400f408b +#define CYREG_UDB_DSI0_HV_L12 0x400f408c +#define CYREG_UDB_DSI0_HV_L13 0x400f408d +#define CYREG_UDB_DSI0_HV_L14 0x400f408e +#define CYREG_UDB_DSI0_HV_L15 0x400f408f +#define CYREG_UDB_DSI0_HS0 0x400f4090 +#define CYFLD_UDB_DSI_HS_BYTE__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_HS_BYTE__SIZE 0x00000008 +#define CYREG_UDB_DSI0_HS1 0x400f4091 +#define CYREG_UDB_DSI0_HS2 0x400f4092 +#define CYREG_UDB_DSI0_HS3 0x400f4093 +#define CYREG_UDB_DSI0_HS4 0x400f4094 +#define CYREG_UDB_DSI0_HS5 0x400f4095 +#define CYREG_UDB_DSI0_HS6 0x400f4096 +#define CYREG_UDB_DSI0_HS7 0x400f4097 +#define CYREG_UDB_DSI0_HS8 0x400f4098 +#define CYREG_UDB_DSI0_HS9 0x400f4099 +#define CYREG_UDB_DSI0_HS10 0x400f409a +#define CYREG_UDB_DSI0_HS11 0x400f409b +#define CYREG_UDB_DSI0_HS12 0x400f409c +#define CYREG_UDB_DSI0_HS13 0x400f409d +#define CYREG_UDB_DSI0_HS14 0x400f409e +#define CYREG_UDB_DSI0_HS15 0x400f409f +#define CYREG_UDB_DSI0_HS16 0x400f40a0 +#define CYREG_UDB_DSI0_HS17 0x400f40a1 +#define CYREG_UDB_DSI0_HS18 0x400f40a2 +#define CYREG_UDB_DSI0_HS19 0x400f40a3 +#define CYREG_UDB_DSI0_HS20 0x400f40a4 +#define CYREG_UDB_DSI0_HS21 0x400f40a5 +#define CYREG_UDB_DSI0_HS22 0x400f40a6 +#define CYREG_UDB_DSI0_HS23 0x400f40a7 +#define CYREG_UDB_DSI0_HV_R0 0x400f40a8 +#define CYREG_UDB_DSI0_HV_R1 0x400f40a9 +#define CYREG_UDB_DSI0_HV_R2 0x400f40aa +#define CYREG_UDB_DSI0_HV_R3 0x400f40ab +#define CYREG_UDB_DSI0_HV_R4 0x400f40ac +#define CYREG_UDB_DSI0_HV_R5 0x400f40ad +#define CYREG_UDB_DSI0_HV_R6 0x400f40ae +#define CYREG_UDB_DSI0_HV_R7 0x400f40af +#define CYREG_UDB_DSI0_HV_R8 0x400f40b0 +#define CYREG_UDB_DSI0_HV_R9 0x400f40b1 +#define CYREG_UDB_DSI0_HV_R10 0x400f40b2 +#define CYREG_UDB_DSI0_HV_R11 0x400f40b3 +#define CYREG_UDB_DSI0_HV_R12 0x400f40b4 +#define CYREG_UDB_DSI0_HV_R13 0x400f40b5 +#define CYREG_UDB_DSI0_HV_R14 0x400f40b6 +#define CYREG_UDB_DSI0_HV_R15 0x400f40b7 +#define CYREG_UDB_DSI0_DSIINP0 0x400f40c0 +#define CYFLD_UDB_DSI_PI_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_PI_TOP__SIZE 0x00000004 +#define CYFLD_UDB_DSI_PI_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_DSI_PI_BOT__SIZE 0x00000004 +#define CYREG_UDB_DSI0_DSIINP1 0x400f40c2 +#define CYREG_UDB_DSI0_DSIINP2 0x400f40c4 +#define CYREG_UDB_DSI0_DSIINP3 0x400f40c6 +#define CYREG_UDB_DSI0_DSIINP4 0x400f40c8 +#define CYREG_UDB_DSI0_DSIINP5 0x400f40ca +#define CYREG_UDB_DSI0_DSIOUTP0 0x400f40cc +#define CYREG_UDB_DSI0_DSIOUTP1 0x400f40ce +#define CYREG_UDB_DSI0_DSIOUTP2 0x400f40d0 +#define CYREG_UDB_DSI0_DSIOUTP3 0x400f40d2 +#define CYREG_UDB_DSI0_DSIOUTT0 0x400f40d4 +#define CYREG_UDB_DSI0_DSIOUTT1 0x400f40d6 +#define CYREG_UDB_DSI0_DSIOUTT2 0x400f40d8 +#define CYREG_UDB_DSI0_DSIOUTT3 0x400f40da +#define CYREG_UDB_DSI0_DSIOUTT4 0x400f40dc +#define CYREG_UDB_DSI0_DSIOUTT5 0x400f40de +#define CYREG_UDB_DSI0_VS0 0x400f40e0 +#define CYFLD_UDB_DSI_VS_TOP__OFFSET 0x00000000 +#define CYFLD_UDB_DSI_VS_TOP__SIZE 0x00000004 +#define CYFLD_UDB_DSI_VS_BOT__OFFSET 0x00000004 +#define CYFLD_UDB_DSI_VS_BOT__SIZE 0x00000004 +#define CYREG_UDB_DSI0_VS1 0x400f40e2 +#define CYREG_UDB_DSI0_VS2 0x400f40e4 +#define CYREG_UDB_DSI0_VS3 0x400f40e6 +#define CYREG_UDB_DSI0_VS4 0x400f40e8 +#define CYREG_UDB_DSI0_VS5 0x400f40ea +#define CYREG_UDB_DSI0_VS6 0x400f40ec +#define CYREG_UDB_DSI0_VS7 0x400f40ee +#define CYDEV_UDB_DSI1_BASE 0x400f4100 +#define CYDEV_UDB_DSI1_SIZE 0x00000100 +#define CYREG_UDB_DSI1_HC0 0x400f4100 +#define CYREG_UDB_DSI1_HC1 0x400f4101 +#define CYREG_UDB_DSI1_HC2 0x400f4102 +#define CYREG_UDB_DSI1_HC3 0x400f4103 +#define CYREG_UDB_DSI1_HC4 0x400f4104 +#define CYREG_UDB_DSI1_HC5 0x400f4105 +#define CYREG_UDB_DSI1_HC6 0x400f4106 +#define CYREG_UDB_DSI1_HC7 0x400f4107 +#define CYREG_UDB_DSI1_HC8 0x400f4108 +#define CYREG_UDB_DSI1_HC9 0x400f4109 +#define CYREG_UDB_DSI1_HC10 0x400f410a +#define CYREG_UDB_DSI1_HC11 0x400f410b +#define CYREG_UDB_DSI1_HC12 0x400f410c +#define CYREG_UDB_DSI1_HC13 0x400f410d +#define CYREG_UDB_DSI1_HC14 0x400f410e +#define CYREG_UDB_DSI1_HC15 0x400f410f +#define CYREG_UDB_DSI1_HC16 0x400f4110 +#define CYREG_UDB_DSI1_HC17 0x400f4111 +#define CYREG_UDB_DSI1_HC18 0x400f4112 +#define CYREG_UDB_DSI1_HC19 0x400f4113 +#define CYREG_UDB_DSI1_HC20 0x400f4114 +#define CYREG_UDB_DSI1_HC21 0x400f4115 +#define CYREG_UDB_DSI1_HC22 0x400f4116 +#define CYREG_UDB_DSI1_HC23 0x400f4117 +#define CYREG_UDB_DSI1_HC24 0x400f4118 +#define CYREG_UDB_DSI1_HC25 0x400f4119 +#define CYREG_UDB_DSI1_HC26 0x400f411a +#define CYREG_UDB_DSI1_HC27 0x400f411b +#define CYREG_UDB_DSI1_HC28 0x400f411c +#define CYREG_UDB_DSI1_HC29 0x400f411d +#define CYREG_UDB_DSI1_HC30 0x400f411e +#define CYREG_UDB_DSI1_HC31 0x400f411f +#define CYREG_UDB_DSI1_HC32 0x400f4120 +#define CYREG_UDB_DSI1_HC33 0x400f4121 +#define CYREG_UDB_DSI1_HC34 0x400f4122 +#define CYREG_UDB_DSI1_HC35 0x400f4123 +#define CYREG_UDB_DSI1_HC36 0x400f4124 +#define CYREG_UDB_DSI1_HC37 0x400f4125 +#define CYREG_UDB_DSI1_HC38 0x400f4126 +#define CYREG_UDB_DSI1_HC39 0x400f4127 +#define CYREG_UDB_DSI1_HC40 0x400f4128 +#define CYREG_UDB_DSI1_HC41 0x400f4129 +#define CYREG_UDB_DSI1_HC42 0x400f412a +#define CYREG_UDB_DSI1_HC43 0x400f412b +#define CYREG_UDB_DSI1_HC44 0x400f412c +#define CYREG_UDB_DSI1_HC45 0x400f412d +#define CYREG_UDB_DSI1_HC46 0x400f412e +#define CYREG_UDB_DSI1_HC47 0x400f412f +#define CYREG_UDB_DSI1_HC48 0x400f4130 +#define CYREG_UDB_DSI1_HC49 0x400f4131 +#define CYREG_UDB_DSI1_HC50 0x400f4132 +#define CYREG_UDB_DSI1_HC51 0x400f4133 +#define CYREG_UDB_DSI1_HC52 0x400f4134 +#define CYREG_UDB_DSI1_HC53 0x400f4135 +#define CYREG_UDB_DSI1_HC54 0x400f4136 +#define CYREG_UDB_DSI1_HC55 0x400f4137 +#define CYREG_UDB_DSI1_HC56 0x400f4138 +#define CYREG_UDB_DSI1_HC57 0x400f4139 +#define CYREG_UDB_DSI1_HC58 0x400f413a +#define CYREG_UDB_DSI1_HC59 0x400f413b +#define CYREG_UDB_DSI1_HC60 0x400f413c +#define CYREG_UDB_DSI1_HC61 0x400f413d +#define CYREG_UDB_DSI1_HC62 0x400f413e +#define CYREG_UDB_DSI1_HC63 0x400f413f +#define CYREG_UDB_DSI1_HC64 0x400f4140 +#define CYREG_UDB_DSI1_HC65 0x400f4141 +#define CYREG_UDB_DSI1_HC66 0x400f4142 +#define CYREG_UDB_DSI1_HC67 0x400f4143 +#define CYREG_UDB_DSI1_HC68 0x400f4144 +#define CYREG_UDB_DSI1_HC69 0x400f4145 +#define CYREG_UDB_DSI1_HC70 0x400f4146 +#define CYREG_UDB_DSI1_HC71 0x400f4147 +#define CYREG_UDB_DSI1_HC72 0x400f4148 +#define CYREG_UDB_DSI1_HC73 0x400f4149 +#define CYREG_UDB_DSI1_HC74 0x400f414a +#define CYREG_UDB_DSI1_HC75 0x400f414b +#define CYREG_UDB_DSI1_HC76 0x400f414c +#define CYREG_UDB_DSI1_HC77 0x400f414d +#define CYREG_UDB_DSI1_HC78 0x400f414e +#define CYREG_UDB_DSI1_HC79 0x400f414f +#define CYREG_UDB_DSI1_HC80 0x400f4150 +#define CYREG_UDB_DSI1_HC81 0x400f4151 +#define CYREG_UDB_DSI1_HC82 0x400f4152 +#define CYREG_UDB_DSI1_HC83 0x400f4153 +#define CYREG_UDB_DSI1_HC84 0x400f4154 +#define CYREG_UDB_DSI1_HC85 0x400f4155 +#define CYREG_UDB_DSI1_HC86 0x400f4156 +#define CYREG_UDB_DSI1_HC87 0x400f4157 +#define CYREG_UDB_DSI1_HC88 0x400f4158 +#define CYREG_UDB_DSI1_HC89 0x400f4159 +#define CYREG_UDB_DSI1_HC90 0x400f415a +#define CYREG_UDB_DSI1_HC91 0x400f415b +#define CYREG_UDB_DSI1_HC92 0x400f415c +#define CYREG_UDB_DSI1_HC93 0x400f415d +#define CYREG_UDB_DSI1_HC94 0x400f415e +#define CYREG_UDB_DSI1_HC95 0x400f415f +#define CYREG_UDB_DSI1_HC96 0x400f4160 +#define CYREG_UDB_DSI1_HC97 0x400f4161 +#define CYREG_UDB_DSI1_HC98 0x400f4162 +#define CYREG_UDB_DSI1_HC99 0x400f4163 +#define CYREG_UDB_DSI1_HC100 0x400f4164 +#define CYREG_UDB_DSI1_HC101 0x400f4165 +#define CYREG_UDB_DSI1_HC102 0x400f4166 +#define CYREG_UDB_DSI1_HC103 0x400f4167 +#define CYREG_UDB_DSI1_HC104 0x400f4168 +#define CYREG_UDB_DSI1_HC105 0x400f4169 +#define CYREG_UDB_DSI1_HC106 0x400f416a +#define CYREG_UDB_DSI1_HC107 0x400f416b +#define CYREG_UDB_DSI1_HC108 0x400f416c +#define CYREG_UDB_DSI1_HC109 0x400f416d +#define CYREG_UDB_DSI1_HC110 0x400f416e +#define CYREG_UDB_DSI1_HC111 0x400f416f +#define CYREG_UDB_DSI1_HC112 0x400f4170 +#define CYREG_UDB_DSI1_HC113 0x400f4171 +#define CYREG_UDB_DSI1_HC114 0x400f4172 +#define CYREG_UDB_DSI1_HC115 0x400f4173 +#define CYREG_UDB_DSI1_HC116 0x400f4174 +#define CYREG_UDB_DSI1_HC117 0x400f4175 +#define CYREG_UDB_DSI1_HC118 0x400f4176 +#define CYREG_UDB_DSI1_HC119 0x400f4177 +#define CYREG_UDB_DSI1_HC120 0x400f4178 +#define CYREG_UDB_DSI1_HC121 0x400f4179 +#define CYREG_UDB_DSI1_HC122 0x400f417a +#define CYREG_UDB_DSI1_HC123 0x400f417b +#define CYREG_UDB_DSI1_HC124 0x400f417c +#define CYREG_UDB_DSI1_HC125 0x400f417d +#define CYREG_UDB_DSI1_HC126 0x400f417e +#define CYREG_UDB_DSI1_HC127 0x400f417f +#define CYREG_UDB_DSI1_HV_L0 0x400f4180 +#define CYREG_UDB_DSI1_HV_L1 0x400f4181 +#define CYREG_UDB_DSI1_HV_L2 0x400f4182 +#define CYREG_UDB_DSI1_HV_L3 0x400f4183 +#define CYREG_UDB_DSI1_HV_L4 0x400f4184 +#define CYREG_UDB_DSI1_HV_L5 0x400f4185 +#define CYREG_UDB_DSI1_HV_L6 0x400f4186 +#define CYREG_UDB_DSI1_HV_L7 0x400f4187 +#define CYREG_UDB_DSI1_HV_L8 0x400f4188 +#define CYREG_UDB_DSI1_HV_L9 0x400f4189 +#define CYREG_UDB_DSI1_HV_L10 0x400f418a +#define CYREG_UDB_DSI1_HV_L11 0x400f418b +#define CYREG_UDB_DSI1_HV_L12 0x400f418c +#define CYREG_UDB_DSI1_HV_L13 0x400f418d +#define CYREG_UDB_DSI1_HV_L14 0x400f418e +#define CYREG_UDB_DSI1_HV_L15 0x400f418f +#define CYREG_UDB_DSI1_HS0 0x400f4190 +#define CYREG_UDB_DSI1_HS1 0x400f4191 +#define CYREG_UDB_DSI1_HS2 0x400f4192 +#define CYREG_UDB_DSI1_HS3 0x400f4193 +#define CYREG_UDB_DSI1_HS4 0x400f4194 +#define CYREG_UDB_DSI1_HS5 0x400f4195 +#define CYREG_UDB_DSI1_HS6 0x400f4196 +#define CYREG_UDB_DSI1_HS7 0x400f4197 +#define CYREG_UDB_DSI1_HS8 0x400f4198 +#define CYREG_UDB_DSI1_HS9 0x400f4199 +#define CYREG_UDB_DSI1_HS10 0x400f419a +#define CYREG_UDB_DSI1_HS11 0x400f419b +#define CYREG_UDB_DSI1_HS12 0x400f419c +#define CYREG_UDB_DSI1_HS13 0x400f419d +#define CYREG_UDB_DSI1_HS14 0x400f419e +#define CYREG_UDB_DSI1_HS15 0x400f419f +#define CYREG_UDB_DSI1_HS16 0x400f41a0 +#define CYREG_UDB_DSI1_HS17 0x400f41a1 +#define CYREG_UDB_DSI1_HS18 0x400f41a2 +#define CYREG_UDB_DSI1_HS19 0x400f41a3 +#define CYREG_UDB_DSI1_HS20 0x400f41a4 +#define CYREG_UDB_DSI1_HS21 0x400f41a5 +#define CYREG_UDB_DSI1_HS22 0x400f41a6 +#define CYREG_UDB_DSI1_HS23 0x400f41a7 +#define CYREG_UDB_DSI1_HV_R0 0x400f41a8 +#define CYREG_UDB_DSI1_HV_R1 0x400f41a9 +#define CYREG_UDB_DSI1_HV_R2 0x400f41aa +#define CYREG_UDB_DSI1_HV_R3 0x400f41ab +#define CYREG_UDB_DSI1_HV_R4 0x400f41ac +#define CYREG_UDB_DSI1_HV_R5 0x400f41ad +#define CYREG_UDB_DSI1_HV_R6 0x400f41ae +#define CYREG_UDB_DSI1_HV_R7 0x400f41af +#define CYREG_UDB_DSI1_HV_R8 0x400f41b0 +#define CYREG_UDB_DSI1_HV_R9 0x400f41b1 +#define CYREG_UDB_DSI1_HV_R10 0x400f41b2 +#define CYREG_UDB_DSI1_HV_R11 0x400f41b3 +#define CYREG_UDB_DSI1_HV_R12 0x400f41b4 +#define CYREG_UDB_DSI1_HV_R13 0x400f41b5 +#define CYREG_UDB_DSI1_HV_R14 0x400f41b6 +#define CYREG_UDB_DSI1_HV_R15 0x400f41b7 +#define CYREG_UDB_DSI1_DSIINP0 0x400f41c0 +#define CYREG_UDB_DSI1_DSIINP1 0x400f41c2 +#define CYREG_UDB_DSI1_DSIINP2 0x400f41c4 +#define CYREG_UDB_DSI1_DSIINP3 0x400f41c6 +#define CYREG_UDB_DSI1_DSIINP4 0x400f41c8 +#define CYREG_UDB_DSI1_DSIINP5 0x400f41ca +#define CYREG_UDB_DSI1_DSIOUTP0 0x400f41cc +#define CYREG_UDB_DSI1_DSIOUTP1 0x400f41ce +#define CYREG_UDB_DSI1_DSIOUTP2 0x400f41d0 +#define CYREG_UDB_DSI1_DSIOUTP3 0x400f41d2 +#define CYREG_UDB_DSI1_DSIOUTT0 0x400f41d4 +#define CYREG_UDB_DSI1_DSIOUTT1 0x400f41d6 +#define CYREG_UDB_DSI1_DSIOUTT2 0x400f41d8 +#define CYREG_UDB_DSI1_DSIOUTT3 0x400f41da +#define CYREG_UDB_DSI1_DSIOUTT4 0x400f41dc +#define CYREG_UDB_DSI1_DSIOUTT5 0x400f41de +#define CYREG_UDB_DSI1_VS0 0x400f41e0 +#define CYREG_UDB_DSI1_VS1 0x400f41e2 +#define CYREG_UDB_DSI1_VS2 0x400f41e4 +#define CYREG_UDB_DSI1_VS3 0x400f41e6 +#define CYREG_UDB_DSI1_VS4 0x400f41e8 +#define CYREG_UDB_DSI1_VS5 0x400f41ea +#define CYREG_UDB_DSI1_VS6 0x400f41ec +#define CYREG_UDB_DSI1_VS7 0x400f41ee +#define CYDEV_UDB_DSI2_BASE 0x400f4200 +#define CYDEV_UDB_DSI2_SIZE 0x00000100 +#define CYREG_UDB_DSI2_HC0 0x400f4200 +#define CYREG_UDB_DSI2_HC1 0x400f4201 +#define CYREG_UDB_DSI2_HC2 0x400f4202 +#define CYREG_UDB_DSI2_HC3 0x400f4203 +#define CYREG_UDB_DSI2_HC4 0x400f4204 +#define CYREG_UDB_DSI2_HC5 0x400f4205 +#define CYREG_UDB_DSI2_HC6 0x400f4206 +#define CYREG_UDB_DSI2_HC7 0x400f4207 +#define CYREG_UDB_DSI2_HC8 0x400f4208 +#define CYREG_UDB_DSI2_HC9 0x400f4209 +#define CYREG_UDB_DSI2_HC10 0x400f420a +#define CYREG_UDB_DSI2_HC11 0x400f420b +#define CYREG_UDB_DSI2_HC12 0x400f420c +#define CYREG_UDB_DSI2_HC13 0x400f420d +#define CYREG_UDB_DSI2_HC14 0x400f420e +#define CYREG_UDB_DSI2_HC15 0x400f420f +#define CYREG_UDB_DSI2_HC16 0x400f4210 +#define CYREG_UDB_DSI2_HC17 0x400f4211 +#define CYREG_UDB_DSI2_HC18 0x400f4212 +#define CYREG_UDB_DSI2_HC19 0x400f4213 +#define CYREG_UDB_DSI2_HC20 0x400f4214 +#define CYREG_UDB_DSI2_HC21 0x400f4215 +#define CYREG_UDB_DSI2_HC22 0x400f4216 +#define CYREG_UDB_DSI2_HC23 0x400f4217 +#define CYREG_UDB_DSI2_HC24 0x400f4218 +#define CYREG_UDB_DSI2_HC25 0x400f4219 +#define CYREG_UDB_DSI2_HC26 0x400f421a +#define CYREG_UDB_DSI2_HC27 0x400f421b +#define CYREG_UDB_DSI2_HC28 0x400f421c +#define CYREG_UDB_DSI2_HC29 0x400f421d +#define CYREG_UDB_DSI2_HC30 0x400f421e +#define CYREG_UDB_DSI2_HC31 0x400f421f +#define CYREG_UDB_DSI2_HC32 0x400f4220 +#define CYREG_UDB_DSI2_HC33 0x400f4221 +#define CYREG_UDB_DSI2_HC34 0x400f4222 +#define CYREG_UDB_DSI2_HC35 0x400f4223 +#define CYREG_UDB_DSI2_HC36 0x400f4224 +#define CYREG_UDB_DSI2_HC37 0x400f4225 +#define CYREG_UDB_DSI2_HC38 0x400f4226 +#define CYREG_UDB_DSI2_HC39 0x400f4227 +#define CYREG_UDB_DSI2_HC40 0x400f4228 +#define CYREG_UDB_DSI2_HC41 0x400f4229 +#define CYREG_UDB_DSI2_HC42 0x400f422a +#define CYREG_UDB_DSI2_HC43 0x400f422b +#define CYREG_UDB_DSI2_HC44 0x400f422c +#define CYREG_UDB_DSI2_HC45 0x400f422d +#define CYREG_UDB_DSI2_HC46 0x400f422e +#define CYREG_UDB_DSI2_HC47 0x400f422f +#define CYREG_UDB_DSI2_HC48 0x400f4230 +#define CYREG_UDB_DSI2_HC49 0x400f4231 +#define CYREG_UDB_DSI2_HC50 0x400f4232 +#define CYREG_UDB_DSI2_HC51 0x400f4233 +#define CYREG_UDB_DSI2_HC52 0x400f4234 +#define CYREG_UDB_DSI2_HC53 0x400f4235 +#define CYREG_UDB_DSI2_HC54 0x400f4236 +#define CYREG_UDB_DSI2_HC55 0x400f4237 +#define CYREG_UDB_DSI2_HC56 0x400f4238 +#define CYREG_UDB_DSI2_HC57 0x400f4239 +#define CYREG_UDB_DSI2_HC58 0x400f423a +#define CYREG_UDB_DSI2_HC59 0x400f423b +#define CYREG_UDB_DSI2_HC60 0x400f423c +#define CYREG_UDB_DSI2_HC61 0x400f423d +#define CYREG_UDB_DSI2_HC62 0x400f423e +#define CYREG_UDB_DSI2_HC63 0x400f423f +#define CYREG_UDB_DSI2_HC64 0x400f4240 +#define CYREG_UDB_DSI2_HC65 0x400f4241 +#define CYREG_UDB_DSI2_HC66 0x400f4242 +#define CYREG_UDB_DSI2_HC67 0x400f4243 +#define CYREG_UDB_DSI2_HC68 0x400f4244 +#define CYREG_UDB_DSI2_HC69 0x400f4245 +#define CYREG_UDB_DSI2_HC70 0x400f4246 +#define CYREG_UDB_DSI2_HC71 0x400f4247 +#define CYREG_UDB_DSI2_HC72 0x400f4248 +#define CYREG_UDB_DSI2_HC73 0x400f4249 +#define CYREG_UDB_DSI2_HC74 0x400f424a +#define CYREG_UDB_DSI2_HC75 0x400f424b +#define CYREG_UDB_DSI2_HC76 0x400f424c +#define CYREG_UDB_DSI2_HC77 0x400f424d +#define CYREG_UDB_DSI2_HC78 0x400f424e +#define CYREG_UDB_DSI2_HC79 0x400f424f +#define CYREG_UDB_DSI2_HC80 0x400f4250 +#define CYREG_UDB_DSI2_HC81 0x400f4251 +#define CYREG_UDB_DSI2_HC82 0x400f4252 +#define CYREG_UDB_DSI2_HC83 0x400f4253 +#define CYREG_UDB_DSI2_HC84 0x400f4254 +#define CYREG_UDB_DSI2_HC85 0x400f4255 +#define CYREG_UDB_DSI2_HC86 0x400f4256 +#define CYREG_UDB_DSI2_HC87 0x400f4257 +#define CYREG_UDB_DSI2_HC88 0x400f4258 +#define CYREG_UDB_DSI2_HC89 0x400f4259 +#define CYREG_UDB_DSI2_HC90 0x400f425a +#define CYREG_UDB_DSI2_HC91 0x400f425b +#define CYREG_UDB_DSI2_HC92 0x400f425c +#define CYREG_UDB_DSI2_HC93 0x400f425d +#define CYREG_UDB_DSI2_HC94 0x400f425e +#define CYREG_UDB_DSI2_HC95 0x400f425f +#define CYREG_UDB_DSI2_HC96 0x400f4260 +#define CYREG_UDB_DSI2_HC97 0x400f4261 +#define CYREG_UDB_DSI2_HC98 0x400f4262 +#define CYREG_UDB_DSI2_HC99 0x400f4263 +#define CYREG_UDB_DSI2_HC100 0x400f4264 +#define CYREG_UDB_DSI2_HC101 0x400f4265 +#define CYREG_UDB_DSI2_HC102 0x400f4266 +#define CYREG_UDB_DSI2_HC103 0x400f4267 +#define CYREG_UDB_DSI2_HC104 0x400f4268 +#define CYREG_UDB_DSI2_HC105 0x400f4269 +#define CYREG_UDB_DSI2_HC106 0x400f426a +#define CYREG_UDB_DSI2_HC107 0x400f426b +#define CYREG_UDB_DSI2_HC108 0x400f426c +#define CYREG_UDB_DSI2_HC109 0x400f426d +#define CYREG_UDB_DSI2_HC110 0x400f426e +#define CYREG_UDB_DSI2_HC111 0x400f426f +#define CYREG_UDB_DSI2_HC112 0x400f4270 +#define CYREG_UDB_DSI2_HC113 0x400f4271 +#define CYREG_UDB_DSI2_HC114 0x400f4272 +#define CYREG_UDB_DSI2_HC115 0x400f4273 +#define CYREG_UDB_DSI2_HC116 0x400f4274 +#define CYREG_UDB_DSI2_HC117 0x400f4275 +#define CYREG_UDB_DSI2_HC118 0x400f4276 +#define CYREG_UDB_DSI2_HC119 0x400f4277 +#define CYREG_UDB_DSI2_HC120 0x400f4278 +#define CYREG_UDB_DSI2_HC121 0x400f4279 +#define CYREG_UDB_DSI2_HC122 0x400f427a +#define CYREG_UDB_DSI2_HC123 0x400f427b +#define CYREG_UDB_DSI2_HC124 0x400f427c +#define CYREG_UDB_DSI2_HC125 0x400f427d +#define CYREG_UDB_DSI2_HC126 0x400f427e +#define CYREG_UDB_DSI2_HC127 0x400f427f +#define CYREG_UDB_DSI2_HV_L0 0x400f4280 +#define CYREG_UDB_DSI2_HV_L1 0x400f4281 +#define CYREG_UDB_DSI2_HV_L2 0x400f4282 +#define CYREG_UDB_DSI2_HV_L3 0x400f4283 +#define CYREG_UDB_DSI2_HV_L4 0x400f4284 +#define CYREG_UDB_DSI2_HV_L5 0x400f4285 +#define CYREG_UDB_DSI2_HV_L6 0x400f4286 +#define CYREG_UDB_DSI2_HV_L7 0x400f4287 +#define CYREG_UDB_DSI2_HV_L8 0x400f4288 +#define CYREG_UDB_DSI2_HV_L9 0x400f4289 +#define CYREG_UDB_DSI2_HV_L10 0x400f428a +#define CYREG_UDB_DSI2_HV_L11 0x400f428b +#define CYREG_UDB_DSI2_HV_L12 0x400f428c +#define CYREG_UDB_DSI2_HV_L13 0x400f428d +#define CYREG_UDB_DSI2_HV_L14 0x400f428e +#define CYREG_UDB_DSI2_HV_L15 0x400f428f +#define CYREG_UDB_DSI2_HS0 0x400f4290 +#define CYREG_UDB_DSI2_HS1 0x400f4291 +#define CYREG_UDB_DSI2_HS2 0x400f4292 +#define CYREG_UDB_DSI2_HS3 0x400f4293 +#define CYREG_UDB_DSI2_HS4 0x400f4294 +#define CYREG_UDB_DSI2_HS5 0x400f4295 +#define CYREG_UDB_DSI2_HS6 0x400f4296 +#define CYREG_UDB_DSI2_HS7 0x400f4297 +#define CYREG_UDB_DSI2_HS8 0x400f4298 +#define CYREG_UDB_DSI2_HS9 0x400f4299 +#define CYREG_UDB_DSI2_HS10 0x400f429a +#define CYREG_UDB_DSI2_HS11 0x400f429b +#define CYREG_UDB_DSI2_HS12 0x400f429c +#define CYREG_UDB_DSI2_HS13 0x400f429d +#define CYREG_UDB_DSI2_HS14 0x400f429e +#define CYREG_UDB_DSI2_HS15 0x400f429f +#define CYREG_UDB_DSI2_HS16 0x400f42a0 +#define CYREG_UDB_DSI2_HS17 0x400f42a1 +#define CYREG_UDB_DSI2_HS18 0x400f42a2 +#define CYREG_UDB_DSI2_HS19 0x400f42a3 +#define CYREG_UDB_DSI2_HS20 0x400f42a4 +#define CYREG_UDB_DSI2_HS21 0x400f42a5 +#define CYREG_UDB_DSI2_HS22 0x400f42a6 +#define CYREG_UDB_DSI2_HS23 0x400f42a7 +#define CYREG_UDB_DSI2_HV_R0 0x400f42a8 +#define CYREG_UDB_DSI2_HV_R1 0x400f42a9 +#define CYREG_UDB_DSI2_HV_R2 0x400f42aa +#define CYREG_UDB_DSI2_HV_R3 0x400f42ab +#define CYREG_UDB_DSI2_HV_R4 0x400f42ac +#define CYREG_UDB_DSI2_HV_R5 0x400f42ad +#define CYREG_UDB_DSI2_HV_R6 0x400f42ae +#define CYREG_UDB_DSI2_HV_R7 0x400f42af +#define CYREG_UDB_DSI2_HV_R8 0x400f42b0 +#define CYREG_UDB_DSI2_HV_R9 0x400f42b1 +#define CYREG_UDB_DSI2_HV_R10 0x400f42b2 +#define CYREG_UDB_DSI2_HV_R11 0x400f42b3 +#define CYREG_UDB_DSI2_HV_R12 0x400f42b4 +#define CYREG_UDB_DSI2_HV_R13 0x400f42b5 +#define CYREG_UDB_DSI2_HV_R14 0x400f42b6 +#define CYREG_UDB_DSI2_HV_R15 0x400f42b7 +#define CYREG_UDB_DSI2_DSIINP0 0x400f42c0 +#define CYREG_UDB_DSI2_DSIINP1 0x400f42c2 +#define CYREG_UDB_DSI2_DSIINP2 0x400f42c4 +#define CYREG_UDB_DSI2_DSIINP3 0x400f42c6 +#define CYREG_UDB_DSI2_DSIINP4 0x400f42c8 +#define CYREG_UDB_DSI2_DSIINP5 0x400f42ca +#define CYREG_UDB_DSI2_DSIOUTP0 0x400f42cc +#define CYREG_UDB_DSI2_DSIOUTP1 0x400f42ce +#define CYREG_UDB_DSI2_DSIOUTP2 0x400f42d0 +#define CYREG_UDB_DSI2_DSIOUTP3 0x400f42d2 +#define CYREG_UDB_DSI2_DSIOUTT0 0x400f42d4 +#define CYREG_UDB_DSI2_DSIOUTT1 0x400f42d6 +#define CYREG_UDB_DSI2_DSIOUTT2 0x400f42d8 +#define CYREG_UDB_DSI2_DSIOUTT3 0x400f42da +#define CYREG_UDB_DSI2_DSIOUTT4 0x400f42dc +#define CYREG_UDB_DSI2_DSIOUTT5 0x400f42de +#define CYREG_UDB_DSI2_VS0 0x400f42e0 +#define CYREG_UDB_DSI2_VS1 0x400f42e2 +#define CYREG_UDB_DSI2_VS2 0x400f42e4 +#define CYREG_UDB_DSI2_VS3 0x400f42e6 +#define CYREG_UDB_DSI2_VS4 0x400f42e8 +#define CYREG_UDB_DSI2_VS5 0x400f42ea +#define CYREG_UDB_DSI2_VS6 0x400f42ec +#define CYREG_UDB_DSI2_VS7 0x400f42ee +#define CYDEV_UDB_DSI3_BASE 0x400f4300 +#define CYDEV_UDB_DSI3_SIZE 0x00000100 +#define CYREG_UDB_DSI3_HC0 0x400f4300 +#define CYREG_UDB_DSI3_HC1 0x400f4301 +#define CYREG_UDB_DSI3_HC2 0x400f4302 +#define CYREG_UDB_DSI3_HC3 0x400f4303 +#define CYREG_UDB_DSI3_HC4 0x400f4304 +#define CYREG_UDB_DSI3_HC5 0x400f4305 +#define CYREG_UDB_DSI3_HC6 0x400f4306 +#define CYREG_UDB_DSI3_HC7 0x400f4307 +#define CYREG_UDB_DSI3_HC8 0x400f4308 +#define CYREG_UDB_DSI3_HC9 0x400f4309 +#define CYREG_UDB_DSI3_HC10 0x400f430a +#define CYREG_UDB_DSI3_HC11 0x400f430b +#define CYREG_UDB_DSI3_HC12 0x400f430c +#define CYREG_UDB_DSI3_HC13 0x400f430d +#define CYREG_UDB_DSI3_HC14 0x400f430e +#define CYREG_UDB_DSI3_HC15 0x400f430f +#define CYREG_UDB_DSI3_HC16 0x400f4310 +#define CYREG_UDB_DSI3_HC17 0x400f4311 +#define CYREG_UDB_DSI3_HC18 0x400f4312 +#define CYREG_UDB_DSI3_HC19 0x400f4313 +#define CYREG_UDB_DSI3_HC20 0x400f4314 +#define CYREG_UDB_DSI3_HC21 0x400f4315 +#define CYREG_UDB_DSI3_HC22 0x400f4316 +#define CYREG_UDB_DSI3_HC23 0x400f4317 +#define CYREG_UDB_DSI3_HC24 0x400f4318 +#define CYREG_UDB_DSI3_HC25 0x400f4319 +#define CYREG_UDB_DSI3_HC26 0x400f431a +#define CYREG_UDB_DSI3_HC27 0x400f431b +#define CYREG_UDB_DSI3_HC28 0x400f431c +#define CYREG_UDB_DSI3_HC29 0x400f431d +#define CYREG_UDB_DSI3_HC30 0x400f431e +#define CYREG_UDB_DSI3_HC31 0x400f431f +#define CYREG_UDB_DSI3_HC32 0x400f4320 +#define CYREG_UDB_DSI3_HC33 0x400f4321 +#define CYREG_UDB_DSI3_HC34 0x400f4322 +#define CYREG_UDB_DSI3_HC35 0x400f4323 +#define CYREG_UDB_DSI3_HC36 0x400f4324 +#define CYREG_UDB_DSI3_HC37 0x400f4325 +#define CYREG_UDB_DSI3_HC38 0x400f4326 +#define CYREG_UDB_DSI3_HC39 0x400f4327 +#define CYREG_UDB_DSI3_HC40 0x400f4328 +#define CYREG_UDB_DSI3_HC41 0x400f4329 +#define CYREG_UDB_DSI3_HC42 0x400f432a +#define CYREG_UDB_DSI3_HC43 0x400f432b +#define CYREG_UDB_DSI3_HC44 0x400f432c +#define CYREG_UDB_DSI3_HC45 0x400f432d +#define CYREG_UDB_DSI3_HC46 0x400f432e +#define CYREG_UDB_DSI3_HC47 0x400f432f +#define CYREG_UDB_DSI3_HC48 0x400f4330 +#define CYREG_UDB_DSI3_HC49 0x400f4331 +#define CYREG_UDB_DSI3_HC50 0x400f4332 +#define CYREG_UDB_DSI3_HC51 0x400f4333 +#define CYREG_UDB_DSI3_HC52 0x400f4334 +#define CYREG_UDB_DSI3_HC53 0x400f4335 +#define CYREG_UDB_DSI3_HC54 0x400f4336 +#define CYREG_UDB_DSI3_HC55 0x400f4337 +#define CYREG_UDB_DSI3_HC56 0x400f4338 +#define CYREG_UDB_DSI3_HC57 0x400f4339 +#define CYREG_UDB_DSI3_HC58 0x400f433a +#define CYREG_UDB_DSI3_HC59 0x400f433b +#define CYREG_UDB_DSI3_HC60 0x400f433c +#define CYREG_UDB_DSI3_HC61 0x400f433d +#define CYREG_UDB_DSI3_HC62 0x400f433e +#define CYREG_UDB_DSI3_HC63 0x400f433f +#define CYREG_UDB_DSI3_HC64 0x400f4340 +#define CYREG_UDB_DSI3_HC65 0x400f4341 +#define CYREG_UDB_DSI3_HC66 0x400f4342 +#define CYREG_UDB_DSI3_HC67 0x400f4343 +#define CYREG_UDB_DSI3_HC68 0x400f4344 +#define CYREG_UDB_DSI3_HC69 0x400f4345 +#define CYREG_UDB_DSI3_HC70 0x400f4346 +#define CYREG_UDB_DSI3_HC71 0x400f4347 +#define CYREG_UDB_DSI3_HC72 0x400f4348 +#define CYREG_UDB_DSI3_HC73 0x400f4349 +#define CYREG_UDB_DSI3_HC74 0x400f434a +#define CYREG_UDB_DSI3_HC75 0x400f434b +#define CYREG_UDB_DSI3_HC76 0x400f434c +#define CYREG_UDB_DSI3_HC77 0x400f434d +#define CYREG_UDB_DSI3_HC78 0x400f434e +#define CYREG_UDB_DSI3_HC79 0x400f434f +#define CYREG_UDB_DSI3_HC80 0x400f4350 +#define CYREG_UDB_DSI3_HC81 0x400f4351 +#define CYREG_UDB_DSI3_HC82 0x400f4352 +#define CYREG_UDB_DSI3_HC83 0x400f4353 +#define CYREG_UDB_DSI3_HC84 0x400f4354 +#define CYREG_UDB_DSI3_HC85 0x400f4355 +#define CYREG_UDB_DSI3_HC86 0x400f4356 +#define CYREG_UDB_DSI3_HC87 0x400f4357 +#define CYREG_UDB_DSI3_HC88 0x400f4358 +#define CYREG_UDB_DSI3_HC89 0x400f4359 +#define CYREG_UDB_DSI3_HC90 0x400f435a +#define CYREG_UDB_DSI3_HC91 0x400f435b +#define CYREG_UDB_DSI3_HC92 0x400f435c +#define CYREG_UDB_DSI3_HC93 0x400f435d +#define CYREG_UDB_DSI3_HC94 0x400f435e +#define CYREG_UDB_DSI3_HC95 0x400f435f +#define CYREG_UDB_DSI3_HC96 0x400f4360 +#define CYREG_UDB_DSI3_HC97 0x400f4361 +#define CYREG_UDB_DSI3_HC98 0x400f4362 +#define CYREG_UDB_DSI3_HC99 0x400f4363 +#define CYREG_UDB_DSI3_HC100 0x400f4364 +#define CYREG_UDB_DSI3_HC101 0x400f4365 +#define CYREG_UDB_DSI3_HC102 0x400f4366 +#define CYREG_UDB_DSI3_HC103 0x400f4367 +#define CYREG_UDB_DSI3_HC104 0x400f4368 +#define CYREG_UDB_DSI3_HC105 0x400f4369 +#define CYREG_UDB_DSI3_HC106 0x400f436a +#define CYREG_UDB_DSI3_HC107 0x400f436b +#define CYREG_UDB_DSI3_HC108 0x400f436c +#define CYREG_UDB_DSI3_HC109 0x400f436d +#define CYREG_UDB_DSI3_HC110 0x400f436e +#define CYREG_UDB_DSI3_HC111 0x400f436f +#define CYREG_UDB_DSI3_HC112 0x400f4370 +#define CYREG_UDB_DSI3_HC113 0x400f4371 +#define CYREG_UDB_DSI3_HC114 0x400f4372 +#define CYREG_UDB_DSI3_HC115 0x400f4373 +#define CYREG_UDB_DSI3_HC116 0x400f4374 +#define CYREG_UDB_DSI3_HC117 0x400f4375 +#define CYREG_UDB_DSI3_HC118 0x400f4376 +#define CYREG_UDB_DSI3_HC119 0x400f4377 +#define CYREG_UDB_DSI3_HC120 0x400f4378 +#define CYREG_UDB_DSI3_HC121 0x400f4379 +#define CYREG_UDB_DSI3_HC122 0x400f437a +#define CYREG_UDB_DSI3_HC123 0x400f437b +#define CYREG_UDB_DSI3_HC124 0x400f437c +#define CYREG_UDB_DSI3_HC125 0x400f437d +#define CYREG_UDB_DSI3_HC126 0x400f437e +#define CYREG_UDB_DSI3_HC127 0x400f437f +#define CYREG_UDB_DSI3_HV_L0 0x400f4380 +#define CYREG_UDB_DSI3_HV_L1 0x400f4381 +#define CYREG_UDB_DSI3_HV_L2 0x400f4382 +#define CYREG_UDB_DSI3_HV_L3 0x400f4383 +#define CYREG_UDB_DSI3_HV_L4 0x400f4384 +#define CYREG_UDB_DSI3_HV_L5 0x400f4385 +#define CYREG_UDB_DSI3_HV_L6 0x400f4386 +#define CYREG_UDB_DSI3_HV_L7 0x400f4387 +#define CYREG_UDB_DSI3_HV_L8 0x400f4388 +#define CYREG_UDB_DSI3_HV_L9 0x400f4389 +#define CYREG_UDB_DSI3_HV_L10 0x400f438a +#define CYREG_UDB_DSI3_HV_L11 0x400f438b +#define CYREG_UDB_DSI3_HV_L12 0x400f438c +#define CYREG_UDB_DSI3_HV_L13 0x400f438d +#define CYREG_UDB_DSI3_HV_L14 0x400f438e +#define CYREG_UDB_DSI3_HV_L15 0x400f438f +#define CYREG_UDB_DSI3_HS0 0x400f4390 +#define CYREG_UDB_DSI3_HS1 0x400f4391 +#define CYREG_UDB_DSI3_HS2 0x400f4392 +#define CYREG_UDB_DSI3_HS3 0x400f4393 +#define CYREG_UDB_DSI3_HS4 0x400f4394 +#define CYREG_UDB_DSI3_HS5 0x400f4395 +#define CYREG_UDB_DSI3_HS6 0x400f4396 +#define CYREG_UDB_DSI3_HS7 0x400f4397 +#define CYREG_UDB_DSI3_HS8 0x400f4398 +#define CYREG_UDB_DSI3_HS9 0x400f4399 +#define CYREG_UDB_DSI3_HS10 0x400f439a +#define CYREG_UDB_DSI3_HS11 0x400f439b +#define CYREG_UDB_DSI3_HS12 0x400f439c +#define CYREG_UDB_DSI3_HS13 0x400f439d +#define CYREG_UDB_DSI3_HS14 0x400f439e +#define CYREG_UDB_DSI3_HS15 0x400f439f +#define CYREG_UDB_DSI3_HS16 0x400f43a0 +#define CYREG_UDB_DSI3_HS17 0x400f43a1 +#define CYREG_UDB_DSI3_HS18 0x400f43a2 +#define CYREG_UDB_DSI3_HS19 0x400f43a3 +#define CYREG_UDB_DSI3_HS20 0x400f43a4 +#define CYREG_UDB_DSI3_HS21 0x400f43a5 +#define CYREG_UDB_DSI3_HS22 0x400f43a6 +#define CYREG_UDB_DSI3_HS23 0x400f43a7 +#define CYREG_UDB_DSI3_HV_R0 0x400f43a8 +#define CYREG_UDB_DSI3_HV_R1 0x400f43a9 +#define CYREG_UDB_DSI3_HV_R2 0x400f43aa +#define CYREG_UDB_DSI3_HV_R3 0x400f43ab +#define CYREG_UDB_DSI3_HV_R4 0x400f43ac +#define CYREG_UDB_DSI3_HV_R5 0x400f43ad +#define CYREG_UDB_DSI3_HV_R6 0x400f43ae +#define CYREG_UDB_DSI3_HV_R7 0x400f43af +#define CYREG_UDB_DSI3_HV_R8 0x400f43b0 +#define CYREG_UDB_DSI3_HV_R9 0x400f43b1 +#define CYREG_UDB_DSI3_HV_R10 0x400f43b2 +#define CYREG_UDB_DSI3_HV_R11 0x400f43b3 +#define CYREG_UDB_DSI3_HV_R12 0x400f43b4 +#define CYREG_UDB_DSI3_HV_R13 0x400f43b5 +#define CYREG_UDB_DSI3_HV_R14 0x400f43b6 +#define CYREG_UDB_DSI3_HV_R15 0x400f43b7 +#define CYREG_UDB_DSI3_DSIINP0 0x400f43c0 +#define CYREG_UDB_DSI3_DSIINP1 0x400f43c2 +#define CYREG_UDB_DSI3_DSIINP2 0x400f43c4 +#define CYREG_UDB_DSI3_DSIINP3 0x400f43c6 +#define CYREG_UDB_DSI3_DSIINP4 0x400f43c8 +#define CYREG_UDB_DSI3_DSIINP5 0x400f43ca +#define CYREG_UDB_DSI3_DSIOUTP0 0x400f43cc +#define CYREG_UDB_DSI3_DSIOUTP1 0x400f43ce +#define CYREG_UDB_DSI3_DSIOUTP2 0x400f43d0 +#define CYREG_UDB_DSI3_DSIOUTP3 0x400f43d2 +#define CYREG_UDB_DSI3_DSIOUTT0 0x400f43d4 +#define CYREG_UDB_DSI3_DSIOUTT1 0x400f43d6 +#define CYREG_UDB_DSI3_DSIOUTT2 0x400f43d8 +#define CYREG_UDB_DSI3_DSIOUTT3 0x400f43da +#define CYREG_UDB_DSI3_DSIOUTT4 0x400f43dc +#define CYREG_UDB_DSI3_DSIOUTT5 0x400f43de +#define CYREG_UDB_DSI3_VS0 0x400f43e0 +#define CYREG_UDB_DSI3_VS1 0x400f43e2 +#define CYREG_UDB_DSI3_VS2 0x400f43e4 +#define CYREG_UDB_DSI3_VS3 0x400f43e6 +#define CYREG_UDB_DSI3_VS4 0x400f43e8 +#define CYREG_UDB_DSI3_VS5 0x400f43ea +#define CYREG_UDB_DSI3_VS6 0x400f43ec +#define CYREG_UDB_DSI3_VS7 0x400f43ee +#define CYDEV_UDB_PA0_BASE 0x400f5000 +#define CYDEV_UDB_PA0_SIZE 0x00000010 +#define CYREG_UDB_PA0_CFG0 0x400f5000 +#define CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET 0x00000002 +#define CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_OFF 0x00000000 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_ON 0x00000001 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE 0x00000002 +#define CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL 0x00000003 +#define CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET 0x00000004 +#define CYFLD_UDB_PA_CLKIN_EN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKIN_EN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKIN_EN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_CLKIN_INV__OFFSET 0x00000005 +#define CYFLD_UDB_PA_CLKIN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKIN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKIN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_NC__OFFSET 0x00000006 +#define CYFLD_UDB_PA_NC__SIZE 0x00000002 +#define CYREG_UDB_PA0_CFG1 0x400f5001 +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET 0x00000002 +#define CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_ON 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL 0x00000003 +#define CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET 0x00000004 +#define CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_EN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_CLKOUT_INV__OFFSET 0x00000005 +#define CYFLD_UDB_PA_CLKOUT_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_INV_INV 0x00000001 +#define CYREG_UDB_PA0_CFG2 0x400f5002 +#define CYFLD_UDB_PA_CLKIN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_CLKIN_SEL__SIZE 0x00000004 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_PA_CLKIN_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP 0x00000009 +#define CYVAL_UDB_PA_CLKIN_SEL_PIN_RC 0x0000000c +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 0x0000000d +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 0x0000000e +#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 0x0000000f +#define CYFLD_UDB_PA_CLKOUT_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_PA_CLKOUT_SEL__SIZE 0x00000004 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 0x00000000 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 0x00000001 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 0x00000002 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 0x00000003 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 0x00000004 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 0x00000005 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 0x00000006 +#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 0x00000007 +#define CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP 0x00000009 +#define CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC 0x0000000c +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 0x0000000d +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 0x0000000e +#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 0x0000000f +#define CYREG_UDB_PA0_CFG3 0x400f5003 +#define CYFLD_UDB_PA_RES_IN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_RES_IN_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_RES_IN_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_RES_IN_INV__OFFSET 0x00000002 +#define CYFLD_UDB_PA_RES_IN_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_IN_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_RES_IN_INV_INV 0x00000001 +#define CYFLD_UDB_PA_NC0__OFFSET 0x00000003 +#define CYFLD_UDB_PA_NC0__SIZE 0x00000001 +#define CYFLD_UDB_PA_RES_OUT_SEL__OFFSET 0x00000004 +#define CYFLD_UDB_PA_RES_OUT_SEL__SIZE 0x00000002 +#define CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC 0x00000000 +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 0x00000001 +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 0x00000002 +#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 0x00000003 +#define CYFLD_UDB_PA_RES_OUT_INV__OFFSET 0x00000006 +#define CYFLD_UDB_PA_RES_OUT_INV__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_OUT_INV_NOINV 0x00000000 +#define CYVAL_UDB_PA_RES_OUT_INV_INV 0x00000001 +#define CYFLD_UDB_PA_NC7__OFFSET 0x00000007 +#define CYFLD_UDB_PA_NC7__SIZE 0x00000001 +#define CYREG_UDB_PA0_CFG4 0x400f5004 +#define CYFLD_UDB_PA_RES_IN_EN__OFFSET 0x00000000 +#define CYFLD_UDB_PA_RES_IN_EN__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_IN_EN_DISABLE 0x00000000 +#define CYVAL_UDB_PA_RES_IN_EN_ENABLE 0x00000001 +#define CYFLD_UDB_PA_RES_OUT_EN__OFFSET 0x00000001 +#define CYFLD_UDB_PA_RES_OUT_EN__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_OUT_EN_DISABLE 0x00000000 +#define CYVAL_UDB_PA_RES_OUT_EN_ENABLE 0x00000001 +#define CYFLD_UDB_PA_RES_OE_EN__OFFSET 0x00000002 +#define CYFLD_UDB_PA_RES_OE_EN__SIZE 0x00000001 +#define CYVAL_UDB_PA_RES_OE_EN_DISABLE 0x00000000 +#define CYVAL_UDB_PA_RES_OE_EN_ENABLE 0x00000001 +#define CYFLD_UDB_PA_NC7654__OFFSET 0x00000003 +#define CYFLD_UDB_PA_NC7654__SIZE 0x00000005 +#define CYREG_UDB_PA0_CFG5 0x400f5005 +#define CYFLD_UDB_PA_PIN_SEL__OFFSET 0x00000000 +#define CYFLD_UDB_PA_PIN_SEL__SIZE 0x00000001 +#define CYVAL_UDB_PA_PIN_SEL_PIN0 0x00000000 +#define CYVAL_UDB_PA_PIN_SEL_PIN1 0x00000001 +#define CYVAL_UDB_PA_PIN_SEL_PIN2 0x00000002 +#define CYVAL_UDB_PA_PIN_SEL_PIN3 0x00000003 +#define CYVAL_UDB_PA_PIN_SEL_PIN4 0x00000004 +#define CYVAL_UDB_PA_PIN_SEL_PIN5 0x00000005 +#define CYVAL_UDB_PA_PIN_SEL_PIN6 0x00000006 +#define CYVAL_UDB_PA_PIN_SEL_PIN7 0x00000007 +#define CYREG_UDB_PA0_CFG6 0x400f5006 +#define CYFLD_UDB_PA_IN_SYNC0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_IN_SYNC0__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC0_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_IN_SYNC1__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC1_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_IN_SYNC2__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC2_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_IN_SYNC3__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC3_RSVD 0x00000003 +#define CYREG_UDB_PA0_CFG7 0x400f5007 +#define CYFLD_UDB_PA_IN_SYNC4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_IN_SYNC4__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC4_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_IN_SYNC5__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC5_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_IN_SYNC6__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC6_RSVD 0x00000003 +#define CYFLD_UDB_PA_IN_SYNC7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_IN_SYNC7__SIZE 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC 0x00000002 +#define CYVAL_UDB_PA_IN_SYNC7_RSVD 0x00000003 +#define CYREG_UDB_PA0_CFG8 0x400f5008 +#define CYFLD_UDB_PA_OUT_SYNC0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OUT_SYNC0__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OUT_SYNC1__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OUT_SYNC2__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OUT_SYNC3__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV 0x00000003 +#define CYREG_UDB_PA0_CFG9 0x400f5009 +#define CYFLD_UDB_PA_OUT_SYNC4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OUT_SYNC4__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OUT_SYNC5__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OUT_SYNC6__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV 0x00000003 +#define CYFLD_UDB_PA_OUT_SYNC7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OUT_SYNC7__SIZE 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCK 0x00000002 +#define CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV 0x00000003 +#define CYREG_UDB_PA0_CFG10 0x400f500a +#define CYFLD_UDB_PA_DATA_SEL0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_DATA_SEL0__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_DATA_SEL1__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_DATA_SEL2__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_DATA_SEL3__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 0x00000003 +#define CYREG_UDB_PA0_CFG11 0x400f500b +#define CYFLD_UDB_PA_DATA_SEL4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_DATA_SEL4__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_DATA_SEL5__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_DATA_SEL6__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 0x00000003 +#define CYFLD_UDB_PA_DATA_SEL7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_DATA_SEL7__SIZE 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 0x00000000 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 0x00000001 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 0x00000002 +#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 0x00000003 +#define CYREG_UDB_PA0_CFG12 0x400f500c +#define CYFLD_UDB_PA_OE_SEL0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OE_SEL0__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OE_SEL1__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OE_SEL2__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OE_SEL3__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 0x00000003 +#define CYREG_UDB_PA0_CFG13 0x400f500d +#define CYFLD_UDB_PA_OE_SEL4__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OE_SEL4__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL5__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OE_SEL5__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL6__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OE_SEL6__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 0x00000003 +#define CYFLD_UDB_PA_OE_SEL7__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OE_SEL7__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 0x00000000 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 0x00000001 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 0x00000002 +#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 0x00000003 +#define CYREG_UDB_PA0_CFG14 0x400f500e +#define CYFLD_UDB_PA_OE_SYNC0__OFFSET 0x00000000 +#define CYFLD_UDB_PA_OE_SYNC0__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 0x00000003 +#define CYFLD_UDB_PA_OE_SYNC1__OFFSET 0x00000002 +#define CYFLD_UDB_PA_OE_SYNC1__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 0x00000003 +#define CYFLD_UDB_PA_OE_SYNC2__OFFSET 0x00000004 +#define CYFLD_UDB_PA_OE_SYNC2__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 0x00000003 +#define CYFLD_UDB_PA_OE_SYNC3__OFFSET 0x00000006 +#define CYFLD_UDB_PA_OE_SYNC3__SIZE 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT 0x00000000 +#define CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC 0x00000001 +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 0x00000002 +#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 0x00000003 +#define CYDEV_UDB_PA1_BASE 0x400f5010 +#define CYDEV_UDB_PA1_SIZE 0x00000010 +#define CYREG_UDB_PA1_CFG0 0x400f5010 +#define CYREG_UDB_PA1_CFG1 0x400f5011 +#define CYREG_UDB_PA1_CFG2 0x400f5012 +#define CYREG_UDB_PA1_CFG3 0x400f5013 +#define CYREG_UDB_PA1_CFG4 0x400f5014 +#define CYREG_UDB_PA1_CFG5 0x400f5015 +#define CYREG_UDB_PA1_CFG6 0x400f5016 +#define CYREG_UDB_PA1_CFG7 0x400f5017 +#define CYREG_UDB_PA1_CFG8 0x400f5018 +#define CYREG_UDB_PA1_CFG9 0x400f5019 +#define CYREG_UDB_PA1_CFG10 0x400f501a +#define CYREG_UDB_PA1_CFG11 0x400f501b +#define CYREG_UDB_PA1_CFG12 0x400f501c +#define CYREG_UDB_PA1_CFG13 0x400f501d +#define CYREG_UDB_PA1_CFG14 0x400f501e +#define CYDEV_UDB_PA2_BASE 0x400f5020 +#define CYDEV_UDB_PA2_SIZE 0x00000010 +#define CYREG_UDB_PA2_CFG0 0x400f5020 +#define CYREG_UDB_PA2_CFG1 0x400f5021 +#define CYREG_UDB_PA2_CFG2 0x400f5022 +#define CYREG_UDB_PA2_CFG3 0x400f5023 +#define CYREG_UDB_PA2_CFG4 0x400f5024 +#define CYREG_UDB_PA2_CFG5 0x400f5025 +#define CYREG_UDB_PA2_CFG6 0x400f5026 +#define CYREG_UDB_PA2_CFG7 0x400f5027 +#define CYREG_UDB_PA2_CFG8 0x400f5028 +#define CYREG_UDB_PA2_CFG9 0x400f5029 +#define CYREG_UDB_PA2_CFG10 0x400f502a +#define CYREG_UDB_PA2_CFG11 0x400f502b +#define CYREG_UDB_PA2_CFG12 0x400f502c +#define CYREG_UDB_PA2_CFG13 0x400f502d +#define CYREG_UDB_PA2_CFG14 0x400f502e +#define CYDEV_UDB_PA3_BASE 0x400f5030 +#define CYDEV_UDB_PA3_SIZE 0x00000010 +#define CYREG_UDB_PA3_CFG0 0x400f5030 +#define CYREG_UDB_PA3_CFG1 0x400f5031 +#define CYREG_UDB_PA3_CFG2 0x400f5032 +#define CYREG_UDB_PA3_CFG3 0x400f5033 +#define CYREG_UDB_PA3_CFG4 0x400f5034 +#define CYREG_UDB_PA3_CFG5 0x400f5035 +#define CYREG_UDB_PA3_CFG6 0x400f5036 +#define CYREG_UDB_PA3_CFG7 0x400f5037 +#define CYREG_UDB_PA3_CFG8 0x400f5038 +#define CYREG_UDB_PA3_CFG9 0x400f5039 +#define CYREG_UDB_PA3_CFG10 0x400f503a +#define CYREG_UDB_PA3_CFG11 0x400f503b +#define CYREG_UDB_PA3_CFG12 0x400f503c +#define CYREG_UDB_PA3_CFG13 0x400f503d +#define CYREG_UDB_PA3_CFG14 0x400f503e +#define CYDEV_UDB_BCTL0_BASE 0x400f6000 +#define CYDEV_UDB_BCTL0_SIZE 0x00001000 +#define CYREG_UDB_BCTL0_DRV 0x400f6000 +#define CYFLD_UDB_BCTL0_DRV__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_DRV__SIZE 0x00000008 +#define CYVAL_UDB_BCTL0_DRV_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DRV_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_MDCLK_EN 0x400f6001 +#define CYFLD_UDB_BCTL0_DCEN__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_DCEN__SIZE 0x00000008 +#define CYVAL_UDB_BCTL0_DCEN_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DCEN_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_MBCLK_EN 0x400f6002 +#define CYFLD_UDB_BCTL0_BCEN__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_BCEN__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_BCEN_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_BCEN_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_BOTSEL_L 0x400f6008 +#define CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_CLK_SEL0__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET 0x00000002 +#define CYFLD_UDB_BCTL0_CLK_SEL1__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET 0x00000004 +#define CYFLD_UDB_BCTL0_CLK_SEL2__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET 0x00000006 +#define CYFLD_UDB_BCTL0_CLK_SEL3__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT 0x00000003 +#define CYREG_UDB_BCTL0_BOTSEL_U 0x400f6009 +#define CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_CLK_SEL4__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET 0x00000002 +#define CYFLD_UDB_BCTL0_CLK_SEL5__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET 0x00000004 +#define CYFLD_UDB_BCTL0_CLK_SEL6__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT 0x00000003 +#define CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET 0x00000006 +#define CYFLD_UDB_BCTL0_CLK_SEL7__SIZE 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES 0x00000000 +#define CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT 0x00000001 +#define CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT 0x00000002 +#define CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT 0x00000003 +#define CYREG_UDB_BCTL0_TOPSEL_L 0x400f600a +#define CYREG_UDB_BCTL0_TOPSEL_U 0x400f600b +#define CYREG_UDB_BCTL0_QCLK_EN0 0x400f6010 +#define CYFLD_UDB_BCTL0_DCEN_Q__OFFSET 0x00000000 +#define CYFLD_UDB_BCTL0_DCEN_Q__SIZE 0x00000008 +#define CYVAL_UDB_BCTL0_DCEN_Q_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DCEN_Q_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_BCEN_Q__OFFSET 0x00000008 +#define CYFLD_UDB_BCTL0_BCEN_Q__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_BCEN_Q_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_BCEN_Q_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET 0x00000009 +#define CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET 0x0000000a +#define CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET 0x0000000b +#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET 0x0000000c +#define CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE 0x00000001 +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET 0x0000000d +#define CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB 0x00000000 +#define CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB 0x00000001 +#define CYFLD_UDB_BCTL0_NC0__OFFSET 0x0000000e +#define CYFLD_UDB_BCTL0_NC0__SIZE 0x00000001 +#define CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET 0x0000000f +#define CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE 0x00000001 +#define CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE 0x00000000 +#define CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE 0x00000001 +#define CYREG_UDB_BCTL0_QCLK_EN1 0x400f6012 +#define CYDEV_UDB_UDBIF_BASE 0x400f7000 +#define CYDEV_UDB_UDBIF_SIZE 0x00001000 +#define CYREG_UDB_UDBIF_BANK_CTL 0x400f7000 +#define CYFLD_UDB_UDBIF_DIS_COR__OFFSET 0x00000000 +#define CYFLD_UDB_UDBIF_DIS_COR__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_DIS_COR_NORMAL 0x00000000 +#define CYVAL_UDB_UDBIF_DIS_COR_DISABLE 0x00000001 +#define CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET 0x00000001 +#define CYFLD_UDB_UDBIF_ROUTE_EN__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE 0x00000000 +#define CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE 0x00000001 +#define CYFLD_UDB_UDBIF_BANK_EN__OFFSET 0x00000002 +#define CYFLD_UDB_UDBIF_BANK_EN__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_BANK_EN_DISABLE 0x00000000 +#define CYVAL_UDB_UDBIF_BANK_EN_ENABLE 0x00000001 +#define CYFLD_UDB_UDBIF_LOCK__OFFSET 0x00000003 +#define CYFLD_UDB_UDBIF_LOCK__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_LOCK_MUTABLE 0x00000000 +#define CYVAL_UDB_UDBIF_LOCK_LOCKED 0x00000001 +#define CYFLD_UDB_UDBIF_PIPE__OFFSET 0x00000004 +#define CYFLD_UDB_UDBIF_PIPE__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_PIPE_BYPASS 0x00000000 +#define CYVAL_UDB_UDBIF_PIPE_PIPELINED 0x00000001 +#define CYFLD_UDB_UDBIF_GLBL_WR__OFFSET 0x00000007 +#define CYFLD_UDB_UDBIF_GLBL_WR__SIZE 0x00000001 +#define CYVAL_UDB_UDBIF_GLBL_WR_DISABLE 0x00000000 +#define CYVAL_UDB_UDBIF_GLBL_WR_ENABLE 0x00000001 +#define CYREG_UDB_UDBIF_WAIT_CFG 0x400f7001 +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET 0x00000000 +#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS 0x00000000 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT 0x00000003 +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET 0x00000002 +#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT 0x00000000 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS 0x00000003 +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET 0x00000004 +#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT 0x00000000 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS 0x00000003 +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET 0x00000006 +#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE 0x00000002 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT 0x00000000 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS 0x00000001 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS 0x00000002 +#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS 0x00000003 +#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x400f701c +#define CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET 0x00000000 +#define CYFLD_UDB_UDBIF_EN_HFCLK__SIZE 0x00000001 +#define CYREG_UDB_INT_CFG 0x400f8000 +#define CYFLD_UDB_INT_MODE_CFG__OFFSET 0x00000000 +#define CYFLD_UDB_INT_MODE_CFG__SIZE 0x00000020 +#define CYVAL_UDB_INT_MODE_CFG_LEVEL 0x00000000 +#define CYVAL_UDB_INT_MODE_CFG_PULSE 0x00000001 +#define CYDEV_CTBM_BASE 0x40100000 +#define CYDEV_CTBM_SIZE 0x00010000 +#define CYREG_CTBM_CTB_CTRL 0x40100000 +#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001f +#define CYFLD_CTBM_ENABLED__SIZE 0x00000001 +#define CYREG_CTBM_OA_RES0_CTRL 0x40100004 +#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002 +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002 +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004 +#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005 +#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006 +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008 +#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002 +#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000 +#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001 +#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002 +#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003 +#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000b +#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001 +#define CYREG_CTBM_OA_RES1_CTRL 0x40100008 +#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002 +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002 +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004 +#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005 +#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006 +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008 +#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002 +#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000 +#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001 +#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002 +#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003 +#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000b +#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001 +#define CYREG_CTBM_COMP_STAT 0x4010000c +#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010 +#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001 +#define CYREG_CTBM_INTR 0x40100020 +#define CYFLD_CTBM_COMP0__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1__SIZE 0x00000001 +#define CYREG_CTBM_INTR_SET 0x40100024 +#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001 +#define CYREG_CTBM_INTR_MASK 0x40100028 +#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001 +#define CYREG_CTBM_INTR_MASKED 0x4010002c +#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001 +#define CYREG_CTBM_DFT_CTRL 0x40100030 +#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003 +#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001f +#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001 +#define CYREG_CTBM_OA0_SW 0x40100080 +#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001 +#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002 +#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001 +#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003 +#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001 +#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008 +#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001 +#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000e +#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001 +#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012 +#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001 +#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015 +#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001 +#define CYREG_CTBM_OA0_SW_CLEAR 0x40100084 +#define CYREG_CTBM_OA1_SW 0x40100088 +#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001 +#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001 +#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001 +#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004 +#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001 +#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008 +#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001 +#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000e +#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012 +#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013 +#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015 +#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001 +#define CYREG_CTBM_OA1_SW_CLEAR 0x4010008c +#define CYREG_CTBM_CTB_SW_HW_CTRL 0x401000c0 +#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002 +#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001 +#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003 +#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001 +#define CYREG_CTBM_CTB_SW_STATUS 0x401000c4 +#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001c +#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001d +#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001e +#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001 +#define CYREG_CTBM_OA0_OFFSET_TRIM 0x40100f00 +#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM 0x40100f04 +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA0_COMP_TRIM 0x40100f08 +#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002 +#define CYREG_CTBM_OA1_OFFSET_TRIM 0x40100f0c +#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM 0x40100f10 +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM_OA1_COMP_TRIM 0x40100f14 +#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002 +#define CYDEV_SAR_BASE 0x401a0000 +#define CYDEV_SAR_SIZE 0x00010000 +#define CYREG_SAR_CTRL 0x401a0000 +#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004 +#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003 +#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000 +#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001 +#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002 +#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003 +#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004 +#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005 +#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006 +#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007 +#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007 +#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001 +#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009 +#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003 +#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000 +#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001 +#define CYVAL_SAR_NEG_SEL_P1 0x00000002 +#define CYVAL_SAR_NEG_SEL_P3 0x00000003 +#define CYVAL_SAR_NEG_SEL_P5 0x00000004 +#define CYVAL_SAR_NEG_SEL_P7 0x00000005 +#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006 +#define CYVAL_SAR_NEG_SEL_VREF 0x00000007 +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000d +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001 +#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000e +#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002 +#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000 +#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001 +#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002 +#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003 +#define CYFLD_SAR_SPARE__OFFSET 0x00000010 +#define CYFLD_SAR_SPARE__SIZE 0x00000004 +#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018 +#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002 +#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000 +#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001 +#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002 +#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003 +#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001c +#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001 +#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001d +#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001 +#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001e +#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001 +#define CYFLD_SAR_ENABLED__OFFSET 0x0000001f +#define CYFLD_SAR_ENABLED__SIZE 0x00000001 +#define CYREG_SAR_SAMPLE_CTRL 0x401a0004 +#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000 +#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000 +#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001 +#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001 +#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001 +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002 +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001 +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000 +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001 +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003 +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001 +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000 +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001 +#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004 +#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003 +#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007 +#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001 +#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010 +#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001 +#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011 +#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001 +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012 +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001 +#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013 +#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001 +#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001f +#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001 +#define CYREG_SAR_SAMPLE_TIME01 0x401a0010 +#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000 +#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000a +#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010 +#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000a +#define CYREG_SAR_SAMPLE_TIME23 0x401a0014 +#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000 +#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000a +#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010 +#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000a +#define CYREG_SAR_RANGE_THRES 0x401a0018 +#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010 +#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010 +#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010 +#define CYREG_SAR_RANGE_COND 0x401a001c +#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001e +#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002 +#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000 +#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001 +#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002 +#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003 +#define CYREG_SAR_CHAN_EN 0x401a0020 +#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010 +#define CYREG_SAR_START_CTRL 0x401a0024 +#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000 +#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001 +#define CYREG_SAR_DFT_CTRL 0x401a0030 +#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000 +#define CYFLD_SAR_DLY_INC__SIZE 0x00000001 +#define CYFLD_SAR_HIZ__OFFSET 0x00000001 +#define CYFLD_SAR_HIZ__SIZE 0x00000001 +#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010 +#define CYFLD_SAR_DFT_INC__SIZE 0x00000004 +#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014 +#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003 +#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018 +#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004 +#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001c +#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001 +#define CYFLD_SAR_DCEN__OFFSET 0x0000001d +#define CYFLD_SAR_DCEN__SIZE 0x00000001 +#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001f +#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001 +#define CYREG_SAR_CHAN_CONFIG00 0x401a0080 +#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000 +#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003 +#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004 +#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003 +#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000 +#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001 +#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002 +#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003 +#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004 +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT 0x00000006 +#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007 +#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008 +#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001 +#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009 +#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_RESOLUTION_12B 0x00000000 +#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001 +#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000a +#define CYFLD_SAR_AVG_EN__SIZE 0x00000001 +#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000c +#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002 +#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001f +#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001 +#define CYREG_SAR_CHAN_CONFIG01 0x401a0084 +#define CYREG_SAR_CHAN_CONFIG02 0x401a0088 +#define CYREG_SAR_CHAN_CONFIG03 0x401a008c +#define CYREG_SAR_CHAN_CONFIG04 0x401a0090 +#define CYREG_SAR_CHAN_CONFIG05 0x401a0094 +#define CYREG_SAR_CHAN_CONFIG06 0x401a0098 +#define CYREG_SAR_CHAN_CONFIG07 0x401a009c +#define CYREG_SAR_CHAN_WORK00 0x401a0100 +#define CYFLD_SAR_WORK__OFFSET 0x00000000 +#define CYFLD_SAR_WORK__SIZE 0x00000010 +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001 +#define CYREG_SAR_CHAN_WORK01 0x401a0104 +#define CYREG_SAR_CHAN_WORK02 0x401a0108 +#define CYREG_SAR_CHAN_WORK03 0x401a010c +#define CYREG_SAR_CHAN_WORK04 0x401a0110 +#define CYREG_SAR_CHAN_WORK05 0x401a0114 +#define CYREG_SAR_CHAN_WORK06 0x401a0118 +#define CYREG_SAR_CHAN_WORK07 0x401a011c +#define CYREG_SAR_CHAN_RESULT00 0x401a0180 +#define CYFLD_SAR_RESULT__OFFSET 0x00000000 +#define CYFLD_SAR_RESULT__SIZE 0x00000010 +#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001d +#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001e +#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001 +#define CYREG_SAR_CHAN_RESULT01 0x401a0184 +#define CYREG_SAR_CHAN_RESULT02 0x401a0188 +#define CYREG_SAR_CHAN_RESULT03 0x401a018c +#define CYREG_SAR_CHAN_RESULT04 0x401a0190 +#define CYREG_SAR_CHAN_RESULT05 0x401a0194 +#define CYREG_SAR_CHAN_RESULT06 0x401a0198 +#define CYREG_SAR_CHAN_RESULT07 0x401a019c +#define CYREG_SAR_CHAN_WORK_VALID 0x401a0200 +#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010 +#define CYREG_SAR_CHAN_RESULT_VALID 0x401a0204 +#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010 +#define CYREG_SAR_STATUS 0x401a0208 +#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000 +#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005 +#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001e +#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001 +#define CYFLD_SAR_BUSY__OFFSET 0x0000001f +#define CYFLD_SAR_BUSY__SIZE 0x00000001 +#define CYREG_SAR_AVG_STAT 0x401a020c +#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000 +#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014 +#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018 +#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008 +#define CYREG_SAR_INTR 0x401a0210 +#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001 +#define CYREG_SAR_INTR_SET 0x401a0214 +#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_SET__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001 +#define CYREG_SAR_INTR_MASK 0x401a0218 +#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001 +#define CYREG_SAR_INTR_MASKED 0x401a021c +#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001 +#define CYREG_SAR_SATURATE_INTR 0x401a0220 +#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_SET 0x401a0224 +#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_MASK 0x401a0228 +#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_MASKED 0x401a022c +#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR 0x401a0230 +#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_SET 0x401a0234 +#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_MASK 0x401a0238 +#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_MASKED 0x401a023c +#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010 +#define CYREG_SAR_INTR_CAUSE 0x401a0240 +#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001e +#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001 +#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001f +#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001 +#define CYREG_SAR_INJ_CHAN_CONFIG 0x401a0280 +#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000 +#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003 +#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003 +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004 +#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006 +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007 +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008 +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009 +#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000 +#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001 +#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000a +#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000c +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002 +#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001e +#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001 +#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001f +#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001 +#define CYREG_SAR_INJ_RESULT 0x401a0290 +#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000 +#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010 +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001c +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001d +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001e +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH0 0x401a0300 +#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004 +#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005 +#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006 +#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007 +#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008 +#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009 +#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000a +#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000b +#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000c +#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000d +#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000e +#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000f +#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010 +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011 +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016 +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017 +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018 +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019 +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001a +#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001b +#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001c +#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001d +#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x401a0304 +#define CYREG_SAR_MUX_SWITCH1 0x401a0308 +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x401a030c +#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x401a0340 +#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004 +#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005 +#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006 +#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007 +#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010 +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011 +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_STATUS 0x401a0348 +#define CYREG_SAR_PUMP_CTRL 0x401a0380 +#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000 +#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001 +#define CYREG_SAR_ANA_TRIM 0x401a0f00 +#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000 +#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003 +#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003 +#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001 +#define CYREG_SAR_WOUNDING 0x401a0f04 +#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000 +#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002 +#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000 +#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001 +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002 +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003 +#define CYDEV_CM0_BASE 0xe0000000 +#define CYDEV_CM0_SIZE 0x00100000 +#define CYREG_CM0_DWT_PID4 0xe0001fd0 +#define CYFLD_CM0_VALUE__OFFSET 0x00000000 +#define CYFLD_CM0_VALUE__SIZE 0x00000020 +#define CYREG_CM0_DWT_PID0 0xe0001fe0 +#define CYREG_CM0_DWT_PID1 0xe0001fe4 +#define CYREG_CM0_DWT_PID2 0xe0001fe8 +#define CYREG_CM0_DWT_PID3 0xe0001fec +#define CYREG_CM0_DWT_CID0 0xe0001ff0 +#define CYREG_CM0_DWT_CID1 0xe0001ff4 +#define CYREG_CM0_DWT_CID2 0xe0001ff8 +#define CYREG_CM0_DWT_CID3 0xe0001ffc +#define CYREG_CM0_BP_PID4 0xe0002fd0 +#define CYREG_CM0_BP_PID0 0xe0002fe0 +#define CYREG_CM0_BP_PID1 0xe0002fe4 +#define CYREG_CM0_BP_PID2 0xe0002fe8 +#define CYREG_CM0_BP_PID3 0xe0002fec +#define CYREG_CM0_BP_CID0 0xe0002ff0 +#define CYREG_CM0_BP_CID1 0xe0002ff4 +#define CYREG_CM0_BP_CID2 0xe0002ff8 +#define CYREG_CM0_BP_CID3 0xe0002ffc +#define CYREG_CM0_SYST_CSR 0xe000e010 +#define CYFLD_CM0_ENABLE__OFFSET 0x00000000 +#define CYFLD_CM0_ENABLE__SIZE 0x00000001 +#define CYFLD_CM0_TICKINT__OFFSET 0x00000001 +#define CYFLD_CM0_TICKINT__SIZE 0x00000001 +#define CYFLD_CM0_CLKSOURCE__OFFSET 0x00000002 +#define CYFLD_CM0_CLKSOURCE__SIZE 0x00000001 +#define CYFLD_CM0_COUNTFLAG__OFFSET 0x00000010 +#define CYFLD_CM0_COUNTFLAG__SIZE 0x00000001 +#define CYREG_CM0_SYST_RVR 0xe000e014 +#define CYFLD_CM0_RELOAD__OFFSET 0x00000000 +#define CYFLD_CM0_RELOAD__SIZE 0x00000018 +#define CYREG_CM0_SYST_CVR 0xe000e018 +#define CYFLD_CM0_CURRENT__OFFSET 0x00000000 +#define CYFLD_CM0_CURRENT__SIZE 0x00000018 +#define CYREG_CM0_SYST_CALIB 0xe000e01c +#define CYFLD_CM0_TENMS__OFFSET 0x00000000 +#define CYFLD_CM0_TENMS__SIZE 0x00000018 +#define CYFLD_CM0_SKEW__OFFSET 0x0000001e +#define CYFLD_CM0_SKEW__SIZE 0x00000001 +#define CYFLD_CM0_NOREF__OFFSET 0x0000001f +#define CYFLD_CM0_NOREF__SIZE 0x00000001 +#define CYREG_CM0_ISER 0xe000e100 +#define CYFLD_CM0_SETENA__OFFSET 0x00000000 +#define CYFLD_CM0_SETENA__SIZE 0x00000020 +#define CYREG_CM0_ICER 0xe000e180 +#define CYFLD_CM0_CLRENA__OFFSET 0x00000000 +#define CYFLD_CM0_CLRENA__SIZE 0x00000020 +#define CYREG_CM0_ISPR 0xe000e200 +#define CYFLD_CM0_SETPEND__OFFSET 0x00000000 +#define CYFLD_CM0_SETPEND__SIZE 0x00000020 +#define CYREG_CM0_ICPR 0xe000e280 +#define CYFLD_CM0_CLRPEND__OFFSET 0x00000000 +#define CYFLD_CM0_CLRPEND__SIZE 0x00000020 +#define CYREG_CM0_IPR0 0xe000e400 +#define CYFLD_CM0_PRI_N0__OFFSET 0x00000006 +#define CYFLD_CM0_PRI_N0__SIZE 0x00000002 +#define CYFLD_CM0_PRI_N1__OFFSET 0x0000000e +#define CYFLD_CM0_PRI_N1__SIZE 0x00000002 +#define CYFLD_CM0_PRI_N2__OFFSET 0x00000016 +#define CYFLD_CM0_PRI_N2__SIZE 0x00000002 +#define CYFLD_CM0_PRI_N3__OFFSET 0x0000001e +#define CYFLD_CM0_PRI_N3__SIZE 0x00000002 +#define CYREG_CM0_IPR1 0xe000e404 +#define CYREG_CM0_IPR2 0xe000e408 +#define CYREG_CM0_IPR3 0xe000e40c +#define CYREG_CM0_IPR4 0xe000e410 +#define CYREG_CM0_IPR5 0xe000e414 +#define CYREG_CM0_IPR6 0xe000e418 +#define CYREG_CM0_IPR7 0xe000e41c +#define CYREG_CM0_CPUID 0xe000ed00 +#define CYFLD_CM0_REVISION__OFFSET 0x00000000 +#define CYFLD_CM0_REVISION__SIZE 0x00000004 +#define CYFLD_CM0_PARTNO__OFFSET 0x00000004 +#define CYFLD_CM0_PARTNO__SIZE 0x0000000c +#define CYFLD_CM0_CONSTANT__OFFSET 0x00000010 +#define CYFLD_CM0_CONSTANT__SIZE 0x00000004 +#define CYFLD_CM0_VARIANT__OFFSET 0x00000014 +#define CYFLD_CM0_VARIANT__SIZE 0x00000004 +#define CYFLD_CM0_IMPLEMENTER__OFFSET 0x00000018 +#define CYFLD_CM0_IMPLEMENTER__SIZE 0x00000008 +#define CYREG_CM0_ICSR 0xe000ed04 +#define CYFLD_CM0_VECTACTIVE__OFFSET 0x00000000 +#define CYFLD_CM0_VECTACTIVE__SIZE 0x00000009 +#define CYFLD_CM0_VECTPENDING__OFFSET 0x0000000c +#define CYFLD_CM0_VECTPENDING__SIZE 0x00000009 +#define CYFLD_CM0_ISRPENDING__OFFSET 0x00000016 +#define CYFLD_CM0_ISRPENDING__SIZE 0x00000001 +#define CYFLD_CM0_ISRPREEMPT__OFFSET 0x00000017 +#define CYFLD_CM0_ISRPREEMPT__SIZE 0x00000001 +#define CYFLD_CM0_PENDSTCLR__OFFSET 0x00000019 +#define CYFLD_CM0_PENDSTCLR__SIZE 0x00000001 +#define CYFLD_CM0_PENDSTSETb__OFFSET 0x0000001a +#define CYFLD_CM0_PENDSTSETb__SIZE 0x00000001 +#define CYFLD_CM0_PENDSVCLR__OFFSET 0x0000001b +#define CYFLD_CM0_PENDSVCLR__SIZE 0x00000001 +#define CYFLD_CM0_PENDSVSET__OFFSET 0x0000001c +#define CYFLD_CM0_PENDSVSET__SIZE 0x00000001 +#define CYFLD_CM0_NMIPENDSET__OFFSET 0x0000001f +#define CYFLD_CM0_NMIPENDSET__SIZE 0x00000001 +#define CYREG_CM0_AIRCR 0xe000ed0c +#define CYFLD_CM0_VECTCLRACTIVE__OFFSET 0x00000001 +#define CYFLD_CM0_VECTCLRACTIVE__SIZE 0x00000001 +#define CYFLD_CM0_SYSRESETREQ__OFFSET 0x00000002 +#define CYFLD_CM0_SYSRESETREQ__SIZE 0x00000001 +#define CYFLD_CM0_ENDIANNESS__OFFSET 0x0000000f +#define CYFLD_CM0_ENDIANNESS__SIZE 0x00000001 +#define CYFLD_CM0_VECTKEY__OFFSET 0x00000010 +#define CYFLD_CM0_VECTKEY__SIZE 0x00000010 +#define CYREG_CM0_SCR 0xe000ed10 +#define CYFLD_CM0_SLEEPONEXIT__OFFSET 0x00000001 +#define CYFLD_CM0_SLEEPONEXIT__SIZE 0x00000001 +#define CYFLD_CM0_SLEEPDEEP__OFFSET 0x00000002 +#define CYFLD_CM0_SLEEPDEEP__SIZE 0x00000001 +#define CYFLD_CM0_SEVONPEND__OFFSET 0x00000004 +#define CYFLD_CM0_SEVONPEND__SIZE 0x00000001 +#define CYREG_CM0_CCR 0xe000ed14 +#define CYFLD_CM0_UNALIGN_TRP__OFFSET 0x00000003 +#define CYFLD_CM0_UNALIGN_TRP__SIZE 0x00000001 +#define CYFLD_CM0_STKALIGN__OFFSET 0x00000009 +#define CYFLD_CM0_STKALIGN__SIZE 0x00000001 +#define CYREG_CM0_SHPR2 0xe000ed1c +#define CYFLD_CM0_PRI_11__OFFSET 0x0000001e +#define CYFLD_CM0_PRI_11__SIZE 0x00000002 +#define CYREG_CM0_SHPR3 0xe000ed20 +#define CYFLD_CM0_PRI_14__OFFSET 0x00000016 +#define CYFLD_CM0_PRI_14__SIZE 0x00000002 +#define CYFLD_CM0_PRI_15__OFFSET 0x0000001e +#define CYFLD_CM0_PRI_15__SIZE 0x00000002 +#define CYREG_CM0_SHCSR 0xe000ed24 +#define CYFLD_CM0_SVCALLPENDED__OFFSET 0x0000000f +#define CYFLD_CM0_SVCALLPENDED__SIZE 0x00000001 +#define CYREG_CM0_SCS_PID4 0xe000efd0 +#define CYREG_CM0_SCS_PID0 0xe000efe0 +#define CYREG_CM0_SCS_PID1 0xe000efe4 +#define CYREG_CM0_SCS_PID2 0xe000efe8 +#define CYREG_CM0_SCS_PID3 0xe000efec +#define CYREG_CM0_SCS_CID0 0xe000eff0 +#define CYREG_CM0_SCS_CID1 0xe000eff4 +#define CYREG_CM0_SCS_CID2 0xe000eff8 +#define CYREG_CM0_SCS_CID3 0xe000effc +#define CYREG_CM0_ROM_SCS 0xe00ff000 +#define CYREG_CM0_ROM_DWT 0xe00ff004 +#define CYREG_CM0_ROM_BPU 0xe00ff008 +#define CYREG_CM0_ROM_END 0xe00ff00c +#define CYREG_CM0_ROM_CSMT 0xe00fffcc +#define CYREG_CM0_ROM_PID4 0xe00fffd0 +#define CYREG_CM0_ROM_PID0 0xe00fffe0 +#define CYREG_CM0_ROM_PID1 0xe00fffe4 +#define CYREG_CM0_ROM_PID2 0xe00fffe8 +#define CYREG_CM0_ROM_PID3 0xe00fffec +#define CYREG_CM0_ROM_CID0 0xe00ffff0 +#define CYREG_CM0_ROM_CID1 0xe00ffff4 +#define CYREG_CM0_ROM_CID2 0xe00ffff8 +#define CYREG_CM0_ROM_CID3 0xe00ffffc +#define CYDEV_CoreSightTable_BASE 0xf0000000 +#define CYDEV_CoreSightTable_SIZE 0x00001000 +#define CYREG_CoreSightTable_DATA_MBASE 0xf0000000 +#define CYREG_CoreSightTable_DATA_MSIZE 0x00001000 +#define CYDEV_FLS_SECTOR_SIZE 0x00008000 +#define CYDEV_FLS_ROW_SIZE 0x00000080 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevicerv_trm.inc b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevicerv_trm.inc new file mode 100644 index 0000000..3431da4 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydevicerv_trm.inc @@ -0,0 +1,19450 @@ +; +; File Name: cydevicerv_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SFLASH_BASE +CYDEV_SFLASH_BASE EQU 0x0ffff000 + ENDIF + IF :LNOT::DEF:CYDEV_SFLASH_SIZE +CYDEV_SFLASH_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW00 +CYREG_SFLASH_PROT_ROW00 EQU 0x0ffff000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA8__OFFSET +CYFLD_SFLASH_DATA8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA8__SIZE +CYFLD_SFLASH_DATA8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW01 +CYREG_SFLASH_PROT_ROW01 EQU 0x0ffff001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW02 +CYREG_SFLASH_PROT_ROW02 EQU 0x0ffff002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW03 +CYREG_SFLASH_PROT_ROW03 EQU 0x0ffff003 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW04 +CYREG_SFLASH_PROT_ROW04 EQU 0x0ffff004 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW05 +CYREG_SFLASH_PROT_ROW05 EQU 0x0ffff005 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW06 +CYREG_SFLASH_PROT_ROW06 EQU 0x0ffff006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW07 +CYREG_SFLASH_PROT_ROW07 EQU 0x0ffff007 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW08 +CYREG_SFLASH_PROT_ROW08 EQU 0x0ffff008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW09 +CYREG_SFLASH_PROT_ROW09 EQU 0x0ffff009 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW10 +CYREG_SFLASH_PROT_ROW10 EQU 0x0ffff00a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW11 +CYREG_SFLASH_PROT_ROW11 EQU 0x0ffff00b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW12 +CYREG_SFLASH_PROT_ROW12 EQU 0x0ffff00c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW13 +CYREG_SFLASH_PROT_ROW13 EQU 0x0ffff00d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW14 +CYREG_SFLASH_PROT_ROW14 EQU 0x0ffff00e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW15 +CYREG_SFLASH_PROT_ROW15 EQU 0x0ffff00f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW16 +CYREG_SFLASH_PROT_ROW16 EQU 0x0ffff010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW17 +CYREG_SFLASH_PROT_ROW17 EQU 0x0ffff011 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW18 +CYREG_SFLASH_PROT_ROW18 EQU 0x0ffff012 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW19 +CYREG_SFLASH_PROT_ROW19 EQU 0x0ffff013 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW20 +CYREG_SFLASH_PROT_ROW20 EQU 0x0ffff014 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW21 +CYREG_SFLASH_PROT_ROW21 EQU 0x0ffff015 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW22 +CYREG_SFLASH_PROT_ROW22 EQU 0x0ffff016 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW23 +CYREG_SFLASH_PROT_ROW23 EQU 0x0ffff017 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW24 +CYREG_SFLASH_PROT_ROW24 EQU 0x0ffff018 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW25 +CYREG_SFLASH_PROT_ROW25 EQU 0x0ffff019 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW26 +CYREG_SFLASH_PROT_ROW26 EQU 0x0ffff01a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW27 +CYREG_SFLASH_PROT_ROW27 EQU 0x0ffff01b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW28 +CYREG_SFLASH_PROT_ROW28 EQU 0x0ffff01c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW29 +CYREG_SFLASH_PROT_ROW29 EQU 0x0ffff01d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW30 +CYREG_SFLASH_PROT_ROW30 EQU 0x0ffff01e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW31 +CYREG_SFLASH_PROT_ROW31 EQU 0x0ffff01f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW32 +CYREG_SFLASH_PROT_ROW32 EQU 0x0ffff020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW33 +CYREG_SFLASH_PROT_ROW33 EQU 0x0ffff021 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW34 +CYREG_SFLASH_PROT_ROW34 EQU 0x0ffff022 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW35 +CYREG_SFLASH_PROT_ROW35 EQU 0x0ffff023 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW36 +CYREG_SFLASH_PROT_ROW36 EQU 0x0ffff024 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW37 +CYREG_SFLASH_PROT_ROW37 EQU 0x0ffff025 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW38 +CYREG_SFLASH_PROT_ROW38 EQU 0x0ffff026 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW39 +CYREG_SFLASH_PROT_ROW39 EQU 0x0ffff027 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW40 +CYREG_SFLASH_PROT_ROW40 EQU 0x0ffff028 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW41 +CYREG_SFLASH_PROT_ROW41 EQU 0x0ffff029 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW42 +CYREG_SFLASH_PROT_ROW42 EQU 0x0ffff02a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW43 +CYREG_SFLASH_PROT_ROW43 EQU 0x0ffff02b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW44 +CYREG_SFLASH_PROT_ROW44 EQU 0x0ffff02c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW45 +CYREG_SFLASH_PROT_ROW45 EQU 0x0ffff02d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW46 +CYREG_SFLASH_PROT_ROW46 EQU 0x0ffff02e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW47 +CYREG_SFLASH_PROT_ROW47 EQU 0x0ffff02f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW48 +CYREG_SFLASH_PROT_ROW48 EQU 0x0ffff030 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW49 +CYREG_SFLASH_PROT_ROW49 EQU 0x0ffff031 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW50 +CYREG_SFLASH_PROT_ROW50 EQU 0x0ffff032 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW51 +CYREG_SFLASH_PROT_ROW51 EQU 0x0ffff033 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW52 +CYREG_SFLASH_PROT_ROW52 EQU 0x0ffff034 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW53 +CYREG_SFLASH_PROT_ROW53 EQU 0x0ffff035 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW54 +CYREG_SFLASH_PROT_ROW54 EQU 0x0ffff036 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW55 +CYREG_SFLASH_PROT_ROW55 EQU 0x0ffff037 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW56 +CYREG_SFLASH_PROT_ROW56 EQU 0x0ffff038 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW57 +CYREG_SFLASH_PROT_ROW57 EQU 0x0ffff039 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW58 +CYREG_SFLASH_PROT_ROW58 EQU 0x0ffff03a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW59 +CYREG_SFLASH_PROT_ROW59 EQU 0x0ffff03b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW60 +CYREG_SFLASH_PROT_ROW60 EQU 0x0ffff03c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW61 +CYREG_SFLASH_PROT_ROW61 EQU 0x0ffff03d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW62 +CYREG_SFLASH_PROT_ROW62 EQU 0x0ffff03e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW63 +CYREG_SFLASH_PROT_ROW63 EQU 0x0ffff03f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_PROTECTION +CYREG_SFLASH_PROT_PROTECTION EQU 0x0ffff07f + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PROT_LEVEL__OFFSET +CYFLD_SFLASH_PROT_LEVEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PROT_LEVEL__SIZE +CYFLD_SFLASH_PROT_LEVEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_VIRGIN +CYVAL_SFLASH_PROT_LEVEL_VIRGIN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_OPEN +CYVAL_SFLASH_PROT_LEVEL_OPEN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_PROTECTED +CYVAL_SFLASH_PROT_LEVEL_PROTECTED EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_KILL +CYVAL_SFLASH_PROT_LEVEL_KILL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B000 +CYREG_SFLASH_AV_PAIRS_8B000 EQU 0x0ffff080 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B001 +CYREG_SFLASH_AV_PAIRS_8B001 EQU 0x0ffff081 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B002 +CYREG_SFLASH_AV_PAIRS_8B002 EQU 0x0ffff082 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B003 +CYREG_SFLASH_AV_PAIRS_8B003 EQU 0x0ffff083 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B004 +CYREG_SFLASH_AV_PAIRS_8B004 EQU 0x0ffff084 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B005 +CYREG_SFLASH_AV_PAIRS_8B005 EQU 0x0ffff085 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B006 +CYREG_SFLASH_AV_PAIRS_8B006 EQU 0x0ffff086 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B007 +CYREG_SFLASH_AV_PAIRS_8B007 EQU 0x0ffff087 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B008 +CYREG_SFLASH_AV_PAIRS_8B008 EQU 0x0ffff088 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B009 +CYREG_SFLASH_AV_PAIRS_8B009 EQU 0x0ffff089 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B010 +CYREG_SFLASH_AV_PAIRS_8B010 EQU 0x0ffff08a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B011 +CYREG_SFLASH_AV_PAIRS_8B011 EQU 0x0ffff08b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B012 +CYREG_SFLASH_AV_PAIRS_8B012 EQU 0x0ffff08c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B013 +CYREG_SFLASH_AV_PAIRS_8B013 EQU 0x0ffff08d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B014 +CYREG_SFLASH_AV_PAIRS_8B014 EQU 0x0ffff08e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B015 +CYREG_SFLASH_AV_PAIRS_8B015 EQU 0x0ffff08f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B016 +CYREG_SFLASH_AV_PAIRS_8B016 EQU 0x0ffff090 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B017 +CYREG_SFLASH_AV_PAIRS_8B017 EQU 0x0ffff091 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B018 +CYREG_SFLASH_AV_PAIRS_8B018 EQU 0x0ffff092 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B019 +CYREG_SFLASH_AV_PAIRS_8B019 EQU 0x0ffff093 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B020 +CYREG_SFLASH_AV_PAIRS_8B020 EQU 0x0ffff094 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B021 +CYREG_SFLASH_AV_PAIRS_8B021 EQU 0x0ffff095 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B022 +CYREG_SFLASH_AV_PAIRS_8B022 EQU 0x0ffff096 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B023 +CYREG_SFLASH_AV_PAIRS_8B023 EQU 0x0ffff097 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B024 +CYREG_SFLASH_AV_PAIRS_8B024 EQU 0x0ffff098 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B025 +CYREG_SFLASH_AV_PAIRS_8B025 EQU 0x0ffff099 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B026 +CYREG_SFLASH_AV_PAIRS_8B026 EQU 0x0ffff09a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B027 +CYREG_SFLASH_AV_PAIRS_8B027 EQU 0x0ffff09b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B028 +CYREG_SFLASH_AV_PAIRS_8B028 EQU 0x0ffff09c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B029 +CYREG_SFLASH_AV_PAIRS_8B029 EQU 0x0ffff09d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B030 +CYREG_SFLASH_AV_PAIRS_8B030 EQU 0x0ffff09e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B031 +CYREG_SFLASH_AV_PAIRS_8B031 EQU 0x0ffff09f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B032 +CYREG_SFLASH_AV_PAIRS_8B032 EQU 0x0ffff0a0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B033 +CYREG_SFLASH_AV_PAIRS_8B033 EQU 0x0ffff0a1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B034 +CYREG_SFLASH_AV_PAIRS_8B034 EQU 0x0ffff0a2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B035 +CYREG_SFLASH_AV_PAIRS_8B035 EQU 0x0ffff0a3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B036 +CYREG_SFLASH_AV_PAIRS_8B036 EQU 0x0ffff0a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B037 +CYREG_SFLASH_AV_PAIRS_8B037 EQU 0x0ffff0a5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B038 +CYREG_SFLASH_AV_PAIRS_8B038 EQU 0x0ffff0a6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B039 +CYREG_SFLASH_AV_PAIRS_8B039 EQU 0x0ffff0a7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B040 +CYREG_SFLASH_AV_PAIRS_8B040 EQU 0x0ffff0a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B041 +CYREG_SFLASH_AV_PAIRS_8B041 EQU 0x0ffff0a9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B042 +CYREG_SFLASH_AV_PAIRS_8B042 EQU 0x0ffff0aa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B043 +CYREG_SFLASH_AV_PAIRS_8B043 EQU 0x0ffff0ab + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B044 +CYREG_SFLASH_AV_PAIRS_8B044 EQU 0x0ffff0ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B045 +CYREG_SFLASH_AV_PAIRS_8B045 EQU 0x0ffff0ad + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B046 +CYREG_SFLASH_AV_PAIRS_8B046 EQU 0x0ffff0ae + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B047 +CYREG_SFLASH_AV_PAIRS_8B047 EQU 0x0ffff0af + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B048 +CYREG_SFLASH_AV_PAIRS_8B048 EQU 0x0ffff0b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B049 +CYREG_SFLASH_AV_PAIRS_8B049 EQU 0x0ffff0b1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B050 +CYREG_SFLASH_AV_PAIRS_8B050 EQU 0x0ffff0b2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B051 +CYREG_SFLASH_AV_PAIRS_8B051 EQU 0x0ffff0b3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B052 +CYREG_SFLASH_AV_PAIRS_8B052 EQU 0x0ffff0b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B053 +CYREG_SFLASH_AV_PAIRS_8B053 EQU 0x0ffff0b5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B054 +CYREG_SFLASH_AV_PAIRS_8B054 EQU 0x0ffff0b6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B055 +CYREG_SFLASH_AV_PAIRS_8B055 EQU 0x0ffff0b7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B056 +CYREG_SFLASH_AV_PAIRS_8B056 EQU 0x0ffff0b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B057 +CYREG_SFLASH_AV_PAIRS_8B057 EQU 0x0ffff0b9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B058 +CYREG_SFLASH_AV_PAIRS_8B058 EQU 0x0ffff0ba + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B059 +CYREG_SFLASH_AV_PAIRS_8B059 EQU 0x0ffff0bb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B060 +CYREG_SFLASH_AV_PAIRS_8B060 EQU 0x0ffff0bc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B061 +CYREG_SFLASH_AV_PAIRS_8B061 EQU 0x0ffff0bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B062 +CYREG_SFLASH_AV_PAIRS_8B062 EQU 0x0ffff0be + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B063 +CYREG_SFLASH_AV_PAIRS_8B063 EQU 0x0ffff0bf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B064 +CYREG_SFLASH_AV_PAIRS_8B064 EQU 0x0ffff0c0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B065 +CYREG_SFLASH_AV_PAIRS_8B065 EQU 0x0ffff0c1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B066 +CYREG_SFLASH_AV_PAIRS_8B066 EQU 0x0ffff0c2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B067 +CYREG_SFLASH_AV_PAIRS_8B067 EQU 0x0ffff0c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B068 +CYREG_SFLASH_AV_PAIRS_8B068 EQU 0x0ffff0c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B069 +CYREG_SFLASH_AV_PAIRS_8B069 EQU 0x0ffff0c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B070 +CYREG_SFLASH_AV_PAIRS_8B070 EQU 0x0ffff0c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B071 +CYREG_SFLASH_AV_PAIRS_8B071 EQU 0x0ffff0c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B072 +CYREG_SFLASH_AV_PAIRS_8B072 EQU 0x0ffff0c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B073 +CYREG_SFLASH_AV_PAIRS_8B073 EQU 0x0ffff0c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B074 +CYREG_SFLASH_AV_PAIRS_8B074 EQU 0x0ffff0ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B075 +CYREG_SFLASH_AV_PAIRS_8B075 EQU 0x0ffff0cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B076 +CYREG_SFLASH_AV_PAIRS_8B076 EQU 0x0ffff0cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B077 +CYREG_SFLASH_AV_PAIRS_8B077 EQU 0x0ffff0cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B078 +CYREG_SFLASH_AV_PAIRS_8B078 EQU 0x0ffff0ce + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B079 +CYREG_SFLASH_AV_PAIRS_8B079 EQU 0x0ffff0cf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B080 +CYREG_SFLASH_AV_PAIRS_8B080 EQU 0x0ffff0d0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B081 +CYREG_SFLASH_AV_PAIRS_8B081 EQU 0x0ffff0d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B082 +CYREG_SFLASH_AV_PAIRS_8B082 EQU 0x0ffff0d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B083 +CYREG_SFLASH_AV_PAIRS_8B083 EQU 0x0ffff0d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B084 +CYREG_SFLASH_AV_PAIRS_8B084 EQU 0x0ffff0d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B085 +CYREG_SFLASH_AV_PAIRS_8B085 EQU 0x0ffff0d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B086 +CYREG_SFLASH_AV_PAIRS_8B086 EQU 0x0ffff0d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B087 +CYREG_SFLASH_AV_PAIRS_8B087 EQU 0x0ffff0d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B088 +CYREG_SFLASH_AV_PAIRS_8B088 EQU 0x0ffff0d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B089 +CYREG_SFLASH_AV_PAIRS_8B089 EQU 0x0ffff0d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B090 +CYREG_SFLASH_AV_PAIRS_8B090 EQU 0x0ffff0da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B091 +CYREG_SFLASH_AV_PAIRS_8B091 EQU 0x0ffff0db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B092 +CYREG_SFLASH_AV_PAIRS_8B092 EQU 0x0ffff0dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B093 +CYREG_SFLASH_AV_PAIRS_8B093 EQU 0x0ffff0dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B094 +CYREG_SFLASH_AV_PAIRS_8B094 EQU 0x0ffff0de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B095 +CYREG_SFLASH_AV_PAIRS_8B095 EQU 0x0ffff0df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B096 +CYREG_SFLASH_AV_PAIRS_8B096 EQU 0x0ffff0e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B097 +CYREG_SFLASH_AV_PAIRS_8B097 EQU 0x0ffff0e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B098 +CYREG_SFLASH_AV_PAIRS_8B098 EQU 0x0ffff0e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B099 +CYREG_SFLASH_AV_PAIRS_8B099 EQU 0x0ffff0e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B100 +CYREG_SFLASH_AV_PAIRS_8B100 EQU 0x0ffff0e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B101 +CYREG_SFLASH_AV_PAIRS_8B101 EQU 0x0ffff0e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B102 +CYREG_SFLASH_AV_PAIRS_8B102 EQU 0x0ffff0e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B103 +CYREG_SFLASH_AV_PAIRS_8B103 EQU 0x0ffff0e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B104 +CYREG_SFLASH_AV_PAIRS_8B104 EQU 0x0ffff0e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B105 +CYREG_SFLASH_AV_PAIRS_8B105 EQU 0x0ffff0e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B106 +CYREG_SFLASH_AV_PAIRS_8B106 EQU 0x0ffff0ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B107 +CYREG_SFLASH_AV_PAIRS_8B107 EQU 0x0ffff0eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B108 +CYREG_SFLASH_AV_PAIRS_8B108 EQU 0x0ffff0ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B109 +CYREG_SFLASH_AV_PAIRS_8B109 EQU 0x0ffff0ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B110 +CYREG_SFLASH_AV_PAIRS_8B110 EQU 0x0ffff0ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B111 +CYREG_SFLASH_AV_PAIRS_8B111 EQU 0x0ffff0ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B112 +CYREG_SFLASH_AV_PAIRS_8B112 EQU 0x0ffff0f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B113 +CYREG_SFLASH_AV_PAIRS_8B113 EQU 0x0ffff0f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B114 +CYREG_SFLASH_AV_PAIRS_8B114 EQU 0x0ffff0f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B115 +CYREG_SFLASH_AV_PAIRS_8B115 EQU 0x0ffff0f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B116 +CYREG_SFLASH_AV_PAIRS_8B116 EQU 0x0ffff0f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B117 +CYREG_SFLASH_AV_PAIRS_8B117 EQU 0x0ffff0f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B118 +CYREG_SFLASH_AV_PAIRS_8B118 EQU 0x0ffff0f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B119 +CYREG_SFLASH_AV_PAIRS_8B119 EQU 0x0ffff0f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B120 +CYREG_SFLASH_AV_PAIRS_8B120 EQU 0x0ffff0f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B121 +CYREG_SFLASH_AV_PAIRS_8B121 EQU 0x0ffff0f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B122 +CYREG_SFLASH_AV_PAIRS_8B122 EQU 0x0ffff0fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B123 +CYREG_SFLASH_AV_PAIRS_8B123 EQU 0x0ffff0fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B124 +CYREG_SFLASH_AV_PAIRS_8B124 EQU 0x0ffff0fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B125 +CYREG_SFLASH_AV_PAIRS_8B125 EQU 0x0ffff0fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B126 +CYREG_SFLASH_AV_PAIRS_8B126 EQU 0x0ffff0fe + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B127 +CYREG_SFLASH_AV_PAIRS_8B127 EQU 0x0ffff0ff + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B00 +CYREG_SFLASH_AV_PAIRS_32B00 EQU 0x0ffff100 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA32__OFFSET +CYFLD_SFLASH_DATA32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA32__SIZE +CYFLD_SFLASH_DATA32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B01 +CYREG_SFLASH_AV_PAIRS_32B01 EQU 0x0ffff104 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B02 +CYREG_SFLASH_AV_PAIRS_32B02 EQU 0x0ffff108 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B03 +CYREG_SFLASH_AV_PAIRS_32B03 EQU 0x0ffff10c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B04 +CYREG_SFLASH_AV_PAIRS_32B04 EQU 0x0ffff110 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B05 +CYREG_SFLASH_AV_PAIRS_32B05 EQU 0x0ffff114 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B06 +CYREG_SFLASH_AV_PAIRS_32B06 EQU 0x0ffff118 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B07 +CYREG_SFLASH_AV_PAIRS_32B07 EQU 0x0ffff11c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B08 +CYREG_SFLASH_AV_PAIRS_32B08 EQU 0x0ffff120 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B09 +CYREG_SFLASH_AV_PAIRS_32B09 EQU 0x0ffff124 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B10 +CYREG_SFLASH_AV_PAIRS_32B10 EQU 0x0ffff128 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B11 +CYREG_SFLASH_AV_PAIRS_32B11 EQU 0x0ffff12c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B12 +CYREG_SFLASH_AV_PAIRS_32B12 EQU 0x0ffff130 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B13 +CYREG_SFLASH_AV_PAIRS_32B13 EQU 0x0ffff134 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B14 +CYREG_SFLASH_AV_PAIRS_32B14 EQU 0x0ffff138 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B15 +CYREG_SFLASH_AV_PAIRS_32B15 EQU 0x0ffff13c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CPUSS_WOUNDING +CYREG_SFLASH_CPUSS_WOUNDING EQU 0x0ffff140 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SILICON_ID +CYREG_SFLASH_SILICON_ID EQU 0x0ffff144 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ID__OFFSET +CYFLD_SFLASH_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ID__SIZE +CYFLD_SFLASH_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CPUSS_PRIV_RAM +CYREG_SFLASH_CPUSS_PRIV_RAM EQU 0x0ffff148 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CPUSS_PRIV_FLASH +CYREG_SFLASH_CPUSS_PRIV_FLASH EQU 0x0ffff14c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_HIB_KEY_DELAY +CYREG_SFLASH_HIB_KEY_DELAY EQU 0x0ffff150 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET +CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE +CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DPSLP_KEY_DELAY +CYREG_SFLASH_DPSLP_KEY_DELAY EQU 0x0ffff152 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SWD_CONFIG +CYREG_SFLASH_SWD_CONFIG EQU 0x0ffff154 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SWD_SELECT__OFFSET +CYFLD_SFLASH_SWD_SELECT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SWD_SELECT__SIZE +CYFLD_SFLASH_SWD_SELECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SWD_LISTEN +CYREG_SFLASH_SWD_LISTEN EQU 0x0ffff158 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CYCLES__OFFSET +CYFLD_SFLASH_CYCLES__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CYCLES__SIZE +CYFLD_SFLASH_CYCLES__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_FLASH_START +CYREG_SFLASH_FLASH_START EQU 0x0ffff15c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ADDRESS__OFFSET +CYFLD_SFLASH_ADDRESS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ADDRESS__SIZE +CYFLD_SFLASH_ADDRESS__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM1_HVIDAC +CYREG_SFLASH_CSD_TRIM1_HVIDAC EQU 0x0ffff160 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TRIM8__OFFSET +CYFLD_SFLASH_TRIM8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TRIM8__SIZE +CYFLD_SFLASH_TRIM8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM2_HVIDAC +CYREG_SFLASH_CSD_TRIM2_HVIDAC EQU 0x0ffff161 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM1_CSD +CYREG_SFLASH_CSD_TRIM1_CSD EQU 0x0ffff162 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM2_CSD +CYREG_SFLASH_CSD_TRIM2_CSD EQU 0x0ffff163 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_MULTIPLIER +CYREG_SFLASH_SAR_TEMP_MULTIPLIER EQU 0x0ffff164 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET +CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE +CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_OFFSET +CYREG_SFLASH_SAR_TEMP_OFFSET EQU 0x0ffff166 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__OFFSET +CYFLD_SFLASH_TEMP_OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__SIZE +CYFLD_SFLASH_TEMP_OFFSET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SKIP_CHECKSUM +CYREG_SFLASH_SKIP_CHECKSUM EQU 0x0ffff169 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SKIP__OFFSET +CYFLD_SFLASH_SKIP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SKIP__SIZE +CYFLD_SFLASH_SKIP__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY0 +CYREG_SFLASH_PROT_VIRGINKEY0 EQU 0x0ffff170 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_KEY8__OFFSET +CYFLD_SFLASH_KEY8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_KEY8__SIZE +CYFLD_SFLASH_KEY8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY1 +CYREG_SFLASH_PROT_VIRGINKEY1 EQU 0x0ffff171 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY2 +CYREG_SFLASH_PROT_VIRGINKEY2 EQU 0x0ffff172 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY3 +CYREG_SFLASH_PROT_VIRGINKEY3 EQU 0x0ffff173 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY4 +CYREG_SFLASH_PROT_VIRGINKEY4 EQU 0x0ffff174 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY5 +CYREG_SFLASH_PROT_VIRGINKEY5 EQU 0x0ffff175 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY6 +CYREG_SFLASH_PROT_VIRGINKEY6 EQU 0x0ffff176 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY7 +CYREG_SFLASH_PROT_VIRGINKEY7 EQU 0x0ffff177 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT0 +CYREG_SFLASH_DIE_LOT0 EQU 0x0ffff178 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_LOT__OFFSET +CYFLD_SFLASH_LOT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_LOT__SIZE +CYFLD_SFLASH_LOT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT1 +CYREG_SFLASH_DIE_LOT1 EQU 0x0ffff179 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT2 +CYREG_SFLASH_DIE_LOT2 EQU 0x0ffff17a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_WAFER +CYREG_SFLASH_DIE_WAFER EQU 0x0ffff17b + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAFER__OFFSET +CYFLD_SFLASH_WAFER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAFER__SIZE +CYFLD_SFLASH_WAFER__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_X +CYREG_SFLASH_DIE_X EQU 0x0ffff17c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_X__OFFSET +CYFLD_SFLASH_X__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_X__SIZE +CYFLD_SFLASH_X__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CRI_PASS__OFFSET +CYFLD_SFLASH_CRI_PASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CRI_PASS__SIZE +CYFLD_SFLASH_CRI_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_Y +CYREG_SFLASH_DIE_Y EQU 0x0ffff17d + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_Y__OFFSET +CYFLD_SFLASH_Y__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_Y__SIZE +CYFLD_SFLASH_Y__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHI_PASS__OFFSET +CYFLD_SFLASH_CHI_PASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHI_PASS__SIZE +CYFLD_SFLASH_CHI_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_SORT +CYREG_SFLASH_DIE_SORT EQU 0x0ffff17e + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S1_PASS__OFFSET +CYFLD_SFLASH_S1_PASS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S1_PASS__SIZE +CYFLD_SFLASH_S1_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S2_PASS__OFFSET +CYFLD_SFLASH_S2_PASS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S2_PASS__SIZE +CYFLD_SFLASH_S2_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S3_PASS__OFFSET +CYFLD_SFLASH_S3_PASS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S3_PASS__SIZE +CYFLD_SFLASH_S3_PASS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_MINOR +CYREG_SFLASH_DIE_MINOR EQU 0x0ffff17f + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MINOR__OFFSET +CYFLD_SFLASH_MINOR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MINOR__SIZE +CYFLD_SFLASH_MINOR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA00 +CYREG_SFLASH_PE_TE_DATA00 EQU 0x0ffff180 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA01 +CYREG_SFLASH_PE_TE_DATA01 EQU 0x0ffff181 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA02 +CYREG_SFLASH_PE_TE_DATA02 EQU 0x0ffff182 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA03 +CYREG_SFLASH_PE_TE_DATA03 EQU 0x0ffff183 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA04 +CYREG_SFLASH_PE_TE_DATA04 EQU 0x0ffff184 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA05 +CYREG_SFLASH_PE_TE_DATA05 EQU 0x0ffff185 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA06 +CYREG_SFLASH_PE_TE_DATA06 EQU 0x0ffff186 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA07 +CYREG_SFLASH_PE_TE_DATA07 EQU 0x0ffff187 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA08 +CYREG_SFLASH_PE_TE_DATA08 EQU 0x0ffff188 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA09 +CYREG_SFLASH_PE_TE_DATA09 EQU 0x0ffff189 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA10 +CYREG_SFLASH_PE_TE_DATA10 EQU 0x0ffff18a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA11 +CYREG_SFLASH_PE_TE_DATA11 EQU 0x0ffff18b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA12 +CYREG_SFLASH_PE_TE_DATA12 EQU 0x0ffff18c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA13 +CYREG_SFLASH_PE_TE_DATA13 EQU 0x0ffff18d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA14 +CYREG_SFLASH_PE_TE_DATA14 EQU 0x0ffff18e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA15 +CYREG_SFLASH_PE_TE_DATA15 EQU 0x0ffff18f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA16 +CYREG_SFLASH_PE_TE_DATA16 EQU 0x0ffff190 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA17 +CYREG_SFLASH_PE_TE_DATA17 EQU 0x0ffff191 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA18 +CYREG_SFLASH_PE_TE_DATA18 EQU 0x0ffff192 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA19 +CYREG_SFLASH_PE_TE_DATA19 EQU 0x0ffff193 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA20 +CYREG_SFLASH_PE_TE_DATA20 EQU 0x0ffff194 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA21 +CYREG_SFLASH_PE_TE_DATA21 EQU 0x0ffff195 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA22 +CYREG_SFLASH_PE_TE_DATA22 EQU 0x0ffff196 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA23 +CYREG_SFLASH_PE_TE_DATA23 EQU 0x0ffff197 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA24 +CYREG_SFLASH_PE_TE_DATA24 EQU 0x0ffff198 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA25 +CYREG_SFLASH_PE_TE_DATA25 EQU 0x0ffff199 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA26 +CYREG_SFLASH_PE_TE_DATA26 EQU 0x0ffff19a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA27 +CYREG_SFLASH_PE_TE_DATA27 EQU 0x0ffff19b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA28 +CYREG_SFLASH_PE_TE_DATA28 EQU 0x0ffff19c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA29 +CYREG_SFLASH_PE_TE_DATA29 EQU 0x0ffff19d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA30 +CYREG_SFLASH_PE_TE_DATA30 EQU 0x0ffff19e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PE_TE_DATA31 +CYREG_SFLASH_PE_TE_DATA31 EQU 0x0ffff19f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PP +CYREG_SFLASH_PP EQU 0x0ffff1a0 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PERIOD__OFFSET +CYFLD_SFLASH_PERIOD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PERIOD__SIZE +CYFLD_SFLASH_PERIOD__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PDAC__OFFSET +CYFLD_SFLASH_PDAC__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PDAC__SIZE +CYFLD_SFLASH_PDAC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_NDAC__OFFSET +CYFLD_SFLASH_NDAC__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_NDAC__SIZE +CYFLD_SFLASH_NDAC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_E +CYREG_SFLASH_E EQU 0x0ffff1a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_P +CYREG_SFLASH_P EQU 0x0ffff1a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_EA_E +CYREG_SFLASH_EA_E EQU 0x0ffff1ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_EA_P +CYREG_SFLASH_EA_P EQU 0x0ffff1b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_ES_E +CYREG_SFLASH_ES_E EQU 0x0ffff1b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_ES_P_EO +CYREG_SFLASH_ES_P_EO EQU 0x0ffff1b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_E_VCTAT +CYREG_SFLASH_E_VCTAT EQU 0x0ffff1bc + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_SLOPE__OFFSET +CYFLD_SFLASH_VCTAT_SLOPE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_SLOPE__SIZE +CYFLD_SFLASH_VCTAT_SLOPE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET +CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE +CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_ENABLE__OFFSET +CYFLD_SFLASH_VCTAT_ENABLE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_ENABLE__SIZE +CYFLD_SFLASH_VCTAT_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_P_VCTAT +CYREG_SFLASH_P_VCTAT EQU 0x0ffff1bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MARGIN +CYREG_SFLASH_MARGIN EQU 0x0ffff1be + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MDAC__OFFSET +CYFLD_SFLASH_MDAC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MDAC__SIZE +CYFLD_SFLASH_MDAC__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SPCIF_TRIM1 +CYREG_SFLASH_SPCIF_TRIM1 EQU 0x0ffff1bf + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_BDAC__OFFSET +CYFLD_SFLASH_BDAC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_BDAC__SIZE +CYFLD_SFLASH_BDAC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF0 +CYREG_SFLASH_IMO_MAXF0 EQU 0x0ffff1c0 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MAXFREQ__OFFSET +CYFLD_SFLASH_MAXFREQ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MAXFREQ__SIZE +CYFLD_SFLASH_MAXFREQ__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS0 +CYREG_SFLASH_IMO_ABS0 EQU 0x0ffff1c1 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET +CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ABS_TRIM_IMO__SIZE +CYFLD_SFLASH_ABS_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO0 +CYREG_SFLASH_IMO_TMPCO0 EQU 0x0ffff1c2 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET +CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE +CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF1 +CYREG_SFLASH_IMO_MAXF1 EQU 0x0ffff1c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS1 +CYREG_SFLASH_IMO_ABS1 EQU 0x0ffff1c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO1 +CYREG_SFLASH_IMO_TMPCO1 EQU 0x0ffff1c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF2 +CYREG_SFLASH_IMO_MAXF2 EQU 0x0ffff1c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS2 +CYREG_SFLASH_IMO_ABS2 EQU 0x0ffff1c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO2 +CYREG_SFLASH_IMO_TMPCO2 EQU 0x0ffff1c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF3 +CYREG_SFLASH_IMO_MAXF3 EQU 0x0ffff1c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS3 +CYREG_SFLASH_IMO_ABS3 EQU 0x0ffff1ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO3 +CYREG_SFLASH_IMO_TMPCO3 EQU 0x0ffff1cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS4 +CYREG_SFLASH_IMO_ABS4 EQU 0x0ffff1cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO4 +CYREG_SFLASH_IMO_TMPCO4 EQU 0x0ffff1cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM00 +CYREG_SFLASH_IMO_TRIM00 EQU 0x0ffff1d0 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_OFFSET__OFFSET +CYFLD_SFLASH_OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_OFFSET__SIZE +CYFLD_SFLASH_OFFSET__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM01 +CYREG_SFLASH_IMO_TRIM01 EQU 0x0ffff1d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM02 +CYREG_SFLASH_IMO_TRIM02 EQU 0x0ffff1d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM03 +CYREG_SFLASH_IMO_TRIM03 EQU 0x0ffff1d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM04 +CYREG_SFLASH_IMO_TRIM04 EQU 0x0ffff1d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM05 +CYREG_SFLASH_IMO_TRIM05 EQU 0x0ffff1d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM06 +CYREG_SFLASH_IMO_TRIM06 EQU 0x0ffff1d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM07 +CYREG_SFLASH_IMO_TRIM07 EQU 0x0ffff1d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM08 +CYREG_SFLASH_IMO_TRIM08 EQU 0x0ffff1d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM09 +CYREG_SFLASH_IMO_TRIM09 EQU 0x0ffff1d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM10 +CYREG_SFLASH_IMO_TRIM10 EQU 0x0ffff1da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM11 +CYREG_SFLASH_IMO_TRIM11 EQU 0x0ffff1db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM12 +CYREG_SFLASH_IMO_TRIM12 EQU 0x0ffff1dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM13 +CYREG_SFLASH_IMO_TRIM13 EQU 0x0ffff1dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM14 +CYREG_SFLASH_IMO_TRIM14 EQU 0x0ffff1de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM15 +CYREG_SFLASH_IMO_TRIM15 EQU 0x0ffff1df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM16 +CYREG_SFLASH_IMO_TRIM16 EQU 0x0ffff1e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM17 +CYREG_SFLASH_IMO_TRIM17 EQU 0x0ffff1e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM18 +CYREG_SFLASH_IMO_TRIM18 EQU 0x0ffff1e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM19 +CYREG_SFLASH_IMO_TRIM19 EQU 0x0ffff1e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM20 +CYREG_SFLASH_IMO_TRIM20 EQU 0x0ffff1e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM21 +CYREG_SFLASH_IMO_TRIM21 EQU 0x0ffff1e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM22 +CYREG_SFLASH_IMO_TRIM22 EQU 0x0ffff1e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM23 +CYREG_SFLASH_IMO_TRIM23 EQU 0x0ffff1e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM24 +CYREG_SFLASH_IMO_TRIM24 EQU 0x0ffff1e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM25 +CYREG_SFLASH_IMO_TRIM25 EQU 0x0ffff1e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM26 +CYREG_SFLASH_IMO_TRIM26 EQU 0x0ffff1ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM27 +CYREG_SFLASH_IMO_TRIM27 EQU 0x0ffff1eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM28 +CYREG_SFLASH_IMO_TRIM28 EQU 0x0ffff1ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM29 +CYREG_SFLASH_IMO_TRIM29 EQU 0x0ffff1ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM30 +CYREG_SFLASH_IMO_TRIM30 EQU 0x0ffff1ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM31 +CYREG_SFLASH_IMO_TRIM31 EQU 0x0ffff1ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM32 +CYREG_SFLASH_IMO_TRIM32 EQU 0x0ffff1f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM33 +CYREG_SFLASH_IMO_TRIM33 EQU 0x0ffff1f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM34 +CYREG_SFLASH_IMO_TRIM34 EQU 0x0ffff1f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM35 +CYREG_SFLASH_IMO_TRIM35 EQU 0x0ffff1f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM36 +CYREG_SFLASH_IMO_TRIM36 EQU 0x0ffff1f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM37 +CYREG_SFLASH_IMO_TRIM37 EQU 0x0ffff1f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM38 +CYREG_SFLASH_IMO_TRIM38 EQU 0x0ffff1f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM39 +CYREG_SFLASH_IMO_TRIM39 EQU 0x0ffff1f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM40 +CYREG_SFLASH_IMO_TRIM40 EQU 0x0ffff1f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM41 +CYREG_SFLASH_IMO_TRIM41 EQU 0x0ffff1f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM42 +CYREG_SFLASH_IMO_TRIM42 EQU 0x0ffff1fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM43 +CYREG_SFLASH_IMO_TRIM43 EQU 0x0ffff1fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM44 +CYREG_SFLASH_IMO_TRIM44 EQU 0x0ffff1fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM45 +CYREG_SFLASH_IMO_TRIM45 EQU 0x0ffff1fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CHECKSUM +CYREG_SFLASH_CHECKSUM EQU 0x0ffff1fe + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHECKSUM__OFFSET +CYFLD_SFLASH_CHECKSUM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHECKSUM__SIZE +CYFLD_SFLASH_CHECKSUM__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_SROM_BASE +CYDEV_SROM_BASE EQU 0x10000000 + ENDIF + IF :LNOT::DEF:CYDEV_SROM_SIZE +CYDEV_SROM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SROM_DATA_MBASE +CYREG_SROM_DATA_MBASE EQU 0x10000000 + ENDIF + IF :LNOT::DEF:CYREG_SROM_DATA_MSIZE +CYREG_SROM_DATA_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CPUSS_BASE +CYDEV_CPUSS_BASE EQU 0x40000000 + ENDIF + IF :LNOT::DEF:CYDEV_CPUSS_SIZE +CYDEV_CPUSS_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_CONFIG +CYREG_CPUSS_CONFIG EQU 0x40000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_VECS_IN_RAM__OFFSET +CYFLD_CPUSS_VECS_IN_RAM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_VECS_IN_RAM__SIZE +CYFLD_CPUSS_VECS_IN_RAM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET +CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE +CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SYSREQ +CYREG_CPUSS_SYSREQ EQU 0x40000004 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_COMMAND__OFFSET +CYFLD_CPUSS_COMMAND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_COMMAND__SIZE +CYFLD_CPUSS_COMMAND__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_NO_RST_OVR__OFFSET +CYFLD_CPUSS_NO_RST_OVR__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_NO_RST_OVR__SIZE +CYFLD_CPUSS_NO_RST_OVR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PRIVILEGED__OFFSET +CYFLD_CPUSS_PRIVILEGED__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PRIVILEGED__SIZE +CYFLD_CPUSS_PRIVILEGED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET +CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_ACCESS_EN__SIZE +CYFLD_CPUSS_ROM_ACCESS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_HMASTER__OFFSET +CYFLD_CPUSS_HMASTER__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_HMASTER__SIZE +CYFLD_CPUSS_HMASTER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSREQ__OFFSET +CYFLD_CPUSS_SYSREQ__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSREQ__SIZE +CYFLD_CPUSS_SYSREQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SYSARG +CYREG_CPUSS_SYSARG EQU 0x40000008 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ARG32__OFFSET +CYFLD_CPUSS_ARG32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ARG32__SIZE +CYFLD_CPUSS_ARG32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PROTECTION +CYREG_CPUSS_PROTECTION EQU 0x4000000c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT__OFFSET +CYFLD_CPUSS_PROT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT__SIZE +CYFLD_CPUSS_PROT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_VIRGIN +CYVAL_CPUSS_PROT_VIRGIN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_OPEN +CYVAL_CPUSS_PROT_OPEN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_PROTECTED +CYVAL_CPUSS_PROT_PROTECTED EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_KILL +CYVAL_CPUSS_PROT_KILL EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_PROT_BOOT +CYVAL_CPUSS_PROT_BOOT EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT_LOCK__OFFSET +CYFLD_CPUSS_PROT_LOCK__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROT_LOCK__SIZE +CYFLD_CPUSS_PROT_LOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_ROM +CYREG_CPUSS_PRIV_ROM EQU 0x40000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_LIMIT__OFFSET +CYFLD_CPUSS_ROM_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_LIMIT__SIZE +CYFLD_CPUSS_ROM_LIMIT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_RAM +CYREG_CPUSS_PRIV_RAM EQU 0x40000014 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_LIMIT__OFFSET +CYFLD_CPUSS_RAM_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_LIMIT__SIZE +CYFLD_CPUSS_RAM_LIMIT__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_FLASH +CYREG_CPUSS_PRIV_FLASH EQU 0x40000018 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_LIMIT__OFFSET +CYFLD_CPUSS_FLASH_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_LIMIT__SIZE +CYFLD_CPUSS_FLASH_LIMIT__SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_WOUNDING +CYREG_CPUSS_WOUNDING EQU 0x4000001c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_SIZE__OFFSET +CYFLD_CPUSS_RAM_SIZE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_SIZE__SIZE +CYFLD_CPUSS_RAM_SIZE__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__OFFSET +CYFLD_CPUSS_RAM_WOUND__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__SIZE +CYFLD_CPUSS_RAM_WOUND__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_FULL +CYVAL_CPUSS_RAM_WOUND_FULL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 +CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__OFFSET +CYFLD_CPUSS_FLASH_WOUND__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__SIZE +CYFLD_CPUSS_FLASH_WOUND__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_FULL +CYVAL_CPUSS_FLASH_WOUND_FULL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 +CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_INTR_SELECT +CYREG_CPUSS_INTR_SELECT EQU 0x40000020 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SELECT32__OFFSET +CYFLD_CPUSS_SELECT32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SELECT32__SIZE +CYFLD_CPUSS_SELECT32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_HSIOM_BASE +CYDEV_HSIOM_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_HSIOM_SIZE +CYDEV_HSIOM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL0 +CYREG_HSIOM_PORT_SEL0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL0__OFFSET +CYFLD_HSIOM_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL0__SIZE +CYFLD_HSIOM_SEL0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_GPIO +CYVAL_HSIOM_SEL0_GPIO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_GPIO_DSI +CYVAL_HSIOM_SEL0_GPIO_DSI EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DSI_DSI +CYVAL_HSIOM_SEL0_DSI_DSI EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DSI_GPIO +CYVAL_HSIOM_SEL0_DSI_GPIO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_CSD_SENSE +CYVAL_HSIOM_SEL0_CSD_SENSE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_CSD_SHIELD +CYVAL_HSIOM_SEL0_CSD_SHIELD EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_AMUXA +CYVAL_HSIOM_SEL0_AMUXA EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_AMUXB +CYVAL_HSIOM_SEL0_AMUXB EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_0 +CYVAL_HSIOM_SEL0_ACT_0 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_1 +CYVAL_HSIOM_SEL0_ACT_1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_2 +CYVAL_HSIOM_SEL0_ACT_2 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_ACT_3 +CYVAL_HSIOM_SEL0_ACT_3 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_LCD_COM +CYVAL_HSIOM_SEL0_LCD_COM EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_LCD_SEG +CYVAL_HSIOM_SEL0_LCD_SEG EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DPSLP_0 +CYVAL_HSIOM_SEL0_DPSLP_0 EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_DPSLP_1 +CYVAL_HSIOM_SEL0_DPSLP_1 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_COMP1_INP +CYVAL_HSIOM_SEL0_COMP1_INP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 +CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL1__OFFSET +CYFLD_HSIOM_SEL1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL1__SIZE +CYFLD_HSIOM_SEL1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL1_COMP1_INN +CYVAL_HSIOM_SEL1_COMP1_INN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 +CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL2__OFFSET +CYFLD_HSIOM_SEL2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL2__SIZE +CYFLD_HSIOM_SEL2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL2_COMP2_INP +CYVAL_HSIOM_SEL2_COMP2_INP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 +CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL3__OFFSET +CYFLD_HSIOM_SEL3__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL3__SIZE +CYFLD_HSIOM_SEL3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL3_COMP2_INN +CYVAL_HSIOM_SEL3_COMP2_INN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL4__OFFSET +CYFLD_HSIOM_SEL4__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL4__SIZE +CYFLD_HSIOM_SEL4__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL4_SCB1_UART_RX +CYVAL_HSIOM_SEL4_SCB1_UART_RX EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL4_SCB1_I2C_SCL +CYVAL_HSIOM_SEL4_SCB1_I2C_SCL EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI +CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL5__OFFSET +CYFLD_HSIOM_SEL5__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL5__SIZE +CYFLD_HSIOM_SEL5__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL5_SCB1_UART_TX +CYVAL_HSIOM_SEL5_SCB1_UART_TX EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL5_SCB1_I2C_SDA +CYVAL_HSIOM_SEL5_SCB1_I2C_SDA EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL5_SCB1_SPI_MISO +CYVAL_HSIOM_SEL5_SCB1_SPI_MISO EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL6__OFFSET +CYFLD_HSIOM_SEL6__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL6__SIZE +CYFLD_HSIOM_SEL6__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL6_EXT_CLK +CYVAL_HSIOM_SEL6_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL6_SCB1_SPI_CLK +CYVAL_HSIOM_SEL6_SCB1_SPI_CLK EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL7__OFFSET +CYFLD_HSIOM_SEL7__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SEL7__SIZE +CYFLD_HSIOM_SEL7__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL7_WAKEUP +CYVAL_HSIOM_SEL7_WAKEUP EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 +CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL1 +CYREG_HSIOM_PORT_SEL1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL2 +CYREG_HSIOM_PORT_SEL2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL3 +CYREG_HSIOM_PORT_SEL3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL4 +CYREG_HSIOM_PORT_SEL4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_CLK_BASE +CYDEV_CLK_BASE EQU 0x40020000 + ENDIF + IF :LNOT::DEF:CYDEV_CLK_SIZE +CYDEV_CLK_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_A00 +CYREG_CLK_DIVIDER_A00 EQU 0x40020000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_A__OFFSET +CYFLD_CLK_DIVIDER_A__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_A__SIZE +CYFLD_CLK_DIVIDER_A__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_A__OFFSET +CYFLD_CLK_ENABLE_A__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_A__SIZE +CYFLD_CLK_ENABLE_A__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_A01 +CYREG_CLK_DIVIDER_A01 EQU 0x40020004 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_A02 +CYREG_CLK_DIVIDER_A02 EQU 0x40020008 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_B00 +CYREG_CLK_DIVIDER_B00 EQU 0x40020040 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_B__OFFSET +CYFLD_CLK_DIVIDER_B__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_B__SIZE +CYFLD_CLK_DIVIDER_B__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_A_B__OFFSET +CYFLD_CLK_CASCADE_A_B__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_A_B__SIZE +CYFLD_CLK_CASCADE_A_B__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_B__OFFSET +CYFLD_CLK_ENABLE_B__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_B__SIZE +CYFLD_CLK_ENABLE_B__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_B01 +CYREG_CLK_DIVIDER_B01 EQU 0x40020044 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_B02 +CYREG_CLK_DIVIDER_B02 EQU 0x40020048 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_C00 +CYREG_CLK_DIVIDER_C00 EQU 0x40020080 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_C__OFFSET +CYFLD_CLK_DIVIDER_C__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_C__SIZE +CYFLD_CLK_DIVIDER_C__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_B_C__OFFSET +CYFLD_CLK_CASCADE_B_C__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CLK_CASCADE_B_C__SIZE +CYFLD_CLK_CASCADE_B_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_C__OFFSET +CYFLD_CLK_ENABLE_C__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CLK_ENABLE_C__SIZE +CYFLD_CLK_ENABLE_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_C01 +CYREG_CLK_DIVIDER_C01 EQU 0x40020084 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_C02 +CYREG_CLK_DIVIDER_C02 EQU 0x40020088 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_FRAC_A00 +CYREG_CLK_DIVIDER_FRAC_A00 EQU 0x40020100 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_A__OFFSET +CYFLD_CLK_FRAC_A__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_A__SIZE +CYFLD_CLK_FRAC_A__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_FRAC_B00 +CYREG_CLK_DIVIDER_FRAC_B00 EQU 0x40020140 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_B__OFFSET +CYFLD_CLK_FRAC_B__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_B__SIZE +CYFLD_CLK_FRAC_B__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DIVIDER_FRAC_C00 +CYREG_CLK_DIVIDER_FRAC_C00 EQU 0x40020180 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_C__OFFSET +CYFLD_CLK_FRAC_C__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_FRAC_C__SIZE +CYFLD_CLK_FRAC_C__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT00 +CYREG_CLK_SELECT00 EQU 0x40020200 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_N__OFFSET +CYFLD_CLK_DIVIDER_N__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_N__SIZE +CYFLD_CLK_DIVIDER_N__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_ABC__OFFSET +CYFLD_CLK_DIVIDER_ABC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CLK_DIVIDER_ABC__SIZE +CYFLD_CLK_DIVIDER_ABC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_OFF +CYVAL_CLK_DIVIDER_ABC_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_A +CYVAL_CLK_DIVIDER_ABC_A EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_B +CYVAL_CLK_DIVIDER_ABC_B EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CLK_DIVIDER_ABC_C +CYVAL_CLK_DIVIDER_ABC_C EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT01 +CYREG_CLK_SELECT01 EQU 0x40020204 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT02 +CYREG_CLK_SELECT02 EQU 0x40020208 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT03 +CYREG_CLK_SELECT03 EQU 0x4002020c + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT04 +CYREG_CLK_SELECT04 EQU 0x40020210 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT05 +CYREG_CLK_SELECT05 EQU 0x40020214 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT06 +CYREG_CLK_SELECT06 EQU 0x40020218 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT07 +CYREG_CLK_SELECT07 EQU 0x4002021c + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT08 +CYREG_CLK_SELECT08 EQU 0x40020220 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT09 +CYREG_CLK_SELECT09 EQU 0x40020224 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT10 +CYREG_CLK_SELECT10 EQU 0x40020228 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT11 +CYREG_CLK_SELECT11 EQU 0x4002022c + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT12 +CYREG_CLK_SELECT12 EQU 0x40020230 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT13 +CYREG_CLK_SELECT13 EQU 0x40020234 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT14 +CYREG_CLK_SELECT14 EQU 0x40020238 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT15 +CYREG_CLK_SELECT15 EQU 0x4002023c + ENDIF + IF :LNOT::DEF:CYDEV_TST_BASE +CYDEV_TST_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_TST_SIZE +CYDEV_TST_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_TST_CTRL +CYREG_TST_CTRL EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_ACCESS__OFFSET +CYFLD_TST_DAP_NO_ACCESS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_ACCESS__SIZE +CYFLD_TST_DAP_NO_ACCESS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_DEBUG__OFFSET +CYFLD_TST_DAP_NO_DEBUG__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DAP_NO_DEBUG__SIZE +CYFLD_TST_DAP_NO_DEBUG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SWD_CONNECTED__OFFSET +CYFLD_TST_SWD_CONNECTED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SWD_CONNECTED__SIZE +CYFLD_TST_SWD_CONNECTED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_RESET_EN_N__OFFSET +CYFLD_TST_TEST_RESET_EN_N__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_RESET_EN_N__SIZE +CYFLD_TST_TEST_RESET_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SET_EN_N__OFFSET +CYFLD_TST_TEST_SET_EN_N__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SET_EN_N__SIZE +CYFLD_TST_TEST_SET_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_ICG_EN_N__OFFSET +CYFLD_TST_TEST_ICG_EN_N__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_ICG_EN_N__SIZE +CYFLD_TST_TEST_ICG_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET +CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_1_EN_N__SIZE +CYFLD_TST_TEST_OCC0_1_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET +CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_OCC0_2_EN_N__SIZE +CYFLD_TST_TEST_OCC0_2_EN_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET +CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPISOLATE_EN__SIZE +CYFLD_TST_TEST_SLPISOLATE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET +CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSISOLATE_EN__SIZE +CYFLD_TST_TEST_SYSISOLATE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET +CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SLPRETAIN_EN__SIZE +CYFLD_TST_TEST_SLPRETAIN_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET +CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SYSRETAIN_EN__SIZE +CYFLD_TST_TEST_SYSRETAIN_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE1_EN__OFFSET +CYFLD_TST_TEST_SPARE1_EN__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE1_EN__SIZE +CYFLD_TST_TEST_SPARE1_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE2_EN__OFFSET +CYFLD_TST_TEST_SPARE2_EN__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_SPARE2_EN__SIZE +CYFLD_TST_TEST_SPARE2_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET +CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_OCC_OBSERVE__SIZE +CYFLD_TST_SCAN_OCC_OBSERVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF1__OFFSET +CYFLD_TST_SCAN_TRF1__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF1__SIZE +CYFLD_TST_SCAN_TRF1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF__OFFSET +CYFLD_TST_SCAN_TRF__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_TRF__SIZE +CYFLD_TST_SCAN_TRF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_IDDQ__OFFSET +CYFLD_TST_SCAN_IDDQ__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_IDDQ__SIZE +CYFLD_TST_SCAN_IDDQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_COMPRESS__OFFSET +CYFLD_TST_SCAN_COMPRESS__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_COMPRESS__SIZE +CYFLD_TST_SCAN_COMPRESS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_MODE__OFFSET +CYFLD_TST_SCAN_MODE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_TST_SCAN_MODE__SIZE +CYFLD_TST_SCAN_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_PTM_MODE_EN__OFFSET +CYFLD_TST_PTM_MODE_EN__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_TST_PTM_MODE_EN__SIZE +CYFLD_TST_PTM_MODE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_ADFT_CTRL +CYREG_TST_ADFT_CTRL EQU 0x40030004 + ENDIF + IF :LNOT::DEF:CYFLD_TST_ENABLE__OFFSET +CYFLD_TST_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TST_ENABLE__SIZE +CYFLD_TST_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_DDFT_CTRL +CYREG_TST_DDFT_CTRL EQU 0x40030008 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL1__OFFSET +CYFLD_TST_DFT_SEL1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL1__SIZE +CYFLD_TST_DFT_SEL1__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_VSS +CYVAL_TST_DFT_SEL1_VSS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_CLK1 +CYVAL_TST_DFT_SEL1_CLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_CLK2 +CYVAL_TST_DFT_SEL1_CLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_PWR1 +CYVAL_TST_DFT_SEL1_PWR1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_PWR2 +CYVAL_TST_DFT_SEL1_PWR2 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_VMON +CYVAL_TST_DFT_SEL1_VMON EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS_VDDA_OK +CYVAL_TST_DFT_SEL1_TSS_VDDA_OK EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_ADFT_TRIP1 +CYVAL_TST_DFT_SEL1_ADFT_TRIP1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_ADFT_TRIP2 +CYVAL_TST_DFT_SEL1_ADFT_TRIP2 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS1 +CYVAL_TST_DFT_SEL1_TSS1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS2 +CYVAL_TST_DFT_SEL1_TSS2 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS3 +CYVAL_TST_DFT_SEL1_TSS3 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_TSS4 +CYVAL_TST_DFT_SEL1_TSS4 EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS +CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI +CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL2__OFFSET +CYFLD_TST_DFT_SEL2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DFT_SEL2__SIZE +CYFLD_TST_DFT_SEL2__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_VSS +CYVAL_TST_DFT_SEL2_VSS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_CLK1 +CYVAL_TST_DFT_SEL2_CLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_CLK2 +CYVAL_TST_DFT_SEL2_CLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_PWR1 +CYVAL_TST_DFT_SEL2_PWR1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_PWR2 +CYVAL_TST_DFT_SEL2_PWR2 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_VMON +CYVAL_TST_DFT_SEL2_VMON EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS_VDDA_OK +CYVAL_TST_DFT_SEL2_TSS_VDDA_OK EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_ADFT_TRIP1 +CYVAL_TST_DFT_SEL2_ADFT_TRIP1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_ADFT_TRIP2 +CYVAL_TST_DFT_SEL2_ADFT_TRIP2 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS1 +CYVAL_TST_DFT_SEL2_TSS1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS2 +CYVAL_TST_DFT_SEL2_TSS2 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS3 +CYVAL_TST_DFT_SEL2_TSS3 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_TSS4 +CYVAL_TST_DFT_SEL2_TSS4 EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS +CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI +CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_TST_EDGE__OFFSET +CYFLD_TST_EDGE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_TST_EDGE__SIZE +CYFLD_TST_EDGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_EDGE_POSEDGE +CYVAL_TST_EDGE_POSEDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_EDGE_NEGEDGE +CYVAL_TST_EDGE_NEGEDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TST_DIVIDE__OFFSET +CYFLD_TST_DIVIDE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_TST_DIVIDE__SIZE +CYFLD_TST_DIVIDE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIRECT +CYVAL_TST_DIVIDE_DIRECT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIV_BY_2 +CYVAL_TST_DIVIDE_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIV_BY_4 +CYVAL_TST_DIVIDE_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TST_DIVIDE_DIV_BY_8 +CYVAL_TST_DIVIDE_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TST_MODE +CYREG_TST_MODE EQU 0x40030014 + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_MODE__OFFSET +CYFLD_TST_TEST_MODE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TST_TEST_MODE__SIZE +CYFLD_TST_TEST_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_TRIM_CNTR1 +CYREG_TST_TRIM_CNTR1 EQU 0x40030018 + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER__OFFSET +CYFLD_TST_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER__SIZE +CYFLD_TST_COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER_DONE__OFFSET +CYFLD_TST_COUNTER_DONE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TST_COUNTER_DONE__SIZE +CYFLD_TST_COUNTER_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_TRIM_CNTR2 +CYREG_TST_TRIM_CNTR2 EQU 0x4003001c + ENDIF + IF :LNOT::DEF:CYDEV_PRT0_BASE +CYDEV_PRT0_BASE EQU 0x40040000 + ENDIF + IF :LNOT::DEF:CYDEV_PRT0_SIZE +CYDEV_PRT0_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40040000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DATAREG__OFFSET +CYFLD_PRT_DATAREG__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DATAREG__SIZE +CYFLD_PRT_DATAREG__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40040004 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE__OFFSET +CYFLD_PRT_PINSTATE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE__SIZE +CYFLD_PRT_PINSTATE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE_FLT__OFFSET +CYFLD_PRT_PINSTATE_FLT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PINSTATE_FLT__SIZE +CYFLD_PRT_PINSTATE_FLT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC +CYREG_PRT0_PC EQU 0x40040008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DM__OFFSET +CYFLD_PRT_DM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_DM__SIZE +CYFLD_PRT_DM__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_OFF +CYVAL_PRT_DM_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_INPUT +CYVAL_PRT_DM_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_0_PU +CYVAL_PRT_DM_0_PU EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_PD_1 +CYVAL_PRT_DM_PD_1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_0_Z +CYVAL_PRT_DM_0_Z EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_Z_1 +CYVAL_PRT_DM_Z_1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_0_1 +CYVAL_PRT_DM_0_1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_DM_PD_PU +CYVAL_PRT_DM_PD_PU EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_VTRIP_SEL__OFFSET +CYFLD_PRT_VTRIP_SEL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_VTRIP_SEL__SIZE +CYFLD_PRT_VTRIP_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_SLOW__OFFSET +CYFLD_PRT_SLOW__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_SLOW__SIZE +CYFLD_PRT_SLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INTCFG +CYREG_PRT0_INTCFG EQU 0x4004000c + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE__OFFSET +CYFLD_PRT_INTTYPE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE__SIZE +CYFLD_PRT_INTTYPE__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_DISABLE +CYVAL_PRT_INTTYPE_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_RISING +CYVAL_PRT_INTTYPE_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FALLING +CYVAL_PRT_INTTYPE_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_BOTH +CYVAL_PRT_INTTYPE_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE_FLT__OFFSET +CYFLD_PRT_INTTYPE_FLT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTTYPE_FLT__SIZE +CYFLD_PRT_INTTYPE_FLT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_DISABLE +CYVAL_PRT_INTTYPE_FLT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_RISING +CYVAL_PRT_INTTYPE_FLT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_FALLING +CYVAL_PRT_INTTYPE_FLT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_PRT_INTTYPE_FLT_BOTH +CYVAL_PRT_INTTYPE_FLT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_FLT_SELECT__OFFSET +CYFLD_PRT_FLT_SELECT__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_FLT_SELECT__SIZE +CYFLD_PRT_FLT_SELECT__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INTSTAT +CYREG_PRT0_INTSTAT EQU 0x40040010 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT__OFFSET +CYFLD_PRT_INTSTAT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT__SIZE +CYFLD_PRT_INTSTAT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT_FLT__OFFSET +CYFLD_PRT_INTSTAT_FLT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INTSTAT_FLT__SIZE +CYFLD_PRT_INTSTAT_FLT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS__OFFSET +CYFLD_PRT_PS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS__SIZE +CYFLD_PRT_PS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS_FLT__OFFSET +CYFLD_PRT_PS_FLT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_PS_FLT__SIZE +CYFLD_PRT_PS_FLT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40040018 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INP_DIS__OFFSET +CYFLD_PRT_INP_DIS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRT_INP_DIS__SIZE +CYFLD_PRT_INP_DIS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PRT1_BASE +CYDEV_PRT1_BASE EQU 0x40040100 + ENDIF + IF :LNOT::DEF:CYDEV_PRT1_SIZE +CYDEV_PRT1_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40040100 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40040104 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC +CYREG_PRT1_PC EQU 0x40040108 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INTCFG +CYREG_PRT1_INTCFG EQU 0x4004010c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INTSTAT +CYREG_PRT1_INTSTAT EQU 0x40040110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x40040118 + ENDIF + IF :LNOT::DEF:CYDEV_PRT2_BASE +CYDEV_PRT2_BASE EQU 0x40040200 + ENDIF + IF :LNOT::DEF:CYDEV_PRT2_SIZE +CYDEV_PRT2_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40040200 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40040204 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC +CYREG_PRT2_PC EQU 0x40040208 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INTCFG +CYREG_PRT2_INTCFG EQU 0x4004020c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INTSTAT +CYREG_PRT2_INTSTAT EQU 0x40040210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40040218 + ENDIF + IF :LNOT::DEF:CYDEV_PRT3_BASE +CYDEV_PRT3_BASE EQU 0x40040300 + ENDIF + IF :LNOT::DEF:CYDEV_PRT3_SIZE +CYDEV_PRT3_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40040300 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40040304 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC +CYREG_PRT3_PC EQU 0x40040308 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INTCFG +CYREG_PRT3_INTCFG EQU 0x4004030c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INTSTAT +CYREG_PRT3_INTSTAT EQU 0x40040310 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x40040318 + ENDIF + IF :LNOT::DEF:CYDEV_PRT4_BASE +CYDEV_PRT4_BASE EQU 0x40040400 + ENDIF + IF :LNOT::DEF:CYDEV_PRT4_SIZE +CYDEV_PRT4_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40040400 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40040404 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC +CYREG_PRT4_PC EQU 0x40040408 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INTCFG +CYREG_PRT4_INTCFG EQU 0x4004040c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INTSTAT +CYREG_PRT4_INTSTAT EQU 0x40040410 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40040418 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_BASE +CYDEV_TCPWM_BASE EQU 0x40050000 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_SIZE +CYDEV_TCPWM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CTRL +CYREG_TCPWM_CTRL EQU 0x40050000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_ENABLED__OFFSET +CYFLD_TCPWM_COUNTER_ENABLED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_ENABLED__SIZE +CYFLD_TCPWM_COUNTER_ENABLED__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CMD +CYREG_TCPWM_CMD EQU 0x40050008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET +CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_CAPTURE__SIZE +CYFLD_TCPWM_COUNTER_CAPTURE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_RELOAD__OFFSET +CYFLD_TCPWM_COUNTER_RELOAD__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_RELOAD__SIZE +CYFLD_TCPWM_COUNTER_RELOAD__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_STOP__OFFSET +CYFLD_TCPWM_COUNTER_STOP__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_STOP__SIZE +CYFLD_TCPWM_COUNTER_STOP__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_START__OFFSET +CYFLD_TCPWM_COUNTER_START__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_START__SIZE +CYFLD_TCPWM_COUNTER_START__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_INTR_CAUSE +CYREG_TCPWM_INTR_CAUSE EQU 0x4005000c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_INT__OFFSET +CYFLD_TCPWM_COUNTER_INT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_INT__SIZE +CYFLD_TCPWM_COUNTER_INT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT0_BASE +CYDEV_TCPWM_CNT0_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT0_SIZE +CYDEV_TCPWM_CNT0_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CTRL +CYREG_TCPWM_CNT0_CTRL EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET +CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE +CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET +CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE +CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET +CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE +CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET +CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE +CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_GENERIC__OFFSET +CYFLD_TCPWM_CNT_GENERIC__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_GENERIC__SIZE +CYFLD_TCPWM_CNT_GENERIC__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY1 +CYVAL_TCPWM_CNT_GENERIC_DIVBY1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY2 +CYVAL_TCPWM_CNT_GENERIC_DIVBY2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY4 +CYVAL_TCPWM_CNT_GENERIC_DIVBY4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY8 +CYVAL_TCPWM_CNT_GENERIC_DIVBY8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY16 +CYVAL_TCPWM_CNT_GENERIC_DIVBY16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY32 +CYVAL_TCPWM_CNT_GENERIC_DIVBY32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY64 +CYVAL_TCPWM_CNT_GENERIC_DIVBY64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY128 +CYVAL_TCPWM_CNT_GENERIC_DIVBY128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET +CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE +CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET +CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_ONE_SHOT__SIZE +CYFLD_TCPWM_CNT_ONE_SHOT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET +CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE +CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT +CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT +CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_MODE__OFFSET +CYFLD_TCPWM_CNT_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_MODE__SIZE +CYFLD_TCPWM_CNT_MODE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_TIMER +CYVAL_TCPWM_CNT_MODE_TIMER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_CAPTURE +CYVAL_TCPWM_CNT_MODE_CAPTURE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_QUAD +CYVAL_TCPWM_CNT_MODE_QUAD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM +CYVAL_TCPWM_CNT_MODE_PWM EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM_DT +CYVAL_TCPWM_CNT_MODE_PWM_DT EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM_PR +CYVAL_TCPWM_CNT_MODE_PWM_PR EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_STATUS +CYREG_TCPWM_CNT0_STATUS EQU 0x40050104 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_DOWN__OFFSET +CYFLD_TCPWM_CNT_DOWN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_DOWN__SIZE +CYFLD_TCPWM_CNT_DOWN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RUNNING__OFFSET +CYFLD_TCPWM_CNT_RUNNING__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RUNNING__SIZE +CYFLD_TCPWM_CNT_RUNNING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_COUNTER +CYREG_TCPWM_CNT0_COUNTER EQU 0x40050108 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNTER__OFFSET +CYFLD_TCPWM_CNT_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNTER__SIZE +CYFLD_TCPWM_CNT_COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CC +CYREG_TCPWM_CNT0_CC EQU 0x4005010c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC__OFFSET +CYFLD_TCPWM_CNT_CC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC__SIZE +CYFLD_TCPWM_CNT_CC__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CC_BUFF +CYREG_TCPWM_CNT0_CC_BUFF EQU 0x40050110 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_PERIOD +CYREG_TCPWM_CNT0_PERIOD EQU 0x40050114 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PERIOD__OFFSET +CYFLD_TCPWM_CNT_PERIOD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PERIOD__SIZE +CYFLD_TCPWM_CNT_PERIOD__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_PERIOD_BUFF +CYREG_TCPWM_CNT0_PERIOD_BUFF EQU 0x40050118 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL0 +CYREG_TCPWM_CNT0_TR_CTRL0 EQU 0x40050120 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET +CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE +CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET +CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_SEL__SIZE +CYFLD_TCPWM_CNT_COUNT_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET +CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE +CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_SEL__OFFSET +CYFLD_TCPWM_CNT_STOP_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_SEL__SIZE +CYFLD_TCPWM_CNT_STOP_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_SEL__OFFSET +CYFLD_TCPWM_CNT_START_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_SEL__SIZE +CYFLD_TCPWM_CNT_START_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL1 +CYREG_TCPWM_CNT0_TR_CTRL1 EQU 0x40050124 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET +CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE +CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET +CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE +CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET +CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE +CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET +CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_EDGE__SIZE +CYFLD_TCPWM_CNT_STOP_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_EDGE__OFFSET +CYFLD_TCPWM_CNT_START_EDGE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_EDGE__SIZE +CYFLD_TCPWM_CNT_START_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL2 +CYREG_TCPWM_CNT0_TR_CTRL2 EQU 0x40050128 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET +CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE +CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET +CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR +CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT +CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET +CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE +CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET +CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR +CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT +CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET +CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE +CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR +CYREG_TCPWM_CNT0_INTR EQU 0x40050130 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_TC__OFFSET +CYFLD_TCPWM_CNT_TC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_TC__SIZE +CYFLD_TCPWM_CNT_TC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH__OFFSET +CYFLD_TCPWM_CNT_CC_MATCH__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH__SIZE +CYFLD_TCPWM_CNT_CC_MATCH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_SET +CYREG_TCPWM_CNT0_INTR_SET EQU 0x40050134 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_MASK +CYREG_TCPWM_CNT0_INTR_MASK EQU 0x40050138 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_MASKED +CYREG_TCPWM_CNT0_INTR_MASKED EQU 0x4005013c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT1_BASE +CYDEV_TCPWM_CNT1_BASE EQU 0x40050140 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT1_SIZE +CYDEV_TCPWM_CNT1_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CTRL +CYREG_TCPWM_CNT1_CTRL EQU 0x40050140 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_STATUS +CYREG_TCPWM_CNT1_STATUS EQU 0x40050144 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_COUNTER +CYREG_TCPWM_CNT1_COUNTER EQU 0x40050148 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CC +CYREG_TCPWM_CNT1_CC EQU 0x4005014c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CC_BUFF +CYREG_TCPWM_CNT1_CC_BUFF EQU 0x40050150 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_PERIOD +CYREG_TCPWM_CNT1_PERIOD EQU 0x40050154 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_PERIOD_BUFF +CYREG_TCPWM_CNT1_PERIOD_BUFF EQU 0x40050158 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL0 +CYREG_TCPWM_CNT1_TR_CTRL0 EQU 0x40050160 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL1 +CYREG_TCPWM_CNT1_TR_CTRL1 EQU 0x40050164 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL2 +CYREG_TCPWM_CNT1_TR_CTRL2 EQU 0x40050168 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR +CYREG_TCPWM_CNT1_INTR EQU 0x40050170 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_SET +CYREG_TCPWM_CNT1_INTR_SET EQU 0x40050174 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_MASK +CYREG_TCPWM_CNT1_INTR_MASK EQU 0x40050178 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_MASKED +CYREG_TCPWM_CNT1_INTR_MASKED EQU 0x4005017c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT2_BASE +CYDEV_TCPWM_CNT2_BASE EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT2_SIZE +CYDEV_TCPWM_CNT2_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CTRL +CYREG_TCPWM_CNT2_CTRL EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_STATUS +CYREG_TCPWM_CNT2_STATUS EQU 0x40050184 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_COUNTER +CYREG_TCPWM_CNT2_COUNTER EQU 0x40050188 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CC +CYREG_TCPWM_CNT2_CC EQU 0x4005018c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CC_BUFF +CYREG_TCPWM_CNT2_CC_BUFF EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_PERIOD +CYREG_TCPWM_CNT2_PERIOD EQU 0x40050194 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_PERIOD_BUFF +CYREG_TCPWM_CNT2_PERIOD_BUFF EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL0 +CYREG_TCPWM_CNT2_TR_CTRL0 EQU 0x400501a0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL1 +CYREG_TCPWM_CNT2_TR_CTRL1 EQU 0x400501a4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL2 +CYREG_TCPWM_CNT2_TR_CTRL2 EQU 0x400501a8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR +CYREG_TCPWM_CNT2_INTR EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_SET +CYREG_TCPWM_CNT2_INTR_SET EQU 0x400501b4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_MASK +CYREG_TCPWM_CNT2_INTR_MASK EQU 0x400501b8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_MASKED +CYREG_TCPWM_CNT2_INTR_MASKED EQU 0x400501bc + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT3_BASE +CYDEV_TCPWM_CNT3_BASE EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT3_SIZE +CYDEV_TCPWM_CNT3_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CTRL +CYREG_TCPWM_CNT3_CTRL EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_STATUS +CYREG_TCPWM_CNT3_STATUS EQU 0x400501c4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_COUNTER +CYREG_TCPWM_CNT3_COUNTER EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CC +CYREG_TCPWM_CNT3_CC EQU 0x400501cc + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CC_BUFF +CYREG_TCPWM_CNT3_CC_BUFF EQU 0x400501d0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_PERIOD +CYREG_TCPWM_CNT3_PERIOD EQU 0x400501d4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_PERIOD_BUFF +CYREG_TCPWM_CNT3_PERIOD_BUFF EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL0 +CYREG_TCPWM_CNT3_TR_CTRL0 EQU 0x400501e0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL1 +CYREG_TCPWM_CNT3_TR_CTRL1 EQU 0x400501e4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL2 +CYREG_TCPWM_CNT3_TR_CTRL2 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR +CYREG_TCPWM_CNT3_INTR EQU 0x400501f0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_SET +CYREG_TCPWM_CNT3_INTR_SET EQU 0x400501f4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_MASK +CYREG_TCPWM_CNT3_INTR_MASK EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_MASKED +CYREG_TCPWM_CNT3_INTR_MASKED EQU 0x400501fc + ENDIF + IF :LNOT::DEF:CYDEV_SCB0_BASE +CYDEV_SCB0_BASE EQU 0x40060000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB0_SIZE +CYDEV_SCB0_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_CTRL +CYREG_SCB0_CTRL EQU 0x40060000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVS__OFFSET +CYFLD_SCB_OVS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVS__SIZE +CYFLD_SCB_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_AM_MODE__OFFSET +CYFLD_SCB_EC_AM_MODE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_AM_MODE__SIZE +CYFLD_SCB_EC_AM_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_OP_MODE__OFFSET +CYFLD_SCB_EC_OP_MODE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_OP_MODE__SIZE +CYFLD_SCB_EC_OP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_MODE__OFFSET +CYFLD_SCB_EZ_MODE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_MODE__SIZE +CYFLD_SCB_EZ_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR_ACCEPT__OFFSET +CYFLD_SCB_ADDR_ACCEPT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR_ACCEPT__SIZE +CYFLD_SCB_ADDR_ACCEPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCK__OFFSET +CYFLD_SCB_BLOCK__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCK__SIZE +CYFLD_SCB_BLOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MODE__OFFSET +CYFLD_SCB_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MODE__SIZE +CYFLD_SCB_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_I2C +CYVAL_SCB_MODE_I2C EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_SPI +CYVAL_SCB_MODE_SPI EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_UART +CYVAL_SCB_MODE_UART EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ENABLED__OFFSET +CYFLD_SCB_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ENABLED__SIZE +CYFLD_SCB_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_STATUS +CYREG_SCB0_STATUS EQU 0x40060004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_BUSY__OFFSET +CYFLD_SCB_EC_BUSY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_BUSY__SIZE +CYFLD_SCB_EC_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_SPI_CTRL +CYREG_SCB0_SPI_CTRL EQU 0x40060020 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CONTINUOUS__OFFSET +CYFLD_SCB_CONTINUOUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CONTINUOUS__SIZE +CYFLD_SCB_CONTINUOUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SELECT_PRECEDE__OFFSET +CYFLD_SCB_SELECT_PRECEDE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SELECT_PRECEDE__SIZE +CYFLD_SCB_SELECT_PRECEDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPHA__OFFSET +CYFLD_SCB_CPHA__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPHA__SIZE +CYFLD_SCB_CPHA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPOL__OFFSET +CYFLD_SCB_CPOL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPOL__SIZE +CYFLD_SCB_CPOL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET +CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LATE_MISO_SAMPLE__SIZE +CYFLD_SCB_LATE_MISO_SAMPLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOOPBACK__OFFSET +CYFLD_SCB_LOOPBACK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOOPBACK__SIZE +CYFLD_SCB_LOOPBACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_SELECT__OFFSET +CYFLD_SCB_SLAVE_SELECT__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_SELECT__SIZE +CYFLD_SCB_SLAVE_SELECT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASTER_MODE__OFFSET +CYFLD_SCB_MASTER_MODE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASTER_MODE__SIZE +CYFLD_SCB_MASTER_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_SPI_STATUS +CYREG_SCB0_SPI_STATUS EQU 0x40060024 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BUS_BUSY__OFFSET +CYFLD_SCB_BUS_BUSY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BUS_BUSY__SIZE +CYFLD_SCB_BUS_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_ADDR__OFFSET +CYFLD_SCB_EZ_ADDR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_ADDR__SIZE +CYFLD_SCB_EZ_ADDR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_CTRL +CYREG_SCB0_UART_CTRL EQU 0x40060040 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_TX_CTRL +CYREG_SCB0_UART_TX_CTRL EQU 0x40060044 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_STOP_BITS__OFFSET +CYFLD_SCB_STOP_BITS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_STOP_BITS__SIZE +CYFLD_SCB_STOP_BITS__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY__OFFSET +CYFLD_SCB_PARITY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY__SIZE +CYFLD_SCB_PARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ENABLED__OFFSET +CYFLD_SCB_PARITY_ENABLED__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ENABLED__SIZE +CYFLD_SCB_PARITY_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RETRY_ON_NACK__OFFSET +CYFLD_SCB_RETRY_ON_NACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RETRY_ON_NACK__SIZE +CYFLD_SCB_RETRY_ON_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_RX_CTRL +CYREG_SCB0_UART_RX_CTRL EQU 0x40060048 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_POLARITY__OFFSET +CYFLD_SCB_POLARITY__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_POLARITY__SIZE +CYFLD_SCB_POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET +CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE +CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET +CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE +CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MP_MODE__OFFSET +CYFLD_SCB_MP_MODE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MP_MODE__SIZE +CYFLD_SCB_MP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LIN_MODE__OFFSET +CYFLD_SCB_LIN_MODE__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LIN_MODE__SIZE +CYFLD_SCB_LIN_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SKIP_START__OFFSET +CYFLD_SCB_SKIP_START__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SKIP_START__SIZE +CYFLD_SCB_SKIP_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_WIDTH__OFFSET +CYFLD_SCB_BREAK_WIDTH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_WIDTH__SIZE +CYFLD_SCB_BREAK_WIDTH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_RX_STATUS +CYREG_SCB0_UART_RX_STATUS EQU 0x4006004c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BR_COUNTER__OFFSET +CYFLD_SCB_BR_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BR_COUNTER__SIZE +CYFLD_SCB_BR_COUNTER__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_CTRL +CYREG_SCB0_I2C_CTRL EQU 0x40060060 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_HIGH_PHASE_OVS__OFFSET +CYFLD_SCB_HIGH_PHASE_OVS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_HIGH_PHASE_OVS__SIZE +CYFLD_SCB_HIGH_PHASE_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOW_PHASE_OVS__OFFSET +CYFLD_SCB_LOW_PHASE_OVS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOW_PHASE_OVS__SIZE +CYFLD_SCB_LOW_PHASE_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READY_DATA_ACK__OFFSET +CYFLD_SCB_M_READY_DATA_ACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READY_DATA_ACK__SIZE +CYFLD_SCB_M_READY_DATA_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET +CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE +CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_GENERAL_IGNORE__OFFSET +CYFLD_SCB_S_GENERAL_IGNORE__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_GENERAL_IGNORE__SIZE +CYFLD_SCB_S_GENERAL_IGNORE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_ADDR_ACK__OFFSET +CYFLD_SCB_S_READY_ADDR_ACK__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_ADDR_ACK__SIZE +CYFLD_SCB_S_READY_ADDR_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_DATA_ACK__OFFSET +CYFLD_SCB_S_READY_DATA_ACK__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_DATA_ACK__SIZE +CYFLD_SCB_S_READY_DATA_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET +CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE +CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET +CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE +CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_MODE__OFFSET +CYFLD_SCB_SLAVE_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_MODE__SIZE +CYFLD_SCB_SLAVE_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_STATUS +CYREG_SCB0_I2C_STATUS EQU 0x40060064 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READ__OFFSET +CYFLD_SCB_S_READ__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READ__SIZE +CYFLD_SCB_S_READ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READ__OFFSET +CYFLD_SCB_M_READ__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READ__SIZE +CYFLD_SCB_M_READ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_M_CMD +CYREG_SCB0_I2C_M_CMD EQU 0x40060068 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START__OFFSET +CYFLD_SCB_M_START__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START__SIZE +CYFLD_SCB_M_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START_ON_IDLE__OFFSET +CYFLD_SCB_M_START_ON_IDLE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START_ON_IDLE__SIZE +CYFLD_SCB_M_START_ON_IDLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_ACK__OFFSET +CYFLD_SCB_M_ACK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_ACK__SIZE +CYFLD_SCB_M_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NACK__OFFSET +CYFLD_SCB_M_NACK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NACK__SIZE +CYFLD_SCB_M_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_STOP__OFFSET +CYFLD_SCB_M_STOP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_STOP__SIZE +CYFLD_SCB_M_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_S_CMD +CYREG_SCB0_I2C_S_CMD EQU 0x4006006c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_ACK__OFFSET +CYFLD_SCB_S_ACK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_ACK__SIZE +CYFLD_SCB_S_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NACK__OFFSET +CYFLD_SCB_S_NACK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NACK__SIZE +CYFLD_SCB_S_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_CFG +CYREG_SCB0_I2C_CFG EQU 0x40060070 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HYS__OFFSET +CYFLD_SCB_SDA_FILT_HYS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HYS__SIZE +CYFLD_SCB_SDA_FILT_HYS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_TRIM__OFFSET +CYFLD_SCB_SDA_FILT_TRIM__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_TRIM__SIZE +CYFLD_SCB_SDA_FILT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HYS__OFFSET +CYFLD_SCB_SCL_FILT_HYS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HYS__SIZE +CYFLD_SCB_SCL_FILT_HYS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_TRIM__OFFSET +CYFLD_SCB_SCL_FILT_TRIM__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_TRIM__SIZE +CYFLD_SCB_SCL_FILT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET +CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE +CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET +CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE +CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HS__OFFSET +CYFLD_SCB_SDA_FILT_HS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_HS__SIZE +CYFLD_SCB_SDA_FILT_HS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_ENABLED__OFFSET +CYFLD_SCB_SDA_FILT_ENABLED__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_ENABLED__SIZE +CYFLD_SCB_SDA_FILT_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HS__OFFSET +CYFLD_SCB_SCL_FILT_HS__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_HS__SIZE +CYFLD_SCB_SCL_FILT_HS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_ENABLED__OFFSET +CYFLD_SCB_SCL_FILT_ENABLED__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_FILT_ENABLED__SIZE +CYFLD_SCB_SCL_FILT_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET +CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_HS__SIZE +CYFLD_SCB_SDA_FILT_OUT_HS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET +CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE +CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_BIST_CONTROL +CYREG_SCB0_BIST_CONTROL EQU 0x40060100 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_ADDR__OFFSET +CYFLD_SCB_RAM_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_ADDR__SIZE +CYFLD_SCB_RAM_ADDR__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP1__OFFSET +CYFLD_SCB_RAM_OP1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP1__SIZE +CYFLD_SCB_RAM_OP1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP2__OFFSET +CYFLD_SCB_RAM_OP2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP2__SIZE +CYFLD_SCB_RAM_OP2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP3__OFFSET +CYFLD_SCB_RAM_OP3__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP3__SIZE +CYFLD_SCB_RAM_OP3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP4__OFFSET +CYFLD_SCB_RAM_OP4__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OP4__SIZE +CYFLD_SCB_RAM_OP4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OPCNT__OFFSET +CYFLD_SCB_RAM_OPCNT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_OPCNT__SIZE +CYFLD_SCB_RAM_OPCNT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_PREADR__OFFSET +CYFLD_SCB_RAM_PREADR__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_PREADR__SIZE +CYFLD_SCB_RAM_PREADR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_WORD__OFFSET +CYFLD_SCB_RAM_WORD__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_WORD__SIZE +CYFLD_SCB_RAM_WORD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_FAIL__OFFSET +CYFLD_SCB_RAM_FAIL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_FAIL__SIZE +CYFLD_SCB_RAM_FAIL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_GO__OFFSET +CYFLD_SCB_RAM_GO__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_GO__SIZE +CYFLD_SCB_RAM_GO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_BIST_DATA +CYREG_SCB0_BIST_DATA EQU 0x40060104 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_DATA__OFFSET +CYFLD_SCB_RAM_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RAM_DATA__SIZE +CYFLD_SCB_RAM_DATA__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_CTRL +CYREG_SCB0_TX_CTRL EQU 0x40060200 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA_WIDTH__OFFSET +CYFLD_SCB_DATA_WIDTH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA_WIDTH__SIZE +CYFLD_SCB_DATA_WIDTH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MSB_FIRST__OFFSET +CYFLD_SCB_MSB_FIRST__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MSB_FIRST__SIZE +CYFLD_SCB_MSB_FIRST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_CTRL +CYREG_SCB0_TX_FIFO_CTRL EQU 0x40060204 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER_LEVEL__OFFSET +CYFLD_SCB_TRIGGER_LEVEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER_LEVEL__SIZE +CYFLD_SCB_TRIGGER_LEVEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CLEAR__OFFSET +CYFLD_SCB_CLEAR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CLEAR__SIZE +CYFLD_SCB_CLEAR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FREEZE__OFFSET +CYFLD_SCB_FREEZE__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FREEZE__SIZE +CYFLD_SCB_FREEZE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_STATUS +CYREG_SCB0_TX_FIFO_STATUS EQU 0x40060208 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_USED__OFFSET +CYFLD_SCB_USED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_USED__SIZE +CYFLD_SCB_USED__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SR_VALID__OFFSET +CYFLD_SCB_SR_VALID__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SR_VALID__SIZE +CYFLD_SCB_SR_VALID__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RD_PTR__OFFSET +CYFLD_SCB_RD_PTR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RD_PTR__SIZE +CYFLD_SCB_RD_PTR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WR_PTR__OFFSET +CYFLD_SCB_WR_PTR__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WR_PTR__SIZE +CYFLD_SCB_WR_PTR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_WR +CYREG_SCB0_TX_FIFO_WR EQU 0x40060240 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA__OFFSET +CYFLD_SCB_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA__SIZE +CYFLD_SCB_DATA__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_CTRL +CYREG_SCB0_RX_CTRL EQU 0x40060300 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MEDIAN__OFFSET +CYFLD_SCB_MEDIAN__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MEDIAN__SIZE +CYFLD_SCB_MEDIAN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_CTRL +CYREG_SCB0_RX_FIFO_CTRL EQU 0x40060304 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_STATUS +CYREG_SCB0_RX_FIFO_STATUS EQU 0x40060308 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_MATCH +CYREG_SCB0_RX_MATCH EQU 0x40060310 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR__OFFSET +CYFLD_SCB_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR__SIZE +CYFLD_SCB_ADDR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASK__OFFSET +CYFLD_SCB_MASK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASK__SIZE +CYFLD_SCB_MASK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_RD +CYREG_SCB0_RX_FIFO_RD EQU 0x40060340 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_RD_SILENT +CYREG_SCB0_RX_FIFO_RD_SILENT EQU 0x40060344 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA00 +CYREG_SCB0_EZ_DATA00 EQU 0x40060400 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_DATA__OFFSET +CYFLD_SCB_EZ_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_DATA__SIZE +CYFLD_SCB_EZ_DATA__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA01 +CYREG_SCB0_EZ_DATA01 EQU 0x40060404 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA02 +CYREG_SCB0_EZ_DATA02 EQU 0x40060408 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA03 +CYREG_SCB0_EZ_DATA03 EQU 0x4006040c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA04 +CYREG_SCB0_EZ_DATA04 EQU 0x40060410 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA05 +CYREG_SCB0_EZ_DATA05 EQU 0x40060414 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA06 +CYREG_SCB0_EZ_DATA06 EQU 0x40060418 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA07 +CYREG_SCB0_EZ_DATA07 EQU 0x4006041c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA08 +CYREG_SCB0_EZ_DATA08 EQU 0x40060420 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA09 +CYREG_SCB0_EZ_DATA09 EQU 0x40060424 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA10 +CYREG_SCB0_EZ_DATA10 EQU 0x40060428 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA11 +CYREG_SCB0_EZ_DATA11 EQU 0x4006042c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA12 +CYREG_SCB0_EZ_DATA12 EQU 0x40060430 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA13 +CYREG_SCB0_EZ_DATA13 EQU 0x40060434 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA14 +CYREG_SCB0_EZ_DATA14 EQU 0x40060438 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA15 +CYREG_SCB0_EZ_DATA15 EQU 0x4006043c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA16 +CYREG_SCB0_EZ_DATA16 EQU 0x40060440 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA17 +CYREG_SCB0_EZ_DATA17 EQU 0x40060444 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA18 +CYREG_SCB0_EZ_DATA18 EQU 0x40060448 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA19 +CYREG_SCB0_EZ_DATA19 EQU 0x4006044c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA20 +CYREG_SCB0_EZ_DATA20 EQU 0x40060450 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA21 +CYREG_SCB0_EZ_DATA21 EQU 0x40060454 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA22 +CYREG_SCB0_EZ_DATA22 EQU 0x40060458 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA23 +CYREG_SCB0_EZ_DATA23 EQU 0x4006045c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA24 +CYREG_SCB0_EZ_DATA24 EQU 0x40060460 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA25 +CYREG_SCB0_EZ_DATA25 EQU 0x40060464 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA26 +CYREG_SCB0_EZ_DATA26 EQU 0x40060468 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA27 +CYREG_SCB0_EZ_DATA27 EQU 0x4006046c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA28 +CYREG_SCB0_EZ_DATA28 EQU 0x40060470 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA29 +CYREG_SCB0_EZ_DATA29 EQU 0x40060474 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA30 +CYREG_SCB0_EZ_DATA30 EQU 0x40060478 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA31 +CYREG_SCB0_EZ_DATA31 EQU 0x4006047c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_CAUSE +CYREG_SCB0_INTR_CAUSE EQU 0x40060e00 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M__OFFSET +CYFLD_SCB_M__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M__SIZE +CYFLD_SCB_M__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S__OFFSET +CYFLD_SCB_S__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S__SIZE +CYFLD_SCB_S__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TX__OFFSET +CYFLD_SCB_TX__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TX__SIZE +CYFLD_SCB_TX__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RX__OFFSET +CYFLD_SCB_RX__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RX__SIZE +CYFLD_SCB_RX__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC__OFFSET +CYFLD_SCB_I2C_EC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC__SIZE +CYFLD_SCB_I2C_EC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC__OFFSET +CYFLD_SCB_SPI_EC__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC__SIZE +CYFLD_SCB_SPI_EC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC +CYREG_SCB0_INTR_I2C_EC EQU 0x40060e80 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WAKE_UP__OFFSET +CYFLD_SCB_WAKE_UP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WAKE_UP__SIZE +CYFLD_SCB_WAKE_UP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_STOP__OFFSET +CYFLD_SCB_EZ_STOP__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_STOP__SIZE +CYFLD_SCB_EZ_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_WRITE_STOP__OFFSET +CYFLD_SCB_EZ_WRITE_STOP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_WRITE_STOP__SIZE +CYFLD_SCB_EZ_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC_MASK +CYREG_SCB0_INTR_I2C_EC_MASK EQU 0x40060e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC_MASKED +CYREG_SCB0_INTR_I2C_EC_MASKED EQU 0x40060e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC +CYREG_SCB0_INTR_SPI_EC EQU 0x40060ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC_MASK +CYREG_SCB0_INTR_SPI_EC_MASK EQU 0x40060ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC_MASKED +CYREG_SCB0_INTR_SPI_EC_MASKED EQU 0x40060ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M +CYREG_SCB0_INTR_M EQU 0x40060f00 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ARB_LOST__OFFSET +CYFLD_SCB_I2C_ARB_LOST__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ARB_LOST__SIZE +CYFLD_SCB_I2C_ARB_LOST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_NACK__OFFSET +CYFLD_SCB_I2C_NACK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_NACK__SIZE +CYFLD_SCB_I2C_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ACK__OFFSET +CYFLD_SCB_I2C_ACK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ACK__SIZE +CYFLD_SCB_I2C_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_STOP__OFFSET +CYFLD_SCB_I2C_STOP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_STOP__SIZE +CYFLD_SCB_I2C_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_BUS_ERROR__OFFSET +CYFLD_SCB_I2C_BUS_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_BUS_ERROR__SIZE +CYFLD_SCB_I2C_BUS_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_DONE__OFFSET +CYFLD_SCB_SPI_DONE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_DONE__SIZE +CYFLD_SCB_SPI_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_SET +CYREG_SCB0_INTR_M_SET EQU 0x40060f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_MASK +CYREG_SCB0_INTR_M_MASK EQU 0x40060f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_MASKED +CYREG_SCB0_INTR_M_MASKED EQU 0x40060f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S +CYREG_SCB0_INTR_S EQU 0x40060f40 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_WRITE_STOP__OFFSET +CYFLD_SCB_I2C_WRITE_STOP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_WRITE_STOP__SIZE +CYFLD_SCB_I2C_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_START__OFFSET +CYFLD_SCB_I2C_START__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_START__SIZE +CYFLD_SCB_I2C_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ADDR_MATCH__OFFSET +CYFLD_SCB_I2C_ADDR_MATCH__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ADDR_MATCH__SIZE +CYFLD_SCB_I2C_ADDR_MATCH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_GENERAL__OFFSET +CYFLD_SCB_I2C_GENERAL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_GENERAL__SIZE +CYFLD_SCB_I2C_GENERAL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET +CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE +CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_STOP__OFFSET +CYFLD_SCB_SPI_EZ_STOP__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_STOP__SIZE +CYFLD_SCB_SPI_EZ_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_BUS_ERROR__OFFSET +CYFLD_SCB_SPI_BUS_ERROR__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_BUS_ERROR__SIZE +CYFLD_SCB_SPI_BUS_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_SET +CYREG_SCB0_INTR_S_SET EQU 0x40060f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_MASK +CYREG_SCB0_INTR_S_MASK EQU 0x40060f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_MASKED +CYREG_SCB0_INTR_S_MASKED EQU 0x40060f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX +CYREG_SCB0_INTR_TX EQU 0x40060f80 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER__OFFSET +CYFLD_SCB_TRIGGER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER__SIZE +CYFLD_SCB_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_FULL__OFFSET +CYFLD_SCB_NOT_FULL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_FULL__SIZE +CYFLD_SCB_NOT_FULL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EMPTY__OFFSET +CYFLD_SCB_EMPTY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EMPTY__SIZE +CYFLD_SCB_EMPTY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVERFLOW__OFFSET +CYFLD_SCB_OVERFLOW__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVERFLOW__SIZE +CYFLD_SCB_OVERFLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UNDERFLOW__OFFSET +CYFLD_SCB_UNDERFLOW__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UNDERFLOW__SIZE +CYFLD_SCB_UNDERFLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCKED__OFFSET +CYFLD_SCB_BLOCKED__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCKED__SIZE +CYFLD_SCB_BLOCKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_NACK__OFFSET +CYFLD_SCB_UART_NACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_NACK__SIZE +CYFLD_SCB_UART_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_DONE__OFFSET +CYFLD_SCB_UART_DONE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_DONE__SIZE +CYFLD_SCB_UART_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_ARB_LOST__OFFSET +CYFLD_SCB_UART_ARB_LOST__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_ARB_LOST__SIZE +CYFLD_SCB_UART_ARB_LOST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_SET +CYREG_SCB0_INTR_TX_SET EQU 0x40060f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_MASK +CYREG_SCB0_INTR_TX_MASK EQU 0x40060f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_MASKED +CYREG_SCB0_INTR_TX_MASKED EQU 0x40060f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX +CYREG_SCB0_INTR_RX EQU 0x40060fc0 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_EMPTY__OFFSET +CYFLD_SCB_NOT_EMPTY__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_EMPTY__SIZE +CYFLD_SCB_NOT_EMPTY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FULL__OFFSET +CYFLD_SCB_FULL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FULL__SIZE +CYFLD_SCB_FULL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FRAME_ERROR__OFFSET +CYFLD_SCB_FRAME_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FRAME_ERROR__SIZE +CYFLD_SCB_FRAME_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ERROR__OFFSET +CYFLD_SCB_PARITY_ERROR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ERROR__SIZE +CYFLD_SCB_PARITY_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BAUD_DETECT__OFFSET +CYFLD_SCB_BAUD_DETECT__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BAUD_DETECT__SIZE +CYFLD_SCB_BAUD_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_DETECT__OFFSET +CYFLD_SCB_BREAK_DETECT__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_DETECT__SIZE +CYFLD_SCB_BREAK_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_SET +CYREG_SCB0_INTR_RX_SET EQU 0x40060fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_MASK +CYREG_SCB0_INTR_RX_MASK EQU 0x40060fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_MASKED +CYREG_SCB0_INTR_RX_MASKED EQU 0x40060fcc + ENDIF + IF :LNOT::DEF:CYDEV_SCB1_BASE +CYDEV_SCB1_BASE EQU 0x40070000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB1_SIZE +CYDEV_SCB1_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_CTRL +CYREG_SCB1_CTRL EQU 0x40070000 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_STATUS +CYREG_SCB1_STATUS EQU 0x40070004 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_SPI_CTRL +CYREG_SCB1_SPI_CTRL EQU 0x40070020 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_SPI_STATUS +CYREG_SCB1_SPI_STATUS EQU 0x40070024 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_CTRL +CYREG_SCB1_UART_CTRL EQU 0x40070040 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_TX_CTRL +CYREG_SCB1_UART_TX_CTRL EQU 0x40070044 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_RX_CTRL +CYREG_SCB1_UART_RX_CTRL EQU 0x40070048 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_RX_STATUS +CYREG_SCB1_UART_RX_STATUS EQU 0x4007004c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_CTRL +CYREG_SCB1_I2C_CTRL EQU 0x40070060 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_STATUS +CYREG_SCB1_I2C_STATUS EQU 0x40070064 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_M_CMD +CYREG_SCB1_I2C_M_CMD EQU 0x40070068 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_S_CMD +CYREG_SCB1_I2C_S_CMD EQU 0x4007006c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_CFG +CYREG_SCB1_I2C_CFG EQU 0x40070070 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_BIST_CONTROL +CYREG_SCB1_BIST_CONTROL EQU 0x40070100 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_BIST_DATA +CYREG_SCB1_BIST_DATA EQU 0x40070104 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_CTRL +CYREG_SCB1_TX_CTRL EQU 0x40070200 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_CTRL +CYREG_SCB1_TX_FIFO_CTRL EQU 0x40070204 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_STATUS +CYREG_SCB1_TX_FIFO_STATUS EQU 0x40070208 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_WR +CYREG_SCB1_TX_FIFO_WR EQU 0x40070240 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_CTRL +CYREG_SCB1_RX_CTRL EQU 0x40070300 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_CTRL +CYREG_SCB1_RX_FIFO_CTRL EQU 0x40070304 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_STATUS +CYREG_SCB1_RX_FIFO_STATUS EQU 0x40070308 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_MATCH +CYREG_SCB1_RX_MATCH EQU 0x40070310 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_RD +CYREG_SCB1_RX_FIFO_RD EQU 0x40070340 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_RD_SILENT +CYREG_SCB1_RX_FIFO_RD_SILENT EQU 0x40070344 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA00 +CYREG_SCB1_EZ_DATA00 EQU 0x40070400 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA01 +CYREG_SCB1_EZ_DATA01 EQU 0x40070404 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA02 +CYREG_SCB1_EZ_DATA02 EQU 0x40070408 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA03 +CYREG_SCB1_EZ_DATA03 EQU 0x4007040c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA04 +CYREG_SCB1_EZ_DATA04 EQU 0x40070410 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA05 +CYREG_SCB1_EZ_DATA05 EQU 0x40070414 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA06 +CYREG_SCB1_EZ_DATA06 EQU 0x40070418 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA07 +CYREG_SCB1_EZ_DATA07 EQU 0x4007041c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA08 +CYREG_SCB1_EZ_DATA08 EQU 0x40070420 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA09 +CYREG_SCB1_EZ_DATA09 EQU 0x40070424 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA10 +CYREG_SCB1_EZ_DATA10 EQU 0x40070428 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA11 +CYREG_SCB1_EZ_DATA11 EQU 0x4007042c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA12 +CYREG_SCB1_EZ_DATA12 EQU 0x40070430 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA13 +CYREG_SCB1_EZ_DATA13 EQU 0x40070434 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA14 +CYREG_SCB1_EZ_DATA14 EQU 0x40070438 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA15 +CYREG_SCB1_EZ_DATA15 EQU 0x4007043c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA16 +CYREG_SCB1_EZ_DATA16 EQU 0x40070440 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA17 +CYREG_SCB1_EZ_DATA17 EQU 0x40070444 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA18 +CYREG_SCB1_EZ_DATA18 EQU 0x40070448 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA19 +CYREG_SCB1_EZ_DATA19 EQU 0x4007044c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA20 +CYREG_SCB1_EZ_DATA20 EQU 0x40070450 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA21 +CYREG_SCB1_EZ_DATA21 EQU 0x40070454 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA22 +CYREG_SCB1_EZ_DATA22 EQU 0x40070458 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA23 +CYREG_SCB1_EZ_DATA23 EQU 0x4007045c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA24 +CYREG_SCB1_EZ_DATA24 EQU 0x40070460 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA25 +CYREG_SCB1_EZ_DATA25 EQU 0x40070464 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA26 +CYREG_SCB1_EZ_DATA26 EQU 0x40070468 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA27 +CYREG_SCB1_EZ_DATA27 EQU 0x4007046c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA28 +CYREG_SCB1_EZ_DATA28 EQU 0x40070470 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA29 +CYREG_SCB1_EZ_DATA29 EQU 0x40070474 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA30 +CYREG_SCB1_EZ_DATA30 EQU 0x40070478 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA31 +CYREG_SCB1_EZ_DATA31 EQU 0x4007047c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_CAUSE +CYREG_SCB1_INTR_CAUSE EQU 0x40070e00 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC +CYREG_SCB1_INTR_I2C_EC EQU 0x40070e80 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC_MASK +CYREG_SCB1_INTR_I2C_EC_MASK EQU 0x40070e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC_MASKED +CYREG_SCB1_INTR_I2C_EC_MASKED EQU 0x40070e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC +CYREG_SCB1_INTR_SPI_EC EQU 0x40070ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC_MASK +CYREG_SCB1_INTR_SPI_EC_MASK EQU 0x40070ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC_MASKED +CYREG_SCB1_INTR_SPI_EC_MASKED EQU 0x40070ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M +CYREG_SCB1_INTR_M EQU 0x40070f00 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_SET +CYREG_SCB1_INTR_M_SET EQU 0x40070f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_MASK +CYREG_SCB1_INTR_M_MASK EQU 0x40070f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_MASKED +CYREG_SCB1_INTR_M_MASKED EQU 0x40070f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S +CYREG_SCB1_INTR_S EQU 0x40070f40 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_SET +CYREG_SCB1_INTR_S_SET EQU 0x40070f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_MASK +CYREG_SCB1_INTR_S_MASK EQU 0x40070f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_MASKED +CYREG_SCB1_INTR_S_MASKED EQU 0x40070f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX +CYREG_SCB1_INTR_TX EQU 0x40070f80 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_SET +CYREG_SCB1_INTR_TX_SET EQU 0x40070f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_MASK +CYREG_SCB1_INTR_TX_MASK EQU 0x40070f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_MASKED +CYREG_SCB1_INTR_TX_MASKED EQU 0x40070f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX +CYREG_SCB1_INTR_RX EQU 0x40070fc0 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_SET +CYREG_SCB1_INTR_RX_SET EQU 0x40070fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_MASK +CYREG_SCB1_INTR_RX_MASK EQU 0x40070fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_MASKED +CYREG_SCB1_INTR_RX_MASKED EQU 0x40070fcc + ENDIF + IF :LNOT::DEF:CYDEV_CSD_BASE +CYDEV_CSD_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_CSD_SIZE +CYDEV_CSD_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CSD_ID +CYREG_CSD_ID EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ID__OFFSET +CYFLD_CSD_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ID__SIZE +CYFLD_CSD_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REVISION__OFFSET +CYFLD_CSD_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REVISION__SIZE +CYFLD_CSD_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CSD_CONFIG +CYREG_CSD_CONFIG EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SAMPLE_EN__OFFSET +CYFLD_CSD_DSI_SAMPLE_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SAMPLE_EN__SIZE +CYFLD_CSD_DSI_SAMPLE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE_SYNC__OFFSET +CYFLD_CSD_SAMPLE_SYNC__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE_SYNC__SIZE +CYFLD_CSD_SAMPLE_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_CLEAR__OFFSET +CYFLD_CSD_PRS_CLEAR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_CLEAR__SIZE +CYFLD_CSD_PRS_CLEAR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_SELECT__OFFSET +CYFLD_CSD_PRS_SELECT__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_SELECT__SIZE +CYFLD_CSD_PRS_SELECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_SELECT_DIV2 +CYVAL_CSD_PRS_SELECT_DIV2 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_SELECT_PRS +CYVAL_CSD_PRS_SELECT_PRS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_12_8__OFFSET +CYFLD_CSD_PRS_12_8__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PRS_12_8__SIZE +CYFLD_CSD_PRS_12_8__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_12_8_8B +CYVAL_CSD_PRS_12_8_8B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PRS_12_8_12B +CYVAL_CSD_PRS_12_8_12B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SENSE_EN__OFFSET +CYFLD_CSD_DSI_SENSE_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SENSE_EN__SIZE +CYFLD_CSD_DSI_SENSE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SHIELD_DELAY__OFFSET +CYFLD_CSD_SHIELD_DELAY__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SHIELD_DELAY__SIZE +CYFLD_CSD_SHIELD_DELAY__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_BW__OFFSET +CYFLD_CSD_SENSE_COMP_BW__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_BW__SIZE +CYFLD_CSD_SENSE_COMP_BW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_COMP_BW_LOW +CYVAL_CSD_SENSE_COMP_BW_LOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_COMP_BW_HIGH +CYVAL_CSD_SENSE_COMP_BW_HIGH EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_EN__OFFSET +CYFLD_CSD_SENSE_EN__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_EN__SIZE +CYFLD_CSD_SENSE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_EN__OFFSET +CYFLD_CSD_REFBUF_EN__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_EN__SIZE +CYFLD_CSD_REFBUF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_MODE__OFFSET +CYFLD_CSD_COMP_MODE__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_MODE__SIZE +CYFLD_CSD_COMP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_MODE_CHARGE_BUF +CYVAL_CSD_COMP_MODE_CHARGE_BUF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_MODE_CHARGE_IO +CYVAL_CSD_COMP_MODE_CHARGE_IO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_PIN__OFFSET +CYFLD_CSD_COMP_PIN__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_PIN__SIZE +CYFLD_CSD_COMP_PIN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_PIN_CHANNEL1 +CYVAL_CSD_COMP_PIN_CHANNEL1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_PIN_CHANNEL2 +CYVAL_CSD_COMP_PIN_CHANNEL2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY__OFFSET +CYFLD_CSD_POLARITY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY__SIZE +CYFLD_CSD_POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_VSSIO +CYVAL_CSD_POLARITY_VSSIO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_VDDIO +CYVAL_CSD_POLARITY_VDDIO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY2__OFFSET +CYFLD_CSD_POLARITY2__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY2__SIZE +CYFLD_CSD_POLARITY2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY2_VSSIO +CYVAL_CSD_POLARITY2_VSSIO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY2_VDDIO +CYVAL_CSD_POLARITY2_VDDIO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_MUTUAL_CAP__OFFSET +CYFLD_CSD_MUTUAL_CAP__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_MUTUAL_CAP__SIZE +CYFLD_CSD_MUTUAL_CAP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_MUTUAL_CAP_SELFCAP +CYVAL_CSD_MUTUAL_CAP_SELFCAP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_MUTUAL_CAP_MUTUALCAP +CYVAL_CSD_MUTUAL_CAP_MUTUALCAP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_EN__OFFSET +CYFLD_CSD_SENSE_COMP_EN__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_COMP_EN__SIZE +CYFLD_CSD_SENSE_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REBUF_OUTSEL__OFFSET +CYFLD_CSD_REBUF_OUTSEL__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REBUF_OUTSEL__SIZE +CYFLD_CSD_REBUF_OUTSEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REBUF_OUTSEL_AMUXA +CYVAL_CSD_REBUF_OUTSEL_AMUXA EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REBUF_OUTSEL_AMUXB +CYVAL_CSD_REBUF_OUTSEL_AMUXB EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_INSEL__OFFSET +CYFLD_CSD_SENSE_INSEL__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_INSEL__SIZE +CYFLD_CSD_SENSE_INSEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 +CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA +CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_DRV__OFFSET +CYFLD_CSD_REFBUF_DRV__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFBUF_DRV__SIZE +CYFLD_CSD_REFBUF_DRV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_OFF +CYVAL_CSD_REFBUF_DRV_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_DRV_1 +CYVAL_CSD_REFBUF_DRV_DRV_1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_DRV_2 +CYVAL_CSD_REFBUF_DRV_DRV_2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFBUF_DRV_DRV_3 +CYVAL_CSD_REFBUF_DRV_DRV_3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTSEL__OFFSET +CYFLD_CSD_DDFTSEL__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTSEL__SIZE +CYFLD_CSD_DDFTSEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_NORMAL +CYVAL_CSD_DDFTSEL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_CSD_SENSE +CYVAL_CSD_DDFTSEL_CSD_SENSE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_CSD_SHIELD +CYVAL_CSD_DDFTSEL_CSD_SHIELD EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_CLK_SAMPLE +CYVAL_CSD_DDFTSEL_CLK_SAMPLE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTSEL_COMP_OUT +CYVAL_CSD_DDFTSEL_COMP_OUT EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADFTEN__OFFSET +CYFLD_CSD_ADFTEN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADFTEN__SIZE +CYFLD_CSD_ADFTEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTCOMP__OFFSET +CYFLD_CSD_DDFTCOMP__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DDFTCOMP__SIZE +CYFLD_CSD_DDFTCOMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTCOMP_REFBUFCOMP +CYVAL_CSD_DDFTCOMP_REFBUFCOMP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DDFTCOMP_SENSECOMP +CYVAL_CSD_DDFTCOMP_SENSECOMP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ENABLE__OFFSET +CYFLD_CSD_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ENABLE__SIZE +CYFLD_CSD_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_IDAC +CYREG_CSD_IDAC EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1__OFFSET +CYFLD_CSD_IDAC1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1__SIZE +CYFLD_CSD_IDAC1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_MODE__OFFSET +CYFLD_CSD_IDAC1_MODE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_MODE__SIZE +CYFLD_CSD_IDAC1_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_OFF +CYVAL_CSD_IDAC1_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_FIXED +CYVAL_CSD_IDAC1_MODE_FIXED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_VARIABLE +CYVAL_CSD_IDAC1_MODE_VARIABLE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_MODE_DSI +CYVAL_CSD_IDAC1_MODE_DSI EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_RANGE__OFFSET +CYFLD_CSD_IDAC1_RANGE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_RANGE__SIZE +CYFLD_CSD_IDAC1_RANGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_RANGE_4X +CYVAL_CSD_IDAC1_RANGE_4X EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC1_RANGE_8X +CYVAL_CSD_IDAC1_RANGE_8X EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2__OFFSET +CYFLD_CSD_IDAC2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2__SIZE +CYFLD_CSD_IDAC2__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_MODE__OFFSET +CYFLD_CSD_IDAC2_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_MODE__SIZE +CYFLD_CSD_IDAC2_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_OFF +CYVAL_CSD_IDAC2_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_FIXED +CYVAL_CSD_IDAC2_MODE_FIXED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_VARIABLE +CYVAL_CSD_IDAC2_MODE_VARIABLE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_MODE_DSI +CYVAL_CSD_IDAC2_MODE_DSI EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_RANGE__OFFSET +CYFLD_CSD_IDAC2_RANGE__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_RANGE__SIZE +CYFLD_CSD_IDAC2_RANGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_RANGE_4X +CYVAL_CSD_IDAC2_RANGE_4X EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_IDAC2_RANGE_8X +CYVAL_CSD_IDAC2_RANGE_8X EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FEEDBACK_MODE__OFFSET +CYFLD_CSD_FEEDBACK_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FEEDBACK_MODE__SIZE +CYFLD_CSD_FEEDBACK_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FEEDBACK_MODE_FLOP +CYVAL_CSD_FEEDBACK_MODE_FLOP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FEEDBACK_MODE_COMP +CYVAL_CSD_FEEDBACK_MODE_COMP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_COUNTER +CYREG_CSD_COUNTER EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COUNTER__OFFSET +CYFLD_CSD_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COUNTER__SIZE +CYFLD_CSD_COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PERIOD__OFFSET +CYFLD_CSD_PERIOD__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PERIOD__SIZE +CYFLD_CSD_PERIOD__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CSD_STATUS +CYREG_CSD_STATUS EQU 0x40080010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_CHARGE__OFFSET +CYFLD_CSD_CSD_CHARGE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_CHARGE__SIZE +CYFLD_CSD_CSD_CHARGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_SENSE__OFFSET +CYFLD_CSD_CSD_SENSE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_SENSE__SIZE +CYFLD_CSD_CSD_SENSE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_OUT__OFFSET +CYFLD_CSD_COMP_OUT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_COMP_OUT__SIZE +CYFLD_CSD_COMP_OUT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_OUT_C_LT_VREF +CYVAL_CSD_COMP_OUT_C_LT_VREF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_COMP_OUT_C_GT_VREF +CYVAL_CSD_COMP_OUT_C_GT_VREF EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE__OFFSET +CYFLD_CSD_SAMPLE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE__SIZE +CYFLD_CSD_SAMPLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR +CYREG_CSD_INTR EQU 0x40080014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD__OFFSET +CYFLD_CSD_CSD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD__SIZE +CYFLD_CSD_CSD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR_SET +CYREG_CSD_INTR_SET EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_CSD_TRIM1 +CYREG_CSD_TRIM1 EQU 0x4008ff00 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET +CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SRC_TRIM__SIZE +CYFLD_CSD_IDAC1_SRC_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET +CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SRC_TRIM__SIZE +CYFLD_CSD_IDAC2_SRC_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CSD_TRIM2 +CYREG_CSD_TRIM2 EQU 0x4008ff04 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET +CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC1_SNK_TRIM__SIZE +CYFLD_CSD_IDAC1_SNK_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET +CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_IDAC2_SNK_TRIM__SIZE +CYFLD_CSD_IDAC2_SNK_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_LCD_BASE +CYDEV_LCD_BASE EQU 0x40090000 + ENDIF + IF :LNOT::DEF:CYDEV_LCD_SIZE +CYDEV_LCD_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_LCD_ID +CYREG_LCD_ID EQU 0x40090000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_ID__OFFSET +CYFLD_LCD_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_ID__SIZE +CYFLD_LCD_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_REVISION__OFFSET +CYFLD_LCD_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_REVISION__SIZE +CYFLD_LCD_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DIVIDER +CYREG_LCD_DIVIDER EQU 0x40090004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_SUBFR_DIV__OFFSET +CYFLD_LCD_SUBFR_DIV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_SUBFR_DIV__SIZE +CYFLD_LCD_SUBFR_DIV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DEAD_DIV__OFFSET +CYFLD_LCD_DEAD_DIV__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DEAD_DIV__SIZE +CYFLD_LCD_DEAD_DIV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LCD_CONTROL +CYREG_LCD_CONTROL EQU 0x40090008 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN__OFFSET +CYFLD_LCD_LS_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN__SIZE +CYFLD_LCD_LS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_HS_EN__OFFSET +CYFLD_LCD_HS_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_HS_EN__SIZE +CYFLD_LCD_HS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LCD_MODE__OFFSET +CYFLD_LCD_LCD_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LCD_MODE__SIZE +CYFLD_LCD_LCD_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_LCD_MODE_LS +CYVAL_LCD_LCD_MODE_LS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_LCD_MODE_HS +CYVAL_LCD_LCD_MODE_HS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_TYPE__OFFSET +CYFLD_LCD_TYPE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_TYPE__SIZE +CYFLD_LCD_TYPE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_TYPE_A +CYVAL_LCD_TYPE_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_TYPE_B +CYVAL_LCD_TYPE_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_OP_MODE__OFFSET +CYFLD_LCD_OP_MODE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_OP_MODE__SIZE +CYFLD_LCD_OP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_OP_MODE_PWM +CYVAL_LCD_OP_MODE_PWM EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_OP_MODE_CORRELATION +CYVAL_LCD_OP_MODE_CORRELATION EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_BIAS__OFFSET +CYFLD_LCD_BIAS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_BIAS__SIZE +CYFLD_LCD_BIAS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_HALF +CYVAL_LCD_BIAS_HALF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_THIRD +CYVAL_LCD_BIAS_THIRD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_FOURTH +CYVAL_LCD_BIAS_FOURTH EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_FIFTH +CYVAL_LCD_BIAS_FIFTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_COM_NUM__OFFSET +CYFLD_LCD_COM_NUM__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_COM_NUM__SIZE +CYFLD_LCD_COM_NUM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN_STAT__OFFSET +CYFLD_LCD_LS_EN_STAT__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN_STAT__SIZE +CYFLD_LCD_LS_EN_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA00 +CYREG_LCD_DATA00 EQU 0x40090100 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DATA__OFFSET +CYFLD_LCD_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DATA__SIZE +CYFLD_LCD_DATA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA01 +CYREG_LCD_DATA01 EQU 0x40090104 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA02 +CYREG_LCD_DATA02 EQU 0x40090108 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA03 +CYREG_LCD_DATA03 EQU 0x4009010c + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA04 +CYREG_LCD_DATA04 EQU 0x40090110 + ENDIF + IF :LNOT::DEF:CYDEV_LPCOMP_BASE +CYDEV_LPCOMP_BASE EQU 0x400a0000 + ENDIF + IF :LNOT::DEF:CYDEV_LPCOMP_SIZE +CYDEV_LPCOMP_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_ID +CYREG_LPCOMP_ID EQU 0x400a0000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ID__OFFSET +CYFLD_LPCOMP_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ID__SIZE +CYFLD_LPCOMP_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_REVISION__OFFSET +CYFLD_LPCOMP_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_REVISION__SIZE +CYFLD_LPCOMP_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_CONFIG +CYREG_LPCOMP_CONFIG EQU 0x400a0004 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE1__OFFSET +CYFLD_LPCOMP_MODE1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE1__SIZE +CYFLD_LPCOMP_MODE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_SLOW +CYVAL_LPCOMP_MODE1_SLOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_FAST +CYVAL_LPCOMP_MODE1_FAST EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_ULP +CYVAL_LPCOMP_MODE1_ULP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST1__OFFSET +CYFLD_LPCOMP_HYST1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST1__SIZE +CYFLD_LPCOMP_HYST1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER1__OFFSET +CYFLD_LPCOMP_FILTER1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER1__SIZE +CYFLD_LPCOMP_FILTER1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE1__OFFSET +CYFLD_LPCOMP_INTTYPE1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE1__SIZE +CYFLD_LPCOMP_INTTYPE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_DISABLE +CYVAL_LPCOMP_INTTYPE1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_RISING +CYVAL_LPCOMP_INTTYPE1_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_FALLING +CYVAL_LPCOMP_INTTYPE1_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_BOTH +CYVAL_LPCOMP_INTTYPE1_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT1__OFFSET +CYFLD_LPCOMP_OUT1__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT1__SIZE +CYFLD_LPCOMP_OUT1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE1__OFFSET +CYFLD_LPCOMP_ENABLE1__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE1__SIZE +CYFLD_LPCOMP_ENABLE1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE2__OFFSET +CYFLD_LPCOMP_MODE2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE2__SIZE +CYFLD_LPCOMP_MODE2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_SLOW +CYVAL_LPCOMP_MODE2_SLOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_FAST +CYVAL_LPCOMP_MODE2_FAST EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_ULP +CYVAL_LPCOMP_MODE2_ULP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST2__OFFSET +CYFLD_LPCOMP_HYST2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST2__SIZE +CYFLD_LPCOMP_HYST2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER2__OFFSET +CYFLD_LPCOMP_FILTER2__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER2__SIZE +CYFLD_LPCOMP_FILTER2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE2__OFFSET +CYFLD_LPCOMP_INTTYPE2__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE2__SIZE +CYFLD_LPCOMP_INTTYPE2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_DISABLE +CYVAL_LPCOMP_INTTYPE2_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_RISING +CYVAL_LPCOMP_INTTYPE2_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_FALLING +CYVAL_LPCOMP_INTTYPE2_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_BOTH +CYVAL_LPCOMP_INTTYPE2_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT2__OFFSET +CYFLD_LPCOMP_OUT2__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT2__SIZE +CYFLD_LPCOMP_OUT2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE2__OFFSET +CYFLD_LPCOMP_ENABLE2__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE2__SIZE +CYFLD_LPCOMP_ENABLE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_DFT +CYREG_LPCOMP_DFT EQU 0x400a0008 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_CAL_EN__OFFSET +CYFLD_LPCOMP_CAL_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_CAL_EN__SIZE +CYFLD_LPCOMP_CAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_BYPASS__OFFSET +CYFLD_LPCOMP_BYPASS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_BYPASS__SIZE +CYFLD_LPCOMP_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR +CYREG_LPCOMP_INTR EQU 0x400a000c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1__OFFSET +CYFLD_LPCOMP_COMP1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1__SIZE +CYFLD_LPCOMP_COMP1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2__OFFSET +CYFLD_LPCOMP_COMP2__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2__SIZE +CYFLD_LPCOMP_COMP2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR_SET +CYREG_LPCOMP_INTR_SET EQU 0x400a0010 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM1 +CYREG_LPCOMP_TRIM1 EQU 0x400aff00 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMA__OFFSET +CYFLD_LPCOMP_COMP1_TRIMA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMA__SIZE +CYFLD_LPCOMP_COMP1_TRIMA__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM2 +CYREG_LPCOMP_TRIM2 EQU 0x400aff04 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMB__OFFSET +CYFLD_LPCOMP_COMP1_TRIMB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMB__SIZE +CYFLD_LPCOMP_COMP1_TRIMB__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM3 +CYREG_LPCOMP_TRIM3 EQU 0x400aff08 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMA__OFFSET +CYFLD_LPCOMP_COMP2_TRIMA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMA__SIZE +CYFLD_LPCOMP_COMP2_TRIMA__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM4 +CYREG_LPCOMP_TRIM4 EQU 0x400aff0c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMB__OFFSET +CYFLD_LPCOMP_COMP2_TRIMB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMB__SIZE +CYFLD_LPCOMP_COMP2_TRIMB__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_PWR_CONTROL +CYREG_PWR_CONTROL EQU 0x400b0000 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_MODE__OFFSET +CYFLD__POWER_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_MODE__SIZE +CYFLD__POWER_MODE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_RESET +CYVAL__POWER_MODE_RESET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_ACTIVE +CYVAL__POWER_MODE_ACTIVE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_SLEEP +CYVAL__POWER_MODE_SLEEP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_DEEP_SLEEP +CYVAL__POWER_MODE_DEEP_SLEEP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_HIBERNATE +CYVAL__POWER_MODE_HIBERNATE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DEBUG_SESSION__OFFSET +CYFLD__DEBUG_SESSION__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DEBUG_SESSION__SIZE +CYFLD__DEBUG_SESSION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DEBUG_SESSION_NO_SESSION +CYVAL__DEBUG_SESSION_NO_SESSION EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DEBUG_SESSION_SESSION_ACTIVE +CYVAL__DEBUG_SESSION_SESSION_ACTIVE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LPM_READY__OFFSET +CYFLD__LPM_READY__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__LPM_READY__SIZE +CYFLD__LPM_READY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EXT_VCCD__OFFSET +CYFLD__EXT_VCCD__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD__EXT_VCCD__SIZE +CYFLD__EXT_VCCD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_ENABLE__OFFSET +CYFLD__HVMON_ENABLE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_ENABLE__SIZE +CYFLD__HVMON_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_RELOAD__OFFSET +CYFLD__HVMON_RELOAD__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_RELOAD__SIZE +CYFLD__HVMON_RELOAD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__FIMO_DISABLE__OFFSET +CYFLD__FIMO_DISABLE__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD__FIMO_DISABLE__SIZE +CYFLD__FIMO_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_DISABLE__OFFSET +CYFLD__HIBERNATE_DISABLE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_DISABLE__SIZE +CYFLD__HIBERNATE_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SHORT__OFFSET +CYFLD__LFCLK_SHORT__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SHORT__SIZE +CYFLD__LFCLK_SHORT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE__OFFSET +CYFLD__HIBERNATE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE__SIZE +CYFLD__HIBERNATE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__HIBERNATE_DEEP_SLEEP +CYVAL__HIBERNATE_DEEP_SLEEP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__HIBERNATE_HIBERNATE +CYVAL__HIBERNATE_HIBERNATE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_INTR +CYREG_PWR_INTR EQU 0x400b0004 + ENDIF + IF :LNOT::DEF:CYFLD__LVD__OFFSET +CYFLD__LVD__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LVD__SIZE +CYFLD__LVD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_INTR_MASK +CYREG_PWR_INTR_MASK EQU 0x400b0008 + ENDIF + IF :LNOT::DEF:CYREG_PWR_KEY_DELAY +CYREG_PWR_KEY_DELAY EQU 0x400b000c + ENDIF + IF :LNOT::DEF:CYFLD__WAKEUP_HOLDOFF__OFFSET +CYFLD__WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WAKEUP_HOLDOFF__SIZE +CYFLD__WAKEUP_HOLDOFF__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_CONFIG +CYREG_PWR_PWRSYS_CONFIG EQU 0x400b0010 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_EN__OFFSET +CYFLD__HIB_TEST_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_EN__SIZE +CYFLD__HIB_TEST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_REP__OFFSET +CYFLD__HIB_TEST_REP__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TEST_REP__SIZE +CYFLD__HIB_TEST_REP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_CONFIG +CYREG_PWR_BG_CONFIG EQU 0x400b0014 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_EN__OFFSET +CYFLD__BG_DFT_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_EN__SIZE +CYFLD__BG_DFT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VREF_SEL__OFFSET +CYFLD__BG_DFT_VREF_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VREF_SEL__SIZE +CYFLD__BG_DFT_VREF_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_CORE_SEL__OFFSET +CYFLD__BG_DFT_CORE_SEL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_CORE_SEL__SIZE +CYFLD__BG_DFT_CORE_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_ICORE_SEL__OFFSET +CYFLD__BG_DFT_ICORE_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_ICORE_SEL__SIZE +CYFLD__BG_DFT_ICORE_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VCORE_SEL__OFFSET +CYFLD__BG_DFT_VCORE_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__BG_DFT_VCORE_SEL__SIZE +CYFLD__BG_DFT_VCORE_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__VREF_EN__OFFSET +CYFLD__VREF_EN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__VREF_EN__SIZE +CYFLD__VREF_EN__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_PWR_VMON_CONFIG +CYREG_PWR_VMON_CONFIG EQU 0x400b0018 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_EN__OFFSET +CYFLD__LVD_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_EN__SIZE +CYFLD__LVD_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_SEL__OFFSET +CYFLD__LVD_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LVD_SEL__SIZE +CYFLD__LVD_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_DDFT_SEL__OFFSET +CYFLD__VMON_DDFT_SEL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_DDFT_SEL__SIZE +CYFLD__VMON_DDFT_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_ADFT_SEL__OFFSET +CYFLD__VMON_ADFT_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_ADFT_SEL__SIZE +CYFLD__VMON_ADFT_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWR_DFT_SELECT +CYREG_PWR_DFT_SELECT EQU 0x400b001c + ENDIF + IF :LNOT::DEF:CYFLD__TVMON1_SEL__OFFSET +CYFLD__TVMON1_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TVMON1_SEL__SIZE +CYFLD__TVMON1_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__TVMON2_SEL__OFFSET +CYFLD__TVMON2_SEL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__TVMON2_SEL__SIZE +CYFLD__TVMON2_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__BYPASS__OFFSET +CYFLD__BYPASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__BYPASS__SIZE +CYFLD__BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_EN__OFFSET +CYFLD__ACTIVE_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_EN__SIZE +CYFLD__ACTIVE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_INRUSH_DIS__OFFSET +CYFLD__ACTIVE_INRUSH_DIS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__ACTIVE_INRUSH_DIS__SIZE +CYFLD__ACTIVE_INRUSH_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LPCOMP_DIS__OFFSET +CYFLD__LPCOMP_DIS__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__LPCOMP_DIS__SIZE +CYFLD__LPCOMP_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BLEED_EN__OFFSET +CYFLD__BLEED_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD__BLEED_EN__SIZE +CYFLD__BLEED_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__IPOR_EN__OFFSET +CYFLD__IPOR_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD__IPOR_EN__SIZE +CYFLD__IPOR_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_BYP__OFFSET +CYFLD__POWER_UP_RAW_BYP__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_BYP__SIZE +CYFLD__POWER_UP_RAW_BYP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_CTL__OFFSET +CYFLD__POWER_UP_RAW_CTL__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_RAW_CTL__SIZE +CYFLD__POWER_UP_RAW_CTL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_EN__OFFSET +CYFLD__DEEPSLEEP_EN__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_EN__SIZE +CYFLD__DEEPSLEEP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_BYPASS__OFFSET +CYFLD__RSVD_BYPASS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_BYPASS__SIZE +CYFLD__RSVD_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_OPEN__OFFSET +CYFLD__NWELL_OPEN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_OPEN__SIZE +CYFLD__NWELL_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_OPEN__OFFSET +CYFLD__HIBERNATE_OPEN__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__HIBERNATE_OPEN__SIZE +CYFLD__HIBERNATE_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_OPEN__OFFSET +CYFLD__DEEPSLEEP_OPEN__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__DEEPSLEEP_OPEN__SIZE +CYFLD__DEEPSLEEP_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_OPEN__OFFSET +CYFLD__QUIET_OPEN__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_OPEN__SIZE +CYFLD__QUIET_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_OPEN__OFFSET +CYFLD__LFCLK_OPEN__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_OPEN__SIZE +CYFLD__LFCLK_OPEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_EN__OFFSET +CYFLD__QUIET_EN__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_EN__SIZE +CYFLD__QUIET_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_EN__OFFSET +CYFLD__BREF_EN__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_EN__SIZE +CYFLD__BREF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_OUTEN__OFFSET +CYFLD__BREF_OUTEN__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_OUTEN__SIZE +CYFLD__BREF_OUTEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_REFSW__OFFSET +CYFLD__BREF_REFSW__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_REFSW__SIZE +CYFLD__BREF_REFSW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BREF_TESTMODE__OFFSET +CYFLD__BREF_TESTMODE__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD__BREF_TESTMODE__SIZE +CYFLD__BREF_TESTMODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_DIS__OFFSET +CYFLD__NWELL_DIS__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_DIS__SIZE +CYFLD__NWELL_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_DFT_OVR__OFFSET +CYFLD__HVMON_DFT_OVR__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__HVMON_DFT_OVR__SIZE +CYFLD__HVMON_DFT_OVR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__IMO_REFGEN_DIS__OFFSET +CYFLD__IMO_REFGEN_DIS__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD__IMO_REFGEN_DIS__SIZE +CYFLD__IMO_REFGEN_DIS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_ACTIVE__OFFSET +CYFLD__POWER_UP_ACTIVE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_ACTIVE__SIZE +CYFLD__POWER_UP_ACTIVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_HIBDPSLP__OFFSET +CYFLD__POWER_UP_HIBDPSLP__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__POWER_UP_HIBDPSLP__SIZE +CYFLD__POWER_UP_HIBDPSLP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_DDFT_SELECT +CYREG_PWR_DDFT_SELECT EQU 0x400b0020 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT1_SEL__OFFSET +CYFLD__DDFT1_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT1_SEL__SIZE +CYFLD__DDFT1_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT2_SEL__OFFSET +CYFLD__DDFT2_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT2_SEL__SIZE +CYFLD__DDFT2_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_DFT_KEY +CYREG_PWR_DFT_KEY EQU 0x400b0024 + ENDIF + IF :LNOT::DEF:CYFLD__KEY16__OFFSET +CYFLD__KEY16__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__KEY16__SIZE +CYFLD__KEY16__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__HBOD_OFF_AWAKE__OFFSET +CYFLD__HBOD_OFF_AWAKE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__HBOD_OFF_AWAKE__SIZE +CYFLD__HBOD_OFF_AWAKE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BODS_OFF__OFFSET +CYFLD__BODS_OFF__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__BODS_OFF__SIZE +CYFLD__BODS_OFF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_MODE__OFFSET +CYFLD__DFT_MODE__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_MODE__SIZE +CYFLD__DFT_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__IO_DISABLE_BYPASS__OFFSET +CYFLD__IO_DISABLE_BYPASS__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__IO_DISABLE_BYPASS__SIZE +CYFLD__IO_DISABLE_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_PD__OFFSET +CYFLD__VMON_PD__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD__VMON_PD__SIZE +CYFLD__VMON_PD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BOD_KEY +CYREG_PWR_BOD_KEY EQU 0x400b0028 + ENDIF + IF :LNOT::DEF:CYREG_PWR_STOP +CYREG_PWR_STOP EQU 0x400b002c + ENDIF + IF :LNOT::DEF:CYFLD__TOKEN__OFFSET +CYFLD__TOKEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TOKEN__SIZE +CYFLD__TOKEN__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__UNLOCK__OFFSET +CYFLD__UNLOCK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__UNLOCK__SIZE +CYFLD__UNLOCK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__POLARITY__OFFSET +CYFLD__POLARITY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__POLARITY__SIZE +CYFLD__POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__FREEZE__OFFSET +CYFLD__FREEZE__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__FREEZE__SIZE +CYFLD__FREEZE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__STOP__OFFSET +CYFLD__STOP__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__STOP__SIZE +CYFLD__STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT +CYREG_CLK_SELECT EQU 0x400b0100 + ENDIF + IF :LNOT::DEF:CYFLD__DIRECT_SEL__OFFSET +CYFLD__DIRECT_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DIRECT_SEL__SIZE +CYFLD__DIRECT_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_IMO +CYVAL__DIRECT_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_EXTCLK +CYVAL__DIRECT_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_ECO +CYVAL__DIRECT_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI0 +CYVAL__DIRECT_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI1 +CYVAL__DIRECT_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI2 +CYVAL__DIRECT_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DIRECT_SEL_DSI3 +CYVAL__DIRECT_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DBL_SEL__OFFSET +CYFLD__DBL_SEL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__DBL_SEL__SIZE +CYFLD__DBL_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_IMO +CYVAL__DBL_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_EXTCLK +CYVAL__DBL_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_ECO +CYVAL__DBL_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI0 +CYVAL__DBL_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI1 +CYVAL__DBL_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI2 +CYVAL__DBL_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DBL_SEL_DSI3 +CYVAL__DBL_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__PLL_SEL__OFFSET +CYFLD__PLL_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__PLL_SEL__SIZE +CYFLD__PLL_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_IMO +CYVAL__PLL_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_EXTCLK +CYVAL__PLL_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_ECO +CYVAL__PLL_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DPLL +CYVAL__PLL_SEL_DPLL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI0 +CYVAL__PLL_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI1 +CYVAL__PLL_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI2 +CYVAL__PLL_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__PLL_SEL_DSI3 +CYVAL__PLL_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DPLLIN_SEL__OFFSET +CYFLD__DPLLIN_SEL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__DPLLIN_SEL__SIZE +CYFLD__DPLLIN_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_IMO +CYVAL__DPLLIN_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_EXTCLK +CYVAL__DPLLIN_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_ECO +CYVAL__DPLLIN_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI0 +CYVAL__DPLLIN_SEL_DSI0 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI1 +CYVAL__DPLLIN_SEL_DSI1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI2 +CYVAL__DPLLIN_SEL_DSI2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLIN_SEL_DSI3 +CYVAL__DPLLIN_SEL_DSI3 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DPLLREF_SEL__OFFSET +CYFLD__DPLLREF_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD__DPLLREF_SEL__SIZE +CYFLD__DPLLREF_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI0 +CYVAL__DPLLREF_SEL_DSI0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI1 +CYVAL__DPLLREF_SEL_DSI1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI2 +CYVAL__DPLLREF_SEL_DSI2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DPLLREF_SEL_DSI3 +CYVAL__DPLLREF_SEL_DSI3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_LOCK__OFFSET +CYFLD__WDT_LOCK__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD__WDT_LOCK__SIZE +CYFLD__WDT_LOCK__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_NO_CHG +CYVAL__WDT_LOCK_NO_CHG EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_CLR0 +CYVAL__WDT_LOCK_CLR0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_CLR1 +CYVAL__WDT_LOCK_CLR1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_LOCK_SET01 +CYVAL__WDT_LOCK_SET01 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_SEL__OFFSET +CYFLD__HFCLK_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_SEL__SIZE +CYFLD__HFCLK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_DIRECT_SEL +CYVAL__HFCLK_SEL_DIRECT_SEL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_DBL +CYVAL__HFCLK_SEL_DBL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_PLL +CYVAL__HFCLK_SEL_PLL EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HALF_EN__OFFSET +CYFLD__HALF_EN__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__HALF_EN__SIZE +CYFLD__HALF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__SYSCLK_DIV__OFFSET +CYFLD__SYSCLK_DIV__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__SYSCLK_DIV__SIZE +CYFLD__SYSCLK_DIV__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_NO_DIV +CYVAL__SYSCLK_DIV_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_2 +CYVAL__SYSCLK_DIV_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_4 +CYVAL__SYSCLK_DIV_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_8 +CYVAL__SYSCLK_DIV_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_16 +CYVAL__SYSCLK_DIV_DIV_BY_16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_32 +CYVAL__SYSCLK_DIV_DIV_BY_32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_64 +CYVAL__SYSCLK_DIV_DIV_BY_64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_128 +CYVAL__SYSCLK_DIV_DIV_BY_128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_CLK_ILO_CONFIG +CYREG_CLK_ILO_CONFIG EQU 0x400b0104 + ENDIF + IF :LNOT::DEF:CYFLD__PD_MODE__OFFSET +CYFLD__PD_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__PD_MODE__SIZE +CYFLD__PD_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__PD_MODE_SLEEP +CYVAL__PD_MODE_SLEEP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__PD_MODE_COMA +CYVAL__PD_MODE_COMA EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TURBO__OFFSET +CYFLD__TURBO__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TURBO__SIZE +CYFLD__TURBO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__SATBIAS__OFFSET +CYFLD__SATBIAS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__SATBIAS__SIZE +CYFLD__SATBIAS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SATBIAS_SATURATED +CYVAL__SATBIAS_SATURATED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SATBIAS_SUBTHRESHOLD +CYVAL__SATBIAS_SUBTHRESHOLD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__ENABLE__OFFSET +CYFLD__ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__ENABLE__SIZE +CYFLD__ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_CONFIG +CYREG_CLK_IMO_CONFIG EQU 0x400b0108 + ENDIF + IF :LNOT::DEF:CYFLD__FLASHPUMP_SEL__OFFSET +CYFLD__FLASHPUMP_SEL__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD__FLASHPUMP_SEL__SIZE +CYFLD__FLASHPUMP_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__FLASHPUMP_SEL_GND +CYVAL__FLASHPUMP_SEL_GND EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__FLASHPUMP_SEL_CLK36 +CYVAL__FLASHPUMP_SEL_CLK36 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EN_FASTBIAS__OFFSET +CYFLD__EN_FASTBIAS__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD__EN_FASTBIAS__SIZE +CYFLD__EN_FASTBIAS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_FASTBIAS__OFFSET +CYFLD__TEST_FASTBIAS__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_FASTBIAS__SIZE +CYFLD__TEST_FASTBIAS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__PUMP_SEL__OFFSET +CYFLD__PUMP_SEL__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD__PUMP_SEL__SIZE +CYFLD__PUMP_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_GND +CYVAL__PUMP_SEL_GND EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_IMO +CYVAL__PUMP_SEL_IMO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_DBL +CYVAL__PUMP_SEL_DBL EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_CLK36 +CYVAL__PUMP_SEL_CLK36 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_FF1 +CYVAL__PUMP_SEL_FF1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_USB_MODE__OFFSET +CYFLD__TEST_USB_MODE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__TEST_USB_MODE__SIZE +CYFLD__TEST_USB_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK36__OFFSET +CYFLD__EN_CLK36__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK36__SIZE +CYFLD__EN_CLK36__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK2X__OFFSET +CYFLD__EN_CLK2X__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__EN_CLK2X__SIZE +CYFLD__EN_CLK2X__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_SPREAD +CYREG_CLK_IMO_SPREAD EQU 0x400b010c + ENDIF + IF :LNOT::DEF:CYFLD__SS_VALUE__OFFSET +CYFLD__SS_VALUE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__SS_VALUE__SIZE +CYFLD__SS_VALUE__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__SS_MAX__OFFSET +CYFLD__SS_MAX__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__SS_MAX__SIZE +CYFLD__SS_MAX__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__SS_RANGE__OFFSET +CYFLD__SS_RANGE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__SS_RANGE__SIZE +CYFLD__SS_RANGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SS_RANGE_M1 +CYVAL__SS_RANGE_M1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SS_RANGE_M2 +CYVAL__SS_RANGE_M2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SS_RANGE_M4 +CYVAL__SS_RANGE_M4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__SS_MODE__OFFSET +CYFLD__SS_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__SS_MODE__SIZE +CYFLD__SS_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_OFF +CYVAL__SS_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_TRIANGLE +CYVAL__SS_MODE_TRIANGLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_LFSR +CYVAL__SS_MODE_LFSR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SS_MODE_DSI +CYVAL__SS_MODE_DSI EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DFT_SELECT +CYREG_CLK_DFT_SELECT EQU 0x400b0110 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL1__OFFSET +CYFLD__DFT_SEL1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL1__SIZE +CYFLD__DFT_SEL1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_NC +CYVAL__DFT_SEL1_NC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_ILO +CYVAL__DFT_SEL1_ILO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_WCO +CYVAL__DFT_SEL1_WCO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_IMO +CYVAL__DFT_SEL1_IMO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_ECO +CYVAL__DFT_SEL1_ECO EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_PLL +CYVAL__DFT_SEL1_PLL EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_DPLL_OUT +CYVAL__DFT_SEL1_DPLL_OUT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_DPLL_REF +CYVAL__DFT_SEL1_DPLL_REF EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_DBL +CYVAL__DFT_SEL1_DBL EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_IMO2X +CYVAL__DFT_SEL1_IMO2X EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_IMO36 +CYVAL__DFT_SEL1_IMO36 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_HFCLK +CYVAL__DFT_SEL1_HFCLK EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_LFCLK +CYVAL__DFT_SEL1_LFCLK EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SYSCLK +CYVAL__DFT_SEL1_SYSCLK EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_EXTCLK +CYVAL__DFT_SEL1_EXTCLK EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_HALFSYSCLK +CYVAL__DFT_SEL1_HALFSYSCLK EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV1__OFFSET +CYFLD__DFT_DIV1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV1__SIZE +CYFLD__DFT_DIV1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_NO_DIV +CYVAL__DFT_DIV1_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_2 +CYVAL__DFT_DIV1_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_4 +CYVAL__DFT_DIV1_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_8 +CYVAL__DFT_DIV1_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL2__OFFSET +CYFLD__DFT_SEL2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL2__SIZE +CYFLD__DFT_SEL2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_NC +CYVAL__DFT_SEL2_NC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_ILO +CYVAL__DFT_SEL2_ILO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_WCO +CYVAL__DFT_SEL2_WCO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_IMO +CYVAL__DFT_SEL2_IMO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_ECO +CYVAL__DFT_SEL2_ECO EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_PLL +CYVAL__DFT_SEL2_PLL EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_DPLL_OUT +CYVAL__DFT_SEL2_DPLL_OUT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_DPLL_REF +CYVAL__DFT_SEL2_DPLL_REF EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_DBL +CYVAL__DFT_SEL2_DBL EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_IMO2X +CYVAL__DFT_SEL2_IMO2X EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_IMO36 +CYVAL__DFT_SEL2_IMO36 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_HFCLK +CYVAL__DFT_SEL2_HFCLK EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_LFCLK +CYVAL__DFT_SEL2_LFCLK EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_SYSCLK +CYVAL__DFT_SEL2_SYSCLK EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_EXTCLK +CYVAL__DFT_SEL2_EXTCLK EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL2_HALFSYSCLK +CYVAL__DFT_SEL2_HALFSYSCLK EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV2__OFFSET +CYFLD__DFT_DIV2__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV2__SIZE +CYFLD__DFT_DIV2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_NO_DIV +CYVAL__DFT_DIV2_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_DIV_BY_2 +CYVAL__DFT_DIV2_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_DIV_BY_4 +CYVAL__DFT_DIV2_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV2_DIV_BY_8 +CYVAL__DFT_DIV2_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CTRLOW +CYREG_WDT_CTRLOW EQU 0x400b0200 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR0__OFFSET +CYFLD__WDT_CTR0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR0__SIZE +CYFLD__WDT_CTR0__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR1__OFFSET +CYFLD__WDT_CTR1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR1__SIZE +CYFLD__WDT_CTR1__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CTRHIGH +CYREG_WDT_CTRHIGH EQU 0x400b0204 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR2__OFFSET +CYFLD__WDT_CTR2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CTR2__SIZE +CYFLD__WDT_CTR2__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_WDT_MATCH +CYREG_WDT_MATCH EQU 0x400b0208 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH0__OFFSET +CYFLD__WDT_MATCH0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH0__SIZE +CYFLD__WDT_MATCH0__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH1__OFFSET +CYFLD__WDT_MATCH1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH1__SIZE +CYFLD__WDT_MATCH1__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CONFIG +CYREG_WDT_CONFIG EQU 0x400b020c + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE0__OFFSET +CYFLD__WDT_MODE0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE0__SIZE +CYFLD__WDT_MODE0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_NOTHING +CYVAL__WDT_MODE0_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_INT +CYVAL__WDT_MODE0_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_RESET +CYVAL__WDT_MODE0_RESET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE0_INT_THEN_RESET +CYVAL__WDT_MODE0_INT_THEN_RESET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR0__OFFSET +CYFLD__WDT_CLEAR0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR0__SIZE +CYFLD__WDT_CLEAR0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE0_1__OFFSET +CYFLD__WDT_CASCADE0_1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE0_1__SIZE +CYFLD__WDT_CASCADE0_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE1__OFFSET +CYFLD__WDT_MODE1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE1__SIZE +CYFLD__WDT_MODE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_NOTHING +CYVAL__WDT_MODE1_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_INT +CYVAL__WDT_MODE1_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_RESET +CYVAL__WDT_MODE1_RESET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE1_INT_THEN_RESET +CYVAL__WDT_MODE1_INT_THEN_RESET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR1__OFFSET +CYFLD__WDT_CLEAR1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CLEAR1__SIZE +CYFLD__WDT_CLEAR1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE1_2__OFFSET +CYFLD__WDT_CASCADE1_2__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD__WDT_CASCADE1_2__SIZE +CYFLD__WDT_CASCADE1_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE2__OFFSET +CYFLD__WDT_MODE2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MODE2__SIZE +CYFLD__WDT_MODE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE2_NOTHING +CYVAL__WDT_MODE2_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__WDT_MODE2_INT +CYVAL__WDT_MODE2_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_BITS2__OFFSET +CYFLD__WDT_BITS2__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_BITS2__SIZE +CYFLD__WDT_BITS2__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SEL__OFFSET +CYFLD__LFCLK_SEL__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_SEL__SIZE +CYFLD__LFCLK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_WDT_CONTROL +CYREG_WDT_CONTROL EQU 0x400b0210 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE0__OFFSET +CYFLD__WDT_ENABLE0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE0__SIZE +CYFLD__WDT_ENABLE0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED0__OFFSET +CYFLD__WDT_ENABLED0__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED0__SIZE +CYFLD__WDT_ENABLED0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT0__OFFSET +CYFLD__WDT_INT0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT0__SIZE +CYFLD__WDT_INT0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET0__OFFSET +CYFLD__WDT_RESET0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET0__SIZE +CYFLD__WDT_RESET0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE1__OFFSET +CYFLD__WDT_ENABLE1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE1__SIZE +CYFLD__WDT_ENABLE1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED1__OFFSET +CYFLD__WDT_ENABLED1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED1__SIZE +CYFLD__WDT_ENABLED1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT1__OFFSET +CYFLD__WDT_INT1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT1__SIZE +CYFLD__WDT_INT1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET1__OFFSET +CYFLD__WDT_RESET1__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET1__SIZE +CYFLD__WDT_RESET1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE2__OFFSET +CYFLD__WDT_ENABLE2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLE2__SIZE +CYFLD__WDT_ENABLE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED2__OFFSET +CYFLD__WDT_ENABLED2__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_ENABLED2__SIZE +CYFLD__WDT_ENABLED2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT2__OFFSET +CYFLD__WDT_INT2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_INT2__SIZE +CYFLD__WDT_INT2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET2__OFFSET +CYFLD__WDT_RESET2__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_RESET2__SIZE +CYFLD__WDT_RESET2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_RES_CAUSE +CYREG_RES_CAUSE EQU 0x400b0300 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_WDT__OFFSET +CYFLD__RESET_WDT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_WDT__SIZE +CYFLD__RESET_WDT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_DSBOD__OFFSET +CYFLD__RESET_DSBOD__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_DSBOD__SIZE +CYFLD__RESET_DSBOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_LOCKUP__OFFSET +CYFLD__RESET_LOCKUP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_LOCKUP__SIZE +CYFLD__RESET_LOCKUP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PROT_FAULT__OFFSET +CYFLD__RESET_PROT_FAULT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PROT_FAULT__SIZE +CYFLD__RESET_PROT_FAULT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_SOFT__OFFSET +CYFLD__RESET_SOFT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_SOFT__SIZE +CYFLD__RESET_SOFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_HVBOD__OFFSET +CYFLD__RESET_HVBOD__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_HVBOD__SIZE +CYFLD__RESET_HVBOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PBOD__OFFSET +CYFLD__RESET_PBOD__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PBOD__SIZE +CYFLD__RESET_PBOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_XRES__OFFSET +CYFLD__RESET_XRES__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_XRES__SIZE +CYFLD__RESET_XRES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM1 +CYREG_PWR_PWRSYS_TRIM1 EQU 0x400bff00 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_BIAS_TRIM__OFFSET +CYFLD__HIB_BIAS_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_BIAS_TRIM__SIZE +CYFLD__HIB_BIAS_TRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TURBO_THRESH__OFFSET +CYFLD__BOD_TURBO_THRESH__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TURBO_THRESH__SIZE +CYFLD__BOD_TURBO_THRESH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TRIM_TRIP__OFFSET +CYFLD__BOD_TRIM_TRIP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__BOD_TRIM_TRIP__SIZE +CYFLD__BOD_TRIM_TRIP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM2 +CYREG_PWR_PWRSYS_TRIM2 EQU 0x400bff04 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_LOAD__OFFSET +CYFLD__LFCLK_TRIM_LOAD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_LOAD__SIZE +CYFLD__LFCLK_TRIM_LOAD__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET +CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__LFCLK_TRIM_VOLTAGE__SIZE +CYFLD__LFCLK_TRIM_VOLTAGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LOAD__OFFSET +CYFLD__DPSLP_TRIM_LOAD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LOAD__SIZE +CYFLD__DPSLP_TRIM_LOAD__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET +CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_LEAKAGE__SIZE +CYFLD__DPSLP_TRIM_LEAKAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET +CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_TRIM_VOLTAGE__SIZE +CYFLD__DPSLP_TRIM_VOLTAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM3 +CYREG_PWR_PWRSYS_TRIM3 EQU 0x400bff08 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_TRIM__OFFSET +CYFLD__NWELL_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__NWELL_TRIM__SIZE +CYFLD__NWELL_TRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_TRIM__OFFSET +CYFLD__QUIET_TRIM__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__QUIET_TRIM__SIZE +CYFLD__QUIET_TRIM__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM4 +CYREG_PWR_PWRSYS_TRIM4 EQU 0x400bff0c + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_NWELL__OFFSET +CYFLD__HIB_TRIM_NWELL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_NWELL__SIZE +CYFLD__HIB_TRIM_NWELL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_LEAKAGE__OFFSET +CYFLD__HIB_TRIM_LEAKAGE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_LEAKAGE__SIZE +CYFLD__HIB_TRIM_LEAKAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_VOLTAGE__OFFSET +CYFLD__HIB_TRIM_VOLTAGE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_VOLTAGE__SIZE +CYFLD__HIB_TRIM_VOLTAGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_REFERENCE__OFFSET +CYFLD__HIB_TRIM_REFERENCE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__HIB_TRIM_REFERENCE__SIZE +CYFLD__HIB_TRIM_REFERENCE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM1 +CYREG_PWR_BG_TRIM1 EQU 0x400bff10 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_MAIN__OFFSET +CYFLD__INL_TRIM_MAIN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_MAIN__SIZE +CYFLD__INL_TRIM_MAIN__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_MAIN__OFFSET +CYFLD__INL_CROSS_MAIN__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_MAIN__SIZE +CYFLD__INL_CROSS_MAIN__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM2 +CYREG_PWR_BG_TRIM2 EQU 0x400bff14 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_SLOPE__OFFSET +CYFLD__VCTAT_SLOPE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_SLOPE__SIZE +CYFLD__VCTAT_SLOPE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE__OFFSET +CYFLD__VCTAT_VOLTAGE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE__SIZE +CYFLD__VCTAT_VOLTAGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_ENABLE__OFFSET +CYFLD__VCTAT_ENABLE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_ENABLE__SIZE +CYFLD__VCTAT_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE_MSB__OFFSET +CYFLD__VCTAT_VOLTAGE_MSB__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD__VCTAT_VOLTAGE_MSB__SIZE +CYFLD__VCTAT_VOLTAGE_MSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM3 +CYREG_PWR_BG_TRIM3 EQU 0x400bff18 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_IMO__OFFSET +CYFLD__INL_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__INL_TRIM_IMO__SIZE +CYFLD__INL_TRIM_IMO__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_IMO__OFFSET +CYFLD__INL_CROSS_IMO__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__INL_CROSS_IMO__SIZE +CYFLD__INL_CROSS_IMO__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM4 +CYREG_PWR_BG_TRIM4 EQU 0x400bff1c + ENDIF + IF :LNOT::DEF:CYFLD__ABS_TRIM_IMO__OFFSET +CYFLD__ABS_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__ABS_TRIM_IMO__SIZE +CYFLD__ABS_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM5 +CYREG_PWR_BG_TRIM5 EQU 0x400bff20 + ENDIF + IF :LNOT::DEF:CYFLD__TMPCO_TRIM_IMO__OFFSET +CYFLD__TMPCO_TRIM_IMO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TMPCO_TRIM_IMO__SIZE +CYFLD__TMPCO_TRIM_IMO__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CLK_ILO_TRIM +CYREG_CLK_ILO_TRIM EQU 0x400bff24 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM__OFFSET +CYFLD__TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM__SIZE +CYFLD__TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__COARSE_TRIM__OFFSET +CYFLD__COARSE_TRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__COARSE_TRIM__SIZE +CYFLD__COARSE_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM1 +CYREG_CLK_IMO_TRIM1 EQU 0x400bff28 + ENDIF + IF :LNOT::DEF:CYFLD__OFFSET__OFFSET +CYFLD__OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__OFFSET__SIZE +CYFLD__OFFSET__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM2 +CYREG_CLK_IMO_TRIM2 EQU 0x400bff2c + ENDIF + IF :LNOT::DEF:CYFLD__FREQ__OFFSET +CYFLD__FREQ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__FREQ__SIZE +CYFLD__FREQ__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM3 +CYREG_CLK_IMO_TRIM3 EQU 0x400bff30 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM_CLK36__OFFSET +CYFLD__TRIM_CLK36__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__TRIM_CLK36__SIZE +CYFLD__TRIM_CLK36__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM4 +CYREG_CLK_IMO_TRIM4 EQU 0x400bff34 + ENDIF + IF :LNOT::DEF:CYFLD__GAIN__OFFSET +CYFLD__GAIN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__GAIN__SIZE +CYFLD__GAIN__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__FSOFFSET__OFFSET +CYFLD__FSOFFSET__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__FSOFFSET__SIZE +CYFLD__FSOFFSET__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_PWR_RSVD_TRIM +CYREG_PWR_RSVD_TRIM EQU 0x400bff38 + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_TRIM__OFFSET +CYFLD__RSVD_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__RSVD_TRIM__SIZE +CYFLD__RSVD_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_SPCIF_BASE +CYDEV_SPCIF_BASE EQU 0x400e0000 + ENDIF + IF :LNOT::DEF:CYDEV_SPCIF_SIZE +CYDEV_SPCIF_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_GEOMETRY +CYREG_SPCIF_GEOMETRY EQU 0x400e0000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH__OFFSET +CYFLD_SPCIF_FLASH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH__SIZE +CYFLD_SPCIF_FLASH__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_SFLASH__OFFSET +CYFLD_SPCIF_SFLASH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_SFLASH__SIZE +CYFLD_SPCIF_SFLASH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NUM_FLASH__OFFSET +CYFLD_SPCIF_NUM_FLASH__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NUM_FLASH__SIZE +CYFLD_SPCIF_NUM_FLASH__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH_ROW__OFFSET +CYFLD_SPCIF_FLASH_ROW__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH_ROW__SIZE +CYFLD_SPCIF_FLASH_ROW__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NVL__OFFSET +CYFLD_SPCIF_NVL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NVL__SIZE +CYFLD_SPCIF_NVL__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DE_CPD_LP__OFFSET +CYFLD_SPCIF_DE_CPD_LP__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DE_CPD_LP__SIZE +CYFLD_SPCIF_DE_CPD_LP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_NVL_WR_DATA +CYREG_SPCIF_NVL_WR_DATA EQU 0x400e001c + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DATA__OFFSET +CYFLD_SPCIF_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DATA__SIZE +CYFLD_SPCIF_DATA__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_BASE +CYDEV_UDB_BASE EQU 0x400f0000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_SIZE +CYDEV_UDB_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W8_BASE +CYDEV_UDB_W8_BASE EQU 0x400f0000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W8_SIZE +CYDEV_UDB_W8_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_00 +CYREG_UDB_W8_A0_00 EQU 0x400f0000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A0__OFFSET +CYFLD_UDB_W8_A0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A0__SIZE +CYFLD_UDB_W8_A0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_01 +CYREG_UDB_W8_A0_01 EQU 0x400f0001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_02 +CYREG_UDB_W8_A0_02 EQU 0x400f0002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A0_03 +CYREG_UDB_W8_A0_03 EQU 0x400f0003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_00 +CYREG_UDB_W8_A1_00 EQU 0x400f0010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A1__OFFSET +CYFLD_UDB_W8_A1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_A1__SIZE +CYFLD_UDB_W8_A1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_01 +CYREG_UDB_W8_A1_01 EQU 0x400f0011 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_02 +CYREG_UDB_W8_A1_02 EQU 0x400f0012 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_A1_03 +CYREG_UDB_W8_A1_03 EQU 0x400f0013 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_00 +CYREG_UDB_W8_D0_00 EQU 0x400f0020 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D0__OFFSET +CYFLD_UDB_W8_D0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D0__SIZE +CYFLD_UDB_W8_D0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_01 +CYREG_UDB_W8_D0_01 EQU 0x400f0021 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_02 +CYREG_UDB_W8_D0_02 EQU 0x400f0022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D0_03 +CYREG_UDB_W8_D0_03 EQU 0x400f0023 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_00 +CYREG_UDB_W8_D1_00 EQU 0x400f0030 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D1__OFFSET +CYFLD_UDB_W8_D1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_D1__SIZE +CYFLD_UDB_W8_D1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_01 +CYREG_UDB_W8_D1_01 EQU 0x400f0031 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_02 +CYREG_UDB_W8_D1_02 EQU 0x400f0032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_D1_03 +CYREG_UDB_W8_D1_03 EQU 0x400f0033 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_00 +CYREG_UDB_W8_F0_00 EQU 0x400f0040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F0__OFFSET +CYFLD_UDB_W8_F0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F0__SIZE +CYFLD_UDB_W8_F0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_01 +CYREG_UDB_W8_F0_01 EQU 0x400f0041 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_02 +CYREG_UDB_W8_F0_02 EQU 0x400f0042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F0_03 +CYREG_UDB_W8_F0_03 EQU 0x400f0043 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_00 +CYREG_UDB_W8_F1_00 EQU 0x400f0050 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F1__OFFSET +CYFLD_UDB_W8_F1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_F1__SIZE +CYFLD_UDB_W8_F1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_01 +CYREG_UDB_W8_F1_01 EQU 0x400f0051 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_02 +CYREG_UDB_W8_F1_02 EQU 0x400f0052 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_F1_03 +CYREG_UDB_W8_F1_03 EQU 0x400f0053 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_00 +CYREG_UDB_W8_ST_00 EQU 0x400f0060 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_ST__OFFSET +CYFLD_UDB_W8_ST__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_ST__SIZE +CYFLD_UDB_W8_ST__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_01 +CYREG_UDB_W8_ST_01 EQU 0x400f0061 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_02 +CYREG_UDB_W8_ST_02 EQU 0x400f0062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ST_03 +CYREG_UDB_W8_ST_03 EQU 0x400f0063 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_00 +CYREG_UDB_W8_CTL_00 EQU 0x400f0070 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CTL__OFFSET +CYFLD_UDB_W8_CTL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CTL__SIZE +CYFLD_UDB_W8_CTL__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_01 +CYREG_UDB_W8_CTL_01 EQU 0x400f0071 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_02 +CYREG_UDB_W8_CTL_02 EQU 0x400f0072 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_CTL_03 +CYREG_UDB_W8_CTL_03 EQU 0x400f0073 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_00 +CYREG_UDB_W8_MSK_00 EQU 0x400f0080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_MSK__OFFSET +CYFLD_UDB_W8_MSK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_MSK__SIZE +CYFLD_UDB_W8_MSK__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_01 +CYREG_UDB_W8_MSK_01 EQU 0x400f0081 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_02 +CYREG_UDB_W8_MSK_02 EQU 0x400f0082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MSK_03 +CYREG_UDB_W8_MSK_03 EQU 0x400f0083 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_00 +CYREG_UDB_W8_ACTL_00 EQU 0x400f0090 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_CLR__OFFSET +CYFLD_UDB_W8_FIFO0_CLR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_CLR__SIZE +CYFLD_UDB_W8_FIFO0_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_CLR_NORMAL +CYVAL_UDB_W8_FIFO0_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_CLR_CLEAR +CYVAL_UDB_W8_FIFO0_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_CLR__OFFSET +CYFLD_UDB_W8_FIFO1_CLR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_CLR__SIZE +CYFLD_UDB_W8_FIFO1_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_CLR_NORMAL +CYVAL_UDB_W8_FIFO1_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_CLR_CLEAR +CYVAL_UDB_W8_FIFO1_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_LVL__OFFSET +CYFLD_UDB_W8_FIFO0_LVL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO0_LVL__SIZE +CYFLD_UDB_W8_FIFO0_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_LVL_NORMAL +CYVAL_UDB_W8_FIFO0_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO0_LVL_MID +CYVAL_UDB_W8_FIFO0_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_LVL__OFFSET +CYFLD_UDB_W8_FIFO1_LVL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_FIFO1_LVL__SIZE +CYFLD_UDB_W8_FIFO1_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_LVL_NORMAL +CYVAL_UDB_W8_FIFO1_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_FIFO1_LVL_MID +CYVAL_UDB_W8_FIFO1_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_INT_EN__OFFSET +CYFLD_UDB_W8_INT_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_INT_EN__SIZE +CYFLD_UDB_W8_INT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_INT_EN_DISABLE +CYVAL_UDB_W8_INT_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_INT_EN_ENABLE +CYVAL_UDB_W8_INT_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CNT_START__OFFSET +CYFLD_UDB_W8_CNT_START__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_CNT_START__SIZE +CYFLD_UDB_W8_CNT_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_CNT_START_DISABLE +CYVAL_UDB_W8_CNT_START_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W8_CNT_START_ENABLE +CYVAL_UDB_W8_CNT_START_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_01 +CYREG_UDB_W8_ACTL_01 EQU 0x400f0091 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_02 +CYREG_UDB_W8_ACTL_02 EQU 0x400f0092 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_ACTL_03 +CYREG_UDB_W8_ACTL_03 EQU 0x400f0093 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_00 +CYREG_UDB_W8_MC_00 EQU 0x400f00a0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD0_MC__OFFSET +CYFLD_UDB_W8_PLD0_MC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD0_MC__SIZE +CYFLD_UDB_W8_PLD0_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD1_MC__OFFSET +CYFLD_UDB_W8_PLD1_MC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W8_PLD1_MC__SIZE +CYFLD_UDB_W8_PLD1_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_01 +CYREG_UDB_W8_MC_01 EQU 0x400f00a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_02 +CYREG_UDB_W8_MC_02 EQU 0x400f00a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W8_MC_03 +CYREG_UDB_W8_MC_03 EQU 0x400f00a3 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_CAT16_BASE +CYDEV_UDB_CAT16_BASE EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_CAT16_SIZE +CYDEV_UDB_CAT16_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_00 +CYREG_UDB_CAT16_A_00 EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A0__OFFSET +CYFLD_UDB_CAT16_A0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A0__SIZE +CYFLD_UDB_CAT16_A0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A1__OFFSET +CYFLD_UDB_CAT16_A1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_A1__SIZE +CYFLD_UDB_CAT16_A1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_01 +CYREG_UDB_CAT16_A_01 EQU 0x400f1002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_02 +CYREG_UDB_CAT16_A_02 EQU 0x400f1004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_A_03 +CYREG_UDB_CAT16_A_03 EQU 0x400f1006 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_00 +CYREG_UDB_CAT16_D_00 EQU 0x400f1040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D0__OFFSET +CYFLD_UDB_CAT16_D0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D0__SIZE +CYFLD_UDB_CAT16_D0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D1__OFFSET +CYFLD_UDB_CAT16_D1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_D1__SIZE +CYFLD_UDB_CAT16_D1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_01 +CYREG_UDB_CAT16_D_01 EQU 0x400f1042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_02 +CYREG_UDB_CAT16_D_02 EQU 0x400f1044 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_D_03 +CYREG_UDB_CAT16_D_03 EQU 0x400f1046 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_00 +CYREG_UDB_CAT16_F_00 EQU 0x400f1080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F0__OFFSET +CYFLD_UDB_CAT16_F0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F0__SIZE +CYFLD_UDB_CAT16_F0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F1__OFFSET +CYFLD_UDB_CAT16_F1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_F1__SIZE +CYFLD_UDB_CAT16_F1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_01 +CYREG_UDB_CAT16_F_01 EQU 0x400f1082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_02 +CYREG_UDB_CAT16_F_02 EQU 0x400f1084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_F_03 +CYREG_UDB_CAT16_F_03 EQU 0x400f1086 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_00 +CYREG_UDB_CAT16_CTL_ST_00 EQU 0x400f10c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_ST__OFFSET +CYFLD_UDB_CAT16_ST__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_ST__SIZE +CYFLD_UDB_CAT16_ST__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CTL__OFFSET +CYFLD_UDB_CAT16_CTL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CTL__SIZE +CYFLD_UDB_CAT16_CTL__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_01 +CYREG_UDB_CAT16_CTL_ST_01 EQU 0x400f10c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_02 +CYREG_UDB_CAT16_CTL_ST_02 EQU 0x400f10c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_CTL_ST_03 +CYREG_UDB_CAT16_CTL_ST_03 EQU 0x400f10c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_00 +CYREG_UDB_CAT16_ACTL_MSK_00 EQU 0x400f1100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_MSK__OFFSET +CYFLD_UDB_CAT16_MSK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_MSK__SIZE +CYFLD_UDB_CAT16_MSK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET +CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_CLR__SIZE +CYFLD_UDB_CAT16_FIFO0_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL +CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR +CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET +CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_CLR__SIZE +CYFLD_UDB_CAT16_FIFO1_CLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL +CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR +CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET +CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO0_LVL__SIZE +CYFLD_UDB_CAT16_FIFO0_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL +CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO0_LVL_MID +CYVAL_UDB_CAT16_FIFO0_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET +CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_FIFO1_LVL__SIZE +CYFLD_UDB_CAT16_FIFO1_LVL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL +CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_FIFO1_LVL_MID +CYVAL_UDB_CAT16_FIFO1_LVL_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_INT_EN__OFFSET +CYFLD_UDB_CAT16_INT_EN__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_INT_EN__SIZE +CYFLD_UDB_CAT16_INT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_INT_EN_DISABLE +CYVAL_UDB_CAT16_INT_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_INT_EN_ENABLE +CYVAL_UDB_CAT16_INT_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CNT_START__OFFSET +CYFLD_UDB_CAT16_CNT_START__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_CNT_START__SIZE +CYFLD_UDB_CAT16_CNT_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_CNT_START_DISABLE +CYVAL_UDB_CAT16_CNT_START_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_CAT16_CNT_START_ENABLE +CYVAL_UDB_CAT16_CNT_START_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_01 +CYREG_UDB_CAT16_ACTL_MSK_01 EQU 0x400f1102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_02 +CYREG_UDB_CAT16_ACTL_MSK_02 EQU 0x400f1104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_ACTL_MSK_03 +CYREG_UDB_CAT16_ACTL_MSK_03 EQU 0x400f1106 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_00 +CYREG_UDB_CAT16_MC_00 EQU 0x400f1140 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD0_MC__OFFSET +CYFLD_UDB_CAT16_PLD0_MC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD0_MC__SIZE +CYFLD_UDB_CAT16_PLD0_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD1_MC__OFFSET +CYFLD_UDB_CAT16_PLD1_MC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_CAT16_PLD1_MC__SIZE +CYFLD_UDB_CAT16_PLD1_MC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_01 +CYREG_UDB_CAT16_MC_01 EQU 0x400f1142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_02 +CYREG_UDB_CAT16_MC_02 EQU 0x400f1144 + ENDIF + IF :LNOT::DEF:CYREG_UDB_CAT16_MC_03 +CYREG_UDB_CAT16_MC_03 EQU 0x400f1146 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W16_BASE +CYDEV_UDB_W16_BASE EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W16_SIZE +CYDEV_UDB_W16_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A0_00 +CYREG_UDB_W16_A0_00 EQU 0x400f1000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_LS__OFFSET +CYFLD_UDB_W16_A0_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_LS__SIZE +CYFLD_UDB_W16_A0_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_MS__OFFSET +CYFLD_UDB_W16_A0_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A0_MS__SIZE +CYFLD_UDB_W16_A0_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A0_01 +CYREG_UDB_W16_A0_01 EQU 0x400f1002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A0_02 +CYREG_UDB_W16_A0_02 EQU 0x400f1004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A1_00 +CYREG_UDB_W16_A1_00 EQU 0x400f1020 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_LS__OFFSET +CYFLD_UDB_W16_A1_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_LS__SIZE +CYFLD_UDB_W16_A1_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_MS__OFFSET +CYFLD_UDB_W16_A1_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_A1_MS__SIZE +CYFLD_UDB_W16_A1_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A1_01 +CYREG_UDB_W16_A1_01 EQU 0x400f1022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_A1_02 +CYREG_UDB_W16_A1_02 EQU 0x400f1024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D0_00 +CYREG_UDB_W16_D0_00 EQU 0x400f1040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_LS__OFFSET +CYFLD_UDB_W16_D0_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_LS__SIZE +CYFLD_UDB_W16_D0_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_MS__OFFSET +CYFLD_UDB_W16_D0_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D0_MS__SIZE +CYFLD_UDB_W16_D0_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D0_01 +CYREG_UDB_W16_D0_01 EQU 0x400f1042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D0_02 +CYREG_UDB_W16_D0_02 EQU 0x400f1044 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D1_00 +CYREG_UDB_W16_D1_00 EQU 0x400f1060 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_LS__OFFSET +CYFLD_UDB_W16_D1_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_LS__SIZE +CYFLD_UDB_W16_D1_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_MS__OFFSET +CYFLD_UDB_W16_D1_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_D1_MS__SIZE +CYFLD_UDB_W16_D1_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D1_01 +CYREG_UDB_W16_D1_01 EQU 0x400f1062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_D1_02 +CYREG_UDB_W16_D1_02 EQU 0x400f1064 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F0_00 +CYREG_UDB_W16_F0_00 EQU 0x400f1080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_LS__OFFSET +CYFLD_UDB_W16_F0_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_LS__SIZE +CYFLD_UDB_W16_F0_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_MS__OFFSET +CYFLD_UDB_W16_F0_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F0_MS__SIZE +CYFLD_UDB_W16_F0_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F0_01 +CYREG_UDB_W16_F0_01 EQU 0x400f1082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F0_02 +CYREG_UDB_W16_F0_02 EQU 0x400f1084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F1_00 +CYREG_UDB_W16_F1_00 EQU 0x400f10a0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_LS__OFFSET +CYFLD_UDB_W16_F1_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_LS__SIZE +CYFLD_UDB_W16_F1_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_MS__OFFSET +CYFLD_UDB_W16_F1_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_F1_MS__SIZE +CYFLD_UDB_W16_F1_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F1_01 +CYREG_UDB_W16_F1_01 EQU 0x400f10a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_F1_02 +CYREG_UDB_W16_F1_02 EQU 0x400f10a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ST_00 +CYREG_UDB_W16_ST_00 EQU 0x400f10c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_LS__OFFSET +CYFLD_UDB_W16_ST_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_LS__SIZE +CYFLD_UDB_W16_ST_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_MS__OFFSET +CYFLD_UDB_W16_ST_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_ST_MS__SIZE +CYFLD_UDB_W16_ST_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ST_01 +CYREG_UDB_W16_ST_01 EQU 0x400f10c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ST_02 +CYREG_UDB_W16_ST_02 EQU 0x400f10c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_CTL_00 +CYREG_UDB_W16_CTL_00 EQU 0x400f10e0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_LS__OFFSET +CYFLD_UDB_W16_CTL_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_LS__SIZE +CYFLD_UDB_W16_CTL_LS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_MS__OFFSET +CYFLD_UDB_W16_CTL_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CTL_MS__SIZE +CYFLD_UDB_W16_CTL_MS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_CTL_01 +CYREG_UDB_W16_CTL_01 EQU 0x400f10e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_CTL_02 +CYREG_UDB_W16_CTL_02 EQU 0x400f10e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MSK_00 +CYREG_UDB_W16_MSK_00 EQU 0x400f1100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_LS__OFFSET +CYFLD_UDB_W16_MSK_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_LS__SIZE +CYFLD_UDB_W16_MSK_LS__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_MS__OFFSET +CYFLD_UDB_W16_MSK_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_MSK_MS__SIZE +CYFLD_UDB_W16_MSK_MS__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MSK_01 +CYREG_UDB_W16_MSK_01 EQU 0x400f1102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MSK_02 +CYREG_UDB_W16_MSK_02 EQU 0x400f1104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ACTL_00 +CYREG_UDB_W16_ACTL_00 EQU 0x400f1120 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET +CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE +CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL +CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR +CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET +CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE +CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL +CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR +CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET +CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE +CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL +CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_LS_MID +CYVAL_UDB_W16_FIFO0_LVL_LS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET +CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE +CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL +CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_LS_MID +CYVAL_UDB_W16_FIFO1_LVL_LS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_LS__OFFSET +CYFLD_UDB_W16_INT_EN_LS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_LS__SIZE +CYFLD_UDB_W16_INT_EN_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_LS_DISABLE +CYVAL_UDB_W16_INT_EN_LS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_LS_ENABLE +CYVAL_UDB_W16_INT_EN_LS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_LS__OFFSET +CYFLD_UDB_W16_CNT_START_LS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_LS__SIZE +CYFLD_UDB_W16_CNT_START_LS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_LS_DISABLE +CYVAL_UDB_W16_CNT_START_LS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_LS_ENABLE +CYVAL_UDB_W16_CNT_START_LS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET +CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE +CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL +CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR +CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET +CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE +CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL +CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR +CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET +CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE +CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL +CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO0_LVL_MS_MID +CYVAL_UDB_W16_FIFO0_LVL_MS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET +CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE +CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL +CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_FIFO1_LVL_MS_MID +CYVAL_UDB_W16_FIFO1_LVL_MS_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_MS__OFFSET +CYFLD_UDB_W16_INT_EN_MS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_INT_EN_MS__SIZE +CYFLD_UDB_W16_INT_EN_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_MS_DISABLE +CYVAL_UDB_W16_INT_EN_MS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_INT_EN_MS_ENABLE +CYVAL_UDB_W16_INT_EN_MS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_MS__OFFSET +CYFLD_UDB_W16_CNT_START_MS__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_CNT_START_MS__SIZE +CYFLD_UDB_W16_CNT_START_MS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_MS_DISABLE +CYVAL_UDB_W16_CNT_START_MS_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W16_CNT_START_MS_ENABLE +CYVAL_UDB_W16_CNT_START_MS_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ACTL_01 +CYREG_UDB_W16_ACTL_01 EQU 0x400f1122 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_ACTL_02 +CYREG_UDB_W16_ACTL_02 EQU 0x400f1124 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MC_00 +CYREG_UDB_W16_MC_00 EQU 0x400f1140 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_LS__OFFSET +CYFLD_UDB_W16_PLD0_MC_LS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_LS__SIZE +CYFLD_UDB_W16_PLD0_MC_LS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_LS__OFFSET +CYFLD_UDB_W16_PLD1_MC_LS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_LS__SIZE +CYFLD_UDB_W16_PLD1_MC_LS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_MS__OFFSET +CYFLD_UDB_W16_PLD0_MC_MS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD0_MC_MS__SIZE +CYFLD_UDB_W16_PLD0_MC_MS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_MS__OFFSET +CYFLD_UDB_W16_PLD1_MC_MS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W16_PLD1_MC_MS__SIZE +CYFLD_UDB_W16_PLD1_MC_MS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MC_01 +CYREG_UDB_W16_MC_01 EQU 0x400f1142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W16_MC_02 +CYREG_UDB_W16_MC_02 EQU 0x400f1144 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W32_BASE +CYDEV_UDB_W32_BASE EQU 0x400f2000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_W32_SIZE +CYDEV_UDB_W32_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_A0_00 +CYREG_UDB_W32_A0_00 EQU 0x400f2000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_0__OFFSET +CYFLD_UDB_W32_A0_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_0__SIZE +CYFLD_UDB_W32_A0_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_1__OFFSET +CYFLD_UDB_W32_A0_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_1__SIZE +CYFLD_UDB_W32_A0_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_2__OFFSET +CYFLD_UDB_W32_A0_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_2__SIZE +CYFLD_UDB_W32_A0_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_3__OFFSET +CYFLD_UDB_W32_A0_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A0_3__SIZE +CYFLD_UDB_W32_A0_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_A1_00 +CYREG_UDB_W32_A1_00 EQU 0x400f2040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_0__OFFSET +CYFLD_UDB_W32_A1_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_0__SIZE +CYFLD_UDB_W32_A1_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_1__OFFSET +CYFLD_UDB_W32_A1_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_1__SIZE +CYFLD_UDB_W32_A1_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_2__OFFSET +CYFLD_UDB_W32_A1_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_2__SIZE +CYFLD_UDB_W32_A1_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_3__OFFSET +CYFLD_UDB_W32_A1_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_A1_3__SIZE +CYFLD_UDB_W32_A1_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_D0_00 +CYREG_UDB_W32_D0_00 EQU 0x400f2080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_0__OFFSET +CYFLD_UDB_W32_D0_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_0__SIZE +CYFLD_UDB_W32_D0_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_1__OFFSET +CYFLD_UDB_W32_D0_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_1__SIZE +CYFLD_UDB_W32_D0_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_2__OFFSET +CYFLD_UDB_W32_D0_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_2__SIZE +CYFLD_UDB_W32_D0_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_3__OFFSET +CYFLD_UDB_W32_D0_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D0_3__SIZE +CYFLD_UDB_W32_D0_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_D1_00 +CYREG_UDB_W32_D1_00 EQU 0x400f20c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_0__OFFSET +CYFLD_UDB_W32_D1_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_0__SIZE +CYFLD_UDB_W32_D1_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_1__OFFSET +CYFLD_UDB_W32_D1_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_1__SIZE +CYFLD_UDB_W32_D1_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_2__OFFSET +CYFLD_UDB_W32_D1_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_2__SIZE +CYFLD_UDB_W32_D1_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_3__OFFSET +CYFLD_UDB_W32_D1_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_D1_3__SIZE +CYFLD_UDB_W32_D1_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_F0_00 +CYREG_UDB_W32_F0_00 EQU 0x400f2100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_0__OFFSET +CYFLD_UDB_W32_F0_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_0__SIZE +CYFLD_UDB_W32_F0_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_1__OFFSET +CYFLD_UDB_W32_F0_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_1__SIZE +CYFLD_UDB_W32_F0_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_2__OFFSET +CYFLD_UDB_W32_F0_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_2__SIZE +CYFLD_UDB_W32_F0_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_3__OFFSET +CYFLD_UDB_W32_F0_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F0_3__SIZE +CYFLD_UDB_W32_F0_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_F1_00 +CYREG_UDB_W32_F1_00 EQU 0x400f2140 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_0__OFFSET +CYFLD_UDB_W32_F1_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_0__SIZE +CYFLD_UDB_W32_F1_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_1__OFFSET +CYFLD_UDB_W32_F1_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_1__SIZE +CYFLD_UDB_W32_F1_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_2__OFFSET +CYFLD_UDB_W32_F1_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_2__SIZE +CYFLD_UDB_W32_F1_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_3__OFFSET +CYFLD_UDB_W32_F1_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_F1_3__SIZE +CYFLD_UDB_W32_F1_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_ST_00 +CYREG_UDB_W32_ST_00 EQU 0x400f2180 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_0__OFFSET +CYFLD_UDB_W32_ST_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_0__SIZE +CYFLD_UDB_W32_ST_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_1__OFFSET +CYFLD_UDB_W32_ST_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_1__SIZE +CYFLD_UDB_W32_ST_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_2__OFFSET +CYFLD_UDB_W32_ST_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_2__SIZE +CYFLD_UDB_W32_ST_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_3__OFFSET +CYFLD_UDB_W32_ST_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_ST_3__SIZE +CYFLD_UDB_W32_ST_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_CTL_00 +CYREG_UDB_W32_CTL_00 EQU 0x400f21c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_0__OFFSET +CYFLD_UDB_W32_CTL_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_0__SIZE +CYFLD_UDB_W32_CTL_0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_1__OFFSET +CYFLD_UDB_W32_CTL_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_1__SIZE +CYFLD_UDB_W32_CTL_1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_2__OFFSET +CYFLD_UDB_W32_CTL_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_2__SIZE +CYFLD_UDB_W32_CTL_2__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_3__OFFSET +CYFLD_UDB_W32_CTL_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CTL_3__SIZE +CYFLD_UDB_W32_CTL_3__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_MSK_00 +CYREG_UDB_W32_MSK_00 EQU 0x400f2200 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_0__OFFSET +CYFLD_UDB_W32_MSK_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_0__SIZE +CYFLD_UDB_W32_MSK_0__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_1__OFFSET +CYFLD_UDB_W32_MSK_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_1__SIZE +CYFLD_UDB_W32_MSK_1__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_2__OFFSET +CYFLD_UDB_W32_MSK_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_2__SIZE +CYFLD_UDB_W32_MSK_2__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_3__OFFSET +CYFLD_UDB_W32_MSK_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_MSK_3__SIZE +CYFLD_UDB_W32_MSK_3__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_ACTL_00 +CYREG_UDB_W32_ACTL_00 EQU 0x400f2240 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_0__SIZE +CYFLD_UDB_W32_FIFO0_CLR_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_0__SIZE +CYFLD_UDB_W32_FIFO1_CLR_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_0__SIZE +CYFLD_UDB_W32_FIFO0_LVL_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_0_MID +CYVAL_UDB_W32_FIFO0_LVL_0_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_0__SIZE +CYFLD_UDB_W32_FIFO1_LVL_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_0_MID +CYVAL_UDB_W32_FIFO1_LVL_0_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_0__OFFSET +CYFLD_UDB_W32_INT_EN_0__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_0__SIZE +CYFLD_UDB_W32_INT_EN_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_0_DISABLE +CYVAL_UDB_W32_INT_EN_0_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_0_ENABLE +CYVAL_UDB_W32_INT_EN_0_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_0__OFFSET +CYFLD_UDB_W32_CNT_START_0__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_0__SIZE +CYFLD_UDB_W32_CNT_START_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_0_DISABLE +CYVAL_UDB_W32_CNT_START_0_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_0_ENABLE +CYVAL_UDB_W32_CNT_START_0_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_1__SIZE +CYFLD_UDB_W32_FIFO0_CLR_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_1__SIZE +CYFLD_UDB_W32_FIFO1_CLR_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_1__SIZE +CYFLD_UDB_W32_FIFO0_LVL_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_1_MID +CYVAL_UDB_W32_FIFO0_LVL_1_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_1__SIZE +CYFLD_UDB_W32_FIFO1_LVL_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_1_MID +CYVAL_UDB_W32_FIFO1_LVL_1_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_1__OFFSET +CYFLD_UDB_W32_INT_EN_1__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_1__SIZE +CYFLD_UDB_W32_INT_EN_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_1_DISABLE +CYVAL_UDB_W32_INT_EN_1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_1_ENABLE +CYVAL_UDB_W32_INT_EN_1_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_1__OFFSET +CYFLD_UDB_W32_CNT_START_1__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_1__SIZE +CYFLD_UDB_W32_CNT_START_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_1_DISABLE +CYVAL_UDB_W32_CNT_START_1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_1_ENABLE +CYVAL_UDB_W32_CNT_START_1_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_2__SIZE +CYFLD_UDB_W32_FIFO0_CLR_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_2__SIZE +CYFLD_UDB_W32_FIFO1_CLR_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_2__SIZE +CYFLD_UDB_W32_FIFO0_LVL_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_2_MID +CYVAL_UDB_W32_FIFO0_LVL_2_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_2__SIZE +CYFLD_UDB_W32_FIFO1_LVL_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_2_MID +CYVAL_UDB_W32_FIFO1_LVL_2_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_2__OFFSET +CYFLD_UDB_W32_INT_EN_2__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_2__SIZE +CYFLD_UDB_W32_INT_EN_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_2_DISABLE +CYVAL_UDB_W32_INT_EN_2_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_2_ENABLE +CYVAL_UDB_W32_INT_EN_2_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_2__OFFSET +CYFLD_UDB_W32_CNT_START_2__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_2__SIZE +CYFLD_UDB_W32_CNT_START_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_2_DISABLE +CYVAL_UDB_W32_CNT_START_2_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_2_ENABLE +CYVAL_UDB_W32_CNT_START_2_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET +CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_CLR_3__SIZE +CYFLD_UDB_W32_FIFO0_CLR_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL +CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR +CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET +CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_CLR_3__SIZE +CYFLD_UDB_W32_FIFO1_CLR_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL +CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR +CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET +CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO0_LVL_3__SIZE +CYFLD_UDB_W32_FIFO0_LVL_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL +CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO0_LVL_3_MID +CYVAL_UDB_W32_FIFO0_LVL_3_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET +CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_FIFO1_LVL_3__SIZE +CYFLD_UDB_W32_FIFO1_LVL_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL +CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_FIFO1_LVL_3_MID +CYVAL_UDB_W32_FIFO1_LVL_3_MID EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_3__OFFSET +CYFLD_UDB_W32_INT_EN_3__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_INT_EN_3__SIZE +CYFLD_UDB_W32_INT_EN_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_3_DISABLE +CYVAL_UDB_W32_INT_EN_3_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_INT_EN_3_ENABLE +CYVAL_UDB_W32_INT_EN_3_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_3__OFFSET +CYFLD_UDB_W32_CNT_START_3__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_CNT_START_3__SIZE +CYFLD_UDB_W32_CNT_START_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_3_DISABLE +CYVAL_UDB_W32_CNT_START_3_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_W32_CNT_START_3_ENABLE +CYVAL_UDB_W32_CNT_START_3_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_W32_MC_00 +CYREG_UDB_W32_MC_00 EQU 0x400f2280 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_0__OFFSET +CYFLD_UDB_W32_PLD0_MC_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_0__SIZE +CYFLD_UDB_W32_PLD0_MC_0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_0__OFFSET +CYFLD_UDB_W32_PLD1_MC_0__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_0__SIZE +CYFLD_UDB_W32_PLD1_MC_0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_1__OFFSET +CYFLD_UDB_W32_PLD0_MC_1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_1__SIZE +CYFLD_UDB_W32_PLD0_MC_1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_1__OFFSET +CYFLD_UDB_W32_PLD1_MC_1__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_1__SIZE +CYFLD_UDB_W32_PLD1_MC_1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_2__OFFSET +CYFLD_UDB_W32_PLD0_MC_2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_2__SIZE +CYFLD_UDB_W32_PLD0_MC_2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_2__OFFSET +CYFLD_UDB_W32_PLD1_MC_2__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_2__SIZE +CYFLD_UDB_W32_PLD1_MC_2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_3__OFFSET +CYFLD_UDB_W32_PLD0_MC_3__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD0_MC_3__SIZE +CYFLD_UDB_W32_PLD0_MC_3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_3__OFFSET +CYFLD_UDB_W32_PLD1_MC_3__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_W32_PLD1_MC_3__SIZE +CYFLD_UDB_W32_PLD1_MC_3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_BASE +CYDEV_UDB_P0_BASE EQU 0x400f3000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_SIZE +CYDEV_UDB_P0_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U0_BASE +CYDEV_UDB_P0_U0_BASE EQU 0x400f3000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U0_SIZE +CYDEV_UDB_P0_U0_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT0 +CYREG_UDB_P0_U0_PLD_IT0 EQU 0x400f3000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET +CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE +CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET +CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE +CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET +CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE +CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET +CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE +CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT1 +CYREG_UDB_P0_U0_PLD_IT1 EQU 0x400f3004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT2 +CYREG_UDB_P0_U0_PLD_IT2 EQU 0x400f3008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT3 +CYREG_UDB_P0_U0_PLD_IT3 EQU 0x400f300c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT4 +CYREG_UDB_P0_U0_PLD_IT4 EQU 0x400f3010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT5 +CYREG_UDB_P0_U0_PLD_IT5 EQU 0x400f3014 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT6 +CYREG_UDB_P0_U0_PLD_IT6 EQU 0x400f3018 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT7 +CYREG_UDB_P0_U0_PLD_IT7 EQU 0x400f301c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT8 +CYREG_UDB_P0_U0_PLD_IT8 EQU 0x400f3020 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT9 +CYREG_UDB_P0_U0_PLD_IT9 EQU 0x400f3024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT10 +CYREG_UDB_P0_U0_PLD_IT10 EQU 0x400f3028 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_IT11 +CYREG_UDB_P0_U0_PLD_IT11 EQU 0x400f302c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT0 +CYREG_UDB_P0_U0_PLD_ORT0 EQU 0x400f3030 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET +CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE +CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET +CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE +CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT1 +CYREG_UDB_P0_U0_PLD_ORT1 EQU 0x400f3032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT2 +CYREG_UDB_P0_U0_PLD_ORT2 EQU 0x400f3034 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_ORT3 +CYREG_UDB_P0_U0_PLD_ORT3 EQU 0x400f3036 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST EQU 0x400f3038 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE +CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE +CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE +CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE +CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV +CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE +CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE +CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE +CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE +CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV +CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED +CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB +CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB EQU 0x400f303a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE +CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF +CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY +CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H +CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L +CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE +CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF +CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY +CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H +CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L +CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_SET_RESET +CYREG_UDB_P0_U0_PLD_MC_SET_RESET EQU 0x400f303c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE +CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE +CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE +CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS +CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS EQU 0x400f303e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC1__OFFSET +CYFLD_UDB_P_U_NC1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC1__SIZE +CYFLD_UDB_P_U_NC1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC3__OFFSET +CYFLD_UDB_P_U_NC3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC3__SIZE +CYFLD_UDB_P_U_NC3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC5__OFFSET +CYFLD_UDB_P_U_NC5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC5__SIZE +CYFLD_UDB_P_U_NC5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE +CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC7__OFFSET +CYFLD_UDB_P_U_NC7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC7__SIZE +CYFLD_UDB_P_U_NC7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC9__OFFSET +CYFLD_UDB_P_U_NC9__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC9__SIZE +CYFLD_UDB_P_U_NC9__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC11__OFFSET +CYFLD_UDB_P_U_NC11__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC11__SIZE +CYFLD_UDB_P_U_NC11__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC13__OFFSET +CYFLD_UDB_P_U_NC13__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC13__SIZE +CYFLD_UDB_P_U_NC13__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET +CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE +CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER +CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL +CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC15__OFFSET +CYFLD_UDB_P_U_NC15__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC15__SIZE +CYFLD_UDB_P_U_NC15__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG0 +CYREG_UDB_P0_U0_CFG0 EQU 0x400f3040 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD0__OFFSET +CYFLD_UDB_P_U_RAD0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD0__SIZE +CYFLD_UDB_P_U_RAD0__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_OFF +CYVAL_UDB_P_U_RAD0_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN0 +CYVAL_UDB_P_U_RAD0_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN1 +CYVAL_UDB_P_U_RAD0_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN2 +CYVAL_UDB_P_U_RAD0_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN3 +CYVAL_UDB_P_U_RAD0_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN4 +CYVAL_UDB_P_U_RAD0_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_DP_IN5 +CYVAL_UDB_P_U_RAD0_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD0_RESERVED +CYVAL_UDB_P_U_RAD0_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD1__OFFSET +CYFLD_UDB_P_U_RAD1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD1__SIZE +CYFLD_UDB_P_U_RAD1__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_OFF +CYVAL_UDB_P_U_RAD1_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN0 +CYVAL_UDB_P_U_RAD1_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN1 +CYVAL_UDB_P_U_RAD1_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN2 +CYVAL_UDB_P_U_RAD1_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN3 +CYVAL_UDB_P_U_RAD1_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN4 +CYVAL_UDB_P_U_RAD1_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_DP_IN5 +CYVAL_UDB_P_U_RAD1_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD1_RESERVED +CYVAL_UDB_P_U_RAD1_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG1 +CYREG_UDB_P0_U0_CFG1 EQU 0x400f3041 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD2__OFFSET +CYFLD_UDB_P_U_RAD2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RAD2__SIZE +CYFLD_UDB_P_U_RAD2__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_OFF +CYVAL_UDB_P_U_RAD2_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN0 +CYVAL_UDB_P_U_RAD2_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN1 +CYVAL_UDB_P_U_RAD2_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN2 +CYVAL_UDB_P_U_RAD2_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN3 +CYVAL_UDB_P_U_RAD2_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN4 +CYVAL_UDB_P_U_RAD2_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_DP_IN5 +CYVAL_UDB_P_U_RAD2_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RAD2_RESERVED +CYVAL_UDB_P_U_RAD2_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG2 +CYREG_UDB_P0_U0_CFG2 EQU 0x400f3042 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_LD__OFFSET +CYFLD_UDB_P_U_F0_LD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_LD__SIZE +CYFLD_UDB_P_U_F0_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_OFF +CYVAL_UDB_P_U_F0_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN0 +CYVAL_UDB_P_U_F0_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN1 +CYVAL_UDB_P_U_F0_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN2 +CYVAL_UDB_P_U_F0_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN3 +CYVAL_UDB_P_U_F0_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN4 +CYVAL_UDB_P_U_F0_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_DP_IN5 +CYVAL_UDB_P_U_F0_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_LD_RESERVED +CYVAL_UDB_P_U_F0_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET +CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE +CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE +CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS +CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_LD__OFFSET +CYFLD_UDB_P_U_F1_LD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_LD__SIZE +CYFLD_UDB_P_U_F1_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_OFF +CYVAL_UDB_P_U_F1_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN0 +CYVAL_UDB_P_U_F1_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN1 +CYVAL_UDB_P_U_F1_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN2 +CYVAL_UDB_P_U_F1_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN3 +CYVAL_UDB_P_U_F1_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN4 +CYVAL_UDB_P_U_F1_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_DP_IN5 +CYVAL_UDB_P_U_F1_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_LD_RESERVED +CYVAL_UDB_P_U_F1_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG3 +CYREG_UDB_P0_U0_CFG3 EQU 0x400f3043 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D0_LD__OFFSET +CYFLD_UDB_P_U_D0_LD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D0_LD__SIZE +CYFLD_UDB_P_U_D0_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_OFF +CYVAL_UDB_P_U_D0_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN0 +CYVAL_UDB_P_U_D0_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN1 +CYVAL_UDB_P_U_D0_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN2 +CYVAL_UDB_P_U_D0_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN3 +CYVAL_UDB_P_U_D0_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN4 +CYVAL_UDB_P_U_D0_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_DP_IN5 +CYVAL_UDB_P_U_D0_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D0_LD_RESERVED +CYVAL_UDB_P_U_D0_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D1_LD__OFFSET +CYFLD_UDB_P_U_D1_LD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_D1_LD__SIZE +CYFLD_UDB_P_U_D1_LD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_OFF +CYVAL_UDB_P_U_D1_LD_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN0 +CYVAL_UDB_P_U_D1_LD_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN1 +CYVAL_UDB_P_U_D1_LD_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN2 +CYVAL_UDB_P_U_D1_LD_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN3 +CYVAL_UDB_P_U_D1_LD_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN4 +CYVAL_UDB_P_U_D1_LD_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_DP_IN5 +CYVAL_UDB_P_U_D1_LD_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_D1_LD_RESERVED +CYVAL_UDB_P_U_D1_LD_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG4 +CYREG_UDB_P0_U0_CFG4 EQU 0x400f3044 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_MUX__OFFSET +CYFLD_UDB_P_U_SI_MUX__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_MUX__SIZE +CYFLD_UDB_P_U_SI_MUX__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_OFF +CYVAL_UDB_P_U_SI_MUX_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN0 +CYVAL_UDB_P_U_SI_MUX_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN1 +CYVAL_UDB_P_U_SI_MUX_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN2 +CYVAL_UDB_P_U_SI_MUX_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN3 +CYVAL_UDB_P_U_SI_MUX_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN4 +CYVAL_UDB_P_U_SI_MUX_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_DP_IN5 +CYVAL_UDB_P_U_SI_MUX_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_MUX_RESERVED +CYVAL_UDB_P_U_SI_MUX_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_MUX__OFFSET +CYFLD_UDB_P_U_CI_MUX__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_MUX__SIZE +CYFLD_UDB_P_U_CI_MUX__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_OFF +CYVAL_UDB_P_U_CI_MUX_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN0 +CYVAL_UDB_P_U_CI_MUX_DP_IN0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN1 +CYVAL_UDB_P_U_CI_MUX_DP_IN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN2 +CYVAL_UDB_P_U_CI_MUX_DP_IN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN3 +CYVAL_UDB_P_U_CI_MUX_DP_IN3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN4 +CYVAL_UDB_P_U_CI_MUX_DP_IN4 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_DP_IN5 +CYVAL_UDB_P_U_CI_MUX_DP_IN5 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_MUX_RESERVED +CYVAL_UDB_P_U_CI_MUX_RESERVED EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG5 +CYREG_UDB_P0_U0_CFG5 EQU 0x400f3045 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT0__OFFSET +CYFLD_UDB_P_U_OUT0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT0__SIZE +CYFLD_UDB_P_U_OUT0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CE0 +CYVAL_UDB_P_U_OUT0_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CL0 +CYVAL_UDB_P_U_OUT0_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_Z0 +CYVAL_UDB_P_U_OUT0_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_FF0 +CYVAL_UDB_P_U_OUT0_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CE1 +CYVAL_UDB_P_U_OUT0_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CL1 +CYVAL_UDB_P_U_OUT0_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_Z1 +CYVAL_UDB_P_U_OUT0_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_FF1 +CYVAL_UDB_P_U_OUT0_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_OV_MSB +CYVAL_UDB_P_U_OUT0_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CO_MSB +CYVAL_UDB_P_U_OUT0_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_CMSBO +CYVAL_UDB_P_U_OUT0_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_SO +CYVAL_UDB_P_U_OUT0_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F0_BLK_STAT +CYVAL_UDB_P_U_OUT0_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F1_BLK_STAT +CYVAL_UDB_P_U_OUT0_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F0_BUS_STAT +CYVAL_UDB_P_U_OUT0_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT0_F1_BUS_STAT +CYVAL_UDB_P_U_OUT0_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT1__OFFSET +CYFLD_UDB_P_U_OUT1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT1__SIZE +CYFLD_UDB_P_U_OUT1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CE0 +CYVAL_UDB_P_U_OUT1_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CL0 +CYVAL_UDB_P_U_OUT1_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_Z0 +CYVAL_UDB_P_U_OUT1_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_FF0 +CYVAL_UDB_P_U_OUT1_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CE1 +CYVAL_UDB_P_U_OUT1_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CL1 +CYVAL_UDB_P_U_OUT1_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_Z1 +CYVAL_UDB_P_U_OUT1_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_FF1 +CYVAL_UDB_P_U_OUT1_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_OV_MSB +CYVAL_UDB_P_U_OUT1_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CO_MSB +CYVAL_UDB_P_U_OUT1_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_CMSBO +CYVAL_UDB_P_U_OUT1_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_SO +CYVAL_UDB_P_U_OUT1_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F0_BLK_STAT +CYVAL_UDB_P_U_OUT1_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F1_BLK_STAT +CYVAL_UDB_P_U_OUT1_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F0_BUS_STAT +CYVAL_UDB_P_U_OUT1_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT1_F1_BUS_STAT +CYVAL_UDB_P_U_OUT1_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG6 +CYREG_UDB_P0_U0_CFG6 EQU 0x400f3046 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT2__OFFSET +CYFLD_UDB_P_U_OUT2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT2__SIZE +CYFLD_UDB_P_U_OUT2__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CE0 +CYVAL_UDB_P_U_OUT2_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CL0 +CYVAL_UDB_P_U_OUT2_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_Z0 +CYVAL_UDB_P_U_OUT2_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_FF0 +CYVAL_UDB_P_U_OUT2_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CE1 +CYVAL_UDB_P_U_OUT2_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CL1 +CYVAL_UDB_P_U_OUT2_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_Z1 +CYVAL_UDB_P_U_OUT2_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_FF1 +CYVAL_UDB_P_U_OUT2_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_OV_MSB +CYVAL_UDB_P_U_OUT2_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CO_MSB +CYVAL_UDB_P_U_OUT2_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_CMSBO +CYVAL_UDB_P_U_OUT2_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_SO +CYVAL_UDB_P_U_OUT2_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F0_BLK_STAT +CYVAL_UDB_P_U_OUT2_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F1_BLK_STAT +CYVAL_UDB_P_U_OUT2_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F0_BUS_STAT +CYVAL_UDB_P_U_OUT2_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT2_F1_BUS_STAT +CYVAL_UDB_P_U_OUT2_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT3__OFFSET +CYFLD_UDB_P_U_OUT3__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT3__SIZE +CYFLD_UDB_P_U_OUT3__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CE0 +CYVAL_UDB_P_U_OUT3_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CL0 +CYVAL_UDB_P_U_OUT3_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_Z0 +CYVAL_UDB_P_U_OUT3_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_FF0 +CYVAL_UDB_P_U_OUT3_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CE1 +CYVAL_UDB_P_U_OUT3_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CL1 +CYVAL_UDB_P_U_OUT3_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_Z1 +CYVAL_UDB_P_U_OUT3_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_FF1 +CYVAL_UDB_P_U_OUT3_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_OV_MSB +CYVAL_UDB_P_U_OUT3_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CO_MSB +CYVAL_UDB_P_U_OUT3_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_CMSBO +CYVAL_UDB_P_U_OUT3_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_SO +CYVAL_UDB_P_U_OUT3_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F0_BLK_STAT +CYVAL_UDB_P_U_OUT3_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F1_BLK_STAT +CYVAL_UDB_P_U_OUT3_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F0_BUS_STAT +CYVAL_UDB_P_U_OUT3_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT3_F1_BUS_STAT +CYVAL_UDB_P_U_OUT3_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG7 +CYREG_UDB_P0_U0_CFG7 EQU 0x400f3047 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT4__OFFSET +CYFLD_UDB_P_U_OUT4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT4__SIZE +CYFLD_UDB_P_U_OUT4__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CE0 +CYVAL_UDB_P_U_OUT4_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CL0 +CYVAL_UDB_P_U_OUT4_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_Z0 +CYVAL_UDB_P_U_OUT4_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_FF0 +CYVAL_UDB_P_U_OUT4_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CE1 +CYVAL_UDB_P_U_OUT4_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CL1 +CYVAL_UDB_P_U_OUT4_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_Z1 +CYVAL_UDB_P_U_OUT4_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_FF1 +CYVAL_UDB_P_U_OUT4_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_OV_MSB +CYVAL_UDB_P_U_OUT4_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CO_MSB +CYVAL_UDB_P_U_OUT4_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_CMSBO +CYVAL_UDB_P_U_OUT4_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_SO +CYVAL_UDB_P_U_OUT4_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F0_BLK_STAT +CYVAL_UDB_P_U_OUT4_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F1_BLK_STAT +CYVAL_UDB_P_U_OUT4_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F0_BUS_STAT +CYVAL_UDB_P_U_OUT4_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT4_F1_BUS_STAT +CYVAL_UDB_P_U_OUT4_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT5__OFFSET +CYFLD_UDB_P_U_OUT5__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT5__SIZE +CYFLD_UDB_P_U_OUT5__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CE0 +CYVAL_UDB_P_U_OUT5_CE0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CL0 +CYVAL_UDB_P_U_OUT5_CL0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_Z0 +CYVAL_UDB_P_U_OUT5_Z0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_FF0 +CYVAL_UDB_P_U_OUT5_FF0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CE1 +CYVAL_UDB_P_U_OUT5_CE1 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CL1 +CYVAL_UDB_P_U_OUT5_CL1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_Z1 +CYVAL_UDB_P_U_OUT5_Z1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_FF1 +CYVAL_UDB_P_U_OUT5_FF1 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_OV_MSB +CYVAL_UDB_P_U_OUT5_OV_MSB EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CO_MSB +CYVAL_UDB_P_U_OUT5_CO_MSB EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_CMSBO +CYVAL_UDB_P_U_OUT5_CMSBO EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_SO +CYVAL_UDB_P_U_OUT5_SO EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F0_BLK_STAT +CYVAL_UDB_P_U_OUT5_F0_BLK_STAT EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F1_BLK_STAT +CYVAL_UDB_P_U_OUT5_F1_BLK_STAT EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F0_BUS_STAT +CYVAL_UDB_P_U_OUT5_F0_BUS_STAT EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT5_F1_BUS_STAT +CYVAL_UDB_P_U_OUT5_F1_BUS_STAT EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG8 +CYREG_UDB_P0_U0_CFG8 EQU 0x400f3048 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT_SYNC__OFFSET +CYFLD_UDB_P_U_OUT_SYNC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_OUT_SYNC__SIZE +CYFLD_UDB_P_U_OUT_SYNC__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT_SYNC_REGISTERED +CYVAL_UDB_P_U_OUT_SYNC_REGISTERED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL +CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC6__OFFSET +CYFLD_UDB_P_U_NC6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC6__SIZE +CYFLD_UDB_P_U_NC6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG9 +CYREG_UDB_P0_U0_CFG9 EQU 0x400f3049 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK__OFFSET +CYFLD_UDB_P_U_AMASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK__SIZE +CYFLD_UDB_P_U_AMASK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG10 +CYREG_UDB_P0_U0_CFG10 EQU 0x400f304a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0__OFFSET +CYFLD_UDB_P_U_CMASK0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0__SIZE +CYFLD_UDB_P_U_CMASK0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG11 +CYREG_UDB_P0_U0_CFG11 EQU 0x400f304b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG12 +CYREG_UDB_P0_U0_CFG12 EQU 0x400f304c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELA__OFFSET +CYFLD_UDB_P_U_SI_SELA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELA__SIZE +CYFLD_UDB_P_U_SI_SELA__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_DEFAULT +CYVAL_UDB_P_U_SI_SELA_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_REGISTERED +CYVAL_UDB_P_U_SI_SELA_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_ROUTE +CYVAL_UDB_P_U_SI_SELA_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELA_CHAIN +CYVAL_UDB_P_U_SI_SELA_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELB__OFFSET +CYFLD_UDB_P_U_SI_SELB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SELB__SIZE +CYFLD_UDB_P_U_SI_SELB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_DEFAULT +CYVAL_UDB_P_U_SI_SELB_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_REGISTERED +CYVAL_UDB_P_U_SI_SELB_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_ROUTE +CYVAL_UDB_P_U_SI_SELB_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SELB_CHAIN +CYVAL_UDB_P_U_SI_SELB_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DEF_SI__OFFSET +CYFLD_UDB_P_U_DEF_SI__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DEF_SI__SIZE +CYFLD_UDB_P_U_DEF_SI__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 +CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 +CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK_EN__OFFSET +CYFLD_UDB_P_U_AMASK_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_AMASK_EN__SIZE +CYFLD_UDB_P_U_AMASK_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_AMASK_EN_DISABLE +CYVAL_UDB_P_U_AMASK_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_AMASK_EN_ENABLE +CYVAL_UDB_P_U_AMASK_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0_EN__OFFSET +CYFLD_UDB_P_U_CMASK0_EN__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK0_EN__SIZE +CYFLD_UDB_P_U_CMASK0_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK0_EN_DISABLE +CYVAL_UDB_P_U_CMASK0_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK0_EN_ENABLE +CYVAL_UDB_P_U_CMASK0_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK1_EN__OFFSET +CYFLD_UDB_P_U_CMASK1_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMASK1_EN__SIZE +CYFLD_UDB_P_U_CMASK1_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK1_EN_DISABLE +CYVAL_UDB_P_U_CMASK1_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMASK1_EN_ENABLE +CYVAL_UDB_P_U_CMASK1_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG13 +CYREG_UDB_P0_U0_CFG13 EQU 0x400f304d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELA__OFFSET +CYFLD_UDB_P_U_CI_SELA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELA__SIZE +CYFLD_UDB_P_U_CI_SELA__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_DEFAULT +CYVAL_UDB_P_U_CI_SELA_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_REGISTERED +CYVAL_UDB_P_U_CI_SELA_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_ROUTE +CYVAL_UDB_P_U_CI_SELA_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELA_CHAIN +CYVAL_UDB_P_U_CI_SELA_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELB__OFFSET +CYFLD_UDB_P_U_CI_SELB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SELB__SIZE +CYFLD_UDB_P_U_CI_SELB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_DEFAULT +CYVAL_UDB_P_U_CI_SELB_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_REGISTERED +CYVAL_UDB_P_U_CI_SELB_REGISTERED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_ROUTE +CYVAL_UDB_P_U_CI_SELB_ROUTE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SELB_CHAIN +CYVAL_UDB_P_U_CI_SELB_CHAIN EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELA__OFFSET +CYFLD_UDB_P_U_CMP_SELA__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELA__SIZE +CYFLD_UDB_P_U_CMP_SELA__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A1_D1 +CYVAL_UDB_P_U_CMP_SELA_A1_D1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A1_A0 +CYVAL_UDB_P_U_CMP_SELA_A1_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A0_D1 +CYVAL_UDB_P_U_CMP_SELA_A0_D1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELA_A0_A0 +CYVAL_UDB_P_U_CMP_SELA_A0_A0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELB__OFFSET +CYFLD_UDB_P_U_CMP_SELB__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SELB__SIZE +CYFLD_UDB_P_U_CMP_SELB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A1_D1 +CYVAL_UDB_P_U_CMP_SELB_A1_D1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A1_A0 +CYVAL_UDB_P_U_CMP_SELB_A1_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A0_D1 +CYVAL_UDB_P_U_CMP_SELB_A0_D1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SELB_A0_A0 +CYVAL_UDB_P_U_CMP_SELB_A0_A0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG14 +CYREG_UDB_P0_U0_CFG14 EQU 0x400f304e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN0__OFFSET +CYFLD_UDB_P_U_CHAIN0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN0__SIZE +CYFLD_UDB_P_U_CHAIN0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN0_DISABLE +CYVAL_UDB_P_U_CHAIN0_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN0_ENABLE +CYVAL_UDB_P_U_CHAIN0_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN1__OFFSET +CYFLD_UDB_P_U_CHAIN1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN1__SIZE +CYFLD_UDB_P_U_CHAIN1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN1_DISABLE +CYVAL_UDB_P_U_CHAIN1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN1_ENABLE +CYVAL_UDB_P_U_CHAIN1_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_FB__OFFSET +CYFLD_UDB_P_U_CHAIN_FB__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_FB__SIZE +CYFLD_UDB_P_U_CHAIN_FB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_FB_DISABLE +CYVAL_UDB_P_U_CHAIN_FB_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_FB_ENABLE +CYVAL_UDB_P_U_CHAIN_FB_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET +CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CHAIN_CMSB__SIZE +CYFLD_UDB_P_U_CHAIN_CMSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE +CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE +CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SEL__OFFSET +CYFLD_UDB_P_U_MSB_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SEL__SIZE +CYFLD_UDB_P_U_MSB_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT0 +CYVAL_UDB_P_U_MSB_SEL_BIT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT1 +CYVAL_UDB_P_U_MSB_SEL_BIT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT2 +CYVAL_UDB_P_U_MSB_SEL_BIT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT3 +CYVAL_UDB_P_U_MSB_SEL_BIT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT4 +CYVAL_UDB_P_U_MSB_SEL_BIT4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT5 +CYVAL_UDB_P_U_MSB_SEL_BIT5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT6 +CYVAL_UDB_P_U_MSB_SEL_BIT6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SEL_BIT7 +CYVAL_UDB_P_U_MSB_SEL_BIT7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_EN__OFFSET +CYFLD_UDB_P_U_MSB_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_EN__SIZE +CYFLD_UDB_P_U_MSB_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_EN_DISABLE +CYVAL_UDB_P_U_MSB_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_EN_ENABLE +CYVAL_UDB_P_U_MSB_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG15 +CYREG_UDB_P0_U0_CFG15 EQU 0x400f304f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_INSEL__OFFSET +CYFLD_UDB_P_U_F0_INSEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_INSEL__SIZE +CYFLD_UDB_P_U_F0_INSEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_INPUT +CYVAL_UDB_P_U_F0_INSEL_INPUT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 +CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 +CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU +CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_INSEL__OFFSET +CYFLD_UDB_P_U_F1_INSEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_INSEL__SIZE +CYFLD_UDB_P_U_F1_INSEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_INPUT +CYVAL_UDB_P_U_F1_INSEL_INPUT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 +CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 +CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU +CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SI__OFFSET +CYFLD_UDB_P_U_MSB_SI__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_MSB_SI__SIZE +CYFLD_UDB_P_U_MSB_SI__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SI_DEFAULT +CYVAL_UDB_P_U_MSB_SI_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_MSB_SI_MSB +CYVAL_UDB_P_U_MSB_SI_MSB EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_DYN__OFFSET +CYFLD_UDB_P_U_PI_DYN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_DYN__SIZE +CYFLD_UDB_P_U_PI_DYN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_DYN_DISABLE +CYVAL_UDB_P_U_PI_DYN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_DYN_ENABLE +CYVAL_UDB_P_U_PI_DYN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT_SEL__OFFSET +CYFLD_UDB_P_U_SHIFT_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT_SEL__SIZE +CYFLD_UDB_P_U_SHIFT_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB +CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_SEL_SOR +CYVAL_UDB_P_U_SHIFT_SEL_SOR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_SEL__OFFSET +CYFLD_UDB_P_U_PI_SEL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PI_SEL__SIZE +CYFLD_UDB_P_U_PI_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_SEL_NORMAL +CYVAL_UDB_P_U_PI_SEL_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PI_SEL_PARALLEL +CYVAL_UDB_P_U_PI_SEL_PARALLEL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG16 +CYREG_UDB_P0_U0_CFG16 EQU 0x400f3050 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET +CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_WRK16_CONCAT__SIZE +CYFLD_UDB_P_U_WRK16_CONCAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT +CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE +CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET +CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CRCPRS__SIZE +CYFLD_UDB_P_U_EXT_CRCPRS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL +CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL +CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET +CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ASYNC__SIZE +CYFLD_UDB_P_U_FIFO_ASYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE +CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE +CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_EDGE__OFFSET +CYFLD_UDB_P_U_FIFO_EDGE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_EDGE__SIZE +CYFLD_UDB_P_U_FIFO_EDGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_EDGE_LEVEL +CYVAL_UDB_P_U_FIFO_EDGE_LEVEL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_EDGE_EDGE +CYVAL_UDB_P_U_FIFO_EDGE_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_CAP__OFFSET +CYFLD_UDB_P_U_FIFO_CAP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_CAP__SIZE +CYFLD_UDB_P_U_FIFO_CAP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_CAP_DISABLE +CYVAL_UDB_P_U_FIFO_CAP_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_CAP_ENABLE +CYVAL_UDB_P_U_FIFO_CAP_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_FAST__OFFSET +CYFLD_UDB_P_U_FIFO_FAST__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_FAST__SIZE +CYFLD_UDB_P_U_FIFO_FAST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_FAST_DISABLE +CYVAL_UDB_P_U_FIFO_FAST_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_FAST_ENABLE +CYVAL_UDB_P_U_FIFO_FAST_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_CK_INV__OFFSET +CYFLD_UDB_P_U_F0_CK_INV__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_CK_INV__SIZE +CYFLD_UDB_P_U_F0_CK_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_CK_INV_NORMAL +CYVAL_UDB_P_U_F0_CK_INV_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_CK_INV_INVERT +CYVAL_UDB_P_U_F0_CK_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_CK_INV__OFFSET +CYFLD_UDB_P_U_F1_CK_INV__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_CK_INV__SIZE +CYFLD_UDB_P_U_F1_CK_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_CK_INV_NORMAL +CYVAL_UDB_P_U_F1_CK_INV_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_CK_INV_INVERT +CYVAL_UDB_P_U_F1_CK_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG17 +CYREG_UDB_P0_U0_CFG17 EQU 0x400f3051 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_DYN__OFFSET +CYFLD_UDB_P_U_F0_DYN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F0_DYN__SIZE +CYFLD_UDB_P_U_F0_DYN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_DYN_STATIC +CYVAL_UDB_P_U_F0_DYN_STATIC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F0_DYN_DYNAMIC +CYVAL_UDB_P_U_F0_DYN_DYNAMIC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_DYN__OFFSET +CYFLD_UDB_P_U_F1_DYN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_F1_DYN__SIZE +CYFLD_UDB_P_U_F1_DYN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_DYN_STATIC +CYVAL_UDB_P_U_F1_DYN_STATIC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_F1_DYN_DYNAMIC +CYVAL_UDB_P_U_F1_DYN_DYNAMIC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC2__OFFSET +CYFLD_UDB_P_U_NC2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC2__SIZE +CYFLD_UDB_P_U_NC2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET +CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE +CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE +CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE +CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG18 +CYREG_UDB_P0_U0_CFG18 EQU 0x400f3052 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD0__OFFSET +CYFLD_UDB_P_U_CTL_MD0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD0__SIZE +CYFLD_UDB_P_U_CTL_MD0__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_DIRECT +CYVAL_UDB_P_U_CTL_MD0_DIRECT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_SYNC +CYVAL_UDB_P_U_CTL_MD0_SYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC +CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD0_PULSE +CYVAL_UDB_P_U_CTL_MD0_PULSE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG19 +CYREG_UDB_P0_U0_CFG19 EQU 0x400f3053 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD1__OFFSET +CYFLD_UDB_P_U_CTL_MD1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CTL_MD1__SIZE +CYFLD_UDB_P_U_CTL_MD1__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_DIRECT +CYVAL_UDB_P_U_CTL_MD1_DIRECT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_SYNC +CYVAL_UDB_P_U_CTL_MD1_SYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC +CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CTL_MD1_PULSE +CYVAL_UDB_P_U_CTL_MD1_PULSE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG20 +CYREG_UDB_P0_U0_CFG20 EQU 0x400f3054 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_STAT_MD__OFFSET +CYFLD_UDB_P_U_STAT_MD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_STAT_MD__SIZE +CYFLD_UDB_P_U_STAT_MD__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG21 +CYREG_UDB_P0_U0_CFG21 EQU 0x400f3055 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC0__OFFSET +CYFLD_UDB_P_U_NC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_NC0__SIZE +CYFLD_UDB_P_U_NC0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG22 +CYREG_UDB_P0_U0_CFG22 EQU 0x400f3056 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET +CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_OUT_CTL__SIZE +CYFLD_UDB_P_U_SC_OUT_CTL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL +CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL +CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER +CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED +CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_INT_MD__OFFSET +CYFLD_UDB_P_U_SC_INT_MD__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_INT_MD__SIZE +CYFLD_UDB_P_U_SC_INT_MD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_INT_MD_NORMAL +CYVAL_UDB_P_U_SC_INT_MD_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_INT_MD_INT_MODE +CYVAL_UDB_P_U_SC_INT_MD_INT_MODE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET +CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_SYNC_MD__SIZE +CYFLD_UDB_P_U_SC_SYNC_MD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL +CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE +CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_EXT_RES__OFFSET +CYFLD_UDB_P_U_SC_EXT_RES__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_EXT_RES__SIZE +CYFLD_UDB_P_U_SC_EXT_RES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_EXT_RES_DISABLED +CYVAL_UDB_P_U_SC_EXT_RES_DISABLED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_EXT_RES_ENABLED +CYVAL_UDB_P_U_SC_EXT_RES_ENABLED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG23 +CYREG_UDB_P0_U0_CFG23 EQU 0x400f3057 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET +CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_LD_SEL__SIZE +CYFLD_UDB_P_U_CNT_LD_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 +CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET +CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CNT_EN_SEL__SIZE +CYFLD_UDB_P_U_CNT_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO +CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_LD__OFFSET +CYFLD_UDB_P_U_ROUTE_LD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_LD__SIZE +CYFLD_UDB_P_U_ROUTE_LD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_LD_DISABLE +CYVAL_UDB_P_U_ROUTE_LD_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_LD_ROUTED +CYVAL_UDB_P_U_ROUTE_LD_ROUTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_EN__OFFSET +CYFLD_UDB_P_U_ROUTE_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ROUTE_EN__SIZE +CYFLD_UDB_P_U_ROUTE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_EN_DISABLE +CYVAL_UDB_P_U_ROUTE_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ROUTE_EN_ROUTED +CYVAL_UDB_P_U_ROUTE_EN_ROUTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_CNT__OFFSET +CYFLD_UDB_P_U_ALT_CNT__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_CNT__SIZE +CYFLD_UDB_P_U_ALT_CNT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE +CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_CNT_ALT_MODE +CYVAL_UDB_P_U_ALT_CNT_ALT_MODE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG24 +CYREG_UDB_P0_U0_CFG24 EQU 0x400f3058 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_SEL__OFFSET +CYFLD_UDB_P_U_RC_EN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_SEL__SIZE +CYFLD_UDB_P_U_RC_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 +CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_MODE__OFFSET +CYFLD_UDB_P_U_RC_EN_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_MODE__SIZE +CYFLD_UDB_P_U_RC_EN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_OFF +CYVAL_UDB_P_U_RC_EN_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_ON +CYVAL_UDB_P_U_RC_EN_MODE_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE +CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_MODE_LEVEL +CYVAL_UDB_P_U_RC_EN_MODE_LEVEL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_INV__OFFSET +CYFLD_UDB_P_U_RC_EN_INV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_EN_INV__SIZE +CYFLD_UDB_P_U_RC_EN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_INV_NOINV +CYVAL_UDB_P_U_RC_EN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_EN_INV_INVERT +CYVAL_UDB_P_U_RC_EN_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_INV__OFFSET +CYFLD_UDB_P_U_RC_INV__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_INV__SIZE +CYFLD_UDB_P_U_RC_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_INV_NOINV +CYVAL_UDB_P_U_RC_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RC_INV_INVERT +CYVAL_UDB_P_U_RC_INV_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET +CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE +CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET +CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RC_RES_SEL1__SIZE +CYFLD_UDB_P_U_RC_RES_SEL1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG25 +CYREG_UDB_P0_U0_CFG25 EQU 0x400f3059 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG26 +CYREG_UDB_P0_U0_CFG26 EQU 0x400f305a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG27 +CYREG_UDB_P0_U0_CFG27 EQU 0x400f305b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG28 +CYREG_UDB_P0_U0_CFG28 EQU 0x400f305c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET +CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE +CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 +CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK +CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET +CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE +CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 +CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK +CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG29 +CYREG_UDB_P0_U0_CFG29 EQU 0x400f305d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_CK_SEL__OFFSET +CYFLD_UDB_P_U_DP_CK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_CK_SEL__SIZE +CYFLD_UDB_P_U_DP_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 +CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK +CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_CK_SEL__OFFSET +CYFLD_UDB_P_U_SC_CK_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_CK_SEL__SIZE +CYFLD_UDB_P_U_SC_CK_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 +CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK +CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK +CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG30 +CYREG_UDB_P0_U0_CFG30 EQU 0x400f305e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_SEL__OFFSET +CYFLD_UDB_P_U_RES_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_SEL__SIZE +CYFLD_UDB_P_U_RES_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN0 +CYVAL_UDB_P_U_RES_SEL_RC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN1 +CYVAL_UDB_P_U_RES_SEL_RC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN2 +CYVAL_UDB_P_U_RES_SEL_RC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_SEL_RC_IN3 +CYVAL_UDB_P_U_RES_SEL_RC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_POL__OFFSET +CYFLD_UDB_P_U_RES_POL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_RES_POL__SIZE +CYFLD_UDB_P_U_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_POL_NEGATED +CYVAL_UDB_P_U_RES_POL_NEGATED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_RES_POL_ASSERTED +CYVAL_UDB_P_U_RES_POL_ASSERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET +CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE +CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE +CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE +CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_GUDB_WR__OFFSET +CYFLD_UDB_P_U_GUDB_WR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_GUDB_WR__SIZE +CYFLD_UDB_P_U_GUDB_WR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_GUDB_WR_DISABLE +CYVAL_UDB_P_U_GUDB_WR_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_GUDB_WR_ENABLE +CYVAL_UDB_P_U_GUDB_WR_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RES_POL__OFFSET +CYFLD_UDB_P_U_DP_RES_POL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_DP_RES_POL__SIZE +CYFLD_UDB_P_U_DP_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RES_POL_NOINV +CYVAL_UDB_P_U_DP_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_DP_RES_POL_INVERT +CYVAL_UDB_P_U_DP_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_RES_POL__OFFSET +CYFLD_UDB_P_U_SC_RES_POL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SC_RES_POL__SIZE +CYFLD_UDB_P_U_SC_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_RES_POL_NOINV +CYVAL_UDB_P_U_SC_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SC_RES_POL_INVERT +CYVAL_UDB_P_U_SC_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_CFG31 +CYREG_UDB_P0_U0_CFG31 EQU 0x400f305f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_RES__OFFSET +CYFLD_UDB_P_U_ALT_RES__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_ALT_RES__SIZE +CYFLD_UDB_P_U_ALT_RES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_RES_COMPATIBLE +CYVAL_UDB_P_U_ALT_RES_COMPATIBLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_ALT_RES_ALTERNATE +CYVAL_UDB_P_U_ALT_RES_ALTERNATE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_SYNC__OFFSET +CYFLD_UDB_P_U_EXT_SYNC__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_SYNC__SIZE +CYFLD_UDB_P_U_EXT_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_SYNC_DISABLE +CYVAL_UDB_P_U_EXT_SYNC_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_SYNC_ENABLE +CYVAL_UDB_P_U_EXT_SYNC_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_STAT__OFFSET +CYFLD_UDB_P_U_EN_RES_STAT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_STAT__SIZE +CYFLD_UDB_P_U_EN_RES_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_STAT_NEGATED +CYVAL_UDB_P_U_EN_RES_STAT_NEGATED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED +CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_DP__OFFSET +CYFLD_UDB_P_U_EN_RES_DP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EN_RES_DP__SIZE +CYFLD_UDB_P_U_EN_RES_DP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_DP_DISABLE +CYVAL_UDB_P_U_EN_RES_DP_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EN_RES_DP_ENABLE +CYVAL_UDB_P_U_EN_RES_DP_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET +CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_EXT_CK_SEL__SIZE +CYFLD_UDB_P_U_EXT_CK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 +CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET +CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD0_RES_POL__SIZE +CYFLD_UDB_P_U_PLD0_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_RES_POL_NOINV +CYVAL_UDB_P_U_PLD0_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD0_RES_POL_INVERT +CYVAL_UDB_P_U_PLD0_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET +CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_PLD1_RES_POL__SIZE +CYFLD_UDB_P_U_PLD1_RES_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_RES_POL_NOINV +CYVAL_UDB_P_U_PLD1_RES_POL_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_PLD1_RES_POL_INVERT +CYVAL_UDB_P_U_PLD1_RES_POL_INVERT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG0 +CYREG_UDB_P0_U0_DCFG0 EQU 0x400f3060 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SEL__OFFSET +CYFLD_UDB_P_U_CMP_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CMP_SEL__SIZE +CYFLD_UDB_P_U_CMP_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SEL_CFG_A +CYVAL_UDB_P_U_CMP_SEL_CFG_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CMP_SEL_CFG_B +CYVAL_UDB_P_U_CMP_SEL_CFG_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SEL__OFFSET +CYFLD_UDB_P_U_SI_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SI_SEL__SIZE +CYFLD_UDB_P_U_SI_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SEL_CFG_A +CYVAL_UDB_P_U_SI_SEL_CFG_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SI_SEL_CFG_B +CYVAL_UDB_P_U_SI_SEL_CFG_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SEL__OFFSET +CYFLD_UDB_P_U_CI_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CI_SEL__SIZE +CYFLD_UDB_P_U_CI_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SEL_CFG_A +CYVAL_UDB_P_U_CI_SEL_CFG_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CI_SEL_CFG_B +CYVAL_UDB_P_U_CI_SEL_CFG_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CFB_EN__OFFSET +CYFLD_UDB_P_U_CFB_EN__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_CFB_EN__SIZE +CYFLD_UDB_P_U_CFB_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CFB_EN_DISABLE +CYVAL_UDB_P_U_CFB_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_CFB_EN_ENABLE +CYVAL_UDB_P_U_CFB_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A1_WR_SRC__OFFSET +CYFLD_UDB_P_U_A1_WR_SRC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A1_WR_SRC__SIZE +CYFLD_UDB_P_U_A1_WR_SRC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE +CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_ALU +CYVAL_UDB_P_U_A1_WR_SRC_ALU EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_D1 +CYVAL_UDB_P_U_A1_WR_SRC_D1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A1_WR_SRC_F1 +CYVAL_UDB_P_U_A1_WR_SRC_F1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A0_WR_SRC__OFFSET +CYFLD_UDB_P_U_A0_WR_SRC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_A0_WR_SRC__SIZE +CYFLD_UDB_P_U_A0_WR_SRC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE +CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_ALU +CYVAL_UDB_P_U_A0_WR_SRC_ALU EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_D0 +CYVAL_UDB_P_U_A0_WR_SRC_D0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_A0_WR_SRC_F0 +CYVAL_UDB_P_U_A0_WR_SRC_F0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT__OFFSET +CYFLD_UDB_P_U_SHIFT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SHIFT__SIZE +CYFLD_UDB_P_U_SHIFT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_NOSHIFT +CYVAL_UDB_P_U_SHIFT_NOSHIFT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_LEFT +CYVAL_UDB_P_U_SHIFT_LEFT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_RIGHT +CYVAL_UDB_P_U_SHIFT_RIGHT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SHIFT_SWAP +CYVAL_UDB_P_U_SHIFT_SWAP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_B__OFFSET +CYFLD_UDB_P_U_SRC_B__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_B__SIZE +CYFLD_UDB_P_U_SRC_B__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_D0 +CYVAL_UDB_P_U_SRC_B_D0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_D1 +CYVAL_UDB_P_U_SRC_B_D1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_A0 +CYVAL_UDB_P_U_SRC_B_A0 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_B_A1 +CYVAL_UDB_P_U_SRC_B_A1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_A__OFFSET +CYFLD_UDB_P_U_SRC_A__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_SRC_A__SIZE +CYFLD_UDB_P_U_SRC_A__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_A_A0 +CYVAL_UDB_P_U_SRC_A_A0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_SRC_A_A1 +CYVAL_UDB_P_U_SRC_A_A1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FUNC__OFFSET +CYFLD_UDB_P_U_FUNC__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_U_FUNC__SIZE +CYFLD_UDB_P_U_FUNC__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_PASS +CYVAL_UDB_P_U_FUNC_PASS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_INC_A +CYVAL_UDB_P_U_FUNC_INC_A EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_DEC_A +CYVAL_UDB_P_U_FUNC_DEC_A EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_ADD +CYVAL_UDB_P_U_FUNC_ADD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_SUB +CYVAL_UDB_P_U_FUNC_SUB EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_XOR +CYVAL_UDB_P_U_FUNC_XOR EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_AND +CYVAL_UDB_P_U_FUNC_AND EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_P_U_FUNC_OR +CYVAL_UDB_P_U_FUNC_OR EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG1 +CYREG_UDB_P0_U0_DCFG1 EQU 0x400f3062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG2 +CYREG_UDB_P0_U0_DCFG2 EQU 0x400f3064 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG3 +CYREG_UDB_P0_U0_DCFG3 EQU 0x400f3066 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG4 +CYREG_UDB_P0_U0_DCFG4 EQU 0x400f3068 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG5 +CYREG_UDB_P0_U0_DCFG5 EQU 0x400f306a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG6 +CYREG_UDB_P0_U0_DCFG6 EQU 0x400f306c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U0_DCFG7 +CYREG_UDB_P0_U0_DCFG7 EQU 0x400f306e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U1_BASE +CYDEV_UDB_P0_U1_BASE EQU 0x400f3080 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_U1_SIZE +CYDEV_UDB_P0_U1_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT0 +CYREG_UDB_P0_U1_PLD_IT0 EQU 0x400f3080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT1 +CYREG_UDB_P0_U1_PLD_IT1 EQU 0x400f3084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT2 +CYREG_UDB_P0_U1_PLD_IT2 EQU 0x400f3088 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT3 +CYREG_UDB_P0_U1_PLD_IT3 EQU 0x400f308c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT4 +CYREG_UDB_P0_U1_PLD_IT4 EQU 0x400f3090 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT5 +CYREG_UDB_P0_U1_PLD_IT5 EQU 0x400f3094 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT6 +CYREG_UDB_P0_U1_PLD_IT6 EQU 0x400f3098 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT7 +CYREG_UDB_P0_U1_PLD_IT7 EQU 0x400f309c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT8 +CYREG_UDB_P0_U1_PLD_IT8 EQU 0x400f30a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT9 +CYREG_UDB_P0_U1_PLD_IT9 EQU 0x400f30a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT10 +CYREG_UDB_P0_U1_PLD_IT10 EQU 0x400f30a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_IT11 +CYREG_UDB_P0_U1_PLD_IT11 EQU 0x400f30ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT0 +CYREG_UDB_P0_U1_PLD_ORT0 EQU 0x400f30b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT1 +CYREG_UDB_P0_U1_PLD_ORT1 EQU 0x400f30b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT2 +CYREG_UDB_P0_U1_PLD_ORT2 EQU 0x400f30b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_ORT3 +CYREG_UDB_P0_U1_PLD_ORT3 EQU 0x400f30b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST EQU 0x400f30b8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB +CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB EQU 0x400f30ba + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_SET_RESET +CYREG_UDB_P0_U1_PLD_MC_SET_RESET EQU 0x400f30bc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS +CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS EQU 0x400f30be + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG0 +CYREG_UDB_P0_U1_CFG0 EQU 0x400f30c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG1 +CYREG_UDB_P0_U1_CFG1 EQU 0x400f30c1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG2 +CYREG_UDB_P0_U1_CFG2 EQU 0x400f30c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG3 +CYREG_UDB_P0_U1_CFG3 EQU 0x400f30c3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG4 +CYREG_UDB_P0_U1_CFG4 EQU 0x400f30c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG5 +CYREG_UDB_P0_U1_CFG5 EQU 0x400f30c5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG6 +CYREG_UDB_P0_U1_CFG6 EQU 0x400f30c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG7 +CYREG_UDB_P0_U1_CFG7 EQU 0x400f30c7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG8 +CYREG_UDB_P0_U1_CFG8 EQU 0x400f30c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG9 +CYREG_UDB_P0_U1_CFG9 EQU 0x400f30c9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG10 +CYREG_UDB_P0_U1_CFG10 EQU 0x400f30ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG11 +CYREG_UDB_P0_U1_CFG11 EQU 0x400f30cb + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG12 +CYREG_UDB_P0_U1_CFG12 EQU 0x400f30cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG13 +CYREG_UDB_P0_U1_CFG13 EQU 0x400f30cd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG14 +CYREG_UDB_P0_U1_CFG14 EQU 0x400f30ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG15 +CYREG_UDB_P0_U1_CFG15 EQU 0x400f30cf + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG16 +CYREG_UDB_P0_U1_CFG16 EQU 0x400f30d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG17 +CYREG_UDB_P0_U1_CFG17 EQU 0x400f30d1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG18 +CYREG_UDB_P0_U1_CFG18 EQU 0x400f30d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG19 +CYREG_UDB_P0_U1_CFG19 EQU 0x400f30d3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG20 +CYREG_UDB_P0_U1_CFG20 EQU 0x400f30d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG21 +CYREG_UDB_P0_U1_CFG21 EQU 0x400f30d5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG22 +CYREG_UDB_P0_U1_CFG22 EQU 0x400f30d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG23 +CYREG_UDB_P0_U1_CFG23 EQU 0x400f30d7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG24 +CYREG_UDB_P0_U1_CFG24 EQU 0x400f30d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG25 +CYREG_UDB_P0_U1_CFG25 EQU 0x400f30d9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG26 +CYREG_UDB_P0_U1_CFG26 EQU 0x400f30da + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG27 +CYREG_UDB_P0_U1_CFG27 EQU 0x400f30db + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG28 +CYREG_UDB_P0_U1_CFG28 EQU 0x400f30dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG29 +CYREG_UDB_P0_U1_CFG29 EQU 0x400f30dd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG30 +CYREG_UDB_P0_U1_CFG30 EQU 0x400f30de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_CFG31 +CYREG_UDB_P0_U1_CFG31 EQU 0x400f30df + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG0 +CYREG_UDB_P0_U1_DCFG0 EQU 0x400f30e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG1 +CYREG_UDB_P0_U1_DCFG1 EQU 0x400f30e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG2 +CYREG_UDB_P0_U1_DCFG2 EQU 0x400f30e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG3 +CYREG_UDB_P0_U1_DCFG3 EQU 0x400f30e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG4 +CYREG_UDB_P0_U1_DCFG4 EQU 0x400f30e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG5 +CYREG_UDB_P0_U1_DCFG5 EQU 0x400f30ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG6 +CYREG_UDB_P0_U1_DCFG6 EQU 0x400f30ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_U1_DCFG7 +CYREG_UDB_P0_U1_DCFG7 EQU 0x400f30ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_ROUTE_BASE +CYDEV_UDB_P0_ROUTE_BASE EQU 0x400f3100 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P0_ROUTE_SIZE +CYDEV_UDB_P0_ROUTE_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC0 +CYREG_UDB_P0_ROUTE_HC0 EQU 0x400f3100 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET +CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE +CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC1 +CYREG_UDB_P0_ROUTE_HC1 EQU 0x400f3101 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC2 +CYREG_UDB_P0_ROUTE_HC2 EQU 0x400f3102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC3 +CYREG_UDB_P0_ROUTE_HC3 EQU 0x400f3103 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC4 +CYREG_UDB_P0_ROUTE_HC4 EQU 0x400f3104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC5 +CYREG_UDB_P0_ROUTE_HC5 EQU 0x400f3105 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC6 +CYREG_UDB_P0_ROUTE_HC6 EQU 0x400f3106 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC7 +CYREG_UDB_P0_ROUTE_HC7 EQU 0x400f3107 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC8 +CYREG_UDB_P0_ROUTE_HC8 EQU 0x400f3108 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC9 +CYREG_UDB_P0_ROUTE_HC9 EQU 0x400f3109 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC10 +CYREG_UDB_P0_ROUTE_HC10 EQU 0x400f310a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC11 +CYREG_UDB_P0_ROUTE_HC11 EQU 0x400f310b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC12 +CYREG_UDB_P0_ROUTE_HC12 EQU 0x400f310c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC13 +CYREG_UDB_P0_ROUTE_HC13 EQU 0x400f310d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC14 +CYREG_UDB_P0_ROUTE_HC14 EQU 0x400f310e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC15 +CYREG_UDB_P0_ROUTE_HC15 EQU 0x400f310f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC16 +CYREG_UDB_P0_ROUTE_HC16 EQU 0x400f3110 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC17 +CYREG_UDB_P0_ROUTE_HC17 EQU 0x400f3111 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC18 +CYREG_UDB_P0_ROUTE_HC18 EQU 0x400f3112 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC19 +CYREG_UDB_P0_ROUTE_HC19 EQU 0x400f3113 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC20 +CYREG_UDB_P0_ROUTE_HC20 EQU 0x400f3114 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC21 +CYREG_UDB_P0_ROUTE_HC21 EQU 0x400f3115 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC22 +CYREG_UDB_P0_ROUTE_HC22 EQU 0x400f3116 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC23 +CYREG_UDB_P0_ROUTE_HC23 EQU 0x400f3117 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC24 +CYREG_UDB_P0_ROUTE_HC24 EQU 0x400f3118 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC25 +CYREG_UDB_P0_ROUTE_HC25 EQU 0x400f3119 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC26 +CYREG_UDB_P0_ROUTE_HC26 EQU 0x400f311a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC27 +CYREG_UDB_P0_ROUTE_HC27 EQU 0x400f311b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC28 +CYREG_UDB_P0_ROUTE_HC28 EQU 0x400f311c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC29 +CYREG_UDB_P0_ROUTE_HC29 EQU 0x400f311d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC30 +CYREG_UDB_P0_ROUTE_HC30 EQU 0x400f311e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC31 +CYREG_UDB_P0_ROUTE_HC31 EQU 0x400f311f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC32 +CYREG_UDB_P0_ROUTE_HC32 EQU 0x400f3120 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC33 +CYREG_UDB_P0_ROUTE_HC33 EQU 0x400f3121 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC34 +CYREG_UDB_P0_ROUTE_HC34 EQU 0x400f3122 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC35 +CYREG_UDB_P0_ROUTE_HC35 EQU 0x400f3123 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC36 +CYREG_UDB_P0_ROUTE_HC36 EQU 0x400f3124 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC37 +CYREG_UDB_P0_ROUTE_HC37 EQU 0x400f3125 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC38 +CYREG_UDB_P0_ROUTE_HC38 EQU 0x400f3126 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC39 +CYREG_UDB_P0_ROUTE_HC39 EQU 0x400f3127 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC40 +CYREG_UDB_P0_ROUTE_HC40 EQU 0x400f3128 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC41 +CYREG_UDB_P0_ROUTE_HC41 EQU 0x400f3129 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC42 +CYREG_UDB_P0_ROUTE_HC42 EQU 0x400f312a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC43 +CYREG_UDB_P0_ROUTE_HC43 EQU 0x400f312b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC44 +CYREG_UDB_P0_ROUTE_HC44 EQU 0x400f312c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC45 +CYREG_UDB_P0_ROUTE_HC45 EQU 0x400f312d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC46 +CYREG_UDB_P0_ROUTE_HC46 EQU 0x400f312e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC47 +CYREG_UDB_P0_ROUTE_HC47 EQU 0x400f312f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC48 +CYREG_UDB_P0_ROUTE_HC48 EQU 0x400f3130 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC49 +CYREG_UDB_P0_ROUTE_HC49 EQU 0x400f3131 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC50 +CYREG_UDB_P0_ROUTE_HC50 EQU 0x400f3132 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC51 +CYREG_UDB_P0_ROUTE_HC51 EQU 0x400f3133 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC52 +CYREG_UDB_P0_ROUTE_HC52 EQU 0x400f3134 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC53 +CYREG_UDB_P0_ROUTE_HC53 EQU 0x400f3135 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC54 +CYREG_UDB_P0_ROUTE_HC54 EQU 0x400f3136 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC55 +CYREG_UDB_P0_ROUTE_HC55 EQU 0x400f3137 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC56 +CYREG_UDB_P0_ROUTE_HC56 EQU 0x400f3138 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC57 +CYREG_UDB_P0_ROUTE_HC57 EQU 0x400f3139 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC58 +CYREG_UDB_P0_ROUTE_HC58 EQU 0x400f313a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC59 +CYREG_UDB_P0_ROUTE_HC59 EQU 0x400f313b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC60 +CYREG_UDB_P0_ROUTE_HC60 EQU 0x400f313c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC61 +CYREG_UDB_P0_ROUTE_HC61 EQU 0x400f313d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC62 +CYREG_UDB_P0_ROUTE_HC62 EQU 0x400f313e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC63 +CYREG_UDB_P0_ROUTE_HC63 EQU 0x400f313f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC64 +CYREG_UDB_P0_ROUTE_HC64 EQU 0x400f3140 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC65 +CYREG_UDB_P0_ROUTE_HC65 EQU 0x400f3141 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC66 +CYREG_UDB_P0_ROUTE_HC66 EQU 0x400f3142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC67 +CYREG_UDB_P0_ROUTE_HC67 EQU 0x400f3143 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC68 +CYREG_UDB_P0_ROUTE_HC68 EQU 0x400f3144 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC69 +CYREG_UDB_P0_ROUTE_HC69 EQU 0x400f3145 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC70 +CYREG_UDB_P0_ROUTE_HC70 EQU 0x400f3146 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC71 +CYREG_UDB_P0_ROUTE_HC71 EQU 0x400f3147 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC72 +CYREG_UDB_P0_ROUTE_HC72 EQU 0x400f3148 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC73 +CYREG_UDB_P0_ROUTE_HC73 EQU 0x400f3149 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC74 +CYREG_UDB_P0_ROUTE_HC74 EQU 0x400f314a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC75 +CYREG_UDB_P0_ROUTE_HC75 EQU 0x400f314b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC76 +CYREG_UDB_P0_ROUTE_HC76 EQU 0x400f314c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC77 +CYREG_UDB_P0_ROUTE_HC77 EQU 0x400f314d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC78 +CYREG_UDB_P0_ROUTE_HC78 EQU 0x400f314e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC79 +CYREG_UDB_P0_ROUTE_HC79 EQU 0x400f314f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC80 +CYREG_UDB_P0_ROUTE_HC80 EQU 0x400f3150 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC81 +CYREG_UDB_P0_ROUTE_HC81 EQU 0x400f3151 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC82 +CYREG_UDB_P0_ROUTE_HC82 EQU 0x400f3152 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC83 +CYREG_UDB_P0_ROUTE_HC83 EQU 0x400f3153 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC84 +CYREG_UDB_P0_ROUTE_HC84 EQU 0x400f3154 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC85 +CYREG_UDB_P0_ROUTE_HC85 EQU 0x400f3155 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC86 +CYREG_UDB_P0_ROUTE_HC86 EQU 0x400f3156 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC87 +CYREG_UDB_P0_ROUTE_HC87 EQU 0x400f3157 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC88 +CYREG_UDB_P0_ROUTE_HC88 EQU 0x400f3158 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC89 +CYREG_UDB_P0_ROUTE_HC89 EQU 0x400f3159 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC90 +CYREG_UDB_P0_ROUTE_HC90 EQU 0x400f315a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC91 +CYREG_UDB_P0_ROUTE_HC91 EQU 0x400f315b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC92 +CYREG_UDB_P0_ROUTE_HC92 EQU 0x400f315c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC93 +CYREG_UDB_P0_ROUTE_HC93 EQU 0x400f315d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC94 +CYREG_UDB_P0_ROUTE_HC94 EQU 0x400f315e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC95 +CYREG_UDB_P0_ROUTE_HC95 EQU 0x400f315f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC96 +CYREG_UDB_P0_ROUTE_HC96 EQU 0x400f3160 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC97 +CYREG_UDB_P0_ROUTE_HC97 EQU 0x400f3161 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC98 +CYREG_UDB_P0_ROUTE_HC98 EQU 0x400f3162 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC99 +CYREG_UDB_P0_ROUTE_HC99 EQU 0x400f3163 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC100 +CYREG_UDB_P0_ROUTE_HC100 EQU 0x400f3164 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC101 +CYREG_UDB_P0_ROUTE_HC101 EQU 0x400f3165 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC102 +CYREG_UDB_P0_ROUTE_HC102 EQU 0x400f3166 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC103 +CYREG_UDB_P0_ROUTE_HC103 EQU 0x400f3167 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC104 +CYREG_UDB_P0_ROUTE_HC104 EQU 0x400f3168 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC105 +CYREG_UDB_P0_ROUTE_HC105 EQU 0x400f3169 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC106 +CYREG_UDB_P0_ROUTE_HC106 EQU 0x400f316a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC107 +CYREG_UDB_P0_ROUTE_HC107 EQU 0x400f316b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC108 +CYREG_UDB_P0_ROUTE_HC108 EQU 0x400f316c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC109 +CYREG_UDB_P0_ROUTE_HC109 EQU 0x400f316d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC110 +CYREG_UDB_P0_ROUTE_HC110 EQU 0x400f316e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC111 +CYREG_UDB_P0_ROUTE_HC111 EQU 0x400f316f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC112 +CYREG_UDB_P0_ROUTE_HC112 EQU 0x400f3170 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC113 +CYREG_UDB_P0_ROUTE_HC113 EQU 0x400f3171 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC114 +CYREG_UDB_P0_ROUTE_HC114 EQU 0x400f3172 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC115 +CYREG_UDB_P0_ROUTE_HC115 EQU 0x400f3173 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC116 +CYREG_UDB_P0_ROUTE_HC116 EQU 0x400f3174 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC117 +CYREG_UDB_P0_ROUTE_HC117 EQU 0x400f3175 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC118 +CYREG_UDB_P0_ROUTE_HC118 EQU 0x400f3176 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC119 +CYREG_UDB_P0_ROUTE_HC119 EQU 0x400f3177 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC120 +CYREG_UDB_P0_ROUTE_HC120 EQU 0x400f3178 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC121 +CYREG_UDB_P0_ROUTE_HC121 EQU 0x400f3179 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC122 +CYREG_UDB_P0_ROUTE_HC122 EQU 0x400f317a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC123 +CYREG_UDB_P0_ROUTE_HC123 EQU 0x400f317b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC124 +CYREG_UDB_P0_ROUTE_HC124 EQU 0x400f317c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC125 +CYREG_UDB_P0_ROUTE_HC125 EQU 0x400f317d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC126 +CYREG_UDB_P0_ROUTE_HC126 EQU 0x400f317e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HC127 +CYREG_UDB_P0_ROUTE_HC127 EQU 0x400f317f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L0 +CYREG_UDB_P0_ROUTE_HV_L0 EQU 0x400f3180 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET +CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE +CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L1 +CYREG_UDB_P0_ROUTE_HV_L1 EQU 0x400f3181 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L2 +CYREG_UDB_P0_ROUTE_HV_L2 EQU 0x400f3182 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L3 +CYREG_UDB_P0_ROUTE_HV_L3 EQU 0x400f3183 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L4 +CYREG_UDB_P0_ROUTE_HV_L4 EQU 0x400f3184 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L5 +CYREG_UDB_P0_ROUTE_HV_L5 EQU 0x400f3185 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L6 +CYREG_UDB_P0_ROUTE_HV_L6 EQU 0x400f3186 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L7 +CYREG_UDB_P0_ROUTE_HV_L7 EQU 0x400f3187 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L8 +CYREG_UDB_P0_ROUTE_HV_L8 EQU 0x400f3188 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L9 +CYREG_UDB_P0_ROUTE_HV_L9 EQU 0x400f3189 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L10 +CYREG_UDB_P0_ROUTE_HV_L10 EQU 0x400f318a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L11 +CYREG_UDB_P0_ROUTE_HV_L11 EQU 0x400f318b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L12 +CYREG_UDB_P0_ROUTE_HV_L12 EQU 0x400f318c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L13 +CYREG_UDB_P0_ROUTE_HV_L13 EQU 0x400f318d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L14 +CYREG_UDB_P0_ROUTE_HV_L14 EQU 0x400f318e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_L15 +CYREG_UDB_P0_ROUTE_HV_L15 EQU 0x400f318f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS0 +CYREG_UDB_P0_ROUTE_HS0 EQU 0x400f3190 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET +CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE +CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS1 +CYREG_UDB_P0_ROUTE_HS1 EQU 0x400f3191 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS2 +CYREG_UDB_P0_ROUTE_HS2 EQU 0x400f3192 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS3 +CYREG_UDB_P0_ROUTE_HS3 EQU 0x400f3193 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS4 +CYREG_UDB_P0_ROUTE_HS4 EQU 0x400f3194 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS5 +CYREG_UDB_P0_ROUTE_HS5 EQU 0x400f3195 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS6 +CYREG_UDB_P0_ROUTE_HS6 EQU 0x400f3196 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS7 +CYREG_UDB_P0_ROUTE_HS7 EQU 0x400f3197 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS8 +CYREG_UDB_P0_ROUTE_HS8 EQU 0x400f3198 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS9 +CYREG_UDB_P0_ROUTE_HS9 EQU 0x400f3199 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS10 +CYREG_UDB_P0_ROUTE_HS10 EQU 0x400f319a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS11 +CYREG_UDB_P0_ROUTE_HS11 EQU 0x400f319b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS12 +CYREG_UDB_P0_ROUTE_HS12 EQU 0x400f319c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS13 +CYREG_UDB_P0_ROUTE_HS13 EQU 0x400f319d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS14 +CYREG_UDB_P0_ROUTE_HS14 EQU 0x400f319e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS15 +CYREG_UDB_P0_ROUTE_HS15 EQU 0x400f319f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS16 +CYREG_UDB_P0_ROUTE_HS16 EQU 0x400f31a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS17 +CYREG_UDB_P0_ROUTE_HS17 EQU 0x400f31a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS18 +CYREG_UDB_P0_ROUTE_HS18 EQU 0x400f31a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS19 +CYREG_UDB_P0_ROUTE_HS19 EQU 0x400f31a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS20 +CYREG_UDB_P0_ROUTE_HS20 EQU 0x400f31a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS21 +CYREG_UDB_P0_ROUTE_HS21 EQU 0x400f31a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS22 +CYREG_UDB_P0_ROUTE_HS22 EQU 0x400f31a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HS23 +CYREG_UDB_P0_ROUTE_HS23 EQU 0x400f31a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R0 +CYREG_UDB_P0_ROUTE_HV_R0 EQU 0x400f31a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R1 +CYREG_UDB_P0_ROUTE_HV_R1 EQU 0x400f31a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R2 +CYREG_UDB_P0_ROUTE_HV_R2 EQU 0x400f31aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R3 +CYREG_UDB_P0_ROUTE_HV_R3 EQU 0x400f31ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R4 +CYREG_UDB_P0_ROUTE_HV_R4 EQU 0x400f31ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R5 +CYREG_UDB_P0_ROUTE_HV_R5 EQU 0x400f31ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R6 +CYREG_UDB_P0_ROUTE_HV_R6 EQU 0x400f31ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R7 +CYREG_UDB_P0_ROUTE_HV_R7 EQU 0x400f31af + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R8 +CYREG_UDB_P0_ROUTE_HV_R8 EQU 0x400f31b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R9 +CYREG_UDB_P0_ROUTE_HV_R9 EQU 0x400f31b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R10 +CYREG_UDB_P0_ROUTE_HV_R10 EQU 0x400f31b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R11 +CYREG_UDB_P0_ROUTE_HV_R11 EQU 0x400f31b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R12 +CYREG_UDB_P0_ROUTE_HV_R12 EQU 0x400f31b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R13 +CYREG_UDB_P0_ROUTE_HV_R13 EQU 0x400f31b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R14 +CYREG_UDB_P0_ROUTE_HV_R14 EQU 0x400f31b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_HV_R15 +CYREG_UDB_P0_ROUTE_HV_R15 EQU 0x400f31b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD0IN0 +CYREG_UDB_P0_ROUTE_PLD0IN0 EQU 0x400f31c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET +CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP__SIZE +CYFLD_UDB_P_ROUTE_PI_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET +CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT__SIZE +CYFLD_UDB_P_ROUTE_PI_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD0IN1 +CYREG_UDB_P0_ROUTE_PLD0IN1 EQU 0x400f31c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD0IN2 +CYREG_UDB_P0_ROUTE_PLD0IN2 EQU 0x400f31c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD1IN0 +CYREG_UDB_P0_ROUTE_PLD1IN0 EQU 0x400f31ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD1IN1 +CYREG_UDB_P0_ROUTE_PLD1IN1 EQU 0x400f31cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_PLD1IN2 +CYREG_UDB_P0_ROUTE_PLD1IN2 EQU 0x400f31ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_DPIN0 +CYREG_UDB_P0_ROUTE_DPIN0 EQU 0x400f31d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_DPIN1 +CYREG_UDB_P0_ROUTE_DPIN1 EQU 0x400f31d2 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET +CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE +CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET +CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE +CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_SCIN +CYREG_UDB_P0_ROUTE_SCIN EQU 0x400f31d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_SCIOIN +CYREG_UDB_P0_ROUTE_SCIOIN EQU 0x400f31d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_RCIN +CYREG_UDB_P0_ROUTE_RCIN EQU 0x400f31de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS0 +CYREG_UDB_P0_ROUTE_VS0 EQU 0x400f31e0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET +CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_TOP__SIZE +CYFLD_UDB_P_ROUTE_VS_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET +CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_P_ROUTE_VS_BOT__SIZE +CYFLD_UDB_P_ROUTE_VS_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS1 +CYREG_UDB_P0_ROUTE_VS1 EQU 0x400f31e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS2 +CYREG_UDB_P0_ROUTE_VS2 EQU 0x400f31e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS3 +CYREG_UDB_P0_ROUTE_VS3 EQU 0x400f31e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS4 +CYREG_UDB_P0_ROUTE_VS4 EQU 0x400f31e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS5 +CYREG_UDB_P0_ROUTE_VS5 EQU 0x400f31ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS6 +CYREG_UDB_P0_ROUTE_VS6 EQU 0x400f31ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P0_ROUTE_VS7 +CYREG_UDB_P0_ROUTE_VS7 EQU 0x400f31ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_BASE +CYDEV_UDB_P1_BASE EQU 0x400f3200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_SIZE +CYDEV_UDB_P1_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U0_BASE +CYDEV_UDB_P1_U0_BASE EQU 0x400f3200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U0_SIZE +CYDEV_UDB_P1_U0_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT0 +CYREG_UDB_P1_U0_PLD_IT0 EQU 0x400f3200 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT1 +CYREG_UDB_P1_U0_PLD_IT1 EQU 0x400f3204 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT2 +CYREG_UDB_P1_U0_PLD_IT2 EQU 0x400f3208 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT3 +CYREG_UDB_P1_U0_PLD_IT3 EQU 0x400f320c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT4 +CYREG_UDB_P1_U0_PLD_IT4 EQU 0x400f3210 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT5 +CYREG_UDB_P1_U0_PLD_IT5 EQU 0x400f3214 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT6 +CYREG_UDB_P1_U0_PLD_IT6 EQU 0x400f3218 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT7 +CYREG_UDB_P1_U0_PLD_IT7 EQU 0x400f321c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT8 +CYREG_UDB_P1_U0_PLD_IT8 EQU 0x400f3220 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT9 +CYREG_UDB_P1_U0_PLD_IT9 EQU 0x400f3224 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT10 +CYREG_UDB_P1_U0_PLD_IT10 EQU 0x400f3228 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_IT11 +CYREG_UDB_P1_U0_PLD_IT11 EQU 0x400f322c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT0 +CYREG_UDB_P1_U0_PLD_ORT0 EQU 0x400f3230 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT1 +CYREG_UDB_P1_U0_PLD_ORT1 EQU 0x400f3232 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT2 +CYREG_UDB_P1_U0_PLD_ORT2 EQU 0x400f3234 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_ORT3 +CYREG_UDB_P1_U0_PLD_ORT3 EQU 0x400f3236 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST EQU 0x400f3238 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB +CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB EQU 0x400f323a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_SET_RESET +CYREG_UDB_P1_U0_PLD_MC_SET_RESET EQU 0x400f323c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS +CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS EQU 0x400f323e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG0 +CYREG_UDB_P1_U0_CFG0 EQU 0x400f3240 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG1 +CYREG_UDB_P1_U0_CFG1 EQU 0x400f3241 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG2 +CYREG_UDB_P1_U0_CFG2 EQU 0x400f3242 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG3 +CYREG_UDB_P1_U0_CFG3 EQU 0x400f3243 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG4 +CYREG_UDB_P1_U0_CFG4 EQU 0x400f3244 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG5 +CYREG_UDB_P1_U0_CFG5 EQU 0x400f3245 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG6 +CYREG_UDB_P1_U0_CFG6 EQU 0x400f3246 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG7 +CYREG_UDB_P1_U0_CFG7 EQU 0x400f3247 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG8 +CYREG_UDB_P1_U0_CFG8 EQU 0x400f3248 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG9 +CYREG_UDB_P1_U0_CFG9 EQU 0x400f3249 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG10 +CYREG_UDB_P1_U0_CFG10 EQU 0x400f324a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG11 +CYREG_UDB_P1_U0_CFG11 EQU 0x400f324b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG12 +CYREG_UDB_P1_U0_CFG12 EQU 0x400f324c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG13 +CYREG_UDB_P1_U0_CFG13 EQU 0x400f324d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG14 +CYREG_UDB_P1_U0_CFG14 EQU 0x400f324e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG15 +CYREG_UDB_P1_U0_CFG15 EQU 0x400f324f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG16 +CYREG_UDB_P1_U0_CFG16 EQU 0x400f3250 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG17 +CYREG_UDB_P1_U0_CFG17 EQU 0x400f3251 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG18 +CYREG_UDB_P1_U0_CFG18 EQU 0x400f3252 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG19 +CYREG_UDB_P1_U0_CFG19 EQU 0x400f3253 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG20 +CYREG_UDB_P1_U0_CFG20 EQU 0x400f3254 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG21 +CYREG_UDB_P1_U0_CFG21 EQU 0x400f3255 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG22 +CYREG_UDB_P1_U0_CFG22 EQU 0x400f3256 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG23 +CYREG_UDB_P1_U0_CFG23 EQU 0x400f3257 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG24 +CYREG_UDB_P1_U0_CFG24 EQU 0x400f3258 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG25 +CYREG_UDB_P1_U0_CFG25 EQU 0x400f3259 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG26 +CYREG_UDB_P1_U0_CFG26 EQU 0x400f325a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG27 +CYREG_UDB_P1_U0_CFG27 EQU 0x400f325b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG28 +CYREG_UDB_P1_U0_CFG28 EQU 0x400f325c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG29 +CYREG_UDB_P1_U0_CFG29 EQU 0x400f325d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG30 +CYREG_UDB_P1_U0_CFG30 EQU 0x400f325e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_CFG31 +CYREG_UDB_P1_U0_CFG31 EQU 0x400f325f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG0 +CYREG_UDB_P1_U0_DCFG0 EQU 0x400f3260 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG1 +CYREG_UDB_P1_U0_DCFG1 EQU 0x400f3262 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG2 +CYREG_UDB_P1_U0_DCFG2 EQU 0x400f3264 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG3 +CYREG_UDB_P1_U0_DCFG3 EQU 0x400f3266 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG4 +CYREG_UDB_P1_U0_DCFG4 EQU 0x400f3268 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG5 +CYREG_UDB_P1_U0_DCFG5 EQU 0x400f326a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG6 +CYREG_UDB_P1_U0_DCFG6 EQU 0x400f326c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U0_DCFG7 +CYREG_UDB_P1_U0_DCFG7 EQU 0x400f326e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U1_BASE +CYDEV_UDB_P1_U1_BASE EQU 0x400f3280 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_U1_SIZE +CYDEV_UDB_P1_U1_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT0 +CYREG_UDB_P1_U1_PLD_IT0 EQU 0x400f3280 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT1 +CYREG_UDB_P1_U1_PLD_IT1 EQU 0x400f3284 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT2 +CYREG_UDB_P1_U1_PLD_IT2 EQU 0x400f3288 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT3 +CYREG_UDB_P1_U1_PLD_IT3 EQU 0x400f328c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT4 +CYREG_UDB_P1_U1_PLD_IT4 EQU 0x400f3290 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT5 +CYREG_UDB_P1_U1_PLD_IT5 EQU 0x400f3294 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT6 +CYREG_UDB_P1_U1_PLD_IT6 EQU 0x400f3298 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT7 +CYREG_UDB_P1_U1_PLD_IT7 EQU 0x400f329c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT8 +CYREG_UDB_P1_U1_PLD_IT8 EQU 0x400f32a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT9 +CYREG_UDB_P1_U1_PLD_IT9 EQU 0x400f32a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT10 +CYREG_UDB_P1_U1_PLD_IT10 EQU 0x400f32a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_IT11 +CYREG_UDB_P1_U1_PLD_IT11 EQU 0x400f32ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT0 +CYREG_UDB_P1_U1_PLD_ORT0 EQU 0x400f32b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT1 +CYREG_UDB_P1_U1_PLD_ORT1 EQU 0x400f32b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT2 +CYREG_UDB_P1_U1_PLD_ORT2 EQU 0x400f32b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_ORT3 +CYREG_UDB_P1_U1_PLD_ORT3 EQU 0x400f32b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST +CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST EQU 0x400f32b8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB +CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB EQU 0x400f32ba + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_SET_RESET +CYREG_UDB_P1_U1_PLD_MC_SET_RESET EQU 0x400f32bc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS +CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS EQU 0x400f32be + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG0 +CYREG_UDB_P1_U1_CFG0 EQU 0x400f32c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG1 +CYREG_UDB_P1_U1_CFG1 EQU 0x400f32c1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG2 +CYREG_UDB_P1_U1_CFG2 EQU 0x400f32c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG3 +CYREG_UDB_P1_U1_CFG3 EQU 0x400f32c3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG4 +CYREG_UDB_P1_U1_CFG4 EQU 0x400f32c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG5 +CYREG_UDB_P1_U1_CFG5 EQU 0x400f32c5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG6 +CYREG_UDB_P1_U1_CFG6 EQU 0x400f32c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG7 +CYREG_UDB_P1_U1_CFG7 EQU 0x400f32c7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG8 +CYREG_UDB_P1_U1_CFG8 EQU 0x400f32c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG9 +CYREG_UDB_P1_U1_CFG9 EQU 0x400f32c9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG10 +CYREG_UDB_P1_U1_CFG10 EQU 0x400f32ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG11 +CYREG_UDB_P1_U1_CFG11 EQU 0x400f32cb + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG12 +CYREG_UDB_P1_U1_CFG12 EQU 0x400f32cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG13 +CYREG_UDB_P1_U1_CFG13 EQU 0x400f32cd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG14 +CYREG_UDB_P1_U1_CFG14 EQU 0x400f32ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG15 +CYREG_UDB_P1_U1_CFG15 EQU 0x400f32cf + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG16 +CYREG_UDB_P1_U1_CFG16 EQU 0x400f32d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG17 +CYREG_UDB_P1_U1_CFG17 EQU 0x400f32d1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG18 +CYREG_UDB_P1_U1_CFG18 EQU 0x400f32d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG19 +CYREG_UDB_P1_U1_CFG19 EQU 0x400f32d3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG20 +CYREG_UDB_P1_U1_CFG20 EQU 0x400f32d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG21 +CYREG_UDB_P1_U1_CFG21 EQU 0x400f32d5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG22 +CYREG_UDB_P1_U1_CFG22 EQU 0x400f32d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG23 +CYREG_UDB_P1_U1_CFG23 EQU 0x400f32d7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG24 +CYREG_UDB_P1_U1_CFG24 EQU 0x400f32d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG25 +CYREG_UDB_P1_U1_CFG25 EQU 0x400f32d9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG26 +CYREG_UDB_P1_U1_CFG26 EQU 0x400f32da + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG27 +CYREG_UDB_P1_U1_CFG27 EQU 0x400f32db + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG28 +CYREG_UDB_P1_U1_CFG28 EQU 0x400f32dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG29 +CYREG_UDB_P1_U1_CFG29 EQU 0x400f32dd + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG30 +CYREG_UDB_P1_U1_CFG30 EQU 0x400f32de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_CFG31 +CYREG_UDB_P1_U1_CFG31 EQU 0x400f32df + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG0 +CYREG_UDB_P1_U1_DCFG0 EQU 0x400f32e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG1 +CYREG_UDB_P1_U1_DCFG1 EQU 0x400f32e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG2 +CYREG_UDB_P1_U1_DCFG2 EQU 0x400f32e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG3 +CYREG_UDB_P1_U1_DCFG3 EQU 0x400f32e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG4 +CYREG_UDB_P1_U1_DCFG4 EQU 0x400f32e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG5 +CYREG_UDB_P1_U1_DCFG5 EQU 0x400f32ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG6 +CYREG_UDB_P1_U1_DCFG6 EQU 0x400f32ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_U1_DCFG7 +CYREG_UDB_P1_U1_DCFG7 EQU 0x400f32ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_ROUTE_BASE +CYDEV_UDB_P1_ROUTE_BASE EQU 0x400f3300 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_P1_ROUTE_SIZE +CYDEV_UDB_P1_ROUTE_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC0 +CYREG_UDB_P1_ROUTE_HC0 EQU 0x400f3300 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC1 +CYREG_UDB_P1_ROUTE_HC1 EQU 0x400f3301 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC2 +CYREG_UDB_P1_ROUTE_HC2 EQU 0x400f3302 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC3 +CYREG_UDB_P1_ROUTE_HC3 EQU 0x400f3303 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC4 +CYREG_UDB_P1_ROUTE_HC4 EQU 0x400f3304 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC5 +CYREG_UDB_P1_ROUTE_HC5 EQU 0x400f3305 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC6 +CYREG_UDB_P1_ROUTE_HC6 EQU 0x400f3306 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC7 +CYREG_UDB_P1_ROUTE_HC7 EQU 0x400f3307 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC8 +CYREG_UDB_P1_ROUTE_HC8 EQU 0x400f3308 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC9 +CYREG_UDB_P1_ROUTE_HC9 EQU 0x400f3309 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC10 +CYREG_UDB_P1_ROUTE_HC10 EQU 0x400f330a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC11 +CYREG_UDB_P1_ROUTE_HC11 EQU 0x400f330b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC12 +CYREG_UDB_P1_ROUTE_HC12 EQU 0x400f330c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC13 +CYREG_UDB_P1_ROUTE_HC13 EQU 0x400f330d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC14 +CYREG_UDB_P1_ROUTE_HC14 EQU 0x400f330e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC15 +CYREG_UDB_P1_ROUTE_HC15 EQU 0x400f330f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC16 +CYREG_UDB_P1_ROUTE_HC16 EQU 0x400f3310 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC17 +CYREG_UDB_P1_ROUTE_HC17 EQU 0x400f3311 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC18 +CYREG_UDB_P1_ROUTE_HC18 EQU 0x400f3312 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC19 +CYREG_UDB_P1_ROUTE_HC19 EQU 0x400f3313 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC20 +CYREG_UDB_P1_ROUTE_HC20 EQU 0x400f3314 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC21 +CYREG_UDB_P1_ROUTE_HC21 EQU 0x400f3315 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC22 +CYREG_UDB_P1_ROUTE_HC22 EQU 0x400f3316 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC23 +CYREG_UDB_P1_ROUTE_HC23 EQU 0x400f3317 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC24 +CYREG_UDB_P1_ROUTE_HC24 EQU 0x400f3318 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC25 +CYREG_UDB_P1_ROUTE_HC25 EQU 0x400f3319 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC26 +CYREG_UDB_P1_ROUTE_HC26 EQU 0x400f331a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC27 +CYREG_UDB_P1_ROUTE_HC27 EQU 0x400f331b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC28 +CYREG_UDB_P1_ROUTE_HC28 EQU 0x400f331c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC29 +CYREG_UDB_P1_ROUTE_HC29 EQU 0x400f331d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC30 +CYREG_UDB_P1_ROUTE_HC30 EQU 0x400f331e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC31 +CYREG_UDB_P1_ROUTE_HC31 EQU 0x400f331f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC32 +CYREG_UDB_P1_ROUTE_HC32 EQU 0x400f3320 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC33 +CYREG_UDB_P1_ROUTE_HC33 EQU 0x400f3321 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC34 +CYREG_UDB_P1_ROUTE_HC34 EQU 0x400f3322 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC35 +CYREG_UDB_P1_ROUTE_HC35 EQU 0x400f3323 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC36 +CYREG_UDB_P1_ROUTE_HC36 EQU 0x400f3324 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC37 +CYREG_UDB_P1_ROUTE_HC37 EQU 0x400f3325 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC38 +CYREG_UDB_P1_ROUTE_HC38 EQU 0x400f3326 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC39 +CYREG_UDB_P1_ROUTE_HC39 EQU 0x400f3327 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC40 +CYREG_UDB_P1_ROUTE_HC40 EQU 0x400f3328 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC41 +CYREG_UDB_P1_ROUTE_HC41 EQU 0x400f3329 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC42 +CYREG_UDB_P1_ROUTE_HC42 EQU 0x400f332a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC43 +CYREG_UDB_P1_ROUTE_HC43 EQU 0x400f332b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC44 +CYREG_UDB_P1_ROUTE_HC44 EQU 0x400f332c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC45 +CYREG_UDB_P1_ROUTE_HC45 EQU 0x400f332d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC46 +CYREG_UDB_P1_ROUTE_HC46 EQU 0x400f332e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC47 +CYREG_UDB_P1_ROUTE_HC47 EQU 0x400f332f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC48 +CYREG_UDB_P1_ROUTE_HC48 EQU 0x400f3330 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC49 +CYREG_UDB_P1_ROUTE_HC49 EQU 0x400f3331 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC50 +CYREG_UDB_P1_ROUTE_HC50 EQU 0x400f3332 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC51 +CYREG_UDB_P1_ROUTE_HC51 EQU 0x400f3333 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC52 +CYREG_UDB_P1_ROUTE_HC52 EQU 0x400f3334 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC53 +CYREG_UDB_P1_ROUTE_HC53 EQU 0x400f3335 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC54 +CYREG_UDB_P1_ROUTE_HC54 EQU 0x400f3336 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC55 +CYREG_UDB_P1_ROUTE_HC55 EQU 0x400f3337 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC56 +CYREG_UDB_P1_ROUTE_HC56 EQU 0x400f3338 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC57 +CYREG_UDB_P1_ROUTE_HC57 EQU 0x400f3339 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC58 +CYREG_UDB_P1_ROUTE_HC58 EQU 0x400f333a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC59 +CYREG_UDB_P1_ROUTE_HC59 EQU 0x400f333b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC60 +CYREG_UDB_P1_ROUTE_HC60 EQU 0x400f333c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC61 +CYREG_UDB_P1_ROUTE_HC61 EQU 0x400f333d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC62 +CYREG_UDB_P1_ROUTE_HC62 EQU 0x400f333e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC63 +CYREG_UDB_P1_ROUTE_HC63 EQU 0x400f333f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC64 +CYREG_UDB_P1_ROUTE_HC64 EQU 0x400f3340 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC65 +CYREG_UDB_P1_ROUTE_HC65 EQU 0x400f3341 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC66 +CYREG_UDB_P1_ROUTE_HC66 EQU 0x400f3342 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC67 +CYREG_UDB_P1_ROUTE_HC67 EQU 0x400f3343 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC68 +CYREG_UDB_P1_ROUTE_HC68 EQU 0x400f3344 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC69 +CYREG_UDB_P1_ROUTE_HC69 EQU 0x400f3345 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC70 +CYREG_UDB_P1_ROUTE_HC70 EQU 0x400f3346 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC71 +CYREG_UDB_P1_ROUTE_HC71 EQU 0x400f3347 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC72 +CYREG_UDB_P1_ROUTE_HC72 EQU 0x400f3348 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC73 +CYREG_UDB_P1_ROUTE_HC73 EQU 0x400f3349 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC74 +CYREG_UDB_P1_ROUTE_HC74 EQU 0x400f334a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC75 +CYREG_UDB_P1_ROUTE_HC75 EQU 0x400f334b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC76 +CYREG_UDB_P1_ROUTE_HC76 EQU 0x400f334c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC77 +CYREG_UDB_P1_ROUTE_HC77 EQU 0x400f334d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC78 +CYREG_UDB_P1_ROUTE_HC78 EQU 0x400f334e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC79 +CYREG_UDB_P1_ROUTE_HC79 EQU 0x400f334f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC80 +CYREG_UDB_P1_ROUTE_HC80 EQU 0x400f3350 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC81 +CYREG_UDB_P1_ROUTE_HC81 EQU 0x400f3351 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC82 +CYREG_UDB_P1_ROUTE_HC82 EQU 0x400f3352 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC83 +CYREG_UDB_P1_ROUTE_HC83 EQU 0x400f3353 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC84 +CYREG_UDB_P1_ROUTE_HC84 EQU 0x400f3354 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC85 +CYREG_UDB_P1_ROUTE_HC85 EQU 0x400f3355 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC86 +CYREG_UDB_P1_ROUTE_HC86 EQU 0x400f3356 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC87 +CYREG_UDB_P1_ROUTE_HC87 EQU 0x400f3357 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC88 +CYREG_UDB_P1_ROUTE_HC88 EQU 0x400f3358 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC89 +CYREG_UDB_P1_ROUTE_HC89 EQU 0x400f3359 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC90 +CYREG_UDB_P1_ROUTE_HC90 EQU 0x400f335a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC91 +CYREG_UDB_P1_ROUTE_HC91 EQU 0x400f335b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC92 +CYREG_UDB_P1_ROUTE_HC92 EQU 0x400f335c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC93 +CYREG_UDB_P1_ROUTE_HC93 EQU 0x400f335d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC94 +CYREG_UDB_P1_ROUTE_HC94 EQU 0x400f335e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC95 +CYREG_UDB_P1_ROUTE_HC95 EQU 0x400f335f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC96 +CYREG_UDB_P1_ROUTE_HC96 EQU 0x400f3360 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC97 +CYREG_UDB_P1_ROUTE_HC97 EQU 0x400f3361 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC98 +CYREG_UDB_P1_ROUTE_HC98 EQU 0x400f3362 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC99 +CYREG_UDB_P1_ROUTE_HC99 EQU 0x400f3363 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC100 +CYREG_UDB_P1_ROUTE_HC100 EQU 0x400f3364 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC101 +CYREG_UDB_P1_ROUTE_HC101 EQU 0x400f3365 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC102 +CYREG_UDB_P1_ROUTE_HC102 EQU 0x400f3366 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC103 +CYREG_UDB_P1_ROUTE_HC103 EQU 0x400f3367 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC104 +CYREG_UDB_P1_ROUTE_HC104 EQU 0x400f3368 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC105 +CYREG_UDB_P1_ROUTE_HC105 EQU 0x400f3369 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC106 +CYREG_UDB_P1_ROUTE_HC106 EQU 0x400f336a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC107 +CYREG_UDB_P1_ROUTE_HC107 EQU 0x400f336b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC108 +CYREG_UDB_P1_ROUTE_HC108 EQU 0x400f336c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC109 +CYREG_UDB_P1_ROUTE_HC109 EQU 0x400f336d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC110 +CYREG_UDB_P1_ROUTE_HC110 EQU 0x400f336e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC111 +CYREG_UDB_P1_ROUTE_HC111 EQU 0x400f336f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC112 +CYREG_UDB_P1_ROUTE_HC112 EQU 0x400f3370 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC113 +CYREG_UDB_P1_ROUTE_HC113 EQU 0x400f3371 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC114 +CYREG_UDB_P1_ROUTE_HC114 EQU 0x400f3372 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC115 +CYREG_UDB_P1_ROUTE_HC115 EQU 0x400f3373 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC116 +CYREG_UDB_P1_ROUTE_HC116 EQU 0x400f3374 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC117 +CYREG_UDB_P1_ROUTE_HC117 EQU 0x400f3375 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC118 +CYREG_UDB_P1_ROUTE_HC118 EQU 0x400f3376 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC119 +CYREG_UDB_P1_ROUTE_HC119 EQU 0x400f3377 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC120 +CYREG_UDB_P1_ROUTE_HC120 EQU 0x400f3378 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC121 +CYREG_UDB_P1_ROUTE_HC121 EQU 0x400f3379 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC122 +CYREG_UDB_P1_ROUTE_HC122 EQU 0x400f337a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC123 +CYREG_UDB_P1_ROUTE_HC123 EQU 0x400f337b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC124 +CYREG_UDB_P1_ROUTE_HC124 EQU 0x400f337c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC125 +CYREG_UDB_P1_ROUTE_HC125 EQU 0x400f337d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC126 +CYREG_UDB_P1_ROUTE_HC126 EQU 0x400f337e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HC127 +CYREG_UDB_P1_ROUTE_HC127 EQU 0x400f337f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L0 +CYREG_UDB_P1_ROUTE_HV_L0 EQU 0x400f3380 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L1 +CYREG_UDB_P1_ROUTE_HV_L1 EQU 0x400f3381 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L2 +CYREG_UDB_P1_ROUTE_HV_L2 EQU 0x400f3382 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L3 +CYREG_UDB_P1_ROUTE_HV_L3 EQU 0x400f3383 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L4 +CYREG_UDB_P1_ROUTE_HV_L4 EQU 0x400f3384 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L5 +CYREG_UDB_P1_ROUTE_HV_L5 EQU 0x400f3385 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L6 +CYREG_UDB_P1_ROUTE_HV_L6 EQU 0x400f3386 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L7 +CYREG_UDB_P1_ROUTE_HV_L7 EQU 0x400f3387 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L8 +CYREG_UDB_P1_ROUTE_HV_L8 EQU 0x400f3388 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L9 +CYREG_UDB_P1_ROUTE_HV_L9 EQU 0x400f3389 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L10 +CYREG_UDB_P1_ROUTE_HV_L10 EQU 0x400f338a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L11 +CYREG_UDB_P1_ROUTE_HV_L11 EQU 0x400f338b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L12 +CYREG_UDB_P1_ROUTE_HV_L12 EQU 0x400f338c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L13 +CYREG_UDB_P1_ROUTE_HV_L13 EQU 0x400f338d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L14 +CYREG_UDB_P1_ROUTE_HV_L14 EQU 0x400f338e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_L15 +CYREG_UDB_P1_ROUTE_HV_L15 EQU 0x400f338f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS0 +CYREG_UDB_P1_ROUTE_HS0 EQU 0x400f3390 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS1 +CYREG_UDB_P1_ROUTE_HS1 EQU 0x400f3391 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS2 +CYREG_UDB_P1_ROUTE_HS2 EQU 0x400f3392 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS3 +CYREG_UDB_P1_ROUTE_HS3 EQU 0x400f3393 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS4 +CYREG_UDB_P1_ROUTE_HS4 EQU 0x400f3394 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS5 +CYREG_UDB_P1_ROUTE_HS5 EQU 0x400f3395 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS6 +CYREG_UDB_P1_ROUTE_HS6 EQU 0x400f3396 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS7 +CYREG_UDB_P1_ROUTE_HS7 EQU 0x400f3397 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS8 +CYREG_UDB_P1_ROUTE_HS8 EQU 0x400f3398 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS9 +CYREG_UDB_P1_ROUTE_HS9 EQU 0x400f3399 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS10 +CYREG_UDB_P1_ROUTE_HS10 EQU 0x400f339a + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS11 +CYREG_UDB_P1_ROUTE_HS11 EQU 0x400f339b + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS12 +CYREG_UDB_P1_ROUTE_HS12 EQU 0x400f339c + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS13 +CYREG_UDB_P1_ROUTE_HS13 EQU 0x400f339d + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS14 +CYREG_UDB_P1_ROUTE_HS14 EQU 0x400f339e + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS15 +CYREG_UDB_P1_ROUTE_HS15 EQU 0x400f339f + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS16 +CYREG_UDB_P1_ROUTE_HS16 EQU 0x400f33a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS17 +CYREG_UDB_P1_ROUTE_HS17 EQU 0x400f33a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS18 +CYREG_UDB_P1_ROUTE_HS18 EQU 0x400f33a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS19 +CYREG_UDB_P1_ROUTE_HS19 EQU 0x400f33a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS20 +CYREG_UDB_P1_ROUTE_HS20 EQU 0x400f33a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS21 +CYREG_UDB_P1_ROUTE_HS21 EQU 0x400f33a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS22 +CYREG_UDB_P1_ROUTE_HS22 EQU 0x400f33a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HS23 +CYREG_UDB_P1_ROUTE_HS23 EQU 0x400f33a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R0 +CYREG_UDB_P1_ROUTE_HV_R0 EQU 0x400f33a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R1 +CYREG_UDB_P1_ROUTE_HV_R1 EQU 0x400f33a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R2 +CYREG_UDB_P1_ROUTE_HV_R2 EQU 0x400f33aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R3 +CYREG_UDB_P1_ROUTE_HV_R3 EQU 0x400f33ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R4 +CYREG_UDB_P1_ROUTE_HV_R4 EQU 0x400f33ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R5 +CYREG_UDB_P1_ROUTE_HV_R5 EQU 0x400f33ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R6 +CYREG_UDB_P1_ROUTE_HV_R6 EQU 0x400f33ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R7 +CYREG_UDB_P1_ROUTE_HV_R7 EQU 0x400f33af + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R8 +CYREG_UDB_P1_ROUTE_HV_R8 EQU 0x400f33b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R9 +CYREG_UDB_P1_ROUTE_HV_R9 EQU 0x400f33b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R10 +CYREG_UDB_P1_ROUTE_HV_R10 EQU 0x400f33b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R11 +CYREG_UDB_P1_ROUTE_HV_R11 EQU 0x400f33b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R12 +CYREG_UDB_P1_ROUTE_HV_R12 EQU 0x400f33b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R13 +CYREG_UDB_P1_ROUTE_HV_R13 EQU 0x400f33b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R14 +CYREG_UDB_P1_ROUTE_HV_R14 EQU 0x400f33b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_HV_R15 +CYREG_UDB_P1_ROUTE_HV_R15 EQU 0x400f33b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD0IN0 +CYREG_UDB_P1_ROUTE_PLD0IN0 EQU 0x400f33c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD0IN1 +CYREG_UDB_P1_ROUTE_PLD0IN1 EQU 0x400f33c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD0IN2 +CYREG_UDB_P1_ROUTE_PLD0IN2 EQU 0x400f33c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD1IN0 +CYREG_UDB_P1_ROUTE_PLD1IN0 EQU 0x400f33ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD1IN1 +CYREG_UDB_P1_ROUTE_PLD1IN1 EQU 0x400f33cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_PLD1IN2 +CYREG_UDB_P1_ROUTE_PLD1IN2 EQU 0x400f33ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_DPIN0 +CYREG_UDB_P1_ROUTE_DPIN0 EQU 0x400f33d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_DPIN1 +CYREG_UDB_P1_ROUTE_DPIN1 EQU 0x400f33d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_SCIN +CYREG_UDB_P1_ROUTE_SCIN EQU 0x400f33d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_SCIOIN +CYREG_UDB_P1_ROUTE_SCIOIN EQU 0x400f33d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_RCIN +CYREG_UDB_P1_ROUTE_RCIN EQU 0x400f33de + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS0 +CYREG_UDB_P1_ROUTE_VS0 EQU 0x400f33e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS1 +CYREG_UDB_P1_ROUTE_VS1 EQU 0x400f33e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS2 +CYREG_UDB_P1_ROUTE_VS2 EQU 0x400f33e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS3 +CYREG_UDB_P1_ROUTE_VS3 EQU 0x400f33e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS4 +CYREG_UDB_P1_ROUTE_VS4 EQU 0x400f33e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS5 +CYREG_UDB_P1_ROUTE_VS5 EQU 0x400f33ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS6 +CYREG_UDB_P1_ROUTE_VS6 EQU 0x400f33ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_P1_ROUTE_VS7 +CYREG_UDB_P1_ROUTE_VS7 EQU 0x400f33ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI0_BASE +CYDEV_UDB_DSI0_BASE EQU 0x400f4000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI0_SIZE +CYDEV_UDB_DSI0_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC0 +CYREG_UDB_DSI0_HC0 EQU 0x400f4000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HC_BYTE__OFFSET +CYFLD_UDB_DSI_HC_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HC_BYTE__SIZE +CYFLD_UDB_DSI_HC_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC1 +CYREG_UDB_DSI0_HC1 EQU 0x400f4001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC2 +CYREG_UDB_DSI0_HC2 EQU 0x400f4002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC3 +CYREG_UDB_DSI0_HC3 EQU 0x400f4003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC4 +CYREG_UDB_DSI0_HC4 EQU 0x400f4004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC5 +CYREG_UDB_DSI0_HC5 EQU 0x400f4005 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC6 +CYREG_UDB_DSI0_HC6 EQU 0x400f4006 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC7 +CYREG_UDB_DSI0_HC7 EQU 0x400f4007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC8 +CYREG_UDB_DSI0_HC8 EQU 0x400f4008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC9 +CYREG_UDB_DSI0_HC9 EQU 0x400f4009 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC10 +CYREG_UDB_DSI0_HC10 EQU 0x400f400a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC11 +CYREG_UDB_DSI0_HC11 EQU 0x400f400b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC12 +CYREG_UDB_DSI0_HC12 EQU 0x400f400c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC13 +CYREG_UDB_DSI0_HC13 EQU 0x400f400d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC14 +CYREG_UDB_DSI0_HC14 EQU 0x400f400e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC15 +CYREG_UDB_DSI0_HC15 EQU 0x400f400f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC16 +CYREG_UDB_DSI0_HC16 EQU 0x400f4010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC17 +CYREG_UDB_DSI0_HC17 EQU 0x400f4011 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC18 +CYREG_UDB_DSI0_HC18 EQU 0x400f4012 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC19 +CYREG_UDB_DSI0_HC19 EQU 0x400f4013 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC20 +CYREG_UDB_DSI0_HC20 EQU 0x400f4014 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC21 +CYREG_UDB_DSI0_HC21 EQU 0x400f4015 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC22 +CYREG_UDB_DSI0_HC22 EQU 0x400f4016 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC23 +CYREG_UDB_DSI0_HC23 EQU 0x400f4017 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC24 +CYREG_UDB_DSI0_HC24 EQU 0x400f4018 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC25 +CYREG_UDB_DSI0_HC25 EQU 0x400f4019 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC26 +CYREG_UDB_DSI0_HC26 EQU 0x400f401a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC27 +CYREG_UDB_DSI0_HC27 EQU 0x400f401b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC28 +CYREG_UDB_DSI0_HC28 EQU 0x400f401c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC29 +CYREG_UDB_DSI0_HC29 EQU 0x400f401d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC30 +CYREG_UDB_DSI0_HC30 EQU 0x400f401e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC31 +CYREG_UDB_DSI0_HC31 EQU 0x400f401f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC32 +CYREG_UDB_DSI0_HC32 EQU 0x400f4020 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC33 +CYREG_UDB_DSI0_HC33 EQU 0x400f4021 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC34 +CYREG_UDB_DSI0_HC34 EQU 0x400f4022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC35 +CYREG_UDB_DSI0_HC35 EQU 0x400f4023 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC36 +CYREG_UDB_DSI0_HC36 EQU 0x400f4024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC37 +CYREG_UDB_DSI0_HC37 EQU 0x400f4025 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC38 +CYREG_UDB_DSI0_HC38 EQU 0x400f4026 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC39 +CYREG_UDB_DSI0_HC39 EQU 0x400f4027 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC40 +CYREG_UDB_DSI0_HC40 EQU 0x400f4028 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC41 +CYREG_UDB_DSI0_HC41 EQU 0x400f4029 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC42 +CYREG_UDB_DSI0_HC42 EQU 0x400f402a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC43 +CYREG_UDB_DSI0_HC43 EQU 0x400f402b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC44 +CYREG_UDB_DSI0_HC44 EQU 0x400f402c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC45 +CYREG_UDB_DSI0_HC45 EQU 0x400f402d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC46 +CYREG_UDB_DSI0_HC46 EQU 0x400f402e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC47 +CYREG_UDB_DSI0_HC47 EQU 0x400f402f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC48 +CYREG_UDB_DSI0_HC48 EQU 0x400f4030 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC49 +CYREG_UDB_DSI0_HC49 EQU 0x400f4031 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC50 +CYREG_UDB_DSI0_HC50 EQU 0x400f4032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC51 +CYREG_UDB_DSI0_HC51 EQU 0x400f4033 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC52 +CYREG_UDB_DSI0_HC52 EQU 0x400f4034 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC53 +CYREG_UDB_DSI0_HC53 EQU 0x400f4035 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC54 +CYREG_UDB_DSI0_HC54 EQU 0x400f4036 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC55 +CYREG_UDB_DSI0_HC55 EQU 0x400f4037 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC56 +CYREG_UDB_DSI0_HC56 EQU 0x400f4038 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC57 +CYREG_UDB_DSI0_HC57 EQU 0x400f4039 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC58 +CYREG_UDB_DSI0_HC58 EQU 0x400f403a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC59 +CYREG_UDB_DSI0_HC59 EQU 0x400f403b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC60 +CYREG_UDB_DSI0_HC60 EQU 0x400f403c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC61 +CYREG_UDB_DSI0_HC61 EQU 0x400f403d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC62 +CYREG_UDB_DSI0_HC62 EQU 0x400f403e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC63 +CYREG_UDB_DSI0_HC63 EQU 0x400f403f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC64 +CYREG_UDB_DSI0_HC64 EQU 0x400f4040 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC65 +CYREG_UDB_DSI0_HC65 EQU 0x400f4041 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC66 +CYREG_UDB_DSI0_HC66 EQU 0x400f4042 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC67 +CYREG_UDB_DSI0_HC67 EQU 0x400f4043 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC68 +CYREG_UDB_DSI0_HC68 EQU 0x400f4044 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC69 +CYREG_UDB_DSI0_HC69 EQU 0x400f4045 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC70 +CYREG_UDB_DSI0_HC70 EQU 0x400f4046 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC71 +CYREG_UDB_DSI0_HC71 EQU 0x400f4047 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC72 +CYREG_UDB_DSI0_HC72 EQU 0x400f4048 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC73 +CYREG_UDB_DSI0_HC73 EQU 0x400f4049 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC74 +CYREG_UDB_DSI0_HC74 EQU 0x400f404a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC75 +CYREG_UDB_DSI0_HC75 EQU 0x400f404b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC76 +CYREG_UDB_DSI0_HC76 EQU 0x400f404c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC77 +CYREG_UDB_DSI0_HC77 EQU 0x400f404d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC78 +CYREG_UDB_DSI0_HC78 EQU 0x400f404e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC79 +CYREG_UDB_DSI0_HC79 EQU 0x400f404f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC80 +CYREG_UDB_DSI0_HC80 EQU 0x400f4050 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC81 +CYREG_UDB_DSI0_HC81 EQU 0x400f4051 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC82 +CYREG_UDB_DSI0_HC82 EQU 0x400f4052 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC83 +CYREG_UDB_DSI0_HC83 EQU 0x400f4053 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC84 +CYREG_UDB_DSI0_HC84 EQU 0x400f4054 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC85 +CYREG_UDB_DSI0_HC85 EQU 0x400f4055 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC86 +CYREG_UDB_DSI0_HC86 EQU 0x400f4056 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC87 +CYREG_UDB_DSI0_HC87 EQU 0x400f4057 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC88 +CYREG_UDB_DSI0_HC88 EQU 0x400f4058 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC89 +CYREG_UDB_DSI0_HC89 EQU 0x400f4059 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC90 +CYREG_UDB_DSI0_HC90 EQU 0x400f405a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC91 +CYREG_UDB_DSI0_HC91 EQU 0x400f405b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC92 +CYREG_UDB_DSI0_HC92 EQU 0x400f405c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC93 +CYREG_UDB_DSI0_HC93 EQU 0x400f405d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC94 +CYREG_UDB_DSI0_HC94 EQU 0x400f405e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC95 +CYREG_UDB_DSI0_HC95 EQU 0x400f405f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC96 +CYREG_UDB_DSI0_HC96 EQU 0x400f4060 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC97 +CYREG_UDB_DSI0_HC97 EQU 0x400f4061 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC98 +CYREG_UDB_DSI0_HC98 EQU 0x400f4062 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC99 +CYREG_UDB_DSI0_HC99 EQU 0x400f4063 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC100 +CYREG_UDB_DSI0_HC100 EQU 0x400f4064 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC101 +CYREG_UDB_DSI0_HC101 EQU 0x400f4065 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC102 +CYREG_UDB_DSI0_HC102 EQU 0x400f4066 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC103 +CYREG_UDB_DSI0_HC103 EQU 0x400f4067 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC104 +CYREG_UDB_DSI0_HC104 EQU 0x400f4068 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC105 +CYREG_UDB_DSI0_HC105 EQU 0x400f4069 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC106 +CYREG_UDB_DSI0_HC106 EQU 0x400f406a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC107 +CYREG_UDB_DSI0_HC107 EQU 0x400f406b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC108 +CYREG_UDB_DSI0_HC108 EQU 0x400f406c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC109 +CYREG_UDB_DSI0_HC109 EQU 0x400f406d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC110 +CYREG_UDB_DSI0_HC110 EQU 0x400f406e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC111 +CYREG_UDB_DSI0_HC111 EQU 0x400f406f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC112 +CYREG_UDB_DSI0_HC112 EQU 0x400f4070 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC113 +CYREG_UDB_DSI0_HC113 EQU 0x400f4071 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC114 +CYREG_UDB_DSI0_HC114 EQU 0x400f4072 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC115 +CYREG_UDB_DSI0_HC115 EQU 0x400f4073 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC116 +CYREG_UDB_DSI0_HC116 EQU 0x400f4074 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC117 +CYREG_UDB_DSI0_HC117 EQU 0x400f4075 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC118 +CYREG_UDB_DSI0_HC118 EQU 0x400f4076 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC119 +CYREG_UDB_DSI0_HC119 EQU 0x400f4077 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC120 +CYREG_UDB_DSI0_HC120 EQU 0x400f4078 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC121 +CYREG_UDB_DSI0_HC121 EQU 0x400f4079 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC122 +CYREG_UDB_DSI0_HC122 EQU 0x400f407a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC123 +CYREG_UDB_DSI0_HC123 EQU 0x400f407b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC124 +CYREG_UDB_DSI0_HC124 EQU 0x400f407c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC125 +CYREG_UDB_DSI0_HC125 EQU 0x400f407d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC126 +CYREG_UDB_DSI0_HC126 EQU 0x400f407e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HC127 +CYREG_UDB_DSI0_HC127 EQU 0x400f407f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L0 +CYREG_UDB_DSI0_HV_L0 EQU 0x400f4080 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HV_BYTE__OFFSET +CYFLD_UDB_DSI_HV_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HV_BYTE__SIZE +CYFLD_UDB_DSI_HV_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L1 +CYREG_UDB_DSI0_HV_L1 EQU 0x400f4081 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L2 +CYREG_UDB_DSI0_HV_L2 EQU 0x400f4082 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L3 +CYREG_UDB_DSI0_HV_L3 EQU 0x400f4083 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L4 +CYREG_UDB_DSI0_HV_L4 EQU 0x400f4084 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L5 +CYREG_UDB_DSI0_HV_L5 EQU 0x400f4085 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L6 +CYREG_UDB_DSI0_HV_L6 EQU 0x400f4086 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L7 +CYREG_UDB_DSI0_HV_L7 EQU 0x400f4087 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L8 +CYREG_UDB_DSI0_HV_L8 EQU 0x400f4088 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L9 +CYREG_UDB_DSI0_HV_L9 EQU 0x400f4089 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L10 +CYREG_UDB_DSI0_HV_L10 EQU 0x400f408a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L11 +CYREG_UDB_DSI0_HV_L11 EQU 0x400f408b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L12 +CYREG_UDB_DSI0_HV_L12 EQU 0x400f408c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L13 +CYREG_UDB_DSI0_HV_L13 EQU 0x400f408d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L14 +CYREG_UDB_DSI0_HV_L14 EQU 0x400f408e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_L15 +CYREG_UDB_DSI0_HV_L15 EQU 0x400f408f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS0 +CYREG_UDB_DSI0_HS0 EQU 0x400f4090 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HS_BYTE__OFFSET +CYFLD_UDB_DSI_HS_BYTE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_HS_BYTE__SIZE +CYFLD_UDB_DSI_HS_BYTE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS1 +CYREG_UDB_DSI0_HS1 EQU 0x400f4091 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS2 +CYREG_UDB_DSI0_HS2 EQU 0x400f4092 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS3 +CYREG_UDB_DSI0_HS3 EQU 0x400f4093 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS4 +CYREG_UDB_DSI0_HS4 EQU 0x400f4094 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS5 +CYREG_UDB_DSI0_HS5 EQU 0x400f4095 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS6 +CYREG_UDB_DSI0_HS6 EQU 0x400f4096 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS7 +CYREG_UDB_DSI0_HS7 EQU 0x400f4097 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS8 +CYREG_UDB_DSI0_HS8 EQU 0x400f4098 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS9 +CYREG_UDB_DSI0_HS9 EQU 0x400f4099 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS10 +CYREG_UDB_DSI0_HS10 EQU 0x400f409a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS11 +CYREG_UDB_DSI0_HS11 EQU 0x400f409b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS12 +CYREG_UDB_DSI0_HS12 EQU 0x400f409c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS13 +CYREG_UDB_DSI0_HS13 EQU 0x400f409d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS14 +CYREG_UDB_DSI0_HS14 EQU 0x400f409e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS15 +CYREG_UDB_DSI0_HS15 EQU 0x400f409f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS16 +CYREG_UDB_DSI0_HS16 EQU 0x400f40a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS17 +CYREG_UDB_DSI0_HS17 EQU 0x400f40a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS18 +CYREG_UDB_DSI0_HS18 EQU 0x400f40a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS19 +CYREG_UDB_DSI0_HS19 EQU 0x400f40a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS20 +CYREG_UDB_DSI0_HS20 EQU 0x400f40a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS21 +CYREG_UDB_DSI0_HS21 EQU 0x400f40a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS22 +CYREG_UDB_DSI0_HS22 EQU 0x400f40a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HS23 +CYREG_UDB_DSI0_HS23 EQU 0x400f40a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R0 +CYREG_UDB_DSI0_HV_R0 EQU 0x400f40a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R1 +CYREG_UDB_DSI0_HV_R1 EQU 0x400f40a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R2 +CYREG_UDB_DSI0_HV_R2 EQU 0x400f40aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R3 +CYREG_UDB_DSI0_HV_R3 EQU 0x400f40ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R4 +CYREG_UDB_DSI0_HV_R4 EQU 0x400f40ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R5 +CYREG_UDB_DSI0_HV_R5 EQU 0x400f40ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R6 +CYREG_UDB_DSI0_HV_R6 EQU 0x400f40ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R7 +CYREG_UDB_DSI0_HV_R7 EQU 0x400f40af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R8 +CYREG_UDB_DSI0_HV_R8 EQU 0x400f40b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R9 +CYREG_UDB_DSI0_HV_R9 EQU 0x400f40b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R10 +CYREG_UDB_DSI0_HV_R10 EQU 0x400f40b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R11 +CYREG_UDB_DSI0_HV_R11 EQU 0x400f40b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R12 +CYREG_UDB_DSI0_HV_R12 EQU 0x400f40b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R13 +CYREG_UDB_DSI0_HV_R13 EQU 0x400f40b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R14 +CYREG_UDB_DSI0_HV_R14 EQU 0x400f40b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_HV_R15 +CYREG_UDB_DSI0_HV_R15 EQU 0x400f40b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP0 +CYREG_UDB_DSI0_DSIINP0 EQU 0x400f40c0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_TOP__OFFSET +CYFLD_UDB_DSI_PI_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_TOP__SIZE +CYFLD_UDB_DSI_PI_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_BOT__OFFSET +CYFLD_UDB_DSI_PI_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_PI_BOT__SIZE +CYFLD_UDB_DSI_PI_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP1 +CYREG_UDB_DSI0_DSIINP1 EQU 0x400f40c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP2 +CYREG_UDB_DSI0_DSIINP2 EQU 0x400f40c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP3 +CYREG_UDB_DSI0_DSIINP3 EQU 0x400f40c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP4 +CYREG_UDB_DSI0_DSIINP4 EQU 0x400f40c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIINP5 +CYREG_UDB_DSI0_DSIINP5 EQU 0x400f40ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP0 +CYREG_UDB_DSI0_DSIOUTP0 EQU 0x400f40cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP1 +CYREG_UDB_DSI0_DSIOUTP1 EQU 0x400f40ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP2 +CYREG_UDB_DSI0_DSIOUTP2 EQU 0x400f40d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTP3 +CYREG_UDB_DSI0_DSIOUTP3 EQU 0x400f40d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT0 +CYREG_UDB_DSI0_DSIOUTT0 EQU 0x400f40d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT1 +CYREG_UDB_DSI0_DSIOUTT1 EQU 0x400f40d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT2 +CYREG_UDB_DSI0_DSIOUTT2 EQU 0x400f40d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT3 +CYREG_UDB_DSI0_DSIOUTT3 EQU 0x400f40da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT4 +CYREG_UDB_DSI0_DSIOUTT4 EQU 0x400f40dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_DSIOUTT5 +CYREG_UDB_DSI0_DSIOUTT5 EQU 0x400f40de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS0 +CYREG_UDB_DSI0_VS0 EQU 0x400f40e0 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_TOP__OFFSET +CYFLD_UDB_DSI_VS_TOP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_TOP__SIZE +CYFLD_UDB_DSI_VS_TOP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_BOT__OFFSET +CYFLD_UDB_DSI_VS_BOT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_DSI_VS_BOT__SIZE +CYFLD_UDB_DSI_VS_BOT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS1 +CYREG_UDB_DSI0_VS1 EQU 0x400f40e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS2 +CYREG_UDB_DSI0_VS2 EQU 0x400f40e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS3 +CYREG_UDB_DSI0_VS3 EQU 0x400f40e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS4 +CYREG_UDB_DSI0_VS4 EQU 0x400f40e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS5 +CYREG_UDB_DSI0_VS5 EQU 0x400f40ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS6 +CYREG_UDB_DSI0_VS6 EQU 0x400f40ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI0_VS7 +CYREG_UDB_DSI0_VS7 EQU 0x400f40ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI1_BASE +CYDEV_UDB_DSI1_BASE EQU 0x400f4100 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI1_SIZE +CYDEV_UDB_DSI1_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC0 +CYREG_UDB_DSI1_HC0 EQU 0x400f4100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC1 +CYREG_UDB_DSI1_HC1 EQU 0x400f4101 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC2 +CYREG_UDB_DSI1_HC2 EQU 0x400f4102 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC3 +CYREG_UDB_DSI1_HC3 EQU 0x400f4103 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC4 +CYREG_UDB_DSI1_HC4 EQU 0x400f4104 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC5 +CYREG_UDB_DSI1_HC5 EQU 0x400f4105 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC6 +CYREG_UDB_DSI1_HC6 EQU 0x400f4106 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC7 +CYREG_UDB_DSI1_HC7 EQU 0x400f4107 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC8 +CYREG_UDB_DSI1_HC8 EQU 0x400f4108 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC9 +CYREG_UDB_DSI1_HC9 EQU 0x400f4109 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC10 +CYREG_UDB_DSI1_HC10 EQU 0x400f410a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC11 +CYREG_UDB_DSI1_HC11 EQU 0x400f410b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC12 +CYREG_UDB_DSI1_HC12 EQU 0x400f410c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC13 +CYREG_UDB_DSI1_HC13 EQU 0x400f410d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC14 +CYREG_UDB_DSI1_HC14 EQU 0x400f410e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC15 +CYREG_UDB_DSI1_HC15 EQU 0x400f410f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC16 +CYREG_UDB_DSI1_HC16 EQU 0x400f4110 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC17 +CYREG_UDB_DSI1_HC17 EQU 0x400f4111 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC18 +CYREG_UDB_DSI1_HC18 EQU 0x400f4112 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC19 +CYREG_UDB_DSI1_HC19 EQU 0x400f4113 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC20 +CYREG_UDB_DSI1_HC20 EQU 0x400f4114 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC21 +CYREG_UDB_DSI1_HC21 EQU 0x400f4115 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC22 +CYREG_UDB_DSI1_HC22 EQU 0x400f4116 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC23 +CYREG_UDB_DSI1_HC23 EQU 0x400f4117 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC24 +CYREG_UDB_DSI1_HC24 EQU 0x400f4118 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC25 +CYREG_UDB_DSI1_HC25 EQU 0x400f4119 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC26 +CYREG_UDB_DSI1_HC26 EQU 0x400f411a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC27 +CYREG_UDB_DSI1_HC27 EQU 0x400f411b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC28 +CYREG_UDB_DSI1_HC28 EQU 0x400f411c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC29 +CYREG_UDB_DSI1_HC29 EQU 0x400f411d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC30 +CYREG_UDB_DSI1_HC30 EQU 0x400f411e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC31 +CYREG_UDB_DSI1_HC31 EQU 0x400f411f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC32 +CYREG_UDB_DSI1_HC32 EQU 0x400f4120 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC33 +CYREG_UDB_DSI1_HC33 EQU 0x400f4121 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC34 +CYREG_UDB_DSI1_HC34 EQU 0x400f4122 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC35 +CYREG_UDB_DSI1_HC35 EQU 0x400f4123 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC36 +CYREG_UDB_DSI1_HC36 EQU 0x400f4124 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC37 +CYREG_UDB_DSI1_HC37 EQU 0x400f4125 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC38 +CYREG_UDB_DSI1_HC38 EQU 0x400f4126 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC39 +CYREG_UDB_DSI1_HC39 EQU 0x400f4127 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC40 +CYREG_UDB_DSI1_HC40 EQU 0x400f4128 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC41 +CYREG_UDB_DSI1_HC41 EQU 0x400f4129 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC42 +CYREG_UDB_DSI1_HC42 EQU 0x400f412a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC43 +CYREG_UDB_DSI1_HC43 EQU 0x400f412b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC44 +CYREG_UDB_DSI1_HC44 EQU 0x400f412c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC45 +CYREG_UDB_DSI1_HC45 EQU 0x400f412d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC46 +CYREG_UDB_DSI1_HC46 EQU 0x400f412e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC47 +CYREG_UDB_DSI1_HC47 EQU 0x400f412f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC48 +CYREG_UDB_DSI1_HC48 EQU 0x400f4130 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC49 +CYREG_UDB_DSI1_HC49 EQU 0x400f4131 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC50 +CYREG_UDB_DSI1_HC50 EQU 0x400f4132 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC51 +CYREG_UDB_DSI1_HC51 EQU 0x400f4133 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC52 +CYREG_UDB_DSI1_HC52 EQU 0x400f4134 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC53 +CYREG_UDB_DSI1_HC53 EQU 0x400f4135 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC54 +CYREG_UDB_DSI1_HC54 EQU 0x400f4136 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC55 +CYREG_UDB_DSI1_HC55 EQU 0x400f4137 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC56 +CYREG_UDB_DSI1_HC56 EQU 0x400f4138 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC57 +CYREG_UDB_DSI1_HC57 EQU 0x400f4139 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC58 +CYREG_UDB_DSI1_HC58 EQU 0x400f413a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC59 +CYREG_UDB_DSI1_HC59 EQU 0x400f413b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC60 +CYREG_UDB_DSI1_HC60 EQU 0x400f413c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC61 +CYREG_UDB_DSI1_HC61 EQU 0x400f413d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC62 +CYREG_UDB_DSI1_HC62 EQU 0x400f413e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC63 +CYREG_UDB_DSI1_HC63 EQU 0x400f413f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC64 +CYREG_UDB_DSI1_HC64 EQU 0x400f4140 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC65 +CYREG_UDB_DSI1_HC65 EQU 0x400f4141 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC66 +CYREG_UDB_DSI1_HC66 EQU 0x400f4142 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC67 +CYREG_UDB_DSI1_HC67 EQU 0x400f4143 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC68 +CYREG_UDB_DSI1_HC68 EQU 0x400f4144 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC69 +CYREG_UDB_DSI1_HC69 EQU 0x400f4145 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC70 +CYREG_UDB_DSI1_HC70 EQU 0x400f4146 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC71 +CYREG_UDB_DSI1_HC71 EQU 0x400f4147 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC72 +CYREG_UDB_DSI1_HC72 EQU 0x400f4148 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC73 +CYREG_UDB_DSI1_HC73 EQU 0x400f4149 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC74 +CYREG_UDB_DSI1_HC74 EQU 0x400f414a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC75 +CYREG_UDB_DSI1_HC75 EQU 0x400f414b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC76 +CYREG_UDB_DSI1_HC76 EQU 0x400f414c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC77 +CYREG_UDB_DSI1_HC77 EQU 0x400f414d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC78 +CYREG_UDB_DSI1_HC78 EQU 0x400f414e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC79 +CYREG_UDB_DSI1_HC79 EQU 0x400f414f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC80 +CYREG_UDB_DSI1_HC80 EQU 0x400f4150 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC81 +CYREG_UDB_DSI1_HC81 EQU 0x400f4151 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC82 +CYREG_UDB_DSI1_HC82 EQU 0x400f4152 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC83 +CYREG_UDB_DSI1_HC83 EQU 0x400f4153 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC84 +CYREG_UDB_DSI1_HC84 EQU 0x400f4154 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC85 +CYREG_UDB_DSI1_HC85 EQU 0x400f4155 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC86 +CYREG_UDB_DSI1_HC86 EQU 0x400f4156 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC87 +CYREG_UDB_DSI1_HC87 EQU 0x400f4157 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC88 +CYREG_UDB_DSI1_HC88 EQU 0x400f4158 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC89 +CYREG_UDB_DSI1_HC89 EQU 0x400f4159 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC90 +CYREG_UDB_DSI1_HC90 EQU 0x400f415a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC91 +CYREG_UDB_DSI1_HC91 EQU 0x400f415b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC92 +CYREG_UDB_DSI1_HC92 EQU 0x400f415c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC93 +CYREG_UDB_DSI1_HC93 EQU 0x400f415d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC94 +CYREG_UDB_DSI1_HC94 EQU 0x400f415e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC95 +CYREG_UDB_DSI1_HC95 EQU 0x400f415f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC96 +CYREG_UDB_DSI1_HC96 EQU 0x400f4160 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC97 +CYREG_UDB_DSI1_HC97 EQU 0x400f4161 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC98 +CYREG_UDB_DSI1_HC98 EQU 0x400f4162 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC99 +CYREG_UDB_DSI1_HC99 EQU 0x400f4163 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC100 +CYREG_UDB_DSI1_HC100 EQU 0x400f4164 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC101 +CYREG_UDB_DSI1_HC101 EQU 0x400f4165 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC102 +CYREG_UDB_DSI1_HC102 EQU 0x400f4166 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC103 +CYREG_UDB_DSI1_HC103 EQU 0x400f4167 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC104 +CYREG_UDB_DSI1_HC104 EQU 0x400f4168 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC105 +CYREG_UDB_DSI1_HC105 EQU 0x400f4169 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC106 +CYREG_UDB_DSI1_HC106 EQU 0x400f416a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC107 +CYREG_UDB_DSI1_HC107 EQU 0x400f416b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC108 +CYREG_UDB_DSI1_HC108 EQU 0x400f416c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC109 +CYREG_UDB_DSI1_HC109 EQU 0x400f416d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC110 +CYREG_UDB_DSI1_HC110 EQU 0x400f416e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC111 +CYREG_UDB_DSI1_HC111 EQU 0x400f416f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC112 +CYREG_UDB_DSI1_HC112 EQU 0x400f4170 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC113 +CYREG_UDB_DSI1_HC113 EQU 0x400f4171 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC114 +CYREG_UDB_DSI1_HC114 EQU 0x400f4172 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC115 +CYREG_UDB_DSI1_HC115 EQU 0x400f4173 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC116 +CYREG_UDB_DSI1_HC116 EQU 0x400f4174 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC117 +CYREG_UDB_DSI1_HC117 EQU 0x400f4175 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC118 +CYREG_UDB_DSI1_HC118 EQU 0x400f4176 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC119 +CYREG_UDB_DSI1_HC119 EQU 0x400f4177 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC120 +CYREG_UDB_DSI1_HC120 EQU 0x400f4178 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC121 +CYREG_UDB_DSI1_HC121 EQU 0x400f4179 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC122 +CYREG_UDB_DSI1_HC122 EQU 0x400f417a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC123 +CYREG_UDB_DSI1_HC123 EQU 0x400f417b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC124 +CYREG_UDB_DSI1_HC124 EQU 0x400f417c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC125 +CYREG_UDB_DSI1_HC125 EQU 0x400f417d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC126 +CYREG_UDB_DSI1_HC126 EQU 0x400f417e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HC127 +CYREG_UDB_DSI1_HC127 EQU 0x400f417f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L0 +CYREG_UDB_DSI1_HV_L0 EQU 0x400f4180 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L1 +CYREG_UDB_DSI1_HV_L1 EQU 0x400f4181 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L2 +CYREG_UDB_DSI1_HV_L2 EQU 0x400f4182 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L3 +CYREG_UDB_DSI1_HV_L3 EQU 0x400f4183 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L4 +CYREG_UDB_DSI1_HV_L4 EQU 0x400f4184 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L5 +CYREG_UDB_DSI1_HV_L5 EQU 0x400f4185 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L6 +CYREG_UDB_DSI1_HV_L6 EQU 0x400f4186 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L7 +CYREG_UDB_DSI1_HV_L7 EQU 0x400f4187 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L8 +CYREG_UDB_DSI1_HV_L8 EQU 0x400f4188 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L9 +CYREG_UDB_DSI1_HV_L9 EQU 0x400f4189 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L10 +CYREG_UDB_DSI1_HV_L10 EQU 0x400f418a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L11 +CYREG_UDB_DSI1_HV_L11 EQU 0x400f418b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L12 +CYREG_UDB_DSI1_HV_L12 EQU 0x400f418c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L13 +CYREG_UDB_DSI1_HV_L13 EQU 0x400f418d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L14 +CYREG_UDB_DSI1_HV_L14 EQU 0x400f418e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_L15 +CYREG_UDB_DSI1_HV_L15 EQU 0x400f418f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS0 +CYREG_UDB_DSI1_HS0 EQU 0x400f4190 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS1 +CYREG_UDB_DSI1_HS1 EQU 0x400f4191 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS2 +CYREG_UDB_DSI1_HS2 EQU 0x400f4192 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS3 +CYREG_UDB_DSI1_HS3 EQU 0x400f4193 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS4 +CYREG_UDB_DSI1_HS4 EQU 0x400f4194 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS5 +CYREG_UDB_DSI1_HS5 EQU 0x400f4195 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS6 +CYREG_UDB_DSI1_HS6 EQU 0x400f4196 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS7 +CYREG_UDB_DSI1_HS7 EQU 0x400f4197 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS8 +CYREG_UDB_DSI1_HS8 EQU 0x400f4198 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS9 +CYREG_UDB_DSI1_HS9 EQU 0x400f4199 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS10 +CYREG_UDB_DSI1_HS10 EQU 0x400f419a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS11 +CYREG_UDB_DSI1_HS11 EQU 0x400f419b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS12 +CYREG_UDB_DSI1_HS12 EQU 0x400f419c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS13 +CYREG_UDB_DSI1_HS13 EQU 0x400f419d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS14 +CYREG_UDB_DSI1_HS14 EQU 0x400f419e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS15 +CYREG_UDB_DSI1_HS15 EQU 0x400f419f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS16 +CYREG_UDB_DSI1_HS16 EQU 0x400f41a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS17 +CYREG_UDB_DSI1_HS17 EQU 0x400f41a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS18 +CYREG_UDB_DSI1_HS18 EQU 0x400f41a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS19 +CYREG_UDB_DSI1_HS19 EQU 0x400f41a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS20 +CYREG_UDB_DSI1_HS20 EQU 0x400f41a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS21 +CYREG_UDB_DSI1_HS21 EQU 0x400f41a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS22 +CYREG_UDB_DSI1_HS22 EQU 0x400f41a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HS23 +CYREG_UDB_DSI1_HS23 EQU 0x400f41a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R0 +CYREG_UDB_DSI1_HV_R0 EQU 0x400f41a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R1 +CYREG_UDB_DSI1_HV_R1 EQU 0x400f41a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R2 +CYREG_UDB_DSI1_HV_R2 EQU 0x400f41aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R3 +CYREG_UDB_DSI1_HV_R3 EQU 0x400f41ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R4 +CYREG_UDB_DSI1_HV_R4 EQU 0x400f41ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R5 +CYREG_UDB_DSI1_HV_R5 EQU 0x400f41ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R6 +CYREG_UDB_DSI1_HV_R6 EQU 0x400f41ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R7 +CYREG_UDB_DSI1_HV_R7 EQU 0x400f41af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R8 +CYREG_UDB_DSI1_HV_R8 EQU 0x400f41b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R9 +CYREG_UDB_DSI1_HV_R9 EQU 0x400f41b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R10 +CYREG_UDB_DSI1_HV_R10 EQU 0x400f41b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R11 +CYREG_UDB_DSI1_HV_R11 EQU 0x400f41b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R12 +CYREG_UDB_DSI1_HV_R12 EQU 0x400f41b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R13 +CYREG_UDB_DSI1_HV_R13 EQU 0x400f41b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R14 +CYREG_UDB_DSI1_HV_R14 EQU 0x400f41b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_HV_R15 +CYREG_UDB_DSI1_HV_R15 EQU 0x400f41b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP0 +CYREG_UDB_DSI1_DSIINP0 EQU 0x400f41c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP1 +CYREG_UDB_DSI1_DSIINP1 EQU 0x400f41c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP2 +CYREG_UDB_DSI1_DSIINP2 EQU 0x400f41c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP3 +CYREG_UDB_DSI1_DSIINP3 EQU 0x400f41c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP4 +CYREG_UDB_DSI1_DSIINP4 EQU 0x400f41c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIINP5 +CYREG_UDB_DSI1_DSIINP5 EQU 0x400f41ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP0 +CYREG_UDB_DSI1_DSIOUTP0 EQU 0x400f41cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP1 +CYREG_UDB_DSI1_DSIOUTP1 EQU 0x400f41ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP2 +CYREG_UDB_DSI1_DSIOUTP2 EQU 0x400f41d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTP3 +CYREG_UDB_DSI1_DSIOUTP3 EQU 0x400f41d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT0 +CYREG_UDB_DSI1_DSIOUTT0 EQU 0x400f41d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT1 +CYREG_UDB_DSI1_DSIOUTT1 EQU 0x400f41d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT2 +CYREG_UDB_DSI1_DSIOUTT2 EQU 0x400f41d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT3 +CYREG_UDB_DSI1_DSIOUTT3 EQU 0x400f41da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT4 +CYREG_UDB_DSI1_DSIOUTT4 EQU 0x400f41dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_DSIOUTT5 +CYREG_UDB_DSI1_DSIOUTT5 EQU 0x400f41de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS0 +CYREG_UDB_DSI1_VS0 EQU 0x400f41e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS1 +CYREG_UDB_DSI1_VS1 EQU 0x400f41e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS2 +CYREG_UDB_DSI1_VS2 EQU 0x400f41e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS3 +CYREG_UDB_DSI1_VS3 EQU 0x400f41e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS4 +CYREG_UDB_DSI1_VS4 EQU 0x400f41e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS5 +CYREG_UDB_DSI1_VS5 EQU 0x400f41ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS6 +CYREG_UDB_DSI1_VS6 EQU 0x400f41ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI1_VS7 +CYREG_UDB_DSI1_VS7 EQU 0x400f41ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI2_BASE +CYDEV_UDB_DSI2_BASE EQU 0x400f4200 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI2_SIZE +CYDEV_UDB_DSI2_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC0 +CYREG_UDB_DSI2_HC0 EQU 0x400f4200 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC1 +CYREG_UDB_DSI2_HC1 EQU 0x400f4201 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC2 +CYREG_UDB_DSI2_HC2 EQU 0x400f4202 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC3 +CYREG_UDB_DSI2_HC3 EQU 0x400f4203 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC4 +CYREG_UDB_DSI2_HC4 EQU 0x400f4204 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC5 +CYREG_UDB_DSI2_HC5 EQU 0x400f4205 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC6 +CYREG_UDB_DSI2_HC6 EQU 0x400f4206 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC7 +CYREG_UDB_DSI2_HC7 EQU 0x400f4207 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC8 +CYREG_UDB_DSI2_HC8 EQU 0x400f4208 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC9 +CYREG_UDB_DSI2_HC9 EQU 0x400f4209 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC10 +CYREG_UDB_DSI2_HC10 EQU 0x400f420a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC11 +CYREG_UDB_DSI2_HC11 EQU 0x400f420b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC12 +CYREG_UDB_DSI2_HC12 EQU 0x400f420c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC13 +CYREG_UDB_DSI2_HC13 EQU 0x400f420d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC14 +CYREG_UDB_DSI2_HC14 EQU 0x400f420e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC15 +CYREG_UDB_DSI2_HC15 EQU 0x400f420f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC16 +CYREG_UDB_DSI2_HC16 EQU 0x400f4210 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC17 +CYREG_UDB_DSI2_HC17 EQU 0x400f4211 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC18 +CYREG_UDB_DSI2_HC18 EQU 0x400f4212 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC19 +CYREG_UDB_DSI2_HC19 EQU 0x400f4213 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC20 +CYREG_UDB_DSI2_HC20 EQU 0x400f4214 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC21 +CYREG_UDB_DSI2_HC21 EQU 0x400f4215 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC22 +CYREG_UDB_DSI2_HC22 EQU 0x400f4216 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC23 +CYREG_UDB_DSI2_HC23 EQU 0x400f4217 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC24 +CYREG_UDB_DSI2_HC24 EQU 0x400f4218 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC25 +CYREG_UDB_DSI2_HC25 EQU 0x400f4219 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC26 +CYREG_UDB_DSI2_HC26 EQU 0x400f421a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC27 +CYREG_UDB_DSI2_HC27 EQU 0x400f421b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC28 +CYREG_UDB_DSI2_HC28 EQU 0x400f421c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC29 +CYREG_UDB_DSI2_HC29 EQU 0x400f421d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC30 +CYREG_UDB_DSI2_HC30 EQU 0x400f421e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC31 +CYREG_UDB_DSI2_HC31 EQU 0x400f421f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC32 +CYREG_UDB_DSI2_HC32 EQU 0x400f4220 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC33 +CYREG_UDB_DSI2_HC33 EQU 0x400f4221 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC34 +CYREG_UDB_DSI2_HC34 EQU 0x400f4222 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC35 +CYREG_UDB_DSI2_HC35 EQU 0x400f4223 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC36 +CYREG_UDB_DSI2_HC36 EQU 0x400f4224 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC37 +CYREG_UDB_DSI2_HC37 EQU 0x400f4225 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC38 +CYREG_UDB_DSI2_HC38 EQU 0x400f4226 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC39 +CYREG_UDB_DSI2_HC39 EQU 0x400f4227 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC40 +CYREG_UDB_DSI2_HC40 EQU 0x400f4228 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC41 +CYREG_UDB_DSI2_HC41 EQU 0x400f4229 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC42 +CYREG_UDB_DSI2_HC42 EQU 0x400f422a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC43 +CYREG_UDB_DSI2_HC43 EQU 0x400f422b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC44 +CYREG_UDB_DSI2_HC44 EQU 0x400f422c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC45 +CYREG_UDB_DSI2_HC45 EQU 0x400f422d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC46 +CYREG_UDB_DSI2_HC46 EQU 0x400f422e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC47 +CYREG_UDB_DSI2_HC47 EQU 0x400f422f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC48 +CYREG_UDB_DSI2_HC48 EQU 0x400f4230 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC49 +CYREG_UDB_DSI2_HC49 EQU 0x400f4231 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC50 +CYREG_UDB_DSI2_HC50 EQU 0x400f4232 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC51 +CYREG_UDB_DSI2_HC51 EQU 0x400f4233 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC52 +CYREG_UDB_DSI2_HC52 EQU 0x400f4234 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC53 +CYREG_UDB_DSI2_HC53 EQU 0x400f4235 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC54 +CYREG_UDB_DSI2_HC54 EQU 0x400f4236 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC55 +CYREG_UDB_DSI2_HC55 EQU 0x400f4237 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC56 +CYREG_UDB_DSI2_HC56 EQU 0x400f4238 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC57 +CYREG_UDB_DSI2_HC57 EQU 0x400f4239 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC58 +CYREG_UDB_DSI2_HC58 EQU 0x400f423a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC59 +CYREG_UDB_DSI2_HC59 EQU 0x400f423b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC60 +CYREG_UDB_DSI2_HC60 EQU 0x400f423c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC61 +CYREG_UDB_DSI2_HC61 EQU 0x400f423d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC62 +CYREG_UDB_DSI2_HC62 EQU 0x400f423e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC63 +CYREG_UDB_DSI2_HC63 EQU 0x400f423f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC64 +CYREG_UDB_DSI2_HC64 EQU 0x400f4240 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC65 +CYREG_UDB_DSI2_HC65 EQU 0x400f4241 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC66 +CYREG_UDB_DSI2_HC66 EQU 0x400f4242 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC67 +CYREG_UDB_DSI2_HC67 EQU 0x400f4243 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC68 +CYREG_UDB_DSI2_HC68 EQU 0x400f4244 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC69 +CYREG_UDB_DSI2_HC69 EQU 0x400f4245 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC70 +CYREG_UDB_DSI2_HC70 EQU 0x400f4246 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC71 +CYREG_UDB_DSI2_HC71 EQU 0x400f4247 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC72 +CYREG_UDB_DSI2_HC72 EQU 0x400f4248 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC73 +CYREG_UDB_DSI2_HC73 EQU 0x400f4249 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC74 +CYREG_UDB_DSI2_HC74 EQU 0x400f424a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC75 +CYREG_UDB_DSI2_HC75 EQU 0x400f424b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC76 +CYREG_UDB_DSI2_HC76 EQU 0x400f424c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC77 +CYREG_UDB_DSI2_HC77 EQU 0x400f424d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC78 +CYREG_UDB_DSI2_HC78 EQU 0x400f424e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC79 +CYREG_UDB_DSI2_HC79 EQU 0x400f424f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC80 +CYREG_UDB_DSI2_HC80 EQU 0x400f4250 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC81 +CYREG_UDB_DSI2_HC81 EQU 0x400f4251 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC82 +CYREG_UDB_DSI2_HC82 EQU 0x400f4252 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC83 +CYREG_UDB_DSI2_HC83 EQU 0x400f4253 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC84 +CYREG_UDB_DSI2_HC84 EQU 0x400f4254 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC85 +CYREG_UDB_DSI2_HC85 EQU 0x400f4255 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC86 +CYREG_UDB_DSI2_HC86 EQU 0x400f4256 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC87 +CYREG_UDB_DSI2_HC87 EQU 0x400f4257 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC88 +CYREG_UDB_DSI2_HC88 EQU 0x400f4258 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC89 +CYREG_UDB_DSI2_HC89 EQU 0x400f4259 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC90 +CYREG_UDB_DSI2_HC90 EQU 0x400f425a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC91 +CYREG_UDB_DSI2_HC91 EQU 0x400f425b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC92 +CYREG_UDB_DSI2_HC92 EQU 0x400f425c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC93 +CYREG_UDB_DSI2_HC93 EQU 0x400f425d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC94 +CYREG_UDB_DSI2_HC94 EQU 0x400f425e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC95 +CYREG_UDB_DSI2_HC95 EQU 0x400f425f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC96 +CYREG_UDB_DSI2_HC96 EQU 0x400f4260 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC97 +CYREG_UDB_DSI2_HC97 EQU 0x400f4261 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC98 +CYREG_UDB_DSI2_HC98 EQU 0x400f4262 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC99 +CYREG_UDB_DSI2_HC99 EQU 0x400f4263 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC100 +CYREG_UDB_DSI2_HC100 EQU 0x400f4264 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC101 +CYREG_UDB_DSI2_HC101 EQU 0x400f4265 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC102 +CYREG_UDB_DSI2_HC102 EQU 0x400f4266 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC103 +CYREG_UDB_DSI2_HC103 EQU 0x400f4267 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC104 +CYREG_UDB_DSI2_HC104 EQU 0x400f4268 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC105 +CYREG_UDB_DSI2_HC105 EQU 0x400f4269 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC106 +CYREG_UDB_DSI2_HC106 EQU 0x400f426a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC107 +CYREG_UDB_DSI2_HC107 EQU 0x400f426b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC108 +CYREG_UDB_DSI2_HC108 EQU 0x400f426c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC109 +CYREG_UDB_DSI2_HC109 EQU 0x400f426d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC110 +CYREG_UDB_DSI2_HC110 EQU 0x400f426e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC111 +CYREG_UDB_DSI2_HC111 EQU 0x400f426f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC112 +CYREG_UDB_DSI2_HC112 EQU 0x400f4270 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC113 +CYREG_UDB_DSI2_HC113 EQU 0x400f4271 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC114 +CYREG_UDB_DSI2_HC114 EQU 0x400f4272 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC115 +CYREG_UDB_DSI2_HC115 EQU 0x400f4273 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC116 +CYREG_UDB_DSI2_HC116 EQU 0x400f4274 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC117 +CYREG_UDB_DSI2_HC117 EQU 0x400f4275 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC118 +CYREG_UDB_DSI2_HC118 EQU 0x400f4276 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC119 +CYREG_UDB_DSI2_HC119 EQU 0x400f4277 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC120 +CYREG_UDB_DSI2_HC120 EQU 0x400f4278 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC121 +CYREG_UDB_DSI2_HC121 EQU 0x400f4279 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC122 +CYREG_UDB_DSI2_HC122 EQU 0x400f427a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC123 +CYREG_UDB_DSI2_HC123 EQU 0x400f427b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC124 +CYREG_UDB_DSI2_HC124 EQU 0x400f427c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC125 +CYREG_UDB_DSI2_HC125 EQU 0x400f427d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC126 +CYREG_UDB_DSI2_HC126 EQU 0x400f427e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HC127 +CYREG_UDB_DSI2_HC127 EQU 0x400f427f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L0 +CYREG_UDB_DSI2_HV_L0 EQU 0x400f4280 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L1 +CYREG_UDB_DSI2_HV_L1 EQU 0x400f4281 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L2 +CYREG_UDB_DSI2_HV_L2 EQU 0x400f4282 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L3 +CYREG_UDB_DSI2_HV_L3 EQU 0x400f4283 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L4 +CYREG_UDB_DSI2_HV_L4 EQU 0x400f4284 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L5 +CYREG_UDB_DSI2_HV_L5 EQU 0x400f4285 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L6 +CYREG_UDB_DSI2_HV_L6 EQU 0x400f4286 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L7 +CYREG_UDB_DSI2_HV_L7 EQU 0x400f4287 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L8 +CYREG_UDB_DSI2_HV_L8 EQU 0x400f4288 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L9 +CYREG_UDB_DSI2_HV_L9 EQU 0x400f4289 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L10 +CYREG_UDB_DSI2_HV_L10 EQU 0x400f428a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L11 +CYREG_UDB_DSI2_HV_L11 EQU 0x400f428b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L12 +CYREG_UDB_DSI2_HV_L12 EQU 0x400f428c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L13 +CYREG_UDB_DSI2_HV_L13 EQU 0x400f428d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L14 +CYREG_UDB_DSI2_HV_L14 EQU 0x400f428e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_L15 +CYREG_UDB_DSI2_HV_L15 EQU 0x400f428f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS0 +CYREG_UDB_DSI2_HS0 EQU 0x400f4290 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS1 +CYREG_UDB_DSI2_HS1 EQU 0x400f4291 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS2 +CYREG_UDB_DSI2_HS2 EQU 0x400f4292 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS3 +CYREG_UDB_DSI2_HS3 EQU 0x400f4293 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS4 +CYREG_UDB_DSI2_HS4 EQU 0x400f4294 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS5 +CYREG_UDB_DSI2_HS5 EQU 0x400f4295 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS6 +CYREG_UDB_DSI2_HS6 EQU 0x400f4296 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS7 +CYREG_UDB_DSI2_HS7 EQU 0x400f4297 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS8 +CYREG_UDB_DSI2_HS8 EQU 0x400f4298 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS9 +CYREG_UDB_DSI2_HS9 EQU 0x400f4299 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS10 +CYREG_UDB_DSI2_HS10 EQU 0x400f429a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS11 +CYREG_UDB_DSI2_HS11 EQU 0x400f429b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS12 +CYREG_UDB_DSI2_HS12 EQU 0x400f429c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS13 +CYREG_UDB_DSI2_HS13 EQU 0x400f429d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS14 +CYREG_UDB_DSI2_HS14 EQU 0x400f429e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS15 +CYREG_UDB_DSI2_HS15 EQU 0x400f429f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS16 +CYREG_UDB_DSI2_HS16 EQU 0x400f42a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS17 +CYREG_UDB_DSI2_HS17 EQU 0x400f42a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS18 +CYREG_UDB_DSI2_HS18 EQU 0x400f42a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS19 +CYREG_UDB_DSI2_HS19 EQU 0x400f42a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS20 +CYREG_UDB_DSI2_HS20 EQU 0x400f42a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS21 +CYREG_UDB_DSI2_HS21 EQU 0x400f42a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS22 +CYREG_UDB_DSI2_HS22 EQU 0x400f42a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HS23 +CYREG_UDB_DSI2_HS23 EQU 0x400f42a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R0 +CYREG_UDB_DSI2_HV_R0 EQU 0x400f42a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R1 +CYREG_UDB_DSI2_HV_R1 EQU 0x400f42a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R2 +CYREG_UDB_DSI2_HV_R2 EQU 0x400f42aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R3 +CYREG_UDB_DSI2_HV_R3 EQU 0x400f42ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R4 +CYREG_UDB_DSI2_HV_R4 EQU 0x400f42ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R5 +CYREG_UDB_DSI2_HV_R5 EQU 0x400f42ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R6 +CYREG_UDB_DSI2_HV_R6 EQU 0x400f42ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R7 +CYREG_UDB_DSI2_HV_R7 EQU 0x400f42af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R8 +CYREG_UDB_DSI2_HV_R8 EQU 0x400f42b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R9 +CYREG_UDB_DSI2_HV_R9 EQU 0x400f42b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R10 +CYREG_UDB_DSI2_HV_R10 EQU 0x400f42b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R11 +CYREG_UDB_DSI2_HV_R11 EQU 0x400f42b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R12 +CYREG_UDB_DSI2_HV_R12 EQU 0x400f42b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R13 +CYREG_UDB_DSI2_HV_R13 EQU 0x400f42b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R14 +CYREG_UDB_DSI2_HV_R14 EQU 0x400f42b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_HV_R15 +CYREG_UDB_DSI2_HV_R15 EQU 0x400f42b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP0 +CYREG_UDB_DSI2_DSIINP0 EQU 0x400f42c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP1 +CYREG_UDB_DSI2_DSIINP1 EQU 0x400f42c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP2 +CYREG_UDB_DSI2_DSIINP2 EQU 0x400f42c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP3 +CYREG_UDB_DSI2_DSIINP3 EQU 0x400f42c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP4 +CYREG_UDB_DSI2_DSIINP4 EQU 0x400f42c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIINP5 +CYREG_UDB_DSI2_DSIINP5 EQU 0x400f42ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP0 +CYREG_UDB_DSI2_DSIOUTP0 EQU 0x400f42cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP1 +CYREG_UDB_DSI2_DSIOUTP1 EQU 0x400f42ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP2 +CYREG_UDB_DSI2_DSIOUTP2 EQU 0x400f42d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTP3 +CYREG_UDB_DSI2_DSIOUTP3 EQU 0x400f42d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT0 +CYREG_UDB_DSI2_DSIOUTT0 EQU 0x400f42d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT1 +CYREG_UDB_DSI2_DSIOUTT1 EQU 0x400f42d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT2 +CYREG_UDB_DSI2_DSIOUTT2 EQU 0x400f42d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT3 +CYREG_UDB_DSI2_DSIOUTT3 EQU 0x400f42da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT4 +CYREG_UDB_DSI2_DSIOUTT4 EQU 0x400f42dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_DSIOUTT5 +CYREG_UDB_DSI2_DSIOUTT5 EQU 0x400f42de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS0 +CYREG_UDB_DSI2_VS0 EQU 0x400f42e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS1 +CYREG_UDB_DSI2_VS1 EQU 0x400f42e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS2 +CYREG_UDB_DSI2_VS2 EQU 0x400f42e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS3 +CYREG_UDB_DSI2_VS3 EQU 0x400f42e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS4 +CYREG_UDB_DSI2_VS4 EQU 0x400f42e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS5 +CYREG_UDB_DSI2_VS5 EQU 0x400f42ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS6 +CYREG_UDB_DSI2_VS6 EQU 0x400f42ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI2_VS7 +CYREG_UDB_DSI2_VS7 EQU 0x400f42ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI3_BASE +CYDEV_UDB_DSI3_BASE EQU 0x400f4300 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_DSI3_SIZE +CYDEV_UDB_DSI3_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC0 +CYREG_UDB_DSI3_HC0 EQU 0x400f4300 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC1 +CYREG_UDB_DSI3_HC1 EQU 0x400f4301 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC2 +CYREG_UDB_DSI3_HC2 EQU 0x400f4302 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC3 +CYREG_UDB_DSI3_HC3 EQU 0x400f4303 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC4 +CYREG_UDB_DSI3_HC4 EQU 0x400f4304 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC5 +CYREG_UDB_DSI3_HC5 EQU 0x400f4305 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC6 +CYREG_UDB_DSI3_HC6 EQU 0x400f4306 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC7 +CYREG_UDB_DSI3_HC7 EQU 0x400f4307 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC8 +CYREG_UDB_DSI3_HC8 EQU 0x400f4308 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC9 +CYREG_UDB_DSI3_HC9 EQU 0x400f4309 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC10 +CYREG_UDB_DSI3_HC10 EQU 0x400f430a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC11 +CYREG_UDB_DSI3_HC11 EQU 0x400f430b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC12 +CYREG_UDB_DSI3_HC12 EQU 0x400f430c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC13 +CYREG_UDB_DSI3_HC13 EQU 0x400f430d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC14 +CYREG_UDB_DSI3_HC14 EQU 0x400f430e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC15 +CYREG_UDB_DSI3_HC15 EQU 0x400f430f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC16 +CYREG_UDB_DSI3_HC16 EQU 0x400f4310 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC17 +CYREG_UDB_DSI3_HC17 EQU 0x400f4311 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC18 +CYREG_UDB_DSI3_HC18 EQU 0x400f4312 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC19 +CYREG_UDB_DSI3_HC19 EQU 0x400f4313 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC20 +CYREG_UDB_DSI3_HC20 EQU 0x400f4314 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC21 +CYREG_UDB_DSI3_HC21 EQU 0x400f4315 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC22 +CYREG_UDB_DSI3_HC22 EQU 0x400f4316 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC23 +CYREG_UDB_DSI3_HC23 EQU 0x400f4317 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC24 +CYREG_UDB_DSI3_HC24 EQU 0x400f4318 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC25 +CYREG_UDB_DSI3_HC25 EQU 0x400f4319 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC26 +CYREG_UDB_DSI3_HC26 EQU 0x400f431a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC27 +CYREG_UDB_DSI3_HC27 EQU 0x400f431b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC28 +CYREG_UDB_DSI3_HC28 EQU 0x400f431c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC29 +CYREG_UDB_DSI3_HC29 EQU 0x400f431d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC30 +CYREG_UDB_DSI3_HC30 EQU 0x400f431e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC31 +CYREG_UDB_DSI3_HC31 EQU 0x400f431f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC32 +CYREG_UDB_DSI3_HC32 EQU 0x400f4320 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC33 +CYREG_UDB_DSI3_HC33 EQU 0x400f4321 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC34 +CYREG_UDB_DSI3_HC34 EQU 0x400f4322 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC35 +CYREG_UDB_DSI3_HC35 EQU 0x400f4323 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC36 +CYREG_UDB_DSI3_HC36 EQU 0x400f4324 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC37 +CYREG_UDB_DSI3_HC37 EQU 0x400f4325 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC38 +CYREG_UDB_DSI3_HC38 EQU 0x400f4326 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC39 +CYREG_UDB_DSI3_HC39 EQU 0x400f4327 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC40 +CYREG_UDB_DSI3_HC40 EQU 0x400f4328 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC41 +CYREG_UDB_DSI3_HC41 EQU 0x400f4329 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC42 +CYREG_UDB_DSI3_HC42 EQU 0x400f432a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC43 +CYREG_UDB_DSI3_HC43 EQU 0x400f432b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC44 +CYREG_UDB_DSI3_HC44 EQU 0x400f432c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC45 +CYREG_UDB_DSI3_HC45 EQU 0x400f432d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC46 +CYREG_UDB_DSI3_HC46 EQU 0x400f432e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC47 +CYREG_UDB_DSI3_HC47 EQU 0x400f432f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC48 +CYREG_UDB_DSI3_HC48 EQU 0x400f4330 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC49 +CYREG_UDB_DSI3_HC49 EQU 0x400f4331 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC50 +CYREG_UDB_DSI3_HC50 EQU 0x400f4332 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC51 +CYREG_UDB_DSI3_HC51 EQU 0x400f4333 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC52 +CYREG_UDB_DSI3_HC52 EQU 0x400f4334 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC53 +CYREG_UDB_DSI3_HC53 EQU 0x400f4335 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC54 +CYREG_UDB_DSI3_HC54 EQU 0x400f4336 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC55 +CYREG_UDB_DSI3_HC55 EQU 0x400f4337 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC56 +CYREG_UDB_DSI3_HC56 EQU 0x400f4338 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC57 +CYREG_UDB_DSI3_HC57 EQU 0x400f4339 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC58 +CYREG_UDB_DSI3_HC58 EQU 0x400f433a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC59 +CYREG_UDB_DSI3_HC59 EQU 0x400f433b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC60 +CYREG_UDB_DSI3_HC60 EQU 0x400f433c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC61 +CYREG_UDB_DSI3_HC61 EQU 0x400f433d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC62 +CYREG_UDB_DSI3_HC62 EQU 0x400f433e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC63 +CYREG_UDB_DSI3_HC63 EQU 0x400f433f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC64 +CYREG_UDB_DSI3_HC64 EQU 0x400f4340 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC65 +CYREG_UDB_DSI3_HC65 EQU 0x400f4341 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC66 +CYREG_UDB_DSI3_HC66 EQU 0x400f4342 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC67 +CYREG_UDB_DSI3_HC67 EQU 0x400f4343 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC68 +CYREG_UDB_DSI3_HC68 EQU 0x400f4344 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC69 +CYREG_UDB_DSI3_HC69 EQU 0x400f4345 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC70 +CYREG_UDB_DSI3_HC70 EQU 0x400f4346 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC71 +CYREG_UDB_DSI3_HC71 EQU 0x400f4347 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC72 +CYREG_UDB_DSI3_HC72 EQU 0x400f4348 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC73 +CYREG_UDB_DSI3_HC73 EQU 0x400f4349 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC74 +CYREG_UDB_DSI3_HC74 EQU 0x400f434a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC75 +CYREG_UDB_DSI3_HC75 EQU 0x400f434b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC76 +CYREG_UDB_DSI3_HC76 EQU 0x400f434c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC77 +CYREG_UDB_DSI3_HC77 EQU 0x400f434d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC78 +CYREG_UDB_DSI3_HC78 EQU 0x400f434e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC79 +CYREG_UDB_DSI3_HC79 EQU 0x400f434f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC80 +CYREG_UDB_DSI3_HC80 EQU 0x400f4350 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC81 +CYREG_UDB_DSI3_HC81 EQU 0x400f4351 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC82 +CYREG_UDB_DSI3_HC82 EQU 0x400f4352 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC83 +CYREG_UDB_DSI3_HC83 EQU 0x400f4353 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC84 +CYREG_UDB_DSI3_HC84 EQU 0x400f4354 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC85 +CYREG_UDB_DSI3_HC85 EQU 0x400f4355 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC86 +CYREG_UDB_DSI3_HC86 EQU 0x400f4356 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC87 +CYREG_UDB_DSI3_HC87 EQU 0x400f4357 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC88 +CYREG_UDB_DSI3_HC88 EQU 0x400f4358 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC89 +CYREG_UDB_DSI3_HC89 EQU 0x400f4359 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC90 +CYREG_UDB_DSI3_HC90 EQU 0x400f435a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC91 +CYREG_UDB_DSI3_HC91 EQU 0x400f435b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC92 +CYREG_UDB_DSI3_HC92 EQU 0x400f435c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC93 +CYREG_UDB_DSI3_HC93 EQU 0x400f435d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC94 +CYREG_UDB_DSI3_HC94 EQU 0x400f435e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC95 +CYREG_UDB_DSI3_HC95 EQU 0x400f435f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC96 +CYREG_UDB_DSI3_HC96 EQU 0x400f4360 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC97 +CYREG_UDB_DSI3_HC97 EQU 0x400f4361 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC98 +CYREG_UDB_DSI3_HC98 EQU 0x400f4362 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC99 +CYREG_UDB_DSI3_HC99 EQU 0x400f4363 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC100 +CYREG_UDB_DSI3_HC100 EQU 0x400f4364 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC101 +CYREG_UDB_DSI3_HC101 EQU 0x400f4365 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC102 +CYREG_UDB_DSI3_HC102 EQU 0x400f4366 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC103 +CYREG_UDB_DSI3_HC103 EQU 0x400f4367 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC104 +CYREG_UDB_DSI3_HC104 EQU 0x400f4368 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC105 +CYREG_UDB_DSI3_HC105 EQU 0x400f4369 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC106 +CYREG_UDB_DSI3_HC106 EQU 0x400f436a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC107 +CYREG_UDB_DSI3_HC107 EQU 0x400f436b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC108 +CYREG_UDB_DSI3_HC108 EQU 0x400f436c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC109 +CYREG_UDB_DSI3_HC109 EQU 0x400f436d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC110 +CYREG_UDB_DSI3_HC110 EQU 0x400f436e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC111 +CYREG_UDB_DSI3_HC111 EQU 0x400f436f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC112 +CYREG_UDB_DSI3_HC112 EQU 0x400f4370 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC113 +CYREG_UDB_DSI3_HC113 EQU 0x400f4371 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC114 +CYREG_UDB_DSI3_HC114 EQU 0x400f4372 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC115 +CYREG_UDB_DSI3_HC115 EQU 0x400f4373 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC116 +CYREG_UDB_DSI3_HC116 EQU 0x400f4374 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC117 +CYREG_UDB_DSI3_HC117 EQU 0x400f4375 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC118 +CYREG_UDB_DSI3_HC118 EQU 0x400f4376 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC119 +CYREG_UDB_DSI3_HC119 EQU 0x400f4377 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC120 +CYREG_UDB_DSI3_HC120 EQU 0x400f4378 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC121 +CYREG_UDB_DSI3_HC121 EQU 0x400f4379 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC122 +CYREG_UDB_DSI3_HC122 EQU 0x400f437a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC123 +CYREG_UDB_DSI3_HC123 EQU 0x400f437b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC124 +CYREG_UDB_DSI3_HC124 EQU 0x400f437c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC125 +CYREG_UDB_DSI3_HC125 EQU 0x400f437d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC126 +CYREG_UDB_DSI3_HC126 EQU 0x400f437e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HC127 +CYREG_UDB_DSI3_HC127 EQU 0x400f437f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L0 +CYREG_UDB_DSI3_HV_L0 EQU 0x400f4380 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L1 +CYREG_UDB_DSI3_HV_L1 EQU 0x400f4381 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L2 +CYREG_UDB_DSI3_HV_L2 EQU 0x400f4382 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L3 +CYREG_UDB_DSI3_HV_L3 EQU 0x400f4383 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L4 +CYREG_UDB_DSI3_HV_L4 EQU 0x400f4384 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L5 +CYREG_UDB_DSI3_HV_L5 EQU 0x400f4385 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L6 +CYREG_UDB_DSI3_HV_L6 EQU 0x400f4386 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L7 +CYREG_UDB_DSI3_HV_L7 EQU 0x400f4387 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L8 +CYREG_UDB_DSI3_HV_L8 EQU 0x400f4388 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L9 +CYREG_UDB_DSI3_HV_L9 EQU 0x400f4389 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L10 +CYREG_UDB_DSI3_HV_L10 EQU 0x400f438a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L11 +CYREG_UDB_DSI3_HV_L11 EQU 0x400f438b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L12 +CYREG_UDB_DSI3_HV_L12 EQU 0x400f438c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L13 +CYREG_UDB_DSI3_HV_L13 EQU 0x400f438d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L14 +CYREG_UDB_DSI3_HV_L14 EQU 0x400f438e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_L15 +CYREG_UDB_DSI3_HV_L15 EQU 0x400f438f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS0 +CYREG_UDB_DSI3_HS0 EQU 0x400f4390 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS1 +CYREG_UDB_DSI3_HS1 EQU 0x400f4391 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS2 +CYREG_UDB_DSI3_HS2 EQU 0x400f4392 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS3 +CYREG_UDB_DSI3_HS3 EQU 0x400f4393 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS4 +CYREG_UDB_DSI3_HS4 EQU 0x400f4394 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS5 +CYREG_UDB_DSI3_HS5 EQU 0x400f4395 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS6 +CYREG_UDB_DSI3_HS6 EQU 0x400f4396 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS7 +CYREG_UDB_DSI3_HS7 EQU 0x400f4397 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS8 +CYREG_UDB_DSI3_HS8 EQU 0x400f4398 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS9 +CYREG_UDB_DSI3_HS9 EQU 0x400f4399 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS10 +CYREG_UDB_DSI3_HS10 EQU 0x400f439a + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS11 +CYREG_UDB_DSI3_HS11 EQU 0x400f439b + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS12 +CYREG_UDB_DSI3_HS12 EQU 0x400f439c + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS13 +CYREG_UDB_DSI3_HS13 EQU 0x400f439d + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS14 +CYREG_UDB_DSI3_HS14 EQU 0x400f439e + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS15 +CYREG_UDB_DSI3_HS15 EQU 0x400f439f + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS16 +CYREG_UDB_DSI3_HS16 EQU 0x400f43a0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS17 +CYREG_UDB_DSI3_HS17 EQU 0x400f43a1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS18 +CYREG_UDB_DSI3_HS18 EQU 0x400f43a2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS19 +CYREG_UDB_DSI3_HS19 EQU 0x400f43a3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS20 +CYREG_UDB_DSI3_HS20 EQU 0x400f43a4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS21 +CYREG_UDB_DSI3_HS21 EQU 0x400f43a5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS22 +CYREG_UDB_DSI3_HS22 EQU 0x400f43a6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HS23 +CYREG_UDB_DSI3_HS23 EQU 0x400f43a7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R0 +CYREG_UDB_DSI3_HV_R0 EQU 0x400f43a8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R1 +CYREG_UDB_DSI3_HV_R1 EQU 0x400f43a9 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R2 +CYREG_UDB_DSI3_HV_R2 EQU 0x400f43aa + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R3 +CYREG_UDB_DSI3_HV_R3 EQU 0x400f43ab + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R4 +CYREG_UDB_DSI3_HV_R4 EQU 0x400f43ac + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R5 +CYREG_UDB_DSI3_HV_R5 EQU 0x400f43ad + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R6 +CYREG_UDB_DSI3_HV_R6 EQU 0x400f43ae + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R7 +CYREG_UDB_DSI3_HV_R7 EQU 0x400f43af + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R8 +CYREG_UDB_DSI3_HV_R8 EQU 0x400f43b0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R9 +CYREG_UDB_DSI3_HV_R9 EQU 0x400f43b1 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R10 +CYREG_UDB_DSI3_HV_R10 EQU 0x400f43b2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R11 +CYREG_UDB_DSI3_HV_R11 EQU 0x400f43b3 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R12 +CYREG_UDB_DSI3_HV_R12 EQU 0x400f43b4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R13 +CYREG_UDB_DSI3_HV_R13 EQU 0x400f43b5 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R14 +CYREG_UDB_DSI3_HV_R14 EQU 0x400f43b6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_HV_R15 +CYREG_UDB_DSI3_HV_R15 EQU 0x400f43b7 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP0 +CYREG_UDB_DSI3_DSIINP0 EQU 0x400f43c0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP1 +CYREG_UDB_DSI3_DSIINP1 EQU 0x400f43c2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP2 +CYREG_UDB_DSI3_DSIINP2 EQU 0x400f43c4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP3 +CYREG_UDB_DSI3_DSIINP3 EQU 0x400f43c6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP4 +CYREG_UDB_DSI3_DSIINP4 EQU 0x400f43c8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIINP5 +CYREG_UDB_DSI3_DSIINP5 EQU 0x400f43ca + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP0 +CYREG_UDB_DSI3_DSIOUTP0 EQU 0x400f43cc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP1 +CYREG_UDB_DSI3_DSIOUTP1 EQU 0x400f43ce + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP2 +CYREG_UDB_DSI3_DSIOUTP2 EQU 0x400f43d0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTP3 +CYREG_UDB_DSI3_DSIOUTP3 EQU 0x400f43d2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT0 +CYREG_UDB_DSI3_DSIOUTT0 EQU 0x400f43d4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT1 +CYREG_UDB_DSI3_DSIOUTT1 EQU 0x400f43d6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT2 +CYREG_UDB_DSI3_DSIOUTT2 EQU 0x400f43d8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT3 +CYREG_UDB_DSI3_DSIOUTT3 EQU 0x400f43da + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT4 +CYREG_UDB_DSI3_DSIOUTT4 EQU 0x400f43dc + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_DSIOUTT5 +CYREG_UDB_DSI3_DSIOUTT5 EQU 0x400f43de + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS0 +CYREG_UDB_DSI3_VS0 EQU 0x400f43e0 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS1 +CYREG_UDB_DSI3_VS1 EQU 0x400f43e2 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS2 +CYREG_UDB_DSI3_VS2 EQU 0x400f43e4 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS3 +CYREG_UDB_DSI3_VS3 EQU 0x400f43e6 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS4 +CYREG_UDB_DSI3_VS4 EQU 0x400f43e8 + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS5 +CYREG_UDB_DSI3_VS5 EQU 0x400f43ea + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS6 +CYREG_UDB_DSI3_VS6 EQU 0x400f43ec + ENDIF + IF :LNOT::DEF:CYREG_UDB_DSI3_VS7 +CYREG_UDB_DSI3_VS7 EQU 0x400f43ee + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA0_BASE +CYDEV_UDB_PA0_BASE EQU 0x400f5000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA0_SIZE +CYDEV_UDB_PA0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG0 +CYREG_UDB_PA0_CFG0 EQU 0x400f5000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET +CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE +CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC +CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET +CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE +CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_OFF +CYVAL_UDB_PA_CLKIN_EN_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_ON +CYVAL_UDB_PA_CLKIN_EN_MODE_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE +CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL +CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET +CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_EN_INV__SIZE +CYFLD_UDB_PA_CLKIN_EN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_INV_NOINV +CYVAL_UDB_PA_CLKIN_EN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_EN_INV_INV +CYVAL_UDB_PA_CLKIN_EN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_INV__OFFSET +CYFLD_UDB_PA_CLKIN_INV__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_INV__SIZE +CYFLD_UDB_PA_CLKIN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_INV_NOINV +CYVAL_UDB_PA_CLKIN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_INV_INV +CYVAL_UDB_PA_CLKIN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC__OFFSET +CYFLD_UDB_PA_NC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC__SIZE +CYFLD_UDB_PA_NC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG1 +CYREG_UDB_PA0_CFG1 EQU 0x400f5001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET +CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE +CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC +CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET +CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE +CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF +CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_ON +CYVAL_UDB_PA_CLKOUT_EN_MODE_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE +CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL +CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET +CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE +CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV +CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_EN_INV_INV +CYVAL_UDB_PA_CLKOUT_EN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_INV__OFFSET +CYFLD_UDB_PA_CLKOUT_INV__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_INV__SIZE +CYFLD_UDB_PA_CLKOUT_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_INV_NOINV +CYVAL_UDB_PA_CLKOUT_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_INV_INV +CYVAL_UDB_PA_CLKOUT_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG2 +CYREG_UDB_PA0_CFG2 EQU 0x400f5002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_SEL__OFFSET +CYFLD_UDB_PA_CLKIN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKIN_SEL__SIZE +CYFLD_UDB_PA_CLKIN_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK0 +CYVAL_UDB_PA_CLKIN_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK1 +CYVAL_UDB_PA_CLKIN_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK2 +CYVAL_UDB_PA_CLKIN_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK3 +CYVAL_UDB_PA_CLKIN_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK4 +CYVAL_UDB_PA_CLKIN_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK5 +CYVAL_UDB_PA_CLKIN_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK6 +CYVAL_UDB_PA_CLKIN_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_GCLK7 +CYVAL_UDB_PA_CLKIN_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP +CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_PIN_RC +CYVAL_UDB_PA_CLKIN_SEL_PIN_RC EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_SEL__OFFSET +CYFLD_UDB_PA_CLKOUT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_CLKOUT_SEL__SIZE +CYFLD_UDB_PA_CLKOUT_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 +CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP +CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC +CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 +CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 +CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 +CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG3 +CYREG_UDB_PA0_CFG3 EQU 0x400f5003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_SEL__OFFSET +CYFLD_UDB_PA_RES_IN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_SEL__SIZE +CYFLD_UDB_PA_RES_IN_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_PIN_RC +CYVAL_UDB_PA_RES_IN_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 +CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 +CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 +CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_INV__OFFSET +CYFLD_UDB_PA_RES_IN_INV__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_INV__SIZE +CYFLD_UDB_PA_RES_IN_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_INV_NOINV +CYVAL_UDB_PA_RES_IN_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_INV_INV +CYVAL_UDB_PA_RES_IN_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC0__OFFSET +CYFLD_UDB_PA_NC0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC0__SIZE +CYFLD_UDB_PA_NC0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_SEL__OFFSET +CYFLD_UDB_PA_RES_OUT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_SEL__SIZE +CYFLD_UDB_PA_RES_OUT_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC +CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 +CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 +CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 +CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_INV__OFFSET +CYFLD_UDB_PA_RES_OUT_INV__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_INV__SIZE +CYFLD_UDB_PA_RES_OUT_INV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_INV_NOINV +CYVAL_UDB_PA_RES_OUT_INV_NOINV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_INV_INV +CYVAL_UDB_PA_RES_OUT_INV_INV EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7__OFFSET +CYFLD_UDB_PA_NC7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7__SIZE +CYFLD_UDB_PA_NC7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG4 +CYREG_UDB_PA0_CFG4 EQU 0x400f5004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_EN__OFFSET +CYFLD_UDB_PA_RES_IN_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_IN_EN__SIZE +CYFLD_UDB_PA_RES_IN_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_EN_DISABLE +CYVAL_UDB_PA_RES_IN_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_IN_EN_ENABLE +CYVAL_UDB_PA_RES_IN_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_EN__OFFSET +CYFLD_UDB_PA_RES_OUT_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OUT_EN__SIZE +CYFLD_UDB_PA_RES_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_EN_DISABLE +CYVAL_UDB_PA_RES_OUT_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OUT_EN_ENABLE +CYVAL_UDB_PA_RES_OUT_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OE_EN__OFFSET +CYFLD_UDB_PA_RES_OE_EN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_RES_OE_EN__SIZE +CYFLD_UDB_PA_RES_OE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OE_EN_DISABLE +CYVAL_UDB_PA_RES_OE_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_RES_OE_EN_ENABLE +CYVAL_UDB_PA_RES_OE_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7654__OFFSET +CYFLD_UDB_PA_NC7654__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_NC7654__SIZE +CYFLD_UDB_PA_NC7654__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG5 +CYREG_UDB_PA0_CFG5 EQU 0x400f5005 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_PIN_SEL__OFFSET +CYFLD_UDB_PA_PIN_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_PIN_SEL__SIZE +CYFLD_UDB_PA_PIN_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN0 +CYVAL_UDB_PA_PIN_SEL_PIN0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN1 +CYVAL_UDB_PA_PIN_SEL_PIN1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN2 +CYVAL_UDB_PA_PIN_SEL_PIN2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN3 +CYVAL_UDB_PA_PIN_SEL_PIN3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN4 +CYVAL_UDB_PA_PIN_SEL_PIN4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN5 +CYVAL_UDB_PA_PIN_SEL_PIN5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN6 +CYVAL_UDB_PA_PIN_SEL_PIN6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_PIN_SEL_PIN7 +CYVAL_UDB_PA_PIN_SEL_PIN7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG6 +CYREG_UDB_PA0_CFG6 EQU 0x400f5006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC0__OFFSET +CYFLD_UDB_PA_IN_SYNC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC0__SIZE +CYFLD_UDB_PA_IN_SYNC0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC0_RSVD +CYVAL_UDB_PA_IN_SYNC0_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC1__OFFSET +CYFLD_UDB_PA_IN_SYNC1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC1__SIZE +CYFLD_UDB_PA_IN_SYNC1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC1_RSVD +CYVAL_UDB_PA_IN_SYNC1_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC2__OFFSET +CYFLD_UDB_PA_IN_SYNC2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC2__SIZE +CYFLD_UDB_PA_IN_SYNC2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC2_RSVD +CYVAL_UDB_PA_IN_SYNC2_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC3__OFFSET +CYFLD_UDB_PA_IN_SYNC3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC3__SIZE +CYFLD_UDB_PA_IN_SYNC3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC3_RSVD +CYVAL_UDB_PA_IN_SYNC3_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG7 +CYREG_UDB_PA0_CFG7 EQU 0x400f5007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC4__OFFSET +CYFLD_UDB_PA_IN_SYNC4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC4__SIZE +CYFLD_UDB_PA_IN_SYNC4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC4_RSVD +CYVAL_UDB_PA_IN_SYNC4_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC5__OFFSET +CYFLD_UDB_PA_IN_SYNC5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC5__SIZE +CYFLD_UDB_PA_IN_SYNC5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC5_RSVD +CYVAL_UDB_PA_IN_SYNC5_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC6__OFFSET +CYFLD_UDB_PA_IN_SYNC6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC6__SIZE +CYFLD_UDB_PA_IN_SYNC6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC6_RSVD +CYVAL_UDB_PA_IN_SYNC6_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC7__OFFSET +CYFLD_UDB_PA_IN_SYNC7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_IN_SYNC7__SIZE +CYFLD_UDB_PA_IN_SYNC7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT +CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC +CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC +CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_IN_SYNC7_RSVD +CYVAL_UDB_PA_IN_SYNC7_RSVD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG8 +CYREG_UDB_PA0_CFG8 EQU 0x400f5008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC0__OFFSET +CYFLD_UDB_PA_OUT_SYNC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC0__SIZE +CYFLD_UDB_PA_OUT_SYNC0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_CLOCK +CYVAL_UDB_PA_OUT_SYNC0_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC1__OFFSET +CYFLD_UDB_PA_OUT_SYNC1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC1__SIZE +CYFLD_UDB_PA_OUT_SYNC1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_CLOCK +CYVAL_UDB_PA_OUT_SYNC1_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC2__OFFSET +CYFLD_UDB_PA_OUT_SYNC2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC2__SIZE +CYFLD_UDB_PA_OUT_SYNC2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_CLOCK +CYVAL_UDB_PA_OUT_SYNC2_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC3__OFFSET +CYFLD_UDB_PA_OUT_SYNC3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC3__SIZE +CYFLD_UDB_PA_OUT_SYNC3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_CLOCK +CYVAL_UDB_PA_OUT_SYNC3_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG9 +CYREG_UDB_PA0_CFG9 EQU 0x400f5009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC4__OFFSET +CYFLD_UDB_PA_OUT_SYNC4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC4__SIZE +CYFLD_UDB_PA_OUT_SYNC4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_CLOCK +CYVAL_UDB_PA_OUT_SYNC4_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC5__OFFSET +CYFLD_UDB_PA_OUT_SYNC5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC5__SIZE +CYFLD_UDB_PA_OUT_SYNC5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_CLOCK +CYVAL_UDB_PA_OUT_SYNC5_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC6__OFFSET +CYFLD_UDB_PA_OUT_SYNC6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC6__SIZE +CYFLD_UDB_PA_OUT_SYNC6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_CLOCK +CYVAL_UDB_PA_OUT_SYNC6_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC7__OFFSET +CYFLD_UDB_PA_OUT_SYNC7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OUT_SYNC7__SIZE +CYFLD_UDB_PA_OUT_SYNC7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT +CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC +CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_CLOCK +CYVAL_UDB_PA_OUT_SYNC7_CLOCK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV +CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG10 +CYREG_UDB_PA0_CFG10 EQU 0x400f500a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL0__OFFSET +CYFLD_UDB_PA_DATA_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL0__SIZE +CYFLD_UDB_PA_DATA_SEL0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL1__OFFSET +CYFLD_UDB_PA_DATA_SEL1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL1__SIZE +CYFLD_UDB_PA_DATA_SEL1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL2__OFFSET +CYFLD_UDB_PA_DATA_SEL2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL2__SIZE +CYFLD_UDB_PA_DATA_SEL2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL3__OFFSET +CYFLD_UDB_PA_DATA_SEL3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL3__SIZE +CYFLD_UDB_PA_DATA_SEL3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG11 +CYREG_UDB_PA0_CFG11 EQU 0x400f500b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL4__OFFSET +CYFLD_UDB_PA_DATA_SEL4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL4__SIZE +CYFLD_UDB_PA_DATA_SEL4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL5__OFFSET +CYFLD_UDB_PA_DATA_SEL5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL5__SIZE +CYFLD_UDB_PA_DATA_SEL5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL6__OFFSET +CYFLD_UDB_PA_DATA_SEL6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL6__SIZE +CYFLD_UDB_PA_DATA_SEL6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL7__OFFSET +CYFLD_UDB_PA_DATA_SEL7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_DATA_SEL7__SIZE +CYFLD_UDB_PA_DATA_SEL7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 +CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG12 +CYREG_UDB_PA0_CFG12 EQU 0x400f500c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL0__OFFSET +CYFLD_UDB_PA_OE_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL0__SIZE +CYFLD_UDB_PA_OE_SEL0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL1__OFFSET +CYFLD_UDB_PA_OE_SEL1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL1__SIZE +CYFLD_UDB_PA_OE_SEL1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL2__OFFSET +CYFLD_UDB_PA_OE_SEL2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL2__SIZE +CYFLD_UDB_PA_OE_SEL2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL3__OFFSET +CYFLD_UDB_PA_OE_SEL3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL3__SIZE +CYFLD_UDB_PA_OE_SEL3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG13 +CYREG_UDB_PA0_CFG13 EQU 0x400f500d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL4__OFFSET +CYFLD_UDB_PA_OE_SEL4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL4__SIZE +CYFLD_UDB_PA_OE_SEL4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL5__OFFSET +CYFLD_UDB_PA_OE_SEL5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL5__SIZE +CYFLD_UDB_PA_OE_SEL5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL6__OFFSET +CYFLD_UDB_PA_OE_SEL6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL6__SIZE +CYFLD_UDB_PA_OE_SEL6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL7__OFFSET +CYFLD_UDB_PA_OE_SEL7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SEL7__SIZE +CYFLD_UDB_PA_OE_SEL7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 +CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA0_CFG14 +CYREG_UDB_PA0_CFG14 EQU 0x400f500e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC0__OFFSET +CYFLD_UDB_PA_OE_SYNC0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC0__SIZE +CYFLD_UDB_PA_OE_SYNC0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC1__OFFSET +CYFLD_UDB_PA_OE_SYNC1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC1__SIZE +CYFLD_UDB_PA_OE_SYNC1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC2__OFFSET +CYFLD_UDB_PA_OE_SYNC2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC2__SIZE +CYFLD_UDB_PA_OE_SYNC2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC3__OFFSET +CYFLD_UDB_PA_OE_SYNC3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_PA_OE_SYNC3__SIZE +CYFLD_UDB_PA_OE_SYNC3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT +CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC +CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 +CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 +CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA1_BASE +CYDEV_UDB_PA1_BASE EQU 0x400f5010 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA1_SIZE +CYDEV_UDB_PA1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG0 +CYREG_UDB_PA1_CFG0 EQU 0x400f5010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG1 +CYREG_UDB_PA1_CFG1 EQU 0x400f5011 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG2 +CYREG_UDB_PA1_CFG2 EQU 0x400f5012 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG3 +CYREG_UDB_PA1_CFG3 EQU 0x400f5013 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG4 +CYREG_UDB_PA1_CFG4 EQU 0x400f5014 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG5 +CYREG_UDB_PA1_CFG5 EQU 0x400f5015 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG6 +CYREG_UDB_PA1_CFG6 EQU 0x400f5016 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG7 +CYREG_UDB_PA1_CFG7 EQU 0x400f5017 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG8 +CYREG_UDB_PA1_CFG8 EQU 0x400f5018 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG9 +CYREG_UDB_PA1_CFG9 EQU 0x400f5019 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG10 +CYREG_UDB_PA1_CFG10 EQU 0x400f501a + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG11 +CYREG_UDB_PA1_CFG11 EQU 0x400f501b + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG12 +CYREG_UDB_PA1_CFG12 EQU 0x400f501c + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG13 +CYREG_UDB_PA1_CFG13 EQU 0x400f501d + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA1_CFG14 +CYREG_UDB_PA1_CFG14 EQU 0x400f501e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA2_BASE +CYDEV_UDB_PA2_BASE EQU 0x400f5020 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA2_SIZE +CYDEV_UDB_PA2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG0 +CYREG_UDB_PA2_CFG0 EQU 0x400f5020 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG1 +CYREG_UDB_PA2_CFG1 EQU 0x400f5021 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG2 +CYREG_UDB_PA2_CFG2 EQU 0x400f5022 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG3 +CYREG_UDB_PA2_CFG3 EQU 0x400f5023 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG4 +CYREG_UDB_PA2_CFG4 EQU 0x400f5024 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG5 +CYREG_UDB_PA2_CFG5 EQU 0x400f5025 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG6 +CYREG_UDB_PA2_CFG6 EQU 0x400f5026 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG7 +CYREG_UDB_PA2_CFG7 EQU 0x400f5027 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG8 +CYREG_UDB_PA2_CFG8 EQU 0x400f5028 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG9 +CYREG_UDB_PA2_CFG9 EQU 0x400f5029 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG10 +CYREG_UDB_PA2_CFG10 EQU 0x400f502a + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG11 +CYREG_UDB_PA2_CFG11 EQU 0x400f502b + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG12 +CYREG_UDB_PA2_CFG12 EQU 0x400f502c + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG13 +CYREG_UDB_PA2_CFG13 EQU 0x400f502d + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA2_CFG14 +CYREG_UDB_PA2_CFG14 EQU 0x400f502e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA3_BASE +CYDEV_UDB_PA3_BASE EQU 0x400f5030 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_PA3_SIZE +CYDEV_UDB_PA3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG0 +CYREG_UDB_PA3_CFG0 EQU 0x400f5030 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG1 +CYREG_UDB_PA3_CFG1 EQU 0x400f5031 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG2 +CYREG_UDB_PA3_CFG2 EQU 0x400f5032 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG3 +CYREG_UDB_PA3_CFG3 EQU 0x400f5033 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG4 +CYREG_UDB_PA3_CFG4 EQU 0x400f5034 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG5 +CYREG_UDB_PA3_CFG5 EQU 0x400f5035 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG6 +CYREG_UDB_PA3_CFG6 EQU 0x400f5036 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG7 +CYREG_UDB_PA3_CFG7 EQU 0x400f5037 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG8 +CYREG_UDB_PA3_CFG8 EQU 0x400f5038 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG9 +CYREG_UDB_PA3_CFG9 EQU 0x400f5039 + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG10 +CYREG_UDB_PA3_CFG10 EQU 0x400f503a + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG11 +CYREG_UDB_PA3_CFG11 EQU 0x400f503b + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG12 +CYREG_UDB_PA3_CFG12 EQU 0x400f503c + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG13 +CYREG_UDB_PA3_CFG13 EQU 0x400f503d + ENDIF + IF :LNOT::DEF:CYREG_UDB_PA3_CFG14 +CYREG_UDB_PA3_CFG14 EQU 0x400f503e + ENDIF + IF :LNOT::DEF:CYDEV_UDB_BCTL0_BASE +CYDEV_UDB_BCTL0_BASE EQU 0x400f6000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_BCTL0_SIZE +CYDEV_UDB_BCTL0_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_DRV +CYREG_UDB_BCTL0_DRV EQU 0x400f6000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DRV__OFFSET +CYFLD_UDB_BCTL0_DRV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DRV__SIZE +CYFLD_UDB_BCTL0_DRV__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DRV_DISABLE +CYVAL_UDB_BCTL0_DRV_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DRV_ENABLE +CYVAL_UDB_BCTL0_DRV_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_MDCLK_EN +CYREG_UDB_BCTL0_MDCLK_EN EQU 0x400f6001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN__OFFSET +CYFLD_UDB_BCTL0_DCEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN__SIZE +CYFLD_UDB_BCTL0_DCEN__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_DISABLE +CYVAL_UDB_BCTL0_DCEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_ENABLE +CYVAL_UDB_BCTL0_DCEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_MBCLK_EN +CYREG_UDB_BCTL0_MBCLK_EN EQU 0x400f6002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN__OFFSET +CYFLD_UDB_BCTL0_BCEN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN__SIZE +CYFLD_UDB_BCTL0_BCEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_DISABLE +CYVAL_UDB_BCTL0_BCEN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_ENABLE +CYVAL_UDB_BCTL0_BCEN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_BOTSEL_L +CYREG_UDB_BCTL0_BOTSEL_L EQU 0x400f6008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL0__SIZE +CYFLD_UDB_BCTL0_CLK_SEL0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL1__SIZE +CYFLD_UDB_BCTL0_CLK_SEL1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL2__SIZE +CYFLD_UDB_BCTL0_CLK_SEL2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL3__SIZE +CYFLD_UDB_BCTL0_CLK_SEL3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_BOTSEL_U +CYREG_UDB_BCTL0_BOTSEL_U EQU 0x400f6009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL4__SIZE +CYFLD_UDB_BCTL0_CLK_SEL4__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL5__SIZE +CYFLD_UDB_BCTL0_CLK_SEL5__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL6__SIZE +CYFLD_UDB_BCTL0_CLK_SEL6__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET +CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_CLK_SEL7__SIZE +CYFLD_UDB_BCTL0_CLK_SEL7__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES +CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT +CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT +CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_TOPSEL_L +CYREG_UDB_BCTL0_TOPSEL_L EQU 0x400f600a + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_TOPSEL_U +CYREG_UDB_BCTL0_TOPSEL_U EQU 0x400f600b + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_QCLK_EN0 +CYREG_UDB_BCTL0_QCLK_EN0 EQU 0x400f6010 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN_Q__OFFSET +CYFLD_UDB_BCTL0_DCEN_Q__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DCEN_Q__SIZE +CYFLD_UDB_BCTL0_DCEN_Q__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_Q_DISABLE +CYVAL_UDB_BCTL0_DCEN_Q_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DCEN_Q_ENABLE +CYVAL_UDB_BCTL0_DCEN_Q_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN_Q__OFFSET +CYFLD_UDB_BCTL0_BCEN_Q__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_BCEN_Q__SIZE +CYFLD_UDB_BCTL0_BCEN_Q__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_Q_DISABLE +CYVAL_UDB_BCTL0_BCEN_Q_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_BCEN_Q_ENABLE +CYVAL_UDB_BCTL0_BCEN_Q_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET +CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE +CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE +CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE +CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET +CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE +CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE +CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE +CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET +CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE +CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE +CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE +CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET +CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE +CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE +CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE +CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET +CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE +CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB +CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB +CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_NC0__OFFSET +CYFLD_UDB_BCTL0_NC0__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_NC0__SIZE +CYFLD_UDB_BCTL0_NC0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET +CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE +CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE +CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE +CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_BCTL0_QCLK_EN1 +CYREG_UDB_BCTL0_QCLK_EN1 EQU 0x400f6012 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_UDBIF_BASE +CYDEV_UDB_UDBIF_BASE EQU 0x400f7000 + ENDIF + IF :LNOT::DEF:CYDEV_UDB_UDBIF_SIZE +CYDEV_UDB_UDBIF_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_UDB_UDBIF_BANK_CTL +CYREG_UDB_UDBIF_BANK_CTL EQU 0x400f7000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_DIS_COR__OFFSET +CYFLD_UDB_UDBIF_DIS_COR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_DIS_COR__SIZE +CYFLD_UDB_UDBIF_DIS_COR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_DIS_COR_NORMAL +CYVAL_UDB_UDBIF_DIS_COR_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_DIS_COR_DISABLE +CYVAL_UDB_UDBIF_DIS_COR_DISABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET +CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_ROUTE_EN__SIZE +CYFLD_UDB_UDBIF_ROUTE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE +CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE +CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_BANK_EN__OFFSET +CYFLD_UDB_UDBIF_BANK_EN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_BANK_EN__SIZE +CYFLD_UDB_UDBIF_BANK_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_BANK_EN_DISABLE +CYVAL_UDB_UDBIF_BANK_EN_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_BANK_EN_ENABLE +CYVAL_UDB_UDBIF_BANK_EN_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_LOCK__OFFSET +CYFLD_UDB_UDBIF_LOCK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_LOCK__SIZE +CYFLD_UDB_UDBIF_LOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_LOCK_MUTABLE +CYVAL_UDB_UDBIF_LOCK_MUTABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_LOCK_LOCKED +CYVAL_UDB_UDBIF_LOCK_LOCKED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_PIPE__OFFSET +CYFLD_UDB_UDBIF_PIPE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_PIPE__SIZE +CYFLD_UDB_UDBIF_PIPE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_PIPE_BYPASS +CYVAL_UDB_UDBIF_PIPE_BYPASS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_PIPE_PIPELINED +CYVAL_UDB_UDBIF_PIPE_PIPELINED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_GLBL_WR__OFFSET +CYFLD_UDB_UDBIF_GLBL_WR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_GLBL_WR__SIZE +CYFLD_UDB_UDBIF_GLBL_WR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_GLBL_WR_DISABLE +CYVAL_UDB_UDBIF_GLBL_WR_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_GLBL_WR_ENABLE +CYVAL_UDB_UDBIF_GLBL_WR_ENABLE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_UDBIF_WAIT_CFG +CYREG_UDB_UDBIF_WAIT_CFG EQU 0x400f7001 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET +CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE +CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS +CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS +CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET +CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE +CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS +CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS +CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET +CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE +CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS +CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS +CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET +CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE +CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT +CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS +CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS +CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS +CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_UDB_UDBIF_INT_CLK_CTL +CYREG_UDB_UDBIF_INT_CLK_CTL EQU 0x400f701c + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET +CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_UDBIF_EN_HFCLK__SIZE +CYFLD_UDB_UDBIF_EN_HFCLK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_UDB_INT_CFG +CYREG_UDB_INT_CFG EQU 0x400f8000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_INT_MODE_CFG__OFFSET +CYFLD_UDB_INT_MODE_CFG__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_UDB_INT_MODE_CFG__SIZE +CYFLD_UDB_INT_MODE_CFG__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_INT_MODE_CFG_LEVEL +CYVAL_UDB_INT_MODE_CFG_LEVEL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_UDB_INT_MODE_CFG_PULSE +CYVAL_UDB_INT_MODE_CFG_PULSE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_CTBM_BASE +CYDEV_CTBM_BASE EQU 0x40100000 + ENDIF + IF :LNOT::DEF:CYDEV_CTBM_SIZE +CYDEV_CTBM_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_CTB_CTRL +CYREG_CTBM_CTB_CTRL EQU 0x40100000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_ENABLED__OFFSET +CYFLD_CTBM_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_ENABLED__SIZE +CYFLD_CTBM_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA_RES0_CTRL +CYREG_CTBM_OA_RES0_CTRL EQU 0x40100004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PWR_MODE__OFFSET +CYFLD_CTBM_OA0_PWR_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PWR_MODE__SIZE +CYFLD_CTBM_OA0_PWR_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET +CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE +CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_EN__OFFSET +CYFLD_CTBM_OA0_COMP_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_EN__SIZE +CYFLD_CTBM_OA0_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_HYST_EN__OFFSET +CYFLD_CTBM_OA0_HYST_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_HYST_EN__SIZE +CYFLD_CTBM_OA0_HYST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET +CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE +CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMPINT__OFFSET +CYFLD_CTBM_OA0_COMPINT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMPINT__SIZE +CYFLD_CTBM_OA0_COMPINT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_DISABLE +CYVAL_CTBM_OA0_COMPINT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_RISING +CYVAL_CTBM_OA0_COMPINT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_FALLING +CYVAL_CTBM_OA0_COMPINT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_BOTH +CYVAL_CTBM_OA0_COMPINT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PUMP_EN__OFFSET +CYFLD_CTBM_OA0_PUMP_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PUMP_EN__SIZE +CYFLD_CTBM_OA0_PUMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA_RES1_CTRL +CYREG_CTBM_OA_RES1_CTRL EQU 0x40100008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PWR_MODE__OFFSET +CYFLD_CTBM_OA1_PWR_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PWR_MODE__SIZE +CYFLD_CTBM_OA1_PWR_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET +CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE +CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_EN__OFFSET +CYFLD_CTBM_OA1_COMP_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_EN__SIZE +CYFLD_CTBM_OA1_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_HYST_EN__OFFSET +CYFLD_CTBM_OA1_HYST_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_HYST_EN__SIZE +CYFLD_CTBM_OA1_HYST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET +CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE +CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMPINT__OFFSET +CYFLD_CTBM_OA1_COMPINT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMPINT__SIZE +CYFLD_CTBM_OA1_COMPINT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_DISABLE +CYVAL_CTBM_OA1_COMPINT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_RISING +CYVAL_CTBM_OA1_COMPINT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_FALLING +CYVAL_CTBM_OA1_COMPINT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_BOTH +CYVAL_CTBM_OA1_COMPINT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PUMP_EN__OFFSET +CYFLD_CTBM_OA1_PUMP_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PUMP_EN__SIZE +CYFLD_CTBM_OA1_PUMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_COMP_STAT +CYREG_CTBM_COMP_STAT EQU 0x4010000c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP__OFFSET +CYFLD_CTBM_OA0_COMP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP__SIZE +CYFLD_CTBM_OA0_COMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP__OFFSET +CYFLD_CTBM_OA1_COMP__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP__SIZE +CYFLD_CTBM_OA1_COMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR +CYREG_CTBM_INTR EQU 0x40100020 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0__OFFSET +CYFLD_CTBM_COMP0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0__SIZE +CYFLD_CTBM_COMP0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1__OFFSET +CYFLD_CTBM_COMP1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1__SIZE +CYFLD_CTBM_COMP1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR_SET +CYREG_CTBM_INTR_SET EQU 0x40100024 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_SET__OFFSET +CYFLD_CTBM_COMP0_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_SET__SIZE +CYFLD_CTBM_COMP0_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_SET__OFFSET +CYFLD_CTBM_COMP1_SET__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_SET__SIZE +CYFLD_CTBM_COMP1_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR_MASK +CYREG_CTBM_INTR_MASK EQU 0x40100028 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASK__OFFSET +CYFLD_CTBM_COMP0_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASK__SIZE +CYFLD_CTBM_COMP0_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASK__OFFSET +CYFLD_CTBM_COMP1_MASK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASK__SIZE +CYFLD_CTBM_COMP1_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_INTR_MASKED +CYREG_CTBM_INTR_MASKED EQU 0x4010002c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASKED__OFFSET +CYFLD_CTBM_COMP0_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASKED__SIZE +CYFLD_CTBM_COMP0_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASKED__OFFSET +CYFLD_CTBM_COMP1_MASKED__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASKED__SIZE +CYFLD_CTBM_COMP1_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_DFT_CTRL +CYREG_CTBM_DFT_CTRL EQU 0x40100030 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_MODE__OFFSET +CYFLD_CTBM_DFT_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_MODE__SIZE +CYFLD_CTBM_DFT_MODE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_EN__OFFSET +CYFLD_CTBM_DFT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_EN__SIZE +CYFLD_CTBM_DFT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_SW +CYREG_CTBM_OA0_SW EQU 0x40100080 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A00__OFFSET +CYFLD_CTBM_OA0P_A00__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A00__SIZE +CYFLD_CTBM_OA0P_A00__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A20__OFFSET +CYFLD_CTBM_OA0P_A20__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A20__SIZE +CYFLD_CTBM_OA0P_A20__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A30__OFFSET +CYFLD_CTBM_OA0P_A30__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A30__SIZE +CYFLD_CTBM_OA0P_A30__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A11__OFFSET +CYFLD_CTBM_OA0M_A11__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A11__SIZE +CYFLD_CTBM_OA0M_A11__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A81__OFFSET +CYFLD_CTBM_OA0M_A81__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A81__SIZE +CYFLD_CTBM_OA0M_A81__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51__OFFSET +CYFLD_CTBM_OA0O_D51__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51__SIZE +CYFLD_CTBM_OA0O_D51__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D81__OFFSET +CYFLD_CTBM_OA0O_D81__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D81__SIZE +CYFLD_CTBM_OA0O_D81__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_SW_CLEAR +CYREG_CTBM_OA0_SW_CLEAR EQU 0x40100084 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_SW +CYREG_CTBM_OA1_SW EQU 0x40100088 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A03__OFFSET +CYFLD_CTBM_OA1P_A03__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A03__SIZE +CYFLD_CTBM_OA1P_A03__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A13__OFFSET +CYFLD_CTBM_OA1P_A13__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A13__SIZE +CYFLD_CTBM_OA1P_A13__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A43__OFFSET +CYFLD_CTBM_OA1P_A43__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A43__SIZE +CYFLD_CTBM_OA1P_A43__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A22__OFFSET +CYFLD_CTBM_OA1M_A22__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A22__SIZE +CYFLD_CTBM_OA1M_A22__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A82__OFFSET +CYFLD_CTBM_OA1M_A82__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A82__SIZE +CYFLD_CTBM_OA1M_A82__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52__OFFSET +CYFLD_CTBM_OA1O_D52__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52__SIZE +CYFLD_CTBM_OA1O_D52__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62__OFFSET +CYFLD_CTBM_OA1O_D62__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62__SIZE +CYFLD_CTBM_OA1O_D62__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D82__OFFSET +CYFLD_CTBM_OA1O_D82__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D82__SIZE +CYFLD_CTBM_OA1O_D82__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_SW_CLEAR +CYREG_CTBM_OA1_SW_CLEAR EQU 0x4010008c + ENDIF + IF :LNOT::DEF:CYREG_CTBM_CTB_SW_HW_CTRL +CYREG_CTBM_CTB_SW_HW_CTRL EQU 0x401000c0 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P2_HW_CTRL__OFFSET +CYFLD_CTBM_P2_HW_CTRL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P2_HW_CTRL__SIZE +CYFLD_CTBM_P2_HW_CTRL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P3_HW_CTRL__OFFSET +CYFLD_CTBM_P3_HW_CTRL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P3_HW_CTRL__SIZE +CYFLD_CTBM_P3_HW_CTRL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_CTB_SW_STATUS +CYREG_CTBM_CTB_SW_STATUS EQU 0x401000c4 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51_STAT__OFFSET +CYFLD_CTBM_OA0O_D51_STAT__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51_STAT__SIZE +CYFLD_CTBM_OA0O_D51_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52_STAT__OFFSET +CYFLD_CTBM_OA1O_D52_STAT__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52_STAT__SIZE +CYFLD_CTBM_OA1O_D52_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62_STAT__OFFSET +CYFLD_CTBM_OA1O_D62_STAT__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62_STAT__SIZE +CYFLD_CTBM_OA1O_D62_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_OFFSET_TRIM +CYREG_CTBM_OA0_OFFSET_TRIM EQU 0x40100f00 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM +CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM EQU 0x40100f04 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA0_COMP_TRIM +CYREG_CTBM_OA0_COMP_TRIM EQU 0x40100f08 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_TRIM__OFFSET +CYFLD_CTBM_OA0_COMP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_TRIM__SIZE +CYFLD_CTBM_OA0_COMP_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_OFFSET_TRIM +CYREG_CTBM_OA1_OFFSET_TRIM EQU 0x40100f0c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM +CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM EQU 0x40100f10 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM_OA1_COMP_TRIM +CYREG_CTBM_OA1_COMP_TRIM EQU 0x40100f14 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_TRIM__OFFSET +CYFLD_CTBM_OA1_COMP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_TRIM__SIZE +CYFLD_CTBM_OA1_COMP_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SAR_BASE +CYDEV_SAR_BASE EQU 0x401a0000 + ENDIF + IF :LNOT::DEF:CYDEV_SAR_SIZE +CYDEV_SAR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CTRL +CYREG_SAR_CTRL EQU 0x401a0000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_SEL__OFFSET +CYFLD_SAR_VREF_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_SEL__SIZE +CYFLD_SAR_VREF_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF0 +CYVAL_SAR_VREF_SEL_VREF0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF1 +CYVAL_SAR_VREF_SEL_VREF1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF2 +CYVAL_SAR_VREF_SEL_VREF2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF_AROUTE +CYVAL_SAR_VREF_SEL_VREF_AROUTE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VBGR +CYVAL_SAR_VREF_SEL_VBGR EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF_EXT +CYVAL_SAR_VREF_SEL_VREF_EXT EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VDDA_DIV_2 +CYVAL_SAR_VREF_SEL_VDDA_DIV_2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VDDA +CYVAL_SAR_VREF_SEL_VDDA EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET +CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_BYP_CAP_EN__SIZE +CYFLD_SAR_VREF_BYP_CAP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_NEG_SEL__OFFSET +CYFLD_SAR_NEG_SEL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_NEG_SEL__SIZE +CYFLD_SAR_NEG_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_VSSA_KELVIN +CYVAL_SAR_NEG_SEL_VSSA_KELVIN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_ART_VSSA +CYVAL_SAR_NEG_SEL_ART_VSSA EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P1 +CYVAL_SAR_NEG_SEL_P1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P3 +CYVAL_SAR_NEG_SEL_P3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P5 +CYVAL_SAR_NEG_SEL_P5 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P7 +CYVAL_SAR_NEG_SEL_P7 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_ACORE +CYVAL_SAR_NEG_SEL_ACORE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_VREF +CYVAL_SAR_NEG_SEL_VREF EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET +CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE +CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PWR_CTRL_VREF__OFFSET +CYFLD_SAR_PWR_CTRL_VREF__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PWR_CTRL_VREF__SIZE +CYFLD_SAR_PWR_CTRL_VREF__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR +CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR +CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR +CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR +CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SPARE__OFFSET +CYFLD_SAR_SPARE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SPARE__SIZE +CYFLD_SAR_SPARE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ICONT_LV__OFFSET +CYFLD_SAR_ICONT_LV__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ICONT_LV__SIZE +CYFLD_SAR_ICONT_LV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_NORMAL_PWR +CYVAL_SAR_ICONT_LV_NORMAL_PWR EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_HALF_PWR +CYVAL_SAR_ICONT_LV_HALF_PWR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_MORE_PWR +CYVAL_SAR_ICONT_LV_MORE_PWR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_QUARTER_PWR +CYVAL_SAR_ICONT_LV_QUARTER_PWR EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET +CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_CONFIG__SIZE +CYFLD_SAR_DSI_SYNC_CONFIG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_MODE__OFFSET +CYFLD_SAR_DSI_MODE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_MODE__SIZE +CYFLD_SAR_DSI_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SWITCH_DISABLE__OFFSET +CYFLD_SAR_SWITCH_DISABLE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SWITCH_DISABLE__SIZE +CYFLD_SAR_SWITCH_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ENABLED__OFFSET +CYFLD_SAR_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ENABLED__SIZE +CYFLD_SAR_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_CTRL +CYREG_SAR_SAMPLE_CTRL EQU 0x401a0004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SUB_RESOLUTION__OFFSET +CYFLD_SAR_SUB_RESOLUTION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SUB_RESOLUTION__SIZE +CYFLD_SAR_SUB_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SUB_RESOLUTION_8B +CYVAL_SAR_SUB_RESOLUTION_8B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SUB_RESOLUTION_10B +CYVAL_SAR_SUB_RESOLUTION_10B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_LEFT_ALIGN__OFFSET +CYFLD_SAR_LEFT_ALIGN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_LEFT_ALIGN__SIZE +CYFLD_SAR_LEFT_ALIGN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET +CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE +CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED +CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED +CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET +CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE +CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED +CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED +CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_CNT__OFFSET +CYFLD_SAR_AVG_CNT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_CNT__SIZE +CYFLD_SAR_AVG_CNT__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_SHIFT__OFFSET +CYFLD_SAR_AVG_SHIFT__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_SHIFT__SIZE +CYFLD_SAR_AVG_SHIFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CONTINUOUS__OFFSET +CYFLD_SAR_CONTINUOUS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CONTINUOUS__SIZE +CYFLD_SAR_CONTINUOUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_EN__OFFSET +CYFLD_SAR_DSI_TRIGGER_EN__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_EN__SIZE +CYFLD_SAR_DSI_TRIGGER_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET +CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE +CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET +CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE +CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET +CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_DSI_OUT_EN__SIZE +CYFLD_SAR_EOS_DSI_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_TIME01 +CYREG_SAR_SAMPLE_TIME01 EQU 0x401a0010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME0__OFFSET +CYFLD_SAR_SAMPLE_TIME0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME0__SIZE +CYFLD_SAR_SAMPLE_TIME0__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME1__OFFSET +CYFLD_SAR_SAMPLE_TIME1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME1__SIZE +CYFLD_SAR_SAMPLE_TIME1__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_TIME23 +CYREG_SAR_SAMPLE_TIME23 EQU 0x401a0014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME2__OFFSET +CYFLD_SAR_SAMPLE_TIME2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME2__SIZE +CYFLD_SAR_SAMPLE_TIME2__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME3__OFFSET +CYFLD_SAR_SAMPLE_TIME3__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME3__SIZE +CYFLD_SAR_SAMPLE_TIME3__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_THRES +CYREG_SAR_RANGE_THRES EQU 0x401a0018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_LOW__OFFSET +CYFLD_SAR_RANGE_LOW__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_LOW__SIZE +CYFLD_SAR_RANGE_LOW__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_HIGH__OFFSET +CYFLD_SAR_RANGE_HIGH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_HIGH__SIZE +CYFLD_SAR_RANGE_HIGH__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_COND +CYREG_SAR_RANGE_COND EQU 0x401a001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_COND__OFFSET +CYFLD_SAR_RANGE_COND__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_COND__SIZE +CYFLD_SAR_RANGE_COND__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_BELOW +CYVAL_SAR_RANGE_COND_BELOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_INSIDE +CYVAL_SAR_RANGE_COND_INSIDE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_ABOVE +CYVAL_SAR_RANGE_COND_ABOVE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_OUTSIDE +CYVAL_SAR_RANGE_COND_OUTSIDE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_EN +CYREG_SAR_CHAN_EN EQU 0x401a0020 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_EN__OFFSET +CYFLD_SAR_CHAN_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_EN__SIZE +CYFLD_SAR_CHAN_EN__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_START_CTRL +CYREG_SAR_START_CTRL EQU 0x401a0024 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_TRIGGER__OFFSET +CYFLD_SAR_FW_TRIGGER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_TRIGGER__SIZE +CYFLD_SAR_FW_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_DFT_CTRL +CYREG_SAR_DFT_CTRL EQU 0x401a0030 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DLY_INC__OFFSET +CYFLD_SAR_DLY_INC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DLY_INC__SIZE +CYFLD_SAR_DLY_INC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_HIZ__OFFSET +CYFLD_SAR_HIZ__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_HIZ__SIZE +CYFLD_SAR_HIZ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_INC__OFFSET +CYFLD_SAR_DFT_INC__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_INC__SIZE +CYFLD_SAR_DFT_INC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_OUTC__OFFSET +CYFLD_SAR_DFT_OUTC__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_OUTC__SIZE +CYFLD_SAR_DFT_OUTC__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SEL_CSEL_DFT__OFFSET +CYFLD_SAR_SEL_CSEL_DFT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SEL_CSEL_DFT__SIZE +CYFLD_SAR_SEL_CSEL_DFT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EN_CSEL_DFT__OFFSET +CYFLD_SAR_EN_CSEL_DFT__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EN_CSEL_DFT__SIZE +CYFLD_SAR_EN_CSEL_DFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DCEN__OFFSET +CYFLD_SAR_DCEN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DCEN__SIZE +CYFLD_SAR_DCEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ADFT_OVERRIDE__OFFSET +CYFLD_SAR_ADFT_OVERRIDE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ADFT_OVERRIDE__SIZE +CYFLD_SAR_ADFT_OVERRIDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG00 +CYREG_SAR_CHAN_CONFIG00 EQU 0x401a0080 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PIN_ADDR__OFFSET +CYFLD_SAR_PIN_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PIN_ADDR__SIZE +CYFLD_SAR_PIN_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PORT_ADDR__OFFSET +CYFLD_SAR_PORT_ADDR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PORT_ADDR__SIZE +CYFLD_SAR_PORT_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_SARMUX +CYVAL_SAR_PORT_ADDR_SARMUX EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB0 +CYVAL_SAR_PORT_ADDR_CTB0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB1 +CYVAL_SAR_PORT_ADDR_CTB1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB2 +CYVAL_SAR_PORT_ADDR_CTB2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB3 +CYVAL_SAR_PORT_ADDR_CTB3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_AROUTE_VIRT +CYVAL_SAR_PORT_ADDR_AROUTE_VIRT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_SARMUX_VIRT +CYVAL_SAR_PORT_ADDR_SARMUX_VIRT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_EN__OFFSET +CYFLD_SAR_DIFFERENTIAL_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_EN__SIZE +CYFLD_SAR_DIFFERENTIAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESOLUTION__OFFSET +CYFLD_SAR_RESOLUTION__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESOLUTION__SIZE +CYFLD_SAR_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RESOLUTION_12B +CYVAL_SAR_RESOLUTION_12B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RESOLUTION_SUBRES +CYVAL_SAR_RESOLUTION_SUBRES EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_EN__OFFSET +CYFLD_SAR_AVG_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_EN__SIZE +CYFLD_SAR_AVG_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET +CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME_SEL__SIZE +CYFLD_SAR_SAMPLE_TIME_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_OUT_EN__OFFSET +CYFLD_SAR_DSI_OUT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_OUT_EN__SIZE +CYFLD_SAR_DSI_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG01 +CYREG_SAR_CHAN_CONFIG01 EQU 0x401a0084 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG02 +CYREG_SAR_CHAN_CONFIG02 EQU 0x401a0088 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG03 +CYREG_SAR_CHAN_CONFIG03 EQU 0x401a008c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG04 +CYREG_SAR_CHAN_CONFIG04 EQU 0x401a0090 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG05 +CYREG_SAR_CHAN_CONFIG05 EQU 0x401a0094 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG06 +CYREG_SAR_CHAN_CONFIG06 EQU 0x401a0098 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG07 +CYREG_SAR_CHAN_CONFIG07 EQU 0x401a009c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK00 +CYREG_SAR_CHAN_WORK00 EQU 0x401a0100 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WORK__OFFSET +CYFLD_SAR_WORK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WORK__SIZE +CYFLD_SAR_WORK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET +CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE +CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK01 +CYREG_SAR_CHAN_WORK01 EQU 0x401a0104 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK02 +CYREG_SAR_CHAN_WORK02 EQU 0x401a0108 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK03 +CYREG_SAR_CHAN_WORK03 EQU 0x401a010c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK04 +CYREG_SAR_CHAN_WORK04 EQU 0x401a0110 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK05 +CYREG_SAR_CHAN_WORK05 EQU 0x401a0114 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK06 +CYREG_SAR_CHAN_WORK06 EQU 0x401a0118 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK07 +CYREG_SAR_CHAN_WORK07 EQU 0x401a011c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT00 +CYREG_SAR_CHAN_RESULT00 EQU 0x401a0180 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESULT__OFFSET +CYFLD_SAR_RESULT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESULT__SIZE +CYFLD_SAR_RESULT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR_MIR__OFFSET +CYFLD_SAR_SATURATE_INTR_MIR__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR_MIR__SIZE +CYFLD_SAR_SATURATE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR_MIR__OFFSET +CYFLD_SAR_RANGE_INTR_MIR__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR_MIR__SIZE +CYFLD_SAR_RANGE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET +CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE +CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT01 +CYREG_SAR_CHAN_RESULT01 EQU 0x401a0184 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT02 +CYREG_SAR_CHAN_RESULT02 EQU 0x401a0188 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT03 +CYREG_SAR_CHAN_RESULT03 EQU 0x401a018c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT04 +CYREG_SAR_CHAN_RESULT04 EQU 0x401a0190 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT05 +CYREG_SAR_CHAN_RESULT05 EQU 0x401a0194 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT06 +CYREG_SAR_CHAN_RESULT06 EQU 0x401a0198 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT07 +CYREG_SAR_CHAN_RESULT07 EQU 0x401a019c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK_VALID +CYREG_SAR_CHAN_WORK_VALID EQU 0x401a0200 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID__OFFSET +CYFLD_SAR_CHAN_WORK_VALID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID__SIZE +CYFLD_SAR_CHAN_WORK_VALID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT_VALID +CYREG_SAR_CHAN_RESULT_VALID EQU 0x401a0204 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID__OFFSET +CYFLD_SAR_CHAN_RESULT_VALID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID__SIZE +CYFLD_SAR_CHAN_RESULT_VALID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_STATUS +CYREG_SAR_STATUS EQU 0x401a0208 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_CHAN__OFFSET +CYFLD_SAR_CUR_CHAN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_CHAN__SIZE +CYFLD_SAR_CUR_CHAN__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SW_VREF_NEG__OFFSET +CYFLD_SAR_SW_VREF_NEG__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SW_VREF_NEG__SIZE +CYFLD_SAR_SW_VREF_NEG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BUSY__OFFSET +CYFLD_SAR_BUSY__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BUSY__SIZE +CYFLD_SAR_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_AVG_STAT +CYREG_SAR_AVG_STAT EQU 0x401a020c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_ACCU__OFFSET +CYFLD_SAR_CUR_AVG_ACCU__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_ACCU__SIZE +CYFLD_SAR_CUR_AVG_ACCU__SIZE EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_CNT__OFFSET +CYFLD_SAR_CUR_AVG_CNT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_CNT__SIZE +CYFLD_SAR_CUR_AVG_CNT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR +CYREG_SAR_INTR EQU 0x401a0210 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_INTR__OFFSET +CYFLD_SAR_EOS_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_INTR__SIZE +CYFLD_SAR_EOS_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_INTR__OFFSET +CYFLD_SAR_OVERFLOW_INTR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_INTR__SIZE +CYFLD_SAR_OVERFLOW_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_INTR__OFFSET +CYFLD_SAR_FW_COLLISION_INTR__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_INTR__SIZE +CYFLD_SAR_FW_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_INTR__OFFSET +CYFLD_SAR_DSI_COLLISION_INTR__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_INTR__SIZE +CYFLD_SAR_DSI_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR__OFFSET +CYFLD_SAR_INJ_EOC_INTR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR__SIZE +CYFLD_SAR_INJ_EOC_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR__OFFSET +CYFLD_SAR_INJ_SATURATE_INTR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR__SIZE +CYFLD_SAR_INJ_SATURATE_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR__OFFSET +CYFLD_SAR_INJ_RANGE_INTR__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR__SIZE +CYFLD_SAR_INJ_RANGE_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR__OFFSET +CYFLD_SAR_INJ_COLLISION_INTR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR__SIZE +CYFLD_SAR_INJ_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_SET +CYREG_SAR_INTR_SET EQU 0x401a0214 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_SET__OFFSET +CYFLD_SAR_EOS_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_SET__SIZE +CYFLD_SAR_EOS_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_SET__OFFSET +CYFLD_SAR_OVERFLOW_SET__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_SET__SIZE +CYFLD_SAR_OVERFLOW_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_SET__OFFSET +CYFLD_SAR_FW_COLLISION_SET__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_SET__SIZE +CYFLD_SAR_FW_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_SET__OFFSET +CYFLD_SAR_DSI_COLLISION_SET__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_SET__SIZE +CYFLD_SAR_DSI_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_SET__OFFSET +CYFLD_SAR_INJ_EOC_SET__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_SET__SIZE +CYFLD_SAR_INJ_EOC_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_SET__OFFSET +CYFLD_SAR_INJ_SATURATE_SET__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_SET__SIZE +CYFLD_SAR_INJ_SATURATE_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_SET__OFFSET +CYFLD_SAR_INJ_RANGE_SET__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_SET__SIZE +CYFLD_SAR_INJ_RANGE_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_SET__OFFSET +CYFLD_SAR_INJ_COLLISION_SET__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_SET__SIZE +CYFLD_SAR_INJ_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_MASK +CYREG_SAR_INTR_MASK EQU 0x401a0218 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASK__OFFSET +CYFLD_SAR_EOS_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASK__SIZE +CYFLD_SAR_EOS_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASK__OFFSET +CYFLD_SAR_OVERFLOW_MASK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASK__SIZE +CYFLD_SAR_OVERFLOW_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASK__OFFSET +CYFLD_SAR_FW_COLLISION_MASK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASK__SIZE +CYFLD_SAR_FW_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASK__OFFSET +CYFLD_SAR_DSI_COLLISION_MASK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASK__SIZE +CYFLD_SAR_DSI_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASK__OFFSET +CYFLD_SAR_INJ_EOC_MASK__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASK__SIZE +CYFLD_SAR_INJ_EOC_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASK__OFFSET +CYFLD_SAR_INJ_SATURATE_MASK__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASK__SIZE +CYFLD_SAR_INJ_SATURATE_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASK__OFFSET +CYFLD_SAR_INJ_RANGE_MASK__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASK__SIZE +CYFLD_SAR_INJ_RANGE_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASK__OFFSET +CYFLD_SAR_INJ_COLLISION_MASK__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASK__SIZE +CYFLD_SAR_INJ_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_MASKED +CYREG_SAR_INTR_MASKED EQU 0x401a021c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED__OFFSET +CYFLD_SAR_EOS_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED__SIZE +CYFLD_SAR_EOS_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED__OFFSET +CYFLD_SAR_OVERFLOW_MASKED__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED__SIZE +CYFLD_SAR_OVERFLOW_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED__OFFSET +CYFLD_SAR_FW_COLLISION_MASKED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED__SIZE +CYFLD_SAR_FW_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET +CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED__SIZE +CYFLD_SAR_DSI_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED__OFFSET +CYFLD_SAR_INJ_EOC_MASKED__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED__SIZE +CYFLD_SAR_INJ_EOC_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET +CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED__SIZE +CYFLD_SAR_INJ_SATURATE_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED__OFFSET +CYFLD_SAR_INJ_RANGE_MASKED__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED__SIZE +CYFLD_SAR_INJ_RANGE_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET +CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED__SIZE +CYFLD_SAR_INJ_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR +CYREG_SAR_SATURATE_INTR EQU 0x401a0220 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR__OFFSET +CYFLD_SAR_SATURATE_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR__SIZE +CYFLD_SAR_SATURATE_INTR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_SET +CYREG_SAR_SATURATE_INTR_SET EQU 0x401a0224 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_SET__OFFSET +CYFLD_SAR_SATURATE_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_SET__SIZE +CYFLD_SAR_SATURATE_SET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_MASK +CYREG_SAR_SATURATE_INTR_MASK EQU 0x401a0228 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASK__OFFSET +CYFLD_SAR_SATURATE_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASK__SIZE +CYFLD_SAR_SATURATE_MASK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_MASKED +CYREG_SAR_SATURATE_INTR_MASKED EQU 0x401a022c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED__OFFSET +CYFLD_SAR_SATURATE_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED__SIZE +CYFLD_SAR_SATURATE_MASKED__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR +CYREG_SAR_RANGE_INTR EQU 0x401a0230 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR__OFFSET +CYFLD_SAR_RANGE_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR__SIZE +CYFLD_SAR_RANGE_INTR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_SET +CYREG_SAR_RANGE_INTR_SET EQU 0x401a0234 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_SET__OFFSET +CYFLD_SAR_RANGE_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_SET__SIZE +CYFLD_SAR_RANGE_SET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_MASK +CYREG_SAR_RANGE_INTR_MASK EQU 0x401a0238 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASK__OFFSET +CYFLD_SAR_RANGE_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASK__SIZE +CYFLD_SAR_RANGE_MASK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_MASKED +CYREG_SAR_RANGE_INTR_MASKED EQU 0x401a023c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED__OFFSET +CYFLD_SAR_RANGE_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED__SIZE +CYFLD_SAR_RANGE_MASKED__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_CAUSE +CYREG_SAR_INTR_CAUSE EQU 0x401a0240 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED_MIR__OFFSET +CYFLD_SAR_EOS_MASKED_MIR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED_MIR__SIZE +CYFLD_SAR_EOS_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET +CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE +CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE +CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE +CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE +CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED_RED__OFFSET +CYFLD_SAR_SATURATE_MASKED_RED__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED_RED__SIZE +CYFLD_SAR_SATURATE_MASKED_RED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED_RED__OFFSET +CYFLD_SAR_RANGE_MASKED_RED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED_RED__SIZE +CYFLD_SAR_RANGE_MASKED_RED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INJ_CHAN_CONFIG +CYREG_SAR_INJ_CHAN_CONFIG EQU 0x401a0280 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PIN_ADDR__OFFSET +CYFLD_SAR_INJ_PIN_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PIN_ADDR__SIZE +CYFLD_SAR_INJ_PIN_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PORT_ADDR__OFFSET +CYFLD_SAR_INJ_PORT_ADDR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PORT_ADDR__SIZE +CYFLD_SAR_INJ_PORT_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_SARMUX +CYVAL_SAR_INJ_PORT_ADDR_SARMUX EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB0 +CYVAL_SAR_INJ_PORT_ADDR_CTB0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB1 +CYVAL_SAR_INJ_PORT_ADDR_CTB1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB2 +CYVAL_SAR_INJ_PORT_ADDR_CTB2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB3 +CYVAL_SAR_INJ_PORT_ADDR_CTB3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT +CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT +CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET +CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE +CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESOLUTION__OFFSET +CYFLD_SAR_INJ_RESOLUTION__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESOLUTION__SIZE +CYFLD_SAR_INJ_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_RESOLUTION_12B +CYVAL_SAR_INJ_RESOLUTION_12B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_RESOLUTION_SUBRES +CYVAL_SAR_INJ_RESOLUTION_SUBRES EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_AVG_EN__OFFSET +CYFLD_SAR_INJ_AVG_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_AVG_EN__SIZE +CYFLD_SAR_INJ_AVG_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET +CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE +CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_TAILGATING__OFFSET +CYFLD_SAR_INJ_TAILGATING__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_TAILGATING__SIZE +CYFLD_SAR_INJ_TAILGATING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_START_EN__OFFSET +CYFLD_SAR_INJ_START_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_START_EN__SIZE +CYFLD_SAR_INJ_START_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INJ_RESULT +CYREG_SAR_INJ_RESULT EQU 0x401a0290 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESULT__OFFSET +CYFLD_SAR_INJ_RESULT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESULT__SIZE +CYFLD_SAR_INJ_RESULT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET +CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE +CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET +CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE +CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET +CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE +CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET +CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE +CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH0 +CYREG_SAR_MUX_SWITCH0 EQU 0x401a0300 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE +CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE +CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET +CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE +CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET +CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE +CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET +CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE +CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET +CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE +CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_CLEAR0 +CYREG_SAR_MUX_SWITCH_CLEAR0 EQU 0x401a0304 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH1 +CYREG_SAR_MUX_SWITCH1 EQU 0x401a0308 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET +CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE +CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET +CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE +CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET +CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE +CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET +CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE +CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_CLEAR1 +CYREG_SAR_MUX_SWITCH_CLEAR1 EQU 0x401a030c + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_HW_CTRL +CYREG_SAR_MUX_SWITCH_HW_CTRL EQU 0x401a0340 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P0__SIZE +CYFLD_SAR_MUX_HW_CTRL_P0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P1__SIZE +CYFLD_SAR_MUX_HW_CTRL_P1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P2__SIZE +CYFLD_SAR_MUX_HW_CTRL_P2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P3__SIZE +CYFLD_SAR_MUX_HW_CTRL_P3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P4__SIZE +CYFLD_SAR_MUX_HW_CTRL_P4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P5__SIZE +CYFLD_SAR_MUX_HW_CTRL_P5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P6__SIZE +CYFLD_SAR_MUX_HW_CTRL_P6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P7__SIZE +CYFLD_SAR_MUX_HW_CTRL_P7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET +CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE +CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET +CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE +CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET +CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE +CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET +CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE +CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_STATUS +CYREG_SAR_MUX_SWITCH_STATUS EQU 0x401a0348 + ENDIF + IF :LNOT::DEF:CYREG_SAR_PUMP_CTRL +CYREG_SAR_PUMP_CTRL EQU 0x401a0380 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CLOCK_SEL__OFFSET +CYFLD_SAR_CLOCK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CLOCK_SEL__SIZE +CYFLD_SAR_CLOCK_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_ANA_TRIM +CYREG_SAR_ANA_TRIM EQU 0x401a0f00 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CAP_TRIM__OFFSET +CYFLD_SAR_CAP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CAP_TRIM__SIZE +CYFLD_SAR_CAP_TRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_TRIMUNIT__OFFSET +CYFLD_SAR_TRIMUNIT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_TRIMUNIT__SIZE +CYFLD_SAR_TRIMUNIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_WOUNDING +CYREG_SAR_WOUNDING EQU 0x401a0f04 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WOUND_RESOLUTION__OFFSET +CYFLD_SAR_WOUND_RESOLUTION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WOUND_RESOLUTION__SIZE +CYFLD_SAR_WOUND_RESOLUTION__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_12BIT +CYVAL_SAR_WOUND_RESOLUTION_12BIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_10BIT +CYVAL_SAR_WOUND_RESOLUTION_10BIT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_8BIT +CYVAL_SAR_WOUND_RESOLUTION_8BIT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO +CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CM0_BASE +CYDEV_CM0_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_CM0_SIZE +CYDEV_CM0_SIZE EQU 0x00100000 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID4 +CYREG_CM0_DWT_PID4 EQU 0xe0001fd0 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VALUE__OFFSET +CYFLD_CM0_VALUE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VALUE__SIZE +CYFLD_CM0_VALUE__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID0 +CYREG_CM0_DWT_PID0 EQU 0xe0001fe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID1 +CYREG_CM0_DWT_PID1 EQU 0xe0001fe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID2 +CYREG_CM0_DWT_PID2 EQU 0xe0001fe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_PID3 +CYREG_CM0_DWT_PID3 EQU 0xe0001fec + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID0 +CYREG_CM0_DWT_CID0 EQU 0xe0001ff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID1 +CYREG_CM0_DWT_CID1 EQU 0xe0001ff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID2 +CYREG_CM0_DWT_CID2 EQU 0xe0001ff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_DWT_CID3 +CYREG_CM0_DWT_CID3 EQU 0xe0001ffc + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID4 +CYREG_CM0_BP_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID0 +CYREG_CM0_BP_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID1 +CYREG_CM0_BP_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID2 +CYREG_CM0_BP_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_PID3 +CYREG_CM0_BP_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID0 +CYREG_CM0_BP_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID1 +CYREG_CM0_BP_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID2 +CYREG_CM0_BP_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_BP_CID3 +CYREG_CM0_BP_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_CSR +CYREG_CM0_SYST_CSR EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENABLE__OFFSET +CYFLD_CM0_ENABLE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENABLE__SIZE +CYFLD_CM0_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TICKINT__OFFSET +CYFLD_CM0_TICKINT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TICKINT__SIZE +CYFLD_CM0_TICKINT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLKSOURCE__OFFSET +CYFLD_CM0_CLKSOURCE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLKSOURCE__SIZE +CYFLD_CM0_CLKSOURCE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_COUNTFLAG__OFFSET +CYFLD_CM0_COUNTFLAG__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_COUNTFLAG__SIZE +CYFLD_CM0_COUNTFLAG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_RVR +CYREG_CM0_SYST_RVR EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_RELOAD__OFFSET +CYFLD_CM0_RELOAD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_RELOAD__SIZE +CYFLD_CM0_RELOAD__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_CVR +CYREG_CM0_SYST_CVR EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CURRENT__OFFSET +CYFLD_CM0_CURRENT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CURRENT__SIZE +CYFLD_CM0_CURRENT__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SYST_CALIB +CYREG_CM0_SYST_CALIB EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TENMS__OFFSET +CYFLD_CM0_TENMS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_TENMS__SIZE +CYFLD_CM0_TENMS__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SKEW__OFFSET +CYFLD_CM0_SKEW__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SKEW__SIZE +CYFLD_CM0_SKEW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NOREF__OFFSET +CYFLD_CM0_NOREF__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NOREF__SIZE +CYFLD_CM0_NOREF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ISER +CYREG_CM0_ISER EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETENA__OFFSET +CYFLD_CM0_SETENA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETENA__SIZE +CYFLD_CM0_SETENA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ICER +CYREG_CM0_ICER EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRENA__OFFSET +CYFLD_CM0_CLRENA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRENA__SIZE +CYFLD_CM0_CLRENA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ISPR +CYREG_CM0_ISPR EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETPEND__OFFSET +CYFLD_CM0_SETPEND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SETPEND__SIZE +CYFLD_CM0_SETPEND__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ICPR +CYREG_CM0_ICPR EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRPEND__OFFSET +CYFLD_CM0_CLRPEND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CLRPEND__SIZE +CYFLD_CM0_CLRPEND__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR0 +CYREG_CM0_IPR0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N0__OFFSET +CYFLD_CM0_PRI_N0__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N0__SIZE +CYFLD_CM0_PRI_N0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N1__OFFSET +CYFLD_CM0_PRI_N1__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N1__SIZE +CYFLD_CM0_PRI_N1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N2__OFFSET +CYFLD_CM0_PRI_N2__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N2__SIZE +CYFLD_CM0_PRI_N2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N3__OFFSET +CYFLD_CM0_PRI_N3__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_N3__SIZE +CYFLD_CM0_PRI_N3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR1 +CYREG_CM0_IPR1 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR2 +CYREG_CM0_IPR2 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR3 +CYREG_CM0_IPR3 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR4 +CYREG_CM0_IPR4 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR5 +CYREG_CM0_IPR5 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR6 +CYREG_CM0_IPR6 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_CM0_IPR7 +CYREG_CM0_IPR7 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_CM0_CPUID +CYREG_CM0_CPUID EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_REVISION__OFFSET +CYFLD_CM0_REVISION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_REVISION__SIZE +CYFLD_CM0_REVISION__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PARTNO__OFFSET +CYFLD_CM0_PARTNO__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PARTNO__SIZE +CYFLD_CM0_PARTNO__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CONSTANT__OFFSET +CYFLD_CM0_CONSTANT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_CONSTANT__SIZE +CYFLD_CM0_CONSTANT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VARIANT__OFFSET +CYFLD_CM0_VARIANT__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VARIANT__SIZE +CYFLD_CM0_VARIANT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_IMPLEMENTER__OFFSET +CYFLD_CM0_IMPLEMENTER__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_IMPLEMENTER__SIZE +CYFLD_CM0_IMPLEMENTER__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ICSR +CYREG_CM0_ICSR EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTACTIVE__OFFSET +CYFLD_CM0_VECTACTIVE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTACTIVE__SIZE +CYFLD_CM0_VECTACTIVE__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTPENDING__OFFSET +CYFLD_CM0_VECTPENDING__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTPENDING__SIZE +CYFLD_CM0_VECTPENDING__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPENDING__OFFSET +CYFLD_CM0_ISRPENDING__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPENDING__SIZE +CYFLD_CM0_ISRPENDING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPREEMPT__OFFSET +CYFLD_CM0_ISRPREEMPT__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ISRPREEMPT__SIZE +CYFLD_CM0_ISRPREEMPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTCLR__OFFSET +CYFLD_CM0_PENDSTCLR__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTCLR__SIZE +CYFLD_CM0_PENDSTCLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTSETb__OFFSET +CYFLD_CM0_PENDSTSETb__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSTSETb__SIZE +CYFLD_CM0_PENDSTSETb__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVCLR__OFFSET +CYFLD_CM0_PENDSVCLR__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVCLR__SIZE +CYFLD_CM0_PENDSVCLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVSET__OFFSET +CYFLD_CM0_PENDSVSET__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PENDSVSET__SIZE +CYFLD_CM0_PENDSVSET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NMIPENDSET__OFFSET +CYFLD_CM0_NMIPENDSET__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_NMIPENDSET__SIZE +CYFLD_CM0_NMIPENDSET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_AIRCR +CYREG_CM0_AIRCR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTCLRACTIVE__OFFSET +CYFLD_CM0_VECTCLRACTIVE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTCLRACTIVE__SIZE +CYFLD_CM0_VECTCLRACTIVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SYSRESETREQ__OFFSET +CYFLD_CM0_SYSRESETREQ__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SYSRESETREQ__SIZE +CYFLD_CM0_SYSRESETREQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENDIANNESS__OFFSET +CYFLD_CM0_ENDIANNESS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_ENDIANNESS__SIZE +CYFLD_CM0_ENDIANNESS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTKEY__OFFSET +CYFLD_CM0_VECTKEY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_VECTKEY__SIZE +CYFLD_CM0_VECTKEY__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCR +CYREG_CM0_SCR EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPONEXIT__OFFSET +CYFLD_CM0_SLEEPONEXIT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPONEXIT__SIZE +CYFLD_CM0_SLEEPONEXIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPDEEP__OFFSET +CYFLD_CM0_SLEEPDEEP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SLEEPDEEP__SIZE +CYFLD_CM0_SLEEPDEEP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SEVONPEND__OFFSET +CYFLD_CM0_SEVONPEND__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SEVONPEND__SIZE +CYFLD_CM0_SEVONPEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_CCR +CYREG_CM0_CCR EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_UNALIGN_TRP__OFFSET +CYFLD_CM0_UNALIGN_TRP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_UNALIGN_TRP__SIZE +CYFLD_CM0_UNALIGN_TRP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_STKALIGN__OFFSET +CYFLD_CM0_STKALIGN__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_STKALIGN__SIZE +CYFLD_CM0_STKALIGN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SHPR2 +CYREG_CM0_SHPR2 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_11__OFFSET +CYFLD_CM0_PRI_11__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_11__SIZE +CYFLD_CM0_PRI_11__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SHPR3 +CYREG_CM0_SHPR3 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_14__OFFSET +CYFLD_CM0_PRI_14__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_14__SIZE +CYFLD_CM0_PRI_14__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_15__OFFSET +CYFLD_CM0_PRI_15__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0_PRI_15__SIZE +CYFLD_CM0_PRI_15__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SHCSR +CYREG_CM0_SHCSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SVCALLPENDED__OFFSET +CYFLD_CM0_SVCALLPENDED__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CM0_SVCALLPENDED__SIZE +CYFLD_CM0_SVCALLPENDED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID4 +CYREG_CM0_SCS_PID4 EQU 0xe000efd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID0 +CYREG_CM0_SCS_PID0 EQU 0xe000efe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID1 +CYREG_CM0_SCS_PID1 EQU 0xe000efe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID2 +CYREG_CM0_SCS_PID2 EQU 0xe000efe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_PID3 +CYREG_CM0_SCS_PID3 EQU 0xe000efec + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID0 +CYREG_CM0_SCS_CID0 EQU 0xe000eff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID1 +CYREG_CM0_SCS_CID1 EQU 0xe000eff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID2 +CYREG_CM0_SCS_CID2 EQU 0xe000eff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_SCS_CID3 +CYREG_CM0_SCS_CID3 EQU 0xe000effc + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_SCS +CYREG_CM0_ROM_SCS EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_DWT +CYREG_CM0_ROM_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_BPU +CYREG_CM0_ROM_BPU EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_END +CYREG_CM0_ROM_END EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CSMT +CYREG_CM0_ROM_CSMT EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID4 +CYREG_CM0_ROM_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID0 +CYREG_CM0_ROM_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID1 +CYREG_CM0_ROM_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID2 +CYREG_CM0_ROM_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_PID3 +CYREG_CM0_ROM_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID0 +CYREG_CM0_ROM_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID1 +CYREG_CM0_ROM_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID2 +CYREG_CM0_ROM_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0_ROM_CID3 +CYREG_CM0_ROM_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_CoreSightTable_BASE +CYDEV_CoreSightTable_BASE EQU 0xf0000000 + ENDIF + IF :LNOT::DEF:CYDEV_CoreSightTable_SIZE +CYDEV_CoreSightTable_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_CoreSightTable_DATA_MBASE +CYREG_CoreSightTable_DATA_MBASE EQU 0xf0000000 + ENDIF + IF :LNOT::DEF:CYREG_CoreSightTable_DATA_MSIZE +CYREG_CoreSightTable_DATA_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000080 + ENDIF + END diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cydisabledsheets.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydisabledsheets.h new file mode 100644 index 0000000..8178873 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter.h new file mode 100644 index 0000000..91fb364 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter.h @@ -0,0 +1,502 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include "cydevice_trm.h" + +/* ADC */ +#define ADC_cy_psoc4_sar__SAR_ANA_TRIM CYREG_SAR_ANA_TRIM +#define ADC_cy_psoc4_sar__SAR_AVG_STAT CYREG_SAR_AVG_STAT +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 CYREG_SAR_CHAN_CONFIG00 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 CYREG_SAR_CHAN_CONFIG01 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 CYREG_SAR_CHAN_CONFIG02 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 CYREG_SAR_CHAN_CONFIG03 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 CYREG_SAR_CHAN_CONFIG04 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 CYREG_SAR_CHAN_CONFIG05 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 CYREG_SAR_CHAN_CONFIG06 +#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 CYREG_SAR_CHAN_CONFIG07 +#define ADC_cy_psoc4_sar__SAR_CHAN_EN CYREG_SAR_CHAN_EN +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID CYREG_SAR_CHAN_RESULT_VALID +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 CYREG_SAR_CHAN_RESULT00 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 CYREG_SAR_CHAN_RESULT01 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 CYREG_SAR_CHAN_RESULT02 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 CYREG_SAR_CHAN_RESULT03 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 CYREG_SAR_CHAN_RESULT04 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 CYREG_SAR_CHAN_RESULT05 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 CYREG_SAR_CHAN_RESULT06 +#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 CYREG_SAR_CHAN_RESULT07 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID CYREG_SAR_CHAN_WORK_VALID +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK00 CYREG_SAR_CHAN_WORK00 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK01 CYREG_SAR_CHAN_WORK01 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK02 CYREG_SAR_CHAN_WORK02 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK03 CYREG_SAR_CHAN_WORK03 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK04 CYREG_SAR_CHAN_WORK04 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK05 CYREG_SAR_CHAN_WORK05 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK06 CYREG_SAR_CHAN_WORK06 +#define ADC_cy_psoc4_sar__SAR_CHAN_WORK07 CYREG_SAR_CHAN_WORK07 +#define ADC_cy_psoc4_sar__SAR_CTRL CYREG_SAR_CTRL +#define ADC_cy_psoc4_sar__SAR_DFT_CTRL CYREG_SAR_DFT_CTRL +#define ADC_cy_psoc4_sar__SAR_INTR CYREG_SAR_INTR +#define ADC_cy_psoc4_sar__SAR_INTR_CAUSE CYREG_SAR_INTR_CAUSE +#define ADC_cy_psoc4_sar__SAR_INTR_MASK CYREG_SAR_INTR_MASK +#define ADC_cy_psoc4_sar__SAR_INTR_MASKED CYREG_SAR_INTR_MASKED +#define ADC_cy_psoc4_sar__SAR_INTR_SET CYREG_SAR_INTR_SET +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0 CYREG_SAR_MUX_SWITCH_CLEAR0 +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1 CYREG_SAR_MUX_SWITCH_CLEAR1 +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL CYREG_SAR_MUX_SWITCH_HW_CTRL +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS CYREG_SAR_MUX_SWITCH_STATUS +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 CYREG_SAR_MUX_SWITCH0 +#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH1 CYREG_SAR_MUX_SWITCH1 +#define ADC_cy_psoc4_sar__SAR_NUMBER 0u +#define ADC_cy_psoc4_sar__SAR_PUMP_CTRL CYREG_SAR_PUMP_CTRL +#define ADC_cy_psoc4_sar__SAR_RANGE_COND CYREG_SAR_RANGE_COND +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR CYREG_SAR_RANGE_INTR +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK CYREG_SAR_RANGE_INTR_MASK +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED CYREG_SAR_RANGE_INTR_MASKED +#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET CYREG_SAR_RANGE_INTR_SET +#define ADC_cy_psoc4_sar__SAR_RANGE_THRES CYREG_SAR_RANGE_THRES +#define ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL CYREG_SAR_SAMPLE_CTRL +#define ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 CYREG_SAR_SAMPLE_TIME01 +#define ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 CYREG_SAR_SAMPLE_TIME23 +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR CYREG_SAR_SATURATE_INTR +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK CYREG_SAR_SATURATE_INTR_MASK +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED CYREG_SAR_SATURATE_INTR_MASKED +#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET CYREG_SAR_SATURATE_INTR_SET +#define ADC_cy_psoc4_sar__SAR_START_CTRL CYREG_SAR_START_CTRL +#define ADC_cy_psoc4_sar__SAR_STATUS CYREG_SAR_STATUS +#define ADC_cy_psoc4_sar__SAR_WOUNDING CYREG_SAR_WOUNDING +#define ADC_intClock__DIVIDER_MASK 0x0000FFFFu +#define ADC_intClock__ENABLE CYREG_CLK_DIVIDER_A00 +#define ADC_intClock__ENABLE_MASK 0x80000000u +#define ADC_intClock__MASK 0x80000000u +#define ADC_intClock__REGISTER CYREG_CLK_DIVIDER_A00 +#define ADC_IRQ__INTC_CLR_EN_REG CYREG_CM0_ICER +#define ADC_IRQ__INTC_CLR_PD_REG CYREG_CM0_ICPR +#define ADC_IRQ__INTC_MASK 0x4000u +#define ADC_IRQ__INTC_NUMBER 14u +#define ADC_IRQ__INTC_PRIOR_MASK 0xC00000u +#define ADC_IRQ__INTC_PRIOR_NUM 3u +#define ADC_IRQ__INTC_PRIOR_REG CYREG_CM0_IPR3 +#define ADC_IRQ__INTC_SET_EN_REG CYREG_CM0_ISER +#define ADC_IRQ__INTC_SET_PD_REG CYREG_CM0_ISPR + +/* LED */ +#define LED__0__DM__MASK 0x1C0000u +#define LED__0__DM__SHIFT 18u +#define LED__0__DR CYREG_PRT1_DR +#define LED__0__HSIOM CYREG_HSIOM_PORT_SEL1 +#define LED__0__HSIOM_MASK 0x0F000000u +#define LED__0__HSIOM_SHIFT 24u +#define LED__0__INTCFG CYREG_PRT1_INTCFG +#define LED__0__INTSTAT CYREG_PRT1_INTSTAT +#define LED__0__MASK 0x40u +#define LED__0__PA__CFG0 CYREG_UDB_PA1_CFG0 +#define LED__0__PA__CFG1 CYREG_UDB_PA1_CFG1 +#define LED__0__PA__CFG10 CYREG_UDB_PA1_CFG10 +#define LED__0__PA__CFG11 CYREG_UDB_PA1_CFG11 +#define LED__0__PA__CFG12 CYREG_UDB_PA1_CFG12 +#define LED__0__PA__CFG13 CYREG_UDB_PA1_CFG13 +#define LED__0__PA__CFG14 CYREG_UDB_PA1_CFG14 +#define LED__0__PA__CFG2 CYREG_UDB_PA1_CFG2 +#define LED__0__PA__CFG3 CYREG_UDB_PA1_CFG3 +#define LED__0__PA__CFG4 CYREG_UDB_PA1_CFG4 +#define LED__0__PA__CFG5 CYREG_UDB_PA1_CFG5 +#define LED__0__PA__CFG6 CYREG_UDB_PA1_CFG6 +#define LED__0__PA__CFG7 CYREG_UDB_PA1_CFG7 +#define LED__0__PA__CFG8 CYREG_UDB_PA1_CFG8 +#define LED__0__PA__CFG9 CYREG_UDB_PA1_CFG9 +#define LED__0__PC CYREG_PRT1_PC +#define LED__0__PC2 CYREG_PRT1_PC2 +#define LED__0__PORT 1u +#define LED__0__PS CYREG_PRT1_PS +#define LED__0__SHIFT 6u +#define LED__DR CYREG_PRT1_DR +#define LED__INTCFG CYREG_PRT1_INTCFG +#define LED__INTSTAT CYREG_PRT1_INTSTAT +#define LED__MASK 0x40u +#define LED__PA__CFG0 CYREG_UDB_PA1_CFG0 +#define LED__PA__CFG1 CYREG_UDB_PA1_CFG1 +#define LED__PA__CFG10 CYREG_UDB_PA1_CFG10 +#define LED__PA__CFG11 CYREG_UDB_PA1_CFG11 +#define LED__PA__CFG12 CYREG_UDB_PA1_CFG12 +#define LED__PA__CFG13 CYREG_UDB_PA1_CFG13 +#define LED__PA__CFG14 CYREG_UDB_PA1_CFG14 +#define LED__PA__CFG2 CYREG_UDB_PA1_CFG2 +#define LED__PA__CFG3 CYREG_UDB_PA1_CFG3 +#define LED__PA__CFG4 CYREG_UDB_PA1_CFG4 +#define LED__PA__CFG5 CYREG_UDB_PA1_CFG5 +#define LED__PA__CFG6 CYREG_UDB_PA1_CFG6 +#define LED__PA__CFG7 CYREG_UDB_PA1_CFG7 +#define LED__PA__CFG8 CYREG_UDB_PA1_CFG8 +#define LED__PA__CFG9 CYREG_UDB_PA1_CFG9 +#define LED__PC CYREG_PRT1_PC +#define LED__PC2 CYREG_PRT1_PC2 +#define LED__PORT 1u +#define LED__PS CYREG_PRT1_PS +#define LED__SHIFT 6u + +/* UART */ +#define UART_SCB__BIST_CONTROL CYREG_SCB0_BIST_CONTROL +#define UART_SCB__BIST_DATA CYREG_SCB0_BIST_DATA +#define UART_SCB__CTRL CYREG_SCB0_CTRL +#define UART_SCB__EZ_DATA00 CYREG_SCB0_EZ_DATA00 +#define UART_SCB__EZ_DATA01 CYREG_SCB0_EZ_DATA01 +#define UART_SCB__EZ_DATA02 CYREG_SCB0_EZ_DATA02 +#define UART_SCB__EZ_DATA03 CYREG_SCB0_EZ_DATA03 +#define UART_SCB__EZ_DATA04 CYREG_SCB0_EZ_DATA04 +#define UART_SCB__EZ_DATA05 CYREG_SCB0_EZ_DATA05 +#define UART_SCB__EZ_DATA06 CYREG_SCB0_EZ_DATA06 +#define UART_SCB__EZ_DATA07 CYREG_SCB0_EZ_DATA07 +#define UART_SCB__EZ_DATA08 CYREG_SCB0_EZ_DATA08 +#define UART_SCB__EZ_DATA09 CYREG_SCB0_EZ_DATA09 +#define UART_SCB__EZ_DATA10 CYREG_SCB0_EZ_DATA10 +#define UART_SCB__EZ_DATA11 CYREG_SCB0_EZ_DATA11 +#define UART_SCB__EZ_DATA12 CYREG_SCB0_EZ_DATA12 +#define UART_SCB__EZ_DATA13 CYREG_SCB0_EZ_DATA13 +#define UART_SCB__EZ_DATA14 CYREG_SCB0_EZ_DATA14 +#define UART_SCB__EZ_DATA15 CYREG_SCB0_EZ_DATA15 +#define UART_SCB__EZ_DATA16 CYREG_SCB0_EZ_DATA16 +#define UART_SCB__EZ_DATA17 CYREG_SCB0_EZ_DATA17 +#define UART_SCB__EZ_DATA18 CYREG_SCB0_EZ_DATA18 +#define UART_SCB__EZ_DATA19 CYREG_SCB0_EZ_DATA19 +#define UART_SCB__EZ_DATA20 CYREG_SCB0_EZ_DATA20 +#define UART_SCB__EZ_DATA21 CYREG_SCB0_EZ_DATA21 +#define UART_SCB__EZ_DATA22 CYREG_SCB0_EZ_DATA22 +#define UART_SCB__EZ_DATA23 CYREG_SCB0_EZ_DATA23 +#define UART_SCB__EZ_DATA24 CYREG_SCB0_EZ_DATA24 +#define UART_SCB__EZ_DATA25 CYREG_SCB0_EZ_DATA25 +#define UART_SCB__EZ_DATA26 CYREG_SCB0_EZ_DATA26 +#define UART_SCB__EZ_DATA27 CYREG_SCB0_EZ_DATA27 +#define UART_SCB__EZ_DATA28 CYREG_SCB0_EZ_DATA28 +#define UART_SCB__EZ_DATA29 CYREG_SCB0_EZ_DATA29 +#define UART_SCB__EZ_DATA30 CYREG_SCB0_EZ_DATA30 +#define UART_SCB__EZ_DATA31 CYREG_SCB0_EZ_DATA31 +#define UART_SCB__I2C_CFG CYREG_SCB0_I2C_CFG +#define UART_SCB__I2C_CTRL CYREG_SCB0_I2C_CTRL +#define UART_SCB__I2C_M_CMD CYREG_SCB0_I2C_M_CMD +#define UART_SCB__I2C_S_CMD CYREG_SCB0_I2C_S_CMD +#define UART_SCB__I2C_STATUS CYREG_SCB0_I2C_STATUS +#define UART_SCB__INTR_CAUSE CYREG_SCB0_INTR_CAUSE +#define UART_SCB__INTR_I2C_EC CYREG_SCB0_INTR_I2C_EC +#define UART_SCB__INTR_I2C_EC_MASK CYREG_SCB0_INTR_I2C_EC_MASK +#define UART_SCB__INTR_I2C_EC_MASKED CYREG_SCB0_INTR_I2C_EC_MASKED +#define UART_SCB__INTR_M CYREG_SCB0_INTR_M +#define UART_SCB__INTR_M_MASK CYREG_SCB0_INTR_M_MASK +#define UART_SCB__INTR_M_MASKED CYREG_SCB0_INTR_M_MASKED +#define UART_SCB__INTR_M_SET CYREG_SCB0_INTR_M_SET +#define UART_SCB__INTR_RX CYREG_SCB0_INTR_RX +#define UART_SCB__INTR_RX_MASK CYREG_SCB0_INTR_RX_MASK +#define UART_SCB__INTR_RX_MASKED CYREG_SCB0_INTR_RX_MASKED +#define UART_SCB__INTR_RX_SET CYREG_SCB0_INTR_RX_SET +#define UART_SCB__INTR_S CYREG_SCB0_INTR_S +#define UART_SCB__INTR_S_MASK CYREG_SCB0_INTR_S_MASK +#define UART_SCB__INTR_S_MASKED CYREG_SCB0_INTR_S_MASKED +#define UART_SCB__INTR_S_SET CYREG_SCB0_INTR_S_SET +#define UART_SCB__INTR_SPI_EC CYREG_SCB0_INTR_SPI_EC +#define UART_SCB__INTR_SPI_EC_MASK CYREG_SCB0_INTR_SPI_EC_MASK +#define UART_SCB__INTR_SPI_EC_MASKED CYREG_SCB0_INTR_SPI_EC_MASKED +#define UART_SCB__INTR_TX CYREG_SCB0_INTR_TX +#define UART_SCB__INTR_TX_MASK CYREG_SCB0_INTR_TX_MASK +#define UART_SCB__INTR_TX_MASKED CYREG_SCB0_INTR_TX_MASKED +#define UART_SCB__INTR_TX_SET CYREG_SCB0_INTR_TX_SET +#define UART_SCB__RX_CTRL CYREG_SCB0_RX_CTRL +#define UART_SCB__RX_FIFO_CTRL CYREG_SCB0_RX_FIFO_CTRL +#define UART_SCB__RX_FIFO_RD CYREG_SCB0_RX_FIFO_RD +#define UART_SCB__RX_FIFO_RD_SILENT CYREG_SCB0_RX_FIFO_RD_SILENT +#define UART_SCB__RX_FIFO_STATUS CYREG_SCB0_RX_FIFO_STATUS +#define UART_SCB__RX_MATCH CYREG_SCB0_RX_MATCH +#define UART_SCB__SPI_CTRL CYREG_SCB0_SPI_CTRL +#define UART_SCB__SPI_STATUS CYREG_SCB0_SPI_STATUS +#define UART_SCB__SS0_POSISTION 0u +#define UART_SCB__SS1_POSISTION 1u +#define UART_SCB__SS2_POSISTION 2u +#define UART_SCB__SS3_POSISTION 3u +#define UART_SCB__STATUS CYREG_SCB0_STATUS +#define UART_SCB__TX_CTRL CYREG_SCB0_TX_CTRL +#define UART_SCB__TX_FIFO_CTRL CYREG_SCB0_TX_FIFO_CTRL +#define UART_SCB__TX_FIFO_STATUS CYREG_SCB0_TX_FIFO_STATUS +#define UART_SCB__TX_FIFO_WR CYREG_SCB0_TX_FIFO_WR +#define UART_SCB__UART_CTRL CYREG_SCB0_UART_CTRL +#define UART_SCB__UART_RX_CTRL CYREG_SCB0_UART_RX_CTRL +#define UART_SCB__UART_RX_STATUS CYREG_SCB0_UART_RX_STATUS +#define UART_SCB__UART_TX_CTRL CYREG_SCB0_UART_TX_CTRL +#define UART_SCBCLK__DIVIDER_MASK 0x0000FFFFu +#define UART_SCBCLK__ENABLE CYREG_CLK_DIVIDER_B00 +#define UART_SCBCLK__ENABLE_MASK 0x80000000u +#define UART_SCBCLK__MASK 0x80000000u +#define UART_SCBCLK__REGISTER CYREG_CLK_DIVIDER_B00 +#define UART_tx__0__DM__MASK 0x38u +#define UART_tx__0__DM__SHIFT 3u +#define UART_tx__0__DR CYREG_PRT4_DR +#define UART_tx__0__HSIOM CYREG_HSIOM_PORT_SEL4 +#define UART_tx__0__HSIOM_GPIO 0u +#define UART_tx__0__HSIOM_I2C 14u +#define UART_tx__0__HSIOM_I2C_SDA 14u +#define UART_tx__0__HSIOM_MASK 0x000000F0u +#define UART_tx__0__HSIOM_SHIFT 4u +#define UART_tx__0__HSIOM_SPI 15u +#define UART_tx__0__HSIOM_SPI_MISO 15u +#define UART_tx__0__HSIOM_UART 9u +#define UART_tx__0__HSIOM_UART_TX 9u +#define UART_tx__0__INTCFG CYREG_PRT4_INTCFG +#define UART_tx__0__INTSTAT CYREG_PRT4_INTSTAT +#define UART_tx__0__MASK 0x02u +#define UART_tx__0__PC CYREG_PRT4_PC +#define UART_tx__0__PC2 CYREG_PRT4_PC2 +#define UART_tx__0__PORT 4u +#define UART_tx__0__PS CYREG_PRT4_PS +#define UART_tx__0__SHIFT 1u +#define UART_tx__DR CYREG_PRT4_DR +#define UART_tx__INTCFG CYREG_PRT4_INTCFG +#define UART_tx__INTSTAT CYREG_PRT4_INTSTAT +#define UART_tx__MASK 0x02u +#define UART_tx__PC CYREG_PRT4_PC +#define UART_tx__PC2 CYREG_PRT4_PC2 +#define UART_tx__PORT 4u +#define UART_tx__PS CYREG_PRT4_PS +#define UART_tx__SHIFT 1u + +/* Input_1 */ +#define Input_1__0__DM__MASK 0xE00u +#define Input_1__0__DM__SHIFT 9u +#define Input_1__0__DR CYREG_PRT2_DR +#define Input_1__0__HSIOM CYREG_HSIOM_PORT_SEL2 +#define Input_1__0__HSIOM_MASK 0x0000F000u +#define Input_1__0__HSIOM_SHIFT 12u +#define Input_1__0__INTCFG CYREG_PRT2_INTCFG +#define Input_1__0__INTSTAT CYREG_PRT2_INTSTAT +#define Input_1__0__MASK 0x08u +#define Input_1__0__PA__CFG0 CYREG_UDB_PA2_CFG0 +#define Input_1__0__PA__CFG1 CYREG_UDB_PA2_CFG1 +#define Input_1__0__PA__CFG10 CYREG_UDB_PA2_CFG10 +#define Input_1__0__PA__CFG11 CYREG_UDB_PA2_CFG11 +#define Input_1__0__PA__CFG12 CYREG_UDB_PA2_CFG12 +#define Input_1__0__PA__CFG13 CYREG_UDB_PA2_CFG13 +#define Input_1__0__PA__CFG14 CYREG_UDB_PA2_CFG14 +#define Input_1__0__PA__CFG2 CYREG_UDB_PA2_CFG2 +#define Input_1__0__PA__CFG3 CYREG_UDB_PA2_CFG3 +#define Input_1__0__PA__CFG4 CYREG_UDB_PA2_CFG4 +#define Input_1__0__PA__CFG5 CYREG_UDB_PA2_CFG5 +#define Input_1__0__PA__CFG6 CYREG_UDB_PA2_CFG6 +#define Input_1__0__PA__CFG7 CYREG_UDB_PA2_CFG7 +#define Input_1__0__PA__CFG8 CYREG_UDB_PA2_CFG8 +#define Input_1__0__PA__CFG9 CYREG_UDB_PA2_CFG9 +#define Input_1__0__PC CYREG_PRT2_PC +#define Input_1__0__PC2 CYREG_PRT2_PC2 +#define Input_1__0__PORT 2u +#define Input_1__0__PS CYREG_PRT2_PS +#define Input_1__0__SHIFT 3u +#define Input_1__DR CYREG_PRT2_DR +#define Input_1__INTCFG CYREG_PRT2_INTCFG +#define Input_1__INTSTAT CYREG_PRT2_INTSTAT +#define Input_1__MASK 0x08u +#define Input_1__PA__CFG0 CYREG_UDB_PA2_CFG0 +#define Input_1__PA__CFG1 CYREG_UDB_PA2_CFG1 +#define Input_1__PA__CFG10 CYREG_UDB_PA2_CFG10 +#define Input_1__PA__CFG11 CYREG_UDB_PA2_CFG11 +#define Input_1__PA__CFG12 CYREG_UDB_PA2_CFG12 +#define Input_1__PA__CFG13 CYREG_UDB_PA2_CFG13 +#define Input_1__PA__CFG14 CYREG_UDB_PA2_CFG14 +#define Input_1__PA__CFG2 CYREG_UDB_PA2_CFG2 +#define Input_1__PA__CFG3 CYREG_UDB_PA2_CFG3 +#define Input_1__PA__CFG4 CYREG_UDB_PA2_CFG4 +#define Input_1__PA__CFG5 CYREG_UDB_PA2_CFG5 +#define Input_1__PA__CFG6 CYREG_UDB_PA2_CFG6 +#define Input_1__PA__CFG7 CYREG_UDB_PA2_CFG7 +#define Input_1__PA__CFG8 CYREG_UDB_PA2_CFG8 +#define Input_1__PA__CFG9 CYREG_UDB_PA2_CFG9 +#define Input_1__PC CYREG_PRT2_PC +#define Input_1__PC2 CYREG_PRT2_PC2 +#define Input_1__PORT 2u +#define Input_1__PS CYREG_PRT2_PS +#define Input_1__SHIFT 3u + +/* Miscellaneous */ +#define CY_PROJECT_NAME "ADC-UART" +#define CY_VERSION "PSoC Creator 4.2" +#define CYDEV_BANDGAP_VOLTAGE 1.024 +#define CYDEV_BCLK__HFCLK__HZ 24000000U +#define CYDEV_BCLK__HFCLK__KHZ 24000U +#define CYDEV_BCLK__HFCLK__MHZ 24U +#define CYDEV_BCLK__SYSCLK__HZ 24000000U +#define CYDEV_BCLK__SYSCLK__KHZ 24000U +#define CYDEV_BCLK__SYSCLK__MHZ 24U +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4 +#define CYDEV_CHIP_JTAG_ID 0x04C81193u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4A +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u +#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u +#define CYDEV_CHIP_REV_TMA4_ES 17u +#define CYDEV_CHIP_REV_TMA4_ES2 33u +#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u +#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u +#define CYDEV_CHIP_REVISION_4G_ES 17u +#define CYDEV_CHIP_REVISION_4G_ES2 33u +#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u +#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4A_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED +#define CYDEV_CONFIG_READ_ACCELERATOR 1 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_DEBUG_PROTECT_KILL 4 +#define CYDEV_DEBUG_PROTECT_OPEN 1 +#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN +#define CYDEV_DEBUG_PROTECT_PROTECTED 2 +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DFT_SELECT_CLK0 1u +#define CYDEV_DFT_SELECT_CLK1 2u +#define CYDEV_HEAP_SIZE 0x0100 +#define CYDEV_IMO_TRIMMED_BY_USB 0u +#define CYDEV_IMO_TRIMMED_BY_WCO 0u +#define CYDEV_IS_EXPORTING_CODE 0 +#define CYDEV_IS_IMPORTING_CODE 0 +#define CYDEV_PROJ_TYPE 0 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LAUNCHER 5 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_STACK_SIZE 0x0400 +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5.0 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5.0 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_WDT_GENERATE_ISR 0u +#define CYIPBLOCK_M0S8_CTBM_VERSION 0 +#define CYIPBLOCK_m0s8cpuss_VERSION 0 +#define CYIPBLOCK_m0s8csd_VERSION 0 +#define CYIPBLOCK_m0s8gpio2_VERSION 0 +#define CYIPBLOCK_m0s8hsiom4a_VERSION 0 +#define CYIPBLOCK_m0s8lcd_VERSION 0 +#define CYIPBLOCK_m0s8lpcomp_VERSION 0 +#define CYIPBLOCK_m0s8pclk_VERSION 0 +#define CYIPBLOCK_m0s8sar_VERSION 0 +#define CYIPBLOCK_m0s8scb_VERSION 0 +#define CYIPBLOCK_m0s8srssv2_VERSION 1 +#define CYIPBLOCK_m0s8tcpwm_VERSION 0 +#define CYIPBLOCK_m0s8udbif_VERSION 0 +#define CYIPBLOCK_S8_GPIO_VERSION 2 +#define CYDEV_BOOTLOADER_ENABLE 0 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter_cfg.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter_cfg.c new file mode 100644 index 0000000..02d1175 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter_cfg.c @@ -0,0 +1,315 @@ + +/******************************************************************************* +* File Name: cyfitter_cfg.c +* +* PSoC Creator 4.2 +* +* Description: +* This file contains device initialization code. +* Except for the user defined sections in CyClockStartupError(), this file should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" +#include "cyfitter_cfg.h" +#include "cyapicallbacks.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #ifndef CY_CFG_SECTION + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #endif + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u + + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* `#START CyClockStartupError` */ + + + + /* `#END` */ + + while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +} +#endif + + + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +CY_CFG_SECTION +static void ClockSetup(void) +{ + /* Enable HALF_EN before trimming for the flash accelerator. */ + CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u)); + + /* Setup and trim IMO based on desired frequency. */ + CySysClkWriteImoFreq(24u); + + /* Disable HALF_EN since it is not required at this IMO frequency. */ + CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu)); + /* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */ + CY_SET_REG32((void *)(CYREG_CLK_ILO_CONFIG), 0x80000006u); + + + /* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */ + CY_SET_REG32((void *)(CYREG_CLK_SELECT02), 0x00000020u); + CY_SET_REG32((void *)(CYREG_CLK_SELECT07), 0x00000010u); + + /* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */ + CY_SET_REG32((void *)(CYREG_CLK_IMO_CONFIG), 0x82000000u); + + /* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */ + CY_SET_REG32((void *)(CYREG_CLK_SELECT), 0x00000000u); + + /* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */ + CY_SET_REG32((void *)(CYREG_CLK_DIVIDER_A00), 0x80000017u); + + /* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */ + CY_SET_REG32((void *)(CYREG_CLK_DIVIDER_B00), 0x80000138u); + + CY_SET_REG32((void *)(CYREG_WDT_CONFIG), 0x00000000u); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + CY_SET_XTND_REG32((void CYFAR *)CYREG_SAR_MUX_SWITCH0, 0x00000008u); +} + + + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_SECTION +void cyfitter_cfg(void) +{ + /* Disable interrupts by default. Let user enable if/when they want. */ + CyGlobalIntDisable; + + { + + CYPACKED typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED_ATTR cfg_memset_t; + + static const cfg_memset_t CYCODE cfg_memset_list[] = { + /* address, size */ + {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, + {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); + } + + /* HSIOM Starting address: CYDEV_HSIOM_BASE */ + CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); + CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL4), 0x00000090u); + + /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ + CY_SET_REG32((void *)(CYDEV_UDB_PA1_BASE), 0x00990000u); + + /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ + CY_SET_REG32((void *)(CYDEV_UDB_PA2_BASE), 0x00990000u); + + /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ + CY_SET_REG32((void *)(CYDEV_UDB_PA3_BASE), 0x00990000u); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u)); + } + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + /* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */ + CY_SET_REG32((void *)(CYDEV_PRT1_BASE), 0x00000040u); + CY_SET_REG32((void *)(CYREG_PRT1_PC), 0x00100000u); + + /* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */ + CY_SET_REG32((void *)(CYDEV_PRT2_BASE), 0x00000008u); + CY_SET_REG32((void *)(CYREG_PRT2_PC2), 0x00000008u); + + /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ + CY_SET_REG32((void *)(CYREG_PRT3_PC), 0x00000D80u); + + /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ + CY_SET_REG32((void *)(CYDEV_PRT4_BASE), 0x00000002u); + CY_SET_REG32((void *)(CYREG_PRT4_PC), 0x00000030u); + CY_SET_REG32((void *)(CYREG_PRT4_PC2), 0x00000002u); + + + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + +} diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter_cfg.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter_cfg.h new file mode 100644 index 0000000..c5ca4c7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitter_cfg.h @@ -0,0 +1,29 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides basic startup and mux configuration settings +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include "cytypes.h" + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfittergnu.inc b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfittergnu.inc new file mode 100644 index 0000000..98e67a6 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfittergnu.inc @@ -0,0 +1,496 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu_trm.inc" + +/* ADC */ +.set ADC_cy_psoc4_sar__SAR_ANA_TRIM, CYREG_SAR_ANA_TRIM +.set ADC_cy_psoc4_sar__SAR_AVG_STAT, CYREG_SAR_AVG_STAT +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00, CYREG_SAR_CHAN_CONFIG00 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01, CYREG_SAR_CHAN_CONFIG01 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02, CYREG_SAR_CHAN_CONFIG02 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03, CYREG_SAR_CHAN_CONFIG03 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04, CYREG_SAR_CHAN_CONFIG04 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05, CYREG_SAR_CHAN_CONFIG05 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06, CYREG_SAR_CHAN_CONFIG06 +.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07, CYREG_SAR_CHAN_CONFIG07 +.set ADC_cy_psoc4_sar__SAR_CHAN_EN, CYREG_SAR_CHAN_EN +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID, CYREG_SAR_CHAN_RESULT_VALID +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT00, CYREG_SAR_CHAN_RESULT00 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT01, CYREG_SAR_CHAN_RESULT01 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT02, CYREG_SAR_CHAN_RESULT02 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT03, CYREG_SAR_CHAN_RESULT03 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT04, CYREG_SAR_CHAN_RESULT04 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT05, CYREG_SAR_CHAN_RESULT05 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT06, CYREG_SAR_CHAN_RESULT06 +.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT07, CYREG_SAR_CHAN_RESULT07 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID, CYREG_SAR_CHAN_WORK_VALID +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK00, CYREG_SAR_CHAN_WORK00 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK01, CYREG_SAR_CHAN_WORK01 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK02, CYREG_SAR_CHAN_WORK02 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK03, CYREG_SAR_CHAN_WORK03 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK04, CYREG_SAR_CHAN_WORK04 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK05, CYREG_SAR_CHAN_WORK05 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK06, CYREG_SAR_CHAN_WORK06 +.set ADC_cy_psoc4_sar__SAR_CHAN_WORK07, CYREG_SAR_CHAN_WORK07 +.set ADC_cy_psoc4_sar__SAR_CTRL, CYREG_SAR_CTRL +.set ADC_cy_psoc4_sar__SAR_DFT_CTRL, CYREG_SAR_DFT_CTRL +.set ADC_cy_psoc4_sar__SAR_INTR, CYREG_SAR_INTR +.set ADC_cy_psoc4_sar__SAR_INTR_CAUSE, CYREG_SAR_INTR_CAUSE +.set ADC_cy_psoc4_sar__SAR_INTR_MASK, CYREG_SAR_INTR_MASK +.set ADC_cy_psoc4_sar__SAR_INTR_MASKED, CYREG_SAR_INTR_MASKED +.set ADC_cy_psoc4_sar__SAR_INTR_SET, CYREG_SAR_INTR_SET +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0, CYREG_SAR_MUX_SWITCH_CLEAR0 +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1, CYREG_SAR_MUX_SWITCH_CLEAR1 +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL, CYREG_SAR_MUX_SWITCH_HW_CTRL +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS, CYREG_SAR_MUX_SWITCH_STATUS +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH0, CYREG_SAR_MUX_SWITCH0 +.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH1, CYREG_SAR_MUX_SWITCH1 +.set ADC_cy_psoc4_sar__SAR_NUMBER, 0 +.set ADC_cy_psoc4_sar__SAR_PUMP_CTRL, CYREG_SAR_PUMP_CTRL +.set ADC_cy_psoc4_sar__SAR_RANGE_COND, CYREG_SAR_RANGE_COND +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR, CYREG_SAR_RANGE_INTR +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK, CYREG_SAR_RANGE_INTR_MASK +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED, CYREG_SAR_RANGE_INTR_MASKED +.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET, CYREG_SAR_RANGE_INTR_SET +.set ADC_cy_psoc4_sar__SAR_RANGE_THRES, CYREG_SAR_RANGE_THRES +.set ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL, CYREG_SAR_SAMPLE_CTRL +.set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01, CYREG_SAR_SAMPLE_TIME01 +.set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23, CYREG_SAR_SAMPLE_TIME23 +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR, CYREG_SAR_SATURATE_INTR +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK, CYREG_SAR_SATURATE_INTR_MASK +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED, CYREG_SAR_SATURATE_INTR_MASKED +.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET, CYREG_SAR_SATURATE_INTR_SET +.set ADC_cy_psoc4_sar__SAR_START_CTRL, CYREG_SAR_START_CTRL +.set ADC_cy_psoc4_sar__SAR_STATUS, CYREG_SAR_STATUS +.set ADC_cy_psoc4_sar__SAR_WOUNDING, CYREG_SAR_WOUNDING +.set ADC_intClock__DIVIDER_MASK, 0x0000FFFF +.set ADC_intClock__ENABLE, CYREG_CLK_DIVIDER_A00 +.set ADC_intClock__ENABLE_MASK, 0x80000000 +.set ADC_intClock__MASK, 0x80000000 +.set ADC_intClock__REGISTER, CYREG_CLK_DIVIDER_A00 +.set ADC_IRQ__INTC_CLR_EN_REG, CYREG_CM0_ICER +.set ADC_IRQ__INTC_CLR_PD_REG, CYREG_CM0_ICPR +.set ADC_IRQ__INTC_MASK, 0x4000 +.set ADC_IRQ__INTC_NUMBER, 14 +.set ADC_IRQ__INTC_PRIOR_MASK, 0xC00000 +.set ADC_IRQ__INTC_PRIOR_NUM, 3 +.set ADC_IRQ__INTC_PRIOR_REG, CYREG_CM0_IPR3 +.set ADC_IRQ__INTC_SET_EN_REG, CYREG_CM0_ISER +.set ADC_IRQ__INTC_SET_PD_REG, CYREG_CM0_ISPR + +/* LED */ +.set LED__0__DM__MASK, 0x1C0000 +.set LED__0__DM__SHIFT, 18 +.set LED__0__DR, CYREG_PRT1_DR +.set LED__0__HSIOM, CYREG_HSIOM_PORT_SEL1 +.set LED__0__HSIOM_MASK, 0x0F000000 +.set LED__0__HSIOM_SHIFT, 24 +.set LED__0__INTCFG, CYREG_PRT1_INTCFG +.set LED__0__INTSTAT, CYREG_PRT1_INTSTAT +.set LED__0__MASK, 0x40 +.set LED__0__PA__CFG0, CYREG_UDB_PA1_CFG0 +.set LED__0__PA__CFG1, CYREG_UDB_PA1_CFG1 +.set LED__0__PA__CFG10, CYREG_UDB_PA1_CFG10 +.set LED__0__PA__CFG11, CYREG_UDB_PA1_CFG11 +.set LED__0__PA__CFG12, CYREG_UDB_PA1_CFG12 +.set LED__0__PA__CFG13, CYREG_UDB_PA1_CFG13 +.set LED__0__PA__CFG14, CYREG_UDB_PA1_CFG14 +.set LED__0__PA__CFG2, CYREG_UDB_PA1_CFG2 +.set LED__0__PA__CFG3, CYREG_UDB_PA1_CFG3 +.set LED__0__PA__CFG4, CYREG_UDB_PA1_CFG4 +.set LED__0__PA__CFG5, CYREG_UDB_PA1_CFG5 +.set LED__0__PA__CFG6, CYREG_UDB_PA1_CFG6 +.set LED__0__PA__CFG7, CYREG_UDB_PA1_CFG7 +.set LED__0__PA__CFG8, CYREG_UDB_PA1_CFG8 +.set LED__0__PA__CFG9, CYREG_UDB_PA1_CFG9 +.set LED__0__PC, CYREG_PRT1_PC +.set LED__0__PC2, CYREG_PRT1_PC2 +.set LED__0__PORT, 1 +.set LED__0__PS, CYREG_PRT1_PS +.set LED__0__SHIFT, 6 +.set LED__DR, CYREG_PRT1_DR +.set LED__INTCFG, CYREG_PRT1_INTCFG +.set LED__INTSTAT, CYREG_PRT1_INTSTAT +.set LED__MASK, 0x40 +.set LED__PA__CFG0, CYREG_UDB_PA1_CFG0 +.set LED__PA__CFG1, CYREG_UDB_PA1_CFG1 +.set LED__PA__CFG10, CYREG_UDB_PA1_CFG10 +.set LED__PA__CFG11, CYREG_UDB_PA1_CFG11 +.set LED__PA__CFG12, CYREG_UDB_PA1_CFG12 +.set LED__PA__CFG13, CYREG_UDB_PA1_CFG13 +.set LED__PA__CFG14, CYREG_UDB_PA1_CFG14 +.set LED__PA__CFG2, CYREG_UDB_PA1_CFG2 +.set LED__PA__CFG3, CYREG_UDB_PA1_CFG3 +.set LED__PA__CFG4, CYREG_UDB_PA1_CFG4 +.set LED__PA__CFG5, CYREG_UDB_PA1_CFG5 +.set LED__PA__CFG6, CYREG_UDB_PA1_CFG6 +.set LED__PA__CFG7, CYREG_UDB_PA1_CFG7 +.set LED__PA__CFG8, CYREG_UDB_PA1_CFG8 +.set LED__PA__CFG9, CYREG_UDB_PA1_CFG9 +.set LED__PC, CYREG_PRT1_PC +.set LED__PC2, CYREG_PRT1_PC2 +.set LED__PORT, 1 +.set LED__PS, CYREG_PRT1_PS +.set LED__SHIFT, 6 + +/* UART */ +.set UART_SCB__BIST_CONTROL, CYREG_SCB0_BIST_CONTROL +.set UART_SCB__BIST_DATA, CYREG_SCB0_BIST_DATA +.set UART_SCB__CTRL, CYREG_SCB0_CTRL +.set UART_SCB__EZ_DATA00, CYREG_SCB0_EZ_DATA00 +.set UART_SCB__EZ_DATA01, CYREG_SCB0_EZ_DATA01 +.set UART_SCB__EZ_DATA02, CYREG_SCB0_EZ_DATA02 +.set UART_SCB__EZ_DATA03, CYREG_SCB0_EZ_DATA03 +.set UART_SCB__EZ_DATA04, CYREG_SCB0_EZ_DATA04 +.set UART_SCB__EZ_DATA05, CYREG_SCB0_EZ_DATA05 +.set UART_SCB__EZ_DATA06, CYREG_SCB0_EZ_DATA06 +.set UART_SCB__EZ_DATA07, CYREG_SCB0_EZ_DATA07 +.set UART_SCB__EZ_DATA08, CYREG_SCB0_EZ_DATA08 +.set UART_SCB__EZ_DATA09, CYREG_SCB0_EZ_DATA09 +.set UART_SCB__EZ_DATA10, CYREG_SCB0_EZ_DATA10 +.set UART_SCB__EZ_DATA11, CYREG_SCB0_EZ_DATA11 +.set UART_SCB__EZ_DATA12, CYREG_SCB0_EZ_DATA12 +.set UART_SCB__EZ_DATA13, CYREG_SCB0_EZ_DATA13 +.set UART_SCB__EZ_DATA14, CYREG_SCB0_EZ_DATA14 +.set UART_SCB__EZ_DATA15, CYREG_SCB0_EZ_DATA15 +.set UART_SCB__EZ_DATA16, CYREG_SCB0_EZ_DATA16 +.set UART_SCB__EZ_DATA17, CYREG_SCB0_EZ_DATA17 +.set UART_SCB__EZ_DATA18, CYREG_SCB0_EZ_DATA18 +.set UART_SCB__EZ_DATA19, CYREG_SCB0_EZ_DATA19 +.set UART_SCB__EZ_DATA20, CYREG_SCB0_EZ_DATA20 +.set UART_SCB__EZ_DATA21, CYREG_SCB0_EZ_DATA21 +.set UART_SCB__EZ_DATA22, CYREG_SCB0_EZ_DATA22 +.set UART_SCB__EZ_DATA23, CYREG_SCB0_EZ_DATA23 +.set UART_SCB__EZ_DATA24, CYREG_SCB0_EZ_DATA24 +.set UART_SCB__EZ_DATA25, CYREG_SCB0_EZ_DATA25 +.set UART_SCB__EZ_DATA26, CYREG_SCB0_EZ_DATA26 +.set UART_SCB__EZ_DATA27, CYREG_SCB0_EZ_DATA27 +.set UART_SCB__EZ_DATA28, CYREG_SCB0_EZ_DATA28 +.set UART_SCB__EZ_DATA29, CYREG_SCB0_EZ_DATA29 +.set UART_SCB__EZ_DATA30, CYREG_SCB0_EZ_DATA30 +.set UART_SCB__EZ_DATA31, CYREG_SCB0_EZ_DATA31 +.set UART_SCB__I2C_CFG, CYREG_SCB0_I2C_CFG +.set UART_SCB__I2C_CTRL, CYREG_SCB0_I2C_CTRL +.set UART_SCB__I2C_M_CMD, CYREG_SCB0_I2C_M_CMD +.set UART_SCB__I2C_S_CMD, CYREG_SCB0_I2C_S_CMD +.set UART_SCB__I2C_STATUS, CYREG_SCB0_I2C_STATUS +.set UART_SCB__INTR_CAUSE, CYREG_SCB0_INTR_CAUSE +.set UART_SCB__INTR_I2C_EC, CYREG_SCB0_INTR_I2C_EC +.set UART_SCB__INTR_I2C_EC_MASK, CYREG_SCB0_INTR_I2C_EC_MASK +.set UART_SCB__INTR_I2C_EC_MASKED, CYREG_SCB0_INTR_I2C_EC_MASKED +.set UART_SCB__INTR_M, CYREG_SCB0_INTR_M +.set UART_SCB__INTR_M_MASK, CYREG_SCB0_INTR_M_MASK +.set UART_SCB__INTR_M_MASKED, CYREG_SCB0_INTR_M_MASKED +.set UART_SCB__INTR_M_SET, CYREG_SCB0_INTR_M_SET +.set UART_SCB__INTR_RX, CYREG_SCB0_INTR_RX +.set UART_SCB__INTR_RX_MASK, CYREG_SCB0_INTR_RX_MASK +.set UART_SCB__INTR_RX_MASKED, CYREG_SCB0_INTR_RX_MASKED +.set UART_SCB__INTR_RX_SET, CYREG_SCB0_INTR_RX_SET +.set UART_SCB__INTR_S, CYREG_SCB0_INTR_S +.set UART_SCB__INTR_S_MASK, CYREG_SCB0_INTR_S_MASK +.set UART_SCB__INTR_S_MASKED, CYREG_SCB0_INTR_S_MASKED +.set UART_SCB__INTR_S_SET, CYREG_SCB0_INTR_S_SET +.set UART_SCB__INTR_SPI_EC, CYREG_SCB0_INTR_SPI_EC +.set UART_SCB__INTR_SPI_EC_MASK, CYREG_SCB0_INTR_SPI_EC_MASK +.set UART_SCB__INTR_SPI_EC_MASKED, CYREG_SCB0_INTR_SPI_EC_MASKED +.set UART_SCB__INTR_TX, CYREG_SCB0_INTR_TX +.set UART_SCB__INTR_TX_MASK, CYREG_SCB0_INTR_TX_MASK +.set UART_SCB__INTR_TX_MASKED, CYREG_SCB0_INTR_TX_MASKED +.set UART_SCB__INTR_TX_SET, CYREG_SCB0_INTR_TX_SET +.set UART_SCB__RX_CTRL, CYREG_SCB0_RX_CTRL +.set UART_SCB__RX_FIFO_CTRL, CYREG_SCB0_RX_FIFO_CTRL +.set UART_SCB__RX_FIFO_RD, CYREG_SCB0_RX_FIFO_RD +.set UART_SCB__RX_FIFO_RD_SILENT, CYREG_SCB0_RX_FIFO_RD_SILENT +.set UART_SCB__RX_FIFO_STATUS, CYREG_SCB0_RX_FIFO_STATUS +.set UART_SCB__RX_MATCH, CYREG_SCB0_RX_MATCH +.set UART_SCB__SPI_CTRL, CYREG_SCB0_SPI_CTRL +.set UART_SCB__SPI_STATUS, CYREG_SCB0_SPI_STATUS +.set UART_SCB__SS0_POSISTION, 0 +.set UART_SCB__SS1_POSISTION, 1 +.set UART_SCB__SS2_POSISTION, 2 +.set UART_SCB__SS3_POSISTION, 3 +.set UART_SCB__STATUS, CYREG_SCB0_STATUS +.set UART_SCB__TX_CTRL, CYREG_SCB0_TX_CTRL +.set UART_SCB__TX_FIFO_CTRL, CYREG_SCB0_TX_FIFO_CTRL +.set UART_SCB__TX_FIFO_STATUS, CYREG_SCB0_TX_FIFO_STATUS +.set UART_SCB__TX_FIFO_WR, CYREG_SCB0_TX_FIFO_WR +.set UART_SCB__UART_CTRL, CYREG_SCB0_UART_CTRL +.set UART_SCB__UART_RX_CTRL, CYREG_SCB0_UART_RX_CTRL +.set UART_SCB__UART_RX_STATUS, CYREG_SCB0_UART_RX_STATUS +.set UART_SCB__UART_TX_CTRL, CYREG_SCB0_UART_TX_CTRL +.set UART_SCBCLK__DIVIDER_MASK, 0x0000FFFF +.set UART_SCBCLK__ENABLE, CYREG_CLK_DIVIDER_B00 +.set UART_SCBCLK__ENABLE_MASK, 0x80000000 +.set UART_SCBCLK__MASK, 0x80000000 +.set UART_SCBCLK__REGISTER, CYREG_CLK_DIVIDER_B00 +.set UART_tx__0__DM__MASK, 0x38 +.set UART_tx__0__DM__SHIFT, 3 +.set UART_tx__0__DR, CYREG_PRT4_DR +.set UART_tx__0__HSIOM, CYREG_HSIOM_PORT_SEL4 +.set UART_tx__0__HSIOM_GPIO, 0 +.set UART_tx__0__HSIOM_I2C, 14 +.set UART_tx__0__HSIOM_I2C_SDA, 14 +.set UART_tx__0__HSIOM_MASK, 0x000000F0 +.set UART_tx__0__HSIOM_SHIFT, 4 +.set UART_tx__0__HSIOM_SPI, 15 +.set UART_tx__0__HSIOM_SPI_MISO, 15 +.set UART_tx__0__HSIOM_UART, 9 +.set UART_tx__0__HSIOM_UART_TX, 9 +.set UART_tx__0__INTCFG, CYREG_PRT4_INTCFG +.set UART_tx__0__INTSTAT, CYREG_PRT4_INTSTAT +.set UART_tx__0__MASK, 0x02 +.set UART_tx__0__PC, CYREG_PRT4_PC +.set UART_tx__0__PC2, CYREG_PRT4_PC2 +.set UART_tx__0__PORT, 4 +.set UART_tx__0__PS, CYREG_PRT4_PS +.set UART_tx__0__SHIFT, 1 +.set UART_tx__DR, CYREG_PRT4_DR +.set UART_tx__INTCFG, CYREG_PRT4_INTCFG +.set UART_tx__INTSTAT, CYREG_PRT4_INTSTAT +.set UART_tx__MASK, 0x02 +.set UART_tx__PC, CYREG_PRT4_PC +.set UART_tx__PC2, CYREG_PRT4_PC2 +.set UART_tx__PORT, 4 +.set UART_tx__PS, CYREG_PRT4_PS +.set UART_tx__SHIFT, 1 + +/* Input_1 */ +.set Input_1__0__DM__MASK, 0xE00 +.set Input_1__0__DM__SHIFT, 9 +.set Input_1__0__DR, CYREG_PRT2_DR +.set Input_1__0__HSIOM, CYREG_HSIOM_PORT_SEL2 +.set Input_1__0__HSIOM_MASK, 0x0000F000 +.set Input_1__0__HSIOM_SHIFT, 12 +.set Input_1__0__INTCFG, CYREG_PRT2_INTCFG +.set Input_1__0__INTSTAT, CYREG_PRT2_INTSTAT +.set Input_1__0__MASK, 0x08 +.set Input_1__0__PA__CFG0, CYREG_UDB_PA2_CFG0 +.set Input_1__0__PA__CFG1, CYREG_UDB_PA2_CFG1 +.set Input_1__0__PA__CFG10, CYREG_UDB_PA2_CFG10 +.set Input_1__0__PA__CFG11, CYREG_UDB_PA2_CFG11 +.set Input_1__0__PA__CFG12, CYREG_UDB_PA2_CFG12 +.set Input_1__0__PA__CFG13, CYREG_UDB_PA2_CFG13 +.set Input_1__0__PA__CFG14, CYREG_UDB_PA2_CFG14 +.set Input_1__0__PA__CFG2, CYREG_UDB_PA2_CFG2 +.set Input_1__0__PA__CFG3, CYREG_UDB_PA2_CFG3 +.set Input_1__0__PA__CFG4, CYREG_UDB_PA2_CFG4 +.set Input_1__0__PA__CFG5, CYREG_UDB_PA2_CFG5 +.set Input_1__0__PA__CFG6, CYREG_UDB_PA2_CFG6 +.set Input_1__0__PA__CFG7, CYREG_UDB_PA2_CFG7 +.set Input_1__0__PA__CFG8, CYREG_UDB_PA2_CFG8 +.set Input_1__0__PA__CFG9, CYREG_UDB_PA2_CFG9 +.set Input_1__0__PC, CYREG_PRT2_PC +.set Input_1__0__PC2, CYREG_PRT2_PC2 +.set Input_1__0__PORT, 2 +.set Input_1__0__PS, CYREG_PRT2_PS +.set Input_1__0__SHIFT, 3 +.set Input_1__DR, CYREG_PRT2_DR +.set Input_1__INTCFG, CYREG_PRT2_INTCFG +.set Input_1__INTSTAT, CYREG_PRT2_INTSTAT +.set Input_1__MASK, 0x08 +.set Input_1__PA__CFG0, CYREG_UDB_PA2_CFG0 +.set Input_1__PA__CFG1, CYREG_UDB_PA2_CFG1 +.set Input_1__PA__CFG10, CYREG_UDB_PA2_CFG10 +.set Input_1__PA__CFG11, CYREG_UDB_PA2_CFG11 +.set Input_1__PA__CFG12, CYREG_UDB_PA2_CFG12 +.set Input_1__PA__CFG13, CYREG_UDB_PA2_CFG13 +.set Input_1__PA__CFG14, CYREG_UDB_PA2_CFG14 +.set Input_1__PA__CFG2, CYREG_UDB_PA2_CFG2 +.set Input_1__PA__CFG3, CYREG_UDB_PA2_CFG3 +.set Input_1__PA__CFG4, CYREG_UDB_PA2_CFG4 +.set Input_1__PA__CFG5, CYREG_UDB_PA2_CFG5 +.set Input_1__PA__CFG6, CYREG_UDB_PA2_CFG6 +.set Input_1__PA__CFG7, CYREG_UDB_PA2_CFG7 +.set Input_1__PA__CFG8, CYREG_UDB_PA2_CFG8 +.set Input_1__PA__CFG9, CYREG_UDB_PA2_CFG9 +.set Input_1__PC, CYREG_PRT2_PC +.set Input_1__PC2, CYREG_PRT2_PC2 +.set Input_1__PORT, 2 +.set Input_1__PS, CYREG_PRT2_PS +.set Input_1__SHIFT, 3 + +/* Miscellaneous */ +.set CYDEV_BCLK__HFCLK__HZ, 24000000 +.set CYDEV_BCLK__HFCLK__KHZ, 24000 +.set CYDEV_BCLK__HFCLK__MHZ, 24 +.set CYDEV_BCLK__SYSCLK__HZ, 24000000 +.set CYDEV_BCLK__SYSCLK__KHZ, 24000 +.set CYDEV_BCLK__SYSCLK__MHZ, 24 +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PSOC4A, 18 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4 +.set CYDEV_CHIP_JTAG_ID, 0x04C81193 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 18 +.set CYDEV_CHIP_MEMBER_4D, 13 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 19 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 17 +.set CYDEV_CHIP_MEMBER_4I, 23 +.set CYDEV_CHIP_MEMBER_4J, 14 +.set CYDEV_CHIP_MEMBER_4K, 15 +.set CYDEV_CHIP_MEMBER_4L, 22 +.set CYDEV_CHIP_MEMBER_4M, 21 +.set CYDEV_CHIP_MEMBER_4N, 10 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 20 +.set CYDEV_CHIP_MEMBER_4Q, 12 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 11 +.set CYDEV_CHIP_MEMBER_4T, 9 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_4V, 16 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 24 +.set CYDEV_CHIP_MEMBER_FM3, 28 +.set CYDEV_CHIP_MEMBER_FM4, 29 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4A +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1 +.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1 +.set CYDEV_CHIP_REV_TMA4_ES, 17 +.set CYDEV_CHIP_REV_TMA4_ES2, 33 +.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 +.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0 +.set CYDEV_CHIP_REVISION_4G_ES, 17 +.set CYDEV_CHIP_REVISION_4G_ES2, 33 +.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_ES, 17 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 +.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4A_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED +.set CYDEV_CONFIG_READ_ACCELERATOR, 1 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_DEBUG_PROTECT_KILL, 4 +.set CYDEV_DEBUG_PROTECT_OPEN, 1 +.set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_OPEN +.set CYDEV_DEBUG_PROTECT_PROTECTED, 2 +.set CYDEV_DEBUGGING_DPS_Disable, 3 +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD +.set CYDEV_DEBUGGING_ENABLE, 1 +.set CYDEV_DFT_SELECT_CLK0, 1 +.set CYDEV_DFT_SELECT_CLK1, 2 +.set CYDEV_HEAP_SIZE, 0x0100 +.set CYDEV_IMO_TRIMMED_BY_USB, 0 +.set CYDEV_IMO_TRIMMED_BY_WCO, 0 +.set CYDEV_IS_EXPORTING_CODE, 0 +.set CYDEV_IS_IMPORTING_CODE, 0 +.set CYDEV_PROJ_TYPE, 0 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LAUNCHER, 5 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_STACK_SIZE, 0x0400 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 0 +.set CYDEV_VDDA_MV, 5000 +.set CYDEV_VDDD_MV, 5000 +.set CYDEV_WDT_GENERATE_ISR, 0 +.set CYIPBLOCK_M0S8_CTBM_VERSION, 0 +.set CYIPBLOCK_m0s8cpuss_VERSION, 0 +.set CYIPBLOCK_m0s8csd_VERSION, 0 +.set CYIPBLOCK_m0s8gpio2_VERSION, 0 +.set CYIPBLOCK_m0s8hsiom4a_VERSION, 0 +.set CYIPBLOCK_m0s8lcd_VERSION, 0 +.set CYIPBLOCK_m0s8lpcomp_VERSION, 0 +.set CYIPBLOCK_m0s8pclk_VERSION, 0 +.set CYIPBLOCK_m0s8sar_VERSION, 0 +.set CYIPBLOCK_m0s8scb_VERSION, 0 +.set CYIPBLOCK_m0s8srssv2_VERSION, 1 +.set CYIPBLOCK_m0s8tcpwm_VERSION, 0 +.set CYIPBLOCK_m0s8udbif_VERSION, 0 +.set CYIPBLOCK_S8_GPIO_VERSION, 2 +.set CYDEV_BOOTLOADER_ENABLE, 0 +.endif diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitteriar.inc b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitteriar.inc new file mode 100644 index 0000000..2a81a83 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitteriar.inc @@ -0,0 +1,496 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#ifndef INCLUDED_CYFITTERIAR_INC +#define INCLUDED_CYFITTERIAR_INC + INCLUDE cydeviceiar_trm.inc + +/* ADC */ +ADC_cy_psoc4_sar__SAR_ANA_TRIM EQU CYREG_SAR_ANA_TRIM +ADC_cy_psoc4_sar__SAR_AVG_STAT EQU CYREG_SAR_AVG_STAT +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 EQU CYREG_SAR_CHAN_CONFIG00 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 EQU CYREG_SAR_CHAN_CONFIG01 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 EQU CYREG_SAR_CHAN_CONFIG02 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 EQU CYREG_SAR_CHAN_CONFIG03 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 EQU CYREG_SAR_CHAN_CONFIG04 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 EQU CYREG_SAR_CHAN_CONFIG05 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 EQU CYREG_SAR_CHAN_CONFIG06 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 EQU CYREG_SAR_CHAN_CONFIG07 +ADC_cy_psoc4_sar__SAR_CHAN_EN EQU CYREG_SAR_CHAN_EN +ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID EQU CYREG_SAR_CHAN_RESULT_VALID +ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 EQU CYREG_SAR_CHAN_RESULT00 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 EQU CYREG_SAR_CHAN_RESULT01 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 EQU CYREG_SAR_CHAN_RESULT02 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 EQU CYREG_SAR_CHAN_RESULT03 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 EQU CYREG_SAR_CHAN_RESULT04 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 EQU CYREG_SAR_CHAN_RESULT05 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 EQU CYREG_SAR_CHAN_RESULT06 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 EQU CYREG_SAR_CHAN_RESULT07 +ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID EQU CYREG_SAR_CHAN_WORK_VALID +ADC_cy_psoc4_sar__SAR_CHAN_WORK00 EQU CYREG_SAR_CHAN_WORK00 +ADC_cy_psoc4_sar__SAR_CHAN_WORK01 EQU CYREG_SAR_CHAN_WORK01 +ADC_cy_psoc4_sar__SAR_CHAN_WORK02 EQU CYREG_SAR_CHAN_WORK02 +ADC_cy_psoc4_sar__SAR_CHAN_WORK03 EQU CYREG_SAR_CHAN_WORK03 +ADC_cy_psoc4_sar__SAR_CHAN_WORK04 EQU CYREG_SAR_CHAN_WORK04 +ADC_cy_psoc4_sar__SAR_CHAN_WORK05 EQU CYREG_SAR_CHAN_WORK05 +ADC_cy_psoc4_sar__SAR_CHAN_WORK06 EQU CYREG_SAR_CHAN_WORK06 +ADC_cy_psoc4_sar__SAR_CHAN_WORK07 EQU CYREG_SAR_CHAN_WORK07 +ADC_cy_psoc4_sar__SAR_CTRL EQU CYREG_SAR_CTRL +ADC_cy_psoc4_sar__SAR_DFT_CTRL EQU CYREG_SAR_DFT_CTRL +ADC_cy_psoc4_sar__SAR_INTR EQU CYREG_SAR_INTR +ADC_cy_psoc4_sar__SAR_INTR_CAUSE EQU CYREG_SAR_INTR_CAUSE +ADC_cy_psoc4_sar__SAR_INTR_MASK EQU CYREG_SAR_INTR_MASK +ADC_cy_psoc4_sar__SAR_INTR_MASKED EQU CYREG_SAR_INTR_MASKED +ADC_cy_psoc4_sar__SAR_INTR_SET EQU CYREG_SAR_INTR_SET +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0 EQU CYREG_SAR_MUX_SWITCH_CLEAR0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1 EQU CYREG_SAR_MUX_SWITCH_CLEAR1 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL EQU CYREG_SAR_MUX_SWITCH_HW_CTRL +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS EQU CYREG_SAR_MUX_SWITCH_STATUS +ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 EQU CYREG_SAR_MUX_SWITCH0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH1 EQU CYREG_SAR_MUX_SWITCH1 +ADC_cy_psoc4_sar__SAR_NUMBER EQU 0 +ADC_cy_psoc4_sar__SAR_PUMP_CTRL EQU CYREG_SAR_PUMP_CTRL +ADC_cy_psoc4_sar__SAR_RANGE_COND EQU CYREG_SAR_RANGE_COND +ADC_cy_psoc4_sar__SAR_RANGE_INTR EQU CYREG_SAR_RANGE_INTR +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK EQU CYREG_SAR_RANGE_INTR_MASK +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED EQU CYREG_SAR_RANGE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET EQU CYREG_SAR_RANGE_INTR_SET +ADC_cy_psoc4_sar__SAR_RANGE_THRES EQU CYREG_SAR_RANGE_THRES +ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL EQU CYREG_SAR_SAMPLE_CTRL +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 EQU CYREG_SAR_SAMPLE_TIME01 +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 EQU CYREG_SAR_SAMPLE_TIME23 +ADC_cy_psoc4_sar__SAR_SATURATE_INTR EQU CYREG_SAR_SATURATE_INTR +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK EQU CYREG_SAR_SATURATE_INTR_MASK +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED EQU CYREG_SAR_SATURATE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET EQU CYREG_SAR_SATURATE_INTR_SET +ADC_cy_psoc4_sar__SAR_START_CTRL EQU CYREG_SAR_START_CTRL +ADC_cy_psoc4_sar__SAR_STATUS EQU CYREG_SAR_STATUS +ADC_cy_psoc4_sar__SAR_WOUNDING EQU CYREG_SAR_WOUNDING +ADC_intClock__DIVIDER_MASK EQU 0x0000FFFF +ADC_intClock__ENABLE EQU CYREG_CLK_DIVIDER_A00 +ADC_intClock__ENABLE_MASK EQU 0x80000000 +ADC_intClock__MASK EQU 0x80000000 +ADC_intClock__REGISTER EQU CYREG_CLK_DIVIDER_A00 +ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER +ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR +ADC_IRQ__INTC_MASK EQU 0x4000 +ADC_IRQ__INTC_NUMBER EQU 14 +ADC_IRQ__INTC_PRIOR_MASK EQU 0xC00000 +ADC_IRQ__INTC_PRIOR_NUM EQU 3 +ADC_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR3 +ADC_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER +ADC_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR + +/* LED */ +LED__0__DM__MASK EQU 0x1C0000 +LED__0__DM__SHIFT EQU 18 +LED__0__DR EQU CYREG_PRT1_DR +LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1 +LED__0__HSIOM_MASK EQU 0x0F000000 +LED__0__HSIOM_SHIFT EQU 24 +LED__0__INTCFG EQU CYREG_PRT1_INTCFG +LED__0__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__0__MASK EQU 0x40 +LED__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__0__PC EQU CYREG_PRT1_PC +LED__0__PC2 EQU CYREG_PRT1_PC2 +LED__0__PORT EQU 1 +LED__0__PS EQU CYREG_PRT1_PS +LED__0__SHIFT EQU 6 +LED__DR EQU CYREG_PRT1_DR +LED__INTCFG EQU CYREG_PRT1_INTCFG +LED__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__MASK EQU 0x40 +LED__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__PC EQU CYREG_PRT1_PC +LED__PC2 EQU CYREG_PRT1_PC2 +LED__PORT EQU 1 +LED__PS EQU CYREG_PRT1_PS +LED__SHIFT EQU 6 + +/* UART */ +UART_SCB__BIST_CONTROL EQU CYREG_SCB0_BIST_CONTROL +UART_SCB__BIST_DATA EQU CYREG_SCB0_BIST_DATA +UART_SCB__CTRL EQU CYREG_SCB0_CTRL +UART_SCB__EZ_DATA00 EQU CYREG_SCB0_EZ_DATA00 +UART_SCB__EZ_DATA01 EQU CYREG_SCB0_EZ_DATA01 +UART_SCB__EZ_DATA02 EQU CYREG_SCB0_EZ_DATA02 +UART_SCB__EZ_DATA03 EQU CYREG_SCB0_EZ_DATA03 +UART_SCB__EZ_DATA04 EQU CYREG_SCB0_EZ_DATA04 +UART_SCB__EZ_DATA05 EQU CYREG_SCB0_EZ_DATA05 +UART_SCB__EZ_DATA06 EQU CYREG_SCB0_EZ_DATA06 +UART_SCB__EZ_DATA07 EQU CYREG_SCB0_EZ_DATA07 +UART_SCB__EZ_DATA08 EQU CYREG_SCB0_EZ_DATA08 +UART_SCB__EZ_DATA09 EQU CYREG_SCB0_EZ_DATA09 +UART_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10 +UART_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11 +UART_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12 +UART_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13 +UART_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14 +UART_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15 +UART_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16 +UART_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17 +UART_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18 +UART_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19 +UART_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20 +UART_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21 +UART_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22 +UART_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23 +UART_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24 +UART_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25 +UART_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26 +UART_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27 +UART_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28 +UART_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29 +UART_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30 +UART_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31 +UART_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG +UART_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL +UART_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD +UART_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD +UART_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS +UART_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE +UART_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC +UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK +UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED +UART_SCB__INTR_M EQU CYREG_SCB0_INTR_M +UART_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK +UART_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED +UART_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET +UART_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX +UART_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK +UART_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED +UART_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET +UART_SCB__INTR_S EQU CYREG_SCB0_INTR_S +UART_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK +UART_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED +UART_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET +UART_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC +UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK +UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED +UART_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX +UART_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK +UART_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED +UART_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET +UART_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL +UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL +UART_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD +UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT +UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS +UART_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH +UART_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL +UART_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS +UART_SCB__SS0_POSISTION EQU 0 +UART_SCB__SS1_POSISTION EQU 1 +UART_SCB__SS2_POSISTION EQU 2 +UART_SCB__SS3_POSISTION EQU 3 +UART_SCB__STATUS EQU CYREG_SCB0_STATUS +UART_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL +UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL +UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS +UART_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR +UART_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL +UART_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL +UART_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS +UART_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL +UART_SCBCLK__DIVIDER_MASK EQU 0x0000FFFF +UART_SCBCLK__ENABLE EQU CYREG_CLK_DIVIDER_B00 +UART_SCBCLK__ENABLE_MASK EQU 0x80000000 +UART_SCBCLK__MASK EQU 0x80000000 +UART_SCBCLK__REGISTER EQU CYREG_CLK_DIVIDER_B00 +UART_tx__0__DM__MASK EQU 0x38 +UART_tx__0__DM__SHIFT EQU 3 +UART_tx__0__DR EQU CYREG_PRT4_DR +UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +UART_tx__0__HSIOM_GPIO EQU 0 +UART_tx__0__HSIOM_I2C EQU 14 +UART_tx__0__HSIOM_I2C_SDA EQU 14 +UART_tx__0__HSIOM_MASK EQU 0x000000F0 +UART_tx__0__HSIOM_SHIFT EQU 4 +UART_tx__0__HSIOM_SPI EQU 15 +UART_tx__0__HSIOM_SPI_MISO EQU 15 +UART_tx__0__HSIOM_UART EQU 9 +UART_tx__0__HSIOM_UART_TX EQU 9 +UART_tx__0__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__0__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__0__MASK EQU 0x02 +UART_tx__0__PC EQU CYREG_PRT4_PC +UART_tx__0__PC2 EQU CYREG_PRT4_PC2 +UART_tx__0__PORT EQU 4 +UART_tx__0__PS EQU CYREG_PRT4_PS +UART_tx__0__SHIFT EQU 1 +UART_tx__DR EQU CYREG_PRT4_DR +UART_tx__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__MASK EQU 0x02 +UART_tx__PC EQU CYREG_PRT4_PC +UART_tx__PC2 EQU CYREG_PRT4_PC2 +UART_tx__PORT EQU 4 +UART_tx__PS EQU CYREG_PRT4_PS +UART_tx__SHIFT EQU 1 + +/* Input_1 */ +Input_1__0__DM__MASK EQU 0xE00 +Input_1__0__DM__SHIFT EQU 9 +Input_1__0__DR EQU CYREG_PRT2_DR +Input_1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 +Input_1__0__HSIOM_MASK EQU 0x0000F000 +Input_1__0__HSIOM_SHIFT EQU 12 +Input_1__0__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__0__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__0__MASK EQU 0x08 +Input_1__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__0__PC EQU CYREG_PRT2_PC +Input_1__0__PC2 EQU CYREG_PRT2_PC2 +Input_1__0__PORT EQU 2 +Input_1__0__PS EQU CYREG_PRT2_PS +Input_1__0__SHIFT EQU 3 +Input_1__DR EQU CYREG_PRT2_DR +Input_1__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__MASK EQU 0x08 +Input_1__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__PC EQU CYREG_PRT2_PC +Input_1__PC2 EQU CYREG_PRT2_PC2 +Input_1__PORT EQU 2 +Input_1__PS EQU CYREG_PRT2_PS +Input_1__SHIFT EQU 3 + +/* Miscellaneous */ +CYDEV_BCLK__HFCLK__HZ EQU 24000000 +CYDEV_BCLK__HFCLK__KHZ EQU 24000 +CYDEV_BCLK__HFCLK__MHZ EQU 24 +CYDEV_BCLK__SYSCLK__HZ EQU 24000000 +CYDEV_BCLK__SYSCLK__KHZ EQU 24000 +CYDEV_BCLK__SYSCLK__MHZ EQU 24 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 +CYDEV_CHIP_JTAG_ID EQU 0x04C81193 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4A +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4A_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_READ_ACCELERATOR EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_PROTECT_KILL EQU 4 +CYDEV_DEBUG_PROTECT_OPEN EQU 1 +CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN +CYDEV_DEBUG_PROTECT_PROTECTED EQU 2 +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DFT_SELECT_CLK0 EQU 1 +CYDEV_DFT_SELECT_CLK1 EQU 2 +CYDEV_HEAP_SIZE EQU 0x0100 +CYDEV_IMO_TRIMMED_BY_USB EQU 0 +CYDEV_IMO_TRIMMED_BY_WCO EQU 0 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 0 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_STACK_SIZE EQU 0x0400 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_WDT_GENERATE_ISR EQU 0 +CYIPBLOCK_M0S8_CTBM_VERSION EQU 0 +CYIPBLOCK_m0s8cpuss_VERSION EQU 0 +CYIPBLOCK_m0s8csd_VERSION EQU 0 +CYIPBLOCK_m0s8gpio2_VERSION EQU 0 +CYIPBLOCK_m0s8hsiom4a_VERSION EQU 0 +CYIPBLOCK_m0s8lcd_VERSION EQU 0 +CYIPBLOCK_m0s8lpcomp_VERSION EQU 0 +CYIPBLOCK_m0s8pclk_VERSION EQU 0 +CYIPBLOCK_m0s8sar_VERSION EQU 0 +CYIPBLOCK_m0s8scb_VERSION EQU 0 +CYIPBLOCK_m0s8srssv2_VERSION EQU 1 +CYIPBLOCK_m0s8tcpwm_VERSION EQU 0 +CYIPBLOCK_m0s8udbif_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 2 +CYDEV_BOOTLOADER_ENABLE EQU 0 + +#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitterrv.inc b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitterrv.inc new file mode 100644 index 0000000..8f6f1e4 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyfitterrv.inc @@ -0,0 +1,496 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv_trm.inc + +; ADC +ADC_cy_psoc4_sar__SAR_ANA_TRIM EQU CYREG_SAR_ANA_TRIM +ADC_cy_psoc4_sar__SAR_AVG_STAT EQU CYREG_SAR_AVG_STAT +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 EQU CYREG_SAR_CHAN_CONFIG00 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 EQU CYREG_SAR_CHAN_CONFIG01 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 EQU CYREG_SAR_CHAN_CONFIG02 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 EQU CYREG_SAR_CHAN_CONFIG03 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 EQU CYREG_SAR_CHAN_CONFIG04 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 EQU CYREG_SAR_CHAN_CONFIG05 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 EQU CYREG_SAR_CHAN_CONFIG06 +ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 EQU CYREG_SAR_CHAN_CONFIG07 +ADC_cy_psoc4_sar__SAR_CHAN_EN EQU CYREG_SAR_CHAN_EN +ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID EQU CYREG_SAR_CHAN_RESULT_VALID +ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 EQU CYREG_SAR_CHAN_RESULT00 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 EQU CYREG_SAR_CHAN_RESULT01 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 EQU CYREG_SAR_CHAN_RESULT02 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 EQU CYREG_SAR_CHAN_RESULT03 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 EQU CYREG_SAR_CHAN_RESULT04 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 EQU CYREG_SAR_CHAN_RESULT05 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 EQU CYREG_SAR_CHAN_RESULT06 +ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 EQU CYREG_SAR_CHAN_RESULT07 +ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID EQU CYREG_SAR_CHAN_WORK_VALID +ADC_cy_psoc4_sar__SAR_CHAN_WORK00 EQU CYREG_SAR_CHAN_WORK00 +ADC_cy_psoc4_sar__SAR_CHAN_WORK01 EQU CYREG_SAR_CHAN_WORK01 +ADC_cy_psoc4_sar__SAR_CHAN_WORK02 EQU CYREG_SAR_CHAN_WORK02 +ADC_cy_psoc4_sar__SAR_CHAN_WORK03 EQU CYREG_SAR_CHAN_WORK03 +ADC_cy_psoc4_sar__SAR_CHAN_WORK04 EQU CYREG_SAR_CHAN_WORK04 +ADC_cy_psoc4_sar__SAR_CHAN_WORK05 EQU CYREG_SAR_CHAN_WORK05 +ADC_cy_psoc4_sar__SAR_CHAN_WORK06 EQU CYREG_SAR_CHAN_WORK06 +ADC_cy_psoc4_sar__SAR_CHAN_WORK07 EQU CYREG_SAR_CHAN_WORK07 +ADC_cy_psoc4_sar__SAR_CTRL EQU CYREG_SAR_CTRL +ADC_cy_psoc4_sar__SAR_DFT_CTRL EQU CYREG_SAR_DFT_CTRL +ADC_cy_psoc4_sar__SAR_INTR EQU CYREG_SAR_INTR +ADC_cy_psoc4_sar__SAR_INTR_CAUSE EQU CYREG_SAR_INTR_CAUSE +ADC_cy_psoc4_sar__SAR_INTR_MASK EQU CYREG_SAR_INTR_MASK +ADC_cy_psoc4_sar__SAR_INTR_MASKED EQU CYREG_SAR_INTR_MASKED +ADC_cy_psoc4_sar__SAR_INTR_SET EQU CYREG_SAR_INTR_SET +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0 EQU CYREG_SAR_MUX_SWITCH_CLEAR0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1 EQU CYREG_SAR_MUX_SWITCH_CLEAR1 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL EQU CYREG_SAR_MUX_SWITCH_HW_CTRL +ADC_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS EQU CYREG_SAR_MUX_SWITCH_STATUS +ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 EQU CYREG_SAR_MUX_SWITCH0 +ADC_cy_psoc4_sar__SAR_MUX_SWITCH1 EQU CYREG_SAR_MUX_SWITCH1 +ADC_cy_psoc4_sar__SAR_NUMBER EQU 0 +ADC_cy_psoc4_sar__SAR_PUMP_CTRL EQU CYREG_SAR_PUMP_CTRL +ADC_cy_psoc4_sar__SAR_RANGE_COND EQU CYREG_SAR_RANGE_COND +ADC_cy_psoc4_sar__SAR_RANGE_INTR EQU CYREG_SAR_RANGE_INTR +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK EQU CYREG_SAR_RANGE_INTR_MASK +ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED EQU CYREG_SAR_RANGE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET EQU CYREG_SAR_RANGE_INTR_SET +ADC_cy_psoc4_sar__SAR_RANGE_THRES EQU CYREG_SAR_RANGE_THRES +ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL EQU CYREG_SAR_SAMPLE_CTRL +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 EQU CYREG_SAR_SAMPLE_TIME01 +ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 EQU CYREG_SAR_SAMPLE_TIME23 +ADC_cy_psoc4_sar__SAR_SATURATE_INTR EQU CYREG_SAR_SATURATE_INTR +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK EQU CYREG_SAR_SATURATE_INTR_MASK +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED EQU CYREG_SAR_SATURATE_INTR_MASKED +ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET EQU CYREG_SAR_SATURATE_INTR_SET +ADC_cy_psoc4_sar__SAR_START_CTRL EQU CYREG_SAR_START_CTRL +ADC_cy_psoc4_sar__SAR_STATUS EQU CYREG_SAR_STATUS +ADC_cy_psoc4_sar__SAR_WOUNDING EQU CYREG_SAR_WOUNDING +ADC_intClock__DIVIDER_MASK EQU 0x0000FFFF +ADC_intClock__ENABLE EQU CYREG_CLK_DIVIDER_A00 +ADC_intClock__ENABLE_MASK EQU 0x80000000 +ADC_intClock__MASK EQU 0x80000000 +ADC_intClock__REGISTER EQU CYREG_CLK_DIVIDER_A00 +ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER +ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR +ADC_IRQ__INTC_MASK EQU 0x4000 +ADC_IRQ__INTC_NUMBER EQU 14 +ADC_IRQ__INTC_PRIOR_MASK EQU 0xC00000 +ADC_IRQ__INTC_PRIOR_NUM EQU 3 +ADC_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR3 +ADC_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER +ADC_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR + +; LED +LED__0__DM__MASK EQU 0x1C0000 +LED__0__DM__SHIFT EQU 18 +LED__0__DR EQU CYREG_PRT1_DR +LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1 +LED__0__HSIOM_MASK EQU 0x0F000000 +LED__0__HSIOM_SHIFT EQU 24 +LED__0__INTCFG EQU CYREG_PRT1_INTCFG +LED__0__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__0__MASK EQU 0x40 +LED__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__0__PC EQU CYREG_PRT1_PC +LED__0__PC2 EQU CYREG_PRT1_PC2 +LED__0__PORT EQU 1 +LED__0__PS EQU CYREG_PRT1_PS +LED__0__SHIFT EQU 6 +LED__DR EQU CYREG_PRT1_DR +LED__INTCFG EQU CYREG_PRT1_INTCFG +LED__INTSTAT EQU CYREG_PRT1_INTSTAT +LED__MASK EQU 0x40 +LED__PA__CFG0 EQU CYREG_UDB_PA1_CFG0 +LED__PA__CFG1 EQU CYREG_UDB_PA1_CFG1 +LED__PA__CFG10 EQU CYREG_UDB_PA1_CFG10 +LED__PA__CFG11 EQU CYREG_UDB_PA1_CFG11 +LED__PA__CFG12 EQU CYREG_UDB_PA1_CFG12 +LED__PA__CFG13 EQU CYREG_UDB_PA1_CFG13 +LED__PA__CFG14 EQU CYREG_UDB_PA1_CFG14 +LED__PA__CFG2 EQU CYREG_UDB_PA1_CFG2 +LED__PA__CFG3 EQU CYREG_UDB_PA1_CFG3 +LED__PA__CFG4 EQU CYREG_UDB_PA1_CFG4 +LED__PA__CFG5 EQU CYREG_UDB_PA1_CFG5 +LED__PA__CFG6 EQU CYREG_UDB_PA1_CFG6 +LED__PA__CFG7 EQU CYREG_UDB_PA1_CFG7 +LED__PA__CFG8 EQU CYREG_UDB_PA1_CFG8 +LED__PA__CFG9 EQU CYREG_UDB_PA1_CFG9 +LED__PC EQU CYREG_PRT1_PC +LED__PC2 EQU CYREG_PRT1_PC2 +LED__PORT EQU 1 +LED__PS EQU CYREG_PRT1_PS +LED__SHIFT EQU 6 + +; UART +UART_SCB__BIST_CONTROL EQU CYREG_SCB0_BIST_CONTROL +UART_SCB__BIST_DATA EQU CYREG_SCB0_BIST_DATA +UART_SCB__CTRL EQU CYREG_SCB0_CTRL +UART_SCB__EZ_DATA00 EQU CYREG_SCB0_EZ_DATA00 +UART_SCB__EZ_DATA01 EQU CYREG_SCB0_EZ_DATA01 +UART_SCB__EZ_DATA02 EQU CYREG_SCB0_EZ_DATA02 +UART_SCB__EZ_DATA03 EQU CYREG_SCB0_EZ_DATA03 +UART_SCB__EZ_DATA04 EQU CYREG_SCB0_EZ_DATA04 +UART_SCB__EZ_DATA05 EQU CYREG_SCB0_EZ_DATA05 +UART_SCB__EZ_DATA06 EQU CYREG_SCB0_EZ_DATA06 +UART_SCB__EZ_DATA07 EQU CYREG_SCB0_EZ_DATA07 +UART_SCB__EZ_DATA08 EQU CYREG_SCB0_EZ_DATA08 +UART_SCB__EZ_DATA09 EQU CYREG_SCB0_EZ_DATA09 +UART_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10 +UART_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11 +UART_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12 +UART_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13 +UART_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14 +UART_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15 +UART_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16 +UART_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17 +UART_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18 +UART_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19 +UART_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20 +UART_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21 +UART_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22 +UART_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23 +UART_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24 +UART_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25 +UART_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26 +UART_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27 +UART_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28 +UART_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29 +UART_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30 +UART_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31 +UART_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG +UART_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL +UART_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD +UART_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD +UART_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS +UART_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE +UART_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC +UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK +UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED +UART_SCB__INTR_M EQU CYREG_SCB0_INTR_M +UART_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK +UART_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED +UART_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET +UART_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX +UART_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK +UART_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED +UART_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET +UART_SCB__INTR_S EQU CYREG_SCB0_INTR_S +UART_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK +UART_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED +UART_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET +UART_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC +UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK +UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED +UART_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX +UART_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK +UART_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED +UART_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET +UART_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL +UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL +UART_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD +UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT +UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS +UART_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH +UART_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL +UART_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS +UART_SCB__SS0_POSISTION EQU 0 +UART_SCB__SS1_POSISTION EQU 1 +UART_SCB__SS2_POSISTION EQU 2 +UART_SCB__SS3_POSISTION EQU 3 +UART_SCB__STATUS EQU CYREG_SCB0_STATUS +UART_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL +UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL +UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS +UART_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR +UART_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL +UART_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL +UART_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS +UART_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL +UART_SCBCLK__DIVIDER_MASK EQU 0x0000FFFF +UART_SCBCLK__ENABLE EQU CYREG_CLK_DIVIDER_B00 +UART_SCBCLK__ENABLE_MASK EQU 0x80000000 +UART_SCBCLK__MASK EQU 0x80000000 +UART_SCBCLK__REGISTER EQU CYREG_CLK_DIVIDER_B00 +UART_tx__0__DM__MASK EQU 0x38 +UART_tx__0__DM__SHIFT EQU 3 +UART_tx__0__DR EQU CYREG_PRT4_DR +UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +UART_tx__0__HSIOM_GPIO EQU 0 +UART_tx__0__HSIOM_I2C EQU 14 +UART_tx__0__HSIOM_I2C_SDA EQU 14 +UART_tx__0__HSIOM_MASK EQU 0x000000F0 +UART_tx__0__HSIOM_SHIFT EQU 4 +UART_tx__0__HSIOM_SPI EQU 15 +UART_tx__0__HSIOM_SPI_MISO EQU 15 +UART_tx__0__HSIOM_UART EQU 9 +UART_tx__0__HSIOM_UART_TX EQU 9 +UART_tx__0__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__0__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__0__MASK EQU 0x02 +UART_tx__0__PC EQU CYREG_PRT4_PC +UART_tx__0__PC2 EQU CYREG_PRT4_PC2 +UART_tx__0__PORT EQU 4 +UART_tx__0__PS EQU CYREG_PRT4_PS +UART_tx__0__SHIFT EQU 1 +UART_tx__DR EQU CYREG_PRT4_DR +UART_tx__INTCFG EQU CYREG_PRT4_INTCFG +UART_tx__INTSTAT EQU CYREG_PRT4_INTSTAT +UART_tx__MASK EQU 0x02 +UART_tx__PC EQU CYREG_PRT4_PC +UART_tx__PC2 EQU CYREG_PRT4_PC2 +UART_tx__PORT EQU 4 +UART_tx__PS EQU CYREG_PRT4_PS +UART_tx__SHIFT EQU 1 + +; Input_1 +Input_1__0__DM__MASK EQU 0xE00 +Input_1__0__DM__SHIFT EQU 9 +Input_1__0__DR EQU CYREG_PRT2_DR +Input_1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 +Input_1__0__HSIOM_MASK EQU 0x0000F000 +Input_1__0__HSIOM_SHIFT EQU 12 +Input_1__0__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__0__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__0__MASK EQU 0x08 +Input_1__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__0__PC EQU CYREG_PRT2_PC +Input_1__0__PC2 EQU CYREG_PRT2_PC2 +Input_1__0__PORT EQU 2 +Input_1__0__PS EQU CYREG_PRT2_PS +Input_1__0__SHIFT EQU 3 +Input_1__DR EQU CYREG_PRT2_DR +Input_1__INTCFG EQU CYREG_PRT2_INTCFG +Input_1__INTSTAT EQU CYREG_PRT2_INTSTAT +Input_1__MASK EQU 0x08 +Input_1__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 +Input_1__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 +Input_1__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 +Input_1__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 +Input_1__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 +Input_1__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 +Input_1__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 +Input_1__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 +Input_1__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 +Input_1__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 +Input_1__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 +Input_1__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 +Input_1__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 +Input_1__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 +Input_1__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 +Input_1__PC EQU CYREG_PRT2_PC +Input_1__PC2 EQU CYREG_PRT2_PC2 +Input_1__PORT EQU 2 +Input_1__PS EQU CYREG_PRT2_PS +Input_1__SHIFT EQU 3 + +; Miscellaneous +CYDEV_BCLK__HFCLK__HZ EQU 24000000 +CYDEV_BCLK__HFCLK__KHZ EQU 24000 +CYDEV_BCLK__HFCLK__MHZ EQU 24 +CYDEV_BCLK__SYSCLK__HZ EQU 24000000 +CYDEV_BCLK__SYSCLK__KHZ EQU 24000 +CYDEV_BCLK__SYSCLK__MHZ EQU 24 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 +CYDEV_CHIP_JTAG_ID EQU 0x04C81193 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4A +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4A_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_READ_ACCELERATOR EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowWithInfo +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_PROTECT_KILL EQU 4 +CYDEV_DEBUG_PROTECT_OPEN EQU 1 +CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN +CYDEV_DEBUG_PROTECT_PROTECTED EQU 2 +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DFT_SELECT_CLK0 EQU 1 +CYDEV_DFT_SELECT_CLK1 EQU 2 +CYDEV_HEAP_SIZE EQU 0x0100 +CYDEV_IMO_TRIMMED_BY_USB EQU 0 +CYDEV_IMO_TRIMMED_BY_WCO EQU 0 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 0 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_STACK_SIZE EQU 0x0400 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_WDT_GENERATE_ISR EQU 0 +CYIPBLOCK_M0S8_CTBM_VERSION EQU 0 +CYIPBLOCK_m0s8cpuss_VERSION EQU 0 +CYIPBLOCK_m0s8csd_VERSION EQU 0 +CYIPBLOCK_m0s8gpio2_VERSION EQU 0 +CYIPBLOCK_m0s8hsiom4a_VERSION EQU 0 +CYIPBLOCK_m0s8lcd_VERSION EQU 0 +CYIPBLOCK_m0s8lpcomp_VERSION EQU 0 +CYIPBLOCK_m0s8pclk_VERSION EQU 0 +CYIPBLOCK_m0s8sar_VERSION EQU 0 +CYIPBLOCK_m0s8scb_VERSION EQU 0 +CYIPBLOCK_m0s8srssv2_VERSION EQU 1 +CYIPBLOCK_m0s8tcpwm_VERSION EQU 0 +CYIPBLOCK_m0s8udbif_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 2 +CYDEV_BOOTLOADER_ENABLE EQU 0 + ENDIF + END diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cymetadata.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/cymetadata.c new file mode 100644 index 0000000..def5fcd --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cymetadata.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: cymetadata.c +* +* PSoC Creator 4.2 +* +* Description: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "stdint.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_FLASH_PROT_SECTION +#define CY_FLASH_PROT_SECTION __attribute__ ((__section__(".cyflashprotect"), used)) +#endif +CY_FLASH_PROT_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyflashprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_flashprotect[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_META_SECTION +#define CY_META_SECTION __attribute__ ((__section__(".cymeta"), used)) +#endif +CY_META_SECTION +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_metadata[] = { + 0x00u, 0x02u, 0x04u, 0xC8u, 0x11u, 0x93u, 0x11u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_CHIP_PROT_SECTION +#define CY_CHIP_PROT_SECTION __attribute__ ((__section__(".cychipprotect"), used)) +#endif +CY_CHIP_PROT_SECTION +#elif defined(__ICCARM__) +#pragma location=".cychipprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_chipprotect[] = { + 0x01u +}; diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cypins.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cypins.h new file mode 100644 index 0000000..53a0b29 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cypins.h @@ -0,0 +1,324 @@ +/******************************************************************************* +* \file cypins.h +* \version 5.70 +* +* \brief This file contains the function prototypes and constants used for +* port/pin in access and control. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cytypes.h" + +/** +* \addtogroup group_pins Pins +* \brief For PSoC 4, there are status registers, data output registers, and port +configuration registers only, so the macro takes two arguments: port register +and pin number. Each port has these registers addresses defined: +CYREG_PRTx_DR +CYREG_PRTx_PS +CYREG_PRTx_PC + +The x is the port number, and the second argument is the pin number. + +* @{ +*/ + +/** @} group_pins */ + + +/************************************** +* Register Constants +**************************************/ + + +#define CY_SYS_PINS_PC_DATAOUT ((uint32) 0x01u) +#define CY_SYS_PINS_PC_DRIVE_MODE_BITS ((uint32) 0x03u) +#define CY_SYS_PINS_PC_DRIVE_MODE_MASK ((uint32) 0x07u) + + +/************************************** +* API Parameter Constants +**************************************/ + +/* SetPinDriveMode */ +#define CY_SYS_PINS_DM_ALG_HIZ ((uint32) 0x00u) +#define CY_SYS_PINS_DM_DIG_HIZ ((uint32) 0x01u) +#define CY_SYS_PINS_DM_RES_UP ((uint32) 0x02u) +#define CY_SYS_PINS_DM_RES_DWN ((uint32) 0x03u) +#define CY_SYS_PINS_DM_OD_LO ((uint32) 0x04u) +#define CY_SYS_PINS_DM_OD_HI ((uint32) 0x05u) +#define CY_SYS_PINS_DM_STRONG ((uint32) 0x06u) +#define CY_SYS_PINS_DM_RES_UPDWN ((uint32) 0x07u) + + +/************************************** +* Compatibility Macros +**************************************/ + +#if(CY_IP_HOBTO_DEVICE) + #define CYREG_PRT0_DR (CYREG_GPIO_PRT0_DR) + #define CYREG_PRT0_PS (CYREG_GPIO_PRT0_PS) + #define CYREG_PRT0_PC (CYREG_GPIO_PRT0_PC) + + #define CYREG_PRT1_DR (CYREG_GPIO_PRT1_DR) + #define CYREG_PRT1_PS (CYREG_GPIO_PRT1_PS) + #define CYREG_PRT1_PC (CYREG_GPIO_PRT1_PC) + + #define CYREG_PRT2_DR (CYREG_GPIO_PRT2_DR) + #define CYREG_PRT2_PS (CYREG_GPIO_PRT2_PS) + #define CYREG_PRT2_PC (CYREG_GPIO_PRT2_PC) + + #define CYREG_PRT3_DR (CYREG_GPIO_PRT3_DR) + #define CYREG_PRT3_PS (CYREG_GPIO_PRT3_PS) + #define CYREG_PRT3_PC (CYREG_GPIO_PRT3_PC) + + #define CYREG_PRT4_DR (CYREG_GPIO_PRT4_DR) + #define CYREG_PRT4_PS (CYREG_GPIO_PRT4_PS) + #define CYREG_PRT4_PC (CYREG_GPIO_PRT4_PC) + + #define CYREG_PRT5_DR (CYREG_GPIO_PRT5_DR) + #define CYREG_PRT5_PS (CYREG_GPIO_PRT5_PS) + #define CYREG_PRT5_PC (CYREG_GPIO_PRT5_PC) + + #define CYREG_PRT6_DR (CYREG_GPIO_PRT6_DR) + #define CYREG_PRT6_PS (CYREG_GPIO_PRT6_PS) + #define CYREG_PRT6_PC (CYREG_GPIO_PRT6_PC) + + #define CYREG_PRT7_DR (CYREG_GPIO_PRT7_DR) + #define CYREG_PRT7_PS (CYREG_GPIO_PRT7_PS) + #define CYREG_PRT7_PC (CYREG_GPIO_PRT7_PC) + + #define CYREG_PRT8_DR (CYREG_GPIO_PRT8_DR) + #define CYREG_PRT8_PS (CYREG_GPIO_PRT8_PS) + #define CYREG_PRT8_PC (CYREG_GPIO_PRT8_PC) + + #define CYREG_PRT9_DR (CYREG_GPIO_PRT9_DR) + #define CYREG_PRT9_PS (CYREG_GPIO_PRT9_PS) + #define CYREG_PRT9_PC (CYREG_GPIO_PRT9_PC) + + #define CYREG_PRT10_DR (CYREG_GPIO_PRT10_DR) + #define CYREG_PRT10_PS (CYREG_GPIO_PRT10_PS) + #define CYREG_PRT10_PC (CYREG_GPIO_PRT10_PC) + + #define CYREG_PRT11_DR (CYREG_GPIO_PRT11_DR) + #define CYREG_PRT11_PS (CYREG_GPIO_PRT11_PS) + #define CYREG_PRT11_PC (CYREG_GPIO_PRT11_PC) + + #define CYREG_PRT12_DR (CYREG_GPIO_PRT12_DR) + #define CYREG_PRT12_PS (CYREG_GPIO_PRT12_PS) + #define CYREG_PRT12_PC (CYREG_GPIO_PRT12_PC) + + #define CYREG_PRT13_DR (CYREG_GPIO_PRT13_DR) + #define CYREG_PRT13_PS (CYREG_GPIO_PRT13_PS) + #define CYREG_PRT13_PC (CYREG_GPIO_PRT13_PC) + + #define CYREG_PRT14_DR (CYREG_GPIO_PRT14_DR) + #define CYREG_PRT14_PS (CYREG_GPIO_PRT14_PS) + #define CYREG_PRT14_PC (CYREG_GPIO_PRT14_PC) + + #define CYREG_PRT15_DR (CYREG_GPIO_PRT15_DR) + #define CYREG_PRT15_PS (CYREG_GPIO_PRT15_PS) + #define CYREG_PRT15_PC (CYREG_GPIO_PRT15_PC) + +#else + + #define CYREG_GPIO_PRT0_DR (CYREG_PRT0_DR) + #define CYREG_GPIO_PRT0_PS (CYREG_PRT0_PS) + #define CYREG_GPIO_PRT0_PC (CYREG_PRT0_PC) + + #define CYREG_GPIO_PRT1_DR (CYREG_PRT1_DR) + #define CYREG_GPIO_PRT1_PS (CYREG_PRT1_PS) + #define CYREG_GPIO_PRT1_PC (CYREG_PRT1_PC) + + #define CYREG_GPIO_PRT2_DR (CYREG_PRT2_DR) + #define CYREG_GPIO_PRT2_PS (CYREG_PRT2_PS) + #define CYREG_GPIO_PRT2_PC (CYREG_PRT2_PC) + + #define CYREG_GPIO_PRT3_DR (CYREG_PRT3_DR) + #define CYREG_GPIO_PRT3_PS (CYREG_PRT3_PS) + #define CYREG_GPIO_PRT3_PC (CYREG_PRT3_PC) + + #define CYREG_GPIO_PRT4_DR (CYREG_PRT4_DR) + #define CYREG_GPIO_PRT4_PS (CYREG_PRT4_PS) + #define CYREG_GPIO_PRT4_PC (CYREG_PRT4_PC) +#endif /* (CY_IP_HOBTO_DEVICE) */ + + +/************************************** +* Pin API Macros +**************************************/ + +/** +* \defgroup group_pins Pins +* @{ +*/ + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_READ_PIN +****************************************************************************//** +* +* Reads the current value on the pin (pin state, PS). +* +* \param portPS Address of the port pin status register (uint32). Definitions +* for each port are provided in the cydevice_trm.h file in the form: +* CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends on the +* selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +* \return Zero - logic low, non-zero - logic high. +* +*******************************************************************************/ +#define CY_SYS_PINS_READ_PIN(portPS, pin) \ + (( *(reg32 *)(portPS) >> (pin)) & CY_SYS_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_SET_PIN +****************************************************************************//** +* +* Set the output value for the pin (data register, DR) to a logic high. +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portDR Address of the port output pin data register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends +* on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +*******************************************************************************/ +#define CY_SYS_PINS_SET_PIN(portDR, pin) \ + ( *(reg32 *)(portDR) |= (CY_SYS_PINS_PC_DATAOUT << (pin)) ) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_CLEAR_PIN +****************************************************************************//** +* +* This macro sets the state of the specified pin to zero. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portDR Address of the port output pin data register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number +* depends on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected device. +* +*******************************************************************************/ +#define CY_SYS_PINS_CLEAR_PIN(portDR, pin) \ + ( *(reg32 *)(portDR) &= ~(CY_SYS_PINS_PC_DATAOUT << (pin)) ) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_SET_DRIVE_MODE +****************************************************************************//** +* +* Sets the drive mode for the pin (DM). +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portPC: Address of the port configuration register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number +* depends on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected device. +* +* \param mode Desired drive mode. +* +* Define Source +* CY_SYS_PINS_DM_ALG_HIZ Analog HiZ +* CY_SYS_PINS_DM_DIG_HIZ Digital HiZ +* CY_SYS_PINS_DM_RES_UP Resistive pull up +* CY_SYS_PINS_DM_RES_DWN Resistive pull down +* CY_SYS_PINS_DM_OD_LO Open drain - drive low +* CY_SYS_PINS_DM_OD_HI Open drain - drive high +* CY_SYS_PINS_DM_STRONG Strong CMOS Output +* CY_SYS_PINS_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CY_SYS_PINS_SET_DRIVE_MODE(portPC, pin, mode) \ + ( *(reg32 *)(portPC) = (*(reg32 *)(portPC) & \ + ~(CY_SYS_PINS_PC_DRIVE_MODE_MASK << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS))) | \ + ((mode) << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS))) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_READ_DRIVE_MODE +****************************************************************************//** +* +* Reads the drive mode for the pin (DM). +* +* \param portPC Address of the port configuration register (uint32). Definitions +* for each port are provided in the cydevice_trm.h file in the form: +* CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends on the +* selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +* \return mode Current drive mode for the pin: +* - CY_SYS_PINS_DM_ALG_HIZ Analog HiZ +* - CY_SYS_PINS_DM_DIG_HIZ Digital HiZ +* - CY_SYS_PINS_DM_RES_UP Resistive pull up +* - CY_SYS_PINS_DM_RES_DWN Resistive pull down +* - CY_SYS_PINS_DM_OD_LO Open drain - drive low +* - CY_SYS_PINS_DM_OD_HI Open drain - drive high +* - CY_SYS_PINS_DM_STRONG Strong CMOS Output +* - CY_SYS_PINS_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CY_SYS_PINS_READ_DRIVE_MODE(portPC, pin) \ + (( *(reg32 *)(portPC) & \ + (CY_SYS_PINS_PC_DRIVE_MODE_MASK << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS)) ) >> \ + (pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS) + +/** @} group_pins */ + +/* Defines function macros for mapping PSoC 4 per-pin functions to PSoC 3/5LP style functions */ +#define CyPins_ReadPin(name) (CY_SYS_PINS_READ_PIN (name ## _PS, name ## _SHIFT)) +#define CyPins_SetPin(name) (CY_SYS_PINS_SET_PIN (name ## _DR, name ## _SHIFT)) +#define CyPins_ClearPin(name) (CY_SYS_PINS_CLEAR_PIN (name ## _DR, name ## _SHIFT)) +#define CyPins_SetPinDriveMode(name, mode) (CY_SYS_PINS_SET_DRIVE_MODE (name ## _PC, name ## _SHIFT, mode)) +#define CyPins_ReadPinDriveMode(name) (CY_SYS_PINS_READ_DRIVE_MODE(name ## _PC, name ## _SHIFT)) + + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cytypes.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/cytypes.h new file mode 100644 index 0000000..d5b3a84 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cytypes.h @@ -0,0 +1,1496 @@ +/***************************************************************************//** +* \file cytypes.h +* \version 5.70 +* +* \brief CyTypes provides register access macros and approved types for use in +* firmware. +* +* \note Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of the type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) +#else + #define CY_PSOC4_4000 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) + +#ifdef CYDEV_CHIP_MEMBER_4F + #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) + #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) +#else + #define CY_PSOC4_4100BL (0u != 0u) + #define CY_PSOC4_4200BL (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4F */ + +#ifdef CYDEV_CHIP_MEMBER_4M + #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) + #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) +#else + #define CY_PSOC4_4100M (0u != 0u) + #define CY_PSOC4_4200M (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4M */ + +#ifdef CYDEV_CHIP_MEMBER_4H + #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H) +#else + #define CY_PSOC4_4200D (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4H */ + +#ifdef CYDEV_CHIP_MEMBER_4L + #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L) +#else + #define CY_PSOC4_4200L (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4L */ + +#ifdef CYDEV_CHIP_MEMBER_4U + #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U) +#else + #define CY_PSOC4_4000U (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4U */ + +#ifdef CYDEV_CHIP_MEMBER_4J + #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J) +#else + #define CY_PSOC4_4000S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4J */ + +#ifdef CYDEV_CHIP_MEMBER_4K + #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K) +#else + #define CY_PSOC4_4100S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4K */ + +#ifdef CYDEV_CHIP_MEMBER_4I + #define CY_PSOC4_4400 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4I) +#else + #define CY_PSOC4_4400 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4I */ + +#ifdef CYDEV_CHIP_MEMBER_4E + #define CY_CCG2 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4E) +#else + #define CY_CCG2 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4E */ + +#ifdef CYDEV_CHIP_MEMBER_4O + #define CY_CCG3 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4O) +#else + #define CY_CCG3 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4O */ + +#ifdef CYDEV_CHIP_MEMBER_4R + #define CY_CCG3PA (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4R) +#else + #define CY_CCG3PA (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4R */ + +#ifdef CYDEV_CHIP_MEMBER_4N + #define CY_CCG4 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4N) +#else + #define CY_CCG4 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4N */ + +#ifdef CYDEV_CHIP_MEMBER_4S + #define CY_CCG5 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4S) +#else + #define CY_CCG5 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4S */ + +#ifdef CYDEV_CHIP_MEMBER_4P + #define CY_PSOC4_4100BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) + #define CY_PSOC4_4200BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) +#else + #define CY_PSOC4_4100BLII (0u != 0u) + #define CY_PSOC4_4200BLII (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4P */ + +#ifdef CYDEV_CHIP_MEMBER_4V + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) +#else + #define CY_PSOC4_4100MS (0u != 0u) + #define CY_PSOC4_4100MS (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4V */ + +#define CY_IP_HOBTO_DEVICE (!(1 == 1)) + + +/******************************************************************************* +* IP blocks +*******************************************************************************/ +#if (CY_PSOC4) + + /* Using SRSSv2 or SRS-Lite */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_SRSSV2 (1 != 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #else + #define CY_IP_SRSSV2 (0 == 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSSV3 (0 == 1) + #define CY_IP_CPUSSV2 (0 == 1) + #define CY_IP_CPUSS (1 == 1) + #else + #define CY_IP_CPUSSV3 (0 != 0) + #define CY_IP_CPUSSV2 (0 != 0) + #define CY_IP_CPUSS (0 == 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_CPUSS_CM0 (0 == 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_CPUSS_CM0 (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0) + #else + #define CY_IP_CPUSS_CM0 (0 == 0) + #define CY_IP_CPUSS_CM0PLUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash memory present or not (1=Flash present, 0=Flash not present) */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0) + #else + #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Product uses FLASH-Lite or regular FLASH */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */ + #define CY_IP_FS (0 != 0) /* FS */ + #define CY_IP_FSLT (0 != 0) /* FSLT */ + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Enable simultaneous execution/programming in multi-macro devices */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_MACROS (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_MACROS (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_MACROS (1u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Number of interrupt request inputs to CM0 */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_INT_NR (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_INT_NR (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_INT_NR (32u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Presence of the BLESS IP block */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (CYIPBLOCK_m0s8bless_VERSION == 3) + #else + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_USBDEV (0 != 0) + #else + #define CY_IP_USBDEV (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /*************************************************************************** + * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use + * the 36MHz Oscillator for Flash operation. Instead, flash write function + * ensures that the charge pump clock and the higher frequency clock (HFCLK) + * are set to the IMO at 48MHz prior to writing the flash. + ***************************************************************************/ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Watch Crystal Oscillator (WCO) is present (32kHz) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #if (CY_IP_BLESSV3) + #define CY_IP_WCO_WCOV2 (0 == 0) + #define CY_IP_WCO_BLESS (0 != 0) + #else + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_BLESS (0 == 0) + #endif + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 == 1) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_WCOV2 || CY_IP_WCO_SRSSV2) + + /* External Crystal Oscillator is present (high frequency) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + + #if (CY_IP_BLESSV3) + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 == 0) + #else + #define CY_IP_ECO_BLESS (0 == 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #endif + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (-1 == 1) + #define CY_IP_ECO_SRSSLT ((0 != 0) && (0 != 0)) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2 || CY_IP_ECO_BLESSV3 || CY_IP_ECO_SRSSLT) + + /* PLL is present */ + #if (CY_IP_HOBTO_DEVICE) + #if(CY_IP_SRSSV2) + #define CY_IP_PLL ((-1 != 0) || \ + (-1 != 0)) + + #define CY_IP_PLL_NR (-1u + \ + -1u) + + #elif (CY_IP_SRSSLT) + #define CY_IP_PLL (-1 == 1) + + #define CY_IP_PLL_NR (1) + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_SRSSV2) */ + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash Macro 0 has extra rows */ + #if (CY_IP_HOBTO_DEVICE) + #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0 + #define CY_SFLASH_XTRA_ROWS (0 == 0) + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */ + + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_USBDEV) + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0) + #endif /* (CY_IP_USBDEV) */ + + + #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0) + #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */ + + + /* DW/DMA Controller present (0=No, 1=Yes) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_DMAC_PRESENT (-1 == 1) + #else + #define CY_IP_DMAC_PRESENT (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_DMAC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_PASS (0 == 1) + #else + #define CY_IP_PASS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + + /* Number of external slave ports on System Interconnect */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SL_NR (-1) + #else + #define CY_IP_SL_NR (-1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + +#else + + #if (CY_PSOC3) + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #else /* PSoC 5LP */ + #define CY_SYSTICK_LFCLK_SOURCE (0 == 0) + #endif /* (CY_PSOC3) */ + +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* The components version defines. Available started from cy_boot 4.20 +* Use the following construction in order to identify cy_boot version: +* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20) +*******************************************************************************/ +#define CY_BOOT_4_20 (420u) +#define CY_BOOT_5_0 (500u) +#define CY_BOOT_5_10 (510u) +#define CY_BOOT_5_20 (520u) +#define CY_BOOT_5_30 (530u) +#define CY_BOOT_5_40 (540u) +#define CY_BOOT_5_50 (550u) +#define CY_BOOT_5_60 (560u) +#define CY_BOOT_5_70 (570u) +#define CY_BOOT_VERSION (CY_BOOT_5_70) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + + /* Specifies a minimum alignment (in bytes) for variables of the + * specified type. + */ + #define CY_ALIGN(align) __align(align) + + + /* Attached to an enum, struct, or union type definition, specified that + * the minimum required memory be used to represent the type. + */ + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE __inline + #elif defined (__GNUC__) + + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE inline + #elif defined (__ICCARM__) + + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #define CY_PACKED __packed + #define CY_PACKED_ATTR + #define CY_INLINE inline + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +#define CY_M_PI (3.14159265358979323846264338327) + + +/** +* \addtogroup group_register_access +A library of macros provides read and write access to the registers of the device. These macros are used with the +defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made +using these macros and not the functions that are used to implement the macros. This allows for device independent code +generation. + +The PSoC 4 processor architecture use little endian ordering. + +SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However, +the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this +little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider +the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers, +as well as function calls that are passed an array of bytes in memory. + +The PSoC 4 requires these accesses to be aligned to the width of the transaction. + +The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might +ignore the transfer and Hard Fault exception will be generated. + +*/ + +/** @} group_register_access */ + + +/** +* \addtogroup group_register_access_macros Register Access +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC3) + /******************************************************************************* + * Macro Name: CY_GET_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * Identical to \ref CY_GET_REG8 for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * Identical to \ref CY_SET_REG8 for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ +/** @} group_register_access_macros */ + + +/** +* \addtogroup group_register_access_bits Bit Manipulation +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC4) + + /******************************************************************************* + * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName) + ****************************************************************************//** + * + * Returns the bit field mask for the specified register size and bit field + * name. + * + * \param regSize Size of the register in bits. + * \param bitFieldName Fully qualified name of the bit field. The biFieldName + * is automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * \return Returns the bit mask. + * + *******************************************************************************/ + #define CY_GET_FIELD_MASK(regSize, bitFieldName) \ + ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\ + ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET) + + + /******************************************************************************* + * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register will remain uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on 32-bit and 16-bit width registers will generate a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG8_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 8-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers, generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG8((registerName), \ + ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \ + (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \ + (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hardfault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG16_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 16-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerNam The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG16((registerName), \ + ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \ + (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\ + (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The Fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields, please, refer to + * a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, otherwise. + * The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG32_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 32-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG32((registerName), \ + ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \ + (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \ + (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_FIELD(regValue, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_FIELD(regValue, bitFieldName) \ + (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value within a given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads and \ref CY_SET_REG32 for atomic writes. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to the respective PSoC family register TRM. + * + *******************************************************************************/ + #define CY_SET_FIELD(regValue, bitFieldName, value) \ + ((regValue) = \ + ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \ + ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET))) + +#endif /* (CY_PSOC4) */ + +/** @} group_register_access_bits */ + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu))) + + +/******************************************************************************* +* Defines the standard return values used in PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 5.10 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_IP_S8FS CY_IP_FS + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ +#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#define CY_UDB_V1 (!CY_UDB_V0) +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + +#if (!CY_PSOC4) + + /* Device is PSoC 3 and the revision is ES2 or earlier */ + #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + + /* Device is PSoC 3 and the revision is ES3 or later */ + #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + + /* Device is PSoC 5 and the revision is ES1 or earlier */ + #define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + + /* Device is PSoC 5 and the revision is ES2 or later */ + #define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* (!CY_PSOC4) */ + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/cyutils.c b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyutils.c new file mode 100644 index 0000000..a9eb657 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/cyutils.c @@ -0,0 +1,75 @@ +/***************************************************************************//** +* \file cyutils.c +* \version 5.70 +* +* \brief Provides a function to handle 24-bit value writes. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + ************************************************************************//** + * + * Writes a 24-bit value to the specified register. + * + * \param addr The address where data must be written. + * \param value The data that must be written. + * + * \reentrant No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + ************************************************************************//** + * + * Reads the 24-bit value from the specified register. + * + * \param addr The address where data must be read. + * + * \reentrant No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 const volatile * addr) + { + uint8 const volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 const volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/device.lib b/TrainingProjects/ADC-UART.cydsn/codegentemp/device.lib new file mode 100644 index 0000000..845d03a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/device.lib @@ -0,0 +1,1640 @@ +/* + Copyright Cypress Semiconductor Corporation, 2010-2011 +*/ +/*library (p4) { + + timescale : 1ns; +*/ + + cell (m0s8clockblockcell) { + pin (imo) { direction : output; } + pin (ext) { direction : output; } + pin (eco) { direction : output; } + pin (ilo) { direction : output; } + pin (wco) { direction : output; } + pin (dbl) { direction : output; } + pin (pll) { direction : output; } + pin (dpll) { direction : output; } + /* TODO: these are backwards from the diagram */ + bundle (dsi_out) { + members (dsi_out_0, dsi_out_1, dsi_out_2, dsi_out_3); + direction : input; + } + bundle (dsi_in) { + members (dsi_in_0, dsi_in_1, dsi_in_2, dsi_in_3); + direction : output; + } + pin (lfclk) { direction : output; } + pin (hfclk) { direction : output; } + pin (sysclk) { direction : output; } + pin (halfsysclk) { direction : output; } + /* TODO: name doesn't match SAS (clk_udbN) */ + bundle (udb_div) { + members (udb_div_0, udb_div_1, udb_div_2, udb_div_3, + udb_div_4, udb_div_5, udb_div_6, udb_div_7); + direction : output; + } + /* TODO: name doesn't match SAS (clk_uabN) */ + bundle (uab_div) { + members (uab_div_0, uab_div_1, uab_div_2, uab_div_3, + uab_div_4, uab_div_5, uab_div_6, uab_div_7); + direction : output; + } + /* TODO: name doesn't match SAS (clk_ffN) */ + bundle (ff_div) { + members (ff_div_0, ff_div_1, ff_div_2, ff_div_3, + ff_div_4, ff_div_5, ff_div_6, ff_div_7); + direction : output; + } + } + + cell (m0s8clockgenblockcell) { + bundle (gen_clk_in) { + members (gen_clk_in_0, gen_clk_in_1, gen_clk_in_2, gen_clk_in_3, + gen_clk_in_4, gen_clk_in_5, gen_clk_in_6, gen_clk_in_7); + direction : input; + } + pin (gen_clk_out_0) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_0"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (gen_clk_out_1) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_1"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (gen_clk_out_2) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_2"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (gen_clk_out_3) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_3"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (gen_clk_out_4) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_4"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (gen_clk_out_5) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_5"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (gen_clk_out_6) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_6"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (gen_clk_out_7) { + direction : output; + timing() { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "gen_clk_in_7"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + } + + cell (carrycell) { + } + + cell (armcell) { + pin (nmi) { + direction : input; + } + } + + cell (interrupt) { + pin (clock) { + direction : input; + clock : true; + } + pin (interrupt) { + direction : input; + } + } + + cell (logicalport) { + pin (interrupt) { + direction : output; + } + pin (precharge) { + direction : input; + } + pin (in_clock) { + direction : input; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + } + + cell (count7cell) { + pin (clock) { + direction : input; + clock : true; + } + pin (clock_n) { + direction : input; + clock : true; + } + pin (extclk) { + direction : input; + clock : true; + } + pin (extclk_n) { + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing() { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.1; + intrinsic_fall : 2.1; + } + timing() { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "clock_n"; + intrinsic_rise : 2.1; + intrinsic_fall : 2.1; + } + timing() { + timing_type : hold_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_rising; + related_pin : "extclk"; + intrinsic_rise : 0; + intrinsic_fall : 0; + } + timing() { + timing_type : hold_rising; + related_pin : "extclk"; + intrinsic_rise : 0.6; + intrinsic_fall : 0.6; + } + timing() { + timing_type : setup_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0; + intrinsic_fall : 0; + } + timing() { + timing_type : hold_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.6; + intrinsic_fall : 0.6; + } + } + pin (reset) { + direction : input; + timing() { + timing_type : recovery_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : recovery_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : recovery_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : recovery_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (load) { + direction : input; + timing() { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 4.22; + intrinsic_fall : 4.22; + } + timing() { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "clock_n"; + intrinsic_rise : 4.22; + intrinsic_fall : 4.22; + } + timing() { + timing_type : hold_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_rising; + related_pin : "extclk"; + intrinsic_rise : 6.22; + intrinsic_fall : 6.22; + } + timing() { + timing_type : hold_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "extclk_n"; + intrinsic_rise : 6.22; + intrinsic_fall : 6.22; + } + timing() { + timing_type : hold_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (enable) { + direction : input; + timing() { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 3.34; + intrinsic_fall : 3.34; + } + timing() { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "clock_n"; + intrinsic_rise : 3.34; + intrinsic_fall : 3.34; + } + timing() { + timing_type : hold_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_rising; + related_pin : "extclk"; + intrinsic_rise : 5.34; + intrinsic_fall : 5.34; + } + timing() { + timing_type : hold_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "extclk_n"; + intrinsic_rise : 5.34; + intrinsic_fall : 5.34; + } + timing() { + timing_type : hold_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + bundle (count) { + members (count_0, count_1, count_2, count_3, count_4, count_5, count_6); + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.11; + intrinsic_fall : 2.11; + } + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.92; + intrinsic_fall : 1.92; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 2.11; + intrinsic_fall : 2.11; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 1.92; + intrinsic_fall : 1.92; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 4.11; + intrinsic_fall : 4.11; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 3.92; + intrinsic_fall : 3.92; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 4.11; + intrinsic_fall : 4.11; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 3.92; + intrinsic_fall : 3.92; + } + timing() { + timing_type : clear; + timing_sense : negative_unate; + related_pin : "reset"; + intrinsic_rise : 7.57; + intrinsic_fall : 7.57; + } + timing() { + timing_type : clear; + timing_sense : negative_unate; + related_pin : "reset"; + intrinsic_rise : 6.24; + intrinsic_fall : 6.24; + } + } + pin (tc) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.58; + intrinsic_fall : 2.58; + } + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.04; + intrinsic_fall : 2.04; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 2.58; + intrinsic_fall : 2.58; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 2.04; + intrinsic_fall : 2.04; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 4.58; + intrinsic_fall : 4.58; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 4.04; + intrinsic_fall : 4.04; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 4.58; + intrinsic_fall : 4.58; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 4.04; + intrinsic_fall : 4.04; + } + timing() { + timing_type : preset; + timing_sense : positive_unate; + related_pin : "reset"; + intrinsic_rise : 8.02; + intrinsic_fall : 8.02; + } + timing() { + timing_type : preset; + timing_sense : positive_unate; + related_pin : "reset"; + intrinsic_rise : 6.19; + intrinsic_fall : 6.19; + } + } + } + + cell (count7cell_alt) { + pin (clock) { + direction : input; + clock : true; + } + pin (clock_n) { + direction : input; + clock : true; + } + pin (extclk) { + direction : input; + clock : true; + } + pin (extclk_n) { + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing() { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.1; + intrinsic_fall : 2.1; + } + timing() { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "clock_n"; + intrinsic_rise : 2.1; + intrinsic_fall : 2.1; + } + timing() { + timing_type : hold_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_rising; + related_pin : "extclk"; + intrinsic_rise : 0; + intrinsic_fall : 0; + } + timing() { + timing_type : hold_rising; + related_pin : "extclk"; + intrinsic_rise : 0.6; + intrinsic_fall : 0.6; + } + timing() { + timing_type : setup_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0; + intrinsic_fall : 0; + } + timing() { + timing_type : hold_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.6; + intrinsic_fall : 0.6; + } + } + pin (reset) { + direction : input; + timing() { + timing_type : recovery_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : recovery_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : recovery_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : recovery_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : removal_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (load) { + direction : input; + timing() { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 4.22; + intrinsic_fall : 4.22; + } + timing() { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "clock_n"; + intrinsic_rise : 4.22; + intrinsic_fall : 4.22; + } + timing() { + timing_type : hold_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_rising; + related_pin : "extclk"; + intrinsic_rise : 6.22; + intrinsic_fall : 6.22; + } + timing() { + timing_type : hold_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "extclk_n"; + intrinsic_rise : 6.22; + intrinsic_fall : 6.22; + } + timing() { + timing_type : hold_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (enable) { + direction : input; + timing() { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 3.34; + intrinsic_fall : 3.34; + } + timing() { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "clock_n"; + intrinsic_rise : 3.34; + intrinsic_fall : 3.34; + } + timing() { + timing_type : hold_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_rising; + related_pin : "extclk"; + intrinsic_rise : 5.34; + intrinsic_fall : 5.34; + } + timing() { + timing_type : hold_rising; + related_pin : "extclk"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "extclk_n"; + intrinsic_rise : 5.34; + intrinsic_fall : 5.34; + } + timing() { + timing_type : hold_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + bundle (count) { + members (count_0, count_1, count_2, count_3, count_4, count_5, count_6); + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.11; + intrinsic_fall : 2.11; + } + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.92; + intrinsic_fall : 1.92; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 2.11; + intrinsic_fall : 2.11; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 1.92; + intrinsic_fall : 1.92; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 4.11; + intrinsic_fall : 4.11; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 3.92; + intrinsic_fall : 3.92; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 4.11; + intrinsic_fall : 4.11; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 3.92; + intrinsic_fall : 3.92; + } + timing() { + timing_type : clear; + timing_sense : negative_unate; + related_pin : "reset"; + intrinsic_rise : 7.57; + intrinsic_fall : 7.57; + } + timing() { + timing_type : clear; + timing_sense : negative_unate; + related_pin : "reset"; + intrinsic_rise : 6.24; + intrinsic_fall : 6.24; + } + } + pin (tc) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.58; + intrinsic_fall : 3.58; + } + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.04; + intrinsic_fall : 2.04; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 3.58; + intrinsic_fall : 3.58; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n"; + intrinsic_rise : 2.04; + intrinsic_fall : 2.04; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 5.58; + intrinsic_fall : 5.58; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk"; + intrinsic_rise : 4.04; + intrinsic_fall : 4.04; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 5.58; + intrinsic_fall : 5.58; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n"; + intrinsic_rise : 4.04; + intrinsic_fall : 4.04; + } + timing() { + timing_type : preset; + timing_sense : positive_unate; + related_pin : "reset"; + intrinsic_rise : 8.02; + intrinsic_fall : 8.02; + } + timing() { + timing_type : preset; + timing_sense : positive_unate; + related_pin : "reset"; + intrinsic_rise : 6.19; + intrinsic_fall : 6.19; + } + } + } + + cell (synccell) { + pin (clock) { + direction : input; + clock : true; + } + + pin (clock_n) { + direction : input; + clock : true; + } + + pin (extclk) { + direction : input; + clock : true; + } + + pin (extclk_n) { + direction : input; + clock : true; + } + + pin (clk_en) { + direction : input; + timing() { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.1; + intrinsic_fall : 2.1; + } + timing() { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_falling; + related_pin : "clock_n"; + intrinsic_rise : 2.1; + intrinsic_fall : 2.1; + } + timing() { + timing_type : hold_falling; + related_pin : "clock_n"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing() { + timing_type : setup_rising; + related_pin : "extclk"; + intrinsic_rise : 0; + intrinsic_fall : 0; + } + timing() { + timing_type : hold_rising; + related_pin : "extclk"; + intrinsic_rise : 0.6; + intrinsic_fall : 0.6; + } + timing() { + timing_type : setup_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0; + intrinsic_fall : 0; + } + timing() { + timing_type : hold_falling; + related_pin : "extclk_n"; + intrinsic_rise : 0.6; + intrinsic_fall : 0.6; + } + } + + pin (in) { + direction : input; + } + + pin (out) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock" + intrinsic_rise : 1.48; + intrinsic_fall : 1.48; + } + timing() { + timing_type : rising_edge; + related_pin : "clock" + intrinsic_rise : 1; + intrinsic_fall : 1; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n" + intrinsic_rise : 1.48; + intrinsic_fall : 1.48; + } + timing() { + timing_type : falling_edge; + related_pin : "clock_n" + intrinsic_rise : 1; + intrinsic_fall : 1; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk" + intrinsic_rise : 3.48; + intrinsic_fall : 3.48; + } + timing() { + timing_type : rising_edge; + related_pin : "extclk" + intrinsic_rise : 3; + intrinsic_fall : 3; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n" + intrinsic_rise : 3.48; + intrinsic_fall : 3.48; + } + timing() { + timing_type : falling_edge; + related_pin : "extclk_n" + intrinsic_rise : 3; + intrinsic_fall : 3; + } + } + } + + cell (sarcell) { + pin (clock) { direction : input; } + pin (clk_udb) { direction : input; } + pin (sof_udb) { direction : input; } + pin (vp_ctl_udb_0) { direction : input; } + pin (vp_ctl_udb_1) { direction : input; } + pin (vp_ctl_udb_2) { direction : input; } + pin (vp_ctl_udb_3) { direction : input; } + pin (vn_ctl_udb_0) { direction : input; } + pin (vn_ctl_udb_1) { direction : input; } + pin (vn_ctl_udb_2) { direction : input; } + pin (vn_ctl_udb_3) { direction : input; } + pin (data_out_udb_0) { direction : output; } + pin (data_out_udb_1) { direction : output; } + pin (data_out_udb_2) { direction : output; } + pin (data_out_udb_3) { direction : output; } + pin (data_out_udb_4) { direction : output; } + pin (data_out_udb_5) { direction : output; } + pin (data_out_udb_6) { direction : output; } + pin (data_out_udb_7) { direction : output; } + pin (data_out_udb_8) { direction : output; } + pin (data_out_udb_9) { direction : output; } + pin (data_out_udb_10) { direction : output; } + pin (data_out_udb_11) { direction : output; } + pin (eof_udb) { direction : output; } + pin (irq) { direction : output; } + } + + cell (ssccell) { + pin (rst_n) { direction : input; } + pin (scli) { direction : input; } + pin (sdai) { direction : input; } + pin (csel) { direction : input; } + pin (sclo) { direction : output; } + pin (sdao) { direction : output; } + pin (irq) { direction : output; } + } + + cell (m0s8lcdcell) { + bundle (com) { + members (com_0, com_1, com_2, com_3, + com_4, com_5, com_6, com_7, + com_8, com_9, com_10, com_11, + com_12, com_13, com_14, com_15); + direction : output; + } + bundle (seg) { + members (seg_0, seg_1, seg_2, seg_3, + seg_4, seg_5, seg_6, seg_7, + seg_8, seg_9, seg_10, seg_11, + seg_12, seg_13, seg_14, seg_15, + seg_16, seg_17, seg_18, seg_19, + seg_20, seg_21, seg_22, seg_23, + seg_24, seg_25, seg_26, seg_27, + seg_28, seg_29, seg_30, seg_31, + seg_32, seg_33, seg_34, seg_35, + seg_36, seg_37, seg_38, seg_39, + seg_40, seg_41, seg_42, seg_43, + seg_44, seg_45, seg_46, seg_47, + seg_48, seg_49, seg_50, seg_51, + seg_52, seg_53, seg_54, seg_55, + seg_56, seg_57, seg_58, seg_59, + seg_60, seg_61, seg_62, seg_63); + direction : output; + } + pin (clock) { + direction : input; + clock : true; + } + } + + cell (m0s8scbcell) { + pin (clock) { + direction : input; + clock : true; + } + pin (interrupt) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (uart_cts) { direction : input; } + pin (uart_rts) { direction : output; } + pin (uart_rx) { direction : input; } + pin (uart_tx) { direction : output; } + pin (mosi_m) { direction : output; } + pin (miso_m) { direction : input; } + bundle (select) { + members (select_m_0, select_m_1, select_m_2, select_m_3); + direction : output; + } + pin (sclk_m) { direction : output; } + pin (mosi_s) { direction : input; } + pin (miso_s) { direction : output; } + pin (select_s) { direction : input; } + pin (sclk_s) { direction : input; } + pin (i2c_scl) { direction : inout; } + pin (i2c_sda) { direction : inout; } + pin (tr_rx_req) { direction : output; } + pin (tr_tx_req) { direction : output; } + } + + cell (m0s8tcpwmcell) { + pin (clock) { + direction : input; + clock : true; + } + pin (capture) { direction : input; } + pin (count) { direction : input; } + pin (reload) { direction : input; } + pin (stop) { direction : input; } + pin (start) { direction : input; } + pin (tr_underflow) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (tr_overflow) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (tr_compare_match) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (line) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (line_compl) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (interrupt) { direction : output; } + } + + cell (m0s8tsscell) { + /* TODO: names don't match DSI file */ + pin (clk_seq) { direction : input; clock : true; } + pin (clk_adc) { direction : input; clock : true; } + + /* Non-routable, optional, pin inputs */ + pin (ext_reject) { direction : input; } + pin (ext_sync) { direction : input; } + + /* DSI input or fixed clock input */ + pin (tx_sync) { direction : input; clock : true; } + + /* DSI connections, in */ + pin (reject_in) { direction : input; } + pin (start_in) { direction : input; } + + /* DSI connections, out */ + pin (lx_det_hi) { direction : output; } + pin (lx_det_lo) { direction : output; } + pin (rej_window) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (tx_hilo) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (phase_end) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + bundle (phase_num) { + members (phase_num_0, phase_num_1, phase_num_2, phase_num_3); + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (ipq_reject) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (ipq_start) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (epq_reject) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (epq_start) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (mcs_reject) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (mcs_start) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk_seq"; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + + pin (do_switch) { direction : output; } + pin (adc_start) { direction : output; } + pin (adc_done) { direction : output; } + } + + cell (p4sarcell) { + pin (clock) { + direction : input; + clock : true; + } + pin (sw_negvref) { direction : input; } + bundle (cfg_st_sel) { + members (cfg_st_sel_0, cfg_st_sel_1); + direction : input; + } + pin (cfg_average) { direction : input; } + pin (cfg_resolution) { direction : input; } + pin (cfg_differential) { direction : input; } + pin (data_hilo_sel) { direction : input; } + pin (tr_sar_in) { direction : input; } + pin (sample_done) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (chan_id_valid) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (data_valid) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + bundle (chan_id) { + members (chan_id_0, chan_id_1, chan_id_2, chan_id_3); + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + bundle (data) { + members (data_0, data_1, data_2, data_3, data_4, data_5, + data_6, data_7, data_8, data_9, data_10, data_11); + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (eos_intr) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (tr_sar_out) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (irq) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : clock; + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + bundle (swctrl) { + members (swctrl_0, swctrl_1); + direction : input; + } + bundle (data_out) { + members (data_out_0, data_out_1, data_out_2, data_out_3, data_out_4, data_out_5, data_out_6, data_out_7); + direction : input; + } + bundle (data_oe) { + members (data_oe_0, data_oe_1, data_oe_2, data_oe_3); + direction : input; + } + } + + cell (p4csdcell) { + pin (clk1) { direction : input; clock : true; } + pin (clk2) { direction : input; clock : true; } + pin (sense_in) { direction : input; } + pin (sample_in) { direction : input; } + pin (cap_hi_en) { direction : output; } + pin (cap_lo_en) { direction : output; } + pin (sense_out) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk2"; /* TODO: this is actually clocked by clk_hf */ + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (sample_out) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk2"; /* TODO: this is actually clocked by clk_sample_o (analog clock) */ + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (irq) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk2"; /* TODO: actual clock not specified */ + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + pin (comp) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clk2"; /* TODO: actual clock not specified */ + intrinsic_rise : 0.0; + intrinsic_fall : 0.0; + } + } + } + + cell (p4halfuabcell) { + pin (clock) { direction : input; clock : true; } + pin (comp) { + direction : output; + /* TODO: add timing arc */ + } + pin (ctrl) { direction : input; clock : true; } + } + + cell (p4csidac8cell) { + pin (en) { direction : input; } + } + + cell (p4csidac7cell) { + pin (en) { direction : input; } + } + + cell (m0s8srsscell) { + pin (clock_pump) { direction : input; } + pin (clock_ss) { direction : input; } + pin (dsi_ss_code) { direction : input; } + pin (dsi_ss_updown) { direction : output; } + pin (interrupt_wdt) { direction : output; } + pin (interrupt_pwr) { direction : output; } + } + + cell (m0s8cpusscell) { + pin (interrupt_spcif) { direction : output; } + pin (interrupt_dma) { direction : output; } + } + + cell (m0s8iosscell) { + pin (interrupt_gpio) { direction : output; } + } + + cell (p4lpcompcell) { + pin (cmpout) { direction : output; } + } + + cell (p4lpcompblockcell) { + pin (interrupt) { direction : output; } + } + + cell (p4passblockcell) { + pin (interrupt_ctbs) { direction : output; } + pin (interrupt_uabs) { direction : output; } + } + + cell (p4abufcell) { + pin (ctb_dsi_comp) { direction : output; } + pin (ctb_dsi_comp_n) { direction : output; } + } + + cell (p4blecell) { + pin (interrupt) { direction : output; } + pin (rfctrl_extpa_en) { direction : output; } + } + + cell (cancell) { + pin (clock) { direction : input; clock: true; } + pin (can_rx) { direction : input; } + pin (can_tx) { direction : output; } + pin (can_tx_en) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.0; + intrinsic_fall : 1.0; + } + } + pin (interrupt) { + direction : output; + timing() { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.0; + intrinsic_fall : 1.0; + } + } + } + + cell (p4usbcell) { + pin (dp) { direction: inout; } + pin (dm) { direction: inout; } + pin (vbus_valid) { direction: input; } + pin (vbus_det) { direction: output; } + pin (interrupt_lo) { direction: output; } + pin (interrupt_med) { direction: output; } + pin (interrupt_hi) { direction: output; } + pin (dsi_usb_sof) { direction: output; } + pin (dma_burstend_0) { direction: input; } + pin (dma_burstend_1) { direction: input; } + pin (dma_burstend_2) { direction: input; } + pin (dma_burstend_3) { direction: input; } + pin (dma_burstend_4) { direction: input; } + pin (dma_burstend_5) { direction: input; } + pin (dma_burstend_6) { direction: input; } + pin (dma_burstend_7) { direction: input; } + pin (dma_req_0) { direction: output; } + pin (dma_req_1) { direction: output; } + pin (dma_req_2) { direction: output; } + pin (dma_req_3) { direction: output; } + pin (dma_req_4) { direction: output; } + pin (dma_req_5) { direction: output; } + pin (dma_req_6) { direction: output; } + pin (dma_req_7) { direction: output; } + pin (sof) { direction : output; } + pin (ep0) { direction : output; } + pin (ep8_1) { direction : output; } + pin (reset) { direction : output; } + pin (arb) { direction : output; } + } + + cell (p4usbpdcell) { + pin (clock_rx) { direction: input; } + pin (clock_tx) { direction: input; } + pin (clock_sar) { direction: input; } + pin (interrupt) { direction: output; } + pin (interrupt_wakeup) { direction: output; } + pin (cmp_out) { direction: output; } + pin (cmp_out_0) { direction: output; } + pin (cmp_out_1) { direction: output; } + pin (tx_data) { direction: input; } + pin (tx_data_en) { direction: input; } + pin (tr_out_0) { direction: output; } + pin (tr_out_1) { direction: output; } + pin (tr_out_2) { direction: output; } + pin (tr_out_3) { direction: output; } + pin (tr_out_4) { direction: output; } + pin (tr_out_5) { direction: output; } + pin (tr_out_6) { direction: output; } + pin (hpd) { direction: inout; } + } + + cell (p4smartiocell) { + pin (clock_smartio) { direction: input; } + pin (data0_i) { direction: input; } + pin (data0_o) { direction: output; } + pin (data0_io) { direction: inout; } + pin (gpio0_i) { direction: input; } + pin (gpio0_o) { direction: output; } + pin (gpio0_io) { direction: inout; } + pin (data1_i) { direction: input; } + pin (data1_o) { direction: output; } + pin (data1_io) { direction: inout; } + pin (gpio1_i) { direction: input; } + pin (gpio1_o) { direction: output; } + pin (gpio1_io) { direction: inout; } + pin (data2_i) { direction: input; } + pin (data2_o) { direction: output; } + pin (data2_io) { direction: inout; } + pin (gpio2_i) { direction: input; } + pin (gpio2_o) { direction: output; } + pin (gpio2_io) { direction: inout; } + pin (data3_i) { direction: input; } + pin (data3_o) { direction: output; } + pin (data3_io) { direction: inout; } + pin (gpio3_i) { direction: input; } + pin (gpio3_o) { direction: output; } + pin (gpio3_io) { direction: inout; } + pin (data4_i) { direction: input; } + pin (data4_o) { direction: output; } + pin (data4_io) { direction: inout; } + pin (gpio4_i) { direction: input; } + pin (gpio4_o) { direction: output; } + pin (gpio4_io) { direction: inout; } + pin (data5_i) { direction: input; } + pin (data5_o) { direction: output; } + pin (data5_io) { direction: inout; } + pin (gpio5_i) { direction: input; } + pin (gpio5_o) { direction: output; } + pin (gpio5_io) { direction: inout; } + pin (data6_i) { direction: input; } + pin (data6_o) { direction: output; } + pin (data6_io) { direction: inout; } + pin (gpio6_i) { direction: input; } + pin (gpio6_o) { direction: output; } + pin (gpio6_io) { direction: inout; } + pin (data7_i) { direction: input; } + pin (data7_o) { direction: output; } + pin (data7_io) { direction: inout; } + pin (gpio7_i) { direction: input; } + pin (gpio7_o) { direction: output; } + pin (gpio7_io) { direction: inout; } + } + + +/*}*/ diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/elab_dependencies.txt b/TrainingProjects/ADC-UART.cydsn/codegentemp/elab_dependencies.txt new file mode 100644 index 0000000..a48491d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/elab_dependencies.txt @@ -0,0 +1,239 @@ +D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\TopDesign\TopDesign.cysch +D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\TopDesign\PSoC4\PSoC 4200\TopDesign.ctl +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\cy_pins_v2_20.cysym +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\cy_pins_v2_20.pdf +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\cy_pins_v2_20.cystate +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\cy_pins_v2_20.cyprimitive +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\version.cypatch +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20 +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\Custom\custom.cs +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\Custom\cyenums.cs +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\Custom\cypinsdata.cs +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\Custom\cypinpicture.cs +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\Custom\cypinutils.cs +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_pins_v2_20\Custom\cygeneralcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC 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Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cypins.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cmFunc.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cmInstr.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\Cm0Iar.icf +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyBootAsmIar.s +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cmsis_armcc.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cmsis_gcc.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cm0plus.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\core_cm0plus_psoc4.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\cmsis_compiler.h +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v5_70\PSoC4\API\CyBootAsmGnu.s +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_lfclk_v1_20\PSoC4\API\CyLFClk.c +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_lfclk_v1_20\PSoC4\API\CyLFClk.h diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/generated_files.txt b/TrainingProjects/ADC-UART.cydsn/codegentemp/generated_files.txt new file mode 100644 index 0000000..756b7b5 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/generated_files.txt @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/lcpsoc3/index b/TrainingProjects/ADC-UART.cydsn/codegentemp/lcpsoc3/index new file mode 100644 index 0000000000000000000000000000000000000000..529a2698479437428876de68cc9d6594d8481308 GIT binary patch literal 1792 zcmZQzVPQZ3CdPpDd*8!w6!7h);{v7+Hbz z7APMi2NLH2Vh{kaErR_RnZP^<0aAMcXr@7zDp1-Fqy%j451^Rcd^JXp9XddBOn?}~ zW^7!vK^vI-uzQlom$8Xb6nR5E#LEKNwg?004vA&p-eG literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/liberty_reader.log b/TrainingProjects/ADC-UART.cydsn/codegentemp/liberty_reader.log new file mode 100644 index 0000000..7c0b9e7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/liberty_reader.log @@ -0,0 +1,93 @@ + ... including file device.lib +Error: space must precede Colon (:) at line 1511 +Error: space must precede Colon (:) at line 1535 +Error: space must precede Colon (:) at line 1536 +Error: space must precede Colon (:) at line 1537 +Error: space must precede Colon (:) at line 1538 +Error: space must precede Colon (:) at line 1539 +Error: space must precede Colon (:) at line 1540 +Error: space must precede Colon (:) at line 1541 +Error: space must precede Colon (:) at line 1542 +Error: space must precede Colon (:) at line 1543 +Error: space must precede Colon (:) at line 1544 +Error: space must precede Colon (:) at line 1545 +Error: space must precede Colon (:) at line 1546 +Error: space must precede Colon (:) at line 1547 +Error: space must precede Colon (:) at line 1548 +Error: space must precede Colon (:) at line 1549 +Error: space must precede Colon (:) at line 1550 +Error: space must precede Colon (:) at line 1551 +Error: space must precede Colon (:) at line 1552 +Error: space must precede Colon (:) at line 1553 +Error: space must precede Colon (:) at line 1554 +Error: space must precede Colon (:) at line 1555 +Error: space must precede Colon (:) at line 1556 +Error: space must precede Colon (:) at line 1557 +Error: space must precede Colon (:) at line 1558 +Error: space must precede Colon (:) at line 1567 +Error: space must precede Colon (:) at line 1568 +Error: space must precede Colon (:) at line 1569 +Error: space must precede Colon (:) at line 1570 +Error: space must precede Colon (:) at line 1571 +Error: space must precede Colon (:) at line 1572 +Error: space must precede Colon (:) at line 1573 +Error: space must precede Colon (:) at line 1574 +Error: space must precede Colon (:) at line 1575 +Error: space must precede Colon (:) at line 1576 +Error: space must precede Colon (:) at line 1577 +Error: space must precede Colon (:) at line 1578 +Error: space must precede Colon (:) at line 1579 +Error: space must precede Colon (:) at line 1580 +Error: space must precede Colon (:) at line 1581 +Error: space must precede Colon (:) at line 1582 +Error: space must precede Colon (:) at line 1583 +Error: space must precede Colon (:) at line 1584 +Error: space must precede Colon (:) at line 1588 +Error: space must precede Colon (:) at line 1589 +Error: space must precede Colon (:) at line 1590 +Error: space must precede Colon (:) at line 1591 +Error: space must precede Colon (:) at line 1592 +Error: space must precede Colon (:) at line 1593 +Error: space must precede Colon (:) at line 1594 +Error: space must precede Colon (:) at line 1595 +Error: space must precede Colon (:) at line 1596 +Error: space must precede Colon (:) at line 1597 +Error: space must precede Colon (:) at line 1598 +Error: space must precede Colon (:) at line 1599 +Error: space must precede Colon (:) at line 1600 +Error: space must precede Colon (:) at line 1601 +Error: space must precede Colon (:) at line 1602 +Error: space must precede Colon (:) at line 1603 +Error: space must precede Colon (:) at line 1604 +Error: space must precede Colon (:) at line 1605 +Error: space must precede Colon (:) at line 1606 +Error: space must precede Colon (:) at line 1607 +Error: space must precede Colon (:) at line 1608 +Error: space must precede Colon (:) at line 1609 +Error: space must precede Colon (:) at line 1610 +Error: space must precede Colon (:) at line 1611 +Error: space must precede Colon (:) at line 1612 +Error: space must precede Colon (:) at line 1613 +Error: space must precede Colon (:) at line 1614 +Error: space must precede Colon (:) at line 1615 +Error: space must precede Colon (:) at line 1616 +Error: space must precede Colon (:) at line 1617 +Error: space must precede Colon (:) at line 1618 +Error: space must precede Colon (:) at line 1619 +Error: space must precede Colon (:) at line 1620 +Error: space must precede Colon (:) at line 1621 +Error: space must precede Colon (:) at line 1622 +Error: space must precede Colon (:) at line 1623 +Error: space must precede Colon (:) at line 1624 +Error: space must precede Colon (:) at line 1625 +Error: space must precede Colon (:) at line 1626 +Error: space must precede Colon (:) at line 1627 +Error: space must precede Colon (:) at line 1628 +Error: space must precede Colon (:) at line 1629 +Error: space must precede Colon (:) at line 1630 +Error: space must precede Colon (:) at line 1631 +Error: space must precede Colon (:) at line 1632 +Error: space must precede Colon (:) at line 1633 +Error: space must precede Colon (:) at line 1634 +Error: space must precede Colon (:) at line 1635 +Error: space must precede Colon (:) at line 1636 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/pins_44-TQFP.xml b/TrainingProjects/ADC-UART.cydsn/codegentemp/pins_44-TQFP.xml new file mode 100644 index 0000000..13fe8de --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/pins_44-TQFP.xml @@ -0,0 +1,414 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/placer.log b/TrainingProjects/ADC-UART.cydsn/codegentemp/placer.log new file mode 100644 index 0000000..3ebae12 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/placer.log @@ -0,0 +1,73 @@ +#*************************************************************************** + +#sjplacer + +#Version: 1.1 + +#Build Date: Dec 5 2017 15:35:27 + +#File Generated: Jul 17 2020 10:59:52 + +#Purpose: + +#Copyright (C) 2010-2011 by Softjin Technologies Pvt Ltd. All rights reserved. + +#*************************************************************************** + +Executing : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin/sjplacer.exe --proj-name ADC-UART --netlist-vh2 ADC-UART_p.vh2 --arch p4_udb2x2a --arch-file C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\arch/udbdsi_2x2_04.cydata --ip-file C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/ip_blocks.cydata --rrg-file C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/route_arch-rrg.cydata --irq-file C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/irqconn.cydata --dsi-conn-file C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc4/psoc4a/dsiconn.cydata --pins-file pins_44-TQFP.xml --lib-file ADC-UART_p.lib --sdc-file ADC-UART.sdc --io-pcf ADC-UART.pci --outdir . + + Softjin Techologies Placer, Version 1.1 + +Build Date : Dec 5 2017 15:33:41 + +D2004: Option and Settings Summary +============================================================= +Netlist vh2 file - ADC-UART_p.vh2 +Architecture file - C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\arch/udbdsi_2x2_04.cydata +Package - +Defparam file - +SDC file - ADC-UART.sdc +Output directory - . +Timing library - ADC-UART_p.lib +IO Placement file - ADC-UART.pci + +D2050: Starting reading inputs for placer +============================================================= +D2065: Reading netlist file : "ADC-UART_p.vh2" +D2065: Reading arch file : "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\arch/udbdsi_2x2_04.cydata" +D2051: Reading of inputs for placer completed successfully + +D2053: Starting placement of the design +============================================================= + +Phase 2 +Phase 3 +I2659: No Constrained paths were found. The placer will run in non-timing driven mode. + +Design Statistics after Packing + Number of Combinational MCs : 0 + Number of Sequential MCs : 0 + Number of DPs : 0 + Number of Controls : 0 + Number of Status : 0 + Number of SyncCells : 0 + Number of count7cells : 0 + +Device Utilization Summary after Packing + Macrocells : 0/32 + UDBS : 0/4 + IOs : 3/36 + + +D2088: Phase 3, elapsed time : 0.0 (sec) + +Phase 4 +D2088: Phase 4, elapsed time : 0.0 (sec) + +Phase 8 +D2088: Phase 8, elapsed time : 0.0 (sec) + +D2054: Placement of the design completed successfully + +I2076: Total run-time: 0.2 sec. + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/project.h b/TrainingProjects/ADC-UART.cydsn/codegentemp/project.h new file mode 100644 index 0000000..ac1bda3 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/project.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: project.h +* +* PSoC Creator 4.2 +* +* Description: +* It contains references to all generated header files and should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "cyfitter_cfg.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "cydisabledsheets.h" +#include "LED.h" +#include "LED_aliases.h" +#include "UART.h" +#include "UART_SPI_UART.h" +#include "UART_PINS.h" +#include "UART_SPI_UART_PVT.h" +#include "UART_PVT.h" +#include "UART_BOOT.h" +#include "Input_1.h" +#include "Input_1_aliases.h" +#include "ADC.h" +#include "UART_SCBCLK.h" +#include "UART_tx.h" +#include "UART_tx_aliases.h" +#include "ADC_IRQ.h" +#include "ADC_intClock.h" +#include "cy_em_eeprom.h" +#include "core_cm0_psoc4.h" +#include "CyFlash.h" +#include "CyLib.h" +#include "cyPm.h" +#include "cytypes.h" +#include "cypins.h" +#include "CyLFClk.h" + +/*[]*/ + diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/project_ids.txt b/TrainingProjects/ADC-UART.cydsn/codegentemp/project_ids.txt new file mode 100644 index 0000000..9c4541d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/project_ids.txt @@ -0,0 +1,7 @@ +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\default\CyAnnotationLibrary\CyAnnotationLibrary.cylib\CyAnnotationLibrary.cyprj|95ce56d3-84a5-4069-99bd-febf027fafda +D:\Users\jagumiel\Documents\PSoC Creator\4.2\Downloads ( 4.2).cylib\Downloads ( 4.2).cyprj|aff49e54-bd0f-41e6-b787-f231342160f3 +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\cycomponentlibraryupdates\CyComponentLibraryUpdates.cylib\CyComponentLibraryUpdates.cyprj|7085e659-a495-4753-b0ef-c425d39d11bd +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\CyComponentLibrary.cyprj|0dc0a6f1-cc18-4c52-aab4-620f62d4acda +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyPrimitives.cyprj|dd4697d8-e3f4-401e-91e7-9c2300175b69 +C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\default\CyReferenceLibrary\CyReferenceLibrary.cylib\CyReferenceLibrary.cyprj|d976c6b1-103e-4085-b9da-96876ff82cbe +D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj|2e093eb3-ab35-49ea-a507-7a7de6551d08 diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/referenced_files.txt b/TrainingProjects/ADC-UART.cydsn/codegentemp/referenced_files.txt new file mode 100644 index 0000000..c044137 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/referenced_files.txt @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/codegentemp/warp_dependencies.txt b/TrainingProjects/ADC-UART.cydsn/codegentemp/warp_dependencies.txt new file mode 100644 index 0000000..7b77298 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/codegentemp/warp_dependencies.txt @@ -0,0 +1,10 @@ +C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/4.2/PSoC\ Creator/warp/lib/ieee/work/stdlogic.vif : + +C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/4.2/PSoC\ Creator/warp/lib/common/stdlogic/mod_genv.vif : + +C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/4.2/PSoC\ Creator/warp/lib/common/cypress.v : + +C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/4.2/PSoC\ Creator/warp/lib/common/cy_psoc3_inc.v : + +C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/4.2/PSoC\ Creator/warp/lib/common/stdlogic/rtlpkg.vif : + diff --git a/TrainingProjects/ADC-UART.cydsn/cyapicallbacks.h b/TrainingProjects/ADC-UART.cydsn/cyapicallbacks.h new file mode 100644 index 0000000..20c280c --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/cyapicallbacks.h @@ -0,0 +1,19 @@ +/* ======================================== + * + * Copyright YOUR COMPANY, THE YEAR + * All Rights Reserved + * UNPUBLISHED, LICENSED SOFTWARE. + * + * CONFIDENTIAL AND PROPRIETARY INFORMATION + * WHICH IS THE PROPERTY OF your company. + * + * ======================================== +*/ +#ifndef CYAPICALLBACKS_H +#define CYAPICALLBACKS_H + + /*Define your macro callbacks here */ + /*For more information, refer to the Macro Callbacks topic in the PSoC Creator Help.*/ + +#endif /* CYAPICALLBACKS_H */ +/* [] */ diff --git a/TrainingProjects/ADC-UART.cydsn/main.c b/TrainingProjects/ADC-UART.cydsn/main.c new file mode 100644 index 0000000..4b7fec2 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/main.c @@ -0,0 +1,208 @@ +/******************************************************************************* +* File Name: main.c +* +* Version: 2.00 +* +* Description: +* This example project shows how to sample four different channels using +* SAR MUX and ADC, and send channel output to HyperTerminal (PC) using UART. +* +******************************************************************************** +* Copyright 2013-2018, Cypress Semiconductor Corporation. All rights reserved. +* This software is owned by Cypress Semiconductor Corporation and is protected +* by and subject to worldwide patent and copyright laws and treaties. +* Therefore, you may use this software only as provided in the license agreement +* accompanying the software package from which you obtained this software. +* CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +* WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +*******************************************************************************/ + +#include + +/* Macro definitions */ +#define LOW (0u) +#define HIGH (1u) +#define CHANNEL_1 (0u) +#define NO_OF_CHANNELS (1u) +#define CLEAR_SCREEN (0x0C) +#define CONVERT_TO_ASCII (0x30u) + +/* Resistor Values and Gain */ +#define RG (2200u) +#define R1 (10000u) +#define GAIN (1 + 2 * (float)R1 / RG) + +/* Send the channel number and voltage to UART */ +static void SendChannelVoltage(uint8 channel, int16 mVolts); + +/* Interrupt prototypes */ +CY_ISR_PROTO(ADC_ISR_Handler); + +/* Global variables */ +volatile uint32 windowFlag = 0u; +volatile uint8 dataReady = 0u; +volatile uint8 channelFlag = 0u; + + +/******************************************************************************* +* Function Name: main +******************************************************************************** +* +* Summary: +* Performs the following tasks: +* - Start the components. +* - Starts ADC conversion. +* - Buffer ADC results. +* - Sends the result to HyperTerminal (PC) using UART. +* - Turns ON an LED when ADC input is outside the voltage +* window of 1250mV to 3750mV. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +int main() +{ + uint8 channel = CHANNEL_1; + int16 adcVal[4u]; + int16 mVolts; + int16 previousValue = 0; + + /* Start the Components */ + UART_Start(); + ADC_Start(); + + /* Start ISRs */ + ADC_IRQ_StartEx(ADC_ISR_Handler); + + /* Enable global interrupts */ + CyGlobalIntEnable; + + /* Start ADC conversion */ + ADC_StartConvert(); + + for(;;) + { + while(dataReady == 0u) + { + ; /* Wait for ADC conversion */ + } + /* Buffer the results */ + adcVal[CHANNEL_1] = ADC_GetResult16(CHANNEL_1); + + /* Check for ADC window limit interrupt */ + if(windowFlag != 0u) + { + /* Turn ON the LED when input is outside the voltage window (1250mV - 3750mV) */ + LED_Write(LOW); + + /* Note: If LED is active HIGH, then replace "LOW" with "HIGH" */ + } + else + { + /* Turn OFF the LED when input is within the voltage window (250mV - 750mV) */ + LED_Write(HIGH); + + /* Note:If LED is active HIGH, then replace "HIGH" with "LOW" */ + } + + + /* Convert the ADC counts of active channel to mVolts */ + mVolts = ADC_CountsTo_mVolts(channel, adcVal[channel]); + + /* If ADC result or channel has been changed, send the data to UART */ + if((previousValue != mVolts) || (channelFlag != 0u)) + { + SendChannelVoltage(channel, mVolts); + previousValue = mVolts; + + /* Clear the flag */ + channelFlag = 0u; + } + dataReady = 0u; + } +} + +/******************************************************************************* +* Function Name: SendChannelVoltage +******************************************************************************** +* +* Summary: +* Performs the following tasks: +* - Converts the channel number to ASCII character +* - Clears terminal screen +* - Sends the channel number and voltage to UART +* +* Parameters: +* uint8 channel : Channel Number +* int16 mVolts : ADC counts +* +* Return: +* None. +* +********************************************************************************/ +static void SendChannelVoltage(uint8 channel, int16 mVolts) +{ + /* Clear screen */ + UART_UartPutChar(CLEAR_SCREEN); + UART_UartPutString("Channel "); + + /* Display the channel number starting from 1 */ + channel++; + channel += CONVERT_TO_ASCII; + UART_UartPutChar(channel); + UART_UartPutString(" = "); + + /* Find the sign of the result */ + if(mVolts < 0) + { + UART_UartPutString("-"); + mVolts = -mVolts; + } + + /* Send voltage to UART */ + UART_UartPutChar((mVolts/1000u) + CONVERT_TO_ASCII); + mVolts %= 1000u; + UART_UartPutChar((mVolts/100u) + CONVERT_TO_ASCII); + mVolts %= 100u; + UART_UartPutChar((mVolts/10u) + CONVERT_TO_ASCII); + mVolts %= 10u; + UART_UartPutChar(mVolts + CONVERT_TO_ASCII); + UART_UartPutString(" mV"); + UART_UartPutCRLF(0u); +} + + +/****************************************************************************** +* Function Name: ADC_ISR_Handler +******************************************************************************* +* +* Summary: +* Interrupt Service Routine. Check the ADC status and sets window and data +* ready flags. +* +******************************************************************************/ +CY_ISR(ADC_ISR_Handler) +{ + uint32 intr_status; + + /* Read interrupt status registers */ + intr_status = ADC_SAR_INTR_MASKED_REG; + /* Check for End of Scan interrupt */ + if((intr_status & ADC_EOS_MASK) != 0u) + { + /* Read range interrupt status and raise the flag */ + windowFlag = ADC_SAR_RANGE_INTR_MASKED_REG; + /* Clear range detect status */ + ADC_SAR_RANGE_INTR_REG = windowFlag; + dataReady = 1u; + } + /* Clear handled interrupt */ + ADC_SAR_INTR_REG = intr_status; +} + +/* [] END OF FILE */

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creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m/crt0.o +START GROUP +LOAD .\ARM_GCC_541\Debug\main.o +LOAD .\ARM_GCC_541\Debug\cyfitter_cfg.o +LOAD .\ARM_GCC_541\Debug\cymetadata.o +LOAD .\ARM_GCC_541\Debug\Cm0Start.o +LOAD .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a +END GROUP +START GROUP +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libc_nano.a +END GROUP +START GROUP +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libc_nano.a +END GROUP +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtend.o +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtn.o +START GROUP +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libc.a +LOAD c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libnosys.a +END GROUP + 0x00000000 CY_APPL_ORIGIN = 0x0 + 0x00000080 CY_FLASH_ROW_SIZE = 0x80 + 0x00000001 CY_APPL_NUM = 0x1 + 0x00000001 CY_APPL_MAX = 0x1 + 0x00000040 CY_METADATA_SIZE = 0x40 + 0x00000000 CY_APPL_LOADABLE = 0x0 + 0x00000000 CY_CHECKSUM_EXCLUDE_SIZE = ALIGN (0x0, CY_FLASH_ROW_SIZE) + 0x00000000 CY_APP_FOR_STACK_AND_COPIER = 0x0 + [!provide] PROVIDE (__cy_heap_start, _end) + 0x00000001 PROVIDE (__cy_region_num, ((__cy_regions_end - __cy_regions) / 0x10)) + 0x20001000 PROVIDE (__cy_stack, (ORIGIN (ram) + LENGTH (ram))) + [!provide] PROVIDE (__cy_heap_end, (__cy_stack - 0x400)) + +.cybootloader 0x00000000 0x0 + *(.cybootloader) + 0x00000000 appl1_start = CY_APPL_ORIGIN?CY_APPL_ORIGIN:ALIGN (CY_FLASH_ROW_SIZE) + 0x00003f80 appl2_start = (appl1_start + ALIGN ((((LENGTH (rom) - appl1_start) - (0x2 * CY_FLASH_ROW_SIZE)) / 0x2), CY_FLASH_ROW_SIZE)) + 0x00000000 appl_start = (CY_APPL_NUM == 0x1)?appl1_start:appl2_start + 0x00000001 cy_project_type_bootloader = (appl_start == 0x0)?0x1:0x0 + 0x00000000 cy_project_type_app_for_stack_and_copier = (CY_APP_FOR_STACK_AND_COPIER == 0x1)?0x1:0x0 + +.text 0x00000000 0x1610 + CREATE_OBJECT_SYMBOLS + 0x00000000 PROVIDE (__cy_interrupt_vector, RomVectors) + *(.romvectors) + .romvectors 0x00000000 0x10 .\ARM_GCC_541\Debug\Cm0Start.o + 0x00000000 RomVectors + 0x00000001 ASSERT ((. != __cy_interrupt_vector), No interrupt vector) + 0x00000001 ASSERT (CY_APPL_ORIGIN?(SIZEOF (.cybootloader) <= CY_APPL_ORIGIN):0x1, Wrong image location) + 0x00000010 PROVIDE (__cy_reset, Reset) + *(.text.Reset) + .text.Reset 0x00000010 0x8 .\ARM_GCC_541\Debug\Cm0Start.o + 0x00000010 Reset + 0x00000001 ASSERT ((. != __cy_reset), No reset code) + *(.psocinit) + .psocinit 0x00000018 0x1a0 .\ARM_GCC_541\Debug\cyfitter_cfg.o + 0x000000a4 cyfitter_cfg + 0x000001b8 . = MAX (., 0x100) + *(.text .text.* .gnu.linkonce.t.*) + .text 0x000001b8 0x60 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .text.main 0x00000218 0x10c .\ARM_GCC_541\Debug\main.o + 0x00000218 main + .text.SendChannelVoltage + 0x00000324 0x128 .\ARM_GCC_541\Debug\main.o + .text.ADC_ISR_Handler + 0x0000044c 0x50 .\ARM_GCC_541\Debug\main.o + 0x0000044c ADC_ISR_Handler + .text.CYMEMZERO + 0x0000049c 0x20 .\ARM_GCC_541\Debug\cyfitter_cfg.o + .text.AnalogSetDefault + 0x000004bc 0x14 .\ARM_GCC_541\Debug\cyfitter_cfg.o + .text.IntDefaultHandler + 0x000004d0 0x14 .\ARM_GCC_541\Debug\Cm0Start.o + 0x000004d0 IntDefaultHandler + .text.Start_c 0x000004e4 0x98 .\ARM_GCC_541\Debug\Cm0Start.o + 0x000004e4 Start_c + .text.initialize_psoc + 0x0000057c 0x64 .\ARM_GCC_541\Debug\Cm0Start.o + 0x0000057c initialize_psoc + .text.LED_Write + 0x000005e0 0x50 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(LED.o) + 0x000005e0 LED_Write + .text.UART_Init + 0x00000630 0x10 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART.o) + 0x00000630 UART_Init + .text.UART_Enable + 0x00000640 0x24 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART.o) + 0x00000640 UART_Enable + .text.UART_Start + 0x00000664 0x24 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART.o) + 0x00000664 UART_Start + .text.UART_ScbEnableIntr + 0x00000688 0xc .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART.o) + .text.UART_ScbModePostEnable + 0x00000694 0x10 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART.o) + .text.UART_SpiUartWriteTxData + 0x000006a4 0x2c .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART_SPI_UART.o) + 0x000006a4 UART_SpiUartWriteTxData + .text.UART_UartInit + 0x000006d0 0xbc .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART_UART.o) + 0x000006d0 UART_UartInit + .text.UART_UartPostEnable + 0x0000078c 0x30 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART_UART.o) + 0x0000078c UART_UartPostEnable + .text.UART_UartPutString + 0x000007bc 0x38 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART_UART.o) + 0x000007bc UART_UartPutString + .text.UART_UartPutCRLF + 0x000007f4 0x24 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART_UART.o) + 0x000007f4 UART_UartPutCRLF + .text.ADC_Start + 0x00000818 0x24 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x00000818 ADC_Start + .text.ADC_Init + 0x0000083c 0x1d0 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x0000083c ADC_Init + .text.ADC_Enable + 0x00000a0c 0x2c .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x00000a0c ADC_Enable + .text.ADC_StartConvert + 0x00000a38 0x1c .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x00000a38 ADC_StartConvert + .text.ADC_GetResult16 + 0x00000a54 0x44 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x00000a54 ADC_GetResult16 + .text.ADC_SetGain + 0x00000a98 0x2c .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x00000a98 ADC_SetGain + .text.ADC_CountsTo_mVolts + 0x00000ac4 0xa0 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x00000ac4 ADC_CountsTo_mVolts + .text.ADC_ISR 0x00000b64 0x20 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_INT.o) + 0x00000b64 ADC_ISR + .text.ADC_IRQ_StartEx + 0x00000b84 0x28 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_IRQ.o) + 0x00000b84 ADC_IRQ_StartEx + .text.ADC_IRQ_SetVector + 0x00000bac 0x1c .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_IRQ.o) + 0x00000bac ADC_IRQ_SetVector + .text.ADC_IRQ_SetPriority + 0x00000bc8 0x50 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_IRQ.o) + 0x00000bc8 ADC_IRQ_SetPriority + .text.ADC_IRQ_Enable + 0x00000c18 0x18 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_IRQ.o) + 0x00000c18 ADC_IRQ_Enable + .text.ADC_IRQ_Disable + 0x00000c30 0x18 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_IRQ.o) + 0x00000c30 ADC_IRQ_Disable + .text.CySysClkWriteImoFreq + 0x00000c48 0x1e4 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + 0x00000c48 CySysClkWriteImoFreq + .text.CyIntSetVector + 0x00000e2c 0x4c .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + 0x00000e2c CyIntSetVector + .text.CyIntSetPriority + 0x00000e78 0xa8 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + 0x00000e78 CyIntSetPriority + .text.CyHalt 0x00000f20 0x18 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + 0x00000f20 CyHalt + .text.CyDelayUs + 0x00000f38 0x28 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + 0x00000f38 CyDelayUs + .text 0x00000f60 0x24 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyBootAsmGnu.o) + 0x00000f60 CyDelayCycles + 0x00000f74 CyEnterCriticalSection + 0x00000f7c CyExitCriticalSection + .text 0x00000f84 0x114 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(_udivsi3.o) + 0x00000f84 __aeabi_uidiv + 0x00000f84 __udivsi3 + 0x00001090 __aeabi_uidivmod + .text 0x00001098 0x1d4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(_divsi3.o) + 0x00001098 __divsi3 + 0x00001098 __aeabi_idiv + 0x00001264 __aeabi_idivmod + .text 0x0000126c 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(_dvmd_tls.o) + 0x0000126c __aeabi_idiv0 + 0x0000126c __aeabi_ldiv0 + .text 0x00001270 0x228 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(mulsf3.o) + 0x00001270 __aeabi_fmul + .text 0x00001498 0x44 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(fixsfsi.o) + 0x00001498 __aeabi_f2iz + .text 0x000014dc 0x90 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(floatsisf.o) + 0x000014dc __aeabi_i2f + .text 0x0000156c 0x3c c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(_clzsi2.o) + 0x0000156c __clzsi2 + .text.__errno 0x000015a8 0xc c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-errno.o) + 0x000015a8 __errno + .text.__libc_init_array + 0x000015b4 0x4c c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-init.o) + 0x000015b4 __libc_init_array + .text.memset 0x00001600 0x10 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-memset.o) + 0x00001600 memset + *(.plt) + *(.gnu.warning) + *(.glue_7t) + .glue_7t 0x00001610 0x0 linker stubs + *(.glue_7) + .glue_7 0x00001610 0x0 linker stubs + *(.vfp11_veneer) + .vfp11_veneer 0x00001610 0x0 linker stubs + *(.bootloader) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + +.v4_bx 0x00001610 0x0 + .v4_bx 0x00001610 0x0 linker stubs + +.iplt 0x00001610 0x0 + .iplt 0x00001610 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + +.eh_frame_hdr + *(.eh_frame_hdr) + +.eh_frame 0x00001610 0x4 + *(.eh_frame) + .eh_frame 0x00001610 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .eh_frame 0x00001610 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtend.o + [!provide] PROVIDE (__exidx_start, .) + +.ARM.exidx + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + 0x00001614 __exidx_end = . + +.rodata 0x00001614 0xcc + *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata 0x00001614 0x18 .\ARM_GCC_541\Debug\main.o + .rodata 0x0000162c 0xc .\ARM_GCC_541\Debug\cyfitter_cfg.o + .rodata 0x00001638 0x2e .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + 0x00001638 cyImoFreqMhz2Reg + *fill* 0x00001666 0x2 + .rodata 0x00001668 0x40 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m\libgcc.a(mulsf3.o) + .rodata.str1.1 + 0x000016a8 0x2 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-impure.o) + 0x000016ac . = ALIGN (0x4) + *fill* 0x000016aa 0x2 + *(.init) + .init 0x000016ac 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crti.o + 0x000016ac _init + .init 0x000016b0 0x8 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtn.o + 0x000016b8 . = ALIGN (0x4) + 0x000016b8 __preinit_array_start = . + *(.preinit_array) + 0x000016b8 __preinit_array_end = . + 0x000016b8 . = ALIGN (0x4) + 0x000016b8 __init_array_start = . + *(SORT(.init_array.*)) + *(.init_array) + .init_array 0x000016b8 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .init_array 0x000016bc 0x4 .\ARM_GCC_541\Debug\Cm0Start.o + 0x000016c0 __init_array_end = . + 0x000016c0 . = ALIGN (0x4) + *(.fini) + .fini 0x000016c0 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crti.o + 0x000016c0 _fini + .fini 0x000016c4 0x8 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtn.o + 0x000016cc . = ALIGN (0x4) + 0x000016cc __fini_array_start = . + *(.fini_array) + .fini_array 0x000016cc 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + *(SORT(.fini_array.*)) + 0x000016d0 __fini_array_end = . + 0x000016d0 . = ALIGN (0x4) + *crtbegin.o(.ctors) + *(EXCLUDE_FILE(*crtend.o) .ctors) + *(SORT(.ctors.*)) + *crtend.o(.ctors) + 0x000016d0 . = ALIGN (0x4) + *crtbegin.o(.dtors) + *(EXCLUDE_FILE(*crtend.o) .dtors) + *(SORT(.dtors.*)) + *crtend.o(.dtors) + 0x000016d0 . = ALIGN (0x4) + 0x000016d0 __cy_regions = . + 0x000016d0 0x4 LONG 0x16e0 __cy_region_init_ram + 0x000016d4 0x4 LONG 0x200000c8 __cy_region_start_data + 0x000016d8 0x4 LONG 0x80 __cy_region_init_size_ram + 0x000016dc 0x4 LONG 0x30 __cy_region_zero_size_ram + 0x000016e0 __cy_regions_end = . + 0x000016e0 . = ALIGN (0x8) + 0x000016e0 _etext = . + +.cy_checksum_exclude + 0x000016e0 0x0 + *(.cy_checksum_exclude) + +.ramvectors 0x20000000 0xc0 + 0x20000000 __cy_region_start_ram = . + *(.ramvectors) + .ramvectors 0x20000000 0xc0 .\ARM_GCC_541\Debug\Cm0Start.o + 0x20000000 CyRamVectors + +.noinit 0x200000c0 0x4 + *(.noinit) + .noinit 0x200000c0 0x4 .\ARM_GCC_541\Debug\Cm0Start.o + +.data 0x200000c8 0x80 load address 0x000016e0 + 0x200000c8 __cy_region_start_data = . + *(.jcr) + .jcr 0x200000c8 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .jcr 0x200000c8 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtend.o + *(.got.plt) + *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + .data 0x200000cc 0x14 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + 0x200000cc cydelayFreqHz + 0x200000d0 cydelayFreqKhz + 0x200000d4 cydelayFreqMhz + 0x200000d8 cydelay32kMs + 0x200000dc CySysClkPumpConfig + .data.impure_data + 0x200000e0 0x60 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-impure.o) + .data._impure_ptr + 0x20000140 0x4 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-impure.o) + 0x20000140 _impure_ptr + 0x20000148 . = ALIGN (0x8) + *fill* 0x20000144 0x4 + *(.ram) + 0x20000148 _edata = . + +.igot.plt 0x20000148 0x0 load address 0x00001760 + .igot.plt 0x20000148 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + +.bss 0x20000148 0x30 load address 0x00001760 + 0x20000148 PROVIDE (__bss_start__, .) + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + .bss 0x20000148 0x1c c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + .bss 0x20000164 0x6 .\ARM_GCC_541\Debug\main.o + 0x20000164 windowFlag + 0x20000168 dataReady + 0x20000169 channelFlag + .bss 0x2000016a 0x4 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART.o) + 0x2000016a UART_initVar + 0x2000016c UART_IntrTxMask + .bss 0x2000016e 0x1 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x2000016e ADC_initVar + *(COMMON) + *fill* 0x2000016f 0x1 + COMMON 0x20000170 0x6 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + 0x20000170 ADC_countsPer10Volt + 0x20000174 ADC_offset + 0x20000178 . = ALIGN (0x8) + *fill* 0x20000176 0x2 + *(.ram.b) + 0x20000178 _end = . + 0x20000178 __end = . + 0x20000178 PROVIDE (end, .) + 0x20000178 PROVIDE (__bss_end__, .) + 0x000016e0 __cy_region_init_ram = LOADADDR (.data) + 0x00000080 __cy_region_init_size_ram = (_edata - ADDR (.data)) + 0x00000030 __cy_region_zero_size_ram = (_end - _edata) + +.heap 0x20000178 0x100 load address 0x00001760 + 0x20000178 . = _end + 0x20000278 . = (. + 0x100) + *fill* 0x20000178 0x100 + 0x20000278 __cy_heap_limit = . + +.stack 0x20000c00 0x400 + 0x20000c00 __cy_stack_limit = . + 0x20001000 . = (. + 0x400) + *fill* 0x20000c00 0x400 + 0x00000001 ASSERT ((__cy_stack_limit >= __cy_heap_limit), region RAM overflowed with stack) + 0x00000000 cy_checksum_exclude_size = (CY_APPL_LOADABLE == 0x1)?SIZEOF (.cy_checksum_exclude):0x0 + 0x00000001 ASSERT ((cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE), CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.) + 0x00007fc0 cyloadermeta_start = (cy_project_type_bootloader || cy_project_type_app_for_stack_and_copier)?(LENGTH (rom) - CY_METADATA_SIZE):0xf0000000 + +.cyloadermeta + *(.cyloadermeta) + 0x00007fc0 cyloadablemeta_start = cy_project_type_app_for_stack_and_copier?((LENGTH (rom) - CY_FLASH_ROW_SIZE) - CY_METADATA_SIZE):((LENGTH (rom) - (CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 0x1))) - CY_METADATA_SIZE) + +.cyloadablemeta + *(.cyloadablemeta) + +.cyflashprotect + 0x90400000 0x20 + *(.cyflashprotect) + .cyflashprotect + 0x90400000 0x20 .\ARM_GCC_541\Debug\cymetadata.o + 0x90400000 cy_meta_flashprotect + +.cymeta 0x90500000 0xc + *(.cymeta) + .cymeta 0x90500000 0xc .\ARM_GCC_541\Debug\cymetadata.o + 0x90500000 cy_metadata + +.cychipprotect 0x90600000 0x1 + *(.cychipprotect) + .cychipprotect + 0x90600000 0x1 .\ARM_GCC_541\Debug\cymetadata.o + 0x90600000 cy_meta_chipprotect + +.rel.dyn 0x00001760 0x0 load address 0x90600004 + .rel.iplt 0x00001760 0x0 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtbegin.o + +.stab + *(.stab) + +.stabstr + *(.stabstr) + +.debug + *(.debug) + +.line + *(.line) + +.debug_srcinfo + *(.debug_srcinfo) + +.debug_sfnames + *(.debug_sfnames) + +.debug_aranges 0x00000000 0x510 + *(.debug_aranges) + .debug_aranges + 0x00000000 0x30 .\ARM_GCC_541\Debug\main.o + .debug_aranges + 0x00000030 0x48 .\ARM_GCC_541\Debug\cyfitter_cfg.o + .debug_aranges + 0x00000078 0x18 .\ARM_GCC_541\Debug\cymetadata.o + .debug_aranges + 0x00000090 0x48 .\ARM_GCC_541\Debug\Cm0Start.o + .debug_aranges + 0x000000d8 0x48 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(LED.o) + .debug_aranges + 0x00000120 0x68 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART.o) + .debug_aranges + 0x00000188 0x48 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART_SPI_UART.o) + .debug_aranges + 0x000001d0 0x58 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(UART_UART.o) + .debug_aranges + 0x00000228 0xa8 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC.o) + .debug_aranges + 0x000002d0 0x20 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_INT.o) + .debug_aranges + 0x000002f0 0x80 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(ADC_IRQ.o) + .debug_aranges + 0x00000370 0x180 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyLib.o) + .debug_aranges + 0x000004f0 0x20 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(CyBootAsmGnu.o) + +.debug_pubnames + *(.debug_pubnames) + +.debug_info 0x00000000 0x20eb + *(.debug_info .gnu.linkonce.wi.*) + .debug_info 0x00000000 0x1ce .\ARM_GCC_541\Debug\main.o + .debug_info 0x000001ce 0x256 .\ARM_GCC_541\Debug\cyfitter_cfg.o + .debug_info 0x00000424 0xf8 .\ARM_GCC_541\Debug\cymetadata.o + .debug_info 0x0000051c 0x312 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c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-memcpy-stub.o) + .debug_frame 0x00001198 0x20 c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-memset.o) + +.debug_str 0x00000000 0xfc3 + *(.debug_str) + .debug_str 0x00000000 0x22d .\ARM_GCC_541\Debug\main.o + 0x280 (size before relaxing) + .debug_str 0x0000022d 0xaa .\ARM_GCC_541\Debug\cyfitter_cfg.o + 0x2a3 (size before relaxing) + .debug_str 0x000002d7 0x63 .\ARM_GCC_541\Debug\cymetadata.o + 0x226 (size before relaxing) + .debug_str 0x0000033a 0x11f .\ARM_GCC_541\Debug\Cm0Start.o + 0x32c (size before relaxing) + .debug_str 0x00000459 0xa8 .\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.a(LED.o) + 0x286 (size before relaxing) + .debug_str 0x00000501 0x101 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creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv6-m\libg_nano.a(lib_a-memset.o) + .ARM.attributes + 0x000005c2 0x2c c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtend.o + .ARM.attributes + 0x000005ee 0x1e c:/program files (x86)/cypress/psoc creator/4.2/psoc creator/import/gnu/arm/5.4.1/bin/../lib/gcc/arm-none-eabi/5.4.1/armv6-m/crtn.o + +/DISCARD/ + *(.note.GNU-stack) +OUTPUT(D:\Users\jagumiel\Desktop\PSoC4-MCU-Analog-Designs-master\ADC\CE95272 - PSoC4 SAR ADC and Differential Amplifier\PSoC4_ADC_with_Differential_PreAmplifier.cydsn\ARM_GCC_541\Debug\PSoC4_ADC_with_Differential_PreAmplifier.elf elf32-littlearm) diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/SOURCE_ASM__ARM_GCC_GENERIC.txt b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/SOURCE_ASM__ARM_GCC_GENERIC.txt new file mode 100644 index 0000000..2c4f007 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/SOURCE_ASM__ARM_GCC_GENERIC.txt @@ -0,0 +1 @@ +'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4\CyBootAsmGnu.s' -o .o -T SOURCE_ASM__ARM_GCC_GENERIC -I 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn' -I 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4' -f 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ARM_GCC_541\Debug\.deps\SOURCE_ASM__ARM_GCC_GENERIC.d' \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/SOURCE_C__ARM_GCC_GENERIC.txt b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/SOURCE_C__ARM_GCC_GENERIC.txt new file mode 100644 index 0000000..9fcd385 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/SOURCE_C__ARM_GCC_GENERIC.txt @@ -0,0 +1 @@ +'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\main.c' 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4\ADC.c' 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4\ADC_PM.c' 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4\ADC_INT.c' -o .o -T SOURCE_C__ARM_GCC_GENERIC -I 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn' -I 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4' -f 'D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ARM_GCC_541\Debug\.deps\SOURCE_C__ARM_GCC_GENERIC.d' \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART.lst new file mode 100644 index 0000000..a3fcad7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART.lst @@ -0,0 +1,2062 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "UART.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .global UART_initVar + 20 .bss + 21 .type UART_initVar, %object + 22 .size UART_initVar, 1 + 23 UART_initVar: + 24 0000 00 .space 1 + 25 .global UART_IntrTxMask + 26 0001 00 .align 1 + 27 .type UART_IntrTxMask, %object + 28 .size UART_IntrTxMask, 2 + 29 UART_IntrTxMask: + 30 0002 0000 .space 2 + 31 .section .text.UART_Init,"ax",%progbits + 32 .align 2 + 33 .global UART_Init + 34 .code 16 + 35 .thumb_func + 36 .type UART_Init, %function + 37 UART_Init: + 38 .LFB0: + 39 .file 1 "Generated_Source\\PSoC4\\UART.c" + 1:Generated_Source\PSoC4/UART.c **** /***************************************************************************//** + 2:Generated_Source\PSoC4/UART.c **** * \file UART.c + 3:Generated_Source\PSoC4/UART.c **** * \version 4.0 + 4:Generated_Source\PSoC4/UART.c **** * + 5:Generated_Source\PSoC4/UART.c **** * \brief + 6:Generated_Source\PSoC4/UART.c **** * This file provides the source code to the API for the SCB Component. + 7:Generated_Source\PSoC4/UART.c **** * + 8:Generated_Source\PSoC4/UART.c **** * Note: + 9:Generated_Source\PSoC4/UART.c **** * + 10:Generated_Source\PSoC4/UART.c **** ******************************************************************************* + 11:Generated_Source\PSoC4/UART.c **** * \copyright + 12:Generated_Source\PSoC4/UART.c **** * Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. + 13:Generated_Source\PSoC4/UART.c **** * You may use this file only in accordance with the license, terms, conditions, + 14:Generated_Source\PSoC4/UART.c **** * disclaimers, and limitations in the end user license agreement accompanying + 15:Generated_Source\PSoC4/UART.c **** * the software package with which this file was provided. + 16:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 17:Generated_Source\PSoC4/UART.c **** + 18:Generated_Source\PSoC4/UART.c **** #include "UART_PVT.h" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 2 + + + 19:Generated_Source\PSoC4/UART.c **** + 20:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_I2C_INC) + 21:Generated_Source\PSoC4/UART.c **** #include "UART_I2C_PVT.h" + 22:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_I2C_INC) */ + 23:Generated_Source\PSoC4/UART.c **** + 24:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_EZI2C_INC) + 25:Generated_Source\PSoC4/UART.c **** #include "UART_EZI2C_PVT.h" + 26:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_EZI2C_INC) */ + 27:Generated_Source\PSoC4/UART.c **** + 28:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) + 29:Generated_Source\PSoC4/UART.c **** #include "UART_SPI_UART_PVT.h" + 30:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) */ + 31:Generated_Source\PSoC4/UART.c **** + 32:Generated_Source\PSoC4/UART.c **** + 33:Generated_Source\PSoC4/UART.c **** /*************************************** + 34:Generated_Source\PSoC4/UART.c **** * Run Time Configuration Vars + 35:Generated_Source\PSoC4/UART.c **** ***************************************/ + 36:Generated_Source\PSoC4/UART.c **** + 37:Generated_Source\PSoC4/UART.c **** /* Stores internal component configuration for Unconfigured mode */ + 38:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 39:Generated_Source\PSoC4/UART.c **** /* Common configuration variables */ + 40:Generated_Source\PSoC4/UART.c **** uint8 UART_scbMode = UART_SCB_MODE_UNCONFIG; + 41:Generated_Source\PSoC4/UART.c **** uint8 UART_scbEnableWake; + 42:Generated_Source\PSoC4/UART.c **** uint8 UART_scbEnableIntr; + 43:Generated_Source\PSoC4/UART.c **** + 44:Generated_Source\PSoC4/UART.c **** /* I2C configuration variables */ + 45:Generated_Source\PSoC4/UART.c **** uint8 UART_mode; + 46:Generated_Source\PSoC4/UART.c **** uint8 UART_acceptAddr; + 47:Generated_Source\PSoC4/UART.c **** + 48:Generated_Source\PSoC4/UART.c **** /* SPI/UART configuration variables */ + 49:Generated_Source\PSoC4/UART.c **** volatile uint8 * UART_rxBuffer; + 50:Generated_Source\PSoC4/UART.c **** uint8 UART_rxDataBits; + 51:Generated_Source\PSoC4/UART.c **** uint32 UART_rxBufferSize; + 52:Generated_Source\PSoC4/UART.c **** + 53:Generated_Source\PSoC4/UART.c **** volatile uint8 * UART_txBuffer; + 54:Generated_Source\PSoC4/UART.c **** uint8 UART_txDataBits; + 55:Generated_Source\PSoC4/UART.c **** uint32 UART_txBufferSize; + 56:Generated_Source\PSoC4/UART.c **** + 57:Generated_Source\PSoC4/UART.c **** /* EZI2C configuration variables */ + 58:Generated_Source\PSoC4/UART.c **** uint8 UART_numberOfAddr; + 59:Generated_Source\PSoC4/UART.c **** uint8 UART_subAddrSize; + 60:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 61:Generated_Source\PSoC4/UART.c **** + 62:Generated_Source\PSoC4/UART.c **** + 63:Generated_Source\PSoC4/UART.c **** /*************************************** + 64:Generated_Source\PSoC4/UART.c **** * Common SCB Vars + 65:Generated_Source\PSoC4/UART.c **** ***************************************/ + 66:Generated_Source\PSoC4/UART.c **** /** + 67:Generated_Source\PSoC4/UART.c **** * \addtogroup group_general + 68:Generated_Source\PSoC4/UART.c **** * \{ + 69:Generated_Source\PSoC4/UART.c **** */ + 70:Generated_Source\PSoC4/UART.c **** + 71:Generated_Source\PSoC4/UART.c **** /** UART_initVar indicates whether the UART + 72:Generated_Source\PSoC4/UART.c **** * component has been initialized. The variable is initialized to 0 + 73:Generated_Source\PSoC4/UART.c **** * and set to 1 the first time SCB_Start() is called. This allows + 74:Generated_Source\PSoC4/UART.c **** * the component to restart without reinitialization after the first + 75:Generated_Source\PSoC4/UART.c **** * call to the UART_Start() routine. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 3 + + + 76:Generated_Source\PSoC4/UART.c **** * + 77:Generated_Source\PSoC4/UART.c **** * If re-initialization of the component is required, then the + 78:Generated_Source\PSoC4/UART.c **** * UART_Init() function can be called before the + 79:Generated_Source\PSoC4/UART.c **** * UART_Start() or UART_Enable() function. + 80:Generated_Source\PSoC4/UART.c **** */ + 81:Generated_Source\PSoC4/UART.c **** uint8 UART_initVar = 0u; + 82:Generated_Source\PSoC4/UART.c **** + 83:Generated_Source\PSoC4/UART.c **** + 84:Generated_Source\PSoC4/UART.c **** #if (! (UART_SCB_MODE_I2C_CONST_CFG || \ + 85:Generated_Source\PSoC4/UART.c **** UART_SCB_MODE_EZI2C_CONST_CFG)) + 86:Generated_Source\PSoC4/UART.c **** /** This global variable stores TX interrupt sources after + 87:Generated_Source\PSoC4/UART.c **** * UART_Stop() is called. Only these TX interrupt sources + 88:Generated_Source\PSoC4/UART.c **** * will be restored on a subsequent UART_Enable() call. + 89:Generated_Source\PSoC4/UART.c **** */ + 90:Generated_Source\PSoC4/UART.c **** uint16 UART_IntrTxMask = 0u; + 91:Generated_Source\PSoC4/UART.c **** #endif /* (! (UART_SCB_MODE_I2C_CONST_CFG || \ + 92:Generated_Source\PSoC4/UART.c **** UART_SCB_MODE_EZI2C_CONST_CFG)) */ + 93:Generated_Source\PSoC4/UART.c **** /** \} globals */ + 94:Generated_Source\PSoC4/UART.c **** + 95:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_IRQ_INTERNAL) + 96:Generated_Source\PSoC4/UART.c **** #if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + 97:Generated_Source\PSoC4/UART.c **** void (*UART_customIntrHandler)(void) = NULL; + 98:Generated_Source\PSoC4/UART.c **** #endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ + 99:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_IRQ_INTERNAL) */ + 100:Generated_Source\PSoC4/UART.c **** + 101:Generated_Source\PSoC4/UART.c **** + 102:Generated_Source\PSoC4/UART.c **** /*************************************** + 103:Generated_Source\PSoC4/UART.c **** * Private Function Prototypes + 104:Generated_Source\PSoC4/UART.c **** ***************************************/ + 105:Generated_Source\PSoC4/UART.c **** + 106:Generated_Source\PSoC4/UART.c **** static void UART_ScbEnableIntr(void); + 107:Generated_Source\PSoC4/UART.c **** static void UART_ScbModeStop(void); + 108:Generated_Source\PSoC4/UART.c **** static void UART_ScbModePostEnable(void); + 109:Generated_Source\PSoC4/UART.c **** + 110:Generated_Source\PSoC4/UART.c **** + 111:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 112:Generated_Source\PSoC4/UART.c **** * Function Name: UART_Init + 113:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 114:Generated_Source\PSoC4/UART.c **** * + 115:Generated_Source\PSoC4/UART.c **** * Initializes the UART component to operate in one of the selected + 116:Generated_Source\PSoC4/UART.c **** * configurations: I2C, SPI, UART or EZI2C. + 117:Generated_Source\PSoC4/UART.c **** * When the configuration is set to "Unconfigured SCB", this function does + 118:Generated_Source\PSoC4/UART.c **** * not do any initialization. Use mode-specific initialization APIs instead: + 119:Generated_Source\PSoC4/UART.c **** * UART_I2CInit, UART_SpiInit, + 120:Generated_Source\PSoC4/UART.c **** * UART_UartInit or UART_EzI2CInit. + 121:Generated_Source\PSoC4/UART.c **** * + 122:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 123:Generated_Source\PSoC4/UART.c **** void UART_Init(void) + 124:Generated_Source\PSoC4/UART.c **** { + 40 .loc 1 124 0 + 41 .cfi_startproc + 42 @ args = 0, pretend = 0, frame = 0 + 43 @ frame_needed = 1, uses_anonymous_args = 0 + 44 0000 80B5 push {r7, lr} + 45 .cfi_def_cfa_offset 8 + 46 .cfi_offset 7, -8 + 47 .cfi_offset 14, -4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 4 + + + 48 0002 00AF add r7, sp, #0 + 49 .cfi_def_cfa_register 7 + 125:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 126:Generated_Source\PSoC4/UART.c **** if (UART_SCB_MODE_UNCONFIG_RUNTM_CFG) + 127:Generated_Source\PSoC4/UART.c **** { + 128:Generated_Source\PSoC4/UART.c **** UART_initVar = 0u; + 129:Generated_Source\PSoC4/UART.c **** } + 130:Generated_Source\PSoC4/UART.c **** else + 131:Generated_Source\PSoC4/UART.c **** { + 132:Generated_Source\PSoC4/UART.c **** /* Initialization was done before this function call */ + 133:Generated_Source\PSoC4/UART.c **** } + 134:Generated_Source\PSoC4/UART.c **** + 135:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_I2C_CONST_CFG) + 136:Generated_Source\PSoC4/UART.c **** UART_I2CInit(); + 137:Generated_Source\PSoC4/UART.c **** + 138:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_SPI_CONST_CFG) + 139:Generated_Source\PSoC4/UART.c **** UART_SpiInit(); + 140:Generated_Source\PSoC4/UART.c **** + 141:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_UART_CONST_CFG) + 142:Generated_Source\PSoC4/UART.c **** UART_UartInit(); + 50 .loc 1 142 0 + 51 0004 FFF7FEFF bl UART_UartInit + 143:Generated_Source\PSoC4/UART.c **** + 144:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_EZI2C_CONST_CFG) + 145:Generated_Source\PSoC4/UART.c **** UART_EzI2CInit(); + 146:Generated_Source\PSoC4/UART.c **** + 147:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 148:Generated_Source\PSoC4/UART.c **** } + 52 .loc 1 148 0 + 53 0008 C046 nop + 54 000a BD46 mov sp, r7 + 55 @ sp needed + 56 000c 80BD pop {r7, pc} + 57 .cfi_endproc + 58 .LFE0: + 59 .size UART_Init, .-UART_Init + 60 000e C046 .section .text.UART_Enable,"ax",%progbits + 61 .align 2 + 62 .global UART_Enable + 63 .code 16 + 64 .thumb_func + 65 .type UART_Enable, %function + 66 UART_Enable: + 67 .LFB1: + 149:Generated_Source\PSoC4/UART.c **** + 150:Generated_Source\PSoC4/UART.c **** + 151:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 152:Generated_Source\PSoC4/UART.c **** * Function Name: UART_Enable + 153:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 154:Generated_Source\PSoC4/UART.c **** * + 155:Generated_Source\PSoC4/UART.c **** * Enables UART component operation: activates the hardware and + 156:Generated_Source\PSoC4/UART.c **** * internal interrupt. It also restores TX interrupt sources disabled after the + 157:Generated_Source\PSoC4/UART.c **** * UART_Stop() function was called (note that level-triggered TX + 158:Generated_Source\PSoC4/UART.c **** * interrupt sources remain disabled to not cause code lock-up). + 159:Generated_Source\PSoC4/UART.c **** * For I2C and EZI2C modes the interrupt is internal and mandatory for + 160:Generated_Source\PSoC4/UART.c **** * operation. For SPI and UART modes the interrupt can be configured as none, + 161:Generated_Source\PSoC4/UART.c **** * internal or external. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 5 + + + 162:Generated_Source\PSoC4/UART.c **** * The UART configuration should be not changed when the component + 163:Generated_Source\PSoC4/UART.c **** * is enabled. Any configuration changes should be made after disabling the + 164:Generated_Source\PSoC4/UART.c **** * component. + 165:Generated_Source\PSoC4/UART.c **** * When configuration is set to “Unconfigured UART”, the component + 166:Generated_Source\PSoC4/UART.c **** * must first be initialized to operate in one of the following configurations: + 167:Generated_Source\PSoC4/UART.c **** * I2C, SPI, UART or EZ I2C, using the mode-specific initialization API. + 168:Generated_Source\PSoC4/UART.c **** * Otherwise this function does not enable the component. + 169:Generated_Source\PSoC4/UART.c **** * + 170:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 171:Generated_Source\PSoC4/UART.c **** void UART_Enable(void) + 172:Generated_Source\PSoC4/UART.c **** { + 68 .loc 1 172 0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 1, uses_anonymous_args = 0 + 72 0000 80B5 push {r7, lr} + 73 .cfi_def_cfa_offset 8 + 74 .cfi_offset 7, -8 + 75 .cfi_offset 14, -4 + 76 0002 00AF add r7, sp, #0 + 77 .cfi_def_cfa_register 7 + 173:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 174:Generated_Source\PSoC4/UART.c **** /* Enable SCB block, only if it is already configured */ + 175:Generated_Source\PSoC4/UART.c **** if (!UART_SCB_MODE_UNCONFIG_RUNTM_CFG) + 176:Generated_Source\PSoC4/UART.c **** { + 177:Generated_Source\PSoC4/UART.c **** UART_CTRL_REG |= UART_CTRL_ENABLED; + 178:Generated_Source\PSoC4/UART.c **** + 179:Generated_Source\PSoC4/UART.c **** UART_ScbEnableIntr(); + 180:Generated_Source\PSoC4/UART.c **** + 181:Generated_Source\PSoC4/UART.c **** /* Call PostEnable function specific to current operation mode */ + 182:Generated_Source\PSoC4/UART.c **** UART_ScbModePostEnable(); + 183:Generated_Source\PSoC4/UART.c **** } + 184:Generated_Source\PSoC4/UART.c **** #else + 185:Generated_Source\PSoC4/UART.c **** UART_CTRL_REG |= UART_CTRL_ENABLED; + 78 .loc 1 185 0 + 79 0004 064B ldr r3, .L3 + 80 0006 064A ldr r2, .L3 + 81 0008 1268 ldr r2, [r2] + 82 000a 8021 movs r1, #128 + 83 000c 0906 lsls r1, r1, #24 + 84 000e 0A43 orrs r2, r1 + 85 0010 1A60 str r2, [r3] + 186:Generated_Source\PSoC4/UART.c **** + 187:Generated_Source\PSoC4/UART.c **** UART_ScbEnableIntr(); + 86 .loc 1 187 0 + 87 0012 FFF7FEFF bl UART_ScbEnableIntr + 188:Generated_Source\PSoC4/UART.c **** + 189:Generated_Source\PSoC4/UART.c **** /* Call PostEnable function specific to current operation mode */ + 190:Generated_Source\PSoC4/UART.c **** UART_ScbModePostEnable(); + 88 .loc 1 190 0 + 89 0016 FFF7FEFF bl UART_ScbModePostEnable + 191:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 192:Generated_Source\PSoC4/UART.c **** } + 90 .loc 1 192 0 + 91 001a C046 nop + 92 001c BD46 mov sp, r7 + 93 @ sp needed + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 6 + + + 94 001e 80BD pop {r7, pc} + 95 .L4: + 96 .align 2 + 97 .L3: + 98 0020 00000640 .word 1074135040 + 99 .cfi_endproc + 100 .LFE1: + 101 .size UART_Enable, .-UART_Enable + 102 .section .text.UART_Start,"ax",%progbits + 103 .align 2 + 104 .global UART_Start + 105 .code 16 + 106 .thumb_func + 107 .type UART_Start, %function + 108 UART_Start: + 109 .LFB2: + 193:Generated_Source\PSoC4/UART.c **** + 194:Generated_Source\PSoC4/UART.c **** + 195:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 196:Generated_Source\PSoC4/UART.c **** * Function Name: UART_Start + 197:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 198:Generated_Source\PSoC4/UART.c **** * + 199:Generated_Source\PSoC4/UART.c **** * Invokes UART_Init() and UART_Enable(). + 200:Generated_Source\PSoC4/UART.c **** * After this function call, the component is enabled and ready for operation. + 201:Generated_Source\PSoC4/UART.c **** * When configuration is set to "Unconfigured SCB", the component must first be + 202:Generated_Source\PSoC4/UART.c **** * initialized to operate in one of the following configurations: I2C, SPI, UART + 203:Generated_Source\PSoC4/UART.c **** * or EZI2C. Otherwise this function does not enable the component. + 204:Generated_Source\PSoC4/UART.c **** * + 205:Generated_Source\PSoC4/UART.c **** * \globalvars + 206:Generated_Source\PSoC4/UART.c **** * UART_initVar - used to check initial configuration, modified + 207:Generated_Source\PSoC4/UART.c **** * on first function call. + 208:Generated_Source\PSoC4/UART.c **** * + 209:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 210:Generated_Source\PSoC4/UART.c **** void UART_Start(void) + 211:Generated_Source\PSoC4/UART.c **** { + 110 .loc 1 211 0 + 111 .cfi_startproc + 112 @ args = 0, pretend = 0, frame = 0 + 113 @ frame_needed = 1, uses_anonymous_args = 0 + 114 0000 80B5 push {r7, lr} + 115 .cfi_def_cfa_offset 8 + 116 .cfi_offset 7, -8 + 117 .cfi_offset 14, -4 + 118 0002 00AF add r7, sp, #0 + 119 .cfi_def_cfa_register 7 + 212:Generated_Source\PSoC4/UART.c **** if (0u == UART_initVar) + 120 .loc 1 212 0 + 121 0004 064B ldr r3, .L7 + 122 0006 1B78 ldrb r3, [r3] + 123 0008 002B cmp r3, #0 + 124 000a 04D1 bne .L6 + 213:Generated_Source\PSoC4/UART.c **** { + 214:Generated_Source\PSoC4/UART.c **** UART_Init(); + 125 .loc 1 214 0 + 126 000c FFF7FEFF bl UART_Init + 215:Generated_Source\PSoC4/UART.c **** UART_initVar = 1u; /* Component was initialized */ + 127 .loc 1 215 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 7 + + + 128 0010 034B ldr r3, .L7 + 129 0012 0122 movs r2, #1 + 130 0014 1A70 strb r2, [r3] + 131 .L6: + 216:Generated_Source\PSoC4/UART.c **** } + 217:Generated_Source\PSoC4/UART.c **** + 218:Generated_Source\PSoC4/UART.c **** UART_Enable(); + 132 .loc 1 218 0 + 133 0016 FFF7FEFF bl UART_Enable + 219:Generated_Source\PSoC4/UART.c **** } + 134 .loc 1 219 0 + 135 001a C046 nop + 136 001c BD46 mov sp, r7 + 137 @ sp needed + 138 001e 80BD pop {r7, pc} + 139 .L8: + 140 .align 2 + 141 .L7: + 142 0020 00000000 .word UART_initVar + 143 .cfi_endproc + 144 .LFE2: + 145 .size UART_Start, .-UART_Start + 146 .section .text.UART_Stop,"ax",%progbits + 147 .align 2 + 148 .global UART_Stop + 149 .code 16 + 150 .thumb_func + 151 .type UART_Stop, %function + 152 UART_Stop: + 153 .LFB3: + 220:Generated_Source\PSoC4/UART.c **** + 221:Generated_Source\PSoC4/UART.c **** + 222:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 223:Generated_Source\PSoC4/UART.c **** * Function Name: UART_Stop + 224:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 225:Generated_Source\PSoC4/UART.c **** * + 226:Generated_Source\PSoC4/UART.c **** * Disables the UART component: disable the hardware and internal + 227:Generated_Source\PSoC4/UART.c **** * interrupt. It also disables all TX interrupt sources so as not to cause an + 228:Generated_Source\PSoC4/UART.c **** * unexpected interrupt trigger because after the component is enabled, the + 229:Generated_Source\PSoC4/UART.c **** * TX FIFO is empty. + 230:Generated_Source\PSoC4/UART.c **** * Refer to the function UART_Enable() for the interrupt + 231:Generated_Source\PSoC4/UART.c **** * configuration details. + 232:Generated_Source\PSoC4/UART.c **** * This function disables the SCB component without checking to see if + 233:Generated_Source\PSoC4/UART.c **** * communication is in progress. Before calling this function it may be + 234:Generated_Source\PSoC4/UART.c **** * necessary to check the status of communication to make sure communication + 235:Generated_Source\PSoC4/UART.c **** * is complete. If this is not done then communication could be stopped mid + 236:Generated_Source\PSoC4/UART.c **** * byte and corrupted data could result. + 237:Generated_Source\PSoC4/UART.c **** * + 238:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 239:Generated_Source\PSoC4/UART.c **** void UART_Stop(void) + 240:Generated_Source\PSoC4/UART.c **** { + 154 .loc 1 240 0 + 155 .cfi_startproc + 156 @ args = 0, pretend = 0, frame = 0 + 157 @ frame_needed = 1, uses_anonymous_args = 0 + 158 0000 80B5 push {r7, lr} + 159 .cfi_def_cfa_offset 8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 8 + + + 160 .cfi_offset 7, -8 + 161 .cfi_offset 14, -4 + 162 0002 00AF add r7, sp, #0 + 163 .cfi_def_cfa_register 7 + 241:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_IRQ_INTERNAL) + 242:Generated_Source\PSoC4/UART.c **** UART_DisableInt(); + 243:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_IRQ_INTERNAL) */ + 244:Generated_Source\PSoC4/UART.c **** + 245:Generated_Source\PSoC4/UART.c **** /* Call Stop function specific to current operation mode */ + 246:Generated_Source\PSoC4/UART.c **** UART_ScbModeStop(); + 164 .loc 1 246 0 + 165 0004 FFF7FEFF bl UART_ScbModeStop + 247:Generated_Source\PSoC4/UART.c **** + 248:Generated_Source\PSoC4/UART.c **** /* Disable SCB IP */ + 249:Generated_Source\PSoC4/UART.c **** UART_CTRL_REG &= (uint32) ~UART_CTRL_ENABLED; + 166 .loc 1 249 0 + 167 0008 054B ldr r3, .L10 + 168 000a 054A ldr r2, .L10 + 169 000c 1268 ldr r2, [r2] + 170 000e 5200 lsls r2, r2, #1 + 171 0010 5208 lsrs r2, r2, #1 + 172 0012 1A60 str r2, [r3] + 250:Generated_Source\PSoC4/UART.c **** + 251:Generated_Source\PSoC4/UART.c **** /* Disable all TX interrupt sources so as not to cause an unexpected + 252:Generated_Source\PSoC4/UART.c **** * interrupt trigger after the component will be enabled because the + 253:Generated_Source\PSoC4/UART.c **** * TX FIFO is empty. + 254:Generated_Source\PSoC4/UART.c **** * For SCB IP v0, it is critical as it does not mask-out interrupt + 255:Generated_Source\PSoC4/UART.c **** * sources when it is disabled. This can cause a code lock-up in the + 256:Generated_Source\PSoC4/UART.c **** * interrupt handler because TX FIFO cannot be loaded after the block + 257:Generated_Source\PSoC4/UART.c **** * is disabled. + 258:Generated_Source\PSoC4/UART.c **** */ + 259:Generated_Source\PSoC4/UART.c **** UART_SetTxInterruptMode(UART_NO_INTR_SOURCES); + 173 .loc 1 259 0 + 174 0014 034B ldr r3, .L10+4 + 175 0016 0022 movs r2, #0 + 176 0018 1A60 str r2, [r3] + 260:Generated_Source\PSoC4/UART.c **** + 261:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_IRQ_INTERNAL) + 262:Generated_Source\PSoC4/UART.c **** UART_ClearPendingInt(); + 263:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_IRQ_INTERNAL) */ + 264:Generated_Source\PSoC4/UART.c **** } + 177 .loc 1 264 0 + 178 001a C046 nop + 179 001c BD46 mov sp, r7 + 180 @ sp needed + 181 001e 80BD pop {r7, pc} + 182 .L11: + 183 .align 2 + 184 .L10: + 185 0020 00000640 .word 1074135040 + 186 0024 880F0640 .word 1074139016 + 187 .cfi_endproc + 188 .LFE3: + 189 .size UART_Stop, .-UART_Stop + 190 .section .text.UART_SetRxFifoLevel,"ax",%progbits + 191 .align 2 + 192 .global UART_SetRxFifoLevel + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 9 + + + 193 .code 16 + 194 .thumb_func + 195 .type UART_SetRxFifoLevel, %function + 196 UART_SetRxFifoLevel: + 197 .LFB4: + 265:Generated_Source\PSoC4/UART.c **** + 266:Generated_Source\PSoC4/UART.c **** + 267:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 268:Generated_Source\PSoC4/UART.c **** * Function Name: UART_SetRxFifoLevel + 269:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 270:Generated_Source\PSoC4/UART.c **** * + 271:Generated_Source\PSoC4/UART.c **** * Sets level in the RX FIFO to generate a RX level interrupt. + 272:Generated_Source\PSoC4/UART.c **** * When the RX FIFO has more entries than the RX FIFO level an RX level + 273:Generated_Source\PSoC4/UART.c **** * interrupt request is generated. + 274:Generated_Source\PSoC4/UART.c **** * + 275:Generated_Source\PSoC4/UART.c **** * \param level: Level in the RX FIFO to generate RX level interrupt. + 276:Generated_Source\PSoC4/UART.c **** * The range of valid level values is between 0 and RX FIFO depth - 1. + 277:Generated_Source\PSoC4/UART.c **** * + 278:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 279:Generated_Source\PSoC4/UART.c **** void UART_SetRxFifoLevel(uint32 level) + 280:Generated_Source\PSoC4/UART.c **** { + 198 .loc 1 280 0 + 199 .cfi_startproc + 200 @ args = 0, pretend = 0, frame = 16 + 201 @ frame_needed = 1, uses_anonymous_args = 0 + 202 0000 80B5 push {r7, lr} + 203 .cfi_def_cfa_offset 8 + 204 .cfi_offset 7, -8 + 205 .cfi_offset 14, -4 + 206 0002 84B0 sub sp, sp, #16 + 207 .cfi_def_cfa_offset 24 + 208 0004 00AF add r7, sp, #0 + 209 .cfi_def_cfa_register 7 + 210 0006 7860 str r0, [r7, #4] + 281:Generated_Source\PSoC4/UART.c **** uint32 rxFifoCtrl; + 282:Generated_Source\PSoC4/UART.c **** + 283:Generated_Source\PSoC4/UART.c **** rxFifoCtrl = UART_RX_FIFO_CTRL_REG; + 211 .loc 1 283 0 + 212 0008 094B ldr r3, .L13 + 213 000a 1B68 ldr r3, [r3] + 214 000c FB60 str r3, [r7, #12] + 284:Generated_Source\PSoC4/UART.c **** + 285:Generated_Source\PSoC4/UART.c **** rxFifoCtrl &= ((uint32) ~UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + 215 .loc 1 285 0 + 216 000e FB68 ldr r3, [r7, #12] + 217 0010 0722 movs r2, #7 + 218 0012 9343 bics r3, r2 + 219 0014 FB60 str r3, [r7, #12] + 286:Generated_Source\PSoC4/UART.c **** rxFifoCtrl |= ((uint32) (UART_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + 220 .loc 1 286 0 + 221 0016 7B68 ldr r3, [r7, #4] + 222 0018 0722 movs r2, #7 + 223 001a 1340 ands r3, r2 + 224 001c FA68 ldr r2, [r7, #12] + 225 001e 1343 orrs r3, r2 + 226 0020 FB60 str r3, [r7, #12] + 287:Generated_Source\PSoC4/UART.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 10 + + + 288:Generated_Source\PSoC4/UART.c **** UART_RX_FIFO_CTRL_REG = rxFifoCtrl; + 227 .loc 1 288 0 + 228 0022 034B ldr r3, .L13 + 229 0024 FA68 ldr r2, [r7, #12] + 230 0026 1A60 str r2, [r3] + 289:Generated_Source\PSoC4/UART.c **** } + 231 .loc 1 289 0 + 232 0028 C046 nop + 233 002a BD46 mov sp, r7 + 234 002c 04B0 add sp, sp, #16 + 235 @ sp needed + 236 002e 80BD pop {r7, pc} + 237 .L14: + 238 .align 2 + 239 .L13: + 240 0030 04030640 .word 1074135812 + 241 .cfi_endproc + 242 .LFE4: + 243 .size UART_SetRxFifoLevel, .-UART_SetRxFifoLevel + 244 .section .text.UART_SetTxFifoLevel,"ax",%progbits + 245 .align 2 + 246 .global UART_SetTxFifoLevel + 247 .code 16 + 248 .thumb_func + 249 .type UART_SetTxFifoLevel, %function + 250 UART_SetTxFifoLevel: + 251 .LFB5: + 290:Generated_Source\PSoC4/UART.c **** + 291:Generated_Source\PSoC4/UART.c **** + 292:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 293:Generated_Source\PSoC4/UART.c **** * Function Name: UART_SetTxFifoLevel + 294:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 295:Generated_Source\PSoC4/UART.c **** * + 296:Generated_Source\PSoC4/UART.c **** * Sets level in the TX FIFO to generate a TX level interrupt. + 297:Generated_Source\PSoC4/UART.c **** * When the TX FIFO has less entries than the TX FIFO level an TX level + 298:Generated_Source\PSoC4/UART.c **** * interrupt request is generated. + 299:Generated_Source\PSoC4/UART.c **** * + 300:Generated_Source\PSoC4/UART.c **** * \param level: Level in the TX FIFO to generate TX level interrupt. + 301:Generated_Source\PSoC4/UART.c **** * The range of valid level values is between 0 and TX FIFO depth - 1. + 302:Generated_Source\PSoC4/UART.c **** * + 303:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 304:Generated_Source\PSoC4/UART.c **** void UART_SetTxFifoLevel(uint32 level) + 305:Generated_Source\PSoC4/UART.c **** { + 252 .loc 1 305 0 + 253 .cfi_startproc + 254 @ args = 0, pretend = 0, frame = 16 + 255 @ frame_needed = 1, uses_anonymous_args = 0 + 256 0000 80B5 push {r7, lr} + 257 .cfi_def_cfa_offset 8 + 258 .cfi_offset 7, -8 + 259 .cfi_offset 14, -4 + 260 0002 84B0 sub sp, sp, #16 + 261 .cfi_def_cfa_offset 24 + 262 0004 00AF add r7, sp, #0 + 263 .cfi_def_cfa_register 7 + 264 0006 7860 str r0, [r7, #4] + 306:Generated_Source\PSoC4/UART.c **** uint32 txFifoCtrl; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 11 + + + 307:Generated_Source\PSoC4/UART.c **** + 308:Generated_Source\PSoC4/UART.c **** txFifoCtrl = UART_TX_FIFO_CTRL_REG; + 265 .loc 1 308 0 + 266 0008 094B ldr r3, .L16 + 267 000a 1B68 ldr r3, [r3] + 268 000c FB60 str r3, [r7, #12] + 309:Generated_Source\PSoC4/UART.c **** + 310:Generated_Source\PSoC4/UART.c **** txFifoCtrl &= ((uint32) ~UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + 269 .loc 1 310 0 + 270 000e FB68 ldr r3, [r7, #12] + 271 0010 0722 movs r2, #7 + 272 0012 9343 bics r3, r2 + 273 0014 FB60 str r3, [r7, #12] + 311:Generated_Source\PSoC4/UART.c **** txFifoCtrl |= ((uint32) (UART_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + 274 .loc 1 311 0 + 275 0016 7B68 ldr r3, [r7, #4] + 276 0018 0722 movs r2, #7 + 277 001a 1340 ands r3, r2 + 278 001c FA68 ldr r2, [r7, #12] + 279 001e 1343 orrs r3, r2 + 280 0020 FB60 str r3, [r7, #12] + 312:Generated_Source\PSoC4/UART.c **** + 313:Generated_Source\PSoC4/UART.c **** UART_TX_FIFO_CTRL_REG = txFifoCtrl; + 281 .loc 1 313 0 + 282 0022 034B ldr r3, .L16 + 283 0024 FA68 ldr r2, [r7, #12] + 284 0026 1A60 str r2, [r3] + 314:Generated_Source\PSoC4/UART.c **** } + 285 .loc 1 314 0 + 286 0028 C046 nop + 287 002a BD46 mov sp, r7 + 288 002c 04B0 add sp, sp, #16 + 289 @ sp needed + 290 002e 80BD pop {r7, pc} + 291 .L17: + 292 .align 2 + 293 .L16: + 294 0030 04020640 .word 1074135556 + 295 .cfi_endproc + 296 .LFE5: + 297 .size UART_SetTxFifoLevel, .-UART_SetTxFifoLevel + 298 .section .text.UART_ScbEnableIntr,"ax",%progbits + 299 .align 2 + 300 .code 16 + 301 .thumb_func + 302 .type UART_ScbEnableIntr, %function + 303 UART_ScbEnableIntr: + 304 .LFB6: + 315:Generated_Source\PSoC4/UART.c **** + 316:Generated_Source\PSoC4/UART.c **** + 317:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_IRQ_INTERNAL) + 318:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 319:Generated_Source\PSoC4/UART.c **** * Function Name: UART_SetCustomInterruptHandler + 320:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 321:Generated_Source\PSoC4/UART.c **** * + 322:Generated_Source\PSoC4/UART.c **** * Registers a function to be called by the internal interrupt handler. + 323:Generated_Source\PSoC4/UART.c **** * First the function that is registered is called, then the internal interrupt + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 12 + + + 324:Generated_Source\PSoC4/UART.c **** * handler performs any operation such as software buffer management functions + 325:Generated_Source\PSoC4/UART.c **** * before the interrupt returns. It is the user's responsibility not to break + 326:Generated_Source\PSoC4/UART.c **** * the software buffer operations. Only one custom handler is supported, which + 327:Generated_Source\PSoC4/UART.c **** * is the function provided by the most recent call. + 328:Generated_Source\PSoC4/UART.c **** * At the initialization time no custom handler is registered. + 329:Generated_Source\PSoC4/UART.c **** * + 330:Generated_Source\PSoC4/UART.c **** * \param func: Pointer to the function to register. + 331:Generated_Source\PSoC4/UART.c **** * The value NULL indicates to remove the current custom interrupt + 332:Generated_Source\PSoC4/UART.c **** * handler. + 333:Generated_Source\PSoC4/UART.c **** * + 334:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 335:Generated_Source\PSoC4/UART.c **** void UART_SetCustomInterruptHandler(void (*func)(void)) + 336:Generated_Source\PSoC4/UART.c **** { + 337:Generated_Source\PSoC4/UART.c **** #if !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) + 338:Generated_Source\PSoC4/UART.c **** UART_customIntrHandler = func; /* Register interrupt handler */ + 339:Generated_Source\PSoC4/UART.c **** #else + 340:Generated_Source\PSoC4/UART.c **** if (NULL != func) + 341:Generated_Source\PSoC4/UART.c **** { + 342:Generated_Source\PSoC4/UART.c **** /* Suppress compiler warning */ + 343:Generated_Source\PSoC4/UART.c **** } + 344:Generated_Source\PSoC4/UART.c **** #endif /* !defined (CY_REMOVE_UART_CUSTOM_INTR_HANDLER) */ + 345:Generated_Source\PSoC4/UART.c **** } + 346:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_IRQ_INTERNAL) */ + 347:Generated_Source\PSoC4/UART.c **** + 348:Generated_Source\PSoC4/UART.c **** + 349:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 350:Generated_Source\PSoC4/UART.c **** * Function Name: UART_ScbModeEnableIntr + 351:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 352:Generated_Source\PSoC4/UART.c **** * + 353:Generated_Source\PSoC4/UART.c **** * Enables an interrupt for a specific mode. + 354:Generated_Source\PSoC4/UART.c **** * + 355:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 356:Generated_Source\PSoC4/UART.c **** static void UART_ScbEnableIntr(void) + 357:Generated_Source\PSoC4/UART.c **** { + 305 .loc 1 357 0 + 306 .cfi_startproc + 307 @ args = 0, pretend = 0, frame = 0 + 308 @ frame_needed = 1, uses_anonymous_args = 0 + 309 0000 80B5 push {r7, lr} + 310 .cfi_def_cfa_offset 8 + 311 .cfi_offset 7, -8 + 312 .cfi_offset 14, -4 + 313 0002 00AF add r7, sp, #0 + 314 .cfi_def_cfa_register 7 + 358:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_IRQ_INTERNAL) + 359:Generated_Source\PSoC4/UART.c **** /* Enable interrupt in NVIC */ + 360:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 361:Generated_Source\PSoC4/UART.c **** if (0u != UART_scbEnableIntr) + 362:Generated_Source\PSoC4/UART.c **** { + 363:Generated_Source\PSoC4/UART.c **** UART_EnableInt(); + 364:Generated_Source\PSoC4/UART.c **** } + 365:Generated_Source\PSoC4/UART.c **** + 366:Generated_Source\PSoC4/UART.c **** #else + 367:Generated_Source\PSoC4/UART.c **** UART_EnableInt(); + 368:Generated_Source\PSoC4/UART.c **** + 369:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 370:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_IRQ_INTERNAL) */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 13 + + + 371:Generated_Source\PSoC4/UART.c **** } + 315 .loc 1 371 0 + 316 0004 C046 nop + 317 0006 BD46 mov sp, r7 + 318 @ sp needed + 319 0008 80BD pop {r7, pc} + 320 .cfi_endproc + 321 .LFE6: + 322 .size UART_ScbEnableIntr, .-UART_ScbEnableIntr + 323 000a C046 .section .text.UART_ScbModePostEnable,"ax",%progbits + 324 .align 2 + 325 .code 16 + 326 .thumb_func + 327 .type UART_ScbModePostEnable, %function + 328 UART_ScbModePostEnable: + 329 .LFB7: + 372:Generated_Source\PSoC4/UART.c **** + 373:Generated_Source\PSoC4/UART.c **** + 374:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 375:Generated_Source\PSoC4/UART.c **** * Function Name: UART_ScbModePostEnable + 376:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 377:Generated_Source\PSoC4/UART.c **** * + 378:Generated_Source\PSoC4/UART.c **** * Calls the PostEnable function for a specific operation mode. + 379:Generated_Source\PSoC4/UART.c **** * + 380:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 381:Generated_Source\PSoC4/UART.c **** static void UART_ScbModePostEnable(void) + 382:Generated_Source\PSoC4/UART.c **** { + 330 .loc 1 382 0 + 331 .cfi_startproc + 332 @ args = 0, pretend = 0, frame = 0 + 333 @ frame_needed = 1, uses_anonymous_args = 0 + 334 0000 80B5 push {r7, lr} + 335 .cfi_def_cfa_offset 8 + 336 .cfi_offset 7, -8 + 337 .cfi_offset 14, -4 + 338 0002 00AF add r7, sp, #0 + 339 .cfi_def_cfa_register 7 + 383:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 384:Generated_Source\PSoC4/UART.c **** #if (!UART_CY_SCBIP_V1) + 385:Generated_Source\PSoC4/UART.c **** if (UART_SCB_MODE_SPI_RUNTM_CFG) + 386:Generated_Source\PSoC4/UART.c **** { + 387:Generated_Source\PSoC4/UART.c **** UART_SpiPostEnable(); + 388:Generated_Source\PSoC4/UART.c **** } + 389:Generated_Source\PSoC4/UART.c **** else if (UART_SCB_MODE_UART_RUNTM_CFG) + 390:Generated_Source\PSoC4/UART.c **** { + 391:Generated_Source\PSoC4/UART.c **** UART_UartPostEnable(); + 392:Generated_Source\PSoC4/UART.c **** } + 393:Generated_Source\PSoC4/UART.c **** else + 394:Generated_Source\PSoC4/UART.c **** { + 395:Generated_Source\PSoC4/UART.c **** /* Unknown mode: do nothing */ + 396:Generated_Source\PSoC4/UART.c **** } + 397:Generated_Source\PSoC4/UART.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 398:Generated_Source\PSoC4/UART.c **** + 399:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_SPI_CONST_CFG) + 400:Generated_Source\PSoC4/UART.c **** UART_SpiPostEnable(); + 401:Generated_Source\PSoC4/UART.c **** + 402:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_UART_CONST_CFG) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 14 + + + 403:Generated_Source\PSoC4/UART.c **** UART_UartPostEnable(); + 340 .loc 1 403 0 + 341 0004 FFF7FEFF bl UART_UartPostEnable + 404:Generated_Source\PSoC4/UART.c **** + 405:Generated_Source\PSoC4/UART.c **** #else + 406:Generated_Source\PSoC4/UART.c **** /* Unknown mode: do nothing */ + 407:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 408:Generated_Source\PSoC4/UART.c **** } + 342 .loc 1 408 0 + 343 0008 C046 nop + 344 000a BD46 mov sp, r7 + 345 @ sp needed + 346 000c 80BD pop {r7, pc} + 347 .cfi_endproc + 348 .LFE7: + 349 .size UART_ScbModePostEnable, .-UART_ScbModePostEnable + 350 000e C046 .section .text.UART_ScbModeStop,"ax",%progbits + 351 .align 2 + 352 .code 16 + 353 .thumb_func + 354 .type UART_ScbModeStop, %function + 355 UART_ScbModeStop: + 356 .LFB8: + 409:Generated_Source\PSoC4/UART.c **** + 410:Generated_Source\PSoC4/UART.c **** + 411:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 412:Generated_Source\PSoC4/UART.c **** * Function Name: UART_ScbModeStop + 413:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 414:Generated_Source\PSoC4/UART.c **** * + 415:Generated_Source\PSoC4/UART.c **** * Calls the Stop function for a specific operation mode. + 416:Generated_Source\PSoC4/UART.c **** * + 417:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 418:Generated_Source\PSoC4/UART.c **** static void UART_ScbModeStop(void) + 419:Generated_Source\PSoC4/UART.c **** { + 357 .loc 1 419 0 + 358 .cfi_startproc + 359 @ args = 0, pretend = 0, frame = 0 + 360 @ frame_needed = 1, uses_anonymous_args = 0 + 361 0000 80B5 push {r7, lr} + 362 .cfi_def_cfa_offset 8 + 363 .cfi_offset 7, -8 + 364 .cfi_offset 14, -4 + 365 0002 00AF add r7, sp, #0 + 366 .cfi_def_cfa_register 7 + 420:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 421:Generated_Source\PSoC4/UART.c **** if (UART_SCB_MODE_I2C_RUNTM_CFG) + 422:Generated_Source\PSoC4/UART.c **** { + 423:Generated_Source\PSoC4/UART.c **** UART_I2CStop(); + 424:Generated_Source\PSoC4/UART.c **** } + 425:Generated_Source\PSoC4/UART.c **** else if (UART_SCB_MODE_EZI2C_RUNTM_CFG) + 426:Generated_Source\PSoC4/UART.c **** { + 427:Generated_Source\PSoC4/UART.c **** UART_EzI2CStop(); + 428:Generated_Source\PSoC4/UART.c **** } + 429:Generated_Source\PSoC4/UART.c **** #if (!UART_CY_SCBIP_V1) + 430:Generated_Source\PSoC4/UART.c **** else if (UART_SCB_MODE_SPI_RUNTM_CFG) + 431:Generated_Source\PSoC4/UART.c **** { + 432:Generated_Source\PSoC4/UART.c **** UART_SpiStop(); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 15 + + + 433:Generated_Source\PSoC4/UART.c **** } + 434:Generated_Source\PSoC4/UART.c **** else if (UART_SCB_MODE_UART_RUNTM_CFG) + 435:Generated_Source\PSoC4/UART.c **** { + 436:Generated_Source\PSoC4/UART.c **** UART_UartStop(); + 437:Generated_Source\PSoC4/UART.c **** } + 438:Generated_Source\PSoC4/UART.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 439:Generated_Source\PSoC4/UART.c **** else + 440:Generated_Source\PSoC4/UART.c **** { + 441:Generated_Source\PSoC4/UART.c **** /* Unknown mode: do nothing */ + 442:Generated_Source\PSoC4/UART.c **** } + 443:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_I2C_CONST_CFG) + 444:Generated_Source\PSoC4/UART.c **** UART_I2CStop(); + 445:Generated_Source\PSoC4/UART.c **** + 446:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_EZI2C_CONST_CFG) + 447:Generated_Source\PSoC4/UART.c **** UART_EzI2CStop(); + 448:Generated_Source\PSoC4/UART.c **** + 449:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_SPI_CONST_CFG) + 450:Generated_Source\PSoC4/UART.c **** UART_SpiStop(); + 451:Generated_Source\PSoC4/UART.c **** + 452:Generated_Source\PSoC4/UART.c **** #elif (UART_SCB_MODE_UART_CONST_CFG) + 453:Generated_Source\PSoC4/UART.c **** UART_UartStop(); + 367 .loc 1 453 0 + 368 0004 FFF7FEFF bl UART_UartStop + 454:Generated_Source\PSoC4/UART.c **** + 455:Generated_Source\PSoC4/UART.c **** #else + 456:Generated_Source\PSoC4/UART.c **** /* Unknown mode: do nothing */ + 457:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 458:Generated_Source\PSoC4/UART.c **** } + 369 .loc 1 458 0 + 370 0008 C046 nop + 371 000a BD46 mov sp, r7 + 372 @ sp needed + 373 000c 80BD pop {r7, pc} + 374 .cfi_endproc + 375 .LFE8: + 376 .size UART_ScbModeStop, .-UART_ScbModeStop + 377 000e C046 .section .text.UART_I2CSlaveNackGeneration,"ax",%progbits + 378 .align 2 + 379 .global UART_I2CSlaveNackGeneration + 380 .code 16 + 381 .thumb_func + 382 .type UART_I2CSlaveNackGeneration, %function + 383 UART_I2CSlaveNackGeneration: + 384 .LFB9: + 459:Generated_Source\PSoC4/UART.c **** + 460:Generated_Source\PSoC4/UART.c **** + 461:Generated_Source\PSoC4/UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 462:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 463:Generated_Source\PSoC4/UART.c **** * Function Name: UART_SetPins + 464:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 465:Generated_Source\PSoC4/UART.c **** * + 466:Generated_Source\PSoC4/UART.c **** * Sets the pins settings accordingly to the selected operation mode. + 467:Generated_Source\PSoC4/UART.c **** * Only available in the Unconfigured operation mode. The mode specific + 468:Generated_Source\PSoC4/UART.c **** * initialization function calls it. + 469:Generated_Source\PSoC4/UART.c **** * Pins configuration is set by PSoC Creator when a specific mode of operation + 470:Generated_Source\PSoC4/UART.c **** * is selected in design time. + 471:Generated_Source\PSoC4/UART.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 16 + + + 472:Generated_Source\PSoC4/UART.c **** * \param mode: Mode of SCB operation. + 473:Generated_Source\PSoC4/UART.c **** * \param subMode: Sub-mode of SCB operation. It is only required for SPI and UART + 474:Generated_Source\PSoC4/UART.c **** * modes. + 475:Generated_Source\PSoC4/UART.c **** * \param uartEnableMask: enables TX or RX direction and RTS and CTS signals. + 476:Generated_Source\PSoC4/UART.c **** * + 477:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 478:Generated_Source\PSoC4/UART.c **** void UART_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask) + 479:Generated_Source\PSoC4/UART.c **** { + 480:Generated_Source\PSoC4/UART.c **** uint32 pinsDm[UART_SCB_PINS_NUMBER]; + 481:Generated_Source\PSoC4/UART.c **** uint32 i; + 482:Generated_Source\PSoC4/UART.c **** + 483:Generated_Source\PSoC4/UART.c **** #if (!UART_CY_SCBIP_V1) + 484:Generated_Source\PSoC4/UART.c **** uint32 pinsInBuf = 0u; + 485:Generated_Source\PSoC4/UART.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 486:Generated_Source\PSoC4/UART.c **** + 487:Generated_Source\PSoC4/UART.c **** uint32 hsiomSel[UART_SCB_PINS_NUMBER] = + 488:Generated_Source\PSoC4/UART.c **** { + 489:Generated_Source\PSoC4/UART.c **** UART_RX_SCL_MOSI_HSIOM_SEL_GPIO, + 490:Generated_Source\PSoC4/UART.c **** UART_TX_SDA_MISO_HSIOM_SEL_GPIO, + 491:Generated_Source\PSoC4/UART.c **** 0u, + 492:Generated_Source\PSoC4/UART.c **** 0u, + 493:Generated_Source\PSoC4/UART.c **** 0u, + 494:Generated_Source\PSoC4/UART.c **** 0u, + 495:Generated_Source\PSoC4/UART.c **** 0u, + 496:Generated_Source\PSoC4/UART.c **** }; + 497:Generated_Source\PSoC4/UART.c **** + 498:Generated_Source\PSoC4/UART.c **** #if (UART_CY_SCBIP_V1) + 499:Generated_Source\PSoC4/UART.c **** /* Supress compiler warning. */ + 500:Generated_Source\PSoC4/UART.c **** if ((0u == subMode) || (0u == uartEnableMask)) + 501:Generated_Source\PSoC4/UART.c **** { + 502:Generated_Source\PSoC4/UART.c **** } + 503:Generated_Source\PSoC4/UART.c **** #endif /* (UART_CY_SCBIP_V1) */ + 504:Generated_Source\PSoC4/UART.c **** + 505:Generated_Source\PSoC4/UART.c **** /* Set default HSIOM to GPIO and Drive Mode to Analog Hi-Z */ + 506:Generated_Source\PSoC4/UART.c **** for (i = 0u; i < UART_SCB_PINS_NUMBER; i++) + 507:Generated_Source\PSoC4/UART.c **** { + 508:Generated_Source\PSoC4/UART.c **** pinsDm[i] = UART_PIN_DM_ALG_HIZ; + 509:Generated_Source\PSoC4/UART.c **** } + 510:Generated_Source\PSoC4/UART.c **** + 511:Generated_Source\PSoC4/UART.c **** if ((UART_SCB_MODE_I2C == mode) || + 512:Generated_Source\PSoC4/UART.c **** (UART_SCB_MODE_EZI2C == mode)) + 513:Generated_Source\PSoC4/UART.c **** { + 514:Generated_Source\PSoC4/UART.c **** #if (UART_RX_SCL_MOSI_PIN) + 515:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_I2C; + 516:Generated_Source\PSoC4/UART.c **** pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; + 517:Generated_Source\PSoC4/UART.c **** #elif (UART_RX_WAKE_SCL_MOSI_PIN) + 518:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_I2C; + 519:Generated_Source\PSoC4/UART.c **** pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; + 520:Generated_Source\PSoC4/UART.c **** #else + 521:Generated_Source\PSoC4/UART.c **** #endif /* (UART_RX_SCL_MOSI_PIN) */ + 522:Generated_Source\PSoC4/UART.c **** + 523:Generated_Source\PSoC4/UART.c **** #if (UART_TX_SDA_MISO_PIN) + 524:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_I2C; + 525:Generated_Source\PSoC4/UART.c **** pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; + 526:Generated_Source\PSoC4/UART.c **** #endif /* (UART_TX_SDA_MISO_PIN) */ + 527:Generated_Source\PSoC4/UART.c **** } + 528:Generated_Source\PSoC4/UART.c **** #if (!UART_CY_SCBIP_V1) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 17 + + + 529:Generated_Source\PSoC4/UART.c **** else if (UART_SCB_MODE_SPI == mode) + 530:Generated_Source\PSoC4/UART.c **** { + 531:Generated_Source\PSoC4/UART.c **** #if (UART_RX_SCL_MOSI_PIN) + 532:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_SPI; + 533:Generated_Source\PSoC4/UART.c **** #elif (UART_RX_WAKE_SCL_MOSI_PIN) + 534:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_SPI; + 535:Generated_Source\PSoC4/UART.c **** #else + 536:Generated_Source\PSoC4/UART.c **** #endif /* (UART_RX_SCL_MOSI_PIN) */ + 537:Generated_Source\PSoC4/UART.c **** + 538:Generated_Source\PSoC4/UART.c **** #if (UART_TX_SDA_MISO_PIN) + 539:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_SPI; + 540:Generated_Source\PSoC4/UART.c **** #endif /* (UART_TX_SDA_MISO_PIN) */ + 541:Generated_Source\PSoC4/UART.c **** + 542:Generated_Source\PSoC4/UART.c **** #if (UART_SCLK_PIN) + 543:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SCLK_PIN_INDEX] = UART_SCLK_HSIOM_SEL_SPI; + 544:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCLK_PIN) */ + 545:Generated_Source\PSoC4/UART.c **** + 546:Generated_Source\PSoC4/UART.c **** if (UART_SPI_SLAVE == subMode) + 547:Generated_Source\PSoC4/UART.c **** { + 548:Generated_Source\PSoC4/UART.c **** /* Slave */ + 549:Generated_Source\PSoC4/UART.c **** pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + 550:Generated_Source\PSoC4/UART.c **** pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; + 551:Generated_Source\PSoC4/UART.c **** pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + 552:Generated_Source\PSoC4/UART.c **** + 553:Generated_Source\PSoC4/UART.c **** #if (UART_SS0_PIN) + 554:Generated_Source\PSoC4/UART.c **** /* Only SS0 is valid choice for Slave */ + 555:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_SPI; + 556:Generated_Source\PSoC4/UART.c **** pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + 557:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS0_PIN) */ + 558:Generated_Source\PSoC4/UART.c **** + 559:Generated_Source\PSoC4/UART.c **** #if (UART_TX_SDA_MISO_PIN) + 560:Generated_Source\PSoC4/UART.c **** /* Disable input buffer */ + 561:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; + 562:Generated_Source\PSoC4/UART.c **** #endif /* (UART_TX_SDA_MISO_PIN) */ + 563:Generated_Source\PSoC4/UART.c **** } + 564:Generated_Source\PSoC4/UART.c **** else + 565:Generated_Source\PSoC4/UART.c **** { + 566:Generated_Source\PSoC4/UART.c **** /* (Master) */ + 567:Generated_Source\PSoC4/UART.c **** pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_STRONG; + 568:Generated_Source\PSoC4/UART.c **** pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + 569:Generated_Source\PSoC4/UART.c **** pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_STRONG; + 570:Generated_Source\PSoC4/UART.c **** + 571:Generated_Source\PSoC4/UART.c **** #if (UART_SS0_PIN) + 572:Generated_Source\PSoC4/UART.c **** hsiomSel [UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_SPI; + 573:Generated_Source\PSoC4/UART.c **** pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; + 574:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_SS0_PIN_MASK; + 575:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS0_PIN) */ + 576:Generated_Source\PSoC4/UART.c **** + 577:Generated_Source\PSoC4/UART.c **** #if (UART_SS1_PIN) + 578:Generated_Source\PSoC4/UART.c **** hsiomSel [UART_SS1_PIN_INDEX] = UART_SS1_HSIOM_SEL_SPI; + 579:Generated_Source\PSoC4/UART.c **** pinsDm [UART_SS1_PIN_INDEX] = UART_PIN_DM_STRONG; + 580:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_SS1_PIN_MASK; + 581:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS1_PIN) */ + 582:Generated_Source\PSoC4/UART.c **** + 583:Generated_Source\PSoC4/UART.c **** #if (UART_SS2_PIN) + 584:Generated_Source\PSoC4/UART.c **** hsiomSel [UART_SS2_PIN_INDEX] = UART_SS2_HSIOM_SEL_SPI; + 585:Generated_Source\PSoC4/UART.c **** pinsDm [UART_SS2_PIN_INDEX] = UART_PIN_DM_STRONG; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 18 + + + 586:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_SS2_PIN_MASK; + 587:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS2_PIN) */ + 588:Generated_Source\PSoC4/UART.c **** + 589:Generated_Source\PSoC4/UART.c **** #if (UART_SS3_PIN) + 590:Generated_Source\PSoC4/UART.c **** hsiomSel [UART_SS3_PIN_INDEX] = UART_SS3_HSIOM_SEL_SPI; + 591:Generated_Source\PSoC4/UART.c **** pinsDm [UART_SS3_PIN_INDEX] = UART_PIN_DM_STRONG; + 592:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_SS3_PIN_MASK; + 593:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS3_PIN) */ + 594:Generated_Source\PSoC4/UART.c **** + 595:Generated_Source\PSoC4/UART.c **** /* Disable input buffers */ + 596:Generated_Source\PSoC4/UART.c **** #if (UART_RX_SCL_MOSI_PIN) + 597:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_RX_SCL_MOSI_PIN_MASK; + 598:Generated_Source\PSoC4/UART.c **** #elif (UART_RX_WAKE_SCL_MOSI_PIN) + 599:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_RX_WAKE_SCL_MOSI_PIN_MASK; + 600:Generated_Source\PSoC4/UART.c **** #else + 601:Generated_Source\PSoC4/UART.c **** #endif /* (UART_RX_SCL_MOSI_PIN) */ + 602:Generated_Source\PSoC4/UART.c **** + 603:Generated_Source\PSoC4/UART.c **** #if (UART_SCLK_PIN) + 604:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_SCLK_PIN_MASK; + 605:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCLK_PIN) */ + 606:Generated_Source\PSoC4/UART.c **** } + 607:Generated_Source\PSoC4/UART.c **** } + 608:Generated_Source\PSoC4/UART.c **** else /* UART */ + 609:Generated_Source\PSoC4/UART.c **** { + 610:Generated_Source\PSoC4/UART.c **** if (UART_UART_MODE_SMARTCARD == subMode) + 611:Generated_Source\PSoC4/UART.c **** { + 612:Generated_Source\PSoC4/UART.c **** /* SmartCard */ + 613:Generated_Source\PSoC4/UART.c **** #if (UART_TX_SDA_MISO_PIN) + 614:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; + 615:Generated_Source\PSoC4/UART.c **** pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; + 616:Generated_Source\PSoC4/UART.c **** #endif /* (UART_TX_SDA_MISO_PIN) */ + 617:Generated_Source\PSoC4/UART.c **** } + 618:Generated_Source\PSoC4/UART.c **** else /* Standard or IrDA */ + 619:Generated_Source\PSoC4/UART.c **** { + 620:Generated_Source\PSoC4/UART.c **** if (0u != (UART_UART_RX_PIN_ENABLE & uartEnableMask)) + 621:Generated_Source\PSoC4/UART.c **** { + 622:Generated_Source\PSoC4/UART.c **** #if (UART_RX_SCL_MOSI_PIN) + 623:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_UART; + 624:Generated_Source\PSoC4/UART.c **** pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + 625:Generated_Source\PSoC4/UART.c **** #elif (UART_RX_WAKE_SCL_MOSI_PIN) + 626:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_UAR + 627:Generated_Source\PSoC4/UART.c **** pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + 628:Generated_Source\PSoC4/UART.c **** #else + 629:Generated_Source\PSoC4/UART.c **** #endif /* (UART_RX_SCL_MOSI_PIN) */ + 630:Generated_Source\PSoC4/UART.c **** } + 631:Generated_Source\PSoC4/UART.c **** + 632:Generated_Source\PSoC4/UART.c **** if (0u != (UART_UART_TX_PIN_ENABLE & uartEnableMask)) + 633:Generated_Source\PSoC4/UART.c **** { + 634:Generated_Source\PSoC4/UART.c **** #if (UART_TX_SDA_MISO_PIN) + 635:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; + 636:Generated_Source\PSoC4/UART.c **** pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; + 637:Generated_Source\PSoC4/UART.c **** + 638:Generated_Source\PSoC4/UART.c **** /* Disable input buffer */ + 639:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; + 640:Generated_Source\PSoC4/UART.c **** #endif /* (UART_TX_SDA_MISO_PIN) */ + 641:Generated_Source\PSoC4/UART.c **** } + 642:Generated_Source\PSoC4/UART.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 19 + + + 643:Generated_Source\PSoC4/UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 644:Generated_Source\PSoC4/UART.c **** if (UART_UART_MODE_STD == subMode) + 645:Generated_Source\PSoC4/UART.c **** { + 646:Generated_Source\PSoC4/UART.c **** if (0u != (UART_UART_CTS_PIN_ENABLE & uartEnableMask)) + 647:Generated_Source\PSoC4/UART.c **** { + 648:Generated_Source\PSoC4/UART.c **** /* CTS input is multiplexed with SCLK */ + 649:Generated_Source\PSoC4/UART.c **** #if (UART_SCLK_PIN) + 650:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SCLK_PIN_INDEX] = UART_SCLK_HSIOM_SEL_UART; + 651:Generated_Source\PSoC4/UART.c **** pinsDm [UART_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; + 652:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCLK_PIN) */ + 653:Generated_Source\PSoC4/UART.c **** } + 654:Generated_Source\PSoC4/UART.c **** + 655:Generated_Source\PSoC4/UART.c **** if (0u != (UART_UART_RTS_PIN_ENABLE & uartEnableMask)) + 656:Generated_Source\PSoC4/UART.c **** { + 657:Generated_Source\PSoC4/UART.c **** /* RTS output is multiplexed with SS0 */ + 658:Generated_Source\PSoC4/UART.c **** #if (UART_SS0_PIN) + 659:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SS0_PIN_INDEX] = UART_SS0_HSIOM_SEL_UART; + 660:Generated_Source\PSoC4/UART.c **** pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; + 661:Generated_Source\PSoC4/UART.c **** + 662:Generated_Source\PSoC4/UART.c **** /* Disable input buffer */ + 663:Generated_Source\PSoC4/UART.c **** pinsInBuf |= UART_SS0_PIN_MASK; + 664:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS0_PIN) */ + 665:Generated_Source\PSoC4/UART.c **** } + 666:Generated_Source\PSoC4/UART.c **** } + 667:Generated_Source\PSoC4/UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 668:Generated_Source\PSoC4/UART.c **** } + 669:Generated_Source\PSoC4/UART.c **** } + 670:Generated_Source\PSoC4/UART.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 671:Generated_Source\PSoC4/UART.c **** + 672:Generated_Source\PSoC4/UART.c **** /* Configure pins: set HSIOM, DM and InputBufEnable */ + 673:Generated_Source\PSoC4/UART.c **** /* Note: the DR register settings do not effect the pin output if HSIOM is other than GPIO */ + 674:Generated_Source\PSoC4/UART.c **** + 675:Generated_Source\PSoC4/UART.c **** #if (UART_RX_SCL_MOSI_PIN) + 676:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_RX_SCL_MOSI_HSIOM_REG, + 677:Generated_Source\PSoC4/UART.c **** UART_RX_SCL_MOSI_HSIOM_MASK, + 678:Generated_Source\PSoC4/UART.c **** UART_RX_SCL_MOSI_HSIOM_POS, + 679:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX]); + 680:Generated_Source\PSoC4/UART.c **** + 681:Generated_Source\PSoC4/UART.c **** UART_uart_rx_i2c_scl_spi_mosi_SetDriveMode((uint8) pinsDm[UART_RX_SCL_MOSI_PIN_INDEX]); + 682:Generated_Source\PSoC4/UART.c **** + 683:Generated_Source\PSoC4/UART.c **** #if (!UART_CY_SCBIP_V1) + 684:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_uart_rx_i2c_scl_spi_mosi_INP_DIS, + 685:Generated_Source\PSoC4/UART.c **** UART_uart_rx_i2c_scl_spi_mosi_MASK, + 686:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_RX_SCL_MOSI_PIN_MASK))); + 687:Generated_Source\PSoC4/UART.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 688:Generated_Source\PSoC4/UART.c **** + 689:Generated_Source\PSoC4/UART.c **** #elif (UART_RX_WAKE_SCL_MOSI_PIN) + 690:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_RX_WAKE_SCL_MOSI_HSIOM_REG, + 691:Generated_Source\PSoC4/UART.c **** UART_RX_WAKE_SCL_MOSI_HSIOM_MASK, + 692:Generated_Source\PSoC4/UART.c **** UART_RX_WAKE_SCL_MOSI_HSIOM_POS, + 693:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX]); + 694:Generated_Source\PSoC4/UART.c **** + 695:Generated_Source\PSoC4/UART.c **** UART_uart_rx_wake_i2c_scl_spi_mosi_SetDriveMode((uint8) + 696:Generated_Source\PSoC4/UART.c **** pinsDm[UART_RX_WAKE_SCL_MOSI_PIN_IND + 697:Generated_Source\PSoC4/UART.c **** + 698:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_uart_rx_wake_i2c_scl_spi_mosi_INP_DIS, + 699:Generated_Source\PSoC4/UART.c **** UART_uart_rx_wake_i2c_scl_spi_mosi_MASK, + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 20 + + + 700:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_RX_WAKE_SCL_MOSI_PIN_MASK))); + 701:Generated_Source\PSoC4/UART.c **** + 702:Generated_Source\PSoC4/UART.c **** /* Set interrupt on falling edge */ + 703:Generated_Source\PSoC4/UART.c **** UART_SET_INCFG_TYPE(UART_RX_WAKE_SCL_MOSI_INTCFG_REG, + 704:Generated_Source\PSoC4/UART.c **** UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_MASK, + 705:Generated_Source\PSoC4/UART.c **** UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_POS, + 706:Generated_Source\PSoC4/UART.c **** UART_INTCFG_TYPE_FALLING_EDGE); + 707:Generated_Source\PSoC4/UART.c **** #else + 708:Generated_Source\PSoC4/UART.c **** #endif /* (UART_RX_WAKE_SCL_MOSI_PIN) */ + 709:Generated_Source\PSoC4/UART.c **** + 710:Generated_Source\PSoC4/UART.c **** #if (UART_TX_SDA_MISO_PIN) + 711:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, + 712:Generated_Source\PSoC4/UART.c **** UART_TX_SDA_MISO_HSIOM_MASK, + 713:Generated_Source\PSoC4/UART.c **** UART_TX_SDA_MISO_HSIOM_POS, + 714:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_TX_SDA_MISO_PIN_INDEX]); + 715:Generated_Source\PSoC4/UART.c **** + 716:Generated_Source\PSoC4/UART.c **** UART_uart_tx_i2c_sda_spi_miso_SetDriveMode((uint8) pinsDm[UART_TX_SDA_MISO_PIN_INDEX]); + 717:Generated_Source\PSoC4/UART.c **** + 718:Generated_Source\PSoC4/UART.c **** #if (!UART_CY_SCBIP_V1) + 719:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_uart_tx_i2c_sda_spi_miso_INP_DIS, + 720:Generated_Source\PSoC4/UART.c **** UART_uart_tx_i2c_sda_spi_miso_MASK, + 721:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_TX_SDA_MISO_PIN_MASK))); + 722:Generated_Source\PSoC4/UART.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 723:Generated_Source\PSoC4/UART.c **** #endif /* (UART_RX_SCL_MOSI_PIN) */ + 724:Generated_Source\PSoC4/UART.c **** + 725:Generated_Source\PSoC4/UART.c **** #if (UART_SCLK_PIN) + 726:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_SCLK_HSIOM_REG, + 727:Generated_Source\PSoC4/UART.c **** UART_SCLK_HSIOM_MASK, + 728:Generated_Source\PSoC4/UART.c **** UART_SCLK_HSIOM_POS, + 729:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SCLK_PIN_INDEX]); + 730:Generated_Source\PSoC4/UART.c **** + 731:Generated_Source\PSoC4/UART.c **** UART_spi_sclk_SetDriveMode((uint8) pinsDm[UART_SCLK_PIN_INDEX]); + 732:Generated_Source\PSoC4/UART.c **** + 733:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_spi_sclk_INP_DIS, + 734:Generated_Source\PSoC4/UART.c **** UART_spi_sclk_MASK, + 735:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_SCLK_PIN_MASK))); + 736:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCLK_PIN) */ + 737:Generated_Source\PSoC4/UART.c **** + 738:Generated_Source\PSoC4/UART.c **** #if (UART_SS0_PIN) + 739:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, + 740:Generated_Source\PSoC4/UART.c **** UART_SS0_HSIOM_MASK, + 741:Generated_Source\PSoC4/UART.c **** UART_SS0_HSIOM_POS, + 742:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SS0_PIN_INDEX]); + 743:Generated_Source\PSoC4/UART.c **** + 744:Generated_Source\PSoC4/UART.c **** UART_spi_ss0_SetDriveMode((uint8) pinsDm[UART_SS0_PIN_INDEX]); + 745:Generated_Source\PSoC4/UART.c **** + 746:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_spi_ss0_INP_DIS, + 747:Generated_Source\PSoC4/UART.c **** UART_spi_ss0_MASK, + 748:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_SS0_PIN_MASK))); + 749:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS0_PIN) */ + 750:Generated_Source\PSoC4/UART.c **** + 751:Generated_Source\PSoC4/UART.c **** #if (UART_SS1_PIN) + 752:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_SS1_HSIOM_REG, + 753:Generated_Source\PSoC4/UART.c **** UART_SS1_HSIOM_MASK, + 754:Generated_Source\PSoC4/UART.c **** UART_SS1_HSIOM_POS, + 755:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SS1_PIN_INDEX]); + 756:Generated_Source\PSoC4/UART.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 21 + + + 757:Generated_Source\PSoC4/UART.c **** UART_spi_ss1_SetDriveMode((uint8) pinsDm[UART_SS1_PIN_INDEX]); + 758:Generated_Source\PSoC4/UART.c **** + 759:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_spi_ss1_INP_DIS, + 760:Generated_Source\PSoC4/UART.c **** UART_spi_ss1_MASK, + 761:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_SS1_PIN_MASK))); + 762:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS1_PIN) */ + 763:Generated_Source\PSoC4/UART.c **** + 764:Generated_Source\PSoC4/UART.c **** #if (UART_SS2_PIN) + 765:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_SS2_HSIOM_REG, + 766:Generated_Source\PSoC4/UART.c **** UART_SS2_HSIOM_MASK, + 767:Generated_Source\PSoC4/UART.c **** UART_SS2_HSIOM_POS, + 768:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SS2_PIN_INDEX]); + 769:Generated_Source\PSoC4/UART.c **** + 770:Generated_Source\PSoC4/UART.c **** UART_spi_ss2_SetDriveMode((uint8) pinsDm[UART_SS2_PIN_INDEX]); + 771:Generated_Source\PSoC4/UART.c **** + 772:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_spi_ss2_INP_DIS, + 773:Generated_Source\PSoC4/UART.c **** UART_spi_ss2_MASK, + 774:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_SS2_PIN_MASK))); + 775:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS2_PIN) */ + 776:Generated_Source\PSoC4/UART.c **** + 777:Generated_Source\PSoC4/UART.c **** #if (UART_SS3_PIN) + 778:Generated_Source\PSoC4/UART.c **** UART_SET_HSIOM_SEL(UART_SS3_HSIOM_REG, + 779:Generated_Source\PSoC4/UART.c **** UART_SS3_HSIOM_MASK, + 780:Generated_Source\PSoC4/UART.c **** UART_SS3_HSIOM_POS, + 781:Generated_Source\PSoC4/UART.c **** hsiomSel[UART_SS3_PIN_INDEX]); + 782:Generated_Source\PSoC4/UART.c **** + 783:Generated_Source\PSoC4/UART.c **** UART_spi_ss3_SetDriveMode((uint8) pinsDm[UART_SS3_PIN_INDEX]); + 784:Generated_Source\PSoC4/UART.c **** + 785:Generated_Source\PSoC4/UART.c **** UART_SET_INP_DIS(UART_spi_ss3_INP_DIS, + 786:Generated_Source\PSoC4/UART.c **** UART_spi_ss3_MASK, + 787:Generated_Source\PSoC4/UART.c **** (0u != (pinsInBuf & UART_SS3_PIN_MASK))); + 788:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SS3_PIN) */ + 789:Generated_Source\PSoC4/UART.c **** } + 790:Generated_Source\PSoC4/UART.c **** + 791:Generated_Source\PSoC4/UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 792:Generated_Source\PSoC4/UART.c **** + 793:Generated_Source\PSoC4/UART.c **** + 794:Generated_Source\PSoC4/UART.c **** #if (UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 795:Generated_Source\PSoC4/UART.c **** /******************************************************************************* + 796:Generated_Source\PSoC4/UART.c **** * Function Name: UART_I2CSlaveNackGeneration + 797:Generated_Source\PSoC4/UART.c **** ****************************************************************************//** + 798:Generated_Source\PSoC4/UART.c **** * + 799:Generated_Source\PSoC4/UART.c **** * Sets command to generate NACK to the address or data. + 800:Generated_Source\PSoC4/UART.c **** * + 801:Generated_Source\PSoC4/UART.c **** *******************************************************************************/ + 802:Generated_Source\PSoC4/UART.c **** void UART_I2CSlaveNackGeneration(void) + 803:Generated_Source\PSoC4/UART.c **** { + 385 .loc 1 803 0 + 386 .cfi_startproc + 387 @ args = 0, pretend = 0, frame = 0 + 388 @ frame_needed = 1, uses_anonymous_args = 0 + 389 0000 80B5 push {r7, lr} + 390 .cfi_def_cfa_offset 8 + 391 .cfi_offset 7, -8 + 392 .cfi_offset 14, -4 + 393 0002 00AF add r7, sp, #0 + 394 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 22 + + + 804:Generated_Source\PSoC4/UART.c **** /* Check for EC_AM toggle condition: EC_AM and clock stretching for address are enabled */ + 805:Generated_Source\PSoC4/UART.c **** if ((0u != (UART_CTRL_REG & UART_CTRL_EC_AM_MODE)) && + 395 .loc 1 805 0 + 396 0004 0F4B ldr r3, .L23 + 397 0006 1A68 ldr r2, [r3] + 398 0008 8023 movs r3, #128 + 399 000a 5B00 lsls r3, r3, #1 + 400 000c 1340 ands r3, r2 + 401 000e 12D0 beq .L22 + 806:Generated_Source\PSoC4/UART.c **** (0u == (UART_I2C_CTRL_REG & UART_I2C_CTRL_S_NOT_READY_ADDR_NACK))) + 402 .loc 1 806 0 discriminator 1 + 403 0010 0D4B ldr r3, .L23+4 + 404 0012 1A68 ldr r2, [r3] + 405 0014 8023 movs r3, #128 + 406 0016 DB01 lsls r3, r3, #7 + 407 0018 1340 ands r3, r2 + 805:Generated_Source\PSoC4/UART.c **** (0u == (UART_I2C_CTRL_REG & UART_I2C_CTRL_S_NOT_READY_ADDR_NACK))) + 408 .loc 1 805 0 discriminator 1 + 409 001a 0CD1 bne .L22 + 807:Generated_Source\PSoC4/UART.c **** { + 808:Generated_Source\PSoC4/UART.c **** /* Toggle EC_AM before NACK generation */ + 809:Generated_Source\PSoC4/UART.c **** UART_CTRL_REG &= ~UART_CTRL_EC_AM_MODE; + 410 .loc 1 809 0 + 411 001c 094B ldr r3, .L23 + 412 001e 094A ldr r2, .L23 + 413 0020 1268 ldr r2, [r2] + 414 0022 0A49 ldr r1, .L23+8 + 415 0024 0A40 ands r2, r1 + 416 0026 1A60 str r2, [r3] + 810:Generated_Source\PSoC4/UART.c **** UART_CTRL_REG |= UART_CTRL_EC_AM_MODE; + 417 .loc 1 810 0 + 418 0028 064B ldr r3, .L23 + 419 002a 064A ldr r2, .L23 + 420 002c 1268 ldr r2, [r2] + 421 002e 8021 movs r1, #128 + 422 0030 4900 lsls r1, r1, #1 + 423 0032 0A43 orrs r2, r1 + 424 0034 1A60 str r2, [r3] + 425 .L22: + 811:Generated_Source\PSoC4/UART.c **** } + 812:Generated_Source\PSoC4/UART.c **** + 813:Generated_Source\PSoC4/UART.c **** UART_I2C_SLAVE_CMD_REG = UART_I2C_SLAVE_CMD_S_NACK; + 426 .loc 1 813 0 + 427 0036 064B ldr r3, .L23+12 + 428 0038 0222 movs r2, #2 + 429 003a 1A60 str r2, [r3] + 814:Generated_Source\PSoC4/UART.c **** } + 430 .loc 1 814 0 + 431 003c C046 nop + 432 003e BD46 mov sp, r7 + 433 @ sp needed + 434 0040 80BD pop {r7, pc} + 435 .L24: + 436 0042 C046 .align 2 + 437 .L23: + 438 0044 00000640 .word 1074135040 + 439 0048 60000640 .word 1074135136 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 23 + + + 440 004c FFFEFFFF .word -257 + 441 0050 6C000640 .word 1074135148 + 442 .cfi_endproc + 443 .LFE9: + 444 .size UART_I2CSlaveNackGeneration, .-UART_I2CSlaveNackGeneration + 445 .text + 446 .Letext0: + 447 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 448 .section .debug_info,"",%progbits + 449 .Ldebug_info0: + 450 0000 D8010000 .4byte 0x1d8 + 451 0004 0400 .2byte 0x4 + 452 0006 00000000 .4byte .Ldebug_abbrev0 + 453 000a 04 .byte 0x4 + 454 000b 01 .uleb128 0x1 + 455 000c 1A010000 .4byte .LASF33 + 456 0010 0C .byte 0xc + 457 0011 B6010000 .4byte .LASF34 + 458 0015 72000000 .4byte .LASF35 + 459 0019 00000000 .4byte .Ldebug_ranges0+0 + 460 001d 00000000 .4byte 0 + 461 0021 00000000 .4byte .Ldebug_line0 + 462 0025 02 .uleb128 0x2 + 463 0026 01 .byte 0x1 + 464 0027 06 .byte 0x6 + 465 0028 87020000 .4byte .LASF0 + 466 002c 02 .uleb128 0x2 + 467 002d 01 .byte 0x1 + 468 002e 08 .byte 0x8 + 469 002f DF000000 .4byte .LASF1 + 470 0033 02 .uleb128 0x2 + 471 0034 02 .byte 0x2 + 472 0035 05 .byte 0x5 + 473 0036 4A020000 .4byte .LASF2 + 474 003a 02 .uleb128 0x2 + 475 003b 02 .byte 0x2 + 476 003c 07 .byte 0x7 + 477 003d 52000000 .4byte .LASF3 + 478 0041 02 .uleb128 0x2 + 479 0042 04 .byte 0x4 + 480 0043 05 .byte 0x5 + 481 0044 72020000 .4byte .LASF4 + 482 0048 02 .uleb128 0x2 + 483 0049 04 .byte 0x4 + 484 004a 07 .byte 0x7 + 485 004b F7000000 .4byte .LASF5 + 486 004f 02 .uleb128 0x2 + 487 0050 08 .byte 0x8 + 488 0051 05 .byte 0x5 + 489 0052 23020000 .4byte .LASF6 + 490 0056 02 .uleb128 0x2 + 491 0057 08 .byte 0x8 + 492 0058 07 .byte 0x7 + 493 0059 F9010000 .4byte .LASF7 + 494 005d 03 .uleb128 0x3 + 495 005e 04 .byte 0x4 + 496 005f 05 .byte 0x5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 24 + + + 497 0060 696E7400 .ascii "int\000" + 498 0064 02 .uleb128 0x2 + 499 0065 04 .byte 0x4 + 500 0066 07 .byte 0x7 + 501 0067 EC010000 .4byte .LASF8 + 502 006b 04 .uleb128 0x4 + 503 006c 09010000 .4byte .LASF9 + 504 0070 02 .byte 0x2 + 505 0071 E401 .2byte 0x1e4 + 506 0073 2C000000 .4byte 0x2c + 507 0077 04 .uleb128 0x4 + 508 0078 AF010000 .4byte .LASF10 + 509 007c 02 .byte 0x2 + 510 007d E501 .2byte 0x1e5 + 511 007f 3A000000 .4byte 0x3a + 512 0083 04 .uleb128 0x4 + 513 0084 D4010000 .4byte .LASF11 + 514 0088 02 .byte 0x2 + 515 0089 E601 .2byte 0x1e6 + 516 008b 48000000 .4byte 0x48 + 517 008f 02 .uleb128 0x2 + 518 0090 04 .byte 0x4 + 519 0091 04 .byte 0x4 + 520 0092 CD000000 .4byte .LASF12 + 521 0096 02 .uleb128 0x2 + 522 0097 08 .byte 0x8 + 523 0098 04 .byte 0x4 + 524 0099 A8010000 .4byte .LASF13 + 525 009d 02 .uleb128 0x2 + 526 009e 01 .byte 0x1 + 527 009f 08 .byte 0x8 + 528 00a0 45020000 .4byte .LASF14 + 529 00a4 04 .uleb128 0x4 + 530 00a5 00000000 .4byte .LASF15 + 531 00a9 02 .byte 0x2 + 532 00aa 9002 .2byte 0x290 + 533 00ac B0000000 .4byte 0xb0 + 534 00b0 05 .uleb128 0x5 + 535 00b1 83000000 .4byte 0x83 + 536 00b5 02 .uleb128 0x2 + 537 00b6 08 .byte 0x8 + 538 00b7 04 .byte 0x4 + 539 00b8 7B020000 .4byte .LASF16 + 540 00bc 02 .uleb128 0x2 + 541 00bd 04 .byte 0x4 + 542 00be 07 .byte 0x7 + 543 00bf 1A020000 .4byte .LASF17 + 544 00c3 06 .uleb128 0x6 + 545 00c4 ED000000 .4byte .LASF18 + 546 00c8 01 .byte 0x1 + 547 00c9 7B .byte 0x7b + 548 00ca 00000000 .4byte .LFB0 + 549 00ce 0E000000 .4byte .LFE0-.LFB0 + 550 00d2 01 .uleb128 0x1 + 551 00d3 9C .byte 0x9c + 552 00d4 06 .uleb128 0x6 + 553 00d5 D3000000 .4byte .LASF19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 25 + + + 554 00d9 01 .byte 0x1 + 555 00da AB .byte 0xab + 556 00db 00000000 .4byte .LFB1 + 557 00df 24000000 .4byte .LFE1-.LFB1 + 558 00e3 01 .uleb128 0x1 + 559 00e4 9C .byte 0x9c + 560 00e5 06 .uleb128 0x6 + 561 00e6 0F010000 .4byte .LASF20 + 562 00ea 01 .byte 0x1 + 563 00eb D2 .byte 0xd2 + 564 00ec 00000000 .4byte .LFB2 + 565 00f0 24000000 .4byte .LFE2-.LFB2 + 566 00f4 01 .uleb128 0x1 + 567 00f5 9C .byte 0x9c + 568 00f6 06 .uleb128 0x6 + 569 00f7 10020000 .4byte .LASF21 + 570 00fb 01 .byte 0x1 + 571 00fc EF .byte 0xef + 572 00fd 00000000 .4byte .LFB3 + 573 0101 28000000 .4byte .LFE3-.LFB3 + 574 0105 01 .uleb128 0x1 + 575 0106 9C .byte 0x9c + 576 0107 07 .uleb128 0x7 + 577 0108 31020000 .4byte .LASF22 + 578 010c 01 .byte 0x1 + 579 010d 1701 .2byte 0x117 + 580 010f 00000000 .4byte .LFB4 + 581 0113 34000000 .4byte .LFE4-.LFB4 + 582 0117 01 .uleb128 0x1 + 583 0118 9C .byte 0x9c + 584 0119 3C010000 .4byte 0x13c + 585 011d 08 .uleb128 0x8 + 586 011e 35000000 .4byte .LASF24 + 587 0122 01 .byte 0x1 + 588 0123 1701 .2byte 0x117 + 589 0125 83000000 .4byte 0x83 + 590 0129 02 .uleb128 0x2 + 591 012a 91 .byte 0x91 + 592 012b 6C .sleb128 -20 + 593 012c 09 .uleb128 0x9 + 594 012d 67020000 .4byte .LASF25 + 595 0131 01 .byte 0x1 + 596 0132 1901 .2byte 0x119 + 597 0134 83000000 .4byte 0x83 + 598 0138 02 .uleb128 0x2 + 599 0139 91 .byte 0x91 + 600 013a 74 .sleb128 -12 + 601 013b 00 .byte 0 + 602 013c 07 .uleb128 0x7 + 603 013d 21000000 .4byte .LASF23 + 604 0141 01 .byte 0x1 + 605 0142 3001 .2byte 0x130 + 606 0144 00000000 .4byte .LFB5 + 607 0148 34000000 .4byte .LFE5-.LFB5 + 608 014c 01 .uleb128 0x1 + 609 014d 9C .byte 0x9c + 610 014e 71010000 .4byte 0x171 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 26 + + + 611 0152 08 .uleb128 0x8 + 612 0153 35000000 .4byte .LASF24 + 613 0157 01 .byte 0x1 + 614 0158 3001 .2byte 0x130 + 615 015a 83000000 .4byte 0x83 + 616 015e 02 .uleb128 0x2 + 617 015f 91 .byte 0x91 + 618 0160 6C .sleb128 -20 + 619 0161 09 .uleb128 0x9 + 620 0162 06000000 .4byte .LASF26 + 621 0166 01 .byte 0x1 + 622 0167 3201 .2byte 0x132 + 623 0169 83000000 .4byte 0x83 + 624 016d 02 .uleb128 0x2 + 625 016e 91 .byte 0x91 + 626 016f 74 .sleb128 -12 + 627 0170 00 .byte 0 + 628 0171 0A .uleb128 0xa + 629 0172 54020000 .4byte .LASF27 + 630 0176 01 .byte 0x1 + 631 0177 6401 .2byte 0x164 + 632 0179 00000000 .4byte .LFB6 + 633 017d 0A000000 .4byte .LFE6-.LFB6 + 634 0181 01 .uleb128 0x1 + 635 0182 9C .byte 0x9c + 636 0183 0B .uleb128 0xb + 637 0184 3B000000 .4byte .LASF28 + 638 0188 01 .byte 0x1 + 639 0189 7D01 .2byte 0x17d + 640 018b 00000000 .4byte .LFB7 + 641 018f 0E000000 .4byte .LFE7-.LFB7 + 642 0193 01 .uleb128 0x1 + 643 0194 9C .byte 0x9c + 644 0195 0B .uleb128 0xb + 645 0196 DB010000 .4byte .LASF29 + 646 019a 01 .byte 0x1 + 647 019b A201 .2byte 0x1a2 + 648 019d 00000000 .4byte .LFB8 + 649 01a1 0E000000 .4byte .LFE8-.LFB8 + 650 01a5 01 .uleb128 0x1 + 651 01a6 9C .byte 0x9c + 652 01a7 0C .uleb128 0xc + 653 01a8 93020000 .4byte .LASF30 + 654 01ac 01 .byte 0x1 + 655 01ad 2203 .2byte 0x322 + 656 01af 00000000 .4byte .LFB9 + 657 01b3 54000000 .4byte .LFE9-.LFB9 + 658 01b7 01 .uleb128 0x1 + 659 01b8 9C .byte 0x9c + 660 01b9 0D .uleb128 0xd + 661 01ba 65000000 .4byte .LASF31 + 662 01be 01 .byte 0x1 + 663 01bf 51 .byte 0x51 + 664 01c0 6B000000 .4byte 0x6b + 665 01c4 05 .uleb128 0x5 + 666 01c5 03 .byte 0x3 + 667 01c6 00000000 .4byte UART_initVar + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 27 + + + 668 01ca 0D .uleb128 0xd + 669 01cb 11000000 .4byte .LASF32 + 670 01cf 01 .byte 0x1 + 671 01d0 5A .byte 0x5a + 672 01d1 77000000 .4byte 0x77 + 673 01d5 05 .uleb128 0x5 + 674 01d6 03 .byte 0x3 + 675 01d7 00000000 .4byte UART_IntrTxMask + 676 01db 00 .byte 0 + 677 .section .debug_abbrev,"",%progbits + 678 .Ldebug_abbrev0: + 679 0000 01 .uleb128 0x1 + 680 0001 11 .uleb128 0x11 + 681 0002 01 .byte 0x1 + 682 0003 25 .uleb128 0x25 + 683 0004 0E .uleb128 0xe + 684 0005 13 .uleb128 0x13 + 685 0006 0B .uleb128 0xb + 686 0007 03 .uleb128 0x3 + 687 0008 0E .uleb128 0xe + 688 0009 1B .uleb128 0x1b + 689 000a 0E .uleb128 0xe + 690 000b 55 .uleb128 0x55 + 691 000c 17 .uleb128 0x17 + 692 000d 11 .uleb128 0x11 + 693 000e 01 .uleb128 0x1 + 694 000f 10 .uleb128 0x10 + 695 0010 17 .uleb128 0x17 + 696 0011 00 .byte 0 + 697 0012 00 .byte 0 + 698 0013 02 .uleb128 0x2 + 699 0014 24 .uleb128 0x24 + 700 0015 00 .byte 0 + 701 0016 0B .uleb128 0xb + 702 0017 0B .uleb128 0xb + 703 0018 3E .uleb128 0x3e + 704 0019 0B .uleb128 0xb + 705 001a 03 .uleb128 0x3 + 706 001b 0E .uleb128 0xe + 707 001c 00 .byte 0 + 708 001d 00 .byte 0 + 709 001e 03 .uleb128 0x3 + 710 001f 24 .uleb128 0x24 + 711 0020 00 .byte 0 + 712 0021 0B .uleb128 0xb + 713 0022 0B .uleb128 0xb + 714 0023 3E .uleb128 0x3e + 715 0024 0B .uleb128 0xb + 716 0025 03 .uleb128 0x3 + 717 0026 08 .uleb128 0x8 + 718 0027 00 .byte 0 + 719 0028 00 .byte 0 + 720 0029 04 .uleb128 0x4 + 721 002a 16 .uleb128 0x16 + 722 002b 00 .byte 0 + 723 002c 03 .uleb128 0x3 + 724 002d 0E .uleb128 0xe + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 28 + + + 725 002e 3A .uleb128 0x3a + 726 002f 0B .uleb128 0xb + 727 0030 3B .uleb128 0x3b + 728 0031 05 .uleb128 0x5 + 729 0032 49 .uleb128 0x49 + 730 0033 13 .uleb128 0x13 + 731 0034 00 .byte 0 + 732 0035 00 .byte 0 + 733 0036 05 .uleb128 0x5 + 734 0037 35 .uleb128 0x35 + 735 0038 00 .byte 0 + 736 0039 49 .uleb128 0x49 + 737 003a 13 .uleb128 0x13 + 738 003b 00 .byte 0 + 739 003c 00 .byte 0 + 740 003d 06 .uleb128 0x6 + 741 003e 2E .uleb128 0x2e + 742 003f 00 .byte 0 + 743 0040 3F .uleb128 0x3f + 744 0041 19 .uleb128 0x19 + 745 0042 03 .uleb128 0x3 + 746 0043 0E .uleb128 0xe + 747 0044 3A .uleb128 0x3a + 748 0045 0B .uleb128 0xb + 749 0046 3B .uleb128 0x3b + 750 0047 0B .uleb128 0xb + 751 0048 27 .uleb128 0x27 + 752 0049 19 .uleb128 0x19 + 753 004a 11 .uleb128 0x11 + 754 004b 01 .uleb128 0x1 + 755 004c 12 .uleb128 0x12 + 756 004d 06 .uleb128 0x6 + 757 004e 40 .uleb128 0x40 + 758 004f 18 .uleb128 0x18 + 759 0050 9642 .uleb128 0x2116 + 760 0052 19 .uleb128 0x19 + 761 0053 00 .byte 0 + 762 0054 00 .byte 0 + 763 0055 07 .uleb128 0x7 + 764 0056 2E .uleb128 0x2e + 765 0057 01 .byte 0x1 + 766 0058 3F .uleb128 0x3f + 767 0059 19 .uleb128 0x19 + 768 005a 03 .uleb128 0x3 + 769 005b 0E .uleb128 0xe + 770 005c 3A .uleb128 0x3a + 771 005d 0B .uleb128 0xb + 772 005e 3B .uleb128 0x3b + 773 005f 05 .uleb128 0x5 + 774 0060 27 .uleb128 0x27 + 775 0061 19 .uleb128 0x19 + 776 0062 11 .uleb128 0x11 + 777 0063 01 .uleb128 0x1 + 778 0064 12 .uleb128 0x12 + 779 0065 06 .uleb128 0x6 + 780 0066 40 .uleb128 0x40 + 781 0067 18 .uleb128 0x18 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 29 + + + 782 0068 9742 .uleb128 0x2117 + 783 006a 19 .uleb128 0x19 + 784 006b 01 .uleb128 0x1 + 785 006c 13 .uleb128 0x13 + 786 006d 00 .byte 0 + 787 006e 00 .byte 0 + 788 006f 08 .uleb128 0x8 + 789 0070 05 .uleb128 0x5 + 790 0071 00 .byte 0 + 791 0072 03 .uleb128 0x3 + 792 0073 0E .uleb128 0xe + 793 0074 3A .uleb128 0x3a + 794 0075 0B .uleb128 0xb + 795 0076 3B .uleb128 0x3b + 796 0077 05 .uleb128 0x5 + 797 0078 49 .uleb128 0x49 + 798 0079 13 .uleb128 0x13 + 799 007a 02 .uleb128 0x2 + 800 007b 18 .uleb128 0x18 + 801 007c 00 .byte 0 + 802 007d 00 .byte 0 + 803 007e 09 .uleb128 0x9 + 804 007f 34 .uleb128 0x34 + 805 0080 00 .byte 0 + 806 0081 03 .uleb128 0x3 + 807 0082 0E .uleb128 0xe + 808 0083 3A .uleb128 0x3a + 809 0084 0B .uleb128 0xb + 810 0085 3B .uleb128 0x3b + 811 0086 05 .uleb128 0x5 + 812 0087 49 .uleb128 0x49 + 813 0088 13 .uleb128 0x13 + 814 0089 02 .uleb128 0x2 + 815 008a 18 .uleb128 0x18 + 816 008b 00 .byte 0 + 817 008c 00 .byte 0 + 818 008d 0A .uleb128 0xa + 819 008e 2E .uleb128 0x2e + 820 008f 00 .byte 0 + 821 0090 03 .uleb128 0x3 + 822 0091 0E .uleb128 0xe + 823 0092 3A .uleb128 0x3a + 824 0093 0B .uleb128 0xb + 825 0094 3B .uleb128 0x3b + 826 0095 05 .uleb128 0x5 + 827 0096 27 .uleb128 0x27 + 828 0097 19 .uleb128 0x19 + 829 0098 11 .uleb128 0x11 + 830 0099 01 .uleb128 0x1 + 831 009a 12 .uleb128 0x12 + 832 009b 06 .uleb128 0x6 + 833 009c 40 .uleb128 0x40 + 834 009d 18 .uleb128 0x18 + 835 009e 9742 .uleb128 0x2117 + 836 00a0 19 .uleb128 0x19 + 837 00a1 00 .byte 0 + 838 00a2 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 30 + + + 839 00a3 0B .uleb128 0xb + 840 00a4 2E .uleb128 0x2e + 841 00a5 00 .byte 0 + 842 00a6 03 .uleb128 0x3 + 843 00a7 0E .uleb128 0xe + 844 00a8 3A .uleb128 0x3a + 845 00a9 0B .uleb128 0xb + 846 00aa 3B .uleb128 0x3b + 847 00ab 05 .uleb128 0x5 + 848 00ac 27 .uleb128 0x27 + 849 00ad 19 .uleb128 0x19 + 850 00ae 11 .uleb128 0x11 + 851 00af 01 .uleb128 0x1 + 852 00b0 12 .uleb128 0x12 + 853 00b1 06 .uleb128 0x6 + 854 00b2 40 .uleb128 0x40 + 855 00b3 18 .uleb128 0x18 + 856 00b4 9642 .uleb128 0x2116 + 857 00b6 19 .uleb128 0x19 + 858 00b7 00 .byte 0 + 859 00b8 00 .byte 0 + 860 00b9 0C .uleb128 0xc + 861 00ba 2E .uleb128 0x2e + 862 00bb 00 .byte 0 + 863 00bc 3F .uleb128 0x3f + 864 00bd 19 .uleb128 0x19 + 865 00be 03 .uleb128 0x3 + 866 00bf 0E .uleb128 0xe + 867 00c0 3A .uleb128 0x3a + 868 00c1 0B .uleb128 0xb + 869 00c2 3B .uleb128 0x3b + 870 00c3 05 .uleb128 0x5 + 871 00c4 27 .uleb128 0x27 + 872 00c5 19 .uleb128 0x19 + 873 00c6 11 .uleb128 0x11 + 874 00c7 01 .uleb128 0x1 + 875 00c8 12 .uleb128 0x12 + 876 00c9 06 .uleb128 0x6 + 877 00ca 40 .uleb128 0x40 + 878 00cb 18 .uleb128 0x18 + 879 00cc 9742 .uleb128 0x2117 + 880 00ce 19 .uleb128 0x19 + 881 00cf 00 .byte 0 + 882 00d0 00 .byte 0 + 883 00d1 0D .uleb128 0xd + 884 00d2 34 .uleb128 0x34 + 885 00d3 00 .byte 0 + 886 00d4 03 .uleb128 0x3 + 887 00d5 0E .uleb128 0xe + 888 00d6 3A .uleb128 0x3a + 889 00d7 0B .uleb128 0xb + 890 00d8 3B .uleb128 0x3b + 891 00d9 0B .uleb128 0xb + 892 00da 49 .uleb128 0x49 + 893 00db 13 .uleb128 0x13 + 894 00dc 3F .uleb128 0x3f + 895 00dd 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 31 + + + 896 00de 02 .uleb128 0x2 + 897 00df 18 .uleb128 0x18 + 898 00e0 00 .byte 0 + 899 00e1 00 .byte 0 + 900 00e2 00 .byte 0 + 901 .section .debug_aranges,"",%progbits + 902 0000 64000000 .4byte 0x64 + 903 0004 0200 .2byte 0x2 + 904 0006 00000000 .4byte .Ldebug_info0 + 905 000a 04 .byte 0x4 + 906 000b 00 .byte 0 + 907 000c 0000 .2byte 0 + 908 000e 0000 .2byte 0 + 909 0010 00000000 .4byte .LFB0 + 910 0014 0E000000 .4byte .LFE0-.LFB0 + 911 0018 00000000 .4byte .LFB1 + 912 001c 24000000 .4byte .LFE1-.LFB1 + 913 0020 00000000 .4byte .LFB2 + 914 0024 24000000 .4byte .LFE2-.LFB2 + 915 0028 00000000 .4byte .LFB3 + 916 002c 28000000 .4byte .LFE3-.LFB3 + 917 0030 00000000 .4byte .LFB4 + 918 0034 34000000 .4byte .LFE4-.LFB4 + 919 0038 00000000 .4byte .LFB5 + 920 003c 34000000 .4byte .LFE5-.LFB5 + 921 0040 00000000 .4byte .LFB6 + 922 0044 0A000000 .4byte .LFE6-.LFB6 + 923 0048 00000000 .4byte .LFB7 + 924 004c 0E000000 .4byte .LFE7-.LFB7 + 925 0050 00000000 .4byte .LFB8 + 926 0054 0E000000 .4byte .LFE8-.LFB8 + 927 0058 00000000 .4byte .LFB9 + 928 005c 54000000 .4byte .LFE9-.LFB9 + 929 0060 00000000 .4byte 0 + 930 0064 00000000 .4byte 0 + 931 .section .debug_ranges,"",%progbits + 932 .Ldebug_ranges0: + 933 0000 00000000 .4byte .LFB0 + 934 0004 0E000000 .4byte .LFE0 + 935 0008 00000000 .4byte .LFB1 + 936 000c 24000000 .4byte .LFE1 + 937 0010 00000000 .4byte .LFB2 + 938 0014 24000000 .4byte .LFE2 + 939 0018 00000000 .4byte .LFB3 + 940 001c 28000000 .4byte .LFE3 + 941 0020 00000000 .4byte .LFB4 + 942 0024 34000000 .4byte .LFE4 + 943 0028 00000000 .4byte .LFB5 + 944 002c 34000000 .4byte .LFE5 + 945 0030 00000000 .4byte .LFB6 + 946 0034 0A000000 .4byte .LFE6 + 947 0038 00000000 .4byte .LFB7 + 948 003c 0E000000 .4byte .LFE7 + 949 0040 00000000 .4byte .LFB8 + 950 0044 0E000000 .4byte .LFE8 + 951 0048 00000000 .4byte .LFB9 + 952 004c 54000000 .4byte .LFE9 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 32 + + + 953 0050 00000000 .4byte 0 + 954 0054 00000000 .4byte 0 + 955 .section .debug_line,"",%progbits + 956 .Ldebug_line0: + 957 0000 20010000 .section .debug_str,"MS",%progbits,1 + 957 02004100 + 957 00000201 + 957 FB0E0D00 + 957 01010101 + 958 .LASF15: + 959 0000 72656733 .ascii "reg32\000" + 959 3200 + 960 .LASF26: + 961 0006 74784669 .ascii "txFifoCtrl\000" + 961 666F4374 + 961 726C00 + 962 .LASF32: + 963 0011 55415254 .ascii "UART_IntrTxMask\000" + 963 5F496E74 + 963 7254784D + 963 61736B00 + 964 .LASF23: + 965 0021 55415254 .ascii "UART_SetTxFifoLevel\000" + 965 5F536574 + 965 54784669 + 965 666F4C65 + 965 76656C00 + 966 .LASF24: + 967 0035 6C657665 .ascii "level\000" + 967 6C00 + 968 .LASF28: + 969 003b 55415254 .ascii "UART_ScbModePostEnable\000" + 969 5F536362 + 969 4D6F6465 + 969 506F7374 + 969 456E6162 + 970 .LASF3: + 971 0052 73686F72 .ascii "short unsigned int\000" + 971 7420756E + 971 7369676E + 971 65642069 + 971 6E7400 + 972 .LASF31: + 973 0065 55415254 .ascii "UART_initVar\000" + 973 5F696E69 + 973 74566172 + 973 00 + 974 .LASF35: + 975 0072 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 975 73657273 + 975 5C6A6167 + 975 756D6965 + 975 6C5C446F + 976 00a0 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 976 50536F43 + 976 2D313031 + 976 5C547261 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 33 + + + 976 696E696E + 977 .LASF12: + 978 00cd 666C6F61 .ascii "float\000" + 978 7400 + 979 .LASF19: + 980 00d3 55415254 .ascii "UART_Enable\000" + 980 5F456E61 + 980 626C6500 + 981 .LASF1: + 982 00df 756E7369 .ascii "unsigned char\000" + 982 676E6564 + 982 20636861 + 982 7200 + 983 .LASF18: + 984 00ed 55415254 .ascii "UART_Init\000" + 984 5F496E69 + 984 7400 + 985 .LASF5: + 986 00f7 6C6F6E67 .ascii "long unsigned int\000" + 986 20756E73 + 986 69676E65 + 986 6420696E + 986 7400 + 987 .LASF9: + 988 0109 75696E74 .ascii "uint8\000" + 988 3800 + 989 .LASF20: + 990 010f 55415254 .ascii "UART_Start\000" + 990 5F537461 + 990 727400 + 991 .LASF33: + 992 011a 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 992 43313120 + 992 352E342E + 992 31203230 + 992 31363036 + 993 014d 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 993 20726576 + 993 6973696F + 993 6E203233 + 993 37373135 + 994 0180 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 994 66756E63 + 994 74696F6E + 994 2D736563 + 994 74696F6E + 995 .LASF13: + 996 01a8 646F7562 .ascii "double\000" + 996 6C6500 + 997 .LASF10: + 998 01af 75696E74 .ascii "uint16\000" + 998 313600 + 999 .LASF34: + 1000 01b6 47656E65 .ascii "Generated_Source\\PSoC4\\UART.c\000" + 1000 72617465 + 1000 645F536F + 1000 75726365 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 34 + + + 1000 5C50536F + 1001 .LASF11: + 1002 01d4 75696E74 .ascii "uint32\000" + 1002 333200 + 1003 .LASF29: + 1004 01db 55415254 .ascii "UART_ScbModeStop\000" + 1004 5F536362 + 1004 4D6F6465 + 1004 53746F70 + 1004 00 + 1005 .LASF8: + 1006 01ec 756E7369 .ascii "unsigned int\000" + 1006 676E6564 + 1006 20696E74 + 1006 00 + 1007 .LASF7: + 1008 01f9 6C6F6E67 .ascii "long long unsigned int\000" + 1008 206C6F6E + 1008 6720756E + 1008 7369676E + 1008 65642069 + 1009 .LASF21: + 1010 0210 55415254 .ascii "UART_Stop\000" + 1010 5F53746F + 1010 7000 + 1011 .LASF17: + 1012 021a 73697A65 .ascii "sizetype\000" + 1012 74797065 + 1012 00 + 1013 .LASF6: + 1014 0223 6C6F6E67 .ascii "long long int\000" + 1014 206C6F6E + 1014 6720696E + 1014 7400 + 1015 .LASF22: + 1016 0231 55415254 .ascii "UART_SetRxFifoLevel\000" + 1016 5F536574 + 1016 52784669 + 1016 666F4C65 + 1016 76656C00 + 1017 .LASF14: + 1018 0245 63686172 .ascii "char\000" + 1018 00 + 1019 .LASF2: + 1020 024a 73686F72 .ascii "short int\000" + 1020 7420696E + 1020 7400 + 1021 .LASF27: + 1022 0254 55415254 .ascii "UART_ScbEnableIntr\000" + 1022 5F536362 + 1022 456E6162 + 1022 6C65496E + 1022 747200 + 1023 .LASF25: + 1024 0267 72784669 .ascii "rxFifoCtrl\000" + 1024 666F4374 + 1024 726C00 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccv2rUUu.s page 35 + + + 1025 .LASF4: + 1026 0272 6C6F6E67 .ascii "long int\000" + 1026 20696E74 + 1026 00 + 1027 .LASF16: + 1028 027b 6C6F6E67 .ascii "long double\000" + 1028 20646F75 + 1028 626C6500 + 1029 .LASF0: + 1030 0287 7369676E .ascii "signed char\000" + 1030 65642063 + 1030 68617200 + 1031 .LASF30: + 1032 0293 55415254 .ascii "UART_I2CSlaveNackGeneration\000" + 1032 5F493243 + 1032 536C6176 + 1032 654E6163 + 1032 6B47656E + 1033 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART.o new file mode 100644 index 0000000000000000000000000000000000000000..d75d3e3db6ee1126fc751769e83dc4eef6d01d3b GIT binary patch literal 6824 zcmbtYdyHIF89(>lnc3OdN4vX)wp+y8c7X+%=}cc>p>&tswk+FX?QRiiO?Mu5cZSZ+ z)H`>}R#ckM1fpm_1Y%NSgP4%;M;l)uCPWg68kGc4qe)F9u@X%{LSoWL#rpf5d(O<6 z+ZGLc$(`T%9_RbM^SIwRcOKlnYlmf7LX#ziMT-;Sjb&03-zZ^NTqD+qV?Pq7E}Z+% zg_m}`xZ~K1FYO?om`vQ+Up}_FGm#n_oT0X5Aw*&%v{|(%J`sD38fVg4GkDmv5lz4G z$vAxN6?>C|GtQ(~GdL4QqMt{W(AV+P;?&|y=j5vL`I+rx^ z^1X7{D|Y(Wi!tXz^s&R7%`vvJ4aXeimrM?pkFDJ=21fc{?UC&>*1$;jYn_vw7*A>< zH8MD(=V?N4o)VLGb9685;P__nT)^a2fq%q8#N@oktUonrg1))uyZ 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zx!^qQJiCOLMdO;YR-@nkvYgSIdlOkt3)#ka7@0NCyp?v$qxl^@YFL*>k4`M;lM8xz zL9Y|a}m5Bcj#-CHJ4L%3k^!q#I+}lcc4xHm`B`n6V zkB#r0KZpMo$0cp&fa-leW@60xUWDfAxn;(0;fL@kIDfqP-@uLcbCnn1h;cQ>36hem>9FZ6q-4on~ncgUs@+L zQ*K;mj5h8&JOBl4&Bnct0o?J#j^BjnSOMfXHhxd+vta!b690sWF&oEdpEbKCnDjO9 Y2{eA^_`GXqd?&N(wc%LBm^HiJ-!bGJEC2ui literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_PM.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_PM.lst new file mode 100644 index 0000000..b8dfdfa --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_PM.lst @@ -0,0 +1,811 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "UART_PM.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .global UART_backup + 20 .bss + 21 .align 2 + 22 .type UART_backup, %object + 23 .size UART_backup, 1 + 24 UART_backup: + 25 0000 00 .space 1 + 26 .section .text.UART_Sleep,"ax",%progbits + 27 .align 2 + 28 .global UART_Sleep + 29 .code 16 + 30 .thumb_func + 31 .type UART_Sleep, %function + 32 UART_Sleep: + 33 .LFB0: + 34 .file 1 "Generated_Source\\PSoC4\\UART_PM.c" + 1:Generated_Source\PSoC4/UART_PM.c **** /***************************************************************************//** + 2:Generated_Source\PSoC4/UART_PM.c **** * \file UART_PM.c + 3:Generated_Source\PSoC4/UART_PM.c **** * \version 4.0 + 4:Generated_Source\PSoC4/UART_PM.c **** * + 5:Generated_Source\PSoC4/UART_PM.c **** * \brief + 6:Generated_Source\PSoC4/UART_PM.c **** * This file provides the source code to the Power Management support for + 7:Generated_Source\PSoC4/UART_PM.c **** * the SCB Component. + 8:Generated_Source\PSoC4/UART_PM.c **** * + 9:Generated_Source\PSoC4/UART_PM.c **** * Note: + 10:Generated_Source\PSoC4/UART_PM.c **** * + 11:Generated_Source\PSoC4/UART_PM.c **** ******************************************************************************** + 12:Generated_Source\PSoC4/UART_PM.c **** * \copyright + 13:Generated_Source\PSoC4/UART_PM.c **** * Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. + 14:Generated_Source\PSoC4/UART_PM.c **** * You may use this file only in accordance with the license, terms, conditions, + 15:Generated_Source\PSoC4/UART_PM.c **** * disclaimers, and limitations in the end user license agreement accompanying + 16:Generated_Source\PSoC4/UART_PM.c **** * the software package with which this file was provided. + 17:Generated_Source\PSoC4/UART_PM.c **** *******************************************************************************/ + 18:Generated_Source\PSoC4/UART_PM.c **** + 19:Generated_Source\PSoC4/UART_PM.c **** #include "UART.h" + 20:Generated_Source\PSoC4/UART_PM.c **** #include "UART_PVT.h" + 21:Generated_Source\PSoC4/UART_PM.c **** + 22:Generated_Source\PSoC4/UART_PM.c **** #if(UART_SCB_MODE_I2C_INC) + 23:Generated_Source\PSoC4/UART_PM.c **** #include "UART_I2C_PVT.h" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 2 + + + 24:Generated_Source\PSoC4/UART_PM.c **** #endif /* (UART_SCB_MODE_I2C_INC) */ + 25:Generated_Source\PSoC4/UART_PM.c **** + 26:Generated_Source\PSoC4/UART_PM.c **** #if(UART_SCB_MODE_EZI2C_INC) + 27:Generated_Source\PSoC4/UART_PM.c **** #include "UART_EZI2C_PVT.h" + 28:Generated_Source\PSoC4/UART_PM.c **** #endif /* (UART_SCB_MODE_EZI2C_INC) */ + 29:Generated_Source\PSoC4/UART_PM.c **** + 30:Generated_Source\PSoC4/UART_PM.c **** #if(UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) + 31:Generated_Source\PSoC4/UART_PM.c **** #include "UART_SPI_UART_PVT.h" + 32:Generated_Source\PSoC4/UART_PM.c **** #endif /* (UART_SCB_MODE_SPI_INC || UART_SCB_MODE_UART_INC) */ + 33:Generated_Source\PSoC4/UART_PM.c **** + 34:Generated_Source\PSoC4/UART_PM.c **** + 35:Generated_Source\PSoC4/UART_PM.c **** /*************************************** + 36:Generated_Source\PSoC4/UART_PM.c **** * Backup Structure declaration + 37:Generated_Source\PSoC4/UART_PM.c **** ***************************************/ + 38:Generated_Source\PSoC4/UART_PM.c **** + 39:Generated_Source\PSoC4/UART_PM.c **** #if(UART_SCB_MODE_UNCONFIG_CONST_CFG || \ + 40:Generated_Source\PSoC4/UART_PM.c **** (UART_SCB_MODE_I2C_CONST_CFG && (!UART_I2C_WAKE_ENABLE_CONST)) || \ + 41:Generated_Source\PSoC4/UART_PM.c **** (UART_SCB_MODE_EZI2C_CONST_CFG && (!UART_EZI2C_WAKE_ENABLE_CONST)) || \ + 42:Generated_Source\PSoC4/UART_PM.c **** (UART_SCB_MODE_SPI_CONST_CFG && (!UART_SPI_WAKE_ENABLE_CONST)) || \ + 43:Generated_Source\PSoC4/UART_PM.c **** (UART_SCB_MODE_UART_CONST_CFG && (!UART_UART_WAKE_ENABLE_CONST))) + 44:Generated_Source\PSoC4/UART_PM.c **** + 45:Generated_Source\PSoC4/UART_PM.c **** UART_BACKUP_STRUCT UART_backup = + 46:Generated_Source\PSoC4/UART_PM.c **** { + 47:Generated_Source\PSoC4/UART_PM.c **** 0u, /* enableState */ + 48:Generated_Source\PSoC4/UART_PM.c **** }; + 49:Generated_Source\PSoC4/UART_PM.c **** #endif + 50:Generated_Source\PSoC4/UART_PM.c **** + 51:Generated_Source\PSoC4/UART_PM.c **** + 52:Generated_Source\PSoC4/UART_PM.c **** /******************************************************************************* + 53:Generated_Source\PSoC4/UART_PM.c **** * Function Name: UART_Sleep + 54:Generated_Source\PSoC4/UART_PM.c **** ****************************************************************************//** + 55:Generated_Source\PSoC4/UART_PM.c **** * + 56:Generated_Source\PSoC4/UART_PM.c **** * Prepares the UART component to enter Deep Sleep. + 57:Generated_Source\PSoC4/UART_PM.c **** * The “Enable wakeup from Deep Sleep Mode” selection has an influence on this + 58:Generated_Source\PSoC4/UART_PM.c **** * function implementation: + 59:Generated_Source\PSoC4/UART_PM.c **** * - Checked: configures the component to be wakeup source from Deep Sleep. + 60:Generated_Source\PSoC4/UART_PM.c **** * - Unchecked: stores the current component state (enabled or disabled) and + 61:Generated_Source\PSoC4/UART_PM.c **** * disables the component. See SCB_Stop() function for details about component + 62:Generated_Source\PSoC4/UART_PM.c **** * disabling. + 63:Generated_Source\PSoC4/UART_PM.c **** * + 64:Generated_Source\PSoC4/UART_PM.c **** * Call the UART_Sleep() function before calling the + 65:Generated_Source\PSoC4/UART_PM.c **** * CyPmSysDeepSleep() function. + 66:Generated_Source\PSoC4/UART_PM.c **** * Refer to the PSoC Creator System Reference Guide for more information about + 67:Generated_Source\PSoC4/UART_PM.c **** * power management functions and Low power section of this document for the + 68:Generated_Source\PSoC4/UART_PM.c **** * selected mode. + 69:Generated_Source\PSoC4/UART_PM.c **** * + 70:Generated_Source\PSoC4/UART_PM.c **** * This function should not be called before entering Sleep. + 71:Generated_Source\PSoC4/UART_PM.c **** * + 72:Generated_Source\PSoC4/UART_PM.c **** *******************************************************************************/ + 73:Generated_Source\PSoC4/UART_PM.c **** void UART_Sleep(void) + 74:Generated_Source\PSoC4/UART_PM.c **** { + 35 .loc 1 74 0 + 36 .cfi_startproc + 37 @ args = 0, pretend = 0, frame = 0 + 38 @ frame_needed = 1, uses_anonymous_args = 0 + 39 0000 80B5 push {r7, lr} + 40 .cfi_def_cfa_offset 8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 3 + + + 41 .cfi_offset 7, -8 + 42 .cfi_offset 14, -4 + 43 0002 00AF add r7, sp, #0 + 44 .cfi_def_cfa_register 7 + 75:Generated_Source\PSoC4/UART_PM.c **** #if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + 76:Generated_Source\PSoC4/UART_PM.c **** + 77:Generated_Source\PSoC4/UART_PM.c **** if(UART_SCB_WAKE_ENABLE_CHECK) + 78:Generated_Source\PSoC4/UART_PM.c **** { + 79:Generated_Source\PSoC4/UART_PM.c **** if(UART_SCB_MODE_I2C_RUNTM_CFG) + 80:Generated_Source\PSoC4/UART_PM.c **** { + 81:Generated_Source\PSoC4/UART_PM.c **** UART_I2CSaveConfig(); + 82:Generated_Source\PSoC4/UART_PM.c **** } + 83:Generated_Source\PSoC4/UART_PM.c **** else if(UART_SCB_MODE_EZI2C_RUNTM_CFG) + 84:Generated_Source\PSoC4/UART_PM.c **** { + 85:Generated_Source\PSoC4/UART_PM.c **** UART_EzI2CSaveConfig(); + 86:Generated_Source\PSoC4/UART_PM.c **** } + 87:Generated_Source\PSoC4/UART_PM.c **** #if(!UART_CY_SCBIP_V1) + 88:Generated_Source\PSoC4/UART_PM.c **** else if(UART_SCB_MODE_SPI_RUNTM_CFG) + 89:Generated_Source\PSoC4/UART_PM.c **** { + 90:Generated_Source\PSoC4/UART_PM.c **** UART_SpiSaveConfig(); + 91:Generated_Source\PSoC4/UART_PM.c **** } + 92:Generated_Source\PSoC4/UART_PM.c **** else if(UART_SCB_MODE_UART_RUNTM_CFG) + 93:Generated_Source\PSoC4/UART_PM.c **** { + 94:Generated_Source\PSoC4/UART_PM.c **** UART_UartSaveConfig(); + 95:Generated_Source\PSoC4/UART_PM.c **** } + 96:Generated_Source\PSoC4/UART_PM.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 97:Generated_Source\PSoC4/UART_PM.c **** else + 98:Generated_Source\PSoC4/UART_PM.c **** { + 99:Generated_Source\PSoC4/UART_PM.c **** /* Unknown mode */ + 100:Generated_Source\PSoC4/UART_PM.c **** } + 101:Generated_Source\PSoC4/UART_PM.c **** } + 102:Generated_Source\PSoC4/UART_PM.c **** else + 103:Generated_Source\PSoC4/UART_PM.c **** { + 104:Generated_Source\PSoC4/UART_PM.c **** UART_backup.enableState = (uint8) UART_GET_CTRL_ENABLED; + 105:Generated_Source\PSoC4/UART_PM.c **** + 106:Generated_Source\PSoC4/UART_PM.c **** if(0u != UART_backup.enableState) + 107:Generated_Source\PSoC4/UART_PM.c **** { + 108:Generated_Source\PSoC4/UART_PM.c **** UART_Stop(); + 109:Generated_Source\PSoC4/UART_PM.c **** } + 110:Generated_Source\PSoC4/UART_PM.c **** } + 111:Generated_Source\PSoC4/UART_PM.c **** + 112:Generated_Source\PSoC4/UART_PM.c **** #else + 113:Generated_Source\PSoC4/UART_PM.c **** + 114:Generated_Source\PSoC4/UART_PM.c **** #if (UART_SCB_MODE_I2C_CONST_CFG && UART_I2C_WAKE_ENABLE_CONST) + 115:Generated_Source\PSoC4/UART_PM.c **** UART_I2CSaveConfig(); + 116:Generated_Source\PSoC4/UART_PM.c **** + 117:Generated_Source\PSoC4/UART_PM.c **** #elif (UART_SCB_MODE_EZI2C_CONST_CFG && UART_EZI2C_WAKE_ENABLE_CONST) + 118:Generated_Source\PSoC4/UART_PM.c **** UART_EzI2CSaveConfig(); + 119:Generated_Source\PSoC4/UART_PM.c **** + 120:Generated_Source\PSoC4/UART_PM.c **** #elif (UART_SCB_MODE_SPI_CONST_CFG && UART_SPI_WAKE_ENABLE_CONST) + 121:Generated_Source\PSoC4/UART_PM.c **** UART_SpiSaveConfig(); + 122:Generated_Source\PSoC4/UART_PM.c **** + 123:Generated_Source\PSoC4/UART_PM.c **** #elif (UART_SCB_MODE_UART_CONST_CFG && UART_UART_WAKE_ENABLE_CONST) + 124:Generated_Source\PSoC4/UART_PM.c **** UART_UartSaveConfig(); + 125:Generated_Source\PSoC4/UART_PM.c **** + 126:Generated_Source\PSoC4/UART_PM.c **** #else + 127:Generated_Source\PSoC4/UART_PM.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 4 + + + 128:Generated_Source\PSoC4/UART_PM.c **** UART_backup.enableState = (uint8) UART_GET_CTRL_ENABLED; + 45 .loc 1 128 0 + 46 0004 074B ldr r3, .L4 + 47 0006 1B68 ldr r3, [r3] + 48 0008 DB0F lsrs r3, r3, #31 + 49 000a DBB2 uxtb r3, r3 + 50 000c 1A00 movs r2, r3 + 51 000e 064B ldr r3, .L4+4 + 52 0010 1A70 strb r2, [r3] + 129:Generated_Source\PSoC4/UART_PM.c **** + 130:Generated_Source\PSoC4/UART_PM.c **** if(0u != UART_backup.enableState) + 53 .loc 1 130 0 + 54 0012 054B ldr r3, .L4+4 + 55 0014 1B78 ldrb r3, [r3] + 56 0016 002B cmp r3, #0 + 57 0018 01D0 beq .L3 + 131:Generated_Source\PSoC4/UART_PM.c **** { + 132:Generated_Source\PSoC4/UART_PM.c **** UART_Stop(); + 58 .loc 1 132 0 + 59 001a FFF7FEFF bl UART_Stop + 60 .L3: + 133:Generated_Source\PSoC4/UART_PM.c **** } + 134:Generated_Source\PSoC4/UART_PM.c **** + 135:Generated_Source\PSoC4/UART_PM.c **** #endif /* defined (UART_SCB_MODE_I2C_CONST_CFG) && (UART_I2C_WAKE_ENABLE_CONST) */ + 136:Generated_Source\PSoC4/UART_PM.c **** + 137:Generated_Source\PSoC4/UART_PM.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 138:Generated_Source\PSoC4/UART_PM.c **** } + 61 .loc 1 138 0 + 62 001e C046 nop + 63 0020 BD46 mov sp, r7 + 64 @ sp needed + 65 0022 80BD pop {r7, pc} + 66 .L5: + 67 .align 2 + 68 .L4: + 69 0024 00000640 .word 1074135040 + 70 0028 00000000 .word UART_backup + 71 .cfi_endproc + 72 .LFE0: + 73 .size UART_Sleep, .-UART_Sleep + 74 .section .text.UART_Wakeup,"ax",%progbits + 75 .align 2 + 76 .global UART_Wakeup + 77 .code 16 + 78 .thumb_func + 79 .type UART_Wakeup, %function + 80 UART_Wakeup: + 81 .LFB1: + 139:Generated_Source\PSoC4/UART_PM.c **** + 140:Generated_Source\PSoC4/UART_PM.c **** + 141:Generated_Source\PSoC4/UART_PM.c **** /******************************************************************************* + 142:Generated_Source\PSoC4/UART_PM.c **** * Function Name: UART_Wakeup + 143:Generated_Source\PSoC4/UART_PM.c **** ****************************************************************************//** + 144:Generated_Source\PSoC4/UART_PM.c **** * + 145:Generated_Source\PSoC4/UART_PM.c **** * Prepares the UART component for Active mode operation after + 146:Generated_Source\PSoC4/UART_PM.c **** * Deep Sleep. + 147:Generated_Source\PSoC4/UART_PM.c **** * The “Enable wakeup from Deep Sleep Mode” selection has influence on this + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 5 + + + 148:Generated_Source\PSoC4/UART_PM.c **** * function implementation: + 149:Generated_Source\PSoC4/UART_PM.c **** * - Checked: restores the component Active mode configuration. + 150:Generated_Source\PSoC4/UART_PM.c **** * - Unchecked: enables the component if it was enabled before enter Deep Sleep. + 151:Generated_Source\PSoC4/UART_PM.c **** * + 152:Generated_Source\PSoC4/UART_PM.c **** * This function should not be called after exiting Sleep. + 153:Generated_Source\PSoC4/UART_PM.c **** * + 154:Generated_Source\PSoC4/UART_PM.c **** * \sideeffect + 155:Generated_Source\PSoC4/UART_PM.c **** * Calling the UART_Wakeup() function without first calling the + 156:Generated_Source\PSoC4/UART_PM.c **** * UART_Sleep() function may produce unexpected behavior. + 157:Generated_Source\PSoC4/UART_PM.c **** * + 158:Generated_Source\PSoC4/UART_PM.c **** *******************************************************************************/ + 159:Generated_Source\PSoC4/UART_PM.c **** void UART_Wakeup(void) + 160:Generated_Source\PSoC4/UART_PM.c **** { + 82 .loc 1 160 0 + 83 .cfi_startproc + 84 @ args = 0, pretend = 0, frame = 0 + 85 @ frame_needed = 1, uses_anonymous_args = 0 + 86 0000 80B5 push {r7, lr} + 87 .cfi_def_cfa_offset 8 + 88 .cfi_offset 7, -8 + 89 .cfi_offset 14, -4 + 90 0002 00AF add r7, sp, #0 + 91 .cfi_def_cfa_register 7 + 161:Generated_Source\PSoC4/UART_PM.c **** #if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + 162:Generated_Source\PSoC4/UART_PM.c **** + 163:Generated_Source\PSoC4/UART_PM.c **** if(UART_SCB_WAKE_ENABLE_CHECK) + 164:Generated_Source\PSoC4/UART_PM.c **** { + 165:Generated_Source\PSoC4/UART_PM.c **** if(UART_SCB_MODE_I2C_RUNTM_CFG) + 166:Generated_Source\PSoC4/UART_PM.c **** { + 167:Generated_Source\PSoC4/UART_PM.c **** UART_I2CRestoreConfig(); + 168:Generated_Source\PSoC4/UART_PM.c **** } + 169:Generated_Source\PSoC4/UART_PM.c **** else if(UART_SCB_MODE_EZI2C_RUNTM_CFG) + 170:Generated_Source\PSoC4/UART_PM.c **** { + 171:Generated_Source\PSoC4/UART_PM.c **** UART_EzI2CRestoreConfig(); + 172:Generated_Source\PSoC4/UART_PM.c **** } + 173:Generated_Source\PSoC4/UART_PM.c **** #if(!UART_CY_SCBIP_V1) + 174:Generated_Source\PSoC4/UART_PM.c **** else if(UART_SCB_MODE_SPI_RUNTM_CFG) + 175:Generated_Source\PSoC4/UART_PM.c **** { + 176:Generated_Source\PSoC4/UART_PM.c **** UART_SpiRestoreConfig(); + 177:Generated_Source\PSoC4/UART_PM.c **** } + 178:Generated_Source\PSoC4/UART_PM.c **** else if(UART_SCB_MODE_UART_RUNTM_CFG) + 179:Generated_Source\PSoC4/UART_PM.c **** { + 180:Generated_Source\PSoC4/UART_PM.c **** UART_UartRestoreConfig(); + 181:Generated_Source\PSoC4/UART_PM.c **** } + 182:Generated_Source\PSoC4/UART_PM.c **** #endif /* (!UART_CY_SCBIP_V1) */ + 183:Generated_Source\PSoC4/UART_PM.c **** else + 184:Generated_Source\PSoC4/UART_PM.c **** { + 185:Generated_Source\PSoC4/UART_PM.c **** /* Unknown mode */ + 186:Generated_Source\PSoC4/UART_PM.c **** } + 187:Generated_Source\PSoC4/UART_PM.c **** } + 188:Generated_Source\PSoC4/UART_PM.c **** else + 189:Generated_Source\PSoC4/UART_PM.c **** { + 190:Generated_Source\PSoC4/UART_PM.c **** if(0u != UART_backup.enableState) + 191:Generated_Source\PSoC4/UART_PM.c **** { + 192:Generated_Source\PSoC4/UART_PM.c **** UART_Enable(); + 193:Generated_Source\PSoC4/UART_PM.c **** } + 194:Generated_Source\PSoC4/UART_PM.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 6 + + + 195:Generated_Source\PSoC4/UART_PM.c **** + 196:Generated_Source\PSoC4/UART_PM.c **** #else + 197:Generated_Source\PSoC4/UART_PM.c **** + 198:Generated_Source\PSoC4/UART_PM.c **** #if (UART_SCB_MODE_I2C_CONST_CFG && UART_I2C_WAKE_ENABLE_CONST) + 199:Generated_Source\PSoC4/UART_PM.c **** UART_I2CRestoreConfig(); + 200:Generated_Source\PSoC4/UART_PM.c **** + 201:Generated_Source\PSoC4/UART_PM.c **** #elif (UART_SCB_MODE_EZI2C_CONST_CFG && UART_EZI2C_WAKE_ENABLE_CONST) + 202:Generated_Source\PSoC4/UART_PM.c **** UART_EzI2CRestoreConfig(); + 203:Generated_Source\PSoC4/UART_PM.c **** + 204:Generated_Source\PSoC4/UART_PM.c **** #elif (UART_SCB_MODE_SPI_CONST_CFG && UART_SPI_WAKE_ENABLE_CONST) + 205:Generated_Source\PSoC4/UART_PM.c **** UART_SpiRestoreConfig(); + 206:Generated_Source\PSoC4/UART_PM.c **** + 207:Generated_Source\PSoC4/UART_PM.c **** #elif (UART_SCB_MODE_UART_CONST_CFG && UART_UART_WAKE_ENABLE_CONST) + 208:Generated_Source\PSoC4/UART_PM.c **** UART_UartRestoreConfig(); + 209:Generated_Source\PSoC4/UART_PM.c **** + 210:Generated_Source\PSoC4/UART_PM.c **** #else + 211:Generated_Source\PSoC4/UART_PM.c **** + 212:Generated_Source\PSoC4/UART_PM.c **** if(0u != UART_backup.enableState) + 92 .loc 1 212 0 + 93 0004 044B ldr r3, .L9 + 94 0006 1B78 ldrb r3, [r3] + 95 0008 002B cmp r3, #0 + 96 000a 01D0 beq .L8 + 213:Generated_Source\PSoC4/UART_PM.c **** { + 214:Generated_Source\PSoC4/UART_PM.c **** UART_Enable(); + 97 .loc 1 214 0 + 98 000c FFF7FEFF bl UART_Enable + 99 .L8: + 215:Generated_Source\PSoC4/UART_PM.c **** } + 216:Generated_Source\PSoC4/UART_PM.c **** + 217:Generated_Source\PSoC4/UART_PM.c **** #endif /* (UART_I2C_WAKE_ENABLE_CONST) */ + 218:Generated_Source\PSoC4/UART_PM.c **** + 219:Generated_Source\PSoC4/UART_PM.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 220:Generated_Source\PSoC4/UART_PM.c **** } + 100 .loc 1 220 0 + 101 0010 C046 nop + 102 0012 BD46 mov sp, r7 + 103 @ sp needed + 104 0014 80BD pop {r7, pc} + 105 .L10: + 106 0016 C046 .align 2 + 107 .L9: + 108 0018 00000000 .word UART_backup + 109 .cfi_endproc + 110 .LFE1: + 111 .size UART_Wakeup, .-UART_Wakeup + 112 .text + 113 .Letext0: + 114 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 115 .file 3 "Generated_Source\\PSoC4\\UART.h" + 116 .section .debug_info,"",%progbits + 117 .Ldebug_info0: + 118 0000 07010000 .4byte 0x107 + 119 0004 0400 .2byte 0x4 + 120 0006 00000000 .4byte .Ldebug_abbrev0 + 121 000a 04 .byte 0x4 + 122 000b 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 7 + + + 123 000c 52010000 .4byte .LASF20 + 124 0010 0C .byte 0xc + 125 0011 E9010000 .4byte .LASF21 + 126 0015 2E000000 .4byte .LASF22 + 127 0019 00000000 .4byte .Ldebug_ranges0+0 + 128 001d 00000000 .4byte 0 + 129 0021 00000000 .4byte .Ldebug_line0 + 130 0025 02 .uleb128 0x2 + 131 0026 01 .byte 0x1 + 132 0027 06 .byte 0x6 + 133 0028 30010000 .4byte .LASF0 + 134 002c 02 .uleb128 0x2 + 135 002d 01 .byte 0x1 + 136 002e 08 .byte 0x8 + 137 002f D5000000 .4byte .LASF1 + 138 0033 02 .uleb128 0x2 + 139 0034 02 .byte 0x2 + 140 0035 05 .byte 0x5 + 141 0036 48010000 .4byte .LASF2 + 142 003a 02 .uleb128 0x2 + 143 003b 02 .byte 0x2 + 144 003c 07 .byte 0x7 + 145 003d 1D010000 .4byte .LASF3 + 146 0041 02 .uleb128 0x2 + 147 0042 04 .byte 0x4 + 148 0043 05 .byte 0x5 + 149 0044 0E010000 .4byte .LASF4 + 150 0048 02 .uleb128 0x2 + 151 0049 04 .byte 0x4 + 152 004a 07 .byte 0x7 + 153 004b 9A000000 .4byte .LASF5 + 154 004f 02 .uleb128 0x2 + 155 0050 08 .byte 0x8 + 156 0051 05 .byte 0x5 + 157 0052 00000000 .4byte .LASF6 + 158 0056 02 .uleb128 0x2 + 159 0057 08 .byte 0x8 + 160 0058 07 .byte 0x7 + 161 0059 AC000000 .4byte .LASF7 + 162 005d 03 .uleb128 0x3 + 163 005e 04 .byte 0x4 + 164 005f 05 .byte 0x5 + 165 0060 696E7400 .ascii "int\000" + 166 0064 02 .uleb128 0x2 + 167 0065 04 .byte 0x4 + 168 0066 07 .byte 0x7 + 169 0067 21000000 .4byte .LASF8 + 170 006b 04 .uleb128 0x4 + 171 006c 94000000 .4byte .LASF9 + 172 0070 02 .byte 0x2 + 173 0071 E401 .2byte 0x1e4 + 174 0073 2C000000 .4byte 0x2c + 175 0077 04 .uleb128 0x4 + 176 0078 0E000000 .4byte .LASF10 + 177 007c 02 .byte 0x2 + 178 007d E601 .2byte 0x1e6 + 179 007f 48000000 .4byte 0x48 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 8 + + + 180 0083 02 .uleb128 0x2 + 181 0084 04 .byte 0x4 + 182 0085 04 .byte 0x4 + 183 0086 CF000000 .4byte .LASF11 + 184 008a 02 .uleb128 0x2 + 185 008b 08 .byte 0x8 + 186 008c 04 .byte 0x4 + 187 008d 07010000 .4byte .LASF12 + 188 0091 02 .uleb128 0x2 + 189 0092 01 .byte 0x1 + 190 0093 08 .byte 0x8 + 191 0094 E3000000 .4byte .LASF13 + 192 0098 04 .uleb128 0x4 + 193 0099 17010000 .4byte .LASF14 + 194 009d 02 .byte 0x2 + 195 009e 9002 .2byte 0x290 + 196 00a0 A4000000 .4byte 0xa4 + 197 00a4 05 .uleb128 0x5 + 198 00a5 77000000 .4byte 0x77 + 199 00a9 02 .uleb128 0x2 + 200 00aa 08 .byte 0x8 + 201 00ab 04 .byte 0x4 + 202 00ac 3C010000 .4byte .LASF15 + 203 00b0 02 .uleb128 0x2 + 204 00b1 04 .byte 0x4 + 205 00b2 07 .byte 0x7 + 206 00b3 E0010000 .4byte .LASF16 + 207 00b7 06 .uleb128 0x6 + 208 00b8 01 .byte 0x1 + 209 00b9 03 .byte 0x3 + 210 00ba 60 .byte 0x60 + 211 00bb CC000000 .4byte 0xcc + 212 00bf 07 .uleb128 0x7 + 213 00c0 FB000000 .4byte .LASF23 + 214 00c4 03 .byte 0x3 + 215 00c5 62 .byte 0x62 + 216 00c6 6B000000 .4byte 0x6b + 217 00ca 00 .byte 0 + 218 00cb 00 .byte 0 + 219 00cc 08 .uleb128 0x8 + 220 00cd E8000000 .4byte .LASF17 + 221 00d1 03 .byte 0x3 + 222 00d2 63 .byte 0x63 + 223 00d3 B7000000 .4byte 0xb7 + 224 00d7 09 .uleb128 0x9 + 225 00d8 89000000 .4byte .LASF18 + 226 00dc 01 .byte 0x1 + 227 00dd 49 .byte 0x49 + 228 00de 00000000 .4byte .LFB0 + 229 00e2 2C000000 .4byte .LFE0-.LFB0 + 230 00e6 01 .uleb128 0x1 + 231 00e7 9C .byte 0x9c + 232 00e8 09 .uleb128 0x9 + 233 00e9 C3000000 .4byte .LASF19 + 234 00ed 01 .byte 0x1 + 235 00ee 9F .byte 0x9f + 236 00ef 00000000 .4byte .LFB1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 9 + + + 237 00f3 1C000000 .4byte .LFE1-.LFB1 + 238 00f7 01 .uleb128 0x1 + 239 00f8 9C .byte 0x9c + 240 00f9 0A .uleb128 0xa + 241 00fa 15000000 .4byte .LASF24 + 242 00fe 01 .byte 0x1 + 243 00ff 2D .byte 0x2d + 244 0100 CC000000 .4byte 0xcc + 245 0104 05 .uleb128 0x5 + 246 0105 03 .byte 0x3 + 247 0106 00000000 .4byte UART_backup + 248 010a 00 .byte 0 + 249 .section .debug_abbrev,"",%progbits + 250 .Ldebug_abbrev0: + 251 0000 01 .uleb128 0x1 + 252 0001 11 .uleb128 0x11 + 253 0002 01 .byte 0x1 + 254 0003 25 .uleb128 0x25 + 255 0004 0E .uleb128 0xe + 256 0005 13 .uleb128 0x13 + 257 0006 0B .uleb128 0xb + 258 0007 03 .uleb128 0x3 + 259 0008 0E .uleb128 0xe + 260 0009 1B .uleb128 0x1b + 261 000a 0E .uleb128 0xe + 262 000b 55 .uleb128 0x55 + 263 000c 17 .uleb128 0x17 + 264 000d 11 .uleb128 0x11 + 265 000e 01 .uleb128 0x1 + 266 000f 10 .uleb128 0x10 + 267 0010 17 .uleb128 0x17 + 268 0011 00 .byte 0 + 269 0012 00 .byte 0 + 270 0013 02 .uleb128 0x2 + 271 0014 24 .uleb128 0x24 + 272 0015 00 .byte 0 + 273 0016 0B .uleb128 0xb + 274 0017 0B .uleb128 0xb + 275 0018 3E .uleb128 0x3e + 276 0019 0B .uleb128 0xb + 277 001a 03 .uleb128 0x3 + 278 001b 0E .uleb128 0xe + 279 001c 00 .byte 0 + 280 001d 00 .byte 0 + 281 001e 03 .uleb128 0x3 + 282 001f 24 .uleb128 0x24 + 283 0020 00 .byte 0 + 284 0021 0B .uleb128 0xb + 285 0022 0B .uleb128 0xb + 286 0023 3E .uleb128 0x3e + 287 0024 0B .uleb128 0xb + 288 0025 03 .uleb128 0x3 + 289 0026 08 .uleb128 0x8 + 290 0027 00 .byte 0 + 291 0028 00 .byte 0 + 292 0029 04 .uleb128 0x4 + 293 002a 16 .uleb128 0x16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 10 + + + 294 002b 00 .byte 0 + 295 002c 03 .uleb128 0x3 + 296 002d 0E .uleb128 0xe + 297 002e 3A .uleb128 0x3a + 298 002f 0B .uleb128 0xb + 299 0030 3B .uleb128 0x3b + 300 0031 05 .uleb128 0x5 + 301 0032 49 .uleb128 0x49 + 302 0033 13 .uleb128 0x13 + 303 0034 00 .byte 0 + 304 0035 00 .byte 0 + 305 0036 05 .uleb128 0x5 + 306 0037 35 .uleb128 0x35 + 307 0038 00 .byte 0 + 308 0039 49 .uleb128 0x49 + 309 003a 13 .uleb128 0x13 + 310 003b 00 .byte 0 + 311 003c 00 .byte 0 + 312 003d 06 .uleb128 0x6 + 313 003e 13 .uleb128 0x13 + 314 003f 01 .byte 0x1 + 315 0040 0B .uleb128 0xb + 316 0041 0B .uleb128 0xb + 317 0042 3A .uleb128 0x3a + 318 0043 0B .uleb128 0xb + 319 0044 3B .uleb128 0x3b + 320 0045 0B .uleb128 0xb + 321 0046 01 .uleb128 0x1 + 322 0047 13 .uleb128 0x13 + 323 0048 00 .byte 0 + 324 0049 00 .byte 0 + 325 004a 07 .uleb128 0x7 + 326 004b 0D .uleb128 0xd + 327 004c 00 .byte 0 + 328 004d 03 .uleb128 0x3 + 329 004e 0E .uleb128 0xe + 330 004f 3A .uleb128 0x3a + 331 0050 0B .uleb128 0xb + 332 0051 3B .uleb128 0x3b + 333 0052 0B .uleb128 0xb + 334 0053 49 .uleb128 0x49 + 335 0054 13 .uleb128 0x13 + 336 0055 38 .uleb128 0x38 + 337 0056 0B .uleb128 0xb + 338 0057 00 .byte 0 + 339 0058 00 .byte 0 + 340 0059 08 .uleb128 0x8 + 341 005a 16 .uleb128 0x16 + 342 005b 00 .byte 0 + 343 005c 03 .uleb128 0x3 + 344 005d 0E .uleb128 0xe + 345 005e 3A .uleb128 0x3a + 346 005f 0B .uleb128 0xb + 347 0060 3B .uleb128 0x3b + 348 0061 0B .uleb128 0xb + 349 0062 49 .uleb128 0x49 + 350 0063 13 .uleb128 0x13 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 11 + + + 351 0064 00 .byte 0 + 352 0065 00 .byte 0 + 353 0066 09 .uleb128 0x9 + 354 0067 2E .uleb128 0x2e + 355 0068 00 .byte 0 + 356 0069 3F .uleb128 0x3f + 357 006a 19 .uleb128 0x19 + 358 006b 03 .uleb128 0x3 + 359 006c 0E .uleb128 0xe + 360 006d 3A .uleb128 0x3a + 361 006e 0B .uleb128 0xb + 362 006f 3B .uleb128 0x3b + 363 0070 0B .uleb128 0xb + 364 0071 27 .uleb128 0x27 + 365 0072 19 .uleb128 0x19 + 366 0073 11 .uleb128 0x11 + 367 0074 01 .uleb128 0x1 + 368 0075 12 .uleb128 0x12 + 369 0076 06 .uleb128 0x6 + 370 0077 40 .uleb128 0x40 + 371 0078 18 .uleb128 0x18 + 372 0079 9642 .uleb128 0x2116 + 373 007b 19 .uleb128 0x19 + 374 007c 00 .byte 0 + 375 007d 00 .byte 0 + 376 007e 0A .uleb128 0xa + 377 007f 34 .uleb128 0x34 + 378 0080 00 .byte 0 + 379 0081 03 .uleb128 0x3 + 380 0082 0E .uleb128 0xe + 381 0083 3A .uleb128 0x3a + 382 0084 0B .uleb128 0xb + 383 0085 3B .uleb128 0x3b + 384 0086 0B .uleb128 0xb + 385 0087 49 .uleb128 0x49 + 386 0088 13 .uleb128 0x13 + 387 0089 3F .uleb128 0x3f + 388 008a 19 .uleb128 0x19 + 389 008b 02 .uleb128 0x2 + 390 008c 18 .uleb128 0x18 + 391 008d 00 .byte 0 + 392 008e 00 .byte 0 + 393 008f 00 .byte 0 + 394 .section .debug_aranges,"",%progbits + 395 0000 24000000 .4byte 0x24 + 396 0004 0200 .2byte 0x2 + 397 0006 00000000 .4byte .Ldebug_info0 + 398 000a 04 .byte 0x4 + 399 000b 00 .byte 0 + 400 000c 0000 .2byte 0 + 401 000e 0000 .2byte 0 + 402 0010 00000000 .4byte .LFB0 + 403 0014 2C000000 .4byte .LFE0-.LFB0 + 404 0018 00000000 .4byte .LFB1 + 405 001c 1C000000 .4byte .LFE1-.LFB1 + 406 0020 00000000 .4byte 0 + 407 0024 00000000 .4byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 12 + + + 408 .section .debug_ranges,"",%progbits + 409 .Ldebug_ranges0: + 410 0000 00000000 .4byte .LFB0 + 411 0004 2C000000 .4byte .LFE0 + 412 0008 00000000 .4byte .LFB1 + 413 000c 1C000000 .4byte .LFE1 + 414 0010 00000000 .4byte 0 + 415 0014 00000000 .4byte 0 + 416 .section .debug_line,"",%progbits + 417 .Ldebug_line0: + 418 0000 7F000000 .section .debug_str,"MS",%progbits,1 + 418 02004E00 + 418 00000201 + 418 FB0E0D00 + 418 01010101 + 419 .LASF6: + 420 0000 6C6F6E67 .ascii "long long int\000" + 420 206C6F6E + 420 6720696E + 420 7400 + 421 .LASF10: + 422 000e 75696E74 .ascii "uint32\000" + 422 333200 + 423 .LASF24: + 424 0015 55415254 .ascii "UART_backup\000" + 424 5F626163 + 424 6B757000 + 425 .LASF8: + 426 0021 756E7369 .ascii "unsigned int\000" + 426 676E6564 + 426 20696E74 + 426 00 + 427 .LASF22: + 428 002e 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 428 73657273 + 428 5C6A6167 + 428 756D6965 + 428 6C5C446F + 429 005c 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 429 50536F43 + 429 2D313031 + 429 5C547261 + 429 696E696E + 430 .LASF18: + 431 0089 55415254 .ascii "UART_Sleep\000" + 431 5F536C65 + 431 657000 + 432 .LASF9: + 433 0094 75696E74 .ascii "uint8\000" + 433 3800 + 434 .LASF5: + 435 009a 6C6F6E67 .ascii "long unsigned int\000" + 435 20756E73 + 435 69676E65 + 435 6420696E + 435 7400 + 436 .LASF7: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 13 + + + 437 00ac 6C6F6E67 .ascii "long long unsigned int\000" + 437 206C6F6E + 437 6720756E + 437 7369676E + 437 65642069 + 438 .LASF19: + 439 00c3 55415254 .ascii "UART_Wakeup\000" + 439 5F57616B + 439 65757000 + 440 .LASF11: + 441 00cf 666C6F61 .ascii "float\000" + 441 7400 + 442 .LASF1: + 443 00d5 756E7369 .ascii "unsigned char\000" + 443 676E6564 + 443 20636861 + 443 7200 + 444 .LASF13: + 445 00e3 63686172 .ascii "char\000" + 445 00 + 446 .LASF17: + 447 00e8 55415254 .ascii "UART_BACKUP_STRUCT\000" + 447 5F424143 + 447 4B55505F + 447 53545255 + 447 435400 + 448 .LASF23: + 449 00fb 656E6162 .ascii "enableState\000" + 449 6C655374 + 449 61746500 + 450 .LASF12: + 451 0107 646F7562 .ascii "double\000" + 451 6C6500 + 452 .LASF4: + 453 010e 6C6F6E67 .ascii "long int\000" + 453 20696E74 + 453 00 + 454 .LASF14: + 455 0117 72656733 .ascii "reg32\000" + 455 3200 + 456 .LASF3: + 457 011d 73686F72 .ascii "short unsigned int\000" + 457 7420756E + 457 7369676E + 457 65642069 + 457 6E7400 + 458 .LASF0: + 459 0130 7369676E .ascii "signed char\000" + 459 65642063 + 459 68617200 + 460 .LASF15: + 461 013c 6C6F6E67 .ascii "long double\000" + 461 20646F75 + 461 626C6500 + 462 .LASF2: + 463 0148 73686F72 .ascii "short int\000" + 463 7420696E + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccdUPzNV.s page 14 + + + 463 7400 + 464 .LASF20: + 465 0152 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 465 43313120 + 465 352E342E + 465 31203230 + 465 31363036 + 466 0185 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 466 20726576 + 466 6973696F + 466 6E203233 + 466 37373135 + 467 01b8 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 467 66756E63 + 467 74696F6E + 467 2D736563 + 467 74696F6E + 468 .LASF16: + 469 01e0 73697A65 .ascii "sizetype\000" + 469 74797065 + 469 00 + 470 .LASF21: + 471 01e9 47656E65 .ascii "Generated_Source\\PSoC4\\UART_PM.c\000" + 471 72617465 + 471 645F536F + 471 75726365 + 471 5C50536F + 472 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_PM.o 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34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "UART_SCBCLK.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.UART_SCBCLK_Start,"ax",%progbits + 20 .align 2 + 21 .global UART_SCBCLK_Start + 22 .code 16 + 23 .thumb_func + 24 .type UART_SCBCLK_Start, %function + 25 UART_SCBCLK_Start: + 26 .LFB0: + 27 .file 1 "Generated_Source\\PSoC4\\UART_SCBCLK.c" + 1:Generated_Source\PSoC4/UART_SCBCLK.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/UART_SCBCLK.c **** * File Name: UART_SCBCLK.c + 3:Generated_Source\PSoC4/UART_SCBCLK.c **** * Version 2.20 + 4:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 5:Generated_Source\PSoC4/UART_SCBCLK.c **** * Description: + 6:Generated_Source\PSoC4/UART_SCBCLK.c **** * Provides system API for the clocking, interrupts and watchdog timer. + 7:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 8:Generated_Source\PSoC4/UART_SCBCLK.c **** * Note: + 9:Generated_Source\PSoC4/UART_SCBCLK.c **** * Documentation of the API's in this file is located in the + 10:Generated_Source\PSoC4/UART_SCBCLK.c **** * System Reference Guide provided with PSoC Creator. + 11:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 12:Generated_Source\PSoC4/UART_SCBCLK.c **** ******************************************************************************** + 13:Generated_Source\PSoC4/UART_SCBCLK.c **** * Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. + 14:Generated_Source\PSoC4/UART_SCBCLK.c **** * You may use this file only in accordance with the license, terms, conditions, + 15:Generated_Source\PSoC4/UART_SCBCLK.c **** * disclaimers, and limitations in the end user license agreement accompanying + 16:Generated_Source\PSoC4/UART_SCBCLK.c **** * the software package with which this file was provided. + 17:Generated_Source\PSoC4/UART_SCBCLK.c **** *******************************************************************************/ + 18:Generated_Source\PSoC4/UART_SCBCLK.c **** + 19:Generated_Source\PSoC4/UART_SCBCLK.c **** #include + 20:Generated_Source\PSoC4/UART_SCBCLK.c **** #include "UART_SCBCLK.h" + 21:Generated_Source\PSoC4/UART_SCBCLK.c **** + 22:Generated_Source\PSoC4/UART_SCBCLK.c **** #if defined CYREG_PERI_DIV_CMD + 23:Generated_Source\PSoC4/UART_SCBCLK.c **** + 24:Generated_Source\PSoC4/UART_SCBCLK.c **** /******************************************************************************* + 25:Generated_Source\PSoC4/UART_SCBCLK.c **** * Function Name: UART_SCBCLK_StartEx + 26:Generated_Source\PSoC4/UART_SCBCLK.c **** ******************************************************************************** + 27:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 28:Generated_Source\PSoC4/UART_SCBCLK.c **** * Summary: + 29:Generated_Source\PSoC4/UART_SCBCLK.c **** * Starts the clock, aligned to the specified running clock. + 30:Generated_Source\PSoC4/UART_SCBCLK.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 2 + + + 31:Generated_Source\PSoC4/UART_SCBCLK.c **** * Parameters: + 32:Generated_Source\PSoC4/UART_SCBCLK.c **** * alignClkDiv: The divider to which phase alignment is performed when the + 33:Generated_Source\PSoC4/UART_SCBCLK.c **** * clock is started. + 34:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 35:Generated_Source\PSoC4/UART_SCBCLK.c **** * Returns: + 36:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 37:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 38:Generated_Source\PSoC4/UART_SCBCLK.c **** *******************************************************************************/ + 39:Generated_Source\PSoC4/UART_SCBCLK.c **** void UART_SCBCLK_StartEx(uint32 alignClkDiv) + 40:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 41:Generated_Source\PSoC4/UART_SCBCLK.c **** /* Make sure any previous start command has finished. */ + 42:Generated_Source\PSoC4/UART_SCBCLK.c **** while((UART_SCBCLK_CMD_REG & UART_SCBCLK_CMD_ENABLE_MASK) != 0u) + 43:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 44:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 45:Generated_Source\PSoC4/UART_SCBCLK.c **** + 46:Generated_Source\PSoC4/UART_SCBCLK.c **** /* Specify the target divider and it's alignment divider, and enable. */ + 47:Generated_Source\PSoC4/UART_SCBCLK.c **** UART_SCBCLK_CMD_REG = + 48:Generated_Source\PSoC4/UART_SCBCLK.c **** ((uint32)UART_SCBCLK__DIV_ID << UART_SCBCLK_CMD_DIV_SHIFT)| + 49:Generated_Source\PSoC4/UART_SCBCLK.c **** (alignClkDiv << UART_SCBCLK_CMD_PA_DIV_SHIFT) | + 50:Generated_Source\PSoC4/UART_SCBCLK.c **** (uint32)UART_SCBCLK_CMD_ENABLE_MASK; + 51:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 52:Generated_Source\PSoC4/UART_SCBCLK.c **** + 53:Generated_Source\PSoC4/UART_SCBCLK.c **** #else + 54:Generated_Source\PSoC4/UART_SCBCLK.c **** + 55:Generated_Source\PSoC4/UART_SCBCLK.c **** /******************************************************************************* + 56:Generated_Source\PSoC4/UART_SCBCLK.c **** * Function Name: UART_SCBCLK_Start + 57:Generated_Source\PSoC4/UART_SCBCLK.c **** ******************************************************************************** + 58:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 59:Generated_Source\PSoC4/UART_SCBCLK.c **** * Summary: + 60:Generated_Source\PSoC4/UART_SCBCLK.c **** * Starts the clock. + 61:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 62:Generated_Source\PSoC4/UART_SCBCLK.c **** * Parameters: + 63:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 64:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 65:Generated_Source\PSoC4/UART_SCBCLK.c **** * Returns: + 66:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 67:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 68:Generated_Source\PSoC4/UART_SCBCLK.c **** *******************************************************************************/ + 69:Generated_Source\PSoC4/UART_SCBCLK.c **** + 70:Generated_Source\PSoC4/UART_SCBCLK.c **** void UART_SCBCLK_Start(void) + 71:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 28 .loc 1 71 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 00AF add r7, sp, #0 + 37 .cfi_def_cfa_register 7 + 72:Generated_Source\PSoC4/UART_SCBCLK.c **** /* Set the bit to enable the clock. */ + 73:Generated_Source\PSoC4/UART_SCBCLK.c **** UART_SCBCLK_ENABLE_REG |= UART_SCBCLK__ENABLE_MASK; + 38 .loc 1 73 0 + 39 0004 044B ldr r3, .L2 + 40 0006 044A ldr r2, .L2 + 41 0008 1268 ldr r2, [r2] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 3 + + + 42 000a 8021 movs r1, #128 + 43 000c 0906 lsls r1, r1, #24 + 44 000e 0A43 orrs r2, r1 + 45 0010 1A60 str r2, [r3] + 74:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 46 .loc 1 74 0 + 47 0012 C046 nop + 48 0014 BD46 mov sp, r7 + 49 @ sp needed + 50 0016 80BD pop {r7, pc} + 51 .L3: + 52 .align 2 + 53 .L2: + 54 0018 40000240 .word 1073872960 + 55 .cfi_endproc + 56 .LFE0: + 57 .size UART_SCBCLK_Start, .-UART_SCBCLK_Start + 58 .section .text.UART_SCBCLK_Stop,"ax",%progbits + 59 .align 2 + 60 .global UART_SCBCLK_Stop + 61 .code 16 + 62 .thumb_func + 63 .type UART_SCBCLK_Stop, %function + 64 UART_SCBCLK_Stop: + 65 .LFB1: + 75:Generated_Source\PSoC4/UART_SCBCLK.c **** + 76:Generated_Source\PSoC4/UART_SCBCLK.c **** #endif /* CYREG_PERI_DIV_CMD */ + 77:Generated_Source\PSoC4/UART_SCBCLK.c **** + 78:Generated_Source\PSoC4/UART_SCBCLK.c **** + 79:Generated_Source\PSoC4/UART_SCBCLK.c **** /******************************************************************************* + 80:Generated_Source\PSoC4/UART_SCBCLK.c **** * Function Name: UART_SCBCLK_Stop + 81:Generated_Source\PSoC4/UART_SCBCLK.c **** ******************************************************************************** + 82:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 83:Generated_Source\PSoC4/UART_SCBCLK.c **** * Summary: + 84:Generated_Source\PSoC4/UART_SCBCLK.c **** * Stops the clock and returns immediately. This API does not require the + 85:Generated_Source\PSoC4/UART_SCBCLK.c **** * source clock to be running but may return before the hardware is actually + 86:Generated_Source\PSoC4/UART_SCBCLK.c **** * disabled. + 87:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 88:Generated_Source\PSoC4/UART_SCBCLK.c **** * Parameters: + 89:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 90:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 91:Generated_Source\PSoC4/UART_SCBCLK.c **** * Returns: + 92:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 93:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 94:Generated_Source\PSoC4/UART_SCBCLK.c **** *******************************************************************************/ + 95:Generated_Source\PSoC4/UART_SCBCLK.c **** void UART_SCBCLK_Stop(void) + 96:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 66 .loc 1 96 0 + 67 .cfi_startproc + 68 @ args = 0, pretend = 0, frame = 0 + 69 @ frame_needed = 1, uses_anonymous_args = 0 + 70 0000 80B5 push {r7, lr} + 71 .cfi_def_cfa_offset 8 + 72 .cfi_offset 7, -8 + 73 .cfi_offset 14, -4 + 74 0002 00AF add r7, sp, #0 + 75 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 4 + + + 97:Generated_Source\PSoC4/UART_SCBCLK.c **** #if defined CYREG_PERI_DIV_CMD + 98:Generated_Source\PSoC4/UART_SCBCLK.c **** + 99:Generated_Source\PSoC4/UART_SCBCLK.c **** /* Make sure any previous start command has finished. */ + 100:Generated_Source\PSoC4/UART_SCBCLK.c **** while((UART_SCBCLK_CMD_REG & UART_SCBCLK_CMD_ENABLE_MASK) != 0u) + 101:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 102:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 103:Generated_Source\PSoC4/UART_SCBCLK.c **** + 104:Generated_Source\PSoC4/UART_SCBCLK.c **** /* Specify the target divider and it's alignment divider, and disable. */ + 105:Generated_Source\PSoC4/UART_SCBCLK.c **** UART_SCBCLK_CMD_REG = + 106:Generated_Source\PSoC4/UART_SCBCLK.c **** ((uint32)UART_SCBCLK__DIV_ID << UART_SCBCLK_CMD_DIV_SHIFT)| + 107:Generated_Source\PSoC4/UART_SCBCLK.c **** ((uint32)UART_SCBCLK_CMD_DISABLE_MASK); + 108:Generated_Source\PSoC4/UART_SCBCLK.c **** + 109:Generated_Source\PSoC4/UART_SCBCLK.c **** #else + 110:Generated_Source\PSoC4/UART_SCBCLK.c **** + 111:Generated_Source\PSoC4/UART_SCBCLK.c **** /* Clear the bit to disable the clock. */ + 112:Generated_Source\PSoC4/UART_SCBCLK.c **** UART_SCBCLK_ENABLE_REG &= (uint32)(~UART_SCBCLK__ENABLE_MASK); + 76 .loc 1 112 0 + 77 0004 044B ldr r3, .L5 + 78 0006 044A ldr r2, .L5 + 79 0008 1268 ldr r2, [r2] + 80 000a 5200 lsls r2, r2, #1 + 81 000c 5208 lsrs r2, r2, #1 + 82 000e 1A60 str r2, [r3] + 113:Generated_Source\PSoC4/UART_SCBCLK.c **** + 114:Generated_Source\PSoC4/UART_SCBCLK.c **** #endif /* CYREG_PERI_DIV_CMD */ + 115:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 83 .loc 1 115 0 + 84 0010 C046 nop + 85 0012 BD46 mov sp, r7 + 86 @ sp needed + 87 0014 80BD pop {r7, pc} + 88 .L6: + 89 0016 C046 .align 2 + 90 .L5: + 91 0018 40000240 .word 1073872960 + 92 .cfi_endproc + 93 .LFE1: + 94 .size UART_SCBCLK_Stop, .-UART_SCBCLK_Stop + 95 .section .text.UART_SCBCLK_SetFractionalDividerRegister,"ax",%progbits + 96 .align 2 + 97 .global UART_SCBCLK_SetFractionalDividerRegister + 98 .code 16 + 99 .thumb_func + 100 .type UART_SCBCLK_SetFractionalDividerRegister, %function + 101 UART_SCBCLK_SetFractionalDividerRegister: + 102 .LFB2: + 116:Generated_Source\PSoC4/UART_SCBCLK.c **** + 117:Generated_Source\PSoC4/UART_SCBCLK.c **** + 118:Generated_Source\PSoC4/UART_SCBCLK.c **** /******************************************************************************* + 119:Generated_Source\PSoC4/UART_SCBCLK.c **** * Function Name: UART_SCBCLK_SetFractionalDividerRegister + 120:Generated_Source\PSoC4/UART_SCBCLK.c **** ******************************************************************************** + 121:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 122:Generated_Source\PSoC4/UART_SCBCLK.c **** * Summary: + 123:Generated_Source\PSoC4/UART_SCBCLK.c **** * Modifies the clock divider and the fractional divider. + 124:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 125:Generated_Source\PSoC4/UART_SCBCLK.c **** * Parameters: + 126:Generated_Source\PSoC4/UART_SCBCLK.c **** * clkDivider: Divider register value (0-65535). This value is NOT the + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 5 + + + 127:Generated_Source\PSoC4/UART_SCBCLK.c **** * divider; the clock hardware divides by clkDivider plus one. For example, + 128:Generated_Source\PSoC4/UART_SCBCLK.c **** * to divide the clock by 2, this parameter should be set to 1. + 129:Generated_Source\PSoC4/UART_SCBCLK.c **** * fracDivider: Fractional Divider register value (0-31). + 130:Generated_Source\PSoC4/UART_SCBCLK.c **** * Returns: + 131:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 132:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 133:Generated_Source\PSoC4/UART_SCBCLK.c **** *******************************************************************************/ + 134:Generated_Source\PSoC4/UART_SCBCLK.c **** void UART_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) + 135:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 103 .loc 1 135 0 + 104 .cfi_startproc + 105 @ args = 0, pretend = 0, frame = 16 + 106 @ frame_needed = 1, uses_anonymous_args = 0 + 107 0000 80B5 push {r7, lr} + 108 .cfi_def_cfa_offset 8 + 109 .cfi_offset 7, -8 + 110 .cfi_offset 14, -4 + 111 0002 84B0 sub sp, sp, #16 + 112 .cfi_def_cfa_offset 24 + 113 0004 00AF add r7, sp, #0 + 114 .cfi_def_cfa_register 7 + 115 0006 0200 movs r2, r0 + 116 0008 BB1D adds r3, r7, #6 + 117 000a 1A80 strh r2, [r3] + 118 000c 7B1D adds r3, r7, #5 + 119 000e 0A1C adds r2, r1, #0 + 120 0010 1A70 strb r2, [r3] + 136:Generated_Source\PSoC4/UART_SCBCLK.c **** uint32 maskVal; + 137:Generated_Source\PSoC4/UART_SCBCLK.c **** uint32 regVal; + 138:Generated_Source\PSoC4/UART_SCBCLK.c **** + 139:Generated_Source\PSoC4/UART_SCBCLK.c **** #if defined (UART_SCBCLK__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + 140:Generated_Source\PSoC4/UART_SCBCLK.c **** + 141:Generated_Source\PSoC4/UART_SCBCLK.c **** /* get all but divider bits */ + 142:Generated_Source\PSoC4/UART_SCBCLK.c **** maskVal = UART_SCBCLK_DIV_REG & + 143:Generated_Source\PSoC4/UART_SCBCLK.c **** (uint32)(~(uint32)(UART_SCBCLK_DIV_INT_MASK | UART_SCBCLK_DIV_FRAC_MASK)); + 144:Generated_Source\PSoC4/UART_SCBCLK.c **** /* combine mask and new divider vals into 32-bit value */ + 145:Generated_Source\PSoC4/UART_SCBCLK.c **** regVal = maskVal | + 146:Generated_Source\PSoC4/UART_SCBCLK.c **** ((uint32)((uint32)clkDivider << UART_SCBCLK_DIV_INT_SHIFT) & UART_SCBCLK_DIV_INT_MASK) | + 147:Generated_Source\PSoC4/UART_SCBCLK.c **** ((uint32)((uint32)clkFractional << UART_SCBCLK_DIV_FRAC_SHIFT) & UART_SCBCLK_DIV_FRAC_MASK) + 148:Generated_Source\PSoC4/UART_SCBCLK.c **** + 149:Generated_Source\PSoC4/UART_SCBCLK.c **** #else + 150:Generated_Source\PSoC4/UART_SCBCLK.c **** /* get all but integer divider bits */ + 151:Generated_Source\PSoC4/UART_SCBCLK.c **** maskVal = UART_SCBCLK_DIV_REG & (uint32)(~(uint32)UART_SCBCLK__DIVIDER_MASK); + 121 .loc 1 151 0 + 122 0012 084B ldr r3, .L8 + 123 0014 1B68 ldr r3, [r3] + 124 0016 1B0C lsrs r3, r3, #16 + 125 0018 1B04 lsls r3, r3, #16 + 126 001a FB60 str r3, [r7, #12] + 152:Generated_Source\PSoC4/UART_SCBCLK.c **** /* combine mask and new divider val into 32-bit value */ + 153:Generated_Source\PSoC4/UART_SCBCLK.c **** regVal = clkDivider | maskVal; + 127 .loc 1 153 0 + 128 001c BB1D adds r3, r7, #6 + 129 001e 1A88 ldrh r2, [r3] + 130 0020 FB68 ldr r3, [r7, #12] + 131 0022 1343 orrs r3, r2 + 132 0024 BB60 str r3, [r7, #8] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 6 + + + 154:Generated_Source\PSoC4/UART_SCBCLK.c **** + 155:Generated_Source\PSoC4/UART_SCBCLK.c **** #endif /* UART_SCBCLK__FRAC_MASK || CYREG_PERI_DIV_CMD */ + 156:Generated_Source\PSoC4/UART_SCBCLK.c **** + 157:Generated_Source\PSoC4/UART_SCBCLK.c **** UART_SCBCLK_DIV_REG = regVal; + 133 .loc 1 157 0 + 134 0026 034B ldr r3, .L8 + 135 0028 BA68 ldr r2, [r7, #8] + 136 002a 1A60 str r2, [r3] + 158:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 137 .loc 1 158 0 + 138 002c C046 nop + 139 002e BD46 mov sp, r7 + 140 0030 04B0 add sp, sp, #16 + 141 @ sp needed + 142 0032 80BD pop {r7, pc} + 143 .L9: + 144 .align 2 + 145 .L8: + 146 0034 40000240 .word 1073872960 + 147 .cfi_endproc + 148 .LFE2: + 149 .size UART_SCBCLK_SetFractionalDividerRegister, .-UART_SCBCLK_SetFractionalDividerRegister + 150 .section .text.UART_SCBCLK_GetDividerRegister,"ax",%progbits + 151 .align 2 + 152 .global UART_SCBCLK_GetDividerRegister + 153 .code 16 + 154 .thumb_func + 155 .type UART_SCBCLK_GetDividerRegister, %function + 156 UART_SCBCLK_GetDividerRegister: + 157 .LFB3: + 159:Generated_Source\PSoC4/UART_SCBCLK.c **** + 160:Generated_Source\PSoC4/UART_SCBCLK.c **** + 161:Generated_Source\PSoC4/UART_SCBCLK.c **** /******************************************************************************* + 162:Generated_Source\PSoC4/UART_SCBCLK.c **** * Function Name: UART_SCBCLK_GetDividerRegister + 163:Generated_Source\PSoC4/UART_SCBCLK.c **** ******************************************************************************** + 164:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 165:Generated_Source\PSoC4/UART_SCBCLK.c **** * Summary: + 166:Generated_Source\PSoC4/UART_SCBCLK.c **** * Gets the clock divider register value. + 167:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 168:Generated_Source\PSoC4/UART_SCBCLK.c **** * Parameters: + 169:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 170:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 171:Generated_Source\PSoC4/UART_SCBCLK.c **** * Returns: + 172:Generated_Source\PSoC4/UART_SCBCLK.c **** * Divide value of the clock minus 1. For example, if the clock is set to + 173:Generated_Source\PSoC4/UART_SCBCLK.c **** * divide by 2, the return value will be 1. + 174:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 175:Generated_Source\PSoC4/UART_SCBCLK.c **** *******************************************************************************/ + 176:Generated_Source\PSoC4/UART_SCBCLK.c **** uint16 UART_SCBCLK_GetDividerRegister(void) + 177:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 158 .loc 1 177 0 + 159 .cfi_startproc + 160 @ args = 0, pretend = 0, frame = 0 + 161 @ frame_needed = 1, uses_anonymous_args = 0 + 162 0000 80B5 push {r7, lr} + 163 .cfi_def_cfa_offset 8 + 164 .cfi_offset 7, -8 + 165 .cfi_offset 14, -4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 7 + + + 166 0002 00AF add r7, sp, #0 + 167 .cfi_def_cfa_register 7 + 178:Generated_Source\PSoC4/UART_SCBCLK.c **** return (uint16)((UART_SCBCLK_DIV_REG & UART_SCBCLK_DIV_INT_MASK) + 168 .loc 1 178 0 + 169 0004 024B ldr r3, .L12 + 170 0006 1B68 ldr r3, [r3] + 171 0008 9BB2 uxth r3, r3 + 179:Generated_Source\PSoC4/UART_SCBCLK.c **** >> UART_SCBCLK_DIV_INT_SHIFT); + 180:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 172 .loc 1 180 0 + 173 000a 1800 movs r0, r3 + 174 000c BD46 mov sp, r7 + 175 @ sp needed + 176 000e 80BD pop {r7, pc} + 177 .L13: + 178 .align 2 + 179 .L12: + 180 0010 40000240 .word 1073872960 + 181 .cfi_endproc + 182 .LFE3: + 183 .size UART_SCBCLK_GetDividerRegister, .-UART_SCBCLK_GetDividerRegister + 184 .section .text.UART_SCBCLK_GetFractionalDividerRegister,"ax",%progbits + 185 .align 2 + 186 .global UART_SCBCLK_GetFractionalDividerRegister + 187 .code 16 + 188 .thumb_func + 189 .type UART_SCBCLK_GetFractionalDividerRegister, %function + 190 UART_SCBCLK_GetFractionalDividerRegister: + 191 .LFB4: + 181:Generated_Source\PSoC4/UART_SCBCLK.c **** + 182:Generated_Source\PSoC4/UART_SCBCLK.c **** + 183:Generated_Source\PSoC4/UART_SCBCLK.c **** /******************************************************************************* + 184:Generated_Source\PSoC4/UART_SCBCLK.c **** * Function Name: UART_SCBCLK_GetFractionalDividerRegister + 185:Generated_Source\PSoC4/UART_SCBCLK.c **** ******************************************************************************** + 186:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 187:Generated_Source\PSoC4/UART_SCBCLK.c **** * Summary: + 188:Generated_Source\PSoC4/UART_SCBCLK.c **** * Gets the clock fractional divider register value. + 189:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 190:Generated_Source\PSoC4/UART_SCBCLK.c **** * Parameters: + 191:Generated_Source\PSoC4/UART_SCBCLK.c **** * None + 192:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 193:Generated_Source\PSoC4/UART_SCBCLK.c **** * Returns: + 194:Generated_Source\PSoC4/UART_SCBCLK.c **** * Fractional Divide value of the clock + 195:Generated_Source\PSoC4/UART_SCBCLK.c **** * 0 if the fractional divider is not in use. + 196:Generated_Source\PSoC4/UART_SCBCLK.c **** * + 197:Generated_Source\PSoC4/UART_SCBCLK.c **** *******************************************************************************/ + 198:Generated_Source\PSoC4/UART_SCBCLK.c **** uint8 UART_SCBCLK_GetFractionalDividerRegister(void) + 199:Generated_Source\PSoC4/UART_SCBCLK.c **** { + 192 .loc 1 199 0 + 193 .cfi_startproc + 194 @ args = 0, pretend = 0, frame = 0 + 195 @ frame_needed = 1, uses_anonymous_args = 0 + 196 0000 80B5 push {r7, lr} + 197 .cfi_def_cfa_offset 8 + 198 .cfi_offset 7, -8 + 199 .cfi_offset 14, -4 + 200 0002 00AF add r7, sp, #0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 8 + + + 201 .cfi_def_cfa_register 7 + 200:Generated_Source\PSoC4/UART_SCBCLK.c **** #if defined (UART_SCBCLK__FRAC_MASK) + 201:Generated_Source\PSoC4/UART_SCBCLK.c **** /* return fractional divider bits */ + 202:Generated_Source\PSoC4/UART_SCBCLK.c **** return (uint8)((UART_SCBCLK_DIV_REG & UART_SCBCLK_DIV_FRAC_MASK) + 203:Generated_Source\PSoC4/UART_SCBCLK.c **** >> UART_SCBCLK_DIV_FRAC_SHIFT); + 204:Generated_Source\PSoC4/UART_SCBCLK.c **** #else + 205:Generated_Source\PSoC4/UART_SCBCLK.c **** return 0u; + 202 .loc 1 205 0 + 203 0004 0023 movs r3, #0 + 206:Generated_Source\PSoC4/UART_SCBCLK.c **** #endif /* UART_SCBCLK__FRAC_MASK */ + 207:Generated_Source\PSoC4/UART_SCBCLK.c **** } + 204 .loc 1 207 0 + 205 0006 1800 movs r0, r3 + 206 0008 BD46 mov sp, r7 + 207 @ sp needed + 208 000a 80BD pop {r7, pc} + 209 .cfi_endproc + 210 .LFE4: + 211 .size UART_SCBCLK_GetFractionalDividerRegister, .-UART_SCBCLK_GetFractionalDividerRegister + 212 .text + 213 .Letext0: + 214 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 215 .section .debug_info,"",%progbits + 216 .Ldebug_info0: + 217 0000 4C010000 .4byte 0x14c + 218 0004 0400 .2byte 0x4 + 219 0006 00000000 .4byte .Ldebug_abbrev0 + 220 000a 04 .byte 0x4 + 221 000b 01 .uleb128 0x1 + 222 000c C5000000 .4byte .LASF24 + 223 0010 0C .byte 0xc + 224 0011 30020000 .4byte .LASF25 + 225 0015 1F000000 .4byte .LASF26 + 226 0019 00000000 .4byte .Ldebug_ranges0+0 + 227 001d 00000000 .4byte 0 + 228 0021 00000000 .4byte .Ldebug_line0 + 229 0025 02 .uleb128 0x2 + 230 0026 01 .byte 0x1 + 231 0027 06 .byte 0x6 + 232 0028 6E020000 .4byte .LASF0 + 233 002c 02 .uleb128 0x2 + 234 002d 01 .byte 0x1 + 235 002e 08 .byte 0x8 + 236 002f 80000000 .4byte .LASF1 + 237 0033 02 .uleb128 0x2 + 238 0034 02 .byte 0x2 + 239 0035 05 .byte 0x5 + 240 0036 55020000 .4byte .LASF2 + 241 003a 02 .uleb128 0x2 + 242 003b 02 .byte 0x2 + 243 003c 07 .byte 0x7 + 244 003d B2000000 .4byte .LASF3 + 245 0041 02 .uleb128 0x2 + 246 0042 04 .byte 0x4 + 247 0043 05 .byte 0x5 + 248 0044 65020000 .4byte .LASF4 + 249 0048 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 9 + + + 250 0049 04 .byte 0x4 + 251 004a 07 .byte 0x7 + 252 004b 8E000000 .4byte .LASF5 + 253 004f 02 .uleb128 0x2 + 254 0050 08 .byte 0x8 + 255 0051 05 .byte 0x5 + 256 0052 1D020000 .4byte .LASF6 + 257 0056 02 .uleb128 0x2 + 258 0057 08 .byte 0x8 + 259 0058 07 .byte 0x7 + 260 0059 BE010000 .4byte .LASF7 + 261 005d 03 .uleb128 0x3 + 262 005e 04 .byte 0x4 + 263 005f 05 .byte 0x5 + 264 0060 696E7400 .ascii "int\000" + 265 0064 02 .uleb128 0x2 + 266 0065 04 .byte 0x4 + 267 0066 07 .byte 0x7 + 268 0067 B1010000 .4byte .LASF8 + 269 006b 04 .uleb128 0x4 + 270 006c 5F020000 .4byte .LASF9 + 271 0070 02 .byte 0x2 + 272 0071 E401 .2byte 0x1e4 + 273 0073 2C000000 .4byte 0x2c + 274 0077 04 .uleb128 0x4 + 275 0078 A3010000 .4byte .LASF10 + 276 007c 02 .byte 0x2 + 277 007d E501 .2byte 0x1e5 + 278 007f 3A000000 .4byte 0x3a + 279 0083 04 .uleb128 0x4 + 280 0084 AA010000 .4byte .LASF11 + 281 0088 02 .byte 0x2 + 282 0089 E601 .2byte 0x1e6 + 283 008b 48000000 .4byte 0x48 + 284 008f 02 .uleb128 0x2 + 285 0090 04 .byte 0x4 + 286 0091 04 .byte 0x4 + 287 0092 7A000000 .4byte .LASF12 + 288 0096 02 .uleb128 0x2 + 289 0097 08 .byte 0x8 + 290 0098 04 .byte 0x4 + 291 0099 5E010000 .4byte .LASF13 + 292 009d 02 .uleb128 0x2 + 293 009e 01 .byte 0x1 + 294 009f 08 .byte 0x8 + 295 00a0 2B020000 .4byte .LASF14 + 296 00a4 04 .uleb128 0x4 + 297 00a5 00000000 .4byte .LASF15 + 298 00a9 02 .byte 0x2 + 299 00aa 9002 .2byte 0x290 + 300 00ac B0000000 .4byte 0xb0 + 301 00b0 05 .uleb128 0x5 + 302 00b1 83000000 .4byte 0x83 + 303 00b5 06 .uleb128 0x6 + 304 00b6 A0000000 .4byte .LASF16 + 305 00ba 01 .byte 0x1 + 306 00bb 46 .byte 0x46 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 10 + + + 307 00bc 00000000 .4byte .LFB0 + 308 00c0 1C000000 .4byte .LFE0-.LFB0 + 309 00c4 01 .uleb128 0x1 + 310 00c5 9C .byte 0x9c + 311 00c6 06 .uleb128 0x6 + 312 00c7 0E000000 .4byte .LASF17 + 313 00cb 01 .byte 0x1 + 314 00cc 5F .byte 0x5f + 315 00cd 00000000 .4byte .LFB1 + 316 00d1 1C000000 .4byte .LFE1-.LFB1 + 317 00d5 01 .uleb128 0x1 + 318 00d6 9C .byte 0x9c + 319 00d7 07 .uleb128 0x7 + 320 00d8 F4010000 .4byte .LASF27 + 321 00dc 01 .byte 0x1 + 322 00dd 86 .byte 0x86 + 323 00de 00000000 .4byte .LFB2 + 324 00e2 38000000 .4byte .LFE2-.LFB2 + 325 00e6 01 .uleb128 0x1 + 326 00e7 9C .byte 0x9c + 327 00e8 25010000 .4byte 0x125 + 328 00ec 08 .uleb128 0x8 + 329 00ed 53010000 .4byte .LASF18 + 330 00f1 01 .byte 0x1 + 331 00f2 86 .byte 0x86 + 332 00f3 77000000 .4byte 0x77 + 333 00f7 02 .uleb128 0x2 + 334 00f8 91 .byte 0x91 + 335 00f9 6E .sleb128 -18 + 336 00fa 08 .uleb128 0x8 + 337 00fb 6C010000 .4byte .LASF19 + 338 00ff 01 .byte 0x1 + 339 0100 86 .byte 0x86 + 340 0101 6B000000 .4byte 0x6b + 341 0105 02 .uleb128 0x2 + 342 0106 91 .byte 0x91 + 343 0107 6D .sleb128 -19 + 344 0108 09 .uleb128 0x9 + 345 0109 06000000 .4byte .LASF20 + 346 010d 01 .byte 0x1 + 347 010e 88 .byte 0x88 + 348 010f 83000000 .4byte 0x83 + 349 0113 02 .uleb128 0x2 + 350 0114 91 .byte 0x91 + 351 0115 74 .sleb128 -12 + 352 0116 09 .uleb128 0x9 + 353 0117 65010000 .4byte .LASF21 + 354 011b 01 .byte 0x1 + 355 011c 89 .byte 0x89 + 356 011d 83000000 .4byte 0x83 + 357 0121 02 .uleb128 0x2 + 358 0122 91 .byte 0x91 + 359 0123 70 .sleb128 -16 + 360 0124 00 .byte 0 + 361 0125 0A .uleb128 0xa + 362 0126 D5010000 .4byte .LASF22 + 363 012a 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 11 + + + 364 012b B0 .byte 0xb0 + 365 012c 77000000 .4byte 0x77 + 366 0130 00000000 .4byte .LFB3 + 367 0134 14000000 .4byte .LFE3-.LFB3 + 368 0138 01 .uleb128 0x1 + 369 0139 9C .byte 0x9c + 370 013a 0A .uleb128 0xa + 371 013b 7A010000 .4byte .LASF23 + 372 013f 01 .byte 0x1 + 373 0140 C6 .byte 0xc6 + 374 0141 6B000000 .4byte 0x6b + 375 0145 00000000 .4byte .LFB4 + 376 0149 0C000000 .4byte .LFE4-.LFB4 + 377 014d 01 .uleb128 0x1 + 378 014e 9C .byte 0x9c + 379 014f 00 .byte 0 + 380 .section .debug_abbrev,"",%progbits + 381 .Ldebug_abbrev0: + 382 0000 01 .uleb128 0x1 + 383 0001 11 .uleb128 0x11 + 384 0002 01 .byte 0x1 + 385 0003 25 .uleb128 0x25 + 386 0004 0E .uleb128 0xe + 387 0005 13 .uleb128 0x13 + 388 0006 0B .uleb128 0xb + 389 0007 03 .uleb128 0x3 + 390 0008 0E .uleb128 0xe + 391 0009 1B .uleb128 0x1b + 392 000a 0E .uleb128 0xe + 393 000b 55 .uleb128 0x55 + 394 000c 17 .uleb128 0x17 + 395 000d 11 .uleb128 0x11 + 396 000e 01 .uleb128 0x1 + 397 000f 10 .uleb128 0x10 + 398 0010 17 .uleb128 0x17 + 399 0011 00 .byte 0 + 400 0012 00 .byte 0 + 401 0013 02 .uleb128 0x2 + 402 0014 24 .uleb128 0x24 + 403 0015 00 .byte 0 + 404 0016 0B .uleb128 0xb + 405 0017 0B .uleb128 0xb + 406 0018 3E .uleb128 0x3e + 407 0019 0B .uleb128 0xb + 408 001a 03 .uleb128 0x3 + 409 001b 0E .uleb128 0xe + 410 001c 00 .byte 0 + 411 001d 00 .byte 0 + 412 001e 03 .uleb128 0x3 + 413 001f 24 .uleb128 0x24 + 414 0020 00 .byte 0 + 415 0021 0B .uleb128 0xb + 416 0022 0B .uleb128 0xb + 417 0023 3E .uleb128 0x3e + 418 0024 0B .uleb128 0xb + 419 0025 03 .uleb128 0x3 + 420 0026 08 .uleb128 0x8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 12 + + + 421 0027 00 .byte 0 + 422 0028 00 .byte 0 + 423 0029 04 .uleb128 0x4 + 424 002a 16 .uleb128 0x16 + 425 002b 00 .byte 0 + 426 002c 03 .uleb128 0x3 + 427 002d 0E .uleb128 0xe + 428 002e 3A .uleb128 0x3a + 429 002f 0B .uleb128 0xb + 430 0030 3B .uleb128 0x3b + 431 0031 05 .uleb128 0x5 + 432 0032 49 .uleb128 0x49 + 433 0033 13 .uleb128 0x13 + 434 0034 00 .byte 0 + 435 0035 00 .byte 0 + 436 0036 05 .uleb128 0x5 + 437 0037 35 .uleb128 0x35 + 438 0038 00 .byte 0 + 439 0039 49 .uleb128 0x49 + 440 003a 13 .uleb128 0x13 + 441 003b 00 .byte 0 + 442 003c 00 .byte 0 + 443 003d 06 .uleb128 0x6 + 444 003e 2E .uleb128 0x2e + 445 003f 00 .byte 0 + 446 0040 3F .uleb128 0x3f + 447 0041 19 .uleb128 0x19 + 448 0042 03 .uleb128 0x3 + 449 0043 0E .uleb128 0xe + 450 0044 3A .uleb128 0x3a + 451 0045 0B .uleb128 0xb + 452 0046 3B .uleb128 0x3b + 453 0047 0B .uleb128 0xb + 454 0048 27 .uleb128 0x27 + 455 0049 19 .uleb128 0x19 + 456 004a 11 .uleb128 0x11 + 457 004b 01 .uleb128 0x1 + 458 004c 12 .uleb128 0x12 + 459 004d 06 .uleb128 0x6 + 460 004e 40 .uleb128 0x40 + 461 004f 18 .uleb128 0x18 + 462 0050 9742 .uleb128 0x2117 + 463 0052 19 .uleb128 0x19 + 464 0053 00 .byte 0 + 465 0054 00 .byte 0 + 466 0055 07 .uleb128 0x7 + 467 0056 2E .uleb128 0x2e + 468 0057 01 .byte 0x1 + 469 0058 3F .uleb128 0x3f + 470 0059 19 .uleb128 0x19 + 471 005a 03 .uleb128 0x3 + 472 005b 0E .uleb128 0xe + 473 005c 3A .uleb128 0x3a + 474 005d 0B .uleb128 0xb + 475 005e 3B .uleb128 0x3b + 476 005f 0B .uleb128 0xb + 477 0060 27 .uleb128 0x27 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 13 + + + 478 0061 19 .uleb128 0x19 + 479 0062 11 .uleb128 0x11 + 480 0063 01 .uleb128 0x1 + 481 0064 12 .uleb128 0x12 + 482 0065 06 .uleb128 0x6 + 483 0066 40 .uleb128 0x40 + 484 0067 18 .uleb128 0x18 + 485 0068 9742 .uleb128 0x2117 + 486 006a 19 .uleb128 0x19 + 487 006b 01 .uleb128 0x1 + 488 006c 13 .uleb128 0x13 + 489 006d 00 .byte 0 + 490 006e 00 .byte 0 + 491 006f 08 .uleb128 0x8 + 492 0070 05 .uleb128 0x5 + 493 0071 00 .byte 0 + 494 0072 03 .uleb128 0x3 + 495 0073 0E .uleb128 0xe + 496 0074 3A .uleb128 0x3a + 497 0075 0B .uleb128 0xb + 498 0076 3B .uleb128 0x3b + 499 0077 0B .uleb128 0xb + 500 0078 49 .uleb128 0x49 + 501 0079 13 .uleb128 0x13 + 502 007a 02 .uleb128 0x2 + 503 007b 18 .uleb128 0x18 + 504 007c 00 .byte 0 + 505 007d 00 .byte 0 + 506 007e 09 .uleb128 0x9 + 507 007f 34 .uleb128 0x34 + 508 0080 00 .byte 0 + 509 0081 03 .uleb128 0x3 + 510 0082 0E .uleb128 0xe + 511 0083 3A .uleb128 0x3a + 512 0084 0B .uleb128 0xb + 513 0085 3B .uleb128 0x3b + 514 0086 0B .uleb128 0xb + 515 0087 49 .uleb128 0x49 + 516 0088 13 .uleb128 0x13 + 517 0089 02 .uleb128 0x2 + 518 008a 18 .uleb128 0x18 + 519 008b 00 .byte 0 + 520 008c 00 .byte 0 + 521 008d 0A .uleb128 0xa + 522 008e 2E .uleb128 0x2e + 523 008f 00 .byte 0 + 524 0090 3F .uleb128 0x3f + 525 0091 19 .uleb128 0x19 + 526 0092 03 .uleb128 0x3 + 527 0093 0E .uleb128 0xe + 528 0094 3A .uleb128 0x3a + 529 0095 0B .uleb128 0xb + 530 0096 3B .uleb128 0x3b + 531 0097 0B .uleb128 0xb + 532 0098 27 .uleb128 0x27 + 533 0099 19 .uleb128 0x19 + 534 009a 49 .uleb128 0x49 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 14 + + + 535 009b 13 .uleb128 0x13 + 536 009c 11 .uleb128 0x11 + 537 009d 01 .uleb128 0x1 + 538 009e 12 .uleb128 0x12 + 539 009f 06 .uleb128 0x6 + 540 00a0 40 .uleb128 0x40 + 541 00a1 18 .uleb128 0x18 + 542 00a2 9742 .uleb128 0x2117 + 543 00a4 19 .uleb128 0x19 + 544 00a5 00 .byte 0 + 545 00a6 00 .byte 0 + 546 00a7 00 .byte 0 + 547 .section .debug_aranges,"",%progbits + 548 0000 3C000000 .4byte 0x3c + 549 0004 0200 .2byte 0x2 + 550 0006 00000000 .4byte .Ldebug_info0 + 551 000a 04 .byte 0x4 + 552 000b 00 .byte 0 + 553 000c 0000 .2byte 0 + 554 000e 0000 .2byte 0 + 555 0010 00000000 .4byte .LFB0 + 556 0014 1C000000 .4byte .LFE0-.LFB0 + 557 0018 00000000 .4byte .LFB1 + 558 001c 1C000000 .4byte .LFE1-.LFB1 + 559 0020 00000000 .4byte .LFB2 + 560 0024 38000000 .4byte .LFE2-.LFB2 + 561 0028 00000000 .4byte .LFB3 + 562 002c 14000000 .4byte .LFE3-.LFB3 + 563 0030 00000000 .4byte .LFB4 + 564 0034 0C000000 .4byte .LFE4-.LFB4 + 565 0038 00000000 .4byte 0 + 566 003c 00000000 .4byte 0 + 567 .section .debug_ranges,"",%progbits + 568 .Ldebug_ranges0: + 569 0000 00000000 .4byte .LFB0 + 570 0004 1C000000 .4byte .LFE0 + 571 0008 00000000 .4byte .LFB1 + 572 000c 1C000000 .4byte .LFE1 + 573 0010 00000000 .4byte .LFB2 + 574 0014 38000000 .4byte .LFE2 + 575 0018 00000000 .4byte .LFB3 + 576 001c 14000000 .4byte .LFE3 + 577 0020 00000000 .4byte .LFB4 + 578 0024 0C000000 .4byte .LFE4 + 579 0028 00000000 .4byte 0 + 580 002c 00000000 .4byte 0 + 581 .section .debug_line,"",%progbits + 582 .Ldebug_line0: + 583 0000 AE000000 .section .debug_str,"MS",%progbits,1 + 583 02004800 + 583 00000201 + 583 FB0E0D00 + 583 01010101 + 584 .LASF15: + 585 0000 72656733 .ascii "reg32\000" + 585 3200 + 586 .LASF20: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 15 + + + 587 0006 6D61736B .ascii "maskVal\000" + 587 56616C00 + 588 .LASF17: + 589 000e 55415254 .ascii "UART_SCBCLK_Stop\000" + 589 5F534342 + 589 434C4B5F + 589 53746F70 + 589 00 + 590 .LASF26: + 591 001f 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 591 73657273 + 591 5C6A6167 + 591 756D6965 + 591 6C5C446F + 592 004d 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 592 50536F43 + 592 2D313031 + 592 5C547261 + 592 696E696E + 593 .LASF12: + 594 007a 666C6F61 .ascii "float\000" + 594 7400 + 595 .LASF1: + 596 0080 756E7369 .ascii "unsigned char\000" + 596 676E6564 + 596 20636861 + 596 7200 + 597 .LASF5: + 598 008e 6C6F6E67 .ascii "long unsigned int\000" + 598 20756E73 + 598 69676E65 + 598 6420696E + 598 7400 + 599 .LASF16: + 600 00a0 55415254 .ascii "UART_SCBCLK_Start\000" + 600 5F534342 + 600 434C4B5F + 600 53746172 + 600 7400 + 601 .LASF3: + 602 00b2 73686F72 .ascii "short unsigned int\000" + 602 7420756E + 602 7369676E + 602 65642069 + 602 6E7400 + 603 .LASF24: + 604 00c5 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 604 43313120 + 604 352E342E + 604 31203230 + 604 31363036 + 605 00f8 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 605 20726576 + 605 6973696F + 605 6E203233 + 605 37373135 + 606 012b 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 16 + + + 606 66756E63 + 606 74696F6E + 606 2D736563 + 606 74696F6E + 607 .LASF18: + 608 0153 636C6B44 .ascii "clkDivider\000" + 608 69766964 + 608 657200 + 609 .LASF13: + 610 015e 646F7562 .ascii "double\000" + 610 6C6500 + 611 .LASF21: + 612 0165 72656756 .ascii "regVal\000" + 612 616C00 + 613 .LASF19: + 614 016c 636C6B46 .ascii "clkFractional\000" + 614 72616374 + 614 696F6E61 + 614 6C00 + 615 .LASF23: + 616 017a 55415254 .ascii "UART_SCBCLK_GetFractionalDividerRegister\000" + 616 5F534342 + 616 434C4B5F + 616 47657446 + 616 72616374 + 617 .LASF10: + 618 01a3 75696E74 .ascii "uint16\000" + 618 313600 + 619 .LASF11: + 620 01aa 75696E74 .ascii "uint32\000" + 620 333200 + 621 .LASF8: + 622 01b1 756E7369 .ascii "unsigned int\000" + 622 676E6564 + 622 20696E74 + 622 00 + 623 .LASF7: + 624 01be 6C6F6E67 .ascii "long long unsigned int\000" + 624 206C6F6E + 624 6720756E + 624 7369676E + 624 65642069 + 625 .LASF22: + 626 01d5 55415254 .ascii "UART_SCBCLK_GetDividerRegister\000" + 626 5F534342 + 626 434C4B5F + 626 47657444 + 626 69766964 + 627 .LASF27: + 628 01f4 55415254 .ascii "UART_SCBCLK_SetFractionalDividerRegister\000" + 628 5F534342 + 628 434C4B5F + 628 53657446 + 628 72616374 + 629 .LASF6: + 630 021d 6C6F6E67 .ascii "long long int\000" + 630 206C6F6E + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccZYyPJg.s page 17 + + + 630 6720696E + 630 7400 + 631 .LASF14: + 632 022b 63686172 .ascii "char\000" + 632 00 + 633 .LASF25: + 634 0230 47656E65 .ascii "Generated_Source\\PSoC4\\UART_SCBCLK.c\000" + 634 72617465 + 634 645F536F + 634 75726365 + 634 5C50536F + 635 .LASF2: + 636 0255 73686F72 .ascii "short int\000" + 636 7420696E + 636 7400 + 637 .LASF9: + 638 025f 75696E74 .ascii "uint8\000" + 638 3800 + 639 .LASF4: + 640 0265 6C6F6E67 .ascii "long int\000" + 640 20696E74 + 640 00 + 641 .LASF0: + 642 026e 7369676E .ascii "signed char\000" + 642 65642063 + 642 68617200 + 643 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_SCBCLK.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_SCBCLK.o new file mode 100644 index 0000000000000000000000000000000000000000..35a73c4f806ecf00da8299f043cb2d7c63606ecc GIT binary patch literal 4600 zcmbtXU2Ggz6+U-n|NN6}VyCfVH!y*;bwzfwn>uMon__nzhu{PvJFb8loY~#+?l!wS z*34{aQY0)leQNW7&|`Ockty?3|9 zMdC>7@1AqMbMC$8{*AwJ_QJdng0u*lqOL~t_dU{+oR%;}6EsE}Kd0M?g~aDZ>Klg# zQiG+5EAP&~Gr#f93|TW>-y$t$wCCOV*!S`l-L~lMLlYY>9U6RSVm-4kS)Ux9Ox(W$ z+l~A6(bC&j?1f*}U;W8+XRZ?1w%X>lZNKgdAT&{02B&u!ue`4c$MMNVQ?M zL}mj<%StY@W~J}2mPmT6CDO05mPsCBEtCEg65EMnqaCsDXWY#yd;TJhf|qy`2J5fl zG`D}k?Z1i7%4~`2GEL&EY!sPKAx4hRdd=E`C;3hMN!`L9F^@m=5Vtl{S%%fFA^mTJ zi&xliid~xzL(eQp+C-#mZ-w_%bdKxAaL^U&*)B&=yr-zt2|z$EPeQ$8X;wQRrAnWF%$z6A627 zzG0;d+baUL*S@@RrpLM^#IdJ)V($qt{RzuPWZ=~vKTa(-y!x!$GzYV~6#45kcY0+x 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zkN4S5yyyCOybn*|r$y)c4h&|#A3*0lu0`{1!(j5>f-JClbPSrb9}Dm!ZYbIIp|RbD?=E;VngrCo_t7@{y@4~z zXPEot`RIN}`|`bye9Y6L^F4runeQ#+<2B)YIPTl|_lmXJ&d0x}`gmW&MeA#l;xO;L;%V3Kz`LatAot6{_q93S z0>-E3%lk%;?^*CLq;(mDKlL= UART_rxBufferTail) + 169:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 170:Generated_Source\PSoC4/UART_SPI_UART.c **** size = (locHead - UART_rxBufferTail); + 171:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 172:Generated_Source\PSoC4/UART_SPI_UART.c **** else + 173:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 174:Generated_Source\PSoC4/UART_SPI_UART.c **** size = (locHead + (UART_INTERNAL_RX_BUFFER_SIZE - UART_rxBufferTail)); + 175:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 176:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 177:Generated_Source\PSoC4/UART_SPI_UART.c **** #else + 178:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 179:Generated_Source\PSoC4/UART_SPI_UART.c **** size = UART_GET_RX_FIFO_ENTRIES; + 180:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 181:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif + 182:Generated_Source\PSoC4/UART_SPI_UART.c **** + 183:Generated_Source\PSoC4/UART_SPI_UART.c **** return (size); + 184:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 185:Generated_Source\PSoC4/UART_SPI_UART.c **** + 186:Generated_Source\PSoC4/UART_SPI_UART.c **** + 187:Generated_Source\PSoC4/UART_SPI_UART.c **** /******************************************************************************* + 188:Generated_Source\PSoC4/UART_SPI_UART.c **** * Function Name: UART_SpiUartClearRxBuffer + 189:Generated_Source\PSoC4/UART_SPI_UART.c **** ****************************************************************************//** + 190:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 191:Generated_Source\PSoC4/UART_SPI_UART.c **** * Clears the receive buffer and RX FIFO. + 192:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 193:Generated_Source\PSoC4/UART_SPI_UART.c **** * \globalvars + 194:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_rxBufferHead - the start index to put data into the + 195:Generated_Source\PSoC4/UART_SPI_UART.c **** * software receive buffer. + 196:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_rxBufferTail - the start index to get data from the + 197:Generated_Source\PSoC4/UART_SPI_UART.c **** * software receive buffer. + 198:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 199:Generated_Source\PSoC4/UART_SPI_UART.c **** *******************************************************************************/ + 200:Generated_Source\PSoC4/UART_SPI_UART.c **** void UART_SpiUartClearRxBuffer(void) + 201:Generated_Source\PSoC4/UART_SPI_UART.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 5 + + + 202:Generated_Source\PSoC4/UART_SPI_UART.c **** #if (UART_CHECK_RX_SW_BUFFER) + 203:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 204:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Lock from component interruption */ + 205:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_DisableInt(); + 206:Generated_Source\PSoC4/UART_SPI_UART.c **** + 207:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Flush RX software buffer */ + 208:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_rxBufferHead = UART_rxBufferTail; + 209:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_rxBufferOverflow = 0u; + 210:Generated_Source\PSoC4/UART_SPI_UART.c **** + 211:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_CLEAR_RX_FIFO; + 212:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_ClearRxInterruptSource(UART_INTR_RX_ALL); + 213:Generated_Source\PSoC4/UART_SPI_UART.c **** + 214:Generated_Source\PSoC4/UART_SPI_UART.c **** #if (UART_CHECK_UART_RTS_CONTROL_FLOW) + 215:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 216:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Enable RX Not Empty interrupt source to continue receiving + 217:Generated_Source\PSoC4/UART_SPI_UART.c **** * data into software buffer. + 218:Generated_Source\PSoC4/UART_SPI_UART.c **** */ + 219:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_INTR_RX_MASK_REG |= UART_INTR_RX_NOT_EMPTY; + 220:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 221:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif + 222:Generated_Source\PSoC4/UART_SPI_UART.c **** + 223:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Release lock */ + 224:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_EnableInt(); + 225:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 226:Generated_Source\PSoC4/UART_SPI_UART.c **** #else + 227:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 228:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_CLEAR_RX_FIFO; + 229:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 230:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif + 231:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 232:Generated_Source\PSoC4/UART_SPI_UART.c **** + 233:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif /* (UART_RX_DIRECTION) */ + 234:Generated_Source\PSoC4/UART_SPI_UART.c **** + 235:Generated_Source\PSoC4/UART_SPI_UART.c **** + 236:Generated_Source\PSoC4/UART_SPI_UART.c **** #if(UART_TX_DIRECTION) + 237:Generated_Source\PSoC4/UART_SPI_UART.c **** /******************************************************************************* + 238:Generated_Source\PSoC4/UART_SPI_UART.c **** * Function Name: UART_SpiUartWriteTxData + 239:Generated_Source\PSoC4/UART_SPI_UART.c **** ****************************************************************************//** + 240:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 241:Generated_Source\PSoC4/UART_SPI_UART.c **** * Places a data entry into the transmit buffer to be sent at the next available + 242:Generated_Source\PSoC4/UART_SPI_UART.c **** * bus time. + 243:Generated_Source\PSoC4/UART_SPI_UART.c **** * This function is blocking and waits until there is space available to put the + 244:Generated_Source\PSoC4/UART_SPI_UART.c **** * requested data in the transmit buffer. + 245:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 246:Generated_Source\PSoC4/UART_SPI_UART.c **** * \param txDataByte: the data to be transmitted. + 247:Generated_Source\PSoC4/UART_SPI_UART.c **** * The amount of data bits to be transmitted depends on TX data bits selection + 248:Generated_Source\PSoC4/UART_SPI_UART.c **** * (the data bit counting starts from LSB of txDataByte). + 249:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 250:Generated_Source\PSoC4/UART_SPI_UART.c **** * \globalvars + 251:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferHead - the start index to put data into the + 252:Generated_Source\PSoC4/UART_SPI_UART.c **** * software transmit buffer. + 253:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferTail - start index to get data from the software + 254:Generated_Source\PSoC4/UART_SPI_UART.c **** * transmit buffer. + 255:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 256:Generated_Source\PSoC4/UART_SPI_UART.c **** *******************************************************************************/ + 257:Generated_Source\PSoC4/UART_SPI_UART.c **** void UART_SpiUartWriteTxData(uint32 txData) + 258:Generated_Source\PSoC4/UART_SPI_UART.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 6 + + + 28 .loc 1 258 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 82B0 sub sp, sp, #8 + 37 .cfi_def_cfa_offset 16 + 38 0004 00AF add r7, sp, #0 + 39 .cfi_def_cfa_register 7 + 40 0006 7860 str r0, [r7, #4] + 259:Generated_Source\PSoC4/UART_SPI_UART.c **** #if (UART_INTERNAL_TX_SW_BUFFER_CONST) + 260:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 locHead; + 261:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + 262:Generated_Source\PSoC4/UART_SPI_UART.c **** + 263:Generated_Source\PSoC4/UART_SPI_UART.c **** #if (UART_CHECK_TX_SW_BUFFER) + 264:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 265:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Put data directly into the TX FIFO */ + 266:Generated_Source\PSoC4/UART_SPI_UART.c **** if ((UART_txBufferHead == UART_txBufferTail) && + 267:Generated_Source\PSoC4/UART_SPI_UART.c **** (UART_SPI_UART_FIFO_SIZE != UART_GET_TX_FIFO_ENTRIES)) + 268:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 269:Generated_Source\PSoC4/UART_SPI_UART.c **** /* TX software buffer is empty: put data directly in TX FIFO */ + 270:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_TX_FIFO_WR_REG = txData; + 271:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 272:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Put data into TX software buffer */ + 273:Generated_Source\PSoC4/UART_SPI_UART.c **** else + 274:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 275:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Head index to put data */ + 276:Generated_Source\PSoC4/UART_SPI_UART.c **** locHead = (UART_txBufferHead + 1u); + 277:Generated_Source\PSoC4/UART_SPI_UART.c **** + 278:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Adjust TX software buffer index */ + 279:Generated_Source\PSoC4/UART_SPI_UART.c **** if (UART_TX_BUFFER_SIZE == locHead) + 280:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 281:Generated_Source\PSoC4/UART_SPI_UART.c **** locHead = 0u; + 282:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 283:Generated_Source\PSoC4/UART_SPI_UART.c **** + 284:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Wait for space in TX software buffer */ + 285:Generated_Source\PSoC4/UART_SPI_UART.c **** while (locHead == UART_txBufferTail) + 286:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 287:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 288:Generated_Source\PSoC4/UART_SPI_UART.c **** + 289:Generated_Source\PSoC4/UART_SPI_UART.c **** /* TX software buffer has at least one room */ + 290:Generated_Source\PSoC4/UART_SPI_UART.c **** + 291:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Clear old status of INTR_TX_NOT_FULL. It sets at the end of transfer when TX FIF + 292:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_ClearTxInterruptSource(UART_INTR_TX_NOT_FULL); + 293:Generated_Source\PSoC4/UART_SPI_UART.c **** + 294:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_PutWordInTxBuffer(locHead, txData); + 295:Generated_Source\PSoC4/UART_SPI_UART.c **** + 296:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_txBufferHead = locHead; + 297:Generated_Source\PSoC4/UART_SPI_UART.c **** + 298:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Check if TX Not Full is disabled in interrupt */ + 299:Generated_Source\PSoC4/UART_SPI_UART.c **** if (0u == (UART_INTR_TX_MASK_REG & UART_INTR_TX_NOT_FULL)) + 300:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 301:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Enable TX Not Full interrupt source to transmit from software buffer */ + 302:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_INTR_TX_MASK_REG |= (uint32) UART_INTR_TX_NOT_FULL; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 7 + + + 303:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 304:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 305:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 306:Generated_Source\PSoC4/UART_SPI_UART.c **** #else + 307:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 308:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Wait until TX FIFO has space to put data element */ + 309:Generated_Source\PSoC4/UART_SPI_UART.c **** while (UART_SPI_UART_FIFO_SIZE == UART_GET_TX_FIFO_ENTRIES) + 41 .loc 1 309 0 + 42 0008 C046 nop + 43 .L2: + 44 .loc 1 309 0 is_stmt 0 discriminator 1 + 45 000a 064B ldr r3, .L3 + 46 000c 1B68 ldr r3, [r3] + 47 000e 0F22 movs r2, #15 + 48 0010 1340 ands r3, r2 + 49 0012 082B cmp r3, #8 + 50 0014 F9D0 beq .L2 + 310:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 311:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 312:Generated_Source\PSoC4/UART_SPI_UART.c **** + 313:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_TX_FIFO_WR_REG = txData; + 51 .loc 1 313 0 is_stmt 1 + 52 0016 044B ldr r3, .L3+4 + 53 0018 7A68 ldr r2, [r7, #4] + 54 001a 1A60 str r2, [r3] + 314:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 315:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif + 316:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 55 .loc 1 316 0 + 56 001c C046 nop + 57 001e BD46 mov sp, r7 + 58 0020 02B0 add sp, sp, #8 + 59 @ sp needed + 60 0022 80BD pop {r7, pc} + 61 .L4: + 62 .align 2 + 63 .L3: + 64 0024 08020640 .word 1074135560 + 65 0028 40020640 .word 1074135616 + 66 .cfi_endproc + 67 .LFE0: + 68 .size UART_SpiUartWriteTxData, .-UART_SpiUartWriteTxData + 69 .section .text.UART_SpiUartPutArray,"ax",%progbits + 70 .align 2 + 71 .global UART_SpiUartPutArray + 72 .code 16 + 73 .thumb_func + 74 .type UART_SpiUartPutArray, %function + 75 UART_SpiUartPutArray: + 76 .LFB1: + 317:Generated_Source\PSoC4/UART_SPI_UART.c **** + 318:Generated_Source\PSoC4/UART_SPI_UART.c **** + 319:Generated_Source\PSoC4/UART_SPI_UART.c **** /******************************************************************************* + 320:Generated_Source\PSoC4/UART_SPI_UART.c **** * Function Name: UART_SpiUartPutArray + 321:Generated_Source\PSoC4/UART_SPI_UART.c **** ****************************************************************************//** + 322:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 323:Generated_Source\PSoC4/UART_SPI_UART.c **** * Places an array of data into the transmit buffer to be sent. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 8 + + + 324:Generated_Source\PSoC4/UART_SPI_UART.c **** * This function is blocking and waits until there is a space available to put + 325:Generated_Source\PSoC4/UART_SPI_UART.c **** * all the requested data in the transmit buffer. The array size can be greater + 326:Generated_Source\PSoC4/UART_SPI_UART.c **** * than transmit buffer size. + 327:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 328:Generated_Source\PSoC4/UART_SPI_UART.c **** * \param wrBuf: pointer to an array of data to be placed in transmit buffer. + 329:Generated_Source\PSoC4/UART_SPI_UART.c **** * The width of the data to be transmitted depends on TX data width selection + 330:Generated_Source\PSoC4/UART_SPI_UART.c **** * (the data bit counting starts from LSB for each array element). + 331:Generated_Source\PSoC4/UART_SPI_UART.c **** * \param count: number of data elements to be placed in the transmit buffer. + 332:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 333:Generated_Source\PSoC4/UART_SPI_UART.c **** * \globalvars + 334:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferHead - the start index to put data into the + 335:Generated_Source\PSoC4/UART_SPI_UART.c **** * software transmit buffer. + 336:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferTail - start index to get data from the software + 337:Generated_Source\PSoC4/UART_SPI_UART.c **** * transmit buffer. + 338:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 339:Generated_Source\PSoC4/UART_SPI_UART.c **** *******************************************************************************/ + 340:Generated_Source\PSoC4/UART_SPI_UART.c **** void UART_SpiUartPutArray(const uint8 wrBuf[], uint32 count) + 341:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 77 .loc 1 341 0 + 78 .cfi_startproc + 79 @ args = 0, pretend = 0, frame = 16 + 80 @ frame_needed = 1, uses_anonymous_args = 0 + 81 0000 80B5 push {r7, lr} + 82 .cfi_def_cfa_offset 8 + 83 .cfi_offset 7, -8 + 84 .cfi_offset 14, -4 + 85 0002 84B0 sub sp, sp, #16 + 86 .cfi_def_cfa_offset 24 + 87 0004 00AF add r7, sp, #0 + 88 .cfi_def_cfa_register 7 + 89 0006 7860 str r0, [r7, #4] + 90 0008 3960 str r1, [r7] + 342:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 i; + 343:Generated_Source\PSoC4/UART_SPI_UART.c **** + 344:Generated_Source\PSoC4/UART_SPI_UART.c **** for (i=0u; i < count; i++) + 91 .loc 1 344 0 + 92 000a 0023 movs r3, #0 + 93 000c FB60 str r3, [r7, #12] + 94 000e 09E0 b .L6 + 95 .L7: + 345:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 346:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_SpiUartWriteTxData((uint32) wrBuf[i]); + 96 .loc 1 346 0 discriminator 3 + 97 0010 7A68 ldr r2, [r7, #4] + 98 0012 FB68 ldr r3, [r7, #12] + 99 0014 D318 adds r3, r2, r3 + 100 0016 1B78 ldrb r3, [r3] + 101 0018 1800 movs r0, r3 + 102 001a FFF7FEFF bl UART_SpiUartWriteTxData + 344:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 103 .loc 1 344 0 discriminator 3 + 104 001e FB68 ldr r3, [r7, #12] + 105 0020 0133 adds r3, r3, #1 + 106 0022 FB60 str r3, [r7, #12] + 107 .L6: + 344:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 108 .loc 1 344 0 is_stmt 0 discriminator 1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 9 + + + 109 0024 FA68 ldr r2, [r7, #12] + 110 0026 3B68 ldr r3, [r7] + 111 0028 9A42 cmp r2, r3 + 112 002a F1D3 bcc .L7 + 347:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 348:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 113 .loc 1 348 0 is_stmt 1 + 114 002c C046 nop + 115 002e BD46 mov sp, r7 + 116 0030 04B0 add sp, sp, #16 + 117 @ sp needed + 118 0032 80BD pop {r7, pc} + 119 .cfi_endproc + 120 .LFE1: + 121 .size UART_SpiUartPutArray, .-UART_SpiUartPutArray + 122 .section .text.UART_SpiUartGetTxBufferSize,"ax",%progbits + 123 .align 2 + 124 .global UART_SpiUartGetTxBufferSize + 125 .code 16 + 126 .thumb_func + 127 .type UART_SpiUartGetTxBufferSize, %function + 128 UART_SpiUartGetTxBufferSize: + 129 .LFB2: + 349:Generated_Source\PSoC4/UART_SPI_UART.c **** + 350:Generated_Source\PSoC4/UART_SPI_UART.c **** + 351:Generated_Source\PSoC4/UART_SPI_UART.c **** /******************************************************************************* + 352:Generated_Source\PSoC4/UART_SPI_UART.c **** * Function Name: UART_SpiUartGetTxBufferSize + 353:Generated_Source\PSoC4/UART_SPI_UART.c **** ****************************************************************************//** + 354:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 355:Generated_Source\PSoC4/UART_SPI_UART.c **** * Returns the number of elements currently in the transmit buffer. + 356:Generated_Source\PSoC4/UART_SPI_UART.c **** * - TX software buffer is disabled: returns the number of used entries in + 357:Generated_Source\PSoC4/UART_SPI_UART.c **** * TX FIFO. + 358:Generated_Source\PSoC4/UART_SPI_UART.c **** * - TX software buffer is enabled: returns the number of elements currently + 359:Generated_Source\PSoC4/UART_SPI_UART.c **** * used in the transmit buffer. This number does not include used entries in + 360:Generated_Source\PSoC4/UART_SPI_UART.c **** * the TX FIFO. The transmit buffer size is zero until the TX FIFO is + 361:Generated_Source\PSoC4/UART_SPI_UART.c **** * not full. + 362:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 363:Generated_Source\PSoC4/UART_SPI_UART.c **** * \return + 364:Generated_Source\PSoC4/UART_SPI_UART.c **** * Number of data elements ready to transmit. + 365:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 366:Generated_Source\PSoC4/UART_SPI_UART.c **** * \globalvars + 367:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferHead - the start index to put data into the + 368:Generated_Source\PSoC4/UART_SPI_UART.c **** * software transmit buffer. + 369:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferTail - start index to get data from the software + 370:Generated_Source\PSoC4/UART_SPI_UART.c **** * transmit buffer. + 371:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 372:Generated_Source\PSoC4/UART_SPI_UART.c **** *******************************************************************************/ + 373:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 UART_SpiUartGetTxBufferSize(void) + 374:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 130 .loc 1 374 0 + 131 .cfi_startproc + 132 @ args = 0, pretend = 0, frame = 8 + 133 @ frame_needed = 1, uses_anonymous_args = 0 + 134 0000 80B5 push {r7, lr} + 135 .cfi_def_cfa_offset 8 + 136 .cfi_offset 7, -8 + 137 .cfi_offset 14, -4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 10 + + + 138 0002 82B0 sub sp, sp, #8 + 139 .cfi_def_cfa_offset 16 + 140 0004 00AF add r7, sp, #0 + 141 .cfi_def_cfa_register 7 + 375:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 size; + 376:Generated_Source\PSoC4/UART_SPI_UART.c **** #if (UART_INTERNAL_TX_SW_BUFFER_CONST) + 377:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 locTail; + 378:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + 379:Generated_Source\PSoC4/UART_SPI_UART.c **** + 380:Generated_Source\PSoC4/UART_SPI_UART.c **** #if (UART_CHECK_TX_SW_BUFFER) + 381:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 382:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Get current Tail index */ + 383:Generated_Source\PSoC4/UART_SPI_UART.c **** locTail = UART_txBufferTail; + 384:Generated_Source\PSoC4/UART_SPI_UART.c **** + 385:Generated_Source\PSoC4/UART_SPI_UART.c **** if (UART_txBufferHead >= locTail) + 386:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 387:Generated_Source\PSoC4/UART_SPI_UART.c **** size = (UART_txBufferHead - locTail); + 388:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 389:Generated_Source\PSoC4/UART_SPI_UART.c **** else + 390:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 391:Generated_Source\PSoC4/UART_SPI_UART.c **** size = (UART_txBufferHead + (UART_TX_BUFFER_SIZE - locTail)); + 392:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 393:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 394:Generated_Source\PSoC4/UART_SPI_UART.c **** #else + 395:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 396:Generated_Source\PSoC4/UART_SPI_UART.c **** size = UART_GET_TX_FIFO_ENTRIES; + 142 .loc 1 396 0 + 143 0006 054B ldr r3, .L10 + 144 0008 1B68 ldr r3, [r3] + 145 000a 0F22 movs r2, #15 + 146 000c 1340 ands r3, r2 + 147 000e 7B60 str r3, [r7, #4] + 397:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 398:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif + 399:Generated_Source\PSoC4/UART_SPI_UART.c **** + 400:Generated_Source\PSoC4/UART_SPI_UART.c **** return (size); + 148 .loc 1 400 0 + 149 0010 7B68 ldr r3, [r7, #4] + 401:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 150 .loc 1 401 0 + 151 0012 1800 movs r0, r3 + 152 0014 BD46 mov sp, r7 + 153 0016 02B0 add sp, sp, #8 + 154 @ sp needed + 155 0018 80BD pop {r7, pc} + 156 .L11: + 157 001a C046 .align 2 + 158 .L10: + 159 001c 08020640 .word 1074135560 + 160 .cfi_endproc + 161 .LFE2: + 162 .size UART_SpiUartGetTxBufferSize, .-UART_SpiUartGetTxBufferSize + 163 .section .text.UART_SpiUartClearTxBuffer,"ax",%progbits + 164 .align 2 + 165 .global UART_SpiUartClearTxBuffer + 166 .code 16 + 167 .thumb_func + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 11 + + + 168 .type UART_SpiUartClearTxBuffer, %function + 169 UART_SpiUartClearTxBuffer: + 170 .LFB3: + 402:Generated_Source\PSoC4/UART_SPI_UART.c **** + 403:Generated_Source\PSoC4/UART_SPI_UART.c **** + 404:Generated_Source\PSoC4/UART_SPI_UART.c **** /******************************************************************************* + 405:Generated_Source\PSoC4/UART_SPI_UART.c **** * Function Name: UART_SpiUartClearTxBuffer + 406:Generated_Source\PSoC4/UART_SPI_UART.c **** ****************************************************************************//** + 407:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 408:Generated_Source\PSoC4/UART_SPI_UART.c **** * Clears the transmit buffer and TX FIFO. + 409:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 410:Generated_Source\PSoC4/UART_SPI_UART.c **** * \globalvars + 411:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferHead - the start index to put data into the + 412:Generated_Source\PSoC4/UART_SPI_UART.c **** * software transmit buffer. + 413:Generated_Source\PSoC4/UART_SPI_UART.c **** * UART_txBufferTail - start index to get data from the software + 414:Generated_Source\PSoC4/UART_SPI_UART.c **** * transmit buffer. + 415:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 416:Generated_Source\PSoC4/UART_SPI_UART.c **** *******************************************************************************/ + 417:Generated_Source\PSoC4/UART_SPI_UART.c **** void UART_SpiUartClearTxBuffer(void) + 418:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 171 .loc 1 418 0 + 172 .cfi_startproc + 173 @ args = 0, pretend = 0, frame = 0 + 174 @ frame_needed = 1, uses_anonymous_args = 0 + 175 0000 80B5 push {r7, lr} + 176 .cfi_def_cfa_offset 8 + 177 .cfi_offset 7, -8 + 178 .cfi_offset 14, -4 + 179 0002 00AF add r7, sp, #0 + 180 .cfi_def_cfa_register 7 + 419:Generated_Source\PSoC4/UART_SPI_UART.c **** #if (UART_CHECK_TX_SW_BUFFER) + 420:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 421:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Lock from component interruption */ + 422:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_DisableInt(); + 423:Generated_Source\PSoC4/UART_SPI_UART.c **** + 424:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Flush TX software buffer */ + 425:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_txBufferHead = UART_txBufferTail; + 426:Generated_Source\PSoC4/UART_SPI_UART.c **** + 427:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_INTR_TX_MASK_REG &= (uint32) ~UART_INTR_TX_NOT_FULL; + 428:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_CLEAR_TX_FIFO; + 429:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_ClearTxInterruptSource(UART_INTR_TX_ALL); + 430:Generated_Source\PSoC4/UART_SPI_UART.c **** + 431:Generated_Source\PSoC4/UART_SPI_UART.c **** /* Release lock */ + 432:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_EnableInt(); + 433:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 434:Generated_Source\PSoC4/UART_SPI_UART.c **** #else + 435:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 436:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_CLEAR_TX_FIFO; + 181 .loc 1 436 0 + 182 0004 074B ldr r3, .L13 + 183 0006 074A ldr r2, .L13 + 184 0008 1268 ldr r2, [r2] + 185 000a 8021 movs r1, #128 + 186 000c 4902 lsls r1, r1, #9 + 187 000e 0A43 orrs r2, r1 + 188 0010 1A60 str r2, [r3] + 189 0012 044B ldr r3, .L13 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 12 + + + 190 0014 034A ldr r2, .L13 + 191 0016 1268 ldr r2, [r2] + 192 0018 0349 ldr r1, .L13+4 + 193 001a 0A40 ands r2, r1 + 194 001c 1A60 str r2, [r3] + 437:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 438:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif + 439:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 195 .loc 1 439 0 + 196 001e C046 nop + 197 0020 BD46 mov sp, r7 + 198 @ sp needed + 199 0022 80BD pop {r7, pc} + 200 .L14: + 201 .align 2 + 202 .L13: + 203 0024 04020640 .word 1074135556 + 204 0028 FFFFFEFF .word -65537 + 205 .cfi_endproc + 206 .LFE3: + 207 .size UART_SpiUartClearTxBuffer, .-UART_SpiUartClearTxBuffer + 208 .section .text.UART_SpiUartDisableIntRx,"ax",%progbits + 209 .align 2 + 210 .global UART_SpiUartDisableIntRx + 211 .code 16 + 212 .thumb_func + 213 .type UART_SpiUartDisableIntRx, %function + 214 UART_SpiUartDisableIntRx: + 215 .LFB4: + 440:Generated_Source\PSoC4/UART_SPI_UART.c **** + 441:Generated_Source\PSoC4/UART_SPI_UART.c **** #endif /* (UART_TX_DIRECTION) */ + 442:Generated_Source\PSoC4/UART_SPI_UART.c **** + 443:Generated_Source\PSoC4/UART_SPI_UART.c **** + 444:Generated_Source\PSoC4/UART_SPI_UART.c **** /******************************************************************************* + 445:Generated_Source\PSoC4/UART_SPI_UART.c **** * Function Name: UART_SpiUartDisableIntRx + 446:Generated_Source\PSoC4/UART_SPI_UART.c **** ****************************************************************************//** + 447:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 448:Generated_Source\PSoC4/UART_SPI_UART.c **** * Disables the RX interrupt sources. + 449:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 450:Generated_Source\PSoC4/UART_SPI_UART.c **** * \return + 451:Generated_Source\PSoC4/UART_SPI_UART.c **** * Returns the RX interrupt sources enabled before the function call. + 452:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 453:Generated_Source\PSoC4/UART_SPI_UART.c **** *******************************************************************************/ + 454:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 UART_SpiUartDisableIntRx(void) + 455:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 216 .loc 1 455 0 + 217 .cfi_startproc + 218 @ args = 0, pretend = 0, frame = 8 + 219 @ frame_needed = 1, uses_anonymous_args = 0 + 220 0000 80B5 push {r7, lr} + 221 .cfi_def_cfa_offset 8 + 222 .cfi_offset 7, -8 + 223 .cfi_offset 14, -4 + 224 0002 82B0 sub sp, sp, #8 + 225 .cfi_def_cfa_offset 16 + 226 0004 00AF add r7, sp, #0 + 227 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 13 + + + 456:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 intSource; + 457:Generated_Source\PSoC4/UART_SPI_UART.c **** + 458:Generated_Source\PSoC4/UART_SPI_UART.c **** intSource = UART_GetRxInterruptMode(); + 228 .loc 1 458 0 + 229 0006 054B ldr r3, .L17 + 230 0008 1B68 ldr r3, [r3] + 231 000a 7B60 str r3, [r7, #4] + 459:Generated_Source\PSoC4/UART_SPI_UART.c **** + 460:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_SetRxInterruptMode(UART_NO_INTR_SOURCES); + 232 .loc 1 460 0 + 233 000c 034B ldr r3, .L17 + 234 000e 0022 movs r2, #0 + 235 0010 1A60 str r2, [r3] + 461:Generated_Source\PSoC4/UART_SPI_UART.c **** + 462:Generated_Source\PSoC4/UART_SPI_UART.c **** return (intSource); + 236 .loc 1 462 0 + 237 0012 7B68 ldr r3, [r7, #4] + 463:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 238 .loc 1 463 0 + 239 0014 1800 movs r0, r3 + 240 0016 BD46 mov sp, r7 + 241 0018 02B0 add sp, sp, #8 + 242 @ sp needed + 243 001a 80BD pop {r7, pc} + 244 .L18: + 245 .align 2 + 246 .L17: + 247 001c C80F0640 .word 1074139080 + 248 .cfi_endproc + 249 .LFE4: + 250 .size UART_SpiUartDisableIntRx, .-UART_SpiUartDisableIntRx + 251 .section .text.UART_SpiUartDisableIntTx,"ax",%progbits + 252 .align 2 + 253 .global UART_SpiUartDisableIntTx + 254 .code 16 + 255 .thumb_func + 256 .type UART_SpiUartDisableIntTx, %function + 257 UART_SpiUartDisableIntTx: + 258 .LFB5: + 464:Generated_Source\PSoC4/UART_SPI_UART.c **** + 465:Generated_Source\PSoC4/UART_SPI_UART.c **** + 466:Generated_Source\PSoC4/UART_SPI_UART.c **** /******************************************************************************* + 467:Generated_Source\PSoC4/UART_SPI_UART.c **** * Function Name: UART_SpiUartDisableIntTx + 468:Generated_Source\PSoC4/UART_SPI_UART.c **** ****************************************************************************//** + 469:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 470:Generated_Source\PSoC4/UART_SPI_UART.c **** * Disables TX interrupt sources. + 471:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 472:Generated_Source\PSoC4/UART_SPI_UART.c **** * \return + 473:Generated_Source\PSoC4/UART_SPI_UART.c **** * Returns TX interrupt sources enabled before function call. + 474:Generated_Source\PSoC4/UART_SPI_UART.c **** * + 475:Generated_Source\PSoC4/UART_SPI_UART.c **** *******************************************************************************/ + 476:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 UART_SpiUartDisableIntTx(void) + 477:Generated_Source\PSoC4/UART_SPI_UART.c **** { + 259 .loc 1 477 0 + 260 .cfi_startproc + 261 @ args = 0, pretend = 0, frame = 8 + 262 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 14 + + + 263 0000 80B5 push {r7, lr} + 264 .cfi_def_cfa_offset 8 + 265 .cfi_offset 7, -8 + 266 .cfi_offset 14, -4 + 267 0002 82B0 sub sp, sp, #8 + 268 .cfi_def_cfa_offset 16 + 269 0004 00AF add r7, sp, #0 + 270 .cfi_def_cfa_register 7 + 478:Generated_Source\PSoC4/UART_SPI_UART.c **** uint32 intSourceMask; + 479:Generated_Source\PSoC4/UART_SPI_UART.c **** + 480:Generated_Source\PSoC4/UART_SPI_UART.c **** intSourceMask = UART_GetTxInterruptMode(); + 271 .loc 1 480 0 + 272 0006 054B ldr r3, .L21 + 273 0008 1B68 ldr r3, [r3] + 274 000a 7B60 str r3, [r7, #4] + 481:Generated_Source\PSoC4/UART_SPI_UART.c **** + 482:Generated_Source\PSoC4/UART_SPI_UART.c **** UART_SetTxInterruptMode(UART_NO_INTR_SOURCES); + 275 .loc 1 482 0 + 276 000c 034B ldr r3, .L21 + 277 000e 0022 movs r2, #0 + 278 0010 1A60 str r2, [r3] + 483:Generated_Source\PSoC4/UART_SPI_UART.c **** + 484:Generated_Source\PSoC4/UART_SPI_UART.c **** return (intSourceMask); + 279 .loc 1 484 0 + 280 0012 7B68 ldr r3, [r7, #4] + 485:Generated_Source\PSoC4/UART_SPI_UART.c **** } + 281 .loc 1 485 0 + 282 0014 1800 movs r0, r3 + 283 0016 BD46 mov sp, r7 + 284 0018 02B0 add sp, sp, #8 + 285 @ sp needed + 286 001a 80BD pop {r7, pc} + 287 .L22: + 288 .align 2 + 289 .L21: + 290 001c 880F0640 .word 1074139016 + 291 .cfi_endproc + 292 .LFE5: + 293 .size UART_SpiUartDisableIntTx, .-UART_SpiUartDisableIntTx + 294 .text + 295 .Letext0: + 296 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 297 .section .debug_info,"",%progbits + 298 .Ldebug_info0: + 299 0000 B3010000 .4byte 0x1b3 + 300 0004 0400 .2byte 0x4 + 301 0006 00000000 .4byte .Ldebug_abbrev0 + 302 000a 04 .byte 0x4 + 303 000b 01 .uleb128 0x1 + 304 000c E3000000 .4byte .LASF28 + 305 0010 0C .byte 0xc + 306 0011 46020000 .4byte .LASF29 + 307 0015 4C000000 .4byte .LASF30 + 308 0019 00000000 .4byte .Ldebug_ranges0+0 + 309 001d 00000000 .4byte 0 + 310 0021 00000000 .4byte .Ldebug_line0 + 311 0025 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 15 + + + 312 0026 01 .byte 0x1 + 313 0027 06 .byte 0x6 + 314 0028 87020000 .4byte .LASF0 + 315 002c 02 .uleb128 0x2 + 316 002d 01 .byte 0x1 + 317 002e 08 .byte 0x8 + 318 002f 77010000 .4byte .LASF1 + 319 0033 02 .uleb128 0x2 + 320 0034 02 .byte 0x2 + 321 0035 05 .byte 0x5 + 322 0036 3C020000 .4byte .LASF2 + 323 003a 02 .uleb128 0x2 + 324 003b 02 .byte 0x2 + 325 003c 07 .byte 0x7 + 326 003d 13000000 .4byte .LASF3 + 327 0041 02 .uleb128 0x2 + 328 0042 04 .byte 0x4 + 329 0043 05 .byte 0x5 + 330 0044 6D020000 .4byte .LASF4 + 331 0048 02 .uleb128 0x2 + 332 0049 04 .byte 0x4 + 333 004a 07 .byte 0x7 + 334 004b CB000000 .4byte .LASF5 + 335 004f 02 .uleb128 0x2 + 336 0050 08 .byte 0x8 + 337 0051 05 .byte 0x5 + 338 0052 FA010000 .4byte .LASF6 + 339 0056 02 .uleb128 0x2 + 340 0057 08 .byte 0x8 + 341 0058 07 .byte 0x7 + 342 0059 DA010000 .4byte .LASF7 + 343 005d 03 .uleb128 0x3 + 344 005e 04 .byte 0x4 + 345 005f 05 .byte 0x5 + 346 0060 696E7400 .ascii "int\000" + 347 0064 02 .uleb128 0x2 + 348 0065 04 .byte 0x4 + 349 0066 07 .byte 0x7 + 350 0067 26000000 .4byte .LASF8 + 351 006b 04 .uleb128 0x4 + 352 006c DD000000 .4byte .LASF9 + 353 0070 02 .byte 0x2 + 354 0071 E401 .2byte 0x1e4 + 355 0073 2C000000 .4byte 0x2c + 356 0077 04 .uleb128 0x4 + 357 0078 8C010000 .4byte .LASF10 + 358 007c 02 .byte 0x2 + 359 007d E601 .2byte 0x1e6 + 360 007f 48000000 .4byte 0x48 + 361 0083 02 .uleb128 0x2 + 362 0084 04 .byte 0x4 + 363 0085 04 .byte 0x4 + 364 0086 A7000000 .4byte .LASF11 + 365 008a 02 .uleb128 0x2 + 366 008b 08 .byte 0x8 + 367 008c 04 .byte 0x4 + 368 008d 85010000 .4byte .LASF12 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 16 + + + 369 0091 02 .uleb128 0x2 + 370 0092 01 .byte 0x1 + 371 0093 08 .byte 0x8 + 372 0094 76020000 .4byte .LASF13 + 373 0098 04 .uleb128 0x4 + 374 0099 00000000 .4byte .LASF14 + 375 009d 02 .byte 0x2 + 376 009e 9002 .2byte 0x290 + 377 00a0 A4000000 .4byte 0xa4 + 378 00a4 05 .uleb128 0x5 + 379 00a5 77000000 .4byte 0x77 + 380 00a9 02 .uleb128 0x2 + 381 00aa 08 .byte 0x8 + 382 00ab 04 .byte 0x4 + 383 00ac 7B020000 .4byte .LASF15 + 384 00b0 02 .uleb128 0x2 + 385 00b1 04 .byte 0x4 + 386 00b2 07 .byte 0x7 + 387 00b3 F1010000 .4byte .LASF16 + 388 00b7 06 .uleb128 0x6 + 389 00b8 08020000 .4byte .LASF17 + 390 00bc 01 .byte 0x1 + 391 00bd 0101 .2byte 0x101 + 392 00bf 00000000 .4byte .LFB0 + 393 00c3 2C000000 .4byte .LFE0-.LFB0 + 394 00c7 01 .uleb128 0x1 + 395 00c8 9C .byte 0x9c + 396 00c9 DD000000 .4byte 0xdd + 397 00cd 07 .uleb128 0x7 + 398 00ce 0C000000 .4byte .LASF19 + 399 00d2 01 .byte 0x1 + 400 00d3 0101 .2byte 0x101 + 401 00d5 77000000 .4byte 0x77 + 402 00d9 02 .uleb128 0x2 + 403 00da 91 .byte 0x91 + 404 00db 74 .sleb128 -12 + 405 00dc 00 .byte 0 + 406 00dd 08 .uleb128 0x8 + 407 00de AD010000 .4byte .LASF18 + 408 00e2 01 .byte 0x1 + 409 00e3 5401 .2byte 0x154 + 410 00e5 00000000 .4byte .LFB1 + 411 00e9 34000000 .4byte .LFE1-.LFB1 + 412 00ed 01 .uleb128 0x1 + 413 00ee 9C .byte 0x9c + 414 00ef 1F010000 .4byte 0x11f + 415 00f3 07 .uleb128 0x7 + 416 00f4 71010000 .4byte .LASF20 + 417 00f8 01 .byte 0x1 + 418 00f9 5401 .2byte 0x154 + 419 00fb 1F010000 .4byte 0x11f + 420 00ff 02 .uleb128 0x2 + 421 0100 91 .byte 0x91 + 422 0101 6C .sleb128 -20 + 423 0102 07 .uleb128 0x7 + 424 0103 06000000 .4byte .LASF21 + 425 0107 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 17 + + + 426 0108 5401 .2byte 0x154 + 427 010a 77000000 .4byte 0x77 + 428 010e 02 .uleb128 0x2 + 429 010f 91 .byte 0x91 + 430 0110 68 .sleb128 -24 + 431 0111 09 .uleb128 0x9 + 432 0112 6900 .ascii "i\000" + 433 0114 01 .byte 0x1 + 434 0115 5601 .2byte 0x156 + 435 0117 77000000 .4byte 0x77 + 436 011b 02 .uleb128 0x2 + 437 011c 91 .byte 0x91 + 438 011d 74 .sleb128 -12 + 439 011e 00 .byte 0 + 440 011f 0A .uleb128 0xa + 441 0120 04 .byte 0x4 + 442 0121 25010000 .4byte 0x125 + 443 0125 0B .uleb128 0xb + 444 0126 6B000000 .4byte 0x6b + 445 012a 0C .uleb128 0xc + 446 012b 20020000 .4byte .LASF23 + 447 012f 01 .byte 0x1 + 448 0130 7501 .2byte 0x175 + 449 0132 77000000 .4byte 0x77 + 450 0136 00000000 .4byte .LFB2 + 451 013a 20000000 .4byte .LFE2-.LFB2 + 452 013e 01 .uleb128 0x1 + 453 013f 9C .byte 0x9c + 454 0140 54010000 .4byte 0x154 + 455 0144 0D .uleb128 0xd + 456 0145 C6000000 .4byte .LASF22 + 457 0149 01 .byte 0x1 + 458 014a 7701 .2byte 0x177 + 459 014c 77000000 .4byte 0x77 + 460 0150 02 .uleb128 0x2 + 461 0151 91 .byte 0x91 + 462 0152 74 .sleb128 -12 + 463 0153 00 .byte 0 + 464 0154 0E .uleb128 0xe + 465 0155 93010000 .4byte .LASF31 + 466 0159 01 .byte 0x1 + 467 015a A101 .2byte 0x1a1 + 468 015c 00000000 .4byte .LFB3 + 469 0160 2C000000 .4byte .LFE3-.LFB3 + 470 0164 01 .uleb128 0x1 + 471 0165 9C .byte 0x9c + 472 0166 0C .uleb128 0xc + 473 0167 33000000 .4byte .LASF24 + 474 016b 01 .byte 0x1 + 475 016c C601 .2byte 0x1c6 + 476 016e 77000000 .4byte 0x77 + 477 0172 00000000 .4byte .LFB4 + 478 0176 20000000 .4byte .LFE4-.LFB4 + 479 017a 01 .uleb128 0x1 + 480 017b 9C .byte 0x9c + 481 017c 90010000 .4byte 0x190 + 482 0180 0D .uleb128 0xd + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 18 + + + 483 0181 D0010000 .4byte .LASF25 + 484 0185 01 .byte 0x1 + 485 0186 C801 .2byte 0x1c8 + 486 0188 77000000 .4byte 0x77 + 487 018c 02 .uleb128 0x2 + 488 018d 91 .byte 0x91 + 489 018e 74 .sleb128 -12 + 490 018f 00 .byte 0 + 491 0190 0F .uleb128 0xf + 492 0191 AD000000 .4byte .LASF26 + 493 0195 01 .byte 0x1 + 494 0196 DC01 .2byte 0x1dc + 495 0198 77000000 .4byte 0x77 + 496 019c 00000000 .4byte .LFB5 + 497 01a0 20000000 .4byte .LFE5-.LFB5 + 498 01a4 01 .uleb128 0x1 + 499 01a5 9C .byte 0x9c + 500 01a6 0D .uleb128 0xd + 501 01a7 C2010000 .4byte .LASF27 + 502 01ab 01 .byte 0x1 + 503 01ac DE01 .2byte 0x1de + 504 01ae 77000000 .4byte 0x77 + 505 01b2 02 .uleb128 0x2 + 506 01b3 91 .byte 0x91 + 507 01b4 74 .sleb128 -12 + 508 01b5 00 .byte 0 + 509 01b6 00 .byte 0 + 510 .section .debug_abbrev,"",%progbits + 511 .Ldebug_abbrev0: + 512 0000 01 .uleb128 0x1 + 513 0001 11 .uleb128 0x11 + 514 0002 01 .byte 0x1 + 515 0003 25 .uleb128 0x25 + 516 0004 0E .uleb128 0xe + 517 0005 13 .uleb128 0x13 + 518 0006 0B .uleb128 0xb + 519 0007 03 .uleb128 0x3 + 520 0008 0E .uleb128 0xe + 521 0009 1B .uleb128 0x1b + 522 000a 0E .uleb128 0xe + 523 000b 55 .uleb128 0x55 + 524 000c 17 .uleb128 0x17 + 525 000d 11 .uleb128 0x11 + 526 000e 01 .uleb128 0x1 + 527 000f 10 .uleb128 0x10 + 528 0010 17 .uleb128 0x17 + 529 0011 00 .byte 0 + 530 0012 00 .byte 0 + 531 0013 02 .uleb128 0x2 + 532 0014 24 .uleb128 0x24 + 533 0015 00 .byte 0 + 534 0016 0B .uleb128 0xb + 535 0017 0B .uleb128 0xb + 536 0018 3E .uleb128 0x3e + 537 0019 0B .uleb128 0xb + 538 001a 03 .uleb128 0x3 + 539 001b 0E .uleb128 0xe + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 19 + + + 540 001c 00 .byte 0 + 541 001d 00 .byte 0 + 542 001e 03 .uleb128 0x3 + 543 001f 24 .uleb128 0x24 + 544 0020 00 .byte 0 + 545 0021 0B .uleb128 0xb + 546 0022 0B .uleb128 0xb + 547 0023 3E .uleb128 0x3e + 548 0024 0B .uleb128 0xb + 549 0025 03 .uleb128 0x3 + 550 0026 08 .uleb128 0x8 + 551 0027 00 .byte 0 + 552 0028 00 .byte 0 + 553 0029 04 .uleb128 0x4 + 554 002a 16 .uleb128 0x16 + 555 002b 00 .byte 0 + 556 002c 03 .uleb128 0x3 + 557 002d 0E .uleb128 0xe + 558 002e 3A .uleb128 0x3a + 559 002f 0B .uleb128 0xb + 560 0030 3B .uleb128 0x3b + 561 0031 05 .uleb128 0x5 + 562 0032 49 .uleb128 0x49 + 563 0033 13 .uleb128 0x13 + 564 0034 00 .byte 0 + 565 0035 00 .byte 0 + 566 0036 05 .uleb128 0x5 + 567 0037 35 .uleb128 0x35 + 568 0038 00 .byte 0 + 569 0039 49 .uleb128 0x49 + 570 003a 13 .uleb128 0x13 + 571 003b 00 .byte 0 + 572 003c 00 .byte 0 + 573 003d 06 .uleb128 0x6 + 574 003e 2E .uleb128 0x2e + 575 003f 01 .byte 0x1 + 576 0040 3F .uleb128 0x3f + 577 0041 19 .uleb128 0x19 + 578 0042 03 .uleb128 0x3 + 579 0043 0E .uleb128 0xe + 580 0044 3A .uleb128 0x3a + 581 0045 0B .uleb128 0xb + 582 0046 3B .uleb128 0x3b + 583 0047 05 .uleb128 0x5 + 584 0048 27 .uleb128 0x27 + 585 0049 19 .uleb128 0x19 + 586 004a 11 .uleb128 0x11 + 587 004b 01 .uleb128 0x1 + 588 004c 12 .uleb128 0x12 + 589 004d 06 .uleb128 0x6 + 590 004e 40 .uleb128 0x40 + 591 004f 18 .uleb128 0x18 + 592 0050 9742 .uleb128 0x2117 + 593 0052 19 .uleb128 0x19 + 594 0053 01 .uleb128 0x1 + 595 0054 13 .uleb128 0x13 + 596 0055 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 20 + + + 597 0056 00 .byte 0 + 598 0057 07 .uleb128 0x7 + 599 0058 05 .uleb128 0x5 + 600 0059 00 .byte 0 + 601 005a 03 .uleb128 0x3 + 602 005b 0E .uleb128 0xe + 603 005c 3A .uleb128 0x3a + 604 005d 0B .uleb128 0xb + 605 005e 3B .uleb128 0x3b + 606 005f 05 .uleb128 0x5 + 607 0060 49 .uleb128 0x49 + 608 0061 13 .uleb128 0x13 + 609 0062 02 .uleb128 0x2 + 610 0063 18 .uleb128 0x18 + 611 0064 00 .byte 0 + 612 0065 00 .byte 0 + 613 0066 08 .uleb128 0x8 + 614 0067 2E .uleb128 0x2e + 615 0068 01 .byte 0x1 + 616 0069 3F .uleb128 0x3f + 617 006a 19 .uleb128 0x19 + 618 006b 03 .uleb128 0x3 + 619 006c 0E .uleb128 0xe + 620 006d 3A .uleb128 0x3a + 621 006e 0B .uleb128 0xb + 622 006f 3B .uleb128 0x3b + 623 0070 05 .uleb128 0x5 + 624 0071 27 .uleb128 0x27 + 625 0072 19 .uleb128 0x19 + 626 0073 11 .uleb128 0x11 + 627 0074 01 .uleb128 0x1 + 628 0075 12 .uleb128 0x12 + 629 0076 06 .uleb128 0x6 + 630 0077 40 .uleb128 0x40 + 631 0078 18 .uleb128 0x18 + 632 0079 9642 .uleb128 0x2116 + 633 007b 19 .uleb128 0x19 + 634 007c 01 .uleb128 0x1 + 635 007d 13 .uleb128 0x13 + 636 007e 00 .byte 0 + 637 007f 00 .byte 0 + 638 0080 09 .uleb128 0x9 + 639 0081 34 .uleb128 0x34 + 640 0082 00 .byte 0 + 641 0083 03 .uleb128 0x3 + 642 0084 08 .uleb128 0x8 + 643 0085 3A .uleb128 0x3a + 644 0086 0B .uleb128 0xb + 645 0087 3B .uleb128 0x3b + 646 0088 05 .uleb128 0x5 + 647 0089 49 .uleb128 0x49 + 648 008a 13 .uleb128 0x13 + 649 008b 02 .uleb128 0x2 + 650 008c 18 .uleb128 0x18 + 651 008d 00 .byte 0 + 652 008e 00 .byte 0 + 653 008f 0A .uleb128 0xa + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 21 + + + 654 0090 0F .uleb128 0xf + 655 0091 00 .byte 0 + 656 0092 0B .uleb128 0xb + 657 0093 0B .uleb128 0xb + 658 0094 49 .uleb128 0x49 + 659 0095 13 .uleb128 0x13 + 660 0096 00 .byte 0 + 661 0097 00 .byte 0 + 662 0098 0B .uleb128 0xb + 663 0099 26 .uleb128 0x26 + 664 009a 00 .byte 0 + 665 009b 49 .uleb128 0x49 + 666 009c 13 .uleb128 0x13 + 667 009d 00 .byte 0 + 668 009e 00 .byte 0 + 669 009f 0C .uleb128 0xc + 670 00a0 2E .uleb128 0x2e + 671 00a1 01 .byte 0x1 + 672 00a2 3F .uleb128 0x3f + 673 00a3 19 .uleb128 0x19 + 674 00a4 03 .uleb128 0x3 + 675 00a5 0E .uleb128 0xe + 676 00a6 3A .uleb128 0x3a + 677 00a7 0B .uleb128 0xb + 678 00a8 3B .uleb128 0x3b + 679 00a9 05 .uleb128 0x5 + 680 00aa 27 .uleb128 0x27 + 681 00ab 19 .uleb128 0x19 + 682 00ac 49 .uleb128 0x49 + 683 00ad 13 .uleb128 0x13 + 684 00ae 11 .uleb128 0x11 + 685 00af 01 .uleb128 0x1 + 686 00b0 12 .uleb128 0x12 + 687 00b1 06 .uleb128 0x6 + 688 00b2 40 .uleb128 0x40 + 689 00b3 18 .uleb128 0x18 + 690 00b4 9742 .uleb128 0x2117 + 691 00b6 19 .uleb128 0x19 + 692 00b7 01 .uleb128 0x1 + 693 00b8 13 .uleb128 0x13 + 694 00b9 00 .byte 0 + 695 00ba 00 .byte 0 + 696 00bb 0D .uleb128 0xd + 697 00bc 34 .uleb128 0x34 + 698 00bd 00 .byte 0 + 699 00be 03 .uleb128 0x3 + 700 00bf 0E .uleb128 0xe + 701 00c0 3A .uleb128 0x3a + 702 00c1 0B .uleb128 0xb + 703 00c2 3B .uleb128 0x3b + 704 00c3 05 .uleb128 0x5 + 705 00c4 49 .uleb128 0x49 + 706 00c5 13 .uleb128 0x13 + 707 00c6 02 .uleb128 0x2 + 708 00c7 18 .uleb128 0x18 + 709 00c8 00 .byte 0 + 710 00c9 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 22 + + + 711 00ca 0E .uleb128 0xe + 712 00cb 2E .uleb128 0x2e + 713 00cc 00 .byte 0 + 714 00cd 3F .uleb128 0x3f + 715 00ce 19 .uleb128 0x19 + 716 00cf 03 .uleb128 0x3 + 717 00d0 0E .uleb128 0xe + 718 00d1 3A .uleb128 0x3a + 719 00d2 0B .uleb128 0xb + 720 00d3 3B .uleb128 0x3b + 721 00d4 05 .uleb128 0x5 + 722 00d5 27 .uleb128 0x27 + 723 00d6 19 .uleb128 0x19 + 724 00d7 11 .uleb128 0x11 + 725 00d8 01 .uleb128 0x1 + 726 00d9 12 .uleb128 0x12 + 727 00da 06 .uleb128 0x6 + 728 00db 40 .uleb128 0x40 + 729 00dc 18 .uleb128 0x18 + 730 00dd 9742 .uleb128 0x2117 + 731 00df 19 .uleb128 0x19 + 732 00e0 00 .byte 0 + 733 00e1 00 .byte 0 + 734 00e2 0F .uleb128 0xf + 735 00e3 2E .uleb128 0x2e + 736 00e4 01 .byte 0x1 + 737 00e5 3F .uleb128 0x3f + 738 00e6 19 .uleb128 0x19 + 739 00e7 03 .uleb128 0x3 + 740 00e8 0E .uleb128 0xe + 741 00e9 3A .uleb128 0x3a + 742 00ea 0B .uleb128 0xb + 743 00eb 3B .uleb128 0x3b + 744 00ec 05 .uleb128 0x5 + 745 00ed 27 .uleb128 0x27 + 746 00ee 19 .uleb128 0x19 + 747 00ef 49 .uleb128 0x49 + 748 00f0 13 .uleb128 0x13 + 749 00f1 11 .uleb128 0x11 + 750 00f2 01 .uleb128 0x1 + 751 00f3 12 .uleb128 0x12 + 752 00f4 06 .uleb128 0x6 + 753 00f5 40 .uleb128 0x40 + 754 00f6 18 .uleb128 0x18 + 755 00f7 9742 .uleb128 0x2117 + 756 00f9 19 .uleb128 0x19 + 757 00fa 00 .byte 0 + 758 00fb 00 .byte 0 + 759 00fc 00 .byte 0 + 760 .section .debug_aranges,"",%progbits + 761 0000 44000000 .4byte 0x44 + 762 0004 0200 .2byte 0x2 + 763 0006 00000000 .4byte .Ldebug_info0 + 764 000a 04 .byte 0x4 + 765 000b 00 .byte 0 + 766 000c 0000 .2byte 0 + 767 000e 0000 .2byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 23 + + + 768 0010 00000000 .4byte .LFB0 + 769 0014 2C000000 .4byte .LFE0-.LFB0 + 770 0018 00000000 .4byte .LFB1 + 771 001c 34000000 .4byte .LFE1-.LFB1 + 772 0020 00000000 .4byte .LFB2 + 773 0024 20000000 .4byte .LFE2-.LFB2 + 774 0028 00000000 .4byte .LFB3 + 775 002c 2C000000 .4byte .LFE3-.LFB3 + 776 0030 00000000 .4byte .LFB4 + 777 0034 20000000 .4byte .LFE4-.LFB4 + 778 0038 00000000 .4byte .LFB5 + 779 003c 20000000 .4byte .LFE5-.LFB5 + 780 0040 00000000 .4byte 0 + 781 0044 00000000 .4byte 0 + 782 .section .debug_ranges,"",%progbits + 783 .Ldebug_ranges0: + 784 0000 00000000 .4byte .LFB0 + 785 0004 2C000000 .4byte .LFE0 + 786 0008 00000000 .4byte .LFB1 + 787 000c 34000000 .4byte .LFE1 + 788 0010 00000000 .4byte .LFB2 + 789 0014 20000000 .4byte .LFE2 + 790 0018 00000000 .4byte .LFB3 + 791 001c 2C000000 .4byte .LFE3 + 792 0020 00000000 .4byte .LFB4 + 793 0024 20000000 .4byte .LFE4 + 794 0028 00000000 .4byte .LFB5 + 795 002c 20000000 .4byte .LFE5 + 796 0030 00000000 .4byte 0 + 797 0034 00000000 .4byte 0 + 798 .section .debug_line,"",%progbits + 799 .Ldebug_line0: + 800 0000 E0000000 .section .debug_str,"MS",%progbits,1 + 800 02004A00 + 800 00000201 + 800 FB0E0D00 + 800 01010101 + 801 .LASF14: + 802 0000 72656733 .ascii "reg32\000" + 802 3200 + 803 .LASF21: + 804 0006 636F756E .ascii "count\000" + 804 7400 + 805 .LASF19: + 806 000c 74784461 .ascii "txData\000" + 806 746100 + 807 .LASF3: + 808 0013 73686F72 .ascii "short unsigned int\000" + 808 7420756E + 808 7369676E + 808 65642069 + 808 6E7400 + 809 .LASF8: + 810 0026 756E7369 .ascii "unsigned int\000" + 810 676E6564 + 810 20696E74 + 810 00 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 24 + + + 811 .LASF24: + 812 0033 55415254 .ascii "UART_SpiUartDisableIntRx\000" + 812 5F537069 + 812 55617274 + 812 44697361 + 812 626C6549 + 813 .LASF30: + 814 004c 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 814 73657273 + 814 5C6A6167 + 814 756D6965 + 814 6C5C446F + 815 007a 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 815 50536F43 + 815 2D313031 + 815 5C547261 + 815 696E696E + 816 .LASF11: + 817 00a7 666C6F61 .ascii "float\000" + 817 7400 + 818 .LASF26: + 819 00ad 55415254 .ascii "UART_SpiUartDisableIntTx\000" + 819 5F537069 + 819 55617274 + 819 44697361 + 819 626C6549 + 820 .LASF22: + 821 00c6 73697A65 .ascii "size\000" + 821 00 + 822 .LASF5: + 823 00cb 6C6F6E67 .ascii "long unsigned int\000" + 823 20756E73 + 823 69676E65 + 823 6420696E + 823 7400 + 824 .LASF9: + 825 00dd 75696E74 .ascii "uint8\000" + 825 3800 + 826 .LASF28: + 827 00e3 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 827 43313120 + 827 352E342E + 827 31203230 + 827 31363036 + 828 0116 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 828 20726576 + 828 6973696F + 828 6E203233 + 828 37373135 + 829 0149 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 829 66756E63 + 829 74696F6E + 829 2D736563 + 829 74696F6E + 830 .LASF20: + 831 0171 77724275 .ascii "wrBuf\000" + 831 6600 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 25 + + + 832 .LASF1: + 833 0177 756E7369 .ascii "unsigned char\000" + 833 676E6564 + 833 20636861 + 833 7200 + 834 .LASF12: + 835 0185 646F7562 .ascii "double\000" + 835 6C6500 + 836 .LASF10: + 837 018c 75696E74 .ascii "uint32\000" + 837 333200 + 838 .LASF31: + 839 0193 55415254 .ascii "UART_SpiUartClearTxBuffer\000" + 839 5F537069 + 839 55617274 + 839 436C6561 + 839 72547842 + 840 .LASF18: + 841 01ad 55415254 .ascii "UART_SpiUartPutArray\000" + 841 5F537069 + 841 55617274 + 841 50757441 + 841 72726179 + 842 .LASF27: + 843 01c2 696E7453 .ascii "intSourceMask\000" + 843 6F757263 + 843 654D6173 + 843 6B00 + 844 .LASF25: + 845 01d0 696E7453 .ascii "intSource\000" + 845 6F757263 + 845 6500 + 846 .LASF7: + 847 01da 6C6F6E67 .ascii "long long unsigned int\000" + 847 206C6F6E + 847 6720756E + 847 7369676E + 847 65642069 + 848 .LASF16: + 849 01f1 73697A65 .ascii "sizetype\000" + 849 74797065 + 849 00 + 850 .LASF6: + 851 01fa 6C6F6E67 .ascii "long long int\000" + 851 206C6F6E + 851 6720696E + 851 7400 + 852 .LASF17: + 853 0208 55415254 .ascii "UART_SpiUartWriteTxData\000" + 853 5F537069 + 853 55617274 + 853 57726974 + 853 65547844 + 854 .LASF23: + 855 0220 55415254 .ascii "UART_SpiUartGetTxBufferSize\000" + 855 5F537069 + 855 55617274 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccEcHPIg.s page 26 + + + 855 47657454 + 855 78427566 + 856 .LASF2: + 857 023c 73686F72 .ascii "short int\000" + 857 7420696E + 857 7400 + 858 .LASF29: + 859 0246 47656E65 .ascii "Generated_Source\\PSoC4\\UART_SPI_UART.c\000" + 859 72617465 + 859 645F536F + 859 75726365 + 859 5C50536F + 860 .LASF4: + 861 026d 6C6F6E67 .ascii "long int\000" + 861 20696E74 + 861 00 + 862 .LASF13: + 863 0276 63686172 .ascii "char\000" + 863 00 + 864 .LASF15: + 865 027b 6C6F6E67 .ascii "long double\000" + 865 20646F75 + 865 626C6500 + 866 .LASF0: + 867 0287 7369676E .ascii "signed char\000" + 867 65642063 + 867 68617200 + 868 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_SPI_UART.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_SPI_UART.o new file mode 100644 index 0000000000000000000000000000000000000000..21b99b6691b8b620259ae0a53b4bee1f3f2b1733 GIT binary patch literal 5268 zcmbtYYiJzT6~1?7UwYeeVoP$Gj#DL3h05`Mo#vb~C7cbhrpDOlCgF*W3K(J!uzt33_1jn2Tg%z& z)3LejrJjejj3*xd=vHLzTxkHdYt!15m1_wtHa?DT2}}t z%($5awy-l$Z#QOQ8GWYrH`BESAvtFO3yen7PTk*O0k>1kE zj#;gJav&R-)1m3J?c;t6R<1?BTVMZVy_xHLR-a=J4Fs~i+e5jiFI3k?|M%d38-o!M zeUI=z13RZR#-0_1=8wi>ufVMF#2L^vEjmV;7T*Gj7Kv6#i^Ok|mWX~#ltlcG06h{d z*F5q)0$=1$MEH>Jr1B4l^;dqFOp(az1c}IZ$;cBgBA;lJc0v0&Jkc}0`@CPzU9e&a zl;ylqKE6uHDRsvq zqK3|3;Ov%`I=T=lTSTGVDRz&>FxK-aDKI=!_%Ig`f8|n%#+k(5$Nub)uIvUW5JUVn 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z;2dWwVlj?=Y`pJ$J^ou9m$n@Ps@MIPi81SY7MiQ*RnxzVAH-+ie3|pVf*Y^L-_?!* zrEk!#FfnF*JJ6Q1>u0nJOpI9{*Tw9*zhWU?hu7sQx9i>ow_`x*ceE#%7_+_vnmNBW z+hY*lS|>D9Zd_-KHtt7!00nK$#=VCQ?D3)P--Kve0pvI~J}35Du>K8+f6By|jbpUm gnq3bt=sVz}Xnf}QeOJ+VPiE(P0S-Qc*6e(L0hU=JEC2ui literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_UART.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_UART.lst new file mode 100644 index 0000000..467f6e6 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_UART.lst @@ -0,0 +1,2199 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "UART_UART.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.UART_UartInit,"ax",%progbits + 20 .align 2 + 21 .global UART_UartInit + 22 .code 16 + 23 .thumb_func + 24 .type UART_UartInit, %function + 25 UART_UartInit: + 26 .LFB0: + 27 .file 1 "Generated_Source\\PSoC4\\UART_UART.c" + 1:Generated_Source\PSoC4/UART_UART.c **** /***************************************************************************//** + 2:Generated_Source\PSoC4/UART_UART.c **** * \file UART_UART.c + 3:Generated_Source\PSoC4/UART_UART.c **** * \version 4.0 + 4:Generated_Source\PSoC4/UART_UART.c **** * + 5:Generated_Source\PSoC4/UART_UART.c **** * \brief + 6:Generated_Source\PSoC4/UART_UART.c **** * This file provides the source code to the API for the SCB Component in + 7:Generated_Source\PSoC4/UART_UART.c **** * UART mode. + 8:Generated_Source\PSoC4/UART_UART.c **** * + 9:Generated_Source\PSoC4/UART_UART.c **** * Note: + 10:Generated_Source\PSoC4/UART_UART.c **** * + 11:Generated_Source\PSoC4/UART_UART.c **** ******************************************************************************* + 12:Generated_Source\PSoC4/UART_UART.c **** * \copyright + 13:Generated_Source\PSoC4/UART_UART.c **** * Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. + 14:Generated_Source\PSoC4/UART_UART.c **** * You may use this file only in accordance with the license, terms, conditions, + 15:Generated_Source\PSoC4/UART_UART.c **** * disclaimers, and limitations in the end user license agreement accompanying + 16:Generated_Source\PSoC4/UART_UART.c **** * the software package with which this file was provided. + 17:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 18:Generated_Source\PSoC4/UART_UART.c **** + 19:Generated_Source\PSoC4/UART_UART.c **** #include "UART_PVT.h" + 20:Generated_Source\PSoC4/UART_UART.c **** #include "UART_SPI_UART_PVT.h" + 21:Generated_Source\PSoC4/UART_UART.c **** #include "cyapicallbacks.h" + 22:Generated_Source\PSoC4/UART_UART.c **** + 23:Generated_Source\PSoC4/UART_UART.c **** #if (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) + 24:Generated_Source\PSoC4/UART_UART.c **** /** + 25:Generated_Source\PSoC4/UART_UART.c **** * \addtogroup group_globals + 26:Generated_Source\PSoC4/UART_UART.c **** * \{ + 27:Generated_Source\PSoC4/UART_UART.c **** */ + 28:Generated_Source\PSoC4/UART_UART.c **** /** This global variable determines whether to enable Skip Start + 29:Generated_Source\PSoC4/UART_UART.c **** * functionality when UART_Sleep() function is called: + 30:Generated_Source\PSoC4/UART_UART.c **** * 0 – disable, other values – enable. Default value is 1. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 2 + + + 31:Generated_Source\PSoC4/UART_UART.c **** * It is only available when Enable wakeup from Deep Sleep Mode is enabled. + 32:Generated_Source\PSoC4/UART_UART.c **** */ + 33:Generated_Source\PSoC4/UART_UART.c **** uint8 UART_skipStart = 1u; + 34:Generated_Source\PSoC4/UART_UART.c **** /** \} globals */ + 35:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_WAKE_ENABLE_CONST && UART_UART_RX_WAKEUP_IRQ) */ + 36:Generated_Source\PSoC4/UART_UART.c **** + 37:Generated_Source\PSoC4/UART_UART.c **** #if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + 38:Generated_Source\PSoC4/UART_UART.c **** + 39:Generated_Source\PSoC4/UART_UART.c **** /*************************************** + 40:Generated_Source\PSoC4/UART_UART.c **** * Configuration Structure Initialization + 41:Generated_Source\PSoC4/UART_UART.c **** ***************************************/ + 42:Generated_Source\PSoC4/UART_UART.c **** + 43:Generated_Source\PSoC4/UART_UART.c **** const UART_UART_INIT_STRUCT UART_configUart = + 44:Generated_Source\PSoC4/UART_UART.c **** { + 45:Generated_Source\PSoC4/UART_UART.c **** UART_UART_SUB_MODE, + 46:Generated_Source\PSoC4/UART_UART.c **** UART_UART_DIRECTION, + 47:Generated_Source\PSoC4/UART_UART.c **** UART_UART_DATA_BITS_NUM, + 48:Generated_Source\PSoC4/UART_UART.c **** UART_UART_PARITY_TYPE, + 49:Generated_Source\PSoC4/UART_UART.c **** UART_UART_STOP_BITS_NUM, + 50:Generated_Source\PSoC4/UART_UART.c **** UART_UART_OVS_FACTOR, + 51:Generated_Source\PSoC4/UART_UART.c **** UART_UART_IRDA_LOW_POWER, + 52:Generated_Source\PSoC4/UART_UART.c **** UART_UART_MEDIAN_FILTER_ENABLE, + 53:Generated_Source\PSoC4/UART_UART.c **** UART_UART_RETRY_ON_NACK, + 54:Generated_Source\PSoC4/UART_UART.c **** UART_UART_IRDA_POLARITY, + 55:Generated_Source\PSoC4/UART_UART.c **** UART_UART_DROP_ON_PARITY_ERR, + 56:Generated_Source\PSoC4/UART_UART.c **** UART_UART_DROP_ON_FRAME_ERR, + 57:Generated_Source\PSoC4/UART_UART.c **** UART_UART_WAKE_ENABLE, + 58:Generated_Source\PSoC4/UART_UART.c **** 0u, + 59:Generated_Source\PSoC4/UART_UART.c **** NULL, + 60:Generated_Source\PSoC4/UART_UART.c **** 0u, + 61:Generated_Source\PSoC4/UART_UART.c **** NULL, + 62:Generated_Source\PSoC4/UART_UART.c **** UART_UART_MP_MODE_ENABLE, + 63:Generated_Source\PSoC4/UART_UART.c **** UART_UART_MP_ACCEPT_ADDRESS, + 64:Generated_Source\PSoC4/UART_UART.c **** UART_UART_MP_RX_ADDRESS, + 65:Generated_Source\PSoC4/UART_UART.c **** UART_UART_MP_RX_ADDRESS_MASK, + 66:Generated_Source\PSoC4/UART_UART.c **** (uint32) UART_SCB_IRQ_INTERNAL, + 67:Generated_Source\PSoC4/UART_UART.c **** UART_UART_INTR_RX_MASK, + 68:Generated_Source\PSoC4/UART_UART.c **** UART_UART_RX_TRIGGER_LEVEL, + 69:Generated_Source\PSoC4/UART_UART.c **** UART_UART_INTR_TX_MASK, + 70:Generated_Source\PSoC4/UART_UART.c **** UART_UART_TX_TRIGGER_LEVEL, + 71:Generated_Source\PSoC4/UART_UART.c **** (uint8) UART_UART_BYTE_MODE_ENABLE, + 72:Generated_Source\PSoC4/UART_UART.c **** (uint8) UART_UART_CTS_ENABLE, + 73:Generated_Source\PSoC4/UART_UART.c **** (uint8) UART_UART_CTS_POLARITY, + 74:Generated_Source\PSoC4/UART_UART.c **** (uint8) UART_UART_RTS_POLARITY, + 75:Generated_Source\PSoC4/UART_UART.c **** (uint8) UART_UART_RTS_FIFO_LEVEL, + 76:Generated_Source\PSoC4/UART_UART.c **** (uint8) UART_UART_RX_BREAK_WIDTH + 77:Generated_Source\PSoC4/UART_UART.c **** }; + 78:Generated_Source\PSoC4/UART_UART.c **** + 79:Generated_Source\PSoC4/UART_UART.c **** + 80:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 81:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartInit + 82:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 83:Generated_Source\PSoC4/UART_UART.c **** * + 84:Generated_Source\PSoC4/UART_UART.c **** * Configures the UART for UART operation. + 85:Generated_Source\PSoC4/UART_UART.c **** * + 86:Generated_Source\PSoC4/UART_UART.c **** * This function is intended specifically to be used when the UART + 87:Generated_Source\PSoC4/UART_UART.c **** * configuration is set to “Unconfigured UART” in the customizer. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 3 + + + 88:Generated_Source\PSoC4/UART_UART.c **** * After initializing the UART in UART mode using this function, + 89:Generated_Source\PSoC4/UART_UART.c **** * the component can be enabled using the UART_Start() or + 90:Generated_Source\PSoC4/UART_UART.c **** * UART_Enable() function. + 91:Generated_Source\PSoC4/UART_UART.c **** * This function uses a pointer to a structure that provides the configuration + 92:Generated_Source\PSoC4/UART_UART.c **** * settings. This structure contains the same information that would otherwise + 93:Generated_Source\PSoC4/UART_UART.c **** * be provided by the customizer settings. + 94:Generated_Source\PSoC4/UART_UART.c **** * + 95:Generated_Source\PSoC4/UART_UART.c **** * \param config: pointer to a structure that contains the following list of + 96:Generated_Source\PSoC4/UART_UART.c **** * fields. These fields match the selections available in the customizer. + 97:Generated_Source\PSoC4/UART_UART.c **** * Refer to the customizer for further description of the settings. + 98:Generated_Source\PSoC4/UART_UART.c **** * + 99:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 100:Generated_Source\PSoC4/UART_UART.c **** void UART_UartInit(const UART_UART_INIT_STRUCT *config) + 101:Generated_Source\PSoC4/UART_UART.c **** { + 102:Generated_Source\PSoC4/UART_UART.c **** uint32 pinsConfig; + 103:Generated_Source\PSoC4/UART_UART.c **** + 104:Generated_Source\PSoC4/UART_UART.c **** if (NULL == config) + 105:Generated_Source\PSoC4/UART_UART.c **** { + 106:Generated_Source\PSoC4/UART_UART.c **** CYASSERT(0u != 0u); /* Halt execution due to bad function parameter */ + 107:Generated_Source\PSoC4/UART_UART.c **** } + 108:Generated_Source\PSoC4/UART_UART.c **** else + 109:Generated_Source\PSoC4/UART_UART.c **** { + 110:Generated_Source\PSoC4/UART_UART.c **** /* Get direction to configure UART pins: TX, RX or TX+RX */ + 111:Generated_Source\PSoC4/UART_UART.c **** pinsConfig = config->direction; + 112:Generated_Source\PSoC4/UART_UART.c **** + 113:Generated_Source\PSoC4/UART_UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 114:Generated_Source\PSoC4/UART_UART.c **** /* Add RTS and CTS pins to configure */ + 115:Generated_Source\PSoC4/UART_UART.c **** pinsConfig |= (0u != config->rtsRxFifoLevel) ? (UART_UART_RTS_PIN_ENABLE) : (0u); + 116:Generated_Source\PSoC4/UART_UART.c **** pinsConfig |= (0u != config->enableCts) ? (UART_UART_CTS_PIN_ENABLE) : (0u); + 117:Generated_Source\PSoC4/UART_UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 118:Generated_Source\PSoC4/UART_UART.c **** + 119:Generated_Source\PSoC4/UART_UART.c **** /* Configure pins */ + 120:Generated_Source\PSoC4/UART_UART.c **** UART_SetPins(UART_SCB_MODE_UART, config->mode, pinsConfig); + 121:Generated_Source\PSoC4/UART_UART.c **** + 122:Generated_Source\PSoC4/UART_UART.c **** /* Store internal configuration */ + 123:Generated_Source\PSoC4/UART_UART.c **** UART_scbMode = (uint8) UART_SCB_MODE_UART; + 124:Generated_Source\PSoC4/UART_UART.c **** UART_scbEnableWake = (uint8) config->enableWake; + 125:Generated_Source\PSoC4/UART_UART.c **** UART_scbEnableIntr = (uint8) config->enableInterrupt; + 126:Generated_Source\PSoC4/UART_UART.c **** + 127:Generated_Source\PSoC4/UART_UART.c **** /* Set RX direction internal variables */ + 128:Generated_Source\PSoC4/UART_UART.c **** UART_rxBuffer = config->rxBuffer; + 129:Generated_Source\PSoC4/UART_UART.c **** UART_rxDataBits = (uint8) config->dataBits; + 130:Generated_Source\PSoC4/UART_UART.c **** UART_rxBufferSize = config->rxBufferSize; + 131:Generated_Source\PSoC4/UART_UART.c **** + 132:Generated_Source\PSoC4/UART_UART.c **** /* Set TX direction internal variables */ + 133:Generated_Source\PSoC4/UART_UART.c **** UART_txBuffer = config->txBuffer; + 134:Generated_Source\PSoC4/UART_UART.c **** UART_txDataBits = (uint8) config->dataBits; + 135:Generated_Source\PSoC4/UART_UART.c **** UART_txBufferSize = config->txBufferSize; + 136:Generated_Source\PSoC4/UART_UART.c **** + 137:Generated_Source\PSoC4/UART_UART.c **** /* Configure UART interface */ + 138:Generated_Source\PSoC4/UART_UART.c **** if(UART_UART_MODE_IRDA == config->mode) + 139:Generated_Source\PSoC4/UART_UART.c **** { + 140:Generated_Source\PSoC4/UART_UART.c **** /* OVS settings: IrDA */ + 141:Generated_Source\PSoC4/UART_UART.c **** UART_CTRL_REG = ((0u != config->enableIrdaLowPower) ? + 142:Generated_Source\PSoC4/UART_UART.c **** (UART_UART_GET_CTRL_OVS_IRDA_LP(config->oversample) + 143:Generated_Source\PSoC4/UART_UART.c **** (UART_CTRL_OVS_IRDA_OVS16)); + 144:Generated_Source\PSoC4/UART_UART.c **** } + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 4 + + + 145:Generated_Source\PSoC4/UART_UART.c **** else + 146:Generated_Source\PSoC4/UART_UART.c **** { + 147:Generated_Source\PSoC4/UART_UART.c **** /* OVS settings: UART and SmartCard */ + 148:Generated_Source\PSoC4/UART_UART.c **** UART_CTRL_REG = UART_GET_CTRL_OVS(config->oversample); + 149:Generated_Source\PSoC4/UART_UART.c **** } + 150:Generated_Source\PSoC4/UART_UART.c **** + 151:Generated_Source\PSoC4/UART_UART.c **** UART_CTRL_REG |= UART_GET_CTRL_BYTE_MODE (config->enableByteMode) | + 152:Generated_Source\PSoC4/UART_UART.c **** UART_GET_CTRL_ADDR_ACCEPT(config->multiprocAcceptAddr) + 153:Generated_Source\PSoC4/UART_UART.c **** UART_CTRL_UART; + 154:Generated_Source\PSoC4/UART_UART.c **** + 155:Generated_Source\PSoC4/UART_UART.c **** /* Configure sub-mode: UART, SmartCard or IrDA */ + 156:Generated_Source\PSoC4/UART_UART.c **** UART_UART_CTRL_REG = UART_GET_UART_CTRL_MODE(config->mode); + 157:Generated_Source\PSoC4/UART_UART.c **** + 158:Generated_Source\PSoC4/UART_UART.c **** /* Configure RX direction */ + 159:Generated_Source\PSoC4/UART_UART.c **** UART_UART_RX_CTRL_REG = UART_GET_UART_RX_CTRL_MODE(config->stopBits) | + 160:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_RX_CTRL_POLARITY(config->enableInvertedRx) + 161:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_RX_CTRL_MP_MODE(config->enableMultiproc) + 162:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(config->dropOnPari + 163:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(config->dropOnFrame + 164:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_RX_CTRL_BREAK_WIDTH(config->breakWidth); + 165:Generated_Source\PSoC4/UART_UART.c **** + 166:Generated_Source\PSoC4/UART_UART.c **** if(UART_UART_PARITY_NONE != config->parity) + 167:Generated_Source\PSoC4/UART_UART.c **** { + 168:Generated_Source\PSoC4/UART_UART.c **** UART_UART_RX_CTRL_REG |= UART_GET_UART_RX_CTRL_PARITY(config->parity) | + 169:Generated_Source\PSoC4/UART_UART.c **** UART_UART_RX_CTRL_PARITY_ENABLED; + 170:Generated_Source\PSoC4/UART_UART.c **** } + 171:Generated_Source\PSoC4/UART_UART.c **** + 172:Generated_Source\PSoC4/UART_UART.c **** UART_RX_CTRL_REG = UART_GET_RX_CTRL_DATA_WIDTH(config->dataBits) | + 173:Generated_Source\PSoC4/UART_UART.c **** UART_GET_RX_CTRL_MEDIAN(config->enableMedianFilter) + 174:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_RX_CTRL_ENABLED(config->direction); + 175:Generated_Source\PSoC4/UART_UART.c **** + 176:Generated_Source\PSoC4/UART_UART.c **** UART_RX_FIFO_CTRL_REG = UART_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(config->rxTriggerLevel); + 177:Generated_Source\PSoC4/UART_UART.c **** + 178:Generated_Source\PSoC4/UART_UART.c **** /* Configure MP address */ + 179:Generated_Source\PSoC4/UART_UART.c **** UART_RX_MATCH_REG = UART_GET_RX_MATCH_ADDR(config->multiprocAddr) | + 180:Generated_Source\PSoC4/UART_UART.c **** UART_GET_RX_MATCH_MASK(config->multiprocAddrMask); + 181:Generated_Source\PSoC4/UART_UART.c **** + 182:Generated_Source\PSoC4/UART_UART.c **** /* Configure RX direction */ + 183:Generated_Source\PSoC4/UART_UART.c **** UART_UART_TX_CTRL_REG = UART_GET_UART_TX_CTRL_MODE(config->stopBits) | + 184:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_TX_CTRL_RETRY_NACK(config->enableRetr + 185:Generated_Source\PSoC4/UART_UART.c **** + 186:Generated_Source\PSoC4/UART_UART.c **** if(UART_UART_PARITY_NONE != config->parity) + 187:Generated_Source\PSoC4/UART_UART.c **** { + 188:Generated_Source\PSoC4/UART_UART.c **** UART_UART_TX_CTRL_REG |= UART_GET_UART_TX_CTRL_PARITY(config->parity) | + 189:Generated_Source\PSoC4/UART_UART.c **** UART_UART_TX_CTRL_PARITY_ENABLED; + 190:Generated_Source\PSoC4/UART_UART.c **** } + 191:Generated_Source\PSoC4/UART_UART.c **** + 192:Generated_Source\PSoC4/UART_UART.c **** UART_TX_CTRL_REG = UART_GET_TX_CTRL_DATA_WIDTH(config->dataBits) | + 193:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_TX_CTRL_ENABLED(config->direction); + 194:Generated_Source\PSoC4/UART_UART.c **** + 195:Generated_Source\PSoC4/UART_UART.c **** UART_TX_FIFO_CTRL_REG = UART_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(config->txTriggerLevel); + 196:Generated_Source\PSoC4/UART_UART.c **** + 197:Generated_Source\PSoC4/UART_UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 198:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG = UART_GET_UART_FLOW_CTRL_CTS_ENABLE(config->enableCts) | \ + 199:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_FLOW_CTRL_CTS_POLARITY (config->ctsPolari + 200:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_FLOW_CTRL_RTS_POLARITY (config->rtsPolari + 201:Generated_Source\PSoC4/UART_UART.c **** UART_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(config->rtsRxFifo + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 5 + + + 202:Generated_Source\PSoC4/UART_UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 203:Generated_Source\PSoC4/UART_UART.c **** + 204:Generated_Source\PSoC4/UART_UART.c **** /* Configure interrupt with UART handler but do not enable it */ + 205:Generated_Source\PSoC4/UART_UART.c **** CyIntDisable (UART_ISR_NUMBER); + 206:Generated_Source\PSoC4/UART_UART.c **** CyIntSetPriority(UART_ISR_NUMBER, UART_ISR_PRIORITY); + 207:Generated_Source\PSoC4/UART_UART.c **** (void) CyIntSetVector(UART_ISR_NUMBER, &UART_SPI_UART_ISR); + 208:Generated_Source\PSoC4/UART_UART.c **** + 209:Generated_Source\PSoC4/UART_UART.c **** /* Configure WAKE interrupt */ + 210:Generated_Source\PSoC4/UART_UART.c **** #if(UART_UART_RX_WAKEUP_IRQ) + 211:Generated_Source\PSoC4/UART_UART.c **** CyIntDisable (UART_RX_WAKE_ISR_NUMBER); + 212:Generated_Source\PSoC4/UART_UART.c **** CyIntSetPriority(UART_RX_WAKE_ISR_NUMBER, UART_RX_WAKE_ISR_PRIORITY); + 213:Generated_Source\PSoC4/UART_UART.c **** (void) CyIntSetVector(UART_RX_WAKE_ISR_NUMBER, &UART_UART_WAKEUP_ISR); + 214:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + 215:Generated_Source\PSoC4/UART_UART.c **** + 216:Generated_Source\PSoC4/UART_UART.c **** /* Configure interrupt sources */ + 217:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_I2C_EC_MASK_REG = UART_NO_INTR_SOURCES; + 218:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_SPI_EC_MASK_REG = UART_NO_INTR_SOURCES; + 219:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_SLAVE_MASK_REG = UART_NO_INTR_SOURCES; + 220:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_MASTER_MASK_REG = UART_NO_INTR_SOURCES; + 221:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_RX_MASK_REG = config->rxInterruptMask; + 222:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_TX_MASK_REG = config->txInterruptMask; + 223:Generated_Source\PSoC4/UART_UART.c **** + 224:Generated_Source\PSoC4/UART_UART.c **** /* Configure TX interrupt sources to restore. */ + 225:Generated_Source\PSoC4/UART_UART.c **** UART_IntrTxMask = LO16(UART_INTR_TX_MASK_REG); + 226:Generated_Source\PSoC4/UART_UART.c **** + 227:Generated_Source\PSoC4/UART_UART.c **** /* Clear RX buffer indexes */ + 228:Generated_Source\PSoC4/UART_UART.c **** UART_rxBufferHead = 0u; + 229:Generated_Source\PSoC4/UART_UART.c **** UART_rxBufferTail = 0u; + 230:Generated_Source\PSoC4/UART_UART.c **** UART_rxBufferOverflow = 0u; + 231:Generated_Source\PSoC4/UART_UART.c **** + 232:Generated_Source\PSoC4/UART_UART.c **** /* Clear TX buffer indexes */ + 233:Generated_Source\PSoC4/UART_UART.c **** UART_txBufferHead = 0u; + 234:Generated_Source\PSoC4/UART_UART.c **** UART_txBufferTail = 0u; + 235:Generated_Source\PSoC4/UART_UART.c **** } + 236:Generated_Source\PSoC4/UART_UART.c **** } + 237:Generated_Source\PSoC4/UART_UART.c **** + 238:Generated_Source\PSoC4/UART_UART.c **** #else + 239:Generated_Source\PSoC4/UART_UART.c **** + 240:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 241:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartInit + 242:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 243:Generated_Source\PSoC4/UART_UART.c **** * + 244:Generated_Source\PSoC4/UART_UART.c **** * Configures the SCB for the UART operation. + 245:Generated_Source\PSoC4/UART_UART.c **** * + 246:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 247:Generated_Source\PSoC4/UART_UART.c **** void UART_UartInit(void) + 248:Generated_Source\PSoC4/UART_UART.c **** { + 28 .loc 1 248 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 00AF add r7, sp, #0 + 37 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 6 + + + 249:Generated_Source\PSoC4/UART_UART.c **** /* Configure UART interface */ + 250:Generated_Source\PSoC4/UART_UART.c **** UART_CTRL_REG = UART_UART_DEFAULT_CTRL; + 38 .loc 1 250 0 + 39 0004 1A4B ldr r3, .L2 + 40 0006 1B4A ldr r2, .L2+4 + 41 0008 1A60 str r2, [r3] + 251:Generated_Source\PSoC4/UART_UART.c **** + 252:Generated_Source\PSoC4/UART_UART.c **** /* Configure sub-mode: UART, SmartCard or IrDA */ + 253:Generated_Source\PSoC4/UART_UART.c **** UART_UART_CTRL_REG = UART_UART_DEFAULT_UART_CTRL; + 42 .loc 1 253 0 + 43 000a 1B4B ldr r3, .L2+8 + 44 000c 0022 movs r2, #0 + 45 000e 1A60 str r2, [r3] + 254:Generated_Source\PSoC4/UART_UART.c **** + 255:Generated_Source\PSoC4/UART_UART.c **** /* Configure RX direction */ + 256:Generated_Source\PSoC4/UART_UART.c **** UART_UART_RX_CTRL_REG = UART_UART_DEFAULT_UART_RX_CTRL; + 46 .loc 1 256 0 + 47 0010 1A4B ldr r3, .L2+12 + 48 0012 1B4A ldr r2, .L2+16 + 49 0014 1A60 str r2, [r3] + 257:Generated_Source\PSoC4/UART_UART.c **** UART_RX_CTRL_REG = UART_UART_DEFAULT_RX_CTRL; + 50 .loc 1 257 0 + 51 0016 1B4B ldr r3, .L2+20 + 52 0018 0722 movs r2, #7 + 53 001a 1A60 str r2, [r3] + 258:Generated_Source\PSoC4/UART_UART.c **** UART_RX_FIFO_CTRL_REG = UART_UART_DEFAULT_RX_FIFO_CTRL; + 54 .loc 1 258 0 + 55 001c 1A4B ldr r3, .L2+24 + 56 001e 0722 movs r2, #7 + 57 0020 1A60 str r2, [r3] + 259:Generated_Source\PSoC4/UART_UART.c **** UART_RX_MATCH_REG = UART_UART_DEFAULT_RX_MATCH_REG; + 58 .loc 1 259 0 + 59 0022 1A4B ldr r3, .L2+28 + 60 0024 0022 movs r2, #0 + 61 0026 1A60 str r2, [r3] + 260:Generated_Source\PSoC4/UART_UART.c **** + 261:Generated_Source\PSoC4/UART_UART.c **** /* Configure TX direction */ + 262:Generated_Source\PSoC4/UART_UART.c **** UART_UART_TX_CTRL_REG = UART_UART_DEFAULT_UART_TX_CTRL; + 62 .loc 1 262 0 + 63 0028 194B ldr r3, .L2+32 + 64 002a 0122 movs r2, #1 + 65 002c 1A60 str r2, [r3] + 263:Generated_Source\PSoC4/UART_UART.c **** UART_TX_CTRL_REG = UART_UART_DEFAULT_TX_CTRL; + 66 .loc 1 263 0 + 67 002e 194B ldr r3, .L2+36 + 68 0030 194A ldr r2, .L2+40 + 69 0032 1A60 str r2, [r3] + 264:Generated_Source\PSoC4/UART_UART.c **** UART_TX_FIFO_CTRL_REG = UART_UART_DEFAULT_TX_FIFO_CTRL; + 70 .loc 1 264 0 + 71 0034 194B ldr r3, .L2+44 + 72 0036 0022 movs r2, #0 + 73 0038 1A60 str r2, [r3] + 265:Generated_Source\PSoC4/UART_UART.c **** + 266:Generated_Source\PSoC4/UART_UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 267:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG = UART_UART_DEFAULT_FLOW_CTRL; + 268:Generated_Source\PSoC4/UART_UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 269:Generated_Source\PSoC4/UART_UART.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 7 + + + 270:Generated_Source\PSoC4/UART_UART.c **** /* Configure interrupt with UART handler but do not enable it */ + 271:Generated_Source\PSoC4/UART_UART.c **** #if(UART_SCB_IRQ_INTERNAL) + 272:Generated_Source\PSoC4/UART_UART.c **** CyIntDisable (UART_ISR_NUMBER); + 273:Generated_Source\PSoC4/UART_UART.c **** CyIntSetPriority(UART_ISR_NUMBER, UART_ISR_PRIORITY); + 274:Generated_Source\PSoC4/UART_UART.c **** (void) CyIntSetVector(UART_ISR_NUMBER, &UART_SPI_UART_ISR); + 275:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_SCB_IRQ_INTERNAL) */ + 276:Generated_Source\PSoC4/UART_UART.c **** + 277:Generated_Source\PSoC4/UART_UART.c **** /* Configure WAKE interrupt */ + 278:Generated_Source\PSoC4/UART_UART.c **** #if(UART_UART_RX_WAKEUP_IRQ) + 279:Generated_Source\PSoC4/UART_UART.c **** CyIntDisable (UART_RX_WAKE_ISR_NUMBER); + 280:Generated_Source\PSoC4/UART_UART.c **** CyIntSetPriority(UART_RX_WAKE_ISR_NUMBER, UART_RX_WAKE_ISR_PRIORITY); + 281:Generated_Source\PSoC4/UART_UART.c **** (void) CyIntSetVector(UART_RX_WAKE_ISR_NUMBER, &UART_UART_WAKEUP_ISR); + 282:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_RX_WAKEUP_IRQ) */ + 283:Generated_Source\PSoC4/UART_UART.c **** + 284:Generated_Source\PSoC4/UART_UART.c **** /* Configure interrupt sources */ + 285:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_I2C_EC_MASK_REG = UART_UART_DEFAULT_INTR_I2C_EC_MASK; + 74 .loc 1 285 0 + 75 003a 194B ldr r3, .L2+48 + 76 003c 0022 movs r2, #0 + 77 003e 1A60 str r2, [r3] + 286:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_SPI_EC_MASK_REG = UART_UART_DEFAULT_INTR_SPI_EC_MASK; + 78 .loc 1 286 0 + 79 0040 184B ldr r3, .L2+52 + 80 0042 0022 movs r2, #0 + 81 0044 1A60 str r2, [r3] + 287:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_SLAVE_MASK_REG = UART_UART_DEFAULT_INTR_SLAVE_MASK; + 82 .loc 1 287 0 + 83 0046 184B ldr r3, .L2+56 + 84 0048 0022 movs r2, #0 + 85 004a 1A60 str r2, [r3] + 288:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_MASTER_MASK_REG = UART_UART_DEFAULT_INTR_MASTER_MASK; + 86 .loc 1 288 0 + 87 004c 174B ldr r3, .L2+60 + 88 004e 0022 movs r2, #0 + 89 0050 1A60 str r2, [r3] + 289:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_RX_MASK_REG = UART_UART_DEFAULT_INTR_RX_MASK; + 90 .loc 1 289 0 + 91 0052 174B ldr r3, .L2+64 + 92 0054 0022 movs r2, #0 + 93 0056 1A60 str r2, [r3] + 290:Generated_Source\PSoC4/UART_UART.c **** UART_INTR_TX_MASK_REG = UART_UART_DEFAULT_INTR_TX_MASK; + 94 .loc 1 290 0 + 95 0058 164B ldr r3, .L2+68 + 96 005a 0022 movs r2, #0 + 97 005c 1A60 str r2, [r3] + 291:Generated_Source\PSoC4/UART_UART.c **** + 292:Generated_Source\PSoC4/UART_UART.c **** /* Configure TX interrupt sources to restore. */ + 293:Generated_Source\PSoC4/UART_UART.c **** UART_IntrTxMask = LO16(UART_INTR_TX_MASK_REG); + 98 .loc 1 293 0 + 99 005e 154B ldr r3, .L2+68 + 100 0060 1B68 ldr r3, [r3] + 101 0062 9AB2 uxth r2, r3 + 102 0064 144B ldr r3, .L2+72 + 103 0066 1A80 strh r2, [r3] + 294:Generated_Source\PSoC4/UART_UART.c **** + 295:Generated_Source\PSoC4/UART_UART.c **** #if(UART_INTERNAL_RX_SW_BUFFER_CONST) + 296:Generated_Source\PSoC4/UART_UART.c **** UART_rxBufferHead = 0u; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 8 + + + 297:Generated_Source\PSoC4/UART_UART.c **** UART_rxBufferTail = 0u; + 298:Generated_Source\PSoC4/UART_UART.c **** UART_rxBufferOverflow = 0u; + 299:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_INTERNAL_RX_SW_BUFFER_CONST) */ + 300:Generated_Source\PSoC4/UART_UART.c **** + 301:Generated_Source\PSoC4/UART_UART.c **** #if(UART_INTERNAL_TX_SW_BUFFER_CONST) + 302:Generated_Source\PSoC4/UART_UART.c **** UART_txBufferHead = 0u; + 303:Generated_Source\PSoC4/UART_UART.c **** UART_txBufferTail = 0u; + 304:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_INTERNAL_TX_SW_BUFFER_CONST) */ + 305:Generated_Source\PSoC4/UART_UART.c **** } + 104 .loc 1 305 0 + 105 0068 C046 nop + 106 006a BD46 mov sp, r7 + 107 @ sp needed + 108 006c 80BD pop {r7, pc} + 109 .L3: + 110 006e C046 .align 2 + 111 .L2: + 112 0070 00000640 .word 1074135040 + 113 0074 07000002 .word 33554439 + 114 0078 40000640 .word 1074135104 + 115 007c 48000640 .word 1074135112 + 116 0080 01000A00 .word 655361 + 117 0084 00030640 .word 1074135808 + 118 0088 04030640 .word 1074135812 + 119 008c 10030640 .word 1074135824 + 120 0090 44000640 .word 1074135108 + 121 0094 00020640 .word 1074135552 + 122 0098 07000080 .word -2147483641 + 123 009c 04020640 .word 1074135556 + 124 00a0 880E0640 .word 1074138760 + 125 00a4 C80E0640 .word 1074138824 + 126 00a8 480F0640 .word 1074138952 + 127 00ac 080F0640 .word 1074138888 + 128 00b0 C80F0640 .word 1074139080 + 129 00b4 880F0640 .word 1074139016 + 130 00b8 00000000 .word UART_IntrTxMask + 131 .cfi_endproc + 132 .LFE0: + 133 .size UART_UartInit, .-UART_UartInit + 134 .section .text.UART_UartPostEnable,"ax",%progbits + 135 .align 2 + 136 .global UART_UartPostEnable + 137 .code 16 + 138 .thumb_func + 139 .type UART_UartPostEnable, %function + 140 UART_UartPostEnable: + 141 .LFB1: + 306:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 307:Generated_Source\PSoC4/UART_UART.c **** + 308:Generated_Source\PSoC4/UART_UART.c **** + 309:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 310:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartPostEnable + 311:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 312:Generated_Source\PSoC4/UART_UART.c **** * + 313:Generated_Source\PSoC4/UART_UART.c **** * Restores HSIOM settings for the UART output pins (TX and/or RTS) to be + 314:Generated_Source\PSoC4/UART_UART.c **** * controlled by the SCB UART. + 315:Generated_Source\PSoC4/UART_UART.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 9 + + + 316:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 317:Generated_Source\PSoC4/UART_UART.c **** void UART_UartPostEnable(void) + 318:Generated_Source\PSoC4/UART_UART.c **** { + 142 .loc 1 318 0 + 143 .cfi_startproc + 144 @ args = 0, pretend = 0, frame = 0 + 145 @ frame_needed = 1, uses_anonymous_args = 0 + 146 0000 80B5 push {r7, lr} + 147 .cfi_def_cfa_offset 8 + 148 .cfi_offset 7, -8 + 149 .cfi_offset 14, -4 + 150 0002 00AF add r7, sp, #0 + 151 .cfi_def_cfa_register 7 + 319:Generated_Source\PSoC4/UART_UART.c **** #if (UART_SCB_MODE_UNCONFIG_CONST_CFG) + 320:Generated_Source\PSoC4/UART_UART.c **** #if (UART_TX_SDA_MISO_PIN) + 321:Generated_Source\PSoC4/UART_UART.c **** if (UART_CHECK_TX_SDA_MISO_PIN_USED) + 322:Generated_Source\PSoC4/UART_UART.c **** { + 323:Generated_Source\PSoC4/UART_UART.c **** /* Set SCB UART to drive the output pin */ + 324:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, UART_TX_SDA_MISO_HSIOM_MASK, + 325:Generated_Source\PSoC4/UART_UART.c **** UART_TX_SDA_MISO_HSIOM_POS, UART_TX_SDA_MISO_HSIOM_SEL_U + 326:Generated_Source\PSoC4/UART_UART.c **** } + 327:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_TX_SDA_MISO_PIN_PIN) */ + 328:Generated_Source\PSoC4/UART_UART.c **** + 329:Generated_Source\PSoC4/UART_UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 330:Generated_Source\PSoC4/UART_UART.c **** #if (UART_SS0_PIN) + 331:Generated_Source\PSoC4/UART_UART.c **** if (UART_CHECK_SS0_PIN_USED) + 332:Generated_Source\PSoC4/UART_UART.c **** { + 333:Generated_Source\PSoC4/UART_UART.c **** /* Set SCB UART to drive the output pin */ + 334:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, UART_SS0_HSIOM_MASK, + 335:Generated_Source\PSoC4/UART_UART.c **** UART_SS0_HSIOM_POS, UART_SS0_HSIOM_SEL_UART); + 336:Generated_Source\PSoC4/UART_UART.c **** } + 337:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_SS0_PIN) */ + 338:Generated_Source\PSoC4/UART_UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 339:Generated_Source\PSoC4/UART_UART.c **** + 340:Generated_Source\PSoC4/UART_UART.c **** #else + 341:Generated_Source\PSoC4/UART_UART.c **** #if (UART_UART_TX_PIN) + 342:Generated_Source\PSoC4/UART_UART.c **** /* Set SCB UART to drive the output pin */ + 343:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_TX_HSIOM_REG, UART_TX_HSIOM_MASK, + 152 .loc 1 343 0 + 153 0004 074B ldr r3, .L5 + 154 0006 074A ldr r2, .L5 + 155 0008 1268 ldr r2, [r2] + 156 000a F021 movs r1, #240 + 157 000c 8A43 bics r2, r1 + 158 000e 9021 movs r1, #144 + 159 0010 0A43 orrs r2, r1 + 160 0012 1A60 str r2, [r3] + 344:Generated_Source\PSoC4/UART_UART.c **** UART_TX_HSIOM_POS, UART_TX_HSIOM_SEL_UART); + 345:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_TX_PIN) */ + 346:Generated_Source\PSoC4/UART_UART.c **** + 347:Generated_Source\PSoC4/UART_UART.c **** #if (UART_UART_RTS_PIN) + 348:Generated_Source\PSoC4/UART_UART.c **** /* Set SCB UART to drive the output pin */ + 349:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_RTS_HSIOM_REG, UART_RTS_HSIOM_MASK, + 350:Generated_Source\PSoC4/UART_UART.c **** UART_RTS_HSIOM_POS, UART_RTS_HSIOM_SEL_UART); + 351:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_RTS_PIN) */ + 352:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 353:Generated_Source\PSoC4/UART_UART.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 10 + + + 354:Generated_Source\PSoC4/UART_UART.c **** /* Restore TX interrupt sources. */ + 355:Generated_Source\PSoC4/UART_UART.c **** UART_SetTxInterruptMode(UART_IntrTxMask); + 161 .loc 1 355 0 + 162 0014 044B ldr r3, .L5+4 + 163 0016 054A ldr r2, .L5+8 + 164 0018 1288 ldrh r2, [r2] + 165 001a 1A60 str r2, [r3] + 356:Generated_Source\PSoC4/UART_UART.c **** } + 166 .loc 1 356 0 + 167 001c C046 nop + 168 001e BD46 mov sp, r7 + 169 @ sp needed + 170 0020 80BD pop {r7, pc} + 171 .L6: + 172 0022 C046 .align 2 + 173 .L5: + 174 0024 10000140 .word 1073807376 + 175 0028 880F0640 .word 1074139016 + 176 002c 00000000 .word UART_IntrTxMask + 177 .cfi_endproc + 178 .LFE1: + 179 .size UART_UartPostEnable, .-UART_UartPostEnable + 180 .section .text.UART_UartStop,"ax",%progbits + 181 .align 2 + 182 .global UART_UartStop + 183 .code 16 + 184 .thumb_func + 185 .type UART_UartStop, %function + 186 UART_UartStop: + 187 .LFB2: + 357:Generated_Source\PSoC4/UART_UART.c **** + 358:Generated_Source\PSoC4/UART_UART.c **** + 359:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 360:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartStop + 361:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 362:Generated_Source\PSoC4/UART_UART.c **** * + 363:Generated_Source\PSoC4/UART_UART.c **** * Changes the HSIOM settings for the UART output pins (TX and/or RTS) to keep + 364:Generated_Source\PSoC4/UART_UART.c **** * them inactive after the block is disabled. The output pins are controlled by + 365:Generated_Source\PSoC4/UART_UART.c **** * the GPIO data register. Also, the function disables the skip start feature + 366:Generated_Source\PSoC4/UART_UART.c **** * to not cause it to trigger after the component is enabled. + 367:Generated_Source\PSoC4/UART_UART.c **** * + 368:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 369:Generated_Source\PSoC4/UART_UART.c **** void UART_UartStop(void) + 370:Generated_Source\PSoC4/UART_UART.c **** { + 188 .loc 1 370 0 + 189 .cfi_startproc + 190 @ args = 0, pretend = 0, frame = 0 + 191 @ frame_needed = 1, uses_anonymous_args = 0 + 192 0000 80B5 push {r7, lr} + 193 .cfi_def_cfa_offset 8 + 194 .cfi_offset 7, -8 + 195 .cfi_offset 14, -4 + 196 0002 00AF add r7, sp, #0 + 197 .cfi_def_cfa_register 7 + 371:Generated_Source\PSoC4/UART_UART.c **** #if(UART_SCB_MODE_UNCONFIG_CONST_CFG) + 372:Generated_Source\PSoC4/UART_UART.c **** #if (UART_TX_SDA_MISO_PIN) + 373:Generated_Source\PSoC4/UART_UART.c **** if (UART_CHECK_TX_SDA_MISO_PIN_USED) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 11 + + + 374:Generated_Source\PSoC4/UART_UART.c **** { + 375:Generated_Source\PSoC4/UART_UART.c **** /* Set GPIO to drive output pin */ + 376:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, UART_TX_SDA_MISO_HSIOM_MASK, + 377:Generated_Source\PSoC4/UART_UART.c **** UART_TX_SDA_MISO_HSIOM_POS, UART_TX_SDA_MISO_HSIOM_SEL_G + 378:Generated_Source\PSoC4/UART_UART.c **** } + 379:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_TX_SDA_MISO_PIN_PIN) */ + 380:Generated_Source\PSoC4/UART_UART.c **** + 381:Generated_Source\PSoC4/UART_UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 382:Generated_Source\PSoC4/UART_UART.c **** #if (UART_SS0_PIN) + 383:Generated_Source\PSoC4/UART_UART.c **** if (UART_CHECK_SS0_PIN_USED) + 384:Generated_Source\PSoC4/UART_UART.c **** { + 385:Generated_Source\PSoC4/UART_UART.c **** /* Set output pin state after block is disabled */ + 386:Generated_Source\PSoC4/UART_UART.c **** UART_spi_ss0_Write(UART_GET_UART_RTS_INACTIVE); + 387:Generated_Source\PSoC4/UART_UART.c **** + 388:Generated_Source\PSoC4/UART_UART.c **** /* Set GPIO to drive output pin */ + 389:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, UART_SS0_HSIOM_MASK, + 390:Generated_Source\PSoC4/UART_UART.c **** UART_SS0_HSIOM_POS, UART_SS0_HSIOM_SEL_GPIO); + 391:Generated_Source\PSoC4/UART_UART.c **** } + 392:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_SS0_PIN) */ + 393:Generated_Source\PSoC4/UART_UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 394:Generated_Source\PSoC4/UART_UART.c **** + 395:Generated_Source\PSoC4/UART_UART.c **** #else + 396:Generated_Source\PSoC4/UART_UART.c **** #if (UART_UART_TX_PIN) + 397:Generated_Source\PSoC4/UART_UART.c **** /* Set GPIO to drive output pin */ + 398:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_TX_HSIOM_REG, UART_TX_HSIOM_MASK, + 198 .loc 1 398 0 + 199 0004 084B ldr r3, .L8 + 200 0006 084A ldr r2, .L8 + 201 0008 1268 ldr r2, [r2] + 202 000a F021 movs r1, #240 + 203 000c 8A43 bics r2, r1 + 204 000e 1A60 str r2, [r3] + 399:Generated_Source\PSoC4/UART_UART.c **** UART_TX_HSIOM_POS, UART_TX_HSIOM_SEL_GPIO); + 400:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_TX_PIN) */ + 401:Generated_Source\PSoC4/UART_UART.c **** + 402:Generated_Source\PSoC4/UART_UART.c **** #if (UART_UART_RTS_PIN) + 403:Generated_Source\PSoC4/UART_UART.c **** /* Set output pin state after block is disabled */ + 404:Generated_Source\PSoC4/UART_UART.c **** UART_rts_Write(UART_GET_UART_RTS_INACTIVE); + 405:Generated_Source\PSoC4/UART_UART.c **** + 406:Generated_Source\PSoC4/UART_UART.c **** /* Set GPIO to drive output pin */ + 407:Generated_Source\PSoC4/UART_UART.c **** UART_SET_HSIOM_SEL(UART_RTS_HSIOM_REG, UART_RTS_HSIOM_MASK, + 408:Generated_Source\PSoC4/UART_UART.c **** UART_RTS_HSIOM_POS, UART_RTS_HSIOM_SEL_GPIO); + 409:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_RTS_PIN) */ + 410:Generated_Source\PSoC4/UART_UART.c **** + 411:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_SCB_MODE_UNCONFIG_CONST_CFG) */ + 412:Generated_Source\PSoC4/UART_UART.c **** + 413:Generated_Source\PSoC4/UART_UART.c **** #if (UART_UART_WAKE_ENABLE_CONST) + 414:Generated_Source\PSoC4/UART_UART.c **** /* Disable skip start feature used for wakeup */ + 415:Generated_Source\PSoC4/UART_UART.c **** UART_UART_RX_CTRL_REG &= (uint32) ~UART_UART_RX_CTRL_SKIP_START; + 416:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_WAKE_ENABLE_CONST) */ + 417:Generated_Source\PSoC4/UART_UART.c **** + 418:Generated_Source\PSoC4/UART_UART.c **** /* Store TX interrupt sources (exclude level triggered). */ + 419:Generated_Source\PSoC4/UART_UART.c **** UART_IntrTxMask = LO16(UART_GetTxInterruptMode() & UART_INTR_UART_TX_RESTORE); + 205 .loc 1 419 0 + 206 0010 064B ldr r3, .L8+4 + 207 0012 1B68 ldr r3, [r3] + 208 0014 9AB2 uxth r2, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 12 + + + 209 0016 E423 movs r3, #228 + 210 0018 DB00 lsls r3, r3, #3 + 211 001a 1340 ands r3, r2 + 212 001c 9AB2 uxth r2, r3 + 213 001e 044B ldr r3, .L8+8 + 214 0020 1A80 strh r2, [r3] + 420:Generated_Source\PSoC4/UART_UART.c **** } + 215 .loc 1 420 0 + 216 0022 C046 nop + 217 0024 BD46 mov sp, r7 + 218 @ sp needed + 219 0026 80BD pop {r7, pc} + 220 .L9: + 221 .align 2 + 222 .L8: + 223 0028 10000140 .word 1073807376 + 224 002c 880F0640 .word 1074139016 + 225 0030 00000000 .word UART_IntrTxMask + 226 .cfi_endproc + 227 .LFE2: + 228 .size UART_UartStop, .-UART_UartStop + 229 .section .text.UART_UartSetRxAddress,"ax",%progbits + 230 .align 2 + 231 .global UART_UartSetRxAddress + 232 .code 16 + 233 .thumb_func + 234 .type UART_UartSetRxAddress, %function + 235 UART_UartSetRxAddress: + 236 .LFB3: + 421:Generated_Source\PSoC4/UART_UART.c **** + 422:Generated_Source\PSoC4/UART_UART.c **** + 423:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 424:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartSetRxAddress + 425:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 426:Generated_Source\PSoC4/UART_UART.c **** * + 427:Generated_Source\PSoC4/UART_UART.c **** * Sets the hardware detectable receiver address for the UART in the + 428:Generated_Source\PSoC4/UART_UART.c **** * Multiprocessor mode. + 429:Generated_Source\PSoC4/UART_UART.c **** * + 430:Generated_Source\PSoC4/UART_UART.c **** * \param address: Address for hardware address detection. + 431:Generated_Source\PSoC4/UART_UART.c **** * + 432:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 433:Generated_Source\PSoC4/UART_UART.c **** void UART_UartSetRxAddress(uint32 address) + 434:Generated_Source\PSoC4/UART_UART.c **** { + 237 .loc 1 434 0 + 238 .cfi_startproc + 239 @ args = 0, pretend = 0, frame = 16 + 240 @ frame_needed = 1, uses_anonymous_args = 0 + 241 0000 80B5 push {r7, lr} + 242 .cfi_def_cfa_offset 8 + 243 .cfi_offset 7, -8 + 244 .cfi_offset 14, -4 + 245 0002 84B0 sub sp, sp, #16 + 246 .cfi_def_cfa_offset 24 + 247 0004 00AF add r7, sp, #0 + 248 .cfi_def_cfa_register 7 + 249 0006 7860 str r0, [r7, #4] + 435:Generated_Source\PSoC4/UART_UART.c **** uint32 matchReg; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 13 + + + 436:Generated_Source\PSoC4/UART_UART.c **** + 437:Generated_Source\PSoC4/UART_UART.c **** matchReg = UART_RX_MATCH_REG; + 250 .loc 1 437 0 + 251 0008 094B ldr r3, .L11 + 252 000a 1B68 ldr r3, [r3] + 253 000c FB60 str r3, [r7, #12] + 438:Generated_Source\PSoC4/UART_UART.c **** + 439:Generated_Source\PSoC4/UART_UART.c **** matchReg &= ((uint32) ~UART_RX_MATCH_ADDR_MASK); /* Clear address bits */ + 254 .loc 1 439 0 + 255 000e FB68 ldr r3, [r7, #12] + 256 0010 FF22 movs r2, #255 + 257 0012 9343 bics r3, r2 + 258 0014 FB60 str r3, [r7, #12] + 440:Generated_Source\PSoC4/UART_UART.c **** matchReg |= ((uint32) (address & UART_RX_MATCH_ADDR_MASK)); /* Set address */ + 259 .loc 1 440 0 + 260 0016 7B68 ldr r3, [r7, #4] + 261 0018 FF22 movs r2, #255 + 262 001a 1340 ands r3, r2 + 263 001c FA68 ldr r2, [r7, #12] + 264 001e 1343 orrs r3, r2 + 265 0020 FB60 str r3, [r7, #12] + 441:Generated_Source\PSoC4/UART_UART.c **** + 442:Generated_Source\PSoC4/UART_UART.c **** UART_RX_MATCH_REG = matchReg; + 266 .loc 1 442 0 + 267 0022 034B ldr r3, .L11 + 268 0024 FA68 ldr r2, [r7, #12] + 269 0026 1A60 str r2, [r3] + 443:Generated_Source\PSoC4/UART_UART.c **** } + 270 .loc 1 443 0 + 271 0028 C046 nop + 272 002a BD46 mov sp, r7 + 273 002c 04B0 add sp, sp, #16 + 274 @ sp needed + 275 002e 80BD pop {r7, pc} + 276 .L12: + 277 .align 2 + 278 .L11: + 279 0030 10030640 .word 1074135824 + 280 .cfi_endproc + 281 .LFE3: + 282 .size UART_UartSetRxAddress, .-UART_UartSetRxAddress + 283 .section .text.UART_UartSetRxAddressMask,"ax",%progbits + 284 .align 2 + 285 .global UART_UartSetRxAddressMask + 286 .code 16 + 287 .thumb_func + 288 .type UART_UartSetRxAddressMask, %function + 289 UART_UartSetRxAddressMask: + 290 .LFB4: + 444:Generated_Source\PSoC4/UART_UART.c **** + 445:Generated_Source\PSoC4/UART_UART.c **** + 446:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 447:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartSetRxAddressMask + 448:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 449:Generated_Source\PSoC4/UART_UART.c **** * + 450:Generated_Source\PSoC4/UART_UART.c **** * Sets the hardware address mask for the UART in the Multiprocessor mode. + 451:Generated_Source\PSoC4/UART_UART.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 14 + + + 452:Generated_Source\PSoC4/UART_UART.c **** * \param addressMask: Address mask. + 453:Generated_Source\PSoC4/UART_UART.c **** * - Bit value 0 – excludes bit from address comparison. + 454:Generated_Source\PSoC4/UART_UART.c **** * - Bit value 1 – the bit needs to match with the corresponding bit + 455:Generated_Source\PSoC4/UART_UART.c **** * of the address. + 456:Generated_Source\PSoC4/UART_UART.c **** * + 457:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 458:Generated_Source\PSoC4/UART_UART.c **** void UART_UartSetRxAddressMask(uint32 addressMask) + 459:Generated_Source\PSoC4/UART_UART.c **** { + 291 .loc 1 459 0 + 292 .cfi_startproc + 293 @ args = 0, pretend = 0, frame = 16 + 294 @ frame_needed = 1, uses_anonymous_args = 0 + 295 0000 80B5 push {r7, lr} + 296 .cfi_def_cfa_offset 8 + 297 .cfi_offset 7, -8 + 298 .cfi_offset 14, -4 + 299 0002 84B0 sub sp, sp, #16 + 300 .cfi_def_cfa_offset 24 + 301 0004 00AF add r7, sp, #0 + 302 .cfi_def_cfa_register 7 + 303 0006 7860 str r0, [r7, #4] + 460:Generated_Source\PSoC4/UART_UART.c **** uint32 matchReg; + 461:Generated_Source\PSoC4/UART_UART.c **** + 462:Generated_Source\PSoC4/UART_UART.c **** matchReg = UART_RX_MATCH_REG; + 304 .loc 1 462 0 + 305 0008 094B ldr r3, .L14 + 306 000a 1B68 ldr r3, [r3] + 307 000c FB60 str r3, [r7, #12] + 463:Generated_Source\PSoC4/UART_UART.c **** + 464:Generated_Source\PSoC4/UART_UART.c **** matchReg &= ((uint32) ~UART_RX_MATCH_MASK_MASK); /* Clear address mask bits */ + 308 .loc 1 464 0 + 309 000e FB68 ldr r3, [r7, #12] + 310 0010 084A ldr r2, .L14+4 + 311 0012 1340 ands r3, r2 + 312 0014 FB60 str r3, [r7, #12] + 465:Generated_Source\PSoC4/UART_UART.c **** matchReg |= ((uint32) (addressMask << UART_RX_MATCH_MASK_POS)); + 313 .loc 1 465 0 + 314 0016 7B68 ldr r3, [r7, #4] + 315 0018 1B04 lsls r3, r3, #16 + 316 001a FA68 ldr r2, [r7, #12] + 317 001c 1343 orrs r3, r2 + 318 001e FB60 str r3, [r7, #12] + 466:Generated_Source\PSoC4/UART_UART.c **** + 467:Generated_Source\PSoC4/UART_UART.c **** UART_RX_MATCH_REG = matchReg; + 319 .loc 1 467 0 + 320 0020 034B ldr r3, .L14 + 321 0022 FA68 ldr r2, [r7, #12] + 322 0024 1A60 str r2, [r3] + 468:Generated_Source\PSoC4/UART_UART.c **** } + 323 .loc 1 468 0 + 324 0026 C046 nop + 325 0028 BD46 mov sp, r7 + 326 002a 04B0 add sp, sp, #16 + 327 @ sp needed + 328 002c 80BD pop {r7, pc} + 329 .L15: + 330 002e C046 .align 2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 15 + + + 331 .L14: + 332 0030 10030640 .word 1074135824 + 333 0034 FFFF00FF .word -16711681 + 334 .cfi_endproc + 335 .LFE4: + 336 .size UART_UartSetRxAddressMask, .-UART_UartSetRxAddressMask + 337 .section .text.UART_UartPutString,"ax",%progbits + 338 .align 2 + 339 .global UART_UartPutString + 340 .code 16 + 341 .thumb_func + 342 .type UART_UartPutString, %function + 343 UART_UartPutString: + 344 .LFB5: + 469:Generated_Source\PSoC4/UART_UART.c **** + 470:Generated_Source\PSoC4/UART_UART.c **** + 471:Generated_Source\PSoC4/UART_UART.c **** #if(UART_UART_RX_DIRECTION) + 472:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 473:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartGetChar + 474:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 475:Generated_Source\PSoC4/UART_UART.c **** * + 476:Generated_Source\PSoC4/UART_UART.c **** * Retrieves next data element from receive buffer. + 477:Generated_Source\PSoC4/UART_UART.c **** * This function is designed for ASCII characters and returns a char where + 478:Generated_Source\PSoC4/UART_UART.c **** * 1 to 255 are valid characters and 0 indicates an error occurred or no data + 479:Generated_Source\PSoC4/UART_UART.c **** * is present. + 480:Generated_Source\PSoC4/UART_UART.c **** * - RX software buffer is disabled: Returns data element retrieved from RX + 481:Generated_Source\PSoC4/UART_UART.c **** * FIFO. + 482:Generated_Source\PSoC4/UART_UART.c **** * - RX software buffer is enabled: Returns data element from the software + 483:Generated_Source\PSoC4/UART_UART.c **** * receive buffer. + 484:Generated_Source\PSoC4/UART_UART.c **** * + 485:Generated_Source\PSoC4/UART_UART.c **** * \return + 486:Generated_Source\PSoC4/UART_UART.c **** * Next data element from the receive buffer. ASCII character values from + 487:Generated_Source\PSoC4/UART_UART.c **** * 1 to 255 are valid. A returned zero signifies an error condition or no + 488:Generated_Source\PSoC4/UART_UART.c **** * data available. + 489:Generated_Source\PSoC4/UART_UART.c **** * + 490:Generated_Source\PSoC4/UART_UART.c **** * \sideeffect + 491:Generated_Source\PSoC4/UART_UART.c **** * The errors bits may not correspond with reading characters due to + 492:Generated_Source\PSoC4/UART_UART.c **** * RX FIFO and software buffer usage. + 493:Generated_Source\PSoC4/UART_UART.c **** * RX software buffer is enabled: The internal software buffer overflow + 494:Generated_Source\PSoC4/UART_UART.c **** * is not treated as an error condition. + 495:Generated_Source\PSoC4/UART_UART.c **** * Check UART_rxBufferOverflow to capture that error condition. + 496:Generated_Source\PSoC4/UART_UART.c **** * + 497:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 498:Generated_Source\PSoC4/UART_UART.c **** uint32 UART_UartGetChar(void) + 499:Generated_Source\PSoC4/UART_UART.c **** { + 500:Generated_Source\PSoC4/UART_UART.c **** uint32 rxData = 0u; + 501:Generated_Source\PSoC4/UART_UART.c **** + 502:Generated_Source\PSoC4/UART_UART.c **** /* Reads data only if there is data to read */ + 503:Generated_Source\PSoC4/UART_UART.c **** if (0u != UART_SpiUartGetRxBufferSize()) + 504:Generated_Source\PSoC4/UART_UART.c **** { + 505:Generated_Source\PSoC4/UART_UART.c **** rxData = UART_SpiUartReadRxData(); + 506:Generated_Source\PSoC4/UART_UART.c **** } + 507:Generated_Source\PSoC4/UART_UART.c **** + 508:Generated_Source\PSoC4/UART_UART.c **** if (UART_CHECK_INTR_RX(UART_INTR_RX_ERR)) + 509:Generated_Source\PSoC4/UART_UART.c **** { + 510:Generated_Source\PSoC4/UART_UART.c **** rxData = 0u; /* Error occurred: returns zero */ + 511:Generated_Source\PSoC4/UART_UART.c **** UART_ClearRxInterruptSource(UART_INTR_RX_ERR); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 16 + + + 512:Generated_Source\PSoC4/UART_UART.c **** } + 513:Generated_Source\PSoC4/UART_UART.c **** + 514:Generated_Source\PSoC4/UART_UART.c **** return (rxData); + 515:Generated_Source\PSoC4/UART_UART.c **** } + 516:Generated_Source\PSoC4/UART_UART.c **** + 517:Generated_Source\PSoC4/UART_UART.c **** + 518:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 519:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartGetByte + 520:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 521:Generated_Source\PSoC4/UART_UART.c **** * + 522:Generated_Source\PSoC4/UART_UART.c **** * Retrieves the next data element from the receive buffer, returns the + 523:Generated_Source\PSoC4/UART_UART.c **** * received byte and error condition. + 524:Generated_Source\PSoC4/UART_UART.c **** * - The RX software buffer is disabled: returns the data element retrieved + 525:Generated_Source\PSoC4/UART_UART.c **** * from the RX FIFO. Undefined data will be returned if the RX FIFO is + 526:Generated_Source\PSoC4/UART_UART.c **** * empty. + 527:Generated_Source\PSoC4/UART_UART.c **** * - The RX software buffer is enabled: returns data element from the + 528:Generated_Source\PSoC4/UART_UART.c **** * software receive buffer. + 529:Generated_Source\PSoC4/UART_UART.c **** * + 530:Generated_Source\PSoC4/UART_UART.c **** * \return + 531:Generated_Source\PSoC4/UART_UART.c **** * Bits 7-0 contain the next data element from the receive buffer and + 532:Generated_Source\PSoC4/UART_UART.c **** * other bits contain the error condition. + 533:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_RX_OVERFLOW - Attempt to write to a full + 534:Generated_Source\PSoC4/UART_UART.c **** * receiver FIFO. + 535:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_RX_UNDERFLOW Attempt to read from an empty + 536:Generated_Source\PSoC4/UART_UART.c **** * receiver FIFO. + 537:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_RX_FRAME_ERROR - UART framing error detected. + 538:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_RX_PARITY_ERROR - UART parity error detected. + 539:Generated_Source\PSoC4/UART_UART.c **** * + 540:Generated_Source\PSoC4/UART_UART.c **** * \sideeffect + 541:Generated_Source\PSoC4/UART_UART.c **** * The errors bits may not correspond with reading characters due to + 542:Generated_Source\PSoC4/UART_UART.c **** * RX FIFO and software buffer usage. + 543:Generated_Source\PSoC4/UART_UART.c **** * RX software buffer is enabled: The internal software buffer overflow + 544:Generated_Source\PSoC4/UART_UART.c **** * is not treated as an error condition. + 545:Generated_Source\PSoC4/UART_UART.c **** * Check UART_rxBufferOverflow to capture that error condition. + 546:Generated_Source\PSoC4/UART_UART.c **** * + 547:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 548:Generated_Source\PSoC4/UART_UART.c **** uint32 UART_UartGetByte(void) + 549:Generated_Source\PSoC4/UART_UART.c **** { + 550:Generated_Source\PSoC4/UART_UART.c **** uint32 rxData; + 551:Generated_Source\PSoC4/UART_UART.c **** uint32 tmpStatus; + 552:Generated_Source\PSoC4/UART_UART.c **** + 553:Generated_Source\PSoC4/UART_UART.c **** #if (UART_CHECK_RX_SW_BUFFER) + 554:Generated_Source\PSoC4/UART_UART.c **** { + 555:Generated_Source\PSoC4/UART_UART.c **** UART_DisableInt(); + 556:Generated_Source\PSoC4/UART_UART.c **** } + 557:Generated_Source\PSoC4/UART_UART.c **** #endif + 558:Generated_Source\PSoC4/UART_UART.c **** + 559:Generated_Source\PSoC4/UART_UART.c **** if (0u != UART_SpiUartGetRxBufferSize()) + 560:Generated_Source\PSoC4/UART_UART.c **** { + 561:Generated_Source\PSoC4/UART_UART.c **** /* Enables interrupt to receive more bytes: at least one byte is in + 562:Generated_Source\PSoC4/UART_UART.c **** * buffer. + 563:Generated_Source\PSoC4/UART_UART.c **** */ + 564:Generated_Source\PSoC4/UART_UART.c **** #if (UART_CHECK_RX_SW_BUFFER) + 565:Generated_Source\PSoC4/UART_UART.c **** { + 566:Generated_Source\PSoC4/UART_UART.c **** UART_EnableInt(); + 567:Generated_Source\PSoC4/UART_UART.c **** } + 568:Generated_Source\PSoC4/UART_UART.c **** #endif + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 17 + + + 569:Generated_Source\PSoC4/UART_UART.c **** + 570:Generated_Source\PSoC4/UART_UART.c **** /* Get received byte */ + 571:Generated_Source\PSoC4/UART_UART.c **** rxData = UART_SpiUartReadRxData(); + 572:Generated_Source\PSoC4/UART_UART.c **** } + 573:Generated_Source\PSoC4/UART_UART.c **** else + 574:Generated_Source\PSoC4/UART_UART.c **** { + 575:Generated_Source\PSoC4/UART_UART.c **** /* Reads a byte directly from RX FIFO: underflow is raised in the + 576:Generated_Source\PSoC4/UART_UART.c **** * case of empty. Otherwise the first received byte will be read. + 577:Generated_Source\PSoC4/UART_UART.c **** */ + 578:Generated_Source\PSoC4/UART_UART.c **** rxData = UART_RX_FIFO_RD_REG; + 579:Generated_Source\PSoC4/UART_UART.c **** + 580:Generated_Source\PSoC4/UART_UART.c **** + 581:Generated_Source\PSoC4/UART_UART.c **** /* Enables interrupt to receive more bytes. */ + 582:Generated_Source\PSoC4/UART_UART.c **** #if (UART_CHECK_RX_SW_BUFFER) + 583:Generated_Source\PSoC4/UART_UART.c **** { + 584:Generated_Source\PSoC4/UART_UART.c **** + 585:Generated_Source\PSoC4/UART_UART.c **** /* The byte has been read from RX FIFO. Clear RX interrupt to + 586:Generated_Source\PSoC4/UART_UART.c **** * not involve interrupt handler when RX FIFO is empty. + 587:Generated_Source\PSoC4/UART_UART.c **** */ + 588:Generated_Source\PSoC4/UART_UART.c **** UART_ClearRxInterruptSource(UART_INTR_RX_NOT_EMPTY); + 589:Generated_Source\PSoC4/UART_UART.c **** + 590:Generated_Source\PSoC4/UART_UART.c **** UART_EnableInt(); + 591:Generated_Source\PSoC4/UART_UART.c **** } + 592:Generated_Source\PSoC4/UART_UART.c **** #endif + 593:Generated_Source\PSoC4/UART_UART.c **** } + 594:Generated_Source\PSoC4/UART_UART.c **** + 595:Generated_Source\PSoC4/UART_UART.c **** /* Get and clear RX error mask */ + 596:Generated_Source\PSoC4/UART_UART.c **** tmpStatus = (UART_GetRxInterruptSource() & UART_INTR_RX_ERR); + 597:Generated_Source\PSoC4/UART_UART.c **** UART_ClearRxInterruptSource(UART_INTR_RX_ERR); + 598:Generated_Source\PSoC4/UART_UART.c **** + 599:Generated_Source\PSoC4/UART_UART.c **** /* Puts together data and error status: + 600:Generated_Source\PSoC4/UART_UART.c **** * MP mode and accept address: 9th bit is set to notify mark. + 601:Generated_Source\PSoC4/UART_UART.c **** */ + 602:Generated_Source\PSoC4/UART_UART.c **** rxData |= ((uint32) (tmpStatus << 8u)); + 603:Generated_Source\PSoC4/UART_UART.c **** + 604:Generated_Source\PSoC4/UART_UART.c **** return (rxData); + 605:Generated_Source\PSoC4/UART_UART.c **** } + 606:Generated_Source\PSoC4/UART_UART.c **** + 607:Generated_Source\PSoC4/UART_UART.c **** + 608:Generated_Source\PSoC4/UART_UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 609:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 610:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartSetRtsPolarity + 611:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 612:Generated_Source\PSoC4/UART_UART.c **** * + 613:Generated_Source\PSoC4/UART_UART.c **** * Sets active polarity of RTS output signal. + 614:Generated_Source\PSoC4/UART_UART.c **** * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + 615:Generated_Source\PSoC4/UART_UART.c **** * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + 616:Generated_Source\PSoC4/UART_UART.c **** * + 617:Generated_Source\PSoC4/UART_UART.c **** * \param polarity: Active polarity of RTS output signal. + 618:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_RTS_ACTIVE_LOW - RTS signal is active low. + 619:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_RTS_ACTIVE_HIGH - RTS signal is active high. + 620:Generated_Source\PSoC4/UART_UART.c **** * + 621:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 622:Generated_Source\PSoC4/UART_UART.c **** void UART_UartSetRtsPolarity(uint32 polarity) + 623:Generated_Source\PSoC4/UART_UART.c **** { + 624:Generated_Source\PSoC4/UART_UART.c **** if(0u != polarity) + 625:Generated_Source\PSoC4/UART_UART.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 18 + + + 626:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_RTS_POLARITY; + 627:Generated_Source\PSoC4/UART_UART.c **** } + 628:Generated_Source\PSoC4/UART_UART.c **** else + 629:Generated_Source\PSoC4/UART_UART.c **** { + 630:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_RTS_POLARITY; + 631:Generated_Source\PSoC4/UART_UART.c **** } + 632:Generated_Source\PSoC4/UART_UART.c **** } + 633:Generated_Source\PSoC4/UART_UART.c **** + 634:Generated_Source\PSoC4/UART_UART.c **** + 635:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 636:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartSetRtsFifoLevel + 637:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 638:Generated_Source\PSoC4/UART_UART.c **** * + 639:Generated_Source\PSoC4/UART_UART.c **** * Sets level in the RX FIFO for RTS signal activation. + 640:Generated_Source\PSoC4/UART_UART.c **** * While the RX FIFO has fewer entries than the RX FIFO level the RTS signal + 641:Generated_Source\PSoC4/UART_UART.c **** * remains active, otherwise the RTS signal becomes inactive. + 642:Generated_Source\PSoC4/UART_UART.c **** * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + 643:Generated_Source\PSoC4/UART_UART.c **** * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + 644:Generated_Source\PSoC4/UART_UART.c **** * + 645:Generated_Source\PSoC4/UART_UART.c **** * \param level: Level in the RX FIFO for RTS signal activation. + 646:Generated_Source\PSoC4/UART_UART.c **** * The range of valid level values is between 0 and RX FIFO depth - 1. + 647:Generated_Source\PSoC4/UART_UART.c **** * Setting level value to 0 disables RTS signal activation. + 648:Generated_Source\PSoC4/UART_UART.c **** * + 649:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 650:Generated_Source\PSoC4/UART_UART.c **** void UART_UartSetRtsFifoLevel(uint32 level) + 651:Generated_Source\PSoC4/UART_UART.c **** { + 652:Generated_Source\PSoC4/UART_UART.c **** uint32 uartFlowCtrl; + 653:Generated_Source\PSoC4/UART_UART.c **** + 654:Generated_Source\PSoC4/UART_UART.c **** uartFlowCtrl = UART_UART_FLOW_CTRL_REG; + 655:Generated_Source\PSoC4/UART_UART.c **** + 656:Generated_Source\PSoC4/UART_UART.c **** uartFlowCtrl &= ((uint32) ~UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask + 657:Generated_Source\PSoC4/UART_UART.c **** uartFlowCtrl |= ((uint32) (UART_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK & level)); + 658:Generated_Source\PSoC4/UART_UART.c **** + 659:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG = uartFlowCtrl; + 660:Generated_Source\PSoC4/UART_UART.c **** } + 661:Generated_Source\PSoC4/UART_UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 662:Generated_Source\PSoC4/UART_UART.c **** + 663:Generated_Source\PSoC4/UART_UART.c **** #endif /* (UART_UART_RX_DIRECTION) */ + 664:Generated_Source\PSoC4/UART_UART.c **** + 665:Generated_Source\PSoC4/UART_UART.c **** + 666:Generated_Source\PSoC4/UART_UART.c **** #if(UART_UART_TX_DIRECTION) + 667:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 668:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartPutString + 669:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 670:Generated_Source\PSoC4/UART_UART.c **** * + 671:Generated_Source\PSoC4/UART_UART.c **** * Places a NULL terminated string in the transmit buffer to be sent at the + 672:Generated_Source\PSoC4/UART_UART.c **** * next available bus time. + 673:Generated_Source\PSoC4/UART_UART.c **** * This function is blocking and waits until there is a space available to put + 674:Generated_Source\PSoC4/UART_UART.c **** * requested data in transmit buffer. + 675:Generated_Source\PSoC4/UART_UART.c **** * + 676:Generated_Source\PSoC4/UART_UART.c **** * \param string: pointer to the null terminated string array to be placed in the + 677:Generated_Source\PSoC4/UART_UART.c **** * transmit buffer. + 678:Generated_Source\PSoC4/UART_UART.c **** * + 679:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 680:Generated_Source\PSoC4/UART_UART.c **** void UART_UartPutString(const char8 string[]) + 681:Generated_Source\PSoC4/UART_UART.c **** { + 345 .loc 1 681 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 19 + + + 346 .cfi_startproc + 347 @ args = 0, pretend = 0, frame = 16 + 348 @ frame_needed = 1, uses_anonymous_args = 0 + 349 0000 80B5 push {r7, lr} + 350 .cfi_def_cfa_offset 8 + 351 .cfi_offset 7, -8 + 352 .cfi_offset 14, -4 + 353 0002 84B0 sub sp, sp, #16 + 354 .cfi_def_cfa_offset 24 + 355 0004 00AF add r7, sp, #0 + 356 .cfi_def_cfa_register 7 + 357 0006 7860 str r0, [r7, #4] + 682:Generated_Source\PSoC4/UART_UART.c **** uint32 bufIndex; + 683:Generated_Source\PSoC4/UART_UART.c **** + 684:Generated_Source\PSoC4/UART_UART.c **** bufIndex = 0u; + 358 .loc 1 684 0 + 359 0008 0023 movs r3, #0 + 360 000a FB60 str r3, [r7, #12] + 685:Generated_Source\PSoC4/UART_UART.c **** + 686:Generated_Source\PSoC4/UART_UART.c **** /* Blocks the control flow until all data has been sent */ + 687:Generated_Source\PSoC4/UART_UART.c **** while(string[bufIndex] != ((char8) 0)) + 361 .loc 1 687 0 + 362 000c 09E0 b .L17 + 363 .L18: + 688:Generated_Source\PSoC4/UART_UART.c **** { + 689:Generated_Source\PSoC4/UART_UART.c **** UART_UartPutChar((uint32) string[bufIndex]); + 364 .loc 1 689 0 + 365 000e 7A68 ldr r2, [r7, #4] + 366 0010 FB68 ldr r3, [r7, #12] + 367 0012 D318 adds r3, r2, r3 + 368 0014 1B78 ldrb r3, [r3] + 369 0016 1800 movs r0, r3 + 370 0018 FFF7FEFF bl UART_SpiUartWriteTxData + 690:Generated_Source\PSoC4/UART_UART.c **** bufIndex++; + 371 .loc 1 690 0 + 372 001c FB68 ldr r3, [r7, #12] + 373 001e 0133 adds r3, r3, #1 + 374 0020 FB60 str r3, [r7, #12] + 375 .L17: + 687:Generated_Source\PSoC4/UART_UART.c **** { + 376 .loc 1 687 0 + 377 0022 7A68 ldr r2, [r7, #4] + 378 0024 FB68 ldr r3, [r7, #12] + 379 0026 D318 adds r3, r2, r3 + 380 0028 1B78 ldrb r3, [r3] + 381 002a 002B cmp r3, #0 + 382 002c EFD1 bne .L18 + 691:Generated_Source\PSoC4/UART_UART.c **** } + 692:Generated_Source\PSoC4/UART_UART.c **** } + 383 .loc 1 692 0 + 384 002e C046 nop + 385 0030 BD46 mov sp, r7 + 386 0032 04B0 add sp, sp, #16 + 387 @ sp needed + 388 0034 80BD pop {r7, pc} + 389 .cfi_endproc + 390 .LFE5: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 20 + + + 391 .size UART_UartPutString, .-UART_UartPutString + 392 0036 C046 .section .text.UART_UartPutCRLF,"ax",%progbits + 393 .align 2 + 394 .global UART_UartPutCRLF + 395 .code 16 + 396 .thumb_func + 397 .type UART_UartPutCRLF, %function + 398 UART_UartPutCRLF: + 399 .LFB6: + 693:Generated_Source\PSoC4/UART_UART.c **** + 694:Generated_Source\PSoC4/UART_UART.c **** + 695:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 696:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartPutCRLF + 697:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 698:Generated_Source\PSoC4/UART_UART.c **** * + 699:Generated_Source\PSoC4/UART_UART.c **** * Places byte of data followed by a carriage return (0x0D) and line feed + 700:Generated_Source\PSoC4/UART_UART.c **** * (0x0A) in the transmit buffer. + 701:Generated_Source\PSoC4/UART_UART.c **** * This function is blocking and waits until there is a space available to put + 702:Generated_Source\PSoC4/UART_UART.c **** * all requested data in transmit buffer. + 703:Generated_Source\PSoC4/UART_UART.c **** * + 704:Generated_Source\PSoC4/UART_UART.c **** * \param txDataByte: the data to be transmitted. + 705:Generated_Source\PSoC4/UART_UART.c **** * + 706:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 707:Generated_Source\PSoC4/UART_UART.c **** void UART_UartPutCRLF(uint32 txDataByte) + 708:Generated_Source\PSoC4/UART_UART.c **** { + 400 .loc 1 708 0 + 401 .cfi_startproc + 402 @ args = 0, pretend = 0, frame = 8 + 403 @ frame_needed = 1, uses_anonymous_args = 0 + 404 0000 80B5 push {r7, lr} + 405 .cfi_def_cfa_offset 8 + 406 .cfi_offset 7, -8 + 407 .cfi_offset 14, -4 + 408 0002 82B0 sub sp, sp, #8 + 409 .cfi_def_cfa_offset 16 + 410 0004 00AF add r7, sp, #0 + 411 .cfi_def_cfa_register 7 + 412 0006 7860 str r0, [r7, #4] + 709:Generated_Source\PSoC4/UART_UART.c **** UART_UartPutChar(txDataByte); /* Blocks control flow until all data has been sent */ + 413 .loc 1 709 0 + 414 0008 7B68 ldr r3, [r7, #4] + 415 000a 1800 movs r0, r3 + 416 000c FFF7FEFF bl UART_SpiUartWriteTxData + 710:Generated_Source\PSoC4/UART_UART.c **** UART_UartPutChar(0x0Du); /* Blocks control flow until all data has been sent */ + 417 .loc 1 710 0 + 418 0010 0D20 movs r0, #13 + 419 0012 FFF7FEFF bl UART_SpiUartWriteTxData + 711:Generated_Source\PSoC4/UART_UART.c **** UART_UartPutChar(0x0Au); /* Blocks control flow until all data has been sent */ + 420 .loc 1 711 0 + 421 0016 0A20 movs r0, #10 + 422 0018 FFF7FEFF bl UART_SpiUartWriteTxData + 712:Generated_Source\PSoC4/UART_UART.c **** } + 423 .loc 1 712 0 + 424 001c C046 nop + 425 001e BD46 mov sp, r7 + 426 0020 02B0 add sp, sp, #8 + 427 @ sp needed + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 21 + + + 428 0022 80BD pop {r7, pc} + 429 .cfi_endproc + 430 .LFE6: + 431 .size UART_UartPutCRLF, .-UART_UartPutCRLF + 432 .section .text.UART_UartSendBreakBlocking,"ax",%progbits + 433 .align 2 + 434 .global UART_UartSendBreakBlocking + 435 .code 16 + 436 .thumb_func + 437 .type UART_UartSendBreakBlocking, %function + 438 UART_UartSendBreakBlocking: + 439 .LFB7: + 713:Generated_Source\PSoC4/UART_UART.c **** + 714:Generated_Source\PSoC4/UART_UART.c **** + 715:Generated_Source\PSoC4/UART_UART.c **** #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) + 716:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 717:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UARTSCB_UartEnableCts + 718:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 719:Generated_Source\PSoC4/UART_UART.c **** * + 720:Generated_Source\PSoC4/UART_UART.c **** * Enables usage of CTS input signal by the UART transmitter. + 721:Generated_Source\PSoC4/UART_UART.c **** * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + 722:Generated_Source\PSoC4/UART_UART.c **** * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + 723:Generated_Source\PSoC4/UART_UART.c **** * + 724:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 725:Generated_Source\PSoC4/UART_UART.c **** void UART_UartEnableCts(void) + 726:Generated_Source\PSoC4/UART_UART.c **** { + 727:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_CTS_ENABLE; + 728:Generated_Source\PSoC4/UART_UART.c **** } + 729:Generated_Source\PSoC4/UART_UART.c **** + 730:Generated_Source\PSoC4/UART_UART.c **** + 731:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 732:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartDisableCts + 733:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 734:Generated_Source\PSoC4/UART_UART.c **** * + 735:Generated_Source\PSoC4/UART_UART.c **** * Disables usage of CTS input signal by the UART transmitter. + 736:Generated_Source\PSoC4/UART_UART.c **** * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + 737:Generated_Source\PSoC4/UART_UART.c **** * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + 738:Generated_Source\PSoC4/UART_UART.c **** * + 739:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 740:Generated_Source\PSoC4/UART_UART.c **** void UART_UartDisableCts(void) + 741:Generated_Source\PSoC4/UART_UART.c **** { + 742:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_CTS_ENABLE; + 743:Generated_Source\PSoC4/UART_UART.c **** } + 744:Generated_Source\PSoC4/UART_UART.c **** + 745:Generated_Source\PSoC4/UART_UART.c **** + 746:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 747:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartSetCtsPolarity + 748:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 749:Generated_Source\PSoC4/UART_UART.c **** * + 750:Generated_Source\PSoC4/UART_UART.c **** * Sets active polarity of CTS input signal. + 751:Generated_Source\PSoC4/UART_UART.c **** * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + 752:Generated_Source\PSoC4/UART_UART.c **** * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + 753:Generated_Source\PSoC4/UART_UART.c **** * + 754:Generated_Source\PSoC4/UART_UART.c **** * \param + 755:Generated_Source\PSoC4/UART_UART.c **** * polarity: Active polarity of CTS output signal. + 756:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_CTS_ACTIVE_LOW - CTS signal is active low. + 757:Generated_Source\PSoC4/UART_UART.c **** * - UART_UART_CTS_ACTIVE_HIGH - CTS signal is active high. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 22 + + + 758:Generated_Source\PSoC4/UART_UART.c **** * + 759:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 760:Generated_Source\PSoC4/UART_UART.c **** void UART_UartSetCtsPolarity(uint32 polarity) + 761:Generated_Source\PSoC4/UART_UART.c **** { + 762:Generated_Source\PSoC4/UART_UART.c **** if (0u != polarity) + 763:Generated_Source\PSoC4/UART_UART.c **** { + 764:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG |= (uint32) UART_UART_FLOW_CTRL_CTS_POLARITY; + 765:Generated_Source\PSoC4/UART_UART.c **** } + 766:Generated_Source\PSoC4/UART_UART.c **** else + 767:Generated_Source\PSoC4/UART_UART.c **** { + 768:Generated_Source\PSoC4/UART_UART.c **** UART_UART_FLOW_CTRL_REG &= (uint32) ~UART_UART_FLOW_CTRL_CTS_POLARITY; + 769:Generated_Source\PSoC4/UART_UART.c **** } + 770:Generated_Source\PSoC4/UART_UART.c **** } + 771:Generated_Source\PSoC4/UART_UART.c **** #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ + 772:Generated_Source\PSoC4/UART_UART.c **** + 773:Generated_Source\PSoC4/UART_UART.c **** + 774:Generated_Source\PSoC4/UART_UART.c **** /******************************************************************************* + 775:Generated_Source\PSoC4/UART_UART.c **** * Function Name: UART_UartSendBreakBlocking + 776:Generated_Source\PSoC4/UART_UART.c **** ****************************************************************************//** + 777:Generated_Source\PSoC4/UART_UART.c **** * + 778:Generated_Source\PSoC4/UART_UART.c **** * Sends a break condition (logic low) of specified width on UART TX line. + 779:Generated_Source\PSoC4/UART_UART.c **** * Blocks until break is completed. Only call this function when UART TX FIFO + 780:Generated_Source\PSoC4/UART_UART.c **** * and shifter are empty. + 781:Generated_Source\PSoC4/UART_UART.c **** * + 782:Generated_Source\PSoC4/UART_UART.c **** * \param breakWidth + 783:Generated_Source\PSoC4/UART_UART.c **** * Width of break condition. Valid range is 4 to 16 bits. + 784:Generated_Source\PSoC4/UART_UART.c **** * + 785:Generated_Source\PSoC4/UART_UART.c **** * \note + 786:Generated_Source\PSoC4/UART_UART.c **** * Before sending break all UART TX interrupt sources are disabled. The state + 787:Generated_Source\PSoC4/UART_UART.c **** * of UART TX interrupt sources is restored before function returns. + 788:Generated_Source\PSoC4/UART_UART.c **** * + 789:Generated_Source\PSoC4/UART_UART.c **** * \sideeffect + 790:Generated_Source\PSoC4/UART_UART.c **** * If this function is called while there is data in the TX FIFO or shifter that + 791:Generated_Source\PSoC4/UART_UART.c **** * data will be shifted out in packets the size of breakWidth. + 792:Generated_Source\PSoC4/UART_UART.c **** * + 793:Generated_Source\PSoC4/UART_UART.c **** *******************************************************************************/ + 794:Generated_Source\PSoC4/UART_UART.c **** void UART_UartSendBreakBlocking(uint32 breakWidth) + 795:Generated_Source\PSoC4/UART_UART.c **** { + 440 .loc 1 795 0 + 441 .cfi_startproc + 442 @ args = 0, pretend = 0, frame = 16 + 443 @ frame_needed = 1, uses_anonymous_args = 0 + 444 0000 80B5 push {r7, lr} + 445 .cfi_def_cfa_offset 8 + 446 .cfi_offset 7, -8 + 447 .cfi_offset 14, -4 + 448 0002 84B0 sub sp, sp, #16 + 449 .cfi_def_cfa_offset 24 + 450 0004 00AF add r7, sp, #0 + 451 .cfi_def_cfa_register 7 + 452 0006 7860 str r0, [r7, #4] + 796:Generated_Source\PSoC4/UART_UART.c **** uint32 txCtrlReg; + 797:Generated_Source\PSoC4/UART_UART.c **** uint32 txIntrReg; + 798:Generated_Source\PSoC4/UART_UART.c **** + 799:Generated_Source\PSoC4/UART_UART.c **** /* Disable all UART TX interrupt source and clear UART TX Done history */ + 800:Generated_Source\PSoC4/UART_UART.c **** txIntrReg = UART_GetTxInterruptMode(); + 453 .loc 1 800 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 23 + + + 454 0008 174B ldr r3, .L22 + 455 000a 1B68 ldr r3, [r3] + 456 000c FB60 str r3, [r7, #12] + 801:Generated_Source\PSoC4/UART_UART.c **** UART_SetTxInterruptMode(0u); + 457 .loc 1 801 0 + 458 000e 164B ldr r3, .L22 + 459 0010 0022 movs r2, #0 + 460 0012 1A60 str r2, [r3] + 802:Generated_Source\PSoC4/UART_UART.c **** UART_ClearTxInterruptSource(UART_INTR_TX_UART_DONE); + 461 .loc 1 802 0 + 462 0014 154B ldr r3, .L22+4 + 463 0016 8022 movs r2, #128 + 464 0018 9200 lsls r2, r2, #2 + 465 001a 1A60 str r2, [r3] + 803:Generated_Source\PSoC4/UART_UART.c **** + 804:Generated_Source\PSoC4/UART_UART.c **** /* Store TX CTRL configuration */ + 805:Generated_Source\PSoC4/UART_UART.c **** txCtrlReg = UART_TX_CTRL_REG; + 466 .loc 1 805 0 + 467 001c 144B ldr r3, .L22+8 + 468 001e 1B68 ldr r3, [r3] + 469 0020 BB60 str r3, [r7, #8] + 806:Generated_Source\PSoC4/UART_UART.c **** + 807:Generated_Source\PSoC4/UART_UART.c **** /* Set break width */ + 808:Generated_Source\PSoC4/UART_UART.c **** UART_TX_CTRL_REG = (UART_TX_CTRL_REG & (uint32) ~UART_TX_CTRL_DATA_WIDTH_MASK) | + 470 .loc 1 808 0 + 471 0022 134B ldr r3, .L22+8 + 472 0024 124A ldr r2, .L22+8 + 473 0026 1268 ldr r2, [r2] + 474 0028 0F21 movs r1, #15 + 475 002a 8A43 bics r2, r1 + 476 002c 1100 movs r1, r2 + 809:Generated_Source\PSoC4/UART_UART.c **** UART_GET_TX_CTRL_DATA_WIDTH(breakWidth); + 477 .loc 1 809 0 + 478 002e 7A68 ldr r2, [r7, #4] + 479 0030 013A subs r2, r2, #1 + 480 0032 0F20 movs r0, #15 + 481 0034 0240 ands r2, r0 + 808:Generated_Source\PSoC4/UART_UART.c **** UART_GET_TX_CTRL_DATA_WIDTH(breakWidth); + 482 .loc 1 808 0 + 483 0036 0A43 orrs r2, r1 + 484 0038 1A60 str r2, [r3] + 810:Generated_Source\PSoC4/UART_UART.c **** + 811:Generated_Source\PSoC4/UART_UART.c **** /* Generate break */ + 812:Generated_Source\PSoC4/UART_UART.c **** UART_TX_FIFO_WR_REG = 0u; + 485 .loc 1 812 0 + 486 003a 0E4B ldr r3, .L22+12 + 487 003c 0022 movs r2, #0 + 488 003e 1A60 str r2, [r3] + 813:Generated_Source\PSoC4/UART_UART.c **** + 814:Generated_Source\PSoC4/UART_UART.c **** /* Wait for break completion */ + 815:Generated_Source\PSoC4/UART_UART.c **** while (0u == (UART_GetTxInterruptSource() & UART_INTR_TX_UART_DONE)) + 489 .loc 1 815 0 + 490 0040 C046 nop + 491 .L21: + 492 .loc 1 815 0 is_stmt 0 discriminator 1 + 493 0042 0A4B ldr r3, .L22+4 + 494 0044 1A68 ldr r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 24 + + + 495 0046 8023 movs r3, #128 + 496 0048 9B00 lsls r3, r3, #2 + 497 004a 1340 ands r3, r2 + 498 004c F9D0 beq .L21 + 816:Generated_Source\PSoC4/UART_UART.c **** { + 817:Generated_Source\PSoC4/UART_UART.c **** } + 818:Generated_Source\PSoC4/UART_UART.c **** + 819:Generated_Source\PSoC4/UART_UART.c **** /* Clear all UART TX interrupt sources to */ + 820:Generated_Source\PSoC4/UART_UART.c **** UART_ClearTxInterruptSource(UART_INTR_TX_ALL); + 499 .loc 1 820 0 is_stmt 1 + 500 004e 074B ldr r3, .L22+4 + 501 0050 094A ldr r2, .L22+16 + 502 0052 1A60 str r2, [r3] + 821:Generated_Source\PSoC4/UART_UART.c **** + 822:Generated_Source\PSoC4/UART_UART.c **** /* Restore TX interrupt sources and data width */ + 823:Generated_Source\PSoC4/UART_UART.c **** UART_TX_CTRL_REG = txCtrlReg; + 503 .loc 1 823 0 + 504 0054 064B ldr r3, .L22+8 + 505 0056 BA68 ldr r2, [r7, #8] + 506 0058 1A60 str r2, [r3] + 824:Generated_Source\PSoC4/UART_UART.c **** UART_SetTxInterruptMode(txIntrReg); + 507 .loc 1 824 0 + 508 005a 034B ldr r3, .L22 + 509 005c FA68 ldr r2, [r7, #12] + 510 005e 1A60 str r2, [r3] + 825:Generated_Source\PSoC4/UART_UART.c **** } + 511 .loc 1 825 0 + 512 0060 C046 nop + 513 0062 BD46 mov sp, r7 + 514 0064 04B0 add sp, sp, #16 + 515 @ sp needed + 516 0066 80BD pop {r7, pc} + 517 .L23: + 518 .align 2 + 519 .L22: + 520 0068 880F0640 .word 1074139016 + 521 006c 800F0640 .word 1074139008 + 522 0070 00020640 .word 1074135552 + 523 0074 40020640 .word 1074135616 + 524 0078 F3070000 .word 2035 + 525 .cfi_endproc + 526 .LFE7: + 527 .size UART_UartSendBreakBlocking, .-UART_UartSendBreakBlocking + 528 .text + 529 .Letext0: + 530 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 531 .file 3 "Generated_Source\\PSoC4\\UART_PVT.h" + 532 .section .debug_info,"",%progbits + 533 .Ldebug_info0: + 534 0000 14020000 .4byte 0x214 + 535 0004 0400 .2byte 0x4 + 536 0006 00000000 .4byte .Ldebug_abbrev0 + 537 000a 04 .byte 0x4 + 538 000b 01 .uleb128 0x1 + 539 000c 55010000 .4byte .LASF35 + 540 0010 0C .byte 0xc + 541 0011 9E020000 .4byte .LASF36 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 25 + + + 542 0015 5E000000 .4byte .LASF37 + 543 0019 00000000 .4byte .Ldebug_ranges0+0 + 544 001d 00000000 .4byte 0 + 545 0021 00000000 .4byte .Ldebug_line0 + 546 0025 02 .uleb128 0x2 + 547 0026 01 .byte 0x1 + 548 0027 06 .byte 0x6 + 549 0028 C1020000 .4byte .LASF0 + 550 002c 02 .uleb128 0x2 + 551 002d 01 .byte 0x1 + 552 002e 08 .byte 0x8 + 553 002f E9000000 .4byte .LASF1 + 554 0033 02 .uleb128 0x2 + 555 0034 02 .byte 0x2 + 556 0035 05 .byte 0x5 + 557 0036 76020000 .4byte .LASF2 + 558 003a 02 .uleb128 0x2 + 559 003b 02 .byte 0x2 + 560 003c 07 .byte 0x7 + 561 003d 31010000 .4byte .LASF3 + 562 0041 02 .uleb128 0x2 + 563 0042 04 .byte 0x4 + 564 0043 05 .byte 0x5 + 565 0044 80020000 .4byte .LASF4 + 566 0048 02 .uleb128 0x2 + 567 0049 04 .byte 0x4 + 568 004a 07 .byte 0x7 + 569 004b 11010000 .4byte .LASF5 + 570 004f 02 .uleb128 0x2 + 571 0050 08 .byte 0x8 + 572 0051 05 .byte 0x5 + 573 0052 00000000 .4byte .LASF6 + 574 0056 02 .uleb128 0x2 + 575 0057 08 .byte 0x8 + 576 0058 07 .byte 0x7 + 577 0059 3D020000 .4byte .LASF7 + 578 005d 03 .uleb128 0x3 + 579 005e 04 .byte 0x4 + 580 005f 05 .byte 0x5 + 581 0060 696E7400 .ascii "int\000" + 582 0064 02 .uleb128 0x2 + 583 0065 04 .byte 0x4 + 584 0066 07 .byte 0x7 + 585 0067 1A020000 .4byte .LASF8 + 586 006b 04 .uleb128 0x4 + 587 006c 0C020000 .4byte .LASF9 + 588 0070 02 .byte 0x2 + 589 0071 E501 .2byte 0x1e5 + 590 0073 3A000000 .4byte 0x3a + 591 0077 04 .uleb128 0x4 + 592 0078 13020000 .4byte .LASF10 + 593 007c 02 .byte 0x2 + 594 007d E601 .2byte 0x1e6 + 595 007f 48000000 .4byte 0x48 + 596 0083 02 .uleb128 0x2 + 597 0084 04 .byte 0x4 + 598 0085 04 .byte 0x4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 26 + + + 599 0086 3E000000 .4byte .LASF11 + 600 008a 02 .uleb128 0x2 + 601 008b 08 .byte 0x8 + 602 008c 04 .byte 0x4 + 603 008d EF010000 .4byte .LASF12 + 604 0091 04 .uleb128 0x4 + 605 0092 F7000000 .4byte .LASF13 + 606 0096 02 .byte 0x2 + 607 0097 F501 .2byte 0x1f5 + 608 0099 9D000000 .4byte 0x9d + 609 009d 02 .uleb128 0x2 + 610 009e 01 .byte 0x1 + 611 009f 08 .byte 0x8 + 612 00a0 71020000 .4byte .LASF14 + 613 00a4 04 .uleb128 0x4 + 614 00a5 0E000000 .4byte .LASF15 + 615 00a9 02 .byte 0x2 + 616 00aa 9002 .2byte 0x290 + 617 00ac B0000000 .4byte 0xb0 + 618 00b0 05 .uleb128 0x5 + 619 00b1 77000000 .4byte 0x77 + 620 00b5 02 .uleb128 0x2 + 621 00b6 08 .byte 0x8 + 622 00b7 04 .byte 0x4 + 623 00b8 92020000 .4byte .LASF16 + 624 00bc 02 .uleb128 0x2 + 625 00bd 04 .byte 0x4 + 626 00be 07 .byte 0x7 + 627 00bf 5D020000 .4byte .LASF17 + 628 00c3 06 .uleb128 0x6 + 629 00c4 27020000 .4byte .LASF18 + 630 00c8 01 .byte 0x1 + 631 00c9 F7 .byte 0xf7 + 632 00ca 00000000 .4byte .LFB0 + 633 00ce BC000000 .4byte .LFE0-.LFB0 + 634 00d2 01 .uleb128 0x1 + 635 00d3 9C .byte 0x9c + 636 00d4 07 .uleb128 0x7 + 637 00d5 FD000000 .4byte .LASF19 + 638 00d9 01 .byte 0x1 + 639 00da 3D01 .2byte 0x13d + 640 00dc 00000000 .4byte .LFB1 + 641 00e0 30000000 .4byte .LFE1-.LFB1 + 642 00e4 01 .uleb128 0x1 + 643 00e5 9C .byte 0x9c + 644 00e6 07 .uleb128 0x7 + 645 00e7 23010000 .4byte .LASF20 + 646 00eb 01 .byte 0x1 + 647 00ec 7101 .2byte 0x171 + 648 00ee 00000000 .4byte .LFB2 + 649 00f2 34000000 .4byte .LFE2-.LFB2 + 650 00f6 01 .uleb128 0x1 + 651 00f7 9C .byte 0x9c + 652 00f8 08 .uleb128 0x8 + 653 00f9 F6010000 .4byte .LASF21 + 654 00fd 01 .byte 0x1 + 655 00fe B101 .2byte 0x1b1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 27 + + + 656 0100 00000000 .4byte .LFB3 + 657 0104 34000000 .4byte .LFE3-.LFB3 + 658 0108 01 .uleb128 0x1 + 659 0109 9C .byte 0x9c + 660 010a 2D010000 .4byte 0x12d + 661 010e 09 .uleb128 0x9 + 662 010f 35020000 .4byte .LASF23 + 663 0113 01 .byte 0x1 + 664 0114 B101 .2byte 0x1b1 + 665 0116 77000000 .4byte 0x77 + 666 011a 02 .uleb128 0x2 + 667 011b 91 .byte 0x91 + 668 011c 6C .sleb128 -20 + 669 011d 0A .uleb128 0xa + 670 011e 89020000 .4byte .LASF25 + 671 0122 01 .byte 0x1 + 672 0123 B301 .2byte 0x1b3 + 673 0125 77000000 .4byte 0x77 + 674 0129 02 .uleb128 0x2 + 675 012a 91 .byte 0x91 + 676 012b 74 .sleb128 -12 + 677 012c 00 .byte 0 + 678 012d 08 .uleb128 0x8 + 679 012e 24000000 .4byte .LASF22 + 680 0132 01 .byte 0x1 + 681 0133 CA01 .2byte 0x1ca + 682 0135 00000000 .4byte .LFB4 + 683 0139 38000000 .4byte .LFE4-.LFB4 + 684 013d 01 .uleb128 0x1 + 685 013e 9C .byte 0x9c + 686 013f 62010000 .4byte 0x162 + 687 0143 09 .uleb128 0x9 + 688 0144 E3010000 .4byte .LASF24 + 689 0148 01 .byte 0x1 + 690 0149 CA01 .2byte 0x1ca + 691 014b 77000000 .4byte 0x77 + 692 014f 02 .uleb128 0x2 + 693 0150 91 .byte 0x91 + 694 0151 6C .sleb128 -20 + 695 0152 0A .uleb128 0xa + 696 0153 89020000 .4byte .LASF25 + 697 0157 01 .byte 0x1 + 698 0158 CC01 .2byte 0x1cc + 699 015a 77000000 .4byte 0x77 + 700 015e 02 .uleb128 0x2 + 701 015f 91 .byte 0x91 + 702 0160 74 .sleb128 -12 + 703 0161 00 .byte 0 + 704 0162 0B .uleb128 0xb + 705 0163 4B000000 .4byte .LASF26 + 706 0167 01 .byte 0x1 + 707 0168 A802 .2byte 0x2a8 + 708 016a 00000000 .4byte .LFB5 + 709 016e 36000000 .4byte .LFE5-.LFB5 + 710 0172 01 .uleb128 0x1 + 711 0173 9C .byte 0x9c + 712 0174 97010000 .4byte 0x197 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 28 + + + 713 0178 09 .uleb128 0x9 + 714 0179 44000000 .4byte .LASF27 + 715 017d 01 .byte 0x1 + 716 017e A802 .2byte 0x2a8 + 717 0180 97010000 .4byte 0x197 + 718 0184 02 .uleb128 0x2 + 719 0185 91 .byte 0x91 + 720 0186 6C .sleb128 -20 + 721 0187 0A .uleb128 0xa + 722 0188 54020000 .4byte .LASF28 + 723 018c 01 .byte 0x1 + 724 018d AA02 .2byte 0x2aa + 725 018f 77000000 .4byte 0x77 + 726 0193 02 .uleb128 0x2 + 727 0194 91 .byte 0x91 + 728 0195 74 .sleb128 -12 + 729 0196 00 .byte 0 + 730 0197 0C .uleb128 0xc + 731 0198 04 .byte 0x4 + 732 0199 9D010000 .4byte 0x19d + 733 019d 0D .uleb128 0xd + 734 019e 91000000 .4byte 0x91 + 735 01a2 0B .uleb128 0xb + 736 01a3 44010000 .4byte .LASF29 + 737 01a7 01 .byte 0x1 + 738 01a8 C302 .2byte 0x2c3 + 739 01aa 00000000 .4byte .LFB6 + 740 01ae 24000000 .4byte .LFE6-.LFB6 + 741 01b2 01 .uleb128 0x1 + 742 01b3 9C .byte 0x9c + 743 01b4 C8010000 .4byte 0x1c8 + 744 01b8 09 .uleb128 0x9 + 745 01b9 66020000 .4byte .LASF30 + 746 01bd 01 .byte 0x1 + 747 01be C302 .2byte 0x2c3 + 748 01c0 77000000 .4byte 0x77 + 749 01c4 02 .uleb128 0x2 + 750 01c5 91 .byte 0x91 + 751 01c6 74 .sleb128 -12 + 752 01c7 00 .byte 0 + 753 01c8 08 .uleb128 0x8 + 754 01c9 C4000000 .4byte .LASF31 + 755 01cd 01 .byte 0x1 + 756 01ce 1A03 .2byte 0x31a + 757 01d0 00000000 .4byte .LFB7 + 758 01d4 7C000000 .4byte .LFE7-.LFB7 + 759 01d8 01 .uleb128 0x1 + 760 01d9 9C .byte 0x9c + 761 01da 0C020000 .4byte 0x20c + 762 01de 09 .uleb128 0x9 + 763 01df B9000000 .4byte .LASF32 + 764 01e3 01 .byte 0x1 + 765 01e4 1A03 .2byte 0x31a + 766 01e6 77000000 .4byte 0x77 + 767 01ea 02 .uleb128 0x2 + 768 01eb 91 .byte 0x91 + 769 01ec 6C .sleb128 -20 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 29 + + + 770 01ed 0A .uleb128 0xa + 771 01ee CD020000 .4byte .LASF33 + 772 01f2 01 .byte 0x1 + 773 01f3 1C03 .2byte 0x31c + 774 01f5 77000000 .4byte 0x77 + 775 01f9 02 .uleb128 0x2 + 776 01fa 91 .byte 0x91 + 777 01fb 70 .sleb128 -16 + 778 01fc 0A .uleb128 0xa + 779 01fd DF000000 .4byte .LASF34 + 780 0201 01 .byte 0x1 + 781 0202 1D03 .2byte 0x31d + 782 0204 77000000 .4byte 0x77 + 783 0208 02 .uleb128 0x2 + 784 0209 91 .byte 0x91 + 785 020a 74 .sleb128 -12 + 786 020b 00 .byte 0 + 787 020c 0E .uleb128 0xe + 788 020d 14000000 .4byte .LASF38 + 789 0211 03 .byte 0x3 + 790 0212 5B .byte 0x5b + 791 0213 6B000000 .4byte 0x6b + 792 0217 00 .byte 0 + 793 .section .debug_abbrev,"",%progbits + 794 .Ldebug_abbrev0: + 795 0000 01 .uleb128 0x1 + 796 0001 11 .uleb128 0x11 + 797 0002 01 .byte 0x1 + 798 0003 25 .uleb128 0x25 + 799 0004 0E .uleb128 0xe + 800 0005 13 .uleb128 0x13 + 801 0006 0B .uleb128 0xb + 802 0007 03 .uleb128 0x3 + 803 0008 0E .uleb128 0xe + 804 0009 1B .uleb128 0x1b + 805 000a 0E .uleb128 0xe + 806 000b 55 .uleb128 0x55 + 807 000c 17 .uleb128 0x17 + 808 000d 11 .uleb128 0x11 + 809 000e 01 .uleb128 0x1 + 810 000f 10 .uleb128 0x10 + 811 0010 17 .uleb128 0x17 + 812 0011 00 .byte 0 + 813 0012 00 .byte 0 + 814 0013 02 .uleb128 0x2 + 815 0014 24 .uleb128 0x24 + 816 0015 00 .byte 0 + 817 0016 0B .uleb128 0xb + 818 0017 0B .uleb128 0xb + 819 0018 3E .uleb128 0x3e + 820 0019 0B .uleb128 0xb + 821 001a 03 .uleb128 0x3 + 822 001b 0E .uleb128 0xe + 823 001c 00 .byte 0 + 824 001d 00 .byte 0 + 825 001e 03 .uleb128 0x3 + 826 001f 24 .uleb128 0x24 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 30 + + + 827 0020 00 .byte 0 + 828 0021 0B .uleb128 0xb + 829 0022 0B .uleb128 0xb + 830 0023 3E .uleb128 0x3e + 831 0024 0B .uleb128 0xb + 832 0025 03 .uleb128 0x3 + 833 0026 08 .uleb128 0x8 + 834 0027 00 .byte 0 + 835 0028 00 .byte 0 + 836 0029 04 .uleb128 0x4 + 837 002a 16 .uleb128 0x16 + 838 002b 00 .byte 0 + 839 002c 03 .uleb128 0x3 + 840 002d 0E .uleb128 0xe + 841 002e 3A .uleb128 0x3a + 842 002f 0B .uleb128 0xb + 843 0030 3B .uleb128 0x3b + 844 0031 05 .uleb128 0x5 + 845 0032 49 .uleb128 0x49 + 846 0033 13 .uleb128 0x13 + 847 0034 00 .byte 0 + 848 0035 00 .byte 0 + 849 0036 05 .uleb128 0x5 + 850 0037 35 .uleb128 0x35 + 851 0038 00 .byte 0 + 852 0039 49 .uleb128 0x49 + 853 003a 13 .uleb128 0x13 + 854 003b 00 .byte 0 + 855 003c 00 .byte 0 + 856 003d 06 .uleb128 0x6 + 857 003e 2E .uleb128 0x2e + 858 003f 00 .byte 0 + 859 0040 3F .uleb128 0x3f + 860 0041 19 .uleb128 0x19 + 861 0042 03 .uleb128 0x3 + 862 0043 0E .uleb128 0xe + 863 0044 3A .uleb128 0x3a + 864 0045 0B .uleb128 0xb + 865 0046 3B .uleb128 0x3b + 866 0047 0B .uleb128 0xb + 867 0048 27 .uleb128 0x27 + 868 0049 19 .uleb128 0x19 + 869 004a 11 .uleb128 0x11 + 870 004b 01 .uleb128 0x1 + 871 004c 12 .uleb128 0x12 + 872 004d 06 .uleb128 0x6 + 873 004e 40 .uleb128 0x40 + 874 004f 18 .uleb128 0x18 + 875 0050 9742 .uleb128 0x2117 + 876 0052 19 .uleb128 0x19 + 877 0053 00 .byte 0 + 878 0054 00 .byte 0 + 879 0055 07 .uleb128 0x7 + 880 0056 2E .uleb128 0x2e + 881 0057 00 .byte 0 + 882 0058 3F .uleb128 0x3f + 883 0059 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 31 + + + 884 005a 03 .uleb128 0x3 + 885 005b 0E .uleb128 0xe + 886 005c 3A .uleb128 0x3a + 887 005d 0B .uleb128 0xb + 888 005e 3B .uleb128 0x3b + 889 005f 05 .uleb128 0x5 + 890 0060 27 .uleb128 0x27 + 891 0061 19 .uleb128 0x19 + 892 0062 11 .uleb128 0x11 + 893 0063 01 .uleb128 0x1 + 894 0064 12 .uleb128 0x12 + 895 0065 06 .uleb128 0x6 + 896 0066 40 .uleb128 0x40 + 897 0067 18 .uleb128 0x18 + 898 0068 9742 .uleb128 0x2117 + 899 006a 19 .uleb128 0x19 + 900 006b 00 .byte 0 + 901 006c 00 .byte 0 + 902 006d 08 .uleb128 0x8 + 903 006e 2E .uleb128 0x2e + 904 006f 01 .byte 0x1 + 905 0070 3F .uleb128 0x3f + 906 0071 19 .uleb128 0x19 + 907 0072 03 .uleb128 0x3 + 908 0073 0E .uleb128 0xe + 909 0074 3A .uleb128 0x3a + 910 0075 0B .uleb128 0xb + 911 0076 3B .uleb128 0x3b + 912 0077 05 .uleb128 0x5 + 913 0078 27 .uleb128 0x27 + 914 0079 19 .uleb128 0x19 + 915 007a 11 .uleb128 0x11 + 916 007b 01 .uleb128 0x1 + 917 007c 12 .uleb128 0x12 + 918 007d 06 .uleb128 0x6 + 919 007e 40 .uleb128 0x40 + 920 007f 18 .uleb128 0x18 + 921 0080 9742 .uleb128 0x2117 + 922 0082 19 .uleb128 0x19 + 923 0083 01 .uleb128 0x1 + 924 0084 13 .uleb128 0x13 + 925 0085 00 .byte 0 + 926 0086 00 .byte 0 + 927 0087 09 .uleb128 0x9 + 928 0088 05 .uleb128 0x5 + 929 0089 00 .byte 0 + 930 008a 03 .uleb128 0x3 + 931 008b 0E .uleb128 0xe + 932 008c 3A .uleb128 0x3a + 933 008d 0B .uleb128 0xb + 934 008e 3B .uleb128 0x3b + 935 008f 05 .uleb128 0x5 + 936 0090 49 .uleb128 0x49 + 937 0091 13 .uleb128 0x13 + 938 0092 02 .uleb128 0x2 + 939 0093 18 .uleb128 0x18 + 940 0094 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 32 + + + 941 0095 00 .byte 0 + 942 0096 0A .uleb128 0xa + 943 0097 34 .uleb128 0x34 + 944 0098 00 .byte 0 + 945 0099 03 .uleb128 0x3 + 946 009a 0E .uleb128 0xe + 947 009b 3A .uleb128 0x3a + 948 009c 0B .uleb128 0xb + 949 009d 3B .uleb128 0x3b + 950 009e 05 .uleb128 0x5 + 951 009f 49 .uleb128 0x49 + 952 00a0 13 .uleb128 0x13 + 953 00a1 02 .uleb128 0x2 + 954 00a2 18 .uleb128 0x18 + 955 00a3 00 .byte 0 + 956 00a4 00 .byte 0 + 957 00a5 0B .uleb128 0xb + 958 00a6 2E .uleb128 0x2e + 959 00a7 01 .byte 0x1 + 960 00a8 3F .uleb128 0x3f + 961 00a9 19 .uleb128 0x19 + 962 00aa 03 .uleb128 0x3 + 963 00ab 0E .uleb128 0xe + 964 00ac 3A .uleb128 0x3a + 965 00ad 0B .uleb128 0xb + 966 00ae 3B .uleb128 0x3b + 967 00af 05 .uleb128 0x5 + 968 00b0 27 .uleb128 0x27 + 969 00b1 19 .uleb128 0x19 + 970 00b2 11 .uleb128 0x11 + 971 00b3 01 .uleb128 0x1 + 972 00b4 12 .uleb128 0x12 + 973 00b5 06 .uleb128 0x6 + 974 00b6 40 .uleb128 0x40 + 975 00b7 18 .uleb128 0x18 + 976 00b8 9642 .uleb128 0x2116 + 977 00ba 19 .uleb128 0x19 + 978 00bb 01 .uleb128 0x1 + 979 00bc 13 .uleb128 0x13 + 980 00bd 00 .byte 0 + 981 00be 00 .byte 0 + 982 00bf 0C .uleb128 0xc + 983 00c0 0F .uleb128 0xf + 984 00c1 00 .byte 0 + 985 00c2 0B .uleb128 0xb + 986 00c3 0B .uleb128 0xb + 987 00c4 49 .uleb128 0x49 + 988 00c5 13 .uleb128 0x13 + 989 00c6 00 .byte 0 + 990 00c7 00 .byte 0 + 991 00c8 0D .uleb128 0xd + 992 00c9 26 .uleb128 0x26 + 993 00ca 00 .byte 0 + 994 00cb 49 .uleb128 0x49 + 995 00cc 13 .uleb128 0x13 + 996 00cd 00 .byte 0 + 997 00ce 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 33 + + + 998 00cf 0E .uleb128 0xe + 999 00d0 34 .uleb128 0x34 + 1000 00d1 00 .byte 0 + 1001 00d2 03 .uleb128 0x3 + 1002 00d3 0E .uleb128 0xe + 1003 00d4 3A .uleb128 0x3a + 1004 00d5 0B .uleb128 0xb + 1005 00d6 3B .uleb128 0x3b + 1006 00d7 0B .uleb128 0xb + 1007 00d8 49 .uleb128 0x49 + 1008 00d9 13 .uleb128 0x13 + 1009 00da 3F .uleb128 0x3f + 1010 00db 19 .uleb128 0x19 + 1011 00dc 3C .uleb128 0x3c + 1012 00dd 19 .uleb128 0x19 + 1013 00de 00 .byte 0 + 1014 00df 00 .byte 0 + 1015 00e0 00 .byte 0 + 1016 .section .debug_aranges,"",%progbits + 1017 0000 54000000 .4byte 0x54 + 1018 0004 0200 .2byte 0x2 + 1019 0006 00000000 .4byte .Ldebug_info0 + 1020 000a 04 .byte 0x4 + 1021 000b 00 .byte 0 + 1022 000c 0000 .2byte 0 + 1023 000e 0000 .2byte 0 + 1024 0010 00000000 .4byte .LFB0 + 1025 0014 BC000000 .4byte .LFE0-.LFB0 + 1026 0018 00000000 .4byte .LFB1 + 1027 001c 30000000 .4byte .LFE1-.LFB1 + 1028 0020 00000000 .4byte .LFB2 + 1029 0024 34000000 .4byte .LFE2-.LFB2 + 1030 0028 00000000 .4byte .LFB3 + 1031 002c 34000000 .4byte .LFE3-.LFB3 + 1032 0030 00000000 .4byte .LFB4 + 1033 0034 38000000 .4byte .LFE4-.LFB4 + 1034 0038 00000000 .4byte .LFB5 + 1035 003c 36000000 .4byte .LFE5-.LFB5 + 1036 0040 00000000 .4byte .LFB6 + 1037 0044 24000000 .4byte .LFE6-.LFB6 + 1038 0048 00000000 .4byte .LFB7 + 1039 004c 7C000000 .4byte .LFE7-.LFB7 + 1040 0050 00000000 .4byte 0 + 1041 0054 00000000 .4byte 0 + 1042 .section .debug_ranges,"",%progbits + 1043 .Ldebug_ranges0: + 1044 0000 00000000 .4byte .LFB0 + 1045 0004 BC000000 .4byte .LFE0 + 1046 0008 00000000 .4byte .LFB1 + 1047 000c 30000000 .4byte .LFE1 + 1048 0010 00000000 .4byte .LFB2 + 1049 0014 34000000 .4byte .LFE2 + 1050 0018 00000000 .4byte .LFB3 + 1051 001c 34000000 .4byte .LFE3 + 1052 0020 00000000 .4byte .LFB4 + 1053 0024 38000000 .4byte .LFE4 + 1054 0028 00000000 .4byte .LFB5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 34 + + + 1055 002c 36000000 .4byte .LFE5 + 1056 0030 00000000 .4byte .LFB6 + 1057 0034 24000000 .4byte .LFE6 + 1058 0038 00000000 .4byte .LFB7 + 1059 003c 7C000000 .4byte .LFE7 + 1060 0040 00000000 .4byte 0 + 1061 0044 00000000 .4byte 0 + 1062 .section .debug_line,"",%progbits + 1063 .Ldebug_line0: + 1064 0000 25010000 .section .debug_str,"MS",%progbits,1 + 1064 02005400 + 1064 00000201 + 1064 FB0E0D00 + 1064 01010101 + 1065 .LASF6: + 1066 0000 6C6F6E67 .ascii "long long int\000" + 1066 206C6F6E + 1066 6720696E + 1066 7400 + 1067 .LASF15: + 1068 000e 72656733 .ascii "reg32\000" + 1068 3200 + 1069 .LASF38: + 1070 0014 55415254 .ascii "UART_IntrTxMask\000" + 1070 5F496E74 + 1070 7254784D + 1070 61736B00 + 1071 .LASF22: + 1072 0024 55415254 .ascii "UART_UartSetRxAddressMask\000" + 1072 5F556172 + 1072 74536574 + 1072 52784164 + 1072 64726573 + 1073 .LASF11: + 1074 003e 666C6F61 .ascii "float\000" + 1074 7400 + 1075 .LASF27: + 1076 0044 73747269 .ascii "string\000" + 1076 6E6700 + 1077 .LASF26: + 1078 004b 55415254 .ascii "UART_UartPutString\000" + 1078 5F556172 + 1078 74507574 + 1078 53747269 + 1078 6E6700 + 1079 .LASF37: + 1080 005e 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 1080 73657273 + 1080 5C6A6167 + 1080 756D6965 + 1080 6C5C446F + 1081 008c 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 1081 50536F43 + 1081 2D313031 + 1081 5C547261 + 1081 696E696E + 1082 .LASF32: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 35 + + + 1083 00b9 62726561 .ascii "breakWidth\000" + 1083 6B576964 + 1083 746800 + 1084 .LASF31: + 1085 00c4 55415254 .ascii "UART_UartSendBreakBlocking\000" + 1085 5F556172 + 1085 7453656E + 1085 64427265 + 1085 616B426C + 1086 .LASF34: + 1087 00df 7478496E .ascii "txIntrReg\000" + 1087 74725265 + 1087 6700 + 1088 .LASF1: + 1089 00e9 756E7369 .ascii "unsigned char\000" + 1089 676E6564 + 1089 20636861 + 1089 7200 + 1090 .LASF13: + 1091 00f7 63686172 .ascii "char8\000" + 1091 3800 + 1092 .LASF19: + 1093 00fd 55415254 .ascii "UART_UartPostEnable\000" + 1093 5F556172 + 1093 74506F73 + 1093 74456E61 + 1093 626C6500 + 1094 .LASF5: + 1095 0111 6C6F6E67 .ascii "long unsigned int\000" + 1095 20756E73 + 1095 69676E65 + 1095 6420696E + 1095 7400 + 1096 .LASF20: + 1097 0123 55415254 .ascii "UART_UartStop\000" + 1097 5F556172 + 1097 7453746F + 1097 7000 + 1098 .LASF3: + 1099 0131 73686F72 .ascii "short unsigned int\000" + 1099 7420756E + 1099 7369676E + 1099 65642069 + 1099 6E7400 + 1100 .LASF29: + 1101 0144 55415254 .ascii "UART_UartPutCRLF\000" + 1101 5F556172 + 1101 74507574 + 1101 43524C46 + 1101 00 + 1102 .LASF35: + 1103 0155 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 1103 43313120 + 1103 352E342E + 1103 31203230 + 1103 31363036 + 1104 0188 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 36 + + + 1104 20726576 + 1104 6973696F + 1104 6E203233 + 1104 37373135 + 1105 01bb 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 1105 66756E63 + 1105 74696F6E + 1105 2D736563 + 1105 74696F6E + 1106 .LASF24: + 1107 01e3 61646472 .ascii "addressMask\000" + 1107 6573734D + 1107 61736B00 + 1108 .LASF12: + 1109 01ef 646F7562 .ascii "double\000" + 1109 6C6500 + 1110 .LASF21: + 1111 01f6 55415254 .ascii "UART_UartSetRxAddress\000" + 1111 5F556172 + 1111 74536574 + 1111 52784164 + 1111 64726573 + 1112 .LASF9: + 1113 020c 75696E74 .ascii "uint16\000" + 1113 313600 + 1114 .LASF10: + 1115 0213 75696E74 .ascii "uint32\000" + 1115 333200 + 1116 .LASF8: + 1117 021a 756E7369 .ascii "unsigned int\000" + 1117 676E6564 + 1117 20696E74 + 1117 00 + 1118 .LASF18: + 1119 0227 55415254 .ascii "UART_UartInit\000" + 1119 5F556172 + 1119 74496E69 + 1119 7400 + 1120 .LASF23: + 1121 0235 61646472 .ascii "address\000" + 1121 65737300 + 1122 .LASF7: + 1123 023d 6C6F6E67 .ascii "long long unsigned int\000" + 1123 206C6F6E + 1123 6720756E + 1123 7369676E + 1123 65642069 + 1124 .LASF28: + 1125 0254 62756649 .ascii "bufIndex\000" + 1125 6E646578 + 1125 00 + 1126 .LASF17: + 1127 025d 73697A65 .ascii "sizetype\000" + 1127 74797065 + 1127 00 + 1128 .LASF30: + 1129 0266 74784461 .ascii "txDataByte\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccc7phAK.s page 37 + + + 1129 74614279 + 1129 746500 + 1130 .LASF14: + 1131 0271 63686172 .ascii "char\000" + 1131 00 + 1132 .LASF2: + 1133 0276 73686F72 .ascii "short int\000" + 1133 7420696E + 1133 7400 + 1134 .LASF4: + 1135 0280 6C6F6E67 .ascii "long int\000" + 1135 20696E74 + 1135 00 + 1136 .LASF25: + 1137 0289 6D617463 .ascii "matchReg\000" + 1137 68526567 + 1137 00 + 1138 .LASF16: + 1139 0292 6C6F6E67 .ascii "long double\000" + 1139 20646F75 + 1139 626C6500 + 1140 .LASF36: + 1141 029e 47656E65 .ascii "Generated_Source\\PSoC4\\UART_UART.c\000" + 1141 72617465 + 1141 645F536F + 1141 75726365 + 1141 5C50536F + 1142 .LASF0: + 1143 02c1 7369676E .ascii "signed char\000" + 1143 65642063 + 1143 68617200 + 1144 .LASF33: + 1145 02cd 74784374 .ascii "txCtrlReg\000" + 1145 726C5265 + 1145 6700 + 1146 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_UART.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_UART.o new file mode 100644 index 0000000000000000000000000000000000000000..381cbe32bf08f3c5e6cda2e6ca6522bfad374fd7 GIT binary patch literal 6628 zcmb_gYiu0V6}~gGFTXa)0_#7MI9&fI=wV$Jo2X-Zi_k zsS_gAqE$(&wj#6wL_>vCDj|eQpimW>sHxybKvbea6;+E$t3Ht`9_oXFOWp6gb7yyU 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the Pins component instance. Use the + 50:Generated_Source\PSoC4/UART_tx.c **** * Per-Pin APIs if you wish to control individual pin's drive modes. + 51:Generated_Source\PSoC4/UART_tx.c **** * + 52:Generated_Source\PSoC4/UART_tx.c **** * Note USBIOs have limited drive functionality. Refer to the Drive Mode + 53:Generated_Source\PSoC4/UART_tx.c **** * parameter for more information. + 54:Generated_Source\PSoC4/UART_tx.c **** * + 55:Generated_Source\PSoC4/UART_tx.c **** * \param mode + 56:Generated_Source\PSoC4/UART_tx.c **** * Mode for the selected signals. Valid options are documented in + 57:Generated_Source\PSoC4/UART_tx.c **** * \ref driveMode. + 58:Generated_Source\PSoC4/UART_tx.c **** * + 59:Generated_Source\PSoC4/UART_tx.c **** * \return + 60:Generated_Source\PSoC4/UART_tx.c **** * None + 61:Generated_Source\PSoC4/UART_tx.c **** * + 62:Generated_Source\PSoC4/UART_tx.c **** * \sideeffect + 63:Generated_Source\PSoC4/UART_tx.c **** * If you use read-modify-write operations that are not atomic, the ISR can + 64:Generated_Source\PSoC4/UART_tx.c **** * cause corruption of this function. An ISR that interrupts this function + 65:Generated_Source\PSoC4/UART_tx.c **** * and performs writes to the Pins component Drive Mode registers can cause + 66:Generated_Source\PSoC4/UART_tx.c **** * corrupted port data. To avoid this issue, you should either use the Per-Pin + 67:Generated_Source\PSoC4/UART_tx.c **** * APIs (primary method) or disable interrupts around this function. + 68:Generated_Source\PSoC4/UART_tx.c **** * + 69:Generated_Source\PSoC4/UART_tx.c **** * \funcusage + 70:Generated_Source\PSoC4/UART_tx.c **** * \snippet UART_tx_SUT.c usage_UART_tx_SetDriveMode + 71:Generated_Source\PSoC4/UART_tx.c **** *******************************************************************************/ + 72:Generated_Source\PSoC4/UART_tx.c **** void UART_tx_SetDriveMode(uint8 mode) + 73:Generated_Source\PSoC4/UART_tx.c **** { + 28 .loc 1 73 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 82B0 sub sp, sp, #8 + 37 .cfi_def_cfa_offset 16 + 38 0004 00AF add r7, sp, #0 + 39 .cfi_def_cfa_register 7 + 40 0006 0200 movs r2, r0 + 41 0008 FB1D adds r3, r7, #7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 3 + + + 42 000a 1A70 strb r2, [r3] + 74:Generated_Source\PSoC4/UART_tx.c **** UART_tx_SetP4PinDriveMode(UART_tx__0__SHIFT, mode); + 43 .loc 1 74 0 + 44 000c 074B ldr r3, .L2 + 45 000e 074A ldr r2, .L2 + 46 0010 1268 ldr r2, [r2] + 47 0012 3821 movs r1, #56 + 48 0014 8A43 bics r2, r1 + 49 0016 1100 movs r1, r2 + 50 0018 FA1D adds r2, r7, #7 + 51 001a 1278 ldrb r2, [r2] + 52 001c D200 lsls r2, r2, #3 + 53 001e 0A43 orrs r2, r1 + 54 0020 1A60 str r2, [r3] + 75:Generated_Source\PSoC4/UART_tx.c **** } + 55 .loc 1 75 0 + 56 0022 C046 nop + 57 0024 BD46 mov sp, r7 + 58 0026 02B0 add sp, sp, #8 + 59 @ sp needed + 60 0028 80BD pop {r7, pc} + 61 .L3: + 62 002a C046 .align 2 + 63 .L2: + 64 002c 08040440 .word 1074005000 + 65 .cfi_endproc + 66 .LFE0: + 67 .size UART_tx_SetDriveMode, .-UART_tx_SetDriveMode + 68 .section .text.UART_tx_Write,"ax",%progbits + 69 .align 2 + 70 .global UART_tx_Write + 71 .code 16 + 72 .thumb_func + 73 .type UART_tx_Write, %function + 74 UART_tx_Write: + 75 .LFB1: + 76:Generated_Source\PSoC4/UART_tx.c **** #endif + 77:Generated_Source\PSoC4/UART_tx.c **** + 78:Generated_Source\PSoC4/UART_tx.c **** + 79:Generated_Source\PSoC4/UART_tx.c **** /******************************************************************************* + 80:Generated_Source\PSoC4/UART_tx.c **** * Function Name: UART_tx_Write + 81:Generated_Source\PSoC4/UART_tx.c **** ****************************************************************************//** + 82:Generated_Source\PSoC4/UART_tx.c **** * + 83:Generated_Source\PSoC4/UART_tx.c **** * \brief Writes the value to the physical port (data output register), masking + 84:Generated_Source\PSoC4/UART_tx.c **** * and shifting the bits appropriately. + 85:Generated_Source\PSoC4/UART_tx.c **** * + 86:Generated_Source\PSoC4/UART_tx.c **** * The data output register controls the signal applied to the physical pin in + 87:Generated_Source\PSoC4/UART_tx.c **** * conjunction with the drive mode parameter. This function avoids changing + 88:Generated_Source\PSoC4/UART_tx.c **** * other bits in the port by using the appropriate method (read-modify-write or + 89:Generated_Source\PSoC4/UART_tx.c **** * bit banding). + 90:Generated_Source\PSoC4/UART_tx.c **** * + 91:Generated_Source\PSoC4/UART_tx.c **** * Note This function should not be used on a hardware digital output pin + 92:Generated_Source\PSoC4/UART_tx.c **** * as it is driven by the hardware signal attached to it. + 93:Generated_Source\PSoC4/UART_tx.c **** * + 94:Generated_Source\PSoC4/UART_tx.c **** * \param value + 95:Generated_Source\PSoC4/UART_tx.c **** * Value to write to the component instance. + 96:Generated_Source\PSoC4/UART_tx.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 4 + + + 97:Generated_Source\PSoC4/UART_tx.c **** * \return + 98:Generated_Source\PSoC4/UART_tx.c **** * None + 99:Generated_Source\PSoC4/UART_tx.c **** * + 100:Generated_Source\PSoC4/UART_tx.c **** * \sideeffect + 101:Generated_Source\PSoC4/UART_tx.c **** * If you use read-modify-write operations that are not atomic; the Interrupt + 102:Generated_Source\PSoC4/UART_tx.c **** * Service Routines (ISR) can cause corruption of this function. An ISR that + 103:Generated_Source\PSoC4/UART_tx.c **** * interrupts this function and performs writes to the Pins component data + 104:Generated_Source\PSoC4/UART_tx.c **** * register can cause corrupted port data. To avoid this issue, you should + 105:Generated_Source\PSoC4/UART_tx.c **** * either use the Per-Pin APIs (primary method) or disable interrupts around + 106:Generated_Source\PSoC4/UART_tx.c **** * this function. + 107:Generated_Source\PSoC4/UART_tx.c **** * + 108:Generated_Source\PSoC4/UART_tx.c **** * \funcusage + 109:Generated_Source\PSoC4/UART_tx.c **** * \snippet UART_tx_SUT.c usage_UART_tx_Write + 110:Generated_Source\PSoC4/UART_tx.c **** *******************************************************************************/ + 111:Generated_Source\PSoC4/UART_tx.c **** void UART_tx_Write(uint8 value) + 112:Generated_Source\PSoC4/UART_tx.c **** { + 76 .loc 1 112 0 + 77 .cfi_startproc + 78 @ args = 0, pretend = 0, frame = 16 + 79 @ frame_needed = 1, uses_anonymous_args = 0 + 80 0000 80B5 push {r7, lr} + 81 .cfi_def_cfa_offset 8 + 82 .cfi_offset 7, -8 + 83 .cfi_offset 14, -4 + 84 0002 84B0 sub sp, sp, #16 + 85 .cfi_def_cfa_offset 24 + 86 0004 00AF add r7, sp, #0 + 87 .cfi_def_cfa_register 7 + 88 0006 0200 movs r2, r0 + 89 0008 FB1D adds r3, r7, #7 + 90 000a 1A70 strb r2, [r3] + 113:Generated_Source\PSoC4/UART_tx.c **** uint8 drVal = (uint8)(UART_tx_DR & (uint8)(~UART_tx_MASK)); + 91 .loc 1 113 0 + 92 000c 0F4B ldr r3, .L5 + 93 000e 1B68 ldr r3, [r3] + 94 0010 DAB2 uxtb r2, r3 + 95 0012 0F23 movs r3, #15 + 96 0014 FB18 adds r3, r7, r3 + 97 0016 0221 movs r1, #2 + 98 0018 8A43 bics r2, r1 + 99 001a 1A70 strb r2, [r3] + 114:Generated_Source\PSoC4/UART_tx.c **** drVal = (drVal | ((uint8)(value << UART_tx_SHIFT) & UART_tx_MASK)); + 100 .loc 1 114 0 + 101 001c FB1D adds r3, r7, #7 + 102 001e 1B78 ldrb r3, [r3] + 103 0020 DB18 adds r3, r3, r3 + 104 0022 DBB2 uxtb r3, r3 + 105 0024 0222 movs r2, #2 + 106 0026 1340 ands r3, r2 + 107 0028 D9B2 uxtb r1, r3 + 108 002a 0F23 movs r3, #15 + 109 002c FB18 adds r3, r7, r3 + 110 002e 0F22 movs r2, #15 + 111 0030 BA18 adds r2, r7, r2 + 112 0032 1278 ldrb r2, [r2] + 113 0034 0A43 orrs r2, r1 + 114 0036 1A70 strb r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 5 + + + 115:Generated_Source\PSoC4/UART_tx.c **** UART_tx_DR = (uint32)drVal; + 115 .loc 1 115 0 + 116 0038 044B ldr r3, .L5 + 117 003a 0F22 movs r2, #15 + 118 003c BA18 adds r2, r7, r2 + 119 003e 1278 ldrb r2, [r2] + 120 0040 1A60 str r2, [r3] + 116:Generated_Source\PSoC4/UART_tx.c **** } + 121 .loc 1 116 0 + 122 0042 C046 nop + 123 0044 BD46 mov sp, r7 + 124 0046 04B0 add sp, sp, #16 + 125 @ sp needed + 126 0048 80BD pop {r7, pc} + 127 .L6: + 128 004a C046 .align 2 + 129 .L5: + 130 004c 00040440 .word 1074004992 + 131 .cfi_endproc + 132 .LFE1: + 133 .size UART_tx_Write, .-UART_tx_Write + 134 .section .text.UART_tx_Read,"ax",%progbits + 135 .align 2 + 136 .global UART_tx_Read + 137 .code 16 + 138 .thumb_func + 139 .type UART_tx_Read, %function + 140 UART_tx_Read: + 141 .LFB2: + 117:Generated_Source\PSoC4/UART_tx.c **** + 118:Generated_Source\PSoC4/UART_tx.c **** + 119:Generated_Source\PSoC4/UART_tx.c **** /******************************************************************************* + 120:Generated_Source\PSoC4/UART_tx.c **** * Function Name: UART_tx_Read + 121:Generated_Source\PSoC4/UART_tx.c **** ****************************************************************************//** + 122:Generated_Source\PSoC4/UART_tx.c **** * + 123:Generated_Source\PSoC4/UART_tx.c **** * \brief Reads the associated physical port (pin status register) and masks + 124:Generated_Source\PSoC4/UART_tx.c **** * the required bits according to the width and bit position of the component + 125:Generated_Source\PSoC4/UART_tx.c **** * instance. + 126:Generated_Source\PSoC4/UART_tx.c **** * + 127:Generated_Source\PSoC4/UART_tx.c **** * The pin's status register returns the current logic level present on the + 128:Generated_Source\PSoC4/UART_tx.c **** * physical pin. + 129:Generated_Source\PSoC4/UART_tx.c **** * + 130:Generated_Source\PSoC4/UART_tx.c **** * \return + 131:Generated_Source\PSoC4/UART_tx.c **** * The current value for the pins in the component as a right justified number. + 132:Generated_Source\PSoC4/UART_tx.c **** * + 133:Generated_Source\PSoC4/UART_tx.c **** * \funcusage + 134:Generated_Source\PSoC4/UART_tx.c **** * \snippet UART_tx_SUT.c usage_UART_tx_Read + 135:Generated_Source\PSoC4/UART_tx.c **** *******************************************************************************/ + 136:Generated_Source\PSoC4/UART_tx.c **** uint8 UART_tx_Read(void) + 137:Generated_Source\PSoC4/UART_tx.c **** { + 142 .loc 1 137 0 + 143 .cfi_startproc + 144 @ args = 0, pretend = 0, frame = 0 + 145 @ frame_needed = 1, uses_anonymous_args = 0 + 146 0000 80B5 push {r7, lr} + 147 .cfi_def_cfa_offset 8 + 148 .cfi_offset 7, -8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 6 + + + 149 .cfi_offset 14, -4 + 150 0002 00AF add r7, sp, #0 + 151 .cfi_def_cfa_register 7 + 138:Generated_Source\PSoC4/UART_tx.c **** return (uint8)((UART_tx_PS & UART_tx_MASK) >> UART_tx_SHIFT); + 152 .loc 1 138 0 + 153 0004 044B ldr r3, .L9 + 154 0006 1B68 ldr r3, [r3] + 155 0008 0222 movs r2, #2 + 156 000a 1340 ands r3, r2 + 157 000c 5B08 lsrs r3, r3, #1 + 158 000e DBB2 uxtb r3, r3 + 139:Generated_Source\PSoC4/UART_tx.c **** } + 159 .loc 1 139 0 + 160 0010 1800 movs r0, r3 + 161 0012 BD46 mov sp, r7 + 162 @ sp needed + 163 0014 80BD pop {r7, pc} + 164 .L10: + 165 0016 C046 .align 2 + 166 .L9: + 167 0018 04040440 .word 1074004996 + 168 .cfi_endproc + 169 .LFE2: + 170 .size UART_tx_Read, .-UART_tx_Read + 171 .section .text.UART_tx_ReadDataReg,"ax",%progbits + 172 .align 2 + 173 .global UART_tx_ReadDataReg + 174 .code 16 + 175 .thumb_func + 176 .type UART_tx_ReadDataReg, %function + 177 UART_tx_ReadDataReg: + 178 .LFB3: + 140:Generated_Source\PSoC4/UART_tx.c **** + 141:Generated_Source\PSoC4/UART_tx.c **** + 142:Generated_Source\PSoC4/UART_tx.c **** /******************************************************************************* + 143:Generated_Source\PSoC4/UART_tx.c **** * Function Name: UART_tx_ReadDataReg + 144:Generated_Source\PSoC4/UART_tx.c **** ****************************************************************************//** + 145:Generated_Source\PSoC4/UART_tx.c **** * + 146:Generated_Source\PSoC4/UART_tx.c **** * \brief Reads the associated physical port's data output register and masks + 147:Generated_Source\PSoC4/UART_tx.c **** * the correct bits according to the width and bit position of the component + 148:Generated_Source\PSoC4/UART_tx.c **** * instance. + 149:Generated_Source\PSoC4/UART_tx.c **** * + 150:Generated_Source\PSoC4/UART_tx.c **** * The data output register controls the signal applied to the physical pin in + 151:Generated_Source\PSoC4/UART_tx.c **** * conjunction with the drive mode parameter. This is not the same as the + 152:Generated_Source\PSoC4/UART_tx.c **** * preferred UART_tx_Read() API because the + 153:Generated_Source\PSoC4/UART_tx.c **** * UART_tx_ReadDataReg() reads the data register instead of the status + 154:Generated_Source\PSoC4/UART_tx.c **** * register. For output pins this is a useful function to determine the value + 155:Generated_Source\PSoC4/UART_tx.c **** * just written to the pin. + 156:Generated_Source\PSoC4/UART_tx.c **** * + 157:Generated_Source\PSoC4/UART_tx.c **** * \return + 158:Generated_Source\PSoC4/UART_tx.c **** * The current value of the data register masked and shifted into a right + 159:Generated_Source\PSoC4/UART_tx.c **** * justified number for the component instance. + 160:Generated_Source\PSoC4/UART_tx.c **** * + 161:Generated_Source\PSoC4/UART_tx.c **** * \funcusage + 162:Generated_Source\PSoC4/UART_tx.c **** * \snippet UART_tx_SUT.c usage_UART_tx_ReadDataReg + 163:Generated_Source\PSoC4/UART_tx.c **** *******************************************************************************/ + 164:Generated_Source\PSoC4/UART_tx.c **** uint8 UART_tx_ReadDataReg(void) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 7 + + + 165:Generated_Source\PSoC4/UART_tx.c **** { + 179 .loc 1 165 0 + 180 .cfi_startproc + 181 @ args = 0, pretend = 0, frame = 0 + 182 @ frame_needed = 1, uses_anonymous_args = 0 + 183 0000 80B5 push {r7, lr} + 184 .cfi_def_cfa_offset 8 + 185 .cfi_offset 7, -8 + 186 .cfi_offset 14, -4 + 187 0002 00AF add r7, sp, #0 + 188 .cfi_def_cfa_register 7 + 166:Generated_Source\PSoC4/UART_tx.c **** return (uint8)((UART_tx_DR & UART_tx_MASK) >> UART_tx_SHIFT); + 189 .loc 1 166 0 + 190 0004 044B ldr r3, .L13 + 191 0006 1B68 ldr r3, [r3] + 192 0008 0222 movs r2, #2 + 193 000a 1340 ands r3, r2 + 194 000c 5B08 lsrs r3, r3, #1 + 195 000e DBB2 uxtb r3, r3 + 167:Generated_Source\PSoC4/UART_tx.c **** } + 196 .loc 1 167 0 + 197 0010 1800 movs r0, r3 + 198 0012 BD46 mov sp, r7 + 199 @ sp needed + 200 0014 80BD pop {r7, pc} + 201 .L14: + 202 0016 C046 .align 2 + 203 .L13: + 204 0018 00040440 .word 1074004992 + 205 .cfi_endproc + 206 .LFE3: + 207 .size UART_tx_ReadDataReg, .-UART_tx_ReadDataReg + 208 .section .text.UART_tx_SetInterruptMode,"ax",%progbits + 209 .align 2 + 210 .global UART_tx_SetInterruptMode + 211 .code 16 + 212 .thumb_func + 213 .type UART_tx_SetInterruptMode, %function + 214 UART_tx_SetInterruptMode: + 215 .LFB4: + 168:Generated_Source\PSoC4/UART_tx.c **** + 169:Generated_Source\PSoC4/UART_tx.c **** + 170:Generated_Source\PSoC4/UART_tx.c **** /******************************************************************************* + 171:Generated_Source\PSoC4/UART_tx.c **** * Function Name: UART_tx_SetInterruptMode + 172:Generated_Source\PSoC4/UART_tx.c **** ****************************************************************************//** + 173:Generated_Source\PSoC4/UART_tx.c **** * + 174:Generated_Source\PSoC4/UART_tx.c **** * \brief Configures the interrupt mode for each of the Pins component's + 175:Generated_Source\PSoC4/UART_tx.c **** * pins. Alternatively you may set the interrupt mode for all the pins + 176:Generated_Source\PSoC4/UART_tx.c **** * specified in the Pins component. + 177:Generated_Source\PSoC4/UART_tx.c **** * + 178:Generated_Source\PSoC4/UART_tx.c **** * Note The interrupt is port-wide and therefore any enabled pin + 179:Generated_Source\PSoC4/UART_tx.c **** * interrupt may trigger it. + 180:Generated_Source\PSoC4/UART_tx.c **** * + 181:Generated_Source\PSoC4/UART_tx.c **** * \param position + 182:Generated_Source\PSoC4/UART_tx.c **** * The pin position as listed in the Pins component. You may OR these to be + 183:Generated_Source\PSoC4/UART_tx.c **** * able to configure the interrupt mode of multiple pins within a Pins + 184:Generated_Source\PSoC4/UART_tx.c **** * component. Or you may use UART_tx_INTR_ALL to configure the + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 8 + + + 185:Generated_Source\PSoC4/UART_tx.c **** * interrupt mode of all the pins in the Pins component. + 186:Generated_Source\PSoC4/UART_tx.c **** * - UART_tx_0_INTR (First pin in the list) + 187:Generated_Source\PSoC4/UART_tx.c **** * - UART_tx_1_INTR (Second pin in the list) + 188:Generated_Source\PSoC4/UART_tx.c **** * - ... + 189:Generated_Source\PSoC4/UART_tx.c **** * - UART_tx_INTR_ALL (All pins in Pins component) + 190:Generated_Source\PSoC4/UART_tx.c **** * + 191:Generated_Source\PSoC4/UART_tx.c **** * \param mode + 192:Generated_Source\PSoC4/UART_tx.c **** * Interrupt mode for the selected pins. Valid options are documented in + 193:Generated_Source\PSoC4/UART_tx.c **** * \ref intrMode. + 194:Generated_Source\PSoC4/UART_tx.c **** * + 195:Generated_Source\PSoC4/UART_tx.c **** * \return + 196:Generated_Source\PSoC4/UART_tx.c **** * None + 197:Generated_Source\PSoC4/UART_tx.c **** * + 198:Generated_Source\PSoC4/UART_tx.c **** * \sideeffect + 199:Generated_Source\PSoC4/UART_tx.c **** * It is recommended that the interrupt be disabled before calling this + 200:Generated_Source\PSoC4/UART_tx.c **** * function to avoid unintended interrupt requests. Note that the interrupt + 201:Generated_Source\PSoC4/UART_tx.c **** * type is port wide, and therefore will trigger for any enabled pin on the + 202:Generated_Source\PSoC4/UART_tx.c **** * port. + 203:Generated_Source\PSoC4/UART_tx.c **** * + 204:Generated_Source\PSoC4/UART_tx.c **** * \funcusage + 205:Generated_Source\PSoC4/UART_tx.c **** * \snippet UART_tx_SUT.c usage_UART_tx_SetInterruptMode + 206:Generated_Source\PSoC4/UART_tx.c **** *******************************************************************************/ + 207:Generated_Source\PSoC4/UART_tx.c **** void UART_tx_SetInterruptMode(uint16 position, uint16 mode) + 208:Generated_Source\PSoC4/UART_tx.c **** { + 216 .loc 1 208 0 + 217 .cfi_startproc + 218 @ args = 0, pretend = 0, frame = 16 + 219 @ frame_needed = 1, uses_anonymous_args = 0 + 220 0000 80B5 push {r7, lr} + 221 .cfi_def_cfa_offset 8 + 222 .cfi_offset 7, -8 + 223 .cfi_offset 14, -4 + 224 0002 84B0 sub sp, sp, #16 + 225 .cfi_def_cfa_offset 24 + 226 0004 00AF add r7, sp, #0 + 227 .cfi_def_cfa_register 7 + 228 0006 0200 movs r2, r0 + 229 0008 BB1D adds r3, r7, #6 + 230 000a 1A80 strh r2, [r3] + 231 000c 3B1D adds r3, r7, #4 + 232 000e 0A1C adds r2, r1, #0 + 233 0010 1A80 strh r2, [r3] + 209:Generated_Source\PSoC4/UART_tx.c **** uint32 intrCfg; + 210:Generated_Source\PSoC4/UART_tx.c **** + 211:Generated_Source\PSoC4/UART_tx.c **** intrCfg = UART_tx_INTCFG & (uint32)(~(uint32)position); + 234 .loc 1 211 0 + 235 0012 0B4B ldr r3, .L16 + 236 0014 1B68 ldr r3, [r3] + 237 0016 BA1D adds r2, r7, #6 + 238 0018 1288 ldrh r2, [r2] + 239 001a D243 mvns r2, r2 + 240 001c 1340 ands r3, r2 + 241 001e FB60 str r3, [r7, #12] + 212:Generated_Source\PSoC4/UART_tx.c **** UART_tx_INTCFG = intrCfg | ((uint32)position & (uint32)mode); + 242 .loc 1 212 0 + 243 0020 074B ldr r3, .L16 + 244 0022 BA1D adds r2, r7, #6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 9 + + + 245 0024 391D adds r1, r7, #4 + 246 0026 1288 ldrh r2, [r2] + 247 0028 0988 ldrh r1, [r1] + 248 002a 0A40 ands r2, r1 + 249 002c 92B2 uxth r2, r2 + 250 002e 1100 movs r1, r2 + 251 0030 FA68 ldr r2, [r7, #12] + 252 0032 0A43 orrs r2, r1 + 253 0034 1A60 str r2, [r3] + 213:Generated_Source\PSoC4/UART_tx.c **** } + 254 .loc 1 213 0 + 255 0036 C046 nop + 256 0038 BD46 mov sp, r7 + 257 003a 04B0 add sp, sp, #16 + 258 @ sp needed + 259 003c 80BD pop {r7, pc} + 260 .L17: + 261 003e C046 .align 2 + 262 .L16: + 263 0040 0C040440 .word 1074005004 + 264 .cfi_endproc + 265 .LFE4: + 266 .size UART_tx_SetInterruptMode, .-UART_tx_SetInterruptMode + 267 .section .text.UART_tx_ClearInterrupt,"ax",%progbits + 268 .align 2 + 269 .global UART_tx_ClearInterrupt + 270 .code 16 + 271 .thumb_func + 272 .type UART_tx_ClearInterrupt, %function + 273 UART_tx_ClearInterrupt: + 274 .LFB5: + 214:Generated_Source\PSoC4/UART_tx.c **** + 215:Generated_Source\PSoC4/UART_tx.c **** + 216:Generated_Source\PSoC4/UART_tx.c **** /******************************************************************************* + 217:Generated_Source\PSoC4/UART_tx.c **** * Function Name: UART_tx_ClearInterrupt + 218:Generated_Source\PSoC4/UART_tx.c **** ****************************************************************************//** + 219:Generated_Source\PSoC4/UART_tx.c **** * + 220:Generated_Source\PSoC4/UART_tx.c **** * \brief Clears any active interrupts attached with the component and returns + 221:Generated_Source\PSoC4/UART_tx.c **** * the value of the interrupt status register allowing determination of which + 222:Generated_Source\PSoC4/UART_tx.c **** * pins generated an interrupt event. + 223:Generated_Source\PSoC4/UART_tx.c **** * + 224:Generated_Source\PSoC4/UART_tx.c **** * \return + 225:Generated_Source\PSoC4/UART_tx.c **** * The right-shifted current value of the interrupt status register. Each pin + 226:Generated_Source\PSoC4/UART_tx.c **** * has one bit set if it generated an interrupt event. For example, bit 0 is + 227:Generated_Source\PSoC4/UART_tx.c **** * for pin 0 and bit 1 is for pin 1 of the Pins component. + 228:Generated_Source\PSoC4/UART_tx.c **** * + 229:Generated_Source\PSoC4/UART_tx.c **** * \sideeffect + 230:Generated_Source\PSoC4/UART_tx.c **** * Clears all bits of the physical port's interrupt status register, not just + 231:Generated_Source\PSoC4/UART_tx.c **** * those associated with the Pins component. + 232:Generated_Source\PSoC4/UART_tx.c **** * + 233:Generated_Source\PSoC4/UART_tx.c **** * \funcusage + 234:Generated_Source\PSoC4/UART_tx.c **** * \snippet UART_tx_SUT.c usage_UART_tx_ClearInterrupt + 235:Generated_Source\PSoC4/UART_tx.c **** *******************************************************************************/ + 236:Generated_Source\PSoC4/UART_tx.c **** uint8 UART_tx_ClearInterrupt(void) + 237:Generated_Source\PSoC4/UART_tx.c **** { + 275 .loc 1 237 0 + 276 .cfi_startproc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 10 + + + 277 @ args = 0, pretend = 0, frame = 8 + 278 @ frame_needed = 1, uses_anonymous_args = 0 + 279 0000 80B5 push {r7, lr} + 280 .cfi_def_cfa_offset 8 + 281 .cfi_offset 7, -8 + 282 .cfi_offset 14, -4 + 283 0002 82B0 sub sp, sp, #8 + 284 .cfi_def_cfa_offset 16 + 285 0004 00AF add r7, sp, #0 + 286 .cfi_def_cfa_register 7 + 238:Generated_Source\PSoC4/UART_tx.c **** uint8 maskedStatus = (uint8)(UART_tx_INTSTAT & UART_tx_MASK); + 287 .loc 1 238 0 + 288 0006 094B ldr r3, .L20 + 289 0008 1B68 ldr r3, [r3] + 290 000a DAB2 uxtb r2, r3 + 291 000c FB1D adds r3, r7, #7 + 292 000e 0221 movs r1, #2 + 293 0010 0A40 ands r2, r1 + 294 0012 1A70 strb r2, [r3] + 239:Generated_Source\PSoC4/UART_tx.c **** UART_tx_INTSTAT = maskedStatus; + 295 .loc 1 239 0 + 296 0014 054B ldr r3, .L20 + 297 0016 FA1D adds r2, r7, #7 + 298 0018 1278 ldrb r2, [r2] + 299 001a 1A60 str r2, [r3] + 240:Generated_Source\PSoC4/UART_tx.c **** return maskedStatus >> UART_tx_SHIFT; + 300 .loc 1 240 0 + 301 001c FB1D adds r3, r7, #7 + 302 001e 1B78 ldrb r3, [r3] + 303 0020 5B08 lsrs r3, r3, #1 + 304 0022 DBB2 uxtb r3, r3 + 241:Generated_Source\PSoC4/UART_tx.c **** } + 305 .loc 1 241 0 + 306 0024 1800 movs r0, r3 + 307 0026 BD46 mov sp, r7 + 308 0028 02B0 add sp, sp, #8 + 309 @ sp needed + 310 002a 80BD pop {r7, pc} + 311 .L21: + 312 .align 2 + 313 .L20: + 314 002c 10040440 .word 1074005008 + 315 .cfi_endproc + 316 .LFE5: + 317 .size UART_tx_ClearInterrupt, .-UART_tx_ClearInterrupt + 318 .text + 319 .Letext0: + 320 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 321 .section .debug_info,"",%progbits + 322 .Ldebug_info0: + 323 0000 96010000 .4byte 0x196 + 324 0004 0400 .2byte 0x4 + 325 0006 00000000 .4byte .Ldebug_abbrev0 + 326 000a 04 .byte 0x4 + 327 000b 01 .uleb128 0x1 + 328 000c CB000000 .4byte .LASF28 + 329 0010 0C .byte 0xc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 11 + + + 330 0011 FE010000 .4byte .LASF29 + 331 0015 0C000000 .4byte .LASF30 + 332 0019 00000000 .4byte .Ldebug_ranges0+0 + 333 001d 00000000 .4byte 0 + 334 0021 00000000 .4byte .Ldebug_line0 + 335 0025 02 .uleb128 0x2 + 336 0026 01 .byte 0x1 + 337 0027 06 .byte 0x6 + 338 0028 51020000 .4byte .LASF0 + 339 002c 02 .uleb128 0x2 + 340 002d 01 .byte 0x1 + 341 002e 08 .byte 0x8 + 342 002f 6D000000 .4byte .LASF1 + 343 0033 02 .uleb128 0x2 + 344 0034 02 .byte 0x2 + 345 0035 05 .byte 0x5 + 346 0036 38020000 .4byte .LASF2 + 347 003a 02 .uleb128 0x2 + 348 003b 02 .byte 0x2 + 349 003c 07 .byte 0x7 + 350 003d A1000000 .4byte .LASF3 + 351 0041 02 .uleb128 0x2 + 352 0042 04 .byte 0x4 + 353 0043 05 .byte 0x5 + 354 0044 48020000 .4byte .LASF4 + 355 0048 02 .uleb128 0x2 + 356 0049 04 .byte 0x4 + 357 004a 07 .byte 0x7 + 358 004b 81000000 .4byte .LASF5 + 359 004f 02 .uleb128 0x2 + 360 0050 08 .byte 0x8 + 361 0051 05 .byte 0x5 + 362 0052 C9010000 .4byte .LASF6 + 363 0056 02 .uleb128 0x2 + 364 0057 08 .byte 0x8 + 365 0058 07 .byte 0x7 + 366 0059 8C010000 .4byte .LASF7 + 367 005d 03 .uleb128 0x3 + 368 005e 04 .byte 0x4 + 369 005f 05 .byte 0x5 + 370 0060 696E7400 .ascii "int\000" + 371 0064 02 .uleb128 0x2 + 372 0065 04 .byte 0x4 + 373 0066 07 .byte 0x7 + 374 0067 7F010000 .4byte .LASF8 + 375 006b 04 .uleb128 0x4 + 376 006c 42020000 .4byte .LASF9 + 377 0070 02 .byte 0x2 + 378 0071 E401 .2byte 0x1e4 + 379 0073 2C000000 .4byte 0x2c + 380 0077 04 .uleb128 0x4 + 381 0078 60010000 .4byte .LASF10 + 382 007c 02 .byte 0x2 + 383 007d E501 .2byte 0x1e5 + 384 007f 3A000000 .4byte 0x3a + 385 0083 04 .uleb128 0x4 + 386 0084 70010000 .4byte .LASF11 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 12 + + + 387 0088 02 .byte 0x2 + 388 0089 E601 .2byte 0x1e6 + 389 008b 48000000 .4byte 0x48 + 390 008f 02 .uleb128 0x2 + 391 0090 04 .byte 0x4 + 392 0091 04 .byte 0x4 + 393 0092 67000000 .4byte .LASF12 + 394 0096 02 .uleb128 0x2 + 395 0097 08 .byte 0x8 + 396 0098 04 .byte 0x4 + 397 0099 59010000 .4byte .LASF13 + 398 009d 02 .uleb128 0x2 + 399 009e 01 .byte 0x1 + 400 009f 08 .byte 0x8 + 401 00a0 F9010000 .4byte .LASF14 + 402 00a4 04 .uleb128 0x4 + 403 00a5 00000000 .4byte .LASF15 + 404 00a9 02 .byte 0x2 + 405 00aa 9002 .2byte 0x290 + 406 00ac B0000000 .4byte 0xb0 + 407 00b0 05 .uleb128 0x5 + 408 00b1 83000000 .4byte 0x83 + 409 00b5 06 .uleb128 0x6 + 410 00b6 D7010000 .4byte .LASF16 + 411 00ba 01 .byte 0x1 + 412 00bb 48 .byte 0x48 + 413 00bc 00000000 .4byte .LFB0 + 414 00c0 30000000 .4byte .LFE0-.LFB0 + 415 00c4 01 .uleb128 0x1 + 416 00c5 9C .byte 0x9c + 417 00c6 D9000000 .4byte 0xd9 + 418 00ca 07 .uleb128 0x7 + 419 00cb A3010000 .4byte .LASF18 + 420 00cf 01 .byte 0x1 + 421 00d0 48 .byte 0x48 + 422 00d1 6B000000 .4byte 0x6b + 423 00d5 02 .uleb128 0x2 + 424 00d6 91 .byte 0x91 + 425 00d7 77 .sleb128 -9 + 426 00d8 00 .byte 0 + 427 00d9 06 .uleb128 0x6 + 428 00da 93000000 .4byte .LASF17 + 429 00de 01 .byte 0x1 + 430 00df 6F .byte 0x6f + 431 00e0 00000000 .4byte .LFB1 + 432 00e4 50000000 .4byte .LFE1-.LFB1 + 433 00e8 01 .uleb128 0x1 + 434 00e9 9C .byte 0x9c + 435 00ea 0B010000 .4byte 0x10b + 436 00ee 07 .uleb128 0x7 + 437 00ef 06000000 .4byte .LASF19 + 438 00f3 01 .byte 0x1 + 439 00f4 6F .byte 0x6f + 440 00f5 6B000000 .4byte 0x6b + 441 00f9 02 .uleb128 0x2 + 442 00fa 91 .byte 0x91 + 443 00fb 6F .sleb128 -17 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 13 + + + 444 00fc 08 .uleb128 0x8 + 445 00fd 7B000000 .4byte .LASF24 + 446 0101 01 .byte 0x1 + 447 0102 71 .byte 0x71 + 448 0103 6B000000 .4byte 0x6b + 449 0107 02 .uleb128 0x2 + 450 0108 91 .byte 0x91 + 451 0109 77 .sleb128 -9 + 452 010a 00 .byte 0 + 453 010b 09 .uleb128 0x9 + 454 010c BC010000 .4byte .LASF20 + 455 0110 01 .byte 0x1 + 456 0111 88 .byte 0x88 + 457 0112 6B000000 .4byte 0x6b + 458 0116 00000000 .4byte .LFB2 + 459 011a 1C000000 .4byte .LFE2-.LFB2 + 460 011e 01 .uleb128 0x1 + 461 011f 9C .byte 0x9c + 462 0120 09 .uleb128 0x9 + 463 0121 A8010000 .4byte .LASF21 + 464 0125 01 .byte 0x1 + 465 0126 A4 .byte 0xa4 + 466 0127 6B000000 .4byte 0x6b + 467 012b 00000000 .4byte .LFB3 + 468 012f 1C000000 .4byte .LFE3-.LFB3 + 469 0133 01 .uleb128 0x1 + 470 0134 9C .byte 0x9c + 471 0135 06 .uleb128 0x6 + 472 0136 1F020000 .4byte .LASF22 + 473 013a 01 .byte 0x1 + 474 013b CF .byte 0xcf + 475 013c 00000000 .4byte .LFB4 + 476 0140 44000000 .4byte .LFE4-.LFB4 + 477 0144 01 .uleb128 0x1 + 478 0145 9C .byte 0x9c + 479 0146 75010000 .4byte 0x175 + 480 014a 07 .uleb128 0x7 + 481 014b 67010000 .4byte .LASF23 + 482 014f 01 .byte 0x1 + 483 0150 CF .byte 0xcf + 484 0151 77000000 .4byte 0x77 + 485 0155 02 .uleb128 0x2 + 486 0156 91 .byte 0x91 + 487 0157 6E .sleb128 -18 + 488 0158 07 .uleb128 0x7 + 489 0159 A3010000 .4byte .LASF18 + 490 015d 01 .byte 0x1 + 491 015e CF .byte 0xcf + 492 015f 77000000 .4byte 0x77 + 493 0163 02 .uleb128 0x2 + 494 0164 91 .byte 0x91 + 495 0165 6C .sleb128 -20 + 496 0166 08 .uleb128 0x8 + 497 0167 77010000 .4byte .LASF25 + 498 016b 01 .byte 0x1 + 499 016c D1 .byte 0xd1 + 500 016d 83000000 .4byte 0x83 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 14 + + + 501 0171 02 .uleb128 0x2 + 502 0172 91 .byte 0x91 + 503 0173 74 .sleb128 -12 + 504 0174 00 .byte 0 + 505 0175 0A .uleb128 0xa + 506 0176 B4000000 .4byte .LASF26 + 507 017a 01 .byte 0x1 + 508 017b EC .byte 0xec + 509 017c 6B000000 .4byte 0x6b + 510 0180 00000000 .4byte .LFB5 + 511 0184 30000000 .4byte .LFE5-.LFB5 + 512 0188 01 .uleb128 0x1 + 513 0189 9C .byte 0x9c + 514 018a 08 .uleb128 0x8 + 515 018b EC010000 .4byte .LASF27 + 516 018f 01 .byte 0x1 + 517 0190 EE .byte 0xee + 518 0191 6B000000 .4byte 0x6b + 519 0195 02 .uleb128 0x2 + 520 0196 91 .byte 0x91 + 521 0197 77 .sleb128 -9 + 522 0198 00 .byte 0 + 523 0199 00 .byte 0 + 524 .section .debug_abbrev,"",%progbits + 525 .Ldebug_abbrev0: + 526 0000 01 .uleb128 0x1 + 527 0001 11 .uleb128 0x11 + 528 0002 01 .byte 0x1 + 529 0003 25 .uleb128 0x25 + 530 0004 0E .uleb128 0xe + 531 0005 13 .uleb128 0x13 + 532 0006 0B .uleb128 0xb + 533 0007 03 .uleb128 0x3 + 534 0008 0E .uleb128 0xe + 535 0009 1B .uleb128 0x1b + 536 000a 0E .uleb128 0xe + 537 000b 55 .uleb128 0x55 + 538 000c 17 .uleb128 0x17 + 539 000d 11 .uleb128 0x11 + 540 000e 01 .uleb128 0x1 + 541 000f 10 .uleb128 0x10 + 542 0010 17 .uleb128 0x17 + 543 0011 00 .byte 0 + 544 0012 00 .byte 0 + 545 0013 02 .uleb128 0x2 + 546 0014 24 .uleb128 0x24 + 547 0015 00 .byte 0 + 548 0016 0B .uleb128 0xb + 549 0017 0B .uleb128 0xb + 550 0018 3E .uleb128 0x3e + 551 0019 0B .uleb128 0xb + 552 001a 03 .uleb128 0x3 + 553 001b 0E .uleb128 0xe + 554 001c 00 .byte 0 + 555 001d 00 .byte 0 + 556 001e 03 .uleb128 0x3 + 557 001f 24 .uleb128 0x24 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 15 + + + 558 0020 00 .byte 0 + 559 0021 0B .uleb128 0xb + 560 0022 0B .uleb128 0xb + 561 0023 3E .uleb128 0x3e + 562 0024 0B .uleb128 0xb + 563 0025 03 .uleb128 0x3 + 564 0026 08 .uleb128 0x8 + 565 0027 00 .byte 0 + 566 0028 00 .byte 0 + 567 0029 04 .uleb128 0x4 + 568 002a 16 .uleb128 0x16 + 569 002b 00 .byte 0 + 570 002c 03 .uleb128 0x3 + 571 002d 0E .uleb128 0xe + 572 002e 3A .uleb128 0x3a + 573 002f 0B .uleb128 0xb + 574 0030 3B .uleb128 0x3b + 575 0031 05 .uleb128 0x5 + 576 0032 49 .uleb128 0x49 + 577 0033 13 .uleb128 0x13 + 578 0034 00 .byte 0 + 579 0035 00 .byte 0 + 580 0036 05 .uleb128 0x5 + 581 0037 35 .uleb128 0x35 + 582 0038 00 .byte 0 + 583 0039 49 .uleb128 0x49 + 584 003a 13 .uleb128 0x13 + 585 003b 00 .byte 0 + 586 003c 00 .byte 0 + 587 003d 06 .uleb128 0x6 + 588 003e 2E .uleb128 0x2e + 589 003f 01 .byte 0x1 + 590 0040 3F .uleb128 0x3f + 591 0041 19 .uleb128 0x19 + 592 0042 03 .uleb128 0x3 + 593 0043 0E .uleb128 0xe + 594 0044 3A .uleb128 0x3a + 595 0045 0B .uleb128 0xb + 596 0046 3B .uleb128 0x3b + 597 0047 0B .uleb128 0xb + 598 0048 27 .uleb128 0x27 + 599 0049 19 .uleb128 0x19 + 600 004a 11 .uleb128 0x11 + 601 004b 01 .uleb128 0x1 + 602 004c 12 .uleb128 0x12 + 603 004d 06 .uleb128 0x6 + 604 004e 40 .uleb128 0x40 + 605 004f 18 .uleb128 0x18 + 606 0050 9742 .uleb128 0x2117 + 607 0052 19 .uleb128 0x19 + 608 0053 01 .uleb128 0x1 + 609 0054 13 .uleb128 0x13 + 610 0055 00 .byte 0 + 611 0056 00 .byte 0 + 612 0057 07 .uleb128 0x7 + 613 0058 05 .uleb128 0x5 + 614 0059 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 16 + + + 615 005a 03 .uleb128 0x3 + 616 005b 0E .uleb128 0xe + 617 005c 3A .uleb128 0x3a + 618 005d 0B .uleb128 0xb + 619 005e 3B .uleb128 0x3b + 620 005f 0B .uleb128 0xb + 621 0060 49 .uleb128 0x49 + 622 0061 13 .uleb128 0x13 + 623 0062 02 .uleb128 0x2 + 624 0063 18 .uleb128 0x18 + 625 0064 00 .byte 0 + 626 0065 00 .byte 0 + 627 0066 08 .uleb128 0x8 + 628 0067 34 .uleb128 0x34 + 629 0068 00 .byte 0 + 630 0069 03 .uleb128 0x3 + 631 006a 0E .uleb128 0xe + 632 006b 3A .uleb128 0x3a + 633 006c 0B .uleb128 0xb + 634 006d 3B .uleb128 0x3b + 635 006e 0B .uleb128 0xb + 636 006f 49 .uleb128 0x49 + 637 0070 13 .uleb128 0x13 + 638 0071 02 .uleb128 0x2 + 639 0072 18 .uleb128 0x18 + 640 0073 00 .byte 0 + 641 0074 00 .byte 0 + 642 0075 09 .uleb128 0x9 + 643 0076 2E .uleb128 0x2e + 644 0077 00 .byte 0 + 645 0078 3F .uleb128 0x3f + 646 0079 19 .uleb128 0x19 + 647 007a 03 .uleb128 0x3 + 648 007b 0E .uleb128 0xe + 649 007c 3A .uleb128 0x3a + 650 007d 0B .uleb128 0xb + 651 007e 3B .uleb128 0x3b + 652 007f 0B .uleb128 0xb + 653 0080 27 .uleb128 0x27 + 654 0081 19 .uleb128 0x19 + 655 0082 49 .uleb128 0x49 + 656 0083 13 .uleb128 0x13 + 657 0084 11 .uleb128 0x11 + 658 0085 01 .uleb128 0x1 + 659 0086 12 .uleb128 0x12 + 660 0087 06 .uleb128 0x6 + 661 0088 40 .uleb128 0x40 + 662 0089 18 .uleb128 0x18 + 663 008a 9742 .uleb128 0x2117 + 664 008c 19 .uleb128 0x19 + 665 008d 00 .byte 0 + 666 008e 00 .byte 0 + 667 008f 0A .uleb128 0xa + 668 0090 2E .uleb128 0x2e + 669 0091 01 .byte 0x1 + 670 0092 3F .uleb128 0x3f + 671 0093 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 17 + + + 672 0094 03 .uleb128 0x3 + 673 0095 0E .uleb128 0xe + 674 0096 3A .uleb128 0x3a + 675 0097 0B .uleb128 0xb + 676 0098 3B .uleb128 0x3b + 677 0099 0B .uleb128 0xb + 678 009a 27 .uleb128 0x27 + 679 009b 19 .uleb128 0x19 + 680 009c 49 .uleb128 0x49 + 681 009d 13 .uleb128 0x13 + 682 009e 11 .uleb128 0x11 + 683 009f 01 .uleb128 0x1 + 684 00a0 12 .uleb128 0x12 + 685 00a1 06 .uleb128 0x6 + 686 00a2 40 .uleb128 0x40 + 687 00a3 18 .uleb128 0x18 + 688 00a4 9742 .uleb128 0x2117 + 689 00a6 19 .uleb128 0x19 + 690 00a7 00 .byte 0 + 691 00a8 00 .byte 0 + 692 00a9 00 .byte 0 + 693 .section .debug_aranges,"",%progbits + 694 0000 44000000 .4byte 0x44 + 695 0004 0200 .2byte 0x2 + 696 0006 00000000 .4byte .Ldebug_info0 + 697 000a 04 .byte 0x4 + 698 000b 00 .byte 0 + 699 000c 0000 .2byte 0 + 700 000e 0000 .2byte 0 + 701 0010 00000000 .4byte .LFB0 + 702 0014 30000000 .4byte .LFE0-.LFB0 + 703 0018 00000000 .4byte .LFB1 + 704 001c 50000000 .4byte .LFE1-.LFB1 + 705 0020 00000000 .4byte .LFB2 + 706 0024 1C000000 .4byte .LFE2-.LFB2 + 707 0028 00000000 .4byte .LFB3 + 708 002c 1C000000 .4byte .LFE3-.LFB3 + 709 0030 00000000 .4byte .LFB4 + 710 0034 44000000 .4byte .LFE4-.LFB4 + 711 0038 00000000 .4byte .LFB5 + 712 003c 30000000 .4byte .LFE5-.LFB5 + 713 0040 00000000 .4byte 0 + 714 0044 00000000 .4byte 0 + 715 .section .debug_ranges,"",%progbits + 716 .Ldebug_ranges0: + 717 0000 00000000 .4byte .LFB0 + 718 0004 30000000 .4byte .LFE0 + 719 0008 00000000 .4byte .LFB1 + 720 000c 50000000 .4byte .LFE1 + 721 0010 00000000 .4byte .LFB2 + 722 0014 1C000000 .4byte .LFE2 + 723 0018 00000000 .4byte .LFB3 + 724 001c 1C000000 .4byte .LFE3 + 725 0020 00000000 .4byte .LFB4 + 726 0024 44000000 .4byte .LFE4 + 727 0028 00000000 .4byte .LFB5 + 728 002c 30000000 .4byte .LFE5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 18 + + + 729 0030 00000000 .4byte 0 + 730 0034 00000000 .4byte 0 + 731 .section .debug_line,"",%progbits + 732 .Ldebug_line0: + 733 0000 BB000000 .section .debug_str,"MS",%progbits,1 + 733 02004400 + 733 00000201 + 733 FB0E0D00 + 733 01010101 + 734 .LASF15: + 735 0000 72656733 .ascii "reg32\000" + 735 3200 + 736 .LASF19: + 737 0006 76616C75 .ascii "value\000" + 737 6500 + 738 .LASF30: + 739 000c 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 739 73657273 + 739 5C6A6167 + 739 756D6965 + 739 6C5C446F + 740 003a 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 740 50536F43 + 740 2D313031 + 740 5C547261 + 740 696E696E + 741 .LASF12: + 742 0067 666C6F61 .ascii "float\000" + 742 7400 + 743 .LASF1: + 744 006d 756E7369 .ascii "unsigned char\000" + 744 676E6564 + 744 20636861 + 744 7200 + 745 .LASF24: + 746 007b 64725661 .ascii "drVal\000" + 746 6C00 + 747 .LASF5: + 748 0081 6C6F6E67 .ascii "long unsigned int\000" + 748 20756E73 + 748 69676E65 + 748 6420696E + 748 7400 + 749 .LASF17: + 750 0093 55415254 .ascii "UART_tx_Write\000" + 750 5F74785F + 750 57726974 + 750 6500 + 751 .LASF3: + 752 00a1 73686F72 .ascii "short unsigned int\000" + 752 7420756E + 752 7369676E + 752 65642069 + 752 6E7400 + 753 .LASF26: + 754 00b4 55415254 .ascii "UART_tx_ClearInterrupt\000" + 754 5F74785F + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 19 + + + 754 436C6561 + 754 72496E74 + 754 65727275 + 755 .LASF28: + 756 00cb 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 756 43313120 + 756 352E342E + 756 31203230 + 756 31363036 + 757 00fe 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 757 20726576 + 757 6973696F + 757 6E203233 + 757 37373135 + 758 0131 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 758 66756E63 + 758 74696F6E + 758 2D736563 + 758 74696F6E + 759 .LASF13: + 760 0159 646F7562 .ascii "double\000" + 760 6C6500 + 761 .LASF10: + 762 0160 75696E74 .ascii "uint16\000" + 762 313600 + 763 .LASF23: + 764 0167 706F7369 .ascii "position\000" + 764 74696F6E + 764 00 + 765 .LASF11: + 766 0170 75696E74 .ascii "uint32\000" + 766 333200 + 767 .LASF25: + 768 0177 696E7472 .ascii "intrCfg\000" + 768 43666700 + 769 .LASF8: + 770 017f 756E7369 .ascii "unsigned int\000" + 770 676E6564 + 770 20696E74 + 770 00 + 771 .LASF7: + 772 018c 6C6F6E67 .ascii "long long unsigned int\000" + 772 206C6F6E + 772 6720756E + 772 7369676E + 772 65642069 + 773 .LASF18: + 774 01a3 6D6F6465 .ascii "mode\000" + 774 00 + 775 .LASF21: + 776 01a8 55415254 .ascii "UART_tx_ReadDataReg\000" + 776 5F74785F + 776 52656164 + 776 44617461 + 776 52656700 + 777 .LASF20: + 778 01bc 55415254 .ascii "UART_tx_Read\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccfnxAg7.s page 20 + + + 778 5F74785F + 778 52656164 + 778 00 + 779 .LASF6: + 780 01c9 6C6F6E67 .ascii "long long int\000" + 780 206C6F6E + 780 6720696E + 780 7400 + 781 .LASF16: + 782 01d7 55415254 .ascii "UART_tx_SetDriveMode\000" + 782 5F74785F + 782 53657444 + 782 72697665 + 782 4D6F6465 + 783 .LASF27: + 784 01ec 6D61736B .ascii "maskedStatus\000" + 784 65645374 + 784 61747573 + 784 00 + 785 .LASF14: + 786 01f9 63686172 .ascii "char\000" + 786 00 + 787 .LASF29: + 788 01fe 47656E65 .ascii "Generated_Source\\PSoC4\\UART_tx.c\000" + 788 72617465 + 788 645F536F + 788 75726365 + 788 5C50536F + 789 .LASF22: + 790 021f 55415254 .ascii "UART_tx_SetInterruptMode\000" + 790 5F74785F + 790 53657449 + 790 6E746572 + 790 72757074 + 791 .LASF2: + 792 0238 73686F72 .ascii "short int\000" + 792 7420696E + 792 7400 + 793 .LASF9: + 794 0242 75696E74 .ascii "uint8\000" + 794 3800 + 795 .LASF4: + 796 0248 6C6F6E67 .ascii "long int\000" + 796 20696E74 + 796 00 + 797 .LASF0: + 798 0251 7369676E .ascii "signed char\000" + 798 65642063 + 798 68617200 + 799 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_tx.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_tx.o new file mode 100644 index 0000000000000000000000000000000000000000..71642a65d0a91573b7ffffd33ea18321ec3c466a GIT binary patch literal 5016 zcmbtXTWlOx89p<6^(BsDr;X#pWfKfdMR#MTNt&hv)?L?0Z~|@;15r}Nv%BNbnU4@G?lR7h2u7sRDc78MUXv=)@_J9EzN z?8Yh}erfhU|Lr^H|Ic-wc=*VaVHiS_A$EwCB*ff$X^HKYY=_t)hQ!j#-?$=PGR5l1 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zA@a@S!$NE$-y-mW5A-_~->dim#hEYTrWHS?_({d(3la8;k{1=fp!lKua^SwG{C+M!PB49_>20Np4r^%fH=n+lFa3cWj#sokV-ZZX$9P_sg!HBhCn4mrr=chXbeZqyH*uWxcf7f@4MxE!w2ktOW3yZtkSmt z=QK?E_Syy|mUHv=>hzXMh5zWsHOQE7zhjU!am|ws;tTr~A=wfvSl{8k`O;?tz@ehNhxZw$g(dAzRtbo?CrzRy5Ky7?Q(yaBUH ze;NDe5R5!)c@wf<*7pzibPSr}15DJ<*-)fy??TpXnl9t{aY*@)Y1^OB4)?p#8|-WL z%Nthr`+g_}O|b$z?te`h?;lWv@kRkM2OaTvLu)+#d)F~gi%}SU&4wavOP~?Py8t}a znRqx#ns}QOo}Pn01MgA2h~Y;(e%m|zvI!v^=rw7-oyt$^ufUIUsfl@zcvpnScP*4J z?@OI8?+}!%E`#v1h{+t+0yz66F(>#nX(P_hBiab9Zjy)66E6a<4h61dc`viyetaBT P7;h`q)l<-E(s=&{rf|q1 literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_tx_PM.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_tx_PM.lst new file mode 100644 index 0000000..5bc8e23 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_tx_PM.lst @@ -0,0 +1,664 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "UART_tx_PM.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .bss + 20 .align 2 + 21 UART_tx_backup: + 22 0000 00000000 .space 12 + 22 00000000 + 22 00000000 + 23 .section .text.UART_tx_Sleep,"ax",%progbits + 24 .align 2 + 25 .global UART_tx_Sleep + 26 .code 16 + 27 .thumb_func + 28 .type UART_tx_Sleep, %function + 29 UART_tx_Sleep: + 30 .LFB0: + 31 .file 1 "Generated_Source\\PSoC4\\UART_tx_PM.c" + 1:Generated_Source\PSoC4/UART_tx_PM.c **** /******************************************************************************* + 2:Generated_Source\PSoC4/UART_tx_PM.c **** * File Name: UART_tx.c + 3:Generated_Source\PSoC4/UART_tx_PM.c **** * Version 2.20 + 4:Generated_Source\PSoC4/UART_tx_PM.c **** * + 5:Generated_Source\PSoC4/UART_tx_PM.c **** * Description: + 6:Generated_Source\PSoC4/UART_tx_PM.c **** * This file contains APIs to set up the Pins component for low power modes. + 7:Generated_Source\PSoC4/UART_tx_PM.c **** * + 8:Generated_Source\PSoC4/UART_tx_PM.c **** * Note: + 9:Generated_Source\PSoC4/UART_tx_PM.c **** * + 10:Generated_Source\PSoC4/UART_tx_PM.c **** ******************************************************************************** + 11:Generated_Source\PSoC4/UART_tx_PM.c **** * Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. + 12:Generated_Source\PSoC4/UART_tx_PM.c **** * You may use this file only in accordance with the license, terms, conditions, + 13:Generated_Source\PSoC4/UART_tx_PM.c **** * disclaimers, and limitations in the end user license agreement accompanying + 14:Generated_Source\PSoC4/UART_tx_PM.c **** * the software package with which this file was provided. + 15:Generated_Source\PSoC4/UART_tx_PM.c **** *******************************************************************************/ + 16:Generated_Source\PSoC4/UART_tx_PM.c **** + 17:Generated_Source\PSoC4/UART_tx_PM.c **** #include "cytypes.h" + 18:Generated_Source\PSoC4/UART_tx_PM.c **** #include "UART_tx.h" + 19:Generated_Source\PSoC4/UART_tx_PM.c **** + 20:Generated_Source\PSoC4/UART_tx_PM.c **** static UART_tx_BACKUP_STRUCT UART_tx_backup = {0u, 0u, 0u}; + 21:Generated_Source\PSoC4/UART_tx_PM.c **** + 22:Generated_Source\PSoC4/UART_tx_PM.c **** + 23:Generated_Source\PSoC4/UART_tx_PM.c **** /******************************************************************************* + 24:Generated_Source\PSoC4/UART_tx_PM.c **** * Function Name: UART_tx_Sleep + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 2 + + + 25:Generated_Source\PSoC4/UART_tx_PM.c **** ****************************************************************************//** + 26:Generated_Source\PSoC4/UART_tx_PM.c **** * + 27:Generated_Source\PSoC4/UART_tx_PM.c **** * \brief Stores the pin configuration and prepares the pin for entering chip + 28:Generated_Source\PSoC4/UART_tx_PM.c **** * deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. + 29:Generated_Source\PSoC4/UART_tx_PM.c **** * It should not be called for GPIO or GPIO_OVT pins. + 30:Generated_Source\PSoC4/UART_tx_PM.c **** * + 31:Generated_Source\PSoC4/UART_tx_PM.c **** * Note This function is available in PSoC 4 only. + 32:Generated_Source\PSoC4/UART_tx_PM.c **** * + 33:Generated_Source\PSoC4/UART_tx_PM.c **** * \return + 34:Generated_Source\PSoC4/UART_tx_PM.c **** * None + 35:Generated_Source\PSoC4/UART_tx_PM.c **** * + 36:Generated_Source\PSoC4/UART_tx_PM.c **** * \sideeffect + 37:Generated_Source\PSoC4/UART_tx_PM.c **** * For SIO pins, this function configures the pin input threshold to CMOS and + 38:Generated_Source\PSoC4/UART_tx_PM.c **** * drive level to Vddio. This is needed for SIO pins when in device + 39:Generated_Source\PSoC4/UART_tx_PM.c **** * deep-sleep/hibernate modes. + 40:Generated_Source\PSoC4/UART_tx_PM.c **** * + 41:Generated_Source\PSoC4/UART_tx_PM.c **** * \funcusage + 42:Generated_Source\PSoC4/UART_tx_PM.c **** * \snippet UART_tx_SUT.c usage_UART_tx_Sleep_Wakeup + 43:Generated_Source\PSoC4/UART_tx_PM.c **** *******************************************************************************/ + 44:Generated_Source\PSoC4/UART_tx_PM.c **** void UART_tx_Sleep(void) + 45:Generated_Source\PSoC4/UART_tx_PM.c **** { + 32 .loc 1 45 0 + 33 .cfi_startproc + 34 @ args = 0, pretend = 0, frame = 0 + 35 @ frame_needed = 1, uses_anonymous_args = 0 + 36 0000 80B5 push {r7, lr} + 37 .cfi_def_cfa_offset 8 + 38 .cfi_offset 7, -8 + 39 .cfi_offset 14, -4 + 40 0002 00AF add r7, sp, #0 + 41 .cfi_def_cfa_register 7 + 46:Generated_Source\PSoC4/UART_tx_PM.c **** #if defined(UART_tx__PC) + 47:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_backup.pcState = UART_tx_PC; + 42 .loc 1 47 0 + 43 0004 034B ldr r3, .L2 + 44 0006 1A68 ldr r2, [r3] + 45 0008 034B ldr r3, .L2+4 + 46 000a 1A60 str r2, [r3] + 48:Generated_Source\PSoC4/UART_tx_PM.c **** #else + 49:Generated_Source\PSoC4/UART_tx_PM.c **** #if (CY_PSOC4_4200L) + 50:Generated_Source\PSoC4/UART_tx_PM.c **** /* Save the regulator state and put the PHY into suspend mode */ + 51:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_backup.usbState = UART_tx_CR1_REG; + 52:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_USB_POWER_REG |= UART_tx_USBIO_ENTER_SLEEP; + 53:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_CR1_REG &= UART_tx_USBIO_CR1_OFF; + 54:Generated_Source\PSoC4/UART_tx_PM.c **** #endif + 55:Generated_Source\PSoC4/UART_tx_PM.c **** #endif + 56:Generated_Source\PSoC4/UART_tx_PM.c **** #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_tx__SIO) + 57:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_backup.sioState = UART_tx_SIO_REG; + 58:Generated_Source\PSoC4/UART_tx_PM.c **** /* SIO requires unregulated output buffer and single ended input buffer */ + 59:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_SIO_REG &= (uint32)(~UART_tx_SIO_LPM_MASK); + 60:Generated_Source\PSoC4/UART_tx_PM.c **** #endif + 61:Generated_Source\PSoC4/UART_tx_PM.c **** } + 47 .loc 1 61 0 + 48 000c C046 nop + 49 000e BD46 mov sp, r7 + 50 @ sp needed + 51 0010 80BD pop {r7, pc} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 3 + + + 52 .L3: + 53 0012 C046 .align 2 + 54 .L2: + 55 0014 08040440 .word 1074005000 + 56 0018 00000000 .word UART_tx_backup + 57 .cfi_endproc + 58 .LFE0: + 59 .size UART_tx_Sleep, .-UART_tx_Sleep + 60 .section .text.UART_tx_Wakeup,"ax",%progbits + 61 .align 2 + 62 .global UART_tx_Wakeup + 63 .code 16 + 64 .thumb_func + 65 .type UART_tx_Wakeup, %function + 66 UART_tx_Wakeup: + 67 .LFB1: + 62:Generated_Source\PSoC4/UART_tx_PM.c **** + 63:Generated_Source\PSoC4/UART_tx_PM.c **** + 64:Generated_Source\PSoC4/UART_tx_PM.c **** /******************************************************************************* + 65:Generated_Source\PSoC4/UART_tx_PM.c **** * Function Name: UART_tx_Wakeup + 66:Generated_Source\PSoC4/UART_tx_PM.c **** ****************************************************************************//** + 67:Generated_Source\PSoC4/UART_tx_PM.c **** * + 68:Generated_Source\PSoC4/UART_tx_PM.c **** * \brief Restores the pin configuration that was saved during Pin_Sleep(). This + 69:Generated_Source\PSoC4/UART_tx_PM.c **** * function applies only to SIO and USBIO pins. It should not be called for + 70:Generated_Source\PSoC4/UART_tx_PM.c **** * GPIO or GPIO_OVT pins. + 71:Generated_Source\PSoC4/UART_tx_PM.c **** * + 72:Generated_Source\PSoC4/UART_tx_PM.c **** * For USBIO pins, the wakeup is only triggered for falling edge interrupts. + 73:Generated_Source\PSoC4/UART_tx_PM.c **** * + 74:Generated_Source\PSoC4/UART_tx_PM.c **** * Note This function is available in PSoC 4 only. + 75:Generated_Source\PSoC4/UART_tx_PM.c **** * + 76:Generated_Source\PSoC4/UART_tx_PM.c **** * \return + 77:Generated_Source\PSoC4/UART_tx_PM.c **** * None + 78:Generated_Source\PSoC4/UART_tx_PM.c **** * + 79:Generated_Source\PSoC4/UART_tx_PM.c **** * \funcusage + 80:Generated_Source\PSoC4/UART_tx_PM.c **** * Refer to UART_tx_Sleep() for an example usage. + 81:Generated_Source\PSoC4/UART_tx_PM.c **** *******************************************************************************/ + 82:Generated_Source\PSoC4/UART_tx_PM.c **** void UART_tx_Wakeup(void) + 83:Generated_Source\PSoC4/UART_tx_PM.c **** { + 68 .loc 1 83 0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 1, uses_anonymous_args = 0 + 72 0000 80B5 push {r7, lr} + 73 .cfi_def_cfa_offset 8 + 74 .cfi_offset 7, -8 + 75 .cfi_offset 14, -4 + 76 0002 00AF add r7, sp, #0 + 77 .cfi_def_cfa_register 7 + 84:Generated_Source\PSoC4/UART_tx_PM.c **** #if defined(UART_tx__PC) + 85:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_PC = UART_tx_backup.pcState; + 78 .loc 1 85 0 + 79 0004 034A ldr r2, .L5 + 80 0006 044B ldr r3, .L5+4 + 81 0008 1B68 ldr r3, [r3] + 82 000a 1360 str r3, [r2] + 86:Generated_Source\PSoC4/UART_tx_PM.c **** #else + 87:Generated_Source\PSoC4/UART_tx_PM.c **** #if (CY_PSOC4_4200L) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 4 + + + 88:Generated_Source\PSoC4/UART_tx_PM.c **** /* Restore the regulator state and come out of suspend mode */ + 89:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_USB_POWER_REG &= UART_tx_USBIO_EXIT_SLEEP_PH1; + 90:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_CR1_REG = UART_tx_backup.usbState; + 91:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_USB_POWER_REG &= UART_tx_USBIO_EXIT_SLEEP_PH2; + 92:Generated_Source\PSoC4/UART_tx_PM.c **** #endif + 93:Generated_Source\PSoC4/UART_tx_PM.c **** #endif + 94:Generated_Source\PSoC4/UART_tx_PM.c **** #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_tx__SIO) + 95:Generated_Source\PSoC4/UART_tx_PM.c **** UART_tx_SIO_REG = UART_tx_backup.sioState; + 96:Generated_Source\PSoC4/UART_tx_PM.c **** #endif + 97:Generated_Source\PSoC4/UART_tx_PM.c **** } + 83 .loc 1 97 0 + 84 000c C046 nop + 85 000e BD46 mov sp, r7 + 86 @ sp needed + 87 0010 80BD pop {r7, pc} + 88 .L6: + 89 0012 C046 .align 2 + 90 .L5: + 91 0014 08040440 .word 1074005000 + 92 0018 00000000 .word UART_tx_backup + 93 .cfi_endproc + 94 .LFE1: + 95 .size UART_tx_Wakeup, .-UART_tx_Wakeup + 96 .text + 97 .Letext0: + 98 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 99 .file 3 "Generated_Source\\PSoC4\\UART_tx.h" + 100 .section .debug_info,"",%progbits + 101 .Ldebug_info0: + 102 0000 05010000 .4byte 0x105 + 103 0004 0400 .2byte 0x4 + 104 0006 00000000 .4byte .Ldebug_abbrev0 + 105 000a 04 .byte 0x4 + 106 000b 01 .uleb128 0x1 + 107 000c A3000000 .4byte .LASF20 + 108 0010 0C .byte 0xc + 109 0011 31010000 .4byte .LASF21 + 110 0015 0F000000 .4byte .LASF22 + 111 0019 00000000 .4byte .Ldebug_ranges0+0 + 112 001d 00000000 .4byte 0 + 113 0021 00000000 .4byte .Ldebug_line0 + 114 0025 02 .uleb128 0x2 + 115 0026 01 .byte 0x1 + 116 0027 06 .byte 0x6 + 117 0028 F1010000 .4byte .LASF0 + 118 002c 02 .uleb128 0x2 + 119 002d 01 .byte 0x1 + 120 002e 08 .byte 0x8 + 121 002f 70000000 .4byte .LASF1 + 122 0033 02 .uleb128 0x2 + 123 0034 02 .byte 0x2 + 124 0035 05 .byte 0x5 + 125 0036 B2010000 .4byte .LASF2 + 126 003a 02 .uleb128 0x2 + 127 003b 02 .byte 0x2 + 128 003c 07 .byte 0x7 + 129 003d 90000000 .4byte .LASF3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 5 + + + 130 0041 02 .uleb128 0x2 + 131 0042 04 .byte 0x4 + 132 0043 05 .byte 0x5 + 133 0044 C4010000 .4byte .LASF4 + 134 0048 02 .uleb128 0x2 + 135 0049 04 .byte 0x4 + 136 004a 07 .byte 0x7 + 137 004b 7E000000 .4byte .LASF5 + 138 004f 02 .uleb128 0x2 + 139 0050 08 .byte 0x8 + 140 0051 05 .byte 0x5 + 141 0052 90010000 .4byte .LASF6 + 142 0056 02 .uleb128 0x2 + 143 0057 08 .byte 0x8 + 144 0058 07 .byte 0x7 + 145 0059 70010000 .4byte .LASF7 + 146 005d 03 .uleb128 0x3 + 147 005e 04 .byte 0x4 + 148 005f 05 .byte 0x5 + 149 0060 696E7400 .ascii "int\000" + 150 0064 02 .uleb128 0x2 + 151 0065 04 .byte 0x4 + 152 0066 07 .byte 0x7 + 153 0067 63010000 .4byte .LASF8 + 154 006b 04 .uleb128 0x4 + 155 006c 5C010000 .4byte .LASF12 + 156 0070 02 .byte 0x2 + 157 0071 E601 .2byte 0x1e6 + 158 0073 48000000 .4byte 0x48 + 159 0077 02 .uleb128 0x2 + 160 0078 04 .byte 0x4 + 161 0079 04 .byte 0x4 + 162 007a 6A000000 .4byte .LASF9 + 163 007e 02 .uleb128 0x2 + 164 007f 08 .byte 0x8 + 165 0080 04 .byte 0x4 + 166 0081 55010000 .4byte .LASF10 + 167 0085 02 .uleb128 0x2 + 168 0086 01 .byte 0x1 + 169 0087 08 .byte 0x8 + 170 0088 9E010000 .4byte .LASF11 + 171 008c 04 .uleb128 0x4 + 172 008d 00000000 .4byte .LASF13 + 173 0091 02 .byte 0x2 + 174 0092 9002 .2byte 0x290 + 175 0094 98000000 .4byte 0x98 + 176 0098 05 .uleb128 0x5 + 177 0099 6B000000 .4byte 0x6b + 178 009d 06 .uleb128 0x6 + 179 009e 0C .byte 0xc + 180 009f 03 .byte 0x3 + 181 00a0 21 .byte 0x21 + 182 00a1 CA000000 .4byte 0xca + 183 00a5 07 .uleb128 0x7 + 184 00a6 BC010000 .4byte .LASF14 + 185 00aa 03 .byte 0x3 + 186 00ab 23 .byte 0x23 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 6 + + + 187 00ac 6B000000 .4byte 0x6b + 188 00b0 00 .byte 0 + 189 00b1 07 .uleb128 0x7 + 190 00b2 87010000 .4byte .LASF15 + 191 00b6 03 .byte 0x3 + 192 00b7 24 .byte 0x24 + 193 00b8 6B000000 .4byte 0x6b + 194 00bc 04 .byte 0x4 + 195 00bd 07 .uleb128 0x7 + 196 00be 06000000 .4byte .LASF16 + 197 00c2 03 .byte 0x3 + 198 00c3 25 .byte 0x25 + 199 00c4 6B000000 .4byte 0x6b + 200 00c8 08 .byte 0x8 + 201 00c9 00 .byte 0 + 202 00ca 08 .uleb128 0x8 + 203 00cb CD010000 .4byte .LASF17 + 204 00cf 03 .byte 0x3 + 205 00d0 26 .byte 0x26 + 206 00d1 9D000000 .4byte 0x9d + 207 00d5 09 .uleb128 0x9 + 208 00d6 E3010000 .4byte .LASF18 + 209 00da 01 .byte 0x1 + 210 00db 2C .byte 0x2c + 211 00dc 00000000 .4byte .LFB0 + 212 00e0 1C000000 .4byte .LFE0-.LFB0 + 213 00e4 01 .uleb128 0x1 + 214 00e5 9C .byte 0x9c + 215 00e6 09 .uleb128 0x9 + 216 00e7 FD010000 .4byte .LASF19 + 217 00eb 01 .byte 0x1 + 218 00ec 52 .byte 0x52 + 219 00ed 00000000 .4byte .LFB1 + 220 00f1 1C000000 .4byte .LFE1-.LFB1 + 221 00f5 01 .uleb128 0x1 + 222 00f6 9C .byte 0x9c + 223 00f7 0A .uleb128 0xa + 224 00f8 A3010000 .4byte .LASF23 + 225 00fc 01 .byte 0x1 + 226 00fd 14 .byte 0x14 + 227 00fe CA000000 .4byte 0xca + 228 0102 05 .uleb128 0x5 + 229 0103 03 .byte 0x3 + 230 0104 00000000 .4byte UART_tx_backup + 231 0108 00 .byte 0 + 232 .section .debug_abbrev,"",%progbits + 233 .Ldebug_abbrev0: + 234 0000 01 .uleb128 0x1 + 235 0001 11 .uleb128 0x11 + 236 0002 01 .byte 0x1 + 237 0003 25 .uleb128 0x25 + 238 0004 0E .uleb128 0xe + 239 0005 13 .uleb128 0x13 + 240 0006 0B .uleb128 0xb + 241 0007 03 .uleb128 0x3 + 242 0008 0E .uleb128 0xe + 243 0009 1B .uleb128 0x1b + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 7 + + + 244 000a 0E .uleb128 0xe + 245 000b 55 .uleb128 0x55 + 246 000c 17 .uleb128 0x17 + 247 000d 11 .uleb128 0x11 + 248 000e 01 .uleb128 0x1 + 249 000f 10 .uleb128 0x10 + 250 0010 17 .uleb128 0x17 + 251 0011 00 .byte 0 + 252 0012 00 .byte 0 + 253 0013 02 .uleb128 0x2 + 254 0014 24 .uleb128 0x24 + 255 0015 00 .byte 0 + 256 0016 0B .uleb128 0xb + 257 0017 0B .uleb128 0xb + 258 0018 3E .uleb128 0x3e + 259 0019 0B .uleb128 0xb + 260 001a 03 .uleb128 0x3 + 261 001b 0E .uleb128 0xe + 262 001c 00 .byte 0 + 263 001d 00 .byte 0 + 264 001e 03 .uleb128 0x3 + 265 001f 24 .uleb128 0x24 + 266 0020 00 .byte 0 + 267 0021 0B .uleb128 0xb + 268 0022 0B .uleb128 0xb + 269 0023 3E .uleb128 0x3e + 270 0024 0B .uleb128 0xb + 271 0025 03 .uleb128 0x3 + 272 0026 08 .uleb128 0x8 + 273 0027 00 .byte 0 + 274 0028 00 .byte 0 + 275 0029 04 .uleb128 0x4 + 276 002a 16 .uleb128 0x16 + 277 002b 00 .byte 0 + 278 002c 03 .uleb128 0x3 + 279 002d 0E .uleb128 0xe + 280 002e 3A .uleb128 0x3a + 281 002f 0B .uleb128 0xb + 282 0030 3B .uleb128 0x3b + 283 0031 05 .uleb128 0x5 + 284 0032 49 .uleb128 0x49 + 285 0033 13 .uleb128 0x13 + 286 0034 00 .byte 0 + 287 0035 00 .byte 0 + 288 0036 05 .uleb128 0x5 + 289 0037 35 .uleb128 0x35 + 290 0038 00 .byte 0 + 291 0039 49 .uleb128 0x49 + 292 003a 13 .uleb128 0x13 + 293 003b 00 .byte 0 + 294 003c 00 .byte 0 + 295 003d 06 .uleb128 0x6 + 296 003e 13 .uleb128 0x13 + 297 003f 01 .byte 0x1 + 298 0040 0B .uleb128 0xb + 299 0041 0B .uleb128 0xb + 300 0042 3A .uleb128 0x3a + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 8 + + + 301 0043 0B .uleb128 0xb + 302 0044 3B .uleb128 0x3b + 303 0045 0B .uleb128 0xb + 304 0046 01 .uleb128 0x1 + 305 0047 13 .uleb128 0x13 + 306 0048 00 .byte 0 + 307 0049 00 .byte 0 + 308 004a 07 .uleb128 0x7 + 309 004b 0D .uleb128 0xd + 310 004c 00 .byte 0 + 311 004d 03 .uleb128 0x3 + 312 004e 0E .uleb128 0xe + 313 004f 3A .uleb128 0x3a + 314 0050 0B .uleb128 0xb + 315 0051 3B .uleb128 0x3b + 316 0052 0B .uleb128 0xb + 317 0053 49 .uleb128 0x49 + 318 0054 13 .uleb128 0x13 + 319 0055 38 .uleb128 0x38 + 320 0056 0B .uleb128 0xb + 321 0057 00 .byte 0 + 322 0058 00 .byte 0 + 323 0059 08 .uleb128 0x8 + 324 005a 16 .uleb128 0x16 + 325 005b 00 .byte 0 + 326 005c 03 .uleb128 0x3 + 327 005d 0E .uleb128 0xe + 328 005e 3A .uleb128 0x3a + 329 005f 0B .uleb128 0xb + 330 0060 3B .uleb128 0x3b + 331 0061 0B .uleb128 0xb + 332 0062 49 .uleb128 0x49 + 333 0063 13 .uleb128 0x13 + 334 0064 00 .byte 0 + 335 0065 00 .byte 0 + 336 0066 09 .uleb128 0x9 + 337 0067 2E .uleb128 0x2e + 338 0068 00 .byte 0 + 339 0069 3F .uleb128 0x3f + 340 006a 19 .uleb128 0x19 + 341 006b 03 .uleb128 0x3 + 342 006c 0E .uleb128 0xe + 343 006d 3A .uleb128 0x3a + 344 006e 0B .uleb128 0xb + 345 006f 3B .uleb128 0x3b + 346 0070 0B .uleb128 0xb + 347 0071 27 .uleb128 0x27 + 348 0072 19 .uleb128 0x19 + 349 0073 11 .uleb128 0x11 + 350 0074 01 .uleb128 0x1 + 351 0075 12 .uleb128 0x12 + 352 0076 06 .uleb128 0x6 + 353 0077 40 .uleb128 0x40 + 354 0078 18 .uleb128 0x18 + 355 0079 9742 .uleb128 0x2117 + 356 007b 19 .uleb128 0x19 + 357 007c 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 9 + + + 358 007d 00 .byte 0 + 359 007e 0A .uleb128 0xa + 360 007f 34 .uleb128 0x34 + 361 0080 00 .byte 0 + 362 0081 03 .uleb128 0x3 + 363 0082 0E .uleb128 0xe + 364 0083 3A .uleb128 0x3a + 365 0084 0B .uleb128 0xb + 366 0085 3B .uleb128 0x3b + 367 0086 0B .uleb128 0xb + 368 0087 49 .uleb128 0x49 + 369 0088 13 .uleb128 0x13 + 370 0089 02 .uleb128 0x2 + 371 008a 18 .uleb128 0x18 + 372 008b 00 .byte 0 + 373 008c 00 .byte 0 + 374 008d 00 .byte 0 + 375 .section .debug_aranges,"",%progbits + 376 0000 24000000 .4byte 0x24 + 377 0004 0200 .2byte 0x2 + 378 0006 00000000 .4byte .Ldebug_info0 + 379 000a 04 .byte 0x4 + 380 000b 00 .byte 0 + 381 000c 0000 .2byte 0 + 382 000e 0000 .2byte 0 + 383 0010 00000000 .4byte .LFB0 + 384 0014 1C000000 .4byte .LFE0-.LFB0 + 385 0018 00000000 .4byte .LFB1 + 386 001c 1C000000 .4byte .LFE1-.LFB1 + 387 0020 00000000 .4byte 0 + 388 0024 00000000 .4byte 0 + 389 .section .debug_ranges,"",%progbits + 390 .Ldebug_ranges0: + 391 0000 00000000 .4byte .LFB0 + 392 0004 1C000000 .4byte .LFE0 + 393 0008 00000000 .4byte .LFB1 + 394 000c 1C000000 .4byte .LFE1 + 395 0010 00000000 .4byte 0 + 396 0014 00000000 .4byte 0 + 397 .section .debug_line,"",%progbits + 398 .Ldebug_line0: + 399 0000 81000000 .section .debug_str,"MS",%progbits,1 + 399 02005400 + 399 00000201 + 399 FB0E0D00 + 399 01010101 + 400 .LASF13: + 401 0000 72656733 .ascii "reg32\000" + 401 3200 + 402 .LASF16: + 403 0006 75736253 .ascii "usbState\000" + 403 74617465 + 403 00 + 404 .LASF22: + 405 000f 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 405 73657273 + 405 5C6A6167 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 10 + + + 405 756D6965 + 405 6C5C446F + 406 003d 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 406 50536F43 + 406 2D313031 + 406 5C547261 + 406 696E696E + 407 .LASF9: + 408 006a 666C6F61 .ascii "float\000" + 408 7400 + 409 .LASF1: + 410 0070 756E7369 .ascii "unsigned char\000" + 410 676E6564 + 410 20636861 + 410 7200 + 411 .LASF5: + 412 007e 6C6F6E67 .ascii "long unsigned int\000" + 412 20756E73 + 412 69676E65 + 412 6420696E + 412 7400 + 413 .LASF3: + 414 0090 73686F72 .ascii "short unsigned int\000" + 414 7420756E + 414 7369676E + 414 65642069 + 414 6E7400 + 415 .LASF20: + 416 00a3 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 416 43313120 + 416 352E342E + 416 31203230 + 416 31363036 + 417 00d6 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 417 20726576 + 417 6973696F + 417 6E203233 + 417 37373135 + 418 0109 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 418 66756E63 + 418 74696F6E + 418 2D736563 + 418 74696F6E + 419 .LASF21: + 420 0131 47656E65 .ascii "Generated_Source\\PSoC4\\UART_tx_PM.c\000" + 420 72617465 + 420 645F536F + 420 75726365 + 420 5C50536F + 421 .LASF10: + 422 0155 646F7562 .ascii "double\000" + 422 6C6500 + 423 .LASF12: + 424 015c 75696E74 .ascii "uint32\000" + 424 333200 + 425 .LASF8: + 426 0163 756E7369 .ascii "unsigned int\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 11 + + + 426 676E6564 + 426 20696E74 + 426 00 + 427 .LASF7: + 428 0170 6C6F6E67 .ascii "long long unsigned int\000" + 428 206C6F6E + 428 6720756E + 428 7369676E + 428 65642069 + 429 .LASF15: + 430 0187 73696F53 .ascii "sioState\000" + 430 74617465 + 430 00 + 431 .LASF6: + 432 0190 6C6F6E67 .ascii "long long int\000" + 432 206C6F6E + 432 6720696E + 432 7400 + 433 .LASF11: + 434 019e 63686172 .ascii "char\000" + 434 00 + 435 .LASF23: + 436 01a3 55415254 .ascii "UART_tx_backup\000" + 436 5F74785F + 436 6261636B + 436 757000 + 437 .LASF2: + 438 01b2 73686F72 .ascii "short int\000" + 438 7420696E + 438 7400 + 439 .LASF14: + 440 01bc 70635374 .ascii "pcState\000" + 440 61746500 + 441 .LASF4: + 442 01c4 6C6F6E67 .ascii "long int\000" + 442 20696E74 + 442 00 + 443 .LASF17: + 444 01cd 55415254 .ascii "UART_tx_BACKUP_STRUCT\000" + 444 5F74785F + 444 4241434B + 444 55505F53 + 444 54525543 + 445 .LASF18: + 446 01e3 55415254 .ascii "UART_tx_Sleep\000" + 446 5F74785F + 446 536C6565 + 446 7000 + 447 .LASF0: + 448 01f1 7369676E .ascii "signed char\000" + 448 65642063 + 448 68617200 + 449 .LASF19: + 450 01fd 55415254 .ascii "UART_tx_Wakeup\000" + 450 5F74785F + 450 57616B65 + 450 757000 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccQdXkUT.s page 12 + + + 451 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_tx_PM.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/UART_tx_PM.o new file mode 100644 index 0000000000000000000000000000000000000000..c58c40e29d44ddced946f6cbffb7bf841e44609a GIT binary patch literal 3528 zcmbtXOKcle6n!&e$4;G?eELg^&{R#^RMf8BCM^^dk~&R4ArR#wgh&;}G|B> zyYIetudkB}$Dbb4G)*Yd#DG|pg!s8Vw8RHP7!ZA8v$*(~_{13BR>6Al=Gcv~i#KkL zC1bH+x`ejVvGMJd-urBE1dfGqV%jxeM;?lYLdEKbuC?8PTGx_`Q0jX8Iwd`^Oeq$> zMJbkejZ!kcOevXI1Q@Y+wGq%}LyFDO@|$)t+!Z?;y2oaz)RG_20UDt%>+b^M=kU?i zVeI${nD_!#V<%N2ahZHS`B(+Lqds9YwdwOPe`0V2e%S)Xl<3A4xqCKh=xPLxRxO ztEE!Vr8EeM&Xz;!RPSRcWG4L~BD1V`sxRE0+SAvq^|TFdedk!85E}+p_UK!YO+S{- zv}AF}@hT*REooJb>My~liy3}uf2BJG+6fnC7ilM)hT~a*Q<|T4o1X2=O-{Q7w9@Rz z)XaQvetvQyYtzwQ3YHcfKU<+7jV%G!4s$d1X*nZ(T2CUpQhh6+>uBjbr+n~$X!^zJ z0OyI(BXhI9_|+6h%8PN3P;QVzW0pl)_ilp^-R32d0f7& ziQ3wZ@4KGA_kWiIa}3>n52OkG)pSRv;Fn4fzbGT=4H z+YL5eXq9*(hv}4Er}mVye{!eiC;_nLE=xugb=?=`41w>c~{CYJSy)U-WO$Ljp!e~ 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z^Yz2v<@*qP{Eo@TJfitBsC)VT0lk1n7tQxM7`%Kd&^g^d_Dl190d+6m7!-b&x@f*x z7`%M8hmSWr&G!Q8UcOUMhBcYOQGFJVm#@de7gIR)^JP35k#^sGx z$GzRh*MZGRoGzMgvybn#W+CPPA|Lm)=1ckb4uOyVM%6`Ecl!8#2EHUf + 22:Generated_Source\PSoC4/cy_em_eeprom.c **** + 23:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + 24:Generated_Source\PSoC4/cy_em_eeprom.c **** #include "em_eeprom/cy_em_eeprom.h" + 25:Generated_Source\PSoC4/cy_em_eeprom.c **** #else + 26:Generated_Source\PSoC4/cy_em_eeprom.c **** #include "cy_em_eeprom.h" + 27:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + 28:Generated_Source\PSoC4/cy_em_eeprom.c **** + 29:Generated_Source\PSoC4/cy_em_eeprom.c **** + 30:Generated_Source\PSoC4/cy_em_eeprom.c **** #if defined(__cplusplus) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 2 + + + 31:Generated_Source\PSoC4/cy_em_eeprom.c **** extern "C" { + 32:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif + 33:Generated_Source\PSoC4/cy_em_eeprom.c **** + 34:Generated_Source\PSoC4/cy_em_eeprom.c **** + 35:Generated_Source\PSoC4/cy_em_eeprom.c **** /*************************************** + 36:Generated_Source\PSoC4/cy_em_eeprom.c **** * Private Function Prototypes + 37:Generated_Source\PSoC4/cy_em_eeprom.c **** ***************************************/ + 38:Generated_Source\PSoC4/cy_em_eeprom.c **** static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context); + 39:Generated_Source\PSoC4/cy_em_eeprom.c **** static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context); + 40:Generated_Source\PSoC4/cy_em_eeprom.c **** static uint8 CalcChecksum(uint8 rowData[], uint32 len); + 41:Generated_Source\PSoC4/cy_em_eeprom.c **** static void GetNextRowToWrite(uint32 seqNum, + 42:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 * rowToWrPtr, + 43:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 * rowToRdPtr, + 44:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context); + 45:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config); + 46:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * + 47:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_ + 48:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + 49:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 dstAddr, + 50:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rowOffset, + 51:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 numBytes, + 52:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context); + 53:Generated_Source\PSoC4/cy_em_eeprom.c **** static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint3 + 54:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context); + 55:Generated_Source\PSoC4/cy_em_eeprom.c **** + 56:Generated_Source\PSoC4/cy_em_eeprom.c **** /** + 57:Generated_Source\PSoC4/cy_em_eeprom.c **** * \addtogroup group_em_eeprom_functions + 58:Generated_Source\PSoC4/cy_em_eeprom.c **** * \{ + 59:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 60:Generated_Source\PSoC4/cy_em_eeprom.c **** + 61:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 62:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: Cy_Em_EEPROM_Init + 63:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 64:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 65:Generated_Source\PSoC4/cy_em_eeprom.c **** * Initializes the Emulated EEPROM library by filling the context structure. + 66:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 67:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param config + 68:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. + 69:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 70:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 71:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure to be filled by the function. + 72:Generated_Source\PSoC4/cy_em_eeprom.c **** * \ref cy_stc_eeprom_context_t. + 73:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 74:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 75:Generated_Source\PSoC4/cy_em_eeprom.c **** * error / status code. See \ref cy_en_em_eeprom_status_t. + 76:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 77:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note + 78:Generated_Source\PSoC4/cy_em_eeprom.c **** * The context structure should not be modified by the user after it is filled + 79:Generated_Source\PSoC4/cy_em_eeprom.c **** * with this function. Modification of context structure may cause the + 80:Generated_Source\PSoC4/cy_em_eeprom.c **** * unexpected behavior of the Cy_Em_EEPROM API functions which rely on it. + 81:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 82:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note + 83:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function uses a buffer of the flash row size to perform read + 84:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation. For the size of the row refer to the specific PSoC device + 85:Generated_Source\PSoC4/cy_em_eeprom.c **** * datasheet. + 86:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 87:Generated_Source\PSoC4/cy_em_eeprom.c **** * \sideeffect + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 3 + + + 88:Generated_Source\PSoC4/cy_em_eeprom.c **** * If the "Redundant Copy" option is used, the function performs a number of + 89:Generated_Source\PSoC4/cy_em_eeprom.c **** * write operations to the EEPROM to initialize flash rows checksums. Therefore, + 90:Generated_Source\PSoC4/cy_em_eeprom.c **** * Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(), + 91:Generated_Source\PSoC4/cy_em_eeprom.c **** * will return a non-zero value that identifies the number of writes performed + 92:Generated_Source\PSoC4/cy_em_eeprom.c **** * by Cy_Em_EEPROM_Init(). + 93:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 94:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 95:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t + 96:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 28 .loc 1 96 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 16 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 90B5 push {r4, r7, lr} + 33 .cfi_def_cfa_offset 12 + 34 .cfi_offset 4, -12 + 35 .cfi_offset 7, -8 + 36 .cfi_offset 14, -4 + 37 0002 85B0 sub sp, sp, #20 + 38 .cfi_def_cfa_offset 32 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 42 0008 3960 str r1, [r7] + 97:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + 43 .loc 1 97 0 + 44 000a 0F23 movs r3, #15 + 45 000c FB18 adds r3, r7, r3 + 46 000e 0122 movs r2, #1 + 47 0010 1A70 strb r2, [r3] + 98:Generated_Source\PSoC4/cy_em_eeprom.c **** + 99:Generated_Source\PSoC4/cy_em_eeprom.c **** if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) && + 48 .loc 1 99 0 + 49 0012 3B68 ldr r3, [r7] + 50 0014 002B cmp r3, #0 + 51 0016 67D0 beq .L2 + 52 .loc 1 99 0 is_stmt 0 discriminator 1 + 53 0018 7B68 ldr r3, [r7, #4] + 54 001a 002B cmp r3, #0 + 55 001c 64D0 beq .L2 + 56 .loc 1 99 0 discriminator 2 + 57 001e 7B68 ldr r3, [r7, #4] + 58 0020 DB68 ldr r3, [r3, #12] + 59 0022 002B cmp r3, #0 + 60 0024 60D0 beq .L2 + 100:Generated_Source\PSoC4/cy_em_eeprom.c **** (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSiz + 61 .loc 1 100 0 is_stmt 1 discriminator 3 + 62 0026 7B68 ldr r3, [r7, #4] + 63 0028 5B68 ldr r3, [r3, #4] + 99:Generated_Source\PSoC4/cy_em_eeprom.c **** (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSiz + 64 .loc 1 99 0 discriminator 3 + 65 002a 0A2B cmp r3, #10 + 66 002c 5CD8 bhi .L2 + 67 .loc 1 100 0 + 68 002e 7B68 ldr r3, [r7, #4] + 69 0030 1B68 ldr r3, [r3] + 70 0032 002B cmp r3, #0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 4 + + + 71 0034 58D0 beq .L2 + 101:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 102:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CheckRanges(config); + 72 .loc 1 102 0 + 73 0036 0F23 movs r3, #15 + 74 0038 FC18 adds r4, r7, r3 + 75 003a 7B68 ldr r3, [r7, #4] + 76 003c 1800 movs r0, r3 + 77 003e FFF7FEFF bl CheckRanges + 78 0042 0300 movs r3, r0 + 79 0044 2370 strb r3, [r4] + 103:Generated_Source\PSoC4/cy_em_eeprom.c **** + 104:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS == ret) + 80 .loc 1 104 0 + 81 0046 0F23 movs r3, #15 + 82 0048 FB18 adds r3, r7, r3 + 83 004a 1B78 ldrb r3, [r3] + 84 004c 002B cmp r3, #0 + 85 004e 4BD1 bne .L2 + 105:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 106:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Copy the user config structure fields into context */ + 107:Generated_Source\PSoC4/cy_em_eeprom.c **** context->eepromSize = config->eepromSize; + 86 .loc 1 107 0 + 87 0050 7B68 ldr r3, [r7, #4] + 88 0052 1A68 ldr r2, [r3] + 89 0054 3B68 ldr r3, [r7] + 90 0056 DA60 str r2, [r3, #12] + 108:Generated_Source\PSoC4/cy_em_eeprom.c **** context->wearLevelingFactor = config->wearLevelingFactor; + 91 .loc 1 108 0 + 92 0058 7B68 ldr r3, [r7, #4] + 93 005a 5A68 ldr r2, [r3, #4] + 94 005c 3B68 ldr r3, [r7] + 95 005e 1A61 str r2, [r3, #16] + 109:Generated_Source\PSoC4/cy_em_eeprom.c **** context->redundantCopy = config->redundantCopy; + 96 .loc 1 109 0 + 97 0060 7B68 ldr r3, [r7, #4] + 98 0062 1A7A ldrb r2, [r3, #8] + 99 0064 3B68 ldr r3, [r7] + 100 0066 1A75 strb r2, [r3, #20] + 110:Generated_Source\PSoC4/cy_em_eeprom.c **** context->blockingWrite = config->blockingWrite; + 101 .loc 1 110 0 + 102 0068 7B68 ldr r3, [r7, #4] + 103 006a 5A7A ldrb r2, [r3, #9] + 104 006c 3B68 ldr r3, [r7] + 105 006e 5A75 strb r2, [r3, #21] + 111:Generated_Source\PSoC4/cy_em_eeprom.c **** context->userFlashStartAddr = config->userFlashStartAddr; + 106 .loc 1 111 0 + 107 0070 7B68 ldr r3, [r7, #4] + 108 0072 DA68 ldr r2, [r3, #12] + 109 0074 3B68 ldr r3, [r7] + 110 0076 9A61 str r2, [r3, #24] + 112:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Store frequently used data for internal use */ + 113:Generated_Source\PSoC4/cy_em_eeprom.c **** context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize); + 111 .loc 1 113 0 + 112 0078 7B68 ldr r3, [r7, #4] + 113 007a 1B68 ldr r3, [r3] + 114 007c 9A09 lsrs r2, r3, #6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 5 + + + 115 007e 7B68 ldr r3, [r7, #4] + 116 0080 1B68 ldr r3, [r3] + 117 0082 3F21 movs r1, #63 + 118 0084 0B40 ands r3, r1 + 119 0086 01D0 beq .L3 + 120 .loc 1 113 0 is_stmt 0 discriminator 1 + 121 0088 0123 movs r3, #1 + 122 008a 00E0 b .L4 + 123 .L3: + 124 .loc 1 113 0 discriminator 2 + 125 008c 0023 movs r3, #0 + 126 .L4: + 127 .loc 1 113 0 discriminator 4 + 128 008e D218 adds r2, r2, r3 + 129 0090 3B68 ldr r3, [r7] + 130 0092 5A60 str r2, [r3, #4] + 114:Generated_Source\PSoC4/cy_em_eeprom.c **** context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->we + 131 .loc 1 114 0 is_stmt 1 discriminator 4 + 132 0094 3B68 ldr r3, [r7] + 133 0096 5A68 ldr r2, [r3, #4] + 134 0098 7B68 ldr r3, [r7, #4] + 135 009a 5B68 ldr r3, [r3, #4] + 136 009c 5343 muls r3, r2 + 137 009e DA01 lsls r2, r3, #7 + 115:Generated_Source\PSoC4/cy_em_eeprom.c **** config->userFlashStartAddr); + 138 .loc 1 115 0 discriminator 4 + 139 00a0 7B68 ldr r3, [r7, #4] + 140 00a2 DB68 ldr r3, [r3, #12] + 114:Generated_Source\PSoC4/cy_em_eeprom.c **** context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->we + 141 .loc 1 114 0 discriminator 4 + 142 00a4 D218 adds r2, r2, r3 + 143 00a6 3B68 ldr r3, [r7] + 144 00a8 1A60 str r2, [r3] + 116:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Find last written EEPROM row and store it for quick access */ + 117:Generated_Source\PSoC4/cy_em_eeprom.c **** FindLastWrittenRow(&context->lastWrRowAddr, context); + 145 .loc 1 117 0 discriminator 4 + 146 00aa 3B68 ldr r3, [r7] + 147 00ac 0833 adds r3, r3, #8 + 148 00ae 3A68 ldr r2, [r7] + 149 00b0 1100 movs r1, r2 + 150 00b2 1800 movs r0, r3 + 151 00b4 FFF7FEFF bl FindLastWrittenRow + 118:Generated_Source\PSoC4/cy_em_eeprom.c **** + 119:Generated_Source\PSoC4/cy_em_eeprom.c **** if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundan + 152 .loc 1 119 0 discriminator 4 + 153 00b8 3B68 ldr r3, [r7] + 154 00ba 9B68 ldr r3, [r3, #8] + 155 00bc 1B68 ldr r3, [r3] + 156 00be 002B cmp r3, #0 + 157 00c0 12D1 bne .L2 + 158 .loc 1 119 0 is_stmt 0 discriminator 1 + 159 00c2 3B68 ldr r3, [r7] + 160 00c4 1B7D ldrb r3, [r3, #20] + 161 00c6 002B cmp r3, #0 + 162 00c8 0ED0 beq .L2 + 120:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 121:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Call the function only after device reprogramming in case + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 6 + + + 122:Generated_Source\PSoC4/cy_em_eeprom.c **** * if redundant copy is enabled. + 123:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 124:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = FillChecksum(context); + 163 .loc 1 124 0 is_stmt 1 + 164 00ca 0F23 movs r3, #15 + 165 00cc FC18 adds r4, r7, r3 + 166 00ce 3B68 ldr r3, [r7] + 167 00d0 1800 movs r0, r3 + 168 00d2 FFF7FEFF bl FillChecksum + 169 00d6 0300 movs r3, r0 + 170 00d8 2370 strb r3, [r4] + 125:Generated_Source\PSoC4/cy_em_eeprom.c **** + 126:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */ + 127:Generated_Source\PSoC4/cy_em_eeprom.c **** FindLastWrittenRow(&context->lastWrRowAddr, context); + 171 .loc 1 127 0 + 172 00da 3B68 ldr r3, [r7] + 173 00dc 0833 adds r3, r3, #8 + 174 00de 3A68 ldr r2, [r7] + 175 00e0 1100 movs r1, r2 + 176 00e2 1800 movs r0, r3 + 177 00e4 FFF7FEFF bl FindLastWrittenRow + 178 .L2: + 128:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 129:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 130:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 131:Generated_Source\PSoC4/cy_em_eeprom.c **** + 132:Generated_Source\PSoC4/cy_em_eeprom.c **** return(ret); + 179 .loc 1 132 0 + 180 00e8 0F23 movs r3, #15 + 181 00ea FB18 adds r3, r7, r3 + 182 00ec 1B78 ldrb r3, [r3] + 133:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 183 .loc 1 133 0 + 184 00ee 1800 movs r0, r3 + 185 00f0 BD46 mov sp, r7 + 186 00f2 05B0 add sp, sp, #20 + 187 @ sp needed + 188 00f4 90BD pop {r4, r7, pc} + 189 .cfi_endproc + 190 .LFE0: + 191 .size Cy_Em_EEPROM_Init, .-Cy_Em_EEPROM_Init + 192 .global __aeabi_uidiv + 193 00f6 C046 .section .text.Cy_Em_EEPROM_Read,"ax",%progbits + 194 .align 2 + 195 .global Cy_Em_EEPROM_Read + 196 .code 16 + 197 .thumb_func + 198 .type Cy_Em_EEPROM_Read, %function + 199 Cy_Em_EEPROM_Read: + 200 .LFB1: + 134:Generated_Source\PSoC4/cy_em_eeprom.c **** + 135:Generated_Source\PSoC4/cy_em_eeprom.c **** + 136:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 137:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: Cy_Em_EEPROM_Read + 138:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 139:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 140:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function takes the logical EEPROM address, converts it to the actual + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 7 + + + 141:Generated_Source\PSoC4/cy_em_eeprom.c **** * physical address where the data is stored and returns the data to the user. + 142:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 143:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param addr + 144:Generated_Source\PSoC4/cy_em_eeprom.c **** * The logical start address in EEPROM to start reading data from. + 145:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 146:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param eepromData + 147:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to a user array to write data to. + 148:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 149:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param size + 150:Generated_Source\PSoC4/cy_em_eeprom.c **** * The amount of data to read. + 151:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 152:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 153:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. + 154:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 155:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 156:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function returns \ref cy_en_em_eeprom_status_t. + 157:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 158:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note + 159:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function uses a buffer of the flash row size to perform read + 160:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation. For the size of the row refer to the specific PSoC device + 161:Generated_Source\PSoC4/cy_em_eeprom.c **** * datasheet. + 162:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 163:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note + 164:Generated_Source\PSoC4/cy_em_eeprom.c **** * In case if redundant copy option is enabled the function may perform writes + 165:Generated_Source\PSoC4/cy_em_eeprom.c **** * to EEPROM. This is done in case if the data in the EEPPROM is corrupted and + 166:Generated_Source\PSoC4/cy_em_eeprom.c **** * the data in redundant copy is valid based on CRC-8 data integrity check. + 167:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 168:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 169:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + 170:Generated_Source\PSoC4/cy_em_eeprom.c **** void * eepromData, + 171:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 size, + 172:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context) + 173:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 201 .loc 1 173 0 + 202 .cfi_startproc + 203 @ args = 0, pretend = 0, frame = 96 + 204 @ frame_needed = 1, uses_anonymous_args = 0 + 205 0000 B0B5 push {r4, r5, r7, lr} + 206 .cfi_def_cfa_offset 16 + 207 .cfi_offset 4, -16 + 208 .cfi_offset 5, -12 + 209 .cfi_offset 7, -8 + 210 .cfi_offset 14, -4 + 211 0002 9AB0 sub sp, sp, #104 + 212 .cfi_def_cfa_offset 120 + 213 0004 02AF add r7, sp, #8 + 214 .cfi_def_cfa 7, 112 + 215 0006 F860 str r0, [r7, #12] + 216 0008 B960 str r1, [r7, #8] + 217 000a 7A60 str r2, [r7, #4] + 218 000c 3B60 str r3, [r7] + 174:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + 219 .loc 1 174 0 + 220 000e 5F23 movs r3, #95 + 221 0010 FB18 adds r3, r7, r3 + 222 0012 0122 movs r2, #1 + 223 0014 1A70 strb r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 8 + + + 175:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 i; + 176:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 numBytesToRead; + 177:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 curEepromBaseAddr; + 178:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 curRowOffset; + 179:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 startRowAddr; + 180:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 actEepromRowNum; + 181:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 curRdEepromRowNum = 0u; + 224 .loc 1 181 0 + 225 0016 0023 movs r3, #0 + 226 0018 FB64 str r3, [r7, #76] + 182:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 dataStartEepromRowNum = 0u; + 227 .loc 1 182 0 + 228 001a 0023 movs r3, #0 + 229 001c BB64 str r3, [r7, #72] + 183:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + 230 .loc 1 183 0 + 231 001e BB68 ldr r3, [r7, #8] + 232 0020 7B64 str r3, [r7, #68] + 184:Generated_Source\PSoC4/cy_em_eeprom.c **** + 185:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Validate input parameters */ + 186:Generated_Source\PSoC4/cy_em_eeprom.c **** if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + 233 .loc 1 186 0 + 234 0022 7B68 ldr r3, [r7, #4] + 235 0024 002B cmp r3, #0 + 236 0026 00D1 bne .LCB175 + 237 0028 78E1 b .L7 @long jump + 238 .LCB175: + 239 .loc 1 186 0 is_stmt 0 discriminator 1 + 240 002a FA68 ldr r2, [r7, #12] + 241 002c 7B68 ldr r3, [r7, #4] + 242 002e D218 adds r2, r2, r3 + 243 0030 3B68 ldr r3, [r7] + 244 0032 DB68 ldr r3, [r3, #12] + 245 0034 9A42 cmp r2, r3 + 246 0036 00D9 bls .LCB182 + 247 0038 70E1 b .L7 @long jump + 248 .LCB182: + 249 .loc 1 186 0 discriminator 2 + 250 003a BB68 ldr r3, [r7, #8] + 251 003c 002B cmp r3, #0 + 252 003e 00D1 bne .LCB185 + 253 0040 6CE1 b .L7 @long jump + 254 .LCB185: + 255 .LBB2: + 187:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 188:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rdAddr = addr; + 256 .loc 1 188 0 is_stmt 1 + 257 0042 FB68 ldr r3, [r7, #12] + 258 0044 3B64 str r3, [r7, #64] + 189:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rdSize = size; + 259 .loc 1 189 0 + 260 0046 7B68 ldr r3, [r7, #4] + 261 0048 FB63 str r3, [r7, #60] + 190:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the sequence number of the last written row */ + 191:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr); + 262 .loc 1 191 0 + 263 004a 3B68 ldr r3, [r7] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 9 + + + 264 004c 9B68 ldr r3, [r3, #8] + 265 004e 1B68 ldr r3, [r3] + 266 0050 7B63 str r3, [r7, #52] + 192:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 updateAddrFlag = 0u; + 267 .loc 1 192 0 + 268 0052 0023 movs r3, #0 + 269 0054 BB63 str r3, [r7, #56] + 193:Generated_Source\PSoC4/cy_em_eeprom.c **** + 194:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate the number of the row read operations. Currently this only concerns + 195:Generated_Source\PSoC4/cy_em_eeprom.c **** * the reads from the EEPROM data locations. + 196:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 197:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) - + 270 .loc 1 197 0 + 271 0056 3A6C ldr r2, [r7, #64] + 272 0058 FB6B ldr r3, [r7, #60] + 273 005a D318 adds r3, r2, r3 + 274 005c 013B subs r3, r3, #1 + 275 005e 9A09 lsrs r2, r3, #6 + 198:Generated_Source\PSoC4/cy_em_eeprom.c **** (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + 276 .loc 1 198 0 + 277 0060 3B6C ldr r3, [r7, #64] + 278 0062 9B09 lsrs r3, r3, #6 + 197:Generated_Source\PSoC4/cy_em_eeprom.c **** (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + 279 .loc 1 197 0 + 280 0064 D31A subs r3, r2, r3 + 281 0066 0133 adds r3, r3, #1 + 282 0068 3B63 str r3, [r7, #48] + 199:Generated_Source\PSoC4/cy_em_eeprom.c **** + 200:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the address of the first row of the currently active EEPROM sector. If + 201:Generated_Source\PSoC4/cy_em_eeprom.c **** * no wear leveling is used - the EEPROM has only one sector, so use the base + 202:Generated_Source\PSoC4/cy_em_eeprom.c **** * addr stored in "context->userFlashStartAddr". + 203:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 204:Generated_Source\PSoC4/cy_em_eeprom.c **** curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) / + 283 .loc 1 204 0 + 284 006a 3B68 ldr r3, [r7] + 285 006c 9A68 ldr r2, [r3, #8] + 286 006e 3B68 ldr r3, [r7] + 287 0070 9B69 ldr r3, [r3, #24] + 288 0072 D21A subs r2, r2, r3 + 205:Generated_Source\PSoC4/cy_em_eeprom.c **** (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + 289 .loc 1 205 0 + 290 0074 3B68 ldr r3, [r7] + 291 0076 5B68 ldr r3, [r3, #4] + 292 0078 DB01 lsls r3, r3, #7 + 204:Generated_Source\PSoC4/cy_em_eeprom.c **** (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + 293 .loc 1 204 0 + 294 007a 1900 movs r1, r3 + 295 007c 1000 movs r0, r2 + 296 007e FFF7FEFF bl __aeabi_uidiv + 297 0082 0300 movs r3, r0 + 298 0084 1A00 movs r2, r3 + 206:Generated_Source\PSoC4/cy_em_eeprom.c **** (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) + + 299 .loc 1 206 0 + 300 0086 3B68 ldr r3, [r7] + 301 0088 5B68 ldr r3, [r3, #4] + 205:Generated_Source\PSoC4/cy_em_eeprom.c **** (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + 302 .loc 1 205 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 10 + + + 303 008a 5343 muls r3, r2 + 304 008c DA01 lsls r2, r3, #7 + 207:Generated_Source\PSoC4/cy_em_eeprom.c **** context->userFlashStartAddr; + 305 .loc 1 207 0 + 306 008e 3B68 ldr r3, [r7] + 307 0090 9B69 ldr r3, [r3, #24] + 204:Generated_Source\PSoC4/cy_em_eeprom.c **** (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + 308 .loc 1 204 0 + 309 0092 D318 adds r3, r2, r3 + 310 0094 FB62 str r3, [r7, #44] + 208:Generated_Source\PSoC4/cy_em_eeprom.c **** + 209:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Find the number of the row that contains the start address of the data */ + 210:Generated_Source\PSoC4/cy_em_eeprom.c **** for(i = 0u; i < context->numberOfRows; i++) + 311 .loc 1 210 0 + 312 0096 0023 movs r3, #0 + 313 0098 BB65 str r3, [r7, #88] + 314 009a 18E0 b .L8 + 315 .L13: + 211:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 212:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i)) + 316 .loc 1 212 0 + 317 009c BB6D ldr r3, [r7, #88] + 318 009e 9A01 lsls r2, r3, #6 + 319 00a0 3B6C ldr r3, [r7, #64] + 320 00a2 9A42 cmp r2, r3 + 321 00a4 08D8 bhi .L9 + 322 .loc 1 212 0 is_stmt 0 discriminator 1 + 323 00a6 BB6D ldr r3, [r7, #88] + 324 00a8 0133 adds r3, r3, #1 + 325 00aa 9B01 lsls r3, r3, #6 + 326 00ac 5A1E subs r2, r3, #1 + 327 00ae 3B6C ldr r3, [r7, #64] + 328 00b0 9A42 cmp r2, r3 + 329 00b2 01D3 bcc .L9 + 330 .loc 1 212 0 discriminator 3 + 331 00b4 0123 movs r3, #1 + 332 00b6 00E0 b .L10 + 333 .L9: + 334 .loc 1 212 0 discriminator 4 + 335 00b8 0023 movs r3, #0 + 336 .L10: + 337 .loc 1 212 0 discriminator 6 + 338 00ba 002B cmp r3, #0 + 339 00bc 04D0 beq .L11 + 213:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 214:Generated_Source\PSoC4/cy_em_eeprom.c **** dataStartEepromRowNum = i; + 340 .loc 1 214 0 is_stmt 1 + 341 00be BB6D ldr r3, [r7, #88] + 342 00c0 BB64 str r3, [r7, #72] + 215:Generated_Source\PSoC4/cy_em_eeprom.c **** curRdEepromRowNum = dataStartEepromRowNum; + 343 .loc 1 215 0 + 344 00c2 BB6C ldr r3, [r7, #72] + 345 00c4 FB64 str r3, [r7, #76] + 216:Generated_Source\PSoC4/cy_em_eeprom.c **** break; + 346 .loc 1 216 0 + 347 00c6 07E0 b .L12 + 348 .L11: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 11 + + + 210:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 349 .loc 1 210 0 discriminator 2 + 350 00c8 BB6D ldr r3, [r7, #88] + 351 00ca 0133 adds r3, r3, #1 + 352 00cc BB65 str r3, [r7, #88] + 353 .L8: + 210:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 354 .loc 1 210 0 is_stmt 0 discriminator 1 + 355 00ce 3B68 ldr r3, [r7] + 356 00d0 5A68 ldr r2, [r3, #4] + 357 00d2 BB6D ldr r3, [r7, #88] + 358 00d4 9A42 cmp r2, r3 + 359 00d6 E1D8 bhi .L13 + 360 .L12: + 217:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 218:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 219:Generated_Source\PSoC4/cy_em_eeprom.c **** + 220:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Find the row number of the last written row */ + 221:Generated_Source\PSoC4/cy_em_eeprom.c **** actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ + 361 .loc 1 221 0 is_stmt 1 + 362 00d8 3B68 ldr r3, [r7] + 363 00da 9A68 ldr r2, [r3, #8] + 364 00dc FB6A ldr r3, [r7, #44] + 365 00de D31A subs r3, r2, r3 + 366 00e0 DB09 lsrs r3, r3, #7 + 367 00e2 BB62 str r3, [r7, #40] + 222:Generated_Source\PSoC4/cy_em_eeprom.c **** + 223:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if wear leveling is used */ + 224:Generated_Source\PSoC4/cy_em_eeprom.c **** if(context->wearLevelingFactor > 1u) + 368 .loc 1 224 0 + 369 00e4 3B68 ldr r3, [r7] + 370 00e6 1B69 ldr r3, [r3, #16] + 371 00e8 012B cmp r3, #1 + 372 00ea 12D9 bls .L14 + 373 .LBB3: + 225:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 226:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u); + 374 .loc 1 226 0 + 375 00ec 3A6B ldr r2, [r7, #48] + 376 00ee BB6C ldr r3, [r7, #72] + 377 00f0 D318 adds r3, r2, r3 + 378 00f2 013B subs r3, r3, #1 + 379 00f4 7B62 str r3, [r7, #36] + 227:Generated_Source\PSoC4/cy_em_eeprom.c **** + 228:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if the future validation of the read address is required. */ + 229:Generated_Source\PSoC4/cy_em_eeprom.c **** updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u : + 380 .loc 1 229 0 + 381 00f6 BA6C ldr r2, [r7, #72] + 382 00f8 BB6A ldr r3, [r7, #40] + 383 00fa 9A42 cmp r2, r3 + 384 00fc 07D8 bhi .L15 + 385 .loc 1 229 0 is_stmt 0 discriminator 1 + 386 00fe 7A6A ldr r2, [r7, #36] + 387 0100 BB6A ldr r3, [r7, #40] + 388 0102 9A42 cmp r2, r3 + 389 0104 01D9 bls .L16 + 390 .loc 1 229 0 discriminator 3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 12 + + + 391 0106 0123 movs r3, #1 + 392 0108 02E0 b .L18 + 393 .L16: + 394 .loc 1 229 0 discriminator 4 + 395 010a 0023 movs r3, #0 + 396 010c 00E0 b .L18 + 397 .L15: + 398 .loc 1 229 0 discriminator 2 + 399 010e 0123 movs r3, #1 + 400 .L18: + 401 .loc 1 229 0 discriminator 8 + 402 0110 BB63 str r3, [r7, #56] + 403 .L14: + 404 .LBE3: + 230:Generated_Source\PSoC4/cy_em_eeprom.c **** ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u); + 231:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 232:Generated_Source\PSoC4/cy_em_eeprom.c **** + 233:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Copy data from the EEPROM data locations to the user buffer */ + 234:Generated_Source\PSoC4/cy_em_eeprom.c **** for(i = 0u; i < numRowReads; i++) + 405 .loc 1 234 0 is_stmt 1 + 406 0112 0023 movs r3, #0 + 407 0114 BB65 str r3, [r7, #88] + 408 0116 68E0 b .L19 + 409 .L26: + 235:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 236:Generated_Source\PSoC4/cy_em_eeprom.c **** startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + 410 .loc 1 236 0 + 411 0118 FB6C ldr r3, [r7, #76] + 412 011a DA01 lsls r2, r3, #7 + 413 011c FB6A ldr r3, [r7, #44] + 414 011e D318 adds r3, r2, r3 + 415 0120 3B65 str r3, [r7, #80] + 237:Generated_Source\PSoC4/cy_em_eeprom.c **** curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + 416 .loc 1 237 0 + 417 0122 3B6C ldr r3, [r7, #64] + 418 0124 3F22 movs r2, #63 + 419 0126 1340 ands r3, r2 + 420 0128 4033 adds r3, r3, #64 + 421 012a 3B62 str r3, [r7, #32] + 238:Generated_Source\PSoC4/cy_em_eeprom.c **** + 239:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if there are more reads pending and update the number of the + 240:Generated_Source\PSoC4/cy_em_eeprom.c **** * remaining bytes to read respectively. + 241:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 242:Generated_Source\PSoC4/cy_em_eeprom.c **** if((i + 1u) < numRowReads) + 422 .loc 1 242 0 + 423 012c BB6D ldr r3, [r7, #88] + 424 012e 5A1C adds r2, r3, #1 + 425 0130 3B6B ldr r3, [r7, #48] + 426 0132 9A42 cmp r2, r3 + 427 0134 06D2 bcs .L20 + 243:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 244:Generated_Source\PSoC4/cy_em_eeprom.c **** numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_ + 428 .loc 1 244 0 + 429 0136 3B6C ldr r3, [r7, #64] + 430 0138 3F22 movs r2, #63 + 431 013a 1340 ands r3, r2 + 432 013c 4022 movs r2, #64 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 13 + + + 433 013e D31A subs r3, r2, r3 + 434 0140 7B65 str r3, [r7, #84] + 435 0142 01E0 b .L21 + 436 .L20: + 245:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 246:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 247:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 248:Generated_Source\PSoC4/cy_em_eeprom.c **** numBytesToRead = rdSize; + 437 .loc 1 248 0 + 438 0144 FB6B ldr r3, [r7, #60] + 439 0146 7B65 str r3, [r7, #84] + 440 .L21: + 249:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 250:Generated_Source\PSoC4/cy_em_eeprom.c **** + 251:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if the read address needs to be updated to point to the correct + 252:Generated_Source\PSoC4/cy_em_eeprom.c **** * EEPROM sector. + 253:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 254:Generated_Source\PSoC4/cy_em_eeprom.c **** if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum)) + 441 .loc 1 254 0 + 442 0148 BB6B ldr r3, [r7, #56] + 443 014a 002B cmp r3, #0 + 444 014c 17D0 beq .L22 + 445 .loc 1 254 0 is_stmt 0 discriminator 1 + 446 014e FA6C ldr r2, [r7, #76] + 447 0150 BB6A ldr r3, [r7, #40] + 448 0152 9A42 cmp r2, r3 + 449 0154 13D9 bls .L22 + 255:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 256:Generated_Source\PSoC4/cy_em_eeprom.c **** startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW; + 450 .loc 1 256 0 is_stmt 1 + 451 0156 3B68 ldr r3, [r7] + 452 0158 5B68 ldr r3, [r3, #4] + 453 015a DB01 lsls r3, r3, #7 + 454 015c 3A6D ldr r2, [r7, #80] + 455 015e D31A subs r3, r2, r3 + 456 0160 3B65 str r3, [r7, #80] + 257:Generated_Source\PSoC4/cy_em_eeprom.c **** + 258:Generated_Source\PSoC4/cy_em_eeprom.c **** if(startRowAddr < context->userFlashStartAddr) + 457 .loc 1 258 0 + 458 0162 3B68 ldr r3, [r7] + 459 0164 9A69 ldr r2, [r3, #24] + 460 0166 3B6D ldr r3, [r7, #80] + 461 0168 9A42 cmp r2, r3 + 462 016a 08D9 bls .L22 + 259:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 260:Generated_Source\PSoC4/cy_em_eeprom.c **** startRowAddr = context->wlEndAddr - + 463 .loc 1 260 0 + 464 016c 3B68 ldr r3, [r7] + 465 016e 1A68 ldr r2, [r3] + 261:Generated_Source\PSoC4/cy_em_eeprom.c **** ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_RO + 466 .loc 1 261 0 + 467 0170 3B68 ldr r3, [r7] + 468 0172 5968 ldr r1, [r3, #4] + 469 0174 FB6C ldr r3, [r7, #76] + 470 0176 CB1A subs r3, r1, r3 + 471 0178 DB01 lsls r3, r3, #7 + 260:Generated_Source\PSoC4/cy_em_eeprom.c **** ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_RO + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 14 + + + 472 .loc 1 260 0 + 473 017a D31A subs r3, r2, r3 + 474 017c 3B65 str r3, [r7, #80] + 475 .L22: + 262:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 263:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 264:Generated_Source\PSoC4/cy_em_eeprom.c **** + 265:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != context->redundantCopy) + 476 .loc 1 265 0 + 477 017e 3B68 ldr r3, [r7] + 478 0180 1B7D ldrb r3, [r3, #20] + 479 0182 002B cmp r3, #0 + 480 0184 12D0 beq .L23 + 266:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 267:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + 268:Generated_Source\PSoC4/cy_em_eeprom.c **** * the corresponding row in redundant copy, otherwise return failure. + 269:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 270:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context); + 481 .loc 1 270 0 + 482 0186 5F23 movs r3, #95 + 483 0188 FC18 adds r4, r7, r3 + 484 018a 7D6D ldr r5, [r7, #84] + 485 018c 3A6A ldr r2, [r7, #32] + 486 018e 796C ldr r1, [r7, #68] + 487 0190 386D ldr r0, [r7, #80] + 488 0192 3B68 ldr r3, [r7] + 489 0194 0093 str r3, [sp] + 490 0196 2B00 movs r3, r5 + 491 0198 FFF7FEFF bl CheckCrcAndCopy + 492 019c 0300 movs r3, r0 + 493 019e 2370 strb r3, [r4] + 271:Generated_Source\PSoC4/cy_em_eeprom.c **** + 272:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS != ret) + 494 .loc 1 272 0 + 495 01a0 5F23 movs r3, #95 + 496 01a2 FB18 adds r3, r7, r3 + 497 01a4 1B78 ldrb r3, [r3] + 498 01a6 002B cmp r3, #0 + 499 01a8 0DD0 beq .L24 + 273:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 274:Generated_Source\PSoC4/cy_em_eeprom.c **** break; + 500 .loc 1 274 0 + 501 01aa 22E0 b .L25 + 502 .L23: + 275:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 276:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 277:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 278:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 279:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Copy the data to the user buffer */ + 280:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)(eeData), + 503 .loc 1 280 0 + 504 01ac 786C ldr r0, [r7, #68] + 281:Generated_Source\PSoC4/cy_em_eeprom.c **** (void *)(startRowAddr + curRowOffset), + 505 .loc 1 281 0 + 506 01ae 3A6D ldr r2, [r7, #80] + 507 01b0 3B6A ldr r3, [r7, #32] + 508 01b2 D318 adds r3, r2, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 15 + + + 280:Generated_Source\PSoC4/cy_em_eeprom.c **** (void *)(startRowAddr + curRowOffset), + 509 .loc 1 280 0 + 510 01b4 1900 movs r1, r3 + 511 01b6 7B6D ldr r3, [r7, #84] + 512 01b8 1A00 movs r2, r3 + 513 01ba FFF7FEFF bl memcpy + 282:Generated_Source\PSoC4/cy_em_eeprom.c **** numBytesToRead); + 283:Generated_Source\PSoC4/cy_em_eeprom.c **** + 284:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Indicate success to be able to execute next code block */ + 285:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; + 514 .loc 1 285 0 + 515 01be 5F23 movs r3, #95 + 516 01c0 FB18 adds r3, r7, r3 + 517 01c2 0022 movs r2, #0 + 518 01c4 1A70 strb r2, [r3] + 519 .L24: + 286:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 287:Generated_Source\PSoC4/cy_em_eeprom.c **** + 288:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Update variables anticipated in the read operation */ + 289:Generated_Source\PSoC4/cy_em_eeprom.c **** rdAddr += numBytesToRead; + 520 .loc 1 289 0 discriminator 2 + 521 01c6 3A6C ldr r2, [r7, #64] + 522 01c8 7B6D ldr r3, [r7, #84] + 523 01ca D318 adds r3, r2, r3 + 524 01cc 3B64 str r3, [r7, #64] + 290:Generated_Source\PSoC4/cy_em_eeprom.c **** rdSize -= numBytesToRead; + 525 .loc 1 290 0 discriminator 2 + 526 01ce FA6B ldr r2, [r7, #60] + 527 01d0 7B6D ldr r3, [r7, #84] + 528 01d2 D31A subs r3, r2, r3 + 529 01d4 FB63 str r3, [r7, #60] + 291:Generated_Source\PSoC4/cy_em_eeprom.c **** eeData += numBytesToRead; + 530 .loc 1 291 0 discriminator 2 + 531 01d6 7A6C ldr r2, [r7, #68] + 532 01d8 7B6D ldr r3, [r7, #84] + 533 01da D318 adds r3, r2, r3 + 534 01dc 7B64 str r3, [r7, #68] + 292:Generated_Source\PSoC4/cy_em_eeprom.c **** curRdEepromRowNum++; + 535 .loc 1 292 0 discriminator 2 + 536 01de FB6C ldr r3, [r7, #76] + 537 01e0 0133 adds r3, r3, #1 + 538 01e2 FB64 str r3, [r7, #76] + 234:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 539 .loc 1 234 0 discriminator 2 + 540 01e4 BB6D ldr r3, [r7, #88] + 541 01e6 0133 adds r3, r3, #1 + 542 01e8 BB65 str r3, [r7, #88] + 543 .L19: + 234:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 544 .loc 1 234 0 is_stmt 0 discriminator 1 + 545 01ea BA6D ldr r2, [r7, #88] + 546 01ec 3B6B ldr r3, [r7, #48] + 547 01ee 9A42 cmp r2, r3 + 548 01f0 92D3 bcc .L26 + 549 .L25: + 293:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 294:Generated_Source\PSoC4/cy_em_eeprom.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 16 + + + 295:Generated_Source\PSoC4/cy_em_eeprom.c **** /* This code block will copy the latest data from the EEPROM headers into the + 296:Generated_Source\PSoC4/cy_em_eeprom.c **** * user buffer. The data previously copied into the user buffer may be updated + 297:Generated_Source\PSoC4/cy_em_eeprom.c **** * as the EEPROM headers contain more recent data. + 298:Generated_Source\PSoC4/cy_em_eeprom.c **** * The code block is executed when two following conditions are true: + 299:Generated_Source\PSoC4/cy_em_eeprom.c **** * 1) The reads from "historic" data locations were successful; + 300:Generated_Source\PSoC4/cy_em_eeprom.c **** * 2) The user performed at least one write operation to Em_EEPROM (0u != + 301:Generated_Source\PSoC4/cy_em_eeprom.c **** * seqNum). + 302:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 303:Generated_Source\PSoC4/cy_em_eeprom.c **** if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum)) + 550 .loc 1 303 0 is_stmt 1 + 551 01f2 5F23 movs r3, #95 + 552 01f4 FB18 adds r3, r7, r3 + 553 01f6 1B78 ldrb r3, [r3] + 554 01f8 002B cmp r3, #0 + 555 01fa 00D0 beq .LCB448 + 556 01fc 8EE0 b .L7 @long jump + 557 .LCB448: + 558 .loc 1 303 0 is_stmt 0 discriminator 1 + 559 01fe 7B6B ldr r3, [r7, #52] + 560 0200 002B cmp r3, #0 + 561 0202 00D1 bne .LCB451 + 562 0204 8AE0 b .L7 @long jump + 563 .LCB451: + 304:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 305:Generated_Source\PSoC4/cy_em_eeprom.c **** numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum); + 564 .loc 1 305 0 is_stmt 1 + 565 0206 3B68 ldr r3, [r7] + 566 0208 5B68 ldr r3, [r3, #4] + 567 020a 7A6B ldr r2, [r7, #52] + 568 020c 9342 cmp r3, r2 + 569 020e 00D9 bls .L27 + 570 0210 1300 movs r3, r2 + 571 .L27: + 572 0212 3B63 str r3, [r7, #48] + 306:Generated_Source\PSoC4/cy_em_eeprom.c **** numRowReads--; + 573 .loc 1 306 0 + 574 0214 3B6B ldr r3, [r7, #48] + 575 0216 013B subs r3, r3, #1 + 576 0218 3B63 str r3, [r7, #48] + 307:Generated_Source\PSoC4/cy_em_eeprom.c **** + 308:Generated_Source\PSoC4/cy_em_eeprom.c **** for(i = (seqNum - numRowReads); i <= seqNum; i++) + 577 .loc 1 308 0 + 578 021a 7A6B ldr r2, [r7, #52] + 579 021c 3B6B ldr r3, [r7, #48] + 580 021e D31A subs r3, r2, r3 + 581 0220 BB65 str r3, [r7, #88] + 582 0222 77E0 b .L28 + 583 .L39: + 309:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 310:Generated_Source\PSoC4/cy_em_eeprom.c **** startRowAddr = GetRowAddrBySeqNum(i, context); + 584 .loc 1 310 0 + 585 0224 3A68 ldr r2, [r7] + 586 0226 BB6D ldr r3, [r7, #88] + 587 0228 1100 movs r1, r2 + 588 022a 1800 movs r0, r3 + 589 022c FFF7FEFF bl GetRowAddrBySeqNum + 590 0230 0300 movs r3, r0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 17 + + + 591 0232 3B65 str r3, [r7, #80] + 311:Generated_Source\PSoC4/cy_em_eeprom.c **** + 312:Generated_Source\PSoC4/cy_em_eeprom.c **** if (0u != startRowAddr) + 592 .loc 1 312 0 + 593 0234 3B6D ldr r3, [r7, #80] + 594 0236 002B cmp r3, #0 + 595 0238 69D0 beq .L29 + 596 .LBB4: + 313:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 314:Generated_Source\PSoC4/cy_em_eeprom.c **** /* The following variables are introduced to increase code readability. */ + 315:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET) + 597 .loc 1 315 0 + 598 023a 3B6D ldr r3, [r7, #80] + 599 023c 0433 adds r3, r3, #4 + 600 023e 1B68 ldr r3, [r3] + 601 0240 FB61 str r3, [r7, #28] + 316:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER + 602 .loc 1 316 0 + 603 0242 3B6D ldr r3, [r7, #80] + 604 0244 0833 adds r3, r3, #8 + 605 0246 1A68 ldr r2, [r3] + 606 0248 FB69 ldr r3, [r7, #28] + 607 024a D318 adds r3, r2, r3 + 608 024c BB61 str r3, [r7, #24] + 317:Generated_Source\PSoC4/cy_em_eeprom.c **** + 318:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if the current row EEPROM header contains the data requested for read + 319:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + siz + 609 .loc 1 319 0 + 610 024e FA69 ldr r2, [r7, #28] + 611 0250 FB68 ldr r3, [r7, #12] + 612 0252 9A42 cmp r2, r3 + 613 0254 08D9 bls .L30 + 614 .loc 1 319 0 is_stmt 0 discriminator 1 + 615 0256 FA68 ldr r2, [r7, #12] + 616 0258 7B68 ldr r3, [r7, #4] + 617 025a D318 adds r3, r2, r3 + 618 025c FA69 ldr r2, [r7, #28] + 619 025e 9A42 cmp r2, r3 + 620 0260 9B41 sbcs r3, r3, r3 + 621 0262 5B42 rsbs r3, r3, #0 + 622 0264 DBB2 uxtb r3, r3 + 623 0266 05E0 b .L31 + 624 .L30: + 625 .loc 1 319 0 discriminator 2 + 626 0268 FA68 ldr r2, [r7, #12] + 627 026a BB69 ldr r3, [r7, #24] + 628 026c 9A42 cmp r2, r3 + 629 026e 9B41 sbcs r3, r3, r3 + 630 0270 5B42 rsbs r3, r3, #0 + 631 0272 DBB2 uxtb r3, r3 + 632 .L31: + 633 .loc 1 319 0 discriminator 4 + 634 0274 002B cmp r3, #0 + 635 0276 4AD0 beq .L29 + 636 .LBB5: + 320:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 321:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 18 + + + 637 .loc 1 321 0 is_stmt 1 + 638 0278 FA69 ldr r2, [r7, #28] + 639 027a FB68 ldr r3, [r7, #12] + 640 027c 9A42 cmp r2, r3 + 641 027e 03D8 bhi .L32 + 642 .loc 1 321 0 is_stmt 0 discriminator 1 + 643 0280 FA68 ldr r2, [r7, #12] + 644 0282 FB69 ldr r3, [r7, #28] + 645 0284 D31A subs r3, r2, r3 + 646 0286 00E0 b .L33 + 647 .L32: + 648 .loc 1 321 0 discriminator 2 + 649 0288 0023 movs r3, #0 + 650 .L33: + 651 .loc 1 321 0 discriminator 4 + 652 028a 7B61 str r3, [r7, #20] + 322:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u); + 653 .loc 1 322 0 is_stmt 1 discriminator 4 + 654 028c FA69 ldr r2, [r7, #28] + 655 028e FB68 ldr r3, [r7, #12] + 656 0290 9A42 cmp r2, r3 + 657 0292 03D9 bls .L34 + 658 .loc 1 322 0 is_stmt 0 discriminator 1 + 659 0294 FA69 ldr r2, [r7, #28] + 660 0296 FB68 ldr r3, [r7, #12] + 661 0298 D31A subs r3, r2, r3 + 662 029a 00E0 b .L35 + 663 .L34: + 664 .loc 1 322 0 discriminator 2 + 665 029c 0023 movs r3, #0 + 666 .L35: + 667 .loc 1 322 0 discriminator 4 + 668 029e 3B61 str r3, [r7, #16] + 323:Generated_Source\PSoC4/cy_em_eeprom.c **** rdAddr = (startAddr > addr) ? (startAddr) : (addr); + 669 .loc 1 323 0 is_stmt 1 discriminator 4 + 670 02a0 FA69 ldr r2, [r7, #28] + 671 02a2 FB68 ldr r3, [r7, #12] + 672 02a4 9342 cmp r3, r2 + 673 02a6 00D2 bcs .L36 + 674 02a8 1300 movs r3, r2 + 675 .L36: + 676 02aa 3B64 str r3, [r7, #64] + 324:Generated_Source\PSoC4/cy_em_eeprom.c **** + 325:Generated_Source\PSoC4/cy_em_eeprom.c **** srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET; + 677 .loc 1 325 0 discriminator 4 + 678 02ac 7B69 ldr r3, [r7, #20] + 679 02ae 0C33 adds r3, r3, #12 + 680 02b0 7B61 str r3, [r7, #20] + 326:Generated_Source\PSoC4/cy_em_eeprom.c **** + 327:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate the number of bytes to be read from the current row's EEPROM h + 328:Generated_Source\PSoC4/cy_em_eeprom.c **** numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rd + 681 .loc 1 328 0 discriminator 4 + 682 02b2 FA68 ldr r2, [r7, #12] + 683 02b4 7B68 ldr r3, [r7, #4] + 684 02b6 D318 adds r3, r2, r3 + 685 02b8 BA69 ldr r2, [r7, #24] + 686 02ba 9342 cmp r3, r2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 19 + + + 687 02bc 00D9 bls .L37 + 688 02be 1300 movs r3, r2 + 689 .L37: + 690 02c0 3A6C ldr r2, [r7, #64] + 691 02c2 9B1A subs r3, r3, r2 + 692 02c4 7B65 str r3, [r7, #84] + 329:Generated_Source\PSoC4/cy_em_eeprom.c **** + 330:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate the offset in the user buffer from which the data will be upda + 331:Generated_Source\PSoC4/cy_em_eeprom.c **** eeData = ((uint32)eepromData) + dstOffset; + 693 .loc 1 331 0 discriminator 4 + 694 02c6 BA68 ldr r2, [r7, #8] + 695 02c8 3B69 ldr r3, [r7, #16] + 696 02ca D318 adds r3, r2, r3 + 697 02cc 7B64 str r3, [r7, #68] + 332:Generated_Source\PSoC4/cy_em_eeprom.c **** + 333:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + 334:Generated_Source\PSoC4/cy_em_eeprom.c **** * corresponding row in redundant copy, otherwise return failure. Copy the d + 335:Generated_Source\PSoC4/cy_em_eeprom.c **** * from the recent EEPROM headers to the user buffer. This will overwrite th + 336:Generated_Source\PSoC4/cy_em_eeprom.c **** * data copied form EEPROM data locations as the data in EEPROM headers is n + 337:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 338:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != context->redundantCopy) + 698 .loc 1 338 0 discriminator 4 + 699 02ce 3B68 ldr r3, [r7] + 700 02d0 1B7D ldrb r3, [r3, #20] + 701 02d2 002B cmp r3, #0 + 702 02d4 12D0 beq .L38 + 339:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 340:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, + 703 .loc 1 340 0 + 704 02d6 5F23 movs r3, #95 + 705 02d8 FC18 adds r4, r7, r3 + 706 02da 7D6D ldr r5, [r7, #84] + 707 02dc 7A69 ldr r2, [r7, #20] + 708 02de 796C ldr r1, [r7, #68] + 709 02e0 386D ldr r0, [r7, #80] + 710 02e2 3B68 ldr r3, [r7] + 711 02e4 0093 str r3, [sp] + 712 02e6 2B00 movs r3, r5 + 713 02e8 FFF7FEFF bl CheckCrcAndCopy + 714 02ec 0300 movs r3, r0 + 715 02ee 2370 strb r3, [r4] + 341:Generated_Source\PSoC4/cy_em_eeprom.c **** + 342:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS != ret) + 716 .loc 1 342 0 + 717 02f0 5F23 movs r3, #95 + 718 02f2 FB18 adds r3, r7, r3 + 719 02f4 1B78 ldrb r3, [r3] + 720 02f6 002B cmp r3, #0 + 721 02f8 09D0 beq .L29 + 343:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 344:Generated_Source\PSoC4/cy_em_eeprom.c **** break; + 722 .loc 1 344 0 + 723 02fa 0FE0 b .L7 + 724 .L38: + 345:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 346:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 347:Generated_Source\PSoC4/cy_em_eeprom.c **** else + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 20 + + + 348:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 349:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numB + 725 .loc 1 349 0 + 726 02fc 786C ldr r0, [r7, #68] + 727 02fe 3A6D ldr r2, [r7, #80] + 728 0300 7B69 ldr r3, [r7, #20] + 729 0302 D318 adds r3, r2, r3 + 730 0304 1900 movs r1, r3 + 731 0306 7B6D ldr r3, [r7, #84] + 732 0308 1A00 movs r2, r3 + 733 030a FFF7FEFF bl memcpy + 734 .L29: + 735 .LBE5: + 736 .LBE4: + 308:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 737 .loc 1 308 0 discriminator 2 + 738 030e BB6D ldr r3, [r7, #88] + 739 0310 0133 adds r3, r3, #1 + 740 0312 BB65 str r3, [r7, #88] + 741 .L28: + 308:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 742 .loc 1 308 0 is_stmt 0 discriminator 1 + 743 0314 BA6D ldr r2, [r7, #88] + 744 0316 7B6B ldr r3, [r7, #52] + 745 0318 9A42 cmp r2, r3 + 746 031a 83D9 bls .L39 + 747 .L7: + 748 .LBE2: + 350:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 351:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 352:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 353:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 354:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 355:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 356:Generated_Source\PSoC4/cy_em_eeprom.c **** + 357:Generated_Source\PSoC4/cy_em_eeprom.c **** return(ret); + 749 .loc 1 357 0 is_stmt 1 + 750 031c 5F23 movs r3, #95 + 751 031e FB18 adds r3, r7, r3 + 752 0320 1B78 ldrb r3, [r3] + 358:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 753 .loc 1 358 0 + 754 0322 1800 movs r0, r3 + 755 0324 BD46 mov sp, r7 + 756 0326 18B0 add sp, sp, #96 + 757 @ sp needed + 758 0328 B0BD pop {r4, r5, r7, pc} + 759 .cfi_endproc + 760 .LFE1: + 761 .size Cy_Em_EEPROM_Read, .-Cy_Em_EEPROM_Read + 762 .global __aeabi_uidivmod + 763 032a C046 .section .text.Cy_Em_EEPROM_Write,"ax",%progbits + 764 .align 2 + 765 .global Cy_Em_EEPROM_Write + 766 .code 16 + 767 .thumb_func + 768 .type Cy_Em_EEPROM_Write, %function + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 21 + + + 769 Cy_Em_EEPROM_Write: + 770 .LFB2: + 359:Generated_Source\PSoC4/cy_em_eeprom.c **** + 360:Generated_Source\PSoC4/cy_em_eeprom.c **** + 361:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 362:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: Cy_Em_EEPROM_Write + 363:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 364:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 365:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function takes the logical EEPROM address and converts it to the actual + 366:Generated_Source\PSoC4/cy_em_eeprom.c **** * physical address and writes data there. If wear leveling is implemented, the + 367:Generated_Source\PSoC4/cy_em_eeprom.c **** * writing process will use the wear leveling techniques. This is a blocking + 368:Generated_Source\PSoC4/cy_em_eeprom.c **** * function and it does not return until the write operation is completed. The + 369:Generated_Source\PSoC4/cy_em_eeprom.c **** * user firmware should not enter Hibernate mode until write is completed. The + 370:Generated_Source\PSoC4/cy_em_eeprom.c **** * write operation is allowed in Sleep and Deep-Sleep modes. During the flash + 371:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation, the device should not be reset, including the XRES pin, a software + 372:Generated_Source\PSoC4/cy_em_eeprom.c **** * reset, and watchdog reset sources. Also, low-voltage detect circuits should + 373:Generated_Source\PSoC4/cy_em_eeprom.c **** * be configured to generate an interrupt instead of a reset. Otherwise, portions + 374:Generated_Source\PSoC4/cy_em_eeprom.c **** * of flash may undergo unexpected changes. + 375:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 376:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param addr + 377:Generated_Source\PSoC4/cy_em_eeprom.c **** * The logical start address in EEPROM to start writing data from. + 378:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 379:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param eepromData + 380:Generated_Source\PSoC4/cy_em_eeprom.c **** * Data to write to EEPROM. + 381:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 382:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param size + 383:Generated_Source\PSoC4/cy_em_eeprom.c **** * The amount of data to write to EEPROM. + 384:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 385:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 386:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. + 387:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 388:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 389:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function returns \ref cy_en_em_eeprom_status_t. + 390:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 391:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note + 392:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function uses a buffer of the flash row size to perform write + 393:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation. For the size of the row refer to the specific PSoC device + 394:Generated_Source\PSoC4/cy_em_eeprom.c **** * datasheet. + 395:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 396:Generated_Source\PSoC4/cy_em_eeprom.c **** * \sideeffect + 397:Generated_Source\PSoC4/cy_em_eeprom.c **** * In case when blocking write option is used, if this function is called by + 398:Generated_Source\PSoC4/cy_em_eeprom.c **** * the CM4 the user code on CM0P and the user code on CM4 are blocked until erase + 399:Generated_Source\PSoC4/cy_em_eeprom.c **** * flash row operation is finished. If this function is called by the CM0P the + 400:Generated_Source\PSoC4/cy_em_eeprom.c **** * user code on CM4 is not blocked and the user code on CM0P is blocked until + 401:Generated_Source\PSoC4/cy_em_eeprom.c **** * erase flash row operation is finished. Plan your task allocation accordingly. + 402:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 403:Generated_Source\PSoC4/cy_em_eeprom.c **** * \sideeffect + 404:Generated_Source\PSoC4/cy_em_eeprom.c **** * In case if non-blocking write option is used and when user flash is used as + 405:Generated_Source\PSoC4/cy_em_eeprom.c **** * an EEPROM storage care should be taken to prevent the read while write (RWW) + 406:Generated_Source\PSoC4/cy_em_eeprom.c **** * exception. To prevent the RWW exception the user flash macro that includes + 407:Generated_Source\PSoC4/cy_em_eeprom.c **** * the EEPROM storage should not be read while the EEPROM write is not completed. + 408:Generated_Source\PSoC4/cy_em_eeprom.c **** * The read also means the user code execution from the respective flash macro. + 409:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 410:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 411:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + 412:Generated_Source\PSoC4/cy_em_eeprom.c **** void * eepromData, + 413:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 size, + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 22 + + + 414:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context) + 415:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 771 .loc 1 415 0 + 772 .cfi_startproc + 773 @ args = 0, pretend = 0, frame = 208 + 774 @ frame_needed = 1, uses_anonymous_args = 0 + 775 0000 B0B5 push {r4, r5, r7, lr} + 776 .cfi_def_cfa_offset 16 + 777 .cfi_offset 4, -16 + 778 .cfi_offset 5, -12 + 779 .cfi_offset 7, -8 + 780 .cfi_offset 14, -4 + 781 0002 B6B0 sub sp, sp, #216 + 782 .cfi_def_cfa_offset 232 + 783 0004 02AF add r7, sp, #8 + 784 .cfi_def_cfa 7, 224 + 785 0006 F860 str r0, [r7, #12] + 786 0008 B960 str r1, [r7, #8] + 787 000a 7A60 str r2, [r7, #4] + 788 000c 3B60 str r3, [r7] + 416:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + 789 .loc 1 416 0 + 790 000e CF23 movs r3, #207 + 791 0010 FB18 adds r3, r7, r3 + 792 0012 0122 movs r2, #1 + 793 0014 1A70 strb r2, [r3] + 417:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 i; + 418:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 wrCnt; + 419:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 actEmEepromRowNum; + 420:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + 421:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 startAddr = 0u; + 794 .loc 1 421 0 + 795 0016 0023 movs r3, #0 + 796 0018 3B62 str r3, [r7, #32] + 422:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 endAddr = 0u; + 797 .loc 1 422 0 + 798 001a 0023 movs r3, #0 + 799 001c FB61 str r3, [r7, #28] + 423:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 tmpRowAddr; + 424:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromRowAddr = context->lastWrRowAddr; + 800 .loc 1 424 0 + 801 001e 3B68 ldr r3, [r7] + 802 0020 9B68 ldr r3, [r3, #8] + 803 0022 BB61 str r3, [r7, #24] + 425:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromRowRdAddr; + 426:Generated_Source\PSoC4/cy_em_eeprom.c **** void * tmpData; + 427:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + 804 .loc 1 427 0 + 805 0024 BB68 ldr r3, [r7, #8] + 806 0026 BC22 movs r2, #188 + 807 0028 BA18 adds r2, r7, r2 + 808 002a 1360 str r3, [r2] + 428:Generated_Source\PSoC4/cy_em_eeprom.c **** + 429:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if the EEPROM data does not exceed the EEPROM capacity */ + 430:Generated_Source\PSoC4/cy_em_eeprom.c **** if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + 809 .loc 1 430 0 + 810 002c 7B68 ldr r3, [r7, #4] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 23 + + + 811 002e 002B cmp r3, #0 + 812 0030 00D1 bne .LCB674 + 813 0032 77E1 b .L42 @long jump + 814 .LCB674: + 815 .loc 1 430 0 is_stmt 0 discriminator 1 + 816 0034 FA68 ldr r2, [r7, #12] + 817 0036 7B68 ldr r3, [r7, #4] + 818 0038 D218 adds r2, r2, r3 + 819 003a 3B68 ldr r3, [r7] + 820 003c DB68 ldr r3, [r3, #12] + 821 003e 9A42 cmp r2, r3 + 822 0040 00D9 bls .LCB681 + 823 0042 6FE1 b .L42 @long jump + 824 .LCB681: + 825 .loc 1 430 0 discriminator 2 + 826 0044 BB68 ldr r3, [r7, #8] + 827 0046 002B cmp r3, #0 + 828 0048 00D1 bne .LCB684 + 829 004a 6BE1 b .L42 @long jump + 830 .LCB684: + 831 .LBB6: + 431:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 432:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u; + 832 .loc 1 432 0 is_stmt 1 + 833 004c 7B68 ldr r3, [r7, #4] + 834 004e 013B subs r3, r3, #1 + 835 0050 3021 movs r1, #48 + 836 0052 1800 movs r0, r3 + 837 0054 FFF7FEFF bl __aeabi_uidiv + 838 0058 0300 movs r3, r0 + 839 005a 0133 adds r3, r3, #1 + 840 005c B422 movs r2, #180 + 841 005e BA18 adds r2, r7, r2 + 842 0060 1360 str r3, [r2] + 433:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 eeHeaderDataOffset = 0u; + 843 .loc 1 433 0 + 844 0062 0023 movs r3, #0 + 845 0064 3B61 str r3, [r7, #16] + 434:Generated_Source\PSoC4/cy_em_eeprom.c **** + 435:Generated_Source\PSoC4/cy_em_eeprom.c **** for(wrCnt = 0u; wrCnt < numWrites; wrCnt++) + 846 .loc 1 435 0 + 847 0066 0023 movs r3, #0 + 848 0068 C422 movs r2, #196 + 849 006a BA18 adds r2, r7, r2 + 850 006c 1360 str r3, [r2] + 851 006e 4EE1 b .L43 + 852 .L61: + 853 .LBB7: + 436:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 437:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 skipOperation = 0u; + 854 .loc 1 437 0 + 855 0070 0023 movs r3, #0 + 856 0072 B822 movs r2, #184 + 857 0074 BA18 adds r2, r7, r2 + 858 0076 1360 str r3, [r2] + 438:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the sequence number of the last written row */ + 439:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 24 + + + 859 .loc 1 439 0 + 860 0078 BB69 ldr r3, [r7, #24] + 861 007a 1B68 ldr r3, [r3] + 862 007c B022 movs r2, #176 + 863 007e BA18 adds r2, r7, r2 + 864 0080 1360 str r3, [r2] + 440:Generated_Source\PSoC4/cy_em_eeprom.c **** + 441:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the address of the row to be written. The "emEepromRowAddr" may be + 442:Generated_Source\PSoC4/cy_em_eeprom.c **** * updated with the proper address (if wear leveling is used). The + 443:Generated_Source\PSoC4/cy_em_eeprom.c **** * "emEepromRowRdAddr" will point to the row address from which the historic + 444:Generated_Source\PSoC4/cy_em_eeprom.c **** * data will be read into the RAM buffer. + 445:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 446:Generated_Source\PSoC4/cy_em_eeprom.c **** GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + 865 .loc 1 446 0 + 866 0082 3B68 ldr r3, [r7] + 867 0084 1422 movs r2, #20 + 868 0086 BA18 adds r2, r7, r2 + 869 0088 1821 movs r1, #24 + 870 008a 7918 adds r1, r7, r1 + 871 008c B020 movs r0, #176 + 872 008e 3818 adds r0, r7, r0 + 873 0090 0068 ldr r0, [r0] + 874 0092 FFF7FEFF bl GetNextRowToWrite + 447:Generated_Source\PSoC4/cy_em_eeprom.c **** + 448:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Clear the RAM buffer so to not put junk into flash */ + 449:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW); + 875 .loc 1 449 0 + 876 0096 2423 movs r3, #36 + 877 0098 FB18 adds r3, r7, r3 + 878 009a 8022 movs r2, #128 + 879 009c 0021 movs r1, #0 + 880 009e 1800 movs r0, r3 + 881 00a0 FFF7FEFF bl memset + 450:Generated_Source\PSoC4/cy_em_eeprom.c **** + 451:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Fill the EM_EEPROM header info for the row in the RAM buffer */ + 452:Generated_Source\PSoC4/cy_em_eeprom.c **** seqNum++; + 882 .loc 1 452 0 + 883 00a4 B023 movs r3, #176 + 884 00a6 FB18 adds r3, r7, r3 + 885 00a8 1B68 ldr r3, [r3] + 886 00aa 0133 adds r3, r3, #1 + 887 00ac B022 movs r2, #176 + 888 00ae BA18 adds r2, r7, r2 + 889 00b0 1360 str r3, [r2] + 453:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + 890 .loc 1 453 0 + 891 00b2 2423 movs r3, #36 + 892 00b4 FB18 adds r3, r7, r3 + 893 00b6 B022 movs r2, #176 + 894 00b8 BA18 adds r2, r7, r2 + 895 00ba 1268 ldr r2, [r2] + 896 00bc 1A60 str r2, [r3] + 454:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr; + 897 .loc 1 454 0 + 898 00be 2423 movs r3, #36 + 899 00c0 FB18 adds r3, r7, r3 + 900 00c2 FA68 ldr r2, [r7, #12] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 25 + + + 901 00c4 5A60 str r2, [r3, #4] + 455:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpData = (void *) eeData; + 902 .loc 1 455 0 + 903 00c6 BC23 movs r3, #188 + 904 00c8 FB18 adds r3, r7, r3 + 905 00ca 1B68 ldr r3, [r3] + 906 00cc AC22 movs r2, #172 + 907 00ce BA18 adds r2, r7, r2 + 908 00d0 1360 str r3, [r2] + 456:Generated_Source\PSoC4/cy_em_eeprom.c **** + 457:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if this is the last row to write */ + 458:Generated_Source\PSoC4/cy_em_eeprom.c **** if(wrCnt == (numWrites - 1u)) + 909 .loc 1 458 0 + 910 00d2 B423 movs r3, #180 + 911 00d4 FB18 adds r3, r7, r3 + 912 00d6 1B68 ldr r3, [r3] + 913 00d8 5A1E subs r2, r3, #1 + 914 00da C423 movs r3, #196 + 915 00dc FB18 adds r3, r7, r3 + 916 00de 1B68 ldr r3, [r3] + 917 00e0 9A42 cmp r2, r3 + 918 00e2 04D1 bne .L44 + 459:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 460:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Fill in the remaining size value to the EEPROM header. */ + 461:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size; + 919 .loc 1 461 0 + 920 00e4 2423 movs r3, #36 + 921 00e6 FB18 adds r3, r7, r3 + 922 00e8 7A68 ldr r2, [r7, #4] + 923 00ea 9A60 str r2, [r3, #8] + 924 00ec 10E0 b .L45 + 925 .L44: + 462:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 463:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 464:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 465:Generated_Source\PSoC4/cy_em_eeprom.c **** /* This is not the last row to write in the current EEPROM write operation. + 466:Generated_Source\PSoC4/cy_em_eeprom.c **** * Write the maximum possible data size to the EEPROM header. Update the + 467:Generated_Source\PSoC4/cy_em_eeprom.c **** * size, eeData and addr respectively. + 468:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 469:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN; + 926 .loc 1 469 0 + 927 00ee 2423 movs r3, #36 + 928 00f0 FB18 adds r3, r7, r3 + 929 00f2 3022 movs r2, #48 + 930 00f4 9A60 str r2, [r3, #8] + 470:Generated_Source\PSoC4/cy_em_eeprom.c **** size -= CY_EM_EEPROM_HEADER_DATA_LEN; + 931 .loc 1 470 0 + 932 00f6 7B68 ldr r3, [r7, #4] + 933 00f8 303B subs r3, r3, #48 + 934 00fa 7B60 str r3, [r7, #4] + 471:Generated_Source\PSoC4/cy_em_eeprom.c **** addr += CY_EM_EEPROM_HEADER_DATA_LEN; + 935 .loc 1 471 0 + 936 00fc FB68 ldr r3, [r7, #12] + 937 00fe 3033 adds r3, r3, #48 + 938 0100 FB60 str r3, [r7, #12] + 472:Generated_Source\PSoC4/cy_em_eeprom.c **** eeData += CY_EM_EEPROM_HEADER_DATA_LEN; + 939 .loc 1 472 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 26 + + + 940 0102 BC23 movs r3, #188 + 941 0104 FB18 adds r3, r7, r3 + 942 0106 1B68 ldr r3, [r3] + 943 0108 3033 adds r3, r3, #48 + 944 010a BC22 movs r2, #188 + 945 010c BA18 adds r2, r7, r2 + 946 010e 1360 str r3, [r2] + 947 .L45: + 473:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 474:Generated_Source\PSoC4/cy_em_eeprom.c **** + 475:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the data to the EEPROM header */ + 476:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32], + 477:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpData, + 478:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]); + 948 .loc 1 478 0 + 949 0110 2423 movs r3, #36 + 950 0112 FB18 adds r3, r7, r3 + 951 0114 9A68 ldr r2, [r3, #8] + 476:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpData, + 952 .loc 1 476 0 + 953 0116 AC23 movs r3, #172 + 954 0118 FB18 adds r3, r7, r3 + 955 011a 1968 ldr r1, [r3] + 956 011c 2423 movs r3, #36 + 957 011e FB18 adds r3, r7, r3 + 958 0120 0C33 adds r3, r3, #12 + 959 0122 1800 movs r0, r3 + 960 0124 FFF7FEFF bl memcpy + 479:Generated_Source\PSoC4/cy_em_eeprom.c **** + 480:Generated_Source\PSoC4/cy_em_eeprom.c **** if(emEepromRowRdAddr != 0UL) + 961 .loc 1 480 0 + 962 0128 7B69 ldr r3, [r7, #20] + 963 012a 002B cmp r3, #0 + 964 012c 09D0 beq .L46 + 481:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 482:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Copy the EEPROM historic data for this row from flash to RAM */ + 483:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + 484:Generated_Source\PSoC4/cy_em_eeprom.c **** (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + 965 .loc 1 484 0 + 966 012e 7B69 ldr r3, [r7, #20] + 967 0130 4033 adds r3, r3, #64 + 483:Generated_Source\PSoC4/cy_em_eeprom.c **** (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + 968 .loc 1 483 0 + 969 0132 1900 movs r1, r3 + 970 0134 2423 movs r3, #36 + 971 0136 FB18 adds r3, r7, r3 + 972 0138 4033 adds r3, r3, #64 + 973 013a 4022 movs r2, #64 + 974 013c 1800 movs r0, r3 + 975 013e FFF7FEFF bl memcpy + 976 .L46: + 485:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_EEPROM_DATA_LEN); + 486:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 487:Generated_Source\PSoC4/cy_em_eeprom.c **** + 488:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if there is data for this location in other EEPROM headers: + 489:Generated_Source\PSoC4/cy_em_eeprom.c **** * find out the row with the lowest possible sequence number which + 490:Generated_Source\PSoC4/cy_em_eeprom.c **** * may contain the data for the current row. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 27 + + + 491:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 492:Generated_Source\PSoC4/cy_em_eeprom.c **** i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u; + 977 .loc 1 492 0 + 978 0142 3B68 ldr r3, [r7] + 979 0144 5A68 ldr r2, [r3, #4] + 980 0146 B023 movs r3, #176 + 981 0148 FB18 adds r3, r7, r3 + 982 014a 1B68 ldr r3, [r3] + 983 014c 9A42 cmp r2, r3 + 984 014e 07D2 bcs .L47 + 985 .loc 1 492 0 is_stmt 0 discriminator 1 + 986 0150 3B68 ldr r3, [r7] + 987 0152 5B68 ldr r3, [r3, #4] + 988 0154 B022 movs r2, #176 + 989 0156 BA18 adds r2, r7, r2 + 990 0158 1268 ldr r2, [r2] + 991 015a D31A subs r3, r2, r3 + 992 015c 0133 adds r3, r3, #1 + 993 015e 00E0 b .L48 + 994 .L47: + 995 .loc 1 492 0 discriminator 2 + 996 0160 0123 movs r3, #1 + 997 .L48: + 998 .loc 1 492 0 discriminator 4 + 999 0162 C822 movs r2, #200 + 1000 0164 BA18 adds r2, r7, r2 + 1001 0166 1360 str r3, [r2] + 493:Generated_Source\PSoC4/cy_em_eeprom.c **** + 494:Generated_Source\PSoC4/cy_em_eeprom.c **** for(; i <= seqNum; i++) + 1002 .loc 1 494 0 is_stmt 1 discriminator 4 + 1003 0168 8AE0 b .L49 + 1004 .L56: + 495:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 496:Generated_Source\PSoC4/cy_em_eeprom.c **** if(i == seqNum) + 1005 .loc 1 496 0 + 1006 016a C823 movs r3, #200 + 1007 016c FB18 adds r3, r7, r3 + 1008 016e 1A68 ldr r2, [r3] + 1009 0170 B023 movs r3, #176 + 1010 0172 FB18 adds r3, r7, r3 + 1011 0174 1B68 ldr r3, [r3] + 1012 0176 9A42 cmp r2, r3 + 1013 0178 05D1 bne .L50 + 497:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 498:Generated_Source\PSoC4/cy_em_eeprom.c **** /* The code reached the row that is about to be written. Analyze the recently + 499:Generated_Source\PSoC4/cy_em_eeprom.c **** * created EEPROM header (stored in the RAM buffer currently): if it contains + 500:Generated_Source\PSoC4/cy_em_eeprom.c **** * the data for EEPROM data locations in the row that is about to be written. + 501:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 502:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpRowAddr = (uint32) writeRamBuffer; + 1014 .loc 1 502 0 + 1015 017a 2423 movs r3, #36 + 1016 017c FB18 adds r3, r7, r3 + 1017 017e C022 movs r2, #192 + 1018 0180 BA18 adds r2, r7, r2 + 1019 0182 1360 str r3, [r2] + 1020 0184 0BE0 b .L51 + 1021 .L50: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 28 + + + 503:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 504:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 505:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 506:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Retrieve the address of the previously written row by its sequence number. + 507:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer will be used to get data from the respective EEPROM header. + 508:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 509:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpRowAddr = GetRowAddrBySeqNum(i, context); + 1022 .loc 1 509 0 + 1023 0186 3A68 ldr r2, [r7] + 1024 0188 C823 movs r3, #200 + 1025 018a FB18 adds r3, r7, r3 + 1026 018c 1B68 ldr r3, [r3] + 1027 018e 1100 movs r1, r2 + 1028 0190 1800 movs r0, r3 + 1029 0192 FFF7FEFF bl GetRowAddrBySeqNum + 1030 0196 0300 movs r3, r0 + 1031 0198 C022 movs r2, #192 + 1032 019a BA18 adds r2, r7, r2 + 1033 019c 1360 str r3, [r2] + 1034 .L51: + 510:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 511:Generated_Source\PSoC4/cy_em_eeprom.c **** + 512:Generated_Source\PSoC4/cy_em_eeprom.c **** actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr, + 1035 .loc 1 512 0 + 1036 019e BA69 ldr r2, [r7, #24] + 1037 01a0 3B68 ldr r3, [r7] + 1038 01a2 9B69 ldr r3, [r3, #24] + 1039 01a4 D31A subs r3, r2, r3 + 1040 01a6 DA09 lsrs r2, r3, #7 + 1041 01a8 3B68 ldr r3, [r7] + 1042 01aa 5B68 ldr r3, [r3, #4] + 1043 01ac 1900 movs r1, r3 + 1044 01ae 1000 movs r0, r2 + 1045 01b0 FFF7FEFF bl __aeabi_uidivmod + 1046 01b4 0B00 movs r3, r1 + 1047 01b6 A822 movs r2, #168 + 1048 01b8 BA18 adds r2, r7, r2 + 1049 01ba 1360 str r3, [r2] + 513:Generated_Source\PSoC4/cy_em_eeprom.c **** context->numberOfRows, + 514:Generated_Source\PSoC4/cy_em_eeprom.c **** context->userFlashStartA + 515:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0UL != tmpRowAddr) + 1050 .loc 1 515 0 + 1051 01bc C023 movs r3, #192 + 1052 01be FB18 adds r3, r7, r3 + 1053 01c0 1B68 ldr r3, [r3] + 1054 01c2 002B cmp r3, #0 + 1055 01c4 1DD0 beq .L52 + 516:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 517:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate the required addressed for the later EEPROM historic data update * + 518:Generated_Source\PSoC4/cy_em_eeprom.c **** skipOperation = GetAddresses( + 519:Generated_Source\PSoC4/cy_em_eeprom.c **** &startAddr, + 520:Generated_Source\PSoC4/cy_em_eeprom.c **** &endAddr, + 521:Generated_Source\PSoC4/cy_em_eeprom.c **** &eeHeaderDataOffset, + 522:Generated_Source\PSoC4/cy_em_eeprom.c **** actEmEepromRowNum, + 523:Generated_Source\PSoC4/cy_em_eeprom.c **** *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFF + 1056 .loc 1 523 0 + 1057 01c6 C023 movs r3, #192 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 29 + + + 1058 01c8 FB18 adds r3, r7, r3 + 1059 01ca 1B68 ldr r3, [r3] + 1060 01cc 0433 adds r3, r3, #4 + 518:Generated_Source\PSoC4/cy_em_eeprom.c **** &startAddr, + 1061 .loc 1 518 0 + 1062 01ce 1A68 ldr r2, [r3] + 524:Generated_Source\PSoC4/cy_em_eeprom.c **** *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFS + 1063 .loc 1 524 0 + 1064 01d0 C023 movs r3, #192 + 1065 01d2 FB18 adds r3, r7, r3 + 1066 01d4 1B68 ldr r3, [r3] + 1067 01d6 0833 adds r3, r3, #8 + 518:Generated_Source\PSoC4/cy_em_eeprom.c **** &startAddr, + 1068 .loc 1 518 0 + 1069 01d8 1B68 ldr r3, [r3] + 1070 01da A821 movs r1, #168 + 1071 01dc 7918 adds r1, r7, r1 + 1072 01de 0D68 ldr r5, [r1] + 1073 01e0 1021 movs r1, #16 + 1074 01e2 7C18 adds r4, r7, r1 + 1075 01e4 1C21 movs r1, #28 + 1076 01e6 7918 adds r1, r7, r1 + 1077 01e8 2020 movs r0, #32 + 1078 01ea 3818 adds r0, r7, r0 + 1079 01ec 0193 str r3, [sp, #4] + 1080 01ee 0092 str r2, [sp] + 1081 01f0 2B00 movs r3, r5 + 1082 01f2 2200 movs r2, r4 + 1083 01f4 FFF7FEFF bl GetAddresses + 1084 01f8 0300 movs r3, r0 + 1085 01fa B822 movs r2, #184 + 1086 01fc BA18 adds r2, r7, r2 + 1087 01fe 1360 str r3, [r2] + 1088 0200 06E0 b .L53 + 1089 .L52: + 525:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 526:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 527:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 528:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Skip writes to the RAM buffer */ + 529:Generated_Source\PSoC4/cy_em_eeprom.c **** skipOperation++; + 1090 .loc 1 529 0 + 1091 0202 B823 movs r3, #184 + 1092 0204 FB18 adds r3, r7, r3 + 1093 0206 1B68 ldr r3, [r3] + 1094 0208 0133 adds r3, r3, #1 + 1095 020a B822 movs r2, #184 + 1096 020c BA18 adds r2, r7, r2 + 1097 020e 1360 str r3, [r2] + 1098 .L53: + 530:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 531:Generated_Source\PSoC4/cy_em_eeprom.c **** + 532:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write data to the RAM buffer */ + 533:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u == skipOperation) + 1099 .loc 1 533 0 + 1100 0210 B823 movs r3, #184 + 1101 0212 FB18 adds r3, r7, r3 + 1102 0214 1B68 ldr r3, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 30 + + + 1103 0216 002B cmp r3, #0 + 1104 0218 1BD1 bne .L54 + 1105 .LBB8: + 534:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 535:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr; + 1106 .loc 1 535 0 + 1107 021a 2423 movs r3, #36 + 1108 021c FA18 adds r2, r7, r3 + 1109 021e 3B6A ldr r3, [r7, #32] + 1110 0220 D318 adds r3, r2, r3 + 1111 0222 A422 movs r2, #164 + 1112 0224 BA18 adds r2, r7, r2 + 1113 0226 1360 str r3, [r2] + 536:Generated_Source\PSoC4/cy_em_eeprom.c **** + 537:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Update the address to point to the EEPROM header data and not to + 538:Generated_Source\PSoC4/cy_em_eeprom.c **** * the start of the row. + 539:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 540:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset; + 1114 .loc 1 540 0 + 1115 0228 3A69 ldr r2, [r7, #16] + 1116 022a C023 movs r3, #192 + 1117 022c FB18 adds r3, r7, r3 + 1118 022e 1B68 ldr r3, [r3] + 1119 0230 D318 adds r3, r2, r3 + 1120 0232 0C33 adds r3, r3, #12 + 1121 0234 C022 movs r2, #192 + 1122 0236 BA18 adds r2, r7, r2 + 1123 0238 1360 str r3, [r2] + 541:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr); + 1124 .loc 1 541 0 + 1125 023a A423 movs r3, #164 + 1126 023c FB18 adds r3, r7, r3 + 1127 023e 1868 ldr r0, [r3] + 1128 0240 C023 movs r3, #192 + 1129 0242 FB18 adds r3, r7, r3 + 1130 0244 1968 ldr r1, [r3] + 1131 0246 FA69 ldr r2, [r7, #28] + 1132 0248 3B6A ldr r3, [r7, #32] + 1133 024a D31A subs r3, r2, r3 + 1134 024c 1A00 movs r2, r3 + 1135 024e FFF7FEFF bl memcpy + 1136 .L54: + 1137 .LBE8: + 542:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 543:Generated_Source\PSoC4/cy_em_eeprom.c **** + 544:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate the checksum if redundant copy is enabled */ + 545:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != context->redundantCopy) + 1138 .loc 1 545 0 + 1139 0252 3B68 ldr r3, [r7] + 1140 0254 1B7D ldrb r3, [r3, #20] + 1141 0256 002B cmp r3, #0 + 1142 0258 0BD0 beq .L55 + 546:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 547:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + 548:Generated_Source\PSoC4/cy_em_eeprom.c **** CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32] + 1143 .loc 1 548 0 + 1144 025a 2423 movs r3, #36 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 31 + + + 1145 025c FB18 adds r3, r7, r3 + 1146 025e 4033 adds r3, r3, #64 + 1147 0260 4021 movs r1, #64 + 1148 0262 1800 movs r0, r3 + 1149 0264 FFF7FEFF bl CalcChecksum + 1150 0268 0300 movs r3, r0 + 547:Generated_Source\PSoC4/cy_em_eeprom.c **** CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32] + 1151 .loc 1 547 0 + 1152 026a 1A00 movs r2, r3 + 1153 026c 2423 movs r3, #36 + 1154 026e FB18 adds r3, r7, r3 + 1155 0270 DA63 str r2, [r3, #60] + 1156 .L55: + 494:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1157 .loc 1 494 0 + 1158 0272 C823 movs r3, #200 + 1159 0274 FB18 adds r3, r7, r3 + 1160 0276 1B68 ldr r3, [r3] + 1161 0278 0133 adds r3, r3, #1 + 1162 027a C822 movs r2, #200 + 1163 027c BA18 adds r2, r7, r2 + 1164 027e 1360 str r3, [r2] + 1165 .L49: + 494:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1166 .loc 1 494 0 is_stmt 0 discriminator 1 + 1167 0280 C823 movs r3, #200 + 1168 0282 FB18 adds r3, r7, r3 + 1169 0284 1A68 ldr r2, [r3] + 1170 0286 B023 movs r3, #176 + 1171 0288 FB18 adds r3, r7, r3 + 1172 028a 1B68 ldr r3, [r3] + 1173 028c 9A42 cmp r2, r3 + 1174 028e 00D8 bhi .LCB1002 + 1175 0290 6BE7 b .L56 @long jump + 1176 .LCB1002: + 549:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_EEPROM_DATA_LEN); + 550:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 551:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 552:Generated_Source\PSoC4/cy_em_eeprom.c **** + 553:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the data to the specified flash row */ + 554:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(emEepromRowAddr, writeRamBuffer, context); + 1177 .loc 1 554 0 is_stmt 1 + 1178 0292 BB69 ldr r3, [r7, #24] + 1179 0294 CF22 movs r2, #207 + 1180 0296 BC18 adds r4, r7, r2 + 1181 0298 3A68 ldr r2, [r7] + 1182 029a 2421 movs r1, #36 + 1183 029c 7918 adds r1, r7, r1 + 1184 029e 1800 movs r0, r3 + 1185 02a0 FFF7FEFF bl WriteRow + 1186 02a4 0300 movs r3, r0 + 1187 02a6 2370 strb r3, [r4] + 555:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpRowAddr = emEepromRowAddr; + 1188 .loc 1 555 0 + 1189 02a8 BB69 ldr r3, [r7, #24] + 1190 02aa C022 movs r2, #192 + 1191 02ac BA18 adds r2, r7, r2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 32 + + + 1192 02ae 1360 str r3, [r2] + 556:Generated_Source\PSoC4/cy_em_eeprom.c **** + 557:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if redundant copy is used */ + 558:Generated_Source\PSoC4/cy_em_eeprom.c **** if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret)) + 1193 .loc 1 558 0 + 1194 02b0 3B68 ldr r3, [r7] + 1195 02b2 1B7D ldrb r3, [r3, #20] + 1196 02b4 002B cmp r3, #0 + 1197 02b6 1BD0 beq .L57 + 1198 .loc 1 558 0 is_stmt 0 discriminator 1 + 1199 02b8 CF23 movs r3, #207 + 1200 02ba FB18 adds r3, r7, r3 + 1201 02bc 1B78 ldrb r3, [r3] + 1202 02be 002B cmp r3, #0 + 1203 02c0 16D1 bne .L57 + 559:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 560:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Update the row address to point to the row in the redundant EEPROM's copy */ + 561:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + 1204 .loc 1 561 0 is_stmt 1 + 1205 02c2 BA69 ldr r2, [r7, #24] + 1206 02c4 3B68 ldr r3, [r7] + 1207 02c6 9B69 ldr r3, [r3, #24] + 1208 02c8 D21A subs r2, r2, r3 + 1209 02ca 3B68 ldr r3, [r7] + 1210 02cc 1B68 ldr r3, [r3] + 1211 02ce D318 adds r3, r2, r3 + 1212 02d0 C022 movs r2, #192 + 1213 02d2 BA18 adds r2, r7, r2 + 1214 02d4 1360 str r3, [r2] + 562:Generated_Source\PSoC4/cy_em_eeprom.c **** + 563:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the data to the specified flash row */ + 564:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + 1215 .loc 1 564 0 + 1216 02d6 CF23 movs r3, #207 + 1217 02d8 FC18 adds r4, r7, r3 + 1218 02da 3A68 ldr r2, [r7] + 1219 02dc 2423 movs r3, #36 + 1220 02de F918 adds r1, r7, r3 + 1221 02e0 C023 movs r3, #192 + 1222 02e2 FB18 adds r3, r7, r3 + 1223 02e4 1B68 ldr r3, [r3] + 1224 02e6 1800 movs r0, r3 + 1225 02e8 FFF7FEFF bl WriteRow + 1226 02ec 0300 movs r3, r0 + 1227 02ee 2370 strb r3, [r4] + 1228 .L57: + 565:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 566:Generated_Source\PSoC4/cy_em_eeprom.c **** + 567:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS == ret) + 1229 .loc 1 567 0 + 1230 02f0 CF23 movs r3, #207 + 1231 02f2 FB18 adds r3, r7, r3 + 1232 02f4 1B78 ldrb r3, [r3] + 1233 02f6 002B cmp r3, #0 + 1234 02f8 13D1 bne .L63 + 568:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 569:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Store last written row address only when EEPROM and redundant + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 33 + + + 570:Generated_Source\PSoC4/cy_em_eeprom.c **** * copy writes were successful. + 571:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 572:Generated_Source\PSoC4/cy_em_eeprom.c **** context->lastWrRowAddr = emEepromRowAddr; + 1235 .loc 1 572 0 + 1236 02fa BA69 ldr r2, [r7, #24] + 1237 02fc 3B68 ldr r3, [r7] + 1238 02fe 9A60 str r2, [r3, #8] + 1239 .LBE7: + 435:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1240 .loc 1 435 0 + 1241 0300 C423 movs r3, #196 + 1242 0302 FB18 adds r3, r7, r3 + 1243 0304 1B68 ldr r3, [r3] + 1244 0306 0133 adds r3, r3, #1 + 1245 0308 C422 movs r2, #196 + 1246 030a BA18 adds r2, r7, r2 + 1247 030c 1360 str r3, [r2] + 1248 .L43: + 435:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1249 .loc 1 435 0 is_stmt 0 discriminator 1 + 1250 030e C423 movs r3, #196 + 1251 0310 FB18 adds r3, r7, r3 + 1252 0312 1A68 ldr r2, [r3] + 1253 0314 B423 movs r3, #180 + 1254 0316 FB18 adds r3, r7, r3 + 1255 0318 1B68 ldr r3, [r3] + 1256 031a 9A42 cmp r2, r3 + 1257 031c 00D2 bcs .LCB1075 + 1258 031e A7E6 b .L61 @long jump + 1259 .LCB1075: + 1260 0320 00E0 b .L42 + 1261 .L63: + 1262 .LBB9: + 573:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 574:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 575:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 576:Generated_Source\PSoC4/cy_em_eeprom.c **** break; + 1263 .loc 1 576 0 is_stmt 1 + 1264 0322 C046 nop + 1265 .L42: + 1266 .LBE9: + 1267 .LBE6: + 577:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 578:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 579:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 580:Generated_Source\PSoC4/cy_em_eeprom.c **** return(ret); + 1268 .loc 1 580 0 + 1269 0324 CF23 movs r3, #207 + 1270 0326 FB18 adds r3, r7, r3 + 1271 0328 1B78 ldrb r3, [r3] + 581:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1272 .loc 1 581 0 + 1273 032a 1800 movs r0, r3 + 1274 032c BD46 mov sp, r7 + 1275 032e 34B0 add sp, sp, #208 + 1276 @ sp needed + 1277 0330 B0BD pop {r4, r5, r7, pc} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 34 + + + 1278 .cfi_endproc + 1279 .LFE2: + 1280 .size Cy_Em_EEPROM_Write, .-Cy_Em_EEPROM_Write + 1281 0332 C046 .section .text.Cy_Em_EEPROM_Erase,"ax",%progbits + 1282 .align 2 + 1283 .global Cy_Em_EEPROM_Erase + 1284 .code 16 + 1285 .thumb_func + 1286 .type Cy_Em_EEPROM_Erase, %function + 1287 Cy_Em_EEPROM_Erase: + 1288 .LFB3: + 582:Generated_Source\PSoC4/cy_em_eeprom.c **** + 583:Generated_Source\PSoC4/cy_em_eeprom.c **** + 584:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 585:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: Cy_Em_EEPROM_Erase + 586:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 587:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 588:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function erases the entire contents of the EEPROM. Erased values are all + 589:Generated_Source\PSoC4/cy_em_eeprom.c **** * zeros. This is a blocking function and it does not return until the write + 590:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation is completed. The user firmware should not enter Hibernate mode until + 591:Generated_Source\PSoC4/cy_em_eeprom.c **** * erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes. + 592:Generated_Source\PSoC4/cy_em_eeprom.c **** * During the flash operation, the device should not be reset, including the + 593:Generated_Source\PSoC4/cy_em_eeprom.c **** * XRES pin, a software reset, and watchdog reset sources. Also, low-voltage + 594:Generated_Source\PSoC4/cy_em_eeprom.c **** * detect circuits should be configured to generate an interrupt instead of a + 595:Generated_Source\PSoC4/cy_em_eeprom.c **** * reset. Otherwise, portions of flash may undergo unexpected changes. + 596:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 597:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 598:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. + 599:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 600:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 601:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function returns \ref cy_en_em_eeprom_status_t. + 602:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 603:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note + 604:Generated_Source\PSoC4/cy_em_eeprom.c **** * For all non PSoC 6 devices the erase operation is performed by clearing + 605:Generated_Source\PSoC4/cy_em_eeprom.c **** * the EEPROM data using flash write. This affects the flash durability. + 606:Generated_Source\PSoC4/cy_em_eeprom.c **** * So it is recommended to use this function in utmost case to prolongate + 607:Generated_Source\PSoC4/cy_em_eeprom.c **** * flash life. + 608:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 609:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note + 610:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function uses a buffer of the flash row size to perform erase + 611:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation. For the size of the row refer to the specific PSoC device + 612:Generated_Source\PSoC4/cy_em_eeprom.c **** * datasheet. + 613:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 614:Generated_Source\PSoC4/cy_em_eeprom.c **** * \sideeffect + 615:Generated_Source\PSoC4/cy_em_eeprom.c **** * In case when blocking write option is used, if this function is called by + 616:Generated_Source\PSoC4/cy_em_eeprom.c **** * the CM4 the user code on CM0P and the user code on CM4 are blocked until erase + 617:Generated_Source\PSoC4/cy_em_eeprom.c **** * flash row operation is finished. If this function is called by the CM0P the + 618:Generated_Source\PSoC4/cy_em_eeprom.c **** * user code on CM4 is not blocked and the user code on CM0P is blocked until + 619:Generated_Source\PSoC4/cy_em_eeprom.c **** * erase flash row operation is finished. Plan your task allocation accordingly. + 620:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 621:Generated_Source\PSoC4/cy_em_eeprom.c **** * \sideeffect + 622:Generated_Source\PSoC4/cy_em_eeprom.c **** * In case if non-blocking write option is used and when user flash is used as + 623:Generated_Source\PSoC4/cy_em_eeprom.c **** * an EEPROM storage care should be taken to prevent the read while write (RWW) + 624:Generated_Source\PSoC4/cy_em_eeprom.c **** * exception. To prevent the RWW exception the user flash macro that includes + 625:Generated_Source\PSoC4/cy_em_eeprom.c **** * the EEPROM storage should not be read while the EEPROM erase is not completed. + 626:Generated_Source\PSoC4/cy_em_eeprom.c **** * The read also means the user code execution from the respective flash macro. + 627:Generated_Source\PSoC4/cy_em_eeprom.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 35 + + + 628:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 629:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context) + 630:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1289 .loc 1 630 0 + 1290 .cfi_startproc + 1291 @ args = 0, pretend = 0, frame = 160 + 1292 @ frame_needed = 1, uses_anonymous_args = 0 + 1293 0000 90B5 push {r4, r7, lr} + 1294 .cfi_def_cfa_offset 12 + 1295 .cfi_offset 4, -12 + 1296 .cfi_offset 7, -8 + 1297 .cfi_offset 14, -4 + 1298 0002 A9B0 sub sp, sp, #164 + 1299 .cfi_def_cfa_offset 176 + 1300 0004 00AF add r7, sp, #0 + 1301 .cfi_def_cfa_register 7 + 1302 0006 7860 str r0, [r7, #4] + 631:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 i; + 632:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 seqNum; + 633:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromRowAddr = context->lastWrRowAddr; + 1303 .loc 1 633 0 + 1304 0008 7B68 ldr r3, [r7, #4] + 1305 000a 9B68 ldr r3, [r3, #8] + 1306 000c 8C22 movs r2, #140 + 1307 000e BA18 adds r2, r7, r2 + 1308 0010 1360 str r3, [r2] + 634:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromRowRdAddr; + 635:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + 1309 .loc 1 635 0 + 1310 0012 9B23 movs r3, #155 + 1311 0014 FB18 adds r3, r7, r3 + 1312 0016 0422 movs r2, #4 + 1313 0018 1A70 strb r2, [r3] + 636:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u}; + 1314 .loc 1 636 0 + 1315 001a 0823 movs r3, #8 + 1316 001c FB18 adds r3, r7, r3 + 1317 001e 1800 movs r0, r3 + 1318 0020 8023 movs r3, #128 + 1319 0022 1A00 movs r2, r3 + 1320 0024 0021 movs r1, #0 + 1321 0026 FFF7FEFF bl memset + 637:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC6) + 638:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromStoredRowAddr = context->lastWrRowAddr; + 639:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 storedSeqNum; + 640:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (!CY_PSOC6) */ + 641:Generated_Source\PSoC4/cy_em_eeprom.c **** + 642:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the sequence number of the last written row */ + 643:Generated_Source\PSoC4/cy_em_eeprom.c **** seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + 1322 .loc 1 643 0 + 1323 002a 8C23 movs r3, #140 + 1324 002c FB18 adds r3, r7, r3 + 1325 002e 1B68 ldr r3, [r3] + 1326 0030 1B68 ldr r3, [r3] + 1327 0032 9422 movs r2, #148 + 1328 0034 BA18 adds r2, r7, r2 + 1329 0036 1360 str r3, [r2] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 36 + + + 644:Generated_Source\PSoC4/cy_em_eeprom.c **** + 645:Generated_Source\PSoC4/cy_em_eeprom.c **** /* If there were no writes to EEPROM - nothing to erase */ + 646:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != seqNum) + 1330 .loc 1 646 0 + 1331 0038 9423 movs r3, #148 + 1332 003a FB18 adds r3, r7, r3 + 1333 003c 1B68 ldr r3, [r3] + 1334 003e 002B cmp r3, #0 + 1335 0040 56D0 beq .L65 + 1336 .LBB10: + 647:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 648:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate the number of row erase operations required */ + 649:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 numWrites = context->numberOfRows * context->wearLevelingFactor; + 1337 .loc 1 649 0 + 1338 0042 7B68 ldr r3, [r7, #4] + 1339 0044 5A68 ldr r2, [r3, #4] + 1340 0046 7B68 ldr r3, [r7, #4] + 1341 0048 1B69 ldr r3, [r3, #16] + 1342 004a 5343 muls r3, r2 + 1343 004c 9022 movs r2, #144 + 1344 004e BA18 adds r2, r7, r2 + 1345 0050 1360 str r3, [r2] + 650:Generated_Source\PSoC4/cy_em_eeprom.c **** + 651:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC6) + 652:Generated_Source\PSoC4/cy_em_eeprom.c **** GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context); + 653:Generated_Source\PSoC4/cy_em_eeprom.c **** storedSeqNum = seqNum + 1u; + 654:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC6) */ + 655:Generated_Source\PSoC4/cy_em_eeprom.c **** + 656:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != context->redundantCopy) + 1346 .loc 1 656 0 + 1347 0052 7B68 ldr r3, [r7, #4] + 1348 0054 1B7D ldrb r3, [r3, #20] + 1349 0056 002B cmp r3, #0 + 1350 0058 0BD0 beq .L66 + 657:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 658:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + 659:Generated_Source\PSoC4/cy_em_eeprom.c **** CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32] + 1351 .loc 1 659 0 + 1352 005a 0823 movs r3, #8 + 1353 005c FB18 adds r3, r7, r3 + 1354 005e 4033 adds r3, r3, #64 + 1355 0060 4021 movs r1, #64 + 1356 0062 1800 movs r0, r3 + 1357 0064 FFF7FEFF bl CalcChecksum + 1358 0068 0300 movs r3, r0 + 658:Generated_Source\PSoC4/cy_em_eeprom.c **** CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32] + 1359 .loc 1 658 0 + 1360 006a 1A00 movs r2, r3 + 1361 006c 0823 movs r3, #8 + 1362 006e FB18 adds r3, r7, r3 + 1363 0070 DA63 str r2, [r3, #60] + 1364 .L66: + 660:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_EEPROM_DATA_LEN); + 661:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 662:Generated_Source\PSoC4/cy_em_eeprom.c **** + 663:Generated_Source\PSoC4/cy_em_eeprom.c **** for(i = 0u; i < numWrites; i++) + 1365 .loc 1 663 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 37 + + + 1366 0072 0023 movs r3, #0 + 1367 0074 9C22 movs r2, #156 + 1368 0076 BA18 adds r2, r7, r2 + 1369 0078 1360 str r3, [r2] + 1370 007a 31E0 b .L67 + 1371 .L68: + 664:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 665:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC6) + 666:Generated_Source\PSoC4/cy_em_eeprom.c **** /* For PSoC 6 the erase operation moves backwards. From last written row + 667:Generated_Source\PSoC4/cy_em_eeprom.c **** * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr" + 668:Generated_Source\PSoC4/cy_em_eeprom.c **** * is zero this means that the row identified by "seqNum" was previously + 669:Generated_Source\PSoC4/cy_em_eeprom.c **** * erased. + 670:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 671:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != emEepromRowAddr) + 672:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 673:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + 674:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 675:Generated_Source\PSoC4/cy_em_eeprom.c **** + 676:Generated_Source\PSoC4/cy_em_eeprom.c **** seqNum--; + 677:Generated_Source\PSoC4/cy_em_eeprom.c **** + 678:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u == seqNum) + 679:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 680:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Exit the loop as there is no more row is EEPROM to be erased */ + 681:Generated_Source\PSoC4/cy_em_eeprom.c **** break; + 682:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 683:Generated_Source\PSoC4/cy_em_eeprom.c **** emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context); + 684:Generated_Source\PSoC4/cy_em_eeprom.c **** #else + 685:Generated_Source\PSoC4/cy_em_eeprom.c **** seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + 1372 .loc 1 685 0 discriminator 3 + 1373 007c 8C23 movs r3, #140 + 1374 007e FB18 adds r3, r7, r3 + 1375 0080 1B68 ldr r3, [r3] + 1376 0082 1B68 ldr r3, [r3] + 1377 0084 9422 movs r2, #148 + 1378 0086 BA18 adds r2, r7, r2 + 1379 0088 1360 str r3, [r2] + 686:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the address of the row to be erased. "emEepromRowAddr" may be updated + 687:Generated_Source\PSoC4/cy_em_eeprom.c **** * with the proper address (if wear leveling is used). + 688:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 689:Generated_Source\PSoC4/cy_em_eeprom.c **** GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + 1380 .loc 1 689 0 discriminator 3 + 1381 008a 7B68 ldr r3, [r7, #4] + 1382 008c 8822 movs r2, #136 + 1383 008e BA18 adds r2, r7, r2 + 1384 0090 8C21 movs r1, #140 + 1385 0092 7918 adds r1, r7, r1 + 1386 0094 9420 movs r0, #148 + 1387 0096 3818 adds r0, r7, r0 + 1388 0098 0068 ldr r0, [r0] + 1389 009a FFF7FEFF bl GetNextRowToWrite + 690:Generated_Source\PSoC4/cy_em_eeprom.c **** seqNum++; + 1390 .loc 1 690 0 discriminator 3 + 1391 009e 9423 movs r3, #148 + 1392 00a0 FB18 adds r3, r7, r3 + 1393 00a2 1B68 ldr r3, [r3] + 1394 00a4 0133 adds r3, r3, #1 + 1395 00a6 9422 movs r2, #148 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 38 + + + 1396 00a8 BA18 adds r2, r7, r2 + 1397 00aa 1360 str r3, [r2] + 691:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[0u] = seqNum; + 1398 .loc 1 691 0 discriminator 3 + 1399 00ac 0823 movs r3, #8 + 1400 00ae FB18 adds r3, r7, r3 + 1401 00b0 9422 movs r2, #148 + 1402 00b2 BA18 adds r2, r7, r2 + 1403 00b4 1268 ldr r2, [r2] + 1404 00b6 1A60 str r2, [r3] + 692:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + 1405 .loc 1 692 0 discriminator 3 + 1406 00b8 8C23 movs r3, #140 + 1407 00ba FB18 adds r3, r7, r3 + 1408 00bc 1B68 ldr r3, [r3] + 1409 00be 0822 movs r2, #8 + 1410 00c0 B918 adds r1, r7, r2 + 1411 00c2 9B22 movs r2, #155 + 1412 00c4 BC18 adds r4, r7, r2 + 1413 00c6 7A68 ldr r2, [r7, #4] + 1414 00c8 1800 movs r0, r3 + 1415 00ca FFF7FEFF bl EraseRow + 1416 00ce 0300 movs r3, r0 + 1417 00d0 2370 strb r3, [r4] + 663:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1418 .loc 1 663 0 discriminator 3 + 1419 00d2 9C23 movs r3, #156 + 1420 00d4 FB18 adds r3, r7, r3 + 1421 00d6 1B68 ldr r3, [r3] + 1422 00d8 0133 adds r3, r3, #1 + 1423 00da 9C22 movs r2, #156 + 1424 00dc BA18 adds r2, r7, r2 + 1425 00de 1360 str r3, [r2] + 1426 .L67: + 663:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1427 .loc 1 663 0 is_stmt 0 discriminator 1 + 1428 00e0 9C23 movs r3, #156 + 1429 00e2 FB18 adds r3, r7, r3 + 1430 00e4 1A68 ldr r2, [r3] + 1431 00e6 9023 movs r3, #144 + 1432 00e8 FB18 adds r3, r7, r3 + 1433 00ea 1B68 ldr r3, [r3] + 1434 00ec 9A42 cmp r2, r3 + 1435 00ee C5D3 bcc .L68 + 1436 .L65: + 1437 .LBE10: + 693:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC6) */ + 694:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 695:Generated_Source\PSoC4/cy_em_eeprom.c **** + 696:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC6) + 697:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS == ret) + 698:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 699:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[0u] = storedSeqNum; + 700:Generated_Source\PSoC4/cy_em_eeprom.c **** + 701:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the previously stored sequence number to the flash row which would be + 702:Generated_Source\PSoC4/cy_em_eeprom.c **** * written next if the erase wouldn't happen. In this case the write to + 703:Generated_Source\PSoC4/cy_em_eeprom.c **** * redundant copy can be skipped as it does not add any value. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 39 + + + 704:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 705:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context); + 706:Generated_Source\PSoC4/cy_em_eeprom.c **** + 707:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS == ret) + 708:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 709:Generated_Source\PSoC4/cy_em_eeprom.c **** context->lastWrRowAddr = emEepromStoredRowAddr; + 710:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 711:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 712:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC6) */ + 713:Generated_Source\PSoC4/cy_em_eeprom.c **** + 714:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 715:Generated_Source\PSoC4/cy_em_eeprom.c **** return(ret); + 1438 .loc 1 715 0 is_stmt 1 + 1439 00f0 9B23 movs r3, #155 + 1440 00f2 FB18 adds r3, r7, r3 + 1441 00f4 1B78 ldrb r3, [r3] + 716:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1442 .loc 1 716 0 + 1443 00f6 1800 movs r0, r3 + 1444 00f8 BD46 mov sp, r7 + 1445 00fa 29B0 add sp, sp, #164 + 1446 @ sp needed + 1447 00fc 90BD pop {r4, r7, pc} + 1448 .cfi_endproc + 1449 .LFE3: + 1450 .size Cy_Em_EEPROM_Erase, .-Cy_Em_EEPROM_Erase + 1451 00fe C046 .section .text.Cy_Em_EEPROM_NumWrites,"ax",%progbits + 1452 .align 2 + 1453 .global Cy_Em_EEPROM_NumWrites + 1454 .code 16 + 1455 .thumb_func + 1456 .type Cy_Em_EEPROM_NumWrites, %function + 1457 Cy_Em_EEPROM_NumWrites: + 1458 .LFB4: + 717:Generated_Source\PSoC4/cy_em_eeprom.c **** + 718:Generated_Source\PSoC4/cy_em_eeprom.c **** + 719:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 720:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: Cy_Em_EEPROM_NumWrites + 721:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 722:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 723:Generated_Source\PSoC4/cy_em_eeprom.c **** * Returns the number of the EEPROM writes completed so far. + 724:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 725:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 726:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. + 727:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 728:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 729:Generated_Source\PSoC4/cy_em_eeprom.c **** * The number of writes performed to the EEPROM. + 730:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 731:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 732:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context) + 733:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1459 .loc 1 733 0 + 1460 .cfi_startproc + 1461 @ args = 0, pretend = 0, frame = 8 + 1462 @ frame_needed = 1, uses_anonymous_args = 0 + 1463 0000 80B5 push {r7, lr} + 1464 .cfi_def_cfa_offset 8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 40 + + + 1465 .cfi_offset 7, -8 + 1466 .cfi_offset 14, -4 + 1467 0002 82B0 sub sp, sp, #8 + 1468 .cfi_def_cfa_offset 16 + 1469 0004 00AF add r7, sp, #0 + 1470 .cfi_def_cfa_register 7 + 1471 0006 7860 str r0, [r7, #4] + 734:Generated_Source\PSoC4/cy_em_eeprom.c **** return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)); + 1472 .loc 1 734 0 + 1473 0008 7B68 ldr r3, [r7, #4] + 1474 000a 9B68 ldr r3, [r3, #8] + 1475 000c 1B68 ldr r3, [r3] + 735:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1476 .loc 1 735 0 + 1477 000e 1800 movs r0, r3 + 1478 0010 BD46 mov sp, r7 + 1479 0012 02B0 add sp, sp, #8 + 1480 @ sp needed + 1481 0014 80BD pop {r7, pc} + 1482 .cfi_endproc + 1483 .LFE4: + 1484 .size Cy_Em_EEPROM_NumWrites, .-Cy_Em_EEPROM_NumWrites + 1485 0016 C046 .section .text.FindLastWrittenRow,"ax",%progbits + 1486 .align 2 + 1487 .code 16 + 1488 .thumb_func + 1489 .type FindLastWrittenRow, %function + 1490 FindLastWrittenRow: + 1491 .LFB5: + 736:Generated_Source\PSoC4/cy_em_eeprom.c **** + 737:Generated_Source\PSoC4/cy_em_eeprom.c **** /** \} */ + 738:Generated_Source\PSoC4/cy_em_eeprom.c **** + 739:Generated_Source\PSoC4/cy_em_eeprom.c **** /** \cond INTERNAL */ + 740:Generated_Source\PSoC4/cy_em_eeprom.c **** + 741:Generated_Source\PSoC4/cy_em_eeprom.c **** + 742:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 743:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: FindLastWrittenRow + 744:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 745:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 746:Generated_Source\PSoC4/cy_em_eeprom.c **** * Performs a search of the last written row address of the EEPROM associated + 747:Generated_Source\PSoC4/cy_em_eeprom.c **** * with the context structure. If there were no writes to the EEPROM the + 748:Generated_Source\PSoC4/cy_em_eeprom.c **** * function returns the start address of the EEPROM. The row address is returned + 749:Generated_Source\PSoC4/cy_em_eeprom.c **** * in the input parameter. + 750:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 751:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param lastWrRowPtr + 752:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to a memory where the last written row will be returned. + 753:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 754:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 755:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. + 756:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 757:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 758:Generated_Source\PSoC4/cy_em_eeprom.c **** static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context) + 759:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1492 .loc 1 759 0 + 1493 .cfi_startproc + 1494 @ args = 0, pretend = 0, frame = 24 + 1495 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 41 + + + 1496 0000 80B5 push {r7, lr} + 1497 .cfi_def_cfa_offset 8 + 1498 .cfi_offset 7, -8 + 1499 .cfi_offset 14, -4 + 1500 0002 86B0 sub sp, sp, #24 + 1501 .cfi_def_cfa_offset 32 + 1502 0004 00AF add r7, sp, #0 + 1503 .cfi_def_cfa_register 7 + 1504 0006 7860 str r0, [r7, #4] + 1505 0008 3960 str r1, [r7] + 760:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 seqNum = 0u; + 1506 .loc 1 760 0 + 1507 000a 0023 movs r3, #0 + 1508 000c BB60 str r3, [r7, #8] + 761:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 prevSeqNum = 0u; + 1509 .loc 1 761 0 + 1510 000e 0023 movs r3, #0 + 1511 0010 7B61 str r3, [r7, #20] + 762:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 numRows; + 763:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromAddr = context->userFlashStartAddr; + 1512 .loc 1 763 0 + 1513 0012 3B68 ldr r3, [r7] + 1514 0014 9B69 ldr r3, [r3, #24] + 1515 0016 FB60 str r3, [r7, #12] + 764:Generated_Source\PSoC4/cy_em_eeprom.c **** + 765:Generated_Source\PSoC4/cy_em_eeprom.c **** *lastWrRowPtr = emEepromAddr; + 1516 .loc 1 765 0 + 1517 0018 7B68 ldr r3, [r7, #4] + 1518 001a FA68 ldr r2, [r7, #12] + 1519 001c 1A60 str r2, [r3] + 766:Generated_Source\PSoC4/cy_em_eeprom.c **** + 767:Generated_Source\PSoC4/cy_em_eeprom.c **** for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++) + 1520 .loc 1 767 0 + 1521 001e 0023 movs r3, #0 + 1522 0020 3B61 str r3, [r7, #16] + 1523 0022 14E0 b .L73 + 1524 .L75: + 768:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 769:Generated_Source\PSoC4/cy_em_eeprom.c **** seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr); + 1525 .loc 1 769 0 + 1526 0024 FB68 ldr r3, [r7, #12] + 1527 0026 1B68 ldr r3, [r3] + 1528 0028 BB60 str r3, [r7, #8] + 770:Generated_Source\PSoC4/cy_em_eeprom.c **** if((0u != seqNum) && (seqNum > prevSeqNum)) + 1529 .loc 1 770 0 + 1530 002a BB68 ldr r3, [r7, #8] + 1531 002c 002B cmp r3, #0 + 1532 002e 08D0 beq .L74 + 1533 .loc 1 770 0 is_stmt 0 discriminator 1 + 1534 0030 BA68 ldr r2, [r7, #8] + 1535 0032 7B69 ldr r3, [r7, #20] + 1536 0034 9A42 cmp r2, r3 + 1537 0036 04D9 bls .L74 + 771:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 772:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Some record in EEPROM was found. Store found sequence + 773:Generated_Source\PSoC4/cy_em_eeprom.c **** * number and row address. + 774:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 42 + + + 775:Generated_Source\PSoC4/cy_em_eeprom.c **** prevSeqNum = seqNum; + 1538 .loc 1 775 0 is_stmt 1 + 1539 0038 BB68 ldr r3, [r7, #8] + 1540 003a 7B61 str r3, [r7, #20] + 776:Generated_Source\PSoC4/cy_em_eeprom.c **** *lastWrRowPtr = emEepromAddr; + 1541 .loc 1 776 0 + 1542 003c 7B68 ldr r3, [r7, #4] + 1543 003e FA68 ldr r2, [r7, #12] + 1544 0040 1A60 str r2, [r3] + 1545 .L74: + 777:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 778:Generated_Source\PSoC4/cy_em_eeprom.c **** + 779:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Switch to the next row */ + 780:Generated_Source\PSoC4/cy_em_eeprom.c **** emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + 1546 .loc 1 780 0 discriminator 2 + 1547 0042 FB68 ldr r3, [r7, #12] + 1548 0044 8033 adds r3, r3, #128 + 1549 0046 FB60 str r3, [r7, #12] + 767:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1550 .loc 1 767 0 discriminator 2 + 1551 0048 3B69 ldr r3, [r7, #16] + 1552 004a 0133 adds r3, r3, #1 + 1553 004c 3B61 str r3, [r7, #16] + 1554 .L73: + 767:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1555 .loc 1 767 0 is_stmt 0 discriminator 1 + 1556 004e 3B68 ldr r3, [r7] + 1557 0050 5A68 ldr r2, [r3, #4] + 1558 0052 3B68 ldr r3, [r7] + 1559 0054 1B69 ldr r3, [r3, #16] + 1560 0056 5A43 muls r2, r3 + 1561 0058 3B69 ldr r3, [r7, #16] + 1562 005a 9A42 cmp r2, r3 + 1563 005c E2D8 bhi .L75 + 781:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 782:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1564 .loc 1 782 0 is_stmt 1 + 1565 005e C046 nop + 1566 0060 BD46 mov sp, r7 + 1567 0062 06B0 add sp, sp, #24 + 1568 @ sp needed + 1569 0064 80BD pop {r7, pc} + 1570 .cfi_endproc + 1571 .LFE5: + 1572 .size FindLastWrittenRow, .-FindLastWrittenRow + 1573 0066 C046 .section .text.GetRowAddrBySeqNum,"ax",%progbits + 1574 .align 2 + 1575 .code 16 + 1576 .thumb_func + 1577 .type GetRowAddrBySeqNum, %function + 1578 GetRowAddrBySeqNum: + 1579 .LFB6: + 783:Generated_Source\PSoC4/cy_em_eeprom.c **** + 784:Generated_Source\PSoC4/cy_em_eeprom.c **** + 785:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 786:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: GetRowAddrBySeqNum + 787:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 43 + + + 788:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 789:Generated_Source\PSoC4/cy_em_eeprom.c **** * Returns the address of the row in EEPROM using its sequence number. + 790:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 791:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param seqNum + 792:Generated_Source\PSoC4/cy_em_eeprom.c **** * The sequence number of the row. + 793:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 794:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 795:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure. + 796:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 797:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 798:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address of the row or zero if the row with the sequence number was not + 799:Generated_Source\PSoC4/cy_em_eeprom.c **** * found. + 800:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 801:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 802:Generated_Source\PSoC4/cy_em_eeprom.c **** static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context) + 803:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1580 .loc 1 803 0 + 1581 .cfi_startproc + 1582 @ args = 0, pretend = 0, frame = 16 + 1583 @ frame_needed = 1, uses_anonymous_args = 0 + 1584 0000 80B5 push {r7, lr} + 1585 .cfi_def_cfa_offset 8 + 1586 .cfi_offset 7, -8 + 1587 .cfi_offset 14, -4 + 1588 0002 84B0 sub sp, sp, #16 + 1589 .cfi_def_cfa_offset 24 + 1590 0004 00AF add r7, sp, #0 + 1591 .cfi_def_cfa_register 7 + 1592 0006 7860 str r0, [r7, #4] + 1593 0008 3960 str r1, [r7] + 804:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromAddr = context->userFlashStartAddr; + 1594 .loc 1 804 0 + 1595 000a 3B68 ldr r3, [r7] + 1596 000c 9B69 ldr r3, [r3, #24] + 1597 000e FB60 str r3, [r7, #12] + 805:Generated_Source\PSoC4/cy_em_eeprom.c **** + 806:Generated_Source\PSoC4/cy_em_eeprom.c **** while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum) + 1598 .loc 1 806 0 + 1599 0010 0AE0 b .L77 + 1600 .L79: + 807:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 808:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Switch to the next row */ + 809:Generated_Source\PSoC4/cy_em_eeprom.c **** emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + 1601 .loc 1 809 0 + 1602 0012 FB68 ldr r3, [r7, #12] + 1603 0014 8033 adds r3, r3, #128 + 1604 0016 FB60 str r3, [r7, #12] + 810:Generated_Source\PSoC4/cy_em_eeprom.c **** + 811:Generated_Source\PSoC4/cy_em_eeprom.c **** if (CY_EM_EEPROM_ADDR_IN_RANGE != + 812:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + 1605 .loc 1 812 0 + 1606 0018 3B68 ldr r3, [r7] + 1607 001a 1A68 ldr r2, [r3] + 811:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + 1608 .loc 1 811 0 + 1609 001c FB68 ldr r3, [r7, #12] + 1610 001e 9A42 cmp r2, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 44 + + + 1611 0020 02D8 bhi .L77 + 813:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 814:Generated_Source\PSoC4/cy_em_eeprom.c **** emEepromAddr = 0u; + 1612 .loc 1 814 0 + 1613 0022 0023 movs r3, #0 + 1614 0024 FB60 str r3, [r7, #12] + 815:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Exit the loop as we reached the end of EEPROM */ + 816:Generated_Source\PSoC4/cy_em_eeprom.c **** break; + 1615 .loc 1 816 0 + 1616 0026 04E0 b .L78 + 1617 .L77: + 806:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1618 .loc 1 806 0 + 1619 0028 FB68 ldr r3, [r7, #12] + 1620 002a 1A68 ldr r2, [r3] + 1621 002c 7B68 ldr r3, [r7, #4] + 1622 002e 9A42 cmp r2, r3 + 1623 0030 EFD1 bne .L79 + 1624 .L78: + 817:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 818:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 819:Generated_Source\PSoC4/cy_em_eeprom.c **** + 820:Generated_Source\PSoC4/cy_em_eeprom.c **** return (emEepromAddr); + 1625 .loc 1 820 0 + 1626 0032 FB68 ldr r3, [r7, #12] + 821:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1627 .loc 1 821 0 + 1628 0034 1800 movs r0, r3 + 1629 0036 BD46 mov sp, r7 + 1630 0038 04B0 add sp, sp, #16 + 1631 @ sp needed + 1632 003a 80BD pop {r7, pc} + 1633 .cfi_endproc + 1634 .LFE6: + 1635 .size GetRowAddrBySeqNum, .-GetRowAddrBySeqNum + 1636 .section .text.GetNextRowToWrite,"ax",%progbits + 1637 .align 2 + 1638 .code 16 + 1639 .thumb_func + 1640 .type GetNextRowToWrite, %function + 1641 GetNextRowToWrite: + 1642 .LFB7: + 822:Generated_Source\PSoC4/cy_em_eeprom.c **** + 823:Generated_Source\PSoC4/cy_em_eeprom.c **** + 824:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 825:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: GetNextRowToWrite + 826:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 827:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 828:Generated_Source\PSoC4/cy_em_eeprom.c **** * Performs a range check of the row that should be written and updates the + 829:Generated_Source\PSoC4/cy_em_eeprom.c **** * address to the row respectively. The similar actions are done for the read + 830:Generated_Source\PSoC4/cy_em_eeprom.c **** * address. + 831:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 832:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param seqNum + 833:Generated_Source\PSoC4/cy_em_eeprom.c **** * The sequence number of the last written row. + 834:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 835:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowToWrPtr + 836:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address of the last written row (input). The address of the row to be + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 45 + + + 837:Generated_Source\PSoC4/cy_em_eeprom.c **** * written (output). + 838:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 839:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowToRdPtr + 840:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address of the row from which the data should be read into the RAM buffer + 841:Generated_Source\PSoC4/cy_em_eeprom.c **** * in a later write operation. Out parameter. + 842:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 843:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 844:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. + 845:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 846:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 847:Generated_Source\PSoC4/cy_em_eeprom.c **** static void GetNextRowToWrite(uint32 seqNum, + 848:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 * rowToWrPtr, + 849:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 * rowToRdPtr, + 850:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context) + 851:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1643 .loc 1 851 0 + 1644 .cfi_startproc + 1645 @ args = 0, pretend = 0, frame = 16 + 1646 @ frame_needed = 1, uses_anonymous_args = 0 + 1647 0000 80B5 push {r7, lr} + 1648 .cfi_def_cfa_offset 8 + 1649 .cfi_offset 7, -8 + 1650 .cfi_offset 14, -4 + 1651 0002 84B0 sub sp, sp, #16 + 1652 .cfi_def_cfa_offset 24 + 1653 0004 00AF add r7, sp, #0 + 1654 .cfi_def_cfa_register 7 + 1655 0006 F860 str r0, [r7, #12] + 1656 0008 B960 str r1, [r7, #8] + 1657 000a 7A60 str r2, [r7, #4] + 1658 000c 3B60 str r3, [r7] + 852:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Switch to the next row to be written if the current sequence number is + 853:Generated_Source\PSoC4/cy_em_eeprom.c **** * not zero. + 854:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 855:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != seqNum) + 1659 .loc 1 855 0 + 1660 000e FB68 ldr r3, [r7, #12] + 1661 0010 002B cmp r3, #0 + 1662 0012 05D0 beq .L82 + 856:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 857:Generated_Source\PSoC4/cy_em_eeprom.c **** *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW); + 1663 .loc 1 857 0 + 1664 0014 BB68 ldr r3, [r7, #8] + 1665 0016 1B68 ldr r3, [r3] + 1666 0018 8033 adds r3, r3, #128 + 1667 001a 1A00 movs r2, r3 + 1668 001c BB68 ldr r3, [r7, #8] + 1669 001e 1A60 str r2, [r3] + 1670 .L82: + 858:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 859:Generated_Source\PSoC4/cy_em_eeprom.c **** + 860:Generated_Source\PSoC4/cy_em_eeprom.c **** /* If the resulting row address is out of EEPROM, then switch to the base + 861:Generated_Source\PSoC4/cy_em_eeprom.c **** * EEPROM address (Row#0). + 862:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 863:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_ADDR_IN_RANGE != + 864:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + 1671 .loc 1 864 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 46 + + + 1672 0020 BB68 ldr r3, [r7, #8] + 1673 0022 1A68 ldr r2, [r3] + 1674 0024 3B68 ldr r3, [r7] + 1675 0026 1B68 ldr r3, [r3] + 863:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + 1676 .loc 1 863 0 + 1677 0028 9A42 cmp r2, r3 + 1678 002a 03D3 bcc .L83 + 865:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 866:Generated_Source\PSoC4/cy_em_eeprom.c **** *rowToWrPtr = context->userFlashStartAddr; + 1679 .loc 1 866 0 + 1680 002c 3B68 ldr r3, [r7] + 1681 002e 9A69 ldr r2, [r3, #24] + 1682 0030 BB68 ldr r3, [r7, #8] + 1683 0032 1A60 str r2, [r3] + 1684 .L83: + 867:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 868:Generated_Source\PSoC4/cy_em_eeprom.c **** + 869:Generated_Source\PSoC4/cy_em_eeprom.c **** *rowToRdPtr = 0u; + 1685 .loc 1 869 0 + 1686 0034 7B68 ldr r3, [r7, #4] + 1687 0036 0022 movs r2, #0 + 1688 0038 1A60 str r2, [r3] + 870:Generated_Source\PSoC4/cy_em_eeprom.c **** + 871:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if the sequence number is larger than the number of rows in the EEPROM. + 872:Generated_Source\PSoC4/cy_em_eeprom.c **** * If not, do not update the row read address because there is no historic + 873:Generated_Source\PSoC4/cy_em_eeprom.c **** * data to be read. + 874:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 875:Generated_Source\PSoC4/cy_em_eeprom.c **** if(context->numberOfRows <= seqNum) + 1689 .loc 1 875 0 + 1690 003a 3B68 ldr r3, [r7] + 1691 003c 5A68 ldr r2, [r3, #4] + 1692 003e FB68 ldr r3, [r7, #12] + 1693 0040 9A42 cmp r2, r3 + 1694 0042 2FD8 bhi .L88 + 876:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 877:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check if wear leveling is used in EEPROM */ + 878:Generated_Source\PSoC4/cy_em_eeprom.c **** if(context->wearLevelingFactor > 1u) + 1695 .loc 1 878 0 + 1696 0044 3B68 ldr r3, [r7] + 1697 0046 1B69 ldr r3, [r3, #16] + 1698 0048 012B cmp r3, #1 + 1699 004a 27D9 bls .L85 + 879:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 880:Generated_Source\PSoC4/cy_em_eeprom.c **** /* The read row address should be taken from an EEPROM copy that became + 881:Generated_Source\PSoC4/cy_em_eeprom.c **** * inactive recently. This condition check handles that. + 882:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 883:Generated_Source\PSoC4/cy_em_eeprom.c **** if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) < + 1700 .loc 1 883 0 + 1701 004c BB68 ldr r3, [r7, #8] + 1702 004e 1A68 ldr r2, [r3] + 1703 0050 3B68 ldr r3, [r7] + 1704 0052 5B68 ldr r3, [r3, #4] + 1705 0054 DB01 lsls r3, r3, #7 + 1706 0056 D21A subs r2, r2, r3 + 884:Generated_Source\PSoC4/cy_em_eeprom.c **** context->userFlashStartAddr) + 1707 .loc 1 884 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 47 + + + 1708 0058 3B68 ldr r3, [r7] + 1709 005a 9B69 ldr r3, [r3, #24] + 883:Generated_Source\PSoC4/cy_em_eeprom.c **** context->userFlashStartAddr) + 1710 .loc 1 883 0 + 1711 005c 9A42 cmp r2, r3 + 1712 005e 14D2 bcs .L86 + 885:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 886:Generated_Source\PSoC4/cy_em_eeprom.c **** *rowToRdPtr = context->userFlashStartAddr + + 1713 .loc 1 886 0 + 1714 0060 3B68 ldr r3, [r7] + 1715 0062 9A69 ldr r2, [r3, #24] + 887:Generated_Source\PSoC4/cy_em_eeprom.c **** (context->numberOfRows * (context->wearLevelingFactor - 1u) * + 1716 .loc 1 887 0 + 1717 0064 3B68 ldr r3, [r7] + 1718 0066 5968 ldr r1, [r3, #4] + 1719 0068 3B68 ldr r3, [r7] + 1720 006a 1B69 ldr r3, [r3, #16] + 1721 006c 0F48 ldr r0, .L89 + 1722 006e 8446 mov ip, r0 + 1723 0070 6344 add r3, r3, ip + 1724 0072 4B43 muls r3, r1 + 1725 0074 DB01 lsls r3, r3, #7 + 886:Generated_Source\PSoC4/cy_em_eeprom.c **** (context->numberOfRows * (context->wearLevelingFactor - 1u) * + 1726 .loc 1 886 0 + 1727 0076 D218 adds r2, r2, r3 + 888:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr + 1728 .loc 1 888 0 + 1729 0078 BB68 ldr r3, [r7, #8] + 1730 007a 1968 ldr r1, [r3] + 1731 007c 3B68 ldr r3, [r7] + 1732 007e 9B69 ldr r3, [r3, #24] + 1733 0080 CB1A subs r3, r1, r3 + 1734 0082 D218 adds r2, r2, r3 + 886:Generated_Source\PSoC4/cy_em_eeprom.c **** (context->numberOfRows * (context->wearLevelingFactor - 1u) * + 1735 .loc 1 886 0 + 1736 0084 7B68 ldr r3, [r7, #4] + 1737 0086 1A60 str r2, [r3] + 889:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 890:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 891:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 892:Generated_Source\PSoC4/cy_em_eeprom.c **** *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW) + 893:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 894:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 895:Generated_Source\PSoC4/cy_em_eeprom.c **** else + 896:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 897:Generated_Source\PSoC4/cy_em_eeprom.c **** /* If no wear leveling, always read from the same flash row that + 898:Generated_Source\PSoC4/cy_em_eeprom.c **** * should be written. + 899:Generated_Source\PSoC4/cy_em_eeprom.c **** */ + 900:Generated_Source\PSoC4/cy_em_eeprom.c **** *rowToRdPtr = *rowToWrPtr; + 901:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 902:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 903:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1738 .loc 1 903 0 + 1739 0088 0CE0 b .L88 + 1740 .L86: + 892:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1741 .loc 1 892 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 48 + + + 1742 008a BB68 ldr r3, [r7, #8] + 1743 008c 1A68 ldr r2, [r3] + 1744 008e 3B68 ldr r3, [r7] + 1745 0090 5B68 ldr r3, [r3, #4] + 1746 0092 DB01 lsls r3, r3, #7 + 1747 0094 D21A subs r2, r2, r3 + 1748 0096 7B68 ldr r3, [r7, #4] + 1749 0098 1A60 str r2, [r3] + 1750 .loc 1 903 0 + 1751 009a 03E0 b .L88 + 1752 .L85: + 900:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1753 .loc 1 900 0 + 1754 009c BB68 ldr r3, [r7, #8] + 1755 009e 1A68 ldr r2, [r3] + 1756 00a0 7B68 ldr r3, [r7, #4] + 1757 00a2 1A60 str r2, [r3] + 1758 .L88: + 1759 .loc 1 903 0 + 1760 00a4 C046 nop + 1761 00a6 BD46 mov sp, r7 + 1762 00a8 04B0 add sp, sp, #16 + 1763 @ sp needed + 1764 00aa 80BD pop {r7, pc} + 1765 .L90: + 1766 .align 2 + 1767 .L89: + 1768 00ac FFFFFF01 .word 33554431 + 1769 .cfi_endproc + 1770 .LFE7: + 1771 .size GetNextRowToWrite, .-GetNextRowToWrite + 1772 .section .text.CalcChecksum,"ax",%progbits + 1773 .align 2 + 1774 .code 16 + 1775 .thumb_func + 1776 .type CalcChecksum, %function + 1777 CalcChecksum: + 1778 .LFB8: + 904:Generated_Source\PSoC4/cy_em_eeprom.c **** + 905:Generated_Source\PSoC4/cy_em_eeprom.c **** + 906:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 907:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: CalcChecksum + 908:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 909:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 910:Generated_Source\PSoC4/cy_em_eeprom.c **** * Implements CRC-8 that is used in checksum calculation for the redundant copy + 911:Generated_Source\PSoC4/cy_em_eeprom.c **** * algorithm. + 912:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 913:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowData + 914:Generated_Source\PSoC4/cy_em_eeprom.c **** * The row data to be used to calculate the checksum. + 915:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 916:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param len + 917:Generated_Source\PSoC4/cy_em_eeprom.c **** * The length of rowData. + 918:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 919:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 920:Generated_Source\PSoC4/cy_em_eeprom.c **** * The calculated value of CRC-8. + 921:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 922:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 49 + + + 923:Generated_Source\PSoC4/cy_em_eeprom.c **** static uint8 CalcChecksum(uint8 rowData[], uint32 len) + 924:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1779 .loc 1 924 0 + 1780 .cfi_startproc + 1781 @ args = 0, pretend = 0, frame = 16 + 1782 @ frame_needed = 1, uses_anonymous_args = 0 + 1783 0000 80B5 push {r7, lr} + 1784 .cfi_def_cfa_offset 8 + 1785 .cfi_offset 7, -8 + 1786 .cfi_offset 14, -4 + 1787 0002 84B0 sub sp, sp, #16 + 1788 .cfi_def_cfa_offset 24 + 1789 0004 00AF add r7, sp, #0 + 1790 .cfi_def_cfa_register 7 + 1791 0006 7860 str r0, [r7, #4] + 1792 0008 3960 str r1, [r7] + 925:Generated_Source\PSoC4/cy_em_eeprom.c **** uint8 crc = CY_EM_EEPROM_CRC8_SEED; + 1793 .loc 1 925 0 + 1794 000a 0F23 movs r3, #15 + 1795 000c FB18 adds r3, r7, r3 + 1796 000e FF22 movs r2, #255 + 1797 0010 1A70 strb r2, [r3] + 926:Generated_Source\PSoC4/cy_em_eeprom.c **** uint8 i; + 927:Generated_Source\PSoC4/cy_em_eeprom.c **** uint16 cnt = 0u; + 1798 .loc 1 927 0 + 1799 0012 0C23 movs r3, #12 + 1800 0014 FB18 adds r3, r7, r3 + 1801 0016 0022 movs r2, #0 + 1802 0018 1A80 strh r2, [r3] + 928:Generated_Source\PSoC4/cy_em_eeprom.c **** + 929:Generated_Source\PSoC4/cy_em_eeprom.c **** while(cnt != len) + 1803 .loc 1 929 0 + 1804 001a 3BE0 b .L92 + 1805 .L97: + 930:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 931:Generated_Source\PSoC4/cy_em_eeprom.c **** crc ^= rowData[cnt]; + 1806 .loc 1 931 0 + 1807 001c 0C23 movs r3, #12 + 1808 001e FB18 adds r3, r7, r3 + 1809 0020 1B88 ldrh r3, [r3] + 1810 0022 7A68 ldr r2, [r7, #4] + 1811 0024 D318 adds r3, r2, r3 + 1812 0026 1978 ldrb r1, [r3] + 1813 0028 0F23 movs r3, #15 + 1814 002a FB18 adds r3, r7, r3 + 1815 002c 0F22 movs r2, #15 + 1816 002e BA18 adds r2, r7, r2 + 1817 0030 1278 ldrb r2, [r2] + 1818 0032 4A40 eors r2, r1 + 1819 0034 1A70 strb r2, [r3] + 932:Generated_Source\PSoC4/cy_em_eeprom.c **** for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + 1820 .loc 1 932 0 + 1821 0036 0E23 movs r3, #14 + 1822 0038 FB18 adds r3, r7, r3 + 1823 003a 0022 movs r2, #0 + 1824 003c 1A70 strb r2, [r3] + 1825 003e 1DE0 b .L93 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 50 + + + 1826 .L96: + 933:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 934:Generated_Source\PSoC4/cy_em_eeprom.c **** crc = CY_EM_EEPROM_CALCULATE_CRC8(crc); + 1827 .loc 1 934 0 + 1828 0040 0F23 movs r3, #15 + 1829 0042 FB18 adds r3, r7, r3 + 1830 0044 1B78 ldrb r3, [r3] + 1831 0046 5BB2 sxtb r3, r3 + 1832 0048 002B cmp r3, #0 + 1833 004a 08DA bge .L94 + 1834 .loc 1 934 0 is_stmt 0 discriminator 1 + 1835 004c 0F23 movs r3, #15 + 1836 004e FB18 adds r3, r7, r3 + 1837 0050 1B78 ldrb r3, [r3] + 1838 0052 DB18 adds r3, r3, r3 + 1839 0054 DBB2 uxtb r3, r3 + 1840 0056 3122 movs r2, #49 + 1841 0058 5340 eors r3, r2 + 1842 005a DBB2 uxtb r3, r3 + 1843 005c 04E0 b .L95 + 1844 .L94: + 1845 .loc 1 934 0 discriminator 2 + 1846 005e 0F23 movs r3, #15 + 1847 0060 FB18 adds r3, r7, r3 + 1848 0062 1B78 ldrb r3, [r3] + 1849 0064 DB18 adds r3, r3, r3 + 1850 0066 DBB2 uxtb r3, r3 + 1851 .L95: + 1852 .loc 1 934 0 discriminator 4 + 1853 0068 0F22 movs r2, #15 + 1854 006a BA18 adds r2, r7, r2 + 1855 006c 1370 strb r3, [r2] + 932:Generated_Source\PSoC4/cy_em_eeprom.c **** for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + 1856 .loc 1 932 0 is_stmt 1 discriminator 4 + 1857 006e 0E23 movs r3, #14 + 1858 0070 FB18 adds r3, r7, r3 + 1859 0072 1A78 ldrb r2, [r3] + 1860 0074 0E23 movs r3, #14 + 1861 0076 FB18 adds r3, r7, r3 + 1862 0078 0132 adds r2, r2, #1 + 1863 007a 1A70 strb r2, [r3] + 1864 .L93: + 932:Generated_Source\PSoC4/cy_em_eeprom.c **** for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + 1865 .loc 1 932 0 is_stmt 0 discriminator 2 + 1866 007c 0E23 movs r3, #14 + 1867 007e FB18 adds r3, r7, r3 + 1868 0080 1B78 ldrb r3, [r3] + 1869 0082 072B cmp r3, #7 + 1870 0084 DCD9 bls .L96 + 935:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 936:Generated_Source\PSoC4/cy_em_eeprom.c **** cnt++; + 1871 .loc 1 936 0 is_stmt 1 + 1872 0086 0C23 movs r3, #12 + 1873 0088 FB18 adds r3, r7, r3 + 1874 008a 1A88 ldrh r2, [r3] + 1875 008c 0C23 movs r3, #12 + 1876 008e FB18 adds r3, r7, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 51 + + + 1877 0090 0132 adds r2, r2, #1 + 1878 0092 1A80 strh r2, [r3] + 1879 .L92: + 929:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1880 .loc 1 929 0 + 1881 0094 0C23 movs r3, #12 + 1882 0096 FB18 adds r3, r7, r3 + 1883 0098 1A88 ldrh r2, [r3] + 1884 009a 3B68 ldr r3, [r7] + 1885 009c 9A42 cmp r2, r3 + 1886 009e BDD1 bne .L97 + 937:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 938:Generated_Source\PSoC4/cy_em_eeprom.c **** + 939:Generated_Source\PSoC4/cy_em_eeprom.c **** return (crc); + 1887 .loc 1 939 0 + 1888 00a0 0F23 movs r3, #15 + 1889 00a2 FB18 adds r3, r7, r3 + 1890 00a4 1B78 ldrb r3, [r3] + 940:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1891 .loc 1 940 0 + 1892 00a6 1800 movs r0, r3 + 1893 00a8 BD46 mov sp, r7 + 1894 00aa 04B0 add sp, sp, #16 + 1895 @ sp needed + 1896 00ac 80BD pop {r7, pc} + 1897 .cfi_endproc + 1898 .LFE8: + 1899 .size CalcChecksum, .-CalcChecksum + 1900 .section .text.CheckRanges,"ax",%progbits + 1901 .align 2 + 1902 .code 16 + 1903 .thumb_func + 1904 .type CheckRanges, %function + 1905 CheckRanges: + 1906 .LFB9: + 941:Generated_Source\PSoC4/cy_em_eeprom.c **** + 942:Generated_Source\PSoC4/cy_em_eeprom.c **** + 943:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 944:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: CheckRanges + 945:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 946:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 947:Generated_Source\PSoC4/cy_em_eeprom.c **** * Checks if the EEPROM of the requested size can be placed in flash. + 948:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 949:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param config + 950:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. + 951:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 952:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 953:Generated_Source\PSoC4/cy_em_eeprom.c **** * error / status code. See \ref cy_en_em_eeprom_status_t. + 954:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 955:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 956:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config) + 957:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1907 .loc 1 957 0 + 1908 .cfi_startproc + 1909 @ args = 0, pretend = 0, frame = 24 + 1910 @ frame_needed = 1, uses_anonymous_args = 0 + 1911 0000 80B5 push {r7, lr} + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 52 + + + 1912 .cfi_def_cfa_offset 8 + 1913 .cfi_offset 7, -8 + 1914 .cfi_offset 14, -4 + 1915 0002 86B0 sub sp, sp, #24 + 1916 .cfi_def_cfa_offset 32 + 1917 0004 00AF add r7, sp, #0 + 1918 .cfi_def_cfa_register 7 + 1919 0006 7860 str r0, [r7, #4] + 958:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA; + 1920 .loc 1 958 0 + 1921 0008 1723 movs r3, #23 + 1922 000a FB18 adds r3, r7, r3 + 1923 000c 0322 movs r2, #3 + 1924 000e 1A70 strb r2, [r3] + 959:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 startAddr = config->userFlashStartAddr; + 1925 .loc 1 959 0 + 1926 0010 7B68 ldr r3, [r7, #4] + 1927 0012 DB68 ldr r3, [r3, #12] + 1928 0014 3B61 str r3, [r7, #16] + 960:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize, + 1929 .loc 1 960 0 + 1930 0016 7B68 ldr r3, [r7, #4] + 1931 0018 1B68 ldr r3, [r3] + 1932 001a 9A09 lsrs r2, r3, #6 + 1933 001c 7B68 ldr r3, [r7, #4] + 1934 001e 1B68 ldr r3, [r3] + 1935 0020 3F21 movs r1, #63 + 1936 0022 0B40 ands r3, r1 + 1937 0024 01D0 beq .L100 + 1938 .loc 1 960 0 is_stmt 0 discriminator 1 + 1939 0026 0123 movs r3, #1 + 1940 0028 00E0 b .L101 + 1941 .L100: + 1942 .loc 1 960 0 discriminator 2 + 1943 002a 0023 movs r3, #0 + 1944 .L101: + 1945 .loc 1 960 0 discriminator 4 + 1946 002c D218 adds r2, r2, r3 + 1947 002e 7B68 ldr r3, [r7, #4] + 1948 0030 5B68 ldr r3, [r3, #4] + 1949 0032 5343 muls r3, r2 + 1950 0034 7A68 ldr r2, [r7, #4] + 1951 0036 127A ldrb r2, [r2, #8] + 1952 0038 0132 adds r2, r2, #1 + 1953 003a 5343 muls r3, r2 + 1954 003c DA01 lsls r2, r3, #7 + 1955 003e 3B69 ldr r3, [r7, #16] + 1956 0040 D318 adds r3, r2, r3 + 1957 0042 FB60 str r3, [r7, #12] + 961:Generated_Source\PSoC4/cy_em_eeprom.c **** config->wearLevelingFactor, config->redundantCopy); + 962:Generated_Source\PSoC4/cy_em_eeprom.c **** + 963:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Range check if there is enough flash for EEPROM */ + 964:Generated_Source\PSoC4/cy_em_eeprom.c **** if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr)) + 1958 .loc 1 964 0 is_stmt 1 discriminator 4 + 1959 0044 3B69 ldr r3, [r7, #16] + 1960 0046 002B cmp r3, #0 + 1961 0048 08D0 beq .L102 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 53 + + + 1962 .loc 1 964 0 is_stmt 0 discriminator 1 + 1963 004a FA68 ldr r2, [r7, #12] + 1964 004c 8023 movs r3, #128 + 1965 004e 1B02 lsls r3, r3, #8 + 1966 0050 9A42 cmp r2, r3 + 1967 0052 03D8 bhi .L102 + 965:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 966:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; + 1968 .loc 1 966 0 is_stmt 1 + 1969 0054 1723 movs r3, #23 + 1970 0056 FB18 adds r3, r7, r3 + 1971 0058 0022 movs r2, #0 + 1972 005a 1A70 strb r2, [r3] + 1973 .L102: + 967:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 968:Generated_Source\PSoC4/cy_em_eeprom.c **** return (ret); + 1974 .loc 1 968 0 + 1975 005c 1723 movs r3, #23 + 1976 005e FB18 adds r3, r7, r3 + 1977 0060 1B78 ldrb r3, [r3] + 969:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 1978 .loc 1 969 0 + 1979 0062 1800 movs r0, r3 + 1980 0064 BD46 mov sp, r7 + 1981 0066 06B0 add sp, sp, #24 + 1982 @ sp needed + 1983 0068 80BD pop {r7, pc} + 1984 .cfi_endproc + 1985 .LFE9: + 1986 .size CheckRanges, .-CheckRanges + 1987 006a C046 .section .text.WriteRow,"ax",%progbits + 1988 .align 2 + 1989 .code 16 + 1990 .thumb_func + 1991 .type WriteRow, %function + 1992 WriteRow: + 1993 .LFB10: + 970:Generated_Source\PSoC4/cy_em_eeprom.c **** + 971:Generated_Source\PSoC4/cy_em_eeprom.c **** + 972:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* + 973:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: WriteRow + 974:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** + 975:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 976:Generated_Source\PSoC4/cy_em_eeprom.c **** * Writes one flash row starting from the specified row address. + 977:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 978:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowAdd + 979:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address of the flash row. + 980:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 981:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowData + 982:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the data to be written to the row. + 983:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 984:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context + 985:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. + 986:Generated_Source\PSoC4/cy_em_eeprom.c **** * + 987:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return + 988:Generated_Source\PSoC4/cy_em_eeprom.c **** * error / status code. See \ref cy_en_em_eeprom_status_t. + 989:Generated_Source\PSoC4/cy_em_eeprom.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 54 + + + 990:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ + 991:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, + 992:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 *rowData, + 993:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context) + 994:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 1994 .loc 1 994 0 + 1995 .cfi_startproc + 1996 @ args = 0, pretend = 0, frame = 32 + 1997 @ frame_needed = 1, uses_anonymous_args = 0 + 1998 0000 80B5 push {r7, lr} + 1999 .cfi_def_cfa_offset 8 + 2000 .cfi_offset 7, -8 + 2001 .cfi_offset 14, -4 + 2002 0002 88B0 sub sp, sp, #32 + 2003 .cfi_def_cfa_offset 40 + 2004 0004 00AF add r7, sp, #0 + 2005 .cfi_def_cfa_register 7 + 2006 0006 F860 str r0, [r7, #12] + 2007 0008 B960 str r1, [r7, #8] + 2008 000a 7A60 str r2, [r7, #4] + 995:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + 2009 .loc 1 995 0 + 2010 000c 1F23 movs r3, #31 + 2011 000e FB18 adds r3, r7, r3 + 2012 0010 0422 movs r2, #4 + 2013 0012 1A70 strb r2, [r3] + 996:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (!CY_PSOC6) + 997:Generated_Source\PSoC4/cy_em_eeprom.c **** cystatus rc; + 998:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rowId; + 999:Generated_Source\PSoC4/cy_em_eeprom.c **** #if ((CY_PSOC3) || (CY_PSOC5)) +1000:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 arrayId; +1001:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC3) */ +1002:Generated_Source\PSoC4/cy_em_eeprom.c **** +1003:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC3) +1004:Generated_Source\PSoC4/cy_em_eeprom.c **** rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK; +1005:Generated_Source\PSoC4/cy_em_eeprom.c **** context = context; /* To avoid compiler warning generation */ +1006:Generated_Source\PSoC4/cy_em_eeprom.c **** #else +1007:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)context; /* To avoid compiler warning generation */ +1008:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* ((CY_PSOC3) */ +1009:Generated_Source\PSoC4/cy_em_eeprom.c **** +1010:Generated_Source\PSoC4/cy_em_eeprom.c **** /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */ +1011:Generated_Source\PSoC4/cy_em_eeprom.c **** rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY; + 2014 .loc 1 1011 0 + 2015 0014 FB68 ldr r3, [r7, #12] + 2016 0016 DB09 lsrs r3, r3, #7 + 2017 0018 FF22 movs r2, #255 + 2018 001a 1340 ands r3, r2 + 2019 001c BB61 str r3, [r7, #24] +1012:Generated_Source\PSoC4/cy_em_eeprom.c **** +1013:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the flash row */ +1014:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC4) +1015:Generated_Source\PSoC4/cy_em_eeprom.c **** rc = CySysFlashWriteRow(rowId, (uint8 *)rowData); + 2020 .loc 1 1015 0 + 2021 001e BA68 ldr r2, [r7, #8] + 2022 0020 BB69 ldr r3, [r7, #24] + 2023 0022 1100 movs r1, r2 + 2024 0024 1800 movs r0, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 55 + + + 2025 0026 FFF7FEFF bl CySysFlashWriteRow + 2026 002a 0300 movs r3, r0 + 2027 002c 7B61 str r3, [r7, #20] +1016:Generated_Source\PSoC4/cy_em_eeprom.c **** #else +1017:Generated_Source\PSoC4/cy_em_eeprom.c **** +1018:Generated_Source\PSoC4/cy_em_eeprom.c **** #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT +1019:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)CySetTemp(); +1020:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */ +1021:Generated_Source\PSoC4/cy_em_eeprom.c **** +1022:Generated_Source\PSoC4/cy_em_eeprom.c **** arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY; +1023:Generated_Source\PSoC4/cy_em_eeprom.c **** rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData); +1024:Generated_Source\PSoC4/cy_em_eeprom.c **** +1025:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC5) +1026:Generated_Source\PSoC4/cy_em_eeprom.c **** CyFlushCache(); +1027:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC5) */ +1028:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC4) */ +1029:Generated_Source\PSoC4/cy_em_eeprom.c **** +1030:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CYRET_SUCCESS == rc) + 2028 .loc 1 1030 0 + 2029 002e 7B69 ldr r3, [r7, #20] + 2030 0030 002B cmp r3, #0 + 2031 0032 03D1 bne .L105 +1031:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1032:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; + 2032 .loc 1 1032 0 + 2033 0034 1F23 movs r3, #31 + 2034 0036 FB18 adds r3, r7, r3 + 2035 0038 0022 movs r2, #0 + 2036 003a 1A70 strb r2, [r3] + 2037 .L105: +1033:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1034:Generated_Source\PSoC4/cy_em_eeprom.c **** #else /* PSoC 6 */ +1035:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != context->blockingWrite) +1036:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1037:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Do blocking write */ +1038:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData)) +1039:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1040:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; +1041:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1042:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1043:Generated_Source\PSoC4/cy_em_eeprom.c **** else +1044:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1045:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Initiate write */ +1046:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData)) +1047:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1048:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; +1049:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_flashdrv_status_t rc; +1050:Generated_Source\PSoC4/cy_em_eeprom.c **** +1051:Generated_Source\PSoC4/cy_em_eeprom.c **** do +1052:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1053:Generated_Source\PSoC4/cy_em_eeprom.c **** CyDelay(1u); /* Wait 1ms */ +1054:Generated_Source\PSoC4/cy_em_eeprom.c **** rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */ +1055:Generated_Source\PSoC4/cy_em_eeprom.c **** countMs--; +1056:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1057:Generated_Source\PSoC4/cy_em_eeprom.c **** while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); +1058:Generated_Source\PSoC4/cy_em_eeprom.c **** +1059:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_FLASH_DRV_SUCCESS == rc) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 56 + + +1060:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1061:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; +1062:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1063:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1064:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1065:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC6) */ +1066:Generated_Source\PSoC4/cy_em_eeprom.c **** +1067:Generated_Source\PSoC4/cy_em_eeprom.c **** return (ret); + 2038 .loc 1 1067 0 + 2039 003c 1F23 movs r3, #31 + 2040 003e FB18 adds r3, r7, r3 + 2041 0040 1B78 ldrb r3, [r3] +1068:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 2042 .loc 1 1068 0 + 2043 0042 1800 movs r0, r3 + 2044 0044 BD46 mov sp, r7 + 2045 0046 08B0 add sp, sp, #32 + 2046 @ sp needed + 2047 0048 80BD pop {r7, pc} + 2048 .cfi_endproc + 2049 .LFE10: + 2050 .size WriteRow, .-WriteRow + 2051 004a C046 .section .text.EraseRow,"ax",%progbits + 2052 .align 2 + 2053 .code 16 + 2054 .thumb_func + 2055 .type EraseRow, %function + 2056 EraseRow: + 2057 .LFB11: +1069:Generated_Source\PSoC4/cy_em_eeprom.c **** +1070:Generated_Source\PSoC4/cy_em_eeprom.c **** +1071:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* +1072:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: EraseRow +1073:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** +1074:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1075:Generated_Source\PSoC4/cy_em_eeprom.c **** * Erases one flash row starting from the specified row address. If the redundant +1076:Generated_Source\PSoC4/cy_em_eeprom.c **** * copy option is enabled the corresponding row in the redundant copy will also +1077:Generated_Source\PSoC4/cy_em_eeprom.c **** * be erased. +1078:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1079:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowAdd +1080:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address of the flash row. +1081:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1082:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param ramBuffAddr +1083:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address of the RAM buffer that contains zeroed data (used only for +1084:Generated_Source\PSoC4/cy_em_eeprom.c **** * non-PSoC 6 devices). +1085:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1086:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context +1087:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +1088:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1089:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return +1090:Generated_Source\PSoC4/cy_em_eeprom.c **** * error / status code. See \ref cy_en_em_eeprom_status_t. +1091:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1092:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ +1093:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, +1094:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 ramBuffAddr, +1095:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context) +1096:Generated_Source\PSoC4/cy_em_eeprom.c **** { + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 57 + + + 2058 .loc 1 1096 0 + 2059 .cfi_startproc + 2060 @ args = 0, pretend = 0, frame = 24 + 2061 @ frame_needed = 1, uses_anonymous_args = 0 + 2062 0000 90B5 push {r4, r7, lr} + 2063 .cfi_def_cfa_offset 12 + 2064 .cfi_offset 4, -12 + 2065 .cfi_offset 7, -8 + 2066 .cfi_offset 14, -4 + 2067 0002 87B0 sub sp, sp, #28 + 2068 .cfi_def_cfa_offset 40 + 2069 0004 00AF add r7, sp, #0 + 2070 .cfi_def_cfa_register 7 + 2071 0006 F860 str r0, [r7, #12] + 2072 0008 B960 str r1, [r7, #8] + 2073 000a 7A60 str r2, [r7, #4] +1097:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 emEepromRowAddr = rowAddr; + 2074 .loc 1 1097 0 + 2075 000c FB68 ldr r3, [r7, #12] + 2076 000e 3B61 str r3, [r7, #16] +1098:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + 2077 .loc 1 1098 0 + 2078 0010 1723 movs r3, #23 + 2079 0012 FB18 adds r3, r7, r3 + 2080 0014 0422 movs r2, #4 + 2081 0016 1A70 strb r2, [r3] +1099:Generated_Source\PSoC4/cy_em_eeprom.c **** #if (CY_PSOC6) +1100:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 i = 1u; +1101:Generated_Source\PSoC4/cy_em_eeprom.c **** +1102:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)ramBuffAddr; /* To avoid compiler warning */ +1103:Generated_Source\PSoC4/cy_em_eeprom.c **** +1104:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != context->redundantCopy) +1105:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1106:Generated_Source\PSoC4/cy_em_eeprom.c **** i++; +1107:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1108:Generated_Source\PSoC4/cy_em_eeprom.c **** +1109:Generated_Source\PSoC4/cy_em_eeprom.c **** do +1110:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1111:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != context->blockingWrite) +1112:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1113:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Erase the flash row */ +1114:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr)) +1115:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1116:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; +1117:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1118:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1119:Generated_Source\PSoC4/cy_em_eeprom.c **** else +1120:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1121:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Initiate erase */ +1122:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr)) +1123:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1124:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; +1125:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_flashdrv_status_t rc; +1126:Generated_Source\PSoC4/cy_em_eeprom.c **** +1127:Generated_Source\PSoC4/cy_em_eeprom.c **** do +1128:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1129:Generated_Source\PSoC4/cy_em_eeprom.c **** CyDelay(1u); /* Wait 1ms */ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 58 + + +1130:Generated_Source\PSoC4/cy_em_eeprom.c **** rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */ +1131:Generated_Source\PSoC4/cy_em_eeprom.c **** countMs--; +1132:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1133:Generated_Source\PSoC4/cy_em_eeprom.c **** while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); +1134:Generated_Source\PSoC4/cy_em_eeprom.c **** +1135:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_FLASH_DRV_SUCCESS == rc) +1136:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1137:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; +1138:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1139:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1140:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1141:Generated_Source\PSoC4/cy_em_eeprom.c **** +1142:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS == ret) +1143:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1144:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Update the address to point to the redundant copy row */ +1145:Generated_Source\PSoC4/cy_em_eeprom.c **** emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; +1146:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1147:Generated_Source\PSoC4/cy_em_eeprom.c **** else +1148:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1149:Generated_Source\PSoC4/cy_em_eeprom.c **** break; +1150:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1151:Generated_Source\PSoC4/cy_em_eeprom.c **** i--; +1152:Generated_Source\PSoC4/cy_em_eeprom.c **** } while (0u != i); +1153:Generated_Source\PSoC4/cy_em_eeprom.c **** #else +1154:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the data to the specified flash row */ +1155:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + 2082 .loc 1 1155 0 + 2083 0018 B968 ldr r1, [r7, #8] + 2084 001a 1723 movs r3, #23 + 2085 001c FC18 adds r4, r7, r3 + 2086 001e 7A68 ldr r2, [r7, #4] + 2087 0020 3B69 ldr r3, [r7, #16] + 2088 0022 1800 movs r0, r3 + 2089 0024 FFF7FEFF bl WriteRow + 2090 0028 0300 movs r3, r0 + 2091 002a 2370 strb r3, [r4] +1156:Generated_Source\PSoC4/cy_em_eeprom.c **** +1157:Generated_Source\PSoC4/cy_em_eeprom.c **** if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy)) + 2092 .loc 1 1157 0 + 2093 002c 1723 movs r3, #23 + 2094 002e FB18 adds r3, r7, r3 + 2095 0030 1B78 ldrb r3, [r3] + 2096 0032 002B cmp r3, #0 + 2097 0034 15D1 bne .L108 + 2098 .loc 1 1157 0 is_stmt 0 discriminator 1 + 2099 0036 7B68 ldr r3, [r7, #4] + 2100 0038 1B7D ldrb r3, [r3, #20] + 2101 003a 002B cmp r3, #0 + 2102 003c 11D0 beq .L108 +1158:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1159:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Update the address to point to the redundant copy row */ +1160:Generated_Source\PSoC4/cy_em_eeprom.c **** emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + 2103 .loc 1 1160 0 is_stmt 1 + 2104 003e 7B68 ldr r3, [r7, #4] + 2105 0040 9B69 ldr r3, [r3, #24] + 2106 0042 3A69 ldr r2, [r7, #16] + 2107 0044 D21A subs r2, r2, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 59 + + + 2108 0046 7B68 ldr r3, [r7, #4] + 2109 0048 1B68 ldr r3, [r3] + 2110 004a D318 adds r3, r2, r3 + 2111 004c 3B61 str r3, [r7, #16] +1161:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + 2112 .loc 1 1161 0 + 2113 004e B968 ldr r1, [r7, #8] + 2114 0050 1723 movs r3, #23 + 2115 0052 FC18 adds r4, r7, r3 + 2116 0054 7A68 ldr r2, [r7, #4] + 2117 0056 3B69 ldr r3, [r7, #16] + 2118 0058 1800 movs r0, r3 + 2119 005a FFF7FEFF bl WriteRow + 2120 005e 0300 movs r3, r0 + 2121 0060 2370 strb r3, [r4] + 2122 .L108: +1162:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1163:Generated_Source\PSoC4/cy_em_eeprom.c **** +1164:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS == ret) + 2123 .loc 1 1164 0 + 2124 0062 1723 movs r3, #23 + 2125 0064 FB18 adds r3, r7, r3 + 2126 0066 1B78 ldrb r3, [r3] + 2127 0068 002B cmp r3, #0 + 2128 006a 02D1 bne .L109 +1165:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1166:Generated_Source\PSoC4/cy_em_eeprom.c **** context->lastWrRowAddr = rowAddr; + 2129 .loc 1 1166 0 + 2130 006c 7B68 ldr r3, [r7, #4] + 2131 006e FA68 ldr r2, [r7, #12] + 2132 0070 9A60 str r2, [r3, #8] + 2133 .L109: +1167:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1168:Generated_Source\PSoC4/cy_em_eeprom.c **** #endif /* (CY_PSOC6) */ +1169:Generated_Source\PSoC4/cy_em_eeprom.c **** +1170:Generated_Source\PSoC4/cy_em_eeprom.c **** return(ret); + 2134 .loc 1 1170 0 + 2135 0072 1723 movs r3, #23 + 2136 0074 FB18 adds r3, r7, r3 + 2137 0076 1B78 ldrb r3, [r3] +1171:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 2138 .loc 1 1171 0 + 2139 0078 1800 movs r0, r3 + 2140 007a BD46 mov sp, r7 + 2141 007c 07B0 add sp, sp, #28 + 2142 @ sp needed + 2143 007e 90BD pop {r4, r7, pc} + 2144 .cfi_endproc + 2145 .LFE11: + 2146 .size EraseRow, .-EraseRow + 2147 .section .text.CheckCrcAndCopy,"ax",%progbits + 2148 .align 2 + 2149 .code 16 + 2150 .thumb_func + 2151 .type CheckCrcAndCopy, %function + 2152 CheckCrcAndCopy: + 2153 .LFB12: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 60 + + +1172:Generated_Source\PSoC4/cy_em_eeprom.c **** +1173:Generated_Source\PSoC4/cy_em_eeprom.c **** +1174:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* +1175:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: CheckCrcAndCopy +1176:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** +1177:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1178:Generated_Source\PSoC4/cy_em_eeprom.c **** * Checks the checksum of the specific row in EEPROM. If the CRC matches - copies +1179:Generated_Source\PSoC4/cy_em_eeprom.c **** * the data to the "datAddr" from EEPROM. f the CRC does not match checks the +1180:Generated_Source\PSoC4/cy_em_eeprom.c **** * CRC of the corresponding row in the EEPROM's redundant copy. If the CRC +1181:Generated_Source\PSoC4/cy_em_eeprom.c **** * matches - copies the data to the "datAddr" from EEPROM redundant copy. If the +1182:Generated_Source\PSoC4/cy_em_eeprom.c **** * CRC of the redundant copy does not match - returns bad checksum. +1183:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1184:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param startAddr +1185:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address that points to the start of the specified row. +1186:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1187:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param datAddr +1188:Generated_Source\PSoC4/cy_em_eeprom.c **** * The start address of where the row data will be copied if the CRC check +1189:Generated_Source\PSoC4/cy_em_eeprom.c **** * will succeed. +1190:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1191:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowOffset +1192:Generated_Source\PSoC4/cy_em_eeprom.c **** * The offset in the row from which the data should be copied. +1193:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1194:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param numBytes +1195:Generated_Source\PSoC4/cy_em_eeprom.c **** * The number of bytes to be copied. +1196:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1197:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context +1198:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +1199:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1200:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return +1201:Generated_Source\PSoC4/cy_em_eeprom.c **** * error / status code. See \ref cy_en_em_eeprom_status_t. +1202:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1203:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note +1204:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function uses a buffer of the flash row size to perform read +1205:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation. For the size of the row refer to the specific PSoC device +1206:Generated_Source\PSoC4/cy_em_eeprom.c **** * datasheet. +1207:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1208:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ +1209:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, +1210:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 dstAddr, +1211:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rowOffset, +1212:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 numBytes, +1213:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_stc_eeprom_context_t * context) +1214:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 2154 .loc 1 1214 0 + 2155 .cfi_startproc + 2156 @ args = 4, pretend = 0, frame = 152 + 2157 @ frame_needed = 1, uses_anonymous_args = 0 + 2158 0000 90B5 push {r4, r7, lr} + 2159 .cfi_def_cfa_offset 12 + 2160 .cfi_offset 4, -12 + 2161 .cfi_offset 7, -8 + 2162 .cfi_offset 14, -4 + 2163 0002 A7B0 sub sp, sp, #156 + 2164 .cfi_def_cfa_offset 168 + 2165 0004 00AF add r7, sp, #0 + 2166 .cfi_def_cfa_register 7 + 2167 0006 F860 str r0, [r7, #12] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 61 + + + 2168 0008 B960 str r1, [r7, #8] + 2169 000a 7A60 str r2, [r7, #4] + 2170 000c 3B60 str r3, [r7] +1215:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret; +1216:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; +1217:Generated_Source\PSoC4/cy_em_eeprom.c **** +1218:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate the row address in the EEPROM's redundant copy */ +1219:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr; + 2171 .loc 1 1219 0 + 2172 000e A823 movs r3, #168 + 2173 0010 FB18 adds r3, r7, r3 + 2174 0012 1B68 ldr r3, [r3] + 2175 0014 9B69 ldr r3, [r3, #24] + 2176 0016 FA68 ldr r2, [r7, #12] + 2177 0018 D21A subs r2, r2, r3 + 2178 001a A823 movs r3, #168 + 2179 001c FB18 adds r3, r7, r3 + 2180 001e 1B68 ldr r3, [r3] + 2181 0020 1B68 ldr r3, [r3] + 2182 0022 D318 adds r3, r2, r3 + 2183 0024 9022 movs r2, #144 + 2184 0026 BA18 adds r2, r7, r2 + 2185 0028 1360 str r3, [r2] +1220:Generated_Source\PSoC4/cy_em_eeprom.c **** +1221:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check the row data CRC in the EEPROM */ +1222:Generated_Source\PSoC4/cy_em_eeprom.c **** if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + 2186 .loc 1 1222 0 + 2187 002a FB68 ldr r3, [r7, #12] + 2188 002c 3C33 adds r3, r3, #60 + 2189 002e 1C68 ldr r4, [r3] +1223:Generated_Source\PSoC4/cy_em_eeprom.c **** ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + 2190 .loc 1 1223 0 + 2191 0030 FB68 ldr r3, [r7, #12] + 2192 0032 4033 adds r3, r3, #64 + 2193 0034 4021 movs r1, #64 + 2194 0036 1800 movs r0, r3 + 2195 0038 FFF7FEFF bl CalcChecksum + 2196 003c 0300 movs r3, r0 +1222:Generated_Source\PSoC4/cy_em_eeprom.c **** ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + 2197 .loc 1 1222 0 + 2198 003e 9C42 cmp r4, r3 + 2199 0040 0DD1 bne .L112 +1224:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_EEPROM_DATA_LEN))) +1225:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1226:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes); + 2200 .loc 1 1226 0 + 2201 0042 B868 ldr r0, [r7, #8] + 2202 0044 FA68 ldr r2, [r7, #12] + 2203 0046 7B68 ldr r3, [r7, #4] + 2204 0048 D318 adds r3, r2, r3 + 2205 004a 1900 movs r1, r3 + 2206 004c 3B68 ldr r3, [r7] + 2207 004e 1A00 movs r2, r3 + 2208 0050 FFF7FEFF bl memcpy +1227:Generated_Source\PSoC4/cy_em_eeprom.c **** +1228:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_SUCCESS; + 2209 .loc 1 1228 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 62 + + + 2210 0054 9723 movs r3, #151 + 2211 0056 FB18 adds r3, r7, r3 + 2212 0058 0022 movs r2, #0 + 2213 005a 1A70 strb r2, [r3] + 2214 005c 39E0 b .L113 + 2215 .L112: +1229:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1230:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Check the row data CRC in the EEPROM's redundant copy */ +1231:Generated_Source\PSoC4/cy_em_eeprom.c **** else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + 2216 .loc 1 1231 0 + 2217 005e 9023 movs r3, #144 + 2218 0060 FB18 adds r3, r7, r3 + 2219 0062 1B68 ldr r3, [r3] + 2220 0064 3C33 adds r3, r3, #60 + 2221 0066 1C68 ldr r4, [r3] +1232:Generated_Source\PSoC4/cy_em_eeprom.c **** ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + 2222 .loc 1 1232 0 + 2223 0068 9023 movs r3, #144 + 2224 006a FB18 adds r3, r7, r3 + 2225 006c 1B68 ldr r3, [r3] + 2226 006e 4033 adds r3, r3, #64 + 2227 0070 4021 movs r1, #64 + 2228 0072 1800 movs r0, r3 + 2229 0074 FFF7FEFF bl CalcChecksum + 2230 0078 0300 movs r3, r0 +1231:Generated_Source\PSoC4/cy_em_eeprom.c **** ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + 2231 .loc 1 1231 0 + 2232 007a 9C42 cmp r4, r3 + 2233 007c 25D1 bne .L114 +1233:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_EEPROM_DATA_LEN))) +1234:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1235:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW) +1236:Generated_Source\PSoC4/cy_em_eeprom.c **** * flash exception. The RWW occurs while trying to write and read the data from +1237:Generated_Source\PSoC4/cy_em_eeprom.c **** * same flash macro. +1238:Generated_Source\PSoC4/cy_em_eeprom.c **** */ +1239:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ + 2234 .loc 1 1239 0 + 2235 007e 9023 movs r3, #144 + 2236 0080 FB18 adds r3, r7, r3 + 2237 0082 1968 ldr r1, [r3] + 2238 0084 1023 movs r3, #16 + 2239 0086 FB18 adds r3, r7, r3 + 2240 0088 8022 movs r2, #128 + 2241 008a 1800 movs r0, r3 + 2242 008c FFF7FEFF bl memcpy +1240:Generated_Source\PSoC4/cy_em_eeprom.c **** +1241:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Restore bad row data from the RAM buffer */ +1242:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context); + 2243 .loc 1 1242 0 + 2244 0090 9723 movs r3, #151 + 2245 0092 FC18 adds r4, r7, r3 + 2246 0094 A823 movs r3, #168 + 2247 0096 FB18 adds r3, r7, r3 + 2248 0098 1A68 ldr r2, [r3] + 2249 009a 1023 movs r3, #16 + 2250 009c F918 adds r1, r7, r3 + 2251 009e FB68 ldr r3, [r7, #12] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 63 + + + 2252 00a0 1800 movs r0, r3 + 2253 00a2 FFF7FEFF bl WriteRow + 2254 00a6 0300 movs r3, r0 + 2255 00a8 2370 strb r3, [r4] +1243:Generated_Source\PSoC4/cy_em_eeprom.c **** +1244:Generated_Source\PSoC4/cy_em_eeprom.c **** if(CY_EM_EEPROM_SUCCESS == ret) + 2256 .loc 1 1244 0 + 2257 00aa 9723 movs r3, #151 + 2258 00ac FB18 adds r3, r7, r3 + 2259 00ae 1B78 ldrb r3, [r3] + 2260 00b0 002B cmp r3, #0 + 2261 00b2 0ED1 bne .L113 +1245:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1246:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes); + 2262 .loc 1 1246 0 + 2263 00b4 B868 ldr r0, [r7, #8] + 2264 00b6 7B68 ldr r3, [r7, #4] + 2265 00b8 9B00 lsls r3, r3, #2 + 2266 00ba 1022 movs r2, #16 + 2267 00bc BA18 adds r2, r7, r2 + 2268 00be D318 adds r3, r2, r3 + 2269 00c0 3A68 ldr r2, [r7] + 2270 00c2 1900 movs r1, r3 + 2271 00c4 FFF7FEFF bl memcpy + 2272 00c8 03E0 b .L113 + 2273 .L114: +1247:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1248:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1249:Generated_Source\PSoC4/cy_em_eeprom.c **** else +1250:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1251:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = CY_EM_EEPROM_BAD_CHECKSUM; + 2274 .loc 1 1251 0 + 2275 00ca 9723 movs r3, #151 + 2276 00cc FB18 adds r3, r7, r3 + 2277 00ce 0222 movs r2, #2 + 2278 00d0 1A70 strb r2, [r3] + 2279 .L113: +1252:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1253:Generated_Source\PSoC4/cy_em_eeprom.c **** +1254:Generated_Source\PSoC4/cy_em_eeprom.c **** return(ret); + 2280 .loc 1 1254 0 + 2281 00d2 9723 movs r3, #151 + 2282 00d4 FB18 adds r3, r7, r3 + 2283 00d6 1B78 ldrb r3, [r3] +1255:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 2284 .loc 1 1255 0 + 2285 00d8 1800 movs r0, r3 + 2286 00da BD46 mov sp, r7 + 2287 00dc 27B0 add sp, sp, #156 + 2288 @ sp needed + 2289 00de 90BD pop {r4, r7, pc} + 2290 .cfi_endproc + 2291 .LFE12: + 2292 .size CheckCrcAndCopy, .-CheckCrcAndCopy + 2293 .section .text.GetAddresses,"ax",%progbits + 2294 .align 2 + 2295 .code 16 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 64 + + + 2296 .thumb_func + 2297 .type GetAddresses, %function + 2298 GetAddresses: + 2299 .LFB13: +1256:Generated_Source\PSoC4/cy_em_eeprom.c **** +1257:Generated_Source\PSoC4/cy_em_eeprom.c **** +1258:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* +1259:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: GetAddresses +1260:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** +1261:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1262:Generated_Source\PSoC4/cy_em_eeprom.c **** * Calculates the start and end address of the row's EEPROM data to be updated. +1263:Generated_Source\PSoC4/cy_em_eeprom.c **** * The start and end are not absolute addresses but a relative addresses in a +1264:Generated_Source\PSoC4/cy_em_eeprom.c **** * flash row. +1265:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1266:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param startAddr +1267:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer the address where the EEPROM data start address will be returned. +1268:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1269:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param endAddr +1270:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer the address where the EEPROM data end address will be returned. +1271:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1272:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param offset +1273:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer the address where the calculated offset of the EEPROM header data +1274:Generated_Source\PSoC4/cy_em_eeprom.c **** * will be returned. +1275:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1276:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param rowNum +1277:Generated_Source\PSoC4/cy_em_eeprom.c **** * The row number that is about to be written. +1278:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1279:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param addr +1280:Generated_Source\PSoC4/cy_em_eeprom.c **** * The address of the EEPROM header data in the currently analyzed row that may +1281:Generated_Source\PSoC4/cy_em_eeprom.c **** * concern to the row about to be written. +1282:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1283:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param len +1284:Generated_Source\PSoC4/cy_em_eeprom.c **** * The length of the EEPROM header data in the currently analyzed row that may +1285:Generated_Source\PSoC4/cy_em_eeprom.c **** * concern to the row about to be written. +1286:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1287:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return +1288:Generated_Source\PSoC4/cy_em_eeprom.c **** * Zero indicates that the currently analyzed row has the data to be written to +1289:Generated_Source\PSoC4/cy_em_eeprom.c **** * the active EEPROM row data locations. Non zero value indicates that there is +1290:Generated_Source\PSoC4/cy_em_eeprom.c **** * no data to be written +1291:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1292:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ +1293:Generated_Source\PSoC4/cy_em_eeprom.c **** static uint32 GetAddresses(uint32 *startAddr, +1294:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 *endAddr, +1295:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 *offset, +1296:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rowNum, +1297:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 addr, +1298:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 len) +1299:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 2300 .loc 1 1299 0 + 2301 .cfi_startproc + 2302 @ args = 8, pretend = 0, frame = 24 + 2303 @ frame_needed = 1, uses_anonymous_args = 0 + 2304 0000 80B5 push {r7, lr} + 2305 .cfi_def_cfa_offset 8 + 2306 .cfi_offset 7, -8 + 2307 .cfi_offset 14, -4 + 2308 0002 86B0 sub sp, sp, #24 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 65 + + + 2309 .cfi_def_cfa_offset 32 + 2310 0004 00AF add r7, sp, #0 + 2311 .cfi_def_cfa_register 7 + 2312 0006 F860 str r0, [r7, #12] + 2313 0008 B960 str r1, [r7, #8] + 2314 000a 7A60 str r2, [r7, #4] + 2315 000c 3B60 str r3, [r7] +1300:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 skip = 0u; + 2316 .loc 1 1300 0 + 2317 000e 0023 movs r3, #0 + 2318 0010 7B61 str r3, [r7, #20] +1301:Generated_Source\PSoC4/cy_em_eeprom.c **** +1302:Generated_Source\PSoC4/cy_em_eeprom.c **** *offset =0u; + 2319 .loc 1 1302 0 + 2320 0012 7B68 ldr r3, [r7, #4] + 2321 0014 0022 movs r2, #0 + 2322 0016 1A60 str r2, [r3] +1303:Generated_Source\PSoC4/cy_em_eeprom.c **** +1304:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum)) + 2323 .loc 1 1304 0 + 2324 0018 3B68 ldr r3, [r7] + 2325 001a 9A01 lsls r2, r3, #6 + 2326 001c 3B6A ldr r3, [r7, #32] + 2327 001e 9A42 cmp r2, r3 + 2328 0020 08D8 bhi .L118 + 2329 .loc 1 1304 0 is_stmt 0 discriminator 1 + 2330 0022 3B68 ldr r3, [r7] + 2331 0024 0133 adds r3, r3, #1 + 2332 0026 9B01 lsls r3, r3, #6 + 2333 0028 5A1E subs r2, r3, #1 + 2334 002a 3B6A ldr r3, [r7, #32] + 2335 002c 9A42 cmp r2, r3 + 2336 002e 01D3 bcc .L118 + 2337 .loc 1 1304 0 discriminator 3 + 2338 0030 0123 movs r3, #1 + 2339 0032 00E0 b .L119 + 2340 .L118: + 2341 .loc 1 1304 0 discriminator 4 + 2342 0034 0023 movs r3, #0 + 2343 .L119: + 2344 .loc 1 1304 0 discriminator 6 + 2345 0036 002B cmp r3, #0 + 2346 0038 26D0 beq .L120 +1305:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1306:Generated_Source\PSoC4/cy_em_eeprom.c **** *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN); + 2347 .loc 1 1306 0 is_stmt 1 + 2348 003a 3B6A ldr r3, [r7, #32] + 2349 003c 3F22 movs r2, #63 + 2350 003e 1340 ands r3, r2 + 2351 0040 4033 adds r3, r3, #64 + 2352 0042 1A00 movs r2, r3 + 2353 0044 FB68 ldr r3, [r7, #12] + 2354 0046 1A60 str r2, [r3] +1307:Generated_Source\PSoC4/cy_em_eeprom.c **** +1308:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + 2355 .loc 1 1308 0 + 2356 0048 3A6A ldr r2, [r7, #32] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 66 + + + 2357 004a 7B6A ldr r3, [r7, #36] + 2358 004c D218 adds r2, r2, r3 + 2359 004e 3B68 ldr r3, [r7] + 2360 0050 9B01 lsls r3, r3, #6 + 2361 0052 9A42 cmp r2, r3 + 2362 0054 0AD3 bcc .L121 + 2363 .loc 1 1308 0 is_stmt 0 discriminator 1 + 2364 0056 3A6A ldr r2, [r7, #32] + 2365 0058 7B6A ldr r3, [r7, #36] + 2366 005a D218 adds r2, r2, r3 + 2367 005c 3B68 ldr r3, [r7] + 2368 005e 0133 adds r3, r3, #1 + 2369 0060 9B01 lsls r3, r3, #6 + 2370 0062 013B subs r3, r3, #1 + 2371 0064 9A42 cmp r2, r3 + 2372 0066 01D8 bhi .L121 + 2373 .loc 1 1308 0 discriminator 3 + 2374 0068 0123 movs r3, #1 + 2375 006a 00E0 b .L122 + 2376 .L121: + 2377 .loc 1 1308 0 discriminator 4 + 2378 006c 0023 movs r3, #0 + 2379 .L122: + 2380 .loc 1 1308 0 discriminator 6 + 2381 006e 002B cmp r3, #0 + 2382 0070 06D0 beq .L123 +1309:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1310:Generated_Source\PSoC4/cy_em_eeprom.c **** *endAddr = *startAddr + len; + 2383 .loc 1 1310 0 is_stmt 1 + 2384 0072 FB68 ldr r3, [r7, #12] + 2385 0074 1A68 ldr r2, [r3] + 2386 0076 7B6A ldr r3, [r7, #36] + 2387 0078 D218 adds r2, r2, r3 + 2388 007a BB68 ldr r3, [r7, #8] + 2389 007c 1A60 str r2, [r3] + 2390 007e 35E0 b .L125 + 2391 .L123: +1311:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1312:Generated_Source\PSoC4/cy_em_eeprom.c **** else +1313:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1314:Generated_Source\PSoC4/cy_em_eeprom.c **** *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW; + 2392 .loc 1 1314 0 + 2393 0080 BB68 ldr r3, [r7, #8] + 2394 0082 8022 movs r2, #128 + 2395 0084 1A60 str r2, [r3] + 2396 0086 31E0 b .L125 + 2397 .L120: +1315:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1316:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1317:Generated_Source\PSoC4/cy_em_eeprom.c **** else +1318:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1319:Generated_Source\PSoC4/cy_em_eeprom.c **** +1320:Generated_Source\PSoC4/cy_em_eeprom.c **** if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + 2398 .loc 1 1320 0 + 2399 0088 3A6A ldr r2, [r7, #32] + 2400 008a 7B6A ldr r3, [r7, #36] + 2401 008c D218 adds r2, r2, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 67 + + + 2402 008e 3B68 ldr r3, [r7] + 2403 0090 9B01 lsls r3, r3, #6 + 2404 0092 9A42 cmp r2, r3 + 2405 0094 0AD3 bcc .L126 + 2406 .loc 1 1320 0 is_stmt 0 discriminator 1 + 2407 0096 3A6A ldr r2, [r7, #32] + 2408 0098 7B6A ldr r3, [r7, #36] + 2409 009a D218 adds r2, r2, r3 + 2410 009c 3B68 ldr r3, [r7] + 2411 009e 0133 adds r3, r3, #1 + 2412 00a0 9B01 lsls r3, r3, #6 + 2413 00a2 013B subs r3, r3, #1 + 2414 00a4 9A42 cmp r2, r3 + 2415 00a6 01D8 bhi .L126 + 2416 .loc 1 1320 0 discriminator 3 + 2417 00a8 0123 movs r3, #1 + 2418 00aa 00E0 b .L127 + 2419 .L126: + 2420 .loc 1 1320 0 discriminator 4 + 2421 00ac 0023 movs r3, #0 + 2422 .L127: + 2423 .loc 1 1320 0 discriminator 6 + 2424 00ae 002B cmp r3, #0 + 2425 00b0 19D0 beq .L128 +1321:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1322:Generated_Source\PSoC4/cy_em_eeprom.c **** *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN; + 2426 .loc 1 1322 0 is_stmt 1 + 2427 00b2 FB68 ldr r3, [r7, #12] + 2428 00b4 4022 movs r2, #64 + 2429 00b6 1A60 str r2, [r3] +1323:Generated_Source\PSoC4/cy_em_eeprom.c **** *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN)); + 2430 .loc 1 1323 0 + 2431 00b8 FB68 ldr r3, [r7, #12] + 2432 00ba 1A68 ldr r2, [r3] + 2433 00bc 7B6A ldr r3, [r7, #36] + 2434 00be D218 adds r2, r2, r3 + 2435 00c0 3B6A ldr r3, [r7, #32] + 2436 00c2 3F21 movs r1, #63 + 2437 00c4 1940 ands r1, r3 + 2438 00c6 FB68 ldr r3, [r7, #12] + 2439 00c8 1B68 ldr r3, [r3] + 2440 00ca CB1A subs r3, r1, r3 + 2441 00cc D218 adds r2, r2, r3 + 2442 00ce BB68 ldr r3, [r7, #8] + 2443 00d0 1A60 str r2, [r3] +1324:Generated_Source\PSoC4/cy_em_eeprom.c **** *offset = len - (*endAddr - *startAddr); + 2444 .loc 1 1324 0 + 2445 00d2 FB68 ldr r3, [r7, #12] + 2446 00d4 1A68 ldr r2, [r3] + 2447 00d6 BB68 ldr r3, [r7, #8] + 2448 00d8 1B68 ldr r3, [r3] + 2449 00da D21A subs r2, r2, r3 + 2450 00dc 7B6A ldr r3, [r7, #36] + 2451 00de D218 adds r2, r2, r3 + 2452 00e0 7B68 ldr r3, [r7, #4] + 2453 00e2 1A60 str r2, [r3] + 2454 00e4 02E0 b .L125 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 68 + + + 2455 .L128: +1325:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1326:Generated_Source\PSoC4/cy_em_eeprom.c **** else +1327:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1328:Generated_Source\PSoC4/cy_em_eeprom.c **** skip++; + 2456 .loc 1 1328 0 + 2457 00e6 7B69 ldr r3, [r7, #20] + 2458 00e8 0133 adds r3, r3, #1 + 2459 00ea 7B61 str r3, [r7, #20] + 2460 .L125: +1329:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1330:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1331:Generated_Source\PSoC4/cy_em_eeprom.c **** +1332:Generated_Source\PSoC4/cy_em_eeprom.c **** return (skip); + 2461 .loc 1 1332 0 + 2462 00ec 7B69 ldr r3, [r7, #20] +1333:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 2463 .loc 1 1333 0 + 2464 00ee 1800 movs r0, r3 + 2465 00f0 BD46 mov sp, r7 + 2466 00f2 06B0 add sp, sp, #24 + 2467 @ sp needed + 2468 00f4 80BD pop {r7, pc} + 2469 .cfi_endproc + 2470 .LFE13: + 2471 .size GetAddresses, .-GetAddresses + 2472 00f6 C046 .section .text.FillChecksum,"ax",%progbits + 2473 .align 2 + 2474 .code 16 + 2475 .thumb_func + 2476 .type FillChecksum, %function + 2477 FillChecksum: + 2478 .LFB14: +1334:Generated_Source\PSoC4/cy_em_eeprom.c **** +1335:Generated_Source\PSoC4/cy_em_eeprom.c **** +1336:Generated_Source\PSoC4/cy_em_eeprom.c **** /******************************************************************************* +1337:Generated_Source\PSoC4/cy_em_eeprom.c **** * Function Name: FillChecksum +1338:Generated_Source\PSoC4/cy_em_eeprom.c **** ****************************************************************************//** +1339:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1340:Generated_Source\PSoC4/cy_em_eeprom.c **** * Performs calculation of the checksum on each row in the Em_EEPROM and fills +1341:Generated_Source\PSoC4/cy_em_eeprom.c **** * the Em_EEPROM headers checksum field with the calculated checksums. +1342:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1343:Generated_Source\PSoC4/cy_em_eeprom.c **** * \param context +1344:Generated_Source\PSoC4/cy_em_eeprom.c **** * The pointer to the EEPROM context structure. +1345:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1346:Generated_Source\PSoC4/cy_em_eeprom.c **** * \return +1347:Generated_Source\PSoC4/cy_em_eeprom.c **** * error / status code. See \ref cy_en_em_eeprom_status_t. +1348:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1349:Generated_Source\PSoC4/cy_em_eeprom.c **** * \theory +1350:Generated_Source\PSoC4/cy_em_eeprom.c **** * In case if redundant copy option is used the Em_EEPROM would return bad +1351:Generated_Source\PSoC4/cy_em_eeprom.c **** * checksum while trying to read the EEPROM rows which were not yet written by +1352:Generated_Source\PSoC4/cy_em_eeprom.c **** * the user. E.g. any read after device reprogramming without previous Write() +1353:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation to the EEPROM would fail. This would happen because the Em_EEPROM +1354:Generated_Source\PSoC4/cy_em_eeprom.c **** * headers checksum field values (which is zero at the moment) would not be +1355:Generated_Source\PSoC4/cy_em_eeprom.c **** * equal to the actual data checksum. This function allows to avoid read failure +1356:Generated_Source\PSoC4/cy_em_eeprom.c **** * after device reprogramming. +1357:Generated_Source\PSoC4/cy_em_eeprom.c **** * + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 69 + + +1358:Generated_Source\PSoC4/cy_em_eeprom.c **** * \note +1359:Generated_Source\PSoC4/cy_em_eeprom.c **** * This function uses a buffer of the flash row size to perform read +1360:Generated_Source\PSoC4/cy_em_eeprom.c **** * operation. For the size of the row refer to the specific PSoC device +1361:Generated_Source\PSoC4/cy_em_eeprom.c **** * datasheet. +1362:Generated_Source\PSoC4/cy_em_eeprom.c **** * +1363:Generated_Source\PSoC4/cy_em_eeprom.c **** *******************************************************************************/ +1364:Generated_Source\PSoC4/cy_em_eeprom.c **** static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context) +1365:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 2479 .loc 1 1365 0 + 2480 .cfi_startproc + 2481 @ args = 0, pretend = 0, frame = 160 + 2482 @ frame_needed = 1, uses_anonymous_args = 0 + 2483 0000 90B5 push {r4, r7, lr} + 2484 .cfi_def_cfa_offset 12 + 2485 .cfi_offset 4, -12 + 2486 .cfi_offset 7, -8 + 2487 .cfi_offset 14, -4 + 2488 0002 A9B0 sub sp, sp, #164 + 2489 .cfi_def_cfa_offset 176 + 2490 0004 00AF add r7, sp, #0 + 2491 .cfi_def_cfa_register 7 + 2492 0006 7860 str r0, [r7, #4] +1366:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 i; +1367:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 rdAddr; +1368:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; +1369:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 wrAddr = context->lastWrRowAddr; + 2493 .loc 1 1369 0 + 2494 0008 7B68 ldr r3, [r7, #4] + 2495 000a 9B68 ldr r3, [r3, #8] + 2496 000c BB60 str r3, [r7, #8] +1370:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 tmpRowAddr; +1371:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the sequence number (number of writes) */ +1372:Generated_Source\PSoC4/cy_em_eeprom.c **** uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr); + 2497 .loc 1 1372 0 + 2498 000e BB68 ldr r3, [r7, #8] + 2499 0010 1B68 ldr r3, [r3] + 2500 0012 9822 movs r2, #152 + 2501 0014 BA18 adds r2, r7, r2 + 2502 0016 1360 str r3, [r2] +1373:Generated_Source\PSoC4/cy_em_eeprom.c **** cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + 2503 .loc 1 1373 0 + 2504 0018 9723 movs r3, #151 + 2505 001a FB18 adds r3, r7, r3 + 2506 001c 0122 movs r2, #1 + 2507 001e 1A70 strb r2, [r3] +1374:Generated_Source\PSoC4/cy_em_eeprom.c **** +1375:Generated_Source\PSoC4/cy_em_eeprom.c **** for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++) + 2508 .loc 1 1375 0 + 2509 0020 0023 movs r3, #0 + 2510 0022 9C22 movs r2, #156 + 2511 0024 BA18 adds r2, r7, r2 + 2512 0026 1360 str r3, [r2] + 2513 0028 53E0 b .L131 + 2514 .L132: +1376:Generated_Source\PSoC4/cy_em_eeprom.c **** { +1377:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Copy the EEPROM row from Flash to RAM */ +1378:Generated_Source\PSoC4/cy_em_eeprom.c **** (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 70 + + + 2515 .loc 1 1378 0 discriminator 3 + 2516 002a BB68 ldr r3, [r7, #8] + 2517 002c 1900 movs r1, r3 + 2518 002e 0C23 movs r3, #12 + 2519 0030 FB18 adds r3, r7, r3 + 2520 0032 8022 movs r2, #128 + 2521 0034 1800 movs r0, r3 + 2522 0036 FFF7FEFF bl memcpy +1379:Generated_Source\PSoC4/cy_em_eeprom.c **** +1380:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Increment the sequence number */ +1381:Generated_Source\PSoC4/cy_em_eeprom.c **** seqNum++; + 2523 .loc 1 1381 0 discriminator 3 + 2524 003a 9823 movs r3, #152 + 2525 003c FB18 adds r3, r7, r3 + 2526 003e 1B68 ldr r3, [r3] + 2527 0040 0133 adds r3, r3, #1 + 2528 0042 9822 movs r2, #152 + 2529 0044 BA18 adds r2, r7, r2 + 2530 0046 1360 str r3, [r2] +1382:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + 2531 .loc 1 1382 0 discriminator 3 + 2532 0048 0C23 movs r3, #12 + 2533 004a FB18 adds r3, r7, r3 + 2534 004c 9822 movs r2, #152 + 2535 004e BA18 adds r2, r7, r2 + 2536 0050 1268 ldr r2, [r2] + 2537 0052 1A60 str r2, [r3] +1383:Generated_Source\PSoC4/cy_em_eeprom.c **** +1384:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Calculate and fill the checksum to the Em_EEPROM header */ +1385:Generated_Source\PSoC4/cy_em_eeprom.c **** writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) +1386:Generated_Source\PSoC4/cy_em_eeprom.c **** CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + 2538 .loc 1 1386 0 discriminator 3 + 2539 0054 0C23 movs r3, #12 + 2540 0056 FB18 adds r3, r7, r3 + 2541 0058 4033 adds r3, r3, #64 + 2542 005a 4021 movs r1, #64 + 2543 005c 1800 movs r0, r3 + 2544 005e FFF7FEFF bl CalcChecksum + 2545 0062 0300 movs r3, r0 +1385:Generated_Source\PSoC4/cy_em_eeprom.c **** CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + 2546 .loc 1 1385 0 discriminator 3 + 2547 0064 1A00 movs r2, r3 + 2548 0066 0C23 movs r3, #12 + 2549 0068 FB18 adds r3, r7, r3 + 2550 006a DA63 str r2, [r3, #60] +1387:Generated_Source\PSoC4/cy_em_eeprom.c **** CY_EM_EEPROM_EEPROM_DATA_LEN); +1388:Generated_Source\PSoC4/cy_em_eeprom.c **** +1389:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the data to the specified flash row */ +1390:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(wrAddr, writeRamBuffer, context); + 2551 .loc 1 1390 0 discriminator 3 + 2552 006c BB68 ldr r3, [r7, #8] + 2553 006e 9722 movs r2, #151 + 2554 0070 BC18 adds r4, r7, r2 + 2555 0072 7A68 ldr r2, [r7, #4] + 2556 0074 0C21 movs r1, #12 + 2557 0076 7918 adds r1, r7, r1 + 2558 0078 1800 movs r0, r3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 71 + + + 2559 007a FFF7FEFF bl WriteRow + 2560 007e 0300 movs r3, r0 + 2561 0080 2370 strb r3, [r4] +1391:Generated_Source\PSoC4/cy_em_eeprom.c **** +1392:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Update the row address to point to the relevant row in the redundant +1393:Generated_Source\PSoC4/cy_em_eeprom.c **** * EEPROM's copy. +1394:Generated_Source\PSoC4/cy_em_eeprom.c **** */ +1395:Generated_Source\PSoC4/cy_em_eeprom.c **** tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr; + 2562 .loc 1 1395 0 discriminator 3 + 2563 0082 BA68 ldr r2, [r7, #8] + 2564 0084 7B68 ldr r3, [r7, #4] + 2565 0086 9B69 ldr r3, [r3, #24] + 2566 0088 D21A subs r2, r2, r3 + 2567 008a 7B68 ldr r3, [r7, #4] + 2568 008c 1B68 ldr r3, [r3] + 2569 008e D318 adds r3, r2, r3 + 2570 0090 9022 movs r2, #144 + 2571 0092 BA18 adds r2, r7, r2 + 2572 0094 1360 str r3, [r2] +1396:Generated_Source\PSoC4/cy_em_eeprom.c **** +1397:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Write the data to the specified flash row */ +1398:Generated_Source\PSoC4/cy_em_eeprom.c **** ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + 2573 .loc 1 1398 0 discriminator 3 + 2574 0096 9723 movs r3, #151 + 2575 0098 FC18 adds r4, r7, r3 + 2576 009a 7A68 ldr r2, [r7, #4] + 2577 009c 0C23 movs r3, #12 + 2578 009e F918 adds r1, r7, r3 + 2579 00a0 9023 movs r3, #144 + 2580 00a2 FB18 adds r3, r7, r3 + 2581 00a4 1B68 ldr r3, [r3] + 2582 00a6 1800 movs r0, r3 + 2583 00a8 FFF7FEFF bl WriteRow + 2584 00ac 0300 movs r3, r0 + 2585 00ae 2370 strb r3, [r4] +1399:Generated_Source\PSoC4/cy_em_eeprom.c **** +1400:Generated_Source\PSoC4/cy_em_eeprom.c **** /* Get the address of the next row to be written. +1401:Generated_Source\PSoC4/cy_em_eeprom.c **** * "rdAddr" is not used in this function but provided to prevent NULL +1402:Generated_Source\PSoC4/cy_em_eeprom.c **** * pointer exception in GetNextRowToWrite(). +1403:Generated_Source\PSoC4/cy_em_eeprom.c **** */ +1404:Generated_Source\PSoC4/cy_em_eeprom.c **** GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context); + 2586 .loc 1 1404 0 discriminator 3 + 2587 00b0 7B68 ldr r3, [r7, #4] + 2588 00b2 8C22 movs r2, #140 + 2589 00b4 BA18 adds r2, r7, r2 + 2590 00b6 0821 movs r1, #8 + 2591 00b8 7918 adds r1, r7, r1 + 2592 00ba 9820 movs r0, #152 + 2593 00bc 3818 adds r0, r7, r0 + 2594 00be 0068 ldr r0, [r0] + 2595 00c0 FFF7FEFF bl GetNextRowToWrite +1375:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 2596 .loc 1 1375 0 discriminator 3 + 2597 00c4 9C23 movs r3, #156 + 2598 00c6 FB18 adds r3, r7, r3 + 2599 00c8 1B68 ldr r3, [r3] + 2600 00ca 0133 adds r3, r3, #1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 72 + + + 2601 00cc 9C22 movs r2, #156 + 2602 00ce BA18 adds r2, r7, r2 + 2603 00d0 1360 str r3, [r2] + 2604 .L131: +1375:Generated_Source\PSoC4/cy_em_eeprom.c **** { + 2605 .loc 1 1375 0 is_stmt 0 discriminator 1 + 2606 00d2 7B68 ldr r3, [r7, #4] + 2607 00d4 5A68 ldr r2, [r3, #4] + 2608 00d6 7B68 ldr r3, [r7, #4] + 2609 00d8 1B69 ldr r3, [r3, #16] + 2610 00da 5A43 muls r2, r3 + 2611 00dc 9C23 movs r3, #156 + 2612 00de FB18 adds r3, r7, r3 + 2613 00e0 1B68 ldr r3, [r3] + 2614 00e2 9A42 cmp r2, r3 + 2615 00e4 A1D8 bhi .L132 +1405:Generated_Source\PSoC4/cy_em_eeprom.c **** } +1406:Generated_Source\PSoC4/cy_em_eeprom.c **** +1407:Generated_Source\PSoC4/cy_em_eeprom.c **** return(ret); + 2616 .loc 1 1407 0 is_stmt 1 + 2617 00e6 9723 movs r3, #151 + 2618 00e8 FB18 adds r3, r7, r3 + 2619 00ea 1B78 ldrb r3, [r3] +1408:Generated_Source\PSoC4/cy_em_eeprom.c **** } + 2620 .loc 1 1408 0 + 2621 00ec 1800 movs r0, r3 + 2622 00ee BD46 mov sp, r7 + 2623 00f0 29B0 add sp, sp, #164 + 2624 @ sp needed + 2625 00f2 90BD pop {r4, r7, pc} + 2626 .cfi_endproc + 2627 .LFE14: + 2628 .size FillChecksum, .-FillChecksum + 2629 .text + 2630 .Letext0: + 2631 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 2632 .file 3 "Generated_Source\\PSoC4\\cy_em_eeprom.h" + 2633 .section .debug_info,"",%progbits + 2634 .Ldebug_info0: + 2635 0000 640A0000 .4byte 0xa64 + 2636 0004 0400 .2byte 0x4 + 2637 0006 00000000 .4byte .Ldebug_abbrev0 + 2638 000a 04 .byte 0x4 + 2639 000b 01 .uleb128 0x1 + 2640 000c E1020000 .4byte .LASF101 + 2641 0010 0C .byte 0xc + 2642 0011 C3000000 .4byte .LASF102 + 2643 0015 78010000 .4byte .LASF103 + 2644 0019 18000000 .4byte .Ldebug_ranges0+0x18 + 2645 001d 00000000 .4byte 0 + 2646 0021 00000000 .4byte .Ldebug_line0 + 2647 0025 02 .uleb128 0x2 + 2648 0026 01 .byte 0x1 + 2649 0027 06 .byte 0x6 + 2650 0028 9B000000 .4byte .LASF0 + 2651 002c 02 .uleb128 0x2 + 2652 002d 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 73 + + + 2653 002e 08 .byte 0x8 + 2654 002f 81040000 .4byte .LASF1 + 2655 0033 02 .uleb128 0x2 + 2656 0034 02 .byte 0x2 + 2657 0035 05 .byte 0x5 + 2658 0036 97040000 .4byte .LASF2 + 2659 003a 02 .uleb128 0x2 + 2660 003b 02 .byte 0x2 + 2661 003c 07 .byte 0x7 + 2662 003d 87020000 .4byte .LASF3 + 2663 0041 02 .uleb128 0x2 + 2664 0042 04 .byte 0x4 + 2665 0043 05 .byte 0x5 + 2666 0044 18010000 .4byte .LASF4 + 2667 0048 02 .uleb128 0x2 + 2668 0049 04 .byte 0x4 + 2669 004a 07 .byte 0x7 + 2670 004b 37020000 .4byte .LASF5 + 2671 004f 02 .uleb128 0x2 + 2672 0050 08 .byte 0x8 + 2673 0051 05 .byte 0x5 + 2674 0052 8D000000 .4byte .LASF6 + 2675 0056 02 .uleb128 0x2 + 2676 0057 08 .byte 0x8 + 2677 0058 07 .byte 0x7 + 2678 0059 66000000 .4byte .LASF7 + 2679 005d 03 .uleb128 0x3 + 2680 005e 04 .byte 0x4 + 2681 005f 05 .byte 0x5 + 2682 0060 696E7400 .ascii "int\000" + 2683 0064 02 .uleb128 0x2 + 2684 0065 04 .byte 0x4 + 2685 0066 07 .byte 0x7 + 2686 0067 21020000 .4byte .LASF8 + 2687 006b 04 .uleb128 0x4 + 2688 006c 34010000 .4byte .LASF9 + 2689 0070 02 .byte 0x2 + 2690 0071 E401 .2byte 0x1e4 + 2691 0073 2C000000 .4byte 0x2c + 2692 0077 04 .uleb128 0x4 + 2693 0078 00000000 .4byte .LASF10 + 2694 007c 02 .byte 0x2 + 2695 007d E501 .2byte 0x1e5 + 2696 007f 3A000000 .4byte 0x3a + 2697 0083 04 .uleb128 0x4 + 2698 0084 4E010000 .4byte .LASF11 + 2699 0088 02 .byte 0x2 + 2700 0089 E601 .2byte 0x1e6 + 2701 008b 48000000 .4byte 0x48 + 2702 008f 02 .uleb128 0x2 + 2703 0090 04 .byte 0x4 + 2704 0091 04 .byte 0x4 + 2705 0092 53040000 .4byte .LASF12 + 2706 0096 02 .uleb128 0x2 + 2707 0097 08 .byte 0x8 + 2708 0098 04 .byte 0x4 + 2709 0099 3A010000 .4byte .LASF13 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 74 + + + 2710 009d 02 .uleb128 0x2 + 2711 009e 01 .byte 0x1 + 2712 009f 08 .byte 0x8 + 2713 00a0 0A050000 .4byte .LASF14 + 2714 00a4 04 .uleb128 0x4 + 2715 00a5 F3050000 .4byte .LASF15 + 2716 00a9 02 .byte 0x2 + 2717 00aa 8602 .2byte 0x286 + 2718 00ac 48000000 .4byte 0x48 + 2719 00b0 02 .uleb128 0x2 + 2720 00b1 08 .byte 0x8 + 2721 00b2 04 .byte 0x4 + 2722 00b3 CA030000 .4byte .LASF16 + 2723 00b7 02 .uleb128 0x2 + 2724 00b8 04 .byte 0x4 + 2725 00b9 07 .byte 0x7 + 2726 00ba C1030000 .4byte .LASF17 + 2727 00be 05 .uleb128 0x5 + 2728 00bf 04 .byte 0x4 + 2729 00c0 06 .uleb128 0x6 + 2730 00c1 10 .byte 0x10 + 2731 00c2 03 .byte 0x3 + 2732 00c3 FB .byte 0xfb + 2733 00c4 09010000 .4byte 0x109 + 2734 00c8 07 .uleb128 0x7 + 2735 00c9 82000000 .4byte .LASF18 + 2736 00cd 03 .byte 0x3 + 2737 00ce FE .byte 0xfe + 2738 00cf 83000000 .4byte 0x83 + 2739 00d3 00 .byte 0 + 2740 00d4 08 .uleb128 0x8 + 2741 00d5 87050000 .4byte .LASF19 + 2742 00d9 03 .byte 0x3 + 2743 00da 0301 .2byte 0x103 + 2744 00dc 83000000 .4byte 0x83 + 2745 00e0 04 .byte 0x4 + 2746 00e1 08 .uleb128 0x8 + 2747 00e2 0A020000 .4byte .LASF20 + 2748 00e6 03 .byte 0x3 + 2749 00e7 0601 .2byte 0x106 + 2750 00e9 6B000000 .4byte 0x6b + 2751 00ed 08 .byte 0x8 + 2752 00ee 08 .uleb128 0x8 + 2753 00ef D3050000 .4byte .LASF21 + 2754 00f3 03 .byte 0x3 + 2755 00f4 0B01 .2byte 0x10b + 2756 00f6 6B000000 .4byte 0x6b + 2757 00fa 09 .byte 0x9 + 2758 00fb 08 .uleb128 0x8 + 2759 00fc 21010000 .4byte .LASF22 + 2760 0100 03 .byte 0x3 + 2761 0101 0E01 .2byte 0x10e + 2762 0103 83000000 .4byte 0x83 + 2763 0107 0C .byte 0xc + 2764 0108 00 .byte 0 + 2765 0109 04 .uleb128 0x4 + 2766 010a 69050000 .4byte .LASF23 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 75 + + + 2767 010e 03 .byte 0x3 + 2768 010f 0F01 .2byte 0x10f + 2769 0111 C0000000 .4byte 0xc0 + 2770 0115 09 .uleb128 0x9 + 2771 0116 1C .byte 0x1c + 2772 0117 03 .byte 0x3 + 2773 0118 1601 .2byte 0x116 + 2774 011a 87010000 .4byte 0x187 + 2775 011e 08 .uleb128 0x8 + 2776 011f 77040000 .4byte .LASF24 + 2777 0123 03 .byte 0x3 + 2778 0124 1B01 .2byte 0x11b + 2779 0126 83000000 .4byte 0x83 + 2780 012a 00 .byte 0 + 2781 012b 08 .uleb128 0x8 + 2782 012c 4F000000 .4byte .LASF25 + 2783 0130 03 .byte 0x3 + 2784 0131 2001 .2byte 0x120 + 2785 0133 83000000 .4byte 0x83 + 2786 0137 04 .byte 0x4 + 2787 0138 08 .uleb128 0x8 + 2788 0139 43050000 .4byte .LASF26 + 2789 013d 03 .byte 0x3 + 2790 013e 2301 .2byte 0x123 + 2791 0140 83000000 .4byte 0x83 + 2792 0144 08 .byte 0x8 + 2793 0145 08 .uleb128 0x8 + 2794 0146 82000000 .4byte .LASF18 + 2795 014a 03 .byte 0x3 + 2796 014b 2601 .2byte 0x126 + 2797 014d 83000000 .4byte 0x83 + 2798 0151 0C .byte 0xc + 2799 0152 08 .uleb128 0x8 + 2800 0153 87050000 .4byte .LASF19 + 2801 0157 03 .byte 0x3 + 2802 0158 2B01 .2byte 0x12b + 2803 015a 83000000 .4byte 0x83 + 2804 015e 10 .byte 0x10 + 2805 015f 08 .uleb128 0x8 + 2806 0160 0A020000 .4byte .LASF20 + 2807 0164 03 .byte 0x3 + 2808 0165 2E01 .2byte 0x12e + 2809 0167 6B000000 .4byte 0x6b + 2810 016b 14 .byte 0x14 + 2811 016c 08 .uleb128 0x8 + 2812 016d D3050000 .4byte .LASF21 + 2813 0171 03 .byte 0x3 + 2814 0172 3301 .2byte 0x133 + 2815 0174 6B000000 .4byte 0x6b + 2816 0178 15 .byte 0x15 + 2817 0179 08 .uleb128 0x8 + 2818 017a 21010000 .4byte .LASF22 + 2819 017e 03 .byte 0x3 + 2820 017f 3601 .2byte 0x136 + 2821 0181 83000000 .4byte 0x83 + 2822 0185 18 .byte 0x18 + 2823 0186 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 76 + + + 2824 0187 04 .uleb128 0x4 + 2825 0188 03040000 .4byte .LASF27 + 2826 018c 03 .byte 0x3 + 2827 018d 3701 .2byte 0x137 + 2828 018f 15010000 .4byte 0x115 + 2829 0193 0A .uleb128 0xa + 2830 0194 01 .byte 0x1 + 2831 0195 2C000000 .4byte 0x2c + 2832 0199 03 .byte 0x3 + 2833 019a 5401 .2byte 0x154 + 2834 019c BF010000 .4byte 0x1bf + 2835 01a0 0B .uleb128 0xb + 2836 01a1 BE050000 .4byte .LASF28 + 2837 01a5 00 .byte 0 + 2838 01a6 0B .uleb128 0xb + 2839 01a7 90030000 .4byte .LASF29 + 2840 01ab 01 .byte 0x1 + 2841 01ac 0B .uleb128 0xb + 2842 01ad A7030000 .4byte .LASF30 + 2843 01b1 02 .byte 0x2 + 2844 01b2 0B .uleb128 0xb + 2845 01b3 61040000 .4byte .LASF31 + 2846 01b7 03 .byte 0x3 + 2847 01b8 0B .uleb128 0xb + 2848 01b9 E9000000 .4byte .LASF32 + 2849 01bd 04 .byte 0x4 + 2850 01be 00 .byte 0 + 2851 01bf 04 .uleb128 0x4 + 2852 01c0 1A000000 .4byte .LASF33 + 2853 01c4 03 .byte 0x3 + 2854 01c5 5A01 .2byte 0x15a + 2855 01c7 93010000 .4byte 0x193 + 2856 01cb 0C .uleb128 0xc + 2857 01cc D0040000 .4byte .LASF36 + 2858 01d0 01 .byte 0x1 + 2859 01d1 5F .byte 0x5f + 2860 01d2 BF010000 .4byte 0x1bf + 2861 01d6 00000000 .4byte .LFB0 + 2862 01da F6000000 .4byte .LFE0-.LFB0 + 2863 01de 01 .uleb128 0x1 + 2864 01df 9C .byte 0x9c + 2865 01e0 0F020000 .4byte 0x20f + 2866 01e4 0D .uleb128 0xd + 2867 01e5 0F050000 .4byte .LASF34 + 2868 01e9 01 .byte 0x1 + 2869 01ea 5F .byte 0x5f + 2870 01eb 0F020000 .4byte 0x20f + 2871 01ef 02 .uleb128 0x2 + 2872 01f0 91 .byte 0x91 + 2873 01f1 64 .sleb128 -28 + 2874 01f2 0D .uleb128 0xd + 2875 01f3 3B050000 .4byte .LASF35 + 2876 01f7 01 .byte 0x1 + 2877 01f8 5F .byte 0x5f + 2878 01f9 15020000 .4byte 0x215 + 2879 01fd 02 .uleb128 0x2 + 2880 01fe 91 .byte 0x91 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 77 + + + 2881 01ff 60 .sleb128 -32 + 2882 0200 0E .uleb128 0xe + 2883 0201 72657400 .ascii "ret\000" + 2884 0205 01 .byte 0x1 + 2885 0206 61 .byte 0x61 + 2886 0207 BF010000 .4byte 0x1bf + 2887 020b 02 .uleb128 0x2 + 2888 020c 91 .byte 0x91 + 2889 020d 6F .sleb128 -17 + 2890 020e 00 .byte 0 + 2891 020f 0F .uleb128 0xf + 2892 0210 04 .byte 0x4 + 2893 0211 09010000 .4byte 0x109 + 2894 0215 0F .uleb128 0xf + 2895 0216 04 .byte 0x4 + 2896 0217 87010000 .4byte 0x187 + 2897 021b 0C .uleb128 0xc + 2898 021c 56020000 .4byte .LASF37 + 2899 0220 01 .byte 0x1 + 2900 0221 A9 .byte 0xa9 + 2901 0222 BF010000 .4byte 0x1bf + 2902 0226 00000000 .4byte .LFB1 + 2903 022a 2A030000 .4byte .LFE1-.LFB1 + 2904 022e 01 .uleb128 0x1 + 2905 022f 9C .byte 0x9c + 2906 0230 BF030000 .4byte 0x3bf + 2907 0234 0D .uleb128 0xd + 2908 0235 7D000000 .4byte .LASF38 + 2909 0239 01 .byte 0x1 + 2910 023a A9 .byte 0xa9 + 2911 023b 83000000 .4byte 0x83 + 2912 023f 03 .uleb128 0x3 + 2913 0240 91 .byte 0x91 + 2914 0241 9C7F .sleb128 -100 + 2915 0243 0D .uleb128 0xd + 2916 0244 C9020000 .4byte .LASF39 + 2917 0248 01 .byte 0x1 + 2918 0249 AA .byte 0xaa + 2919 024a BE000000 .4byte 0xbe + 2920 024e 03 .uleb128 0x3 + 2921 024f 91 .byte 0x91 + 2922 0250 987F .sleb128 -104 + 2923 0252 0D .uleb128 0xd + 2924 0253 82020000 .4byte .LASF40 + 2925 0257 01 .byte 0x1 + 2926 0258 AB .byte 0xab + 2927 0259 83000000 .4byte 0x83 + 2928 025d 03 .uleb128 0x3 + 2929 025e 91 .byte 0x91 + 2930 025f 947F .sleb128 -108 + 2931 0261 0D .uleb128 0xd + 2932 0262 3B050000 .4byte .LASF35 + 2933 0266 01 .byte 0x1 + 2934 0267 AC .byte 0xac + 2935 0268 15020000 .4byte 0x215 + 2936 026c 03 .uleb128 0x3 + 2937 026d 91 .byte 0x91 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 78 + + + 2938 026e 907F .sleb128 -112 + 2939 0270 0E .uleb128 0xe + 2940 0271 72657400 .ascii "ret\000" + 2941 0275 01 .byte 0x1 + 2942 0276 AE .byte 0xae + 2943 0277 BF010000 .4byte 0x1bf + 2944 027b 02 .uleb128 0x2 + 2945 027c 91 .byte 0x91 + 2946 027d 6F .sleb128 -17 + 2947 027e 0E .uleb128 0xe + 2948 027f 6900 .ascii "i\000" + 2949 0281 01 .byte 0x1 + 2950 0282 AF .byte 0xaf + 2951 0283 83000000 .4byte 0x83 + 2952 0287 02 .uleb128 0x2 + 2953 0288 91 .byte 0x91 + 2954 0289 68 .sleb128 -24 + 2955 028a 10 .uleb128 0x10 + 2956 028b 16050000 .4byte .LASF41 + 2957 028f 01 .byte 0x1 + 2958 0290 B0 .byte 0xb0 + 2959 0291 83000000 .4byte 0x83 + 2960 0295 02 .uleb128 0x2 + 2961 0296 91 .byte 0x91 + 2962 0297 64 .sleb128 -28 + 2963 0298 10 .uleb128 0x10 + 2964 0299 6F030000 .4byte .LASF42 + 2965 029d 01 .byte 0x1 + 2966 029e B1 .byte 0xb1 + 2967 029f 83000000 .4byte 0x83 + 2968 02a3 03 .uleb128 0x3 + 2969 02a4 91 .byte 0x91 + 2970 02a5 BC7F .sleb128 -68 + 2971 02a7 10 .uleb128 0x10 + 2972 02a8 5C050000 .4byte .LASF43 + 2973 02ac 01 .byte 0x1 + 2974 02ad B2 .byte 0xb2 + 2975 02ae 83000000 .4byte 0x83 + 2976 02b2 03 .uleb128 0x3 + 2977 02b3 91 .byte 0x91 + 2978 02b4 B07F .sleb128 -80 + 2979 02b6 10 .uleb128 0x10 + 2980 02b7 D4020000 .4byte .LASF44 + 2981 02bb 01 .byte 0x1 + 2982 02bc B3 .byte 0xb3 + 2983 02bd 83000000 .4byte 0x83 + 2984 02c1 02 .uleb128 0x2 + 2985 02c2 91 .byte 0x91 + 2986 02c3 60 .sleb128 -32 + 2987 02c4 10 .uleb128 0x10 + 2988 02c5 55010000 .4byte .LASF45 + 2989 02c9 01 .byte 0x1 + 2990 02ca B4 .byte 0xb4 + 2991 02cb 83000000 .4byte 0x83 + 2992 02cf 03 .uleb128 0x3 + 2993 02d0 91 .byte 0x91 + 2994 02d1 B87F .sleb128 -72 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 79 + + + 2995 02d3 10 .uleb128 0x10 + 2996 02d4 E1050000 .4byte .LASF46 + 2997 02d8 01 .byte 0x1 + 2998 02d9 B5 .byte 0xb5 + 2999 02da 83000000 .4byte 0x83 + 3000 02de 02 .uleb128 0x2 + 3001 02df 91 .byte 0x91 + 3002 02e0 5C .sleb128 -36 + 3003 02e1 10 .uleb128 0x10 + 3004 02e2 BA040000 .4byte .LASF47 + 3005 02e6 01 .byte 0x1 + 3006 02e7 B6 .byte 0xb6 + 3007 02e8 83000000 .4byte 0x83 + 3008 02ec 02 .uleb128 0x2 + 3009 02ed 91 .byte 0x91 + 3010 02ee 58 .sleb128 -40 + 3011 02ef 10 .uleb128 0x10 + 3012 02f0 2D060000 .4byte .LASF48 + 3013 02f4 01 .byte 0x1 + 3014 02f5 B7 .byte 0xb7 + 3015 02f6 83000000 .4byte 0x83 + 3016 02fa 02 .uleb128 0x2 + 3017 02fb 91 .byte 0x91 + 3018 02fc 54 .sleb128 -44 + 3019 02fd 11 .uleb128 0x11 + 3020 02fe 42000000 .4byte .LBB2 + 3021 0302 DA020000 .4byte .LBE2-.LBB2 + 3022 0306 10 .uleb128 0x10 + 3023 0307 9A050000 .4byte .LASF49 + 3024 030b 01 .byte 0x1 + 3025 030c BC .byte 0xbc + 3026 030d 83000000 .4byte 0x83 + 3027 0311 02 .uleb128 0x2 + 3028 0312 91 .byte 0x91 + 3029 0313 50 .sleb128 -48 + 3030 0314 10 .uleb128 0x10 + 3031 0315 80050000 .4byte .LASF50 + 3032 0319 01 .byte 0x1 + 3033 031a BD .byte 0xbd + 3034 031b 83000000 .4byte 0x83 + 3035 031f 02 .uleb128 0x2 + 3036 0320 91 .byte 0x91 + 3037 0321 4C .sleb128 -52 + 3038 0322 10 .uleb128 0x10 + 3039 0323 FC030000 .4byte .LASF51 + 3040 0327 01 .byte 0x1 + 3041 0328 BF .byte 0xbf + 3042 0329 83000000 .4byte 0x83 + 3043 032d 02 .uleb128 0x2 + 3044 032e 91 .byte 0x91 + 3045 032f 44 .sleb128 -60 + 3046 0330 10 .uleb128 0x10 + 3047 0331 D3010000 .4byte .LASF52 + 3048 0335 01 .byte 0x1 + 3049 0336 C0 .byte 0xc0 + 3050 0337 83000000 .4byte 0x83 + 3051 033b 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 80 + + + 3052 033c 91 .byte 0x91 + 3053 033d 48 .sleb128 -56 + 3054 033e 10 .uleb128 0x10 + 3055 033f 11060000 .4byte .LASF53 + 3056 0343 01 .byte 0x1 + 3057 0344 C5 .byte 0xc5 + 3058 0345 83000000 .4byte 0x83 + 3059 0349 02 .uleb128 0x2 + 3060 034a 91 .byte 0x91 + 3061 034b 40 .sleb128 -64 + 3062 034c 12 .uleb128 0x12 + 3063 034d EC000000 .4byte .LBB3 + 3064 0351 26000000 .4byte .LBE3-.LBB3 + 3065 0355 69030000 .4byte 0x369 + 3066 0359 10 .uleb128 0x10 + 3067 035a EA010000 .4byte .LASF54 + 3068 035e 01 .byte 0x1 + 3069 035f E2 .byte 0xe2 + 3070 0360 83000000 .4byte 0x83 + 3071 0364 03 .uleb128 0x3 + 3072 0365 91 .byte 0x91 + 3073 0366 B47F .sleb128 -76 + 3074 0368 00 .byte 0 + 3075 0369 11 .uleb128 0x11 + 3076 036a 3A020000 .4byte .LBB4 + 3077 036e D4000000 .4byte .LBE4-.LBB4 + 3078 0372 13 .uleb128 0x13 + 3079 0373 25050000 .4byte .LASF55 + 3080 0377 01 .byte 0x1 + 3081 0378 3B01 .2byte 0x13b + 3082 037a 83000000 .4byte 0x83 + 3083 037e 03 .uleb128 0x3 + 3084 037f 91 .byte 0x91 + 3085 0380 AC7F .sleb128 -84 + 3086 0382 13 .uleb128 0x13 + 3087 0383 59040000 .4byte .LASF56 + 3088 0387 01 .byte 0x1 + 3089 0388 3C01 .2byte 0x13c + 3090 038a 83000000 .4byte 0x83 + 3091 038e 03 .uleb128 0x3 + 3092 038f 91 .byte 0x91 + 3093 0390 A87F .sleb128 -88 + 3094 0392 11 .uleb128 0x11 + 3095 0393 78020000 .4byte .LBB5 + 3096 0397 96000000 .4byte .LBE5-.LBB5 + 3097 039b 13 .uleb128 0x13 + 3098 039c 78020000 .4byte .LASF57 + 3099 03a0 01 .byte 0x1 + 3100 03a1 4101 .2byte 0x141 + 3101 03a3 83000000 .4byte 0x83 + 3102 03a7 03 .uleb128 0x3 + 3103 03a8 91 .byte 0x91 + 3104 03a9 A47F .sleb128 -92 + 3105 03ab 13 .uleb128 0x13 + 3106 03ac A1050000 .4byte .LASF58 + 3107 03b0 01 .byte 0x1 + 3108 03b1 4201 .2byte 0x142 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 81 + + + 3109 03b3 83000000 .4byte 0x83 + 3110 03b7 03 .uleb128 0x3 + 3111 03b8 91 .byte 0x91 + 3112 03b9 A07F .sleb128 -96 + 3113 03bb 00 .byte 0 + 3114 03bc 00 .byte 0 + 3115 03bd 00 .byte 0 + 3116 03be 00 .byte 0 + 3117 03bf 14 .uleb128 0x14 + 3118 03c0 E9030000 .4byte .LASF59 + 3119 03c4 01 .byte 0x1 + 3120 03c5 9B01 .2byte 0x19b + 3121 03c7 BF010000 .4byte 0x1bf + 3122 03cb 00000000 .4byte .LFB2 + 3123 03cf 32030000 .4byte .LFE2-.LFB2 + 3124 03d3 01 .uleb128 0x1 + 3125 03d4 9C .byte 0x9c + 3126 03d5 37050000 .4byte 0x537 + 3127 03d9 15 .uleb128 0x15 + 3128 03da 7D000000 .4byte .LASF38 + 3129 03de 01 .byte 0x1 + 3130 03df 9B01 .2byte 0x19b + 3131 03e1 83000000 .4byte 0x83 + 3132 03e5 03 .uleb128 0x3 + 3133 03e6 91 .byte 0x91 + 3134 03e7 AC7E .sleb128 -212 + 3135 03e9 15 .uleb128 0x15 + 3136 03ea C9020000 .4byte .LASF39 + 3137 03ee 01 .byte 0x1 + 3138 03ef 9C01 .2byte 0x19c + 3139 03f1 BE000000 .4byte 0xbe + 3140 03f5 03 .uleb128 0x3 + 3141 03f6 91 .byte 0x91 + 3142 03f7 A87E .sleb128 -216 + 3143 03f9 15 .uleb128 0x15 + 3144 03fa 82020000 .4byte .LASF40 + 3145 03fe 01 .byte 0x1 + 3146 03ff 9D01 .2byte 0x19d + 3147 0401 83000000 .4byte 0x83 + 3148 0405 03 .uleb128 0x3 + 3149 0406 91 .byte 0x91 + 3150 0407 A47E .sleb128 -220 + 3151 0409 15 .uleb128 0x15 + 3152 040a 3B050000 .4byte .LASF35 + 3153 040e 01 .byte 0x1 + 3154 040f 9E01 .2byte 0x19e + 3155 0411 15020000 .4byte 0x215 + 3156 0415 03 .uleb128 0x3 + 3157 0416 91 .byte 0x91 + 3158 0417 A07E .sleb128 -224 + 3159 0419 16 .uleb128 0x16 + 3160 041a 72657400 .ascii "ret\000" + 3161 041e 01 .byte 0x1 + 3162 041f A001 .2byte 0x1a0 + 3163 0421 BF010000 .4byte 0x1bf + 3164 0425 02 .uleb128 0x2 + 3165 0426 91 .byte 0x91 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 82 + + + 3166 0427 6F .sleb128 -17 + 3167 0428 16 .uleb128 0x16 + 3168 0429 6900 .ascii "i\000" + 3169 042b 01 .byte 0x1 + 3170 042c A101 .2byte 0x1a1 + 3171 042e 83000000 .4byte 0x83 + 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3592 0774 16 .uleb128 0x16 + 3593 0775 636E7400 .ascii "cnt\000" + 3594 0779 01 .byte 0x1 + 3595 077a 9F03 .2byte 0x39f + 3596 077c 77000000 .4byte 0x77 + 3597 0780 02 .uleb128 0x2 + 3598 0781 91 .byte 0x91 + 3599 0782 74 .sleb128 -12 + 3600 0783 00 .byte 0 + 3601 0784 0F .uleb128 0xf + 3602 0785 04 .byte 0x4 + 3603 0786 6B000000 .4byte 0x6b + 3604 078a 1C .uleb128 0x1c + 3605 078b 3A040000 .4byte .LASF84 + 3606 078f 01 .byte 0x1 + 3607 0790 BC03 .2byte 0x3bc + 3608 0792 BF010000 .4byte 0x1bf + 3609 0796 00000000 .4byte .LFB9 + 3610 079a 6A000000 .4byte .LFE9-.LFB9 + 3611 079e 01 .uleb128 0x1 + 3612 079f 9C .byte 0x9c + 3613 07a0 E1070000 .4byte 0x7e1 + 3614 07a4 15 .uleb128 0x15 + 3615 07a5 0F050000 .4byte .LASF34 + 3616 07a9 01 .byte 0x1 + 3617 07aa BC03 .2byte 0x3bc + 3618 07ac 0F020000 .4byte 0x20f + 3619 07b0 02 .uleb128 0x2 + 3620 07b1 91 .byte 0x91 + 3621 07b2 64 .sleb128 -28 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 90 + + + 3622 07b3 16 .uleb128 0x16 + 3623 07b4 72657400 .ascii "ret\000" + 3624 07b8 01 .byte 0x1 + 3625 07b9 BE03 .2byte 0x3be + 3626 07bb BF010000 .4byte 0x1bf + 3627 07bf 02 .uleb128 0x2 + 3628 07c0 91 .byte 0x91 + 3629 07c1 77 .sleb128 -9 + 3630 07c2 13 .uleb128 0x13 + 3631 07c3 25050000 .4byte .LASF55 + 3632 07c7 01 .byte 0x1 + 3633 07c8 BF03 .2byte 0x3bf + 3634 07ca 83000000 .4byte 0x83 + 3635 07ce 02 .uleb128 0x2 + 3636 07cf 91 .byte 0x91 + 3637 07d0 70 .sleb128 -16 + 3638 07d1 13 .uleb128 0x13 + 3639 07d2 59040000 .4byte .LASF56 + 3640 07d6 01 .byte 0x1 + 3641 07d7 C003 .2byte 0x3c0 + 3642 07d9 83000000 .4byte 0x83 + 3643 07dd 02 .uleb128 0x2 + 3644 07de 91 .byte 0x91 + 3645 07df 6C .sleb128 -20 + 3646 07e0 00 .byte 0 + 3647 07e1 1E .uleb128 0x1e + 3648 07e2 A7000000 .4byte .LASF85 + 3649 07e6 01 .byte 0x1 + 3650 07e7 DF03 .2byte 0x3df + 3651 07e9 BF010000 .4byte 0x1bf + 3652 07ed 00000000 .4byte .LFB10 + 3653 07f1 4A000000 .4byte .LFE10-.LFB10 + 3654 07f5 01 .uleb128 0x1 + 3655 07f6 9C .byte 0x9c + 3656 07f7 55080000 .4byte 0x855 + 3657 07fb 15 .uleb128 0x15 + 3658 07fc 8F040000 .4byte .LASF86 + 3659 0800 01 .byte 0x1 + 3660 0801 DF03 .2byte 0x3df + 3661 0803 83000000 .4byte 0x83 + 3662 0807 02 .uleb128 0x2 + 3663 0808 91 .byte 0x91 + 3664 0809 64 .sleb128 -28 + 3665 080a 15 .uleb128 0x15 + 3666 080b 09060000 .4byte .LASF83 + 3667 080f 01 .byte 0x1 + 3668 0810 E003 .2byte 0x3e0 + 3669 0812 7F060000 .4byte 0x67f + 3670 0816 02 .uleb128 0x2 + 3671 0817 91 .byte 0x91 + 3672 0818 60 .sleb128 -32 + 3673 0819 15 .uleb128 0x15 + 3674 081a 3B050000 .4byte .LASF35 + 3675 081e 01 .byte 0x1 + 3676 081f E103 .2byte 0x3e1 + 3677 0821 15020000 .4byte 0x215 + 3678 0825 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 91 + + + 3679 0826 91 .byte 0x91 + 3680 0827 5C .sleb128 -36 + 3681 0828 16 .uleb128 0x16 + 3682 0829 72657400 .ascii "ret\000" + 3683 082d 01 .byte 0x1 + 3684 082e E303 .2byte 0x3e3 + 3685 0830 BF010000 .4byte 0x1bf + 3686 0834 02 .uleb128 0x2 + 3687 0835 91 .byte 0x91 + 3688 0836 77 .sleb128 -9 + 3689 0837 16 .uleb128 0x16 + 3690 0838 726300 .ascii "rc\000" + 3691 083b 01 .byte 0x1 + 3692 083c E503 .2byte 0x3e5 + 3693 083e A4000000 .4byte 0xa4 + 3694 0842 02 .uleb128 0x2 + 3695 0843 91 .byte 0x91 + 3696 0844 6C .sleb128 -20 + 3697 0845 13 .uleb128 0x13 + 3698 0846 81030000 .4byte .LASF87 + 3699 084a 01 .byte 0x1 + 3700 084b E603 .2byte 0x3e6 + 3701 084d 83000000 .4byte 0x83 + 3702 0851 02 .uleb128 0x2 + 3703 0852 91 .byte 0x91 + 3704 0853 70 .sleb128 -16 + 3705 0854 00 .byte 0 + 3706 0855 1E .uleb128 0x1e + 3707 0856 87030000 .4byte .LASF88 + 3708 085a 01 .byte 0x1 + 3709 085b 4504 .2byte 0x445 + 3710 085d BF010000 .4byte 0x1bf + 3711 0861 00000000 .4byte .LFB11 + 3712 0865 80000000 .4byte .LFE11-.LFB11 + 3713 0869 01 .uleb128 0x1 + 3714 086a 9C .byte 0x9c + 3715 086b BB080000 .4byte 0x8bb + 3716 086f 15 .uleb128 0x15 + 3717 0870 8F040000 .4byte .LASF86 + 3718 0874 01 .byte 0x1 + 3719 0875 4504 .2byte 0x445 + 3720 0877 83000000 .4byte 0x83 + 3721 087b 02 .uleb128 0x2 + 3722 087c 91 .byte 0x91 + 3723 087d 64 .sleb128 -28 + 3724 087e 15 .uleb128 0x15 + 3725 087f FE010000 .4byte .LASF89 + 3726 0883 01 .byte 0x1 + 3727 0884 4604 .2byte 0x446 + 3728 0886 83000000 .4byte 0x83 + 3729 088a 02 .uleb128 0x2 + 3730 088b 91 .byte 0x91 + 3731 088c 60 .sleb128 -32 + 3732 088d 15 .uleb128 0x15 + 3733 088e 3B050000 .4byte .LASF35 + 3734 0892 01 .byte 0x1 + 3735 0893 4704 .2byte 0x447 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 92 + + + 3736 0895 15020000 .4byte 0x215 + 3737 0899 02 .uleb128 0x2 + 3738 089a 91 .byte 0x91 + 3739 089b 5C .sleb128 -36 + 3740 089c 13 .uleb128 0x13 + 3741 089d 1D060000 .4byte .LASF64 + 3742 08a1 01 .byte 0x1 + 3743 08a2 4904 .2byte 0x449 + 3744 08a4 83000000 .4byte 0x83 + 3745 08a8 02 .uleb128 0x2 + 3746 08a9 91 .byte 0x91 + 3747 08aa 68 .sleb128 -24 + 3748 08ab 16 .uleb128 0x16 + 3749 08ac 72657400 .ascii "ret\000" + 3750 08b0 01 .byte 0x1 + 3751 08b1 4A04 .2byte 0x44a + 3752 08b3 BF010000 .4byte 0x1bf + 3753 08b7 02 .uleb128 0x2 + 3754 08b8 91 .byte 0x91 + 3755 08b9 6F .sleb128 -17 + 3756 08ba 00 .byte 0 + 3757 08bb 1E .uleb128 0x1e + 3758 08bc 68020000 .4byte .LASF90 + 3759 08c0 01 .byte 0x1 + 3760 08c1 B904 .2byte 0x4b9 + 3761 08c3 BF010000 .4byte 0x1bf + 3762 08c7 00000000 .4byte .LFB12 + 3763 08cb E0000000 .4byte .LFE12-.LFB12 + 3764 08cf 01 .uleb128 0x1 + 3765 08d0 9C .byte 0x9c + 3766 08d1 53090000 .4byte 0x953 + 3767 08d5 15 .uleb128 0x15 + 3768 08d6 25050000 .4byte .LASF55 + 3769 08da 01 .byte 0x1 + 3770 08db B904 .2byte 0x4b9 + 3771 08dd 83000000 .4byte 0x83 + 3772 08e1 03 .uleb128 0x3 + 3773 08e2 91 .byte 0x91 + 3774 08e3 E47E .sleb128 -156 + 3775 08e5 15 .uleb128 0x15 + 3776 08e6 40000000 .4byte .LASF91 + 3777 08ea 01 .byte 0x1 + 3778 08eb BA04 .2byte 0x4ba + 3779 08ed 83000000 .4byte 0x83 + 3780 08f1 03 .uleb128 0x3 + 3781 08f2 91 .byte 0x91 + 3782 08f3 E07E .sleb128 -160 + 3783 08f5 15 .uleb128 0x15 + 3784 08f6 F1040000 .4byte .LASF92 + 3785 08fa 01 .byte 0x1 + 3786 08fb BB04 .2byte 0x4bb + 3787 08fd 83000000 .4byte 0x83 + 3788 0901 03 .uleb128 0x3 + 3789 0902 91 .byte 0x91 + 3790 0903 DC7E .sleb128 -164 + 3791 0905 15 .uleb128 0x15 + 3792 0906 2E020000 .4byte .LASF93 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 93 + + + 3793 090a 01 .byte 0x1 + 3794 090b BC04 .2byte 0x4bc + 3795 090d 83000000 .4byte 0x83 + 3796 0911 03 .uleb128 0x3 + 3797 0912 91 .byte 0x91 + 3798 0913 D87E .sleb128 -168 + 3799 0915 15 .uleb128 0x15 + 3800 0916 3B050000 .4byte .LASF35 + 3801 091a 01 .byte 0x1 + 3802 091b BD04 .2byte 0x4bd + 3803 091d 15020000 .4byte 0x215 + 3804 0921 02 .uleb128 0x2 + 3805 0922 91 .byte 0x91 + 3806 0923 00 .sleb128 0 + 3807 0924 16 .uleb128 0x16 + 3808 0925 72657400 .ascii "ret\000" + 3809 0929 01 .byte 0x1 + 3810 092a BF04 .2byte 0x4bf + 3811 092c BF010000 .4byte 0x1bf + 3812 0930 02 .uleb128 0x2 + 3813 0931 91 .byte 0x91 + 3814 0932 6F .sleb128 -17 + 3815 0933 13 .uleb128 0x13 + 3816 0934 E2040000 .4byte .LASF62 + 3817 0938 01 .byte 0x1 + 3818 0939 C004 .2byte 0x4c0 + 3819 093b 37050000 .4byte 0x537 + 3820 093f 03 .uleb128 0x3 + 3821 0940 91 .byte 0x91 + 3822 0941 E87E .sleb128 -152 + 3823 0943 13 .uleb128 0x13 + 3824 0944 FB040000 .4byte .LASF94 + 3825 0948 01 .byte 0x1 + 3826 0949 C304 .2byte 0x4c3 + 3827 094b 83000000 .4byte 0x83 + 3828 094f 02 .uleb128 0x2 + 3829 0950 91 .byte 0x91 + 3830 0951 68 .sleb128 -24 + 3831 0952 00 .byte 0 + 3832 0953 1C .uleb128 0x1c + 3833 0954 49020000 .4byte .LASF95 + 3834 0958 01 .byte 0x1 + 3835 0959 0D05 .2byte 0x50d + 3836 095b 83000000 .4byte 0x83 + 3837 095f 00000000 .4byte .LFB13 + 3838 0963 F6000000 .4byte .LFE13-.LFB13 + 3839 0967 01 .uleb128 0x1 + 3840 0968 9C .byte 0x9c + 3841 0969 D7090000 .4byte 0x9d7 + 3842 096d 15 .uleb128 0x15 + 3843 096e 25050000 .4byte .LASF55 + 3844 0972 01 .byte 0x1 + 3845 0973 0D05 .2byte 0x50d + 3846 0975 7F060000 .4byte 0x67f + 3847 0979 02 .uleb128 0x2 + 3848 097a 91 .byte 0x91 + 3849 097b 6C .sleb128 -20 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 94 + + + 3850 097c 15 .uleb128 0x15 + 3851 097d 59040000 .4byte .LASF56 + 3852 0981 01 .byte 0x1 + 3853 0982 0E05 .2byte 0x50e + 3854 0984 7F060000 .4byte 0x67f + 3855 0988 02 .uleb128 0x2 + 3856 0989 91 .byte 0x91 + 3857 098a 68 .sleb128 -24 + 3858 098b 15 .uleb128 0x15 + 3859 098c 34050000 .4byte .LASF96 + 3860 0990 01 .byte 0x1 + 3861 0991 0F05 .2byte 0x50f + 3862 0993 7F060000 .4byte 0x67f + 3863 0997 02 .uleb128 0x2 + 3864 0998 91 .byte 0x91 + 3865 0999 64 .sleb128 -28 + 3866 099a 15 .uleb128 0x15 + 3867 099b 48000000 .4byte .LASF97 + 3868 099f 01 .byte 0x1 + 3869 09a0 1005 .2byte 0x510 + 3870 09a2 83000000 .4byte 0x83 + 3871 09a6 02 .uleb128 0x2 + 3872 09a7 91 .byte 0x91 + 3873 09a8 60 .sleb128 -32 + 3874 09a9 15 .uleb128 0x15 + 3875 09aa 7D000000 .4byte .LASF38 + 3876 09ae 01 .byte 0x1 + 3877 09af 1105 .2byte 0x511 + 3878 09b1 83000000 .4byte 0x83 + 3879 09b5 02 .uleb128 0x2 + 3880 09b6 91 .byte 0x91 + 3881 09b7 00 .sleb128 0 + 3882 09b8 1D .uleb128 0x1d + 3883 09b9 6C656E00 .ascii "len\000" + 3884 09bd 01 .byte 0x1 + 3885 09be 1205 .2byte 0x512 + 3886 09c0 83000000 .4byte 0x83 + 3887 09c4 02 .uleb128 0x2 + 3888 09c5 91 .byte 0x91 + 3889 09c6 04 .sleb128 4 + 3890 09c7 13 .uleb128 0x13 + 3891 09c8 2F050000 .4byte .LASF98 + 3892 09cc 01 .byte 0x1 + 3893 09cd 1405 .2byte 0x514 + 3894 09cf 83000000 .4byte 0x83 + 3895 09d3 02 .uleb128 0x2 + 3896 09d4 91 .byte 0x91 + 3897 09d5 74 .sleb128 -12 + 3898 09d6 00 .byte 0 + 3899 09d7 1F .uleb128 0x1f + 3900 09d8 2D040000 .4byte .LASF99 + 3901 09dc 01 .byte 0x1 + 3902 09dd 5405 .2byte 0x554 + 3903 09df BF010000 .4byte 0x1bf + 3904 09e3 00000000 .4byte .LFB14 + 3905 09e7 F4000000 .4byte .LFE14-.LFB14 + 3906 09eb 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 95 + + + 3907 09ec 9C .byte 0x9c + 3908 09ed 15 .uleb128 0x15 + 3909 09ee 3B050000 .4byte .LASF35 + 3910 09f2 01 .byte 0x1 + 3911 09f3 5405 .2byte 0x554 + 3912 09f5 15020000 .4byte 0x215 + 3913 09f9 03 .uleb128 0x3 + 3914 09fa 91 .byte 0x91 + 3915 09fb D47E .sleb128 -172 + 3916 09fd 16 .uleb128 0x16 + 3917 09fe 6900 .ascii "i\000" + 3918 0a00 01 .byte 0x1 + 3919 0a01 5605 .2byte 0x556 + 3920 0a03 83000000 .4byte 0x83 + 3921 0a07 02 .uleb128 0x2 + 3922 0a08 91 .byte 0x91 + 3923 0a09 6C .sleb128 -20 + 3924 0a0a 13 .uleb128 0x13 + 3925 0a0b 9A050000 .4byte .LASF49 + 3926 0a0f 01 .byte 0x1 + 3927 0a10 5705 .2byte 0x557 + 3928 0a12 83000000 .4byte 0x83 + 3929 0a16 02 .uleb128 0x2 + 3930 0a17 91 .byte 0x91 + 3931 0a18 5C .sleb128 -36 + 3932 0a19 13 .uleb128 0x13 + 3933 0a1a E2040000 .4byte .LASF62 + 3934 0a1e 01 .byte 0x1 + 3935 0a1f 5805 .2byte 0x558 + 3936 0a21 37050000 .4byte 0x537 + 3937 0a25 03 .uleb128 0x3 + 3938 0a26 91 .byte 0x91 + 3939 0a27 DC7E .sleb128 -164 + 3940 0a29 13 .uleb128 0x13 + 3941 0a2a 46040000 .4byte .LASF100 + 3942 0a2e 01 .byte 0x1 + 3943 0a2f 5905 .2byte 0x559 + 3944 0a31 83000000 .4byte 0x83 + 3945 0a35 03 .uleb128 0x3 + 3946 0a36 91 .byte 0x91 + 3947 0a37 D87E .sleb128 -168 + 3948 0a39 13 .uleb128 0x13 + 3949 0a3a 51050000 .4byte .LASF63 + 3950 0a3e 01 .byte 0x1 + 3951 0a3f 5A05 .2byte 0x55a + 3952 0a41 83000000 .4byte 0x83 + 3953 0a45 02 .uleb128 0x2 + 3954 0a46 91 .byte 0x91 + 3955 0a47 60 .sleb128 -32 + 3956 0a48 13 .uleb128 0x13 + 3957 0a49 FC030000 .4byte .LASF51 + 3958 0a4d 01 .byte 0x1 + 3959 0a4e 5C05 .2byte 0x55c + 3960 0a50 83000000 .4byte 0x83 + 3961 0a54 02 .uleb128 0x2 + 3962 0a55 91 .byte 0x91 + 3963 0a56 68 .sleb128 -24 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 96 + + + 3964 0a57 16 .uleb128 0x16 + 3965 0a58 72657400 .ascii "ret\000" + 3966 0a5c 01 .byte 0x1 + 3967 0a5d 5D05 .2byte 0x55d + 3968 0a5f BF010000 .4byte 0x1bf + 3969 0a63 02 .uleb128 0x2 + 3970 0a64 91 .byte 0x91 + 3971 0a65 67 .sleb128 -25 + 3972 0a66 00 .byte 0 + 3973 0a67 00 .byte 0 + 3974 .section .debug_abbrev,"",%progbits + 3975 .Ldebug_abbrev0: + 3976 0000 01 .uleb128 0x1 + 3977 0001 11 .uleb128 0x11 + 3978 0002 01 .byte 0x1 + 3979 0003 25 .uleb128 0x25 + 3980 0004 0E .uleb128 0xe + 3981 0005 13 .uleb128 0x13 + 3982 0006 0B .uleb128 0xb + 3983 0007 03 .uleb128 0x3 + 3984 0008 0E .uleb128 0xe + 3985 0009 1B .uleb128 0x1b + 3986 000a 0E .uleb128 0xe + 3987 000b 55 .uleb128 0x55 + 3988 000c 17 .uleb128 0x17 + 3989 000d 11 .uleb128 0x11 + 3990 000e 01 .uleb128 0x1 + 3991 000f 10 .uleb128 0x10 + 3992 0010 17 .uleb128 0x17 + 3993 0011 00 .byte 0 + 3994 0012 00 .byte 0 + 3995 0013 02 .uleb128 0x2 + 3996 0014 24 .uleb128 0x24 + 3997 0015 00 .byte 0 + 3998 0016 0B .uleb128 0xb + 3999 0017 0B .uleb128 0xb + 4000 0018 3E .uleb128 0x3e + 4001 0019 0B .uleb128 0xb + 4002 001a 03 .uleb128 0x3 + 4003 001b 0E .uleb128 0xe + 4004 001c 00 .byte 0 + 4005 001d 00 .byte 0 + 4006 001e 03 .uleb128 0x3 + 4007 001f 24 .uleb128 0x24 + 4008 0020 00 .byte 0 + 4009 0021 0B .uleb128 0xb + 4010 0022 0B .uleb128 0xb + 4011 0023 3E .uleb128 0x3e + 4012 0024 0B .uleb128 0xb + 4013 0025 03 .uleb128 0x3 + 4014 0026 08 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006b 0B .uleb128 0xb + 4084 006c 0B .uleb128 0xb + 4085 006d 3A .uleb128 0x3a + 4086 006e 0B .uleb128 0xb + 4087 006f 3B .uleb128 0x3b + 4088 0070 05 .uleb128 0x5 + 4089 0071 01 .uleb128 0x1 + 4090 0072 13 .uleb128 0x13 + 4091 0073 00 .byte 0 + 4092 0074 00 .byte 0 + 4093 0075 0A .uleb128 0xa + 4094 0076 04 .uleb128 0x4 + 4095 0077 01 .byte 0x1 + 4096 0078 0B .uleb128 0xb + 4097 0079 0B .uleb128 0xb + 4098 007a 49 .uleb128 0x49 + 4099 007b 13 .uleb128 0x13 + 4100 007c 3A .uleb128 0x3a + 4101 007d 0B .uleb128 0xb + 4102 007e 3B .uleb128 0x3b + 4103 007f 05 .uleb128 0x5 + 4104 0080 01 .uleb128 0x1 + 4105 0081 13 .uleb128 0x13 + 4106 0082 00 .byte 0 + 4107 0083 00 .byte 0 + 4108 0084 0B .uleb128 0xb + 4109 0085 28 .uleb128 0x28 + 4110 0086 00 .byte 0 + 4111 0087 03 .uleb128 0x3 + 4112 0088 0E .uleb128 0xe + 4113 0089 1C .uleb128 0x1c + 4114 008a 0B .uleb128 0xb + 4115 008b 00 .byte 0 + 4116 008c 00 .byte 0 + 4117 008d 0C .uleb128 0xc + 4118 008e 2E .uleb128 0x2e + 4119 008f 01 .byte 0x1 + 4120 0090 3F .uleb128 0x3f + 4121 0091 19 .uleb128 0x19 + 4122 0092 03 .uleb128 0x3 + 4123 0093 0E .uleb128 0xe + 4124 0094 3A .uleb128 0x3a + 4125 0095 0B .uleb128 0xb + 4126 0096 3B .uleb128 0x3b + 4127 0097 0B .uleb128 0xb + 4128 0098 27 .uleb128 0x27 + 4129 0099 19 .uleb128 0x19 + 4130 009a 49 .uleb128 0x49 + 4131 009b 13 .uleb128 0x13 + 4132 009c 11 .uleb128 0x11 + 4133 009d 01 .uleb128 0x1 + 4134 009e 12 .uleb128 0x12 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 99 + + + 4135 009f 06 .uleb128 0x6 + 4136 00a0 40 .uleb128 0x40 + 4137 00a1 18 .uleb128 0x18 + 4138 00a2 9642 .uleb128 0x2116 + 4139 00a4 19 .uleb128 0x19 + 4140 00a5 01 .uleb128 0x1 + 4141 00a6 13 .uleb128 0x13 + 4142 00a7 00 .byte 0 + 4143 00a8 00 .byte 0 + 4144 00a9 0D .uleb128 0xd + 4145 00aa 05 .uleb128 0x5 + 4146 00ab 00 .byte 0 + 4147 00ac 03 .uleb128 0x3 + 4148 00ad 0E .uleb128 0xe + 4149 00ae 3A .uleb128 0x3a + 4150 00af 0B .uleb128 0xb + 4151 00b0 3B .uleb128 0x3b + 4152 00b1 0B .uleb128 0xb + 4153 00b2 49 .uleb128 0x49 + 4154 00b3 13 .uleb128 0x13 + 4155 00b4 02 .uleb128 0x2 + 4156 00b5 18 .uleb128 0x18 + 4157 00b6 00 .byte 0 + 4158 00b7 00 .byte 0 + 4159 00b8 0E .uleb128 0xe + 4160 00b9 34 .uleb128 0x34 + 4161 00ba 00 .byte 0 + 4162 00bb 03 .uleb128 0x3 + 4163 00bc 08 .uleb128 0x8 + 4164 00bd 3A .uleb128 0x3a + 4165 00be 0B .uleb128 0xb + 4166 00bf 3B .uleb128 0x3b + 4167 00c0 0B .uleb128 0xb + 4168 00c1 49 .uleb128 0x49 + 4169 00c2 13 .uleb128 0x13 + 4170 00c3 02 .uleb128 0x2 + 4171 00c4 18 .uleb128 0x18 + 4172 00c5 00 .byte 0 + 4173 00c6 00 .byte 0 + 4174 00c7 0F .uleb128 0xf + 4175 00c8 0F .uleb128 0xf + 4176 00c9 00 .byte 0 + 4177 00ca 0B .uleb128 0xb + 4178 00cb 0B .uleb128 0xb + 4179 00cc 49 .uleb128 0x49 + 4180 00cd 13 .uleb128 0x13 + 4181 00ce 00 .byte 0 + 4182 00cf 00 .byte 0 + 4183 00d0 10 .uleb128 0x10 + 4184 00d1 34 .uleb128 0x34 + 4185 00d2 00 .byte 0 + 4186 00d3 03 .uleb128 0x3 + 4187 00d4 0E .uleb128 0xe + 4188 00d5 3A .uleb128 0x3a + 4189 00d6 0B .uleb128 0xb + 4190 00d7 3B .uleb128 0x3b + 4191 00d8 0B .uleb128 0xb + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 100 + + + 4192 00d9 49 .uleb128 0x49 + 4193 00da 13 .uleb128 0x13 + 4194 00db 02 .uleb128 0x2 + 4195 00dc 18 .uleb128 0x18 + 4196 00dd 00 .byte 0 + 4197 00de 00 .byte 0 + 4198 00df 11 .uleb128 0x11 + 4199 00e0 0B .uleb128 0xb + 4200 00e1 01 .byte 0x1 + 4201 00e2 11 .uleb128 0x11 + 4202 00e3 01 .uleb128 0x1 + 4203 00e4 12 .uleb128 0x12 + 4204 00e5 06 .uleb128 0x6 + 4205 00e6 00 .byte 0 + 4206 00e7 00 .byte 0 + 4207 00e8 12 .uleb128 0x12 + 4208 00e9 0B .uleb128 0xb + 4209 00ea 01 .byte 0x1 + 4210 00eb 11 .uleb128 0x11 + 4211 00ec 01 .uleb128 0x1 + 4212 00ed 12 .uleb128 0x12 + 4213 00ee 06 .uleb128 0x6 + 4214 00ef 01 .uleb128 0x1 + 4215 00f0 13 .uleb128 0x13 + 4216 00f1 00 .byte 0 + 4217 00f2 00 .byte 0 + 4218 00f3 13 .uleb128 0x13 + 4219 00f4 34 .uleb128 0x34 + 4220 00f5 00 .byte 0 + 4221 00f6 03 .uleb128 0x3 + 4222 00f7 0E .uleb128 0xe + 4223 00f8 3A .uleb128 0x3a + 4224 00f9 0B .uleb128 0xb + 4225 00fa 3B .uleb128 0x3b + 4226 00fb 05 .uleb128 0x5 + 4227 00fc 49 .uleb128 0x49 + 4228 00fd 13 .uleb128 0x13 + 4229 00fe 02 .uleb128 0x2 + 4230 00ff 18 .uleb128 0x18 + 4231 0100 00 .byte 0 + 4232 0101 00 .byte 0 + 4233 0102 14 .uleb128 0x14 + 4234 0103 2E .uleb128 0x2e + 4235 0104 01 .byte 0x1 + 4236 0105 3F .uleb128 0x3f + 4237 0106 19 .uleb128 0x19 + 4238 0107 03 .uleb128 0x3 + 4239 0108 0E .uleb128 0xe + 4240 0109 3A .uleb128 0x3a + 4241 010a 0B .uleb128 0xb + 4242 010b 3B .uleb128 0x3b + 4243 010c 05 .uleb128 0x5 + 4244 010d 27 .uleb128 0x27 + 4245 010e 19 .uleb128 0x19 + 4246 010f 49 .uleb128 0x49 + 4247 0110 13 .uleb128 0x13 + 4248 0111 11 .uleb128 0x11 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 101 + + + 4249 0112 01 .uleb128 0x1 + 4250 0113 12 .uleb128 0x12 + 4251 0114 06 .uleb128 0x6 + 4252 0115 40 .uleb128 0x40 + 4253 0116 18 .uleb128 0x18 + 4254 0117 9642 .uleb128 0x2116 + 4255 0119 19 .uleb128 0x19 + 4256 011a 01 .uleb128 0x1 + 4257 011b 13 .uleb128 0x13 + 4258 011c 00 .byte 0 + 4259 011d 00 .byte 0 + 4260 011e 15 .uleb128 0x15 + 4261 011f 05 .uleb128 0x5 + 4262 0120 00 .byte 0 + 4263 0121 03 .uleb128 0x3 + 4264 0122 0E .uleb128 0xe + 4265 0123 3A .uleb128 0x3a + 4266 0124 0B .uleb128 0xb + 4267 0125 3B .uleb128 0x3b + 4268 0126 05 .uleb128 0x5 + 4269 0127 49 .uleb128 0x49 + 4270 0128 13 .uleb128 0x13 + 4271 0129 02 .uleb128 0x2 + 4272 012a 18 .uleb128 0x18 + 4273 012b 00 .byte 0 + 4274 012c 00 .byte 0 + 4275 012d 16 .uleb128 0x16 + 4276 012e 34 .uleb128 0x34 + 4277 012f 00 .byte 0 + 4278 0130 03 .uleb128 0x3 + 4279 0131 08 .uleb128 0x8 + 4280 0132 3A .uleb128 0x3a + 4281 0133 0B .uleb128 0xb + 4282 0134 3B .uleb128 0x3b + 4283 0135 05 .uleb128 0x5 + 4284 0136 49 .uleb128 0x49 + 4285 0137 13 .uleb128 0x13 + 4286 0138 02 .uleb128 0x2 + 4287 0139 18 .uleb128 0x18 + 4288 013a 00 .byte 0 + 4289 013b 00 .byte 0 + 4290 013c 17 .uleb128 0x17 + 4291 013d 0B .uleb128 0xb + 4292 013e 01 .byte 0x1 + 4293 013f 55 .uleb128 0x55 + 4294 0140 17 .uleb128 0x17 + 4295 0141 00 .byte 0 + 4296 0142 00 .byte 0 + 4297 0143 18 .uleb128 0x18 + 4298 0144 01 .uleb128 0x1 + 4299 0145 01 .byte 0x1 + 4300 0146 49 .uleb128 0x49 + 4301 0147 13 .uleb128 0x13 + 4302 0148 01 .uleb128 0x1 + 4303 0149 13 .uleb128 0x13 + 4304 014a 00 .byte 0 + 4305 014b 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 102 + + + 4306 014c 19 .uleb128 0x19 + 4307 014d 21 .uleb128 0x21 + 4308 014e 00 .byte 0 + 4309 014f 49 .uleb128 0x49 + 4310 0150 13 .uleb128 0x13 + 4311 0151 2F .uleb128 0x2f + 4312 0152 0B .uleb128 0xb + 4313 0153 00 .byte 0 + 4314 0154 00 .byte 0 + 4315 0155 1A .uleb128 0x1a + 4316 0156 2E .uleb128 0x2e + 4317 0157 01 .byte 0x1 + 4318 0158 3F .uleb128 0x3f + 4319 0159 19 .uleb128 0x19 + 4320 015a 03 .uleb128 0x3 + 4321 015b 0E .uleb128 0xe + 4322 015c 3A .uleb128 0x3a + 4323 015d 0B .uleb128 0xb + 4324 015e 3B .uleb128 0x3b + 4325 015f 05 .uleb128 0x5 + 4326 0160 27 .uleb128 0x27 + 4327 0161 19 .uleb128 0x19 + 4328 0162 49 .uleb128 0x49 + 4329 0163 13 .uleb128 0x13 + 4330 0164 11 .uleb128 0x11 + 4331 0165 01 .uleb128 0x1 + 4332 0166 12 .uleb128 0x12 + 4333 0167 06 .uleb128 0x6 + 4334 0168 40 .uleb128 0x40 + 4335 0169 18 .uleb128 0x18 + 4336 016a 9742 .uleb128 0x2117 + 4337 016c 19 .uleb128 0x19 + 4338 016d 01 .uleb128 0x1 + 4339 016e 13 .uleb128 0x13 + 4340 016f 00 .byte 0 + 4341 0170 00 .byte 0 + 4342 0171 1B .uleb128 0x1b + 4343 0172 2E .uleb128 0x2e + 4344 0173 01 .byte 0x1 + 4345 0174 03 .uleb128 0x3 + 4346 0175 0E .uleb128 0xe + 4347 0176 3A .uleb128 0x3a + 4348 0177 0B .uleb128 0xb + 4349 0178 3B .uleb128 0x3b + 4350 0179 05 .uleb128 0x5 + 4351 017a 27 .uleb128 0x27 + 4352 017b 19 .uleb128 0x19 + 4353 017c 11 .uleb128 0x11 + 4354 017d 01 .uleb128 0x1 + 4355 017e 12 .uleb128 0x12 + 4356 017f 06 .uleb128 0x6 + 4357 0180 40 .uleb128 0x40 + 4358 0181 18 .uleb128 0x18 + 4359 0182 9742 .uleb128 0x2117 + 4360 0184 19 .uleb128 0x19 + 4361 0185 01 .uleb128 0x1 + 4362 0186 13 .uleb128 0x13 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 103 + + + 4363 0187 00 .byte 0 + 4364 0188 00 .byte 0 + 4365 0189 1C .uleb128 0x1c + 4366 018a 2E .uleb128 0x2e + 4367 018b 01 .byte 0x1 + 4368 018c 03 .uleb128 0x3 + 4369 018d 0E .uleb128 0xe + 4370 018e 3A .uleb128 0x3a + 4371 018f 0B .uleb128 0xb + 4372 0190 3B .uleb128 0x3b + 4373 0191 05 .uleb128 0x5 + 4374 0192 27 .uleb128 0x27 + 4375 0193 19 .uleb128 0x19 + 4376 0194 49 .uleb128 0x49 + 4377 0195 13 .uleb128 0x13 + 4378 0196 11 .uleb128 0x11 + 4379 0197 01 .uleb128 0x1 + 4380 0198 12 .uleb128 0x12 + 4381 0199 06 .uleb128 0x6 + 4382 019a 40 .uleb128 0x40 + 4383 019b 18 .uleb128 0x18 + 4384 019c 9742 .uleb128 0x2117 + 4385 019e 19 .uleb128 0x19 + 4386 019f 01 .uleb128 0x1 + 4387 01a0 13 .uleb128 0x13 + 4388 01a1 00 .byte 0 + 4389 01a2 00 .byte 0 + 4390 01a3 1D .uleb128 0x1d + 4391 01a4 05 .uleb128 0x5 + 4392 01a5 00 .byte 0 + 4393 01a6 03 .uleb128 0x3 + 4394 01a7 08 .uleb128 0x8 + 4395 01a8 3A .uleb128 0x3a + 4396 01a9 0B .uleb128 0xb + 4397 01aa 3B .uleb128 0x3b + 4398 01ab 05 .uleb128 0x5 + 4399 01ac 49 .uleb128 0x49 + 4400 01ad 13 .uleb128 0x13 + 4401 01ae 02 .uleb128 0x2 + 4402 01af 18 .uleb128 0x18 + 4403 01b0 00 .byte 0 + 4404 01b1 00 .byte 0 + 4405 01b2 1E .uleb128 0x1e + 4406 01b3 2E .uleb128 0x2e + 4407 01b4 01 .byte 0x1 + 4408 01b5 03 .uleb128 0x3 + 4409 01b6 0E .uleb128 0xe + 4410 01b7 3A .uleb128 0x3a + 4411 01b8 0B .uleb128 0xb + 4412 01b9 3B .uleb128 0x3b + 4413 01ba 05 .uleb128 0x5 + 4414 01bb 27 .uleb128 0x27 + 4415 01bc 19 .uleb128 0x19 + 4416 01bd 49 .uleb128 0x49 + 4417 01be 13 .uleb128 0x13 + 4418 01bf 11 .uleb128 0x11 + 4419 01c0 01 .uleb128 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 104 + + + 4420 01c1 12 .uleb128 0x12 + 4421 01c2 06 .uleb128 0x6 + 4422 01c3 40 .uleb128 0x40 + 4423 01c4 18 .uleb128 0x18 + 4424 01c5 9642 .uleb128 0x2116 + 4425 01c7 19 .uleb128 0x19 + 4426 01c8 01 .uleb128 0x1 + 4427 01c9 13 .uleb128 0x13 + 4428 01ca 00 .byte 0 + 4429 01cb 00 .byte 0 + 4430 01cc 1F .uleb128 0x1f + 4431 01cd 2E .uleb128 0x2e + 4432 01ce 01 .byte 0x1 + 4433 01cf 03 .uleb128 0x3 + 4434 01d0 0E .uleb128 0xe + 4435 01d1 3A .uleb128 0x3a + 4436 01d2 0B .uleb128 0xb + 4437 01d3 3B .uleb128 0x3b + 4438 01d4 05 .uleb128 0x5 + 4439 01d5 27 .uleb128 0x27 + 4440 01d6 19 .uleb128 0x19 + 4441 01d7 49 .uleb128 0x49 + 4442 01d8 13 .uleb128 0x13 + 4443 01d9 11 .uleb128 0x11 + 4444 01da 01 .uleb128 0x1 + 4445 01db 12 .uleb128 0x12 + 4446 01dc 06 .uleb128 0x6 + 4447 01dd 40 .uleb128 0x40 + 4448 01de 18 .uleb128 0x18 + 4449 01df 9642 .uleb128 0x2116 + 4450 01e1 19 .uleb128 0x19 + 4451 01e2 00 .byte 0 + 4452 01e3 00 .byte 0 + 4453 01e4 00 .byte 0 + 4454 .section .debug_aranges,"",%progbits + 4455 0000 8C000000 .4byte 0x8c + 4456 0004 0200 .2byte 0x2 + 4457 0006 00000000 .4byte .Ldebug_info0 + 4458 000a 04 .byte 0x4 + 4459 000b 00 .byte 0 + 4460 000c 0000 .2byte 0 + 4461 000e 0000 .2byte 0 + 4462 0010 00000000 .4byte .LFB0 + 4463 0014 F6000000 .4byte .LFE0-.LFB0 + 4464 0018 00000000 .4byte .LFB1 + 4465 001c 2A030000 .4byte .LFE1-.LFB1 + 4466 0020 00000000 .4byte .LFB2 + 4467 0024 32030000 .4byte .LFE2-.LFB2 + 4468 0028 00000000 .4byte .LFB3 + 4469 002c FE000000 .4byte .LFE3-.LFB3 + 4470 0030 00000000 .4byte .LFB4 + 4471 0034 16000000 .4byte .LFE4-.LFB4 + 4472 0038 00000000 .4byte .LFB5 + 4473 003c 66000000 .4byte .LFE5-.LFB5 + 4474 0040 00000000 .4byte .LFB6 + 4475 0044 3C000000 .4byte .LFE6-.LFB6 + 4476 0048 00000000 .4byte .LFB7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 105 + + + 4477 004c B0000000 .4byte .LFE7-.LFB7 + 4478 0050 00000000 .4byte .LFB8 + 4479 0054 AE000000 .4byte .LFE8-.LFB8 + 4480 0058 00000000 .4byte .LFB9 + 4481 005c 6A000000 .4byte .LFE9-.LFB9 + 4482 0060 00000000 .4byte .LFB10 + 4483 0064 4A000000 .4byte .LFE10-.LFB10 + 4484 0068 00000000 .4byte .LFB11 + 4485 006c 80000000 .4byte .LFE11-.LFB11 + 4486 0070 00000000 .4byte .LFB12 + 4487 0074 E0000000 .4byte .LFE12-.LFB12 + 4488 0078 00000000 .4byte .LFB13 + 4489 007c F6000000 .4byte .LFE13-.LFB13 + 4490 0080 00000000 .4byte .LFB14 + 4491 0084 F4000000 .4byte .LFE14-.LFB14 + 4492 0088 00000000 .4byte 0 + 4493 008c 00000000 .4byte 0 + 4494 .section .debug_ranges,"",%progbits + 4495 .Ldebug_ranges0: + 4496 0000 70000000 .4byte .LBB7 + 4497 0004 00030000 .4byte .LBE7 + 4498 0008 22030000 .4byte .LBB9 + 4499 000c 24030000 .4byte .LBE9 + 4500 0010 00000000 .4byte 0 + 4501 0014 00000000 .4byte 0 + 4502 0018 00000000 .4byte .LFB0 + 4503 001c F6000000 .4byte .LFE0 + 4504 0020 00000000 .4byte .LFB1 + 4505 0024 2A030000 .4byte .LFE1 + 4506 0028 00000000 .4byte .LFB2 + 4507 002c 32030000 .4byte .LFE2 + 4508 0030 00000000 .4byte .LFB3 + 4509 0034 FE000000 .4byte .LFE3 + 4510 0038 00000000 .4byte .LFB4 + 4511 003c 16000000 .4byte .LFE4 + 4512 0040 00000000 .4byte .LFB5 + 4513 0044 66000000 .4byte .LFE5 + 4514 0048 00000000 .4byte .LFB6 + 4515 004c 3C000000 .4byte .LFE6 + 4516 0050 00000000 .4byte .LFB7 + 4517 0054 B0000000 .4byte .LFE7 + 4518 0058 00000000 .4byte .LFB8 + 4519 005c AE000000 .4byte .LFE8 + 4520 0060 00000000 .4byte .LFB9 + 4521 0064 6A000000 .4byte .LFE9 + 4522 0068 00000000 .4byte .LFB10 + 4523 006c 4A000000 .4byte .LFE10 + 4524 0070 00000000 .4byte .LFB11 + 4525 0074 80000000 .4byte .LFE11 + 4526 0078 00000000 .4byte .LFB12 + 4527 007c E0000000 .4byte .LFE12 + 4528 0080 00000000 .4byte .LFB13 + 4529 0084 F6000000 .4byte .LFE13 + 4530 0088 00000000 .4byte .LFB14 + 4531 008c F4000000 .4byte .LFE14 + 4532 0090 00000000 .4byte 0 + 4533 0094 00000000 .4byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 106 + + + 4534 .section .debug_line,"",%progbits + 4535 .Ldebug_line0: + 4536 0000 E3040000 .section .debug_str,"MS",%progbits,1 + 4536 02005B00 + 4536 00000201 + 4536 FB0E0D00 + 4536 01010101 + 4537 .LASF10: + 4538 0000 75696E74 .ascii "uint16\000" + 4538 313600 + 4539 .LASF79: + 4540 0007 726F7754 .ascii "rowToWrPtr\000" + 4540 6F577250 + 4540 747200 + 4541 .LASF66: + 4542 0012 746D7044 .ascii "tmpData\000" + 4542 61746100 + 4543 .LASF33: + 4544 001a 63795F65 .ascii "cy_en_em_eeprom_status_t\000" + 4544 6E5F656D + 4544 5F656570 + 4544 726F6D5F + 4544 73746174 + 4545 .LASF76: + 4546 0033 656D4565 .ascii "emEepromAddr\000" + 4546 70726F6D + 4546 41646472 + 4546 00 + 4547 .LASF91: + 4548 0040 64737441 .ascii "dstAddr\000" + 4548 64647200 + 4549 .LASF97: + 4550 0048 726F774E .ascii "rowNum\000" + 4550 756D00 + 4551 .LASF25: + 4552 004f 6E756D62 .ascii "numberOfRows\000" + 4552 65724F66 + 4552 526F7773 + 4552 00 + 4553 .LASF67: + 4554 005c 6E756D57 .ascii "numWrites\000" + 4554 72697465 + 4554 7300 + 4555 .LASF7: + 4556 0066 6C6F6E67 .ascii "long long unsigned int\000" + 4556 206C6F6E + 4556 6720756E + 4556 7369676E + 4556 65642069 + 4557 .LASF38: + 4558 007d 61646472 .ascii "addr\000" + 4558 00 + 4559 .LASF18: + 4560 0082 65657072 .ascii "eepromSize\000" + 4560 6F6D5369 + 4560 7A6500 + 4561 .LASF6: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 107 + + + 4562 008d 6C6F6E67 .ascii "long long int\000" + 4562 206C6F6E + 4562 6720696E + 4562 7400 + 4563 .LASF0: + 4564 009b 7369676E .ascii "signed char\000" + 4564 65642063 + 4564 68617200 + 4565 .LASF85: + 4566 00a7 57726974 .ascii "WriteRow\000" + 4566 65526F77 + 4566 00 + 4567 .LASF77: + 4568 00b0 46696E64 .ascii "FindLastWrittenRow\000" + 4568 4C617374 + 4568 57726974 + 4568 74656E52 + 4568 6F7700 + 4569 .LASF102: + 4570 00c3 47656E65 .ascii "Generated_Source\\PSoC4\\cy_em_eeprom.c\000" + 4570 72617465 + 4570 645F536F + 4570 75726365 + 4570 5C50536F + 4571 .LASF32: + 4572 00e9 43595F45 .ascii "CY_EM_EEPROM_WRITE_FAIL\000" + 4572 4D5F4545 + 4572 50524F4D + 4572 5F575249 + 4572 54455F46 + 4573 .LASF72: + 4574 0101 43795F45 .ascii "Cy_Em_EEPROM_NumWrites\000" + 4574 6D5F4545 + 4574 50524F4D + 4574 5F4E756D + 4574 57726974 + 4575 .LASF4: + 4576 0118 6C6F6E67 .ascii "long int\000" + 4576 20696E74 + 4576 00 + 4577 .LASF22: + 4578 0121 75736572 .ascii "userFlashStartAddr\000" + 4578 466C6173 + 4578 68537461 + 4578 72744164 + 4578 647200 + 4579 .LASF9: + 4580 0134 75696E74 .ascii "uint8\000" + 4580 3800 + 4581 .LASF13: + 4582 013a 646F7562 .ascii "double\000" + 4582 6C6500 + 4583 .LASF73: + 4584 0141 6C617374 .ascii "lastWrRowPtr\000" + 4584 5772526F + 4584 77507472 + 4584 00 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccT1bflm.s page 108 + + + 4585 .LASF11: + 4586 014e 75696E74 .ascii "uint32\000" + 4586 333200 + 4587 .LASF45: + 4588 0155 61637445 .ascii "actEepromRowNum\000" + 4588 6570726F + 4588 6D526F77 + 4588 4E756D00 + 4589 .LASF68: + 4590 0165 65654865 .ascii "eeHeaderDataOffset\000" + 4590 61646572 + 4590 44617461 + 4590 4F666673 + 4590 657400 + 4591 .LASF103: + 4592 0178 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 4592 73657273 + 4592 5C6A6167 + 4592 756D6965 + 4592 6C5C446F + 4593 01a6 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 4593 50536F43 + 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z3;hhHx`MdM1@$0qz);Z~D^7cE~l)SW0Hf4VK zP8y%Q_fHC^y->*JP`I^cdvm0-y$e$y>%rDmd=pi(pj+_CnxA1)I$Yj@Pm5t&1!h)M zv~_jx?+vNF+VKYg2;o~^MKF5`ds+g`YhB_^=$@Y@fGxiAeXA|8R%<48}-pITi-*dr|R2}vs^X+ zSSZKx0Dh_Z=$s#I)R&E)t?y~n)AYfZ7j1U2^^Kw-Rqi>+acp+6<=#OrOWNhTKK>=k z5uB42=EN>G?}-e32cYi}oVnD;J;ff!a~b+(!WiG*>|$5HpCR|LPlyAy5YU!;0hQGF zdGQiG2tMu3!Oyn)W`@2m!KtUfw~MXsjSPKHL0tiXGdtpq%~`u_p2ra=Dy literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyfitter_cfg.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyfitter_cfg.lst new file mode 100644 index 0000000..6c997fa --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyfitter_cfg.lst @@ -0,0 +1,1677 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "cyfitter_cfg.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.CYMEMZERO,"ax",%progbits + 20 .align 2 + 21 .code 16 + 22 .thumb_func + 23 .type CYMEMZERO, %function + 24 CYMEMZERO: + 25 .LFB0: + 26 .file 1 "Generated_Source\\PSoC4\\cyfitter_cfg.c" + 1:Generated_Source\PSoC4/cyfitter_cfg.c **** + 2:Generated_Source\PSoC4/cyfitter_cfg.c **** /******************************************************************************* + 3:Generated_Source\PSoC4/cyfitter_cfg.c **** * File Name: cyfitter_cfg.c + 4:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 5:Generated_Source\PSoC4/cyfitter_cfg.c **** * PSoC Creator 4.2 + 6:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 7:Generated_Source\PSoC4/cyfitter_cfg.c **** * Description: + 8:Generated_Source\PSoC4/cyfitter_cfg.c **** * This file contains device initialization code. + 9:Generated_Source\PSoC4/cyfitter_cfg.c **** * Except for the user defined sections in CyClockStartupError(), this file should not be modified. + 10:Generated_Source\PSoC4/cyfitter_cfg.c **** * This file is automatically generated by PSoC Creator. + 11:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 12:Generated_Source\PSoC4/cyfitter_cfg.c **** ******************************************************************************** + 13:Generated_Source\PSoC4/cyfitter_cfg.c **** * Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. + 14:Generated_Source\PSoC4/cyfitter_cfg.c **** * You may use this file only in accordance with the license, terms, conditions, + 15:Generated_Source\PSoC4/cyfitter_cfg.c **** * disclaimers, and limitations in the end user license agreement accompanying + 16:Generated_Source\PSoC4/cyfitter_cfg.c **** * the software package with which this file was provided. + 17:Generated_Source\PSoC4/cyfitter_cfg.c **** ********************************************************************************/ + 18:Generated_Source\PSoC4/cyfitter_cfg.c **** + 19:Generated_Source\PSoC4/cyfitter_cfg.c **** #include + 20:Generated_Source\PSoC4/cyfitter_cfg.c **** #include "cytypes.h" + 21:Generated_Source\PSoC4/cyfitter_cfg.c **** #include "cydevice_trm.h" + 22:Generated_Source\PSoC4/cyfitter_cfg.c **** #include "cyfitter.h" + 23:Generated_Source\PSoC4/cyfitter_cfg.c **** #include "CyLib.h" + 24:Generated_Source\PSoC4/cyfitter_cfg.c **** #include "cyfitter_cfg.h" + 25:Generated_Source\PSoC4/cyfitter_cfg.c **** #include "cyapicallbacks.h" + 26:Generated_Source\PSoC4/cyfitter_cfg.c **** + 27:Generated_Source\PSoC4/cyfitter_cfg.c **** + 28:Generated_Source\PSoC4/cyfitter_cfg.c **** #if defined(__GNUC__) || defined(__ARMCC_VERSION) + 29:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYPACKED + 30:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYPACKED_ATTR __attribute__ ((packed)) + 31:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYALIGNED __attribute__ ((aligned)) + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 2 + + + 32:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CY_CFG_UNUSED __attribute__ ((unused)) + 33:Generated_Source\PSoC4/cyfitter_cfg.c **** #ifndef CY_CFG_SECTION + 34:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + 35:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 36:Generated_Source\PSoC4/cyfitter_cfg.c **** + 37:Generated_Source\PSoC4/cyfitter_cfg.c **** #if defined(__ARMCC_VERSION) + 38:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CY_CFG_MEMORY_BARRIER() __memory_changed() + 39:Generated_Source\PSoC4/cyfitter_cfg.c **** #else + 40:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + 41:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 42:Generated_Source\PSoC4/cyfitter_cfg.c **** + 43:Generated_Source\PSoC4/cyfitter_cfg.c **** #elif defined(__ICCARM__) + 44:Generated_Source\PSoC4/cyfitter_cfg.c **** #include + 45:Generated_Source\PSoC4/cyfitter_cfg.c **** + 46:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYPACKED __packed + 47:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYPACKED_ATTR + 48:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYALIGNED _Pragma("data_alignment=4") + 49:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + 50:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + 51:Generated_Source\PSoC4/cyfitter_cfg.c **** + 52:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CY_CFG_MEMORY_BARRIER() __DMB() + 53:Generated_Source\PSoC4/cyfitter_cfg.c **** + 54:Generated_Source\PSoC4/cyfitter_cfg.c **** #else + 55:Generated_Source\PSoC4/cyfitter_cfg.c **** #error Unsupported toolchain + 56:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 57:Generated_Source\PSoC4/cyfitter_cfg.c **** + 58:Generated_Source\PSoC4/cyfitter_cfg.c **** #ifndef CYCODE + 59:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYCODE + 60:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 61:Generated_Source\PSoC4/cyfitter_cfg.c **** #ifndef CYDATA + 62:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYDATA + 63:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 64:Generated_Source\PSoC4/cyfitter_cfg.c **** #ifndef CYFAR + 65:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYFAR + 66:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 67:Generated_Source\PSoC4/cyfitter_cfg.c **** #ifndef CYXDATA + 68:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYXDATA + 69:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 70:Generated_Source\PSoC4/cyfitter_cfg.c **** + 71:Generated_Source\PSoC4/cyfitter_cfg.c **** + 72:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 73:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CYMEMZERO(void *s, size_t n); + 74:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 75:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CYMEMZERO(void *s, size_t n) + 76:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 27 .loc 1 76 0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 8 + 30 @ frame_needed = 1, uses_anonymous_args = 0 + 31 0000 80B5 push {r7, lr} + 32 .cfi_def_cfa_offset 8 + 33 .cfi_offset 7, -8 + 34 .cfi_offset 14, -4 + 35 0002 82B0 sub sp, sp, #8 + 36 .cfi_def_cfa_offset 16 + 37 0004 00AF add r7, sp, #0 + 38 .cfi_def_cfa_register 7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 3 + + + 39 0006 7860 str r0, [r7, #4] + 40 0008 3960 str r1, [r7] + 77:Generated_Source\PSoC4/cyfitter_cfg.c **** (void)memset(s, 0, n); + 41 .loc 1 77 0 + 42 000a 3A68 ldr r2, [r7] + 43 000c 7B68 ldr r3, [r7, #4] + 44 000e 0021 movs r1, #0 + 45 0010 1800 movs r0, r3 + 46 0012 FFF7FEFF bl memset + 78:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 47 .loc 1 78 0 + 48 0016 C046 nop + 49 0018 BD46 mov sp, r7 + 50 001a 02B0 add sp, sp, #8 + 51 @ sp needed + 52 001c 80BD pop {r7, pc} + 53 .cfi_endproc + 54 .LFE0: + 55 .size CYMEMZERO, .-CYMEMZERO + 56 001e C046 .section .text.CYCONFIGCPY,"ax",%progbits + 57 .align 2 + 58 .code 16 + 59 .thumb_func + 60 .type CYCONFIGCPY, %function + 61 CYCONFIGCPY: + 62 .LFB1: + 79:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 80:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CYCONFIGCPY(void *dest, const void *src, size_t n); + 81:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 82:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CYCONFIGCPY(void *dest, const void *src, size_t n) + 83:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 63 .loc 1 83 0 + 64 .cfi_startproc + 65 @ args = 0, pretend = 0, frame = 16 + 66 @ frame_needed = 1, uses_anonymous_args = 0 + 67 0000 80B5 push {r7, lr} + 68 .cfi_def_cfa_offset 8 + 69 .cfi_offset 7, -8 + 70 .cfi_offset 14, -4 + 71 0002 84B0 sub sp, sp, #16 + 72 .cfi_def_cfa_offset 24 + 73 0004 00AF add r7, sp, #0 + 74 .cfi_def_cfa_register 7 + 75 0006 F860 str r0, [r7, #12] + 76 0008 B960 str r1, [r7, #8] + 77 000a 7A60 str r2, [r7, #4] + 84:Generated_Source\PSoC4/cyfitter_cfg.c **** (void)memcpy(dest, src, n); + 78 .loc 1 84 0 + 79 000c 7A68 ldr r2, [r7, #4] + 80 000e B968 ldr r1, [r7, #8] + 81 0010 FB68 ldr r3, [r7, #12] + 82 0012 1800 movs r0, r3 + 83 0014 FFF7FEFF bl memcpy + 85:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 84 .loc 1 85 0 + 85 0018 C046 nop + 86 001a BD46 mov sp, r7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 4 + + + 87 001c 04B0 add sp, sp, #16 + 88 @ sp needed + 89 001e 80BD pop {r7, pc} + 90 .cfi_endproc + 91 .LFE1: + 92 .size CYCONFIGCPY, .-CYCONFIGCPY + 93 .section .text.CYCONFIGCPYCODE,"ax",%progbits + 94 .align 2 + 95 .code 16 + 96 .thumb_func + 97 .type CYCONFIGCPYCODE, %function + 98 CYCONFIGCPYCODE: + 99 .LFB2: + 86:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 87:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); + 88:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 89:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) + 90:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 100 .loc 1 90 0 + 101 .cfi_startproc + 102 @ args = 0, pretend = 0, frame = 16 + 103 @ frame_needed = 1, uses_anonymous_args = 0 + 104 0000 80B5 push {r7, lr} + 105 .cfi_def_cfa_offset 8 + 106 .cfi_offset 7, -8 + 107 .cfi_offset 14, -4 + 108 0002 84B0 sub sp, sp, #16 + 109 .cfi_def_cfa_offset 24 + 110 0004 00AF add r7, sp, #0 + 111 .cfi_def_cfa_register 7 + 112 0006 F860 str r0, [r7, #12] + 113 0008 B960 str r1, [r7, #8] + 114 000a 7A60 str r2, [r7, #4] + 91:Generated_Source\PSoC4/cyfitter_cfg.c **** (void)memcpy(dest, src, n); + 115 .loc 1 91 0 + 116 000c 7A68 ldr r2, [r7, #4] + 117 000e B968 ldr r1, [r7, #8] + 118 0010 FB68 ldr r3, [r7, #12] + 119 0012 1800 movs r0, r3 + 120 0014 FFF7FEFF bl memcpy + 92:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 121 .loc 1 92 0 + 122 0018 C046 nop + 123 001a BD46 mov sp, r7 + 124 001c 04B0 add sp, sp, #16 + 125 @ sp needed + 126 001e 80BD pop {r7, pc} + 127 .cfi_endproc + 128 .LFE2: + 129 .size CYCONFIGCPYCODE, .-CYCONFIGCPYCODE + 130 .section .psocinit,"ax",%progbits + 131 .align 2 + 132 .code 16 + 133 .thumb_func + 134 .type ClockSetup, %function + 135 ClockSetup: + 136 .LFB3: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 5 + + + 93:Generated_Source\PSoC4/cyfitter_cfg.c **** + 94:Generated_Source\PSoC4/cyfitter_cfg.c **** + 95:Generated_Source\PSoC4/cyfitter_cfg.c **** + 96:Generated_Source\PSoC4/cyfitter_cfg.c **** + 97:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Clock startup error codes */ + 98:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYCLOCKSTART_NO_ERROR 0u + 99:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYCLOCKSTART_XTAL_ERROR 1u + 100:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYCLOCKSTART_32KHZ_ERROR 2u + 101:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYCLOCKSTART_PLL_ERROR 3u + 102:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYCLOCKSTART_FLL_ERROR 4u + 103:Generated_Source\PSoC4/cyfitter_cfg.c **** #define CYCLOCKSTART_WCO_ERROR 5u + 104:Generated_Source\PSoC4/cyfitter_cfg.c **** + 105:Generated_Source\PSoC4/cyfitter_cfg.c **** + 106:Generated_Source\PSoC4/cyfitter_cfg.c **** #ifdef CY_NEED_CYCLOCKSTARTUPERROR + 107:Generated_Source\PSoC4/cyfitter_cfg.c **** /******************************************************************************* + 108:Generated_Source\PSoC4/cyfitter_cfg.c **** * Function Name: CyClockStartupError + 109:Generated_Source\PSoC4/cyfitter_cfg.c **** ******************************************************************************** + 110:Generated_Source\PSoC4/cyfitter_cfg.c **** * Summary: + 111:Generated_Source\PSoC4/cyfitter_cfg.c **** * If an error is encountered during clock configuration (crystal startup error, + 112:Generated_Source\PSoC4/cyfitter_cfg.c **** * PLL lock error, etc.), the system will end up here. Unless reimplemented by + 113:Generated_Source\PSoC4/cyfitter_cfg.c **** * the customer, this function will stop in an infinite loop. + 114:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 115:Generated_Source\PSoC4/cyfitter_cfg.c **** * Parameters: + 116:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 117:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 118:Generated_Source\PSoC4/cyfitter_cfg.c **** * Return: + 119:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 120:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 121:Generated_Source\PSoC4/cyfitter_cfg.c **** *******************************************************************************/ + 122:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 123:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CyClockStartupError(uint8 errorCode); + 124:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_UNUSED + 125:Generated_Source\PSoC4/cyfitter_cfg.c **** static void CyClockStartupError(uint8 errorCode) + 126:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 127:Generated_Source\PSoC4/cyfitter_cfg.c **** /* To remove the compiler warning if errorCode not used. */ + 128:Generated_Source\PSoC4/cyfitter_cfg.c **** errorCode = errorCode; + 129:Generated_Source\PSoC4/cyfitter_cfg.c **** + 130:Generated_Source\PSoC4/cyfitter_cfg.c **** /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + 131:Generated_Source\PSoC4/cyfitter_cfg.c **** /* we will end up here to allow the customer to implement something to */ + 132:Generated_Source\PSoC4/cyfitter_cfg.c **** /* deal with the clock condition. */ + 133:Generated_Source\PSoC4/cyfitter_cfg.c **** + 134:Generated_Source\PSoC4/cyfitter_cfg.c **** #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + 135:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_Clock_Startup_ErrorCallback(); + 136:Generated_Source\PSoC4/cyfitter_cfg.c **** #else + 137:Generated_Source\PSoC4/cyfitter_cfg.c **** /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + 138:Generated_Source\PSoC4/cyfitter_cfg.c **** /* `#START CyClockStartupError` */ + 139:Generated_Source\PSoC4/cyfitter_cfg.c **** + 140:Generated_Source\PSoC4/cyfitter_cfg.c **** + 141:Generated_Source\PSoC4/cyfitter_cfg.c **** + 142:Generated_Source\PSoC4/cyfitter_cfg.c **** /* `#END` */ + 143:Generated_Source\PSoC4/cyfitter_cfg.c **** + 144:Generated_Source\PSoC4/cyfitter_cfg.c **** while(1) {} + 145:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ + 146:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 147:Generated_Source\PSoC4/cyfitter_cfg.c **** #endif + 148:Generated_Source\PSoC4/cyfitter_cfg.c **** + 149:Generated_Source\PSoC4/cyfitter_cfg.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 6 + + + 150:Generated_Source\PSoC4/cyfitter_cfg.c **** + 151:Generated_Source\PSoC4/cyfitter_cfg.c **** /******************************************************************************* + 152:Generated_Source\PSoC4/cyfitter_cfg.c **** * Function Name: ClockSetup + 153:Generated_Source\PSoC4/cyfitter_cfg.c **** ******************************************************************************** + 154:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 155:Generated_Source\PSoC4/cyfitter_cfg.c **** * Summary: + 156:Generated_Source\PSoC4/cyfitter_cfg.c **** * Performs the initialization of all of the clocks in the device based on the + 157:Generated_Source\PSoC4/cyfitter_cfg.c **** * settings in the Clock tab of the DWR. This includes enabling the requested + 158:Generated_Source\PSoC4/cyfitter_cfg.c **** * clocks and setting the necessary dividers to produce the desired frequency. + 159:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 160:Generated_Source\PSoC4/cyfitter_cfg.c **** * Parameters: + 161:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 162:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 163:Generated_Source\PSoC4/cyfitter_cfg.c **** * Return: + 164:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 165:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 166:Generated_Source\PSoC4/cyfitter_cfg.c **** *******************************************************************************/ + 167:Generated_Source\PSoC4/cyfitter_cfg.c **** static void ClockSetup(void); + 168:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_SECTION + 169:Generated_Source\PSoC4/cyfitter_cfg.c **** static void ClockSetup(void) + 170:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 137 .loc 1 170 0 + 138 .cfi_startproc + 139 @ args = 0, pretend = 0, frame = 0 + 140 @ frame_needed = 1, uses_anonymous_args = 0 + 141 0000 80B5 push {r7, lr} + 142 .cfi_def_cfa_offset 8 + 143 .cfi_offset 7, -8 + 144 .cfi_offset 14, -4 + 145 0002 00AF add r7, sp, #0 + 146 .cfi_def_cfa_register 7 + 171:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Enable HALF_EN before trimming for the flash accelerator. */ + 172:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040 + 147 .loc 1 172 0 + 148 0004 154B ldr r3, .L5 + 149 0006 154A ldr r2, .L5 + 150 0008 1268 ldr r2, [r2] + 151 000a 8021 movs r1, #128 + 152 000c C902 lsls r1, r1, #11 + 153 000e 0A43 orrs r2, r1 + 154 0010 1A60 str r2, [r3] + 173:Generated_Source\PSoC4/cyfitter_cfg.c **** + 174:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Setup and trim IMO based on desired frequency. */ + 175:Generated_Source\PSoC4/cyfitter_cfg.c **** CySysClkWriteImoFreq(24u); + 155 .loc 1 175 0 + 156 0012 1820 movs r0, #24 + 157 0014 FFF7FEFF bl CySysClkWriteImoFreq + 176:Generated_Source\PSoC4/cyfitter_cfg.c **** + 177:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Disable HALF_EN since it is not required at this IMO frequency. */ + 178:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBF + 158 .loc 1 178 0 + 159 0018 104B ldr r3, .L5 + 160 001a 104A ldr r2, .L5 + 161 001c 1268 ldr r2, [r2] + 162 001e 1049 ldr r1, .L5+4 + 163 0020 0A40 ands r2, r1 + 164 0022 1A60 str r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 7 + + + 179:Generated_Source\PSoC4/cyfitter_cfg.c **** /* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */ + 180:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_CLK_ILO_CONFIG), 0x80000006u); + 165 .loc 1 180 0 + 166 0024 0F4B ldr r3, .L5+8 + 167 0026 104A ldr r2, .L5+12 + 168 0028 1A60 str r2, [r3] + 181:Generated_Source\PSoC4/cyfitter_cfg.c **** + 182:Generated_Source\PSoC4/cyfitter_cfg.c **** + 183:Generated_Source\PSoC4/cyfitter_cfg.c **** /* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */ + 184:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_CLK_SELECT02), 0x00000020u); + 169 .loc 1 184 0 + 170 002a 104B ldr r3, .L5+16 + 171 002c 2022 movs r2, #32 + 172 002e 1A60 str r2, [r3] + 185:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_CLK_SELECT07), 0x00000010u); + 173 .loc 1 185 0 + 174 0030 0F4B ldr r3, .L5+20 + 175 0032 1022 movs r2, #16 + 176 0034 1A60 str r2, [r3] + 186:Generated_Source\PSoC4/cyfitter_cfg.c **** + 187:Generated_Source\PSoC4/cyfitter_cfg.c **** /* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */ + 188:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_CLK_IMO_CONFIG), 0x82000000u); + 177 .loc 1 188 0 + 178 0036 0F4B ldr r3, .L5+24 + 179 0038 8222 movs r2, #130 + 180 003a 1206 lsls r2, r2, #24 + 181 003c 1A60 str r2, [r3] + 189:Generated_Source\PSoC4/cyfitter_cfg.c **** + 190:Generated_Source\PSoC4/cyfitter_cfg.c **** /* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */ + 191:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_CLK_SELECT), 0x00000000u); + 182 .loc 1 191 0 + 183 003e 074B ldr r3, .L5 + 184 0040 0022 movs r2, #0 + 185 0042 1A60 str r2, [r3] + 192:Generated_Source\PSoC4/cyfitter_cfg.c **** + 193:Generated_Source\PSoC4/cyfitter_cfg.c **** /* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */ + 194:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_CLK_DIVIDER_A00), 0x80000017u); + 186 .loc 1 194 0 + 187 0044 0C4B ldr r3, .L5+28 + 188 0046 0D4A ldr r2, .L5+32 + 189 0048 1A60 str r2, [r3] + 195:Generated_Source\PSoC4/cyfitter_cfg.c **** + 196:Generated_Source\PSoC4/cyfitter_cfg.c **** /* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */ + 197:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_CLK_DIVIDER_B00), 0x80000138u); + 190 .loc 1 197 0 + 191 004a 0D4B ldr r3, .L5+36 + 192 004c 0D4A ldr r2, .L5+40 + 193 004e 1A60 str r2, [r3] + 198:Generated_Source\PSoC4/cyfitter_cfg.c **** + 199:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_WDT_CONFIG), 0x00000000u); + 194 .loc 1 199 0 + 195 0050 0D4B ldr r3, .L5+44 + 196 0052 0022 movs r2, #0 + 197 0054 1A60 str r2, [r3] + 200:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 198 .loc 1 200 0 + 199 0056 C046 nop + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 8 + + + 200 0058 BD46 mov sp, r7 + 201 @ sp needed + 202 005a 80BD pop {r7, pc} + 203 .L6: + 204 .align 2 + 205 .L5: + 206 005c 00010B40 .word 1074462976 + 207 0060 FFFFFBFF .word -262145 + 208 0064 04010B40 .word 1074462980 + 209 0068 06000080 .word -2147483642 + 210 006c 08020240 .word 1073873416 + 211 0070 1C020240 .word 1073873436 + 212 0074 08010B40 .word 1074462984 + 213 0078 00000240 .word 1073872896 + 214 007c 17000080 .word -2147483625 + 215 0080 40000240 .word 1073872960 + 216 0084 38010080 .word -2147483336 + 217 0088 0C020B40 .word 1074463244 + 218 .cfi_endproc + 219 .LFE3: + 220 .size ClockSetup, .-ClockSetup + 221 .section .text.AnalogSetDefault,"ax",%progbits + 222 .align 2 + 223 .code 16 + 224 .thumb_func + 225 .type AnalogSetDefault, %function + 226 AnalogSetDefault: + 227 .LFB4: + 201:Generated_Source\PSoC4/cyfitter_cfg.c **** + 202:Generated_Source\PSoC4/cyfitter_cfg.c **** + 203:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Analog API Functions */ + 204:Generated_Source\PSoC4/cyfitter_cfg.c **** + 205:Generated_Source\PSoC4/cyfitter_cfg.c **** + 206:Generated_Source\PSoC4/cyfitter_cfg.c **** /******************************************************************************* + 207:Generated_Source\PSoC4/cyfitter_cfg.c **** * Function Name: AnalogSetDefault + 208:Generated_Source\PSoC4/cyfitter_cfg.c **** ******************************************************************************** + 209:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 210:Generated_Source\PSoC4/cyfitter_cfg.c **** * Summary: + 211:Generated_Source\PSoC4/cyfitter_cfg.c **** * Sets up the analog portions of the chip to default values based on chip + 212:Generated_Source\PSoC4/cyfitter_cfg.c **** * configuration options from the project. + 213:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 214:Generated_Source\PSoC4/cyfitter_cfg.c **** * Parameters: + 215:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 216:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 217:Generated_Source\PSoC4/cyfitter_cfg.c **** * Return: + 218:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 219:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 220:Generated_Source\PSoC4/cyfitter_cfg.c **** *******************************************************************************/ + 221:Generated_Source\PSoC4/cyfitter_cfg.c **** static void AnalogSetDefault(void); + 222:Generated_Source\PSoC4/cyfitter_cfg.c **** static void AnalogSetDefault(void) + 223:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 228 .loc 1 223 0 + 229 .cfi_startproc + 230 @ args = 0, pretend = 0, frame = 0 + 231 @ frame_needed = 1, uses_anonymous_args = 0 + 232 0000 80B5 push {r7, lr} + 233 .cfi_def_cfa_offset 8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 9 + + + 234 .cfi_offset 7, -8 + 235 .cfi_offset 14, -4 + 236 0002 00AF add r7, sp, #0 + 237 .cfi_def_cfa_register 7 + 224:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_XTND_REG32((void CYFAR *)CYREG_SAR_MUX_SWITCH0, 0x00000008u); + 238 .loc 1 224 0 + 239 0004 024B ldr r3, .L8 + 240 0006 0822 movs r2, #8 + 241 0008 1A60 str r2, [r3] + 225:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 242 .loc 1 225 0 + 243 000a C046 nop + 244 000c BD46 mov sp, r7 + 245 @ sp needed + 246 000e 80BD pop {r7, pc} + 247 .L9: + 248 .align 2 + 249 .L8: + 250 0010 00031A40 .word 1075446528 + 251 .cfi_endproc + 252 .LFE4: + 253 .size AnalogSetDefault, .-AnalogSetDefault + 254 .section .psocinit + 255 .align 2 + 256 .global cyfitter_cfg + 257 .code 16 + 258 .thumb_func + 259 .type cyfitter_cfg, %function + 260 cyfitter_cfg: + 261 .LFB5: + 226:Generated_Source\PSoC4/cyfitter_cfg.c **** + 227:Generated_Source\PSoC4/cyfitter_cfg.c **** + 228:Generated_Source\PSoC4/cyfitter_cfg.c **** + 229:Generated_Source\PSoC4/cyfitter_cfg.c **** + 230:Generated_Source\PSoC4/cyfitter_cfg.c **** /******************************************************************************* + 231:Generated_Source\PSoC4/cyfitter_cfg.c **** * Function Name: cyfitter_cfg + 232:Generated_Source\PSoC4/cyfitter_cfg.c **** ******************************************************************************** + 233:Generated_Source\PSoC4/cyfitter_cfg.c **** * Summary: + 234:Generated_Source\PSoC4/cyfitter_cfg.c **** * This function is called by the start-up code for the selected device. It + 235:Generated_Source\PSoC4/cyfitter_cfg.c **** * performs all of the necessary device configuration based on the design + 236:Generated_Source\PSoC4/cyfitter_cfg.c **** * settings. This includes settings from the Design Wide Resources (DWR) such + 237:Generated_Source\PSoC4/cyfitter_cfg.c **** * as Clocks and Pins as well as any component configuration that is necessary. + 238:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 239:Generated_Source\PSoC4/cyfitter_cfg.c **** * Parameters: + 240:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 241:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 242:Generated_Source\PSoC4/cyfitter_cfg.c **** * Return: + 243:Generated_Source\PSoC4/cyfitter_cfg.c **** * void + 244:Generated_Source\PSoC4/cyfitter_cfg.c **** * + 245:Generated_Source\PSoC4/cyfitter_cfg.c **** *******************************************************************************/ + 246:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_CFG_SECTION + 247:Generated_Source\PSoC4/cyfitter_cfg.c **** void cyfitter_cfg(void) + 248:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 262 .loc 1 248 0 + 263 .cfi_startproc + 264 @ args = 0, pretend = 0, frame = 8 + 265 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 10 + + + 266 008c 80B5 push {r7, lr} + 267 .cfi_def_cfa_offset 8 + 268 .cfi_offset 7, -8 + 269 .cfi_offset 14, -4 + 270 008e 82B0 sub sp, sp, #8 + 271 .cfi_def_cfa_offset 16 + 272 0090 00AF add r7, sp, #0 + 273 .cfi_def_cfa_register 7 + 249:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Disable interrupts by default. Let user enable if/when they want. */ + 250:Generated_Source\PSoC4/cyfitter_cfg.c **** CyGlobalIntDisable; + 274 .loc 1 250 0 + 275 .syntax divided + 276 @ 250 "Generated_Source\PSoC4\cyfitter_cfg.c" 1 + 277 0092 72B6 CPSID i + 278 @ 0 "" 2 + 279 .thumb + 280 .syntax unified + 281 .LBB2: + 251:Generated_Source\PSoC4/cyfitter_cfg.c **** + 252:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 253:Generated_Source\PSoC4/cyfitter_cfg.c **** + 254:Generated_Source\PSoC4/cyfitter_cfg.c **** CYPACKED typedef struct { + 255:Generated_Source\PSoC4/cyfitter_cfg.c **** void CYFAR *address; + 256:Generated_Source\PSoC4/cyfitter_cfg.c **** uint16 size; + 257:Generated_Source\PSoC4/cyfitter_cfg.c **** } CYPACKED_ATTR cfg_memset_t; + 258:Generated_Source\PSoC4/cyfitter_cfg.c **** + 259:Generated_Source\PSoC4/cyfitter_cfg.c **** static const cfg_memset_t CYCODE cfg_memset_list[] = { + 260:Generated_Source\PSoC4/cyfitter_cfg.c **** /* address, size */ + 261:Generated_Source\PSoC4/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, + 262:Generated_Source\PSoC4/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, + 263:Generated_Source\PSoC4/cyfitter_cfg.c **** }; + 264:Generated_Source\PSoC4/cyfitter_cfg.c **** + 265:Generated_Source\PSoC4/cyfitter_cfg.c **** uint8 CYDATA i; + 266:Generated_Source\PSoC4/cyfitter_cfg.c **** + 267:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Zero out critical memory blocks before beginning configuration */ + 268:Generated_Source\PSoC4/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + 282 .loc 1 268 0 + 283 0094 FB1D adds r3, r7, #7 + 284 0096 0022 movs r2, #0 + 285 0098 1A70 strb r2, [r3] + 286 009a 22E0 b .L11 + 287 .L12: + 288 .LBB3: + 269:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 270:Generated_Source\PSoC4/cyfitter_cfg.c **** const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + 289 .loc 1 270 0 discriminator 3 + 290 009c FB1D adds r3, r7, #7 + 291 009e 1A78 ldrb r2, [r3] + 292 00a0 1300 movs r3, r2 + 293 00a2 5B00 lsls r3, r3, #1 + 294 00a4 9B18 adds r3, r3, r2 + 295 00a6 5B00 lsls r3, r3, #1 + 296 00a8 2E4A ldr r2, .L13 + 297 00aa 9B18 adds r3, r3, r2 + 298 00ac 3B60 str r3, [r7] + 271:Generated_Source\PSoC4/cyfitter_cfg.c **** CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); + 299 .loc 1 271 0 discriminator 3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 11 + + + 300 00ae 3B68 ldr r3, [r7] + 301 00b0 1A78 ldrb r2, [r3] + 302 00b2 5978 ldrb r1, [r3, #1] + 303 00b4 0902 lsls r1, r1, #8 + 304 00b6 0A43 orrs r2, r1 + 305 00b8 9978 ldrb r1, [r3, #2] + 306 00ba 0904 lsls r1, r1, #16 + 307 00bc 0A43 orrs r2, r1 + 308 00be DB78 ldrb r3, [r3, #3] + 309 00c0 1B06 lsls r3, r3, #24 + 310 00c2 1343 orrs r3, r2 + 311 00c4 1800 movs r0, r3 + 312 00c6 3B68 ldr r3, [r7] + 313 00c8 1A79 ldrb r2, [r3, #4] + 314 00ca 5B79 ldrb r3, [r3, #5] + 315 00cc 1B02 lsls r3, r3, #8 + 316 00ce 1343 orrs r3, r2 + 317 00d0 9BB2 uxth r3, r3 + 318 00d2 1900 movs r1, r3 + 319 00d4 FFF7FEFF bl CYMEMZERO + 320 .LBE3: + 268:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 321 .loc 1 268 0 discriminator 3 + 322 00d8 FB1D adds r3, r7, #7 + 323 00da 1A78 ldrb r2, [r3] + 324 00dc FB1D adds r3, r7, #7 + 325 00de 0132 adds r2, r2, #1 + 326 00e0 1A70 strb r2, [r3] + 327 .L11: + 268:Generated_Source\PSoC4/cyfitter_cfg.c **** { + 328 .loc 1 268 0 is_stmt 0 discriminator 1 + 329 00e2 FB1D adds r3, r7, #7 + 330 00e4 1B78 ldrb r3, [r3] + 331 00e6 012B cmp r3, #1 + 332 00e8 D8D9 bls .L12 + 272:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 273:Generated_Source\PSoC4/cyfitter_cfg.c **** + 274:Generated_Source\PSoC4/cyfitter_cfg.c **** /* HSIOM Starting address: CYDEV_HSIOM_BASE */ + 275:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); + 333 .loc 1 275 0 is_stmt 1 + 334 00ea 1F4B ldr r3, .L13+4 + 335 00ec EE22 movs r2, #238 + 336 00ee 1202 lsls r2, r2, #8 + 337 00f0 1A60 str r2, [r3] + 276:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL4), 0x00000090u); + 338 .loc 1 276 0 + 339 00f2 1E4B ldr r3, .L13+8 + 340 00f4 9022 movs r2, #144 + 341 00f6 1A60 str r2, [r3] + 277:Generated_Source\PSoC4/cyfitter_cfg.c **** + 278:Generated_Source\PSoC4/cyfitter_cfg.c **** /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ + 279:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYDEV_UDB_PA1_BASE), 0x00990000u); + 342 .loc 1 279 0 + 343 00f8 1D4B ldr r3, .L13+12 + 344 00fa 9922 movs r2, #153 + 345 00fc 1204 lsls r2, r2, #16 + 346 00fe 1A60 str r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 12 + + + 280:Generated_Source\PSoC4/cyfitter_cfg.c **** + 281:Generated_Source\PSoC4/cyfitter_cfg.c **** /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ + 282:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYDEV_UDB_PA2_BASE), 0x00990000u); + 347 .loc 1 282 0 + 348 0100 1C4B ldr r3, .L13+16 + 349 0102 9922 movs r2, #153 + 350 0104 1204 lsls r2, r2, #16 + 351 0106 1A60 str r2, [r3] + 283:Generated_Source\PSoC4/cyfitter_cfg.c **** + 284:Generated_Source\PSoC4/cyfitter_cfg.c **** /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ + 285:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYDEV_UDB_PA3_BASE), 0x00990000u); + 352 .loc 1 285 0 + 353 0108 1B4B ldr r3, .L13+20 + 354 010a 9922 movs r2, #153 + 355 010c 1204 lsls r2, r2, #16 + 356 010e 1A60 str r2, [r3] + 286:Generated_Source\PSoC4/cyfitter_cfg.c **** + 287:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Enable digital routing */ + 288:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDB + 357 .loc 1 288 0 + 358 0110 1A4A ldr r2, .L13+24 + 359 0112 1A4B ldr r3, .L13+24 + 360 0114 1B78 ldrb r3, [r3] + 361 0116 DBB2 uxtb r3, r3 + 362 0118 0621 movs r1, #6 + 363 011a 0B43 orrs r3, r1 + 364 011c DBB2 uxtb r3, r3 + 365 011e 1370 strb r3, [r2] + 366 .LBE2: + 289:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 290:Generated_Source\PSoC4/cyfitter_cfg.c **** + 291:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Perform second pass device configuration. These items must be configured in specific order afte + 292:Generated_Source\PSoC4/cyfitter_cfg.c **** /* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */ + 293:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYDEV_PRT1_BASE), 0x00000040u); + 367 .loc 1 293 0 + 368 0120 174B ldr r3, .L13+28 + 369 0122 4022 movs r2, #64 + 370 0124 1A60 str r2, [r3] + 294:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_PRT1_PC), 0x00100000u); + 371 .loc 1 294 0 + 372 0126 174B ldr r3, .L13+32 + 373 0128 8022 movs r2, #128 + 374 012a 5203 lsls r2, r2, #13 + 375 012c 1A60 str r2, [r3] + 295:Generated_Source\PSoC4/cyfitter_cfg.c **** + 296:Generated_Source\PSoC4/cyfitter_cfg.c **** /* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */ + 297:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYDEV_PRT2_BASE), 0x00000008u); + 376 .loc 1 297 0 + 377 012e 164B ldr r3, .L13+36 + 378 0130 0822 movs r2, #8 + 379 0132 1A60 str r2, [r3] + 298:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_PRT2_PC2), 0x00000008u); + 380 .loc 1 298 0 + 381 0134 154B ldr r3, .L13+40 + 382 0136 0822 movs r2, #8 + 383 0138 1A60 str r2, [r3] + 299:Generated_Source\PSoC4/cyfitter_cfg.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 13 + + + 300:Generated_Source\PSoC4/cyfitter_cfg.c **** /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ + 301:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_PRT3_PC), 0x00000D80u); + 384 .loc 1 301 0 + 385 013a 154B ldr r3, .L13+44 + 386 013c D822 movs r2, #216 + 387 013e 1201 lsls r2, r2, #4 + 388 0140 1A60 str r2, [r3] + 302:Generated_Source\PSoC4/cyfitter_cfg.c **** + 303:Generated_Source\PSoC4/cyfitter_cfg.c **** /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ + 304:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYDEV_PRT4_BASE), 0x00000002u); + 389 .loc 1 304 0 + 390 0142 144B ldr r3, .L13+48 + 391 0144 0222 movs r2, #2 + 392 0146 1A60 str r2, [r3] + 305:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_PRT4_PC), 0x00000030u); + 393 .loc 1 305 0 + 394 0148 134B ldr r3, .L13+52 + 395 014a 3022 movs r2, #48 + 396 014c 1A60 str r2, [r3] + 306:Generated_Source\PSoC4/cyfitter_cfg.c **** CY_SET_REG32((void *)(CYREG_PRT4_PC2), 0x00000002u); + 397 .loc 1 306 0 + 398 014e 134B ldr r3, .L13+56 + 399 0150 0222 movs r2, #2 + 400 0152 1A60 str r2, [r3] + 307:Generated_Source\PSoC4/cyfitter_cfg.c **** + 308:Generated_Source\PSoC4/cyfitter_cfg.c **** + 309:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Setup clocks based on selections from Clock DWR */ + 310:Generated_Source\PSoC4/cyfitter_cfg.c **** ClockSetup(); + 401 .loc 1 310 0 + 402 0154 FFF754FF bl ClockSetup + 311:Generated_Source\PSoC4/cyfitter_cfg.c **** + 312:Generated_Source\PSoC4/cyfitter_cfg.c **** /* Perform basic analog initialization to defaults */ + 313:Generated_Source\PSoC4/cyfitter_cfg.c **** AnalogSetDefault(); + 403 .loc 1 313 0 + 404 0158 FFF7FEFF bl AnalogSetDefault + 314:Generated_Source\PSoC4/cyfitter_cfg.c **** + 315:Generated_Source\PSoC4/cyfitter_cfg.c **** } + 405 .loc 1 315 0 + 406 015c C046 nop + 407 015e BD46 mov sp, r7 + 408 0160 02B0 add sp, sp, #8 + 409 @ sp needed + 410 0162 80BD pop {r7, pc} + 411 .L14: + 412 .align 2 + 413 .L13: + 414 0164 00000000 .word cfg_memset_list.4847 + 415 0168 0C000140 .word 1073807372 + 416 016c 10000140 .word 1073807376 + 417 0170 10500F40 .word 1074745360 + 418 0174 20500F40 .word 1074745376 + 419 0178 30500F40 .word 1074745392 + 420 017c 00700F40 .word 1074753536 + 421 0180 00010440 .word 1074004224 + 422 0184 08010440 .word 1074004232 + 423 0188 00020440 .word 1074004480 + 424 018c 18020440 .word 1074004504 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 14 + + + 425 0190 08030440 .word 1074004744 + 426 0194 00040440 .word 1074004992 + 427 0198 08040440 .word 1074005000 + 428 019c 18040440 .word 1074005016 + 429 .cfi_endproc + 430 .LFE5: + 431 .size cyfitter_cfg, .-cyfitter_cfg + 432 .section .rodata + 433 .align 2 + 434 .type cfg_memset_list.4847, %object + 435 .size cfg_memset_list.4847, 12 + 436 cfg_memset_list.4847: + 437 0000 00300F40 .word 1074737152 + 438 0004 0004 .short 1024 + 439 0006 00400F40 .4byte 1074741248 + 440 000a 0004 .short 1024 + 441 .text + 442 .Letext0: + 443 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\4.2\\psoc creator\\import\\gnu\\arm\\5.4. + 444 .file 3 "Generated_Source\\PSoC4\\cytypes.h" + 445 .section .debug_info,"",%progbits + 446 .Ldebug_info0: + 447 0000 52020000 .4byte 0x252 + 448 0004 0400 .2byte 0x4 + 449 0006 00000000 .4byte .Ldebug_abbrev0 + 450 000a 04 .byte 0x4 + 451 000b 01 .uleb128 0x1 + 452 000c DE000000 .4byte .LASF30 + 453 0010 0C .byte 0xc + 454 0011 1C020000 .4byte .LASF31 + 455 0015 4C000000 .4byte .LASF32 + 456 0019 00000000 .4byte .Ldebug_ranges0+0 + 457 001d 00000000 .4byte 0 + 458 0021 00000000 .4byte .Ldebug_line0 + 459 0025 02 .uleb128 0x2 + 460 0026 04 .byte 0x4 + 461 0027 05 .byte 0x5 + 462 0028 696E7400 .ascii "int\000" + 463 002c 03 .uleb128 0x3 + 464 002d 06000000 .4byte .LASF12 + 465 0031 02 .byte 0x2 + 466 0032 D8 .byte 0xd8 + 467 0033 37000000 .4byte 0x37 + 468 0037 04 .uleb128 0x4 + 469 0038 04 .byte 0x4 + 470 0039 07 .byte 0x7 + 471 003a 9C010000 .4byte .LASF0 + 472 003e 04 .uleb128 0x4 + 473 003f 08 .byte 0x8 + 474 0040 05 .byte 0x5 + 475 0041 DE010000 .4byte .LASF1 + 476 0045 04 .uleb128 0x4 + 477 0046 08 .byte 0x8 + 478 0047 04 .byte 0x4 + 479 0048 04020000 .4byte .LASF2 + 480 004c 04 .uleb128 0x4 + 481 004d 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 15 + + + 482 004e 06 .byte 0x6 + 483 004f 10020000 .4byte .LASF3 + 484 0053 04 .uleb128 0x4 + 485 0054 01 .byte 0x1 + 486 0055 08 .byte 0x8 + 487 0056 6C010000 .4byte .LASF4 + 488 005a 04 .uleb128 0x4 + 489 005b 02 .byte 0x2 + 490 005c 05 .byte 0x5 + 491 005d F1010000 .4byte .LASF5 + 492 0061 04 .uleb128 0x4 + 493 0062 02 .byte 0x2 + 494 0063 07 .byte 0x7 + 495 0064 39000000 .4byte .LASF6 + 496 0068 04 .uleb128 0x4 + 497 0069 04 .byte 0x4 + 498 006a 05 .byte 0x5 + 499 006b FB010000 .4byte .LASF7 + 500 006f 04 .uleb128 0x4 + 501 0070 04 .byte 0x4 + 502 0071 07 .byte 0x7 + 503 0072 BC000000 .4byte .LASF8 + 504 0076 04 .uleb128 0x4 + 505 0077 08 .byte 0x8 + 506 0078 07 .byte 0x7 + 507 0079 B1010000 .4byte .LASF9 + 508 007d 04 .uleb128 0x4 + 509 007e 04 .byte 0x4 + 510 007f 07 .byte 0x7 + 511 0080 D5010000 .4byte .LASF10 + 512 0084 05 .uleb128 0x5 + 513 0085 04 .byte 0x4 + 514 0086 04 .uleb128 0x4 + 515 0087 01 .byte 0x1 + 516 0088 08 .byte 0x8 + 517 0089 EC010000 .4byte .LASF11 + 518 008d 06 .uleb128 0x6 + 519 008e CE000000 .4byte .LASF13 + 520 0092 03 .byte 0x3 + 521 0093 E401 .2byte 0x1e4 + 522 0095 53000000 .4byte 0x53 + 523 0099 06 .uleb128 0x6 + 524 009a 8E010000 .4byte .LASF14 + 525 009e 03 .byte 0x3 + 526 009f E501 .2byte 0x1e5 + 527 00a1 61000000 .4byte 0x61 + 528 00a5 06 .uleb128 0x6 + 529 00a6 95010000 .4byte .LASF15 + 530 00aa 03 .byte 0x3 + 531 00ab E601 .2byte 0x1e6 + 532 00ad 6F000000 .4byte 0x6f + 533 00b1 04 .uleb128 0x4 + 534 00b2 04 .byte 0x4 + 535 00b3 04 .byte 0x4 + 536 00b4 A7000000 .4byte .LASF16 + 537 00b8 04 .uleb128 0x4 + 538 00b9 08 .byte 0x8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 16 + + + 539 00ba 04 .byte 0x4 + 540 00bb 7A010000 .4byte .LASF17 + 541 00bf 06 .uleb128 0x6 + 542 00c0 B7000000 .4byte .LASF18 + 543 00c4 03 .byte 0x3 + 544 00c5 8E02 .2byte 0x28e + 545 00c7 CB000000 .4byte 0xcb + 546 00cb 07 .uleb128 0x7 + 547 00cc 8D000000 .4byte 0x8d + 548 00d0 06 .uleb128 0x6 + 549 00d1 00000000 .4byte .LASF19 + 550 00d5 03 .byte 0x3 + 551 00d6 9002 .2byte 0x290 + 552 00d8 DC000000 .4byte 0xdc + 553 00dc 07 .uleb128 0x7 + 554 00dd A5000000 .4byte 0xa5 + 555 00e1 08 .uleb128 0x8 + 556 00e2 D4000000 .4byte .LASF20 + 557 00e6 01 .byte 0x1 + 558 00e7 4B .byte 0x4b + 559 00e8 00000000 .4byte .LFB0 + 560 00ec 1E000000 .4byte .LFE0-.LFB0 + 561 00f0 01 .uleb128 0x1 + 562 00f1 9C .byte 0x9c + 563 00f2 0F010000 .4byte 0x10f + 564 00f6 09 .uleb128 0x9 + 565 00f7 7300 .ascii "s\000" + 566 00f9 01 .byte 0x1 + 567 00fa 4B .byte 0x4b + 568 00fb 84000000 .4byte 0x84 + 569 00ff 02 .uleb128 0x2 + 570 0100 91 .byte 0x91 + 571 0101 74 .sleb128 -12 + 572 0102 09 .uleb128 0x9 + 573 0103 6E00 .ascii "n\000" + 574 0105 01 .byte 0x1 + 575 0106 4B .byte 0x4b + 576 0107 2C000000 .4byte 0x2c + 577 010b 02 .uleb128 0x2 + 578 010c 91 .byte 0x91 + 579 010d 70 .sleb128 -16 + 580 010e 00 .byte 0 + 581 010f 08 .uleb128 0x8 + 582 0110 52020000 .4byte .LASF21 + 583 0114 01 .byte 0x1 + 584 0115 52 .byte 0x52 + 585 0116 00000000 .4byte .LFB1 + 586 011a 20000000 .4byte .LFE1-.LFB1 + 587 011e 01 .uleb128 0x1 + 588 011f 9C .byte 0x9c + 589 0120 4D010000 .4byte 0x14d + 590 0124 0A .uleb128 0xa + 591 0125 AD000000 .4byte .LASF22 + 592 0129 01 .byte 0x1 + 593 012a 52 .byte 0x52 + 594 012b 84000000 .4byte 0x84 + 595 012f 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 17 + + + 596 0130 91 .byte 0x91 + 597 0131 74 .sleb128 -12 + 598 0132 09 .uleb128 0x9 + 599 0133 73726300 .ascii "src\000" + 600 0137 01 .byte 0x1 + 601 0138 52 .byte 0x52 + 602 0139 4D010000 .4byte 0x14d + 603 013d 02 .uleb128 0x2 + 604 013e 91 .byte 0x91 + 605 013f 70 .sleb128 -16 + 606 0140 09 .uleb128 0x9 + 607 0141 6E00 .ascii "n\000" + 608 0143 01 .byte 0x1 + 609 0144 52 .byte 0x52 + 610 0145 2C000000 .4byte 0x2c + 611 0149 02 .uleb128 0x2 + 612 014a 91 .byte 0x91 + 613 014b 6C .sleb128 -20 + 614 014c 00 .byte 0 + 615 014d 0B .uleb128 0xb + 616 014e 04 .byte 0x4 + 617 014f 53010000 .4byte 0x153 + 618 0153 0C .uleb128 0xc + 619 0154 08 .uleb128 0x8 + 620 0155 42020000 .4byte .LASF23 + 621 0159 01 .byte 0x1 + 622 015a 59 .byte 0x59 + 623 015b 00000000 .4byte .LFB2 + 624 015f 20000000 .4byte .LFE2-.LFB2 + 625 0163 01 .uleb128 0x1 + 626 0164 9C .byte 0x9c + 627 0165 92010000 .4byte 0x192 + 628 0169 0A .uleb128 0xa + 629 016a AD000000 .4byte .LASF22 + 630 016e 01 .byte 0x1 + 631 016f 59 .byte 0x59 + 632 0170 84000000 .4byte 0x84 + 633 0174 02 .uleb128 0x2 + 634 0175 91 .byte 0x91 + 635 0176 74 .sleb128 -12 + 636 0177 09 .uleb128 0x9 + 637 0178 73726300 .ascii "src\000" + 638 017c 01 .byte 0x1 + 639 017d 59 .byte 0x59 + 640 017e 4D010000 .4byte 0x14d + 641 0182 02 .uleb128 0x2 + 642 0183 91 .byte 0x91 + 643 0184 70 .sleb128 -16 + 644 0185 09 .uleb128 0x9 + 645 0186 6E00 .ascii "n\000" + 646 0188 01 .byte 0x1 + 647 0189 59 .byte 0x59 + 648 018a 2C000000 .4byte 0x2c + 649 018e 02 .uleb128 0x2 + 650 018f 91 .byte 0x91 + 651 0190 6C .sleb128 -20 + 652 0191 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 18 + + + 653 0192 0D .uleb128 0xd + 654 0193 2E000000 .4byte .LASF24 + 655 0197 01 .byte 0x1 + 656 0198 A9 .byte 0xa9 + 657 0199 00000000 .4byte .LFB3 + 658 019d 8C000000 .4byte .LFE3-.LFB3 + 659 01a1 01 .uleb128 0x1 + 660 01a2 9C .byte 0x9c + 661 01a3 0E .uleb128 0xe + 662 01a4 0D000000 .4byte .LASF25 + 663 01a8 01 .byte 0x1 + 664 01a9 DE .byte 0xde + 665 01aa 00000000 .4byte .LFB4 + 666 01ae 14000000 .4byte .LFE4-.LFB4 + 667 01b2 01 .uleb128 0x1 + 668 01b3 9C .byte 0x9c + 669 01b4 0F .uleb128 0xf + 670 01b5 81010000 .4byte .LASF33 + 671 01b9 01 .byte 0x1 + 672 01ba F7 .byte 0xf7 + 673 01bb 8C000000 .4byte .LFB5 + 674 01bf 14010000 .4byte .LFE5-.LFB5 + 675 01c3 01 .uleb128 0x1 + 676 01c4 9C .byte 0x9c + 677 01c5 10 .uleb128 0x10 + 678 01c6 94000000 .4byte .LBB2 + 679 01ca 8C000000 .4byte .LBE2-.LBB2 + 680 01ce 11 .uleb128 0x11 + 681 01cf 06 .byte 0x6 + 682 01d0 01 .byte 0x1 + 683 01d1 FE .byte 0xfe + 684 01d2 F0010000 .4byte 0x1f0 + 685 01d6 12 .uleb128 0x12 + 686 01d7 A9010000 .4byte .LASF26 + 687 01db 01 .byte 0x1 + 688 01dc FF .byte 0xff + 689 01dd 84000000 .4byte 0x84 + 690 01e1 00 .byte 0 + 691 01e2 13 .uleb128 0x13 + 692 01e3 B2000000 .4byte .LASF27 + 693 01e7 01 .byte 0x1 + 694 01e8 0001 .2byte 0x100 + 695 01ea 99000000 .4byte 0x99 + 696 01ee 04 .byte 0x4 + 697 01ef 00 .byte 0 + 698 01f0 06 .uleb128 0x6 + 699 01f1 C8010000 .4byte .LASF28 + 700 01f5 01 .byte 0x1 + 701 01f6 0101 .2byte 0x101 + 702 01f8 CE010000 .4byte 0x1ce + 703 01fc 14 .uleb128 0x14 + 704 01fd 0C020000 .4byte 0x20c + 705 0201 0C020000 .4byte 0x20c + 706 0205 15 .uleb128 0x15 + 707 0206 7D000000 .4byte 0x7d + 708 020a 01 .byte 0x1 + 709 020b 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 19 + + + 710 020c 16 .uleb128 0x16 + 711 020d F0010000 .4byte 0x1f0 + 712 0211 17 .uleb128 0x17 + 713 0212 1E000000 .4byte .LASF29 + 714 0216 01 .byte 0x1 + 715 0217 0301 .2byte 0x103 + 716 0219 23020000 .4byte 0x223 + 717 021d 05 .uleb128 0x5 + 718 021e 03 .byte 0x3 + 719 021f 00000000 .4byte cfg_memset_list.4847 + 720 0223 16 .uleb128 0x16 + 721 0224 FC010000 .4byte 0x1fc + 722 0228 18 .uleb128 0x18 + 723 0229 6900 .ascii "i\000" + 724 022b 01 .byte 0x1 + 725 022c 0901 .2byte 0x109 + 726 022e 8D000000 .4byte 0x8d + 727 0232 02 .uleb128 0x2 + 728 0233 91 .byte 0x91 + 729 0234 77 .sleb128 -9 + 730 0235 10 .uleb128 0x10 + 731 0236 9C000000 .4byte .LBB3 + 732 023a 3C000000 .4byte .LBE3-.LBB3 + 733 023e 18 .uleb128 0x18 + 734 023f 6D7300 .ascii "ms\000" + 735 0242 01 .byte 0x1 + 736 0243 0E01 .2byte 0x10e + 737 0245 4C020000 .4byte 0x24c + 738 0249 02 .uleb128 0x2 + 739 024a 91 .byte 0x91 + 740 024b 70 .sleb128 -16 + 741 024c 0B .uleb128 0xb + 742 024d 04 .byte 0x4 + 743 024e 0C020000 .4byte 0x20c + 744 0252 00 .byte 0 + 745 0253 00 .byte 0 + 746 0254 00 .byte 0 + 747 0255 00 .byte 0 + 748 .section .debug_abbrev,"",%progbits + 749 .Ldebug_abbrev0: + 750 0000 01 .uleb128 0x1 + 751 0001 11 .uleb128 0x11 + 752 0002 01 .byte 0x1 + 753 0003 25 .uleb128 0x25 + 754 0004 0E .uleb128 0xe + 755 0005 13 .uleb128 0x13 + 756 0006 0B .uleb128 0xb + 757 0007 03 .uleb128 0x3 + 758 0008 0E .uleb128 0xe + 759 0009 1B .uleb128 0x1b + 760 000a 0E .uleb128 0xe + 761 000b 55 .uleb128 0x55 + 762 000c 17 .uleb128 0x17 + 763 000d 11 .uleb128 0x11 + 764 000e 01 .uleb128 0x1 + 765 000f 10 .uleb128 0x10 + 766 0010 17 .uleb128 0x17 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 20 + + + 767 0011 00 .byte 0 + 768 0012 00 .byte 0 + 769 0013 02 .uleb128 0x2 + 770 0014 24 .uleb128 0x24 + 771 0015 00 .byte 0 + 772 0016 0B .uleb128 0xb + 773 0017 0B .uleb128 0xb + 774 0018 3E .uleb128 0x3e + 775 0019 0B .uleb128 0xb + 776 001a 03 .uleb128 0x3 + 777 001b 08 .uleb128 0x8 + 778 001c 00 .byte 0 + 779 001d 00 .byte 0 + 780 001e 03 .uleb128 0x3 + 781 001f 16 .uleb128 0x16 + 782 0020 00 .byte 0 + 783 0021 03 .uleb128 0x3 + 784 0022 0E .uleb128 0xe + 785 0023 3A .uleb128 0x3a + 786 0024 0B .uleb128 0xb + 787 0025 3B .uleb128 0x3b + 788 0026 0B .uleb128 0xb + 789 0027 49 .uleb128 0x49 + 790 0028 13 .uleb128 0x13 + 791 0029 00 .byte 0 + 792 002a 00 .byte 0 + 793 002b 04 .uleb128 0x4 + 794 002c 24 .uleb128 0x24 + 795 002d 00 .byte 0 + 796 002e 0B .uleb128 0xb + 797 002f 0B .uleb128 0xb + 798 0030 3E .uleb128 0x3e + 799 0031 0B .uleb128 0xb + 800 0032 03 .uleb128 0x3 + 801 0033 0E .uleb128 0xe + 802 0034 00 .byte 0 + 803 0035 00 .byte 0 + 804 0036 05 .uleb128 0x5 + 805 0037 0F .uleb128 0xf + 806 0038 00 .byte 0 + 807 0039 0B .uleb128 0xb + 808 003a 0B .uleb128 0xb + 809 003b 00 .byte 0 + 810 003c 00 .byte 0 + 811 003d 06 .uleb128 0x6 + 812 003e 16 .uleb128 0x16 + 813 003f 00 .byte 0 + 814 0040 03 .uleb128 0x3 + 815 0041 0E .uleb128 0xe + 816 0042 3A .uleb128 0x3a + 817 0043 0B .uleb128 0xb + 818 0044 3B .uleb128 0x3b + 819 0045 05 .uleb128 0x5 + 820 0046 49 .uleb128 0x49 + 821 0047 13 .uleb128 0x13 + 822 0048 00 .byte 0 + 823 0049 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 21 + + + 824 004a 07 .uleb128 0x7 + 825 004b 35 .uleb128 0x35 + 826 004c 00 .byte 0 + 827 004d 49 .uleb128 0x49 + 828 004e 13 .uleb128 0x13 + 829 004f 00 .byte 0 + 830 0050 00 .byte 0 + 831 0051 08 .uleb128 0x8 + 832 0052 2E .uleb128 0x2e + 833 0053 01 .byte 0x1 + 834 0054 03 .uleb128 0x3 + 835 0055 0E .uleb128 0xe + 836 0056 3A .uleb128 0x3a + 837 0057 0B .uleb128 0xb + 838 0058 3B .uleb128 0x3b + 839 0059 0B .uleb128 0xb + 840 005a 27 .uleb128 0x27 + 841 005b 19 .uleb128 0x19 + 842 005c 11 .uleb128 0x11 + 843 005d 01 .uleb128 0x1 + 844 005e 12 .uleb128 0x12 + 845 005f 06 .uleb128 0x6 + 846 0060 40 .uleb128 0x40 + 847 0061 18 .uleb128 0x18 + 848 0062 9642 .uleb128 0x2116 + 849 0064 19 .uleb128 0x19 + 850 0065 01 .uleb128 0x1 + 851 0066 13 .uleb128 0x13 + 852 0067 00 .byte 0 + 853 0068 00 .byte 0 + 854 0069 09 .uleb128 0x9 + 855 006a 05 .uleb128 0x5 + 856 006b 00 .byte 0 + 857 006c 03 .uleb128 0x3 + 858 006d 08 .uleb128 0x8 + 859 006e 3A .uleb128 0x3a + 860 006f 0B .uleb128 0xb + 861 0070 3B .uleb128 0x3b + 862 0071 0B .uleb128 0xb + 863 0072 49 .uleb128 0x49 + 864 0073 13 .uleb128 0x13 + 865 0074 02 .uleb128 0x2 + 866 0075 18 .uleb128 0x18 + 867 0076 00 .byte 0 + 868 0077 00 .byte 0 + 869 0078 0A .uleb128 0xa + 870 0079 05 .uleb128 0x5 + 871 007a 00 .byte 0 + 872 007b 03 .uleb128 0x3 + 873 007c 0E .uleb128 0xe + 874 007d 3A .uleb128 0x3a + 875 007e 0B .uleb128 0xb + 876 007f 3B .uleb128 0x3b + 877 0080 0B .uleb128 0xb + 878 0081 49 .uleb128 0x49 + 879 0082 13 .uleb128 0x13 + 880 0083 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 22 + + + 881 0084 18 .uleb128 0x18 + 882 0085 00 .byte 0 + 883 0086 00 .byte 0 + 884 0087 0B .uleb128 0xb + 885 0088 0F .uleb128 0xf + 886 0089 00 .byte 0 + 887 008a 0B .uleb128 0xb + 888 008b 0B .uleb128 0xb + 889 008c 49 .uleb128 0x49 + 890 008d 13 .uleb128 0x13 + 891 008e 00 .byte 0 + 892 008f 00 .byte 0 + 893 0090 0C .uleb128 0xc + 894 0091 26 .uleb128 0x26 + 895 0092 00 .byte 0 + 896 0093 00 .byte 0 + 897 0094 00 .byte 0 + 898 0095 0D .uleb128 0xd + 899 0096 2E .uleb128 0x2e + 900 0097 00 .byte 0 + 901 0098 03 .uleb128 0x3 + 902 0099 0E .uleb128 0xe + 903 009a 3A .uleb128 0x3a + 904 009b 0B .uleb128 0xb + 905 009c 3B .uleb128 0x3b + 906 009d 0B .uleb128 0xb + 907 009e 27 .uleb128 0x27 + 908 009f 19 .uleb128 0x19 + 909 00a0 11 .uleb128 0x11 + 910 00a1 01 .uleb128 0x1 + 911 00a2 12 .uleb128 0x12 + 912 00a3 06 .uleb128 0x6 + 913 00a4 40 .uleb128 0x40 + 914 00a5 18 .uleb128 0x18 + 915 00a6 9642 .uleb128 0x2116 + 916 00a8 19 .uleb128 0x19 + 917 00a9 00 .byte 0 + 918 00aa 00 .byte 0 + 919 00ab 0E .uleb128 0xe + 920 00ac 2E .uleb128 0x2e + 921 00ad 00 .byte 0 + 922 00ae 03 .uleb128 0x3 + 923 00af 0E .uleb128 0xe + 924 00b0 3A .uleb128 0x3a + 925 00b1 0B .uleb128 0xb + 926 00b2 3B .uleb128 0x3b + 927 00b3 0B .uleb128 0xb + 928 00b4 27 .uleb128 0x27 + 929 00b5 19 .uleb128 0x19 + 930 00b6 11 .uleb128 0x11 + 931 00b7 01 .uleb128 0x1 + 932 00b8 12 .uleb128 0x12 + 933 00b9 06 .uleb128 0x6 + 934 00ba 40 .uleb128 0x40 + 935 00bb 18 .uleb128 0x18 + 936 00bc 9742 .uleb128 0x2117 + 937 00be 19 .uleb128 0x19 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 23 + + + 938 00bf 00 .byte 0 + 939 00c0 00 .byte 0 + 940 00c1 0F .uleb128 0xf + 941 00c2 2E .uleb128 0x2e + 942 00c3 01 .byte 0x1 + 943 00c4 3F .uleb128 0x3f + 944 00c5 19 .uleb128 0x19 + 945 00c6 03 .uleb128 0x3 + 946 00c7 0E .uleb128 0xe + 947 00c8 3A .uleb128 0x3a + 948 00c9 0B .uleb128 0xb + 949 00ca 3B .uleb128 0x3b + 950 00cb 0B .uleb128 0xb + 951 00cc 27 .uleb128 0x27 + 952 00cd 19 .uleb128 0x19 + 953 00ce 11 .uleb128 0x11 + 954 00cf 01 .uleb128 0x1 + 955 00d0 12 .uleb128 0x12 + 956 00d1 06 .uleb128 0x6 + 957 00d2 40 .uleb128 0x40 + 958 00d3 18 .uleb128 0x18 + 959 00d4 9642 .uleb128 0x2116 + 960 00d6 19 .uleb128 0x19 + 961 00d7 00 .byte 0 + 962 00d8 00 .byte 0 + 963 00d9 10 .uleb128 0x10 + 964 00da 0B .uleb128 0xb + 965 00db 01 .byte 0x1 + 966 00dc 11 .uleb128 0x11 + 967 00dd 01 .uleb128 0x1 + 968 00de 12 .uleb128 0x12 + 969 00df 06 .uleb128 0x6 + 970 00e0 00 .byte 0 + 971 00e1 00 .byte 0 + 972 00e2 11 .uleb128 0x11 + 973 00e3 13 .uleb128 0x13 + 974 00e4 01 .byte 0x1 + 975 00e5 0B .uleb128 0xb + 976 00e6 0B .uleb128 0xb + 977 00e7 3A .uleb128 0x3a + 978 00e8 0B .uleb128 0xb + 979 00e9 3B .uleb128 0x3b + 980 00ea 0B .uleb128 0xb + 981 00eb 01 .uleb128 0x1 + 982 00ec 13 .uleb128 0x13 + 983 00ed 00 .byte 0 + 984 00ee 00 .byte 0 + 985 00ef 12 .uleb128 0x12 + 986 00f0 0D .uleb128 0xd + 987 00f1 00 .byte 0 + 988 00f2 03 .uleb128 0x3 + 989 00f3 0E .uleb128 0xe + 990 00f4 3A .uleb128 0x3a + 991 00f5 0B .uleb128 0xb + 992 00f6 3B .uleb128 0x3b + 993 00f7 0B .uleb128 0xb + 994 00f8 49 .uleb128 0x49 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 24 + + + 995 00f9 13 .uleb128 0x13 + 996 00fa 38 .uleb128 0x38 + 997 00fb 0B .uleb128 0xb + 998 00fc 00 .byte 0 + 999 00fd 00 .byte 0 + 1000 00fe 13 .uleb128 0x13 + 1001 00ff 0D .uleb128 0xd + 1002 0100 00 .byte 0 + 1003 0101 03 .uleb128 0x3 + 1004 0102 0E .uleb128 0xe + 1005 0103 3A .uleb128 0x3a + 1006 0104 0B .uleb128 0xb + 1007 0105 3B .uleb128 0x3b + 1008 0106 05 .uleb128 0x5 + 1009 0107 49 .uleb128 0x49 + 1010 0108 13 .uleb128 0x13 + 1011 0109 38 .uleb128 0x38 + 1012 010a 0B .uleb128 0xb + 1013 010b 00 .byte 0 + 1014 010c 00 .byte 0 + 1015 010d 14 .uleb128 0x14 + 1016 010e 01 .uleb128 0x1 + 1017 010f 01 .byte 0x1 + 1018 0110 49 .uleb128 0x49 + 1019 0111 13 .uleb128 0x13 + 1020 0112 01 .uleb128 0x1 + 1021 0113 13 .uleb128 0x13 + 1022 0114 00 .byte 0 + 1023 0115 00 .byte 0 + 1024 0116 15 .uleb128 0x15 + 1025 0117 21 .uleb128 0x21 + 1026 0118 00 .byte 0 + 1027 0119 49 .uleb128 0x49 + 1028 011a 13 .uleb128 0x13 + 1029 011b 2F .uleb128 0x2f + 1030 011c 0B .uleb128 0xb + 1031 011d 00 .byte 0 + 1032 011e 00 .byte 0 + 1033 011f 16 .uleb128 0x16 + 1034 0120 26 .uleb128 0x26 + 1035 0121 00 .byte 0 + 1036 0122 49 .uleb128 0x49 + 1037 0123 13 .uleb128 0x13 + 1038 0124 00 .byte 0 + 1039 0125 00 .byte 0 + 1040 0126 17 .uleb128 0x17 + 1041 0127 34 .uleb128 0x34 + 1042 0128 00 .byte 0 + 1043 0129 03 .uleb128 0x3 + 1044 012a 0E .uleb128 0xe + 1045 012b 3A .uleb128 0x3a + 1046 012c 0B .uleb128 0xb + 1047 012d 3B .uleb128 0x3b + 1048 012e 05 .uleb128 0x5 + 1049 012f 49 .uleb128 0x49 + 1050 0130 13 .uleb128 0x13 + 1051 0131 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 25 + + + 1052 0132 18 .uleb128 0x18 + 1053 0133 00 .byte 0 + 1054 0134 00 .byte 0 + 1055 0135 18 .uleb128 0x18 + 1056 0136 34 .uleb128 0x34 + 1057 0137 00 .byte 0 + 1058 0138 03 .uleb128 0x3 + 1059 0139 08 .uleb128 0x8 + 1060 013a 3A .uleb128 0x3a + 1061 013b 0B .uleb128 0xb + 1062 013c 3B .uleb128 0x3b + 1063 013d 05 .uleb128 0x5 + 1064 013e 49 .uleb128 0x49 + 1065 013f 13 .uleb128 0x13 + 1066 0140 02 .uleb128 0x2 + 1067 0141 18 .uleb128 0x18 + 1068 0142 00 .byte 0 + 1069 0143 00 .byte 0 + 1070 0144 00 .byte 0 + 1071 .section .debug_aranges,"",%progbits + 1072 0000 44000000 .4byte 0x44 + 1073 0004 0200 .2byte 0x2 + 1074 0006 00000000 .4byte .Ldebug_info0 + 1075 000a 04 .byte 0x4 + 1076 000b 00 .byte 0 + 1077 000c 0000 .2byte 0 + 1078 000e 0000 .2byte 0 + 1079 0010 00000000 .4byte .LFB0 + 1080 0014 1E000000 .4byte .LFE0-.LFB0 + 1081 0018 00000000 .4byte .LFB1 + 1082 001c 20000000 .4byte .LFE1-.LFB1 + 1083 0020 00000000 .4byte .LFB2 + 1084 0024 20000000 .4byte .LFE2-.LFB2 + 1085 0028 00000000 .4byte .LFB3 + 1086 002c 8C000000 .4byte .LFE3-.LFB3 + 1087 0030 00000000 .4byte .LFB4 + 1088 0034 14000000 .4byte .LFE4-.LFB4 + 1089 0038 8C000000 .4byte .LFB5 + 1090 003c 14010000 .4byte .LFE5-.LFB5 + 1091 0040 00000000 .4byte 0 + 1092 0044 00000000 .4byte 0 + 1093 .section .debug_ranges,"",%progbits + 1094 .Ldebug_ranges0: + 1095 0000 00000000 .4byte .LFB0 + 1096 0004 1E000000 .4byte .LFE0 + 1097 0008 00000000 .4byte .LFB1 + 1098 000c 20000000 .4byte .LFE1 + 1099 0010 00000000 .4byte .LFB2 + 1100 0014 20000000 .4byte .LFE2 + 1101 0018 00000000 .4byte .LFB3 + 1102 001c 8C000000 .4byte .LFE3 + 1103 0020 00000000 .4byte .LFB4 + 1104 0024 14000000 .4byte .LFE4 + 1105 0028 8C000000 .4byte .LFB5 + 1106 002c A0010000 .4byte .LFE5 + 1107 0030 00000000 .4byte 0 + 1108 0034 00000000 .4byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 26 + + + 1109 .section .debug_line,"",%progbits + 1110 .Ldebug_line0: + 1111 0000 65010000 .section .debug_str,"MS",%progbits,1 + 1111 0200CB00 + 1111 00000201 + 1111 FB0E0D00 + 1111 01010101 + 1112 .LASF19: + 1113 0000 72656733 .ascii "reg32\000" + 1113 3200 + 1114 .LASF12: + 1115 0006 73697A65 .ascii "size_t\000" + 1115 5F7400 + 1116 .LASF25: + 1117 000d 416E616C .ascii "AnalogSetDefault\000" + 1117 6F675365 + 1117 74446566 + 1117 61756C74 + 1117 00 + 1118 .LASF29: + 1119 001e 6366675F .ascii "cfg_memset_list\000" + 1119 6D656D73 + 1119 65745F6C + 1119 69737400 + 1120 .LASF24: + 1121 002e 436C6F63 .ascii "ClockSetup\000" + 1121 6B536574 + 1121 757000 + 1122 .LASF6: + 1123 0039 73686F72 .ascii "short unsigned int\000" + 1123 7420756E + 1123 7369676E + 1123 65642069 + 1123 6E7400 + 1124 .LASF32: + 1125 004c 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 1125 73657273 + 1125 5C6A6167 + 1125 756D6965 + 1125 6C5C446F + 1126 007a 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 1126 50536F43 + 1126 2D313031 + 1126 5C547261 + 1126 696E696E + 1127 .LASF16: + 1128 00a7 666C6F61 .ascii "float\000" + 1128 7400 + 1129 .LASF22: + 1130 00ad 64657374 .ascii "dest\000" + 1130 00 + 1131 .LASF27: + 1132 00b2 73697A65 .ascii "size\000" + 1132 00 + 1133 .LASF18: + 1134 00b7 72656738 .ascii "reg8\000" + 1134 00 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 27 + + + 1135 .LASF8: + 1136 00bc 6C6F6E67 .ascii "long unsigned int\000" + 1136 20756E73 + 1136 69676E65 + 1136 6420696E + 1136 7400 + 1137 .LASF13: + 1138 00ce 75696E74 .ascii "uint8\000" + 1138 3800 + 1139 .LASF20: + 1140 00d4 43594D45 .ascii "CYMEMZERO\000" + 1140 4D5A4552 + 1140 4F00 + 1141 .LASF30: + 1142 00de 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 1142 43313120 + 1142 352E342E + 1142 31203230 + 1142 31363036 + 1143 0111 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 1143 20726576 + 1143 6973696F + 1143 6E203233 + 1143 37373135 + 1144 0144 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 1144 66756E63 + 1144 74696F6E + 1144 2D736563 + 1144 74696F6E + 1145 .LASF4: + 1146 016c 756E7369 .ascii "unsigned char\000" + 1146 676E6564 + 1146 20636861 + 1146 7200 + 1147 .LASF17: + 1148 017a 646F7562 .ascii "double\000" + 1148 6C6500 + 1149 .LASF33: + 1150 0181 63796669 .ascii "cyfitter_cfg\000" + 1150 74746572 + 1150 5F636667 + 1150 00 + 1151 .LASF14: + 1152 018e 75696E74 .ascii "uint16\000" + 1152 313600 + 1153 .LASF15: + 1154 0195 75696E74 .ascii "uint32\000" + 1154 333200 + 1155 .LASF0: + 1156 019c 756E7369 .ascii "unsigned int\000" + 1156 676E6564 + 1156 20696E74 + 1156 00 + 1157 .LASF26: + 1158 01a9 61646472 .ascii "address\000" + 1158 65737300 + 1159 .LASF9: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cca1tp66.s page 28 + + + 1160 01b1 6C6F6E67 .ascii "long long unsigned int\000" + 1160 206C6F6E + 1160 6720756E + 1160 7369676E + 1160 65642069 + 1161 .LASF28: + 1162 01c8 6366675F .ascii "cfg_memset_t\000" + 1162 6D656D73 + 1162 65745F74 + 1162 00 + 1163 .LASF10: + 1164 01d5 73697A65 .ascii "sizetype\000" + 1164 74797065 + 1164 00 + 1165 .LASF1: + 1166 01de 6C6F6E67 .ascii "long long int\000" + 1166 206C6F6E + 1166 6720696E + 1166 7400 + 1167 .LASF11: + 1168 01ec 63686172 .ascii "char\000" + 1168 00 + 1169 .LASF5: + 1170 01f1 73686F72 .ascii "short int\000" + 1170 7420696E + 1170 7400 + 1171 .LASF7: + 1172 01fb 6C6F6E67 .ascii "long int\000" + 1172 20696E74 + 1172 00 + 1173 .LASF2: + 1174 0204 6C6F6E67 .ascii "long double\000" + 1174 20646F75 + 1174 626C6500 + 1175 .LASF3: + 1176 0210 7369676E .ascii "signed char\000" + 1176 65642063 + 1176 68617200 + 1177 .LASF31: + 1178 021c 47656E65 .ascii "Generated_Source\\PSoC4\\cyfitter_cfg.c\000" + 1178 72617465 + 1178 645F536F + 1178 75726365 + 1178 5C50536F + 1179 .LASF23: + 1180 0242 4359434F .ascii "CYCONFIGCPYCODE\000" + 1180 4E464947 + 1180 43505943 + 1180 4F444500 + 1181 .LASF21: + 1182 0252 4359434F .ascii "CYCONFIGCPY\000" + 1182 4E464947 + 1182 43505900 + 1183 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyfitter_cfg.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyfitter_cfg.o new file mode 100644 index 0000000000000000000000000000000000000000..221ff2b0425ad727f92d898dcce37fe5a153f973 GIT binary patch literal 6052 zcmbtYdu&_P8UN0`H;xnMRVQg&r=_=93#o>UQ_?n+g*rHGDQ;+&wydFMwPWAd2ETTF zJ(99VK$Xy>t!g*e)KMlTu?J`fR;`;5pz+tl#Dp}&v?35f8=IyHZSWV9g2;Z~z30X^ zDH2Tkq;r1X>wM=sk9*Fszq#+wejx<8BxsnL644)mwxwm%hGE)F8)@`BS+j=o zTYQm3Aili3w5$PrM2mh!iEl*lLncz<1JK2RV}cetltA1WtNH7tO^8t&dS_`OMS3xi5;;?YYR>>1*=OPj=w zaBXSR;Jo?<(T)*HL09 zR6`LO=0n3YXz>t=Uj?rLQ9>w-m+2YB?oZCC8je#8?KFyWJ*^N}CQZD}{cMEdkgaG| ziq=xBSfpYRNV&2bwWhUR#MaaNEpOYPX&guRdTj8QSgEvpU_!?H$69f$-=acK>py}zR3ytkI83@-H<1^gi8qM5FKmUZK5M(jvD7XZ z;1zlWq9T^C39)O~iXsje6~oL}M()(nYQxMLsUt_LiBZb#N!841-prKsxnjwv>%;S7 zySAsY3pLZI*Hg86HLGV$BV$#~)M#|aYDKYJtD06SUumQ=W;wMpIvO2Gm5Q^ed^XFP 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zfD@h@(Tru8#o301u>S*LtJ(Jf?>i=5FE3$R+O!2VmY7sWyvmPlOgK_-%YC{Z?_X}? z?N^8F67ORs-hXWUZ#>>-I*Lnfyf_rzcyD>)aV~DWyTE(n z@jlg2Tyo>_dFGAxt|uPn<;LUo-gpl~ew-DO+;}y}-gxgJo(>(4mv47B-Z#K|lG}vOb#K3CdYm(b`{ldIotM|ZyKTVIZY(OFJubPn zSE2C6djav%&~ZF|b-3}~1@E>2OI5@xdK51E4s70d872XSOe)c>Q)^@%isLm)OR|kBZTypTqBER{(OqOd6cL`As6fH1wPw-{o$8{qVy# zUW3Y}8qW9;R{*+w@tnJ70h^zIg6~k5T$a%@JbD80&OyQN>1`<7FQ(qk%^PnNo9Qv= IU2^077vzF!G5`Po literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cymetadata.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cymetadata.lst new file mode 100644 index 0000000..65a8118 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cymetadata.lst @@ -0,0 +1,430 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "cymetadata.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .global cy_meta_flashprotect + 20 .section .cyflashprotect,"a",%progbits + 21 .align 2 + 22 .type cy_meta_flashprotect, %object + 23 .size cy_meta_flashprotect, 32 + 24 cy_meta_flashprotect: + 25 0000 00000000 .space 32 + 25 00000000 + 25 00000000 + 25 00000000 + 25 00000000 + 26 .global cy_metadata + 27 .section .cymeta,"a",%progbits + 28 .align 2 + 29 .type cy_metadata, %object + 30 .size cy_metadata, 12 + 31 cy_metadata: + 32 0000 00 .byte 0 + 33 0001 02 .byte 2 + 34 0002 04 .byte 4 + 35 0003 C8 .byte -56 + 36 0004 11 .byte 17 + 37 0005 93 .byte -109 + 38 0006 11 .byte 17 + 39 0007 01 .byte 1 + 40 0008 00 .byte 0 + 41 0009 00 .byte 0 + 42 000a 00 .byte 0 + 43 000b 00 .byte 0 + 44 .global cy_meta_chipprotect + 45 .section .cychipprotect,"a",%progbits + 46 .align 2 + 47 .type cy_meta_chipprotect, %object + 48 .size cy_meta_chipprotect, 1 + 49 cy_meta_chipprotect: + 50 0000 01 .byte 1 + 51 .text + 52 .Letext0: + 53 .file 1 "c:\\program files (x86)\\cypress\\psoc creator\\4.2\\psoc creator\\import\\gnu\\arm\\5.4. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 2 + + + 54 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\4.2\\psoc creator\\import\\gnu\\arm\\5.4. + 55 .file 3 "Generated_Source\\PSoC4\\cymetadata.c" + 56 .section .debug_info,"",%progbits + 57 .Ldebug_info0: + 58 0000 F4000000 .4byte 0xf4 + 59 0004 0400 .2byte 0x4 + 60 0006 00000000 .4byte .Ldebug_abbrev0 + 61 000a 04 .byte 0x4 + 62 000b 01 .uleb128 0x1 + 63 000c 21010000 .4byte .LASF15 + 64 0010 0C .byte 0xc + 65 0011 38000000 .4byte .LASF16 + 66 0015 6E000000 .4byte .LASF17 + 67 0019 00000000 .4byte .Ldebug_line0 + 68 001d 02 .uleb128 0x2 + 69 001e 01 .byte 0x1 + 70 001f 06 .byte 0x6 + 71 0020 1A020000 .4byte .LASF0 + 72 0024 03 .uleb128 0x3 + 73 0025 00000000 .4byte .LASF9 + 74 0029 01 .byte 0x1 + 75 002a 1D .byte 0x1d + 76 002b 2F000000 .4byte 0x2f + 77 002f 02 .uleb128 0x2 + 78 0030 01 .byte 0x1 + 79 0031 08 .byte 0x8 + 80 0032 2A000000 .4byte .LASF1 + 81 0036 02 .uleb128 0x2 + 82 0037 02 .byte 0x2 + 83 0038 05 .byte 0x5 + 84 0039 07020000 .4byte .LASF2 + 85 003d 02 .uleb128 0x2 + 86 003e 02 .byte 0x2 + 87 003f 07 .byte 0x7 + 88 0040 0E010000 .4byte .LASF3 + 89 0044 02 .uleb128 0x2 + 90 0045 04 .byte 0x4 + 91 0046 05 .byte 0x5 + 92 0047 11020000 .4byte .LASF4 + 93 004b 02 .uleb128 0x2 + 94 004c 04 .byte 0x4 + 95 004d 07 .byte 0x7 + 96 004e 5C000000 .4byte .LASF5 + 97 0052 02 .uleb128 0x2 + 98 0053 08 .byte 0x8 + 99 0054 05 .byte 0x5 + 100 0055 F9010000 .4byte .LASF6 + 101 0059 02 .uleb128 0x2 + 102 005a 08 .byte 0x8 + 103 005b 07 .byte 0x7 + 104 005c BC010000 .4byte .LASF7 + 105 0060 04 .uleb128 0x4 + 106 0061 04 .byte 0x4 + 107 0062 05 .byte 0x5 + 108 0063 696E7400 .ascii "int\000" + 109 0067 02 .uleb128 0x2 + 110 0068 04 .byte 0x4 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 3 + + + 111 0069 07 .byte 0x7 + 112 006a AF010000 .4byte .LASF8 + 113 006e 03 .uleb128 0x3 + 114 006f D3010000 .4byte .LASF10 + 115 0073 02 .byte 0x2 + 116 0074 18 .byte 0x18 + 117 0075 24000000 .4byte 0x24 + 118 0079 05 .uleb128 0x5 + 119 007a 90000000 .4byte 0x90 + 120 007e 89000000 .4byte 0x89 + 121 0082 06 .uleb128 0x6 + 122 0083 89000000 .4byte 0x89 + 123 0087 1F .byte 0x1f + 124 0088 00 .byte 0 + 125 0089 02 .uleb128 0x2 + 126 008a 04 .byte 0x4 + 127 008b 07 .byte 0x7 + 128 008c F0010000 .4byte .LASF11 + 129 0090 07 .uleb128 0x7 + 130 0091 6E000000 .4byte 0x6e + 131 0095 08 .uleb128 0x8 + 132 0096 DB010000 .4byte .LASF12 + 133 009a 03 .byte 0x3 + 134 009b 1F .byte 0x1f + 135 009c A6000000 .4byte 0xa6 + 136 00a0 05 .uleb128 0x5 + 137 00a1 03 .byte 0x3 + 138 00a2 00000000 .4byte cy_meta_flashprotect + 139 00a6 07 .uleb128 0x7 + 140 00a7 79000000 .4byte 0x79 + 141 00ab 05 .uleb128 0x5 + 142 00ac 90000000 .4byte 0x90 + 143 00b0 BB000000 .4byte 0xbb + 144 00b4 06 .uleb128 0x6 + 145 00b5 89000000 .4byte 0x89 + 146 00b9 0B .byte 0xb + 147 00ba 00 .byte 0 + 148 00bb 08 .uleb128 0x8 + 149 00bc 1E000000 .4byte .LASF13 + 150 00c0 03 .byte 0x3 + 151 00c1 30 .byte 0x30 + 152 00c2 CC000000 .4byte 0xcc + 153 00c6 05 .uleb128 0x5 + 154 00c7 03 .byte 0x3 + 155 00c8 00000000 .4byte cy_metadata + 156 00cc 07 .uleb128 0x7 + 157 00cd AB000000 .4byte 0xab + 158 00d1 05 .uleb128 0x5 + 159 00d2 90000000 .4byte 0x90 + 160 00d6 E1000000 .4byte 0xe1 + 161 00da 06 .uleb128 0x6 + 162 00db 89000000 .4byte 0x89 + 163 00df 00 .byte 0 + 164 00e0 00 .byte 0 + 165 00e1 08 .uleb128 0x8 + 166 00e2 0A000000 .4byte .LASF14 + 167 00e6 03 .byte 0x3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 4 + + + 168 00e7 3F .byte 0x3f + 169 00e8 F2000000 .4byte 0xf2 + 170 00ec 05 .uleb128 0x5 + 171 00ed 03 .byte 0x3 + 172 00ee 00000000 .4byte cy_meta_chipprotect + 173 00f2 07 .uleb128 0x7 + 174 00f3 D1000000 .4byte 0xd1 + 175 00f7 00 .byte 0 + 176 .section .debug_abbrev,"",%progbits + 177 .Ldebug_abbrev0: + 178 0000 01 .uleb128 0x1 + 179 0001 11 .uleb128 0x11 + 180 0002 01 .byte 0x1 + 181 0003 25 .uleb128 0x25 + 182 0004 0E .uleb128 0xe + 183 0005 13 .uleb128 0x13 + 184 0006 0B .uleb128 0xb + 185 0007 03 .uleb128 0x3 + 186 0008 0E .uleb128 0xe + 187 0009 1B .uleb128 0x1b + 188 000a 0E .uleb128 0xe + 189 000b 10 .uleb128 0x10 + 190 000c 17 .uleb128 0x17 + 191 000d 00 .byte 0 + 192 000e 00 .byte 0 + 193 000f 02 .uleb128 0x2 + 194 0010 24 .uleb128 0x24 + 195 0011 00 .byte 0 + 196 0012 0B .uleb128 0xb + 197 0013 0B .uleb128 0xb + 198 0014 3E .uleb128 0x3e + 199 0015 0B .uleb128 0xb + 200 0016 03 .uleb128 0x3 + 201 0017 0E .uleb128 0xe + 202 0018 00 .byte 0 + 203 0019 00 .byte 0 + 204 001a 03 .uleb128 0x3 + 205 001b 16 .uleb128 0x16 + 206 001c 00 .byte 0 + 207 001d 03 .uleb128 0x3 + 208 001e 0E .uleb128 0xe + 209 001f 3A .uleb128 0x3a + 210 0020 0B .uleb128 0xb + 211 0021 3B .uleb128 0x3b + 212 0022 0B .uleb128 0xb + 213 0023 49 .uleb128 0x49 + 214 0024 13 .uleb128 0x13 + 215 0025 00 .byte 0 + 216 0026 00 .byte 0 + 217 0027 04 .uleb128 0x4 + 218 0028 24 .uleb128 0x24 + 219 0029 00 .byte 0 + 220 002a 0B .uleb128 0xb + 221 002b 0B .uleb128 0xb + 222 002c 3E .uleb128 0x3e + 223 002d 0B .uleb128 0xb + 224 002e 03 .uleb128 0x3 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 5 + + + 225 002f 08 .uleb128 0x8 + 226 0030 00 .byte 0 + 227 0031 00 .byte 0 + 228 0032 05 .uleb128 0x5 + 229 0033 01 .uleb128 0x1 + 230 0034 01 .byte 0x1 + 231 0035 49 .uleb128 0x49 + 232 0036 13 .uleb128 0x13 + 233 0037 01 .uleb128 0x1 + 234 0038 13 .uleb128 0x13 + 235 0039 00 .byte 0 + 236 003a 00 .byte 0 + 237 003b 06 .uleb128 0x6 + 238 003c 21 .uleb128 0x21 + 239 003d 00 .byte 0 + 240 003e 49 .uleb128 0x49 + 241 003f 13 .uleb128 0x13 + 242 0040 2F .uleb128 0x2f + 243 0041 0B .uleb128 0xb + 244 0042 00 .byte 0 + 245 0043 00 .byte 0 + 246 0044 07 .uleb128 0x7 + 247 0045 26 .uleb128 0x26 + 248 0046 00 .byte 0 + 249 0047 49 .uleb128 0x49 + 250 0048 13 .uleb128 0x13 + 251 0049 00 .byte 0 + 252 004a 00 .byte 0 + 253 004b 08 .uleb128 0x8 + 254 004c 34 .uleb128 0x34 + 255 004d 00 .byte 0 + 256 004e 03 .uleb128 0x3 + 257 004f 0E .uleb128 0xe + 258 0050 3A .uleb128 0x3a + 259 0051 0B .uleb128 0xb + 260 0052 3B .uleb128 0x3b + 261 0053 0B .uleb128 0xb + 262 0054 49 .uleb128 0x49 + 263 0055 13 .uleb128 0x13 + 264 0056 3F .uleb128 0x3f + 265 0057 19 .uleb128 0x19 + 266 0058 02 .uleb128 0x2 + 267 0059 18 .uleb128 0x18 + 268 005a 00 .byte 0 + 269 005b 00 .byte 0 + 270 005c 00 .byte 0 + 271 .section .debug_aranges,"",%progbits + 272 0000 14000000 .4byte 0x14 + 273 0004 0200 .2byte 0x2 + 274 0006 00000000 .4byte .Ldebug_info0 + 275 000a 04 .byte 0x4 + 276 000b 00 .byte 0 + 277 000c 0000 .2byte 0 + 278 000e 0000 .2byte 0 + 279 0010 00000000 .4byte 0 + 280 0014 00000000 .4byte 0 + 281 .section .debug_line,"",%progbits + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 6 + + + 282 .Ldebug_line0: + 283 0000 3D010000 .section .debug_str,"MS",%progbits,1 + 283 02003701 + 283 00000201 + 283 FB0E0D00 + 283 01010101 + 284 .LASF9: + 285 0000 5F5F7569 .ascii "__uint8_t\000" + 285 6E74385F + 285 7400 + 286 .LASF14: + 287 000a 63795F6D .ascii "cy_meta_chipprotect\000" + 287 6574615F + 287 63686970 + 287 70726F74 + 287 65637400 + 288 .LASF13: + 289 001e 63795F6D .ascii "cy_metadata\000" + 289 65746164 + 289 61746100 + 290 .LASF1: + 291 002a 756E7369 .ascii "unsigned char\000" + 291 676E6564 + 291 20636861 + 291 7200 + 292 .LASF16: + 293 0038 47656E65 .ascii "Generated_Source\\PSoC4\\cymetadata.c\000" + 293 72617465 + 293 645F536F + 293 75726365 + 293 5C50536F + 294 .LASF5: + 295 005c 6C6F6E67 .ascii "long unsigned int\000" + 295 20756E73 + 295 69676E65 + 295 6420696E + 295 7400 + 296 .LASF17: + 297 006e 443A5C55 .ascii "D:\\Users\\jagumiel\\Desktop\\PSoC4-MCU-Analog-Desi" + 297 73657273 + 297 5C6A6167 + 297 756D6965 + 297 6C5C4465 + 298 009d 676E732D .ascii "gns-master\\ADC\\CE95272 - PSoC4 SAR ADC and Differ" + 298 6D617374 + 298 65725C41 + 298 44435C43 + 298 45393532 + 299 00ce 656E7469 .ascii "ential Amplifier\\PSoC4_ADC_with_Differential_PreAm" + 299 616C2041 + 299 6D706C69 + 299 66696572 + 299 5C50536F + 300 0100 706C6966 .ascii "plifier.cydsn\000" + 300 6965722E + 300 63796473 + 300 6E00 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 7 + + + 301 .LASF3: + 302 010e 73686F72 .ascii "short unsigned int\000" + 302 7420756E + 302 7369676E + 302 65642069 + 302 6E7400 + 303 .LASF15: + 304 0121 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 304 43313120 + 304 352E342E + 304 31203230 + 304 31363036 + 305 0154 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 305 20726576 + 305 6973696F + 305 6E203233 + 305 37373135 + 306 0187 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 306 66756E63 + 306 74696F6E + 306 2D736563 + 306 74696F6E + 307 .LASF8: + 308 01af 756E7369 .ascii "unsigned int\000" + 308 676E6564 + 308 20696E74 + 308 00 + 309 .LASF7: + 310 01bc 6C6F6E67 .ascii "long long unsigned int\000" + 310 206C6F6E + 310 6720756E + 310 7369676E + 310 65642069 + 311 .LASF10: + 312 01d3 75696E74 .ascii "uint8_t\000" + 312 385F7400 + 313 .LASF12: + 314 01db 63795F6D .ascii "cy_meta_flashprotect\000" + 314 6574615F + 314 666C6173 + 314 6870726F + 314 74656374 + 315 .LASF11: + 316 01f0 73697A65 .ascii "sizetype\000" + 316 74797065 + 316 00 + 317 .LASF6: + 318 01f9 6C6F6E67 .ascii "long long int\000" + 318 206C6F6E + 318 6720696E + 318 7400 + 319 .LASF2: + 320 0207 73686F72 .ascii "short int\000" + 320 7420696E + 320 7400 + 321 .LASF4: + 322 0211 6C6F6E67 .ascii "long int\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccJSdqlm.s page 8 + + + 322 20696E74 + 322 00 + 323 .LASF0: + 324 021a 7369676E .ascii "signed char\000" + 324 65642063 + 324 68617200 + 325 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cymetadata.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cymetadata.o new file mode 100644 index 0000000000000000000000000000000000000000..529d097cc8d74feebcf450b71df973b9b20e9675 GIT binary patch literal 3036 zcmcgu&2Jk;6rc6laf;idZd&>!+NsnQ7qPArlBNxm)^ggY5-CyB2qCsw*6XpoWk1Z$ zF4SDOa6#gLgv5m#sO0jmjP?s)#S~i9PQbML zJd_}tThOMC6d2P<)gC#E--0&%7_maB3`e0*p23_#u~a3kST@NwUHXlT)8%_$#bU_~ zV)A_iP5+8KhfV@kdK*7)VocG`aYFnEXPI(Oe?!>gA3!Xn$;(3$X~t(5>5K}SJ_cED zd`_+r>O&F<^({tz95e*9i3`M5a}>Q!{fFedg%Q-h)`vNmi*m4HejjnLe{p zd9reC4$IH%D04~EuFYw%O`TxZ=FV2I*3%G>VR3uHrNf0o2)-W!1p$ppn~M0kNV{jt z^sD_ovxnhiA=80s&WbsR!d_(iyz6>G^4gvA=gyeUa1aS8&4COZ?nJ_l!^m8$FN_;p ze-K8o*$WcWj(l^ezF40p$q2$g7{YG5rW-h3(h;U_JAF40?ElIqhmx&{Kty&dI@V^G zM2;{wHp3Qftkn@+JMm&G9u9=8_o)z;j61k6P*6Z;=!@9y*s)!A(pzX*37qGx7%q!^ z7Irg0;bP%z+X&B+K)Ss^bhy*EqX(=2)y>8C!l1{ur_rTdT`{+$h@^Sj?j^n}JabjZ zm*Q|R+JLd%+A^Af?S(x94y2QYZ_8LjW^=V=wys=QT3BA-22Z!kH=8#&?A#7IeAVrC zMI?gQwLRYS2cFw?F)amJ09miPao@_Ltc^%)1MAMPBLgP;IQ8)*uU+5bt@(MLUID() zm_OGz*SNrIk?@2q#TouW^TzsF;kQMnBRa;C(T?oE>GMdu;z~CR_`(y*%kxXOxZyj4 zmjtwskjj(+iM!9ncRL!)$e=YLl zfp$Gx_SK0>_ccM6BR82sjW)g=G&SW;o2|84E4)UvxEY3?ZN0&!c9++8Y5R)%wFBBg{g8H8JE9$%0%nq^4JazI zpZ-uXaeb`glRoM#3Zsu2v{IoJ8Twd`#=DTtN)!H44omT;Cj8?o)>(N1ziUFLmb*hb z+r6Ve(%GH~eSEb#n`PAu!NIH857m{3B2}^eg;YyhCv>cD>?xn@Z1;z;>y$N(v_bq` z13_;`+yatNp295U8u0@eKTI6U<(YmeaU%jIU+dVWY2fiI(kRFBic#Na)WM&2&rth+h`gr=e5yFdIE7r0FOR1nT#bMZ0P%Fd9047 zShwRia@$D^{J*860Ma|5y%OOIGDhlEoPd>Z>DL~75=TCwM=|K{(?8)J2ZrXT_!N(0 zC{nNMDH!s&o6zYVDN?vq81lFmGkp^G+=ShR{;LAze4CKz1zyG=8sK?;3Ql*IUMl6K zeL5JFSJCrOZYc#^`I4MW?oZ&Le>I8}?qwMAd22{Qc_=S+0G0O*$Z8Hm_63w?&Y(p4 z<3=*IQ=(ZM%xP70=;WjEUd9z}3GIvCk0OP;3j;z7l>IJn^GX3H91*Qo-2u`Y*u=*q kWTbG!bIW00Bi;s#c%JE?{qDt}n&jiva0pjnQ>5bk31q$OlK=n! literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyutils.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyutils.lst new file mode 100644 index 0000000..79ff8f8 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyutils.lst @@ -0,0 +1,705 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "cyutils.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .section .text.CySetReg24,"ax",%progbits + 20 .align 2 + 21 .global CySetReg24 + 22 .code 16 + 23 .thumb_func + 24 .type CySetReg24, %function + 25 CySetReg24: + 26 .LFB0: + 27 .file 1 "Generated_Source\\PSoC4\\cyutils.c" + 1:Generated_Source\PSoC4/cyutils.c **** /***************************************************************************//** + 2:Generated_Source\PSoC4/cyutils.c **** * \file cyutils.c + 3:Generated_Source\PSoC4/cyutils.c **** * \version 5.70 + 4:Generated_Source\PSoC4/cyutils.c **** * + 5:Generated_Source\PSoC4/cyutils.c **** * \brief Provides a function to handle 24-bit value writes. + 6:Generated_Source\PSoC4/cyutils.c **** * + 7:Generated_Source\PSoC4/cyutils.c **** ******************************************************************************** + 8:Generated_Source\PSoC4/cyutils.c **** * \copyright + 9:Generated_Source\PSoC4/cyutils.c **** * Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. + 10:Generated_Source\PSoC4/cyutils.c **** * You may use this file only in accordance with the license, terms, conditions, + 11:Generated_Source\PSoC4/cyutils.c **** * disclaimers, and limitations in the end user license agreement accompanying + 12:Generated_Source\PSoC4/cyutils.c **** * the software package with which this file was provided. + 13:Generated_Source\PSoC4/cyutils.c **** *******************************************************************************/ + 14:Generated_Source\PSoC4/cyutils.c **** + 15:Generated_Source\PSoC4/cyutils.c **** #include "cytypes.h" + 16:Generated_Source\PSoC4/cyutils.c **** + 17:Generated_Source\PSoC4/cyutils.c **** #if (!CY_PSOC3) + 18:Generated_Source\PSoC4/cyutils.c **** + 19:Generated_Source\PSoC4/cyutils.c **** /*************************************************************************** + 20:Generated_Source\PSoC4/cyutils.c **** * Function Name: CySetReg24 + 21:Generated_Source\PSoC4/cyutils.c **** ************************************************************************//** + 22:Generated_Source\PSoC4/cyutils.c **** * + 23:Generated_Source\PSoC4/cyutils.c **** * Writes a 24-bit value to the specified register. + 24:Generated_Source\PSoC4/cyutils.c **** * + 25:Generated_Source\PSoC4/cyutils.c **** * \param addr The address where data must be written. + 26:Generated_Source\PSoC4/cyutils.c **** * \param value The data that must be written. + 27:Generated_Source\PSoC4/cyutils.c **** * + 28:Generated_Source\PSoC4/cyutils.c **** * \reentrant No + 29:Generated_Source\PSoC4/cyutils.c **** * + 30:Generated_Source\PSoC4/cyutils.c **** ***************************************************************************/ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 2 + + + 31:Generated_Source\PSoC4/cyutils.c **** void CySetReg24(uint32 volatile * addr, uint32 value) + 32:Generated_Source\PSoC4/cyutils.c **** { + 28 .loc 1 32 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 16 + 31 @ frame_needed = 1, uses_anonymous_args = 0 + 32 0000 80B5 push {r7, lr} + 33 .cfi_def_cfa_offset 8 + 34 .cfi_offset 7, -8 + 35 .cfi_offset 14, -4 + 36 0002 84B0 sub sp, sp, #16 + 37 .cfi_def_cfa_offset 24 + 38 0004 00AF add r7, sp, #0 + 39 .cfi_def_cfa_register 7 + 40 0006 7860 str r0, [r7, #4] + 41 0008 3960 str r1, [r7] + 33:Generated_Source\PSoC4/cyutils.c **** uint8 volatile *tmpAddr; + 34:Generated_Source\PSoC4/cyutils.c **** + 35:Generated_Source\PSoC4/cyutils.c **** tmpAddr = (uint8 volatile *) addr; + 42 .loc 1 35 0 + 43 000a 7B68 ldr r3, [r7, #4] + 44 000c FB60 str r3, [r7, #12] + 36:Generated_Source\PSoC4/cyutils.c **** + 37:Generated_Source\PSoC4/cyutils.c **** tmpAddr[0u] = (uint8) value; + 45 .loc 1 37 0 + 46 000e 3B68 ldr r3, [r7] + 47 0010 DAB2 uxtb r2, r3 + 48 0012 FB68 ldr r3, [r7, #12] + 49 0014 1A70 strb r2, [r3] + 38:Generated_Source\PSoC4/cyutils.c **** tmpAddr[1u] = (uint8) (value >> 8u); + 50 .loc 1 38 0 + 51 0016 FB68 ldr r3, [r7, #12] + 52 0018 0133 adds r3, r3, #1 + 53 001a 3A68 ldr r2, [r7] + 54 001c 120A lsrs r2, r2, #8 + 55 001e D2B2 uxtb r2, r2 + 56 0020 1A70 strb r2, [r3] + 39:Generated_Source\PSoC4/cyutils.c **** tmpAddr[2u] = (uint8) (value >> 16u); + 57 .loc 1 39 0 + 58 0022 FB68 ldr r3, [r7, #12] + 59 0024 0233 adds r3, r3, #2 + 60 0026 3A68 ldr r2, [r7] + 61 0028 120C lsrs r2, r2, #16 + 62 002a D2B2 uxtb r2, r2 + 63 002c 1A70 strb r2, [r3] + 40:Generated_Source\PSoC4/cyutils.c **** } + 64 .loc 1 40 0 + 65 002e C046 nop + 66 0030 BD46 mov sp, r7 + 67 0032 04B0 add sp, sp, #16 + 68 @ sp needed + 69 0034 80BD pop {r7, pc} + 70 .cfi_endproc + 71 .LFE0: + 72 .size CySetReg24, .-CySetReg24 + 73 0036 C046 .section .text.CyGetReg24,"ax",%progbits + 74 .align 2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 3 + + + 75 .global CyGetReg24 + 76 .code 16 + 77 .thumb_func + 78 .type CyGetReg24, %function + 79 CyGetReg24: + 80 .LFB1: + 41:Generated_Source\PSoC4/cyutils.c **** + 42:Generated_Source\PSoC4/cyutils.c **** + 43:Generated_Source\PSoC4/cyutils.c **** #if(CY_PSOC4) + 44:Generated_Source\PSoC4/cyutils.c **** + 45:Generated_Source\PSoC4/cyutils.c **** /*************************************************************************** + 46:Generated_Source\PSoC4/cyutils.c **** * Function Name: CyGetReg24 + 47:Generated_Source\PSoC4/cyutils.c **** ************************************************************************//** + 48:Generated_Source\PSoC4/cyutils.c **** * + 49:Generated_Source\PSoC4/cyutils.c **** * Reads the 24-bit value from the specified register. + 50:Generated_Source\PSoC4/cyutils.c **** * + 51:Generated_Source\PSoC4/cyutils.c **** * \param addr The address where data must be read. + 52:Generated_Source\PSoC4/cyutils.c **** * + 53:Generated_Source\PSoC4/cyutils.c **** * \reentrant No + 54:Generated_Source\PSoC4/cyutils.c **** * + 55:Generated_Source\PSoC4/cyutils.c **** ***************************************************************************/ + 56:Generated_Source\PSoC4/cyutils.c **** uint32 CyGetReg24(uint32 const volatile * addr) + 57:Generated_Source\PSoC4/cyutils.c **** { + 81 .loc 1 57 0 + 82 .cfi_startproc + 83 @ args = 0, pretend = 0, frame = 16 + 84 @ frame_needed = 1, uses_anonymous_args = 0 + 85 0000 80B5 push {r7, lr} + 86 .cfi_def_cfa_offset 8 + 87 .cfi_offset 7, -8 + 88 .cfi_offset 14, -4 + 89 0002 84B0 sub sp, sp, #16 + 90 .cfi_def_cfa_offset 24 + 91 0004 00AF add r7, sp, #0 + 92 .cfi_def_cfa_register 7 + 93 0006 7860 str r0, [r7, #4] + 58:Generated_Source\PSoC4/cyutils.c **** uint8 const volatile *tmpAddr; + 59:Generated_Source\PSoC4/cyutils.c **** uint32 value; + 60:Generated_Source\PSoC4/cyutils.c **** + 61:Generated_Source\PSoC4/cyutils.c **** tmpAddr = (uint8 const volatile *) addr; + 94 .loc 1 61 0 + 95 0008 7B68 ldr r3, [r7, #4] + 96 000a FB60 str r3, [r7, #12] + 62:Generated_Source\PSoC4/cyutils.c **** + 63:Generated_Source\PSoC4/cyutils.c **** value = (uint32) tmpAddr[0u]; + 97 .loc 1 63 0 + 98 000c FB68 ldr r3, [r7, #12] + 99 000e 1B78 ldrb r3, [r3] + 100 0010 DBB2 uxtb r3, r3 + 101 0012 BB60 str r3, [r7, #8] + 64:Generated_Source\PSoC4/cyutils.c **** value |= ((uint32) tmpAddr[1u] << 8u ); + 102 .loc 1 64 0 + 103 0014 FB68 ldr r3, [r7, #12] + 104 0016 0133 adds r3, r3, #1 + 105 0018 1B78 ldrb r3, [r3] + 106 001a DBB2 uxtb r3, r3 + 107 001c 1B02 lsls r3, r3, #8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 4 + + + 108 001e BA68 ldr r2, [r7, #8] + 109 0020 1343 orrs r3, r2 + 110 0022 BB60 str r3, [r7, #8] + 65:Generated_Source\PSoC4/cyutils.c **** value |= ((uint32) tmpAddr[2u] << 16u); + 111 .loc 1 65 0 + 112 0024 FB68 ldr r3, [r7, #12] + 113 0026 0233 adds r3, r3, #2 + 114 0028 1B78 ldrb r3, [r3] + 115 002a DBB2 uxtb r3, r3 + 116 002c 1B04 lsls r3, r3, #16 + 117 002e BA68 ldr r2, [r7, #8] + 118 0030 1343 orrs r3, r2 + 119 0032 BB60 str r3, [r7, #8] + 66:Generated_Source\PSoC4/cyutils.c **** + 67:Generated_Source\PSoC4/cyutils.c **** return(value); + 120 .loc 1 67 0 + 121 0034 BB68 ldr r3, [r7, #8] + 68:Generated_Source\PSoC4/cyutils.c **** } + 122 .loc 1 68 0 + 123 0036 1800 movs r0, r3 + 124 0038 BD46 mov sp, r7 + 125 003a 04B0 add sp, sp, #16 + 126 @ sp needed + 127 003c 80BD pop {r7, pc} + 128 .cfi_endproc + 129 .LFE1: + 130 .size CyGetReg24, .-CyGetReg24 + 131 003e C046 .text + 132 .Letext0: + 133 .file 2 "Generated_Source\\PSoC4\\cytypes.h" + 134 .section .debug_info,"",%progbits + 135 .Ldebug_info0: + 136 0000 45010000 .4byte 0x145 + 137 0004 0400 .2byte 0x4 + 138 0006 00000000 .4byte .Ldebug_abbrev0 + 139 000a 04 .byte 0x4 + 140 000b 01 .uleb128 0x1 + 141 000c BD000000 .4byte .LASF17 + 142 0010 0C .byte 0xc + 143 0011 7D010000 .4byte .LASF18 + 144 0015 21000000 .4byte .LASF19 + 145 0019 00000000 .4byte .Ldebug_ranges0+0 + 146 001d 00000000 .4byte 0 + 147 0021 00000000 .4byte .Ldebug_line0 + 148 0025 02 .uleb128 0x2 + 149 0026 01 .byte 0x1 + 150 0027 06 .byte 0x6 + 151 0028 CA010000 .4byte .LASF0 + 152 002c 02 .uleb128 0x2 + 153 002d 01 .byte 0x1 + 154 002e 08 .byte 0x8 + 155 002f 82000000 .4byte .LASF1 + 156 0033 02 .uleb128 0x2 + 157 0034 02 .byte 0x2 + 158 0035 05 .byte 0x5 + 159 0036 B1010000 .4byte .LASF2 + 160 003a 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 5 + + + 161 003b 02 .byte 0x2 + 162 003c 07 .byte 0x7 + 163 003d AA000000 .4byte .LASF3 + 164 0041 02 .uleb128 0x2 + 165 0042 04 .byte 0x4 + 166 0043 05 .byte 0x5 + 167 0044 C1010000 .4byte .LASF4 + 168 0048 02 .uleb128 0x2 + 169 0049 04 .byte 0x4 + 170 004a 07 .byte 0x7 + 171 004b 98000000 .4byte .LASF5 + 172 004f 02 .uleb128 0x2 + 173 0050 08 .byte 0x8 + 174 0051 05 .byte 0x5 + 175 0052 9E010000 .4byte .LASF6 + 176 0056 02 .uleb128 0x2 + 177 0057 08 .byte 0x8 + 178 0058 07 .byte 0x7 + 179 0059 66010000 .4byte .LASF7 + 180 005d 03 .uleb128 0x3 + 181 005e 04 .byte 0x4 + 182 005f 05 .byte 0x5 + 183 0060 696E7400 .ascii "int\000" + 184 0064 02 .uleb128 0x2 + 185 0065 04 .byte 0x4 + 186 0066 07 .byte 0x7 + 187 0067 59010000 .4byte .LASF8 + 188 006b 04 .uleb128 0x4 + 189 006c BB010000 .4byte .LASF9 + 190 0070 02 .byte 0x2 + 191 0071 E401 .2byte 0x1e4 + 192 0073 2C000000 .4byte 0x2c + 193 0077 04 .uleb128 0x4 + 194 0078 52010000 .4byte .LASF10 + 195 007c 02 .byte 0x2 + 196 007d E601 .2byte 0x1e6 + 197 007f 48000000 .4byte 0x48 + 198 0083 02 .uleb128 0x2 + 199 0084 04 .byte 0x4 + 200 0085 04 .byte 0x4 + 201 0086 7C000000 .4byte .LASF11 + 202 008a 02 .uleb128 0x2 + 203 008b 08 .byte 0x8 + 204 008c 04 .byte 0x4 + 205 008d 4B010000 .4byte .LASF12 + 206 0091 02 .uleb128 0x2 + 207 0092 01 .byte 0x1 + 208 0093 08 .byte 0x8 + 209 0094 AC010000 .4byte .LASF13 + 210 0098 05 .uleb128 0x5 + 211 0099 6B000000 .4byte 0x6b + 212 009d 05 .uleb128 0x5 + 213 009e 77000000 .4byte 0x77 + 214 00a2 06 .uleb128 0x6 + 215 00a3 16000000 .4byte .LASF20 + 216 00a7 01 .byte 0x1 + 217 00a8 1F .byte 0x1f + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 6 + + + 218 00a9 00000000 .4byte .LFB0 + 219 00ad 36000000 .4byte .LFE0-.LFB0 + 220 00b1 01 .uleb128 0x1 + 221 00b2 9C .byte 0x9c + 222 00b3 E2000000 .4byte 0xe2 + 223 00b7 07 .uleb128 0x7 + 224 00b8 00000000 .4byte .LASF14 + 225 00bc 01 .byte 0x1 + 226 00bd 1F .byte 0x1f + 227 00be E2000000 .4byte 0xe2 + 228 00c2 02 .uleb128 0x2 + 229 00c3 91 .byte 0x91 + 230 00c4 6C .sleb128 -20 + 231 00c5 07 .uleb128 0x7 + 232 00c6 05000000 .4byte .LASF15 + 233 00ca 01 .byte 0x1 + 234 00cb 1F .byte 0x1f + 235 00cc 77000000 .4byte 0x77 + 236 00d0 02 .uleb128 0x2 + 237 00d1 91 .byte 0x91 + 238 00d2 68 .sleb128 -24 + 239 00d3 08 .uleb128 0x8 + 240 00d4 90000000 .4byte .LASF16 + 241 00d8 01 .byte 0x1 + 242 00d9 21 .byte 0x21 + 243 00da E8000000 .4byte 0xe8 + 244 00de 02 .uleb128 0x2 + 245 00df 91 .byte 0x91 + 246 00e0 74 .sleb128 -12 + 247 00e1 00 .byte 0 + 248 00e2 09 .uleb128 0x9 + 249 00e3 04 .byte 0x4 + 250 00e4 9D000000 .4byte 0x9d + 251 00e8 09 .uleb128 0x9 + 252 00e9 04 .byte 0x4 + 253 00ea 98000000 .4byte 0x98 + 254 00ee 0A .uleb128 0xa + 255 00ef 0B000000 .4byte .LASF21 + 256 00f3 01 .byte 0x1 + 257 00f4 38 .byte 0x38 + 258 00f5 77000000 .4byte 0x77 + 259 00f9 00000000 .4byte .LFB1 + 260 00fd 3E000000 .4byte .LFE1-.LFB1 + 261 0101 01 .uleb128 0x1 + 262 0102 9C .byte 0x9c + 263 0103 32010000 .4byte 0x132 + 264 0107 07 .uleb128 0x7 + 265 0108 00000000 .4byte .LASF14 + 266 010c 01 .byte 0x1 + 267 010d 38 .byte 0x38 + 268 010e 32010000 .4byte 0x132 + 269 0112 02 .uleb128 0x2 + 270 0113 91 .byte 0x91 + 271 0114 6C .sleb128 -20 + 272 0115 08 .uleb128 0x8 + 273 0116 90000000 .4byte .LASF16 + 274 011a 01 .byte 0x1 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 7 + + + 275 011b 3A .byte 0x3a + 276 011c 3D010000 .4byte 0x13d + 277 0120 02 .uleb128 0x2 + 278 0121 91 .byte 0x91 + 279 0122 74 .sleb128 -12 + 280 0123 08 .uleb128 0x8 + 281 0124 05000000 .4byte .LASF15 + 282 0128 01 .byte 0x1 + 283 0129 3B .byte 0x3b + 284 012a 77000000 .4byte 0x77 + 285 012e 02 .uleb128 0x2 + 286 012f 91 .byte 0x91 + 287 0130 70 .sleb128 -16 + 288 0131 00 .byte 0 + 289 0132 09 .uleb128 0x9 + 290 0133 04 .byte 0x4 + 291 0134 38010000 .4byte 0x138 + 292 0138 0B .uleb128 0xb + 293 0139 9D000000 .4byte 0x9d + 294 013d 09 .uleb128 0x9 + 295 013e 04 .byte 0x4 + 296 013f 43010000 .4byte 0x143 + 297 0143 0B .uleb128 0xb + 298 0144 98000000 .4byte 0x98 + 299 0148 00 .byte 0 + 300 .section .debug_abbrev,"",%progbits + 301 .Ldebug_abbrev0: + 302 0000 01 .uleb128 0x1 + 303 0001 11 .uleb128 0x11 + 304 0002 01 .byte 0x1 + 305 0003 25 .uleb128 0x25 + 306 0004 0E .uleb128 0xe + 307 0005 13 .uleb128 0x13 + 308 0006 0B .uleb128 0xb + 309 0007 03 .uleb128 0x3 + 310 0008 0E .uleb128 0xe + 311 0009 1B .uleb128 0x1b + 312 000a 0E .uleb128 0xe + 313 000b 55 .uleb128 0x55 + 314 000c 17 .uleb128 0x17 + 315 000d 11 .uleb128 0x11 + 316 000e 01 .uleb128 0x1 + 317 000f 10 .uleb128 0x10 + 318 0010 17 .uleb128 0x17 + 319 0011 00 .byte 0 + 320 0012 00 .byte 0 + 321 0013 02 .uleb128 0x2 + 322 0014 24 .uleb128 0x24 + 323 0015 00 .byte 0 + 324 0016 0B .uleb128 0xb + 325 0017 0B .uleb128 0xb + 326 0018 3E .uleb128 0x3e + 327 0019 0B .uleb128 0xb + 328 001a 03 .uleb128 0x3 + 329 001b 0E .uleb128 0xe + 330 001c 00 .byte 0 + 331 001d 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 8 + + + 332 001e 03 .uleb128 0x3 + 333 001f 24 .uleb128 0x24 + 334 0020 00 .byte 0 + 335 0021 0B .uleb128 0xb + 336 0022 0B .uleb128 0xb + 337 0023 3E .uleb128 0x3e + 338 0024 0B .uleb128 0xb + 339 0025 03 .uleb128 0x3 + 340 0026 08 .uleb128 0x8 + 341 0027 00 .byte 0 + 342 0028 00 .byte 0 + 343 0029 04 .uleb128 0x4 + 344 002a 16 .uleb128 0x16 + 345 002b 00 .byte 0 + 346 002c 03 .uleb128 0x3 + 347 002d 0E .uleb128 0xe + 348 002e 3A .uleb128 0x3a + 349 002f 0B .uleb128 0xb + 350 0030 3B .uleb128 0x3b + 351 0031 05 .uleb128 0x5 + 352 0032 49 .uleb128 0x49 + 353 0033 13 .uleb128 0x13 + 354 0034 00 .byte 0 + 355 0035 00 .byte 0 + 356 0036 05 .uleb128 0x5 + 357 0037 35 .uleb128 0x35 + 358 0038 00 .byte 0 + 359 0039 49 .uleb128 0x49 + 360 003a 13 .uleb128 0x13 + 361 003b 00 .byte 0 + 362 003c 00 .byte 0 + 363 003d 06 .uleb128 0x6 + 364 003e 2E .uleb128 0x2e + 365 003f 01 .byte 0x1 + 366 0040 3F .uleb128 0x3f + 367 0041 19 .uleb128 0x19 + 368 0042 03 .uleb128 0x3 + 369 0043 0E .uleb128 0xe + 370 0044 3A .uleb128 0x3a + 371 0045 0B .uleb128 0xb + 372 0046 3B .uleb128 0x3b + 373 0047 0B .uleb128 0xb + 374 0048 27 .uleb128 0x27 + 375 0049 19 .uleb128 0x19 + 376 004a 11 .uleb128 0x11 + 377 004b 01 .uleb128 0x1 + 378 004c 12 .uleb128 0x12 + 379 004d 06 .uleb128 0x6 + 380 004e 40 .uleb128 0x40 + 381 004f 18 .uleb128 0x18 + 382 0050 9742 .uleb128 0x2117 + 383 0052 19 .uleb128 0x19 + 384 0053 01 .uleb128 0x1 + 385 0054 13 .uleb128 0x13 + 386 0055 00 .byte 0 + 387 0056 00 .byte 0 + 388 0057 07 .uleb128 0x7 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 9 + + + 389 0058 05 .uleb128 0x5 + 390 0059 00 .byte 0 + 391 005a 03 .uleb128 0x3 + 392 005b 0E .uleb128 0xe + 393 005c 3A .uleb128 0x3a + 394 005d 0B .uleb128 0xb + 395 005e 3B .uleb128 0x3b + 396 005f 0B .uleb128 0xb + 397 0060 49 .uleb128 0x49 + 398 0061 13 .uleb128 0x13 + 399 0062 02 .uleb128 0x2 + 400 0063 18 .uleb128 0x18 + 401 0064 00 .byte 0 + 402 0065 00 .byte 0 + 403 0066 08 .uleb128 0x8 + 404 0067 34 .uleb128 0x34 + 405 0068 00 .byte 0 + 406 0069 03 .uleb128 0x3 + 407 006a 0E .uleb128 0xe + 408 006b 3A .uleb128 0x3a + 409 006c 0B .uleb128 0xb + 410 006d 3B .uleb128 0x3b + 411 006e 0B .uleb128 0xb + 412 006f 49 .uleb128 0x49 + 413 0070 13 .uleb128 0x13 + 414 0071 02 .uleb128 0x2 + 415 0072 18 .uleb128 0x18 + 416 0073 00 .byte 0 + 417 0074 00 .byte 0 + 418 0075 09 .uleb128 0x9 + 419 0076 0F .uleb128 0xf + 420 0077 00 .byte 0 + 421 0078 0B .uleb128 0xb + 422 0079 0B .uleb128 0xb + 423 007a 49 .uleb128 0x49 + 424 007b 13 .uleb128 0x13 + 425 007c 00 .byte 0 + 426 007d 00 .byte 0 + 427 007e 0A .uleb128 0xa + 428 007f 2E .uleb128 0x2e + 429 0080 01 .byte 0x1 + 430 0081 3F .uleb128 0x3f + 431 0082 19 .uleb128 0x19 + 432 0083 03 .uleb128 0x3 + 433 0084 0E .uleb128 0xe + 434 0085 3A .uleb128 0x3a + 435 0086 0B .uleb128 0xb + 436 0087 3B .uleb128 0x3b + 437 0088 0B .uleb128 0xb + 438 0089 27 .uleb128 0x27 + 439 008a 19 .uleb128 0x19 + 440 008b 49 .uleb128 0x49 + 441 008c 13 .uleb128 0x13 + 442 008d 11 .uleb128 0x11 + 443 008e 01 .uleb128 0x1 + 444 008f 12 .uleb128 0x12 + 445 0090 06 .uleb128 0x6 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 10 + + + 446 0091 40 .uleb128 0x40 + 447 0092 18 .uleb128 0x18 + 448 0093 9742 .uleb128 0x2117 + 449 0095 19 .uleb128 0x19 + 450 0096 01 .uleb128 0x1 + 451 0097 13 .uleb128 0x13 + 452 0098 00 .byte 0 + 453 0099 00 .byte 0 + 454 009a 0B .uleb128 0xb + 455 009b 26 .uleb128 0x26 + 456 009c 00 .byte 0 + 457 009d 49 .uleb128 0x49 + 458 009e 13 .uleb128 0x13 + 459 009f 00 .byte 0 + 460 00a0 00 .byte 0 + 461 00a1 00 .byte 0 + 462 .section .debug_aranges,"",%progbits + 463 0000 24000000 .4byte 0x24 + 464 0004 0200 .2byte 0x2 + 465 0006 00000000 .4byte .Ldebug_info0 + 466 000a 04 .byte 0x4 + 467 000b 00 .byte 0 + 468 000c 0000 .2byte 0 + 469 000e 0000 .2byte 0 + 470 0010 00000000 .4byte .LFB0 + 471 0014 36000000 .4byte .LFE0-.LFB0 + 472 0018 00000000 .4byte .LFB1 + 473 001c 3E000000 .4byte .LFE1-.LFB1 + 474 0020 00000000 .4byte 0 + 475 0024 00000000 .4byte 0 + 476 .section .debug_ranges,"",%progbits + 477 .Ldebug_ranges0: + 478 0000 00000000 .4byte .LFB0 + 479 0004 36000000 .4byte .LFE0 + 480 0008 00000000 .4byte .LFB1 + 481 000c 3E000000 .4byte .LFE1 + 482 0010 00000000 .4byte 0 + 483 0014 00000000 .4byte 0 + 484 .section .debug_line,"",%progbits + 485 .Ldebug_line0: + 486 0000 73000000 .section .debug_str,"MS",%progbits,1 + 486 02004400 + 486 00000201 + 486 FB0E0D00 + 486 01010101 + 487 .LASF14: + 488 0000 61646472 .ascii "addr\000" + 488 00 + 489 .LASF15: + 490 0005 76616C75 .ascii "value\000" + 490 6500 + 491 .LASF21: + 492 000b 43794765 .ascii "CyGetReg24\000" + 492 74526567 + 492 323400 + 493 .LASF20: + 494 0016 43795365 .ascii "CySetReg24\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 11 + + + 494 74526567 + 494 323400 + 495 .LASF19: + 496 0021 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 496 73657273 + 496 5C6A6167 + 496 756D6965 + 496 6C5C446F + 497 004f 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 497 50536F43 + 497 2D313031 + 497 5C547261 + 497 696E696E + 498 .LASF11: + 499 007c 666C6F61 .ascii "float\000" + 499 7400 + 500 .LASF1: + 501 0082 756E7369 .ascii "unsigned char\000" + 501 676E6564 + 501 20636861 + 501 7200 + 502 .LASF16: + 503 0090 746D7041 .ascii "tmpAddr\000" + 503 64647200 + 504 .LASF5: + 505 0098 6C6F6E67 .ascii "long unsigned int\000" + 505 20756E73 + 505 69676E65 + 505 6420696E + 505 7400 + 506 .LASF3: + 507 00aa 73686F72 .ascii "short unsigned int\000" + 507 7420756E + 507 7369676E + 507 65642069 + 507 6E7400 + 508 .LASF17: + 509 00bd 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 509 43313120 + 509 352E342E + 509 31203230 + 509 31363036 + 510 00f0 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 510 20726576 + 510 6973696F + 510 6E203233 + 510 37373135 + 511 0123 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 511 66756E63 + 511 74696F6E + 511 2D736563 + 511 74696F6E + 512 .LASF12: + 513 014b 646F7562 .ascii "double\000" + 513 6C6500 + 514 .LASF10: + 515 0152 75696E74 .ascii "uint32\000" + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\ccjv6qAT.s page 12 + + + 515 333200 + 516 .LASF8: + 517 0159 756E7369 .ascii "unsigned int\000" + 517 676E6564 + 517 20696E74 + 517 00 + 518 .LASF7: + 519 0166 6C6F6E67 .ascii "long long unsigned int\000" + 519 206C6F6E + 519 6720756E + 519 7369676E + 519 65642069 + 520 .LASF18: + 521 017d 47656E65 .ascii "Generated_Source\\PSoC4\\cyutils.c\000" + 521 72617465 + 521 645F536F + 521 75726365 + 521 5C50536F + 522 .LASF6: + 523 019e 6C6F6E67 .ascii "long long int\000" + 523 206C6F6E + 523 6720696E + 523 7400 + 524 .LASF13: + 525 01ac 63686172 .ascii "char\000" + 525 00 + 526 .LASF2: + 527 01b1 73686F72 .ascii "short int\000" + 527 7420696E + 527 7400 + 528 .LASF9: + 529 01bb 75696E74 .ascii "uint8\000" + 529 3800 + 530 .LASF4: + 531 01c1 6C6F6E67 .ascii "long int\000" + 531 20696E74 + 531 00 + 532 .LASF0: + 533 01ca 7369676E .ascii "signed char\000" + 533 65642063 + 533 68617200 + 534 .ident "GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyutils.o b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/cyutils.o new file mode 100644 index 0000000000000000000000000000000000000000..40432e8ec0f1e7a7f7d6c553496f2cac1836c6e2 GIT binary patch literal 3416 zcmbtWU2GIp6ux(Mx844*&=zP*jZBjYC1ICsDNstl)`eDr)LQ5Rp$fCR)7{10on~eh zX~aN;=#vH#j69%;`lKNdNk~va#1~_HGzJrWGsN(wKKNkzfZsPWw>vE)ns|~s-}$@e zo_p@SXZPHJ7sjQOLXi~xqAm$>ugSB-hCJvOonoyxf9v86@%fpPyHCDeTs*m_`18%h z;)eOfqTD`GY;XSICV7o~EBSllcgLeQ&fmQ^uI6#pVzKAUFE{T1<#uvC+E>Mn3}wxi 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zvDDF1=!vPknXMI0l&W(UCVRY*&7v8KkkvqoESLycpYXV*T&kKX1acCooK@jZLU`7k zZB*cdu9Grc*DhsiF2eqI>VYdtzVvcfpD?Kx+Y2TA)Qer|M;mD~2G8W*{I;j`0q)WIne*pQ8c;^_8`M-jp=71G{ zLHL+VK*}}`S@ATzkAm^-DN;7(9bWf57U7-by40(6FMwBbz>2RCkA8}j?Hm;0cvlfm zhmP^sLsh)@z^gf6#ZQQ*{yI`tw#(qd@opm?-yY+!E2?-Of#;kw25AxpeP0EEOqPT7 z5Bv4u?OD(%Qhr}TL0-`n_)RGR$aP7#Fv9tL7uqj-p~{c_1}X7aJbHk514;m@wKzxJ sQJNnj-hDCwDL*1gwnSaHBvVkXhX(&yy>(e9<`#}u#J%EMP^9Ah17UU8K>z>% literal 0 HcmV?d00001 diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/library.deps b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/library.deps new file mode 100644 index 0000000..ae88069 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/library.deps @@ -0,0 +1 @@ +D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ARM_GCC_541\Debug\ADC-UART.a : .\ARM_GCC_541\Debug\LED.o .\ARM_GCC_541\Debug\LED_PM.o .\ARM_GCC_541\Debug\UART.o .\ARM_GCC_541\Debug\UART_SPI_UART.o .\ARM_GCC_541\Debug\UART_SPI_UART_INT.o .\ARM_GCC_541\Debug\UART_PM.o .\ARM_GCC_541\Debug\UART_UART.o .\ARM_GCC_541\Debug\UART_BOOT.o .\ARM_GCC_541\Debug\UART_UART_BOOT.o .\ARM_GCC_541\Debug\Input_1.o .\ARM_GCC_541\Debug\Input_1_PM.o .\ARM_GCC_541\Debug\ADC.o .\ARM_GCC_541\Debug\ADC_PM.o .\ARM_GCC_541\Debug\ADC_INT.o .\ARM_GCC_541\Debug\UART_SCBCLK.o .\ARM_GCC_541\Debug\UART_tx.o .\ARM_GCC_541\Debug\UART_tx_PM.o .\ARM_GCC_541\Debug\ADC_IRQ.o .\ARM_GCC_541\Debug\ADC_intClock.o .\ARM_GCC_541\Debug\cy_em_eeprom.o .\ARM_GCC_541\Debug\CyFlash.o .\ARM_GCC_541\Debug\CyLib.o .\ARM_GCC_541\Debug\cyPm.o .\ARM_GCC_541\Debug\cyutils.o .\ARM_GCC_541\Debug\CyLFClk.o .\ARM_GCC_541\Debug\CyBootAsmGnu.o diff --git a/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/main.lst b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/main.lst new file mode 100644 index 0000000..72a5166 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/ARM_GCC_541/Debug/main.lst @@ -0,0 +1,1316 @@ +ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m0 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 6 + 11 .eabi_attribute 34, 0 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .syntax unified + 15 .file "main.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .global windowFlag + 20 .bss + 21 .align 2 + 22 .type windowFlag, %object + 23 .size windowFlag, 4 + 24 windowFlag: + 25 0000 00000000 .space 4 + 26 .global dataReady + 27 .type dataReady, %object + 28 .size dataReady, 1 + 29 dataReady: + 30 0004 00 .space 1 + 31 .global channelFlag + 32 .type channelFlag, %object + 33 .size channelFlag, 1 + 34 channelFlag: + 35 0005 00 .space 1 + 36 .section .text.main,"ax",%progbits + 37 .align 2 + 38 .global main + 39 .code 16 + 40 .thumb_func + 41 .type main, %function + 42 main: + 43 .LFB32: + 44 .file 1 "main.c" + 1:main.c **** /******************************************************************************* + 2:main.c **** * File Name: main.c + 3:main.c **** * + 4:main.c **** * Version: 2.00 + 5:main.c **** * + 6:main.c **** * Description: + 7:main.c **** * This example project shows how to sample four different channels using + 8:main.c **** * SAR MUX and ADC, and send channel output to HyperTerminal (PC) using UART. + 9:main.c **** * + 10:main.c **** ******************************************************************************** + 11:main.c **** * Copyright 2013-2018, Cypress Semiconductor Corporation. All rights reserved. + 12:main.c **** * This software is owned by Cypress Semiconductor Corporation and is protected + 13:main.c **** * by and subject to worldwide patent and copyright laws and treaties. + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 2 + + + 14:main.c **** * Therefore, you may use this software only as provided in the license agreement + 15:main.c **** * accompanying the software package from which you obtained this software. + 16:main.c **** * CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + 17:main.c **** * WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, + 18:main.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + 19:main.c **** *******************************************************************************/ + 20:main.c **** + 21:main.c **** #include + 22:main.c **** + 23:main.c **** /* Macro definitions */ + 24:main.c **** #define LOW (0u) + 25:main.c **** #define HIGH (1u) + 26:main.c **** #define CHANNEL_1 (0u) + 27:main.c **** #define NO_OF_CHANNELS (1u) + 28:main.c **** #define CLEAR_SCREEN (0x0C) + 29:main.c **** #define CONVERT_TO_ASCII (0x30u) + 30:main.c **** + 31:main.c **** /* Resistor Values and Gain */ + 32:main.c **** #define RG (2200u) + 33:main.c **** #define R1 (10000u) + 34:main.c **** #define GAIN (1 + 2 * (float)R1 / RG) + 35:main.c **** + 36:main.c **** /* Send the channel number and voltage to UART */ + 37:main.c **** static void SendChannelVoltage(uint8 channel, int16 mVolts); + 38:main.c **** + 39:main.c **** /* Interrupt prototypes */ + 40:main.c **** CY_ISR_PROTO(ADC_ISR_Handler); + 41:main.c **** + 42:main.c **** /* Global variables */ + 43:main.c **** volatile uint32 windowFlag = 0u; + 44:main.c **** volatile uint8 dataReady = 0u; + 45:main.c **** volatile uint8 channelFlag = 0u; + 46:main.c **** + 47:main.c **** + 48:main.c **** /******************************************************************************* + 49:main.c **** * Function Name: main + 50:main.c **** ******************************************************************************** + 51:main.c **** * + 52:main.c **** * Summary: + 53:main.c **** * Performs the following tasks: + 54:main.c **** * - Start the components. + 55:main.c **** * - Starts ADC conversion. + 56:main.c **** * - Buffer ADC results. + 57:main.c **** * - Sends the result to HyperTerminal (PC) using UART. + 58:main.c **** * - Turns ON an LED when ADC input is outside the voltage + 59:main.c **** * window of 1250mV to 3750mV. + 60:main.c **** * + 61:main.c **** * Parameters: + 62:main.c **** * None. + 63:main.c **** * + 64:main.c **** * Return: + 65:main.c **** * None. + 66:main.c **** * + 67:main.c **** *******************************************************************************/ + 68:main.c **** int main() + 69:main.c **** { + 45 .loc 1 69 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 3 + + + 46 .cfi_startproc + 47 @ args = 0, pretend = 0, frame = 16 + 48 @ frame_needed = 1, uses_anonymous_args = 0 + 49 0000 90B5 push {r4, r7, lr} + 50 .cfi_def_cfa_offset 12 + 51 .cfi_offset 4, -12 + 52 .cfi_offset 7, -8 + 53 .cfi_offset 14, -4 + 54 0002 85B0 sub sp, sp, #20 + 55 .cfi_def_cfa_offset 32 + 56 0004 00AF add r7, sp, #0 + 57 .cfi_def_cfa_register 7 + 70:main.c **** uint8 channel = CHANNEL_1; + 58 .loc 1 70 0 + 59 0006 0D23 movs r3, #13 + 60 0008 FB18 adds r3, r7, r3 + 61 000a 0022 movs r2, #0 + 62 000c 1A70 strb r2, [r3] + 71:main.c **** int16 adcVal[4u]; + 72:main.c **** int16 mVolts; + 73:main.c **** int16 previousValue = 0; + 63 .loc 1 73 0 + 64 000e 0E23 movs r3, #14 + 65 0010 FB18 adds r3, r7, r3 + 66 0012 0022 movs r2, #0 + 67 0014 1A80 strh r2, [r3] + 74:main.c **** + 75:main.c **** /* Start the Components */ + 76:main.c **** UART_Start(); + 68 .loc 1 76 0 + 69 0016 FFF7FEFF bl UART_Start + 77:main.c **** ADC_Start(); + 70 .loc 1 77 0 + 71 001a FFF7FEFF bl ADC_Start + 78:main.c **** + 79:main.c **** /* Start ISRs */ + 80:main.c **** ADC_IRQ_StartEx(ADC_ISR_Handler); + 72 .loc 1 80 0 + 73 001e 2B4B ldr r3, .L8 + 74 0020 1800 movs r0, r3 + 75 0022 FFF7FEFF bl ADC_IRQ_StartEx + 81:main.c **** + 82:main.c **** /* Enable global interrupts */ + 83:main.c **** CyGlobalIntEnable; + 76 .loc 1 83 0 + 77 .syntax divided + 78 @ 83 "main.c" 1 + 79 0026 62B6 CPSIE i + 80 @ 0 "" 2 + 84:main.c **** + 85:main.c **** /* Start ADC conversion */ + 86:main.c **** ADC_StartConvert(); + 81 .loc 1 86 0 + 82 .thumb + 83 .syntax unified + 84 0028 FFF7FEFF bl ADC_StartConvert + 85 .L7: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 4 + + + 87:main.c **** + 88:main.c **** for(;;) + 89:main.c **** { + 90:main.c **** while(dataReady == 0u) + 86 .loc 1 90 0 + 87 002c C046 nop + 88 .L2: + 89 .loc 1 90 0 is_stmt 0 discriminator 1 + 90 002e 284B ldr r3, .L8+4 + 91 0030 1B78 ldrb r3, [r3] + 92 0032 DBB2 uxtb r3, r3 + 93 0034 002B cmp r3, #0 + 94 0036 FAD0 beq .L2 + 91:main.c **** { + 92:main.c **** ; /* Wait for ADC conversion */ + 93:main.c **** } + 94:main.c **** /* Buffer the results */ + 95:main.c **** adcVal[CHANNEL_1] = ADC_GetResult16(CHANNEL_1); + 95 .loc 1 95 0 is_stmt 1 + 96 0038 0020 movs r0, #0 + 97 003a FFF7FEFF bl ADC_GetResult16 + 98 003e 0300 movs r3, r0 + 99 0040 1A00 movs r2, r3 + 100 0042 3B00 movs r3, r7 + 101 0044 1A80 strh r2, [r3] + 96:main.c **** + 97:main.c **** /* Check for ADC window limit interrupt */ + 98:main.c **** if(windowFlag != 0u) + 102 .loc 1 98 0 + 103 0046 234B ldr r3, .L8+8 + 104 0048 1B68 ldr r3, [r3] + 105 004a 002B cmp r3, #0 + 106 004c 03D0 beq .L3 + 99:main.c **** { + 100:main.c **** /* Turn ON the LED when input is outside the voltage window (1250mV - 3750mV) */ + 101:main.c **** LED_Write(LOW); + 107 .loc 1 101 0 + 108 004e 0020 movs r0, #0 + 109 0050 FFF7FEFF bl LED_Write + 110 0054 02E0 b .L4 + 111 .L3: + 102:main.c **** + 103:main.c **** /* Note: If LED is active HIGH, then replace "LOW" with "HIGH" */ + 104:main.c **** } + 105:main.c **** else + 106:main.c **** { + 107:main.c **** /* Turn OFF the LED when input is within the voltage window (250mV - 750mV) */ + 108:main.c **** LED_Write(HIGH); + 112 .loc 1 108 0 + 113 0056 0120 movs r0, #1 + 114 0058 FFF7FEFF bl LED_Write + 115 .L4: + 109:main.c **** + 110:main.c **** /* Note:If LED is active HIGH, then replace "HIGH" with "LOW" */ + 111:main.c **** } + 112:main.c **** + 113:main.c **** + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 5 + + + 114:main.c **** /* Convert the ADC counts of active channel to mVolts */ + 115:main.c **** mVolts = ADC_CountsTo_mVolts(channel, adcVal[channel]); + 116 .loc 1 115 0 + 117 005c 0D23 movs r3, #13 + 118 005e FB18 adds r3, r7, r3 + 119 0060 1878 ldrb r0, [r3] + 120 0062 0D23 movs r3, #13 + 121 0064 FB18 adds r3, r7, r3 + 122 0066 1A78 ldrb r2, [r3] + 123 0068 3B00 movs r3, r7 + 124 006a 5200 lsls r2, r2, #1 + 125 006c D35E ldrsh r3, [r2, r3] + 126 006e 0A22 movs r2, #10 + 127 0070 BC18 adds r4, r7, r2 + 128 0072 1900 movs r1, r3 + 129 0074 FFF7FEFF bl ADC_CountsTo_mVolts + 130 0078 0300 movs r3, r0 + 131 007a 2380 strh r3, [r4] + 116:main.c **** + 117:main.c **** /* If ADC result or channel has been changed, send the data to UART */ + 118:main.c **** if((previousValue != mVolts) || (channelFlag != 0u)) + 132 .loc 1 118 0 + 133 007c 0E23 movs r3, #14 + 134 007e FA18 adds r2, r7, r3 + 135 0080 0A23 movs r3, #10 + 136 0082 FB18 adds r3, r7, r3 + 137 0084 0021 movs r1, #0 + 138 0086 525E ldrsh r2, [r2, r1] + 139 0088 0021 movs r1, #0 + 140 008a 5B5E ldrsh r3, [r3, r1] + 141 008c 9A42 cmp r2, r3 + 142 008e 04D1 bne .L5 + 143 .loc 1 118 0 is_stmt 0 discriminator 1 + 144 0090 114B ldr r3, .L8+12 + 145 0092 1B78 ldrb r3, [r3] + 146 0094 DBB2 uxtb r3, r3 + 147 0096 002B cmp r3, #0 + 148 0098 13D0 beq .L6 + 149 .L5: + 119:main.c **** { + 120:main.c **** SendChannelVoltage(channel, mVolts); + 150 .loc 1 120 0 is_stmt 1 + 151 009a 0A23 movs r3, #10 + 152 009c FB18 adds r3, r7, r3 + 153 009e 0022 movs r2, #0 + 154 00a0 9A5E ldrsh r2, [r3, r2] + 155 00a2 0D23 movs r3, #13 + 156 00a4 FB18 adds r3, r7, r3 + 157 00a6 1B78 ldrb r3, [r3] + 158 00a8 1100 movs r1, r2 + 159 00aa 1800 movs r0, r3 + 160 00ac FFF7FEFF bl SendChannelVoltage + 121:main.c **** previousValue = mVolts; + 161 .loc 1 121 0 + 162 00b0 0E23 movs r3, #14 + 163 00b2 FB18 adds r3, r7, r3 + 164 00b4 0A22 movs r2, #10 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 6 + + + 165 00b6 BA18 adds r2, r7, r2 + 166 00b8 1288 ldrh r2, [r2] + 167 00ba 1A80 strh r2, [r3] + 122:main.c **** + 123:main.c **** /* Clear the flag */ + 124:main.c **** channelFlag = 0u; + 168 .loc 1 124 0 + 169 00bc 064B ldr r3, .L8+12 + 170 00be 0022 movs r2, #0 + 171 00c0 1A70 strb r2, [r3] + 172 .L6: + 125:main.c **** } + 126:main.c **** dataReady = 0u; + 173 .loc 1 126 0 + 174 00c2 034B ldr r3, .L8+4 + 175 00c4 0022 movs r2, #0 + 176 00c6 1A70 strb r2, [r3] + 127:main.c **** } + 177 .loc 1 127 0 + 178 00c8 B0E7 b .L7 + 179 .L9: + 180 00ca C046 .align 2 + 181 .L8: + 182 00cc 00000000 .word ADC_ISR_Handler + 183 00d0 00000000 .word dataReady + 184 00d4 00000000 .word windowFlag + 185 00d8 00000000 .word channelFlag + 186 .cfi_endproc + 187 .LFE32: + 188 .size main, .-main + 189 .section .rodata + 190 .align 2 + 191 .LC4: + 192 0000 4368616E .ascii "Channel \000" + 192 6E656C20 + 192 00 + 193 0009 000000 .align 2 + 194 .LC6: + 195 000c 203D2000 .ascii " = \000" + 196 .align 2 + 197 .LC8: + 198 0010 2D00 .ascii "-\000" + 199 .global __aeabi_uidiv + 200 .global __aeabi_uidivmod + 201 0012 0000 .align 2 + 202 .LC10: + 203 0014 206D5600 .ascii " mV\000" + 204 .section .text.SendChannelVoltage,"ax",%progbits + 205 .align 2 + 206 .code 16 + 207 .thumb_func + 208 .type SendChannelVoltage, %function + 209 SendChannelVoltage: + 210 .LFB33: + 128:main.c **** } + 129:main.c **** + 130:main.c **** /******************************************************************************* + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 7 + + + 131:main.c **** * Function Name: SendChannelVoltage + 132:main.c **** ******************************************************************************** + 133:main.c **** * + 134:main.c **** * Summary: + 135:main.c **** * Performs the following tasks: + 136:main.c **** * - Converts the channel number to ASCII character + 137:main.c **** * - Clears terminal screen + 138:main.c **** * - Sends the channel number and voltage to UART + 139:main.c **** * + 140:main.c **** * Parameters: + 141:main.c **** * uint8 channel : Channel Number + 142:main.c **** * int16 mVolts : ADC counts + 143:main.c **** * + 144:main.c **** * Return: + 145:main.c **** * None. + 146:main.c **** * + 147:main.c **** ********************************************************************************/ + 148:main.c **** static void SendChannelVoltage(uint8 channel, int16 mVolts) + 149:main.c **** { + 211 .loc 1 149 0 + 212 .cfi_startproc + 213 @ args = 0, pretend = 0, frame = 8 + 214 @ frame_needed = 1, uses_anonymous_args = 0 + 215 0000 80B5 push {r7, lr} + 216 .cfi_def_cfa_offset 8 + 217 .cfi_offset 7, -8 + 218 .cfi_offset 14, -4 + 219 0002 82B0 sub sp, sp, #8 + 220 .cfi_def_cfa_offset 16 + 221 0004 00AF add r7, sp, #0 + 222 .cfi_def_cfa_register 7 + 223 0006 0200 movs r2, r0 + 224 0008 FB1D adds r3, r7, #7 + 225 000a 1A70 strb r2, [r3] + 226 000c 3B1D adds r3, r7, #4 + 227 000e 0A1C adds r2, r1, #0 + 228 0010 1A80 strh r2, [r3] + 150:main.c **** /* Clear screen */ + 151:main.c **** UART_UartPutChar(CLEAR_SCREEN); + 229 .loc 1 151 0 + 230 0012 0C20 movs r0, #12 + 231 0014 FFF7FEFF bl UART_SpiUartWriteTxData + 152:main.c **** UART_UartPutString("Channel "); + 232 .loc 1 152 0 + 233 0018 3F4B ldr r3, .L12 + 234 001a 1800 movs r0, r3 + 235 001c FFF7FEFF bl UART_UartPutString + 153:main.c **** + 154:main.c **** /* Display the channel number starting from 1 */ + 155:main.c **** channel++; + 236 .loc 1 155 0 + 237 0020 FB1D adds r3, r7, #7 + 238 0022 1A78 ldrb r2, [r3] + 239 0024 FB1D adds r3, r7, #7 + 240 0026 0132 adds r2, r2, #1 + 241 0028 1A70 strb r2, [r3] + 156:main.c **** channel += CONVERT_TO_ASCII; + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 8 + + + 242 .loc 1 156 0 + 243 002a FB1D adds r3, r7, #7 + 244 002c FA1D adds r2, r7, #7 + 245 002e 1278 ldrb r2, [r2] + 246 0030 3032 adds r2, r2, #48 + 247 0032 1A70 strb r2, [r3] + 157:main.c **** UART_UartPutChar(channel); + 248 .loc 1 157 0 + 249 0034 FB1D adds r3, r7, #7 + 250 0036 1B78 ldrb r3, [r3] + 251 0038 1800 movs r0, r3 + 252 003a FFF7FEFF bl UART_SpiUartWriteTxData + 158:main.c **** UART_UartPutString(" = "); + 253 .loc 1 158 0 + 254 003e 374B ldr r3, .L12+4 + 255 0040 1800 movs r0, r3 + 256 0042 FFF7FEFF bl UART_UartPutString + 159:main.c **** + 160:main.c **** /* Find the sign of the result */ + 161:main.c **** if(mVolts < 0) + 257 .loc 1 161 0 + 258 0046 3B1D adds r3, r7, #4 + 259 0048 0022 movs r2, #0 + 260 004a 9B5E ldrsh r3, [r3, r2] + 261 004c 002B cmp r3, #0 + 262 004e 09DA bge .L11 + 162:main.c **** { + 163:main.c **** UART_UartPutString("-"); + 263 .loc 1 163 0 + 264 0050 334B ldr r3, .L12+8 + 265 0052 1800 movs r0, r3 + 266 0054 FFF7FEFF bl UART_UartPutString + 164:main.c **** mVolts = -mVolts; + 267 .loc 1 164 0 + 268 0058 3B1D adds r3, r7, #4 + 269 005a 1B88 ldrh r3, [r3] + 270 005c 5B42 rsbs r3, r3, #0 + 271 005e 9AB2 uxth r2, r3 + 272 0060 3B1D adds r3, r7, #4 + 273 0062 1A80 strh r2, [r3] + 274 .L11: + 165:main.c **** } + 166:main.c **** + 167:main.c **** /* Send voltage to UART */ + 168:main.c **** UART_UartPutChar((mVolts/1000u) + CONVERT_TO_ASCII); + 275 .loc 1 168 0 + 276 0064 3B1D adds r3, r7, #4 + 277 0066 0022 movs r2, #0 + 278 0068 9A5E ldrsh r2, [r3, r2] + 279 006a FA23 movs r3, #250 + 280 006c 9900 lsls r1, r3, #2 + 281 006e 1000 movs r0, r2 + 282 0070 FFF7FEFF bl __aeabi_uidiv + 283 0074 0300 movs r3, r0 + 284 0076 3033 adds r3, r3, #48 + 285 0078 1800 movs r0, r3 + 286 007a FFF7FEFF bl UART_SpiUartWriteTxData + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 9 + + + 169:main.c **** mVolts %= 1000u; + 287 .loc 1 169 0 + 288 007e 3B1D adds r3, r7, #4 + 289 0080 0022 movs r2, #0 + 290 0082 9A5E ldrsh r2, [r3, r2] + 291 0084 FA23 movs r3, #250 + 292 0086 9900 lsls r1, r3, #2 + 293 0088 1000 movs r0, r2 + 294 008a FFF7FEFF bl __aeabi_uidivmod + 295 008e 0B00 movs r3, r1 + 296 0090 1A00 movs r2, r3 + 297 0092 3B1D adds r3, r7, #4 + 298 0094 1A80 strh r2, [r3] + 170:main.c **** UART_UartPutChar((mVolts/100u) + CONVERT_TO_ASCII); + 299 .loc 1 170 0 + 300 0096 3B1D adds r3, r7, #4 + 301 0098 0022 movs r2, #0 + 302 009a 9B5E ldrsh r3, [r3, r2] + 303 009c 6421 movs r1, #100 + 304 009e 1800 movs r0, r3 + 305 00a0 FFF7FEFF bl __aeabi_uidiv + 306 00a4 0300 movs r3, r0 + 307 00a6 3033 adds r3, r3, #48 + 308 00a8 1800 movs r0, r3 + 309 00aa FFF7FEFF bl UART_SpiUartWriteTxData + 171:main.c **** mVolts %= 100u; + 310 .loc 1 171 0 + 311 00ae 3B1D adds r3, r7, #4 + 312 00b0 0022 movs r2, #0 + 313 00b2 9B5E ldrsh r3, [r3, r2] + 314 00b4 6421 movs r1, #100 + 315 00b6 1800 movs r0, r3 + 316 00b8 FFF7FEFF bl __aeabi_uidivmod + 317 00bc 0B00 movs r3, r1 + 318 00be 1A00 movs r2, r3 + 319 00c0 3B1D adds r3, r7, #4 + 320 00c2 1A80 strh r2, [r3] + 172:main.c **** UART_UartPutChar((mVolts/10u) + CONVERT_TO_ASCII); + 321 .loc 1 172 0 + 322 00c4 3B1D adds r3, r7, #4 + 323 00c6 0022 movs r2, #0 + 324 00c8 9B5E ldrsh r3, [r3, r2] + 325 00ca 0A21 movs r1, #10 + 326 00cc 1800 movs r0, r3 + 327 00ce FFF7FEFF bl __aeabi_uidiv + 328 00d2 0300 movs r3, r0 + 329 00d4 3033 adds r3, r3, #48 + 330 00d6 1800 movs r0, r3 + 331 00d8 FFF7FEFF bl UART_SpiUartWriteTxData + 173:main.c **** mVolts %= 10u; + 332 .loc 1 173 0 + 333 00dc 3B1D adds r3, r7, #4 + 334 00de 0022 movs r2, #0 + 335 00e0 9B5E ldrsh r3, [r3, r2] + 336 00e2 0A21 movs r1, #10 + 337 00e4 1800 movs r0, r3 + 338 00e6 FFF7FEFF bl __aeabi_uidivmod + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 10 + + + 339 00ea 0B00 movs r3, r1 + 340 00ec 1A00 movs r2, r3 + 341 00ee 3B1D adds r3, r7, #4 + 342 00f0 1A80 strh r2, [r3] + 174:main.c **** UART_UartPutChar(mVolts + CONVERT_TO_ASCII); + 343 .loc 1 174 0 + 344 00f2 3B1D adds r3, r7, #4 + 345 00f4 0022 movs r2, #0 + 346 00f6 9B5E ldrsh r3, [r3, r2] + 347 00f8 3033 adds r3, r3, #48 + 348 00fa 1800 movs r0, r3 + 349 00fc FFF7FEFF bl UART_SpiUartWriteTxData + 175:main.c **** UART_UartPutString(" mV"); + 350 .loc 1 175 0 + 351 0100 084B ldr r3, .L12+12 + 352 0102 1800 movs r0, r3 + 353 0104 FFF7FEFF bl UART_UartPutString + 176:main.c **** UART_UartPutCRLF(0u); + 354 .loc 1 176 0 + 355 0108 0020 movs r0, #0 + 356 010a FFF7FEFF bl UART_UartPutCRLF + 177:main.c **** } + 357 .loc 1 177 0 + 358 010e C046 nop + 359 0110 BD46 mov sp, r7 + 360 0112 02B0 add sp, sp, #8 + 361 @ sp needed + 362 0114 80BD pop {r7, pc} + 363 .L13: + 364 0116 C046 .align 2 + 365 .L12: + 366 0118 00000000 .word .LC4 + 367 011c 0C000000 .word .LC6 + 368 0120 10000000 .word .LC8 + 369 0124 14000000 .word .LC10 + 370 .cfi_endproc + 371 .LFE33: + 372 .size SendChannelVoltage, .-SendChannelVoltage + 373 .section .text.ADC_ISR_Handler,"ax",%progbits + 374 .align 2 + 375 .global ADC_ISR_Handler + 376 .code 16 + 377 .thumb_func + 378 .type ADC_ISR_Handler, %function + 379 ADC_ISR_Handler: + 380 .LFB34: + 178:main.c **** + 179:main.c **** + 180:main.c **** /****************************************************************************** + 181:main.c **** * Function Name: ADC_ISR_Handler + 182:main.c **** ******************************************************************************* + 183:main.c **** * + 184:main.c **** * Summary: + 185:main.c **** * Interrupt Service Routine. Check the ADC status and sets window and data + 186:main.c **** * ready flags. + 187:main.c **** * + 188:main.c **** ******************************************************************************/ + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 11 + + + 189:main.c **** CY_ISR(ADC_ISR_Handler) + 190:main.c **** { + 381 .loc 1 190 0 + 382 .cfi_startproc + 383 @ args = 0, pretend = 0, frame = 8 + 384 @ frame_needed = 1, uses_anonymous_args = 0 + 385 0000 80B5 push {r7, lr} + 386 .cfi_def_cfa_offset 8 + 387 .cfi_offset 7, -8 + 388 .cfi_offset 14, -4 + 389 0002 82B0 sub sp, sp, #8 + 390 .cfi_def_cfa_offset 16 + 391 0004 00AF add r7, sp, #0 + 392 .cfi_def_cfa_register 7 + 191:main.c **** uint32 intr_status; + 192:main.c **** + 193:main.c **** /* Read interrupt status registers */ + 194:main.c **** intr_status = ADC_SAR_INTR_MASKED_REG; + 393 .loc 1 194 0 + 394 0006 0C4B ldr r3, .L16 + 395 0008 1B68 ldr r3, [r3] + 396 000a 7B60 str r3, [r7, #4] + 195:main.c **** /* Check for End of Scan interrupt */ + 196:main.c **** if((intr_status & ADC_EOS_MASK) != 0u) + 397 .loc 1 196 0 + 398 000c 7B68 ldr r3, [r7, #4] + 399 000e 0122 movs r2, #1 + 400 0010 1340 ands r3, r2 + 401 0012 0AD0 beq .L15 + 197:main.c **** { + 198:main.c **** /* Read range interrupt status and raise the flag */ + 199:main.c **** windowFlag = ADC_SAR_RANGE_INTR_MASKED_REG; + 402 .loc 1 199 0 + 403 0014 094B ldr r3, .L16+4 + 404 0016 1A68 ldr r2, [r3] + 405 0018 094B ldr r3, .L16+8 + 406 001a 1A60 str r2, [r3] + 200:main.c **** /* Clear range detect status */ + 201:main.c **** ADC_SAR_RANGE_INTR_REG = windowFlag; + 407 .loc 1 201 0 + 408 001c 094A ldr r2, .L16+12 + 409 001e 084B ldr r3, .L16+8 + 410 0020 1B68 ldr r3, [r3] + 411 0022 1360 str r3, [r2] + 202:main.c **** dataReady = 1u; + 412 .loc 1 202 0 + 413 0024 084B ldr r3, .L16+16 + 414 0026 0122 movs r2, #1 + 415 0028 1A70 strb r2, [r3] + 416 .L15: + 203:main.c **** } + 204:main.c **** /* Clear handled interrupt */ + 205:main.c **** ADC_SAR_INTR_REG = intr_status; + 417 .loc 1 205 0 + 418 002a 084B ldr r3, .L16+20 + 419 002c 7A68 ldr r2, [r7, #4] + 420 002e 1A60 str r2, [r3] + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 12 + + + 206:main.c **** } + 421 .loc 1 206 0 + 422 0030 C046 nop + 423 0032 BD46 mov sp, r7 + 424 0034 02B0 add sp, sp, #8 + 425 @ sp needed + 426 0036 80BD pop {r7, pc} + 427 .L17: + 428 .align 2 + 429 .L16: + 430 0038 1C021A40 .word 1075446300 + 431 003c 3C021A40 .word 1075446332 + 432 0040 00000000 .word windowFlag + 433 0044 30021A40 .word 1075446320 + 434 0048 00000000 .word dataReady + 435 004c 10021A40 .word 1075446288 + 436 .cfi_endproc + 437 .LFE34: + 438 .size ADC_ISR_Handler, .-ADC_ISR_Handler + 439 .text + 440 .Letext0: + 441 .file 2 "Generated_Source\\PSoC4/cytypes.h" + 442 .section .debug_info,"",%progbits + 443 .Ldebug_info0: + 444 0000 B0010000 .4byte 0x1b0 + 445 0004 0400 .2byte 0x4 + 446 0006 00000000 .4byte .Ldebug_abbrev0 + 447 000a 04 .byte 0x4 + 448 000b 01 .uleb128 0x1 + 449 000c E8000000 .4byte .LASF28 + 450 0010 0C .byte 0xc + 451 0011 D9010000 .4byte .LASF29 + 452 0015 43000000 .4byte .LASF30 + 453 0019 00000000 .4byte .Ldebug_ranges0+0 + 454 001d 00000000 .4byte 0 + 455 0021 00000000 .4byte .Ldebug_line0 + 456 0025 02 .uleb128 0x2 + 457 0026 01 .byte 0x1 + 458 0027 06 .byte 0x6 + 459 0028 21020000 .4byte .LASF0 + 460 002c 02 .uleb128 0x2 + 461 002d 01 .byte 0x1 + 462 002e 08 .byte 0x8 + 463 002f B0000000 .4byte .LASF1 + 464 0033 02 .uleb128 0x2 + 465 0034 02 .byte 0x2 + 466 0035 05 .byte 0x5 + 467 0036 02020000 .4byte .LASF2 + 468 003a 02 .uleb128 0x2 + 469 003b 02 .byte 0x2 + 470 003c 07 .byte 0x7 + 471 003d 20000000 .4byte .LASF3 + 472 0041 02 .uleb128 0x2 + 473 0042 04 .byte 0x4 + 474 0043 05 .byte 0x5 + 475 0044 0C020000 .4byte .LASF4 + 476 0048 02 .uleb128 0x2 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 13 + + + 477 0049 04 .byte 0x4 + 478 004a 07 .byte 0x7 + 479 004b C4000000 .4byte .LASF5 + 480 004f 02 .uleb128 0x2 + 481 0050 08 .byte 0x8 + 482 0051 05 .byte 0x5 + 483 0052 CB010000 .4byte .LASF6 + 484 0056 02 .uleb128 0x2 + 485 0057 08 .byte 0x8 + 486 0058 07 .byte 0x7 + 487 0059 A4010000 .4byte .LASF7 + 488 005d 03 .uleb128 0x3 + 489 005e 04 .byte 0x4 + 490 005f 05 .byte 0x5 + 491 0060 696E7400 .ascii "int\000" + 492 0064 02 .uleb128 0x2 + 493 0065 04 .byte 0x4 + 494 0066 07 .byte 0x7 + 495 0067 97010000 .4byte .LASF8 + 496 006b 04 .uleb128 0x4 + 497 006c E2000000 .4byte .LASF9 + 498 0070 02 .byte 0x2 + 499 0071 E401 .2byte 0x1e4 + 500 0073 2C000000 .4byte 0x2c + 501 0077 04 .uleb128 0x4 + 502 0078 90010000 .4byte .LASF10 + 503 007c 02 .byte 0x2 + 504 007d E601 .2byte 0x1e6 + 505 007f 48000000 .4byte 0x48 + 506 0083 04 .uleb128 0x4 + 507 0084 BE000000 .4byte .LASF11 + 508 0088 02 .byte 0x2 + 509 0089 E801 .2byte 0x1e8 + 510 008b 33000000 .4byte 0x33 + 511 008f 02 .uleb128 0x2 + 512 0090 04 .byte 0x4 + 513 0091 04 .byte 0x4 + 514 0092 9E000000 .4byte .LASF12 + 515 0096 02 .uleb128 0x2 + 516 0097 08 .byte 0x8 + 517 0098 04 .byte 0x4 + 518 0099 84010000 .4byte .LASF13 + 519 009d 02 .uleb128 0x2 + 520 009e 01 .byte 0x1 + 521 009f 08 .byte 0x8 + 522 00a0 E0010000 .4byte .LASF14 + 523 00a4 05 .uleb128 0x5 + 524 00a5 6B000000 .4byte 0x6b + 525 00a9 04 .uleb128 0x4 + 526 00aa 00000000 .4byte .LASF15 + 527 00ae 02 .byte 0x2 + 528 00af 9002 .2byte 0x290 + 529 00b1 B5000000 .4byte 0xb5 + 530 00b5 05 .uleb128 0x5 + 531 00b6 77000000 .4byte 0x77 + 532 00ba 02 .uleb128 0x2 + 533 00bb 08 .byte 0x8 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 14 + + + 534 00bc 04 .byte 0x4 + 535 00bd 15020000 .4byte .LASF16 + 536 00c1 02 .uleb128 0x2 + 537 00c2 04 .byte 0x4 + 538 00c3 07 .byte 0x7 + 539 00c4 C2010000 .4byte .LASF17 + 540 00c8 06 .uleb128 0x6 + 541 00c9 8B010000 .4byte .LASF22 + 542 00cd 01 .byte 0x1 + 543 00ce 44 .byte 0x44 + 544 00cf 5D000000 .4byte 0x5d + 545 00d3 00000000 .4byte .LFB32 + 546 00d7 DC000000 .4byte .LFE32-.LFB32 + 547 00db 01 .uleb128 0x1 + 548 00dc 9C .byte 0x9c + 549 00dd 1A010000 .4byte 0x11a + 550 00e1 07 .uleb128 0x7 + 551 00e2 06000000 .4byte .LASF18 + 552 00e6 01 .byte 0x1 + 553 00e7 46 .byte 0x46 + 554 00e8 6B000000 .4byte 0x6b + 555 00ec 02 .uleb128 0x2 + 556 00ed 91 .byte 0x91 + 557 00ee 6D .sleb128 -19 + 558 00ef 07 .uleb128 0x7 + 559 00f0 19000000 .4byte .LASF19 + 560 00f4 01 .byte 0x1 + 561 00f5 47 .byte 0x47 + 562 00f6 1A010000 .4byte 0x11a + 563 00fa 02 .uleb128 0x2 + 564 00fb 91 .byte 0x91 + 565 00fc 60 .sleb128 -32 + 566 00fd 07 .uleb128 0x7 + 567 00fe BB010000 .4byte .LASF20 + 568 0102 01 .byte 0x1 + 569 0103 48 .byte 0x48 + 570 0104 83000000 .4byte 0x83 + 571 0108 02 .uleb128 0x2 + 572 0109 91 .byte 0x91 + 573 010a 6A .sleb128 -22 + 574 010b 07 .uleb128 0x7 + 575 010c 76010000 .4byte .LASF21 + 576 0110 01 .byte 0x1 + 577 0111 49 .byte 0x49 + 578 0112 83000000 .4byte 0x83 + 579 0116 02 .uleb128 0x2 + 580 0117 91 .byte 0x91 + 581 0118 6E .sleb128 -18 + 582 0119 00 .byte 0 + 583 011a 08 .uleb128 0x8 + 584 011b 83000000 .4byte 0x83 + 585 011f 2A010000 .4byte 0x12a + 586 0123 09 .uleb128 0x9 + 587 0124 C1000000 .4byte 0xc1 + 588 0128 03 .byte 0x3 + 589 0129 00 .byte 0 + 590 012a 0A .uleb128 0xa + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 15 + + + 591 012b E5010000 .4byte .LASF31 + 592 012f 01 .byte 0x1 + 593 0130 94 .byte 0x94 + 594 0131 00000000 .4byte .LFB33 + 595 0135 28010000 .4byte .LFE33-.LFB33 + 596 0139 01 .uleb128 0x1 + 597 013a 9C .byte 0x9c + 598 013b 5C010000 .4byte 0x15c + 599 013f 0B .uleb128 0xb + 600 0140 06000000 .4byte .LASF18 + 601 0144 01 .byte 0x1 + 602 0145 94 .byte 0x94 + 603 0146 6B000000 .4byte 0x6b + 604 014a 02 .uleb128 0x2 + 605 014b 91 .byte 0x91 + 606 014c 77 .sleb128 -9 + 607 014d 0B .uleb128 0xb + 608 014e BB010000 .4byte .LASF20 + 609 0152 01 .byte 0x1 + 610 0153 94 .byte 0x94 + 611 0154 83000000 .4byte 0x83 + 612 0158 02 .uleb128 0x2 + 613 0159 91 .byte 0x91 + 614 015a 74 .sleb128 -12 + 615 015b 00 .byte 0 + 616 015c 0C .uleb128 0xc + 617 015d 33000000 .4byte .LASF23 + 618 0161 01 .byte 0x1 + 619 0162 BD .byte 0xbd + 620 0163 00000000 .4byte .LFB34 + 621 0167 50000000 .4byte .LFE34-.LFB34 + 622 016b 01 .uleb128 0x1 + 623 016c 9C .byte 0x9c + 624 016d 80010000 .4byte 0x180 + 625 0171 07 .uleb128 0x7 + 626 0172 D6000000 .4byte .LASF24 + 627 0176 01 .byte 0x1 + 628 0177 BF .byte 0xbf + 629 0178 77000000 .4byte 0x77 + 630 017c 02 .uleb128 0x2 + 631 017d 91 .byte 0x91 + 632 017e 74 .sleb128 -12 + 633 017f 00 .byte 0 + 634 0180 0D .uleb128 0xd + 635 0181 0E000000 .4byte .LASF25 + 636 0185 01 .byte 0x1 + 637 0186 2B .byte 0x2b + 638 0187 B5000000 .4byte 0xb5 + 639 018b 05 .uleb128 0x5 + 640 018c 03 .byte 0x3 + 641 018d 00000000 .4byte windowFlag + 642 0191 0D .uleb128 0xd + 643 0192 F8010000 .4byte .LASF26 + 644 0196 01 .byte 0x1 + 645 0197 2C .byte 0x2c + 646 0198 A4000000 .4byte 0xa4 + 647 019c 05 .uleb128 0x5 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 16 + + + 648 019d 03 .byte 0x3 + 649 019e 00000000 .4byte dataReady + 650 01a2 0D .uleb128 0xd + 651 01a3 A4000000 .4byte .LASF27 + 652 01a7 01 .byte 0x1 + 653 01a8 2D .byte 0x2d + 654 01a9 A4000000 .4byte 0xa4 + 655 01ad 05 .uleb128 0x5 + 656 01ae 03 .byte 0x3 + 657 01af 00000000 .4byte channelFlag + 658 01b3 00 .byte 0 + 659 .section .debug_abbrev,"",%progbits + 660 .Ldebug_abbrev0: + 661 0000 01 .uleb128 0x1 + 662 0001 11 .uleb128 0x11 + 663 0002 01 .byte 0x1 + 664 0003 25 .uleb128 0x25 + 665 0004 0E .uleb128 0xe + 666 0005 13 .uleb128 0x13 + 667 0006 0B .uleb128 0xb + 668 0007 03 .uleb128 0x3 + 669 0008 0E .uleb128 0xe + 670 0009 1B .uleb128 0x1b + 671 000a 0E .uleb128 0xe + 672 000b 55 .uleb128 0x55 + 673 000c 17 .uleb128 0x17 + 674 000d 11 .uleb128 0x11 + 675 000e 01 .uleb128 0x1 + 676 000f 10 .uleb128 0x10 + 677 0010 17 .uleb128 0x17 + 678 0011 00 .byte 0 + 679 0012 00 .byte 0 + 680 0013 02 .uleb128 0x2 + 681 0014 24 .uleb128 0x24 + 682 0015 00 .byte 0 + 683 0016 0B .uleb128 0xb + 684 0017 0B .uleb128 0xb + 685 0018 3E .uleb128 0x3e + 686 0019 0B .uleb128 0xb + 687 001a 03 .uleb128 0x3 + 688 001b 0E .uleb128 0xe + 689 001c 00 .byte 0 + 690 001d 00 .byte 0 + 691 001e 03 .uleb128 0x3 + 692 001f 24 .uleb128 0x24 + 693 0020 00 .byte 0 + 694 0021 0B .uleb128 0xb + 695 0022 0B .uleb128 0xb + 696 0023 3E .uleb128 0x3e + 697 0024 0B .uleb128 0xb + 698 0025 03 .uleb128 0x3 + 699 0026 08 .uleb128 0x8 + 700 0027 00 .byte 0 + 701 0028 00 .byte 0 + 702 0029 04 .uleb128 0x4 + 703 002a 16 .uleb128 0x16 + 704 002b 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 17 + + + 705 002c 03 .uleb128 0x3 + 706 002d 0E .uleb128 0xe + 707 002e 3A .uleb128 0x3a + 708 002f 0B .uleb128 0xb + 709 0030 3B .uleb128 0x3b + 710 0031 05 .uleb128 0x5 + 711 0032 49 .uleb128 0x49 + 712 0033 13 .uleb128 0x13 + 713 0034 00 .byte 0 + 714 0035 00 .byte 0 + 715 0036 05 .uleb128 0x5 + 716 0037 35 .uleb128 0x35 + 717 0038 00 .byte 0 + 718 0039 49 .uleb128 0x49 + 719 003a 13 .uleb128 0x13 + 720 003b 00 .byte 0 + 721 003c 00 .byte 0 + 722 003d 06 .uleb128 0x6 + 723 003e 2E .uleb128 0x2e + 724 003f 01 .byte 0x1 + 725 0040 3F .uleb128 0x3f + 726 0041 19 .uleb128 0x19 + 727 0042 03 .uleb128 0x3 + 728 0043 0E .uleb128 0xe + 729 0044 3A .uleb128 0x3a + 730 0045 0B .uleb128 0xb + 731 0046 3B .uleb128 0x3b + 732 0047 0B .uleb128 0xb + 733 0048 49 .uleb128 0x49 + 734 0049 13 .uleb128 0x13 + 735 004a 11 .uleb128 0x11 + 736 004b 01 .uleb128 0x1 + 737 004c 12 .uleb128 0x12 + 738 004d 06 .uleb128 0x6 + 739 004e 40 .uleb128 0x40 + 740 004f 18 .uleb128 0x18 + 741 0050 9642 .uleb128 0x2116 + 742 0052 19 .uleb128 0x19 + 743 0053 01 .uleb128 0x1 + 744 0054 13 .uleb128 0x13 + 745 0055 00 .byte 0 + 746 0056 00 .byte 0 + 747 0057 07 .uleb128 0x7 + 748 0058 34 .uleb128 0x34 + 749 0059 00 .byte 0 + 750 005a 03 .uleb128 0x3 + 751 005b 0E .uleb128 0xe + 752 005c 3A .uleb128 0x3a + 753 005d 0B .uleb128 0xb + 754 005e 3B .uleb128 0x3b + 755 005f 0B .uleb128 0xb + 756 0060 49 .uleb128 0x49 + 757 0061 13 .uleb128 0x13 + 758 0062 02 .uleb128 0x2 + 759 0063 18 .uleb128 0x18 + 760 0064 00 .byte 0 + 761 0065 00 .byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 18 + + + 762 0066 08 .uleb128 0x8 + 763 0067 01 .uleb128 0x1 + 764 0068 01 .byte 0x1 + 765 0069 49 .uleb128 0x49 + 766 006a 13 .uleb128 0x13 + 767 006b 01 .uleb128 0x1 + 768 006c 13 .uleb128 0x13 + 769 006d 00 .byte 0 + 770 006e 00 .byte 0 + 771 006f 09 .uleb128 0x9 + 772 0070 21 .uleb128 0x21 + 773 0071 00 .byte 0 + 774 0072 49 .uleb128 0x49 + 775 0073 13 .uleb128 0x13 + 776 0074 2F .uleb128 0x2f + 777 0075 0B .uleb128 0xb + 778 0076 00 .byte 0 + 779 0077 00 .byte 0 + 780 0078 0A .uleb128 0xa + 781 0079 2E .uleb128 0x2e + 782 007a 01 .byte 0x1 + 783 007b 03 .uleb128 0x3 + 784 007c 0E .uleb128 0xe + 785 007d 3A .uleb128 0x3a + 786 007e 0B .uleb128 0xb + 787 007f 3B .uleb128 0x3b + 788 0080 0B .uleb128 0xb + 789 0081 27 .uleb128 0x27 + 790 0082 19 .uleb128 0x19 + 791 0083 11 .uleb128 0x11 + 792 0084 01 .uleb128 0x1 + 793 0085 12 .uleb128 0x12 + 794 0086 06 .uleb128 0x6 + 795 0087 40 .uleb128 0x40 + 796 0088 18 .uleb128 0x18 + 797 0089 9642 .uleb128 0x2116 + 798 008b 19 .uleb128 0x19 + 799 008c 01 .uleb128 0x1 + 800 008d 13 .uleb128 0x13 + 801 008e 00 .byte 0 + 802 008f 00 .byte 0 + 803 0090 0B .uleb128 0xb + 804 0091 05 .uleb128 0x5 + 805 0092 00 .byte 0 + 806 0093 03 .uleb128 0x3 + 807 0094 0E .uleb128 0xe + 808 0095 3A .uleb128 0x3a + 809 0096 0B .uleb128 0xb + 810 0097 3B .uleb128 0x3b + 811 0098 0B .uleb128 0xb + 812 0099 49 .uleb128 0x49 + 813 009a 13 .uleb128 0x13 + 814 009b 02 .uleb128 0x2 + 815 009c 18 .uleb128 0x18 + 816 009d 00 .byte 0 + 817 009e 00 .byte 0 + 818 009f 0C .uleb128 0xc + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 19 + + + 819 00a0 2E .uleb128 0x2e + 820 00a1 01 .byte 0x1 + 821 00a2 3F .uleb128 0x3f + 822 00a3 19 .uleb128 0x19 + 823 00a4 03 .uleb128 0x3 + 824 00a5 0E .uleb128 0xe + 825 00a6 3A .uleb128 0x3a + 826 00a7 0B .uleb128 0xb + 827 00a8 3B .uleb128 0x3b + 828 00a9 0B .uleb128 0xb + 829 00aa 27 .uleb128 0x27 + 830 00ab 19 .uleb128 0x19 + 831 00ac 11 .uleb128 0x11 + 832 00ad 01 .uleb128 0x1 + 833 00ae 12 .uleb128 0x12 + 834 00af 06 .uleb128 0x6 + 835 00b0 40 .uleb128 0x40 + 836 00b1 18 .uleb128 0x18 + 837 00b2 9742 .uleb128 0x2117 + 838 00b4 19 .uleb128 0x19 + 839 00b5 01 .uleb128 0x1 + 840 00b6 13 .uleb128 0x13 + 841 00b7 00 .byte 0 + 842 00b8 00 .byte 0 + 843 00b9 0D .uleb128 0xd + 844 00ba 34 .uleb128 0x34 + 845 00bb 00 .byte 0 + 846 00bc 03 .uleb128 0x3 + 847 00bd 0E .uleb128 0xe + 848 00be 3A .uleb128 0x3a + 849 00bf 0B .uleb128 0xb + 850 00c0 3B .uleb128 0x3b + 851 00c1 0B .uleb128 0xb + 852 00c2 49 .uleb128 0x49 + 853 00c3 13 .uleb128 0x13 + 854 00c4 3F .uleb128 0x3f + 855 00c5 19 .uleb128 0x19 + 856 00c6 02 .uleb128 0x2 + 857 00c7 18 .uleb128 0x18 + 858 00c8 00 .byte 0 + 859 00c9 00 .byte 0 + 860 00ca 00 .byte 0 + 861 .section .debug_aranges,"",%progbits + 862 0000 2C000000 .4byte 0x2c + 863 0004 0200 .2byte 0x2 + 864 0006 00000000 .4byte .Ldebug_info0 + 865 000a 04 .byte 0x4 + 866 000b 00 .byte 0 + 867 000c 0000 .2byte 0 + 868 000e 0000 .2byte 0 + 869 0010 00000000 .4byte .LFB32 + 870 0014 DC000000 .4byte .LFE32-.LFB32 + 871 0018 00000000 .4byte .LFB33 + 872 001c 28010000 .4byte .LFE33-.LFB33 + 873 0020 00000000 .4byte .LFB34 + 874 0024 50000000 .4byte .LFE34-.LFB34 + 875 0028 00000000 .4byte 0 + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 20 + + + 876 002c 00000000 .4byte 0 + 877 .section .debug_ranges,"",%progbits + 878 .Ldebug_ranges0: + 879 0000 00000000 .4byte .LFB32 + 880 0004 DC000000 .4byte .LFE32 + 881 0008 00000000 .4byte .LFB33 + 882 000c 28010000 .4byte .LFE33 + 883 0010 00000000 .4byte .LFB34 + 884 0014 50000000 .4byte .LFE34 + 885 0018 00000000 .4byte 0 + 886 001c 00000000 .4byte 0 + 887 .section .debug_line,"",%progbits + 888 .Ldebug_line0: + 889 0000 B2000000 .section .debug_str,"MS",%progbits,1 + 889 02004100 + 889 00000201 + 889 FB0E0D00 + 889 01010101 + 890 .LASF15: + 891 0000 72656733 .ascii "reg32\000" + 891 3200 + 892 .LASF18: + 893 0006 6368616E .ascii "channel\000" + 893 6E656C00 + 894 .LASF25: + 895 000e 77696E64 .ascii "windowFlag\000" + 895 6F77466C + 895 616700 + 896 .LASF19: + 897 0019 61646356 .ascii "adcVal\000" + 897 616C00 + 898 .LASF3: + 899 0020 73686F72 .ascii "short unsigned int\000" + 899 7420756E + 899 7369676E + 899 65642069 + 899 6E7400 + 900 .LASF23: + 901 0033 4144435F .ascii "ADC_ISR_Handler\000" + 901 4953525F + 901 48616E64 + 901 6C657200 + 902 .LASF30: + 903 0043 443A5C55 .ascii "D:\\Users\\jagumiel\\Documents\\PSoC Creator\\PSoC-" + 903 73657273 + 903 5C6A6167 + 903 756D6965 + 903 6C5C446F + 904 0071 3130315C .ascii "101\\PSoC-101\\TrainingProjects\\ADC-UART.cydsn\000" + 904 50536F43 + 904 2D313031 + 904 5C547261 + 904 696E696E + 905 .LASF12: + 906 009e 666C6F61 .ascii "float\000" + 906 7400 + 907 .LASF27: + ARM GAS C:\Users\jagumiel\AppData\Local\Temp\cc1cPPqc.s page 21 + + + 908 00a4 6368616E .ascii "channelFlag\000" + 908 6E656C46 + 908 6C616700 + 909 .LASF1: + 910 00b0 756E7369 .ascii "unsigned char\000" + 910 676E6564 + 910 20636861 + 910 7200 + 911 .LASF11: + 912 00be 696E7431 .ascii "int16\000" + 912 3600 + 913 .LASF5: + 914 00c4 6C6F6E67 .ascii "long unsigned int\000" + 914 20756E73 + 914 69676E65 + 914 6420696E + 914 7400 + 915 .LASF24: + 916 00d6 696E7472 .ascii "intr_status\000" + 916 5F737461 + 916 74757300 + 917 .LASF9: + 918 00e2 75696E74 .ascii "uint8\000" + 918 3800 + 919 .LASF28: + 920 00e8 474E5520 .ascii "GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br" + 920 43313120 + 920 352E342E + 920 31203230 + 920 31363036 + 921 011b 616E6368 .ascii "anch revision 237715] -mcpu=cortex-m0 -mthumb -g -O" + 921 20726576 + 921 6973696F + 921 6E203233 + 921 37373135 + 922 014e 30202D66 .ascii "0 -ffunction-sections -ffat-lto-objects\000" + 922 66756E63 + 922 74696F6E + 922 2D736563 + 922 74696F6E + 923 .LASF21: + 924 0176 70726576 .ascii "previousValue\000" + 924 696F7573 + 924 56616C75 + 924 6500 + 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Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ADC-UART.cyprj" -d CY8C4245AXI-483 -s "D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\Generated_Source\PSoC4" -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE +Elaborating Design... +HDL Generation... +Synthesis... +Tech Mapping... +Info: mpr.M0053: Information from the design wide resources Pin Editor has overridden the control file entry for "\UART:tx(0)\". (App=cydsfit) +ADD: pft.M0040: information: The following 1 pin(s) will be assigned a location by the fitter: Input_1(0) +Analog Placement... +Analog Routing... +Analog Code Generation... +Digital Placement... +Digital Routing... +Bitstream Generation... +Bitstream Verification... +Static timing analysis... +API Generation... +Dependency Generation... +Cleanup... +arm-none-eabi-gcc.exe -mcpu=cortex-m0 -mthumb -I. -IGenerated_Source\PSoC4 -Wa,-alh=.\ARM_GCC_541\Debug/main.lst -g -Wall -ffunction-sections -ffat-lto-objects -O0 -c main.c -o .\ARM_GCC_541\Debug\main.o +arm-none-eabi-gcc.exe -mcpu=cortex-m0 -mthumb -I. -IGenerated_Source\PSoC4 -Wa,-alh=.\ARM_GCC_541\Debug/ADC.lst -g -Wall -ffunction-sections -ffat-lto-objects -O0 -c Generated_Source\PSoC4\ADC.c -o .\ARM_GCC_541\Debug\ADC.o +arm-none-eabi-gcc.exe -mcpu=cortex-m0 -mthumb -I. -IGenerated_Source\PSoC4 -Wa,-alh=.\ARM_GCC_541\Debug/ADC_PM.lst -g -Wall -ffunction-sections -ffat-lto-objects -O0 -c Generated_Source\PSoC4\ADC_PM.c -o .\ARM_GCC_541\Debug\ADC_PM.o +arm-none-eabi-gcc.exe -mcpu=cortex-m0 -mthumb -I. -IGenerated_Source\PSoC4 -Wa,-alh=.\ARM_GCC_541\Debug/ADC_INT.lst -g -Wall -ffunction-sections -ffat-lto-objects -O0 -c Generated_Source\PSoC4\ADC_INT.c -o .\ARM_GCC_541\Debug\ADC_INT.o +arm-none-eabi-ar.exe -rs .\ARM_GCC_541\Debug\ADC-UART.a .\ARM_GCC_541\Debug\LED.o .\ARM_GCC_541\Debug\LED_PM.o .\ARM_GCC_541\Debug\UART.o .\ARM_GCC_541\Debug\UART_SPI_UART.o .\ARM_GCC_541\Debug\UART_SPI_UART_INT.o .\ARM_GCC_541\Debug\UART_PM.o .\ARM_GCC_541\Debug\UART_UART.o .\ARM_GCC_541\Debug\UART_BOOT.o .\ARM_GCC_541\Debug\UART_UART_BOOT.o .\ARM_GCC_541\Debug\Input_1.o .\ARM_GCC_541\Debug\Input_1_PM.o .\ARM_GCC_541\Debug\ADC.o .\ARM_GCC_541\Debug\ADC_PM.o .\ARM_GCC_541\Debug\ADC_INT.o .\ARM_GCC_541\Debug\UART_SCBCLK.o .\ARM_GCC_541\Debug\UART_tx.o .\ARM_GCC_541\Debug\UART_tx_PM.o .\ARM_GCC_541\Debug\ADC_IRQ.o .\ARM_GCC_541\Debug\ADC_intClock.o .\ARM_GCC_541\Debug\cy_em_eeprom.o .\ARM_GCC_541\Debug\CyFlash.o .\ARM_GCC_541\Debug\CyLib.o .\ARM_GCC_541\Debug\cyPm.o .\ARM_GCC_541\Debug\cyutils.o .\ARM_GCC_541\Debug\CyLFClk.o .\ARM_GCC_541\Debug\CyBootAsmGnu.o +arm-none-eabi-ar.exe: creating .\ARM_GCC_541\Debug\ADC-UART.a +arm-none-eabi-gcc.exe -Wl,--start-group -o "D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ARM_GCC_541\Debug\ADC-UART.elf" .\ARM_GCC_541\Debug\main.o .\ARM_GCC_541\Debug\cyfitter_cfg.o .\ARM_GCC_541\Debug\cymetadata.o .\ARM_GCC_541\Debug\Cm0Start.o .\ARM_GCC_541\Debug\ADC-UART.a -mcpu=cortex-m0 -mthumb -L Generated_Source\PSoC4 -Wl,-Map,.\ARM_GCC_541\Debug/ADC-UART.map -T Generated_Source\PSoC4\cm0gcc.ld -specs=nano.specs -Wl,--gc-sections -g -ffunction-sections -O0 -ffat-lto-objects -Wl,--end-group +cyelftool.exe -C "D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ARM_GCC_541\Debug\ADC-UART.elf" --flash_row_size 128 --flash_size 32768 --flash_offset 0x00000000 +No ELF section .cychecksum found, creating one +Application checksum calculated and stored in ELF section .cychecksum +Checksum calculated and stored in ELF section .cymeta +cyelftool.exe -S "D:\Users\jagumiel\Documents\PSoC Creator\PSoC-101\PSoC-101\TrainingProjects\ADC-UART.cydsn\ARM_GCC_541\Debug\ADC-UART.elf" +Flash used: 5016 of 32768 bytes (15,3 %). +SRAM used: 1652 of 4096 bytes (40,3 %). Stack: 1024 bytes. Heap: 256 bytes. +--------------- Build Succeeded: 07/17/2020 11:00:02 --------------- diff --git a/TrainingProjects/ADC-UART.cydsn/Export/PSoCCreatorExportIDE.xml b/TrainingProjects/ADC-UART.cydsn/Export/PSoCCreatorExportIDE.xml new file mode 100644 index 0000000..06db1ca --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Export/PSoCCreatorExportIDE.xml @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ADC-UART.svd + + + .\Generated_Source\PSoC4\cm0gcc.ld + .\Generated_Source\PSoC4\Cm0RealView.scat + .\Generated_Source\PSoC4\Cm0Iar.icf + + + + + main.c + device.h + cyapicallbacks.h + + + + + Generated_Source\PSoC4\cyfitter_cfg.h + Generated_Source\PSoC4\cyfitter_cfg.c + Generated_Source\PSoC4\cymetadata.c + Generated_Source\PSoC4\cydevice_trm.h + Generated_Source\PSoC4\cydevicegnu_trm.inc + Generated_Source\PSoC4\cydevicerv_trm.inc + Generated_Source\PSoC4\cydeviceiar_trm.inc + Generated_Source\PSoC4\cyfittergnu.inc + Generated_Source\PSoC4\cyfitterrv.inc + Generated_Source\PSoC4\cyfitteriar.inc + Generated_Source\PSoC4\cyfitter.h + Generated_Source\PSoC4\cydisabledsheets.h + Generated_Source\PSoC4\LED.c + Generated_Source\PSoC4\LED.h + Generated_Source\PSoC4\LED_aliases.h + Generated_Source\PSoC4\LED_PM.c + Generated_Source\PSoC4\UART.c + Generated_Source\PSoC4\UART.h + Generated_Source\PSoC4\UART_SPI_UART.h + Generated_Source\PSoC4\UART_SPI_UART.c + Generated_Source\PSoC4\UART_SPI_UART_INT.c + Generated_Source\PSoC4\UART_PM.c + Generated_Source\PSoC4\UART_UART.c + Generated_Source\PSoC4\UART_BOOT.c + Generated_Source\PSoC4\UART_UART_BOOT.c + Generated_Source\PSoC4\UART_PINS.h + Generated_Source\PSoC4\UART_SPI_UART_PVT.h + Generated_Source\PSoC4\UART_PVT.h + Generated_Source\PSoC4\UART_BOOT.h + Generated_Source\PSoC4\Input_1.c + Generated_Source\PSoC4\Input_1.h + Generated_Source\PSoC4\Input_1_aliases.h + Generated_Source\PSoC4\Input_1_PM.c + Generated_Source\PSoC4\ADC.c + Generated_Source\PSoC4\ADC.h + Generated_Source\PSoC4\ADC_PM.c + Generated_Source\PSoC4\ADC_INT.c + Generated_Source\PSoC4\UART_SCBCLK.c + Generated_Source\PSoC4\UART_SCBCLK.h + Generated_Source\PSoC4\UART_tx.c + Generated_Source\PSoC4\UART_tx.h + Generated_Source\PSoC4\UART_tx_aliases.h + Generated_Source\PSoC4\UART_tx_PM.c + Generated_Source\PSoC4\ADC_IRQ.c + Generated_Source\PSoC4\ADC_IRQ.h + Generated_Source\PSoC4\ADC_intClock.c + Generated_Source\PSoC4\ADC_intClock.h + Generated_Source\PSoC4\cy_em_eeprom.c + Generated_Source\PSoC4\cy_em_eeprom.h + Generated_Source\PSoC4\cm0gcc.ld + Generated_Source\PSoC4\Cm0RealView.scat + Generated_Source\PSoC4\Cm0Start.c + Generated_Source\PSoC4\core_cm0.h + Generated_Source\PSoC4\core_cm0_psoc4.h + Generated_Source\PSoC4\CyBootAsmRv.s + Generated_Source\PSoC4\CyFlash.c + Generated_Source\PSoC4\CyFlash.h + Generated_Source\PSoC4\CyLib.c + Generated_Source\PSoC4\CyLib.h + Generated_Source\PSoC4\cyPm.c + Generated_Source\PSoC4\cyPm.h + Generated_Source\PSoC4\cytypes.h + Generated_Source\PSoC4\cyutils.c + Generated_Source\PSoC4\cypins.h + Generated_Source\PSoC4\core_cmFunc.h + Generated_Source\PSoC4\core_cmInstr.h + Generated_Source\PSoC4\Cm0Iar.icf + Generated_Source\PSoC4\CyBootAsmIar.s + Generated_Source\PSoC4\cmsis_armcc.h + Generated_Source\PSoC4\cmsis_gcc.h + Generated_Source\PSoC4\cmsis_compiler.h + Generated_Source\PSoC4\CyBootAsmGnu.s + Generated_Source\PSoC4\CyLFClk.c + Generated_Source\PSoC4\CyLFClk.h + Generated_Source\PSoC4\project.h + Generated_Source\PSoC4\cycodeshareimport.ld + Generated_Source\PSoC4\cycodeshareexport.ld + Generated_Source\PSoC4\cycodeshareimport.scat + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/TrainingProjects/ADC-UART.cydsn/GENERATE_API.log b/TrainingProjects/ADC-UART.cydsn/GENERATE_API.log new file mode 100644 index 0000000..fcb7bdd --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/GENERATE_API.log @@ -0,0 +1,21 @@ +--------------- Build Started: 07/17/2020 09:21:46 Project: PSoC4_ADC_with_Differential_PreAmplifier, Configuration: ARM GCC 5.4-2016-q2-update Debug --------------- +cydsfit.exe -.appdatapath "C:\Users\jagumiel\AppData\Local\Cypress Semiconductor\PSoC Creator\4.2" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p "D:\Users\jagumiel\Desktop\PSoC4-MCU-Analog-Designs-master\ADC\CE95272 - PSoC4 SAR ADC and Differential Amplifier\PSoC4_ADC_with_Differential_PreAmplifier.cydsn\PSoC4_ADC_with_Differential_PreAmplifier.cyprj" -d CY8C4245AXI-483 -s "D:\Users\jagumiel\Desktop\PSoC4-MCU-Analog-Designs-master\ADC\CE95272 - PSoC4 SAR ADC and Differential Amplifier\PSoC4_ADC_with_Differential_PreAmplifier.cydsn\Generated_Source\PSoC4" -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE +Elaborating Design... +ADD: sdb.M0061: information: Info from component: ADC. The actual sample rate (292 SPS) differs from the desired sample rate (300 SPS) due to the clock configuration in the DWR. + * D:\Users\jagumiel\Desktop\PSoC4-MCU-Analog-Designs-master\ADC\CE95272 - PSoC4 SAR ADC and Differential Amplifier\PSoC4_ADC_with_Differential_PreAmplifier.cydsn\TopDesign\TopDesign.cysch (Instance:ADC) +HDL Generation... +Synthesis... +Tech Mapping... +ADD: pft.M0040: information: The following 1 pin(s) will be assigned a location by the fitter: Input_1(0) +Analog Placement... +Analog Routing... +Analog Code Generation... +Digital Placement... +Digital Routing... +Bitstream Generation... +Bitstream Verification... +Static timing analysis... +API Generation... +Dependency Generation... +Cleanup... +--------------- Build Succeeded: 07/17/2020 09:22:02 --------------- diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.c new file mode 100644 index 0000000..f313f71 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.c @@ -0,0 +1,881 @@ +/******************************************************************************* +* File Name: ADC.c +* Version 2.50 +* +* Description: +* This file provides the source code to the API for the Sequencing Successive +* Approximation ADC Component Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC.h" + + +/*************************************** +* Global data allocation +***************************************/ +uint8 ADC_initVar = 0u; +volatile int16 ADC_offset[ADC_TOTAL_CHANNELS_NUM]; +volatile int32 ADC_countsPer10Volt[ADC_TOTAL_CHANNELS_NUM]; /* Gain compensation */ + + +/*************************************** +* Local data allocation +***************************************/ +/* Channels configuration generated by customiser */ +static const uint32 CYCODE ADC_channelsConfig[] = { 0x00000402u }; + + +/******************************************************************************* +* Function Name: ADC_Start +******************************************************************************** +* +* Summary: +* Performs all required initialization for this component +* and enables the power. The power will be set to the appropriate +* power based on the clock frequency. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* The ADC_initVar variable is used to indicate when/if initial +* configuration of this component has happened. The variable is initialized to +* zero and set to 1 the first time ADC_Start() is called. This allows for +* component Re-Start without re-initialization in all subsequent calls to the +* ADC_Start() routine. +* If re-initialization of the component is required the variable should be set +* to zero before call of ADC_Start() routine, or the user may call +* ADC_Init() and ADC_Enable() as done in the +* ADC_Start() routine. +* +*******************************************************************************/ +void ADC_Start(void) +{ + /* If not Initialized then initialize all required hardware and software */ + if(ADC_initVar == 0u) + { + ADC_Init(); + ADC_initVar = 1u; + } + ADC_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_Init +******************************************************************************** +* +* Summary: +* Initialize component's parameters to the parameters set by user in the +* customizer of the component placed onto schematic. Usually called in +* ADC_Start(). +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* The ADC_offset variable is initialized. +* +*******************************************************************************/ +void ADC_Init(void) +{ + uint32 chNum; + uint32 tmpRegVal; + int32 counts; + + #if(ADC_TOTAL_CHANNELS_NUM > 1u) + static const uint8 CYCODE ADC_InputsPlacement[] = + { + (uint8)(ADC_cy_psoc4_sarmux_8__CH_0_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_0_PIN + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_1_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_1_PIN + #if(ADC_TOTAL_CHANNELS_NUM > 2u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_2_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_2_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 2u */ + #if(ADC_TOTAL_CHANNELS_NUM > 3u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_3_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_3_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 3u */ + #if(ADC_TOTAL_CHANNELS_NUM > 4u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_4_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_4_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 4u */ + #if(ADC_TOTAL_CHANNELS_NUM > 5u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_5_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_5_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 5u */ + #if(ADC_TOTAL_CHANNELS_NUM > 6u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_6_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_6_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 6u */ + #if(ADC_TOTAL_CHANNELS_NUM > 7u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_7_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_7_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 7u */ + #if(ADC_TOTAL_CHANNELS_NUM > 8u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_8_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_8_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 8u */ + #if(ADC_TOTAL_CHANNELS_NUM > 9u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_9_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_9_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 9u */ + #if(ADC_TOTAL_CHANNELS_NUM > 10u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_10_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_10_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 10u */ + #if(ADC_TOTAL_CHANNELS_NUM > 11u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_11_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_11_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 11u */ + #if(ADC_TOTAL_CHANNELS_NUM > 12u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_12_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_12_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 12u */ + #if(ADC_TOTAL_CHANNELS_NUM > 13u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_13_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_13_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 13u */ + #if(ADC_TOTAL_CHANNELS_NUM > 14u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_14_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_14_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 14u */ + #if(ADC_TOTAL_CHANNELS_NUM > 15u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_15_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_15_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 15u */ + #if(ADC_TOTAL_CHANNELS_NUM > 16u) + ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_16_PORT << 4u) | + (uint8)ADC_cy_psoc4_sarmux_8__CH_16_PIN + #endif /* End ADC_TOTAL_CHANNELS_NUM > 16u */ + }; + #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */ + + #if(ADC_IRQ_REMOVE == 0u) + /* Start and set interrupt vector */ + CyIntSetPriority(ADC_INTC_NUMBER, ADC_INTC_PRIOR_NUMBER); + (void)CyIntSetVector(ADC_INTC_NUMBER, &ADC_ISR); + #endif /* End ADC_IRQ_REMOVE */ + + /* Init SAR and MUX registers */ + ADC_SAR_CHAN_EN_REG = ADC_DEFAULT_EN_CHANNELS; + ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | + /* Enable the SAR internal pump when global pump is enabled */ + (((ADC_PUMP_CTRL_REG & ADC_PUMP_CTRL_ENABLED) != 0u) ? + ADC_BOOSTPUMP_EN : 0u); + ADC_SAR_SAMPLE_CTRL_REG = ADC_DEFAULT_SAMPLE_CTRL_REG_CFG; + ADC_SAR_RANGE_THRES_REG = ADC_DEFAULT_RANGE_THRES_REG_CFG; + ADC_SAR_RANGE_COND_REG = ADC_COMPARE_MODE; + ADC_SAR_SAMPLE_TIME01_REG = ADC_DEFAULT_SAMPLE_TIME01_REG_CFG; + ADC_SAR_SAMPLE_TIME23_REG = ADC_DEFAULT_SAMPLE_TIME23_REG_CFG; + + /* Connect Vm to VSSA when even one channel is single-ended or multiple channels configured */ + #if(ADC_DEFAULT_MUX_SWITCH0 != 0u) + ADC_MUX_SWITCH0_REG |= ADC_DEFAULT_MUX_SWITCH0; + /* Set MUX_HW_CTRL_VSSA in MUX_SWITCH_HW_CTRL when multiple channels enabled */ + #if(ADC_TOTAL_CHANNELS_NUM > 1u) + ADC_MUX_SWITCH_HW_CTRL_REG |= ADC_DEFAULT_MUX_SWITCH0; + #endif /* ADC_TOTAL_CHANNELS_NUM > 1u */ + #endif /*ADC_CHANNELS_MODE !=0 */ + + ADC_SAR_SATURATE_INTR_MASK_REG = 0u; + ADC_SAR_RANGE_INTR_MASK_REG = 0u; + ADC_SAR_INTR_MASK_REG = ADC_SAR_INTR_MASK; + + #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) + ADC_ANA_TRIM_REG = ADC_TRIM_COEF; + #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */ + + /* Read and modify default configuration based on characterization */ + tmpRegVal = ADC_SAR_DFT_CTRL_REG; + tmpRegVal &= (uint32)~ADC_DCEN; + + #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) + #if(ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 2)) + tmpRegVal |= ADC_SEL_CSEL_DFT_CHAR; + #else /* clock speed < 9 Mhz */ + tmpRegVal |= ADC_DLY_INC; + #endif /* clock speed > 9 Mhz */ + #else + #if ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \ + (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)) + tmpRegVal |= ADC_DLY_INC; + #else + tmpRegVal |= ADC_DCEN; + tmpRegVal &= (uint32)~ADC_DLY_INC; + #endif /* ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \ + (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)) */ + #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */ + + ADC_SAR_DFT_CTRL_REG = tmpRegVal; + + #if(ADC_MAX_RESOLUTION != ADC_RESOLUTION_12) + ADC_WOUNDING_REG = ADC_ALT_WOUNDING; + #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */ + + for(chNum = 0u; chNum < ADC_TOTAL_CHANNELS_NUM; chNum++) + { + tmpRegVal = (ADC_channelsConfig[chNum] & ADC_CHANNEL_CONFIG_MASK); + #if(ADC_TOTAL_CHANNELS_NUM > 1u) + tmpRegVal |= ADC_InputsPlacement[chNum]; + #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */ + + + /* When the part is limited to 10-bit then the SUB_RESOLUTION bit + * will be ignored and the RESOLUTION bit selects between 10-bit + * (0) and 8-bit (1) resolution. + */ + #if((ADC_MAX_RESOLUTION != ADC_RESOLUTION_12) && \ + (ADC_ALT_WOUNDING == ADC_WOUNDING_10BIT)) + tmpRegVal &= (uint32)(~ADC_ALT_RESOLUTION_ON); + #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */ + + #if(ADC_INJ_CHANNEL_ENABLED) + if(chNum < ADC_SEQUENCED_CHANNELS_NUM) + #endif /* ADC_INJ_CHANNEL_ENABLED */ + { + CY_SET_REG32((reg32 *)(ADC_SAR_CHAN_CONFIG_IND + (uint32)(chNum << 2)), tmpRegVal); + + if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u) + { + ADC_SAR_SATURATE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + } + + if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u) + { + ADC_SAR_RANGE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + } + } + #if(ADC_INJ_CHANNEL_ENABLED) + else + { + CY_SET_REG32(ADC_SAR_INJ_CHAN_CONFIG_PTR, tmpRegVal | ADC_INJ_TAILGATING); + + if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u) + { + ADC_SAR_INTR_MASK_REG |= ADC_INJ_SATURATE_MASK; + } + + if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u) + { + ADC_SAR_INTR_MASK_REG |= ADC_INJ_RANGE_MASK; + } + } + #endif /* ADC_INJ_CHANNEL_ENABLED */ + + if((ADC_channelsConfig[chNum] & ADC_ALT_RESOLUTION_ON) != 0u) + { + counts = (int32)ADC_DEFAULT_MAX_WRK_ALT; + } + else + { + counts = (int32)ADC_SAR_WRK_MAX_12BIT; + } + + if((ADC_channelsConfig[chNum] & ADC_DIFFERENTIAL_EN) == 0u) + { + #if((ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED) && \ + (ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF)) + /* Set offset to the minus half scale to convert results to unsigned format */ + ADC_offset[chNum] = (int16)(counts / -2); + #else + ADC_offset[chNum] = 0; + #endif /* end DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED */ + } + else /* Differential channel */ + { + #if(ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED) + /* Set offset to the half scale to convert results to signed format */ + ADC_offset[chNum] = (int16)(counts / 2); + #else + ADC_offset[chNum] = 0; + #endif /* end ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED */ + } + /* Calculate gain in counts per 10 volts with rounding */ + ADC_countsPer10Volt[chNum] = (int16)(((counts * ADC_10MV_COUNTS) + + ADC_DEFAULT_VREF_MV_VALUE) / (ADC_DEFAULT_VREF_MV_VALUE * 2)); + } +} + +/******************************************************************************* +* Function Name: ADC_SAR_1_Enable +******************************************************************************** +* +* Summary: +* Enables the clock and analog power for SAR ADC. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_Enable(void) +{ + if (0u == (ADC_SAR_CTRL_REG & ADC_ENABLE)) + { + #if(ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) + + while (0u != (ADC_SAR_STATUS_REG & ADC_STATUS_BUSY)) + { + /* wait for SAR to go idle to avoid deadlock */ + } + #endif /* (ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) */ + + ADC_SAR_CTRL_REG |= ADC_ENABLE; + + /* The block is ready to use 10 us after the enable signal is set high. */ + CyDelayUs(ADC_10US_DELAY); + } +} + + +/******************************************************************************* +* Function Name: ADC_Stop +******************************************************************************** +* +* Summary: +* This function stops ADC conversions and puts the ADC into its lowest power +* mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_Stop(void) +{ + ADC_SAR_CTRL_REG &= (uint32)~ADC_ENABLE; +} + + +/******************************************************************************* +* Function Name: ADC_StartConvert +******************************************************************************** +* +* Summary: +* Description: +* For free running mode, this API starts the conversion process and it +* runs continuously. +* +* In a triggered mode, this routine triggers every conversion by +* writing into the FW_TRIGGER bit in SAR_START_CTRL reg. In triggered mode, +* every conversion has to start by this API. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_StartConvert(void) +{ + #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + ADC_SAR_SAMPLE_CTRL_REG |= ADC_CONTINUOUS_EN; + #else /* Firmware trigger */ + ADC_SAR_START_CTRL_REG = ADC_FW_TRIGGER; + #endif /* End ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ + +} + + +/******************************************************************************* +* Function Name: ADC_StopConvert +******************************************************************************** +* +* Summary: +* Forces the ADC to stop all conversions. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_StopConvert(void) +{ + #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + ADC_SAR_SAMPLE_CTRL_REG &= (uint32)(~ADC_CONTINUOUS_EN); + #endif /* ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ +} + + +/******************************************************************************* +* Function Name: ADC_IsEndConversion +******************************************************************************** +* +* Summary: +* Description: Checks for ADC end of conversion for the case one +* channel and end of scan for the case of multiple channels. It acts +* as a software version of the EOC. This function provides the +* programmer with two options. In one mode this function +* immediately returns with the conversion status. In the other mode, +* the function does not return (blocking) until the conversion has +* completed. +* +* Parameters: +* ADC_RETURN_STATUS -> Immediately returns conversion result status +* ADC_WAIT_FOR_RESULT -> Does not return until ADC complete +* ADC_RETURN_STATUS_INJ -> Immediately returns conversion result status +* for injection channel +* ADC_WAIT_FOR_RESULT_INJ -> Does not return until ADC completes injection +* channel conversion +* +* Return: +* If a non-zero value is returned, the last conversion or scan has completed. +* If the returned value is zero, the ADC is still in the process of a scan. +* +*******************************************************************************/ +uint32 ADC_IsEndConversion(uint32 retMode) +{ + uint32 status = 0u; + + if((retMode & (ADC_RETURN_STATUS | ADC_WAIT_FOR_RESULT)) != 0u) + { + do + { + status = ADC_SAR_INTR_REG & ADC_EOS_MASK; + }while((status == 0u) && ((retMode & ADC_WAIT_FOR_RESULT) != 0u)); + + if(status != 0u) + { + /* Clear EOS bit */ + ADC_SAR_INTR_REG = ADC_EOS_MASK; + } + } + + #if(ADC_INJ_CHANNEL_ENABLED) + if((retMode & (ADC_RETURN_STATUS_INJ | ADC_WAIT_FOR_RESULT_INJ)) != 0u) + { + do + { + status |= ADC_SAR_INTR_REG & ADC_INJ_EOC_MASK; + }while(((status & ADC_INJ_EOC_MASK) == 0u) && + ((retMode & ADC_WAIT_FOR_RESULT_INJ) != 0u)); + + if((status & ADC_INJ_EOC_MASK) != 0u) + { + /* Clear Injection EOS bit */ + ADC_SAR_INTR_REG = ADC_INJ_EOC_MASK; + } + } + #endif /* ADC_INJ_CHANNEL_ENABLED */ + + return (status); +} + + +/******************************************************************************* +* Function Name: ADC_GetResult16 +******************************************************************************** +* +* Summary: +* Gets the data available in the SAR DATA register. +* +* Parameters: +* chan: The ADC channel in which to return the result. The first channel +* is 0 and the injection channel if enabled is the number of valid channels. +* +* Return: +* Returns converted data as a signed 16-bit integer +* +*******************************************************************************/ +int16 ADC_GetResult16(uint32 chan) +{ + uint32 result; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + if(chan < ADC_SEQUENCED_CHANNELS_NUM) + { + result = CY_GET_REG32((reg32 *)(ADC_SAR_CHAN_RESULT_IND + (uint32)(chan << 2u))) & + ADC_RESULT_MASK; + } + else + { + #if(ADC_INJ_CHANNEL_ENABLED) + result = ADC_SAR_INJ_RESULT_REG & ADC_RESULT_MASK; + #else + result = 0u; + #endif /* ADC_INJ_CHANNEL_ENABLED */ + } + + return ( (int16)result ); +} + + +/******************************************************************************* +* Function Name: ADC_SetChanMask +******************************************************************************** +* +* Summary: +* Sets the channel enable mask. +* +* Parameters: +* mask: Sets which channels that will be +* scanned. Setting bits for channels that do not exist will have no +* effect. For example, if only 6 channels were enabled, setting a +* mask of 0x0103 would only enable the last two channels (0 and 1). +* This API will not enable the injection channel. +* Examples: If the component is setup to sequence through 8 +* channels, a mask of 0x000F would enable channels 0, 1, 2, and 3. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetChanMask(uint32 mask) +{ + ADC_SAR_CHAN_EN_REG = mask & ADC_MAX_CHANNELS_EN_MASK; +} + +#if(ADC_INJ_CHANNEL_ENABLED) + + + /******************************************************************************* + * Function Name: ADC_EnableInjection + ******************************************************************************** + * + * Summary: + * Enables the injection channel for the next scan only. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void ADC_EnableInjection(void) + { + ADC_SAR_INJ_CHAN_CONFIG_REG |= ADC_INJ_CHAN_EN; + } + +#endif /* ADC_INJ_CHANNEL_ENABLED */ + + +/******************************************************************************* +* Function Name: ADC_SetLowLimit +******************************************************************************** +* +* Summary: +* Sets the low limit parameter for a limit condition. +* +* Parameters: +* lowLimit: The low limit for a limit condition. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetLowLimit(uint32 lowLimit) +{ + ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_LOW_MASK); + ADC_SAR_RANGE_THRES_REG |= lowLimit & ADC_RANGE_LOW_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SetHighLimit +******************************************************************************** +* +* Summary: +* Sets the low limit parameter for a limit condition. +* +* Parameters: +* highLimit: The high limit for a limit condition. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetHighLimit(uint32 highLimit) +{ + ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_HIGH_MASK); + ADC_SAR_RANGE_THRES_REG |= (uint32)(highLimit << ADC_RANGE_HIGH_OFFSET); +} + + +/******************************************************************************* +* Function Name: ADC_SetLimitMask +******************************************************************************** +* +* Summary: +* Sets the channel limit condition mask. +* +* Parameters: +* mask: Sets which channels that may cause a +* limit condition interrupt. Setting bits for channels that do not exist +* will have no effect. For example, if only 6 channels were enabled, +* setting a mask of 0x0103 would only enable the last two channels (0 and 1). +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetLimitMask(uint32 mask) +{ + ADC_SAR_RANGE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SetSatMask +******************************************************************************** +* +* Summary: +* Sets the channel saturation event mask. +* +* Parameters: +* mask: Sets which channels that may cause a +* saturation event interrupt. Setting bits for channels that do not exist +* will have no effect. For example, if only 8 channels were enabled, +* setting a mask of 0x01C0 would only enable two channels (6 and 7). +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SetSatMask(uint32 mask) +{ + ADC_SAR_SATURATE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SetOffset +******************************************************************************** +* +* Summary: +* Description: Sets the ADC offset which is used by the functions +* ADC_CountsTo_uVolts, ADC_CountsTo_mVolts and ADC_CountsTo_Volts +* to substract the offset from the given reading +* before calculating the voltage conversion. +* +* Parameters: +* chan: ADC channel number. +* offset: This value is a measured value when the +* inputs are shorted or connected to the same input voltage. +* +* Return: +* None. +* +* Global variables: +* ADC_Offset: Modified to set the user provided offset. +* +*******************************************************************************/ +void ADC_SetOffset(uint32 chan, int16 offset) +{ + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + ADC_offset[chan] = offset; +} + + +/******************************************************************************* +* Function Name: ADC_SetGain +******************************************************************************** +* +* Summary: +* Description: Sets the ADC gain in counts per 10 volt for the voltage +* conversion functions below. This value is set by default by the +* reference and input range settings. It should only be used to further +* calibrate the ADC with a known input or if an external reference is +* used. Affects the ADC_CountsTo_uVolts, ADC_CountsTo_mVolts +* and ADC_CountsTo_Volts functions by supplying the correct +* conversion between ADC counts and voltage. +* +* Parameters: +* chan: ADC channel number. +* adcGain: ADC gain in counts per 10 volts. +* +* Return: +* None. +* +* Global variables: +* ADC_CountsPer10Volt: modified to set the ADC gain in counts +* per 10 volt. +* +*******************************************************************************/ +void ADC_SetGain(uint32 chan, int32 adcGain) +{ + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + ADC_countsPer10Volt[chan] = adcGain; +} + + +#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT) + + + /******************************************************************************* + * Function Name: ADC_CountsTo_mVolts + ******************************************************************************** + * + * Summary: + * This function converts ADC counts to mVolts + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * adcCounts: Result from the ADC conversion + * + * Return: + * Results in mVolts + * + * Global variables: + * ADC_countsPer10Volt: used to convert ADC counts to mVolts. + * ADC_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + *******************************************************************************/ + int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts) + { + int16 mVolts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_offset[chan]; + + mVolts = (int16)((((int32)adcCounts * ADC_10MV_COUNTS) + ( (adcCounts > 0) ? + (ADC_countsPer10Volt[chan] / 2) : (-(ADC_countsPer10Volt[chan] / 2)) )) + / ADC_countsPer10Volt[chan]); + + return( mVolts ); + } + + + /******************************************************************************* + * Function Name: ADC_CountsTo_uVolts + ******************************************************************************** + * + * Summary: + * This function converts ADC counts to micro Volts + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * adcCounts: Result from the ADC conversion + * + * Return: + * Results in uVolts + * + * Global variables: + * ADC_countsPer10Volt: used to convert ADC counts to uVolts. + * ADC_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + * Theory: + * Care must be taken to not exceed the maximum value for a 31 bit signed + * number in the conversion to uVolts and at the same time not loose + * resolution. + * To convert adcCounts to microVolts it is required to be multiplied + * on 10 million and later divide on gain in counts per 10V. + * + *******************************************************************************/ + int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts) + { + int64 uVolts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_offset[chan]; + + uVolts = ((int64)adcCounts * ADC_10UV_COUNTS) / ADC_countsPer10Volt[chan]; + + return( (int32)uVolts ); + } + + + /******************************************************************************* + * Function Name: ADC_CountsTo_Volts + ******************************************************************************** + * + * Summary: + * Converts the ADC output to Volts as a floating point number. + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * Result from the ADC conversion + * + * Return: + * Results in Volts + * + * Global variables: + * ADC_countsPer10Volt: used to convert ADC counts to Volts. + * ADC_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + *******************************************************************************/ + float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts) + { + float32 volts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE) + if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_offset[chan]; + + volts = ((float32)adcCounts * ADC_10V_COUNTS) / (float32)ADC_countsPer10Volt[chan]; + + return( volts ); + } + +#endif /* End ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.h new file mode 100644 index 0000000..78a0469 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC.h @@ -0,0 +1,713 @@ +/******************************************************************************* +* File Name: ADC.h +* Version 2.50 +* +* Description: +* This file contains the function prototypes and constants used in +* the Sequencing Successive Approximation ADC Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_ADC_SAR_SEQ_ADC_H) +#define CY_ADC_SAR_SEQ_ADC_H + +#include "cytypes.h" +#include "CyLib.h" + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint32 dftRegVal; +} ADC_BACKUP_STRUCT; + + +/************************************** +* Enumerated Types and Parameters +**************************************/ + +/* Clock Source setting constants */ +#define ADC__EXTERNAL 0 +#define ADC__INTERNAL 1 + +/* Sample Mode setting constants */ +#define ADC__FREERUNNING 0 +#define ADC__HARDWARESOC 1 + +/* Reference type setting constants */ +#define ADC__VDDA_2 0 +#define ADC__VDDA 1 +#define ADC__INTERNAL1024 2 +#define ADC__INTERNAL1024BYPASSED 3 +#define ADC__INTERNALVREF 4 +#define ADC__INTERNALVREFBYPASSED 5 +#define ADC__VDDA_2BYPASSED 6 +#define ADC__EXTERNALVREF 7 + +/* Input buffer gain setting constants */ +#define ADC__DISABLED 0 +#define ADC__ONE 1 +#define ADC__TWO 2 +#define ADC__FOUR 3 +#define ADC__EIGHT 4 +#define ADC__SIXTEEN 5 + +/* Negative input setting sonstants in single ended mode */ +#define ADC__VSS 0 +#define ADC__VREF 1 +#define ADC__OTHER 2 + +/* Compare mode setting constants: +* Mode0 - Disable +* Mode1 - Result < Low_Limit +* Mode2 - Low_Limit <= Result < High_Limit +* Mode3 - High_Limit <= Result +* Mode4 - (Result < Low_Limit) or (High_Limit <= Result) +*/ +#define ADC__MODE0 0 +#define ADC__MODE1 1 +#define ADC__MODE2 2 +#define ADC__MODE3 3 + +#define ADC__RES8 0 +#define ADC__RES10 1 + +#define ADC__RIGHT 0 +#define ADC__LEFT 1 + +#define ADC__FSIGNED 1 +#define ADC__FUNSIGNED 0 + +#define ADC__ACCUMULATE 0 +#define ADC__FIXEDRESOLUTION 1 + + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#define ADC_CY_SAR_IP_VER0 (0u) +#define ADC_CY_SAR_IP_VER1 (1u) + +#if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define ADC_CY_SAR_IP_VER (ADC_CY_SAR_IP_VER0) +#else /* Other devices */ + #define ADC_CY_SAR_IP_VER (ADC_CY_SAR_IP_VER1) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + +/*************************************** +* Initial Parameter Constants +***************************************/ +#define ADC_DEFAULT_SAMPLE_MODE_SEL (0u) +#define ADC_DEFAULT_VREF_SEL (1u) +#define ADC_DEFAULT_NEG_INPUT_SEL (0u) +#define ADC_DEFAULT_ALT_RESOLUTION_SEL (0u) +#define ADC_DEFAULT_JUSTIFICATION_SEL (0u) +#define ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL (0u) +#define ADC_DEFAULT_SE_RESULT_FORMAT_SEL (1u) +#define ADC_DEFAULT_CLOCK_SOURCE (1u) +#define ADC_DEFAULT_VREF_MV_VALUE (5000) +#define ADC_DEFAULT_BUFFER_GAIN (0u) +#define ADC_DEFAULT_AVG_SAMPLES_NUM (7u) +#define ADC_DEFAULT_AVG_SAMPLES_DIV (7u < 4u) ? (int16)(0x100u >> (7u - 7u)) : (int16)(0x100u >> 4u) +#define ADC_DEFAULT_AVG_MODE (1u) +#define ADC_MAX_RESOLUTION (12u) +#define ADC_DEFAULT_LOW_LIMIT (511u) +#define ADC_DEFAULT_HIGH_LIMIT (1534u) +#define ADC_DEFAULT_COMPARE_MODE (3u) +#define ADC_DEFAULT_ACLKS_NUM (2u) +#define ADC_DEFAULT_BCLKS_NUM (2u) +#define ADC_DEFAULT_CCLKS_NUM (2u) +#define ADC_DEFAULT_DCLKS_NUM (2u) +#define ADC_TOTAL_CHANNELS_NUM (1u) +#define ADC_SEQUENCED_CHANNELS_NUM (1u) +#define ADC_DEFAULT_EN_CHANNELS (1u) +#define ADC_NOMINAL_CLOCK_FREQ (1000000) +#define ADC_INJ_CHANNEL_ENABLED (0u) +#define ADC_IRQ_REMOVE (0u) + +/* Determines whether the configuration contains external negative input. */ +#define ADC_SINGLE_PRESENT (0u) +#define ADC_CHANNELS_MODE (0u) +#define ADC_MAX_CHANNELS_EN_MASK (0xffffu >> (16u - ADC_SEQUENCED_CHANNELS_NUM)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void ADC_Start(void); +void ADC_Stop(void); +void ADC_Init(void); +void ADC_Enable(void); +void ADC_StartConvert(void); +void ADC_StopConvert(void); +uint32 ADC_IsEndConversion(uint32 retMode); +int16 ADC_GetResult16(uint32 chan); +void ADC_SetChanMask(uint32 mask); +void ADC_SetLowLimit(uint32 lowLimit); +void ADC_SetHighLimit(uint32 highLimit); +void ADC_SetLimitMask(uint32 mask); +void ADC_SetSatMask(uint32 mask); +void ADC_SetOffset(uint32 chan, int16 offset); +void ADC_SetGain(uint32 chan, int32 adcGain); +#if(ADC_INJ_CHANNEL_ENABLED) + void ADC_EnableInjection(void); +#endif /* ADC_INJ_CHANNEL_ENABLED */ +#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT) + int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts); + int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts); + float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts); +#endif /* End ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */ +void ADC_Sleep(void); +void ADC_Wakeup(void); +void ADC_SaveConfig(void); +void ADC_RestoreConfig(void); + +CY_ISR_PROTO( ADC_ISR ); + + +/************************************** +* API Constants +**************************************/ +/* Constants for Sleep mode states */ +#define ADC_DISABLED (0x00u) +#define ADC_ENABLED (0x01u) +#define ADC_STARTED (0x02u) +#define ADC_BOOSTPUMP_ENABLED (0x04u) + +/* Constants for IsEndConversion() "retMode" parameter */ +#define ADC_RETURN_STATUS (0x01u) +#define ADC_WAIT_FOR_RESULT (0x02u) +#define ADC_RETURN_STATUS_INJ (0x04u) +#define ADC_WAIT_FOR_RESULT_INJ (0x08u) + +#define ADC_MAX_FREQUENCY (18000000) /*18Mhz*/ + +#define ADC_RESOLUTION_12 (12u) +#define ADC_RESOLUTION_10 (10u) +#define ADC_RESOLUTION_8 (8u) + +#define ADC_10US_DELAY (10u) + +#define ADC_10V_COUNTS (10.0F) +#define ADC_10MV_COUNTS (10000) +#define ADC_10UV_COUNTS (10000000L) + + +/*************************************** +* Global variables external identifier +***************************************/ + +extern uint8 ADC_initVar; +extern volatile int16 ADC_offset[ADC_TOTAL_CHANNELS_NUM]; +extern volatile int32 ADC_countsPer10Volt[ADC_TOTAL_CHANNELS_NUM]; + + +/*************************************** +* Registers +***************************************/ + +#define ADC_SAR_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CTRL ) +#define ADC_SAR_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CTRL ) + +#define ADC_SAR_SAMPLE_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL ) +#define ADC_SAR_SAMPLE_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL ) + +#define ADC_SAR_SAMPLE_TIME01_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 ) +#define ADC_SAR_SAMPLE_TIME01_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 ) + +#define ADC_SAR_SAMPLE_TIME23_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 ) +#define ADC_SAR_SAMPLE_TIME23_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 ) + +#define ADC_SAR_RANGE_THRES_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_THRES ) +#define ADC_SAR_RANGE_THRES_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_THRES ) + +#define ADC_SAR_RANGE_COND_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_COND ) +#define ADC_SAR_RANGE_COND_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_COND ) + +#define ADC_SAR_CHAN_EN_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_EN ) +#define ADC_SAR_CHAN_EN_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_EN ) + +#define ADC_SAR_START_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_START_CTRL ) +#define ADC_SAR_START_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_START_CTRL ) + +#define ADC_SAR_DFT_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_DFT_CTRL ) +#define ADC_SAR_DFT_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_DFT_CTRL ) + +#define ADC_SAR_CHAN_CONFIG_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 ) +#define ADC_SAR_CHAN_CONFIG_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 ) +#define ADC_SAR_CHAN_CONFIG_IND ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 + +#define ADC_SAR_CHAN_WORK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK00 ) +#define ADC_SAR_CHAN_WORK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK00 ) + +#define ADC_SAR_CHAN_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_CHAN_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_CHAN_RESULT_IND ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 + +#define ADC_SAR_CHAN0_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_CHAN0_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 ) + +#define ADC_SAR_CHAN1_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 ) +#define ADC_SAR_CHAN1_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 ) + +#define ADC_SAR_CHAN2_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 ) +#define ADC_SAR_CHAN2_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 ) + +#define ADC_SAR_CHAN3_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 ) +#define ADC_SAR_CHAN3_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 ) + +#define ADC_SAR_CHAN4_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 ) +#define ADC_SAR_CHAN4_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 ) + +#define ADC_SAR_CHAN5_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 ) +#define ADC_SAR_CHAN5_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 ) + +#define ADC_SAR_CHAN6_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 ) +#define ADC_SAR_CHAN6_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 ) + +#define ADC_SAR_CHAN7_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 ) +#define ADC_SAR_CHAN7_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 ) + +#if(ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) + #define ADC_SAR_CHAN8_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 ) + #define ADC_SAR_CHAN8_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 ) + + #define ADC_SAR_CHAN9_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 ) + #define ADC_SAR_CHAN9_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 ) + + #define ADC_SAR_CHAN10_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 ) + #define ADC_SAR_CHAN10_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 ) + + #define ADC_SAR_CHAN11_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 ) + #define ADC_SAR_CHAN11_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 ) + + #define ADC_SAR_CHAN12_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 ) + #define ADC_SAR_CHAN12_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 ) + + #define ADC_SAR_CHAN13_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 ) + #define ADC_SAR_CHAN13_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 ) + + #define ADC_SAR_CHAN14_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 ) + #define ADC_SAR_CHAN14_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 ) + + #define ADC_SAR_CHAN15_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 ) + #define ADC_SAR_CHAN15_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 ) +#endif /* (ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) */ + +#define ADC_SAR_CHAN_WORK_VALID_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID) +#define ADC_SAR_CHAN_WORK_VALID_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID) + +#define ADC_SAR_CHAN_RESULT_VALID_REG ( *(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID ) +#define ADC_SAR_CHAN_RESULT_VALID_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID ) + +#define ADC_SAR_STATUS_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_STATUS ) +#define ADC_SAR_STATUS_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_STATUS ) + +#define ADC_SAR_AVG_START_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_AVG_STAT ) +#define ADC_SAR_AVG_START_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_AVG_STAT ) + +#define ADC_SAR_INTR_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR ) +#define ADC_SAR_INTR_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR ) + +#define ADC_SAR_INTR_SET_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_SET ) +#define ADC_SAR_INTR_SET_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_SET ) + +#define ADC_SAR_INTR_MASK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASK ) +#define ADC_SAR_INTR_MASK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASK ) + +#define ADC_SAR_INTR_MASKED_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASKED ) +#define ADC_SAR_INTR_MASKED_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASKED ) + +#define ADC_SAR_SATURATE_INTR_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR ) +#define ADC_SAR_SATURATE_INTR_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR ) + +#define ADC_SAR_SATURATE_INTR_SET_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET ) +#define ADC_SAR_SATURATE_INTR_SET_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET ) + +#define ADC_SAR_SATURATE_INTR_MASK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK ) +#define ADC_SAR_SATURATE_INTR_MASK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK ) + +#define ADC_SAR_SATURATE_INTR_MASKED_REG \ + (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED ) +#define ADC_SAR_SATURATE_INTR_MASKED_PTR \ + ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED ) + +#define ADC_SAR_RANGE_INTR_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR ) +#define ADC_SAR_RANGE_INTR_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR ) + +#define ADC_SAR_RANGE_INTR_SET_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET ) +#define ADC_SAR_RANGE_INTR_SET_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET ) + +#define ADC_SAR_RANGE_INTR_MASK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK ) +#define ADC_SAR_RANGE_INTR_MASK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK ) + +#define ADC_SAR_RANGE_INTR_MASKED_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED ) +#define ADC_SAR_RANGE_INTR_MASKED_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED ) + +#define ADC_SAR_INTR_CAUSE_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_CAUSE ) +#define ADC_SAR_INTR_CAUSE_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_CAUSE ) + +#if(ADC_INJ_CHANNEL_ENABLED) + #define ADC_SAR_INJ_CHAN_CONFIG_REG \ + (*(reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG ) + #define ADC_SAR_INJ_CHAN_CONFIG_PTR \ + ( (reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG ) + + #define ADC_SAR_INJ_RESULT_REG (*(reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_RESULT ) + #define ADC_SAR_INJ_RESULT_PTR ( (reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_RESULT ) +#endif /* ADC_INJ_CHANNEL_ENABLED */ + +#define ADC_MUX_SWITCH0_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 ) +#define ADC_MUX_SWITCH0_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 ) + +#define ADC_MUX_SWITCH_HW_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL ) +#define ADC_MUX_SWITCH_HW_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL ) + +#define ADC_PUMP_CTRL_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_PUMP_CTRL ) +#define ADC_PUMP_CTRL_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_PUMP_CTRL ) + +#define ADC_ANA_TRIM_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_ANA_TRIM ) +#define ADC_ANA_TRIM_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_ANA_TRIM ) + +#define ADC_WOUNDING_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_WOUNDING ) +#define ADC_WOUNDING_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_WOUNDING ) + + +/************************************** +* Register Constants +**************************************/ +#define ADC_INTC_NUMBER (ADC_IRQ__INTC_NUMBER) +#define ADC_INTC_PRIOR_NUMBER (ADC_IRQ__INTC_PRIOR_NUM) + +/* defines for CTRL register */ +#define ADC_VREF_INTERNAL1024 (0x00000040Lu) +#define ADC_VREF_EXTERNAL (0x00000050Lu) +#define ADC_VREF_VDDA_2 (0x00000060Lu) +#define ADC_VREF_VDDA (0x00000070Lu) +#define ADC_VREF_INTERNAL1024BYPASSED (0x000000C0Lu) +#define ADC_VREF_VDDA_2BYPASSED (0x000000E0Lu) +#define ADC_VREF_INTERNALVREF (0x00000040Lu) +#define ADC_VREF_INTERNALVREFBYPASSED (0x000000C0Lu) + +#define ADC_NEG_VSSA_KELVIN (0x00000000Lu) +#define ADC_NEG_VSSA (0x00000200Lu) +#define ADC_NEG_VREF (0x00000E00Lu) +#if(ADC_TOTAL_CHANNELS_NUM > 1u) + #define ADC_NEG_OTHER (uint16)((uint16)ADC_cy_psoc4_sarmux_8__VNEG0 << 9u) +#else + #define ADC_NEG_OTHER (0) +#endif /* ADC_TOTAL_CHANNELS_NUM > 1u */ + +#define ADC_SAR_HW_CTRL_NEGVREF (0x00002000Lu) + +#define ADC_BOOSTPUMP_EN (0x00100000Lu) + +#define ADC_NORMAL_PWR (0x00000000Lu) +#define ADC_HALF_PWR (0x01000000Lu) +#define ADC_MORE_PWR (0x02000000Lu) +#define ADC_QUARTER_PWR (0x03000000Lu) +#define ADC_DEEPSLEEP_ON (0x08000000Lu) + +#define ADC_DSI_SYNC_CONFIG (0x10000000Lu) +#define ADC_DSI_MODE (0x20000000Lu) +#define ADC_SWITCH_DISABLE (0x40000000Lu) +#define ADC_ENABLE (0x80000000Lu) + +/* defines for STATUS register */ +#define ADC_STATUS_BUSY (0x80000000Lu) + +/* defines for SAMPLE_CTRL register */ +#define ADC_ALT_RESOLUTION_10BIT (0x00000001Lu) +#define ADC_ALT_RESOLUTION_8BIT (0x00000000Lu) + +#define ADC_DATA_ALIGN_LEFT (0x00000002Lu) +#define ADC_DATA_ALIGN_RIGHT (0x00000000Lu) + +#define ADC_SE_SIGNED_RESULT (0x00000004Lu) +#define ADC_SE_UNSIGNED_RESULT (0x00000000Lu) + +#define ADC_DIFF_SIGNED_RESULT (0x00000008Lu) +#define ADC_DIFF_UNSIGNED_RESULT (0x00000000Lu) + +#define ADC_AVG_CNT_OFFSET (4u) +#define ADC_AVG_CNT_MASK (0x00000070Lu) +#define ADC_AVG_SHIFT (0x00000080Lu) + +#define ADC_CONTINUOUS_EN (0x00010000Lu) +#define ADC_DSI_TRIGGER_EN (0x00020000Lu) +#define ADC_DSI_TRIGGER_LEVEL (0x00040000Lu) +#define ADC_DSI_SYNC_TRIGGER (0x00080000Lu) +#define ADC_EOS_DSI_OUT_EN (0x80000000Lu) + +/* defines for SAMPLE_TIME01 / SAMPLE_TIME23 registers */ +#define ADC_SAMPLE_TIME13_OFFSET (16u) +#define ADC_SAMPLE_TIME02_MASK (0x000003FFLu) +#define ADC_SAMPLE_TIME13_MASK (0x03FF0000Lu) + +/* defines for RANGE_THRES registers */ +#define ADC_RANGE_HIGH_OFFSET (16u) +#define ADC_RANGE_HIGH_MASK (0xFFFF0000Lu) +#define ADC_RANGE_LOW_MASK (0x0000FFFFLu) + +/* defines for RANGE_COND register */ +/* Compare mode setting constants: +* BELOW - Result < Low_Limit +* INSIDE - Low_Limit <= Result < High_Limit +* ABOVE - High_Limit <= Result +* OUTSIDE - (Result < Low_Limit) or (High_Limit <= Result) +*/ +#define ADC_CMP_MODE_BELOW (0x00000000Lu) +#define ADC_CMP_MODE_INSIDE (0x40000000Lu) +#define ADC_CMP_MODE_ABOVE (0x80000000Lu) +#define ADC_CMP_MODE_OUTSIDE (0xC0000000Lu) +#define ADC_CMP_OFFSET (30u) + +/* defines for _START_CTRL register */ +#define ADC_FW_TRIGGER (0x00000001Lu) + +/* defines for DFT_CTRL register */ +#define ADC_DLY_INC (0x00000001Lu) +#define ADC_HIZ (0x00000002Lu) +#define ADC_DFT_INC_MASK (0x000F0000Lu) +#define ADC_DFT_OUTC_MASK (0x00700000Lu) +#define ADC_SEL_CSEL_DFT_MASK (0x0F000000Lu) + +/* configuration for clock speed > 9 Mhz based on +* characterization results +*/ +#define ADC_SEL_CSEL_DFT_CHAR (0x03000000Lu) +#define ADC_EN_CSEL_DFT (0x10000000Lu) +#define ADC_DCEN (0x20000000Lu) +#define ADC_ADFT_OVERRIDE (0x80000000Lu) + +/* defines for CHAN_CONFIG / DIE_CHAN_CONFIG register +* and channelsConfig parameter +*/ +#define ADC_SARMUX_VIRT_SELECT (0x00000070Lu) +#define ADC_DIFFERENTIAL_EN (0x00000100Lu) +#define ADC_ALT_RESOLUTION_ON (0x00000200Lu) +#define ADC_AVERAGING_EN (0x00000400Lu) + +#define ADC_SAMPLE_TIME_SEL_SHIFT (12u) +#define ADC_SAMPLE_TIME_SEL_MASK (0x00003000Lu) + +#define ADC_CHANNEL_CONFIG_MASK (0x00003700Lu) + +/* for CHAN_CONFIG only */ +#define ADC_DSI_OUT_EN (0x80000000Lu) + +/* for INJ_CHAN_CONFIG only */ +#define ADC_INJ_TAILGATING (0x40000000Lu) +#define ADC_INJ_CHAN_EN (0x80000000Lu) + +/* defines for CHAN_WORK register */ +#define ADC_SAR_WRK_MAX_12BIT (0x00001000Lu) +#define ADC_SAR_WRK_MAX_10BIT (0x00000400Lu) +#define ADC_SAR_WRK_MAX_8BIT (0x00000100Lu) + +/* defines for CHAN_RESULT register */ +#define ADC_RESULT_MASK (0x0000FFFFLu) +#define ADC_SATURATE_INTR_MIR (0x20000000Lu) +#define ADC_RANGE_INTR_MIR (0x40000000Lu) +#define ADC_CHAN_RESULT_VALID_MIR (0x80000000Lu) + +/* defines for INTR_MASK register */ +#define ADC_EOS_MASK (0x00000001Lu) +#define ADC_OVERFLOW_MASK (0x00000002Lu) +#define ADC_FW_COLLISION_MASK (0x00000004Lu) +#define ADC_DSI_COLLISION_MASK (0x00000008Lu) +#define ADC_INJ_EOC_MASK (0x00000010Lu) +#define ADC_INJ_SATURATE_MASK (0x00000020Lu) +#define ADC_INJ_RANGE_MASK (0x00000040Lu) +#define ADC_INJ_COLLISION_MASK (0x00000080Lu) + +/* defines for INJ_RESULT register */ +#define ADC_INJ_COLLISION_INTR_MIR (0x10000000Lu) +#define ADC_INJ_SATURATE_INTR_MIR (0x20000000Lu) +#define ADC_INJ_RANGE_INTR_MIR (0x40000000Lu) +#define ADC_INJ_EOC_INTR_MIR (0x80000000Lu) + +/* defines for MUX_SWITCH0 register */ +#define ADC_MUX_FW_VSSA_VMINUS (0x00010000Lu) + +/* defines for PUMP_CTRL register */ +#define ADC_PUMP_CTRL_ENABLED (0x80000000Lu) + +/* additional defines for channelsConfig parameter */ +#define ADC_IS_SATURATE_EN_MASK (0x00000001Lu) +#define ADC_IS_RANGE_CTRL_EN_MASK (0x00000002Lu) + +/* defines for WOUNDING register */ +#define ADC_WOUNDING_12BIT (0x00000000Lu) +#define ADC_WOUNDING_10BIT (0x00000001Lu) +#define ADC_WOUNDING_8BIT (0x00000002Lu) + +/* Trim value based on characterization */ +#define ADC_TRIM_COEF (2u) + +#if(ADC_MAX_RESOLUTION == ADC_RESOLUTION_10) + #define ADC_ALT_WOUNDING ADC_WOUNDING_10BIT +#else + #define ADC_ALT_WOUNDING ADC_WOUNDING_8BIT +#endif /* ADC_MAX_RESOLUTION == ADC_RESOLUTION_10 */ + +#if(ADC_DEFAULT_VREF_SEL == ADC__VDDA_2) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_VDDA_2 +#elif(ADC_DEFAULT_VREF_SEL == ADC__VDDA) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_VDDA +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNAL1024 +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024BYPASSED) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNAL1024BYPASSED +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNALVREF +#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREFBYPASSED) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_INTERNALVREFBYPASSED +#elif(ADC_DEFAULT_VREF_SEL == ADC__VDDA_2BYPASSED) + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_VDDA_2BYPASSED +#else + #define ADC_DEFAULT_VREF_SOURCE ADC_VREF_EXTERNAL +#endif /* ADC_DEFAULT_VREF_SEL == ADC__VDDA_2 */ + +#if(ADC_DEFAULT_NEG_INPUT_SEL == ADC__VSS) + /* Connect NEG input of SARADC to VSSA close to the SARADC for single channel mode */ + #if(ADC_TOTAL_CHANNELS_NUM == 1u) + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_VSSA + #else + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_VSSA_KELVIN + #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ + /* Do not connect VSSA to VMINUS when one channel in differential mode used */ + #if((ADC_TOTAL_CHANNELS_NUM == 1u) && (ADC_CHANNELS_MODE != 0u)) + #define ADC_DEFAULT_MUX_SWITCH0 0u + #else /* miltiple channels or one single channel */ + #define ADC_DEFAULT_MUX_SWITCH0 ADC_MUX_FW_VSSA_VMINUS + #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ +#elif(ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF) + /* Do not connect VNEG to VREF when one channel in differential mode used */ + #if((ADC_TOTAL_CHANNELS_NUM == 1u) && (ADC_CHANNELS_MODE != 0u)) + #define ADC_DEFAULT_SE_NEG_INPUT 0u + #else /* miltiple channels or one single channel */ + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_VREF + #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ + #define ADC_DEFAULT_MUX_SWITCH0 0u +#elif (ADC_SINGLE_PRESENT != 0u) + #define ADC_DEFAULT_SE_NEG_INPUT ADC_NEG_OTHER + #define ADC_DEFAULT_MUX_SWITCH0 0u +#else + #define ADC_DEFAULT_SE_NEG_INPUT 0u + #define ADC_DEFAULT_MUX_SWITCH0 0u +#endif /* ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF */ + +/* If the SAR is configured for multiple channels, always set SAR_HW_CTRL_NEGVREF to 1 */ +#if(ADC_TOTAL_CHANNELS_NUM == 1u) + #define ADC_DEFAULT_HW_CTRL_NEGVREF 0u +#else + #define ADC_DEFAULT_HW_CTRL_NEGVREF ADC_SAR_HW_CTRL_NEGVREF +#endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */ + + +#if(ADC_DEFAULT_ALT_RESOLUTION_SEL == ADC__RES8) + #define ADC_DEFAULT_ALT_RESOLUTION (ADC_ALT_RESOLUTION_8BIT) + #define ADC_DEFAULT_MAX_WRK_ALT (ADC_SAR_WRK_MAX_8BIT) +#else + #define ADC_DEFAULT_ALT_RESOLUTION (ADC_ALT_RESOLUTION_10BIT) + #define ADC_DEFAULT_MAX_WRK_ALT (ADC_SAR_WRK_MAX_10BIT) +#endif /* End ADC_DEFAULT_ALT_RESOLUTION_SEL == ADC__RES8 */ + +#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT) + #define ADC_DEFAULT_JUSTIFICATION ADC_DATA_ALIGN_RIGHT +#else + #define ADC_DEFAULT_JUSTIFICATION ADC_DATA_ALIGN_LEFT +#endif /* ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */ + +#if(ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FSIGNED) + #define ADC_DEFAULT_DIFF_RESULT_FORMAT ADC_DIFF_SIGNED_RESULT +#else + #define ADC_DEFAULT_DIFF_RESULT_FORMAT ADC_DIFF_UNSIGNED_RESULT +#endif /* ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FSIGNED */ + +#if(ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED) + #define ADC_DEFAULT_SE_RESULT_FORMAT ADC_SE_SIGNED_RESULT +#else + #define ADC_DEFAULT_SE_RESULT_FORMAT ADC_SE_UNSIGNED_RESULT +#endif /* ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED */ + +#if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING) + #define ADC_DSI_TRIGGER 0u +#else /* Firmware trigger */ + #define ADC_DSI_TRIGGER (ADC_DSI_TRIGGER_EN | ADC_DSI_SYNC_TRIGGER) +#endif /* End ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */ + +#if(ADC_INJ_CHANNEL_ENABLED) + #define ADC_SAR_INTR_MASK (ADC_EOS_MASK | ADC_INJ_EOC_MASK) +#else + #define ADC_SAR_INTR_MASK (ADC_EOS_MASK) +#endif /* ADC_INJ_CHANNEL_ENABLED*/ + +#if(ADC_DEFAULT_AVG_MODE == ADC__FIXEDRESOLUTION) + #define ADC_AVG_SHIFT_MODE ADC_AVG_SHIFT +#else + #define ADC_AVG_SHIFT_MODE 0u +#endif /* End ADC_DEFAULT_AVG_MODE */ + +#define ADC_COMPARE_MODE (uint32)((uint32)(ADC_DEFAULT_COMPARE_MODE) \ + << ADC_CMP_OFFSET) + +#if(ADC_TOTAL_CHANNELS_NUM > 1u) + #define ADC_DEFAULT_SWITCH_CONF 0u +#else /* Disable SAR sequencer from enabling routing switches in single channel mode */ + #define ADC_DEFAULT_SWITCH_CONF ADC_SWITCH_DISABLE +#endif /* End ADC_TOTAL_CHANNELS_NUM > 1 */ + +#define ADC_DEFAULT_POWER \ + ((ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 4)) ? ADC_NORMAL_PWR : \ + ((ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 8)) ? ADC_HALF_PWR : \ + ADC_QUARTER_PWR)) + +#define ADC_DEFAULT_CTRL_REG_CFG (ADC_DEFAULT_VREF_SOURCE \ + | ADC_DEFAULT_SE_NEG_INPUT \ + | ADC_DEFAULT_HW_CTRL_NEGVREF \ + | ADC_DEFAULT_POWER \ + | ADC_DSI_SYNC_CONFIG \ + | ADC_DEFAULT_SWITCH_CONF) + +#define ADC_DEFAULT_SAMPLE_CTRL_REG_CFG (ADC_DEFAULT_DIFF_RESULT_FORMAT \ + | ADC_DEFAULT_SE_RESULT_FORMAT \ + | ADC_DEFAULT_JUSTIFICATION \ + | ADC_DEFAULT_ALT_RESOLUTION \ + | (uint8)(ADC_DEFAULT_AVG_SAMPLES_NUM \ + << ADC_AVG_CNT_OFFSET) \ + | ADC_AVG_SHIFT_MODE \ + | ADC_DSI_TRIGGER \ + | ADC_EOS_DSI_OUT_EN) + +#define ADC_DEFAULT_RANGE_THRES_REG_CFG (ADC_DEFAULT_LOW_LIMIT \ + | (uint32)((uint32)ADC_DEFAULT_HIGH_LIMIT << ADC_RANGE_HIGH_OFFSET)) + +#define ADC_DEFAULT_SAMPLE_TIME01_REG_CFG (ADC_DEFAULT_ACLKS_NUM \ + | (uint32)((uint32)ADC_DEFAULT_BCLKS_NUM << ADC_SAMPLE_TIME13_OFFSET)) + +#define ADC_DEFAULT_SAMPLE_TIME23_REG_CFG (ADC_DEFAULT_CCLKS_NUM \ + | (uint32)((uint32)ADC_DEFAULT_DCLKS_NUM << ADC_SAMPLE_TIME13_OFFSET)) + + +#endif /* End CY_ADC_SAR_SEQ_ADC_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_INT.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_INT.c new file mode 100644 index 0000000..5b3cc04 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_INT.c @@ -0,0 +1,78 @@ +/******************************************************************************* +* File Name: ADC_INT.c +* Version 2.50 +* +* Description: +* This file contains the code that operates during the ADC_SAR interrupt +* service routine. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC.h" +#include "cyapicallbacks.h" + + +/****************************************************************************** +* Custom Declarations and Variables +* - add user inlcude files, prototypes and variables between the following +* #START and #END tags +******************************************************************************/ +/* `#START ADC_SYS_VAR` */ + +/* `#END` */ + +#if(ADC_IRQ_REMOVE == 0u) + + + /****************************************************************************** + * Function Name: ADC_ISR + ******************************************************************************* + * + * Summary: + * Handle Interrupt Service Routine. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Reentrant: + * No. + * + ******************************************************************************/ + CY_ISR( ADC_ISR ) + { + uint32 intr_status; + + /* Read interrupt status register */ + intr_status = ADC_SAR_INTR_REG; + + #ifdef ADC_ISR_INTERRUPT_CALLBACK + ADC_ISR_InterruptCallback(); + #endif /* ADC_ISR_INTERRUPT_CALLBACK */ + + + /************************************************************************ + * Custom Code + * - add user ISR code between the following #START and #END tags + *************************************************************************/ + /* `#START MAIN_ADC_ISR` */ + + /* `#END` */ + + /* Clear handled interrupt */ + ADC_SAR_INTR_REG = intr_status; + } + +#endif /* End ADC_IRQ_REMOVE */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_IRQ.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_IRQ.c new file mode 100644 index 0000000..677a33d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_IRQ.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: ADC_IRQ.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(ADC_IRQ__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START ADC_IRQ_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: ADC_IRQ_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Start(void) +{ + /* For all we know the interrupt is active. */ + ADC_IRQ_Disable(); + + /* Set the ISR to point to the ADC_IRQ Interrupt. */ + ADC_IRQ_SetVector(&ADC_IRQ_Interrupt); + + /* Set the priority. */ + ADC_IRQ_SetPriority((uint8)ADC_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + ADC_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + ADC_IRQ_Disable(); + + /* Set the ISR to point to the ADC_IRQ Interrupt. */ + ADC_IRQ_SetVector(address); + + /* Set the priority. */ + ADC_IRQ_SetPriority((uint8)ADC_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + ADC_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Stop(void) +{ + /* Disable this interrupt. */ + ADC_IRQ_Disable(); + + /* Set the ISR to point to the passive one. */ + ADC_IRQ_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for ADC_IRQ. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(ADC_IRQ_Interrupt) +{ + #ifdef ADC_IRQ_INTERRUPT_INTERRUPT_CALLBACK + ADC_IRQ_Interrupt_InterruptCallback(); + #endif /* ADC_IRQ_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START ADC_IRQ_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling ADC_IRQ_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use ADC_IRQ_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + ADC_IRQ__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress ADC_IRQ_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + ADC_IRQ__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling ADC_IRQ_Start or ADC_IRQ_StartEx will +* override any effect this API would have had. This API should only be called +* after ADC_IRQ_Start or ADC_IRQ_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((ADC_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *ADC_IRQ_INTC_PRIOR = (*ADC_IRQ_INTC_PRIOR & (uint32)(~ADC_IRQ__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 ADC_IRQ_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((ADC_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*ADC_IRQ_INTC_PRIOR & ADC_IRQ__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Enable(void) +{ + /* Enable the general interrupt. */ + *ADC_IRQ_INTC_SET_EN = ADC_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 ADC_IRQ_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*ADC_IRQ_INTC_SET_EN & (uint32)ADC_IRQ__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_Disable(void) +{ + /* Disable the general interrupt. */ + *ADC_IRQ_INTC_CLR_EN = ADC_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void ADC_IRQ_SetPending(void) +{ + *ADC_IRQ_INTC_SET_PD = ADC_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_IRQ_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_IRQ_ClearPending(void) +{ + *ADC_IRQ_INTC_CLR_PD = ADC_IRQ__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_IRQ.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_IRQ.h new file mode 100644 index 0000000..d91008a --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_IRQ.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* File Name: ADC_IRQ.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_ADC_IRQ_H) +#define CY_ISR_ADC_IRQ_H + + +#include +#include + +/* Interrupt Controller API. */ +void ADC_IRQ_Start(void); +void ADC_IRQ_StartEx(cyisraddress address); +void ADC_IRQ_Stop(void); + +CY_ISR_PROTO(ADC_IRQ_Interrupt); + +void ADC_IRQ_SetVector(cyisraddress address); +cyisraddress ADC_IRQ_GetVector(void); + +void ADC_IRQ_SetPriority(uint8 priority); +uint8 ADC_IRQ_GetPriority(void); + +void ADC_IRQ_Enable(void); +uint8 ADC_IRQ_GetState(void); +void ADC_IRQ_Disable(void); + +void ADC_IRQ_SetPending(void); +void ADC_IRQ_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the ADC_IRQ ISR. */ +#define ADC_IRQ_INTC_VECTOR ((reg32 *) ADC_IRQ__INTC_VECT) + +/* Address of the ADC_IRQ ISR priority. */ +#define ADC_IRQ_INTC_PRIOR ((reg32 *) ADC_IRQ__INTC_PRIOR_REG) + +/* Priority of the ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_PRIOR_NUMBER ADC_IRQ__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_SET_EN ((reg32 *) ADC_IRQ__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_CLR_EN ((reg32 *) ADC_IRQ__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the ADC_IRQ interrupt state to pending. */ +#define ADC_IRQ_INTC_SET_PD ((reg32 *) ADC_IRQ__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the ADC_IRQ interrupt. */ +#define ADC_IRQ_INTC_CLR_PD ((reg32 *) ADC_IRQ__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_ADC_IRQ_H */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_PM.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_PM.c new file mode 100644 index 0000000..b159bba --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_PM.c @@ -0,0 +1,158 @@ +/******************************************************************************* +* File Name: ADC_PM.c +* Version 2.50 +* +* Description: +* This file provides Sleep/WakeUp APIs functionality. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC.h" + + +/*************************************** +* Local data allocation +***************************************/ + +static ADC_BACKUP_STRUCT ADC_backup = +{ + ADC_DISABLED, + 0u +}; + + +/******************************************************************************* +* Function Name: ADC_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SaveConfig(void) +{ + /* All configuration registers are marked as [reset_all_retention] */ +} + + +/******************************************************************************* +* Function Name: ADC_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_RestoreConfig(void) +{ + /* All configuration registers are marked as [reset_all_retention] */ +} + + +/******************************************************************************* +* Function Name: ADC_Sleep +******************************************************************************** +* +* Summary: +* Stops the ADC operation and saves the configuration registers and component +* enable state. Should be called just prior to entering sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* ADC_backup - modified. +* +*******************************************************************************/ +void ADC_Sleep(void) +{ + /* During deepsleep/ hibernate mode keep SARMUX active, i.e. do not open + * all switches (disconnect), to be used for ADFT + */ + ADC_backup.dftRegVal = ADC_SAR_DFT_CTRL_REG & (uint32)~ADC_ADFT_OVERRIDE; + ADC_SAR_DFT_CTRL_REG |= ADC_ADFT_OVERRIDE; + if((ADC_SAR_CTRL_REG & ADC_ENABLE) != 0u) + { + if((ADC_SAR_SAMPLE_CTRL_REG & ADC_CONTINUOUS_EN) != 0u) + { + ADC_backup.enableState = ADC_ENABLED | ADC_STARTED; + } + else + { + ADC_backup.enableState = ADC_ENABLED; + } + ADC_StopConvert(); + ADC_Stop(); + + /* Disable the SAR internal pump before entering the chip low power mode */ + if((ADC_SAR_CTRL_REG & ADC_BOOSTPUMP_EN) != 0u) + { + ADC_SAR_CTRL_REG &= (uint32)~ADC_BOOSTPUMP_EN; + ADC_backup.enableState |= ADC_BOOSTPUMP_ENABLED; + } + } + else + { + ADC_backup.enableState = ADC_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: ADC_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component enable state and configuration registers. +* This should be called just after awaking from sleep mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* ADC_backup - used. +* +*******************************************************************************/ +void ADC_Wakeup(void) +{ + ADC_SAR_DFT_CTRL_REG = ADC_backup.dftRegVal; + if(ADC_backup.enableState != ADC_DISABLED) + { + /* Enable the SAR internal pump */ + if((ADC_backup.enableState & ADC_BOOSTPUMP_ENABLED) != 0u) + { + ADC_SAR_CTRL_REG |= ADC_BOOSTPUMP_EN; + } + ADC_Enable(); + if((ADC_backup.enableState & ADC_STARTED) != 0u) + { + ADC_StartConvert(); + } + } +} +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_intClock.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_intClock.c new file mode 100644 index 0000000..0ade334 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_intClock.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: ADC_intClock.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "ADC_intClock.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: ADC_intClock_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void ADC_intClock_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((ADC_intClock_CMD_REG & ADC_intClock_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + ADC_intClock_CMD_REG = + ((uint32)ADC_intClock__DIV_ID << ADC_intClock_CMD_DIV_SHIFT)| + (alignClkDiv << ADC_intClock_CMD_PA_DIV_SHIFT) | + (uint32)ADC_intClock_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: ADC_intClock_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void ADC_intClock_Start(void) +{ + /* Set the bit to enable the clock. */ + ADC_intClock_ENABLE_REG |= ADC_intClock__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: ADC_intClock_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void ADC_intClock_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((ADC_intClock_CMD_REG & ADC_intClock_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + ADC_intClock_CMD_REG = + ((uint32)ADC_intClock__DIV_ID << ADC_intClock_CMD_DIV_SHIFT)| + ((uint32)ADC_intClock_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + ADC_intClock_ENABLE_REG &= (uint32)(~ADC_intClock__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: ADC_intClock_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void ADC_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (ADC_intClock__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = ADC_intClock_DIV_REG & + (uint32)(~(uint32)(ADC_intClock_DIV_INT_MASK | ADC_intClock_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << ADC_intClock_DIV_INT_SHIFT) & ADC_intClock_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << ADC_intClock_DIV_FRAC_SHIFT) & ADC_intClock_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = ADC_intClock_DIV_REG & (uint32)(~(uint32)ADC_intClock__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* ADC_intClock__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + ADC_intClock_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: ADC_intClock_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 ADC_intClock_GetDividerRegister(void) +{ + return (uint16)((ADC_intClock_DIV_REG & ADC_intClock_DIV_INT_MASK) + >> ADC_intClock_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: ADC_intClock_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 ADC_intClock_GetFractionalDividerRegister(void) +{ +#if defined (ADC_intClock__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((ADC_intClock_DIV_REG & ADC_intClock_DIV_FRAC_MASK) + >> ADC_intClock_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* ADC_intClock__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_intClock.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_intClock.h new file mode 100644 index 0000000..1f0e651 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/ADC_intClock.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* File Name: ADC_intClock.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_ADC_intClock_H) +#define CY_CLOCK_ADC_intClock_H + +#include +#include + + +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void ADC_intClock_StartEx(uint32 alignClkDiv); +#define ADC_intClock_Start() \ + ADC_intClock_StartEx(ADC_intClock__PA_DIV_ID) + +#else + +void ADC_intClock_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void ADC_intClock_Stop(void); + +void ADC_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 ADC_intClock_GetDividerRegister(void); +uint8 ADC_intClock_GetFractionalDividerRegister(void); + +#define ADC_intClock_Enable() ADC_intClock_Start() +#define ADC_intClock_Disable() ADC_intClock_Stop() +#define ADC_intClock_SetDividerRegister(clkDivider, reset) \ + ADC_intClock_SetFractionalDividerRegister((clkDivider), 0u) +#define ADC_intClock_SetDivider(clkDivider) ADC_intClock_SetDividerRegister((clkDivider), 1u) +#define ADC_intClock_SetDividerValue(clkDivider) ADC_intClock_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define ADC_intClock_DIV_ID ADC_intClock__DIV_ID + +#define ADC_intClock_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define ADC_intClock_CTRL_REG (*(reg32 *)ADC_intClock__CTRL_REGISTER) +#define ADC_intClock_DIV_REG (*(reg32 *)ADC_intClock__DIV_REGISTER) + +#define ADC_intClock_CMD_DIV_SHIFT (0u) +#define ADC_intClock_CMD_PA_DIV_SHIFT (8u) +#define ADC_intClock_CMD_DISABLE_SHIFT (30u) +#define ADC_intClock_CMD_ENABLE_SHIFT (31u) + +#define ADC_intClock_CMD_DISABLE_MASK ((uint32)((uint32)1u << ADC_intClock_CMD_DISABLE_SHIFT)) +#define ADC_intClock_CMD_ENABLE_MASK ((uint32)((uint32)1u << ADC_intClock_CMD_ENABLE_SHIFT)) + +#define ADC_intClock_DIV_FRAC_MASK (0x000000F8u) +#define ADC_intClock_DIV_FRAC_SHIFT (3u) +#define ADC_intClock_DIV_INT_MASK (0xFFFFFF00u) +#define ADC_intClock_DIV_INT_SHIFT (8u) + +#else + +#define ADC_intClock_DIV_REG (*(reg32 *)ADC_intClock__REGISTER) +#define ADC_intClock_ENABLE_REG ADC_intClock_DIV_REG +#define ADC_intClock_DIV_FRAC_MASK ADC_intClock__FRAC_MASK +#define ADC_intClock_DIV_FRAC_SHIFT (16u) +#define ADC_intClock_DIV_INT_MASK ADC_intClock__DIVIDER_MASK +#define ADC_intClock_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_ADC_intClock_H) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0Iar.icf b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0Iar.icf new file mode 100644 index 0000000..f45b65d --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0Iar.icf @@ -0,0 +1,226 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 32768 - 1; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + 4096 - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0100; +/**** End of ICF editor section. ###ICF###*/ + + +/******** Definitions ********/ +define symbol CY_FLASH_SIZE = 32768; +define symbol CY_APPL_ORIGIN = 0; +define symbol CY_FLASH_ROW_SIZE = 128; +define symbol CY_APPL_LOADABLE = 0; +define symbol CY_APPL_LOADER = 0; +define symbol CY_APPL_NUM = 1; +define symbol CY_METADATA_SIZE = 64; +define symbol CY_APPL_MAX = 1; +define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0; +define symbol CY_APPL_FOR_STACK_AND_COPIER = 0; +define symbol CY_FIRST_AVAILABLE_META_ROW = 0; + +define symbol CYDEV_IS_IMPORTING_CODE = 0; +define symbol CYDEV_IS_EXPORTING_CODE = 0; + + + +if (!CY_APPL_LOADABLE) { + define symbol CYDEV_BTLDR_SIZE = 0; + + /* The first 0x100 Flash bytes become unavailable right after remapping of the vector table to RAM. + * This space should be used for .romvectors section. + */ + define block ROMVEC with size = 0x100 {readonly section .romvectors}; + + define block APPL with fixed order {block ROMVEC, section .psocinit, readonly}; +} else { + define block APPL with fixed order {readonly section .romvectors, section .psocinit, readonly}; +} + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, last block CSTACK}; + +define block RAMVEC with fixed order {readwrite section .ramvectors, readwrite section .bootloaderruntype}; + +if (CY_APPL_LOADABLE) +{ + define block LOADER { readonly section .cybootloader }; +} + +/* The address of the Flash row next after the Bootloader image */ +define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? + (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); + +/* The start address of Standard/Loader/Loadable#1 image */ +define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; + +/* The number of metadata records located at the end of Flash */ +define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); + +/* The application area size measured in rows */ +define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; + +/* The start address of Loadable#2 image if any */ +define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; + +/* The current image (Standard/Loader/Loadable) start address */ +define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; + +/* Define APPL region that will limit application size */ +define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; + + +/****** Initializations ******/ +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { readwrite section .ramvectors, readwrite section .bootloaderruntype }; + +/******** Placements *********/ +if (CY_APPL_LOADABLE) +{ +".cybootloader" : place at start of ROM_region {block LOADER}; +} + +"APPL" : place at start of APPL_region {block APPL}; + +"RAMVEC" : place at start of RAM_region { block RAMVEC }; +"readwrite" : place in RAM_region { readwrite }; +"HSTACK" : place at end of RAM_region { block HSTACK}; + +keep { section .cybootloader, + section .cyloadermeta, + section .cyloadablemeta, + section .cy_checksum_exclude, + section .cyflashprotect, + section .cymeta, + section .cychipprotect }; + + +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if ((CY_APPL_LOADER)&&!(CY_APPL_LOADABLE)) +{ + ".cyloadermeta" : place at address mem : (CY_FLASH_SIZE - CY_METADATA_SIZE) { readonly section .cyloadermeta }; +} +else +{ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + ".cyloadermeta" : place at address mem : (CY_FLASH_SIZE - CY_METADATA_SIZE) { readonly section .cyloadermeta }; + } + else + { + /* Must be part of the image, but beyond rom memory. */ + ".cyloadermeta" : place at address mem : 0x90700000 { readonly section .cyloadermeta }; + } +} + + + +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* General case */ + if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (CY_APPL_NUM - 1); + } + + /* Stack Project (SP) */ + if (CYDEV_IS_EXPORTING_CODE == 1) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (0); + } + + /* App for SP+L */ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (1); + } + + define symbol CYLOADABLEMETA_START_ADDR = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_METADATA_SLOT_NUM - CY_METADATA_SIZE); + + + ".cyloadablemeta" : place at address mem : CYLOADABLEMETA_START_ADDR { readonly section .cyloadablemeta }; +} + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* Align size to the flash row size */ + define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0); + + if (CY_CHECKSUM_EXCLUDE_SIZE != 0) + { + + /* General case */ + if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + { + if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + else + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + } + + + if (CY_APPL_MAX == 1) + { + /* Stack Project (SP) */ + if (CYDEV_IS_EXPORTING_CODE == 1) + { + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; + } + + /* App for SP+L */ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * 2) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + } + } + + } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */ +} +else +{ + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; +} + + +".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; +".cychipprotect" : place at address mem : 0x90600000 { readonly section .cychipprotect }; + + +/* EOF */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0RealView.scat b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0RealView.scat new file mode 100644 index 0000000..732f8a4 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0RealView.scat @@ -0,0 +1,245 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************** +;* \file Cm0RealView.scat +;* \version 5.70 +;* +;* \brief This Linker Descriptor file describes the memory layout of the PSOC4 +;* device family. The memory layout of the final binary and hex images as well +;* as the placement in the PSOC4 memory is described. +;* +;* romvectors: Cypress default Interrupt service routine vector table. +;* +;* This is the ISR vector table at bootup. Used only for the reset vector. +;* +;* +;* ramvectors: Cypress ram interrupt service routine vector table. +;* +;* This is the ISR vector table used by the application. +;* +;******************************************************************************** +;* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;********************************************************************************/ +#include "cyfitter.h" +#include "cycodeshareimport.scat" + +#define CY_FLASH_SIZE 32768 +#define CY_APPL_ORIGIN 0 +#define CY_FLASH_ROW_SIZE 128 +#define CY_METADATA_SIZE 64 + +#define CY_APPL_FOR_STACK_AND_COPIER 0 +#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE) +#define CY_APPL_NUM 1 +#define CY_APPL_MAX 1 + + +; Define application base address +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + #if CY_APPL_ORIGIN + #define APPL1_START CY_APPL_ORIGIN + #else + #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) + #endif + + #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) + +#else + + #define APPL_START 0 + +#endif + + +; Place Bootloader at the beginning of Flash +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + CYBOOTLOADER 0 + { + .cybootloader +0 + { + * (.cybootloader) + } + } + + #if CY_APPL_ORIGIN + ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER)) + #endif + +#endif + + +APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) +{ + VECTORS +0 + { + * (.romvectors) + } + + RELOCATION +0 + { + * (.psocinit) + } + + CODE ((ImageLimit(RELOCATION) < 0x100) ? 0x100 : ImageLimit(RELOCATION)) FIXED + { + * (+RO) + } + + ISRVECTORS (0x20000000) UNINIT + { + * (.ramvectors, +FIRST) + } + + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + BTLDR_RUN +0 UNINIT + { + * (.bootloaderruntype) + } + #endif + + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + DATA +0 + { + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP (0x20000000 + 4096 - 0x0100 - 0x0400) EMPTY 0x0100 + { + } + + ARM_LIB_STACK (0x20000000 + 4096) EMPTY -0x0400 + { + } +} + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + + #if (0 != 0) + + /* General case */ + #if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + #define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #else + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + #endif + + #if (CY_APPL_MAX == 1) + + /* Stack Project (SP) */ + #if (CYDEV_IS_EXPORTING_CODE == 1) + #define CY_CHECKSUM_EXCLUDE_START (+0) + #endif + + /* App for SP+L */ + #if ((CYDEV_IS_IMPORTING_CODE == 1) && (0 == 2)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * 2) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + #endif + + CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START) + { + .cy_checksum_exclude +0 + { + * (.cy_checksum_exclude) + } + } + + #endif /* (0 != 0) */ + +#endif + + +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER || \ + CY_APPL_FOR_STACK_AND_COPIER) + + CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif + + +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* General case */ + #if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + #define CY_APPL_METADATA_SLOT_NUM (CY_APPL_NUM - 1) + #endif + + /* Stack Project (SP) */ + #if (CYDEV_IS_EXPORTING_CODE == 1) + #define CY_APPL_METADATA_SLOT_NUM (0) + #endif + + /* App for SP+L */ + #if ((CYDEV_IS_IMPORTING_CODE == 1) && (0 == 2)) + #define CY_APPL_METADATA_SLOT_NUM (1) + #endif + + #define CYLOADABLEMETA_START_ADDR (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_METADATA_SLOT_NUM - CY_METADATA_SIZE) + + CYLOADABLEMETA (CYLOADABLEMETA_START_ADDR) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } +#endif + +CYFLASHPROTECT 0x90400000 +{ + .cyflashprotect +0 { * (.cyflashprotect) } +} + +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +CYCHIPPROTECT 0x90600000 +{ + .cychipprotect +0 { * (.cychipprotect) } +} + + +/******************************************************************************* +* Bootloader Metadata Section. Must be part of the image, but beyond rom memory. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) && \ + !(CY_APPL_FOR_STACK_AND_COPIER)) + + CYLOADERMETA +0 + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif + diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0Start.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0Start.c new file mode 100644 index 0000000..e3d9780 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/Cm0Start.c @@ -0,0 +1,545 @@ +/***************************************************************************//** +* \file Cm0Start.c +* \version 5.70 +* +* \brief Startup code for the ARM CM0. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "cyfitter.h" +#include "cyapicallbacks.h" + +#define CY_NUM_VECTORS (CY_INT_IRQ_BASE + CY_NUM_INTERRUPTS) + +#if (CY_IP_CPUSS_CM0) + #define CY_CPUSS_CONFIG_VECT_IN_RAM (( uint32 ) 0x01) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#if (CY_IP_CPUSS_CM0) + /* CPUSS Configuration register */ + #define CY_CPUSS_CONFIG_REG (*(reg32 *) CYREG_CPUSS_CONFIG) + #define CY_CPUSS_CONFIG_PTR ( (reg32 *) CYREG_CPUSS_CONFIG) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#if defined (__ICCARM__) + #define CY_NUM_ROM_VECTORS (CY_NUM_VECTORS) +#else + #define CY_NUM_ROM_VECTORS (4u) +#endif /* defined (__ICCARM__) */ + +/* Vector table address in SRAM */ +#define CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM (0x20000000u) + +#ifndef CY_SYS_INITIAL_STACK_POINTER + + #if defined(__ARMCC_VERSION) + #define CY_SYS_INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) + #elif defined (__GNUC__) + #define CY_SYS_INITIAL_STACK_POINTER (&__cy_stack) + #elif defined (__ICCARM__) + #pragma language=extended + #pragma segment="CSTACK" + #define CY_SYS_INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + + extern void __iar_program_start( void ); + extern void __iar_data_init3 (void); + #endif /* (__ARMCC_VERSION) */ + +#endif /* CY_SYS_INITIAL_STACK_POINTER */ + + +#if defined(__GNUC__) + #include + extern int end; +#endif /* defined(__GNUC__) */ + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +#if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + + /******************************************************************************* + This variable is used by the Bootloader/Bootloadable components to schedule + what application will be started after a software reset. + *******************************************************************************/ + #if (__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* (__ARMCC_VERSION) */ + volatile uint32 cyBtldrRunType; + +#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + + +/******************************************************************************* +* Function Name: IntDefaultHandler +****************************************************************************//** +* +* This function is called for all interrupts, other than a reset that is called +* before the system is setup. +* +*******************************************************************************/ +CY_NORETURN +CY_ISR(IntDefaultHandler) +{ + /*************************************************************************** + * We must not get here. If we do, a serious problem occurs, so go into + * an infinite loop. + ***************************************************************************/ + + #if defined(__GNUC__) + if (errno == ENOMEM) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK + CyBoot_IntDefaultHandler_Enomem_Exception_Callback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */ + + while(1) + { + /* Out Of Heap Space + * This can be increased in the System tab of the Design Wide Resources. + */ + } + } + else + #endif + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + + } + } +} + +#if defined(__ARMCC_VERSION) + +/* Local function for device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +/* Linker-generated Stack Base addresses, Two Region and One Region */ +extern unsigned long Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the MDK toolchains. +* This is the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + /* The bootloadable application image is started at Reset() handler + * as a result of a branch instruction execution from the bootloader. + * So, the stack pointer needs to be reset to be sure that + * there is no garbage in the stack. + */ + register uint32_t msp __asm("msp"); + msp = (uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit; + #endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + __main(); +} + +/******************************************************************************* +* Function Name: $Sub$$main +****************************************************************************//** +* +* This function is called immediately before the users main +* +*******************************************************************************/ +__attribute__ ((noreturn, __noinline__)) +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* The static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* System Calls of the Red Hat newlib C Library +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: _exit +****************************************************************************//** +* +* Exit a program without cleaning up files. If your system doesn't provide +* this, it is best to avoid linking with subroutines that require it (exit, +* system). +* +* \param status: Status caused program exit. +* +*******************************************************************************/ +__attribute__((weak)) +void _exit(int status) +{ + CyHalt((uint8) status); + + while(1) + { + + } +} + + +/******************************************************************************* +* Function Name: _sbrk +****************************************************************************//** +* +* Increase program data space. As malloc and related functions depend on this, +* it is useful to have a working implementation. The following suffices for a +* standalone system; it exploits the symbol end automatically defined by the +* GNU linker. +* +* \param nbytes: The number of bytes requested (if the parameter value is positive) +* from the heap or returned back to the heap (if the parameter value is +* negative). +* +*******************************************************************************/ +__attribute__((weak)) +void * _sbrk (int nbytes) +{ + extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */ + void * returnValue; + + /* The statically held previous end of the heap, with its initialization. */ + static uint8 *heapPointer = (uint8 *) &end; /* Previous end */ + + if (((heapPointer + nbytes) - (uint8 *) &end) <= CYDEV_HEAP_SIZE) + { + returnValue = (void *) heapPointer; + heapPointer += nbytes; + } + else + { + errno = ENOMEM; + returnValue = (void *) -1; + } + + return (returnValue); +} + + +/******************************************************************************* +* Function Name: Start_c +****************************************************************************//** +* +* This function handles initializing the .data and .bss sections in +* preparation for running the standard c code. Once initialization is complete +* it will call main(). This function will never return. +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn, noinline)); +void Start_c(void) +{ + #ifdef CY_BOOT_START_C_CALLBACK + CyBoot_Start_c_Callback(); + #else + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num; regions != 0u; regions--) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = *src; + dst++; + src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = 0u; + dst++; + } + + rptr++; + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } + + #endif /* CY_BOOT_START_C_CALLBACK */ +} + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the GCC toolchain. This is +* the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* The bootloadable application image is started at Reset() handler + * as a result of a branch instruction execution from the bootloader. + * So, the stack pointer needs to be reset to be sure that + * there is no garbage in the stack. + */ + __asm volatile ("MSR msp, %0\n" : : "r" ((uint32)&__cy_stack) : "sp"); + #endif /* CYDEV_PROJ_TYPE_LOADABLE */ + + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + Start_c(); +} + +#elif defined (__ICCARM__) + + +/******************************************************************************* +* Function Name: __low_level_init +****************************************************************************//** +* +* This function performs early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of reset interrupt handler +* before the data sections are initialized. +* +* \return The value that determines whether or not data sections should be +* initialized by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +#pragma inline = never +int __low_level_init(void) +{ + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + +#if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); +#endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* Ram Interrupt Vector table storage area. Must be placed at 0x20000000. +*******************************************************************************/ + +#if defined (__ICCARM__) + #pragma location=".ramvectors" +#elif defined (__ARMCC_VERSION) + #ifndef CY_SYS_RAM_VECTOR_SECTION + #define CY_SYS_RAM_VECTOR_SECTION __attribute__((section(".ramvectors"), zero_init)) + #endif /* CY_SYS_RAM_VECTOR_SECTION */ + CY_SYS_RAM_VECTOR_SECTION +#else + #ifndef CY_SYS_RAM_VECTOR_SECTION + #define CY_SYS_RAM_VECTOR_SECTION CY_SECTION(".ramvectors") + #endif /* CY_SYS_RAM_VECTOR_SECTION */ + CY_SYS_RAM_VECTOR_SECTION +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Rom Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ + +#if defined(__ARMCC_VERSION) + /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + #pragma diag_suppress 1296 +#endif /* defined(__ARMCC_VERSION) */ + +#if defined (__ICCARM__) + #pragma location=".romvectors" + const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = +#else + #ifndef CY_SYS_ROM_VECTOR_SECTION + #define CY_SYS_ROM_VECTOR_SECTION CY_SECTION(".romvectors") + #endif /* CY_SYS_ROM_VECTOR_SECTION */ + CY_SYS_ROM_VECTOR_SECTION + const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = +#endif /* defined (__ICCARM__) */ +{ + CY_SYS_INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #if defined (__ICCARM__) /* The reset handler 1 */ + __iar_program_start, + #else + (cyisraddress)&Reset, + #endif /* defined (__ICCARM__) */ + &IntDefaultHandler, /* The NMI handler 2 */ + &IntDefaultHandler, /* The hard fault handler 3 */ +}; + +#if defined(__ARMCC_VERSION) + #pragma diag_default 1296 +#endif /* defined(__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: initialize_psoc +****************************************************************************//** +* +* This function is used to initialize the PSoC chip before calling main. +* +*******************************************************************************/ +#if(defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif /* (defined(__GNUC__) && !defined(__ARMCC_VERSION)) */ +void initialize_psoc(void) +{ + uint32 indexInit; + + #if(CY_IP_CPUSSV2) + #if (CY_IP_CPUSS_CM0) + /*********************************************************************** + * Make sure that Vector Table is located at 0000_0000 in Flash, before + * accessing RomVectors or calling functions that may be placed in + * .psocinit (cyfitter_cfg and ClockSetup). Note The CY_CPUSS_CONFIG_REG + * register is retention for the specified device family. + ***********************************************************************/ + CY_CPUSS_CONFIG_REG &= (uint32) ~CY_CPUSS_CONFIG_VECT_IN_RAM; + #endif /* (CY_IP_CPUSS_CM0) */ + #endif /* (CY_IP_CPUSSV2) */ + + /* Set Ram interrupt vectors to default functions. */ + for (indexInit = 0u; indexInit < CY_NUM_VECTORS; indexInit++) + { + CyRamVectors[indexInit] = (indexInit < CY_NUM_ROM_VECTORS) ? + #if defined (__ICCARM__) + __vector_table[indexInit].__fun : &IntDefaultHandler; + #else + RomVectors[indexInit] : &IntDefaultHandler; + #endif /* defined (__ICCARM__) */ + } + + /* Initialize configuration registers. */ + cyfitter_cfg(); + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ + + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + + /* Need to make sure that this variable will not be optimized out */ + if (0u == cyBtldrRunType) + { + cyBtldrRunType = 0u; + } + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + + #if (CY_IP_CPUSS_CM0) + /* Vector Table is located at 0x2000:0000 in SRAM */ + CY_CPUSS_CONFIG_REG |= CY_CPUSS_CONFIG_VECT_IN_RAM; + #else + (*(uint32 *)CYREG_CM0P_VTOR) = CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM; + #endif /* (CY_IP_CPUSS_CM0) */ +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s new file mode 100644 index 0000000..b4dd111 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s @@ -0,0 +1,140 @@ +/***************************************************************************//** +* \file CyBootAsmGnu.s +* \version 5.70 +* +* \brief Assembly routines for GNU as. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.syntax unified +.text +.thumb +.include "cyfittergnu.inc" + + +/******************************************************************************* +* Function Name: CyDelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32 cycles: number of cycles to delay. +* +* \return +* None +* +*******************************************************************************/ +/* void CyDelayCycles(uint32 cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global CyDelayCycles +.func CyDelayCycles, CyDelayCycles +.type CyDelayCycles, %function +.thumb_func +CyDelayCycles: /* cycles bytes */ + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ +.IFDEF CYIPBLOCK_m0s8cpuss_VERSION + NOP /* 1 2 Loop alignment padding */ +.ELSE + .IFDEF CYIPBLOCK_s8srsslt_VERSION + .IFDEF CYIPBLOCK_m0s8cpussv2_VERSION + .IFDEF CYIPBLOCK_mxusbpd_VERSION + /* Do nothing */ + .ELSE + .IFDEF CYIPBLOCK_m0s8usbpd_VERSION + /* Do nothing */ + .ELSE + NOP /* 1 2 Loop alignment padding */ + .ENDIF + .ENDIF + .ENDIF + .ENDIF + /* Leave loop unaligned */ +.ENDIF +CyDelayCycles_loop: +/* For CM0+ branch instruction takes 2 CPU cycles, for CM0 it takes 3 cycles */ +.IFDEF CYDEV_CM0P_BASE + ADDS r0, r0, #1 /* 1 2 Increment counter */ + SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + BNE CyDelayCycles_loop /* 2 2 2 CPU cycles (if branche is taken)*/ + NOP /* 1 2 Loop alignment padding */ +.ELSE + SUBS r0, r0, #1 /* 1 2 Decrement counter */ + BNE CyDelayCycles_loop /* 3 2 3 CPU cycles (if branche is taken)*/ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ +.ENDIF +CyDelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ +.endfunc + + +/******************************************************************************* +* Function Name: CyEnterCriticalSection +****************************************************************************//** +* +* CyEnterCriticalSection disables interrupts and returns a value indicating +* whether interrupts were previously enabled (the actual value depends on +* whether the device is PSoC 3 or PSoC 5). +* +* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +* with interrupts still enabled. The test and set of the interrupt bits is not +* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +* corrupting processor state, it must be the policy that all interrupt routines +* restore the interrupt enable bits as they were found on entry. +* +* \return +* uint8 +* Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8 CyEnterCriticalSection(void) */ +.global CyEnterCriticalSection +.func CyEnterCriticalSection, CyEnterCriticalSection +.type CyEnterCriticalSection, %function +.thumb_func +CyEnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: CyExitCriticalSection +****************************************************************************//** +* +* CyExitCriticalSection re-enables interrupts if they were enabled before +* CyEnterCriticalSection was called. The argument should be the value returned +* from CyEnterCriticalSection. +* +* \param uint8 savedIntrStatus: +* Saved interrupt status returned by the CyEnterCriticalSection function. +* +* \return +* None +* +*******************************************************************************/ +/* void CyExitCriticalSection(uint8 savedIntrStatus) */ +.global CyExitCriticalSection +.func CyExitCriticalSection, CyExitCriticalSection +.type CyExitCriticalSection, %function +.thumb_func +CyExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmIar.s b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmIar.s new file mode 100644 index 0000000..81aa2af --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmIar.s @@ -0,0 +1,132 @@ +;------------------------------------------------------------------------------- +; \file CyBootAsmIar.s +; \version 5.70 +; +; \brief Assembly routines for IAR Embedded Workbench IDE. +; +;------------------------------------------------------------------------------- +; Copyright 2013-2018, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + SECTION .text:CODE:ROOT(4) + PUBLIC CyDelayCycles + PUBLIC CyEnterCriticalSection + PUBLIC CyExitCriticalSection + THUMB + INCLUDE cyfitter.h + + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + +CyDelayCycles: + ADDS r0, r0, #2 + LSRS r0, r0, #2 + BEQ CyDelayCycles_done + #ifdef CYIPBLOCK_m0s8cpuss_VERSION + NOP ; 1 2 Loop alignment padding + #else + #ifdef CYIPBLOCK_s8srsslt_VERSION + #ifdef CYIPBLOCK_m0s8cpussv2_VERSION + #ifdef CYIPBLOCK_mxusbpd_VERSION + /* Do nothing */ + #else + #ifdef CYIPBLOCK_m0s8usbpd_VERSION + /* Do nothing */ + #else + NOP ; 1 2 Loop alignment padding + #endif + #endif + #endif + #endif + ;Leave loop unaligned + #endif +CyDelayCycles_loop: + #ifdef CYDEV_CM0P_BASE + ADDS r0, r0, #1 + SUBS r0, r0, #2 + BNE CyDelayCycles_loop + NOP + #else + SUBS r0, r0, #1 + BNE CyDelayCycles_loop + NOP + NOP + #endif +CyDelayCycles_done: + BX lr + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled. +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic. Therefore, to avoid corrupting processor state, it must be the policy +; that all interrupt routines restore the interrupt enable bits as they were +; found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) + +CyEnterCriticalSection: + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) + +CyExitCriticalSection: + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + + END + +;Undefine temporary defines +#undef CYIPBLOCK_m0s8cpussv2_VERSION +#undef CYIPBLOCK_m0s8srssv2_VERSION diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmRv.s b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmRv.s new file mode 100644 index 0000000..a1396f0 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyBootAsmRv.s @@ -0,0 +1,136 @@ +;------------------------------------------------------------------------------- +; \file CyBootAsmRv.s +; \version 5.70 +; +; \brief Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + INCLUDE cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + IF :DEF: CYIPBLOCK_m0s8cpuss_VERSION + NOP ; 1 2 Loop alignment padding + ELSE + IF :DEF: CYIPBLOCK_s8srsslt_VERSION + IF :DEF: CYIPBLOCK_m0s8cpussv2_VERSION + IF :DEF: CYIPBLOCK_mxusbpd_VERSION + ; Do nothing + ELSE + IF :DEF: CYIPBLOCK_m0s8usbpd_VERSION + ; Do nothing + ELSE + NOP ; 1 2 Loop alignment padding + ENDIF + ENDIF + ENDIF + ENDIF + ;Leave loop unaligned + ENDIF +CyDelayCycles_loop + ; For CM0+ branch instruction takes 2 CPU cycles, for CM0 it takes 3 cycles + IF :DEF: CYDEV_CM0P_BASE + ADDS r0, r0, #1 ; 1 2 Increment counter + SUBS r0, r0, #2 ; 1 2 Decrement counter by 2 + BNE CyDelayCycles_loop ; 2 2 2 CPU cycles (if branche is taken) + NOP ; 1 2 Loop alignment padding + ELSE + SUBS r0, r0, #1 ; 1 2 Decrement counter + BNE CyDelayCycles_loop ; 3 2 3 CPU cycles (if branche is taken) + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + ENDIF +CyDelayCycles_done + BX lr ; 3 2 + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyFlash.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyFlash.c new file mode 100644 index 0000000..2a1f2ad --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyFlash.c @@ -0,0 +1,803 @@ +/***************************************************************************//** +* \file CyFlash.c +* \version 5.70 +* +* \brief Provides an API for the FLASH. +* +* \note This code is endian agnostic. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + + +/******************************************************************************* +* Cypress identified a defect with the Flash write functionality of the +* PSoC 4000, PSoC 4000U, PSoC 4100, and PSoC 4200 devices. The +* CySysFlashWriteRow() function now checks the data to be written and, if +* necessary, modifies it to have a non-zero checksum. After writing to Flash, +* the modified data is replaced (Flash program) with +* the correct (original) data. +*******************************************************************************/ +#define CY_FLASH_CHECKSUM_WORKAROUND (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + +#if (CY_IP_FM || ((!CY_PSOC4_4000) && CY_IP_SPCIF_SYNCHRONOUS) || (!CY_IP_FM) && CY_PSOC4_4000) + static CY_SYS_FLASH_CLOCK_BACKUP_STRUCT cySysFlashBackup; +#endif /* (CY_IP_FM || ((!CY_PSOC4_4000) && CY_IP_SPCIF_SYNCHRONOUS) || (!CY_IP_FM) && CY_PSOC4_4000) */ + +static cystatus CySysFlashClockBackup(void); +static cystatus CySysFlashClockRestore(void); +#if(CY_IP_SPCIF_SYNCHRONOUS) + static cystatus CySysFlashClockConfig(void); +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + +/******************************************************************************* +* Function Name: CySysFlashWriteRow +****************************************************************************//** +* +* Erases a row of Flash and programs it with the new data. +* +* The IMO must be enabled before calling this function. The operation of the +* flash writing hardware is dependent on the IMO. +* +* For PSoC 4000, PSoC 4100 BLE and PSoC 4200 BLE devices (PSoC 4100 BLE and +* PSoC 4200 BLE devices with 256K of Flash memory are not affected), this API +* will automatically modify the clock settings for the device. Writing to +* flash requires that changes be made to the IMO and HFCLK settings. The +* configuration is restored before returning. This will impact the operation +* of most of the hardware in the device. +* +* For PSoC 4000 devices this API will automatically modify the clock settings +* for the device. Writing to flash requires that changes be made to the IMO +* and HFCLK settings. The configuration is restored before returning. HFCLK +* will have several frequency changes during the operation of this API between +* a minimum frequency of the current IMO frequency divided by 8 and a maximum +* frequency of 12 MHz. This will impact the operation of most of the hardware +* in the device. +* +* \param rowNum The flash row number. The number of the flash rows is defined by +* the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. Refer to the +* device datasheet for the details. +* \note The target flash array is calculated based on the specified flash row. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_FLASH_SIZEOF_ROW macro. Refer to the device datasheet for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashWriteRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA) / sizeof(uint32)]; + uint8 interruptState; + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + uint32 needChecksumWorkaround = 0u; + uint32 savedIndex = 0u; + uint32 savedValue = 0u; + uint32 checksum = 0u; + uint32 bits = 0u; + uint32 i; + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + if ((rowNum < CY_FLASH_NUMBER_ROWS) && (rowData != 0u)) + { + /* Copy data to be written into internal variable */ + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + + for (i = 2u; i < ((CY_FLASH_SIZEOF_ROW / sizeof(uint32)) + 2u); i++) + { + uint32 tmp = parameters[i]; + if (tmp != 0u) + { + checksum += tmp; + bits |= tmp; + savedIndex = i; + } + } + + needChecksumWorkaround = ((checksum == 0u) && (bits != 0u)) ? 1u : 0u; + if (needChecksumWorkaround != 0u) + { + savedValue = parameters[savedIndex]; + parameters[savedIndex] = 0u; + } + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + clkCnfRetValue = CySysFlashClockBackup(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Write Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_WRITE_ROW) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_WRITE_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + + if ((retValue == CYRET_SUCCESS) && (needChecksumWorkaround != 0u)) + { + (void)memset((void *)¶meters[2u], 0, CY_FLASH_SIZEOF_ROW); + parameters[savedIndex] = savedValue; + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Program Row */ + parameters[0u] = + (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_PROGRAM_ROW) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_PROGRAM_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + } + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + clkCnfRetValue = CySysFlashClockRestore(); + + if(clkCnfRetValue != CY_SYS_FLASH_SUCCESS) + { + retValue = clkCnfRetValue; + } + } + + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} + + + +#if (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) +/******************************************************************************* +* Function Name: CySysFlashStartWriteRow +****************************************************************************//** +* +* Initiates a write to a row of Flash. A call to this API is non-blocking. +* Use CySysFlashResumeWriteRow() to resume flash writes and +* CySysFlashGetWriteRowStatus() to ascertain status of the write operation. +* +* The devices require HFCLK to be sourced by 48 MHz IMO during flash write. +* This API will modify IMO configuration; it can be later restored to original +* configuration by calling \ref CySysFlashGetWriteRowStatus(). +* +* \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API +* is complete. The CPUSS_SYSARG register will be reflecting the SRAM address +* during an ongoing non-blocking operation. +* +* \param rowNum The flash row number. The number of the flash rows is defined by +* the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. Refer to the +* device datasheet for the details. +* \note The target flash array is calculated based on the specified flash row. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_FLASH_SIZEOF_ROW macro. Refer to the device datasheet for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashStartWriteRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA) / sizeof(uint32)]; + uint8 interruptState; + +#if(CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if ((rowNum < CY_FLASH_NUMBER_ROWS) && (rowData != 0u)) + { + /* Copy data to be written into internal variable */ + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + clkCnfRetValue = CySysFlashClockBackup(); + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #else + (void)CySysFlashClockBackup(); + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Non-blocking Write Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} + + +/******************************************************************************* +* Function Name: CySysFlashGetWriteRowStatus +****************************************************************************//** +* +* Returns the current status of the flash write operation. +* +** \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API +* is complete. The CPUSS_SYSARG register will be reflecting the SRAM address +* during an ongoing non-blocking operation. +* Calling this API before starting a non-blocking write row operation +* using the \ref CySysFlashStartWriteRow() API will cause improper operation. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashGetWriteRowStatus(void) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + (void) CySysFlashClockRestore(); + + return (retValue); +} + + +/******************************************************************************* +* Function Name: CySysFlashResumeWriteRow +****************************************************************************//** +* +* This API must be called, once the SPC interrupt is triggered to complete the +* non-blocking operation. It is advised not to prolong calling this API for +* more than 25 ms. +* +* The non-blocking write row API \ref CySysFlashStartWriteRow() requires that +* this API be called 3 times to complete the write. This can be done by +* configuring SPCIF interrupt and placing a call to this API. +* +* For CM0 based device, a non-blocking call to program a row of macro 0 +* requires the user to set the CPUSS_CONFIG.VECS_IN_RAM bit so that the +* interrupt vector for the SPC is fetched from the SRAM rather than the FLASH. +* +* For CM0+ based device, if the user wants to keep the vector table in flash +* when performing non-blocking flash write then they need to make sure the +* vector table is placed in the flash macro which is not getting programmed by +* configuring the VTOR register. +* +* \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last Resume API is complete. +* The CPUSS_SYSARG register will be reflecting the SRAM address during an +* ongoing non-blocking operation. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashResumeWriteRow(void) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + static volatile uint32 parameters[1u]; + + /* Resume */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING; + + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + return (retValue); +} + +#endif /* (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) */ + + +/******************************************************************************* +* Function Name: CySysFlashSetWaitCycles +****************************************************************************//** +* +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from Flash. This function must be called before increasing the +* SYSCLK clock frequency. It can optionally be called after lowering SYSCLK +* clock frequency in order to improve the CPU performance. +* +* \param freq The System clock frequency in MHz. +* +* \note Invalid frequency will be ignored in Release mode and the CPU will be +* halted if project is compiled in Debug mode. +* +*******************************************************************************/ +void CySysFlashSetWaitCycles(uint32 freq) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_CPUSS) + + if ( freq <= CY_FLASH_SYSCLK_BOUNDARY_MHZ ) + { + CY_SYS_CLK_SELECT_REG &= (uint32)(~CY_FLASH_WAIT_STATE_EN); + } + else + { + CY_SYS_CLK_SELECT_REG |= CY_FLASH_WAIT_STATE_EN; + } + #else + #if (CY_IP_CPUSS_FLASHC_PRESENT) + /* CY_IP_FM and CY_IP_FS */ + if (freq <= CY_FLASH_CTL_WS_0_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_0_VALUE; + } else + if (freq <= CY_FLASH_CTL_WS_1_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_1_VALUE; + } else + #if (CY_IP_FMLT || CY_IP_FSLT) + if (freq <= CY_FLASH_CTL_WS_2_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_2_VALUE; + } + else + #endif /* (CY_IP_FMLT || CY_IP_FSLT) */ + #endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + { + /* Halt CPU in debug mode if frequency is invalid */ + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_CPUSS) */ + + CyExitCriticalSection(interruptState); +} + + +#if (CY_SFLASH_XTRA_ROWS) +/******************************************************************************* +* Function Name: CySysSFlashWriteUserRow +****************************************************************************//** +* +* Writes data to a row of SFlash user configurable area. +* +* This API is applicable for PSoC 4100 BLE, PSoC 4200 BLE, PSoC 4100M, +* PSoC 4200M, and PSoC 4200L family of devices. +* +* \param rowNum The flash row number. The flash row number. The number of the +* flash rows is defined by the CY_SFLASH_NUMBER_USERROWS macro for the selected +* device. Valid range is 0-3. Refer to the device TRM for details. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_SFLASH_SIZEOF_USERROW macro. Refer to the device TRM for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysSFlashWriteUserRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA)/4u]; + uint8 interruptState; + + + if ((rowNum < CY_SFLASH_NUMBER_USERROWS) && (rowData != 0u)) + { + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + clkCnfRetValue = CySysFlashClockBackup(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Write User Sflash Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) rowNum; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + clkCnfRetValue = CySysFlashClockRestore(); + } + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} +#endif /* (CY_SFLASH_XTRA_ROWS) */ + + +/******************************************************************************* +* Function Name: CySysFlashClockBackup +****************************************************************************//** +* +* Backups the device clock configuration. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockBackup(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; +#if(!CY_IP_FM) + #if !(CY_PSOC4_4000) + #if (CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 parameters[2u]; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + #endif /* !(CY_PSOC4_4000) */ +#endif /* (!CY_IP_FM) */ + +#if(CY_IP_FM) + + /*************************************************************** + * Preserve IMO configuration that could be changed during + * system call execution (Cypress ID #150448). + ***************************************************************/ + cySysFlashBackup.imoConfigReg = CY_SYS_CLK_IMO_CONFIG_REG; + +#else /* (CY_IP_FMLT) */ + + #if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings backup for the PSOC4 4000 devices (the + * corresponding system call is not available). + ***************************************************************************/ + + /*************************************************************************** + * The registers listed below are modified by CySysFlashClockConfig(). + * + * The registers to be saved: + * - CY_SYS_CLK_IMO_CONFIG_REG - IMO enable state. + * - CY_SYS_CLK_SELECT_REG - HFCLK source, divider, pump source. Save + * entire register as it can be directly + * written on restore (no special + * requirements). + * - CY_SYS_CLK_IMO_SELECT_REG - Save IMO frequency. + * + * The registers not to be saved: + * - CY_SYS_CLK_IMO_TRIM1_REG - No need to save. Function of frequency. + * Restored by CySysClkWriteImoFreq(). + * - CY_SYS_CLK_IMO_TRIM3_REG - No need to save. Function of frequency. + * Restored by CySysClkWriteImoFreq(). + * - REG_CPUSS_FLASH_CTL - Flash wait cycles. Unmodified due to system + * clock 16 MHz limit. + ***************************************************************************/ + + cySysFlashBackup.clkSelectReg = CY_SYS_CLK_SELECT_REG; + cySysFlashBackup.clkImoEna = CY_SYS_CLK_IMO_CONFIG_REG & CY_SYS_CLK_IMO_CONFIG_ENABLE; + cySysFlashBackup.clkImoFreq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ + (CY_SYS_CLK_IMO_SELECT_REG << 2u); + + #else + + #if (CY_IP_SPCIF_SYNCHRONOUS) + /* FM-Lite Clock Backup System Call */ + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_BACKUP) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_BACKUP; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ + + return (retValue); +} + + +#if(CY_IP_SPCIF_SYNCHRONOUS) +/******************************************************************************* +* Function Name: CySysFlashClockConfig +****************************************************************************//** +* +* Configures the device clocks for the flash writing. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockConfig(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; + + /*************************************************************************** + * The FM-Lite IP uses the IMO at 48MHz for the pump clock and SPC timer + * clock. The PUMP_SEL and HF clock must be set to IMO before calling Flash + * write or erase operation. + ***************************************************************************/ +#if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings setup for the PSOC4 4000 devices (the + * corresponding system call is not reliable): + * - The IMO frequency should be 48 MHz + * - The IMO should be source for the HFCLK + * - The IMO should be the source for the charge pump clock + * + * Note The structure members used below are initialized by + * the CySysFlashClockBackup() function. + ***************************************************************************/ + if ((cySysFlashBackup.clkImoFreq != 48u) || + ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCLK_IMO) || + (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELECT_PUMP_SEL_MASK) != + CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + { + /*********************************************************************** + Set HFCLK divider to divide-by-4 to ensure that System clock frequency + * is within the valid limit (16 MHz for the PSoC4 4000). + ***********************************************************************/ + CySysClkWriteHfclkDiv(CY_SYS_CLK_HFCLK_DIV_4); + + /* The IMO frequency should be 48 MHz */ + if (cySysFlashBackup.clkImoFreq != 48u) + { + CySysClkWriteImoFreq(48u); + } + CySysClkImoStart(); + + /* The IMO should be source for the HFCLK */ + CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO); + + /* The IMO should be the source for the charge pump clock */ + CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & + ((uint32)~(uint32)(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT))) | + ((uint32)((uint32)1u << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT)); + } + +#else + + /* FM-Lite Clock Configuration */ + CY_FLASH_CPUSS_SYSARG_REG = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_CONFIG) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_CONFIG; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + +#endif /* (CY_PSOC4_4000) */ + + return (retValue); +} +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + +/******************************************************************************* +* Function Name: CySysFlashClockRestore +****************************************************************************//** +* +* Restores the device clock configuration. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockRestore(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; +#if(!CY_IP_FM) + #if !(CY_PSOC4_4000) + #if (CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 parameters[2u]; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + #endif /* !(CY_PSOC4_4000) */ +#endif /* (!CY_IP_FM) */ + +#if(CY_IP_FM) + + /*************************************************************** + * Restore IMO configuration that could be changed during + * system call execution (Cypress ID #150448). + ***************************************************************/ + CY_SYS_CLK_IMO_CONFIG_REG = cySysFlashBackup.imoConfigReg; + +#else + + #if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings restore for the PSOC4 4000 devices (the + * corresponding system call is not available). + ***************************************************************************/ + + /* Restore clock settings */ + if ((cySysFlashBackup.clkImoFreq != 48u) || + ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCLK_IMO) || + (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELECT_PUMP_SEL_MASK) != + CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + { + /* Restore IMO frequency if needed */ + if (cySysFlashBackup.clkImoFreq != 48u) + { + CySysClkWriteImoFreq(cySysFlashBackup.clkImoFreq); + } + + /* Restore HFCLK clock source */ + CySysClkWriteHfclkDirect(cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + + /* Restore HFCLK divider and source for pump */ + CY_SYS_CLK_SELECT_REG = cySysFlashBackup.clkSelectReg; + + /* Stop IMO if needed */ + if (0u == cySysFlashBackup.clkImoEna) + { + CySysClkImoStop(); + } + } + + #else + + #if (CY_IP_SPCIF_SYNCHRONOUS) + /* FM-Lite Clock Restore */ + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ + + return (retValue); +} + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyFlash.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyFlash.h new file mode 100644 index 0000000..0ea8ecf --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyFlash.h @@ -0,0 +1,293 @@ +/***************************************************************************//** +* \file CyFlash.h +* \version 5.70 +* +* \brief Provides the function definitions for the FLASH. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "CyLib.h" + +/** +* \addtogroup group_flash + +\brief Flash memory in PSoC devices provides nonvolatile storage for user +firmware, user configuration data, and bulk data storage. See the device +datasheet and TRM for more information on Flash architecture. + +\section section_flash_protection Flash Protection +PSoC devices include a flexible flash-protection model that prevents access +and visibility to on-chip flash memory. The device offers the ability to +assign one of two protection levels to each row of flash: unprotected and +full protection. The required protection level can be selected using the Flash +Security tab of the PSoC Creator DWR file. Flash protection levels can only be +changed by performing a complete flash erase. The Flash programming APIs will +fail to write a row with Full Protection level. For more information on +protection model, refer to the Flash Security Editor section in the PSoC +Creator Help. + +\section section_flash_working_with Working with Flash +Flash programming operations are implemented as system calls. System calls are +executed out of SROM in the privileged mode of operation. Users have no access +to read or modify the SROM code. The CPU requests the system call by writing +the function opcode and parameters to the System Performance Controller (SPC) +input registers, and then requesting the SROM to execute the function. Based +on the function opcode, the SPC executes the corresponding system call from +SROM and updates the SPC status register. The CPU should read this status +register for the pass/fail result of the function execution. As part of +function execution, the code in SROM interacts with the SPC interface to do +the actual flash programming operations. + +It can take as many as 20 milliseconds to write to flash. During this time, +the device should not be reset, or unexpected changes may be made to portions +of the flash. Reset sources include XRES pin, software reset, and watchdog. +Make sure that these are not inadvertently activated. Also, the low voltage +detect circuits should be configured to generate an interrupt instead of a +reset. + +The flash can be read either by the cache controller or the SPC. Flash write +can be performed only by the SPC. Both the SPC and cache cannot simultaneously +access flash memory. If the cache controller tries to access flash at the same +time as the SPC, then it must wait until the SPC completes its flash access +operation. The CPU, which accesses the flash memory through the cache +controller, is therefore also stalled in this circumstance. If a CPU code +fetch has to be done from flash memory due to a cache miss condition, then the +cache would have to wait until the SPC completes the flash write operation. +Thus the CPU code execution will also be halted till the flash write is +complete. Flash is directly mapped into memory space and can be read directly. + +\note Flash write operations on PSoC 4000 devices modify the clock settings of +the device during the period of the write operation. +Refer to the \ref CySysFlashWriteRow() API documentation for details. + +* @{ +*/ + +uint32 CySysFlashWriteRow (uint32 rowNum, const uint8 rowData[]); +#if (CY_SFLASH_XTRA_ROWS) + uint32 CySysSFlashWriteUserRow (uint32 rowNum, const uint8 rowData[]); +#endif /* (CY_SFLASH_XTRA_ROWS) */ +void CySysFlashSetWaitCycles (uint32 freq); + +#if (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) + uint32 CySysFlashStartWriteRow(uint32 rowNum, const uint8 rowData[]); + uint32 CySysFlashGetWriteRowStatus(void); + uint32 CySysFlashResumeWriteRow(void); +#endif /* (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) */ + +/** @} group_flash */ + + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) /**< The base pointer of the Flash memory.*/ +#define CY_FLASH_SIZE (CYDEV_FLASH_SIZE) /**< The size of the Flash memory. */ +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE) /**< The size of Flash array. */ +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) /**< The size of the Flash row. */ +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) /**< The number of Flash row. */ +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) /**< The number of Flash arrays. */ + +#if (CY_SFLASH_XTRA_ROWS) + #define CY_SFLASH_USERBASE (CYREG_SFLASH_MACRO_0_FREE_SFLASH0) /**< The base pointer of the user SFlash memory. */ + #define CY_SFLASH_SIZE (CYDEV_SFLASH_SIZE) /**< The size of the SFlash memory. */ + #define CY_SFLASH_SIZEOF_USERROW (CYDEV_FLS_ROW_SIZE) /**< The size of the SFlash row. */ + #define CY_SFLASH_NUMBER_USERROWS (4u) /**< The number of SFlash row. */ +#endif /* (CY_SFLASH_XTRA_ROWS) */ + + +/** +* \addtogroup group_flash_status_codes Flash API status codes +* \ingroup group_flash +* @{ +*/ + +/** Completed successfully. */ +#define CY_SYS_FLASH_SUCCESS (0x00u) +/** Specified flash row address is invalid. The row id or byte address provided is outside of the available memory. */ +#define CY_SYS_FLASH_INVALID_ADDR (0x04u) +/** Specified flash row is protected. */ +#define CY_SYS_FLASH_PROTECTED (0x05u) +/** Resume Completed. All non-blocking calls have completed. The resume/abort function cannot be called until the +next non-blocking. */ +#define CY_SYS_FLASH_RESUME_COMPLETED (0x07u) +/** \brief Pending Resume. A non-blocking was initiated and must be completed by calling the resume API, before any other +function may be called. */ +#define CY_SYS_FLASH_PENDING_RESUME (0x08u) +/** System Call Still In Progress. A resume or non-blocking is still in progress. The SPC ISR must fire before +attempting the next resume. */ +#define CY_SYS_FLASH_CALL_IN_PROGRESS (0x09u) +/** Invalid Flash Clock. Products using CY_IP_SRSSLT must set the IMO to 48MHz and the HF clock source to the IMO clock +before Write/Erase operations. */ +#define CY_SYS_FLASH_INVALID_CLOCK (0x12u) +/** @} group_flash_status_codes */ + +#define CY_SYS_SFLASH_SUCCESS (CY_SYS_FLASH_SUCCESS) +#define CY_SYS_SFLASH_INVALID_ADDR (CY_SYS_FLASH_INVALID_ADDR) +#define CY_SYS_SFLASH_PROTECTED (CY_SYS_FLASH_PROTECTED) + +/* CySysFlashSetWaitCycles() - implementation definitions */ +#define CY_FLASH_WAIT_STATE_EN (( uint32 )(( uint32 )0x01u << 18u)) +#define CY_FLASH_SYSCLK_BOUNDARY_MHZ (24u) +#if (CY_IP_CPUSS_FLASHC_PRESENT) + /* CySysFlashSetWaitCycles() */ + #if(CY_IP_FM || CY_IP_FS) + #define CY_FLASH_CTL_WS_0_FREQ_MIN (0u) + #define CY_FLASH_CTL_WS_0_FREQ_MAX (24u) + + #define CY_FLASH_CTL_WS_1_FREQ_MIN (24u) + #define CY_FLASH_CTL_WS_1_FREQ_MAX (48u) + #else /* (CY_IP_FMLT || CY_IP_FSLT) */ + #define CY_FLASH_CTL_WS_0_FREQ_MIN (0u) + #define CY_FLASH_CTL_WS_0_FREQ_MAX (16u) + + #define CY_FLASH_CTL_WS_1_FREQ_MIN (16u) + #define CY_FLASH_CTL_WS_1_FREQ_MAX (32u) + + #define CY_FLASH_CTL_WS_2_FREQ_MIN (32u) + #define CY_FLASH_CTL_WS_2_FREQ_MAX (48u) + #endif /* (CY_IP_FM || CY_IP_FS) */ + + #define CY_FLASH_CTL_WS_MASK ((uint32) 0x03u) + #define CY_FLASH_CTL_WS_0_VALUE (0x00u) + #define CY_FLASH_CTL_WS_1_VALUE (0x01u) + #if(CY_IP_FMLT || CY_IP_FSLT) + #define CY_FLASH_CTL_WS_2_VALUE (0x02u) + #endif /* (CY_IP_FMLT || CY_IP_FSLT) */ +#endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + + +#define CY_FLASH_KEY_ONE (0xB6u) +#define CY_FLASH_KEY_TWO(x) ((uint32) (((uint16) 0xD3u) + ((uint16) (x)))) + +#define CY_FLASH_PAGE_LATCH_START_ADDR ((uint32) (0x00u)) +#define CY_FLASH_ROW_NUM_MASK (0x100u) +#define CY_FLASH_CPUSS_REQ_START (( uint32 )(( uint32 )0x1u << 31u)) + +/* Opcodes */ +#define CY_FLASH_API_OPCODE_LOAD (0x04u) +#define CY_FLASH_API_OPCODE_WRITE_ROW (0x05u) +#define CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW (0x07u) +#define CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING (0x09u) + +#define CY_FLASH_API_OPCODE_PROGRAM_ROW (0x06u) +#define CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW (0x18u) + +#define CY_FLASH_API_OPCODE_CLK_CONFIG (0x15u) +#define CY_FLASH_API_OPCODE_CLK_BACKUP (0x16u) +#define CY_FLASH_API_OPCODE_CLK_RESTORE (0x17u) + +/* SROM API parameters offsets */ +#define CY_FLASH_PARAM_KEY_TWO_OFFSET (8u) +#define CY_FLASH_PARAM_ADDR_OFFSET (16u) +#define CY_FLASH_PARAM_MACRO_SEL_OFFSET (24u) + +#if (CY_IP_FLASH_MACROS == 2u) + /* Macro #0: rows 0x00-0x1ff, Macro #1: rows 0x200-0x3ff */ + #define CY_FLASH_GET_MACRO_FROM_ROW(row) ((uint32)(((row) > 0x1ffu) ? 1u : 0u)) +#else + /* Only macro # 0 is available */ + #define CY_FLASH_GET_MACRO_FROM_ROW(row) ((uint32)(((row) != 0u) ? 0u : 0u)) +#endif /* (CY_IP_FLASH_MACROS == 2u) */ + +#if(CY_IP_FMLT) + /* SROM size greater than 4k */ + #define CY_FLASH_IS_BACKUP_RESTORE (CYDEV_SROM_SIZE > 0x00001000u) +#endif /* (CY_IP_FMLT) */ + + +#if(CY_IP_SRSSV2) + #define CY_FLASH_CLOCK_BACKUP_SIZE (4u) +#else /* CY_IP_SRSSLT */ + #define CY_FLASH_CLOCK_BACKUP_SIZE (6u) +#endif /* (CY_IP_SRSSV2) */ + + +typedef struct cySysFlashClockBackupStruct +{ +#if(CY_IP_FM) + uint32 imoConfigReg; +#else /* (CY_IP_FMLT) */ + #if (CY_PSOC4_4000) + uint32 clkSelectReg; + uint32 clkImoEna; + uint32 clkImoFreq; + #else + + #if(CY_IP_SRSSV2) + uint32 clkImoPump; + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_SPCIF_SYNCHRONOUS) + uint32 clockSettings[CY_FLASH_CLOCK_BACKUP_SIZE]; /* FM-Lite Clock Backup */ + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ +} CY_SYS_FLASH_CLOCK_BACKUP_STRUCT; + + +/* SYSARG control register */ +#define CY_FLASH_CPUSS_SYSARG_REG (*(reg32 *) CYREG_CPUSS_SYSARG) +#define CY_FLASH_CPUSS_SYSARG_PTR ( (reg32 *) CYREG_CPUSS_SYSARG) + +/* SYSCALL control register */ +#define CY_FLASH_CPUSS_SYSREQ_REG (*(reg32 *) CYREG_CPUSS_SYSREQ) +#define CY_FLASH_CPUSS_SYSREQ_PTR ( (reg32 *) CYREG_CPUSS_SYSREQ) + +#if (CY_IP_CPUSS_FLASHC_PRESENT) + /* SYSARG control register */ + #define CY_FLASH_CTL_REG (*(reg32 *) CYREG_CPUSS_FLASH_CTL) + #define CY_FLASH_CTL_PTR ( (reg32 *) CYREG_CPUSS_FLASH_CTL) +#endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + + +#define CY_FLASH_API_RETURN (((CY_FLASH_CPUSS_SYSARG_REG & 0xF0000000u) == 0xF0000000u) ? \ + (CY_FLASH_CPUSS_SYSARG_REG & 0x000000FFu) : \ + (((CY_FLASH_CPUSS_SYSARG_REG & 0xF0000000u) == 0xA0000000u) ? \ + CYRET_SUCCESS : (CY_FLASH_CPUSS_SYSARG_REG & 0x000000FFu))) + + +/******************************************************************************* +* Thne following code is OBSOLETE and must not be used starting with cy_boot +* 4.20. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_FLASH_SRAM_ROM_KEY1 (( uint32 )0x00u) +#define CY_FLASH_SRAM_ROM_PARAM2 (CY_FLASH_SRAM_ROM_KEY1 + 0x04u) +#define CY_FLASH_SRAM_ROM_DATA (CY_FLASH_SRAM_ROM_KEY1 + 0x08u) + +#define CY_FLASH_SROM_CMD_RETURN_MASK (0xF0000000u) +#define CY_FLASH_SROM_CMD_RETURN_SUCC (0xA0000000u) +#define CY_FLASH_SROM_KEY1 (( uint32 )0xB6u) +#define CY_FLASH_SROM_KEY2_LOAD (( uint32 )0xD7u) +#define CY_FLASH_SROM_KEY2_WRITE (( uint32 )0xD8u) +#define CY_FLASH_SROM_LOAD_CMD ((CY_FLASH_SROM_KEY2_LOAD << 8u) | CY_FLASH_SROM_KEY1) +#define CY_FLASH_LOAD_BYTE_OPCODE (( uint32 )0x04u) +#define CY_FLASH_WRITE_ROW_OPCODE (( uint32 )0x05u) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.c new file mode 100644 index 0000000..acd01f7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.c @@ -0,0 +1,3230 @@ +/***************************************************************************//** +* \file .c +* \version 1.20 +* +* \brief +* This file provides the source code for configuring watchdog timers WDTs, +* low frequency clocks (LFCLK) and the Real-time Clock (RTC) component in +* PSoC Creator for the PSoC 4 families. +* +******************************************************************************** +* \copyright +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "CyLFClk.h" +#include "CyLib.h" + +#if (CY_IP_WCO && CY_IP_SRSSV2) + static uint32 CySysClkGetLfclkSource(void); +#endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + /* Default Ilo Trim Register value for ILO trimming*/ + static volatile uint16 defaultIloTrimRegValue = CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE; +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + +#if(CY_IP_SRSSV2) + /* CySysClkLfclkPosedgeCatch() / CySysClkLfclkPosedgeRestore() */ + static uint32 lfclkPosedgeWdtCounter0Enabled = 0u; + static uint32 lfclkPosedgeWdtCounter0Mode = CY_SYS_WDT_MODE_NONE; + + static volatile uint32 disableServicedIsr = 0uL; + static volatile uint32 wdtIsrMask = CY_SYS_WDT_COUNTER0_INT |\ + CY_SYS_WDT_COUNTER1_INT |\ + CY_SYS_WDT_COUNTER2_INT; + + static const uint32 counterIntMaskTbl[CY_WDT_NUM_OF_WDT] = {CY_SYS_WDT_COUNTER0_INT, + CY_SYS_WDT_COUNTER1_INT, + CY_SYS_WDT_COUNTER2_INT}; + + static void CySysClkLfclkPosedgeCatch(void); + static void CySysClkLfclkPosedgeRestore(void); + + static uint32 CySysWdtLocked(void); + static uint32 CySysClkIloEnabled(void); +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + static uint32 CySysClkGetTimerSource(void); + static volatile uint32 disableTimerServicedIsr = 0uL; + static volatile uint32 timerIsrMask = CY_SYS_TIMER0_INT |\ + CY_SYS_TIMER1_INT |\ + CY_SYS_TIMER2_INT; + + static const uint32 counterTimerIntMaskTbl[CY_SYS_NUM_OF_TIMERS] = {CY_SYS_TIMER0_INT, + CY_SYS_TIMER1_INT, + CY_SYS_TIMER2_INT}; + + static cyTimerCallback cySysTimerCallback[CY_SYS_NUM_OF_TIMERS] = {(void *)0, (void *)0, (void *)0}; +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_DWT_EN) */ + +#if(CY_IP_SRSSV2) + static cyWdtCallback cySysWdtCallback[CY_WDT_NUM_OF_WDT] = {(void *)0, (void *)0, (void *)0}; +#else + static cyWdtCallback cySysWdtCallback = (void *)0; +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Function Name: CySysClkIloStart +****************************************************************************//** +* \brief +* Enables ILO. +* +* Refer to the device datasheet for the ILO startup time. +* +*******************************************************************************/ +void CySysClkIloStart(void) +{ + CY_SYS_CLK_ILO_CONFIG_REG |= CY_SYS_CLK_ILO_CONFIG_ENABLE; +} + + +/******************************************************************************* +* Function Name: CySysClkIloStop +****************************************************************************//** +* \brief +* Disables the ILO. +* +* This function has no effect if WDT is locked (CySysWdtLock() is +* called). Call CySysWdtUnlock() to unlock WDT and stop ILO. +* +* PSoC 4100 / PSoC 4200: Note that ILO is required for WDT's operation. +* +* PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / +* PSoC 4200M: +* Stopping ILO affects the peripheral clocked by LFCLK, if +* LFCLK is configured to be sourced by ILO. +* +* If the ILO is disabled, all blocks run by ILO will stop functioning. +* +*******************************************************************************/ +void CySysClkIloStop(void) +{ + #if(CY_IP_SRSSV2) + uint8 interruptState; + + /* Do nothing if WDT is locked or ILO is disabled */ + if (0u == CySysWdtLocked()) + { + if (0u != CySysClkIloEnabled()) + { + + #if (CY_IP_WCO) + if (CY_SYS_CLK_LFCLK_SRC_ILO == CySysClkGetLfclkSource()) + { + #endif /* (CY_IP_WCO) */ + + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + + #if (CY_IP_WCO) + } + else /* Safe to disable - shortened pulse does not impact peripheral */ + { + CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + } + #endif /* (CY_IP_WCO) */ + + } + } + #else + CY_SYS_CLK_ILO_CONFIG_REG &= ( uint32 ) ( ~( uint32 )CY_SYS_CLK_ILO_CONFIG_ENABLE); + #endif /* (CY_IP_SRSSV2) */ +} + + +/****************************************************************************** +* Function Name: CySysClkIloStartMeasurement +***************************************************************************//** +* \brief +* Starts the ILO accuracy measurement. +* +* This function is non-blocking and needs to be called before using the +* CySysClkIloTrim() and CySysClkIloCompensate() API. +* +* This API configures measurement counters to be sourced by SysClk (Counter 1) +* and ILO (Counter 2). +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* In addition, this API stores the factory ILO trim settings on the first call +* after reset. This stored factory setting is used by the +* CySysClkIloRestoreFactoryTrim() API to restore the ILO factory trim. +* Hence, it is important to call this API before restoring the ILO +* factory trim settings. +* +******************************************************************************/ +void CySysClkIloStartMeasurement(void) +{ +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + static uint8 iloTrimTrig = 0u; + + /* Write default ILO trim value while ILO starting ( Cypress ID 225244 )*/ + if (0u == iloTrimTrig) + { + defaultIloTrimRegValue = ((uint8)(CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK)); + iloTrimTrig = 1u; + } +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + + /* Configure measurement counters to source by SysClk (Counter 1) and ILO (Counter 2)*/ + CY_SYS_CLK_DFT_REG = (CY_SYS_CLK_DFT_REG & (uint32) ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK) | + CY_SYS_CLK_SEL_ILO_DFT_SOURCE; + + CY_SYS_TST_DDFT_CTRL_REG = (CY_SYS_TST_DDFT_CTRL_REG & (uint32) ~ CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK) | + CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1; +} + + +/****************************************************************************** +* Function Name: CySysClkIloStopMeasurement +***************************************************************************//** +* \brief +* Stops the ILO accuracy measurement. +* +* Calling this function immediately stops the the ILO frequency measurement. +* This function should be called before placing the device to deepsleep, if +* CySysClkIloStartMeasurement() API was called before. +* +******************************************************************************/ +void CySysClkIloStopMeasurement(void) +{ + /* Set default configurations in 11...8 DFT register bits to zero */ + CY_SYS_CLK_DFT_REG &= ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK; + #if(CY_IP_SRSSLT) + CY_SYS_TST_DDFT_CTRL_REG &= ((uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + #endif /* (CY_IP_SRSSLT) */ +} + + +/****************************************************************************** +* Function Name: CySysClkIloCompensate +***************************************************************************//** +* \brief +* This API measures the current ILO accuracy. +* +* Basing on the measured frequency the required number of ILO cycles for a +* given delay (in microseconds) is obtained. The desired delay that needs to +* be compensated is passed through the desiredDelay parameter. The compensated +* cycle count is returned through the compesatedCycles pointer. +* The compensated ILO cycles can then be used to define the WDT period value, +* effectively compensating for the ILO inaccuracy and allowing a more +* accurate WDT interrupt generation. +* +* CySysClkIloStartMeasurement() API should be called prior to calling this API. +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* \note If the System clock frequency is changed in runtime, the CyDelayFreq() +* with the appropriate parameter (Frequency of bus clock in Hertz) should be +* called before calling a next CySysClkIloCompensate(). +* +* \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS. +* +* \param desiredDelay Required delay in microseconds. +* +* \param *compensatedCycles The pointer to the variable in which the required +* number of ILO cycles for the given delay will be returned. +* +* \details +* The value returned in *compensatedCycles pointer is not valid until the +* function returns CYRET_SUCCESS. +* +* The desiredDelay parameter value should be in next range:
From 100 to +* 2 000 000 microseconds for PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog +* Coprocessor devices.
From 100 to 4 000 000 000 microseconds for +* PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / +* PSoC 4200L / PSoC 4100M /PSoC 4200M devices. +* +* \return CYRET_SUCCESS - The compensation process is complete and the +* compensated cycles value is returned in the compensatedCycles pointer. +* +* \return CYRET_STARTED - Indicates measurement is in progress. It is +* strongly recommended to do not make pauses between API calling. The +* function should be called repeatedly until the API returns CYRET_SUCCESS. +* +* \return CYRET_INVALID_STATE - Indicates that measurement not started. +* The user should call CySysClkIloStartMeasurement() API before calling +* this API. +* +* \note For a correct WDT or DeepSleep Timers functioning with ILO compensating +* the CySysClkIloCompensate() should be called before WDT or DeepSleep Timers +* enabling. +* +*******************************************************************************/ +cystatus CySysClkIloCompensate(uint32 desiredDelay , uint32* compensatedCycles) +{ + uint32 iloCompensatedCycles; + uint32 desiredDelayInCounts; + static uint32 compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + uint32 checkStatus; + cystatus returnStatus; + + checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + + /* Check if CySysStartMeasurement was called before */ + if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + (CY_SYS_CLK_MAX_DELAY_US >= desiredDelay) && + (CY_SYS_CLK_MIN_DELAY_US <= desiredDelay) && + (compensatedCycles != NULL)) + { + if(CY_SYS_CLK_TRIM_OR_COMP_FINISHED != compensateRunningStatus) + { + /* Wait until counter 1 stopped counting and after it calculate compensated cycles */ + if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + if (0u != CY_SYS_CNT_REG2_REG) + { + /* Calculate required number of ILO cycles for given delay */ + #if(CY_IP_SRSSV2) + if (CY_SYS_CLK_DELAY_COUNTS_LIMIT < desiredDelay) + { + desiredDelayInCounts = (desiredDelay / CY_SYS_CLK_ILO_PERIOD); + iloCompensatedCycles = + (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) >> + CY_SYS_CLK_ILO_FREQ_2MSB) * (desiredDelayInCounts / CY_SYS_CLK_ILO_FREQ_3LSB); + } + else + { + desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + + CY_SYS_CLK_HALF_OF_CLOCK) / CY_SYS_CLK_ILO_PERIOD_PPH; + + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) * + desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED_FREQ_HZ; + } + #else /* (CY_IP_SRSSLT) */ + desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + CY_SYS_CLK_HALF_OF_CLOCK) / + CY_SYS_CLK_ILO_PERIOD_PPH; + if(CY_SYS_CLK_MAX_LITE_NUMBER < desiredDelayInCounts) + { + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> + CY_SYS_CLK_SYS_CLK_DEVIDER)) / CY_SYS_CLK_ILO_FREQ_2MSB) * + (desiredDelayInCounts / CY_SYS_CLK_ILO_FREQ_3LSB); + } + else + { + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) * + desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED_FREQ_HZ; + } + #endif /* (CY_IP_SRSSV2) */ + + *compensatedCycles = iloCompensatedCycles; + compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + returnStatus = CYRET_SUCCESS; + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + } + else + { + returnStatus = CYRET_STARTED; + } + } + else + { + /* Reload CNTR 1 count value for next measurement cycle*/ + CY_SYS_CNT_REG1_REG = (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER); + compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + returnStatus = CYRET_STARTED; + } + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + + return (returnStatus); +} + + +#if(CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysClkIloEnabled + ****************************************************************************//** + * + * \internal + * Reports the ILO enable state. + * + * \return + * 1 if ILO is enabled, and 0 if ILO is disabled. + * + * \endinternal + ********************************************************************************/ + static uint32 CySysClkIloEnabled(void) + { + /* Prohibits writing to WDT registers and ILO/WCO registers when not equal to 0 */ + return ((0u != (CY_SYS_CLK_ILO_CONFIG_REG & (uint32)(CY_SYS_CLK_ILO_CONFIG_ENABLE))) ? + (uint32) 1u : + (uint32) 0u); + } +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) +/******************************************************************************** +* Function Name: CySysClkIloTrim +*****************************************************************************//** +* \brief +* The API trims the ILO frequency to +/- 10% accuracy range using accurate +* SysClk. +* +* The API can be blocking or non-blocking depending on the value of the mode +* parameter passed. The accuracy of ILO after trimming in parts per thousand +* is returned through the iloAccuracyInPPT pointer. A positive number indicates +* that the ILO is running fast and a negative number indicates that the ILO is +* running slowly. This error is relative to the error in the reference clock +* (SysClk), so the absolute error will be higher and depends on the accuracy +* of the reference. +* +* The CySysClkIloStartMeasurement() API should be called prior to calling this +* API. Otherwise it will return CYRET_INVALID_STATE as the measurement was not +* started. +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* \note If System clock frequency is changed in runtime, the CyDelayFreq() +* with the appropriate parameter (Frequency of bus clock in Hertz) should be +* called before next CySysClkIloCompensate() usage. +* +* \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS +* or CYRET_TIMEOUT. +* +* Available for all PSoC 4 devices with ILO trim capability. This excludes +* PSoC 4000 / PSoC 4100 / PSoC 4200 / PSoC 4000S / PSoC 4100S / PSoC +* Analog Coprocessor devices. +* +* \param mode +* CY_SYS_CLK_BLOCKING - The function does not return until the ILO is +* within +/-10% accuracy range or time out has occurred.
+* CY_SYS_CLK_NON_BLOCKING - The function returns immediately after +* performing a single iteration of the trim process. The function should be +* called repeatedly until the trimming is completed successfully. +* +* \param *iloAccuracyInPPT Pointer to an integer in which the trimmed ILO +* accuracy will be returned. +* +* \details The value returned in *iloAccuracyInPPT pointer is not valid +* until the function returns CYRET_SUCCESS. ILO accuracy in PPT is given by: +* +* IloAccuracyInPPT = ((MeasuredIloFreq - DesiredIloFreq) * +* CY_SYS_CLK_PERTHOUSAND) / DesiredIloFreq); +* +* DesiredIloFreq = 32000, CY_SYS_CLK_PERTHOUSAND = 1000; +* +* \return CYRET_SUCCESS - Indicates trimming is complete. This value indicates +* trimming is successful and iloAccuracyInPPT is within +/- 10%. +* +* \return CYRET_STARTED - Indicates measurement is in progress. This is applicable +* only for non-blocking mode. +* +* \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. You should +* call CySysClkIloStartMeasurement() before calling this API. +* +* \return CYRET_TIMEOUT - Indicates trimming was unsuccessful. This is applicable +* only for blocking mode. Timeout means the trimming was tried 5 times without +* success (i.e. ILO accuracy > +/- 10%). The user can call the API again for +* another try or wait for some time before calling it again (to let the system +* to settle to another operating point change in temperature etc.) and continue +* using the previous trim value till the next call. +* +**********************************************************************************/ +cystatus CySysClkIloTrim(uint32 mode, int32* iloAccuracyInPPT) +{ + uint32 timeOutClocks = CY_SYS_CLK_TIMEOUT; + uint32 waitUntilCntr1Stops; + static uint32 trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + uint32 checkStatus; + cystatus returnStatus; + + checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + + /* Check if DFT and CTRL registers were configures in CySysStartMeasurement*/ + if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + (iloAccuracyInPPT != NULL)) + { + if(CY_SYS_CLK_BLOCKING == mode) + { + waitUntilCntr1Stops = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + do + { + /* Reload CNTR 1 count value for measuring cycle*/ + CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + + /* Wait until counter CNTR 1 will finish down-counting */ + while (0u == (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + waitUntilCntr1Stops--; + if (0u == waitUntilCntr1Stops) + { + break; + } + } + trimRunningStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + timeOutClocks--; + + /* Untill ILO accuracy will be in range less than +/- 10% or timeout occurs*/ + } while((CYRET_SUCCESS != trimRunningStatus) && + (CYRET_INVALID_STATE != trimRunningStatus) && + (0u != timeOutClocks)); + + if (CYRET_SUCCESS == trimRunningStatus) + { + returnStatus = CYRET_SUCCESS; + } + else + { + if(0u == timeOutClocks) + { + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + returnStatus = CYRET_TIMEOUT; + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + } + } + /* Non - blocking mode */ + else + { + if (CY_SYS_CLK_TRIM_OR_COMP_FINISHED != trimRunningStatus) + { + /* Checking if the counter CNTR 1 finished down-counting */ + if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + returnStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + } + else + { + returnStatus = CYRET_STARTED; + } + } + else + { + /* Reload CNTR 1 count value for next measuring */ + CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + returnStatus = CYRET_STARTED; + } + } + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + + return (returnStatus); +} + + +/******************************************************************************** +* Function Name: CySysClkIloUpdateTrimReg +********************************************************************************* +* +* \internal +* Function calculates ILO accuracy and check is error range is higher than +* +/- 10%. If Measured frequency is higher than +/- 10% function updates +* ILO Trim register. +* +* \param +* iloAccuracyInPPT Pointer to an integer in which the trimmed ILO +* accuracy will be returned. The value returned in this pointer is not valid +* until the function returns CYRET_SUCCESS. If ILO frequency error is lower +* than +/- 10% then the value returned in this pointer will be updated. +* +* \return CYRET_SUCCESS - Indicates that ILO frequency error is lower than +* +/- 10% and no actions are required. +* +* \return CYRET_STARTED - Indicates that ILO frequency error is higher than +* +/- 10% and ILO Trim register was updated. +* +* \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. +* +* Post #1 - To obtain 10% ILO accuracy the calculated accuracy should be equal +* CY_SYS_CLK_ERROR_RANGE = 5.6%. Error value should take to account IMO error of +* +/-2% (+/-0.64kHz), trim step of 2.36kHz (+/-1.18kHz) and error while ILO +* frequency measuring. +* +* \endinternal +* +**********************************************************************************/ +cystatus CySysClkIloUpdateTrimReg(int32* iloAccuracyInPPT) +{ + uint32 measuredIloFreq; + uint32 currentIloTrimValue; + int32 iloAccuracyValue; + int32 trimStep; + cystatus errorRangeStatus; + + if(0u != CY_SYS_CNT_REG2_REG) + { + measuredIloFreq = (CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER); + + /* Calculate value of error in PPT according to formula - + * ((measuredIlofrequency - iloDesired frequency) * 1000 / iloDesired frequency) */ + iloAccuracyValue = (((int32) measuredIloFreq - (int32) CY_SYS_CLK_ILO_DESIRED_FREQ_HZ) * \ + ((int32) CY_SYS_CLK_PERTHOUSAND)) / ((int32) CY_SYS_CLK_ILO_DESIRED_FREQ_HZ); + + /* Check if ILO accuracy is more than +/- CY_SYS_CLK_ERROR_RANGE. See post #1 of API description.*/ + if(CY_SYS_CLK_ERROR_RANGE < (uint32) (CY_SYS_CLK_ABS_MACRO(iloAccuracyValue))) + { + if (0 < iloAccuracyValue) + { + trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) + + CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + } + else + { + trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) - + CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + } + currentIloTrimValue = (CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK); + trimStep = (int32) currentIloTrimValue - trimStep; + + if(trimStep > CY_SYS_CLK_FOURBITS_MAX) + { + trimStep = CY_SYS_CLK_FOURBITS_MAX; + } + if(trimStep < 0) + { + trimStep = 0; + } + CY_SYS_CLK_ILO_TRIM_REG = (CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MASK)) | + ((uint32) trimStep); + errorRangeStatus = CYRET_STARTED; + } /* Else return success because error is in +/- 10% range*/ + else + { + /* Write trimmed ILO accuracy through pointer. */ + *iloAccuracyInPPT = iloAccuracyValue; + errorRangeStatus = CYRET_SUCCESS; + } + } + else + { + errorRangeStatus = CYRET_INVALID_STATE; + } +return (errorRangeStatus); +} + + +/******************************************************************************* +* Function Name: CySysClkIloRestoreFactoryTrim +****************************************************************************//** +* \brief +* Restores the ILO Trim Register to factory value. +* +* The CySysClkIloStartMeasurement() API should be called prior to +* calling this API. Otherwise CYRET_UNKNOWN will be returned. +* +* Available for all PSoC 4 devices except for PSoC 4000 / PSoC 4100 / PSoC 4200 +* / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. +* +* \return CYRET_SUCCESS - Operation was successful. +* \return CYRET_UNKNOWN - CySysClkIloStartMeasurement() was not called +* before this API. Hence the trim value cannot be updated. +* +******************************************************************************/ +cystatus CySysClkIloRestoreFactoryTrim(void) +{ + cystatus returnStatus = CYRET_SUCCESS; + + /* Check was defaultIloTrimRegValue modified in CySysClkIloStartMeasurement */ + if(CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE != defaultIloTrimRegValue) + { + CY_SYS_CLK_ILO_TRIM_REG = ((CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MASK)) | + (defaultIloTrimRegValue & CY_SYS_CLK_ILO_TRIM_MASK)); + } + else + { + returnStatus = CYRET_UNKNOWN; + } + + return (returnStatus); +} +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + + +#if (CY_IP_WCO && CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysClkGetLfclkSource + ******************************************************************************** + * + * \internal + * Gets the clock source for the LFCLK clock. + * The function is applicable only for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L. + * + * \return The LFCLK source: + * CY_SYS_CLK_LFCLK_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) + * CY_SYS_CLK_LFCLK_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) + * + * \endinternal + * + *******************************************************************************/ + static uint32 CySysClkGetLfclkSource(void) + { + uint32 lfclkSource; + lfclkSource = CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK; + return (lfclkSource); + } + + + /******************************************************************************* + * Function Name: CySysClkSetLfclkSource + ****************************************************************************//** + * \brief + * Sets the clock source for the LFCLK clock. + * + * The switch between LFCLK sources must be done between the positive edges of + * LFCLK, because the glitch risk is around the LFCLK positive edge. To ensure + * that the switch can be done safely, the WDT counter value is read until it + * changes. + * + * That means that the positive edge just finished and the switch is performed. + * The enabled WDT counter is used for that purpose. If no counters are enabled, + * counter 0 is enabled. And after the LFCLK source is switched, counter 0 + * configuration is restored. + * + * The function is applicable only for devices with more than one source for + * LFCLK - PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L. + * + * \note For PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices LFCLK can + * only be sourced from ILO even though WCO is available. + * + * \param + * source + * CY_SYS_CLK_LFCLK_SRC_ILO - Internal Low Frequency (32 kHz) + * Oscillator (ILO).
+ * CY_SYS_CLK_LFCLK_SRC_WCO - Low Frequency Watch Crystal Oscillator (WCO). + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is called). + * Call CySysWdtUnlock() to unlock WDT. + * + * Both the current source and the new source must be running and stable before + * calling this function. + * + * Changing the LFCLK clock source may change the LFCLK clock frequency and + * affect the functionality that uses this clock. For example, watchdog timer + * "uses this clock" or "this clock uses" (WDT) is clocked by LFCLK. + * + *******************************************************************************/ + void CySysClkSetLfclkSource(uint32 source) + { + uint8 interruptState; + + if (CySysClkGetLfclkSource() != source) + { + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_WDT_CONFIG_REG = (CY_SYS_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_LFCLK_SEL_MASK)) | + (source & CY_SYS_CLK_LFCLK_SEL_MASK); + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + } + } +#endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + + +#if (CY_IP_WCO) + /******************************************************************************* + * Function Name: CySysClkWcoStart + ****************************************************************************//** + * \brief + * Enables Watch Crystal Oscillator (WCO). + * + * This API enables WCO which is used as a source for LFCLK. Similar to ILO, + * WCO is also available in all modes except Hibernate and Stop modes. + * \note In PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices + * WCO cannot be a source for the LFCLK. + * + * WCO is always enabled in High Power Mode (HPM). Refer to the device + * datasheet for the WCO startup time. Once WCO becomes stable it can be + * switched to Low Power Mode (LPM). Note that oscillator can be unstable + * during a switch and hence its output should not be used at that moment. + * + * The CySysClkWcoSetPowerMode() function configures the WCO power mode. + * + *******************************************************************************/ + void CySysClkWcoStart(void) + { + CySysClkWcoSetHighPowerMode(); + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + } + + + /******************************************************************************* + * Function Name: CySysClkWcoStop + ****************************************************************************//** + * \brief + * Disables the 32 KHz Crystal Oscillator. + * + * API switch of WCO. + * \note PSoC 4100S / PSoC Analog Coprocessor: WCO is required for DeepSleep + * Timer's operation. + * + *******************************************************************************/ + void CySysClkWcoStop(void) + { + #if (CY_IP_SRSSV2) + uint8 interruptState; + #endif /* (CY_IP_SRSSV2) */ + + if (0u != CySysClkWcoEnabled()) + { + #if (CY_IP_SRSSV2) + if (CY_SYS_CLK_LFCLK_SRC_WCO == CySysClkGetLfclkSource()) + { + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + } + else /* Safe to disable - shortened pulse does not impact peripheral */ + #endif /* (CY_IP_SRSSV2) */ + { + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + } + } /* Otherwise do nothing. WCO configuration cannot be changed. */ + } + + + /******************************************************************************* + * Function Name: CySysClkWcoEnabled + ****************************************************************************//** + * \internal Reports the WCO enable state. + * + * \return 1 if WCO is enabled + * \return 0 if WCO is disabled. + * \endinternal + *******************************************************************************/ + uint32 CySysClkWcoEnabled(void) + { + return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE))) ? + (uint32) 1u : + (uint32) 0u); + } + + + /******************************************************************************* + * Function Name: CySysClkWcoSetPowerMode + ****************************************************************************//** + * \brief + * Sets the power mode for the 32 KHz WCO. + * + * By default (if this function is not called), the WCO is in High power mode + * during Active and device's low power modes + * + * \param mode + * CY_SYS_CLK_WCO_HPM - The High Power mode.
+ * CY_SYS_CLK_WCO_LPM - The Low Power mode. + * + * \return A previous power mode. The same as the parameters. + * + * \note + * The WCO Low Power mode is applicable for PSoC 4100 BLE / PSoC 4200 BLE devices. + * + *******************************************************************************/ + uint32 CySysClkWcoSetPowerMode(uint32 mode) + { + uint32 powerModeStatus; + + powerModeStatus = CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_LPM_EN; + + switch(mode) + { + case CY_SYS_CLK_WCO_HPM: + CySysClkWcoSetHighPowerMode(); + break; + + #if(CY_IP_BLESS) + case CY_SYS_CLK_WCO_LPM: + CySysClkWcoSetLowPowerMode(); + break; + #endif /* (CY_IP_BLESS) */ + + default: + CYASSERT(0u != 0u); + break; + } + + return (powerModeStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkWcoClockOutSelect + ****************************************************************************//** + * \brief + * Selects the WCO block output source. + * + * In addition to generating 32.768 kHz clock from external crystals, WCO + * can be sourced by external clock source using wco_out pin. The API help to + * lets you select between the sources: External crystal or external pin. + * + * If you want to use external pin to drive WCO the next procedure is required: + *
1) Disable the WCO. + *
2) Drive the wco_out pin to an external signal source. + *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_PIN). + *
4) Enable the WCO and wait for 15 us before clocking the XO pad at the high + * potential. Let's assume you are using the 1.6v clock amplitude, then the + * sequence would start at 1.6v, then 0v, then 1.6v etc at a chosen frequency. + * + * If you want to use WCO after using an external pin source: + *
1) Disable the WCO. + *
2) Drive off wco_out pin with external signal source. + *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_CRYSTAL). + *
4) Enable the WCO. + * + * \warning + * Do not use the oscillator output clock prior to a 15uS delay in your system. + * There are no limitations on the external clock frequency. + * \warning + * When external clock source was selected to drive WCO block the IMO can be + * trimmed only when external clock source period is equal to WCO external + * crystal period. Also external clock source accuracy should be higher + * or equal to WCO external crystal accuracy. + * + * \param clockSel + * CY_SYS_CLK_WCO_SEL_CRYSTAL - Selects External crystal as clock + * source of WCO.
+ * CY_SYS_CLK_WCO_SEL_PIN - Selects External clock input on wco_in pin as + * clock source of WCO. + * + *******************************************************************************/ + void CySysClkWcoClockOutSelect(uint32 clockSel) + { + if (0u != CySysClkWcoEnabled()) + { + if (1u >= clockSel) + { + CY_SYS_CLK_WCO_CONFIG_REG = (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(~CY_SYS_CLK_WCO_SELECT_PIN_MASK)) | + (clockSel << CY_SYS_CLK_WCO_SELECT_PIN_OFFSET); + } + else + { + CYASSERT(0u != 0u); + } + } + } +#endif /* (CY_IP_WCO) */ + + +#if(CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysWdtLock + ****************************************************************************//** + * \brief + * Locks out configuration changes to the Watchdog timer registers and ILO + * configuration register. + * + * After this function is called, ILO clock can't be disabled until + * CySysWdtUnlock() is called. + * + *******************************************************************************/ + void CySysWdtLock(void) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BITS_MASK; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtLocked + ****************************************************************************//** + * \internal + * Reports the WDT lock state. + * + * \return 1 - WDT is locked, and 0 - WDT is unlocked. + * \endinternal + *******************************************************************************/ + static uint32 CySysWdtLocked(void) + { + /* Prohibits writing to WDT registers and ILO/WCO registers when not equal 0 */ + return ((0u != (CY_SYS_CLK_SELECT_REG & (uint32)(CY_SYS_WDT_CLK_LOCK_BITS_MASK))) ? (uint32) 1u : (uint32) 0u); + } + + + /******************************************************************************* + * Function Name: CySysWdtUnlock + ****************************************************************************//** + * \brief + * Unlocks the Watchdog Timer configuration register. + * + *******************************************************************************/ + void CySysWdtUnlock(void) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + /* Removing WDT lock requires two writes */ + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BIT0); + + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BIT1); + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetEnabledStatus + ****************************************************************************//** + * \brief + * Reads the enabled status of one of the three WDT counters. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \return The status of the WDT counter: + * \return 0 - If the counter is disabled. + * \return 1 - If the counter is enabled. + * + * \details + * This function returns an actual WDT counter status from the status register. It may + * take up to 3 LFCLK cycles for the WDT status register to contain actual data + * after the WDT counter is enabled. + * + *******************************************************************************/ + uint32 CySysWdtGetEnabledStatus(uint32 counterNum) + { + CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + return ((CY_SYS_WDT_CONTROL_REG >> ((CY_SYS_WDT_CNT_SHIFT * counterNum) + CY_SYS_WDT_CNT_STTS_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMode + ****************************************************************************//** + * \brief + * Writes the mode of one of the three WDT counters. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \param mode + * CY_SYS_WDT_MODE_NONE - Free running.
+ * CY_SYS_WDT_MODE_INT - The interrupt generated on match for counter 0 + * and 1, and on bit toggle for counter 2.
+ * CY_SYS_WDT_MODE_RESET - Reset on match (valid for counter 0 and 1 only).
+ * CY_SYS_WDT_MODE_INT_RESET - Generate an interrupt. Generate a reset on + * the 3rd non-handled interrupt (valid for counter 0 and counter 1 only). + * + * \details + * WDT counter counterNum should be disabled to set a mode. Otherwise, this + * function call has no effect. If the specified counter is enabled, + * call the CySysWdtDisable() function with the corresponding parameter to + * disable the specified counter and wait for it to stop. + * + *******************************************************************************/ + void CySysWdtSetMode(uint32 counterNum, uint32 mode) + { + uint32 configRegValue; + + CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + + if(0u == CySysWdtGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG & + (uint32)~((uint32)(CY_SYS_WDT_MODE_MASK << (counterNum * CY_SYS_WDT_CNT_SHIFT))); + configRegValue |= (uint32)((mode & CY_SYS_WDT_MODE_MASK) << (counterNum * CY_SYS_WDT_CNT_SHIFT)); + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMode + ****************************************************************************//** + * + * \brief Reads the mode of one of the three WDT counters. + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + * \return The mode of the counter. The same enumerated values as the mode + * parameter used in CySysWdtSetMode(). + * + *******************************************************************************/ + uint32 CySysWdtGetMode(uint32 counterNum) + { + return ((CY_SYS_WDT_CONFIG_REG >> (counterNum * CY_SYS_WDT_CNT_SHIFT)) & CY_SYS_WDT_MODE_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetClearOnMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter "clear on match" setting. + * + * If configured to "clear on match", the counter counts from 0 to MatchValue + * giving it a period of (MatchValue + 1). + * + * \param counterNum + * Valid range [0-1]. The number of the WDT counter. The match values are not + * supported by counter 2. + * + * \param enable 0 to disable appropriate counter
+ * 1 to enable appropriate counter + * + * \details + * WDT counter counterNum should be disabled. Otherwise this function call + * has no effect. If the specified counter is enabled, call the CySysWdtDisable() + * function with the corresponding parameter to disable the specified counter and + * wait for it to stop. This may take up to three LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetClearOnMatch(uint32 counterNum, uint32 enable) + { + uint32 configRegValue; + + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + if(0u == CySysWdtGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << + ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT))); + + configRegValue + |= (uint32)(enable << ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)); + + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetClearOnMatch + ****************************************************************************//** + * \brief + * Reads the "clear on match" setting for the specified counter. + * + * \param + * counterNum Valid range [0-1]. The number of the WDT counter. The match values + * are not supported by counter 2. + * + * \return The "clear on match" status:
1 if enabled
0 if disabled + * + *******************************************************************************/ + uint32 CySysWdtGetClearOnMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + return (uint32)((CY_SYS_WDT_CONFIG_REG >> + ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnable + ****************************************************************************//** + * + * \brief Enables the specified WDT counters. + * + * All the counters specified in the mask are enabled. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to enable.
+ * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to enable.
+ * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to enable. + * + * \details + * Enabling or disabling WDT requires 3 LFCLK cycles to come into effect. + * Therefore, the WDT enable state must not be changed more than once in + * that period. + * + * After WDT is enabled, it is illegal to write WDT configuration (WDT_CONFIG) + * and control (WDT_CONTROL) registers. This means that all WDT functions that + * contain 'write' in the name (with the exception of CySysWdtSetMatch() + * function) are illegal to call if WDT is enabled. + * + * PSoC 4100 / PSoC 4200: This function enables ILO. + * + * PSoC 4100 BLE / PSoC 4200 BLE / PSoC4200L / PSoC 4100M + * / PSoC 4200M: + * LFLCK should be configured before calling this function. The desired + * source should be enabled and configured to be the source for LFCLK. + * + *******************************************************************************/ + void CySysWdtEnable(uint32 counterMask) + { + #if (!CY_IP_WCO) + CySysClkIloStart(); + #endif /* (!CY_IP_WCO) */ + + CY_SYS_WDT_CONTROL_REG |= counterMask; + + if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + /* Wait for changes to come into effect */ + } + } + } + + + /******************************************************************************* + * Function Name: CySysWdtDisable + ****************************************************************************//** + * + * \brief Disables the specified WDT counters. + * All the counters specified in the mask are disabled. The function waits for + * the changes to come into effect. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to disable.
+ * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to disable.
+ * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to disable. + * + *******************************************************************************/ + void CySysWdtDisable(uint32 counterMask) + { + if (0uL == CySysWdtLocked()) + { + CY_SYS_WDT_CONTROL_REG &= ~counterMask; + + if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + /* Wait for changes to come into effect */ + } + } + } + } + + + /******************************************************************************* + * Function Name: CySysWdtSetCascade + ****************************************************************************//** + * \brief + * Writes the two WDT cascade values based on the combination of mask values + * specified. + * + * \param cascadeMask The mask value used to set or clear the cascade values: + * CY_SYS_WDT_CASCADE_NONE - Neither
+ * CY_SYS_WDT_CASCADE_01 - Cascade 01
+ * CY_SYS_WDT_CASCADE_12 - Cascade 12 + * + * If only one cascade mask is specified, the second cascade is disabled. + * To set both cascade modes, two defines should be ORed: + * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). + * \note If CySysWdtSetCascade() was called with ORed defines it is necessary + * to call CySysWdtSetClearOnMatch(1,1). It is needed to make sure that + * Counter 2 will be updated in the expected way. + * + * WDT counters that are part of the specified cascade should be disabled. + * Otherwise this function call has no effect. If the specified + * counter is enabled, call CySysWdtDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. This may + * take up to 3 LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetCascade(uint32 cascadeMask) + { + uint32 configRegValue; + uint32 countersEnableStatus; + + countersEnableStatus = CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0) | + CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1) | + CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2); + + if (0u == countersEnableStatus) + { + configRegValue = CY_SYS_WDT_CONFIG_REG; + configRegValue &= ((uint32)(~(CY_SYS_WDT_CASCADE_01|CY_SYS_WDT_CASCADE_12))); + configRegValue |= cascadeMask; + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCascade + ****************************************************************************//** + * + * \brief Reads the two WDT cascade values returning a mask of the bits set. + * + * \return The mask of the cascade values set. + * \return CY_SYS_WDT_CASCADE_NONE - Neither + * \return CY_SYS_WDT_CASCADE_01 - Cascade 01 + * \return CY_SYS_WDT_CASCADE_12 - Cascade 12 + * + *******************************************************************************/ + uint32 CySysWdtGetCascade(void) + { + return (CY_SYS_WDT_CONFIG_REG & (CY_SYS_WDT_CASCADE_01 | CY_SYS_WDT_CASCADE_12)); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter match comparison value. + * + * \param counterNum + * Valid range [0-1]. The number of the WDT counter. The match values are not + * supported by counter 2. + * + * \param match + * Valid range [0-65535]. The value to be used to match against the counter. + * + *******************************************************************************/ + void CySysWdtSetMatch(uint32 counterNum, uint32 match) + { + uint32 regValue; + + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + /* Wait for previous changes to come into effect */ + CyDelayUs(CY_SYS_WDT_3LFCLK_DELAY_US); + + regValue = CY_SYS_WDT_MATCH_REG; + regValue &= (uint32)~((uint32)(CY_SYS_WDT_LOWER_16BITS_MASK << (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT))); + CY_SYS_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT))); + + /* Make sure match synchronization has started */ + CyDelayUs(CY_SYS_WDT_1LFCLK_DELAY_US); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetToggleBit + ****************************************************************************//** + * \brief + * Configures which bit in WDT counter 2 to monitor for a toggle. + * + * When that bit toggles, an interrupt is generated if the mode for counter 2 has + * enabled interrupts. + * + * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. + * + * \details + * WDT Counter 2 should be disabled. Otherwise this function call has no + * effect. + * + * If the specified counter is enabled, call the CySysWdtDisable() function with + * the corresponding parameter to disable the specified counter and wait for it to + * stop. This may take up to 3 LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetToggleBit(uint32 bits) + { + uint32 configRegValue; + + if (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG; + configRegValue &= (uint32)(~((uint32)(CY_SYS_WDT_CONFIG_BITS2_MASK << CY_SYS_WDT_CONFIG_BITS2_POS))); + configRegValue |= ((bits & CY_SYS_WDT_CONFIG_BITS2_MASK) << CY_SYS_WDT_CONFIG_BITS2_POS); + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetToggleBit + ****************************************************************************//** + * \brief + * Reads which bit in WDT counter 2 is monitored for a toggle. + * + * \return The bit that is monitored (range of 0 to 31) + * + *******************************************************************************/ + uint32 CySysWdtGetToggleBit(void) + { + return ((CY_SYS_WDT_CONFIG_REG >> CY_SYS_WDT_CONFIG_BITS2_POS) & CY_SYS_WDT_CONFIG_BITS2_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMatch + ****************************************************************************//** + * + * \brief Reads the WDT counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the WDT counter. The match + * values are not supported by counter 2. + * + * \return A 16-bit match value. + * + *******************************************************************************/ + uint32 CySysWdtGetMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + return ((uint32)(CY_SYS_WDT_MATCH_REG >> + (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT)) & CY_SYS_WDT_LOWER_16BITS_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCount + ****************************************************************************//** + * + * \brief Reads the current WDT counter value. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters + * and counter 2 is a 32 bit counter. + * + *******************************************************************************/ + uint32 CySysWdtGetCount(uint32 counterNum) + { + uint32 regValue = 0u; + + switch(counterNum) + { + /* WDT Counter 0 */ + case 0u: + regValue = CY_SYS_WDT_CTRLOW_REG & CY_SYS_WDT_LOWER_16BITS_MASK; + break; + + /* WDT Counter 1 */ + case 1u: + regValue = (CY_SYS_WDT_CTRLOW_REG >> CY_SYS_WDT_CNT_MATCH_SHIFT) & CY_SYS_WDT_LOWER_16BITS_MASK; + break; + + /* WDT Counter 2 */ + case 2u: + regValue = CY_SYS_WDT_CTRHIGH_REG; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + return (regValue); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetInterruptSource + ****************************************************************************//** + * \brief + * Reads a mask containing all the WDT counters interrupts that are currently + * set by the hardware, if a corresponding mode is selected. + * + * \return The mask of interrupts set + * \return CY_SYS_WDT_COUNTER0_INT - Counter 0 + * \return CY_SYS_WDT_COUNTER1_INT - Counter 1 + * \return CY_SYS_WDT_COUNTER2_INT - Counter 2 + * + *******************************************************************************/ + uint32 CySysWdtGetInterruptSource(void) + { + return (CY_SYS_WDT_CONTROL_REG & (CY_SYS_WDT_COUNTER0_INT | CY_SYS_WDT_COUNTER1_INT | CY_SYS_WDT_COUNTER2_INT)); + } + + + /******************************************************************************* + * Function Name: CySysWdtClearInterrupt + ****************************************************************************//** + * \brief + * Clears all the WDT counter interrupts set in the mask. + * + * Calling this function also prevents from Reset when the counter mode is set + * to generate 3 interrupts and then the device resets. + * + * All the WDT interrupts are to be cleared by the firmware, otherwise + * interrupts are generated continuously. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_INT - Clears counter 0 interrupts
+ * CY_SYS_WDT_COUNTER1_INT - Clears counter 1 interrupts
+ * CY_SYS_WDT_COUNTER2_INT - Clears counter 2 interrupts + * + * \details + * This function temporary removes the watchdog lock, if it was set, and + * restores the lock state after cleaning the WDT interrupts that are set in + * a mask. + * + *******************************************************************************/ + void CySysWdtClearInterrupt(uint32 counterMask) + { + uint8 interruptState; + uint32 wdtLockState; + + interruptState = CyEnterCriticalSection(); + + if (0u != CySysWdtLocked()) + { + wdtLockState = 1u; + CySysWdtUnlock(); + } + else + { + wdtLockState = 0u; + } + + /* Set new WDT control register value */ + counterMask &= (CY_SYS_WDT_COUNTER0_INT | + CY_SYS_WDT_COUNTER1_INT | + CY_SYS_WDT_COUNTER2_INT); + + CY_SYS_WDT_CONTROL_REG = counterMask | (CY_SYS_WDT_CONTROL_REG & ~(CY_SYS_WDT_COUNTER0_INT | + CY_SYS_WDT_COUNTER1_INT | + CY_SYS_WDT_COUNTER2_INT)); + + /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. + * Cypress ID #207093, #206231 + */ + (void)CY_SYS_WDT_CONTROL_REG; + + if (1u == wdtLockState) + { + CySysWdtLock(); + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtResetCounters + ****************************************************************************//** + * \brief + * Resets all the WDT counters set in the mask. + * + * \param countersMask + * CY_SYS_WDT_COUNTER0_RESET - Reset counter 0
+ * CY_SYS_WDT_COUNTER1_RESET - Reset counter 1
+ * CY_SYS_WDT_COUNTER2_RESET - Reset counter 2 + * + * \details + * This function does not reset counter values if the Watchdog is locked. + * This function waits while corresponding counters will be reset. This may + * take up to 3 LFCLK cycles. + * The LFCLK source must be enabled. Otherwise, the function will never exit. + * + *******************************************************************************/ + void CySysWdtResetCounters(uint32 countersMask) + { + /* Set new WDT reset value */ + CY_SYS_WDT_CONTROL_REG |= (countersMask & CY_SYS_WDT_COUNTERS_RESET); + + while (0uL != (CY_SYS_WDT_CONTROL_REG & CY_SYS_WDT_COUNTERS_RESET)) + { + /* Wait for reset to come into effect */ + } + } + + + /******************************************************************************* + * Function Name: CySysWdtSetInterruptCallback + ****************************************************************************//** + * \brief + * Sets the ISR callback function for the particular WDT counter. + * These functions are called on the WDT interrupt. + * + * \param counterNum The number of the WDT counter. + * \param function The pointer to the callback function. + * + * \return The pointer to the previous callback function. + * \return NULL is returned if the specified address is not set. + * + *******************************************************************************/ + cyWdtCallback CySysWdtSetInterruptCallback(uint32 counterNum, cyWdtCallback function) + { + cyWdtCallback prevCallback = (void *)0; + + if(counterNum < CY_WDT_NUM_OF_WDT) + { + prevCallback = cySysWdtCallback[counterNum]; + cySysWdtCallback[counterNum] = function; + } + else + { + CYASSERT(0u != 0u); + } + + return((cyWdtCallback)prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetInterruptCallback + ****************************************************************************//** + * \brief + * Gets the ISR callback function for the particular WDT counter. + * + * \param counterNum The number of the WDT counter. + * + * \return The pointer to the callback function registered for a particular WDT by + * a particular address that are passed through arguments. + * + *******************************************************************************/ + cyWdtCallback CySysWdtGetInterruptCallback(uint32 counterNum) + { + cyWdtCallback retCallback = (void *)0; + + if(counterNum < CY_WDT_NUM_OF_WDT) + { + retCallback = (cyWdtCallback)cySysWdtCallback[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + + return(retCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnableCounterIsr + ****************************************************************************//** + * \brief + * Enables the ISR callback servicing for the particular WDT counter + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + * Value corresponds to appropriate WDT counter. For example value 1 + * corresponds to second WDT counter. + * + *******************************************************************************/ + void CySysWdtEnableCounterIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_WDT_COUNTER2) + { + disableServicedIsr &= ~counterIntMaskTbl[counterNum]; + wdtIsrMask |= counterIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysWdtDisableCounterIsr + ****************************************************************************//** + * \brief + * Disables the ISR callback servicing for the particular WDT counter + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + *******************************************************************************/ + void CySysWdtDisableCounterIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_WDT_COUNTER2) + { + wdtIsrMask &= ~counterIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysWdtIsr + ****************************************************************************//** + * \brief + * This is the handler of the WDT interrupt in CPU NVIC. + * + * The handler checks which WDT triggered in the interrupt and calls the + * respective callback functions configured by the user by using + * CySysWdtSetIsrCallback() API. + * + * The order of the callback execution is incremental. Callback-0 is + * run as the first one and callback-2 is called as the last one. + * + * \details + * This function clears the WDT interrupt every time when it is called. + * Reset after the 3rd interrupt does not happen if this function is registered + * as the interrupt handler even if the "Watchdog with Interrupt" mode is + * selected on the "Low Frequency Clocks" tab. + * + *******************************************************************************/ + void CySysWdtIsr(void) + { + if(0u != (CY_SYS_WDT_COUNTER0_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER0_INT & wdtIsrMask)) + { + wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER0_INT); + disableServicedIsr &= ~CY_SYS_WDT_COUNTER0_INT; + if(cySysWdtCallback[CY_SYS_WDT_COUNTER0] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER0])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + + if(0u != (CY_SYS_WDT_COUNTER1_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER1_INT & wdtIsrMask)) + { + wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER1_INT); + disableServicedIsr &= ~CY_SYS_WDT_COUNTER1_INT; + if(cySysWdtCallback[CY_SYS_WDT_COUNTER1] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER1])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + + if(0u != (CY_SYS_WDT_COUNTER2_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER2_INT & wdtIsrMask)) + { + if(cySysWdtCallback[CY_SYS_WDT_COUNTER2] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER2])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER2_INT); + } + } + + + /******************************************************************************* + * Function Name: CySysWatchdogFeed + ****************************************************************************//** + * \brief + * Feeds the corresponded Watchdog Counter before it causes the device reset. + * + * Supported only for first WDT0 and second WDT1 counters in the "Watchdog" or + * "Watchdog w/ Interrupts" modes. + * + * \param counterNum + * CY_SYS_WDT_COUNTER0 - Feeds the Counter 0
+ * CY_SYS_WDT_COUNTER1 - Feeds the Counter 1 + * + * Value of counterNum corresponds to appropriate counter. For example value 1 + * corresponds to second WDT1 Counter. + * + * \details + * Clears the WDT counter in the "Watchdog" mode or clears the WDT interrupt in + * "Watchdog w/ Interrupts" mode. Does nothing in other modes. + * + *******************************************************************************/ + void CySysWatchdogFeed(uint32 counterNum) + { + if(counterNum == CY_SYS_WDT_COUNTER0) + { + if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtResetCounters(CY_SYS_WDT_COUNTER0_RESET); + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + else + { + /* Do nothing. */ + } + } + else if(counterNum == CY_SYS_WDT_COUNTER1) + { + if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtResetCounters(CY_SYS_WDT_COUNTER1_RESET); + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + else + { + /* Do nothing. */ + } + } + else + { + /* Do nothing. */ + } + } + + + /******************************************************************************* + * Function Name: CySysClkLfclkPosedgeCatch + ****************************************************************************//** + * \internal + * Returns once the LFCLK positive edge occurred. + * + * CySysClkLfclkPosedgeRestore() should be called after this function + * to restore the WDT configuration. + * + * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() + * functions is expected to be called inside a critical section. + * + * To ensure that the WDT counter value is read until it changes, the enabled + * WDT counter is used. If no counter is enabled, counter 0 is enabled. + * And after the LFCLK source is switched, the counter 0 configuration + * is restored. + * + * Not applicable for the PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog + * Coprocessor devices. + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is + * called). Call CySysWdtUnlock() to unlock WDT. + * \endinternal + *******************************************************************************/ + static void CySysClkLfclkPosedgeCatch(void) + { + uint32 firstCount; + static uint32 lfclkPosedgeEnabledWdtCounter = 0u; + + if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + } + else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER1; + } + else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER2; + } + else /* All WDT counters are disabled */ + { + /* Configure WDT counter # 0 */ + lfclkPosedgeWdtCounter0Enabled = 1u; + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + + lfclkPosedgeWdtCounter0Mode = CySysWdtGetMode(CY_SYS_WDT_COUNTER0); + CySysWdtSetMode(CY_SYS_WDT_COUNTER0, CY_SYS_WDT_MODE_NONE); + CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK); + } + + firstCount = CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter); + while (CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter) == firstCount) + { + /* Wait for counter to increment */ + } + } + + + /******************************************************************************* + * Function Name: CySysClkLfclkPosedgeRestore + ****************************************************************************//** + * \internal + * Restores the WDT configuration after a CySysClkLfclkPosedgeCatch() call. + * + * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() + * functions is expected to be called inside a critical section. + * + * Not applicable for the PSoC 4000/PSoC 4000S / PSoC 4100S / PSoC Analog + * Coprocessor devices. + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is + * called). Call CySysWdtUnlock() to unlock WDT. + * + * \endinternal + *******************************************************************************/ + static void CySysClkLfclkPosedgeRestore(void) + { + if (lfclkPosedgeWdtCounter0Enabled != 0u) + { + /* Restore counter # 0 configuration and force its shutdown */ + CY_SYS_WDT_CONTROL_REG &= (uint32)(~CY_SYS_WDT_COUNTER0_MASK); + CySysWdtSetMode(CY_SYS_WDT_COUNTER0, lfclkPosedgeWdtCounter0Mode); + lfclkPosedgeWdtCounter0Enabled = 0u; + } + } + +#else + + /******************************************************************************* + * Function Name: CySysWdtGetEnabledStatus + ****************************************************************************//** + * + * \brief Reads the enabled status of the WDT counter. + * + * \return The status of the WDT counter: + * \return 0 - Counter is disabled + * \return 1 - Counter is enabled + * + *******************************************************************************/ + uint32 CySysWdtGetEnabledStatus(void) + { + return ((CY_SYS_WDT_DISABLE_KEY_REG == CY_SYS_WDT_KEY) ? (uint32) 0u : (uint32) 1u); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnable + ****************************************************************************//** + * + * \brief + * Enables watchdog timer reset generation. + * + * CySysWdtClearInterrupt() feeds the watchdog. Two unserviced interrupts lead + * to a system reset (i.e. at the third match). + * + * ILO is enabled by the hardware once WDT is started. + * + *******************************************************************************/ + void CySysWdtEnable(void) + { + CY_SYS_WDT_DISABLE_KEY_REG = 0u; + } + + + /******************************************************************************* + * Function Name: CySysWdtDisable + ****************************************************************************//** + * + * \brief Disables the WDT reset generation. + * + * This function unlocks the ENABLE bit in the CLK_ILO_CONFIG registers and + * enables the user to disable ILO. + * + *******************************************************************************/ + void CySysWdtDisable(void) + { + CY_SYS_WDT_DISABLE_KEY_REG = CY_SYS_WDT_KEY; + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter match comparison value. + * + * \param match Valid range [0-65535]. The value to be used to match against + * the counter. + * + *******************************************************************************/ + void CySysWdtSetMatch(uint32 match) + { + match &= CY_SYS_WDT_MATCH_MASK; + CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_MATCH_MASK)) | match; + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMatch + ****************************************************************************//** + * + * \brief Reads the WDT counter match comparison value. + * + * \return The counter match value. + * + *******************************************************************************/ + uint32 CySysWdtGetMatch(void) + { + return (CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_MATCH_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCount + ****************************************************************************//** + * + * \brief Reads the current WDT counter value. + * + * \return A live counter value. + * + *******************************************************************************/ + uint32 CySysWdtGetCount(void) + { + return ((uint32)CY_SYS_WDT_COUNTER_REG); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetIgnoreBits + ****************************************************************************//** + * + * \brief + * Configures the number of the MSB bits of the watchdog timer that are not + * checked against the match. + * + * \param bitsNum Valid range [0-15]. The number of the MSB bits. + * + * \details The value of bitsNum controls the time-to-reset of the watchdog + * (which happens after 3 successive matches). + * + *******************************************************************************/ + void CySysWdtSetIgnoreBits(uint32 bitsNum) + { + bitsNum = ((uint32)(bitsNum << CY_SYS_WDT_IGNORE_BITS_SHIFT) & CY_SYS_WDT_IGNORE_BITS_MASK); + CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_IGNORE_BITS_MASK)) | bitsNum; + } + + + /******************************************************************************* + * Function Name: CySysWdtGetIgnoreBits + ****************************************************************************//** + * + * \brief + * Reads the number of the MSB bits of the watchdog timer that are not + * checked against the match. + * + * \return The number of the MSB bits. + * + *******************************************************************************/ + uint32 CySysWdtGetIgnoreBits(void) + { + return((uint32)((CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_IGNORE_BITS_MASK) >> CY_SYS_WDT_IGNORE_BITS_SHIFT)); + } + + + /******************************************************************************* + * Function Name: CySysWdtClearInterrupt + ****************************************************************************//** + * + * \brief + * Feeds the watchdog. + * Cleans the WDT match flag which is set every time the WDT counter reaches a + * WDT match value. Two unserviced interrupts lead to a system reset + * (i.e. at the third match). + * + *******************************************************************************/ + void CySysWdtClearInterrupt(void) + { + CY_SYS_SRSS_INTR_REG |= CY_SYS_WDT_LOWER_BIT_MASK; + } + + + /******************************************************************************* + * Function Name: CySysWdtMaskInterrupt + ****************************************************************************//** + * + * \brief + * After masking interrupts from WDT, they are not passed to CPU. + * This function does not disable WDT reset generation. + * + *******************************************************************************/ + void CySysWdtMaskInterrupt(void) + { + CY_SYS_SRSS_INTR_MASK_REG &= (uint32)(~ (uint32)CY_SYS_WDT_LOWER_BIT_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtUnmaskInterrupt + ****************************************************************************//** + * + * \brief + * After unmasking interrupts from WDT, they are passed to CPU. + * This function does not impact the reset generation. + * + *******************************************************************************/ + void CySysWdtUnmaskInterrupt(void) + { + CY_SYS_SRSS_INTR_MASK_REG |= CY_SYS_WDT_LOWER_BIT_MASK; + } + + + /******************************************************************************* + * Function Name: CySysWdtSetIsrCallback + ****************************************************************************//** + * + * \brief + * Sets the ISR callback function for the WDT counter + * + * \param function The pointer to the callback function. + * + * \return The pointer to a previous callback function. + * + *******************************************************************************/ + cyWdtCallback CySysWdtSetInterruptCallback(cyWdtCallback function) + { + cyWdtCallback prevCallback = (void *)0; + + prevCallback = cySysWdtCallback; + cySysWdtCallback = function; + + return(prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetIsrCallback + ****************************************************************************//** + * + * \brief + * Gets the ISR callback function for the WDT counter + * + * \return The pointer to the callback function registered for WDT. + * + *******************************************************************************/ + cyWdtCallback CySysWdtGetInterruptCallback(void) + { + return(cySysWdtCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtIsr + ****************************************************************************//** + * + * \brief + * This is the handler of the WDT interrupt in CPU NVIC. + * + * The handler calls the respective callback functions configured by the user + * by using CySysWdtSetIsrCallback() API. + * + * + * \details + * This function clears the WDT interrupt every time when it is called. + * Reset after the 3rd interrupt does not happen if this function is registered + * as the interrupt handler even if the "Watchdog with Interrupt" mode is + * selected on the "Low Frequency Clocks" tab. + * + *******************************************************************************/ + void CySysWdtIsr(void) + { + if(cySysWdtCallback != (void *) 0) + { + (void)(cySysWdtCallback)(); + } + + CySysWdtClearInterrupt(); + } + +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + +/******************************************************************************* +* Function Name: CySysClkGetTimerSource +******************************************************************************** +* +* \brief Gets the clock source for the DeepSleep Timers. +* +* The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor. +* +* \return The DeepSleep Timer source +* CY_SYS_CLK_TIMER_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) +* CY_SYS_CLK_TIMER_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) +* +*******************************************************************************/ + static uint32 CySysClkGetTimerSource(void) + { + uint32 timerSource; + timerSource = CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK; + return (timerSource); + } + + +/******************************************************************************* +* Function Name: CySysClkSetTimerSource +****************************************************************************//** +* +* \brief Sets the clock source for the DeepSleep Timers. +* +* The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor +* devices. +* +* \param source +* CY_SYS_CLK_TIMER_SRC_ILO - Internal Low Frequency (32 kHz) Oscillator +* (ILO).
+* CY_SYS_CLK_TIMER_SRC_WCO - Low Frequency Watch Crystal Oscillator +* (WCO). +* +* \details Both the current source and the new source must be running and stable +* before calling this function. +* +* \warning DeepSleep Timer reset is required if Timer source was switched while +* DeepSleep Timers were running. Call CySysTimerResetCounters() API after +* Timer source switching. +* It is highly recommended to disable DeepSleep Timers before Timer source +* switching. Changing the Timer source may change the functionality that uses +* this Timers as clock source. +*******************************************************************************/ + void CySysClkSetTimerSource(uint32 source) + { + uint8 interruptState; + + if (CySysClkGetTimerSource() != source) + { + + /* Reset both _EN bits in WCO_WDT_CLKEN register */ + CY_SYS_WCO_WDT_CLKEN_REG &= ~CY_SYS_WCO_WDT_CLKEN_RESET_MASK; + + /* Wait 4 new clock source-cycles for change to come into effect */ + CyDelayUs(CY_SYS_4TIMER_DELAY_US); + + interruptState = CyEnterCriticalSection(); + CY_SYS_WCO_WDT_CONFIG_REG = (CY_SYS_WCO_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_TIMER_SEL_MASK)) | + (source & CY_SYS_CLK_TIMER_SEL_MASK); + CyExitCriticalSection(interruptState); + } + + CY_SYS_WCO_WDT_CLKEN_REG = (CY_SYS_WCO_WDT_CLKEN_REG & (uint32)(~CY_SYS_WCO_WDT_CLKEN_RESET_MASK)) | + CY_SYS_SET_CURRENT_TIMER_SOURCE_BIT; + } + + + /******************************************************************************* + * Function Name: CySysTimerGetEnabledStatus + ****************************************************************************//** + * + * \brief Reads the enabled status of one of the three DeepSleep Timer + * counters. + * + * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer + * counter. + * + * \return The status of the Timers counter: + * \return 0 - If the Counter is disabled. + * \return 1 - If the Counter is enabled. + * + * \details + * This function returns an actual DeepSleep Timer counter status from the + * status register. It may take up to 3 LFCLK cycles for the Timer status + * register to contain actual data after the Timer counter is enabled. + * + *******************************************************************************/ + uint32 CySysTimerGetEnabledStatus(uint32 counterNum) + { + CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); + return ((CY_SYS_WCO_WDT_CONTROL_REG >> ((CY_SYS_TIMER_CNT_SHIFT * counterNum) + + CY_SYS_TIMER_CNT_STTS_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetMode + ****************************************************************************//** + * + * \brief Writes the mode of one of the three DeepSleep Timer counters. + * + * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer + * counter. + * + * \param mode + * CY_SYS_TIMER_MODE_NONE - Free running.
+ * CY_SYS_TIMER_MODE_INT - The interrupt generated on match for counter 0 + * and 1, and on bit toggle for counter 2. + * + * \details + * DeepSleep Timer counter counterNum should be disabled to set a mode. + * Otherwise, this function call has no effect. If the specified counter is + * enabled, call the CySysTimerDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. + * + *******************************************************************************/ + void CySysTimerSetMode(uint32 counterNum, uint32 mode) + { + uint32 configRegValue; + + CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); + + CYASSERT(mode <= CY_SYS_TIMER_MODE_MASK); + + if(0u == CySysTimerGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & + (uint32)~((uint32)(CY_SYS_TIMER_MODE_MASK << (counterNum * CY_SYS_TIMER_CNT_SHIFT))); + configRegValue |= (uint32)((mode & CY_SYS_TIMER_MODE_MASK) << (counterNum * CY_SYS_TIMER_CNT_SHIFT)); + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetMode + ****************************************************************************//** + * + * \brief Reads the mode of one of the three DeepSleep Timer counters. + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * \return The mode of the counter. The same enumerated values as the mode + * parameter used in CySysTimerSetMode(). + * + *******************************************************************************/ + uint32 CySysTimerGetMode(uint32 counterNum) + { + return ((CY_SYS_WCO_WDT_CONFIG_REG >> (counterNum * CY_SYS_TIMER_CNT_SHIFT)) & CY_SYS_TIMER_MODE_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetClearOnMatch + ****************************************************************************//** + * + * \brief Configures the DeepSleep Timer counter "clear on match" setting. + * + * If configured to "clear on match", the counter counts from 0 to MatchValue + * giving it a period of (MatchValue + 1). + * + * \param counterNum + * Valid range [0-1]. The number of the Timer counter. The match values are not + * supported by counter 2. + * \param enable 0 to disable appropriate counter
+ * 1 to enable appropriate counter + * + * \details + * Timer counter counterNum should be disabled. Otherwise this function call + * has no effect. If the specified counter is enabled, call the CySysTimerDisable() + * function with the corresponding parameter to disable the specified counter and + * wait for it to stop. This may take up to three Timer source-cycles. + * + *******************************************************************************/ + void CySysTimerSetClearOnMatch(uint32 counterNum, uint32 enable) + { + uint32 configRegValue; + + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + if(0u == CySysTimerGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << + ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT))); + + configRegValue + |= (uint32)(enable << ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT)); + + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetClearOnMatch + ****************************************************************************//** + * + * \brief Reads the "clear on match" setting for the specified DeepSleep Timer + * counter. + * + * \param counterNum Valid range [0-1]. The number of the Timer counter. The + * match values are not supported by counter 2. + * + * \return The "clear on match" status:
1 if enabled
0 if disabled + * + *******************************************************************************/ + uint32 CySysTimerGetClearOnMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + return (uint32)((CY_SYS_WCO_WDT_CONFIG_REG >> + ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTimerEnable + ****************************************************************************//** + * + * \brief Enables the specified DeepSleep Timer counters. All the counters + * specified in the mask are enabled. + * + * \param counterMask CY_SYS_TIMER0_MASK - The mask for counter 0 to enable.
+ * CY_SYS_TIMER1_MASK - The mask for counter 1 to enable.
+ * CY_SYS_TIMER2_MASK - The mask for counter 2 to enable. + * + * \details + * Enabling or disabling Timer requires 3 Timer source-cycles to come into effect. + * Therefore, the Timer enable state must not be changed more than once in + * that period. + * + * After Timer is enabled, it is illegal to write Timer configuration + * (WCO_WDT_CONFIG) and control (WCO_WDT_CONTROL) registers. This means that all + * Timer functions that contain 'write' in the name (with the exception of + * CySysTimerSetMatch() function) are illegal to call once Timer enabled. + * + * Timer current source must be running and stable before calling this + * function. + * + *******************************************************************************/ + void CySysTimerEnable(uint32 counterMask) + { + CY_SYS_WCO_WDT_CONTROL_REG |= counterMask; + + if(0u != (counterMask & CY_SYS_TIMER0_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER1_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER2_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + /* Wait for changes to come into effect */ + } + } + } + + + /******************************************************************************* + * Function Name: CySysTimerDisable + ****************************************************************************//** + * + * \brief Disables the specified DeepSleep Timer counters. + * + * All the counters specified in the mask are disabled. The function waits for + * the changes to come into effect. + * + * \param counterMask + * CY_SYS_TIMER0_MASK - The mask for Counter 0 to disable.
+ * CY_SYS_TIMER1_MASK - The mask for Counter 1 to disable.
+ * CY_SYS_TIMER2_MASK - The mask for Counter 2 to disable. + * + *******************************************************************************/ + void CySysTimerDisable(uint32 counterMask) + { + + CY_SYS_WCO_WDT_CONTROL_REG &= ~counterMask; + + if(0u != (counterMask & CY_SYS_TIMER0_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER1_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER2_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + /* Wait for changes to come into effect */ + } + } + + } + + + /******************************************************************************* + * Function Name: CySysTimerSetCascade + ****************************************************************************//** + * + * \brief + * Writes the two DeepSleep Timers cascade values based on the combination of + * mask values specified. + * + * \param cascadeMask The mask value used to set or clear the cascade values: + * CY_SYS_TIMER_CASCADE_NONE - Neither
+ * CY_SYS_TIMER_CASCADE_01 - Cascade 01
+ * CY_SYS_TIMER_CASCADE_12 - Cascade 12 + * + * If only one cascade mask is specified, the second cascade is disabled. + * To set both cascade modes, two defines should be ORed: + * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). + * \note If CySysTimerSetCascade() was called with ORed defines it is necessary + * to call CySysTimeSetClearOnMatch(1,1). It is needed to make sure that + * Counter 2 will be updated in the expected way. + * + * Timer counters that are part of the specified cascade should be disabled. + * Otherwise this function call has no effect. If the specified + * counter is enabled, call CySysTimerDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. This may + * take up to 3 Timers source-cycles. + * + *******************************************************************************/ + void CySysTimerSetCascade(uint32 cascadeMask) + { + uint32 configRegValue; + uint32 countersEnableStatus; + + countersEnableStatus = CySysTimerGetEnabledStatus(CY_SYS_TIMER0) | + CySysTimerGetEnabledStatus(CY_SYS_TIMER1) | + CySysTimerGetEnabledStatus(CY_SYS_TIMER2); + + if (0u == countersEnableStatus) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; + configRegValue &= ((uint32)(~(CY_SYS_TIMER_CASCADE_01|CY_SYS_TIMER_CASCADE_12))); + configRegValue |= cascadeMask; + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetCascade + ****************************************************************************//** + * + * \brief Reads the two DeepSleep Timer cascade values returning a mask of the + * bits set. + * + * \return The mask of the cascade values set. + * \return CY_SYS_TIMER_CASCADE_NONE - Neither + * \return CY_SYS_TIMER_CASCADE_01 - Cascade 01 + * \return CY_SYS_TIMER_CASCADE_12 - Cascade 12 + * + *******************************************************************************/ + uint32 CySysTimerGetCascade(void) + { + return (CY_SYS_WCO_WDT_CONFIG_REG & (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12)); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetMatch + ****************************************************************************//** + * + * \brief Configures the Timer counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the Timer counter. The + * match values are not supported by counter 2. + * + * \param match Valid range [0-65535]. The value to be used to match against + * the counter. + * + *******************************************************************************/ + void CySysTimerSetMatch(uint32 counterNum, uint32 match) + { + uint32 regValue; + + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + /* Wait for previous changes to come into effect */ + CyDelayUs(CY_SYS_3TIMER_DELAY_US); + + regValue = CY_SYS_WCO_WDT_MATCH_REG; + regValue &= (uint32)~((uint32)(CY_SYS_TIMER_LOWER_16BITS_MASK << (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT))); + CY_SYS_WCO_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT))); + + /* Make sure match synchronization has started */ + CyDelayUs(CY_SYS_1TIMER_DELAY_US); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetToggleBit + ****************************************************************************//** + * + * \brief Configures which bit in Timer counter 2 to monitor for a toggle. + * + * When that bit toggles, an interrupt is generated if mode for counter 2 has + * enabled interrupts. + * + * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. + * + * \details Timer counter 2 should be disabled. Otherwise this function call has + * no effect. + * + * If the specified counter is enabled, call the CySysTimerDisable() function with + * the corresponding parameter to disable the specified counter and wait for it to + * stop. This may take up to three Timer source-cycles. + * + *******************************************************************************/ + void CySysTimerSetToggleBit(uint32 bits) + { + uint32 configRegValue; + + if (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; + configRegValue &= (uint32)(~((uint32)(CY_SYS_TIMER_CONFIG_BITS2_MASK << CY_SYS_TIMER_CONFIG_BITS2_POS))); + configRegValue |= ((bits & CY_SYS_TIMER_CONFIG_BITS2_MASK) << CY_SYS_TIMER_CONFIG_BITS2_POS); + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetToggleBit + ****************************************************************************//** + * + * \brief Reads which bit in Timer counter 2 is monitored for a toggle. + * + * \return The bit that is monitored (range of 0 to 31) + * + *******************************************************************************/ + uint32 CySysTimerGetToggleBit(void) + { + return ((CY_SYS_WCO_WDT_CONFIG_REG >> CY_SYS_TIMER_CONFIG_BITS2_POS) & CY_SYS_TIMER_CONFIG_BITS2_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetMatch + ****************************************************************************//** + * + * \brief Reads the Timer counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the DeepSleep Timer + * counter. The match values are not supported by counter 2. + * + * \return A 16-bit match value. + * + *******************************************************************************/ + uint32 CySysTimerGetMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + return ((uint32)(CY_SYS_WCO_WDT_MATCH_REG >> (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT)) & + CY_SYS_TIMER_LOWER_16BITS_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetCount + ****************************************************************************//** + * + * \brief Reads the current DeepSleep Timer counter value. + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters + * and counter 2 is a 32 bit counter. + * + *******************************************************************************/ + uint32 CySysTimerGetCount(uint32 counterNum) + { + uint32 regValue = 0u; + + switch(counterNum) + { + /* Timer Counter 0 */ + case 0u: + regValue = CY_SYS_WCO_WDT_CTRLOW_REG & CY_SYS_TIMER_LOWER_16BITS_MASK; + break; + + /* Timer Counter 1 */ + case 1u: + regValue = (CY_SYS_WCO_WDT_CTRLOW_REG >> CY_SYS_TIMER_CNT_MATCH_SHIFT) & CY_SYS_TIMER_LOWER_16BITS_MASK; + break; + + /* Timer Counter 2 */ + case 2u: + regValue = CY_SYS_WCO_WDT_CTRHIGH_REG; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + return (regValue); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetInterruptSource + ****************************************************************************//** + * + * \brief + * Reads a mask containing all the DeepSleep Timer counters interrupts that are + * currently set by the hardware, if a corresponding mode is selected. + * + * \return The mask of interrupts set + * \return CY_SYS_TIMER0_INT - Set interrupt for Counter 0 + * \return CY_SYS_TIMER1_INT - Set interrupt for Counter 1 + * \return CY_SYS_TIMER2_INT - Set interrupt for Counter 2 + * + *******************************************************************************/ + uint32 CySysTimerGetInterruptSource(void) + { + return (CY_SYS_WCO_WDT_CONTROL_REG & (CY_SYS_TIMER0_INT | CY_SYS_TIMER1_INT | CY_SYS_TIMER2_INT)); + } + + + /******************************************************************************* + * Function Name: CySysTimerClearInterrupt + ****************************************************************************//** + * + * \brief Clears all the DeepSleep Timer counter interrupts set in the mask. + * + * All the Timer interrupts are to be cleared by the firmware, otherwise + * interrupts are generated continuously. + * + * \param counterMask + * CY_SYS_TIMER0_INT - Clear counter 0
+ * CY_SYS_TIMER1_INT - Clear counter 1
+ * CY_SYS_TIMER2_INT - Clear counter 2 + * + *******************************************************************************/ + void CySysTimerClearInterrupt(uint32 counterMask) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + /* Set new WCO_TIMER control register value */ + counterMask &= (CY_SYS_TIMER0_INT | + CY_SYS_TIMER1_INT | + CY_SYS_TIMER2_INT); + + CY_SYS_WCO_WDT_CONTROL_REG = counterMask | (CY_SYS_WCO_WDT_CONTROL_REG & ~(CY_SYS_TIMER0_INT | + CY_SYS_TIMER1_INT | + CY_SYS_TIMER2_INT)); + + /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. + * Cypress ID #207093, #206231 + */ + (void)CY_SYS_WCO_WDT_CONTROL_REG; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetInterruptCallback + ****************************************************************************//** + * + * \brief + * Sets the ISR callback function for the particular DeepSleep Timer counter. + * + * These functions are called on the Timer interrupt. + * + * \param counterNum The number of the Timer counter. + * \param function The pointer to the callback function. + * + * \return The pointer to the previous callback function. + * \return NULL is returned if the specified address is not set. + * + *******************************************************************************/ + cyTimerCallback CySysTimerSetInterruptCallback(uint32 counterNum, cyTimerCallback function) + { + cyTimerCallback prevCallback = (void *)0; + + if(counterNum < CY_SYS_NUM_OF_TIMERS) + { + prevCallback = cySysTimerCallback[counterNum]; + cySysTimerCallback[counterNum] = function; + } + else + { + CYASSERT(0u != 0u); + } + + return((cyTimerCallback)prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetInterruptCallback + ****************************************************************************//** + * + * \brief Gets the ISR callback function for the particular DeepSleep Timer + * counter. + * + * \param counterNum The number of the Timer counter. + * + * \return + * The pointer to the callback function registered for a particular Timer by + * a particular address that are passed through arguments. + * + *******************************************************************************/ + cyTimerCallback CySysTimerGetInterruptCallback(uint32 counterNum) + { + cyTimerCallback retCallback = (void *)0; + + if(counterNum < CY_SYS_NUM_OF_TIMERS) + { + retCallback = (cyTimerCallback)cySysTimerCallback[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + + return(retCallback); + } + + + /******************************************************************************* + * Function Name: CySysTimerEnableIsr + ****************************************************************************//** + * + * \brief Enables the ISR callback servicing for the particular Timer counter + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * Value corresponds to appropriate Timer counter. For example value 1 + * corresponds to second Timer counter. + * + *******************************************************************************/ + void CySysTimerEnableIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_TIMER2) + { + disableTimerServicedIsr &= ~counterTimerIntMaskTbl[counterNum]; + timerIsrMask |= counterTimerIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerDisableIsr + ****************************************************************************//** + * + * \brief Disables the ISR callback servicing for the particular Timer counter + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + *******************************************************************************/ + void CySysTimerDisableIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_TIMER2) + { + timerIsrMask &= ~counterTimerIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerIsr + ****************************************************************************//** + * + * \brief This is the handler of the DeepSleep Timer interrupt in CPU NVIC. + * + * The handler checks which Timer triggered in the interrupt and calls the + * respective callback functions configured by the user by using + * CySysTimerSetIsrCallback() API. + * + * The order of the callback execution is incremental. Callback-0 is + * run as the first one and callback-2 is called as the last one. + * + * \details This function clears the DeepSleep Timer interrupt every time when + * it is called. + * + *******************************************************************************/ + void CySysTimerIsr(void) + { + if(0u != (CY_SYS_TIMER0_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER0_INT & timerIsrMask)) + { + timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER0_INT); + disableTimerServicedIsr &= ~CY_SYS_TIMER0_INT; + if(cySysTimerCallback[CY_SYS_TIMER0] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER0])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER0_INT); + } + + if(0u != (CY_SYS_TIMER1_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER1_INT & timerIsrMask)) + { + timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER1_INT); + disableTimerServicedIsr &= ~CY_SYS_TIMER1_INT; + if(cySysTimerCallback[CY_SYS_TIMER1] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER1])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER1_INT); + } + + if(0u != (CY_SYS_TIMER2_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER2_INT & timerIsrMask)) + { + if(cySysTimerCallback[CY_SYS_TIMER2] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER2])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER2_INT); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerResetCounters + ****************************************************************************//** + * + * \brief Resets all the Timer counters set in the mask. + * + * \param countersMask + * CY_SYS_TIMER0_RESET - Reset the Counter 0
+ * CY_SYS_TIMER1_RESET - Reset the Counter 1
+ * CY_SYS_TIMER2_RESET - Reset the Counter 2 + * + * \details + * This function waits while corresponding counters will be reset. This may + * take up to 3 DeepSleep Timer source-cycles. DeepSleep Timer source must be + * enabled. Otherwise, the function will never exit. + * + *******************************************************************************/ + void CySysTimerResetCounters(uint32 countersMask) + { + /* Set new Timer reset value */ + CY_SYS_WCO_WDT_CONTROL_REG |= (countersMask & CY_SYS_TIMER_RESET); + + while (0uL != (CY_SYS_WCO_WDT_CONTROL_REG & CY_SYS_TIMER_RESET)) + { + /* Wait for reset to come into effect */ + } + } +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + + +#if(CY_IP_SRSSV2 || (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT)) + /******************************************************************************* + * Function Name: CySysTimerDelay + ****************************************************************************//** + * + * \brief + * The function implements the delay specified in the LFCLK clock ticks. + * + * This API is applicable for PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / + * PSoC 4200 BLE / PRoC BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to + * use WDT. Also this API is available to use for PSoC4100S and / PSoC Analog + * Coprocessor devices to use DeepSleep Timers. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The specified WDT counter should be configured as described below and started. + * + * For PSoC 4100S / PSoC Analog Coprocessor devices: + * The specified DeepSleep Timer counter should be configured as described below + * and started. + * + * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In + * the "WAIT" mode, the function waits for the specified number of ticks. In the + * "INTERRUPT" mode, the interrupt is generated after the specified number of + * ticks. + * + * For the correct function operation, the "Clear On Match" option should be + * disabled for the specified WDT or DeepSleep Timer counter. Use + * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep + * Timer function with the "enable" parameter equal to zero for the used WDT + * counter or DeepSleep Timer counter. + * + * The corresponding WDT counter should be configured to match the selected + * mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. + * + * Or the corresponding DeepSleep Timer counter should be configured to match the + * selected mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" for the "INTERRUPT" mode. + * + * This can be configured in two ways: + * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." + * button, in the "Configure System Clocks" window click on the + * "Low Frequency Clocks" tab and choose the appropriate option for the used + * WDT or DeepSleep Timer counter. + * + * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep + * Timer function. Call it with the appropriate "mode" parameter for the + * used WDT or DeepSleep Timer counter. + * + * For the "INTERRUPT" mode, the recommended sequence is the following: + * - Call the CySysWdtDisableCounterIsr() for WDT or + * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing + * interrupts of the specified WDT or DeepSleep Timer counter. + * + * - Call the CySysWdtSetInterruptCallback() for WDT or + * CySysTimerSetIsrCallback() for DeepSleep Timer function to register + * the callback function for the corresponding WDT or DeepSleep Timer counter. + * + * - Call the CySysTimerDelay() function. + * + * \param counterNum Valid range [0-1]. The number of the counter + * (Timer0 or Timer1). + * \param delayType + * CY_SYS_TIMER_WAIT - "WAIT" mode.
+ * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. + * \param delay The delay value in the LFCLK ticks + * (allowable range - 16-bit value). + * + * \details + * In the "INTERRUPT" mode, this function enables ISR callback servicing + * from the corresponding WDT or DeepSleep Timer counter. Servicing of this ISR + * callback will be disabled after the expiration of the delay time. + * + *******************************************************************************/ + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay) + { + uint32 regValue; + uint32 matchValue; + + #if(CY_IP_SRSSV2) + if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) && + (delay <= CY_SYS_UINT16_MAX_VAL)) + { + regValue = CySysWdtGetCount(counterNum); + matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; + + CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) + if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && + (delay <= CY_SYS_UINT16_MAX_VAL)) + { + regValue = CySysTimerGetCount(counterNum); + matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; + + CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_WCO_WDT_EN) */ + } + + + /******************************************************************************* + * Function Name: CySysTimerDelayUntilMatch + ****************************************************************************//** + * + * \brief + * The function implements the delay specified as the number of WDT or DeepSleep + * Timer clock source ticks between WDT or DeepSleep Timer current value and + * match" value. + * + * This API is applicable for PSoC 4100 / PSoC 4200 / PRoC BLE / PSoC 4100 BLE / + * PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to use WDT. + * Also this API is available to use for PSoC4100S / Analog Coprocessor devices + * to use DeepSleep Timers. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The function implements the delay specified as the number of LFCLK ticks + * between the specified WDT counter's current value and the "match" + * passed as the parameter to this function. The current WDT counter value can + * be obtained using the CySysWdtGetCount() function. + * + * For PSoC4100 S and Analog Coprocessor devices: + * The function implements the delay specified as the number of DeepSleep Timer + * input clock ticks for Timer0/Timer1 counter's current value and the "match" + * passed as the parameter to this function. The current DeepSleep Timer counter + * value can be obtained using the CySysWdtGetCount() function. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The specified WDT counter should be configured as described below and started. + * + * For PSoC PSoC 4100S / PSoC Analog Coprocessor devices: + * The specified DeepSleep Timer counter should be configured as described below + * and started. + * + * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In + * the "WAIT" mode, the function waits for the specified number of ticks. In the + * "INTERRUPT" mode, the interrupt is generated after the specified number of + * ticks. + * + * For the correct function operation, the "Clear On Match" option should be + * disabled for the specified WDT or DeepSleep Timer counter. Use + * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep + * Timer function with the "enable" parameter equal to zero for the used WDT + * or DeepSleep Timer counter. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M/PSoC 4200M devices: + * The corresponding WDT counter should be configured to match the selected + * mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. + * + * For PSoC 4100S / PSoC Analog Coprocessor devices: + * Corresponding DeepSleep Timer counter should be configured to match the + * selected mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" for the "INTERRUPT" mode. + * + * This can be configured in two ways: + * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." + * button, in the "Configure System Clocks" window click on the + * "Low Frequency Clocks" tab and choose the appropriate option for the used + * WDT or DeepSleep Timer counter. + * + * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep + * Timer function. Call it with the appropriate "mode" parameter for the + * used WDT or DeepSleep Timer counter. + * + * For the "INTERRUPT" mode, the recommended sequence is the following: + * - Call the CySysWdtDisableCounterIsr() for WDT or + * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing + * interrupts of the specified WDT or DeepSleep Timer counter. + * + * - Call the CySysWdtSetInterruptCallback() for WDT or + * CySysTimerSetInterruptCallback() for DeepSleep Timer function to register + * the callback function for the corresponding WDT or DeepSleep Timer counter. + * + * - Call the CySysTimerDelay() function. + * + * \param counterNum Valid range [0-1]. The number of the WDT or DeepSleep + * Timer. + * counter (Timer0 or Timer1). + * \param delayType CY_SYS_TIMER_WAIT - "WAIT" mode.
+ * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. + * \param delay The delay value in the LFCLK ticks + * (allowable range - 16-bit value). + * + * \details + * In the "INTERRUPT" mode, this function enables ISR callback servicing + * from the corresponding WDT counter. Servicing of this ISR callback will be + * disabled after the expiration of the delay time. + * + *******************************************************************************/ + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match) + { + uint32 tmpValue; + + #if(CY_IP_SRSSV2) + if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) && + (match <= CY_SYS_UINT16_MAX_VAL)) + { + if(delayType == CY_SYS_TIMER_WAIT) + { + do + { + tmpValue = CySysWdtGetCount(counterNum); + }while(tmpValue > match); + + do + { + tmpValue = CySysWdtGetCount(counterNum); + }while(tmpValue < match); + } + else + { + tmpValue = counterIntMaskTbl[counterNum]; + CySysWdtSetMatch(counterNum, match); + + disableServicedIsr |= tmpValue; + wdtIsrMask |= tmpValue; + } + } + else + { + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) + if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && + (match <= CY_SYS_UINT16_MAX_VAL)) + { + if(delayType == CY_SYS_TIMER_WAIT) + { + do + { + tmpValue = CySysTimerGetCount(counterNum); + }while(tmpValue > match); + + do + { + tmpValue = CySysTimerGetCount(counterNum); + }while(tmpValue < match); + } + else + { + tmpValue = counterTimerIntMaskTbl[counterNum]; + CySysTimerSetMatch(counterNum, match); + + disableTimerServicedIsr |= tmpValue; + timerIsrMask |= tmpValue; + } + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) */ + } + +#endif /* (CY_IP_SRSSV2 || (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.h b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.h new file mode 100644 index 0000000..c3bf4f7 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLFClk.h @@ -0,0 +1,724 @@ +/***************************************************************************//** +* \file .h +* \version 1.20 +* +* \brief +* This file provides the source code to API for the lfclk and wdt. +* +******************************************************************************** +* \copyright +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_LFCLK_CYLIB_H) +#define CY_LFCLK_CYLIB_H + +#include "cytypes.h" +#include "cydevice_trm.h" + +#define CY_IP_WCO_WDT_EN (-1 == 1) + +typedef enum +{ + CY_SYS_TIMER_WAIT = 0u, + CY_SYS_TIMER_INTERRUPT = 1u +} cy_sys_timer_delaytype_enum; + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +/* Clocks API */ +void CySysClkIloStart(void); +void CySysClkIloStop(void); +/** @} general */ + +/** +* \addtogroup group_compensate +* @{ +*/ +cystatus CySysClkIloCompensate(uint32 desiredDelay, uint32 *compensatedCycles); +void CySysClkIloStartMeasurement(void); +void CySysClkIloStopMeasurement(void); +/** @} compensate */ + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + /** + * \addtogroup group_compensate + * @{ + */ + cystatus CySysClkIloTrim(uint32 mode, int32 *iloAccuracyInPPT); + cystatus CySysClkIloRestoreFactoryTrim(void); + /** @} compensate */ + cystatus CySysClkIloUpdateTrimReg(int32* iloAccuracyInPPT); +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + +#if(CY_IP_SRSSV2 && CY_IP_WCO) + /** + * \addtogroup group_general + * @{ + */ + void CySysClkSetLfclkSource(uint32 source); + /** @} group_general */ +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + +#if (CY_IP_WCO) + /** + * \addtogroup group_wco + * @{ + */ + void CySysClkWcoStart(void); + void CySysClkWcoStop(void); + uint32 CySysClkWcoSetPowerMode(uint32 mode); + void CySysClkWcoClockOutSelect(uint32 clockSel); + /** @} wco */ + + uint32 CySysClkWcoEnabled(void); + +#endif /* (CY_IP_WCO) */ + +typedef void (*cyWdtCallback)(void); + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + typedef void (*cyTimerCallback)(void); +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +#if(CY_IP_SRSSV2) + /** + * \addtogroup group_wdtsrssv2 + * @{ + */ + /* WDT API */ + void CySysWdtLock(void); + void CySysWdtUnlock(void); + void CySysWdtSetMode(uint32 counterNum, uint32 mode); + uint32 CySysWdtGetMode(uint32 counterNum); + uint32 CySysWdtGetEnabledStatus(uint32 counterNum); + void CySysWdtSetClearOnMatch(uint32 counterNum, uint32 enable); + uint32 CySysWdtGetClearOnMatch(uint32 counterNum); + void CySysWdtEnable(uint32 counterMask); + void CySysWdtDisable(uint32 counterMask); + void CySysWdtSetCascade(uint32 cascadeMask); + uint32 CySysWdtGetCascade(void); + void CySysWdtSetMatch(uint32 counterNum, uint32 match); + void CySysWdtSetToggleBit(uint32 bits); + uint32 CySysWdtGetToggleBit(void); + uint32 CySysWdtGetMatch(uint32 counterNum); + uint32 CySysWdtGetCount(uint32 counterNum); + uint32 CySysWdtGetInterruptSource(void); + void CySysWdtClearInterrupt(uint32 counterMask); + void CySysWdtResetCounters(uint32 countersMask); + cyWdtCallback CySysWdtSetInterruptCallback(uint32 counterNum, cyWdtCallback function); + cyWdtCallback CySysWdtGetInterruptCallback(uint32 counterNum); + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay); + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match); + void CySysWatchdogFeed(uint32 counterNum); + void CySysWdtEnableCounterIsr(uint32 counterNum); + void CySysWdtDisableCounterIsr(uint32 counterNum); + void CySysWdtIsr(void); + /** @} wdtsrssv2 */ +#else + /** + * \addtogroup group_wdtsrsslite + * @{ + */ + /* WDT API */ + uint32 CySysWdtGetEnabledStatus(void); + void CySysWdtEnable(void); + void CySysWdtDisable(void); + void CySysWdtSetMatch(uint32 match); + uint32 CySysWdtGetMatch(void); + uint32 CySysWdtGetCount(void); + void CySysWdtSetIgnoreBits(uint32 bitsNum); + uint32 CySysWdtGetIgnoreBits(void); + void CySysWdtClearInterrupt(void); + void CySysWdtMaskInterrupt(void); + void CySysWdtUnmaskInterrupt(void); + cyWdtCallback CySysWdtSetInterruptCallback(cyWdtCallback function); + cyWdtCallback CySysWdtGetInterruptCallback(void); + void CySysWdtIsr(void); + /** @} wdtsrsslite*/ +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + /** + * \addtogroup group_deepsleepwdt + * @{ + */ + /* WCO WDT APIs */ + void CySysClkSetTimerSource(uint32 source); + void CySysTimerSetMode(uint32 counterNum, uint32 mode); + uint32 CySysTimerGetMode(uint32 counterNum); + uint32 CySysTimerGetEnabledStatus(uint32 counterNum); + void CySysTimerSetClearOnMatch(uint32 counterNum, uint32 enable); + uint32 CySysTimerGetClearOnMatch(uint32 counterNum); + void CySysTimerEnable(uint32 counterMask); + void CySysTimerDisable(uint32 counterMask); + void CySysTimerSetCascade(uint32 cascadeMask); + uint32 CySysTimerGetCascade(void); + void CySysTimerSetMatch(uint32 counterNum, uint32 match); + void CySysTimerSetToggleBit(uint32 bits); + uint32 CySysTimerGetToggleBit(void); + uint32 CySysTimerGetMatch(uint32 counterNum); + uint32 CySysTimerGetCount(uint32 counterNum); + uint32 CySysTimerGetInterruptSource(void); + void CySysTimerClearInterrupt(uint32 counterMask); + cyTimerCallback CySysTimerSetInterruptCallback(uint32 counterNum, cyTimerCallback function); + cyTimerCallback CySysTimerGetInterruptCallback(uint32 counterNum); + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay); + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match); + void CySysTimerResetCounters(uint32 countersMask); + void CySysTimerEnableIsr(uint32 counterNum); + void CySysTimerDisableIsr(uint32 counterNum); + void CySysTimerIsr(void); + /** @} deepsleepwdt */ +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + + +/******************************************************************************* +* API Constants +*******************************************************************************/ +#define CY_SYS_UINT16_MAX_VAL (0xFFFFu) + + +/******************************************************************************* +* Clock API Constants +*******************************************************************************/ + +/* CySysClkIloStart()/CySysClkIloStop() - implementation definitions */ +#define CY_SYS_CLK_ILO_CONFIG_ENABLE ((uint32)(( uint32 )0x01u << 31u)) +#define CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK ((uint32)(( uint32 )0x0fu << 8u )) + +/* CySysClkIloCompensate() - one ILO clock in uS multiplied on thousand */ +#if (CY_IP_SRSSV2) + #define CY_SYS_CLK_ILO_PERIOD_PPH ((uint32) (0x0C35u)) +#else + #define CY_SYS_CLK_ILO_PERIOD_PPH ((uint32) (0x09C4u)) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkIloCompensate() - implementation definitions */ +#define CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK ((uint32)(( uint32 )0x01u << 31u)) +#define CY_SYS_CLK_ILO_DFT_LSB_MASK ((uint32)(0x00000FFFu)) +#define CY_SYS_CLK_TRIM_OR_COMP_STARTED (1u) +#define CY_SYS_CLK_TRIM_OR_COMP_FINISHED (0u) +#define CY_SYS_CLK_COEF_PHUNDRED ((uint32) (0x64u)) +#define CY_SYS_CLK_HALF_OF_CLOCK ((uint32) ((uint32) CY_SYS_CLK_ILO_PERIOD_PPH >> 2u)) + +/* CySysClkIloCompensate() - maximum value of desiredDelay argument */ +#if (CY_IP_SRSSV2) + #define CY_SYS_CLK_MAX_DELAY_US ((uint32) (0xEE6B2800u)) + #define CY_SYS_CLK_ILO_PERIOD ((uint32) (0x1Fu)) + #define CY_SYS_CLK_ILO_FREQ_2MSB ((uint32) 5u) +#else + #define CY_SYS_CLK_MAX_DELAY_US ((uint32) (0x1E8480u)) + #define CY_SYS_CLK_ILO_FREQ_2MSB ((uint32) (0x28u )) + + /********************************************************************************** + * CySysClkIloCompensate() - value to walk over oversamling in calculations with + * srsslite. The oversample can be obtained when ilo frequency in equal 80 KHz and + * desired clocks are 80 000 clocks. + **********************************************************************************/ + #define CY_SYS_CLK_MAX_LITE_NUMBER ((uint32) 53600u) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_CLK_ILO_FREQ_3LSB ((uint32) (0x3E8u)) +#define CY_SYS_CLK_DELAY_COUNTS_LIMIT ((uint32) (0xD160u)) +#define CY_SYS_CLK_MIN_DELAY_US ((uint32) (0x64u)) + +/* CySysClkSetLfclkSource() - parameter definitions */ +#if (CY_IP_SRSSV2 && CY_IP_WCO) + + /** Internal Low Frequency (32 kHz) Oscillator (ILO) */ + #define CY_SYS_CLK_LFCLK_SRC_ILO (0u) + + /** Low Frequency Watch Crystal Oscillator (WCO) */ + #define CY_SYS_CLK_LFCLK_SRC_WCO ((uint32)(( uint32 )0x01u << 30u)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + + +#if (CY_IP_WCO) + + /* CySysClkSetLfclkSource() - implementation definitions */ + #define CY_SYS_CLK_LFCLK_SEL_MASK ((uint32)(( uint32 )0x03u << 30u)) +#endif /* (CY_IP_WCO) */ + +/* CySysClkSetTimerSource() - implementation definitions */ +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + #define CY_SYS_CLK_TIMER_SEL_MASK ((uint32)(( uint32 )0x03u << 30u)) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkSetTimerSource() - parameter definitions */ +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + /** Internal Low Frequency (32 kHz) Oscillator (ILO) */ + #define CY_SYS_CLK_TIMER_SRC_ILO (0u) + + /** Low Frequency Watch Crystal Oscillator (WCO) */ + #define CY_SYS_CLK_TIMER_SRC_WCO ((uint32)(( uint32 )0x01u << 30u)) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkWcoClockOutSelect() - parameter definitions */ +#if (CY_IP_WCO) + + /** Selects External crystal as WCO’s clock source */ + #define CY_SYS_CLK_WCO_SEL_CRYSTAL (1u) + + /** Selects External clock input on wco_in pin as WCO’s clock source */ + #define CY_SYS_CLK_WCO_SEL_PIN (0u) +#endif /* (CY_IP_WCO) */ + +/* CySysClkWcoClockOutSelect() - implementation definitions */ +#if (CY_IP_WCO) + #define CY_SYS_CLK_WCO_SELECT_PIN_MASK ((uint32)(( uint32 )0x01u << 2u)) + #define CY_SYS_CLK_WCO_SELECT_PIN_OFFSET ((uint32) 0x02u) +#endif /* (CY_IP_WCO) */ + +/* CySysClkIloRestoreFactoryTrim() - implementation definitions */ +#if (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) + #define CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE ((uint8 )(0xF0u)) + #define CY_SYS_CLK_ILO_TRIM_DEFAULT_MASK ((uint32)((uint32)0x01u << 3u)) + #define CY_SYS_CLK_ILO_TRIM_MASK ((uint32)(0x0Fu)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) */ + +/* CySysIloTrim() - parameter definitions and macros*/ +#if (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) + #define CY_SYS_CLK_BLOCKING (0u) + #define CY_SYS_CLK_NON_BLOCKING (1u) + #define CY_SYS_CLK_PERTHOUSAND ((uint32) 0x000003E8u ) + #define CY_SYS_CLK_ABS_MACRO(x) ((0 > (x)) ? (-(x)) : (x)) + #define CY_SYS_CLK_ERROR_RANGE ((uint32) 0x38u) + #define CY_SYS_CLK_TIMEOUT ((uint8 ) 0x05u) + + /* ILO error step is 7,37 % error range */ + #define CY_SYS_CLK_ERROR_STEP (( int32) 0x02E1u) + #define CY_SYS_CLK_ERROR_COEF ((uint32) 0x0Au) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) */ + +#if (CY_IP_WCO) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_LPM_EN (( uint32 )(( uint32 )0x01u << 0u)) + #define CY_SYS_CLK_WCO_CONFIG_LPM_AUTO (( uint32 )(( uint32 )0x01u << 1u)) + #define CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE (( uint32 )(( uint32 )0x01u << 31u)) + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_OUT_BLNK_A (( uint32 )(( uint32 )0x01u << 0u)) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_XGM_MASK (( uint32 ) 0x07u) + #define CY_SYS_CLK_WCO_TRIM_XGM_SHIFT (( uint32 ) 0x00u) + + #define CY_SYS_CLK_WCO_TRIM_XGM_3370NA (( uint32 ) 0x00u) + #define CY_SYS_CLK_WCO_TRIM_XGM_2620NA (( uint32 ) 0x01u) + #define CY_SYS_CLK_WCO_TRIM_XGM_2250NA (( uint32 ) 0x02u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1500NA (( uint32 ) 0x03u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1870NA (( uint32 ) 0x04u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1120NA (( uint32 ) 0x05u) + #define CY_SYS_CLK_WCO_TRIM_XGM_750NA (( uint32 ) 0x06u) + #define CY_SYS_CLK_WCO_TRIM_XGM_0NA (( uint32 ) 0x07u) + + #define CY_SYS_CLK_WCO_TRIM_GM_MASK (( uint32 )(( uint32 )0x03u << 4u)) + #define CY_SYS_CLK_WCO_TRIM_GM_SHIFT (( uint32 ) 0x04u) + #define CY_SYS_CLK_WCO_TRIM_GM_HPM (( uint32 ) 0x01u) + #define CY_SYS_CLK_WCO_TRIM_GM_LPM (( uint32 ) 0x02u) +#endif /* (CY_IP_WCO) */ + + +/******************************************************************************* +* WDT API Constants +*******************************************************************************/ +#if(CY_IP_SRSSV2) + + #define CY_SYS_WDT_MODE_NONE (0u) + #define CY_SYS_WDT_MODE_INT (1u) + #define CY_SYS_WDT_MODE_RESET (2u) + #define CY_SYS_WDT_MODE_INT_RESET (3u) + + #define CY_SYS_WDT_COUNTER0_MASK ((uint32)((uint32)0x01u)) /**< Counter 0 */ + #define CY_SYS_WDT_COUNTER1_MASK ((uint32)((uint32)0x01u << 8u)) /**< Counter 1 */ + #define CY_SYS_WDT_COUNTER2_MASK ((uint32)((uint32)0x01u << 16u)) /**< Counter 2 */ + + #define CY_SYS_WDT_CASCADE_NONE ((uint32)0x00u) /**< Neither */ + #define CY_SYS_WDT_CASCADE_01 ((uint32)0x01u << 3u) /**< Cascade 01 */ + #define CY_SYS_WDT_CASCADE_12 ((uint32)0x01u << 11u) /**< Cascade 12 */ + + #define CY_SYS_WDT_COUNTER0_INT ((uint32)0x01u << 2u) + #define CY_SYS_WDT_COUNTER1_INT ((uint32)0x01u << 10u) + #define CY_SYS_WDT_COUNTER2_INT ((uint32)0x01u << 18u) + + #define CY_SYS_WDT_COUNTER0_RESET ((uint32)0x01u << 3u) /**< Counter 0 */ + #define CY_SYS_WDT_COUNTER1_RESET ((uint32)0x01u << 11u) /**< Counter 1 */ + #define CY_SYS_WDT_COUNTER2_RESET ((uint32)0x01u << 19u) /**< Counter 2 */ + + #define CY_SYS_WDT_COUNTERS_RESET (CY_SYS_WDT_COUNTER0_RESET |\ + CY_SYS_WDT_COUNTER1_RESET |\ + CY_SYS_WDT_COUNTER2_RESET) + + #define CY_SYS_WDT_COUNTER0 (0x00u) + #define CY_SYS_WDT_COUNTER1 (0x01u) + #define CY_SYS_WDT_COUNTER2 (0x02u) + + #define CY_SYS_WDT_COUNTER0_OFFSET (0x00u) + #define CY_SYS_WDT_COUNTER1_OFFSET (0x02u) + #define CY_SYS_WDT_COUNTER2_OFFSET (0x04u) + + #define CY_SYS_WDT_MODE_MASK ((uint32)(0x03u)) + + #define CY_SYS_WDT_CONFIG_BITS2_MASK (uint32)(0x1Fu) + #define CY_SYS_WDT_CONFIG_BITS2_POS (uint32)(24u) + #define CY_SYS_WDT_LOWER_16BITS_MASK (uint32)(0x0000FFFFu) + #define CY_SYS_WDT_HIGHER_16BITS_MASK (uint32)(0xFFFF0000u) + #define CY_SYS_WDT_COUNTERS_MAX (0x03u) + #define CY_SYS_WDT_CNT_SHIFT (0x08u) + #define CY_SYS_WDT_CNT_MATCH_CLR_SHIFT (0x02u) + #define CY_SYS_WDT_CNT_STTS_SHIFT (0x01u) + #define CY_SYS_WDT_CNT_MATCH_SHIFT (0x10u) + + #define CY_SYS_WDT_CLK_LOCK_BITS_MASK ((uint32)0x03u << 14u) + #define CY_SYS_WDT_CLK_LOCK_BIT0 ((uint32)0x01u << 14u) + #define CY_SYS_WDT_CLK_LOCK_BIT1 ((uint32)0x01u << 15u) + + #define CY_WDT_NUM_OF_WDT (3u) + #define CY_WDT_NUM_OF_CALLBACKS (3u) + + #else + #define CY_WDT_NUM_OF_WDT (1u) + #define CY_WDT_NUM_OF_CALLBACKS (3u) + #define CY_SYS_WDT_KEY ((uint32)(0xACED8865u)) + #define CY_SYS_WDT_MATCH_MASK ((uint32)(0x0000FFFFu)) + #define CY_SYS_WDT_IGNORE_BITS_MASK ((uint32)(0x000F0000u)) + #define CY_SYS_WDT_IGNORE_BITS_SHIFT ((uint32)(16u)) + #define CY_SYS_WDT_LOWER_BIT_MASK ((uint32)(0x00000001u)) + + #define CY_SYS_WDT_COUNTER0 (0x00u) + +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSV2 && CY_IP_WCO) + #define CY_SYS_WDT_1LFCLK_ILO_DELAY_US ((uint16)( 67u)) + #define CY_SYS_WDT_3LFCLK_ILO_DELAY_US ((uint16)(201u)) + #define CY_SYS_WDT_1LFCLK_WCO_DELAY_US ((uint16)( 31u)) + #define CY_SYS_WDT_3LFCLK_WCO_DELAY_US ((uint16)( 93u)) + + #define CY_SYS_WDT_1LFCLK_DELAY_US \ + ((CY_SYS_CLK_LFCLK_SRC_ILO == (CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK)) ? \ + (CY_SYS_WDT_1LFCLK_ILO_DELAY_US) : \ + (CY_SYS_WDT_1LFCLK_WCO_DELAY_US)) + + #define CY_SYS_WDT_3LFCLK_DELAY_US \ + ((CY_SYS_CLK_LFCLK_SRC_ILO == (CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK)) ? \ + (CY_SYS_WDT_3LFCLK_ILO_DELAY_US) : \ + (CY_SYS_WDT_3LFCLK_WCO_DELAY_US)) + #else + #define CY_SYS_WDT_1LFCLK_DELAY_US ((uint16) (67u)) + #define CY_SYS_WDT_3LFCLK_DELAY_US ((uint16) (201u)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + #define CY_SYS_TIMER_MODE_NONE (0u) + #define CY_SYS_TIMER_MODE_INT (1u) + + #define CY_SYS_TIMER0_MASK ((uint32)((uint32)0x01u)) /**< Counter 0 */ + #define CY_SYS_TIMER1_MASK ((uint32)((uint32)0x01u << 8u)) /**< Counter 1 */ + #define CY_SYS_TIMER2_MASK ((uint32)((uint32)0x01u << 16u)) /**< Counter 2 */ + + #define CY_SYS_TIMER0_RESET ((uint32)0x01u << 3u) /**< Counter 0 */ + #define CY_SYS_TIMER1_RESET ((uint32)0x01u << 11u) /**< Counter 1 */ + #define CY_SYS_TIMER2_RESET ((uint32)0x01u << 19u) /**< Counter 2 */ + + #define CY_SYS_TIMER_RESET (CY_SYS_TIMER0_RESET |\ + CY_SYS_TIMER1_RESET |\ + CY_SYS_TIMER2_RESET) + + #define CY_SYS_TIMER_CASCADE_NONE ((uint32)0x00u) /**< Neither */ + #define CY_SYS_TIMER_CASCADE_01 ((uint32)0x01u << 3u) /**< Cascade 01 */ + #define CY_SYS_TIMER_CASCADE_12 ((uint32)0x01u << 11u) /**< Cascade 12 */ + + #define CY_SYS_TIMER0_INT ((uint32)0x01u << 2u) + #define CY_SYS_TIMER1_INT ((uint32)0x01u << 10u) + #define CY_SYS_TIMER2_INT ((uint32)0x01u << 18u) + + #define CY_SYS_TIMER0 (0x00u) + #define CY_SYS_TIMER1 (0x01u) + #define CY_SYS_TIMER2 (0x02u) + + #define CY_SYS_TIMER_MODE_MASK ((uint32)(0x01u)) + + #define CY_SYS_TIMER_CONFIG_BITS2_MASK (uint32)(0x1Fu) + #define CY_SYS_TIMER_CONFIG_BITS2_POS (uint32)(24u) + #define CY_SYS_TIMER_LOWER_16BITS_MASK (uint32)(0x0000FFFFu) + #define CY_SYS_TIMER_HIGHER_16BITS_MASK (uint32)(0xFFFF0000u) + #define CY_SYS_TIMER_COUNTERS_MAX (0x03u) + #define CY_SYS_TIMER_CNT_SHIFT (0x08u) + #define CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT (0x02u) + #define CY_SYS_TIMER_CNT_STTS_SHIFT (0x01u) + #define CY_SYS_TIMER_CNT_MATCH_SHIFT (0x10u) + + #define CY_SYS_NUM_OF_TIMERS (3u) + + #define CY_SYS_SET_NEW_TIMER_SOURCE_ILO ((uint16)(0x02u)) + #define CY_SYS_SET_NEW_TIMER_SOURCE_WCO ((uint16)(0x01u)) + #define CY_SYS_WCO_WDT_CLKEN_RESET_MASK ((uint32)(0x03u)) + + #define CY_SYS_TIMER_1ILO_DELAY_US ((uint16)( 67u)) + #define CY_SYS_TIMER_4ILO_DELAY_US ((uint16)(268u)) + #define CY_SYS_TIMER_3ILO_DELAY_US ((uint16)(201u)) + + #define CY_SYS_TIMER_1WCO_DELAY_US ((uint16)( 31u)) + #define CY_SYS_TIMER_4WCO_DELAY_US ((uint16)(124u)) + #define CY_SYS_TIMER_3WCO_DELAY_US ((uint16)( 93u)) + + #define CY_SYS_1TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_1ILO_DELAY_US) : \ + (CY_SYS_TIMER_1WCO_DELAY_US)) + + #define CY_SYS_4TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_4WCO_DELAY_US) : \ + (CY_SYS_TIMER_4ILO_DELAY_US)) + + #define CY_SYS_3TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_3ILO_DELAY_US) : \ + (CY_SYS_TIMER_3WCO_DELAY_US)) + + #define CY_SYS_SET_CURRENT_TIMER_SOURCE_BIT \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_SET_NEW_TIMER_SOURCE_ILO) : \ + (CY_SYS_SET_NEW_TIMER_SOURCE_WCO)) + +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkWcoSetPowerMode() */ +#define CY_SYS_CLK_WCO_HPM (0x0u) /**< WCO High power mode */ + +#if(CY_IP_BLESS) + #define CY_SYS_CLK_WCO_LPM (0x1u) /**< WCO Low power mode */ +#endif /* (CY_IP_BLESS) */ + + +/******************************************************************************* +* Trim Registers Constants +********************************************************************************/ +#define CY_SYS_CLK_SYS_CLK_DEVIDER ((uint32)0x0Au) +#define CY_SYS_CLK_SEL_ILO_DFT_SOURCE ((uint32)0x00000100u) +#define CY_SYS_CLK_FOURBITS_MAX (( int32)0x0f) +#define CY_SYS_CLK_HALF_OF_STEP (( int32)((uint32) CY_SYS_CLK_ERROR_STEP >> 1u)) + +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_ILO_DESIRED_FREQ_HZ (32000u) + #define CY_SYS_CLK_DFT_SELSIZE ((uint32) 0x3F) +#else + #define CY_SYS_CLK_ILO_DESIRED_FREQ_HZ (40000u) + #define CY_SYS_CLK_DFT_SELSIZE ((uint32) 0x0F) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK ((uint32)((CY_SYS_CLK_DFT_SELSIZE << 8u) | (CY_SYS_CLK_DFT_SELSIZE ))) +#define CY_SYS_TST_DDFT_SELECT_CLK1 ((uint32) ((uint32) CYDEV_DFT_SELECT_CLK1 << 8u)) +#define CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1 ((uint32) (CY_SYS_TST_DDFT_SELECT_CLK1 | CYDEV_DFT_SELECT_CLK0)) + + +/******************************************************************************* +* Trim Registers +********************************************************************************/ +/* DFT TST Control Register*/ +#define CY_SYS_TST_DDFT_CTRL_REG (*(reg32*) CYREG_TST_DDFT_CTRL) +#define CY_SYS_CNT_CTRL_PTR ( (reg32*) CYREG_TST_DDFT_CTRL) + +/* DFT TST Counter 1 Register*/ +#define CY_SYS_CNT_REG1_REG (*(reg32*) CYREG_TST_TRIM_CNTR1) +#define CY_SYS_CNT_REG1_PTR ( (reg32*) CYREG_TST_TRIM_CNTR1) + +/* DFT TST Counter 2 Register*/ +#define CY_SYS_CNT_REG2_REG (*(reg32*) CYREG_TST_TRIM_CNTR2) +#define CY_SYS_CNT_REG2_PTR ( (reg32*) CYREG_TST_TRIM_CNTR2) + +/* DFT Muxes Configuration Register*/ +#define CY_SYS_CLK_DFT_REG (*(reg32*) CYREG_CLK_DFT_SELECT) +#define CY_SYS_CLK_DFT_PTR ( (reg32*) CYREG_CLK_DFT_SELECT) + +/* ILO Configuration Register*/ +#define CY_SYS_CLK_ILO_CONFIG_REG (*(reg32 *) CYREG_CLK_ILO_CONFIG) +#define CY_SYS_CLK_ILO_CONFIG_PTR ( (reg32 *) CYREG_CLK_ILO_CONFIG) + +/* ILO Trim Register*/ +#if(CY_IP_SRSSV2 && CY_IP_WCO) + #define CY_SYS_CLK_ILO_TRIM_REG (*(reg32 *) CYREG_CLK_ILO_TRIM) + #define CY_SYS_CLK_ILO_TRIM_PTR ( (reg32 *) CYREG_CLK_ILO_TRIM) +#endif /* (CY_IP_SRSSV2) && CY_IP_WCO*/ + +#if (CY_IP_WCO) + #if (CY_IP_BLESS) + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_STATUS) + #define CY_SYS_CLK_WCO_STATUS_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_STATUS) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_CONFIG) + #define CY_SYS_CLK_WCO_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_CONFIG) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_TRIM) + #define CY_SYS_CLK_WCO_TRIM_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_TRIM) + #else + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_REG (*(reg32 *) CYREG_WCO_STATUS) + #define CY_SYS_CLK_WCO_STATUS_PTR ( (reg32 *) CYREG_WCO_STATUS) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_REG (*(reg32 *) CYREG_WCO_CONFIG) + #define CY_SYS_CLK_WCO_CONFIG_PTR ( (reg32 *) CYREG_WCO_CONFIG) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_REG (*(reg32 *) CYREG_WCO_TRIM) + #define CY_SYS_CLK_WCO_TRIM_PTR ( (reg32 *) CYREG_WCO_TRIM) + #endif /* (CY_IP_BLESS) */ +#endif /* (CY_IP_WCO) */ + + +/******************************************************************************* +* WDT API Registers +*******************************************************************************/ +#if(CY_IP_SRSSV2) + #define CY_SYS_WDT_CTRLOW_REG (*(reg32 *) CYREG_WDT_CTRLOW) + #define CY_SYS_WDT_CTRLOW_PTR ( (reg32 *) CYREG_WDT_CTRLOW) + + #define CY_SYS_WDT_CTRHIGH_REG (*(reg32 *) CYREG_WDT_CTRHIGH) + #define CY_SYS_WDT_CTRHIGH_PTR ( (reg32 *) CYREG_WDT_CTRHIGH) + + #define CY_SYS_WDT_MATCH_REG (*(reg32 *) CYREG_WDT_MATCH) + #define CY_SYS_WDT_MATCH_PTR ( (reg32 *) CYREG_WDT_MATCH) + + #define CY_SYS_WDT_CONFIG_REG (*(reg32 *) CYREG_WDT_CONFIG) + #define CY_SYS_WDT_CONFIG_PTR ( (reg32 *) CYREG_WDT_CONFIG) + + #define CY_SYS_WDT_CONTROL_REG (*(reg32 *) CYREG_WDT_CONTROL) + #define CY_SYS_WDT_CONTROL_PTR ( (reg32 *) CYREG_WDT_CONTROL) +#else + #define CY_SYS_WDT_DISABLE_KEY_REG (*(reg32 *) CYREG_WDT_DISABLE_KEY) + #define CY_SYS_WDT_DISABLE_KEY_PTR ( (reg32 *) CYREG_WDT_DISABLE_KEY) + + #define CY_SYS_WDT_MATCH_REG (*(reg32 *) CYREG_WDT_MATCH) + #define CY_SYS_WDT_MATCH_PTR ( (reg32 *) CYREG_WDT_MATCH) + + #define CY_SYS_WDT_COUNTER_REG (*(reg32 *) CYREG_WDT_COUNTER) + #define CY_SYS_WDT_COUNTER_PTR ( (reg32 *) CYREG_WDT_COUNTER) + + #define CY_SYS_SRSS_INTR_REG (*(reg32 *) CYREG_SRSS_INTR) + #define CY_SYS_SRSS_INTR_PTR ( (reg32 *) CYREG_SRSS_INTR) + + #define CY_SYS_SRSS_INTR_MASK_REG (*(reg32 *) CYREG_SRSS_INTR_MASK) + #define CY_SYS_SRSS_INTR_MASK_PTR ( (reg32 *) CYREG_SRSS_INTR_MASK) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + #define CY_SYS_WCO_WDT_CTRLOW_REG (*(reg32 *) CYREG_WCO_WDT_CTRLOW) + #define CY_SYS_WCO_WDT_CTRLOW_PTR ( (reg32 *) CYREG_WCO_WDT_CTRLOW) + + #define CY_SYS_WCO_WDT_CTRHIGH_REG (*(reg32 *) CYREG_WCO_WDT_CTRHIGH) + #define CY_SYS_WCO_WDT_CTRHIGH_PTR ( (reg32 *) CYREG_WCO_WDT_CTRHIGH) + + #define CY_SYS_WCO_WDT_MATCH_REG (*(reg32 *) CYREG_WCO_WDT_MATCH) + #define CY_SYS_WCO_WDT_MATCH_PTR ( (reg32 *) CYREG_WCO_WDT_MATCH) + + #define CY_SYS_WCO_WDT_CONFIG_REG (*(reg32 *) CYREG_WCO_WDT_CONFIG) + #define CY_SYS_WCO_WDT_CONFIG_PTR ( (reg32 *) CYREG_WCO_WDT_CONFIG) + + #define CY_SYS_WCO_WDT_CONTROL_REG (*(reg32 *) CYREG_WCO_WDT_CONTROL) + #define CY_SYS_WCO_WDT_CONTROL_PTR ( (reg32 *) CYREG_WCO_WDT_CONTROL) + + #define CY_SYS_WCO_WDT_CLKEN_REG (*(reg32 *) CYREG_WCO_WDT_CLKEN) + #define CY_SYS_WCO_WDT_CLKEN_PTR ( (reg32 *) CYREG_WCO_WDT_CLKEN) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +#if (CY_IP_WCO) + + /******************************************************************************* + * Function Name: CySysClkWcoSetHighPowerMode + ******************************************************************************** + * + * Summary: + * Sets the high power mode for the 32 KHz WCO. + * + *******************************************************************************/ + static CY_INLINE void CySysClkWcoSetHighPowerMode(void) + { + /* Switch off low power mode for WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_EN; + + /* Switch off auto low power mode in WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= ((uint32)~CY_SYS_CLK_WCO_CONFIG_LPM_AUTO); + + /* Restore WCO trim register HPM settings */ + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_GM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_GM_HPM << CY_SYS_CLK_WCO_TRIM_GM_SHIFT); + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_XGM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_XGM_2620NA << CY_SYS_CLK_WCO_TRIM_XGM_SHIFT); + } + + #if(CY_IP_BLESS) + /******************************************************************************* + * Function Name: CySysClkWcoSetLowPowerMode + ******************************************************************************** + * + * Summary: + * Sets the low power mode for the 32 KHz WCO. + * + * Note LPM available only for PSoC 4100 BLE / PSoC4 4200 BLE + *******************************************************************************/ + static CY_INLINE void CySysClkWcoSetLowPowerMode(void) + { + /* Switch off auto low power mode in WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= ((uint32)~CY_SYS_CLK_WCO_CONFIG_LPM_AUTO); + + /* Change WCO trim register settings to LPM */ + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_XGM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_XGM_2250NA << CY_SYS_CLK_WCO_TRIM_XGM_SHIFT); + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_GM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_GM_LPM << CY_SYS_CLK_WCO_TRIM_GM_SHIFT); + + /* Switch on low power mode for WCO */ + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_LPM_EN; + } + #endif /* (CY_IP_BLESS) */ + +#endif /* (CY_IP_WCO) */ + + +/* These defines are intended to maintain the backward compatibility for + * projects which use cy_boot_v4_20 or earlier. +*/ +#define CySysWdtWriteMode CySysWdtSetMode +#define CySysWdtReadMode CySysWdtGetMode +#define CySysWdtWriteClearOnMatch CySysWdtSetClearOnMatch +#define CySysWdtReadClearOnMatch CySysWdtGetClearOnMatch +#define CySysWdtReadEnabledStatus CySysWdtGetEnabledStatus +#define CySysWdtWriteCascade CySysWdtSetCascade +#define CySysWdtReadCascade CySysWdtGetCascade +#define CySysWdtWriteMatch CySysWdtSetMatch +#define CySysWdtWriteToggleBit CySysWdtSetToggleBit +#define CySysWdtReadToggleBit CySysWdtGetToggleBit +#define CySysWdtReadMatch CySysWdtGetMatch +#define CySysWdtReadCount CySysWdtGetCount +#define CySysWdtWriteIgnoreBits CySysWdtSetIgnoreBits +#define CySysWdtReadIgnoreBits CySysWdtGetIgnoreBits +#define CySysWdtSetIsrCallback CySysWdtSetInterruptCallback +#define CySysWdtGetIsrCallback CySysWdtGetInterruptCallback + +#endif /* (CY_LFCLK_CYLIB_H) */ + +/* [] END OF FILE */ diff --git a/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.c b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.c new file mode 100644 index 0000000..75d5292 --- /dev/null +++ b/TrainingProjects/ADC-UART.cydsn/Generated_Source/PSoC4/CyLib.c @@ -0,0 +1,3504 @@ +/***************************************************************************//** +* \file CyLib.c +* \version 5.70 +* +* \brief Provides a system API for the Clocking, Interrupts, SysTick, and +* Voltage Detect. +* +* \note Documentation of the API's in this file is located in the PSoC 4 System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + +/* CySysClkWriteImoFreq() || CySysClkImoEnableWcoLock() */ +#if ((CY_IP_SRSSV2 && CY_IP_FMLT) || CY_IP_IMO_TRIMMABLE_BY_WCO) + #include "CyFlash.h" +#endif /* (CY_IP_SRSSV2 && CY_IP_FMLT) */ + +/* Do not use these definitions directly in your application */ +uint32 cydelayFreqHz = CYDEV_BCLK__SYSCLK__HZ; +uint32 cydelayFreqKhz = (CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; +uint8 cydelayFreqMhz = (uint8)((CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); +uint32 cydelay32kMs = CY_DELAY_MS_OVERFLOW * ((CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD); + + +static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; +static void CySysTickServiceCallbacks(void); + +#if (CY_IP_PLL) + static uint32 CySysClkPllGetBypassMode(uint32 pll); + static cystatus CySysClkPllConfigChangeAllowed(uint32 pll); +#endif /* (CY_IP_PLL) */ + + +/***************************************************************************//** +* Indicates whether or not the SysTick has been initialized. The variable is +* initialized to 0 and set to 1 the first time CySysTickStart() is called. +* +* This allows the component to restart without reinitialization after the first +* call to the CySysTickStart() routine. +* +* If reinitialization of the SysTick is required, call CySysTickInit() before +* calling CySysTickStart(). Alternatively, the SysTick can be reinitialized by +* calling the CySysTickInit() and CySysTickEnable() functions. +*******************************************************************************/ +uint32 CySysTickInitVar = 0u; + + +#if(CY_IP_SRSSV2) + /* Conversion between CySysClkWriteImoFreq() parameter and register's value */ + const uint8 cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_FREQ_TABLE_SIZE] = { + /* 3 MHz */ 0x03u, /* 4 MHz */ 0x04u, /* 5 MHz */ 0x05u, /* 6 MHz */ 0x06u, + /* 7 MHz */ 0x07u, /* 8 MHz */ 0x08u, /* 9 MHz */ 0x09u, /* 10 MHz */ 0x0Au, + /* 11 MHz */ 0x0Bu, /* 12 MHz */ 0x0Cu, /* 13 MHz */ 0x0Eu, /* 14 MHz */ 0x0Fu, + /* 15 MHz */ 0x10u, /* 16 MHz */ 0x11u, /* 17 MHz */ 0x12u, /* 18 MHz */ 0x13u, + /* 19 MHz */ 0x14u, /* 20 MHz */ 0x15u, /* 21 MHz */ 0x16u, /* 22 MHz */ 0x17u, + /* 23 MHz */ 0x18u, /* 24 MHz */ 0x19u, /* 25 MHz */ 0x1Bu, /* 26 MHz */ 0x1Cu, + /* 27 MHz */ 0x1Du, /* 28 MHz */ 0x1Eu, /* 29 MHz */ 0x1Fu, /* 30 MHz */ 0x20u, + /* 31 MHz */ 0x21u, /* 32 MHz */ 0x22u, /* 33 MHz */ 0x23u, /* 34 MHz */ 0x25u, + /* 35 MHz */ 0x26u, /* 36 MHz */ 0x27u, /* 37 MHz */ 0x28u, /* 38 MHz */ 0x29u, + /* 39 MHz */ 0x2Au, /* 40 MHz */ 0x2Bu, /* 41 MHz */ 0x2Eu, /* 42 MHz */ 0x2Fu, + /* 43 MHz */ 0x30u, /* 44 MHz */ 0x31u, /* 45 MHz */ 0x32u, /* 46 MHz */ 0x33u, + /* 47 MHz */ 0x34u, /* 48 MHz */ 0x35u }; +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* Conversion between IMO frequency and WCO DPLL max offset steps */ + const uint8 cyImoFreqMhz2DpllOffset[CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE] = { + /* 26 MHz */ 238u, /* 27 MHz */ 219u, /* 28 MHz */ 201u, /* 29 MHz */ 185u, + /* 30 MHz */ 170u, /* 31 MHz */ 155u, /* 32 MHz */ 142u, /* 33 MHz */ 130u, + /* 34 MHz */ 118u, /* 35 MHz */ 107u, /* 36 MHz */ 96u, /* 37 MHz */ 86u, + /* 38 MHz */ 77u, /* 39 MHz */ 68u, /* 40 MHz */ 59u, /* 41 MHz */ 51u, + /* 42 MHz */ 44u, /* 43 MHz */ 36u, /* 44 MHz */ 29u, /* 45 MHz */ 23u, + /* 46 MHz */ 16u, /* 47 MHz */ 10u, /* 48 MHz */ 4u }; +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + +/* Stored CY_SYS_CLK_IMO_TRIM4_REG when modified for USB lock */ +#if (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSV2) + uint32 CySysClkImoTrim4 = 0u; + uint32 CySysClkImoTrim5 = 0u; +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSV2) */ + +/* Stored PUMP_SEL configuration during disable (IMO output by default) */ +uint32 CySysClkPumpConfig = CY_SYS_CLK_PUMP_ENABLE; + +/******************************************************************************* +* Function Name: CySysClkImoStart +****************************************************************************//** +* +* Enables the IMO. +* +* For PSoC 4100M / PSoC 4200M / PSoC 4000S / PSoC 4100S / PSoC Analog +* Coprocessor devices, this function will also enable WCO lock if selected in +* the Design Wide Resources tab. +* +* For PSoC 4200L devices, this function will also enable USB lock if selected +* in the Design Wide Resources tab. +* +*******************************************************************************/ +void CySysClkImoStart(void) +{ + CY_SYS_CLK_IMO_CONFIG_REG |= CY_SYS_CLK_IMO_CONFIG_ENABLE; + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + #if (CYDEV_IMO_TRIMMED_BY_WCO == 1u) + CySysClkImoEnableWcoLock(); + #endif /* (CYDEV_IMO_TRIMMED_BY_WCO == 1u) */ + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + #if (CYDEV_IMO_TRIMMED_BY_USB == 1u) + CySysClkImoEnableUsbLock(); + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 1u) */ + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +} + + +/******************************************************************************* +* Function Name: CySysClkImoStop +****************************************************************************//** +* +* Disables the IMO. +* +* For PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / +* PSoC Analog Coprocessor devices, this function will also disable WCO lock. +* +* For PSoC PSoC 4200L devices, this function will also disable USB lock. +* +*******************************************************************************/ +void CySysClkImoStop(void) +{ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + CySysClkImoDisableWcoLock(); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + CySysClkImoDisableUsbLock(); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CY_SYS_CLK_IMO_CONFIG_REG &= ( uint32 ) ( ~( uint32 )CY_SYS_CLK_IMO_CONFIG_ENABLE); +} + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + + /******************************************************************************* + * Function Name: CySysClkImoEnableWcoLock + ****************************************************************************//** + * + * Enables the IMO to WCO lock feature. This function works only if the WCO is + * already enabled. If the WCO is not enabled then this function returns + * without enabling the lock feature. + * + * It takes up to 20 ms for the IMO to stabilize. The delay is implemented with + * CyDelay() function. The delay interval is measured based on the system + * frequency defined by PSoC Creator at build time. If System clock frequency + * is changed in runtime, the CyDelayFreq() with the appropriate parameter + * should be called. + * + * For PSoC 4200L devices, note that the IMO can lock to either WCO or USB + * but not both. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + *******************************************************************************/ + void CySysClkImoEnableWcoLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + #endif /* (CY_IP_SRSSV2) */ + + uint32 freq; + uint8 interruptState; + uint32 regTmp; + uint32 lfLimit = 0u; + volatile uint32 flashCtlReg; + + if (0u != CySysClkWcoEnabled()) + { + interruptState = CyEnterCriticalSection(); + + /* Set oscillator interface control port to WCO */ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + CY_SYS_CLK_OSCINTF_CTL_REG = + (CY_SYS_CLK_OSCINTF_CTL_REG & (uint32) ~CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK) | + CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_WCO; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + /* Get current IMO frequency based on the register value */ + #if(CY_IP_SRSSV2) + freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #else + /* Calculate frequency by shifting register field value and adding constant. */ + #if(CY_IP_SRSSLT) + freq = (((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> + ((CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT) & + (uint32) CY_SYS_CLK_SELECT_HFCLK_DIV_MASK)); + #else + freq = ((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #endif /* (CY_IP_SRSSLT) */ + + #endif /* (CY_IP_SRSSV2) */ + + /* For the WCO locking mode, the IMO gain needs to be CY_SYS_CLK_IMO_TRIM4_GAIN */ + #if(CY_IP_SRSSV2) + if ((CY_SYS_CLK_IMO_TRIM4_REG & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) == 0u) + { + CY_SYS_CLK_IMO_TRIM4_REG = (CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SYS_CLK_IMO_TRIM4_WCO_GAIN; + } + #endif /* (CY_IP_SRSSV2) */ + + regTmp = CY_SYS_CLK_WCO_DPLL_REG & ~(CY_SYS_CLK_WCO_DPLL_MULT_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK); + + /* Set multiplier to determine IMO frequency in multiples of the WCO frequency */ + regTmp |= (CY_SYS_CLK_WCO_DPLL_MULT_VALUE(freq) & CY_SYS_CLK_WCO_DPLL_MULT_MASK); + + /* Set DPLL Loop Filter Integral and Proportional Gains Setting */ + regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN | CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN); + + /* Set maximum allowed IMO offset */ + if (freq < CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT) + { + regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); + } + else + { + lfLimit = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + + cyImoFreqMhz2DpllOffset[freq - CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET]; + + lfLimit = (lfLimit > CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX) ? + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX : lfLimit; + + regTmp |= (lfLimit << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); + } + + CY_SYS_CLK_WCO_DPLL_REG = regTmp; + + flashCtlReg = CY_FLASH_CTL_REG; + CySysFlashSetWaitCycles(CY_SYS_CLK_IMO_MAX_FREQ_MHZ); + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + CyDelay(CY_SYS_CLK_WCO_IMO_TIMEOUT_MS); + CY_FLASH_CTL_REG = flashCtlReg; + + CyExitCriticalSection(interruptState); + } + } + + + /******************************************************************************* + * Function Name: CySysClkImoDisableWcoLock + ****************************************************************************//** + * + * Disables the IMO to WCO lock feature. + * + * For PSoC 4200L devices, note that the IMO can lock to either WCO or USB + * but not both. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + *******************************************************************************/ + void CySysClkImoDisableWcoLock(void) + { + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + } + + + /******************************************************************************* + * Function Name: CySysClkImoGetWcoLock + ****************************************************************************//** + * + * Reports the IMO to WCO lock enable state. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + * \return 1 if IMO to WCO lock is enabled. + * \return 0 if IMO to WCO lock is disabled. + * + *******************************************************************************/ + uint32 CySysClkImoGetWcoLock(void) + { + return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE)) ? + (uint32) 1u : + (uint32) 0u); + } + +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +#if (CY_IP_IMO_TRIMMABLE_BY_USB) + + /******************************************************************************* + * Function Name: CySysClkImoEnableUsbLock + ****************************************************************************//** + * + * Enables the IMO to USB lock feature. + * + * This function must be called before CySysClkWriteImoFreq(). + * + * This function is called from CySysClkImoStart() function if USB lock + * selected in the Design Wide Resources tab. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + *******************************************************************************/ + void CySysClkImoEnableUsbLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + + /* Check for new trim algorithm */ + uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_REV_REG & + CY_SFLASH_S1_TESTPGM_REV_MASK)) ? 1u : 0u); + + /* Get current IMO frequency based on the register value */ + uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #endif /* (CY_IP_SRSSV2) */ + + /* Set oscillator interface control port to USB */ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + CY_SYS_CLK_OSCINTF_CTL_REG = (CY_SYS_CLK_OSCINTF_CTL_REG & (uint32) ~CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK) | + CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_USB; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + #if(CY_IP_SRSSV2) + + /* Save CY_SYS_CLK_IMO_TRIM4_REG and set IMO gain for USB lock */ + CySysClkImoTrim4 = CY_SYS_CLK_IMO_TRIM4_REG; + + if(0u != CySysClkUsbCuSortTrim) + { + CySysClkImoTrim5 = CY_PWR_BG_TRIM5_REG; + + CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG; + CY_PWR_BG_TRIM5_REG = CY_SFLASH_USBMODE_IMO_TEMPCO_REG; + + } + else + { + CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SYS_CLK_IMO_TRIM4_USB_GAIN; + + } + + if (48u == freq) + { + CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_48_REG : + (uint32)CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + } + else if (24u == freq) + { + CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_24_REG : + (uint32)CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + } + else + { + /* Do nothing */ + } + + #endif /* (CY_IP_SRSSV2) */ + + CY_SYS_CLK_USBDEVv2_CR1_REG |= CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + } + + + /******************************************************************************* + * Function Name: CySysClkImoDisableUsbLock + ****************************************************************************//** + * + * Disables the IMO to USB lock feature. + * + * This function is called from CySysClkImoStop() function if USB lock selected + * in the Design Wide Resources tab. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + *******************************************************************************/ + void CySysClkImoDisableUsbLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + + /* Check for new trim algorithm */ + uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_REV_REG & + CY_SFLASH_S1_TESTPGM_REV_MASK)) ? 1u : 0u); + + /* Get current IMO frequency based on the register value */ + uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ;; + + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #endif /* (CY_IP_SRSSV2) */ + + CY_SYS_CLK_USBDEVv2_CR1_REG &= (uint32) ~CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + + #if(CY_IP_SRSSV2) + /* Restore CY_SYS_CLK_IMO_TRIM4_REG */ + CY_SYS_CLK_IMO_TRIM4_REG = ((CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + (CySysClkImoTrim4 & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK)); + + if(0u != CySysClkUsbCuSortTrim) + { + CY_PWR_BG_TRIM5_REG = CySysClkImoTrim5; + } + + CY_SYS_CLK_IMO_TRIM1_REG = CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET); + + #endif /* (CY_IP_SRSSV2) */ + } + + + /******************************************************************************* + * Function Name: CySysClkImoGetUsbLock + ****************************************************************************//** + * + * Reports the IMO to USB lock enable state. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + * \return 1 if IMO to USB lock is enabled. + * \return 0 if IMO to USB lock is disabled. + * + *******************************************************************************/ + uint32 CySysClkImoGetUsbLock(void) + { + return ((0u != (CY_SYS_CLK_USBDEVv2_CR1_REG & CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK)) ? + (uint32) 1u : + (uint32) 0u); + } +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + + +/******************************************************************************* +* Function Name: CySysClkWriteHfclkDirect +****************************************************************************//** +* +* Selects the direct source for the HFCLK. +* +* The new source must be running and stable before calling this function. +* +* PSoC 4000: +* The SYSCLK has a maximum speed of 16 MHz, so HFCLK and SYSCLK dividers should +* be selected in a way to not to exceed 16 MHz for the System clock. +* +* If the SYSCLK clock frequency increases during device operation, call +* CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number +* of clock cycles the cache will wait before sampling data comes back from +* Flash. If the SYSCLK clock frequency decreases, you can call +* CySysFlashSetWaitCycles() to improve the CPU performance. See +* CySysFlashSetWaitCycles() description for more information. +* +* Do not select PLL as the source for HFCLK if PLL output frequency exceeds +* maximum permissible value for HFCLK. +* +* \param clkSelect One of the available HFCLK direct sources. +* CY_SYS_CLK_HFCLK_IMO IMO. +* CY_SYS_CLK_HFCLK_EXTCLK External clock pin. +* CY_SYS_CLK_HFCLK_ECO External crystal oscillator. Applicable for +* PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / +* 4100S with ECO. +* CY_SYS_CLK_HFCLK_PLL0 PLL#0. Applicable for PSoC 4200L / +* 4100S with PLL. +* CY_SYS_CLK_HFCLK_PLL1 PLL#1. Applicable for PSoC 4200L. +* +*******************************************************************************/ +void CySysClkWriteHfclkDirect(uint32 clkSelect) +{ + uint8 interruptState; + uint32 tmpReg; + + #if (CY_IP_SRSSLT && CY_IP_PLL) + uint8 i = 0u; + #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + interruptState = CyEnterCriticalSection(); + +#if (CY_IP_SRSSLT && CY_IP_PLL) + if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_ECO == clkSelect)) + { + tmpReg = CY_SYS_CLK_SELECT_REG & ~CY_SYS_CLK_SELECT_DIRECT_SEL_MASK; + tmpReg |= CY_SYS_CLK_HFCLK_IMO; + CY_SYS_CLK_SELECT_REG = tmpReg; + + /* SRSSLT block does not have registers to select PLL. It is part of EXCO */ + tmpReg = CY_SYS_ECO_CLK_SELECT_REG & ~CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK; + tmpReg |= ((clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_PLL_MASK) >> CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT); + CY_SYS_ECO_CLK_SELECT_REG = tmpReg; + + /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) + { + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + } + + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + } +#endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + tmpReg = CY_SYS_CLK_SELECT_REG & ~(CY_SYS_CLK_SELECT_DIRECT_SEL_MASK | + CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + +#if (CY_IP_SRSSV2 && CY_IP_PLL) + if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_PLL1 == clkSelect)) + { + tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + } + else +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + { + tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + } + + CY_SYS_CLK_SELECT_REG = tmpReg; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysEnablePumpClock +****************************************************************************//** +* +* Enables / disables the pump clock. +* +* \param enable +* CY_SYS_CLK_PUMP_DISABLE - Disables the pump clock +* CY_SYS_CLK_PUMP_ENABLE - Enables and restores the operating source of +* the pump clock. +* +* \sideeffect +* Enabling/disabling the pump clock does not guarantee glitch free operation +* when changing the IMO parameters or clock divider settings. +* +*******************************************************************************/ +void CySysEnablePumpClock(uint32 enable) +{ + #if(CY_IP_SRSSV2) + if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + { + CY_SYS_CLK_IMO_CONFIG_REG |= (CySysClkPumpConfig << CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT); + } + else + { + CySysClkPumpConfig = (CY_SYS_CLK_IMO_CONFIG_REG >> CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT) & + CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK; + CY_SYS_CLK_IMO_CONFIG_REG &= ~(CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK << CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT); + } + #else /* CY_IP_SRSSLT */ + if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + { + CY_SYS_CLK_SELECT_REG |= (CySysClkPumpConfig << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT); + } + else + { + CySysClkPumpConfig = (CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & + CY_SYS_CLK_SELECT_PUMP_SEL_MASK; + CY_SYS_CLK_SELECT_REG &= ~(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT); + } + #endif /* (CY_IP_SRSSV2) */ +} + + +/******************************************************************************* +* Function Name: CySysClkGetSysclkSource +****************************************************************************//** +* +* Returns the source of the System clock. +* +* \return The same as \ref CySysClkWriteHfclkDirect() function parameters. +* +*******************************************************************************/ +uint32 CySysClkGetSysclkSource(void) +{ + uint8 interruptState; + uint32 sysclkSource; + + interruptState = CyEnterCriticalSection(); + +#if (CY_IP_SRSSV2 && CY_IP_PLL) + if ((CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK) != 0u) + { + sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + } + else +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + { + sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + + #if (CY_IP_SRSSLT && CY_IP_PLL) + sysclkSource |= (((uint32)(CY_SYS_ECO_CLK_SELECT_REG & CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK)) << + CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT); + #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + } + + CyExitCriticalSection(interruptState); + + return (sysclkSource); +} + + +/******************************************************************************* +* Function Name: CySysClkWriteSysclkDiv +****************************************************************************//** +* +* Selects the prescaler divide amount for SYSCLK from HFCLK. +* +* PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers +* should be selected in a way, not to exceed 16 MHz for SYSCLK. +* +* PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, +* so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz +* for SYSCLK. +* +* If the SYSCLK clock frequency increases during the device operation, call +* \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the +* number of clock cycles the cache will wait before sampling data comes back +* from Flash. If the SYSCLK clock frequency decreases, you can call +* \ref CySysFlashSetWaitCycles() to improve the CPU performance. See +* \ref CySysFlashSetWaitCycles() description for more information. +* +* \param divider Power of 2 prescaler selection +* CY_SYS_CLK_SYSCLK_DIV1 SYSCLK = HFCLK / 1 +* CY_SYS_CLK_SYSCLK_DIV2 SYSCLK = HFCLK / 2 +* CY_SYS_CLK_SYSCLK_DIV4 SYSCLK = HFCLK / 4 +* CY_SYS_CLK_SYSCLK_DIV8 SYSCLK = HFCLK / 8 +* CY_SYS_CLK_SYSCLK_DIV16 SYSCLK = HFCLK / 16 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV32 SYSCLK = HFCLK / 32 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV64 SYSCLK = HFCLK / 64 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV128 SYSCLK = HFCLK / 128 (N/A for 4000 Family) +* +*******************************************************************************/ +void CySysClkWriteSysclkDiv(uint32 divider) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = ((uint32)(((uint32)divider & CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK) << + CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)) | + (CY_SYS_CLK_SELECT_REG & ((uint32)(~(uint32)(CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK << + CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)))); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysClkWriteImoFreq +****************************************************************************//** +* +* Sets the frequency of the IMO. +* +* PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers +* should be selected in a way, not to exceed 16 MHz for SYSCLK. +* +* PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, +* so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz +* for SYSCLK. +* +* For PSoC 4200M and PSoC 4200L device families, if WCO lock feature is enabled +* then this API will disable the lock, write the new IMO frequency and then +* re-enable the lock. +* +* For PSoC 4200L device families, this function enables the USB lock when 24 or +* 48 MHz passed as a parameter if the USB lock option is enabled in Design Wide +* Resources tab or CySysClkImoEnableUsbLock() was called before. Note the USB +* lock is disabled during IMO frequency change. +* +* The CPU is halted if new frequency is invalid and project is compiled +* in debug mode. +* +* If the SYSCLK clock frequency increases during the device operation, call +* \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the +* number of clock cycles the cache will wait before sampling data comes back +* from Flash. If the SYSCLK clock frequency decreases, you can call +* \ref CySysFlashSetWaitCycles() to improve the CPU performance. See +* \ref CySysFlashSetWaitCycles() description for more information. +* +* PSoC 4000: The System Clock (SYSCLK) has maximum speed of 16 MHz, so HFCLK +* and SYSCLK dividers should be selected in a way, to not to exceed 16 MHz for +* the System clock. +* +* \param freq All PSoC 4 families excluding the following: Valid range [3-48] +* with step size equals 1. PSoC 4000: Valid values are 24, 32, and 48. +* PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor: Valid range [24-48] with +* step size equals 4. +* +*******************************************************************************/ +#if(CY_IP_SRSSV2) + void CySysClkWriteImoFreq(uint32 freq) + { + #if (CY_IP_FMLT) + volatile uint32 parameters[2u]; + volatile uint32 regValues[4u]; + #else + uint8 bgTrim4; + uint8 bgTrim5; + uint8 newImoTrim2Value; + uint8 currentImoTrim2Value; + #endif /* (CY_IP_FM) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + uint32 wcoLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + uint32 usbLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + uint8 interruptState; + + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if(0u != CySysClkImoGetWcoLock()) + { + wcoLock = 1u; + CySysClkImoDisableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + if(0u != CySysClkImoGetUsbLock()) + { + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + if ((24u == freq) || (48u == freq)) + { + usbLock = 1u; + CySysClkImoDisableUsbLock(); + } + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + } + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + + #if (CY_IP_FMLT) + + /* FM-Lite Clock Restore */ + regValues[0u] = CY_SYS_CLK_IMO_CONFIG_REG; + regValues[1u] = CY_SYS_CLK_SELECT_REG; + regValues[2u] = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + regValues[3u] = CY_FLASH_CTL_REG; + + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) ®Values[0u]; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + (void) CY_FLASH_CPUSS_SYSARG_REG; + + #else /* (CY_IP_FM) */ + + if ((freq >= CY_SYS_CLK_IMO_MIN_FREQ_MHZ) && (freq <= CY_SYS_CLK_IMO_MAX_FREQ_MHZ)) + { + if(freq <= CY_SFLASH_IMO_MAXF0_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS0_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO0_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF1_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS1_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO1_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF2_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS2_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO2_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF3_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS3_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO3_REG; + } + else + { + bgTrim4 = CY_SFLASH_IMO_ABS4_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO4_REG; + } + + /* Get IMO_TRIM2 value for the new frequency */ + newImoTrim2Value = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + + + /**************************************************************************** + * The IMO can have a different trim per frequency. To avoid possible corner + * cases where a trim change can exceed the maximum frequency, the trim must + * be applied at a frequency that is low enough. + * + * Comparing IMO_TRIM2 values for the current and new frequencies, since + * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + * function and is time-invariant. + ***************************************************************************/ + if ((newImoTrim2Value >= CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2) && (freq >= CY_SYS_CLK_IMO_BOUNDARY_FREQ_MHZ)) + { + /* Set boundary IMO frequency: safe for IMO above 48 MHZ trimming */ + CY_SYS_CLK_IMO_TRIM2_REG = (uint32) cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_TEMP_FREQ_MHZ - + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + + currentImoTrim2Value = CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2; + } + else + { + currentImoTrim2Value = (uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK); + } + + + /*************************************************************************** + * A trim change needs to be allowed to settle (within 5us) before the Freq + * can be changed to a new frequency. + * + * Comparing IMO_TRIM2 values for the current and new frequencies, since + * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + * function and is time-invariant. + ***************************************************************************/ + if (newImoTrim2Value < currentImoTrim2Value) + { + /* Set new IMO frequency */ + CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + } + + /* Set trims for the new IMO frequency */ + CY_SYS_CLK_IMO_TRIM1_REG = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET); + CY_PWR_BG_TRIM4_REG = bgTrim4; + CY_PWR_BG_TRIM5_REG = bgTrim5; + CyDelayUs(CY_SYS_CLK_IMO_TRIM_TIMEOUT_US); + + if (newImoTrim2Value > currentImoTrim2Value) + { + /* Set new IMO frequency */ + CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + } + } + else + { + /* Halt CPU in debug mode if new frequency is invalid */ + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_FMLT) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (1u == wcoLock) + { + CySysClkImoEnableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if (1u == usbLock) + { + CySysClkImoEnableUsbLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CyExitCriticalSection(interruptState); + } + +#else + + void CySysClkWriteImoFreq(uint32 freq) + { + uint8 interruptState; + uint8 imoTrim1Value; + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + uint32 wcoLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + uint32 usbLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + #if (CY_PSOC4_4000) + if ((freq == 24u) || (freq == 32u) || (freq == 48u)) + #elif (CY_CCG3) + if ((freq == 24u) || (freq == 36u) || (freq == 48u)) + #else + if ((freq == 24u) || (freq == 28u) || (freq == 32u) || + (freq == 36u) || (freq == 40u) || (freq == 44u) || + (freq == 48u)) + #endif /* (CY_PSOC4_4000) */ + { + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if(0u != CySysClkImoGetWcoLock()) + { + wcoLock = 1u; + CySysClkImoDisableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + if(0u != CySysClkImoGetUsbLock()) + { + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + if (48u == freq) + { + usbLock = 1u; + CySysClkImoDisableUsbLock(); + } + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + } + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + + /* Set IMO to 24 MHz - CLK_IMO_SELECT.FREQ = 0 */ + CY_SYS_CLK_IMO_SELECT_REG &= ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + + + /* Apply coarse trim */ + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if ((1u == usbLock) && (48u == freq)) + { + imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + } + else if ((1u == usbLock) && (24u == freq)) + { + imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + } + else + { + imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + } + #else + imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + CY_SYS_CLK_IMO_TRIM1_REG = (uint32) imoTrim1Value; + + /* Zero out fine trim */ + CY_SYS_CLK_IMO_TRIM2_REG = CY_SYS_CLK_IMO_TRIM2_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM2_FSOFFSET_MASK); + + /* Apply TC trim */ + CY_SYS_CLK_IMO_TRIM3_REG = (CY_SYS_CLK_IMO_TRIM3_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM3_VALUES_MASK)) | + (CY_SFLASH_IMO_TCTRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) & CY_SYS_CLK_IMO_TRIM3_VALUES_MASK); + + CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); + + if (freq > CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + { + /* Select nearby intermediate frequency */ + CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) | + (((freq - 4u - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + + CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); + + /* Make small step to final frequency */ + /* Select nearby intermediate frequency */ + CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) | + (((freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + } + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (1u == wcoLock) + { + CySysClkImoEnableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if (1u == usbLock) + { + CySysClkImoEnableUsbLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CyExitCriticalSection(interruptState); + } + else + { + /* Halt CPU in debug mode if new frequency is invalid */ + CYASSERT(0u != 0u); + } + } + +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT) + /******************************************************************************* + * Function Name: CySysClkWriteHfclkDiv + ****************************************************************************//** + * + * Selects the pre-scaler divider value for HFCLK from IMO. + * + * The HFCLK predivider allows the device to divide the HFCLK selection mux + * input before use as HFCLK. The predivider is capable of dividing the HFCLK by + * powers of 2 between 1 and 8. + * + * PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers + * should be selected in a way, not to exceed 16 MHz for SYSCLK. + * + * If the SYSCLK clock frequency increases during the device operation, call + * \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the + * number of clock cycles the cache will wait before sampling data comes back + * from Flash. If the SYSCLK clock frequency decreases, you can call + * \ref CySysFlashSetWaitCycles() to improve the CPU performance. See + * \ref CySysFlashSetWaitCycles() description for more information. + * + * \param \ref CY_SYS_CLK_HFCLK_DIV_NODIV Transparent mode (w/o dividing) + * \param \ref CY_SYS_CLK_HFCLK_DIV_2 Divide selected clock source by 2 + * \param \ref CY_SYS_CLK_HFCLK_DIV_4 Divide selected clock source by 4 + * \param \ref CY_SYS_CLK_HFCLK_DIV_8 Divide selected clock source by 8 + * + *******************************************************************************/ + void CySysClkWriteHfclkDiv(uint32 divider) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & ((uint32) (~(CY_SYS_CLK_SELECT_HFCLK_DIV_MASK << + CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT)))) | + ((uint32)((divider & CY_SYS_CLK_SELECT_HFCLK_DIV_MASK) << CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT))); + + CyExitCriticalSection(interruptState); + } +#endif /* (CY_IP_SRSSLT) */ + + +#if (CY_IP_ECO) + + /******************************************************************************* + * Function Name: CySysClkEcoStart + ****************************************************************************//** + * + * Starts the External Crystal Oscillator (ECO). Refer to the device datasheet + * for the ECO startup time. + * + * The timeout interval is measured based on the system frequency defined by + * PSoC Creator at build time. If System clock frequency is changed in + * runtime, the \ref CyDelayFreq() with the appropriate parameter should be + * called. + * + * PSoC 4100 BLE / PSoC 4200 BLE: The WCO must be enabled prior to enabling ECO. + * + * \param timeoutUs Timeout in microseconds. + * + * If zero is specified, the function does not wait for timeout and returns + * CYRET_SUCCESS. If non-zero is specified, the function waits for the timeout. + * + * \return \ref CYRET_SUCCESS Completed successfully. The ECO is oscillating and + * amplitude reached 60% and it does not mean 24 MHz crystal is within 50 ppm. + * + * \return \ref CYRET_TIMEOUT Timeout occurred. If the crystal is not oscillating + * or amplitude didn't reach 60% after specified amount of time, CYRET_TIMEOUT + * is returned. + * + * \return \ref CYRET_BAD_PARAM One or more invalid parameters. + * + *******************************************************************************/ + cystatus CySysClkEcoStart(uint32 timeoutUs) + { + cystatus returnStatus = CYRET_SUCCESS; + + #if (CY_IP_ECO_BLESS) + /* Enable the RF oscillator band gap */ + CY_SYS_XTAL_BLESS_RF_CONFIG_REG |= CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; + + /* Update trimming register */ + CY_SYS_XTAL_BLERD_BB_XO_REG = CY_SYS_XTAL_BLERD_BB_XO_TRIM; + + /* Enable the Crystal */ + CY_SYS_XTAL_BLERD_DBUS_REG |= CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; + + #elif (CY_IP_ECO_BLESSV3) + uint32 regConfig; + uint32 intrRegMaskStore = 0u; + + if (0u != (CY_SYS_BLESS_MT_CFG_REG & (CY_SYS_BLESS_MT_CFG_ENABLE_BLERD << CYFLD_BLE_BLESS_ENABLE_BLERD__OFFSET))) + { + CY_SYS_BLESS_MT_CFG_REG |= (CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET); + } + else + { + /* Init BLE core */ + CY_SYS_BLESS_MT_DELAY_CFG_REG = CY_SYS_BLESS_MT_DELAY_CFG_INIT; + CY_SYS_BLESS_MT_DELAY_CFG2_REG = CY_SYS_BLESS_MT_DELAY_CFG2_INIT; + CY_SYS_BLESS_MT_DELAY_CFG3_REG = CY_SYS_BLESS_MT_DELAY_CFG3_INIT; + + /* RCB init */ + regConfig = CY_SYS_RCB_CTRL_REG; + regConfig &= CY_SYS_RCB_CTRL_CLEAR; + regConfig |= CY_SYS_RCB_CTRL_INIT; + CY_SYS_RCB_CTRL_REG = regConfig; + + intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; + if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG &= ~CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; + } + + /* Enable BLE core */ + regConfig = CY_SYS_BLESS_MT_CFG_REG; + regConfig &= CY_SYS_BLESS_MT_CFG_CLEAR; + regConfig |= CY_SYS_BLESS_MT_CFG_INIT; + CY_SYS_BLESS_MT_CFG_REG = regConfig; + + while(0u == ((CY_SYS_BLESS_BLERD_ACTIVE_INTR_STAT & CY_SYS_BLESS_INTR_STAT_REG))) + { + /* Wait until BLERD55 moves to active state */ + } + + if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG |= CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; + } + + /* Send write commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_NRST_SET; + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_DIG_CLK_SET; + + #if (CY_SYS_BLE_CLK_ECO_FREQ_32MHZ == CYDEV_ECO_CLK_MHZ) + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_DIV_SET; + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | CY_SYS_RCB_RBUS_IB_VAL); + #else + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_NODIV_SET; + #endif + + intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; + if(0u != (CY_SYS_RCB_INTR_RCB_DONE & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG &= ~(CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY); + } + + /* Send read commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RD_CMD | + (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET & ~CY_SYS_RCB_RBUS_VAL_MASK)); + + while (0u == (CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY & CY_SYS_RCB_INTR_REG)) + { + /* Wait until RX_FIFO_NOT_EMPTY state */ + } + + CY_SYS_RCB_INTR_REG |= CY_SYS_RCB_INTR_RCB_DONE; + + regConfig = CY_SYS_RCB_RX_FIFO_RD_REG & CY_SYS_RCB_RBUS_TRIM_MASK; + + /* Send write commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | regConfig | CY_SYS_RCB_RBUS_TRIM_VAL); + + while (0u == (CY_SYS_RCB_INTR_RCB_DONE & CY_SYS_RCB_INTR_REG)) + { + /* Wait until RCB_DONE state */ + } + + /* Clear Interrupt */ + CY_SYS_RCB_INTR_REG = CY_SYS_RCB_INTR_CLEAR; + + if(0u != ((CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY) & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG |= intrRegMaskStore; + } + + } + #else /* CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT */ + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_ENABLE; + CyDelayUs(CY_SYS_CLK_ECO_CONFIG_CLK_EN_TIMEOUT_US); + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_CLK_EN; + #endif /* (CY_IP_ECO_BLESS) */ + + if(timeoutUs > 0u) + { + returnStatus = CYRET_TIMEOUT; + + for( ; timeoutUs > 0u; timeoutUs--) + { + CyDelayUs(1u); + + if(0u != CySysClkEcoReadStatus()) + { + returnStatus = CYRET_SUCCESS; + break; + } + } + + } + + return(returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkEcoStop + ****************************************************************************//** + * + * Stops the megahertz crystal. + * + * If ECO is disabled when it is sourcing HFCLK, the CPU will halt. In addition, + * for PSoC 4100 BLE / PSoC 4200 BLE devices, the BLE sub-system will stop + * functioning. + * + *******************************************************************************/ + void CySysClkEcoStop(void) + { + #if (CY_IP_WCO_BLESS) + /* Disable the RF oscillator band gap */ + CY_SYS_XTAL_BLESS_RF_CONFIG_REG &= (uint32) ~CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; + + /* Disable the Crystal */ + CY_SYS_XTAL_BLERD_DBUS_REG &= (uint32) ~CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; + #elif (CY_IP_ECO_BLESSV3) + CY_SYS_BLESS_MT_CFG_REG &= ~(CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET); + #else + CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~(CY_SYS_CLK_ECO_CONFIG_ENABLE | CY_SYS_CLK_ECO_CONFIG_CLK_EN); + #endif /* (CY_IP_WCO_BLESS) */ + } + + + /******************************************************************************* + * Function Name: CySysClkEcoReadStatus + ****************************************************************************//** + * + * Reads the status bit for the megahertz crystal. + * + * For PSoC 4100 BLE / PSoC 4200 BLE devices, the status bit is the + * XO_AMP_DETECT bit in FSM register. + * + * For PSoC 4200L / 4100S with ECO devices, the error status bit is the + * WATCHDOG_ERROR bit in ECO_STATUS register. + * + * \return PSoC 4100 BLE/PSoC 4200 BLE: Non-zero indicates that ECO output + * reached 50 ppm and is oscillating in valid range. + * + * \return PSoC 4200L / 4100S with ECO: Non-zero indicates that ECO is running. + * + *******************************************************************************/ + uint32 CySysClkEcoReadStatus(void) + { + uint32 returnValue; + + #if (CY_IP_WCO_BLESS) + returnValue = CY_SYS_XTAL_BLERD_FSM_REG & CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT; + #elif (CY_IP_ECO_BLESSV3) + returnValue = (CY_SYS_BLESS_MT_STATUS_REG & CY_SYS_BLESS_MT_STATUS_CURR_STATE_MASK) >> CYFLD_BLE_BLESS_MT_CURR_STATE__OFFSET; + + returnValue = ((CY_SYS_BLESS_MT_STATUS_BLERD_IDLE == returnValue) || + (CY_SYS_BLESS_MT_STATUS_SWITCH_EN == returnValue) || + (CY_SYS_BLESS_MT_STATUS_ACTIVE == returnValue) || + (CY_SYS_BLESS_MT_STATUS_ISOLATE == returnValue)); + #else + returnValue = (0u != (CY_SYS_CLK_ECO_STATUS_REG & CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR)) ? 0u : 1u; + #endif /* (CY_IP_WCO_BLESS) */ + + return (returnValue); + } + + #if (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) + /******************************************************************************* + * Function Name: CySysClkWriteEcoDiv + ****************************************************************************//** + * + * Selects value for the ECO divider. + * + * The ECO must not be the HFCLK clock source when this function is called. + * The HFCLK source can be changed to the other clock source by call to the + * CySysClkWriteHfclkDirect() function. If the ECO sources the HFCLK this + * function will not have any effect if compiler in release mode, and halt the + * CPU when compiler in debug mode. + * + * If the SYSCLK clock frequency increases during the device operation, call + * CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number + * of clock cycles the cache will wait before sampling data comes back from + * Flash. If the SYSCLK clock frequency decreases, you can call + * CySysFlashSetWaitCycles() to improve the CPU performance. See + * CySysFlashSetWaitCycles() description for more information. + * + * \param divider Power of 2 divider selection. + * - \ref CY_SYS_CLK_ECO_DIV1 + * - \ref CY_SYS_CLK_ECO_DIV2 + * - \ref CY_SYS_CLK_ECO_DIV4 + * - \ref CY_SYS_CLK_ECO_DIV8 + * + *******************************************************************************/ + void CySysClkWriteEcoDiv(uint32 divider) + { + uint8 interruptState; + + if (CY_SYS_CLK_HFCLK_ECO != (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK)) + { + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG = (divider & CY_SYS_CLK_XTAL_CLK_DIV_MASK) | + (CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG & ((uint32) ~CY_SYS_CLK_XTAL_CLK_DIV_MASK)); + + CyExitCriticalSection(interruptState); + } + else + { + /* Halt CPU in debug mode if ECO sources HFCLK */ + CYASSERT(0u != 0u); + } + } + + #else + + /******************************************************************************* + * Function Name: CySysClkConfigureEcoTrim + ****************************************************************************//** + * + * Selects trim setting values for ECO. This API is available only for PSoC + * 4200L / 4100S with ECO devices only. + * + * The following parameters can be trimmed for ECO. The affected registers are + * ECO_TRIM0 and ECO_TRIM1. + * + * Watchdog trim - This bit field sets the error threshold below the steady + * state amplitude level. + * + * Amplitude trim - This bit field is to set the crystal drive level when + * ECO_CONFIG.AGC_EN = 1. WARNING: use care when setting this field because + * driving a crystal beyond its rated limit can permanently damage the crystal. + * + * Filter frequency trim - This bit field sets LPF frequency trim and affects + * the 3rd harmonic content. + * + * Feedback resistor trim - This bit field sets the feedback resistor trim and + * impacts the oscillation amplitude. + * + * Amplifier gain trim - This bit field sets the amplifier gain trim and affects + * the startup time of the crystal. + * + * Use care when setting the amplitude trim field because driving a crystal + * beyond its rated limit can permanently damage the crystal. + * + * \param wDTrim: Watchdog trim + * - \ref CY_SYS_CLK_ECO_WDTRIM0 Error threshold is 0.05 V + * - \ref CY_SYS_CLK_ECO_WDTRIM1 Error threshold is 0.10 V + * - \ref CY_SYS_CLK_ECO_WDTRIM2 Error threshold is 0.15 V + * - \ref CY_SYS_CLK_ECO_WDTRIM3 Error threshold is 0.20 V + * + * \param aTrim: Amplitude trim + * - \ref CY_SYS_CLK_ECO_ATRIM0 Amplitude is 0.3 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM1 Amplitude is 0.4 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM2 Amplitude is 0.5 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM3 Amplitude is 0.6 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM4 Amplitude is 0.7 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM5 Amplitude is 0.8 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM6 Amplitude is 0.9 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM7 Amplitude is 1.0 Vpp + * + * \param fTrim: Filter frequency trim + * - \ref CY_SYS_CLK_ECO_FTRIM0 Crystal frequency > 30 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM1 24 MHz < Crystal frequency <= 30 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM2 17 MHz < Crystal frequency <= 24 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM3 Crystal frequency <= 17 MHz + * + * \param rTrim: Feedback resistor trim + * - \ref CY_SYS_CLK_ECO_RTRIM0 Crystal frequency > 30 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM1 24 MHz < Crystal frequency <= 30 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM2 17 MHz < Crystal frequency <= 24 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM3 Crystal frequency <= 17 MHz + * + * \param gTrim: Amplifier gain trim. Calculate the minimum required gm + * (trans-conductance value). Divide the calculated gm value by 4.5 to + * obtain an integer value 'result'. For more information please refer + * to the device TRM. + * - \ref CY_SYS_CLK_ECO_GTRIM0 If result = 1 + * - \ref CY_SYS_CLK_ECO_GTRIM1 If result = 0 + * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 2 + * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 3 + * + *******************************************************************************/ + void CySysClkConfigureEcoTrim(uint32 wDTrim, uint32 aTrim, uint32 fTrim, uint32 rTrim, uint32 gTrim) + { + uint8 interruptState; + uint32 regTmp; + + interruptState = CyEnterCriticalSection(); + + regTmp = CY_SYS_CLK_ECO_TRIM0_REG & ~(CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK | CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK); + regTmp |= ((uint32) (wDTrim << CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK); + regTmp |= ((uint32) (aTrim << CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK); + CY_SYS_CLK_ECO_TRIM0_REG = regTmp; + + regTmp = CY_SYS_CLK_ECO_TRIM1_REG & ~(CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK | + CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK | + CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK); + regTmp |= ((uint32) (fTrim << CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK); + regTmp |= ((uint32) (rTrim << CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK); + regTmp |= ((uint32) (gTrim << CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK); + + CY_SYS_CLK_ECO_TRIM1_REG = regTmp; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkConfigureEcoDrive + ****************************************************************************//** + * + * Selects trim setting values for ECO based on crystal parameters. Use care + * when setting the driveLevel parameter because driving a crystal beyond its + * rated limit can permanently damage the crystal. + * + * This API is available only for PSoC 4200L / 4100S with ECO devices only. + * + * \param freq Frequency of the crystal in kHz. + * \param cLoad Crystal load capacitance in pF. + * \param esr Equivalent series resistance of the crystal in ohm. + * maxAmplitude: maximum amplitude level in mV. Calculate as + * ((sqrt(driveLevel in uW / 2 / esr))/(3.14 * freq * cLoad)) * 10^9. + * + * The Automatic Gain Control (AGC) is disabled when the specified maximum + * amplitude level equals or above 2. In this case the amplitude is not + * explicitly controlled and will grow until it saturates to the supply rail + * (1.8V nom). WARNING: use care when disabling AGC because driving a crystal + * beyond its rated limit can permanently damage the crystal. + * + * \return \ref CYRET_SUCCESS ECO configuration completed successfully. + * \return \ref CYRET_BAD_PARAM One or more invalid parameters. + * + *******************************************************************************/ + cystatus CySysClkConfigureEcoDrive(uint32 freq, uint32 cLoad, uint32 esr, uint32 maxAmplitude) + { + cystatus returnStatus = CYRET_SUCCESS; + + uint32 wDTrim; + uint32 aTrim; + uint32 fTrim; + uint32 rTrim; + uint32 gTrim; + + uint32 gmMin; + + + if ((maxAmplitude < CY_SYS_CLK_ECO_MAX_AMPL_MIN_mV) || + (freq < CY_SYS_CLK_ECO_FREQ_KHZ_MIN) || (freq > CY_SYS_CLK_ECO_FREQ_KHZ_MAX)) + { + returnStatus = CYRET_BAD_PARAM; + } + else + { + /* Calculate amplitude trim */ + aTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/100u) - 4u) : 7u; + + if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM0) + { + aTrim = CY_SYS_CLK_ECO_ATRIM0; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM1) + { + aTrim = CY_SYS_CLK_ECO_ATRIM1; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM2) + { + aTrim = CY_SYS_CLK_ECO_ATRIM2; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM3) + { + aTrim = CY_SYS_CLK_ECO_ATRIM3; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM4) + { + aTrim = CY_SYS_CLK_ECO_ATRIM4; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM5) + { + aTrim = CY_SYS_CLK_ECO_ATRIM5; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM6) + { + aTrim = CY_SYS_CLK_ECO_ATRIM6; + } + else + { + aTrim = CY_SYS_CLK_ECO_ATRIM7; + } + + /* Calculate Watchdog trim. */ + wDTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/200u) - 2u) : 3u; + + /* Calculate amplifier gain trim. */ + gmMin = (uint32) (((((CY_SYS_CLK_ECO_GMMIN_COEFFICIENT * freq * cLoad) / 1000) * ((freq * cLoad * esr) / 1000)) / 100u) / 4500000u); + if (gmMin > 3u) + { + returnStatus = CYRET_BAD_PARAM; + gTrim = 0u; + } + else if (gmMin > 1u) + { + gTrim = gmMin; + } + else + { + gTrim = (gmMin == 1u) ? 0u : 1u; + } + + /* Calculate feedback resistor trim */ + if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM0) + { + rTrim = CY_SYS_CLK_ECO_FTRIM0; + } + else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM1) + { + rTrim = CY_SYS_CLK_ECO_FTRIM1; + } + else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM2) + { + rTrim = CY_SYS_CLK_ECO_FTRIM2; + } + else + { + rTrim = CY_SYS_CLK_ECO_FTRIM3; + } + + /* Calculate filter frequency trim */ + fTrim = rTrim; + + CySysClkConfigureEcoTrim(wDTrim, aTrim, fTrim, rTrim, gTrim); + + /* Automatic Gain Control (AGC) enable */ + if (maxAmplitude < 2u) + { + /* The oscillation amplitude is controlled to the level selected by amplitude trim */ + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_AGC_EN; + } + else + { + /* The amplitude is not explicitly controlled and will grow until it saturates to the + * supply rail (1.8V nom). + */ + CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_ECO_CONFIG_AGC_EN; + } + } + + return (returnStatus); + } + + #endif /* CY_IP_ECO_BLESS */ + +#endif /* (CY_IP_ECO) */ + + +#if (CY_IP_PLL) + /******************************************************************************* + * Function Name: CySysClkPllStart + ****************************************************************************//** + * + * Enables the PLL. Optionally waits for it to become stable. Waits at least + * 250 us or until it is detected that the PLL is stable. + * + * Clears the unlock occurred status bit by calling CySysClkPllGetUnlockStatus(), + * once the PLL is locked if the wait parameter is 1). + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param wait: + * 0 - Return immediately after configuration. + * 1 - Wait for PLL lock or timeout. This API shall use the CyDelayUs() to + * implement the timeout feature. + * + * \return CYRET_SUCCESS Completed successfully. + * \return CYRET_TIMEOUT The timeout occurred without detecting a stable clock. + * If the input source of the clock is jittery, then the lock indication may + * not occur. However, after the timeout has expired, the generated PLL clock can + * still be used. + * \return CYRET_BAD_PARAM - Either the PLL or wait parameter is invalid. + * + *******************************************************************************/ + cystatus CySysClkPllStart(uint32 pll, uint32 wait) + { + uint32 counts = CY_SYS_CLK_PLL_MAX_STARTUP_US; + uint8 interruptState; + cystatus returnStatus = CYRET_SUCCESS; + + if((pll < CY_IP_PLL_NR) && (wait <= 1u)) + { + interruptState = CyEnterCriticalSection(); + + /* Isolate PLL outputs */ + CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~CY_SYS_CLK_PLL_CONFIG_ISOLATE; + + /* Enable PLL */ + CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ENABLE; + + CyExitCriticalSection(interruptState); + + /* De-isolate >= CY_SYS_CLK_PLL_MIN_STARTUP_US after PLL enabled */ + CyDelayUs(CY_SYS_CLK_PLL_MIN_STARTUP_US); + interruptState = CyEnterCriticalSection(); + CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ISOLATE; + CyExitCriticalSection(interruptState); + + if(wait != 0u) + { + returnStatus = CYRET_TIMEOUT; + + while(0u != counts) + { + + if(0u != CySysClkPllGetLockStatus(pll)) + { + returnStatus = CYRET_SUCCESS; + (void) CySysClkPllGetUnlockStatus(pll); + break; + } + + CyDelayUs(1u); + counts--; + } + } + } + else + { + returnStatus = CYRET_BAD_PARAM; + } + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetLockStatus + ****************************************************************************//** + * + * Returns non-zero if the output of the specified PLL output is locked. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return A non-zero value when the specified PLL is locked. + * + *******************************************************************************/ + uint32 CySysClkPllGetLockStatus(uint32 pll) + { + uint8 interruptState; + uint32 returnStatus; + + CYASSERT(pll < CY_IP_PLL_NR); + + interruptState = CyEnterCriticalSection(); + + /* PLL is locked if reported so for two consecutive read. */ + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; + if(0u != returnStatus) + { + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + /******************************************************************************* + * Function Name: CySysClkPllStop + ****************************************************************************//** + * + * Disables the PLL. + * + * Ensures that either PLL is not the source of HFCLK before it is disabled, + * otherwise, the CPU will halt. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + *******************************************************************************/ + void CySysClkPllStop(uint32 pll) + { + uint8 interruptState; + + if (pll < CY_IP_PLL_NR) + { + interruptState = CyEnterCriticalSection(); + CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~(CY_SYS_CLK_PLL_CONFIG_ISOLATE | CY_SYS_CLK_PLL_CONFIG_ENABLE); + CyExitCriticalSection(interruptState); + } + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetPQ + ****************************************************************************//** + * + * Sets feedback (P) and reference the (Q) divider value. This API also sets the + * programmable charge pump current value. Note that the PLL has to be disabled + * before calling this API. If this function is called while any PLL is sourcing, + * the SYSCLK will return an error. + * + * The PLL must not be the system clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param feedback The P divider. Range 4 - 259. Control bits for the feedback + * divider. + * + * \param reference The Q divider. Range 1 - 64. Divide by the reference. + * + * \param current Charge the pump current in uA. The 2 uA for output frequencies + * of 67 MHz or less, and 3 uA for higher output frequencies. The default + * value is 2 uA. + * + * \return CYRET_SUCCESS Completed successfully. + * \return CYRET_BAD_PARAM The parameters are out of range or the specified PLL + * sources the system clock. + * + *******************************************************************************/ + cystatus CySysClkPllSetPQ(uint32 pll, uint32 feedback, uint32 reference, uint32 current) + { + uint32 regTmp; + cystatus tmp; + uint8 interruptState; + cystatus returnStatus = CYRET_BAD_PARAM; + + interruptState = CyEnterCriticalSection(); + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && + (feedback >= CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MIN) && (feedback <= CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MAX) && + (reference >= CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MIN) && (reference <= CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MAX) && + (current >= CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MIN ) && (current <= CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MAX) && + (CYRET_SUCCESS == tmp)) + { + /* Set new feedback, reference and current values */ + regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK | + CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK | + CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK); + + regTmp |= ((feedback << CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK); + regTmp |= (((reference - 1u) << CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK); + regTmp |= ((current << CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT) & CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK); + + CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; + + returnStatus = CYRET_SUCCESS; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetBypassMode + ****************************************************************************//** + * + * Sets the bypass mode for the specified PLL. + * + * The PLL must not be the system clock source when calling this function. + * The PLL output will glitch during this function call. + * + * When the PLL's reference input is higher than HFCLK frequency the device may + * lock due to incorrect flash wait cycle configuration and bypass switches from + * PLL output to the reference input. See description of + * CySysFlashSetWaitCycles() for more information. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param bypass: The bypass mode. + * CY_SYS_PLL_BYPASS_AUTO - Automatic usage of the lock indicator. When unlocked, + * automatically selects PLL the reference input (bypass mode). When locked, + * automatically selects the PLL output. + * + * CY_SYS_PLL_BYPASS_PLL_REF - Selects the PLL reference input (bypass mode). + * Ignores the lock indicator. + * + * CY_SYS_PLL_BYPASS_PLL_OUT - Selects the PLL output. Ignores the lock indicator. + * + *******************************************************************************/ + void CySysClkPllSetBypassMode(uint32 pll, uint32 bypass) + { + uint32 regTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + if ((pll < CY_IP_PLL_NR) && (bypass <= CY_SYS_PLL_BYPASS_PLL_OUT)) + { + regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK; + regTmp |= (uint32)(bypass << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT); + CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetBypassMode + ****************************************************************************//** + * + * Gets the bypass mode for the specified PLL. + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param bypass: Bypass mode. + * The same as the parameter of the CySysClkPllSetBypassMode(). + * + *******************************************************************************/ + static uint32 CySysClkPllGetBypassMode(uint32 pll) + { + uint32 returnValue; + uint8 interruptState; + + CYASSERT(pll < CY_IP_PLL_NR); + + interruptState = CyEnterCriticalSection(); + + returnValue = CY_SYS_CLK_PLL_BASE.pll[pll].config & CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK; + returnValue = returnValue >> CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT; + + CyExitCriticalSection(interruptState); + + return (returnValue); + } + + + /******************************************************************************* + * Function Name: CySysClkPllConfigChangeAllowed + ****************************************************************************//** + * + * The function returns non-zero value if the specified PLL sources the System + * clock and the PLL is not in the bypass mode. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return Non-zero value when the specified PLL sources the System clock and + * the PLL is not in the bypass mode. + * + *******************************************************************************/ + static cystatus CySysClkPllConfigChangeAllowed(uint32 pll) + { + uint32 pllBypassMode; + uint32 sysclkSource; + cystatus returnValue = CYRET_INVALID_STATE; + + sysclkSource = CySysClkGetSysclkSource(); + pllBypassMode = CySysClkPllGetBypassMode(pll); + + if ((CY_SYS_PLL_BYPASS_PLL_REF == pllBypassMode) || + ((CY_SYS_CLK_HFCLK_PLL0 != sysclkSource) && (0u == pll)) + #if (CY_IP_SRSSV2) + || ((CY_SYS_CLK_HFCLK_PLL1 != sysclkSource) && (1u == pll)) + #endif /* (CY_IP_SRSSV2) */ + ) + { + returnValue = CYRET_SUCCESS; + } + + return (returnValue); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetUnlockStatus + ****************************************************************************//** + * + * Returns a non-zero value if the specified PLL output was unlocked. + * The unlock status is an indicator that the PLL has lost a lock at least once + * during its operation. The unlock status is cleared once it is read using + * this API. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return Non-zero value when the specified PLL was unlocked. + * + *******************************************************************************/ + uint32 CySysClkPllGetUnlockStatus(uint32 pll) + { + uint32 returnStatus = 0u; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].test & CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK; + CY_SYS_CLK_PLL_BASE.pll[pll].test |= CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK; + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetFrequency + ****************************************************************************//** + * + * Configures either PLL#0 or PLL#1 for the requested input/output frequencies. + * The input frequency is the frequency of the source to the PLL. The source is + * set using the CySysClkPllSetSource() function. + * + * The PLL must not be the system clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param pll: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param inputFreq The reference frequency in KHz. The valid range is from 1000 to 49152 KHz. + * + * \param pllFreq The target frequency in KHz. The valid range is from 22500 to 49152 KHz. + * + * \param divider The output clock divider for the PLL: + * CY_SYS_PLL_OUTPUT_DIVPASS Pass Through + * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 + * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 + * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 + * + * \param freqTol The tolerance in ppm, 10 ppm is equal to 0.001%. + * + * \return CYRET_SUCCESS The PLL was successfully configured for the requested + * frequency. + * + * \return CYRET_BAD_PARAM The PLL was not able to successfully configure for the + * requested frequency. + * + *******************************************************************************/ + cystatus CySysClkPllSetFrequency(uint32 pll, uint32 inputFreq, uint32 pllFreq, uint32 divider, uint32 freqTol) + { + uint32 qMin; + uint32 qMax; + + uint32 qVal = CY_SYS_CLK_PLL_INVALID; + uint32 pVal = CY_SYS_CLK_PLL_INVALID; + + uint32 q; + uint32 p; + + uint32 fvco; + int32 ferr; + + cystatus tmp; + cystatus returnStatus = CYRET_BAD_PARAM; + + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && + (inputFreq >= CY_SYS_CLK_PLL_INPUT_FREQ_MIN ) && (inputFreq <= CY_SYS_CLK_PLL_INPUT_FREQ_MAX) && + (pllFreq >= CY_SYS_CLK_PLL_OUTPUT_FREQ_MIN ) && (pllFreq <= CY_SYS_CLK_PLL_OUTPUT_FREQ_MAX) && + (divider <= CY_SYS_PLL_OUTPUT_DIV8) && + (CYRET_SUCCESS == tmp)) + { + + /* Minimum feed forward loop divisor */ + qMin = (inputFreq + (CY_SYS_CLK_PLL_FPFDMAX - 1u)) / CY_SYS_CLK_PLL_FPFDMAX; + qMin = (qMin < CY_SYS_CLK_PLL_QMINIP) ? CY_SYS_CLK_PLL_QMINIP : qMin; + + /* Maximum feed forward loop divisor */ + qMax = inputFreq / CY_SYS_CLK_PLL_FPFDMIN; + qMax = (qMax > CY_SYS_CLK_PLL_QMAXIP) ? CY_SYS_CLK_PLL_QMAXIP : qMax; + + if (qMin <= qMax) + { + for(q = qMin; q <= qMax; q++) + { + /* Solve for the feedback divisor value */ + + /* INT((pllFreq * q ) / inputFreq), where INT is normal rounding */ + p = ((pllFreq * q) + (inputFreq / 2u)) / inputFreq; + + /* Calculate the actual VCO frequency (FVCO) */ + fvco = ((inputFreq * p) / q); + + /* Calculate the frequency error (FERR) */ + ferr = ((1000000 * ((int32) fvco - (int32) pllFreq))/ (int32) pllFreq); + + /* Bound check the frequency error and decide next action */ + if ((( -1 * (int32) freqTol) <= ferr) && (ferr <= (int32) freqTol)) + { + qVal = q; + pVal = p; + break; + } + } + + + if ((pVal != CY_SYS_CLK_PLL_INVALID) && (qVal != CY_SYS_CLK_PLL_INVALID)) + { + if (CySysClkPllSetPQ(pll, pVal, qVal, CY_SYS_CLK_PLL_CURRENT_DEFAULT) == CYRET_SUCCESS) + { + returnStatus = CySysClkPllSetOutputDivider(pll, divider); + } + } + } + + } + + return (returnStatus); + } + + /******************************************************************************* + * Function Name: CySysClkPllSetSource + ****************************************************************************//** + * + * Sets the input clock source to the PLL. The PLL must be disabled before + * calling this function. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param source: + * CY_SYS_PLL_SOURCE_IMO IMO + * CY_SYS_PLL_SOURCE_EXTCLK External Clock (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_ECO ECO + * CY_SYS_PLL_SOURCE_DSI0 DSI_OUT[0] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI1 DSI_OUT[1] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI2 DSI_OUT[2] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI3 DSI_OUT[3] (available only for PSoC 4200L) + * + *******************************************************************************/ + void CySysClkPllSetSource(uint32 pll, uint32 source) + { + uint32 regTmp; + uint8 interruptState; + + #if (CY_IP_SRSSLT) + uint8 i = 0u; + #endif /* (CY_IP_SRSSLT) */ + + interruptState = CyEnterCriticalSection(); + + if (pll < CY_IP_PLL_NR) + { + #if(CY_IP_SRSSV2) + regTmp = CY_SYS_CLK_SELECT_REG & (uint32) ~CY_SYS_CLK_SELECT_PLL_MASK(pll); + regTmp |= ((source << CY_SYS_CLK_SELECT_PLL_SHIFT(pll)) & CY_SYS_CLK_SELECT_PLL_MASK(pll)); + CY_SYS_CLK_SELECT_REG = regTmp; + #else + regTmp = CY_SYS_ECO_CLK_SELECT_REG & (uint32) ~CY_SYS_ECO_CLK_SELECT_PLL0_MASK; + regTmp |= ((source << CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT) & CY_SYS_ECO_CLK_SELECT_PLL0_MASK); + CY_SYS_ECO_CLK_SELECT_REG = regTmp; + + /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) + { + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + } + + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + #endif /* (CY_IP_SRSSV2) */ + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetOutputDivider + ****************************************************************************//** + * + * Sets the output clock divider for the PLL. + * + * The PLL must not be the System Clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param divider: + * CY_SYS_PLL_OUTPUT_DIVPASS Pass through + * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 + * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 + * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 + * + * \return \ref CYRET_SUCCESS Completed successfully. + * \return \ref CYRET_BAD_PARAM The parameters are out of range or the + * specified PLL sources the System clock. + * + *******************************************************************************/ + cystatus CySysClkPllSetOutputDivider(uint32 pll, uint32 divider) + { + uint32 tmpReg; + uint8 interruptState; + cystatus returnStatus = CYRET_BAD_PARAM; + cystatus tmp; + + + interruptState = CyEnterCriticalSection(); + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && (CYRET_SUCCESS == tmp) && (divider <= CY_SYS_PLL_OUTPUT_DIV8)) + { + tmpReg = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK); + tmpReg |= ((divider << CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK); + + CY_SYS_CLK_PLL_BASE.pll[pll].config = tmpReg; + + returnStatus = CYRET_SUCCESS; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } +#endif /* (CY_IP_PLL) */ + + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Function Name: CySysLvdEnable + ****************************************************************************//** + * + * Enables the output of the low-voltage monitor when Vddd is at or below the + * trip point, configures the device to generate an interrupt, and sets the + * voltage trip level. + * + * \param threshold: Threshold selection for Low Voltage Detect circuit. + * Threshold variation is +/- 2.5% from these typical voltage choices. + * Define Voltage threshold + * CY_LVD_THRESHOLD_1_75_V 1.7500 V + * CY_LVD_THRESHOLD_1_80_V 1.8000 V + * CY_LVD_THRESHOLD_1_90_V 1.9000 V + * CY_LVD_THRESHOLD_2_00_V 2.0000 V + * CY_LVD_THRESHOLD_2_10_V 2.1000 V + * CY_LVD_THRESHOLD_2_20_V 2.2000 V + * CY_LVD_THRESHOLD_2_30_V 2.3000 V + * CY_LVD_THRESHOLD_2_40_V 2.4000 V + * CY_LVD_THRESHOLD_2_50_V 2.5000 V + * CY_LVD_THRESHOLD_2_60_V 2.6000 V + * CY_LVD_THRESHOLD_2_70_V 2.7000 V + * CY_LVD_THRESHOLD_2_80_V 2.8000 V + * CY_LVD_THRESHOLD_2_90_V 2.9000 V + * CY_LVD_THRESHOLD_3_00_V 3.0000 V + * CY_LVD_THRESHOLD_3_20_V 3.2000 V + * CY_LVD_THRESHOLD_4_50_V 4.5000 V + * + *******************************************************************************/ + void CySysLvdEnable(uint32 threshold) + { + /* Prevent propagating a false interrupt */ + CY_LVD_PWR_INTR_MASK_REG &= (uint32) ~CY_LVD_PROPAGATE_INT_TO_CPU; + + /* Set specified threshold */ + CY_LVD_PWR_VMON_CONFIG_REG = (CY_LVD_PWR_VMON_CONFIG_REG & ~CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK) | + ((threshold << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT) & CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK); + + /* Enable the LVD. This may cause a false LVD event. */ + CY_LVD_PWR_VMON_CONFIG_REG |= CY_LVD_PWR_VMON_CONFIG_LVD_EN; + + /* Wait for the circuit to stabilize */ + CyDelayUs(CY_LVD_STABILIZE_TIMEOUT_US); + + /* Clear the false event */ + CySysLvdClearInterrupt(); + + /* Unmask the interrupt */ + CY_LVD_PWR_INTR_MASK_REG |= CY_LVD_PROPAGATE_INT_TO_CPU; + } + + + /******************************************************************************* + * Function Name: CySysLvdDisable + ****************************************************************************//** + * + * Disables the low voltage detection. A low voltage interrupt is disabled. + * + *******************************************************************************/ + void CySysLvdDisable(void) + { + CY_LVD_PWR_INTR_MASK_REG &= ~CY_LVD_PROPAGATE_INT_TO_CPU; + CY_LVD_PWR_VMON_CONFIG_REG &= ~CY_LVD_PWR_VMON_CONFIG_LVD_EN; + } + + + /******************************************************************************* + * Function Name: CySysLvdGetInterruptSource + ****************************************************************************//** + * + * Gets the low voltage detection interrupt status (without clearing). + * + * \return + * Interrupt request value: + * CY_SYS_LVD_INT - Indicates an Low Voltage Detect interrupt + * + *******************************************************************************/ + uint32 CySysLvdGetInterruptSource(void) + { + return (CY_LVD_PWR_INTR_REG & CY_SYS_LVD_INT); + } + + + /******************************************************************************* + * Function Name: CySysLvdClearInterrupt + ****************************************************************************//** + * + * Clears the low voltage detection interrupt status. + * + * \return + * None + * + *******************************************************************************/ + void CySysLvdClearInterrupt(void) + { + CY_LVD_PWR_INTR_REG = CY_SYS_LVD_INT; + } + +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Function Name: CySysGetResetReason +****************************************************************************//** +* +* Reports the cause for the latest reset(s) that occurred in the system. All +* the bits in the RES_CAUSE register assert when the corresponding reset cause +* occurs and must be cleared by the firmware. These bits are cleared by the +* hardware only during XRES, POR, or a detected brown-out. +* +* \param reason: bits in the RES_CAUSE register to clear. +* CY_SYS_RESET_WDT - WDT caused a reset +* CY_SYS_RESET_PROTFAULT - Occured protection violation that requires reset +* CY_SYS_RESET_SW - Cortex-M0 requested a system reset. +* +* \return +* Status. Same enumerated bit values as used for the reason parameter. +* +*******************************************************************************/ +uint32 CySysGetResetReason(uint32 reason) +{ + uint32 returnStatus; + + reason &= (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); + returnStatus = CY_SYS_RES_CAUSE_REG & + (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); + CY_SYS_RES_CAUSE_REG = reason; + + return (returnStatus); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +****************************************************************************//** +* +* Disables all interrupts. +* +* \return +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + + /* Get current interrupt state. */ + intState = CY_INT_CLEAR_REG; + + /* Disable all interrupts. */ + CY_INT_CLEAR_REG = CY_INT_CLEAR_DISABLE_ALL; + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +****************************************************************************//** +* +* Enables interrupts to a given state. +* +* \param mask The 32 bit mask of interrupts to enable. +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + CY_INT_ENABLE_REG = mask; +} + + +/******************************************************************************* +* Function Name: CyIntSetSysVector +****************************************************************************//** +* +* Sets the interrupt vector of the specified system interrupt number. These +* interrupts are for SysTick, PendSV and others. +* +* \param number: System interrupt number: +* CY_INT_NMI_IRQN - Non Maskable Interrupt +* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +* CY_INT_SVCALL_IRQN - SV Call Interrupt +* CY_INT_PEND_SV_IRQN - Pend SV Interrupt +* CY_INT_SYSTICK_IRQN - System Tick Interrupt +* +* \param address Pointer to an interrupt service routine. +* +* \return The old ISR vector at this location. +* +*******************************************************************************/ +cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) +{ + cyisraddress oldIsr; + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_INT_IRQ_BASE); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number] = address; + + return(oldIsr); +} + + +/******************************************************************************* +* Function Name: CyIntGetSysVector +****************************************************************************//** +* +* Gets the interrupt vector of the specified system interrupt number. These +* interrupts are for SysTick, PendSV and others. +* +* \param number: System interrupt number: +* CY_INT_NMI_IRQN - Non Maskable Interrupt +* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +* CY_INT_SVCALL_IRQN - SV Call Interrupt +* CY_INT_PEND_SV_IRQN - Pend SV Interrupt +* CY_INT_SYSTICK_IRQN - System Tick Interrupt +* +* \return Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress CyIntGetSysVector(uint8 number) +{ + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_INT_IRQ_BASE); + + return(ramVectorTable[number]); +} + + +/******************************************************************************* +* Function Name: CyIntSetVector +****************************************************************************//** +* +* Sets the interrupt vector of the specified interrupt number. +* +* \param number Valid range [0-31]. Interrupt number +* \param address Pointer to an interrupt service routine +* +* \return Previous interrupt vector value. +* +*******************************************************************************/ +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) +{ + cyisraddress oldIsr; + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + number]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + number] = address; + + return(oldIsr); +} + + +/******************************************************************************* +* Function Name: CyIntGetVector +****************************************************************************//** +* +* Gets the interrupt vector of the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number +* +* \return Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress CyIntGetVector(uint8 number) +{ + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + return (ramVectorTable[CY_INT_IRQ_BASE + number]); +} + +/******************************************************************************* +* Function Name: CyIntSetPriority +****************************************************************************//** +* +* Sets the priority of the interrupt. +* +* \param priority: Priority of the interrupt. 0 - 3, 0 being the highest. +* \param number: The number of the interrupt, 0 - 31. +* +*******************************************************************************/ +void CyIntSetPriority(uint8 number, uint8 priority) +{ + uint8 interruptState; + uint32 shift; + uint32 value; + + CYASSERT(priority <= CY_MIN_PRIORITY); + CYASSERT(number < CY_NUM_INTERRUPTS); + + shift = CY_INT_PRIORITY_SHIFT(number); + + interruptState = CyEnterCriticalSection(); + + value = CY_INT_PRIORITY_REG(number); + value &= (uint32)(~((uint32)(CY_INT_PRIORITY_MASK << shift))); + value |= ((uint32)priority << shift); + CY_INT_PRIORITY_REG(number) = value; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyIntGetPriority +****************************************************************************//** +* +* Gets the priority of the interrupt. +* +* \param number: The number of the interrupt, 0 - 31. +* +* \return +* Priority of the interrupt. 0 - 3, 0 being the highest. +* +*******************************************************************************/ +uint8 CyIntGetPriority(uint8 number) +{ + uint8 priority; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + priority = (uint8) (CY_INT_PRIORITY_REG(number) >> CY_INT_PRIORITY_SHIFT(number)); + + return (priority & (uint8) CY_INT_PRIORITY_MASK); +} + + +/******************************************************************************* +* Function Name: CyIntEnable +****************************************************************************//** +* +* Enables the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number +* +*******************************************************************************/ +void CyIntEnable(uint8 number) +{ + CY_INT_ENABLE_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyIntGetState +****************************************************************************//** +* +* Gets the enable state of the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +* \return +* Enable status: 1 if enabled, 0 if disabled +* +*******************************************************************************/ +uint8 CyIntGetState(uint8 number) +{ + /* Get state of interrupt. */ + return ((0u != (CY_INT_ENABLE_REG & ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)))) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyIntDisable +****************************************************************************//** +* +* Disables the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntDisable(uint8 number) +{ + CY_INT_CLEAR_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + +/******************************************************************************* +* Function Name: CyIntSetPending +****************************************************************************//** +* +* Forces the specified interrupt number to be pending. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntSetPending(uint8 number) +{ + CY_INT_SET_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyIntClearPending +****************************************************************************//** +* +* Clears any pending interrupt for the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntClearPending(uint8 number) +{ + CY_INT_CLR_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyHalt +****************************************************************************//** +* +* Halts the CPU. +* +* \param reason: Value to be used during debugging. +* +*******************************************************************************/ +void CyHalt(uint8 reason) +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +****************************************************************************//** +* +* Forces a software reset of the device. +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + /*************************************************************************** + * Setting the system reset request bit. The vector key value must be written + * to the register, otherwise the register write is unpredictable. + ***************************************************************************/ + CY_SYS_AIRCR_REG = (CY_SYS_AIRCR_REG & (uint32)(~CY_SYS_AIRCR_VECTKEY_MASK)) | + CY_SYS_AIRCR_VECTKEY | CY_SYS_AIRCR_SYSRESETREQ; +} + + +/******************************************************************************* +* Function Name: CyDelay +****************************************************************************//** +* +* Blocks for milliseconds. +* +* \param milliseconds: number of milliseconds to delay. +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) +{ + while (milliseconds > CY_DELAY_MS_OVERFLOW) + { + /* This loop prevents overflow. + * At 100MHz, milliseconds * cydelayFreqKhz overflows at about 42 seconds + */ + CyDelayCycles(cydelay32kMs); + milliseconds -= CY_DELAY_MS_OVERFLOW; + } + + CyDelayCycles(milliseconds * cydelayFreqKhz); +} + + +/******************************************************************************* +* Function Name: CyDelayUs +****************************************************************************//** +* Blocks for microseconds. +* +* \param microseconds: number of microseconds to delay. +* +*******************************************************************************/ +void CyDelayUs(uint16 microseconds) +{ + CyDelayCycles((uint32)microseconds * cydelayFreqMhz); +} + + +/******************************************************************************* +* Function Name: CyDelayFreq +****************************************************************************//** +* Sets clock frequency for CyDelay. +* +* \param freq: Frequency of bus clock in Hertz. +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) +{ + if (freq != 0u) + { + cydelayFreqHz = freq; + } + else + { + cydelayFreqHz = CYDEV_BCLK__SYSCLK__HZ; + } + + cydelayFreqMhz = (uint8)((cydelayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cydelayFreqKhz = (cydelayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cydelay32kMs = CY_DELAY_MS_OVERFLOW * cydelayFreqKhz; +} + + +/******************************************************************************* +* Function Name: CySysTick_Start +****************************************************************************//** +* +* Starts the system timer (SysTick): configures SysTick to generate interrupt +* every 1 ms and enables the interrupt. +* +* There are components (LIN, CapSense Gesture) that relies on the default +* interval (1 ms). And that changing the interval will negatively impact +* their functionality. +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +void CySysTickStart(void) +{ + if (0u == CySysTickInitVar) + { + CySysTickInit(); + CySysTickInitVar = 1u; + } + + CySysTickEnable(); +} + + +/******************************************************************************* +* Function Name: CySysTickInit +****************************************************************************//** +* +* Initializes the callback addresses with pointers to NULL, associates the +* SysTick system vector with the function that is responsible for calling +* registered callback functions, configures SysTick timer to generate interrupt +* every 1 ms. +* +* The 1 ms interrupt interval is configured based on the frequency determined +* by PSoC Creator at build time. If System clock frequency is changed in +* runtime, the CyDelayFreq() with the appropriate parameter should be called. +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +void CySysTickInit(void) +{ + uint32 i; + + for (i = 0u; i> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ); + } + +#endif /* (CY_SYSTICK_LFCLK_SOURCE) */ + + +/******************************************************************************* +* Function Name: CySysTickGetCountFlag +****************************************************************************//** +* +* The count flag is set once SysTick counter reaches zero. +* The flag cleared on read. +* +* \return + * Returns non-zero value if flag is set, otherwise zero is returned. +* +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +uint32 CySysTickGetCountFlag(void) +{ + return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); +} + + +/******************************************************************************* +* Function Name: CySysTickClear +****************************************************************************//** +* +* Clears the SysTick counter for well-defined startup. +* +*******************************************************************************/ +void CySysTickClear(void) +{ + CY_SYS_SYST_CVR_REG = 0u; +} + + +/******************************************************************************* +* Function Name: CySysTickSetCallback +****************************************************************************//** +* +* This function allows up to five user-defined interrupt service routine +* functions to be associated with the SysTick interrupt. These are specified +* through the use of pointers to the function. +* +* To set a custom callback function without the overhead of the system provided +* one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress