diff --git a/clang-tools-extra/clang-tidy/utils/IncludeInserter.h b/clang-tools-extra/clang-tidy/utils/IncludeInserter.h
index 95236c732f1309..74903b2d166db1 100644
--- a/clang-tools-extra/clang-tidy/utils/IncludeInserter.h
+++ b/clang-tools-extra/clang-tidy/utils/IncludeInserter.h
@@ -34,7 +34,7 @@ namespace utils {
 ///  public:
 ///   void registerPPCallbacks(const SourceManager &SM, Preprocessor *PP,
 ///                            Preprocessor *ModuleExpanderPP) override {
-///     Inserter.registerPreprocessor();
+///     Inserter.registerPreprocessor(PP);
 ///   }
 ///
 ///   void registerMatchers(ast_matchers::MatchFinder* Finder) override { ... }
@@ -42,8 +42,7 @@ namespace utils {
 ///   void check(
 ///       const ast_matchers::MatchFinder::MatchResult& Result) override {
 ///     ...
-///     Inserter.createMainFileIncludeInsertion("path/to/Header.h",
-///                                             /*IsAngled=*/false);
+///     Inserter.createMainFileIncludeInsertion("path/to/Header.h");
 ///     ...
 ///   }
 ///
diff --git a/clang-tools-extra/clangd/ClangdLSPServer.cpp b/clang-tools-extra/clangd/ClangdLSPServer.cpp
index 9ed635c88e7195..d46147ac89cd8a 100644
--- a/clang-tools-extra/clangd/ClangdLSPServer.cpp
+++ b/clang-tools-extra/clangd/ClangdLSPServer.cpp
@@ -7,6 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "ClangdLSPServer.h"
+#include "ClangdServer.h"
 #include "CodeComplete.h"
 #include "Diagnostics.h"
 #include "DraftStore.h"
@@ -18,6 +19,7 @@
 #include "URI.h"
 #include "refactor/Tweak.h"
 #include "support/Context.h"
+#include "support/MemoryTree.h"
 #include "support/Trace.h"
 #include "clang/Basic/Version.h"
 #include "clang/Tooling/Core/Replacement.h"
@@ -26,6 +28,7 @@
 #include "llvm/ADT/ScopeExit.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/iterator_range.h"
+#include "llvm/Support/Allocator.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/FormatVariadic.h"
@@ -33,6 +36,7 @@
 #include "llvm/Support/Path.h"
 #include "llvm/Support/SHA1.h"
 #include "llvm/Support/ScopedPrinter.h"
+#include <chrono>
 #include <cstddef>
 #include <memory>
 #include <mutex>
@@ -144,7 +148,6 @@ llvm::Error validateEdits(const DraftStore &DraftMgr, const FileEdits &FE) {
   return error("Files must be saved first: {0} (and {1} others)",
                LastInvalidFile, InvalidFileCount - 1);
 }
-
 } // namespace
 
 // MessageHandler dispatches incoming LSP messages.
@@ -163,14 +166,16 @@ class ClangdLSPServer::MessageHandler : public Transport::MessageHandler {
     log("<-- {0}", Method);
     if (Method == "exit")
       return false;
-    if (!Server.Server)
+    if (!Server.Server) {
       elog("Notification {0} before initialization", Method);
-    else if (Method == "$/cancelRequest")
+    } else if (Method == "$/cancelRequest") {
       onCancel(std::move(Params));
-    else if (auto Handler = Notifications.lookup(Method))
+    } else if (auto Handler = Notifications.lookup(Method)) {
       Handler(std::move(Params));
-    else
+      Server.maybeExportMemoryProfile();
+    } else {
       log("unhandled notification {0}", Method);
+    }
     return true;
   }
 
@@ -1049,22 +1054,21 @@ void ClangdLSPServer::onCompletion(const CompletionParams &Params,
     vlog("ignored auto-triggered completion, preceding char did not match");
     return Reply(CompletionList());
   }
-  Server->codeComplete(Params.textDocument.uri.file(), Params.position,
-                       Opts.CodeComplete,
-                       [Reply = std::move(Reply),
-                        this](llvm::Expected<CodeCompleteResult> List) mutable {
-                         if (!List)
-                           return Reply(List.takeError());
-                         CompletionList LSPList;
-                         LSPList.isIncomplete = List->HasMore;
-                         for (const auto &R : List->Completions) {
-                           CompletionItem C = R.render(Opts.CodeComplete);
-                           C.kind = adjustKindToCapability(
-                               C.kind, SupportedCompletionItemKinds);
-                           LSPList.items.push_back(std::move(C));
-                         }
-                         return Reply(std::move(LSPList));
-                       });
+  Server->codeComplete(
+      Params.textDocument.uri.file(), Params.position, Opts.CodeComplete,
+      [Reply = std::move(Reply),
+       this](llvm::Expected<CodeCompleteResult> List) mutable {
+        if (!List)
+          return Reply(List.takeError());
+        CompletionList LSPList;
+        LSPList.isIncomplete = List->HasMore;
+        for (const auto &R : List->Completions) {
+          CompletionItem C = R.render(Opts.CodeComplete);
+          C.kind = adjustKindToCapability(C.kind, SupportedCompletionItemKinds);
+          LSPList.items.push_back(std::move(C));
+        }
+        return Reply(std::move(LSPList));
+      });
 }
 
 void ClangdLSPServer::onSignatureHelp(const TextDocumentPositionParams &Params,
@@ -1235,6 +1239,25 @@ void ClangdLSPServer::publishDiagnostics(
   notify("textDocument/publishDiagnostics", Params);
 }
 
+void ClangdLSPServer::maybeExportMemoryProfile() {
+  if (!trace::enabled())
+    return;
+  // Profiling might be expensive, so we throttle it to happen once every 5
+  // minutes.
+  static constexpr auto ProfileInterval = std::chrono::minutes(5);
+  auto Now = std::chrono::steady_clock::now();
+  if (Now < NextProfileTime)
+    return;
+
+  static constexpr trace::Metric MemoryUsage(
+      "memory_usage", trace::Metric::Value, "component_name");
+  trace::Span Tracer("ProfileBrief");
+  MemoryTree MT;
+  profile(MT);
+  record(MT, "clangd_lsp_server", MemoryUsage);
+  NextProfileTime = Now + ProfileInterval;
+}
+
 // FIXME: This function needs to be properly tested.
 void ClangdLSPServer::onChangeConfiguration(
     const DidChangeConfigurationParams &Params) {
@@ -1405,6 +1428,9 @@ ClangdLSPServer::ClangdLSPServer(class Transport &Transp,
   if (Opts.FoldingRanges)
     MsgHandler->bind("textDocument/foldingRange", &ClangdLSPServer::onFoldingRange);
   // clang-format on
+
+  // Delay first profile until we've finished warming up.
+  NextProfileTime = std::chrono::steady_clock::now() + std::chrono::minutes(1);
 }
 
 ClangdLSPServer::~ClangdLSPServer() {
@@ -1425,6 +1451,11 @@ bool ClangdLSPServer::run() {
   return CleanExit && ShutdownRequestReceived;
 }
 
+void ClangdLSPServer::profile(MemoryTree &MT) const {
+  if (Server)
+    Server->profile(MT.child("clangd_server"));
+}
+
 std::vector<Fix> ClangdLSPServer::getFixes(llvm::StringRef File,
                                            const clangd::Diagnostic &D) {
   std::lock_guard<std::mutex> Lock(FixItsMutex);
diff --git a/clang-tools-extra/clangd/ClangdLSPServer.h b/clang-tools-extra/clangd/ClangdLSPServer.h
index a853a408715620..7054c48652c568 100644
--- a/clang-tools-extra/clangd/ClangdLSPServer.h
+++ b/clang-tools-extra/clangd/ClangdLSPServer.h
@@ -17,11 +17,13 @@
 #include "Protocol.h"
 #include "Transport.h"
 #include "support/Context.h"
+#include "support/MemoryTree.h"
 #include "support/Path.h"
 #include "clang/Tooling/Core/Replacement.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/StringSet.h"
 #include "llvm/Support/JSON.h"
+#include <chrono>
 #include <memory>
 
 namespace clang {
@@ -67,6 +69,9 @@ class ClangdLSPServer : private ClangdServer::Callbacks {
   /// \return Whether we shut down cleanly with a 'shutdown' -> 'exit' sequence.
   bool run();
 
+  /// Profiles resource-usage.
+  void profile(MemoryTree &MT) const;
+
 private:
   // Implement ClangdServer::Callbacks.
   void onDiagnosticsReady(PathRef File, llvm::StringRef Version,
@@ -160,6 +165,14 @@ class ClangdLSPServer : private ClangdServer::Callbacks {
   /// Sends a "publishDiagnostics" notification to the LSP client.
   void publishDiagnostics(const PublishDiagnosticsParams &);
 
+  /// Runs profiling and exports memory usage metrics if tracing is enabled and
+  /// profiling hasn't happened recently.
+  void maybeExportMemoryProfile();
+
+  /// Timepoint until which profiling is off. It is used to throttle profiling
+  /// requests.
+  std::chrono::steady_clock::time_point NextProfileTime;
+
   /// Since initialization of CDBs and ClangdServer is done lazily, the
   /// following context captures the one used while creating ClangdLSPServer and
   /// passes it to above mentioned object instances to make sure they share the
diff --git a/clang-tools-extra/clangd/ClangdServer.cpp b/clang-tools-extra/clangd/ClangdServer.cpp
index 93e3b10b50d55e..82dd7436b6f42f 100644
--- a/clang-tools-extra/clangd/ClangdServer.cpp
+++ b/clang-tools-extra/clangd/ClangdServer.cpp
@@ -28,6 +28,7 @@
 #include "refactor/Tweak.h"
 #include "support/Logger.h"
 #include "support/Markup.h"
+#include "support/MemoryTree.h"
 #include "support/ThreadsafeFS.h"
 #include "support/Trace.h"
 #include "clang/Format/Format.h"
@@ -826,5 +827,12 @@ ClangdServer::blockUntilIdleForTest(llvm::Optional<double> TimeoutSeconds) {
           BackgroundIdx->blockUntilIdleForTest(TimeoutSeconds));
 }
 
+void ClangdServer::profile(MemoryTree &MT) const {
+  if (DynamicIdx)
+    DynamicIdx->profile(MT.child("dynamic_index"));
+  if (BackgroundIdx)
+    BackgroundIdx->profile(MT.child("background_index"));
+  WorkScheduler.profile(MT.child("tuscheduler"));
+}
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/ClangdServer.h b/clang-tools-extra/clangd/ClangdServer.h
index efba7ace648964..555f387ff3297e 100644
--- a/clang-tools-extra/clangd/ClangdServer.h
+++ b/clang-tools-extra/clangd/ClangdServer.h
@@ -25,6 +25,7 @@
 #include "refactor/Tweak.h"
 #include "support/Cancellation.h"
 #include "support/Function.h"
+#include "support/MemoryTree.h"
 #include "support/ThreadsafeFS.h"
 #include "clang/Tooling/CompilationDatabase.h"
 #include "clang/Tooling/Core/Replacement.h"
@@ -337,6 +338,9 @@ class ClangdServer {
   LLVM_NODISCARD bool
   blockUntilIdleForTest(llvm::Optional<double> TimeoutSeconds = 10);
 
+  /// Builds a nested representation of memory used by components.
+  void profile(MemoryTree &MT) const;
+
 private:
   void formatCode(PathRef File, llvm::StringRef Code,
                   ArrayRef<tooling::Range> Ranges,
diff --git a/clang-tools-extra/clangd/Protocol.cpp b/clang-tools-extra/clangd/Protocol.cpp
index f8aca226a599e4..f41cea28fea35b 100644
--- a/clang-tools-extra/clangd/Protocol.cpp
+++ b/clang-tools-extra/clangd/Protocol.cpp
@@ -484,12 +484,10 @@ bool fromJSON(const llvm::json::Value &Params, DidSaveTextDocumentParams &R,
 bool fromJSON(const llvm::json::Value &Params, DidChangeTextDocumentParams &R,
               llvm::json::Path P) {
   llvm::json::ObjectMapper O(Params, P);
-  if (!O)
-    return false;
-  O.map("forceRebuild", R.forceRebuild);  // Optional clangd extension.
-  return O.map("textDocument", R.textDocument) &&
+  return O && O.map("textDocument", R.textDocument) &&
          O.map("contentChanges", R.contentChanges) &&
-         O.map("wantDiagnostics", R.wantDiagnostics);
+         O.map("wantDiagnostics", R.wantDiagnostics) &&
+         O.mapOptional("forceRebuild", R.forceRebuild);
 }
 
 bool fromJSON(const llvm::json::Value &E, FileChangeType &Out,
@@ -578,12 +576,10 @@ llvm::json::Value toJSON(const Diagnostic &D) {
 bool fromJSON(const llvm::json::Value &Params, Diagnostic &R,
               llvm::json::Path P) {
   llvm::json::ObjectMapper O(Params, P);
-  if (!O || !O.map("range", R.range) || !O.map("message", R.message))
-    return false;
-  O.map("severity", R.severity);
-  O.map("category", R.category);
-  O.map("code", R.code);
-  O.map("source", R.source);
+  return O && O.map("range", R.range) && O.map("message", R.message) &&
+         O.mapOptional("severity", R.severity) &&
+         O.mapOptional("category", R.category) &&
+         O.mapOptional("code", R.code) && O.mapOptional("source", R.source);
   return true;
 }
 
@@ -800,10 +796,8 @@ llvm::json::Value toJSON(const ApplyWorkspaceEditParams &Params) {
 bool fromJSON(const llvm::json::Value &Response, ApplyWorkspaceEditResponse &R,
               llvm::json::Path P) {
   llvm::json::ObjectMapper O(Response, P);
-  if (!O || !O.map("applied", R.applied))
-    return false;
-  O.map("failureReason", R.failureReason);
-  return true;
+  return O && O.map("applied", R.applied) &&
+         O.map("failureReason", R.failureReason);
 }
 
 bool fromJSON(const llvm::json::Value &Params, TextDocumentPositionParams &R,
@@ -816,16 +810,11 @@ bool fromJSON(const llvm::json::Value &Params, TextDocumentPositionParams &R,
 bool fromJSON(const llvm::json::Value &Params, CompletionContext &R,
               llvm::json::Path P) {
   llvm::json::ObjectMapper O(Params, P);
-  if (!O)
-    return false;
-
   int TriggerKind;
-  if (!O.map("triggerKind", TriggerKind))
+  if (!O || !O.map("triggerKind", TriggerKind) ||
+      !O.mapOptional("triggerCharacter", R.triggerCharacter))
     return false;
   R.triggerKind = static_cast<CompletionTriggerKind>(TriggerKind);
-
-  if (auto *TC = Params.getAsObject()->get("triggerCharacter"))
-    return fromJSON(*TC, R.triggerCharacter, P.field("triggerCharacter"));
   return true;
 }
 
@@ -1126,8 +1115,8 @@ bool fromJSON(const llvm::json::Value &Params, ConfigurationSettings &S,
   llvm::json::ObjectMapper O(Params, P);
   if (!O)
     return true; // 'any' type in LSP.
-  O.map("compilationDatabaseChanges", S.compilationDatabaseChanges);
-  return true;
+  return O.mapOptional("compilationDatabaseChanges",
+                       S.compilationDatabaseChanges);
 }
 
 bool fromJSON(const llvm::json::Value &Params, InitializationOptions &Opts,
@@ -1136,11 +1125,10 @@ bool fromJSON(const llvm::json::Value &Params, InitializationOptions &Opts,
   if (!O)
     return true; // 'any' type in LSP.
 
-  fromJSON(Params, Opts.ConfigSettings, P);
-  O.map("compilationDatabasePath", Opts.compilationDatabasePath);
-  O.map("fallbackFlags", Opts.fallbackFlags);
-  O.map("clangdFileStatus", Opts.FileStatus);
-  return true;
+  return fromJSON(Params, Opts.ConfigSettings, P) &&
+         O.map("compilationDatabasePath", Opts.compilationDatabasePath) &&
+         O.mapOptional("fallbackFlags", Opts.fallbackFlags) &&
+         O.mapOptional("clangdFileStatus", Opts.FileStatus);
 }
 
 bool fromJSON(const llvm::json::Value &E, TypeHierarchyDirection &Out,
@@ -1193,20 +1181,13 @@ bool fromJSON(const llvm::json::Value &Params, TypeHierarchyItem &I,
   llvm::json::ObjectMapper O(Params, P);
 
   // Required fields.
-  if (!(O && O.map("name", I.name) && O.map("kind", I.kind) &&
-        O.map("uri", I.uri) && O.map("range", I.range) &&
-        O.map("selectionRange", I.selectionRange))) {
-    return false;
-  }
-
-  // Optional fields.
-  O.map("detail", I.detail);
-  O.map("deprecated", I.deprecated);
-  O.map("parents", I.parents);
-  O.map("children", I.children);
-  O.map("data", I.data);
-
-  return true;
+  return O && O.map("name", I.name) && O.map("kind", I.kind) &&
+         O.map("uri", I.uri) && O.map("range", I.range) &&
+         O.map("selectionRange", I.selectionRange) &&
+         O.mapOptional("detail", I.detail) &&
+         O.mapOptional("deprecated", I.deprecated) &&
+         O.mapOptional("parents", I.parents) &&
+         O.mapOptional("children", I.children) && O.mapOptional("data", I.data);
 }
 
 bool fromJSON(const llvm::json::Value &Params,
diff --git a/clang-tools-extra/clangd/TUScheduler.cpp b/clang-tools-extra/clangd/TUScheduler.cpp
index c408c8c0731de5..baf3f910b45ee8 100644
--- a/clang-tools-extra/clangd/TUScheduler.cpp
+++ b/clang-tools-extra/clangd/TUScheduler.cpp
@@ -56,6 +56,7 @@
 #include "support/Cancellation.h"
 #include "support/Context.h"
 #include "support/Logger.h"
+#include "support/MemoryTree.h"
 #include "support/Path.h"
 #include "support/Threading.h"
 #include "support/Trace.h"
@@ -932,9 +933,9 @@ TUScheduler::FileStats ASTWorker::stats() const {
   // Note that we don't report the size of ASTs currently used for processing
   // the in-flight requests. We used this information for debugging purposes
   // only, so this should be fine.
-  Result.UsedBytes = IdleASTs.getUsedBytes(this);
+  Result.UsedBytesAST = IdleASTs.getUsedBytes(this);
   if (auto Preamble = getPossiblyStalePreamble())
-    Result.UsedBytes += Preamble->Preamble.getSize();
+    Result.UsedBytesPreamble = Preamble->Preamble.getSize();
   return Result;
 }
 
@@ -1429,5 +1430,14 @@ DebouncePolicy DebouncePolicy::fixed(clock::duration T) {
   return P;
 }
 
+void TUScheduler::profile(MemoryTree &MT) const {
+  for (const auto &Elem : fileStats()) {
+    MT.detail(Elem.first())
+        .child("preamble")
+        .addUsage(Opts.StorePreamblesInMemory ? Elem.second.UsedBytesPreamble
+                                              : 0);
+    MT.detail(Elem.first()).child("ast").addUsage(Elem.second.UsedBytesAST);
+  }
+}
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/TUScheduler.h b/clang-tools-extra/clangd/TUScheduler.h
index 5d545b366ec3e0..cc38db8071aba5 100644
--- a/clang-tools-extra/clangd/TUScheduler.h
+++ b/clang-tools-extra/clangd/TUScheduler.h
@@ -14,6 +14,7 @@
 #include "GlobalCompilationDatabase.h"
 #include "index/CanonicalIncludes.h"
 #include "support/Function.h"
+#include "support/MemoryTree.h"
 #include "support/Path.h"
 #include "support/Threading.h"
 #include "llvm/ADT/Optional.h"
@@ -207,7 +208,8 @@ class TUScheduler {
   ~TUScheduler();
 
   struct FileStats {
-    std::size_t UsedBytes = 0;
+    std::size_t UsedBytesAST = 0;
+    std::size_t UsedBytesPreamble = 0;
     unsigned PreambleBuilds = 0;
     unsigned ASTBuilds = 0;
   };
@@ -311,6 +313,8 @@ class TUScheduler {
   // FIXME: move to ClangdServer via createProcessingContext.
   static llvm::Optional<llvm::StringRef> getFileBeingProcessedInContext();
 
+  void profile(MemoryTree &MT) const;
+
 private:
   const GlobalCompilationDatabase &CDB;
   Options Opts;
diff --git a/clang-tools-extra/clangd/index/Background.cpp b/clang-tools-extra/clangd/index/Background.cpp
index a1aafeaf31a96e..4779cb8d4c23af 100644
--- a/clang-tools-extra/clangd/index/Background.cpp
+++ b/clang-tools-extra/clangd/index/Background.cpp
@@ -16,6 +16,7 @@
 #include "URI.h"
 #include "index/BackgroundIndexLoader.h"
 #include "index/FileIndex.h"
+#include "index/Index.h"
 #include "index/IndexAction.h"
 #include "index/MemIndex.h"
 #include "index/Ref.h"
@@ -414,5 +415,10 @@ BackgroundIndex::loadProject(std::vector<std::string> MainFiles) {
   return {TUsToIndex.begin(), TUsToIndex.end()};
 }
 
+void BackgroundIndex::profile(MemoryTree &MT) const {
+  IndexedSymbols.profile(MT.child("symbols"));
+  // We don't want to mix memory used by index and symbols, so call base class.
+  MT.child("index").addUsage(SwapIndex::estimateMemoryUsage());
+}
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/index/Background.h b/clang-tools-extra/clangd/index/Background.h
index 472603013a53ac..e8f9468889f2a9 100644
--- a/clang-tools-extra/clangd/index/Background.h
+++ b/clang-tools-extra/clangd/index/Background.h
@@ -16,9 +16,11 @@
 #include "index/Index.h"
 #include "index/Serialization.h"
 #include "support/Context.h"
+#include "support/MemoryTree.h"
 #include "support/Path.h"
 #include "support/Threading.h"
 #include "support/ThreadsafeFS.h"
+#include "support/Trace.h"
 #include "clang/Tooling/CompilationDatabase.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/Support/Threading.h"
@@ -172,6 +174,8 @@ class BackgroundIndex : public SwapIndex {
     return Queue.blockUntilIdleForTest(TimeoutSeconds);
   }
 
+  void profile(MemoryTree &MT) const;
+
 private:
   /// Represents the state of a single file when indexing was performed.
   struct ShardVersion {
diff --git a/clang-tools-extra/clangd/index/FileIndex.cpp b/clang-tools-extra/clangd/index/FileIndex.cpp
index ad55b6ad7f5db1..587c7eb781700c 100644
--- a/clang-tools-extra/clangd/index/FileIndex.cpp
+++ b/clang-tools-extra/clangd/index/FileIndex.cpp
@@ -22,6 +22,7 @@
 #include "index/SymbolOrigin.h"
 #include "index/dex/Dex.h"
 #include "support/Logger.h"
+#include "support/MemoryTree.h"
 #include "support/Path.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/Index/IndexingAction.h"
@@ -388,6 +389,25 @@ FileSymbols::buildIndex(IndexType Type, DuplicateHandling DuplicateHandle,
   llvm_unreachable("Unknown clangd::IndexType");
 }
 
+void FileSymbols::profile(MemoryTree &MT) const {
+  std::lock_guard<std::mutex> Lock(Mutex);
+  for (const auto &SymSlab : SymbolsSnapshot) {
+    MT.detail(SymSlab.first())
+        .child("symbols")
+        .addUsage(SymSlab.second->bytes());
+  }
+  for (const auto &RefSlab : RefsSnapshot) {
+    MT.detail(RefSlab.first())
+        .child("references")
+        .addUsage(RefSlab.second.Slab->bytes());
+  }
+  for (const auto &RelSlab : RelationsSnapshot) {
+    MT.detail(RelSlab.first())
+        .child("relations")
+        .addUsage(RelSlab.second->bytes());
+  }
+}
+
 FileIndex::FileIndex(bool UseDex, bool CollectMainFileRefs)
     : MergedIndex(&MainFileIndex, &PreambleIndex), UseDex(UseDex),
       CollectMainFileRefs(CollectMainFileRefs),
@@ -457,5 +477,15 @@ void FileIndex::updateMain(PathRef Path, ParsedAST &AST) {
   }
 }
 
+void FileIndex::profile(MemoryTree &MT) const {
+  PreambleSymbols.profile(MT.child("preamble").child("symbols"));
+  MT.child("preamble")
+      .child("index")
+      .addUsage(PreambleIndex.estimateMemoryUsage());
+  MainFileSymbols.profile(MT.child("main_file").child("symbols"));
+  MT.child("main_file")
+      .child("index")
+      .addUsage(MainFileIndex.estimateMemoryUsage());
+}
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/index/FileIndex.h b/clang-tools-extra/clangd/index/FileIndex.h
index 127203c84c48ab..8ecae66373a5e3 100644
--- a/clang-tools-extra/clangd/index/FileIndex.h
+++ b/clang-tools-extra/clangd/index/FileIndex.h
@@ -24,6 +24,7 @@
 #include "index/Relation.h"
 #include "index/Serialization.h"
 #include "index/Symbol.h"
+#include "support/MemoryTree.h"
 #include "support/Path.h"
 #include "clang/Lex/Preprocessor.h"
 #include "clang/Tooling/CompilationDatabase.h"
@@ -87,6 +88,8 @@ class FileSymbols {
              DuplicateHandling DuplicateHandle = DuplicateHandling::PickOne,
              size_t *Version = nullptr);
 
+  void profile(MemoryTree &MT) const;
+
 private:
   struct RefSlabAndCountReferences {
     std::shared_ptr<RefSlab> Slab;
@@ -116,6 +119,8 @@ class FileIndex : public MergedIndex {
   /// `indexMainDecls`.
   void updateMain(PathRef Path, ParsedAST &AST);
 
+  void profile(MemoryTree &MT) const;
+
 private:
   bool UseDex; // FIXME: this should be always on.
   bool CollectMainFileRefs;
diff --git a/clang-tools-extra/clangd/support/CMakeLists.txt b/clang-tools-extra/clangd/support/CMakeLists.txt
index ce08f7d58cd09d..e3412447142c44 100644
--- a/clang-tools-extra/clangd/support/CMakeLists.txt
+++ b/clang-tools-extra/clangd/support/CMakeLists.txt
@@ -21,6 +21,7 @@ add_clang_library(clangdSupport
   Context.cpp
   Logger.cpp
   Markup.cpp
+  MemoryTree.cpp
   Shutdown.cpp
   Threading.cpp
   ThreadsafeFS.cpp
diff --git a/clang-tools-extra/clangd/support/MemoryTree.cpp b/clang-tools-extra/clangd/support/MemoryTree.cpp
new file mode 100644
index 00000000000000..a495778b9e5bce
--- /dev/null
+++ b/clang-tools-extra/clangd/support/MemoryTree.cpp
@@ -0,0 +1,51 @@
+#include "support/MemoryTree.h"
+#include "Trace.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringRef.h"
+#include <cstddef>
+
+namespace clang {
+namespace clangd {
+
+namespace {
+
+size_t traverseTree(const MemoryTree &MT, std::string &ComponentName,
+                    const trace::Metric &Out) {
+  size_t OriginalLen = ComponentName.size();
+  if (!ComponentName.empty())
+    ComponentName += '.';
+  size_t Total = MT.self();
+  for (const auto &Entry : MT.children()) {
+    ComponentName += Entry.first;
+    Total += traverseTree(Entry.getSecond(), ComponentName, Out);
+    ComponentName.resize(OriginalLen + 1);
+  }
+  ComponentName.resize(OriginalLen);
+  Out.record(Total, ComponentName);
+  return Total;
+}
+} // namespace
+
+MemoryTree &MemoryTree::createChild(llvm::StringRef Name) {
+  auto &Child = Children.try_emplace(Name, DetailAlloc).first->getSecond();
+  return Child;
+}
+
+const llvm::DenseMap<llvm::StringRef, MemoryTree> &
+MemoryTree::children() const {
+  return Children;
+}
+
+size_t MemoryTree::total() const {
+  size_t Total = Size;
+  for (const auto &Entry : Children)
+    Total += Entry.getSecond().total();
+  return Total;
+}
+
+void record(const MemoryTree &MT, std::string RootName,
+            const trace::Metric &Out) {
+  traverseTree(MT, RootName, Out);
+}
+} // namespace clangd
+} // namespace clang
diff --git a/clang-tools-extra/clangd/support/MemoryTree.h b/clang-tools-extra/clangd/support/MemoryTree.h
new file mode 100644
index 00000000000000..903cd64ebb7cfa
--- /dev/null
+++ b/clang-tools-extra/clangd/support/MemoryTree.h
@@ -0,0 +1,92 @@
+//===--- MemoryTree.h - A special tree for components and sizes -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANGD_SUPPORT_MEMORYTREE_H_
+#define LLVM_CLANG_TOOLS_EXTRA_CLANGD_SUPPORT_MEMORYTREE_H_
+
+#include "Trace.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/Allocator.h"
+#include "llvm/Support/StringSaver.h"
+#include <cstddef>
+#include <string>
+#include <vector>
+
+namespace clang {
+namespace clangd {
+
+/// A tree that can be used to represent memory usage of nested components while
+/// preserving the hierarchy.
+/// Edges have associated names. An edge that might not be interesting to all
+/// traversers or costly to copy (e.g. file names) can be marked as "detail".
+/// Tree construction allows chosing between a detailed and brief mode, in brief
+/// mode all "detail" edges are ignored and tree is constructed without any
+/// string copies.
+struct MemoryTree {
+public:
+  /// If Alloc is nullptr, tree is in brief mode and will ignore detail edges.
+  MemoryTree(llvm::BumpPtrAllocator *DetailAlloc = nullptr)
+      : DetailAlloc(DetailAlloc) {}
+
+  /// No copy of the \p Name.
+  /// Note that returned pointers are invalidated with subsequent calls to
+  /// child/detail.
+  MemoryTree &child(llvm::StringLiteral Name) { return createChild(Name); }
+
+  MemoryTree(const MemoryTree &) = delete;
+  MemoryTree &operator=(const MemoryTree &) = delete;
+
+  MemoryTree(MemoryTree &&) = default;
+  MemoryTree &operator=(MemoryTree &&) = default;
+
+  /// Makes a copy of the \p Name in detailed mode, returns current node
+  /// otherwise.
+  /// Note that returned pointers are invalidated with subsequent calls to
+  /// child/detail.
+  MemoryTree &detail(llvm::StringRef Name) {
+    return DetailAlloc ? createChild(Name.copy(*DetailAlloc)) : *this;
+  }
+
+  /// Increases size of current node by \p Increment.
+  void addUsage(size_t Increment) { Size += Increment; }
+
+  /// Returns edges to direct children of this node.
+  const llvm::DenseMap<llvm::StringRef, MemoryTree> &children() const;
+
+  /// Returns total number of bytes used by this sub-tree. Performs a traversal.
+  size_t total() const;
+
+  /// Returns total number of bytes used by this node only.
+  size_t self() const { return Size; }
+
+private:
+  /// Adds a child with an edge labeled as \p Name. Multiple calls to this
+  /// function returns the same node.
+  MemoryTree &createChild(llvm::StringRef Name);
+
+  /// Allocator to use for detailed edge names.
+  llvm::BumpPtrAllocator *DetailAlloc = nullptr;
+
+  /// Bytes owned by this component specifically.
+  size_t Size = 0;
+
+  /// Edges from current node to its children. Keys are the labels for edges.
+  llvm::DenseMap<llvm::StringRef, MemoryTree> Children;
+};
+
+/// Records total memory usage of each node under \p Out. Labels are edges on
+/// the path joined with ".", starting with \p RootName.
+void record(const MemoryTree &MT, std::string RootName,
+            const trace::Metric &Out);
+
+} // namespace clangd
+} // namespace clang
+
+#endif
diff --git a/clang-tools-extra/clangd/support/Trace.cpp b/clang-tools-extra/clangd/support/Trace.cpp
index 7ab09cd23e6a76..d69b1c2bbde593 100644
--- a/clang-tools-extra/clangd/support/Trace.cpp
+++ b/clang-tools-extra/clangd/support/Trace.cpp
@@ -53,9 +53,12 @@ class JSONTracer : public EventTracer {
 
   // We stash a Span object in the context. It will record the start/end,
   // and this also allows us to look up the parent Span's information.
-  Context beginSpan(llvm::StringRef Name, llvm::json::Object *Args) override {
-    return Context::current().derive(
-        SpanKey, std::make_unique<JSONSpan>(this, Name, Args));
+  Context beginSpan(
+      llvm::StringRef Name,
+      llvm::function_ref<void(llvm::json::Object *)> AttachDetails) override {
+    auto JS = std::make_unique<JSONSpan>(this, Name);
+    AttachDetails(&JS->Args);
+    return Context::current().derive(SpanKey, std::move(JS));
   }
 
   // Trace viewer requires each thread to properly stack events.
@@ -85,9 +88,9 @@ class JSONTracer : public EventTracer {
 private:
   class JSONSpan {
   public:
-    JSONSpan(JSONTracer *Tracer, llvm::StringRef Name, llvm::json::Object *Args)
+    JSONSpan(JSONTracer *Tracer, llvm::StringRef Name)
         : StartTime(Tracer->timestamp()), EndTime(0), Name(Name),
-          TID(llvm::get_threadid()), Tracer(Tracer), Args(Args) {
+          TID(llvm::get_threadid()), Tracer(Tracer) {
       // ~JSONSpan() may run in a different thread, so we need to capture now.
       Tracer->captureThreadMetadata();
 
@@ -125,7 +128,7 @@ class JSONTracer : public EventTracer {
       // Finally, record the event (ending at EndTime, not timestamp())!
       Tracer->jsonEvent("X",
                         llvm::json::Object{{"name", std::move(Name)},
-                                           {"args", std::move(*Args)},
+                                           {"args", std::move(Args)},
                                            {"dur", EndTime - StartTime}},
                         TID, StartTime);
     }
@@ -133,6 +136,8 @@ class JSONTracer : public EventTracer {
     // May be called by any thread.
     void markEnded() { EndTime = Tracer->timestamp(); }
 
+    llvm::json::Object Args;
+
   private:
     static int64_t nextID() {
       static std::atomic<int64_t> Next = {0};
@@ -144,7 +149,6 @@ class JSONTracer : public EventTracer {
     std::string Name;
     uint64_t TID;
     JSONTracer *Tracer;
-    llvm::json::Object *Args;
   };
   static Key<std::unique_ptr<JSONSpan>> SpanKey;
 
@@ -277,12 +281,13 @@ void log(const llvm::Twine &Message) {
   T->instant("Log", llvm::json::Object{{"Message", Message.str()}});
 }
 
-// Returned context owns Args.
-static Context makeSpanContext(llvm::Twine Name, llvm::json::Object *Args,
-                               const Metric &LatencyMetric) {
+bool enabled() { return T != nullptr; }
+
+// The JSON object is event args (owned by context), if the tracer wants them.
+static std::pair<Context, llvm::json::Object *>
+makeSpanContext(llvm::Twine Name, const Metric &LatencyMetric) {
   if (!T)
-    return Context::current().clone();
-  WithContextValue WithArgs{std::unique_ptr<llvm::json::Object>(Args)};
+    return std::make_pair(Context::current().clone(), nullptr);
   llvm::Optional<WithContextValue> WithLatency;
   using Clock = std::chrono::high_resolution_clock;
   WithLatency.emplace(llvm::make_scope_exit(
@@ -293,9 +298,15 @@ static Context makeSpanContext(llvm::Twine Name, llvm::json::Object *Args,
                 .count(),
             Name);
       }));
-  return T->beginSpan(Name.isSingleStringRef() ? Name.getSingleStringRef()
-                                               : llvm::StringRef(Name.str()),
-                      Args);
+  llvm::json::Object *Args = nullptr;
+  Context Ctx = T->beginSpan(
+      Name.isSingleStringRef() ? Name.getSingleStringRef()
+                               : llvm::StringRef(Name.str()),
+      [&](llvm::json::Object *A) {
+        assert(A && A->empty() && "Invalid AttachDetails() placeholder!");
+        Args = A;
+      });
+  return std::make_pair(std::move(Ctx), Args);
 }
 
 // Fallback metric that measures latencies for spans without an explicit latency
@@ -307,8 +318,9 @@ constexpr Metric SpanLatency("span_latency", Metric::Distribution, "span_name");
 // beginSpan() context is destroyed, when the tracing engine will consume them.
 Span::Span(llvm::Twine Name) : Span(Name, SpanLatency) {}
 Span::Span(llvm::Twine Name, const Metric &LatencyMetric)
-    : Args(T ? new llvm::json::Object() : nullptr),
-      RestoreCtx(makeSpanContext(Name, Args, LatencyMetric)) {}
+    : Span(makeSpanContext(Name, LatencyMetric)) {}
+Span::Span(std::pair<Context, llvm::json::Object *> Pair)
+    : Args(Pair.second), RestoreCtx(std::move(Pair.first)) {}
 
 Span::~Span() {
   if (T)
@@ -323,7 +335,9 @@ void Metric::record(double Value, llvm::StringRef Label) const {
   T->record(*this, Value, Label);
 }
 
-Context EventTracer::beginSpan(llvm::StringRef Name, llvm::json::Object *Args) {
+Context EventTracer::beginSpan(
+    llvm::StringRef Name,
+    llvm::function_ref<void(llvm::json::Object *)> AttachDetails) {
   return Context::current().clone();
 }
 } // namespace trace
diff --git a/clang-tools-extra/clangd/support/Trace.h b/clang-tools-extra/clangd/support/Trace.h
index 9dc397a84b7449..52ee2ae617da60 100644
--- a/clang-tools-extra/clangd/support/Trace.h
+++ b/clang-tools-extra/clangd/support/Trace.h
@@ -79,8 +79,13 @@ class EventTracer {
   /// Returns a derived context that will be destroyed when the event ends.
   /// Usually implementations will store an object in the returned context
   /// whose destructor records the end of the event.
-  /// The args are *Args, only complete when the event ends.
-  virtual Context beginSpan(llvm::StringRef Name, llvm::json::Object *Args);
+  /// The tracer may capture event details provided in SPAN_ATTACH() calls.
+  /// In this case it should call AttachDetails(), and pass in an empty Object
+  /// to hold them. This Object should be owned by the context, and the data
+  /// will be complete by the time the context is destroyed.
+  virtual Context
+  beginSpan(llvm::StringRef Name,
+            llvm::function_ref<void(llvm::json::Object *)> AttachDetails);
   // Called when a Span is destroyed (it may still be active on other threads).
   // beginSpan() and endSpan() will always form a proper stack on each thread.
   // The Context returned by beginSpan is active, but Args is not ready.
@@ -123,6 +128,9 @@ std::unique_ptr<EventTracer> createCSVMetricTracer(llvm::raw_ostream &OS);
 /// Records a single instant event, associated with the current thread.
 void log(const llvm::Twine &Name);
 
+/// Returns true if there is an active tracer.
+bool enabled();
+
 /// Records an event whose duration is the lifetime of the Span object.
 /// This lifetime is extended when the span's context is reused.
 ///
@@ -146,6 +154,8 @@ class Span {
   llvm::json::Object *const Args;
 
 private:
+  // Awkward constructor works around constant initialization.
+  Span(std::pair<Context, llvm::json::Object *>);
   WithContext RestoreCtx;
 };
 
diff --git a/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp b/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp
index adf39a915c1a15..4f089519530a2c 100644
--- a/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp
+++ b/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp
@@ -21,6 +21,7 @@ using ::testing::AllOf;
 using ::testing::Contains;
 using ::testing::ElementsAre;
 using ::testing::Not;
+using ::testing::Pair;
 using ::testing::UnorderedElementsAre;
 
 namespace clang {
@@ -916,5 +917,18 @@ TEST(BackgroundQueueTest, Progress) {
   EXPECT_EQ(S.LastIdle, 2000u);
 }
 
+TEST(BackgroundIndex, Profile) {
+  MockFS FS;
+  MockCompilationDatabase CDB;
+  BackgroundIndex Idx(FS, CDB, [](llvm::StringRef) { return nullptr; },
+                      /*Opts=*/{});
+
+  llvm::BumpPtrAllocator Alloc;
+  MemoryTree MT(&Alloc);
+  Idx.profile(MT);
+  ASSERT_THAT(MT.children(),
+              UnorderedElementsAre(Pair("symbols", _), Pair("index", _)));
+}
+
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/unittests/CMakeLists.txt b/clang-tools-extra/clangd/unittests/CMakeLists.txt
index a84fd0b71ca511..de8eaca6059fa7 100644
--- a/clang-tools-extra/clangd/unittests/CMakeLists.txt
+++ b/clang-tools-extra/clangd/unittests/CMakeLists.txt
@@ -99,6 +99,7 @@ add_unittest(ClangdUnitTests ClangdTests
   support/ContextTests.cpp
   support/FunctionTests.cpp
   support/MarkupTests.cpp
+  support/MemoryTreeTests.cpp
   support/ThreadingTests.cpp
   support/TestTracer.cpp
   support/TraceTests.cpp
diff --git a/clang-tools-extra/clangd/unittests/ClangdTests.cpp b/clang-tools-extra/clangd/unittests/ClangdTests.cpp
index 813b95aa3c824b..f2d6d6b8192b42 100644
--- a/clang-tools-extra/clangd/unittests/ClangdTests.cpp
+++ b/clang-tools-extra/clangd/unittests/ClangdTests.cpp
@@ -17,6 +17,7 @@
 #include "TestFS.h"
 #include "TestTU.h"
 #include "URI.h"
+#include "support/MemoryTree.h"
 #include "support/Path.h"
 #include "support/Threading.h"
 #include "clang/Config/config.h"
@@ -27,6 +28,7 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/Support/Allocator.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Regex.h"
@@ -48,6 +50,7 @@ namespace clangd {
 namespace {
 
 using ::testing::AllOf;
+using ::testing::Contains;
 using ::testing::ElementsAre;
 using ::testing::Field;
 using ::testing::Gt;
@@ -565,7 +568,9 @@ int hello;
 }
 
 MATCHER_P4(Stats, Name, UsesMemory, PreambleBuilds, ASTBuilds, "") {
-  return arg.first() == Name && (arg.second.UsedBytes != 0) == UsesMemory &&
+  return arg.first() == Name &&
+         (arg.second.UsedBytesAST + arg.second.UsedBytesPreamble != 0) ==
+             UsesMemory &&
          std::tie(arg.second.PreambleBuilds, ASTBuilds) ==
              std::tie(PreambleBuilds, ASTBuilds);
 }
@@ -1234,6 +1239,21 @@ TEST(ClangdServer, TidyOverrideTest) {
   EXPECT_FALSE(DiagConsumer.HadDiagsInLastCallback);
 }
 
+TEST(ClangdServer, MemoryUsageTest) {
+  MockFS FS;
+  MockCompilationDatabase CDB;
+  ClangdServer Server(CDB, FS, ClangdServer::optsForTest());
+
+  auto FooCpp = testPath("foo.cpp");
+  Server.addDocument(FooCpp, "");
+  ASSERT_TRUE(Server.blockUntilIdleForTest());
+
+  llvm::BumpPtrAllocator Alloc;
+  MemoryTree MT(&Alloc);
+  Server.profile(MT);
+  ASSERT_TRUE(MT.children().count("tuscheduler"));
+  EXPECT_TRUE(MT.child("tuscheduler").children().count(FooCpp));
+}
 } // namespace
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/unittests/FileIndexTests.cpp b/clang-tools-extra/clangd/unittests/FileIndexTests.cpp
index c5bfbe132d37f4..2b20b7e7fef0d2 100644
--- a/clang-tools-extra/clangd/unittests/FileIndexTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FileIndexTests.cpp
@@ -22,20 +22,25 @@
 #include "index/Relation.h"
 #include "index/Serialization.h"
 #include "index/Symbol.h"
+#include "index/SymbolID.h"
 #include "support/Threading.h"
 #include "clang/Frontend/CompilerInvocation.h"
 #include "clang/Frontend/Utils.h"
 #include "clang/Index/IndexSymbol.h"
 #include "clang/Lex/Preprocessor.h"
 #include "clang/Tooling/CompilationDatabase.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/Support/Allocator.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 #include <utility>
+#include <vector>
 
 using ::testing::_;
 using ::testing::AllOf;
 using ::testing::Contains;
 using ::testing::ElementsAre;
+using ::testing::Gt;
 using ::testing::IsEmpty;
 using ::testing::Pair;
 using ::testing::UnorderedElementsAre;
@@ -88,6 +93,13 @@ std::unique_ptr<RefSlab> refSlab(const SymbolID &ID, const char *Path) {
   return std::make_unique<RefSlab>(std::move(Slab).build());
 }
 
+std::unique_ptr<RelationSlab> relSlab(llvm::ArrayRef<const Relation> Rels) {
+  RelationSlab::Builder RelBuilder;
+  for (auto &Rel : Rels)
+    RelBuilder.insert(Rel);
+  return std::make_unique<RelationSlab>(std::move(RelBuilder).build());
+}
+
 TEST(FileSymbolsTest, UpdateAndGet) {
   FileSymbols FS;
   EXPECT_THAT(runFuzzyFind(*FS.buildIndex(IndexType::Light), ""), IsEmpty());
@@ -643,6 +655,50 @@ TEST(FileShardedIndexTest, Sharding) {
     EXPECT_TRUE(Shard->Cmd.hasValue());
   }
 }
+
+TEST(FileIndexTest, Profile) {
+  FileIndex FI;
+
+  auto FileName = testPath("foo.cpp");
+  auto AST = TestTU::withHeaderCode("int a;").build();
+  FI.updateMain(FileName, AST);
+  FI.updatePreamble(FileName, "v1", AST.getASTContext(),
+                    AST.getPreprocessorPtr(), AST.getCanonicalIncludes());
+
+  llvm::BumpPtrAllocator Alloc;
+  MemoryTree MT(&Alloc);
+  FI.profile(MT);
+  ASSERT_THAT(MT.children(),
+              UnorderedElementsAre(Pair("preamble", _), Pair("main_file", _)));
+
+  ASSERT_THAT(MT.child("preamble").children(),
+              UnorderedElementsAre(Pair("index", _), Pair("symbols", _)));
+  ASSERT_THAT(MT.child("main_file").children(),
+              UnorderedElementsAre(Pair("index", _), Pair("symbols", _)));
+
+  ASSERT_THAT(MT.child("preamble").child("index").total(), Gt(0U));
+  ASSERT_THAT(MT.child("main_file").child("index").total(), Gt(0U));
+}
+
+TEST(FileSymbolsTest, Profile) {
+  FileSymbols FS;
+  FS.update("f1", numSlab(1, 2), nullptr, nullptr, false);
+  FS.update("f2", nullptr, refSlab(SymbolID("1"), "f1"), nullptr, false);
+  FS.update("f3", nullptr, nullptr,
+            relSlab({{SymbolID("1"), RelationKind::BaseOf, SymbolID("2")}}),
+            false);
+  llvm::BumpPtrAllocator Alloc;
+  MemoryTree MT(&Alloc);
+  FS.profile(MT);
+  ASSERT_THAT(MT.children(), UnorderedElementsAre(Pair("f1", _), Pair("f2", _),
+                                                  Pair("f3", _)));
+  EXPECT_THAT(MT.child("f1").children(), ElementsAre(Pair("symbols", _)));
+  EXPECT_THAT(MT.child("f1").total(), Gt(0U));
+  EXPECT_THAT(MT.child("f2").children(), ElementsAre(Pair("references", _)));
+  EXPECT_THAT(MT.child("f2").total(), Gt(0U));
+  EXPECT_THAT(MT.child("f3").children(), ElementsAre(Pair("relations", _)));
+  EXPECT_THAT(MT.child("f3").total(), Gt(0U));
+}
 } // namespace
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp b/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp
index 65d9cffeedc73d..9b7b2e2dcd4796 100644
--- a/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp
+++ b/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp
@@ -57,6 +57,17 @@ MATCHER_P(DeclNamed, Name, "") {
   return false;
 }
 
+MATCHER_P(DeclKind, Kind, "") {
+  if (NamedDecl *ND = dyn_cast<NamedDecl>(arg))
+    if (ND->getDeclKindName() == Kind)
+      return true;
+  if (auto *Stream = result_listener->stream()) {
+    llvm::raw_os_ostream OS(*Stream);
+    arg->dump(OS);
+  }
+  return false;
+}
+
 // Matches if the Decl has template args equal to ArgName. If the decl is a
 // NamedDecl and ArgName is an empty string it also matches.
 MATCHER_P(WithTemplateArgs, ArgName, "") {
@@ -93,15 +104,22 @@ MATCHER(EqInc, "") {
          std::tie(Expected.HashLine, Expected.Written);
 }
 
-TEST(ParsedASTTest, TopLevelDecls) {
+// FIXME: figure out why it fails on clang-ppc64le-rhel buildbot.
+TEST(ParsedASTTest, DISABLED_TopLevelDecls) {
   TestTU TU;
   TU.HeaderCode = R"(
     int header1();
     int header2;
   )";
-  TU.Code = "int main();";
+  TU.Code = R"cpp(
+    int main();
+    template <typename> bool X = true;
+  )cpp";
   auto AST = TU.build();
-  EXPECT_THAT(AST.getLocalTopLevelDecls(), ElementsAre(DeclNamed("main")));
+  EXPECT_THAT(AST.getLocalTopLevelDecls(),
+              testing::UnorderedElementsAreArray(
+                  {AllOf(DeclNamed("main"), DeclKind("Function")),
+                   AllOf(DeclNamed("X"), DeclKind("VarTemplate"))}));
 }
 
 TEST(ParsedASTTest, DoesNotGetIncludedTopDecls) {
diff --git a/clang-tools-extra/clangd/unittests/support/MemoryTreeTests.cpp b/clang-tools-extra/clangd/unittests/support/MemoryTreeTests.cpp
new file mode 100644
index 00000000000000..7d3d29a9e1ddfc
--- /dev/null
+++ b/clang-tools-extra/clangd/unittests/support/MemoryTreeTests.cpp
@@ -0,0 +1,121 @@
+//===-- MemoryTreeTests.cpp -------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "support/MemoryTree.h"
+#include "support/TestTracer.h"
+#include "support/Trace.h"
+#include "llvm/Support/Allocator.h"
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
+#include <ostream>
+
+namespace clang {
+namespace clangd {
+namespace {
+using testing::Contains;
+using testing::ElementsAre;
+using testing::IsEmpty;
+using testing::UnorderedElementsAre;
+
+MATCHER_P2(WithNameAndSize, Name, Size, "") {
+  return arg.first == Name &&
+         arg.getSecond().total() == static_cast<size_t>(Size);
+}
+
+TEST(MemoryTree, Basics) {
+  MemoryTree MT;
+  EXPECT_EQ(MT.total(), 0U);
+  EXPECT_THAT(MT.children(), IsEmpty());
+
+  MT.addUsage(42);
+  EXPECT_EQ(MT.total(), 42U);
+  EXPECT_THAT(MT.children(), IsEmpty());
+
+  MT.child("leaf").addUsage(1);
+  EXPECT_EQ(MT.total(), 43U);
+  EXPECT_THAT(MT.children(), UnorderedElementsAre(WithNameAndSize("leaf", 1)));
+
+  // child should be idempotent.
+  MT.child("leaf").addUsage(1);
+  EXPECT_EQ(MT.total(), 44U);
+  EXPECT_THAT(MT.children(), UnorderedElementsAre(WithNameAndSize("leaf", 2)));
+}
+
+TEST(MemoryTree, DetailedNodesWithoutDetails) {
+  MemoryTree MT;
+  MT.detail("should_be_ignored").addUsage(2);
+  EXPECT_THAT(MT.children(), IsEmpty());
+  EXPECT_EQ(MT.total(), 2U);
+
+  // Make sure children from details are merged.
+  MT.detail("first_detail").child("leaf").addUsage(1);
+  MT.detail("second_detail").child("leaf").addUsage(1);
+  EXPECT_THAT(MT.children(), Contains(WithNameAndSize("leaf", 2)));
+}
+
+TEST(MemoryTree, DetailedNodesWithDetails) {
+  llvm::BumpPtrAllocator Alloc;
+  MemoryTree MT(&Alloc);
+
+  {
+    auto &Detail = MT.detail("first_detail");
+    Detail.child("leaf").addUsage(1);
+    EXPECT_THAT(MT.children(), Contains(WithNameAndSize("first_detail", 1)));
+    EXPECT_THAT(Detail.children(), Contains(WithNameAndSize("leaf", 1)));
+  }
+
+  {
+    auto &Detail = MT.detail("second_detail");
+    Detail.child("leaf").addUsage(1);
+    EXPECT_THAT(MT.children(), Contains(WithNameAndSize("second_detail", 1)));
+    EXPECT_THAT(Detail.children(), Contains(WithNameAndSize("leaf", 1)));
+  }
+}
+
+TEST(MemoryTree, Record) {
+  trace::TestTracer Tracer;
+  static constexpr llvm::StringLiteral MetricName = "memory_usage";
+  static constexpr trace::Metric OutMetric(MetricName, trace::Metric::Value,
+                                           "component_name");
+  auto AddNodes = [](MemoryTree Root) {
+    Root.child("leaf").addUsage(1);
+
+    {
+      auto &Detail = Root.detail("detail");
+      Detail.addUsage(1);
+      Detail.child("leaf").addUsage(1);
+      auto &Child = Detail.child("child");
+      Child.addUsage(1);
+      Child.child("leaf").addUsage(1);
+    }
+
+    {
+      auto &Child = Root.child("child");
+      Child.addUsage(1);
+      Child.child("leaf").addUsage(1);
+    }
+    return Root;
+  };
+
+  llvm::BumpPtrAllocator Alloc;
+  record(AddNodes(MemoryTree(&Alloc)), "root", OutMetric);
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root"), ElementsAre(7));
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root.leaf"), ElementsAre(1));
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root.detail"), ElementsAre(4));
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root.detail.leaf"),
+              ElementsAre(1));
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root.detail.child"),
+              ElementsAre(2));
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root.detail.child.leaf"),
+              ElementsAre(1));
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root.child"), ElementsAre(2));
+  EXPECT_THAT(Tracer.takeMetric(MetricName, "root.child.leaf"), ElementsAre(1));
+}
+} // namespace
+} // namespace clangd
+} // namespace clang
diff --git a/clang-tools-extra/clangd/unittests/support/TraceTests.cpp b/clang-tools-extra/clangd/unittests/support/TraceTests.cpp
index 116d9fcee02c77..bb515edd72535d 100644
--- a/clang-tools-extra/clangd/unittests/support/TraceTests.cpp
+++ b/clang-tools-extra/clangd/unittests/support/TraceTests.cpp
@@ -186,6 +186,11 @@ TEST_F(CSVMetricsTracerTest, Escaping) {
                                          StartsWith("d,dist,\"a\nb\",1"), ""));
 }
 
+TEST_F(CSVMetricsTracerTest, IgnoresArgs) {
+  trace::Span Tracer("Foo");
+  EXPECT_EQ(nullptr, Tracer.Args);
+}
+
 } // namespace
 } // namespace clangd
 } // namespace clang
diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp
index 3f314c59ade6ec..01a16575c239cf 100644
--- a/clang/lib/Parse/ParseDecl.cpp
+++ b/clang/lib/Parse/ParseDecl.cpp
@@ -2195,6 +2195,7 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes(
 
   // Inform the current actions module that we just parsed this declarator.
   Decl *ThisDecl = nullptr;
+  Decl *OuterDecl = nullptr;
   switch (TemplateInfo.Kind) {
   case ParsedTemplateInfo::NonTemplate:
     ThisDecl = Actions.ActOnDeclarator(getCurScope(), D);
@@ -2205,10 +2206,12 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes(
     ThisDecl = Actions.ActOnTemplateDeclarator(getCurScope(),
                                                *TemplateInfo.TemplateParams,
                                                D);
-    if (VarTemplateDecl *VT = dyn_cast_or_null<VarTemplateDecl>(ThisDecl))
+    if (VarTemplateDecl *VT = dyn_cast_or_null<VarTemplateDecl>(ThisDecl)) {
       // Re-direct this decl to refer to the templated decl so that we can
       // initialize it.
       ThisDecl = VT->getTemplatedDecl();
+      OuterDecl = VT;
+    }
     break;
   }
   case ParsedTemplateInfo::ExplicitInstantiation: {
@@ -2385,8 +2388,7 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes(
   }
 
   Actions.FinalizeDeclaration(ThisDecl);
-
-  return ThisDecl;
+  return OuterDecl ? OuterDecl : ThisDecl;
 }
 
 /// ParseSpecifierQualifierList
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 68a8777eae73a1..f0cb227ff58ee5 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -6375,6 +6375,21 @@ ExprResult Sema::BuildCallExpr(Scope *Scope, Expr *Fn, SourceLocation LParenLoc,
     checkDirectCallValidity(*this, Fn, FD, ArgExprs);
   }
 
+  if (Context.isDependenceAllowed() &&
+      (Fn->isTypeDependent() || Expr::hasAnyTypeDependentArguments(ArgExprs))) {
+    assert(!getLangOpts().CPlusPlus);
+    assert(Fn->containsErrors() ||
+           llvm::any_of(ArgExprs,
+                        [](clang::Expr *E) { return E->containsErrors(); }) &&
+               "should only occur in error-recovery path.");
+    QualType ReturnType =
+        llvm::isa_and_nonnull<FunctionDecl>(NDecl)
+            ? dyn_cast<FunctionDecl>(NDecl)->getCallResultType()
+            : Context.DependentTy;
+    return CallExpr::Create(Context, Fn, ArgExprs, ReturnType,
+                            Expr::getValueKindForType(ReturnType), RParenLoc,
+                            CurFPFeatureOverrides());
+  }
   return BuildResolvedCallExpr(Fn, NDecl, LParenLoc, ArgExprs, RParenLoc,
                                ExecConfig, IsExecConfig);
 }
@@ -6515,7 +6530,7 @@ ExprResult Sema::BuildResolvedCallExpr(Expr *Fn, NamedDecl *NDecl,
                          CurFPFeatureOverrides(), NumParams, UsesADL);
   }
 
-  if (!getLangOpts().CPlusPlus) {
+  if (!Context.isDependenceAllowed()) {
     // Forget about the nulled arguments since typo correction
     // do not handle them well.
     TheCall->shrinkNumArgs(Args.size());
@@ -8479,7 +8494,7 @@ ExprResult Sema::ActOnConditionalOp(SourceLocation QuestionLoc,
                                     SourceLocation ColonLoc,
                                     Expr *CondExpr, Expr *LHSExpr,
                                     Expr *RHSExpr) {
-  if (!getLangOpts().CPlusPlus) {
+  if (!Context.isDependenceAllowed()) {
     // C cannot handle TypoExpr nodes in the condition because it
     // doesn't handle dependent types properly, so make sure any TypoExprs have
     // been dealt with before checking the operands.
@@ -19052,7 +19067,7 @@ static ExprResult diagnoseUnknownAnyExpr(Sema &S, Expr *E) {
 /// Check for operands with placeholder types and complain if found.
 /// Returns ExprError() if there was an error and no recovery was possible.
 ExprResult Sema::CheckPlaceholderExpr(Expr *E) {
-  if (!getLangOpts().CPlusPlus) {
+  if (!Context.isDependenceAllowed()) {
     // C cannot handle TypoExpr nodes on either side of a binop because it
     // doesn't handle dependent types properly, so make sure any TypoExprs have
     // been dealt with before checking the operands.
diff --git a/clang/test/AST/ast-dump-recovery.c b/clang/test/AST/ast-dump-recovery.c
index d14aedebe4903b..f7b3c7bb4f2f4a 100644
--- a/clang/test/AST/ast-dump-recovery.c
+++ b/clang/test/AST/ast-dump-recovery.c
@@ -24,14 +24,10 @@ int postfix_inc = a++;
 int unary_address = &(a + 1);
 
 // CHECK:       VarDecl {{.*}} ternary 'int' cinit
-// CHECK-NEXT:  `-RecoveryExpr {{.*}}
+// CHECK-NEXT:  `-ConditionalOperator {{.*}}
 // CHECK-NEXT:    |-DeclRefExpr {{.*}} 'a'
-// CHECK-NEXT:    |-TypoExpr {{.*}}
+// CHECK-NEXT:    |-RecoveryExpr {{.*}}
 // CHECK-NEXT:    `-DeclRefExpr {{.*}} 'a'
-// FIXME: The TypoExpr should never be print, and should be downgraded to
-// RecoveryExpr -- typo correction is performed too early in C-only codepath,
-// which makes no correction when clang finishes the full expr (Sema::Sema::ActOnFinishFullExpr).
-// this will be fixed when we support dependent mechanism and delayed typo correction for C.
 int ternary = a ? undef : a;
 
 void test1() {
@@ -87,3 +83,18 @@ void test2() {
   // CHECK-NEXT:   `-DeclRefExpr {{.*}} 'some_func'
   (float)some_func();
 }
+
+void test3() {
+  // CHECK:     CallExpr {{.*}} '<dependent type>' contains-errors
+  // CHECK-NEXT: |-ParenExpr {{.*}} contains-errors lvalue
+  // CHECK-NEXT: | `-RecoveryExpr {{.*}} contains-errors
+  // CHECK-NEXT: |   `-DeclRefExpr {{.*}} '__builtin_classify_type'
+  // CHECK-NEXT: `-IntegerLiteral {{.*}} 'int' 1
+  (*__builtin_classify_type)(1);
+
+  extern void ext();
+  // CHECK:     CallExpr {{.*}} 'void' contains-errors
+  // CHECK-NEXT: |-DeclRefExpr {{.*}} 'ext'
+  // CHECK-NEXT: `-RecoveryExpr {{.*}} '<dependent type>'
+  ext(undef_var);
+}
diff --git a/clang/test/Sema/error-dependence.c b/clang/test/Sema/error-dependence.c
index 41733cdba3fe7d..608e9af4444e0c 100644
--- a/clang/test/Sema/error-dependence.c
+++ b/clang/test/Sema/error-dependence.c
@@ -10,6 +10,9 @@ void test1(int s) {
   // verify diagnostic "operand of type '<dependent type>' where arithmetic or
   // pointer type is required" is not emitted.
   (float)call(); // expected-error {{too few arguments to function call}}
+  // verify disgnostic "called object type '<dependent type>' is not a function
+  // or function pointer" is not emitted.
+  (*__builtin_classify_type)(1); // expected-error {{builtin functions must be directly called}}
 }
 
 void test2(int* ptr, float f) {
diff --git a/lldb/docs/lldb-platform-packets.txt b/lldb/docs/lldb-platform-packets.txt
index 8d3fed7ab3410e..e688fc92bb7ef4 100644
--- a/lldb/docs/lldb-platform-packets.txt
+++ b/lldb/docs/lldb-platform-packets.txt
@@ -411,6 +411,12 @@ incompatible with the flags that gdb specifies.
 //
 //  Response is F, followed by the number of bytes read (base 10), a
 //  semicolon, followed by the data in the binary-escaped-data encoding.
+//
+//  COMPATIBILITY
+//    The gdb-remote serial protocol documentation says that numbers
+//    in "vFile:" packets should be hexidecimal. Instead lldb uses
+//    decimal for the number of bytes and offset.
+//    lldb-server can process either format.
 
 
 //----------------------------------------------------------------------
@@ -430,7 +436,11 @@ incompatible with the flags that gdb specifies.
 //     3. binary-escaped-data to be written
 //
 //  Response is F, followed by the number of bytes written (base 10)
-
+//
+//  COMPATIBILITY
+//    The gdb-remote serial protocol documentation says that numbers
+//    in "vFile:" packets should be hexidecimal. Instead lldb uses
+//    decimal for the offset. lldb-server can process either format.
 
 
 
diff --git a/lldb/include/lldb/Utility/UnimplementedError.h b/lldb/include/lldb/Utility/UnimplementedError.h
new file mode 100644
index 00000000000000..c6fab0a9483c01
--- /dev/null
+++ b/lldb/include/lldb/Utility/UnimplementedError.h
@@ -0,0 +1,28 @@
+//===-- UnimplementedError.h ------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_UTILITY_UNIMPLEMENTEDERROR_H
+#define LLDB_UTILITY_UNIMPLEMENTEDERROR_H
+
+#include "llvm/Support/Errc.h"
+#include "llvm/Support/Error.h"
+
+namespace lldb_private {
+class UnimplementedError : public llvm::ErrorInfo<UnimplementedError> {
+public:
+  static char ID;
+
+  void log(llvm::raw_ostream &OS) const override { OS << "Not implemented"; }
+
+  std::error_code convertToErrorCode() const override {
+    return llvm::errc::not_supported;
+  };
+};
+} // namespace lldb_private
+
+#endif // LLDB_UTILITY_UNIMPLEMENTEDERROR_H
diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.cpp
index b78f0916b9b982..60548efc0f33f3 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.cpp
@@ -12,11 +12,11 @@
 
 #include "GDBRemoteCommunicationServer.h"
 
-#include <cstring>
-
 #include "ProcessGDBRemoteLog.h"
 #include "lldb/Utility/StreamString.h"
 #include "lldb/Utility/StringExtractorGDBRemote.h"
+#include "lldb/Utility/UnimplementedError.h"
+#include <cstring>
 
 using namespace lldb;
 using namespace lldb_private;
@@ -113,18 +113,17 @@ GDBRemoteCommunicationServer::SendErrorResponse(const Status &error) {
 
 GDBRemoteCommunication::PacketResult
 GDBRemoteCommunicationServer::SendErrorResponse(llvm::Error error) {
+  assert(error);
   std::unique_ptr<llvm::ErrorInfoBase> EIB;
-  std::unique_ptr<PacketUnimplementedError> PUE;
+  std::unique_ptr<UnimplementedError> UE;
   llvm::handleAllErrors(
       std::move(error),
-      [&](std::unique_ptr<PacketUnimplementedError> E) { PUE = std::move(E); },
+      [&](std::unique_ptr<UnimplementedError> E) { UE = std::move(E); },
       [&](std::unique_ptr<llvm::ErrorInfoBase> E) { EIB = std::move(E); });
 
   if (EIB)
     return SendErrorResponse(Status(llvm::Error(std::move(EIB))));
-  if (PUE)
-    return SendUnimplementedResponse(PUE->message().c_str());
-  return SendErrorResponse(Status("Unknown Error"));
+  return SendUnimplementedResponse("");
 }
 
 GDBRemoteCommunication::PacketResult
@@ -152,5 +151,3 @@ GDBRemoteCommunicationServer::SendOKResponse() {
 bool GDBRemoteCommunicationServer::HandshakeWithClient() {
   return GetAck() == PacketResult::Success;
 }
-
-char PacketUnimplementedError::ID;
diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.h b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.h
index a7c2ea47e3bad0..63567bb9b5dee7 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.h
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.h
@@ -79,18 +79,6 @@ class GDBRemoteCommunicationServer : public GDBRemoteCommunication {
   operator=(const GDBRemoteCommunicationServer &) = delete;
 };
 
-class PacketUnimplementedError
-    : public llvm::ErrorInfo<PacketUnimplementedError, llvm::StringError> {
-public:
-  static char ID;
-  using llvm::ErrorInfo<PacketUnimplementedError,
-                        llvm::StringError>::ErrorInfo; // inherit constructors
-  PacketUnimplementedError(const llvm::Twine &S)
-      : ErrorInfo(S, llvm::errc::not_supported) {}
-
-  PacketUnimplementedError() : ErrorInfo(llvm::errc::not_supported) {}
-};
-
 } // namespace process_gdb_remote
 } // namespace lldb_private
 
diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
index ae2f4bd041c9b2..6f4d18364b266b 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -10,13 +10,12 @@
 
 #include "lldb/Host/Config.h"
 
-#include "GDBRemoteCommunicationServerLLGS.h"
-#include "lldb/Utility/GDBRemote.h"
 
 #include <chrono>
 #include <cstring>
 #include <thread>
 
+#include "GDBRemoteCommunicationServerLLGS.h"
 #include "lldb/Host/ConnectionFileDescriptor.h"
 #include "lldb/Host/Debug.h"
 #include "lldb/Host/File.h"
@@ -32,11 +31,13 @@
 #include "lldb/Utility/Args.h"
 #include "lldb/Utility/DataBuffer.h"
 #include "lldb/Utility/Endian.h"
+#include "lldb/Utility/GDBRemote.h"
 #include "lldb/Utility/LLDBAssert.h"
 #include "lldb/Utility/Log.h"
 #include "lldb/Utility/RegisterValue.h"
 #include "lldb/Utility/State.h"
 #include "lldb/Utility/StreamString.h"
+#include "lldb/Utility/UnimplementedError.h"
 #include "lldb/Utility/UriParser.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Support/JSON.h"
@@ -2876,8 +2877,7 @@ GDBRemoteCommunicationServerLLGS::ReadXferObject(llvm::StringRef object,
   if (object == "features" && annex == "target.xml")
     return BuildTargetXml();
 
-  return llvm::make_error<PacketUnimplementedError>(
-      "Xfer object not supported");
+  return llvm::make_error<UnimplementedError>();
 }
 
 GDBRemoteCommunication::PacketResult
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
index 9f4556f791aedf..3f7301871f957c 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -632,8 +632,7 @@ DWARFDebugInfo &SymbolFileDWARF::DebugInfo() {
   return *m_info;
 }
 
-DWARFUnit *
-SymbolFileDWARF::GetDWARFCompileUnit(lldb_private::CompileUnit *comp_unit) {
+DWARFCompileUnit *SymbolFileDWARF::GetDWARFCompileUnit(CompileUnit *comp_unit) {
   if (!comp_unit)
     return nullptr;
 
@@ -641,7 +640,9 @@ SymbolFileDWARF::GetDWARFCompileUnit(lldb_private::CompileUnit *comp_unit) {
   DWARFUnit *dwarf_cu = DebugInfo().GetUnitAtIndex(comp_unit->GetID());
   if (dwarf_cu && dwarf_cu->GetUserData() == nullptr)
     dwarf_cu->SetUserData(comp_unit);
-  return dwarf_cu;
+
+  // It must be DWARFCompileUnit when it created a CompileUnit.
+  return llvm::cast_or_null<DWARFCompileUnit>(dwarf_cu);
 }
 
 DWARFDebugRanges *SymbolFileDWARF::GetDebugRanges() {
@@ -1599,8 +1600,7 @@ static uint64_t GetDWOId(DWARFCompileUnit &dwarf_cu,
 llvm::Optional<uint64_t> SymbolFileDWARF::GetDWOId() {
   if (GetNumCompileUnits() == 1) {
     if (auto comp_unit = GetCompileUnitAtIndex(0))
-      if (DWARFCompileUnit *cu = llvm::dyn_cast_or_null<DWARFCompileUnit>(
-              GetDWARFCompileUnit(comp_unit.get())))
+      if (DWARFCompileUnit *cu = GetDWARFCompileUnit(comp_unit.get()))
         if (DWARFDebugInfoEntry *cu_die = cu->DIE().GetDIE())
           if (uint64_t dwo_id = ::GetDWOId(*cu, *cu_die))
             return dwo_id;
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
index 76ceb279c718e2..019f76c67c637c 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
@@ -346,7 +346,7 @@ class SymbolFileDWARF : public lldb_private::SymbolFile,
 
   lldb::CompUnitSP ParseCompileUnit(DWARFCompileUnit &dwarf_cu);
 
-  virtual DWARFUnit *
+  virtual DWARFCompileUnit *
   GetDWARFCompileUnit(lldb_private::CompileUnit *comp_unit);
 
   DWARFUnit *GetNextUnparsedDWARFCompileUnit(DWARFUnit *prev_cu);
diff --git a/lldb/source/Utility/CMakeLists.txt b/lldb/source/Utility/CMakeLists.txt
index 1e3d859e2a6cbe..875738178541fd 100644
--- a/lldb/source/Utility/CMakeLists.txt
+++ b/lldb/source/Utility/CMakeLists.txt
@@ -65,6 +65,7 @@ add_lldb_library(lldbUtility
   StructuredData.cpp
   TildeExpressionResolver.cpp
   Timer.cpp
+  UnimplementedError.cpp
   UUID.cpp
   UriParser.cpp
   UserID.cpp
diff --git a/lldb/source/Utility/UnimplementedError.cpp b/lldb/source/Utility/UnimplementedError.cpp
new file mode 100644
index 00000000000000..034ad5b17b6402
--- /dev/null
+++ b/lldb/source/Utility/UnimplementedError.cpp
@@ -0,0 +1,11 @@
+//===-- UnimplementedError.cpp --------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "lldb/Utility/UnimplementedError.h"
+
+char lldb_private::UnimplementedError::ID;
diff --git a/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationServerTest.cpp b/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationServerTest.cpp
index 4c4916e3668f87..6ab37599ae36bb 100644
--- a/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationServerTest.cpp
+++ b/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationServerTest.cpp
@@ -9,9 +9,9 @@
 #include "gtest/gtest.h"
 
 #include "GDBRemoteTestUtils.h"
-
 #include "Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.h"
 #include "lldb/Utility/Connection.h"
+#include "lldb/Utility/UnimplementedError.h"
 
 namespace lldb_private {
 namespace process_gdb_remote {
@@ -39,8 +39,7 @@ TEST(GDBRemoteCommunicationServerTest, SendErrorResponse_Status) {
 TEST(GDBRemoteCommunicationServerTest, SendErrorResponse_UnimplementedError) {
   MockServerWithMockConnection server;
 
-  auto error =
-      llvm::make_error<PacketUnimplementedError>("Test unimplemented error");
+  auto error = llvm::make_error<UnimplementedError>();
   server.SendErrorResponse(std::move(error));
 
   EXPECT_THAT(server.GetPackets(), testing::ElementsAre("$#00"));
@@ -61,8 +60,8 @@ TEST(GDBRemoteCommunicationServerTest, SendErrorResponse_StringError) {
 TEST(GDBRemoteCommunicationServerTest, SendErrorResponse_ErrorList) {
   MockServerWithMockConnection server;
 
-  auto error = llvm::joinErrors(llvm::make_error<PacketUnimplementedError>(),
-                                llvm::make_error<PacketUnimplementedError>());
+  auto error = llvm::joinErrors(llvm::make_error<UnimplementedError>(),
+                                llvm::make_error<UnimplementedError>());
 
   server.SendErrorResponse(std::move(error));
   // Make sure only one packet is sent even when there are multiple errors.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index b8a7a3437915a2..107814aab102f4 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -427,7 +427,7 @@ class TargetLoweringBase {
   virtual TargetLoweringBase::LegalizeTypeAction
   getPreferredVectorAction(MVT VT) const {
     // The default action for one element vectors is to scalarize
-    if (VT.getVectorElementCount() == 1)
+    if (VT.getVectorElementCount().isScalar())
       return TypeScalarizeVector;
     // The default action for an odd-width vector is to widen.
     if (!VT.isPow2VectorType())
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h
index d409196af8d9d5..958711f1529cca 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -214,9 +214,7 @@ namespace llvm {
     }
 
     /// Return true if the bit size is a multiple of 8.
-    bool isByteSized() const {
-      return getSizeInBits().isByteSized();
-    }
+    bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); }
 
     /// Return true if the size is a power-of-two number of bytes.
     bool isRound() const {
diff --git a/llvm/include/llvm/IR/Intrinsics.h b/llvm/include/llvm/IR/Intrinsics.h
index f68c834e4cf6d1..7926dc5aa4a491 100644
--- a/llvm/include/llvm/IR/Intrinsics.h
+++ b/llvm/include/llvm/IR/Intrinsics.h
@@ -188,8 +188,7 @@ namespace Intrinsic {
     }
 
     static IITDescriptor getVector(unsigned Width, bool IsScalable) {
-      IITDescriptor Result;
-      Result.Kind = Vector;
+      IITDescriptor Result = {Vector, {0}};
       Result.Vector_Width = ElementCount::get(Width, IsScalable);
       return Result;
     }
diff --git a/llvm/include/llvm/Support/JSON.h b/llvm/include/llvm/Support/JSON.h
index 455673e42e9700..9a8f915eeef79c 100644
--- a/llvm/include/llvm/Support/JSON.h
+++ b/llvm/include/llvm/Support/JSON.h
@@ -741,10 +741,9 @@ template <typename T> Value toJSON(const llvm::Optional<T> &Opt) {
 /// \code
 ///   bool fromJSON(const Value &E, MyStruct &R, Path P) {
 ///     ObjectMapper O(E, P);
-///     if (!O || !O.map("mandatory_field", R.MandatoryField))
-///       return false; // error details are already reported
-///     O.map("optional_field", R.OptionalField);
-///     return true;
+///     // When returning false, error details were already reported.
+///     return O && O.map("mandatory_field", R.MandatoryField) &&
+///         O.mapOptional("optional_field", R.OptionalField);
 ///   }
 /// \endcode
 class ObjectMapper {
@@ -780,6 +779,16 @@ class ObjectMapper {
     return true;
   }
 
+  /// Maps a property to a field, if it exists.
+  /// If the property exists and is invalid, reports an error.
+  /// If the property does not exist, Out is unchanged.
+  template <typename T> bool mapOptional(StringLiteral Prop, T &Out) {
+    assert(*this && "Must check this is an object before calling map()");
+    if (const Value *E = O->get(Prop))
+      return fromJSON(*E, Out, P.field(Prop));
+    return true;
+  }
+
 private:
   const Object *O;
   Path P;
diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h
index 4361d68bcb8da3..33b0fe6750c626 100644
--- a/llvm/include/llvm/Support/MachineValueType.h
+++ b/llvm/include/llvm/Support/MachineValueType.h
@@ -980,9 +980,7 @@ namespace llvm {
 
     /// Returns true if the number of bits for the type is a multiple of an
     /// 8-bit byte.
-    bool isByteSized() const {
-      return getSizeInBits().isByteSized();
-    }
+    bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); }
 
     /// Return true if we know at compile time this has more bits than VT.
     bool knownBitsGT(MVT VT) const {
diff --git a/llvm/include/llvm/Support/TypeSize.h b/llvm/include/llvm/Support/TypeSize.h
index 47aa41b851bffb..47fb90d21c0bae 100644
--- a/llvm/include/llvm/Support/TypeSize.h
+++ b/llvm/include/llvm/Support/TypeSize.h
@@ -25,148 +25,58 @@ namespace llvm {
 
 template <typename T> struct DenseMapInfo;
 
-class ElementCount {
-private:
-  unsigned Min;  // Minimum number of vector elements.
-  bool Scalable; // If true, NumElements is a multiple of 'Min' determined
-                 // at runtime rather than compile time.
-
-  /// Prevent code from using initializer-list contructors like
-  /// ElementCount EC = {<unsigned>, <bool>}. The static `get*`
-  /// methods below are preferred, as users should always make a
-  /// conscious choice on the type of `ElementCount` they are
-  /// requesting.
-  ElementCount(unsigned Min, bool Scalable) : Min(Min), Scalable(Scalable) {}
+// TODO: This class will be redesigned in a later patch that introduces full
+// polynomial behaviour, i.e. the ability to have composites made up of both
+// fixed and scalable sizes.
+template <typename T> class PolySize {
+protected:
+  T MinVal;        // The minimum value that it could be.
+  bool IsScalable; // If true, the total value is determined by multiplying
+                   // 'MinVal' by a runtime determinded quantity, 'vscale'.
+
+  constexpr PolySize(T MinVal, bool IsScalable)
+      : MinVal(MinVal), IsScalable(IsScalable) {}
 
 public:
-  ElementCount() = default;
 
-  ElementCount operator*(unsigned RHS) {
-    return { Min * RHS, Scalable };
+  static constexpr PolySize getFixed(T MinVal) { return {MinVal, false}; }
+  static constexpr PolySize getScalable(T MinVal) { return {MinVal, true}; }
+  static constexpr PolySize get(T MinVal, bool IsScalable) {
+    return {MinVal, IsScalable};
   }
 
-  friend ElementCount operator-(const ElementCount &LHS,
-                                const ElementCount &RHS) {
-    assert(LHS.Scalable == RHS.Scalable &&
-           "Arithmetic using mixed scalable and fixed types");
-    return {LHS.Min - RHS.Min, LHS.Scalable};
-  }
-
-  bool operator==(const ElementCount& RHS) const {
-    return Min == RHS.Min && Scalable == RHS.Scalable;
-  }
-  bool operator!=(const ElementCount& RHS) const {
-    return !(*this == RHS);
-  }
-  bool operator==(unsigned RHS) const { return Min == RHS && !Scalable; }
-  bool operator!=(unsigned RHS) const { return !(*this == RHS); }
-
-  ElementCount &operator*=(unsigned RHS) {
-    Min *= RHS;
-    return *this;
-  }
-
-  /// We do not provide the '/' operator here because division for polynomial
-  /// types does not work in the same way as for normal integer types. We can
-  /// only divide the minimum value (or coefficient) by RHS, which is not the
-  /// same as
-  ///   (Min * Vscale) / RHS
-  /// The caller is recommended to use this function in combination with
-  /// isKnownMultipleOf(RHS), which lets the caller know if it's possible to
-  /// perform a lossless divide by RHS.
-  ElementCount divideCoefficientBy(unsigned RHS) const {
-    return ElementCount(Min / RHS, Scalable);
-  }
+  static constexpr PolySize getNull() { return {0, false}; }
 
-  ElementCount NextPowerOf2() const {
-    return {(unsigned)llvm::NextPowerOf2(Min), Scalable};
-  }
-
-  /// This function tells the caller whether the element count is known at
-  /// compile time to be a multiple of the scalar value RHS.
-  bool isKnownMultipleOf(unsigned RHS) const {
-    return Min % RHS == 0;
-  }
-
-  static ElementCount getFixed(unsigned Min) { return {Min, false}; }
-  static ElementCount getScalable(unsigned Min) { return {Min, true}; }
-  static ElementCount get(unsigned Min, bool Scalable) {
-    return {Min, Scalable};
-  }
-
-  /// Printing function.
-  void print(raw_ostream &OS) const {
-    if (Scalable)
-      OS << "vscale x ";
-    OS << Min;
-  }
   /// Counting predicates.
   ///
-  /// Notice that Min = 1 and Scalable = true is considered more than
-  /// one element.
-  ///
   ///@{ No elements..
-  bool isZero() const { return Min == 0; }
+  bool isZero() const { return MinVal == 0; }
   /// At least one element.
-  bool isNonZero() const { return Min != 0; }
+  bool isNonZero() const { return !isZero(); }
   /// A return value of true indicates we know at compile time that the number
   /// of elements (vscale * Min) is definitely even. However, returning false
   /// does not guarantee that the total number of elements is odd.
-  bool isKnownEven() const { return (Min & 0x1) == 0; }
-  /// Exactly one element.
-  bool isScalar() const { return !Scalable && Min == 1; }
-  /// One or more elements.
-  bool isVector() const { return (Scalable && Min != 0) || Min > 1; }
+  bool isKnownEven() const { return (MinVal & 0x1) == 0; }
   ///@}
 
-  unsigned getKnownMinValue() const { return Min; }
+  T getKnownMinValue() const { return MinVal; }
 
   // Return the minimum value with the assumption that the count is exact.
   // Use in places where a scalable count doesn't make sense (e.g. non-vector
   // types, or vectors in backends which don't support scalable vectors).
-  unsigned getFixedValue() const {
-    assert(!Scalable &&
+  T getFixedValue() const {
+    assert(!IsScalable &&
            "Request for a fixed element count on a scalable object");
-    return Min;
-  }
-
-  bool isScalable() const { return Scalable; }
-};
-
-/// Stream operator function for `ElementCount`.
-inline raw_ostream &operator<<(raw_ostream &OS, const ElementCount &EC) {
-  EC.print(OS);
-  return OS;
-}
-
-// This class is used to represent the size of types. If the type is of fixed
-// size, it will represent the exact size. If the type is a scalable vector,
-// it will represent the known minimum size.
-class TypeSize {
-  uint64_t MinSize;   // The known minimum size.
-  bool IsScalable;    // If true, then the runtime size is an integer multiple
-                      // of MinSize.
-
-public:
-  constexpr TypeSize(uint64_t MinSize, bool Scalable)
-    : MinSize(MinSize), IsScalable(Scalable) {}
-
-  static constexpr TypeSize Fixed(uint64_t Size) {
-    return TypeSize(Size, /*Scalable=*/false);
+    return MinVal;
   }
 
-  static constexpr TypeSize Scalable(uint64_t MinSize) {
-    return TypeSize(MinSize, /*Scalable=*/true);
-  }
+  bool isScalable() const { return IsScalable; }
 
-  // Scalable vector types with the same minimum size as a fixed size type are
-  // not guaranteed to be the same size at runtime, so they are never
-  // considered to be equal.
-  bool operator==(const TypeSize &RHS) const {
-    return MinSize == RHS.MinSize && IsScalable == RHS.IsScalable;
+  bool operator==(const PolySize &RHS) const {
+    return MinVal == RHS.MinVal && IsScalable == RHS.IsScalable;
   }
 
-  bool operator!=(const TypeSize &RHS) const { return !(*this == RHS); }
+  bool operator!=(const PolySize &RHS) const { return !(*this == RHS); }
 
   // For some cases, size ordering between scalable and fixed size types cannot
   // be determined at compile time, so such comparisons aren't allowed.
@@ -178,43 +88,129 @@ class TypeSize {
   // All the functions below make use of the fact vscale is always >= 1, which
   // means that <vscale x 4 x i32> is guaranteed to be >= <4 x i32>, etc.
 
-  static bool isKnownLT(const TypeSize &LHS, const TypeSize &RHS) {
+  static bool isKnownLT(const PolySize &LHS, const PolySize &RHS) {
     if (!LHS.IsScalable || RHS.IsScalable)
-      return LHS.MinSize < RHS.MinSize;
+      return LHS.MinVal < RHS.MinVal;
 
     // LHS.IsScalable = true, RHS.IsScalable = false
     return false;
   }
 
-  static bool isKnownGT(const TypeSize &LHS, const TypeSize &RHS) {
+  static bool isKnownGT(const PolySize &LHS, const PolySize &RHS) {
     if (LHS.IsScalable || !RHS.IsScalable)
-      return LHS.MinSize > RHS.MinSize;
+      return LHS.MinVal > RHS.MinVal;
 
     // LHS.IsScalable = false, RHS.IsScalable = true
     return false;
   }
 
-  static bool isKnownLE(const TypeSize &LHS, const TypeSize &RHS) {
+  static bool isKnownLE(const PolySize &LHS, const PolySize &RHS) {
     if (!LHS.IsScalable || RHS.IsScalable)
-      return LHS.MinSize <= RHS.MinSize;
+      return LHS.MinVal <= RHS.MinVal;
 
     // LHS.IsScalable = true, RHS.IsScalable = false
     return false;
   }
 
-  static bool isKnownGE(const TypeSize &LHS, const TypeSize &RHS) {
+  static bool isKnownGE(const PolySize &LHS, const PolySize &RHS) {
     if (LHS.IsScalable || !RHS.IsScalable)
-      return LHS.MinSize >= RHS.MinSize;
+      return LHS.MinVal >= RHS.MinVal;
 
     // LHS.IsScalable = false, RHS.IsScalable = true
     return false;
   }
 
+  PolySize operator*(T RHS) { return {MinVal * RHS, IsScalable}; }
+
+  PolySize &operator*=(T RHS) {
+    MinVal *= RHS;
+    return *this;
+  }
+
+  friend PolySize operator-(const PolySize &LHS, const PolySize &RHS) {
+    assert(LHS.IsScalable == RHS.IsScalable &&
+           "Arithmetic using mixed scalable and fixed types");
+    return {LHS.MinVal - RHS.MinVal, LHS.IsScalable};
+  }
+
+  /// This function tells the caller whether the element count is known at
+  /// compile time to be a multiple of the scalar value RHS.
+  bool isKnownMultipleOf(T RHS) const { return MinVal % RHS == 0; }
+
+  /// We do not provide the '/' operator here because division for polynomial
+  /// types does not work in the same way as for normal integer types. We can
+  /// only divide the minimum value (or coefficient) by RHS, which is not the
+  /// same as
+  ///   (Min * Vscale) / RHS
+  /// The caller is recommended to use this function in combination with
+  /// isKnownMultipleOf(RHS), which lets the caller know if it's possible to
+  /// perform a lossless divide by RHS.
+  PolySize divideCoefficientBy(T RHS) const {
+    return PolySize(MinVal / RHS, IsScalable);
+  }
+
+  PolySize coefficientNextPowerOf2() const {
+    return PolySize(static_cast<T>(llvm::NextPowerOf2(MinVal)), IsScalable);
+  }
+
+  /// Printing function.
+  void print(raw_ostream &OS) const {
+    if (IsScalable)
+      OS << "vscale x ";
+    OS << MinVal;
+  }
+};
+
+/// Stream operator function for `PolySize`.
+template <typename T>
+inline raw_ostream &operator<<(raw_ostream &OS, const PolySize<T> &PS) {
+  PS.print(OS);
+  return OS;
+}
+
+class ElementCount : public PolySize<unsigned> {
+public:
+
+  constexpr ElementCount(PolySize<unsigned> V) : PolySize(V) {}
+
+  /// Counting predicates.
+  ///
+  /// Notice that MinVal = 1 and IsScalable = true is considered more than
+  /// one element.
+  ///
+  ///@{ No elements..
+  /// Exactly one element.
+  bool isScalar() const { return !IsScalable && MinVal == 1; }
+  /// One or more elements.
+  bool isVector() const { return (IsScalable && MinVal != 0) || MinVal > 1; }
+  ///@}
+};
+
+// This class is used to represent the size of types. If the type is of fixed
+// size, it will represent the exact size. If the type is a scalable vector,
+// it will represent the known minimum size.
+class TypeSize : public PolySize<uint64_t> {
+public:
+  constexpr TypeSize(PolySize<uint64_t> V) : PolySize(V) {}
+
+  constexpr TypeSize(uint64_t MinVal, bool IsScalable)
+      : PolySize(MinVal, IsScalable) {}
+
+  static constexpr TypeSize Fixed(uint64_t MinVal) {
+    return TypeSize(MinVal, false);
+  }
+  static constexpr TypeSize Scalable(uint64_t MinVal) {
+    return TypeSize(MinVal, true);
+  }
+
+  uint64_t getFixedSize() const { return getFixedValue(); }
+  uint64_t getKnownMinSize() const { return getKnownMinValue(); }
+
   friend bool operator<(const TypeSize &LHS, const TypeSize &RHS) {
     assert(LHS.IsScalable == RHS.IsScalable &&
            "Ordering comparison of scalable and fixed types");
 
-    return LHS.MinSize < RHS.MinSize;
+    return LHS.MinVal < RHS.MinVal;
   }
 
   friend bool operator>(const TypeSize &LHS, const TypeSize &RHS) {
@@ -229,83 +225,26 @@ class TypeSize {
     return !(LHS < RHS);
   }
 
-  // Convenience operators to obtain relative sizes independently of
-  // the scalable flag.
-  TypeSize operator*(unsigned RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
-
-  friend TypeSize operator*(const unsigned LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
-  }
-
-  /// We do not provide the '/' operator here because division for polynomial
-  /// types does not work in the same way as for normal integer types. We can
-  /// only divide the minimum value (or coefficient) by RHS, which is not the
-  /// same as
-  ///   (MinSize * Vscale) / RHS
-  /// The caller is recommended to use this function in combination with
-  /// isKnownMultipleOf(RHS), which lets the caller know if it's possible to
-  /// perform a lossless divide by RHS.
-  TypeSize divideCoefficientBy(uint64_t RHS) const {
-    return {MinSize / RHS, IsScalable};
-  }
-
   TypeSize &operator-=(TypeSize RHS) {
     assert(IsScalable == RHS.IsScalable &&
            "Subtraction using mixed scalable and fixed types");
-    MinSize -= RHS.MinSize;
+    MinVal -= RHS.MinVal;
     return *this;
   }
 
   TypeSize &operator+=(TypeSize RHS) {
     assert(IsScalable == RHS.IsScalable &&
            "Addition using mixed scalable and fixed types");
-    MinSize += RHS.MinSize;
+    MinVal += RHS.MinVal;
     return *this;
   }
 
   friend TypeSize operator-(const TypeSize &LHS, const TypeSize &RHS) {
     assert(LHS.IsScalable == RHS.IsScalable &&
            "Arithmetic using mixed scalable and fixed types");
-    return {LHS.MinSize - RHS.MinSize, LHS.IsScalable};
-  }
-
-  // Return the minimum size with the assumption that the size is exact.
-  // Use in places where a scalable size doesn't make sense (e.g. non-vector
-  // types, or vectors in backends which don't support scalable vectors).
-  uint64_t getFixedSize() const {
-    assert(!IsScalable && "Request for a fixed size on a scalable object");
-    return MinSize;
-  }
-
-  // Return the known minimum size. Use in places where the scalable property
-  // doesn't matter (e.g. determining alignment) or in conjunction with the
-  // isScalable method below.
-  uint64_t getKnownMinSize() const {
-    return MinSize;
-  }
-
-  // Return whether or not the size is scalable.
-  bool isScalable() const {
-    return IsScalable;
+    return {LHS.MinVal - RHS.MinVal, LHS.IsScalable};
   }
 
-  // Returns true if the number of bits is a multiple of an 8-bit byte.
-  bool isByteSized() const {
-    return (MinSize & 7) == 0;
-  }
-
-  // Returns true if the type size is non-zero.
-  bool isNonZero() const { return MinSize != 0; }
-
-  // Returns true if the type size is zero.
-  bool isZero() const { return MinSize == 0; }
-
-  /// This function tells the caller whether the type size is known at
-  /// compile time to be a multiple of the scalar value RHS.
-  bool isKnownMultipleOf(uint64_t RHS) const { return MinSize % RHS == 0; }
-
   // Casts to a uint64_t if this is a fixed-width size.
   //
   // This interface is deprecated and will be removed in a future version
@@ -317,53 +256,51 @@ class TypeSize {
   // To determine how to upgrade the code:
   //
   //   if (<algorithm works for both scalable and fixed-width vectors>)
-  //     use getKnownMinSize()
+  //     use getKnownMinValue()
   //   else if (<algorithm works only for fixed-width vectors>) {
   //     if <algorithm can be adapted for both scalable and fixed-width vectors>
-  //       update the algorithm and use getKnownMinSize()
+  //       update the algorithm and use getKnownMinValue()
   //     else
-  //       bail out early for scalable vectors and use getFixedSize()
+  //       bail out early for scalable vectors and use getFixedValue()
   //   }
   operator uint64_t() const {
 #ifdef STRICT_FIXED_SIZE_VECTORS
-    return getFixedSize();
+    return getFixedValue();
 #else
     if (isScalable())
       WithColor::warning() << "Compiler has made implicit assumption that "
                               "TypeSize is not scalable. This may or may not "
                               "lead to broken code.\n";
-    return getKnownMinSize();
+    return getKnownMinValue();
 #endif
   }
 
+  // Convenience operators to obtain relative sizes independently of
+  // the scalable flag.
+  TypeSize operator*(unsigned RHS) const { return {MinVal * RHS, IsScalable}; }
+
+  friend TypeSize operator*(const unsigned LHS, const TypeSize &RHS) {
+    return {LHS * RHS.MinVal, RHS.IsScalable};
+  }
+
   // Additional convenience operators needed to avoid ambiguous parses.
   // TODO: Make uint64_t the default operator?
-  TypeSize operator*(uint64_t RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
+  TypeSize operator*(uint64_t RHS) const { return {MinVal * RHS, IsScalable}; }
 
-  TypeSize operator*(int RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
+  TypeSize operator*(int RHS) const { return {MinVal * RHS, IsScalable}; }
 
-  TypeSize operator*(int64_t RHS) const {
-    return { MinSize * RHS, IsScalable };
-  }
+  TypeSize operator*(int64_t RHS) const { return {MinVal * RHS, IsScalable}; }
 
   friend TypeSize operator*(const uint64_t LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
+    return {LHS * RHS.MinVal, RHS.IsScalable};
   }
 
   friend TypeSize operator*(const int LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
+    return {LHS * RHS.MinVal, RHS.IsScalable};
   }
 
   friend TypeSize operator*(const int64_t LHS, const TypeSize &RHS) {
-    return { LHS * RHS.MinSize, RHS.IsScalable };
-  }
-
-  TypeSize NextPowerOf2() const {
-    return TypeSize(llvm::NextPowerOf2(MinSize), IsScalable);
+    return {LHS * RHS.MinVal, RHS.IsScalable};
   }
 };
 
@@ -374,7 +311,7 @@ class TypeSize {
 /// Similar to the alignTo functions in MathExtras.h
 inline TypeSize alignTo(TypeSize Size, uint64_t Align) {
   assert(Align != 0u && "Align must be non-zero");
-  return {(Size.getKnownMinSize() + Align - 1) / Align * Align,
+  return {(Size.getKnownMinValue() + Align - 1) / Align * Align,
           Size.isScalable()};
 }
 
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 899fb44a776997..036d80649110aa 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -3505,15 +3505,15 @@ const SCEV *ScalarEvolution::getUMinExpr(SmallVectorImpl<const SCEV *> &Ops) {
 }
 
 const SCEV *ScalarEvolution::getSizeOfExpr(Type *IntTy, Type *AllocTy) {
-  // We can bypass creating a target-independent
-  // constant expression and then folding it back into a ConstantInt.
-  // This is just a compile-time optimization.
   if (isa<ScalableVectorType>(AllocTy)) {
     Constant *NullPtr = Constant::getNullValue(AllocTy->getPointerTo());
     Constant *One = ConstantInt::get(IntTy, 1);
     Constant *GEP = ConstantExpr::getGetElementPtr(AllocTy, NullPtr, One);
-    return getSCEV(ConstantExpr::getPtrToInt(GEP, IntTy));
+    return getUnknown(ConstantExpr::getPtrToInt(GEP, IntTy));
   }
+  // We can bypass creating a target-independent
+  // constant expression and then folding it back into a ConstantInt.
+  // This is just a compile-time optimization.
   return getConstant(IntTy, getDataLayout().getTypeAllocSize(AllocTy));
 }
 
@@ -5500,16 +5500,14 @@ ScalarEvolution::getRangeRef(const SCEV *S,
         auto RangeFromAffine = getRangeForAffineAR(
             AddRec->getStart(), AddRec->getStepRecurrence(*this), MaxBECount,
             BitWidth);
-        if (!RangeFromAffine.isFullSet())
-          ConservativeResult =
-              ConservativeResult.intersectWith(RangeFromAffine, RangeType);
+        ConservativeResult =
+            ConservativeResult.intersectWith(RangeFromAffine, RangeType);
 
         auto RangeFromFactoring = getRangeViaFactoring(
             AddRec->getStart(), AddRec->getStepRecurrence(*this), MaxBECount,
             BitWidth);
-        if (!RangeFromFactoring.isFullSet())
-          ConservativeResult =
-              ConservativeResult.intersectWith(RangeFromFactoring, RangeType);
+        ConservativeResult =
+            ConservativeResult.intersectWith(RangeFromFactoring, RangeType);
       }
     }
 
@@ -6303,6 +6301,36 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
       return getSCEV(U->getOperand(0));
     break;
 
+  case Instruction::PtrToInt: {
+    // It's tempting to handle inttoptr and ptrtoint as no-ops,
+    // however this can lead to pointer expressions which cannot safely be
+    // expanded to GEPs because ScalarEvolution doesn't respect
+    // the GEP aliasing rules when simplifying integer expressions.
+    //
+    // However, given
+    //   %x = ???
+    //   %y = ptrtoint %x
+    //   %z = ptrtoint %x
+    // it is safe to say that %y and %z are the same thing.
+    //
+    // So instead of modelling the cast itself as unknown,
+    // since the casts are transparent within SCEV,
+    // we can at least model the casts original value as unknow instead.
+
+    // BUT, there's caveat. If we simply model %x as unknown, unrelated uses
+    // of %x will also see it as unknown, which is obviously bad.
+    // So we can only do this iff %x would be modelled as unknown anyways.
+    auto *OpSCEV = getSCEV(U->getOperand(0));
+    if (isa<SCEVUnknown>(OpSCEV))
+      return getTruncateOrZeroExtend(OpSCEV, U->getType());
+    // If we can model the operand, however, we must fallback to modelling
+    // the whole cast as unknown instead.
+    LLVM_FALLTHROUGH;
+  }
+  case Instruction::IntToPtr:
+    // We can't do this for inttoptr at all, however.
+    return getUnknown(V);
+
   case Instruction::SDiv:
     // If both operands are non-negative, this is just an udiv.
     if (isKnownNonNegative(getSCEV(U->getOperand(0))) &&
@@ -6317,11 +6345,6 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
       return getURemExpr(getSCEV(U->getOperand(0)), getSCEV(U->getOperand(1)));
     break;
 
-  // It's tempting to handle inttoptr and ptrtoint as no-ops, however this can
-  // lead to pointer expressions which cannot safely be expanded to GEPs,
-  // because ScalarEvolution doesn't respect the GEP aliasing rules when
-  // simplifying integer expressions.
-
   case Instruction::GetElementPtr:
     return createNodeForGEP(cast<GEPOperator>(U));
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 65a5c79115035b..eab6bc39b1c6a5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19573,7 +19573,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
                             V.getOperand(0), NewIndex);
             return DAG.getBitcast(NVT, NewExtract);
           }
-          if (NewExtEC == 1 &&
+          if (NewExtEC.isScalar() &&
               TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, ScalarVT)) {
             SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL);
             SDValue NewExtract =
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 0000fcb1dde1bb..8c2efe89d6f110 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1129,27 +1129,44 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
   SDValue Lo = GetPromotedInteger(N->getOperand(1));
   SDValue Amount = GetPromotedInteger(N->getOperand(2));
 
-  unsigned OldBits = N->getOperand(0).getScalarValueSizeInBits();
-  unsigned NewBits = Hi.getScalarValueSizeInBits();
-
-  // Shift Lo up to occupy the upper bits of the promoted type.
   SDLoc DL(N);
+  EVT OldVT = N->getOperand(0).getValueType();
   EVT VT = Lo.getValueType();
-  Lo = DAG.getNode(ISD::SHL, DL, VT, Lo,
-                   DAG.getConstant(NewBits - OldBits, DL, VT));
+  unsigned Opcode = N->getOpcode();
+  bool IsFSHR = Opcode == ISD::FSHR;
+  unsigned OldBits = OldVT.getScalarSizeInBits();
+  unsigned NewBits = VT.getScalarSizeInBits();
 
   // Amount has to be interpreted modulo the old bit width.
   Amount =
       DAG.getNode(ISD::UREM, DL, VT, Amount, DAG.getConstant(OldBits, DL, VT));
 
-  unsigned Opcode = N->getOpcode();
-  if (Opcode == ISD::FSHR) {
-    // Increase Amount to shift the result into the lower bits of the promoted
-    // type.
-    Amount = DAG.getNode(ISD::ADD, DL, VT, Amount,
-                         DAG.getConstant(NewBits - OldBits, DL, VT));
+  // If the promoted type is twice the size (or more), then we use the
+  // traditional funnel 'double' shift codegen. This isn't necessary if the
+  // shift amount is constant.
+  // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
+  // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
+  if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Amount) &&
+      !TLI.isOperationLegalOrCustom(Opcode, VT)) {
+    SDValue HiShift = DAG.getConstant(OldBits, DL, VT);
+    Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift);
+    Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT);
+    SDValue Res = DAG.getNode(ISD::OR, DL, VT, Hi, Lo);
+    Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amount);
+    if (!IsFSHR)
+      Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift);
+    return Res;
   }
 
+  // Shift Lo up to occupy the upper bits of the promoted type.
+  SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, VT);
+  Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset);
+
+  // Increase Amount to shift the result into the lower bits of the promoted
+  // type.
+  if (IsFSHR)
+    Amount = DAG.getNode(ISD::ADD, DL, VT, Amount, ShiftOffset);
+
   return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amount);
 }
 
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index ead52b80345927..84ff390126a14e 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -862,7 +862,7 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
   EVT EltVT = VT.getVectorElementType();
 
   // Vectors with only one element are always scalarized.
-  if (NumElts == 1)
+  if (NumElts.isScalar())
     return LegalizeKind(TypeScalarizeVector, EltVT);
 
   if (VT.getVectorElementCount() == ElementCount::getScalable(1))
@@ -875,7 +875,7 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
     // Vectors with a number of elements that is not a power of two are always
     // widened, for example <3 x i8> -> <4 x i8>.
     if (!VT.isPow2VectorType()) {
-      NumElts = NumElts.NextPowerOf2();
+      NumElts = NumElts.coefficientNextPowerOf2();
       EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
       return LegalizeKind(TypeWidenVector, NVT);
     }
@@ -924,7 +924,7 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
   // If there is no wider legal type, split the vector.
   while (true) {
     // Round up to the next power of 2.
-    NumElts = NumElts.NextPowerOf2();
+    NumElts = NumElts.coefficientNextPowerOf2();
 
     // If there is no simple vector type with this many elements then there
     // cannot be a larger legal vector type.  Note that this assumes that
@@ -1499,7 +1499,7 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT
     TypeSize NewVTSize = NewVT.getSizeInBits();
     // Convert sizes such as i33 to i64.
     if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
-      NewVTSize = NewVTSize.NextPowerOf2();
+      NewVTSize = NewVTSize.coefficientNextPowerOf2();
     return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
   }
 
diff --git a/llvm/lib/Support/LowLevelType.cpp b/llvm/lib/Support/LowLevelType.cpp
index fe77cb3db4139a..63559d5ac3eee8 100644
--- a/llvm/lib/Support/LowLevelType.cpp
+++ b/llvm/lib/Support/LowLevelType.cpp
@@ -23,7 +23,7 @@ LLT::LLT(MVT VT) {
   } else if (VT.isValid()) {
     // Aggregates are no different from real scalars as far as GlobalISel is
     // concerned.
-    assert(VT.getSizeInBits() != 0 && "invalid zero-sized type");
+    assert(VT.getSizeInBits().isNonZero() && "invalid zero-sized type");
     init(/*IsPointer=*/false, /*IsVector=*/false, /*NumElements=*/0,
          VT.getSizeInBits(), /*AddressSpace=*/0);
   } else {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c2972ab4f2f7c9..b1c4903cb5e307 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1114,24 +1114,16 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::UMAX, MVT::v2i64, Custom);
       setOperationAction(ISD::UMIN, MVT::v1i64, Custom);
       setOperationAction(ISD::UMIN, MVT::v2i64, Custom);
-      setOperationAction(ISD::VECREDUCE_AND, MVT::v8i8, Custom);
-      setOperationAction(ISD::VECREDUCE_AND, MVT::v16i8, Custom);
-      setOperationAction(ISD::VECREDUCE_AND, MVT::v4i16, Custom);
-      setOperationAction(ISD::VECREDUCE_AND, MVT::v8i16, Custom);
-      setOperationAction(ISD::VECREDUCE_AND, MVT::v2i32, Custom);
-      setOperationAction(ISD::VECREDUCE_AND, MVT::v4i32, Custom);
-      setOperationAction(ISD::VECREDUCE_AND, MVT::v2i64, Custom);
-      setOperationAction(ISD::VECREDUCE_OR, MVT::v8i8, Custom);
-      setOperationAction(ISD::VECREDUCE_OR, MVT::v16i8, Custom);
-      setOperationAction(ISD::VECREDUCE_OR, MVT::v4i16, Custom);
-      setOperationAction(ISD::VECREDUCE_OR, MVT::v8i16, Custom);
-      setOperationAction(ISD::VECREDUCE_OR, MVT::v2i32, Custom);
-      setOperationAction(ISD::VECREDUCE_OR, MVT::v4i32, Custom);
-      setOperationAction(ISD::VECREDUCE_OR, MVT::v2i64, Custom);
       setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
       setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
       setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
       setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
+      for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
+                      MVT::v2i32, MVT::v4i32, MVT::v2i64}) {
+        setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
+        setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
+        setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
+      }
     }
   }
 
@@ -1275,6 +1267,7 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
   setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
   setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
   setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
+  setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
   setOperationAction(ISD::VSELECT, VT, Custom);
   setOperationAction(ISD::XOR, VT, Custom);
   setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
@@ -3953,6 +3946,7 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
   case ISD::VECREDUCE_ADD:
   case ISD::VECREDUCE_AND:
   case ISD::VECREDUCE_OR:
+  case ISD::VECREDUCE_XOR:
   case ISD::VECREDUCE_SMAX:
   case ISD::VECREDUCE_SMIN:
   case ISD::VECREDUCE_UMAX:
@@ -9742,6 +9736,7 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
   EVT SrcVT = Src.getValueType();
   bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND ||
                       Op.getOpcode() == ISD::VECREDUCE_OR ||
+                      Op.getOpcode() == ISD::VECREDUCE_XOR ||
                       (Op.getOpcode() != ISD::VECREDUCE_ADD &&
                        SrcVT.getVectorElementType() == MVT::i64);
   if (useSVEForFixedLengthVectorVT(SrcVT, OverrideNEON)) {
@@ -9760,6 +9755,8 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
       return LowerFixedLengthReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG);
     case ISD::VECREDUCE_UMIN:
       return LowerFixedLengthReductionToSVE(AArch64ISD::UMINV_PRED, Op, DAG);
+    case ISD::VECREDUCE_XOR:
+      return LowerFixedLengthReductionToSVE(AArch64ISD::EORV_PRED, Op, DAG);
     case ISD::VECREDUCE_FMAX:
       return LowerFixedLengthReductionToSVE(AArch64ISD::FMAXNMV_PRED, Op, DAG);
     case ISD::VECREDUCE_FMIN:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 79975f82f69468..565ad7ecd53d37 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -679,6 +679,11 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
   /// } Stack
 
+  /// Branch {
+  // VE doesn't have BRCOND
+  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+  /// } Branch
+
   /// Int Ops {
   for (MVT IntVT : {MVT::i32, MVT::i64}) {
     // VE has no REM or DIVREM operations.
@@ -735,6 +740,14 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
   /// } Conversion
 
   /// Floating-point Ops {
+  /// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem,
+  ///       and fcmp.
+
+  // VE doesn't have following floating point operations.
+  for (MVT VT : MVT::fp_valuetypes()) {
+    setOperationAction(ISD::FNEG, VT, Expand);
+    setOperationAction(ISD::FREM, VT, Expand);
+  }
 
   // VE doesn't have fdiv of f128.
   setOperationAction(ISD::FDIV, MVT::f128, Expand);
@@ -745,6 +758,15 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
   }
   /// } Floating-point Ops
 
+  /// Floating-point math functions {
+
+  // VE doesn't have following floating point math functions.
+  for (MVT VT : MVT::fp_valuetypes()) {
+    setOperationAction(ISD::FCOPYSIGN, VT, Expand);
+  }
+
+  /// } Floating-point math functions
+
   setStackPointerRegisterToSaveRestore(VE::SX11);
 
   // We have target-specific dag combine patterns for the following nodes:
diff --git a/llvm/lib/Target/X86/X86InterleavedAccess.cpp b/llvm/lib/Target/X86/X86InterleavedAccess.cpp
index a19e12766e101a..866c53235db42b 100644
--- a/llvm/lib/Target/X86/X86InterleavedAccess.cpp
+++ b/llvm/lib/Target/X86/X86InterleavedAccess.cpp
@@ -211,7 +211,7 @@ void X86InterleavedAccessGroup::decompose(
     VecBasePtr = Builder.CreateBitCast(LI->getPointerOperand(), VecBasePtrTy);
   }
   // Generate N loads of T type.
-  assert(VecBaseTy->getPrimitiveSizeInBits().isByteSized() &&
+  assert(VecBaseTy->getPrimitiveSizeInBits().isKnownMultipleOf(8) &&
          "VecBaseTy's size must be a multiple of 8");
   const Align FirstAlignment = LI->getAlign();
   const Align SubsequentAlignment = commonAlignment(
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 227a0ab649041a..fb415bf20d1a3e 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2067,13 +2067,19 @@ static Instruction *matchFunnelShift(Instruction &Or, InstCombinerImpl &IC) {
 
   Value *ShVal0, *ShVal1, *ShAmt0, *ShAmt1;
   if (!match(Or0, m_OneUse(m_LogicalShift(m_Value(ShVal0), m_Value(ShAmt0)))) ||
-      !match(Or1, m_OneUse(m_LogicalShift(m_Value(ShVal1), m_Value(ShAmt1)))))
+      !match(Or1, m_OneUse(m_LogicalShift(m_Value(ShVal1), m_Value(ShAmt1)))) ||
+      Or0->getOpcode() == Or1->getOpcode())
     return nullptr;
 
-  BinaryOperator::BinaryOps ShiftOpcode0 = Or0->getOpcode();
-  BinaryOperator::BinaryOps ShiftOpcode1 = Or1->getOpcode();
-  if (ShiftOpcode0 == ShiftOpcode1)
-    return nullptr;
+  // Canonicalize to or(shl(ShVal0, ShAmt0), lshr(ShVal1, ShAmt1)).
+  if (Or0->getOpcode() == BinaryOperator::LShr) {
+    std::swap(Or0, Or1);
+    std::swap(ShVal0, ShVal1);
+    std::swap(ShAmt0, ShAmt1);
+  }
+  assert(Or0->getOpcode() == BinaryOperator::Shl &&
+         Or1->getOpcode() == BinaryOperator::LShr &&
+         "Illegal or(shift,shift) pair");
 
   // Match the shift amount operands for a funnel shift pattern. This always
   // matches a subtraction on the R operand.
@@ -2134,20 +2140,17 @@ static Instruction *matchFunnelShift(Instruction &Or, InstCombinerImpl &IC) {
   };
 
   Value *ShAmt = matchShiftAmount(ShAmt0, ShAmt1, Width);
-  bool SubIsOnLHS = false;
+  bool IsFshl = true; // Sub on LSHR.
   if (!ShAmt) {
     ShAmt = matchShiftAmount(ShAmt1, ShAmt0, Width);
-    SubIsOnLHS = true;
+    IsFshl = false; // Sub on SHL.
   }
   if (!ShAmt)
     return nullptr;
 
-  bool IsFshl = (!SubIsOnLHS && ShiftOpcode0 == BinaryOperator::Shl) ||
-                (SubIsOnLHS && ShiftOpcode1 == BinaryOperator::Shl);
   Intrinsic::ID IID = IsFshl ? Intrinsic::fshl : Intrinsic::fshr;
   Function *F = Intrinsic::getDeclaration(Or.getModule(), IID, Or.getType());
-  return IntrinsicInst::Create(
-      F, {IsFshl ? ShVal0 : ShVal1, IsFshl ? ShVal1 : ShVal0, ShAmt});
+  return IntrinsicInst::Create(F, {ShVal0, ShVal1, ShAmt});
 }
 
 /// Attempt to combine or(zext(x),shl(zext(y),bw/2) concat packing patterns.
diff --git a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
index 2d71b0fff88940..3e280a66175c88 100644
--- a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
@@ -427,7 +427,7 @@ static bool willNotOverflow(ScalarEvolution *SE, Instruction::BinaryOps BinOp,
              : &ScalarEvolution::getZeroExtendExpr;
 
   // Check ext(LHS op RHS) == ext(LHS) op ext(RHS)
-  auto *NarrowTy = cast<IntegerType>(LHS->getType());
+  auto *NarrowTy = cast<IntegerType>(SE->getEffectiveSCEVType(LHS->getType()));
   auto *WideTy =
     IntegerType::get(NarrowTy->getContext(), NarrowTy->getBitWidth() * 2);
 
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index d0539cca27b82e..95d55d062da03c 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -353,7 +353,9 @@ static bool hasIrregularType(Type *Ty, const DataLayout &DL, ElementCount VF) {
   // with a <VF x Ty> vector.
   if (VF.isVector()) {
     auto *VectorTy = VectorType::get(Ty, VF);
-    return VF * DL.getTypeAllocSize(Ty) != DL.getTypeStoreSize(VectorTy);
+    return TypeSize::get(VF.getKnownMinValue() *
+                             DL.getTypeAllocSize(Ty).getFixedValue(),
+                         VF.isScalable()) != DL.getTypeStoreSize(VectorTy);
   }
 
   // If the vectorization factor is one, we just check if an array of type Ty
@@ -2166,7 +2168,7 @@ Value *InnerLoopVectorizer::getOrCreateVectorValue(Value *V, unsigned Part) {
 
     // If we aren't vectorizing, we can just copy the scalar map values over to
     // the vector map.
-    if (VF == 1) {
+    if (VF.isScalar()) {
       VectorLoopValueMap.setVectorValue(V, Part, ScalarValue);
       return ScalarValue;
     }
@@ -2242,7 +2244,7 @@ InnerLoopVectorizer::getOrCreateScalarValue(Value *V,
   // extractelement instruction.
   auto *U = getOrCreateVectorValue(V, Instance.Part);
   if (!U->getType()->isVectorTy()) {
-    assert(VF == 1 && "Value not scalarized has non-vector type");
+    assert(VF.isScalar() && "Value not scalarized has non-vector type");
     return U;
   }
 
@@ -3933,7 +3935,7 @@ void InnerLoopVectorizer::fixReduction(PHINode *Phi) {
   if (RK == RecurrenceDescriptor::RK_IntegerMinMax ||
       RK == RecurrenceDescriptor::RK_FloatMinMax) {
     // MinMax reduction have the start value as their identify.
-    if (VF == 1 || IsInLoopReductionPhi) {
+    if (VF.isScalar() || IsInLoopReductionPhi) {
       VectorStart = Identity = ReductionStartValue;
     } else {
       VectorStart = Identity =
@@ -3943,7 +3945,7 @@ void InnerLoopVectorizer::fixReduction(PHINode *Phi) {
     // Handle other reduction kinds:
     Constant *Iden = RecurrenceDescriptor::getRecurrenceIdentity(
         RK, MinMaxKind, VecTy->getScalarType());
-    if (VF == 1 || IsInLoopReductionPhi) {
+    if (VF.isScalar() || IsInLoopReductionPhi) {
       Identity = Iden;
       // This vector is the Identity vector where the first element is the
       // incoming scalar reduction.
@@ -4343,7 +4345,7 @@ void InnerLoopVectorizer::widenGEP(GetElementPtrInst *GEP, VPUser &Operands,
               ? Builder.CreateInBoundsGEP(GEP->getSourceElementType(), Ptr,
                                           Indices)
               : Builder.CreateGEP(GEP->getSourceElementType(), Ptr, Indices);
-      assert((VF == 1 || NewGEP->getType()->isVectorTy()) &&
+      assert((VF.isScalar() || NewGEP->getType()->isVectorTy()) &&
              "NewGEP is not a pointer vector");
       VectorLoopValueMap.setVectorValue(GEP, Part, NewGEP);
       addMetadata(NewGEP, GEP);
@@ -8413,7 +8415,7 @@ bool LoopVectorizePass::processLoop(Loop *L) {
     return false;
   }
 
-  if (VF.Width == 1) {
+  if (VF.Width.isScalar()) {
     LLVM_DEBUG(dbgs() << "LV: Vectorization is possible but not beneficial.\n");
     VecDiagMsg = std::make_pair(
         "VectorizationNotBeneficial",
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 852e9454cf0745..a009393d029cc4 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -536,7 +536,7 @@ void VPlan::execute(VPTransformState *State) {
                                    "trip.count.minus.1");
     auto VF = State->VF;
     Value *VTCMO =
-        VF == 1 ? TCMO : Builder.CreateVectorSplat(VF, TCMO, "broadcast");
+        VF.isScalar() ? TCMO : Builder.CreateVectorSplat(VF, TCMO, "broadcast");
     for (unsigned Part = 0, UF = State->UF; Part < UF; ++Part)
       State->set(BackedgeTakenCount, VTCMO, Part);
   }
@@ -930,7 +930,8 @@ void VPWidenCanonicalIVRecipe::execute(VPTransformState &State) {
           ConstantInt::get(STy, Part * VF.getKnownMinValue() + Lane));
     // If VF == 1, there is only one iteration in the loop above, thus the
     // element pushed back into Indices is ConstantInt::get(STy, Part)
-    Constant *VStep = VF == 1 ? Indices.back() : ConstantVector::get(Indices);
+    Constant *VStep =
+        VF.isScalar() ? Indices.back() : ConstantVector::get(Indices);
     // Add the consecutive indices to the vector value.
     Value *CanonicalVectorIV = Builder.CreateAdd(VStart, VStep, "vec.iv");
     State.set(getVPValue(), CanonicalVectorIV, Part);
diff --git a/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll b/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll
index 93a3bf4d4c3786..e798e2715ba1da 100644
--- a/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll
+++ b/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll
@@ -33,9 +33,9 @@ define i32 @d(i32 %base) {
 ; CHECK-NEXT:    %1 = load i32*, i32** @c, align 8
 ; CHECK-NEXT:    --> %1 U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %for.cond: Variant }
 ; CHECK-NEXT:    %sub.ptr.lhs.cast = ptrtoint i32* %1 to i64
-; CHECK-NEXT:    --> %sub.ptr.lhs.cast U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %for.cond: Variant }
+; CHECK-NEXT:    --> %1 U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %for.cond: Variant }
 ; CHECK-NEXT:    %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, ptrtoint ([1 x i32]* @b to i64)
-; CHECK-NEXT:    --> ((-1 * ptrtoint ([1 x i32]* @b to i64)) + %sub.ptr.lhs.cast) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %for.cond: Variant }
+; CHECK-NEXT:    --> ((-1 * @b) + %1) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %for.cond: Variant }
 ; CHECK-NEXT:    %sub.ptr.div = sdiv exact i64 %sub.ptr.sub, 4
 ; CHECK-NEXT:    --> %sub.ptr.div U: full-set S: [-2305843009213693952,2305843009213693952) Exits: <<Unknown>> LoopDispositions: { %for.cond: Variant }
 ; CHECK-NEXT:    %arrayidx1 = getelementptr inbounds [1 x i8], [1 x i8]* %arrayidx, i64 0, i64 %sub.ptr.div
diff --git a/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll b/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll
index 5a7bb3c9e5cd54..eb669cab0c790f 100644
--- a/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll
+++ b/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll
@@ -170,14 +170,14 @@ define void @f3(i8* %x_addr, i8* %y_addr, i32* %tmp_addr) {
   %int5 = add i32 %int0, 5
   %int.zext = zext i32 %int5 to i64
 ; CHECK:  %int.zext = zext i32 %int5 to i64
-; CHECK-NEXT:  -->  (1 + (zext i32 (4 + %int0) to i64))<nuw><nsw> U: [1,4294967294) S: [1,4294967297)
+; CHECK-NEXT:  -->  (1 + (zext i32 (4 + (trunc [16 x i8]* @z_addr to i32)) to i64))<nuw><nsw> U: [1,4294967294) S: [1,4294967297)
 
   %ptr_noalign = bitcast [16 x i8]* @z_addr_noalign to i8*
   %int0_na = ptrtoint i8* %ptr_noalign to i32
   %int5_na = add i32 %int0_na, 5
   %int.zext_na = zext i32 %int5_na to i64
 ; CHECK:  %int.zext_na = zext i32 %int5_na to i64
-; CHECK-NEXT:  -->  (zext i32 (5 + %int0_na) to i64) U: [0,4294967296) S: [0,4294967296)
+; CHECK-NEXT:  -->  (zext i32 (5 + (trunc [16 x i8]* @z_addr_noalign to i32)) to i64) U: [0,4294967296) S: [0,4294967296)
 
   %tmp = load i32, i32* %tmp_addr
   %mul = and i32 %tmp, -4
diff --git a/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll b/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
index e3e9330e241f83..ac08fb24775e51 100644
--- a/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
+++ b/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
@@ -16,25 +16,25 @@ define void @ptrtoint(i8* %in, i64* %out0, i32* %out1, i16* %out2, i128* %out3)
 ; X64-LABEL: 'ptrtoint'
 ; X64-NEXT:  Classifying expressions for: @ptrtoint
 ; X64-NEXT:    %p0 = ptrtoint i8* %in to i64
-; X64-NEXT:    --> %p0 U: full-set S: full-set
+; X64-NEXT:    --> %in U: full-set S: full-set
 ; X64-NEXT:    %p1 = ptrtoint i8* %in to i32
-; X64-NEXT:    --> %p1 U: full-set S: full-set
+; X64-NEXT:    --> (trunc i8* %in to i32) U: full-set S: full-set
 ; X64-NEXT:    %p2 = ptrtoint i8* %in to i16
-; X64-NEXT:    --> %p2 U: full-set S: full-set
+; X64-NEXT:    --> (trunc i8* %in to i16) U: full-set S: full-set
 ; X64-NEXT:    %p3 = ptrtoint i8* %in to i128
-; X64-NEXT:    --> %p3 U: [0,18446744073709551616) S: [-18446744073709551616,18446744073709551616)
+; X64-NEXT:    --> (zext i8* %in to i128) U: [0,18446744073709551616) S: [0,18446744073709551616)
 ; X64-NEXT:  Determining loop execution counts for: @ptrtoint
 ;
 ; X32-LABEL: 'ptrtoint'
 ; X32-NEXT:  Classifying expressions for: @ptrtoint
 ; X32-NEXT:    %p0 = ptrtoint i8* %in to i64
-; X32-NEXT:    --> %p0 U: [0,4294967296) S: [-4294967296,4294967296)
+; X32-NEXT:    --> (zext i8* %in to i64) U: [0,4294967296) S: [0,4294967296)
 ; X32-NEXT:    %p1 = ptrtoint i8* %in to i32
-; X32-NEXT:    --> %p1 U: full-set S: full-set
+; X32-NEXT:    --> %in U: full-set S: full-set
 ; X32-NEXT:    %p2 = ptrtoint i8* %in to i16
-; X32-NEXT:    --> %p2 U: full-set S: full-set
+; X32-NEXT:    --> (trunc i8* %in to i16) U: full-set S: full-set
 ; X32-NEXT:    %p3 = ptrtoint i8* %in to i128
-; X32-NEXT:    --> %p3 U: [0,4294967296) S: [-4294967296,4294967296)
+; X32-NEXT:    --> (zext i8* %in to i128) U: [0,4294967296) S: [0,4294967296)
 ; X32-NEXT:  Determining loop execution counts for: @ptrtoint
 ;
   %p0 = ptrtoint i8* %in to i64
@@ -53,25 +53,25 @@ define void @ptrtoint_as1(i8 addrspace(1)* %in, i64* %out0, i32* %out1, i16* %ou
 ; X64-LABEL: 'ptrtoint_as1'
 ; X64-NEXT:  Classifying expressions for: @ptrtoint_as1
 ; X64-NEXT:    %p0 = ptrtoint i8 addrspace(1)* %in to i64
-; X64-NEXT:    --> %p0 U: full-set S: full-set
+; X64-NEXT:    --> %in U: full-set S: full-set
 ; X64-NEXT:    %p1 = ptrtoint i8 addrspace(1)* %in to i32
-; X64-NEXT:    --> %p1 U: full-set S: full-set
+; X64-NEXT:    --> (trunc i8 addrspace(1)* %in to i32) U: full-set S: full-set
 ; X64-NEXT:    %p2 = ptrtoint i8 addrspace(1)* %in to i16
-; X64-NEXT:    --> %p2 U: full-set S: full-set
+; X64-NEXT:    --> (trunc i8 addrspace(1)* %in to i16) U: full-set S: full-set
 ; X64-NEXT:    %p3 = ptrtoint i8 addrspace(1)* %in to i128
-; X64-NEXT:    --> %p3 U: [0,18446744073709551616) S: [-18446744073709551616,18446744073709551616)
+; X64-NEXT:    --> (zext i8 addrspace(1)* %in to i128) U: [0,18446744073709551616) S: [0,18446744073709551616)
 ; X64-NEXT:  Determining loop execution counts for: @ptrtoint_as1
 ;
 ; X32-LABEL: 'ptrtoint_as1'
 ; X32-NEXT:  Classifying expressions for: @ptrtoint_as1
 ; X32-NEXT:    %p0 = ptrtoint i8 addrspace(1)* %in to i64
-; X32-NEXT:    --> %p0 U: [0,4294967296) S: [-4294967296,4294967296)
+; X32-NEXT:    --> (zext i8 addrspace(1)* %in to i64) U: [0,4294967296) S: [0,4294967296)
 ; X32-NEXT:    %p1 = ptrtoint i8 addrspace(1)* %in to i32
-; X32-NEXT:    --> %p1 U: full-set S: full-set
+; X32-NEXT:    --> %in U: full-set S: full-set
 ; X32-NEXT:    %p2 = ptrtoint i8 addrspace(1)* %in to i16
-; X32-NEXT:    --> %p2 U: full-set S: full-set
+; X32-NEXT:    --> (trunc i8 addrspace(1)* %in to i16) U: full-set S: full-set
 ; X32-NEXT:    %p3 = ptrtoint i8 addrspace(1)* %in to i128
-; X32-NEXT:    --> %p3 U: [0,4294967296) S: [-4294967296,4294967296)
+; X32-NEXT:    --> (zext i8 addrspace(1)* %in to i128) U: [0,4294967296) S: [0,4294967296)
 ; X32-NEXT:  Determining loop execution counts for: @ptrtoint_as1
 ;
   %p0 = ptrtoint i8 addrspace(1)* %in to i64
@@ -92,7 +92,7 @@ define void @ptrtoint_of_bitcast(i8* %in, i64* %out0) {
 ; X64-NEXT:    %in_casted = bitcast i8* %in to float*
 ; X64-NEXT:    --> %in U: full-set S: full-set
 ; X64-NEXT:    %p0 = ptrtoint float* %in_casted to i64
-; X64-NEXT:    --> %p0 U: full-set S: full-set
+; X64-NEXT:    --> %in U: full-set S: full-set
 ; X64-NEXT:  Determining loop execution counts for: @ptrtoint_of_bitcast
 ;
 ; X32-LABEL: 'ptrtoint_of_bitcast'
@@ -100,7 +100,7 @@ define void @ptrtoint_of_bitcast(i8* %in, i64* %out0) {
 ; X32-NEXT:    %in_casted = bitcast i8* %in to float*
 ; X32-NEXT:    --> %in U: full-set S: full-set
 ; X32-NEXT:    %p0 = ptrtoint float* %in_casted to i64
-; X32-NEXT:    --> %p0 U: [0,4294967296) S: [-4294967296,4294967296)
+; X32-NEXT:    --> (zext i8* %in to i64) U: [0,4294967296) S: [0,4294967296)
 ; X32-NEXT:  Determining loop execution counts for: @ptrtoint_of_bitcast
 ;
   %in_casted = bitcast i8* %in to float*
@@ -116,7 +116,7 @@ define void @ptrtoint_of_addrspacecast(i8* %in, i64* %out0) {
 ; X64-NEXT:    %in_casted = addrspacecast i8* %in to i8 addrspace(1)*
 ; X64-NEXT:    --> %in_casted U: full-set S: full-set
 ; X64-NEXT:    %p0 = ptrtoint i8 addrspace(1)* %in_casted to i64
-; X64-NEXT:    --> %p0 U: full-set S: full-set
+; X64-NEXT:    --> %in_casted U: full-set S: full-set
 ; X64-NEXT:  Determining loop execution counts for: @ptrtoint_of_addrspacecast
 ;
 ; X32-LABEL: 'ptrtoint_of_addrspacecast'
@@ -124,7 +124,7 @@ define void @ptrtoint_of_addrspacecast(i8* %in, i64* %out0) {
 ; X32-NEXT:    %in_casted = addrspacecast i8* %in to i8 addrspace(1)*
 ; X32-NEXT:    --> %in_casted U: full-set S: full-set
 ; X32-NEXT:    %p0 = ptrtoint i8 addrspace(1)* %in_casted to i64
-; X32-NEXT:    --> %p0 U: [0,4294967296) S: [-4294967296,4294967296)
+; X32-NEXT:    --> (zext i8 addrspace(1)* %in_casted to i64) U: [0,4294967296) S: [0,4294967296)
 ; X32-NEXT:  Determining loop execution counts for: @ptrtoint_of_addrspacecast
 ;
   %in_casted = addrspacecast i8* %in to i8 addrspace(1)*
@@ -140,7 +140,7 @@ define void @ptrtoint_of_inttoptr(i64 %in, i64* %out0) {
 ; X64-NEXT:    %in_casted = inttoptr i64 %in to i8*
 ; X64-NEXT:    --> %in_casted U: full-set S: full-set
 ; X64-NEXT:    %p0 = ptrtoint i8* %in_casted to i64
-; X64-NEXT:    --> %p0 U: full-set S: full-set
+; X64-NEXT:    --> %in_casted U: full-set S: full-set
 ; X64-NEXT:  Determining loop execution counts for: @ptrtoint_of_inttoptr
 ;
 ; X32-LABEL: 'ptrtoint_of_inttoptr'
@@ -148,7 +148,7 @@ define void @ptrtoint_of_inttoptr(i64 %in, i64* %out0) {
 ; X32-NEXT:    %in_casted = inttoptr i64 %in to i8*
 ; X32-NEXT:    --> %in_casted U: full-set S: full-set
 ; X32-NEXT:    %p0 = ptrtoint i8* %in_casted to i64
-; X32-NEXT:    --> %p0 U: [0,4294967296) S: [-4294967296,4294967296)
+; X32-NEXT:    --> (zext i8* %in_casted to i64) U: [0,4294967296) S: [0,4294967296)
 ; X32-NEXT:  Determining loop execution counts for: @ptrtoint_of_inttoptr
 ;
   %in_casted = inttoptr i64 %in to i8*
@@ -197,11 +197,17 @@ define void @ptrtoint_of_nullptr(i64* %out0) {
 
 ; A constant inttoptr argument of an ptrtoint is still bad.
 define void @ptrtoint_of_constantexpr_inttoptr(i64* %out0) {
-; ALL-LABEL: 'ptrtoint_of_constantexpr_inttoptr'
-; ALL-NEXT:  Classifying expressions for: @ptrtoint_of_constantexpr_inttoptr
-; ALL-NEXT:    %p0 = ptrtoint i8* inttoptr (i64 42 to i8*) to i64
-; ALL-NEXT:    --> %p0 U: [42,43) S: [-64,64)
-; ALL-NEXT:  Determining loop execution counts for: @ptrtoint_of_constantexpr_inttoptr
+; X64-LABEL: 'ptrtoint_of_constantexpr_inttoptr'
+; X64-NEXT:  Classifying expressions for: @ptrtoint_of_constantexpr_inttoptr
+; X64-NEXT:    %p0 = ptrtoint i8* inttoptr (i64 42 to i8*) to i64
+; X64-NEXT:    --> inttoptr (i64 42 to i8*) U: [42,43) S: [-64,64)
+; X64-NEXT:  Determining loop execution counts for: @ptrtoint_of_constantexpr_inttoptr
+;
+; X32-LABEL: 'ptrtoint_of_constantexpr_inttoptr'
+; X32-NEXT:  Classifying expressions for: @ptrtoint_of_constantexpr_inttoptr
+; X32-NEXT:    %p0 = ptrtoint i8* inttoptr (i64 42 to i8*) to i64
+; X32-NEXT:    --> (zext i8* inttoptr (i64 42 to i8*) to i64) U: [42,43) S: [0,4294967296)
+; X32-NEXT:  Determining loop execution counts for: @ptrtoint_of_constantexpr_inttoptr
 ;
   %p0 = ptrtoint i8* inttoptr (i64 42 to i8*) to i64
   store i64 %p0, i64* %out0
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
index efab691b4a9f45..ffe72b511e0d9e 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
@@ -343,6 +343,329 @@ define i64 @andv_v32i64(<32 x i64>* %a) #0 {
   ret i64 %res
 }
 
+;
+; EORV
+;
+
+; No single instruction NEON EORV support. Use SVE.
+define i8 @eorv_v8i8(<8 x i8> %a) #0 {
+; CHECK-LABEL: eorv_v8i8:
+; CHECK: ptrue [[PG:p[0-9]+]].b, vl8
+; CHECK: eorv b[[REDUCE:[0-9]+]], [[PG]], z0.b
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+  %res = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> %a)
+  ret i8 %res
+}
+
+; No single instruction NEON EORV support. Use SVE.
+define i8 @eorv_v16i8(<16 x i8> %a) #0 {
+; CHECK-LABEL: eorv_v16i8:
+; CHECK: ptrue [[PG:p[0-9]+]].b, vl16
+; CHECK: eorv b[[REDUCE:[0-9]+]], [[PG]], z0.b
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+  %res = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> %a)
+  ret i8 %res
+}
+
+define i8 @eorv_v32i8(<32 x i8>* %a) #0 {
+; CHECK-LABEL: eorv_v32i8:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].b, vl32
+; VBITS_GE_256-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: eorv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+  %op = load <32 x i8>, <32 x i8>* %a
+  %res = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> %op)
+  ret i8 %res
+}
+
+define i8 @eorv_v64i8(<64 x i8>* %a) #0 {
+; CHECK-LABEL: eorv_v64i8:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64
+; VBITS_GE_512-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: eorv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_512-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
+; VBITS_EQ_256-DAG: mov w[[A_HI:[0-9]+]], #32
+; VBITS_EQ_256-DAG: ld1b { [[LO:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1b { [[HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A_HI]]]
+; VBITS_EQ_256-DAG: eor [[EOR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: eorv b[[REDUCE:[0-9]+]], [[PG]], [[EOR]].b
+; VBITS_EQ_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+
+  %op = load <64 x i8>, <64 x i8>* %a
+  %res = call i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8> %op)
+  ret i8 %res
+}
+
+define i8 @eorv_v128i8(<128 x i8>* %a) #0 {
+; CHECK-LABEL: eorv_v128i8:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128
+; VBITS_GE_1024-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: eorv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <128 x i8>, <128 x i8>* %a
+  %res = call i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8> %op)
+  ret i8 %res
+}
+
+define i8 @eorv_v256i8(<256 x i8>* %a) #0 {
+; CHECK-LABEL: eorv_v256i8:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256
+; VBITS_GE_2048-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: eorv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
+; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <256 x i8>, <256 x i8>* %a
+  %res = call i8 @llvm.experimental.vector.reduce.xor.v256i8(<256 x i8> %op)
+  ret i8 %res
+}
+
+; No single instruction NEON EORV support. Use SVE.
+define i16 @eorv_v4i16(<4 x i16> %a) #0 {
+; CHECK-LABEL: eorv_v4i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl4
+; CHECK: eorv h[[REDUCE:[0-9]+]], [[PG]], z0.h
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+  %res = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> %a)
+  ret i16 %res
+}
+
+; No single instruction NEON EORV support. Use SVE.
+define i16 @eorv_v8i16(<8 x i16> %a) #0 {
+; CHECK-LABEL: eorv_v8i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl8
+; CHECK: eorv h[[REDUCE:[0-9]+]], [[PG]], z0.h
+; CHECK: fmov w0, s[[REDUCE]]
+; CHECK: ret
+  %res = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> %a)
+  ret i16 %res
+}
+
+define i16 @eorv_v16i16(<16 x i16>* %a) #0 {
+; CHECK-LABEL: eorv_v16i16:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].h, vl16
+; VBITS_GE_256-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: eorv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+  %op = load <16 x i16>, <16 x i16>* %a
+  %res = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> %op)
+  ret i16 %res
+}
+
+define i16 @eorv_v32i16(<32 x i16>* %a) #0 {
+; CHECK-LABEL: eorv_v32i16:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32
+; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: eorv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_512-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1h { [[LO:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1h { [[HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: eor [[EOR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: eorv h[[REDUCE:[0-9]+]], [[PG]], [[EOR]].h
+; VBITS_EQ_256-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <32 x i16>, <32 x i16>* %a
+  %res = call i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16> %op)
+  ret i16 %res
+}
+
+define i16 @eorv_v64i16(<64 x i16>* %a) #0 {
+; CHECK-LABEL: eorv_v64i16:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64
+; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: eorv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <64 x i16>, <64 x i16>* %a
+  %res = call i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16> %op)
+  ret i16 %res
+}
+
+define i16 @eorv_v128i16(<128 x i16>* %a) #0 {
+; CHECK-LABEL: eorv_v128i16:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128
+; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: eorv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
+; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <128 x i16>, <128 x i16>* %a
+  %res = call i16 @llvm.experimental.vector.reduce.xor.v128i16(<128 x i16> %op)
+  ret i16 %res
+}
+
+; No single instruction NEON EORV support. Use SVE.
+define i32 @eorv_v2i32(<2 x i32> %a) #0 {
+; CHECK-LABEL: eorv_v2i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl2
+; CHECK: eorv [[REDUCE:s[0-9]+]], [[PG]], z0.s
+; CHECK: fmov w0, [[REDUCE]]
+; CHECK: ret
+  %res = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> %a)
+  ret i32 %res
+}
+
+; No single instruction NEON EORV support. Use SVE.
+define i32 @eorv_v4i32(<4 x i32> %a) #0 {
+; CHECK-LABEL: eorv_v4i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl4
+; CHECK: eorv [[REDUCE:s[0-9]+]], [[PG]], z0.s
+; CHECK: fmov w0, [[REDUCE]]
+; CHECK: ret
+  %res = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %a)
+  ret i32 %res
+}
+
+define i32 @eorv_v8i32(<8 x i32>* %a) #0 {
+; CHECK-LABEL: eorv_v8i32:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].s, vl8
+; VBITS_GE_256-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: eorv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_256-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+  %op = load <8 x i32>, <8 x i32>* %a
+  %res = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> %op)
+  ret i32 %res
+}
+
+define i32 @eorv_v16i32(<16 x i32>* %a) #0 {
+; CHECK-LABEL: eorv_v16i32:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
+; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: eorv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_512-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1w { [[LO:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1w { [[HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: eor [[EOR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: eorv [[REDUCE:s[0-9]+]], [[PG]], [[EOR]].s
+; VBITS_EQ_256-NEXT: fmov w0, [[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <16 x i32>, <16 x i32>* %a
+  %res = call i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32> %op)
+  ret i32 %res
+}
+
+define i32 @eorv_v32i32(<32 x i32>* %a) #0 {
+; CHECK-LABEL: eorv_v32i32:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
+; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: eorv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_1024-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <32 x i32>, <32 x i32>* %a
+  %res = call i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32> %op)
+  ret i32 %res
+}
+
+define i32 @eorv_v64i32(<64 x i32>* %a) #0 {
+; CHECK-LABEL: eorv_v64i32:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
+; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: eorv [[REDUCE:s[0-9]+]], [[PG]], [[OP]].s
+; VBITS_GE_2048-NEXT: fmov w0, [[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <64 x i32>, <64 x i32>* %a
+  %res = call i32 @llvm.experimental.vector.reduce.xor.v64i32(<64 x i32> %op)
+  ret i32 %res
+}
+
+; Nothing to do for single element vectors.
+define i64 @eorv_v1i64(<1 x i64> %a) #0 {
+; CHECK-LABEL: eorv_v1i64:
+; CHECK: fmov x0, d0
+; CHECK: ret
+  %res = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> %a)
+  ret i64 %res
+}
+
+; Use SVE for 128-bit vectors
+define i64 @eorv_v2i64(<2 x i64> %a) #0 {
+; CHECK-LABEL: eorv_v2i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
+; CHECK: eorv [[REDUCE:d[0-9]+]], [[PG]], z0.d
+; CHECK: fmov x0, [[REDUCE]]
+; CHECK: ret
+  %res = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> %a)
+  ret i64 %res
+}
+
+define i64 @eorv_v4i64(<4 x i64>* %a) #0 {
+; CHECK-LABEL: eorv_v4i64:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].d, vl4
+; VBITS_GE_256-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: eorv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_256-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_256-NEXT: ret
+  %op = load <4 x i64>, <4 x i64>* %a
+  %res = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> %op)
+  ret i64 %res
+}
+
+define i64 @eorv_v8i64(<8 x i64>* %a) #0 {
+; CHECK-LABEL: eorv_v8i64:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
+; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: eorv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_512-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1d { [[LO:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1d { [[HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: eor [[EOR:z[0-9]+]].d, [[LO]].d, [[HI]].d
+; VBITS_EQ_256-DAG: eorv [[REDUCE:d[0-9]+]], [[PG]], [[EOR]].d
+; VBITS_EQ_256-NEXT: fmov x0, [[REDUCE]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <8 x i64>, <8 x i64>* %a
+  %res = call i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64> %op)
+  ret i64 %res
+}
+
+define i64 @eorv_v16i64(<16 x i64>* %a) #0 {
+; CHECK-LABEL: eorv_v16i64:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
+; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: eorv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_1024-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <16 x i64>, <16 x i64>* %a
+  %res = call i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64> %op)
+  ret i64 %res
+}
+
+define i64 @eorv_v32i64(<32 x i64>* %a) #0 {
+; CHECK-LABEL: eorv_v32i64:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
+; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: eorv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_2048-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <32 x i64>, <32 x i64>* %a
+  %res = call i64 @llvm.experimental.vector.reduce.xor.v32i64(<32 x i64> %op)
+  ret i64 %res
+}
+
 ;
 ; ORV
 ;
@@ -723,3 +1046,31 @@ declare i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64>)
 declare i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64>)
 declare i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64>)
 declare i64 @llvm.experimental.vector.reduce.or.v32i64(<32 x i64>)
+
+declare i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8>)
+declare i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8>)
+declare i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8>)
+declare i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8>)
+declare i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8>)
+declare i8 @llvm.experimental.vector.reduce.xor.v256i8(<256 x i8>)
+
+declare i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16>)
+declare i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16>)
+declare i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16>)
+declare i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16>)
+declare i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16>)
+declare i16 @llvm.experimental.vector.reduce.xor.v128i16(<128 x i16>)
+
+declare i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32>)
+declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
+declare i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32>)
+declare i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32>)
+declare i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32>)
+declare i32 @llvm.experimental.vector.reduce.xor.v64i32(<64 x i32>)
+
+declare i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64>)
+declare i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64>)
+declare i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64>)
+declare i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64>)
+declare i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64>)
+declare i64 @llvm.experimental.vector.reduce.xor.v32i64(<32 x i64>)
diff --git a/llvm/test/CodeGen/ARM/funnel-shift.ll b/llvm/test/CodeGen/ARM/funnel-shift.ll
index a8b6aff767a748..54c93b493c9817 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift.ll
@@ -19,13 +19,10 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define i16 @fshl_i16(i16 %x, i16 %y, i16 %z) {
 ; CHECK-LABEL: fshl_i16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r2, r2, #15
-; CHECK-NEXT:    mov r3, #31
-; CHECK-NEXT:    lsl r1, r1, #16
-; CHECK-NEXT:    bic r3, r3, r2
-; CHECK-NEXT:    lsl r0, r0, r2
-; CHECK-NEXT:    lsr r1, r1, #1
-; CHECK-NEXT:    orr r0, r0, r1, lsr r3
+; CHECK-NEXT:    pkhbt r0, r1, r0, lsl #16
+; CHECK-NEXT:    and r1, r2, #15
+; CHECK-NEXT:    lsl r0, r0, r1
+; CHECK-NEXT:    lsr r0, r0, #16
 ; CHECK-NEXT:    bx lr
   %f = call i16 @llvm.fshl.i16(i16 %x, i16 %y, i16 %z)
   ret i16 %f
@@ -188,15 +185,9 @@ define i8 @fshl_i8_const_fold() {
 define i16 @fshr_i16(i16 %x, i16 %y, i16 %z) {
 ; CHECK-LABEL: fshr_i16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r3, #1
-; CHECK-NEXT:    lsl r0, r0, #1
-; CHECK-NEXT:    bfi r2, r3, #4, #28
-; CHECK-NEXT:    mov r3, #31
-; CHECK-NEXT:    bic r3, r3, r2
-; CHECK-NEXT:    and r2, r2, #31
-; CHECK-NEXT:    lsl r1, r1, #16
-; CHECK-NEXT:    lsl r0, r0, r3
-; CHECK-NEXT:    orr r0, r0, r1, lsr r2
+; CHECK-NEXT:    pkhbt r0, r1, r0, lsl #16
+; CHECK-NEXT:    and r1, r2, #15
+; CHECK-NEXT:    lsr r0, r0, r1
 ; CHECK-NEXT:    bx lr
   %f = call i16 @llvm.fshr.i16(i16 %x, i16 %y, i16 %z)
   ret i16 %f
diff --git a/llvm/test/CodeGen/ARM/lsr-undef-in-binop.ll b/llvm/test/CodeGen/ARM/lsr-undef-in-binop.ll
index 564328d999982c..e7339721447580 100644
--- a/llvm/test/CodeGen/ARM/lsr-undef-in-binop.ll
+++ b/llvm/test/CodeGen/ARM/lsr-undef-in-binop.ll
@@ -186,7 +186,9 @@ define linkonce_odr i32 @vector_insert(%"class.std::__1::vector.182"*, [1 x i32]
   br i1 %114, label %124, label %115
 
 ; CHECK-LABEL: .preheader:
-; CHECK-NEXT: sub i32 [[OLD_CAST]], [[NEW_CAST]]
+; CHECK-NEXT: [[NEG_NEW:%[0-9]+]] = sub i32 0, [[NEW_CAST]]
+; CHECK-NEXT: getelementptr i8, i8* %97, i32 [[NEG_NEW]]
+
 ; <label>:115:                                    ; preds = %111, %115
   %116 = phi i8* [ %118, %115 ], [ %97, %111 ]
   %117 = phi i8* [ %119, %115 ], [ %11, %111 ]
diff --git a/llvm/test/CodeGen/Mips/funnel-shift.ll b/llvm/test/CodeGen/Mips/funnel-shift.ll
index 47d3db18c00370..99029b7b9410c7 100644
--- a/llvm/test/CodeGen/Mips/funnel-shift.ll
+++ b/llvm/test/CodeGen/Mips/funnel-shift.ll
@@ -19,15 +19,13 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define i16 @fshl_i16(i16 %x, i16 %y, i16 %z) {
 ; CHECK-LABEL: fshl_i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi $1, $6, 15
-; CHECK-NEXT:    sllv $2, $4, $1
-; CHECK-NEXT:    sll $3, $5, 16
-; CHECK-NEXT:    srl $3, $3, 1
-; CHECK-NEXT:    not $1, $1
-; CHECK-NEXT:    andi $1, $1, 31
-; CHECK-NEXT:    srlv $1, $3, $1
+; CHECK-NEXT:    andi $1, $5, 65535
+; CHECK-NEXT:    sll $2, $4, 16
+; CHECK-NEXT:    or $1, $2, $1
+; CHECK-NEXT:    andi $2, $6, 15
+; CHECK-NEXT:    sllv $1, $1, $2
 ; CHECK-NEXT:    jr $ra
-; CHECK-NEXT:    or $2, $2, $1
+; CHECK-NEXT:    srl $2, $1, 16
   %f = call i16 @llvm.fshl.i16(i16 %x, i16 %y, i16 %z)
   ret i16 %f
 }
@@ -288,15 +286,12 @@ define i8 @fshl_i8_const_fold() {
 define i16 @fshr_i16(i16 %x, i16 %y, i16 %z) {
 ; CHECK-LABEL: fshr_i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sll $1, $5, 16
+; CHECK-NEXT:    andi $1, $5, 65535
+; CHECK-NEXT:    sll $2, $4, 16
+; CHECK-NEXT:    or $1, $2, $1
 ; CHECK-NEXT:    andi $2, $6, 15
-; CHECK-NEXT:    ori $3, $2, 16
-; CHECK-NEXT:    srlv $1, $1, $3
-; CHECK-NEXT:    sll $3, $4, 1
-; CHECK-NEXT:    xori $2, $2, 15
-; CHECK-NEXT:    sllv $2, $3, $2
 ; CHECK-NEXT:    jr $ra
-; CHECK-NEXT:    or $2, $2, $1
+; CHECK-NEXT:    srlv $2, $1, $2
   %f = call i16 @llvm.fshr.i16(i16 %x, i16 %y, i16 %z)
   ret i16 %f
 }
diff --git a/llvm/test/CodeGen/RISCV/rv64Zbt.ll b/llvm/test/CodeGen/RISCV/rv64Zbt.ll
index 3e6201bac96794..dc736ade807179 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbt.ll
@@ -109,14 +109,13 @@ declare i32 @llvm.fshl.i32(i32, i32, i32)
 define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
 ; RV64I-LABEL: fshl_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a2, a2, 31
-; RV64I-NEXT:    sll a0, a0, a2
-; RV64I-NEXT:    not a2, a2
+; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 1
-; RV64I-NEXT:    srl a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    andi a1, a2, 31
+; RV64I-NEXT:    sll a0, a0, a1
+; RV64I-NEXT:    srai a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshl_i32:
@@ -162,14 +161,12 @@ declare i32 @llvm.fshr.i32(i32, i32, i32)
 define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
 ; RV64I-LABEL: fshr_i32:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    andi a2, a2, 31
-; RV64I-NEXT:    ori a3, a2, 32
-; RV64I-NEXT:    srl a1, a1, a3
-; RV64I-NEXT:    slli a0, a0, 1
-; RV64I-NEXT:    xori a2, a2, 31
-; RV64I-NEXT:    sll a0, a0, a2
+; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    andi a1, a2, 31
+; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/VE/brcond.ll b/llvm/test/CodeGen/VE/brcond.ll
new file mode 100644
index 00000000000000..515b6878c3edf3
--- /dev/null
+++ b/llvm/test/CodeGen/VE/brcond.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+; Function Attrs: nounwind
+define void @test_then(i1 zeroext %0) {
+; CHECK-LABEL: test_then:
+; CHECK:       .LBB{{[0-9]+}}_4:
+; CHECK-NEXT:    breq.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s11, 0, %s9
+  br i1 %0, label %2, label %3
+
+2:                                                ; preds = %1
+  tail call void asm sideeffect "nop", ""()
+  br label %3
+
+3:                                                ; preds = %2, %1
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @test_else(i1 zeroext %0) {
+; CHECK-LABEL: test_else:
+; CHECK:       .LBB{{[0-9]+}}_4:
+; CHECK-NEXT:    brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s11, 0, %s9
+  br i1 %0, label %3, label %2
+
+2:                                                ; preds = %1
+  tail call void asm sideeffect "nop", ""()
+  br label %3
+
+3:                                                ; preds = %2, %1
+  ret void
+}
diff --git a/llvm/test/CodeGen/VE/fp_copysign.ll b/llvm/test/CodeGen/VE/fp_copysign.ll
new file mode 100644
index 00000000000000..677e2b96abb420
--- /dev/null
+++ b/llvm/test/CodeGen/VE/fp_copysign.ll
@@ -0,0 +1,195 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+;;; Test ‘llvm.copysign.*’ Intrinsic
+;;;
+;;; Syntax:
+;;;   This is an overloaded intrinsic. You can use llvm.copysign on any
+;;;   floating-point or vector of floating-point type. Not all targets
+;;;   support all types however.
+;;;
+;;; declare float     @llvm.copysign.f32(float  %Mag, float  %Sgn)
+;;; declare double    @llvm.copysign.f64(double %Mag, double %Sgn)
+;;; declare x86_fp80  @llvm.copysign.f80(x86_fp80  %Mag, x86_fp80  %Sgn)
+;;; declare fp128     @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
+;;; declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128  %Mag, ppc_fp128  %Sgn)
+;;;
+;;; Overview:
+;;;   The ‘llvm.copysign.*’ intrinsics return a value with the magnitude of
+;;;   the first operand and the sign of the second operand.
+;;;
+;;; Arguments:
+;;;   The arguments and return value are floating-point numbers of the same
+;;;   type.
+;;;
+;;; Semantics:
+;;;   This function returns the same values as the libm copysign functions
+;;;   would, and handles error conditions in the same way.
+;;;
+;;; Note:
+;;;   We test only float/double/fp128.
+
+; Function Attrs: nounwind readnone
+define float @copysign_float_var(float %0, float %1) {
+; CHECK-LABEL: copysign_float_var:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    sra.l %s1, %s1, 32
+; CHECK-NEXT:    lea %s2, -2147483648
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    and %s1, %s1, %s2
+; CHECK-NEXT:    sra.l %s0, %s0, 32
+; CHECK-NEXT:    and %s0, %s0, (33)0
+; CHECK-NEXT:    or %s0, %s0, %s1
+; CHECK-NEXT:    sll %s0, %s0, 32
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = tail call float @llvm.copysign.f32(float %0, float %1)
+  ret float %3
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare float @llvm.copysign.f32(float, float)
+
+; Function Attrs: nounwind readnone
+define double @copysign_double_var(double %0, double %1) {
+; CHECK-LABEL: copysign_double_var:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    and %s1, %s1, (1)1
+; CHECK-NEXT:    and %s0, %s0, (1)0
+; CHECK-NEXT:    or %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = tail call double @llvm.copysign.f64(double %0, double %1)
+  ret double %3
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare double @llvm.copysign.f64(double, double)
+
+; Function Attrs: nounwind readnone
+define fp128 @copysign_quad_var(fp128 %0, fp128 %1) {
+; CHECK-LABEL: copysign_quad_var:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    st %s3, 192(, %s11)
+; CHECK-NEXT:    st %s2, 200(, %s11)
+; CHECK-NEXT:    st %s1, 176(, %s11)
+; CHECK-NEXT:    st %s0, 184(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 207(, %s11)
+; CHECK-NEXT:    ld1b.zx %s1, 191(, %s11)
+; CHECK-NEXT:    lea %s2, 128
+; CHECK-NEXT:    and %s0, %s0, %s2
+; CHECK-NEXT:    and %s1, %s1, (57)0
+; CHECK-NEXT:    or %s0, %s1, %s0
+; CHECK-NEXT:    st1b %s0, 191(, %s11)
+; CHECK-NEXT:    ld %s1, 176(, %s11)
+; CHECK-NEXT:    ld %s0, 184(, %s11)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = tail call fp128 @llvm.copysign.f128(fp128 %0, fp128 %1)
+  ret fp128 %3
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare fp128 @llvm.copysign.f128(fp128, fp128)
+
+; Function Attrs: nounwind readnone
+define float @copysign_float_zero(float %0) {
+; CHECK-LABEL: copysign_float_zero:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    sra.l %s0, %s0, 32
+; CHECK-NEXT:    lea %s1, -2147483648
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    and %s0, %s0, %s1
+; CHECK-NEXT:    sll %s0, %s0, 32
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = tail call float @llvm.copysign.f32(float 0.000000e+00, float %0)
+  ret float %2
+}
+
+; Function Attrs: nounwind readnone
+define double @copysign_double_zero(double %0) {
+; CHECK-LABEL: copysign_double_zero:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    and %s0, %s0, (1)1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = tail call double @llvm.copysign.f64(double 0.000000e+00, double %0)
+  ret double %2
+}
+
+; Function Attrs: nounwind readnone
+define fp128 @copysign_quad_zero(fp128 %0) {
+; CHECK-LABEL: copysign_quad_zero:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, .LCPI{{[0-9]+}}_0@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
+; CHECK-NEXT:    ld %s4, 8(, %s2)
+; CHECK-NEXT:    ld %s5, (, %s2)
+; CHECK-NEXT:    st %s1, 192(, %s11)
+; CHECK-NEXT:    st %s0, 200(, %s11)
+; CHECK-NEXT:    st %s5, 176(, %s11)
+; CHECK-NEXT:    st %s4, 184(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 207(, %s11)
+; CHECK-NEXT:    ld1b.zx %s1, 191(, %s11)
+; CHECK-NEXT:    lea %s2, 128
+; CHECK-NEXT:    and %s0, %s0, %s2
+; CHECK-NEXT:    and %s1, %s1, (57)0
+; CHECK-NEXT:    or %s0, %s1, %s0
+; CHECK-NEXT:    st1b %s0, 191(, %s11)
+; CHECK-NEXT:    ld %s1, 176(, %s11)
+; CHECK-NEXT:    ld %s0, 184(, %s11)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = tail call fp128 @llvm.copysign.f128(fp128 0xL00000000000000000000000000000000, fp128 %0)
+  ret fp128 %2
+}
+
+; Function Attrs: nounwind readnone
+define float @copysign_float_const(float %0) {
+; CHECK-LABEL: copysign_float_const:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    sra.l %s0, %s0, 32
+; CHECK-NEXT:    lea %s1, -2147483648
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    and %s0, %s0, %s1
+; CHECK-NEXT:    lea %s1, 1073741824
+; CHECK-NEXT:    or %s0, %s0, %s1
+; CHECK-NEXT:    sll %s0, %s0, 32
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = tail call float @llvm.copysign.f32(float -2.000000e+00, float %0)
+  ret float %2
+}
+
+; Function Attrs: nounwind readnone
+define double @copysign_double_const(double %0) {
+; CHECK-LABEL: copysign_double_const:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    and %s0, %s0, (1)1
+; CHECK-NEXT:    lea.sl %s1, 1073741824
+; CHECK-NEXT:    or %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = tail call double @llvm.copysign.f64(double -2.000000e+00, double %0)
+  ret double %2
+}
+
+; Function Attrs: nounwind readnone
+define fp128 @copysign_quad_const(fp128 %0) {
+; CHECK-LABEL: copysign_quad_const:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, .LCPI{{[0-9]+}}_0@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
+; CHECK-NEXT:    ld %s4, 8(, %s2)
+; CHECK-NEXT:    ld %s5, (, %s2)
+; CHECK-NEXT:    st %s1, 192(, %s11)
+; CHECK-NEXT:    st %s0, 200(, %s11)
+; CHECK-NEXT:    st %s5, 176(, %s11)
+; CHECK-NEXT:    st %s4, 184(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 207(, %s11)
+; CHECK-NEXT:    ld1b.zx %s1, 191(, %s11)
+; CHECK-NEXT:    lea %s2, 128
+; CHECK-NEXT:    and %s0, %s0, %s2
+; CHECK-NEXT:    and %s1, %s1, (57)0
+; CHECK-NEXT:    or %s0, %s1, %s0
+; CHECK-NEXT:    st1b %s0, 191(, %s11)
+; CHECK-NEXT:    ld %s1, 176(, %s11)
+; CHECK-NEXT:    ld %s0, 184(, %s11)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = tail call fp128 @llvm.copysign.f128(fp128 0xL0000000000000000C000000000000000, fp128 %0)
+  ret fp128 %2
+}
diff --git a/llvm/test/CodeGen/VE/fp_fneg.ll b/llvm/test/CodeGen/VE/fp_fneg.ll
new file mode 100644
index 00000000000000..8ebec6b9500fa4
--- /dev/null
+++ b/llvm/test/CodeGen/VE/fp_fneg.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+;;; Test ‘fneg’ Instruction
+;;;
+;;; Syntax:
+;;;   <result> = fneg [fast-math flags]* <ty> <op1>   ; yields ty:result
+;;;
+;;; Overview:
+;;;    The ‘fneg’ instruction returns the negation of its operand.
+;;;
+;;; Arguments:
+;;;   The argument to the ‘fneg’ instruction must be a floating-point or
+;;;   vector of floating-point values.
+;;;
+;;; Semantics:
+;;;
+;;;   The value produced is a copy of the operand with its sign bit flipped.
+;;;   This instruction can also take any number of fast-math flags, which are
+;;;   optimization hints to enable otherwise unsafe floating-point
+;;;   optimizations.
+;;;
+;;; Example:
+;;;   <result> = fneg float %val          ; yields float:result = -%var
+;;;
+;;; Note:
+;;;   We test only float/double/fp128.
+
+; Function Attrs: norecurse nounwind readnone
+define float @fneg_float(float %0) {
+; CHECK-LABEL: fneg_float:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    sra.l %s0, %s0, 32
+; CHECK-NEXT:    lea %s1, -2147483648
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    xor %s0, %s0, %s1
+; CHECK-NEXT:    sll %s0, %s0, 32
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = fneg float %0
+  ret float %2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define double @fneg_double(double %0) {
+; CHECK-LABEL: fneg_double:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    xor %s0, %s0, (1)1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = fneg double %0
+  ret double %2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define fp128 @fneg_quad(fp128 %0) {
+; CHECK-LABEL: fneg_quad:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    st %s1, 176(, %s11)
+; CHECK-NEXT:    st %s0, 184(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
+; CHECK-NEXT:    lea %s1, 128
+; CHECK-NEXT:    xor %s0, %s0, %s1
+; CHECK-NEXT:    st1b %s0, 191(, %s11)
+; CHECK-NEXT:    ld %s1, 176(, %s11)
+; CHECK-NEXT:    ld %s0, 184(, %s11)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = fneg fp128 %0
+  ret fp128 %2
+}
diff --git a/llvm/test/CodeGen/VE/fp_frem.ll b/llvm/test/CodeGen/VE/fp_frem.ll
new file mode 100644
index 00000000000000..3906c67dc333df
--- /dev/null
+++ b/llvm/test/CodeGen/VE/fp_frem.ll
@@ -0,0 +1,171 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+;;; Test ‘frem’ Instruction
+;;;
+;;; Syntax:
+;;;   <result> = frem [fast-math flags]* <ty> <op1>, <op2> ; yields ty:result
+;;;
+;;; Overview:
+;;;   The ‘frem’ instruction returns the remainder from the division of its two
+;;;   operands.
+;;;
+;;; Arguments:
+;;;   The two arguments to the ‘frem’ instruction must be floating-point or
+;;;   vector of floating-point values. Both arguments must have identical types.
+;;;
+;;; Semantics:
+;;;   The value produced is the floating-point remainder of the two operands.
+;;;   This is the same output as a libm ‘fmod’ function, but without any
+;;;   possibility of setting errno. The remainder has the same sign as the
+;;;   dividend. This instruction is assumed to execute in the default
+;;;   floating-point environment. This instruction can also take any number
+;;;   of fast-math flags, which are optimization hints to enable otherwise
+;;;   unsafe floating-point optimizations:
+;;;
+;;; Example:
+;;;
+;;;   <result> = frem float 4.0, %var ; yields float:result = 4.0 % %var
+;;;
+;;; Note:
+;;;   We test only float/double/fp128.
+;;;   We have no way to generated frem from C source code, so convert fdiv
+;;;   to frem by using sed program.
+
+; Function Attrs: norecurse nounwind readnone
+define float @frem_float_var(float %0, float %1) {
+; CHECK-LABEL: frem_float_var:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, fmodf@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s2)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = frem float %0, %1
+  ret float %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define double @frem_double_var(double %0, double %1) {
+; CHECK-LABEL: frem_double_var:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, fmod@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmod@hi(, %s2)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = frem double %0, %1
+  ret double %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define fp128 @frem_quad_var(fp128 %0, fp128 %1) {
+; CHECK-LABEL: frem_quad_var:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s4, fmodl@lo
+; CHECK-NEXT:    and %s4, %s4, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodl@hi(, %s4)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = frem fp128 %0, %1
+  ret fp128 %3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define float @frem_float_zero(float %0) {
+; CHECK-LABEL: frem_float_zero:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea.sl %s0, 0
+; CHECK-NEXT:    lea %s2, fmodf@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s2)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = frem float 0.000000e+00, %0
+  ret float %2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define double @frem_double_zero(double %0) {
+; CHECK-LABEL: frem_double_zero:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea %s0, fmod@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmod@hi(, %s0)
+; CHECK-NEXT:    lea.sl %s0, 0
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = frem double 0.000000e+00, %0
+  ret double %2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define fp128 @frem_quad_zero(fp128 %0) {
+; CHECK-LABEL: frem_quad_zero:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s2, 0, %s0
+; CHECK-NEXT:    or %s3, 0, %s1
+; CHECK-NEXT:    lea %s0, .LCPI{{[0-9]+}}_0@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s4, .LCPI{{[0-9]+}}_0@hi(, %s0)
+; CHECK-NEXT:    ld %s0, 8(, %s4)
+; CHECK-NEXT:    ld %s1, (, %s4)
+; CHECK-NEXT:    lea %s4, fmodl@lo
+; CHECK-NEXT:    and %s4, %s4, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodl@hi(, %s4)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = frem fp128 0xL00000000000000000000000000000000, %0
+  ret fp128 %2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define float @frem_float_cont(float %0) {
+; CHECK-LABEL: frem_float_cont:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea.sl %s0, -1073741824
+; CHECK-NEXT:    lea %s2, fmodf@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s2)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = frem float -2.000000e+00, %0
+  ret float %2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define double @frem_double_cont(double %0) {
+; CHECK-LABEL: frem_double_cont:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea %s0, fmod@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmod@hi(, %s0)
+; CHECK-NEXT:    lea.sl %s0, -1073741824
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = frem double -2.000000e+00, %0
+  ret double %2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define fp128 @frem_quad_cont(fp128 %0) {
+; CHECK-LABEL: frem_quad_cont:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s2, 0, %s0
+; CHECK-NEXT:    or %s3, 0, %s1
+; CHECK-NEXT:    lea %s0, .LCPI{{[0-9]+}}_0@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s4, .LCPI{{[0-9]+}}_0@hi(, %s0)
+; CHECK-NEXT:    ld %s0, 8(, %s4)
+; CHECK-NEXT:    ld %s1, (, %s4)
+; CHECK-NEXT:    lea %s4, fmodl@lo
+; CHECK-NEXT:    and %s4, %s4, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodl@hi(, %s4)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = frem fp128 0xL0000000000000000C000000000000000, %0
+  ret fp128 %2
+}
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 670477c4c28514..d4dd7352aa5261 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -268,9 +268,9 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:  LBB0_48: ## %if.then1477
 ; CHECK-NEXT:    movl $1, %edx
 ; CHECK-NEXT:    callq _write
-; CHECK-NEXT:    subq %rbx, %r14
 ; CHECK-NEXT:    movq _syHistory@{{.*}}(%rip), %rax
-; CHECK-NEXT:    leaq 8189(%r14,%rax), %rax
+; CHECK-NEXT:    subq %rbx, %rax
+; CHECK-NEXT:    leaq 8189(%rax,%r14), %rax
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_49: ## %for.body1723
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported.s b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
index 34a9d4686e204a..425bd27e625115 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
@@ -6,1097 +6,1097 @@
 //===----------------------------------------------------------------------===//
 
 buffer_atomic_add_f32 v255, off, s[8:11], s3 offset:4095
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 buffer_atomic_pk_add_f16 v255, off, s[8:11], s3 offset:4095
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 buffer_store_lds_dword s[4:7], s0 lds
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 buffer_wbinvl1_vol
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 global_atomic_add_f32 v[1:2], v2, off
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 global_atomic_pk_add_f16 v[1:2], v2, off
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_cbranch_g_fork -1, s[4:5]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_cbranch_i_fork exec, 12609
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_cbranch_join 1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_dcache_inv_vol
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_dcache_wb_vol
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_rfe_restore_b64 -1, s2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_set_gpr_idx_idx -1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_set_gpr_idx_mode 0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_set_gpr_idx_off
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_set_gpr_idx_on -1, 0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_setvskip -1, s2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_accvgpr_read_b32 a0, a0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_accvgpr_write_b32 a0, 65
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_i16 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_i32 lds_direct, v0, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_i32_e32 v0, vcc, 0.5, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_i32_e64 v1, s[0:1], v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u16 v0, (i1+100)*2, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u16_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u16_sdwa v0, scc, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u32 v0, execz, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u32_e32 v1, s1, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u32_e64 v0, scc, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_add_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_co_u32 v0, vcc, shared_base, v0, vcc
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_co_u32_e32 v3, vcc, 12345, v3, vcc
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_u32 v0, vcc, exec_hi, v0, vcc
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_u32_e32 v1, -1, v2, v3, s0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_u32_e64 v0, s[0:1], s0, s0, s[0:1]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_addc_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_ashr_i32 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_ashr_i32_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_ashr_i64 v[254:255], v[1:2], v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_f_i16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_f_i16_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_f_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_f_u16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_f_u16_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_f_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_t_i16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_t_i16_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_t_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_t_u16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_t_u16_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmp_t_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_eq_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_eq_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_f_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_f_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_f_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ge_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ge_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_gt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_gt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_le_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_le_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_le_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lg_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lg_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_neq_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_neq_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nge_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nge_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ngt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ngt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nle_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nle_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlg_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlg_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_o_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_o_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_o_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_tru_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_tru_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_u_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_u_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_u_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmps_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_eq_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_eq_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_f_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_f_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_f_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ge_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ge_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_gt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_gt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_le_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_le_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_le_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lg_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lg_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_neq_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_neq_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nge_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nge_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ngt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ngt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nle_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nle_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlg_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlg_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlt_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlt_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_o_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_o_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_o_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_tru_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_tru_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_u_f32 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_u_f32_e64 flat_scratch, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_u_f64 vcc, -1, v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpsx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_f_i16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_f_i16_e64 exec, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_f_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_f_u16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_f_u16_e64 exec, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_f_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_t_i16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_t_i16_e64 exec, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_t_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_t_u16 vcc, -1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_t_u16_e64 exec, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cmpx_t_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cvt_pkaccum_u8_f32 v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_cvt_pkaccum_u8_f32_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_div_fixup_legacy_f16 v255, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_div_fixup_legacy_f16_e64 v5, 0.5, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2_f32_f16 v0, -v1, -v2, -v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2_i32_i16 v0, -v1, -v2, -v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2_u32_u16 v0, -v1, -v2, -v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2c_f32_f16 v0, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2c_f32_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2c_f32_f16_e32 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2c_i32_i16 v0, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot2c_i32_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot4_i32_i8 v0, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot4_u32_u8 v0, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot4c_i32_i8 v0, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot4c_i32_i8_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot4c_i32_i8_e32 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot8_i32_i4 v0, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot8_u32_u4 v0, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot8c_i32_i4 v0, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_dot8c_i32_i4_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_exp_legacy_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_exp_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_exp_legacy_f32_e64 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_exp_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_fma_legacy_f16 v255, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_fma_legacy_f16_e64 v5, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_interp_p2_legacy_f16 v255, v2, attr0.x, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_log_clamp_f32 v1, 0.5
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_log_clamp_f32_e64 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_log_legacy_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_log_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_log_legacy_f32_e64 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_log_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_lshl_b32 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_lshl_b32_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_lshl_b64 v[254:255], v[1:2], v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_lshr_b32 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_lshr_b32_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_lshr_b64 v[254:255], v[1:2], v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mac_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mac_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mac_f16_e64 v0, -4.0, flat_scratch_lo
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mac_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_f16 v255, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_f16_e64 v5, 0.5, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_legacy_f16 v255, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_legacy_f16_e64 v5, 0.5, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_legacy_i16 v255, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_legacy_i16_e64 v5, 0, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_legacy_u16 v255, v1, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_legacy_u16_e64 v5, 0, v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_mix_f32 v0, -abs(v1), v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_madak_f16 v0, src_lds_direct, v0, 0x1121
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_madmk_f16 v0, src_lds_direct, 0x1121, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_max_legacy_f32 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_max_legacy_f32_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_16x16x16f16 a[0:3], a[0:1], a[1:2], -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_16x16x1f32 a[0:15], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_16x16x2bf16 a[0:15], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_16x16x4f16 a[0:15], a[0:1], a[1:2], -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_16x16x4f32 a[0:3], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_16x16x8bf16 a[0:3], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_32x32x1f32 a[0:31], 1, v1, a[1:32]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_32x32x2bf16 a[0:31], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_32x32x2f32 a[0:15], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_32x32x4bf16 a[0:15], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_32x32x4f16 a[0:31], a[0:1], a[1:2], -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_32x32x8f16 a[0:15], a[0:1], a[1:2], -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_4x4x1f32 a[0:3], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_4x4x2bf16 a[0:3], a0, a1, -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_f32_4x4x4f16 a[0:3], a[0:1], a[1:2], -2.0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_i32_16x16x16i8 a[0:3], a0, a1, 2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_i32_16x16x4i8 a[0:15], a0, a1, 2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_i32_32x32x4i8 a[0:31], a0, a1, 2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_i32_32x32x8i8 a[0:15], a0, a1, 2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_mfma_i32_4x4x4i8 a[0:3], a0, a1, 2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_min_legacy_f32 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_min_legacy_f32_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_clamp_f32 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_clamp_f32_e64 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_clamp_f64 v[254:255], v[1:2]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_clamp_f64_e64 v[254:255], v[1:2]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_legacy_f32 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_legacy_f32_e64 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rsq_clamp_f32 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rsq_clamp_f32_e64 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rsq_clamp_f64 v[254:255], v[1:2]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rsq_clamp_f64_e64 v[254:255], v[1:2]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rsq_legacy_f32 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rsq_legacy_f32_e64 v255, v1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_screen_partition_4se_b32 v5, -1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_screen_partition_4se_b32_e64 v5, -1
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_screen_partition_4se_b32_sdwa v5, v1 src0_sel:BYTE_0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_i16 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_i32 v1, s[0:1], v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_i32_e64 v255, s[12:13], v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u16_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u32 v1, 4.0, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u32_e32 v1, s1, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u32_e64 v255, s[12:13], v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_sub_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_co_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_u32 v1, s[0:1], v2, v3, vcc
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subb_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_co_u32 v0, vcc, src_lds_direct, v0, vcc
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_u32 v1, s[0:1], v2, v3, vcc
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subbrev_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_i32 v1, s[0:1], v2, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_i32_e64 v255, s[12:13], v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u16 v0, src_lds_direct, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u16_e64 v255, v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u32 v0, src_lds_direct, v0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u32_e32 v1, s1, v3
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u32_e64 v255, s[12:13], v1, v2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_subrev_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
-// CHECK: error: instruction not supported on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 //===----------------------------------------------------------------------===//
 // Unsupported e32 variants.
 //===----------------------------------------------------------------------===//
 
 v_add_co_u32_e32 v2, vcc, s0, v2
-// CHECK: error: e32 variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
 
 v_sub_co_u32_e32 v2, vcc, s0, v2
-// CHECK: error: e32 variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
 
 v_subrev_co_u32_e32 v2, vcc, s0, v2
-// CHECK: error: e32 variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
 
 //===----------------------------------------------------------------------===//
 // Unsupported e64 variants.
 //===----------------------------------------------------------------------===//
 
 v_swap_b32_e64 v1, v2
-// CHECK: error: e64 variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e64 variant of this instruction is not supported
 
 //===----------------------------------------------------------------------===//
 // Unsupported dpp variants.
 //===----------------------------------------------------------------------===//
 
 v_add_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_ashrrev_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_lshlrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_lshrrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_max_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_max_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_min_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_min_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_mul_lo_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_sub_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 v_subrev_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: error: dpp variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 //===----------------------------------------------------------------------===//
 // Unsupported sdwa variants.
 //===----------------------------------------------------------------------===//
 
 v_add_co_u32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_mac_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_max_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_sub_co_u32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
 
 v_subrev_co_u32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: error: sdwa variant of this instruction is not supported
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
diff --git a/llvm/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll b/llvm/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
index e1ef6bd6635d1f..bc756c666bde5f 100644
--- a/llvm/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
+++ b/llvm/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
@@ -166,21 +166,23 @@ define i8 @testnullptrint(i8* %buf, i8* %end) nounwind {
 ; PTR64-NEXT:    ret i8 [[RET]]
 ;
 ; PTR32-LABEL: @testnullptrint(
+; PTR32-NEXT:    [[BUF1:%.*]] = ptrtoint i8* [[BUF:%.*]] to i32
 ; PTR32-NEXT:    br label [[LOOPGUARD:%.*]]
 ; PTR32:       loopguard:
-; PTR32-NEXT:    [[BI:%.*]] = ptrtoint i8* [[BUF:%.*]] to i32
+; PTR32-NEXT:    [[BI:%.*]] = ptrtoint i8* [[BUF]] to i32
 ; PTR32-NEXT:    [[EI:%.*]] = ptrtoint i8* [[END:%.*]] to i32
 ; PTR32-NEXT:    [[CNT:%.*]] = sub i32 [[EI]], [[BI]]
-; PTR32-NEXT:    [[CNT1:%.*]] = inttoptr i32 [[CNT]] to i8*
 ; PTR32-NEXT:    [[GUARD:%.*]] = icmp ult i32 0, [[CNT]]
 ; PTR32-NEXT:    br i1 [[GUARD]], label [[PREHEADER:%.*]], label [[EXIT:%.*]]
 ; PTR32:       preheader:
+; PTR32-NEXT:    [[TMP1:%.*]] = sub i32 0, [[BUF1]]
+; PTR32-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, i8* [[END]], i32 [[TMP1]]
 ; PTR32-NEXT:    br label [[LOOP:%.*]]
 ; PTR32:       loop:
 ; PTR32-NEXT:    [[P_01_US_US:%.*]] = phi i8* [ null, [[PREHEADER]] ], [ [[GEP:%.*]], [[LOOP]] ]
 ; PTR32-NEXT:    [[GEP]] = getelementptr inbounds i8, i8* [[P_01_US_US]], i64 1
-; PTR32-NEXT:    [[SNEXT:%.*]] = load i8, i8* [[GEP]]
-; PTR32-NEXT:    [[EXITCOND:%.*]] = icmp ne i8* [[GEP]], [[CNT1]]
+; PTR32-NEXT:    [[SNEXT:%.*]] = load i8, i8* [[GEP]], align 1
+; PTR32-NEXT:    [[EXITCOND:%.*]] = icmp ne i8* [[GEP]], [[SCEVGEP]]
 ; PTR32-NEXT:    br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT_LOOPEXIT:%.*]]
 ; PTR32:       exit.loopexit:
 ; PTR32-NEXT:    [[SNEXT_LCSSA:%.*]] = phi i8 [ [[SNEXT]], [[LOOP]] ]
@@ -256,10 +258,10 @@ define i8 @testptrint(i8* %buf, i8* %end) nounwind {
 ; PTR32-NEXT:    [[P_01_US_US:%.*]] = phi i8* [ [[BUF]], [[PREHEADER]] ], [ [[GEP:%.*]], [[LOOP]] ]
 ; PTR32-NEXT:    [[IV:%.*]] = phi i32 [ [[BI]], [[PREHEADER]] ], [ [[IVNEXT:%.*]], [[LOOP]] ]
 ; PTR32-NEXT:    [[GEP]] = getelementptr inbounds i8, i8* [[P_01_US_US]], i64 1
-; PTR32-NEXT:    [[SNEXT:%.*]] = load i8, i8* [[GEP]]
+; PTR32-NEXT:    [[SNEXT:%.*]] = load i8, i8* [[GEP]], align 1
 ; PTR32-NEXT:    [[IVNEXT]] = add nuw i32 [[IV]], 1
-; PTR32-NEXT:    [[EXITCOND:%.*]] = icmp ne i32 [[IVNEXT]], [[CNT]]
-; PTR32-NEXT:    br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT_LOOPEXIT:%.*]]
+; PTR32-NEXT:    [[CMP:%.*]] = icmp ult i32 [[IVNEXT]], [[CNT]]
+; PTR32-NEXT:    br i1 [[CMP]], label [[LOOP]], label [[EXIT_LOOPEXIT:%.*]]
 ; PTR32:       exit.loopexit:
 ; PTR32-NEXT:    [[SNEXT_LCSSA:%.*]] = phi i8 [ [[SNEXT]], [[LOOP]] ]
 ; PTR32-NEXT:    br label [[EXIT]]
diff --git a/llvm/test/Transforms/InstCombine/funnel.ll b/llvm/test/Transforms/InstCombine/funnel.ll
index 291a597546d3f8..7277681a108819 100644
--- a/llvm/test/Transforms/InstCombine/funnel.ll
+++ b/llvm/test/Transforms/InstCombine/funnel.ll
@@ -183,7 +183,7 @@ define i64 @fshl_sub_mask(i64 %x, i64 %y, i64 %a) {
 
 define i64 @fshr_sub_mask(i64 %x, i64 %y, i64 %a) {
 ; CHECK-LABEL: @fshr_sub_mask(
-; CHECK-NEXT:    [[R:%.*]] = call i64 @llvm.fshr.i64(i64 [[X:%.*]], i64 [[Y:%.*]], i64 [[A:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = call i64 @llvm.fshr.i64(i64 [[Y:%.*]], i64 [[X:%.*]], i64 [[A:%.*]])
 ; CHECK-NEXT:    ret i64 [[R]]
 ;
   %mask = and i64 %a, 63
@@ -196,7 +196,7 @@ define i64 @fshr_sub_mask(i64 %x, i64 %y, i64 %a) {
 
 define <2 x i64> @fshr_sub_mask_vector(<2 x i64> %x, <2 x i64> %y, <2 x i64> %a) {
 ; CHECK-LABEL: @fshr_sub_mask_vector(
-; CHECK-NEXT:    [[R:%.*]] = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> [[Y:%.*]], <2 x i64> [[X:%.*]], <2 x i64> [[A:%.*]])
 ; CHECK-NEXT:    ret <2 x i64> [[R]]
 ;
   %mask = and <2 x i64> %a, <i64 63, i64 63>
diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
new file mode 100644
index 00000000000000..1ccb1889a6fb63
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
@@ -0,0 +1,2572 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=armv8 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s
+
+  .text
+  adc	r1, r2, #15
+  adc	r1, r2, #240
+  adc	r1, r2, #3840
+  adc	r1, r2, #61440
+  adc	r1, r2, #983040
+  adc	r1, r2, #15728640
+  adc	r1, r2, #251658240
+  adc	r1, r2, #-268435456
+  adc	r1, r2, #-268435441
+  adc	r7, r8, #-2147483638
+  adc	r7, r8, #40, #2
+  adcs	r1, r2, #3840
+  adcs	r7, r8, #40, #2
+  adcseq	r1, r2, #3840
+  adceq	r1, r2, #3840
+  adc	r4, r5, r6
+  adc	r4, r5, r6, lsl #1
+  adc	r4, r5, r6, lsl #31
+  adc	r4, r5, r6, lsr #1
+  adc	r4, r5, r6, lsr #31
+  adc	r4, r5, r6, lsr #32
+  adc	r4, r5, r6, asr #1
+  adc	r4, r5, r6, asr #31
+  adc	r4, r5, r6, asr #32
+  adc	r4, r5, r6, ror #1
+  adc	r4, r5, r6, ror #31
+  adc	r6, r7, r8, lsl r9
+  adc	r6, r7, r8, lsr r9
+  adc	r6, r7, r8, asr r9
+  adc	r6, r7, r8, ror r9
+  adc	r4, r5, r6, rrx
+  adc	r5, r5, r6
+  adc	r4, r4, r5, lsl #1
+  adc	r4, r4, r5, lsl #31
+  adc	r4, r4, r5, lsr #1
+  adc	r4, r4, r5, lsr #31
+  adc	r4, r4, r5, lsr #32
+  adc	r4, r4, r5, asr #1
+  adc	r4, r4, r5, asr #31
+  adc	r4, r4, r5, asr #32
+  adc	r4, r4, r5, ror #1
+  adc	r4, r4, r5, ror #31
+  adc	r4, r4, r5, rrx
+  adc	r6, r6, r7, lsl r9
+  adc	r6, r6, r7, lsr r9
+  adc	r6, r6, r7, asr r9
+  adc	r6, r6, r7, ror r9
+  adc	r4, r4, r5, rrx
+  add	r4, r5, #61440
+  add	r7, r8, #-2147483638
+  add	r7, r8, #40, #2
+  add	r4, r5, r6
+  add	r4, r5, r6, lsl #5
+  add	r4, r5, r6, lsr #5
+  add	r4, r5, r6, lsr #5
+  add	r4, r5, r6, asr #5
+  add	r4, r5, r6, ror #5
+  add	r6, r7, r8, lsl r9
+  add	r6, r7, r8, lsr r9
+  add	r6, r7, r8, asr r9
+  add	r6, r7, r8, ror r9
+  add	r4, r5, r6, rrx
+  add	r5, r5, #61440
+  add	r4, r4, r5
+  add	r4, r4, r5, lsl #5
+  add	r4, r4, r5, lsr #5
+  add	r4, r4, r5, lsr #5
+  add	r4, r4, r5, asr #5
+  add	r4, r4, r5, ror #5
+  add	r6, r6, r7, lsl r9
+  add	r6, r6, r7, lsr r9
+  add	r6, r6, r7, asr r9
+  add	r6, r6, r7, ror r9
+  add	r4, r4, r5, rrx
+  adds	r7, r8, #-2147483638
+  adds	r7, r8, #40, #2
+  add	r2, pc, #3
+  sub	r2, pc, #3
+  sub	r1, pc, #0
+  sub	r1, pc, #301989888
+  add	r1, pc, #301989888
+  and	r10, r1, #15
+  and	r7, r8, #-2147483638
+  and	r7, r8, #40, #2
+  and	r10, r1, r6
+  and	r10, r1, r6, lsl #10
+  and	r10, r1, r6, lsr #10
+  and	r10, r1, r6, lsr #10
+  and	r10, r1, r6, asr #10
+  and	r10, r1, r6, ror #10
+  and	r6, r7, r8, lsl r2
+  and	r6, r7, r8, lsr r2
+  and	r6, r7, r8, asr r2
+  and	r6, r7, r8, ror r2
+  and	r10, r1, r6, rrx
+  and	r1, r1, #15
+  and	r10, r10, r1
+  and	r10, r10, r1, lsl #10
+  and	r10, r10, r1, lsr #10
+  and	r10, r10, r1, lsr #10
+  and	r10, r10, r1, asr #10
+  and	r10, r10, r1, ror #10
+  and	r6, r6, r7, lsl r2
+  and	r6, r6, r7, lsr r2
+  and	r6, r6, r7, asr r2
+  and	r6, r6, r7, ror r2
+  and	r10, r10, r1, rrx
+  bfc	r5, #3, #17
+  bfclo	r5, #3, #17
+  bfi	r5, r2, #3, #17
+  bfine	r5, r2, #3, #17
+  bic	r10, r1, #15
+  bic	r7, r8, #-2147483638
+  bic	r7, r8, #40, #2
+  bic	r10, r1, r6
+  bic	r10, r1, r6, lsl #10
+  bic	r10, r1, r6, lsr #10
+  bic	r10, r1, r6, lsr #10
+  bic	r10, r1, r6, asr #10
+  bic	r10, r1, r6, ror #10
+  bic	r6, r7, r8, lsl r2
+  bic	r6, r7, r8, lsr r2
+  bic	r6, r7, r8, asr r2
+  bic	r6, r7, r8, ror r2
+  bic	r10, r1, r6, rrx
+  bic	r1, r1, #15
+  bic	r10, r10, r1
+  bic	r10, r10, r1, lsl #10
+  bic	r10, r10, r1, lsr #10
+  bic	r10, r10, r1, lsr #10
+  bic	r10, r10, r1, asr #10
+  bic	r10, r10, r1, ror #10
+  bic	r6, r6, r7, lsl r2
+  bic	r6, r6, r7, lsr r2
+  bic	r6, r6, r7, asr r2
+  bic	r6, r6, r7, ror r2
+  bic	r10, r10, r1, rrx
+  bkpt	#10
+  bkpt	#65535
+  blx	r2
+  blxne	r2
+  blx	#32424576
+  blx	#16212288
+  bx	r2
+  bxne	r2
+  bxj	r2
+  bxjne	r2
+  clrex
+  clz	r1, r2
+  clzeq	r1, r2
+  cmn	r1, #15
+  cmn	r7, #40, #2
+  cmn	r7, #-2147483638
+  cmn	r1, r6
+  cmn	r1, r6, lsl #10
+  cmn	r1, r6, lsr #10
+  cmn	sp, r6, lsr #10
+  cmn	r1, r6, asr #10
+  cmn	r1, r6, ror #10
+  cmn	r7, r8, lsl r2
+  cmn	sp, r8, lsr r2
+  cmn	r7, r8, asr r2
+  cmn	r7, r8, ror r2
+  cmn	r1, r6, rrx
+  cmp	r1, #15
+  cmp	r7, #40, #2
+  cmp	r7, #-2147483638
+  cmp	r1, r6
+  cmp	r1, r6, lsl #10
+  cmp	r1, r6, lsr #10
+  cmp	sp, r6, lsr #10
+  cmp	r1, r6, asr #10
+  cmp	r1, r6, ror #10
+  cmp	r7, r8, lsl r2
+  cmp	sp, r8, lsr r2
+  cmp	r7, r8, asr r2
+  cmp	r7, r8, ror r2
+  cmp	r1, r6, rrx
+  cpsie	aif
+  cps	#15
+  cpsid	if, #10
+  cpsid	af, #17
+  cpsie	f, #26
+  dbg	#0
+  dbg	#5
+  dbg	#15
+  dmb	#0x0
+  dmb	oshld
+  dmb	oshst
+  dmb	osh
+  dmb	#0x4
+  dmb	nshld
+  dmb	nshst
+  dmb	nsh
+  dmb	#0x8
+  dmb	ishld
+  dmb	ishst
+  dmb	ish
+  dmb	#0xc
+  dmb	ld
+  dmb	st
+  dmb	sy
+  ssbb
+  dsb	oshld
+  dsb	oshst
+  dsb	osh
+  pssbb
+  dsb	nshld
+  dsb	nshst
+  dsb	nsh
+  dsb	#0x8
+  dsb	ishld
+  dsb	ishst
+  dsb	ish
+  dsb	#0xc
+  dsb	ld
+  dsb	st
+  dsb	sy
+  eor	r4, r5, #61440
+  eor	r7, r8, #-2147483638
+  eor	r7, r8, #40, #2
+  eor	r4, r5, r6
+  eor	r4, r5, r6, lsl #5
+  eor	r4, r5, r6, lsr #5
+  eor	r4, r5, r6, lsr #5
+  eor	r4, r5, r6, asr #5
+  eor	r4, r5, r6, ror #5
+  eor	r6, r7, r8, lsl r9
+  eor	r6, r7, r8, lsr r9
+  eor	r6, r7, r8, asr r9
+  eor	r6, r7, r8, ror r9
+  eor	r4, r5, r6, rrx
+  eor	r5, r5, #61440
+  eor	r4, r4, r5
+  eor	r4, r4, r5, lsl #5
+  eor	r4, r4, r5, lsr #5
+  eor	r4, r4, r5, lsr #5
+  eor	r4, r4, r5, asr #5
+  eor	r4, r4, r5, ror #5
+  eor	r6, r6, r7, lsl r9
+  eor	r6, r6, r7, lsr r9
+  eor	r6, r6, r7, asr r9
+  eor	r6, r6, r7, ror r9
+  eor	r4, r4, r5, rrx
+  isb	sy
+  isb	#0xa
+  ldm	r2, {r1, r3, r4, r5, r6, sp}
+  ldmib	r2, {r1, r3, r4, r5, r6, sp}
+  ldmda	r2, {r1, r3, r4, r5, r6, sp}
+  ldmdb	r2, {r1, r3, r4, r5, r6, sp}
+  ldm	r2!, {r1, r3, r4, r5, r6, sp}
+  ldmib	r2!, {r1, r3, r4, r5, r6, sp}
+  ldmda	r2!, {r1, r3, r4, r5, r6, sp}
+  ldmdb	r2!, {r1, r3, r4, r5, r6, sp}
+  ldrexb	r3, [r4]
+  ldrexh	r2, [r5]
+  ldrex	r1, [r7]
+  ldrexd	r6, r7, [r8]
+  mla	r1, r2, r3, r4
+  mlas	r1, r2, r3, r4
+  mlane	r1, r2, r3, r4
+  mlasne	r1, r2, r3, r4
+  mls	r2, r5, r6, r3
+  mlsne	r2, r5, r6, r3
+  mov	r3, #7
+  mov	r4, #4080
+  mov	r5, #16711680
+  mov	sp, #35
+  mov	r9, #240, #30
+  mov	r7, #-2147483638
+  mov	pc, #2147483658
+  movw	r6, #65535
+  movw	r9, #65535
+  movw	sp, #1193
+  movs	r3, #7
+  movs	r11, #99
+  movs	r11, #240, #30
+  moveq	r4, #4080
+  movseq	r5, #16711680
+  mov	r2, r3
+  movs	r2, r3
+  moveq	r2, r3
+  movseq	r2, r3
+  movt	r3, #7
+  movt	r6, #65535
+  movt	sp, #3397
+  movteq	r4, #4080
+  mrc	p14, #0, r1, c1, c2, #4
+  mrc	p15, #7, apsr_nzcv, c15, c6, #6
+  mrs	r8, apsr
+  mrs	r8, spsr
+  msr	CPSR_fc, #5
+  msr	APSR_g, #5
+  msr	APSR_nzcvq, #5
+  msr	APSR_nzcvq, #5
+  msr	APSR_nzcvqg, #5
+  msr	CPSR_fc, #5
+  msr	CPSR_c, #5
+  msr	CPSR_x, #5
+  msr	CPSR_fc, #5
+  msr	CPSR_fc, #5
+  msr	CPSR_fsx, #5
+  msr	SPSR_fc, #5
+  msr	SPSR_fsxc, #5
+  msr	CPSR_fsxc, #5
+  msr	APSR_nzcvq, #2147483658
+  msr	SPSR_fsxc, #40, #2
+  msr	CPSR_fc, r0
+  msr	APSR_g, r0
+  msr	APSR_nzcvq, r0
+  msr	APSR_nzcvq, r0
+  msr	APSR_nzcvqg, r0
+  msr	CPSR_fc, r0
+  msr	CPSR_c, r0
+  msr	CPSR_x, r0
+  msr	CPSR_fc, r0
+  msr	CPSR_fc, r0
+  msr	CPSR_fsx, r0
+  msr	SPSR_fc, r0
+  msr	SPSR_fsxc, r0
+  msr	CPSR_fsxc, r0
+  mul	r5, r6, r7
+  muls	r5, r6, r7
+  mulgt	r5, r6, r7
+  mulsle	r5, r6, r7
+  mvn	r3, #7
+  mvn	r4, #4080
+  mvn	r5, #16711680
+  mvn	r7, #40, #2
+  mvn	r7, #-2147483638
+  mvns	r3, #7
+  mvns	r11, #240, #30
+  mvns	r11, #-2147483638
+  mvneq	r4, #4080
+  mvnseq	r5, #16711680
+  mvn	r2, r3
+  mvns	r2, r3
+  mvn	r5, r6, lsl #19
+  mvn	r5, r6, lsr #9
+  mvn	r5, r6, asr #4
+  mvn	r5, r6, ror #6
+  mvn	r5, r6, rrx
+  mvneq	r2, r3
+  mvnseq	r2, r3, lsl #10
+  mvn	r5, r6, lsl r7
+  mvns	r5, r6, lsr r7
+  mvngt	r5, r6, asr r7
+  mvnslt	r5, r6, ror r7
+  nop
+  nopgt
+  orr	r4, r5, #61440
+  orr	r7, r8, #-2147483638
+  orr	r7, r8, #40, #2
+  orr	r4, r5, r6
+  orr	r4, r5, r6, lsl #5
+  orr	r4, r5, r6, lsr #5
+  orr	r4, r5, r6, lsr #5
+  orr	r4, r5, r6, asr #5
+  orr	r4, r5, r6, ror #5
+  orr	r6, r7, r8, lsl r9
+  orr	r6, r7, r8, lsr r9
+  orr	r6, r7, r8, asr r9
+  orr	r6, r7, r8, ror r9
+  orr	r4, r5, r6, rrx
+  orr	r5, r5, #61440
+  orr	r4, r4, r5
+  orr	r4, r4, r5, lsl #5
+  orr	r4, r4, r5, lsr #5
+  orr	r4, r4, r5, lsr #5
+  orr	r4, r4, r5, asr #5
+  orr	r4, r4, r5, ror #5
+  orr	r6, r6, r7, lsl r9
+  orr	r6, r6, r7, lsr r9
+  orr	r6, r6, r7, asr r9
+  orr	r6, r6, r7, ror r9
+  orr	r4, r4, r5, rrx
+  orrseq	r4, r5, #61440
+  orrne	r4, r5, r6
+  orrseq	r4, r5, r6, lsl #5
+  orrlo	r6, r7, r8, ror r9
+  orrshi	r4, r5, r6, rrx
+  orrhs	r5, r5, #61440
+  orrseq	r4, r4, r5
+  orrne	r6, r6, r7, asr r9
+  orrslt	r6, r6, r7, ror r9
+  orrsgt	r4, r4, r5, rrx
+  pkhbt	r2, r2, r3
+  pkhbt	r2, r2, r3, lsl #31
+  pkhbt	r2, r2, r3
+  pkhbt	r2, r2, r3, lsl #15
+  pkhbt	r2, r2, r3
+  pkhtb	r2, r2, r3, asr #31
+  pkhtb	r2, r2, r3, asr #15
+  ldr	r7, [sp], #4
+  pop	{r7, r8, r9, r10}
+  str	r7, [sp, #-4]!
+  push	{r7, r8, r9, r10}
+  qadd	r1, r2, r3
+  qaddne	r1, r2, r3
+  qadd16	r1, r2, r3
+  qadd16gt	r1, r2, r3
+  qadd8	r1, r2, r3
+  qadd8le	r1, r2, r3
+  qdadd	r6, r7, r8
+  qdaddhi	r6, r7, r8
+  qdsub	r6, r7, r8
+  qdsubhi	r6, r7, r8
+  qsax	r9, r12, r0
+  qsaxeq	r9, r12, r0
+  qsub	r1, r2, r3
+  qsubne	r1, r2, r3
+  qsub16	r1, r2, r3
+  qsub16gt	r1, r2, r3
+  qsub8	r1, r2, r3
+  qsub8le	r1, r2, r3
+  rbit	r1, r2
+  rbitne	r1, r2
+  rev	r1, r9
+  revne	r1, r5
+  rev16	r8, r3
+  rev16ne	r12, r4
+  revsh	r4, r9
+  revshne	r9, r1
+  rfeda	r2
+  rfedb	r3
+  rfeia	r5
+  rfeib	r6
+  rfeda	r4!
+  rfedb	r7!
+  rfeia	r9!
+  rfeib	r8!
+  rfeda	r2
+  rfedb	r3
+  rfeia	r5
+  rfeib	r6
+  rfeda	r4!
+  rfedb	r7!
+  rfeia	r9!
+  rfeib	r8!
+  rfeia	r1
+  rfeia	r1!
+  rsb	r4, r5, #61440
+  rsb	r7, r8, #-2147483638
+  rsb	r7, r8, #40, #2
+  rsb	r4, r5, r6
+  rsb	r4, r5, r6, lsl #5
+  rsblo	r4, r5, r6, lsr #5
+  rsb	r4, r5, r6, lsr #5
+  rsb	r4, r5, r6, asr #5
+  rsb	r4, r5, r6, ror #5
+  rsb	r6, r7, r8, lsl r9
+  rsb	r6, r7, r8, lsr r9
+  rsb	r6, r7, r8, asr r9
+  rsble	r6, r7, r8, ror r9
+  rsb	r4, r5, r6, rrx
+  rsb	r5, r5, #61440
+  rsb	r4, r4, r5
+  rsb	r4, r4, r5, lsl #5
+  rsb	r4, r4, r5, lsr #5
+  rsbne	r4, r4, r5, lsr #5
+  rsb	r4, r4, r5, asr #5
+  rsb	r4, r4, r5, ror #5
+  rsbgt	r6, r6, r7, lsl r9
+  rsb	r6, r6, r7, lsr r9
+  rsb	r6, r6, r7, asr r9
+  rsb	r6, r6, r7, ror r9
+  rsb	r4, r4, r5, rrx
+  rsbs	r7, r8, #-2147483638
+  rsbs	r7, r8, #40, #2
+  rsc	r4, r5, #61440
+  rsc	r7, r8, #-2147483638
+  rsc	r7, r8, #40, #2
+  rsc	r4, r5, r6
+  rsc	r4, r5, r6, lsl #5
+  rsclo	r4, r5, r6, lsr #5
+  rsc	r4, r5, r6, lsr #5
+  rsc	r4, r5, r6, asr #5
+  rsc	r4, r5, r6, ror #5
+  rsc	r6, r7, r8, lsl r9
+  rsc	r6, r7, r8, lsr r9
+  rsc	r6, r7, r8, asr r9
+  rscle	r6, r7, r8, ror r9
+  rsc	r5, r5, #61440
+  rsc	r4, r4, r5
+  rsc	r4, r4, r5, lsl #5
+  rsc	r4, r4, r5, lsr #5
+  rscne	r4, r4, r5, lsr #5
+  rsc	r4, r4, r5, asr #5
+  rsc	r4, r4, r5, ror #5
+  rscgt	r6, r6, r7, lsl r9
+  rsc	r6, r6, r7, lsr r9
+  rsc	r6, r6, r7, asr r9
+  rsc	r6, r6, r7, ror r9
+  rrx	r0, r1
+  rrx	sp, pc
+  rrx	pc, lr
+  rrx	lr, sp
+  rrxs	r0, r1
+  rrxs	sp, pc
+  rrxs	pc, lr
+  rrxs	lr, sp
+  sadd16	r1, r2, r3
+  sadd16gt	r1, r2, r3
+  sadd8	r1, r2, r3
+  sadd8le	r1, r2, r3
+  sasx	r9, r12, r0
+  sasxeq	r9, r12, r0
+  sbc	r4, r5, #61440
+  sbc	r7, r8, #-2147483638
+  sbc	r7, r8, #40, #2
+  sbc	r4, r5, r6
+  sbc	r4, r5, r6, lsl #5
+  sbc	r4, r5, r6, lsr #5
+  sbc	r4, r5, r6, lsr #5
+  sbc	r4, r5, r6, asr #5
+  sbc	r4, r5, r6, ror #5
+  sbc	r6, r7, r8, lsl r9
+  sbc	r6, r7, r8, lsr r9
+  sbc	r6, r7, r8, asr r9
+  sbc	r6, r7, r8, ror r9
+  sbc	r5, r5, #61440
+  sbc	r4, r4, r5
+  sbc	r4, r4, r5, lsl #5
+  sbc	r4, r4, r5, lsr #5
+  sbc	r4, r4, r5, lsr #5
+  sbc	r4, r4, r5, asr #5
+  sbc	r4, r4, r5, ror #5
+  sbc	r6, r6, r7, lsl r9
+  sbc	r6, r6, r7, lsr r9
+  sbc	r6, r6, r7, asr r9
+  sbc	r6, r6, r7, ror r9
+  sbfx	r4, r5, #16, #1
+  sbfxgt	r4, r5, #16, #16
+  sel	r9, r2, r1
+  selne	r9, r2, r1
+  setend	be
+  setend	le
+  sev
+  seveq
+  shadd16	r4, r8, r2
+  shadd16gt	r4, r8, r2
+  shadd8	r4, r8, r2
+  shadd8gt	r4, r8, r2
+  shasx	r4, r8, r2
+  shasxgt	r4, r8, r2
+  shsub16	r4, r8, r2
+  shsub16gt	r4, r8, r2
+  shsub8	r4, r8, r2
+  shsub8gt	r4, r8, r2
+  smlabb	r3, r1, r9, r0
+  smlabt	r5, r6, r4, r1
+  smlatb	r4, r2, r3, r2
+  smlatt	r8, r3, r8, r4
+  smlabbge	r3, r1, r9, r0
+  smlabtle	r5, r6, r4, r1
+  smlatbne	r4, r2, r3, r2
+  smlatteq	r8, r3, r8, r4
+  smlad	r2, r3, r5, r8
+  smladx	r2, r3, r5, r8
+  smladeq	r2, r3, r5, r8
+  smladxhi	r2, r3, r5, r8
+  smlal	r2, r3, r5, r8
+  smlals	r2, r3, r5, r8
+  smlaleq	r2, r3, r5, r8
+  smlalshi	r2, r3, r5, r8
+  smlalbb	r3, r1, r9, r0
+  smlalbt	r5, r6, r4, r1
+  smlaltb	r4, r2, r3, r2
+  smlaltt	r8, r3, r8, r4
+  smlalbbge	r3, r1, r9, r0
+  smlalbtle	r5, r6, r4, r1
+  smlaltbne	r4, r2, r3, r2
+  smlaltteq	r8, r3, r8, r4
+  smlald	r2, r3, r5, r8
+  smlaldx	r2, r3, r5, r8
+  smlaldeq	r2, r3, r5, r8
+  smlaldxhi	r2, r3, r5, r8
+  smlawb	r2, r3, r10, r8
+  smlawt	r8, r3, r5, r9
+  smlawbeq	r2, r7, r5, r8
+  smlawthi	r1, r3, r0, r8
+  smlsd	r2, r3, r5, r8
+  smlsdx	r2, r3, r5, r8
+  smlsdeq	r2, r3, r5, r8
+  smlsdxhi	r2, r3, r5, r8
+  smlsld	r2, r9, r5, r1
+  smlsldx	r4, r11, r2, r8
+  smlsldeq	r8, r2, r5, r6
+  smlsldxhi	r1, r0, r3, r8
+  smmla	r1, r2, r3, r4
+  smmlar	r4, r3, r2, r1
+  smmlalo	r1, r2, r3, r4
+  smmlarhs	r4, r3, r2, r1
+  smmls	r1, r2, r3, r4
+  smmlsr	r4, r3, r2, r1
+  smmlslo	r1, r2, r3, r4
+  smmlsrhs	r4, r3, r2, r1
+  smmul	r2, r3, r4
+  smmulr	r3, r2, r1
+  smmullo	r2, r3, r4
+  smmulrhs	r3, r2, r1
+  smuad	r2, r3, r4
+  smuadx	r3, r2, r1
+  smuadlt	r2, r3, r4
+  smuadxge	r3, r2, r1
+  smulbb	r3, r9, r0
+  smulbt	r5, r4, r1
+  smultb	r4, r2, r2
+  smultt	r8, r3, r4
+  smulbbge	r1, r9, r0
+  smulbtle	r5, r6, r4
+  smultbne	r2, r3, r2
+  smultteq	r8, r3, r4
+  smull	r3, r9, r0, r1
+  smulls	r3, r9, r0, r2
+  smulleq	r8, r3, r4, r5
+  smullseq	r8, r3, r4, r3
+  smulwb	r3, r9, r0
+  smulwt	r3, r9, r2
+  smusd	r3, r0, r1
+  smusdx	r3, r9, r2
+  smusdeq	r8, r3, r2
+  smusdxne	r7, r4, r3
+  srsda	sp, #5
+  srsdb	sp, #1
+  srsia	sp, #0
+  srsib	sp, #15
+  srsda	sp!, #31
+  srsdb	sp!, #19
+  srsia	sp!, #2
+  srsib	sp!, #14
+  srsda	sp, #11
+  srsdb	sp, #10
+  srsia	sp, #9
+  srsib	sp, #5
+  srsda	sp!, #5
+  srsdb	sp!, #5
+  srsia	sp!, #5
+  srsib	sp!, #5
+  srsia	sp, #5
+  srsia	sp!, #5
+  ssat	r8, #1, r10
+  ssat	r8, #1, r10, lsl #31
+  ssat	r8, #1, r10, asr #32
+  ssat	r8, #1, r10, asr #1
+  ssat16	r2, #1, r7
+  ssat16	r3, #16, r5
+  ssax	r2, r3, r4
+  ssaxlt	r2, r3, r4
+  ssub16	r1, r0, r6
+  ssub16ne	r5, r3, r2
+  ssub8	r9, r2, r4
+  ssub8eq	r5, r1, r2
+  stm	r2, {r1, r3, r4, r5, r6, sp}
+  stm	r3, {r1, r3, r4, r5, r6, lr}
+  stmib	r4, {r1, r3, r4, r5, r6, sp}
+  stmda	r5, {r1, r3, r4, r5, r6, sp}
+  stmdb	r6, {r1, r3, r4, r5, r6, r8}
+  stmdb	sp, {r1, r3, r4, r5, r6, sp}
+  stm	r8!, {r1, r3, r4, r5, r6, sp}
+  stmib	r9!, {r1, r3, r4, r5, r6, sp}
+  stmda	sp!, {r1, r3, r4, r5, r6}
+  stmdb	r0!, {r1, r5, r7, sp}
+  strexb	r1, r3, [r4]
+  strexh	r4, r2, [r5]
+  strex	r2, r1, [r7]
+  strexd	r6, r2, r3, [r8]
+  strexd	sp, r0, r1, [r0]
+  sub	r4, r5, #61440
+  sub	r7, r8, #-2147483638
+  sub	r7, r8, #40, #2
+  sub	r4, r5, r6
+  sub	r4, r5, r6, lsl #5
+  sub	r4, r5, r6, lsr #5
+  sub	r4, r5, r6, lsr #5
+  sub	r4, r5, r6, asr #5
+  sub	r4, r5, r6, ror #5
+  sub	r6, r7, r8, lsl r9
+  sub	r6, r7, r8, lsr r9
+  sub	r6, r7, r8, asr r9
+  sub	r6, r7, r8, ror r9
+  sub	r5, r5, #61440
+  sub	r4, r4, r5
+  sub	r4, r4, r5, lsl #5
+  sub	r4, r4, r5, lsr #5
+  sub	r4, r4, r5, lsr #5
+  sub	r4, r4, r5, asr #5
+  sub	r4, r4, r5, ror #5
+  sub	r6, r6, r7, lsl r9
+  sub	r6, r6, r7, lsr r9
+  sub	r6, r6, r7, asr r9
+  sub	r6, r6, r7, ror r9
+  subs	r7, r8, #-2147483638
+  subs	r7, r8, #40, #2
+  svc	#16
+  svc	#0
+  svc	#16777215
+  sxtab	r2, r3, r4
+  sxtab	r4, r5, r6
+  sxtablt	r6, r2, r9, ror #8
+  sxtab	r5, r1, r4, ror #16
+  sxtab	r7, r8, r3, ror #24
+  sxtab16ge	r0, r1, r4
+  sxtab16	r6, r2, r7
+  sxtab16	r3, r5, r8, ror #8
+  sxtab16	r3, r2, r1, ror #16
+  sxtab16eq	r1, r2, r3, ror #24
+  sxtah	r1, r3, r9
+  sxtahhi	r6, r1, r6
+  sxtah	r3, r8, r3, ror #8
+  sxtahlo	r2, r2, r4, ror #16
+  sxtah	r9, r3, r3, ror #24
+  sxtbge	r2, r4
+  sxtb	r5, r6
+  sxtb	r6, r9, ror #8
+  sxtblo	r5, r1, ror #16
+  sxtb	r8, r3, ror #24
+  sxtb16	r1, r4
+  sxtb16	r6, r7
+  sxtb16hs	r3, r5, ror #8
+  sxtb16	r3, r1, ror #16
+  sxtb16ge	r2, r3, ror #24
+  sxthne	r3, r9
+  sxth	r1, r6
+  sxth	r3, r8, ror #8
+  sxthle	r2, r2, ror #16
+  sxth	r9, r3, ror #24
+  teq	r5, #61440
+  teq	r7, #-2147483638
+  teq	r7, #40, #2
+  teq	r4, r5
+  teq	r4, r5, lsl #5
+  teq	r4, r5, lsr #5
+  teq	r4, r5, lsr #5
+  teq	r4, r5, asr #5
+  teq	r4, r5, ror #5
+  teq	r6, r7, lsl r9
+  teq	r6, r7, lsr r9
+  teq	r6, r7, asr r9
+  teq	r6, r7, ror r9
+  tst	r5, #61440
+  tst	r7, #-2147483638
+  tst	r7, #40, #2
+  tst	r4, r5
+  tst	r4, r5, lsl #5
+  tst	r4, r5, lsr #5
+  tst	r4, r5, lsr #5
+  tst	r4, r5, asr #5
+  tst	r4, r5, ror #5
+  tst	r6, r7, lsl r9
+  tst	r6, r7, lsr r9
+  tst	r6, r7, asr r9
+  tst	r6, r7, ror r9
+  uadd16	r1, r2, r3
+  uadd16gt	r1, r2, r3
+  uadd8	r1, r2, r3
+  uadd8le	r1, r2, r3
+  uasx	r9, r12, r0
+  uasxeq	r9, r12, r0
+  ubfx	r4, r5, #16, #1
+  ubfxgt	r4, r5, #16, #16
+  uhadd16	r4, r8, r2
+  uhadd16gt	r4, r8, r2
+  uhadd8	r4, r8, r2
+  uhadd8gt	r4, r8, r2
+  uhasx	r4, r8, r2
+  uhasxgt	r4, r8, r2
+  uhsub16	r4, r8, r2
+  uhsub16gt	r4, r8, r2
+  uhsub8	r4, r8, r2
+  uhsub8gt	r4, r8, r2
+  umaal	r3, r4, r5, r6
+  umaallt	r3, r4, r5, r6
+  umlal	r2, r4, r6, r8
+  umlalgt	r6, r1, r2, r6
+  umlals	r2, r9, r2, r3
+  umlalseq	r3, r5, r1, r2
+  umull	r2, r4, r6, r8
+  umullgt	r6, r1, r2, r6
+  umulls	r2, r9, r2, r3
+  umullseq	r3, r5, r1, r2
+  uqadd16	r1, r2, r3
+  uqadd16gt	r4, r7, r9
+  uqadd8	r3, r4, r8
+  uqadd8le	r8, r1, r2
+  uqasx	r2, r4, r1
+  uqasxhi	r5, r2, r9
+  uqsax	r1, r3, r7
+  uqsax	r3, r6, r2
+  uqsub16	r1, r5, r3
+  uqsub16gt	r3, r2, r5
+  uqsub8	r2, r1, r4
+  uqsub8le	r4, r6, r9
+  usad8	r2, r1, r4
+  usad8le	r4, r6, r9
+  usada8	r1, r5, r3, r7
+  usada8gt	r3, r2, r5, r1
+  usat	r8, #1, r10
+  usat	r8, #4, r10
+  usat	r8, #5, r10, lsl #31
+  usat	r8, #31, r10, asr #32
+  usat	r8, #16, r10, asr #1
+  usat16	r2, #2, r7
+  usat16	r3, #15, r5
+  usax	r2, r3, r4
+  usaxne	r2, r3, r4
+  usub16	r4, r2, r7
+  usub16hi	r1, r1, r3
+  usub8	r1, r8, r5
+  usub8le	r9, r2, r3
+  uxtab	r2, r3, r4
+  uxtab	r4, r5, r6
+  uxtablt	r6, r2, r9, ror #8
+  uxtab	r5, r1, r4, ror #16
+  uxtab	r7, r8, r3, ror #24
+  uxtab16ge	r0, r1, r4
+  uxtab16	r6, r2, r7
+  uxtab16	r3, r5, r8, ror #8
+  uxtab16	r3, r2, r1, ror #16
+  uxtab16eq	r1, r2, r3, ror #24
+  uxtah	r1, r3, r9
+  uxtahhi	r6, r1, r6
+  uxtah	r3, r8, r3, ror #8
+  uxtahlo	r2, r2, r4, ror #16
+  uxtah	r9, r3, r3, ror #24
+  uxtbge	r2, r4
+  uxtb	r5, r6
+  uxtb	r6, r9, ror #8
+  uxtblo	r5, r1, ror #16
+  uxtb	r8, r3, ror #24
+  uxtb16	r1, r4
+  uxtb16	r6, r7
+  uxtb16hs	r3, r5, ror #8
+  uxtb16	r3, r1, ror #16
+  uxtb16ge	r2, r3, ror #24
+  uxthne	r3, r9
+  uxth	r1, r6
+  uxth	r3, r8, ror #8
+  uxthle	r2, r2, ror #16
+  uxth	r9, r3, ror #24
+  wfe
+  wfehi
+  wfi
+  wfilt
+  yield
+  yieldne
+  sevl
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #15
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #240
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #3840
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #61440
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #983040
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #15728640
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #251658240
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #-268435456
+# CHECK-NEXT:  1      1     0.50                        adc	r1, r2, #-268435441
+# CHECK-NEXT:  1      1     0.50                        adc	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        adc	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        adcs	r1, r2, #3840
+# CHECK-NEXT:  1      1     0.50                        adcs	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        adcseq	r1, r2, #3840
+# CHECK-NEXT:  1      1     0.50                        adceq	r1, r2, #3840
+# CHECK-NEXT:  1      1     0.50                        adc	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, lsl #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, lsl #31
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, lsr #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, lsr #31
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, lsr #32
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, asr #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, asr #31
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, asr #32
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, ror #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, ror #31
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r5, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        adc	r5, r5, r6
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, lsl #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, lsl #31
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, lsr #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, lsr #31
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, lsr #32
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, asr #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, asr #31
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, asr #32
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, ror #1
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, ror #31
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, rrx
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        adc	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     1.00                        adc	r4, r4, r5, rrx
+# CHECK-NEXT:  1      1     0.50                        add	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        add	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        add	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        add	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        add	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r5, r6, asr #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r5, r6, ror #5
+# CHECK-NEXT:  1      2     1.00                        add	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        add	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        add	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        add	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     1.00                        add	r4, r5, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        add	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        add	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        add	r4, r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        add	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        add	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        add	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        add	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     1.00                        add	r4, r4, r5, rrx
+# CHECK-NEXT:  1      1     0.50                        adds	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        adds	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        adr	r2, #3
+# CHECK-NEXT:  1      1     0.50                        sub	r2, pc, #3
+# CHECK-NEXT:  1      1     0.50                        sub	r1, pc, #0
+# CHECK-NEXT:  1      1     0.50                        sub	r1, pc, #301989888
+# CHECK-NEXT:  1      1     0.50                        adr	r1, #301989888
+# CHECK-NEXT:  1      1     0.50                        and	r10, r1, #15
+# CHECK-NEXT:  1      1     0.50                        and	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        and	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        and	r10, r1, r6
+# CHECK-NEXT:  1      2     1.00                        and	r10, r1, r6, lsl #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r1, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r1, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r1, r6, asr #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r1, r6, ror #10
+# CHECK-NEXT:  1      2     1.00                        and	r6, r7, r8, lsl r2
+# CHECK-NEXT:  1      2     1.00                        and	r6, r7, r8, lsr r2
+# CHECK-NEXT:  1      2     1.00                        and	r6, r7, r8, asr r2
+# CHECK-NEXT:  1      2     1.00                        and	r6, r7, r8, ror r2
+# CHECK-NEXT:  1      2     1.00                        and	r10, r1, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        and	r1, r1, #15
+# CHECK-NEXT:  1      1     0.50                        and	r10, r10, r1
+# CHECK-NEXT:  1      2     1.00                        and	r10, r10, r1, lsl #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r10, r1, lsr #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r10, r1, lsr #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r10, r1, asr #10
+# CHECK-NEXT:  1      2     1.00                        and	r10, r10, r1, ror #10
+# CHECK-NEXT:  1      2     1.00                        and	r6, r6, r7, lsl r2
+# CHECK-NEXT:  1      2     1.00                        and	r6, r6, r7, lsr r2
+# CHECK-NEXT:  1      2     1.00                        and	r6, r6, r7, asr r2
+# CHECK-NEXT:  1      2     1.00                        and	r6, r6, r7, ror r2
+# CHECK-NEXT:  1      2     1.00                        and	r10, r10, r1, rrx
+# CHECK-NEXT:  1      2     1.00                        bfc	r5, #3, #17
+# CHECK-NEXT:  1      2     1.00                        bfclo	r5, #3, #17
+# CHECK-NEXT:  1      2     1.00                        bfi	r5, r2, #3, #17
+# CHECK-NEXT:  1      2     1.00                        bfine	r5, r2, #3, #17
+# CHECK-NEXT:  1      1     0.50                        bic	r10, r1, #15
+# CHECK-NEXT:  1      1     0.50                        bic	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        bic	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        bic	r10, r1, r6
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r1, r6, lsl #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r1, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r1, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r1, r6, asr #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r1, r6, ror #10
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r7, r8, lsl r2
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r7, r8, lsr r2
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r7, r8, asr r2
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r7, r8, ror r2
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r1, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        bic	r1, r1, #15
+# CHECK-NEXT:  1      1     0.50                        bic	r10, r10, r1
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r10, r1, lsl #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r10, r1, lsr #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r10, r1, lsr #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r10, r1, asr #10
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r10, r1, ror #10
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r6, r7, lsl r2
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r6, r7, lsr r2
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r6, r7, asr r2
+# CHECK-NEXT:  1      2     1.00                        bic	r6, r6, r7, ror r2
+# CHECK-NEXT:  1      2     1.00                        bic	r10, r10, r1, rrx
+# CHECK-NEXT:  0      0     0.00                  U     bkpt	#10
+# CHECK-NEXT:  0      0     0.00                  U     bkpt	#65535
+# CHECK-NEXT:  2      2     1.00                        blx	r2
+# CHECK-NEXT:  2      2     1.00                        blxne	r2
+# CHECK-NEXT:  2      1     1.00                  U     blx	#32424576
+# CHECK-NEXT:  2      1     1.00                  U     blx	#16212288
+# CHECK-NEXT:  1      1     1.00                  U     bx	r2
+# CHECK-NEXT:  1      1     1.00                  U     bxne	r2
+# CHECK-NEXT:  1      1     1.00                  U     bxj	r2
+# CHECK-NEXT:  1      1     1.00                  U     bxjne	r2
+# CHECK-NEXT:  0      0     0.00    *      *      U     clrex
+# CHECK-NEXT:  1      1     0.50                        clz	r1, r2
+# CHECK-NEXT:  1      1     0.50                        clzeq	r1, r2
+# CHECK-NEXT:  1      1     0.50                        cmn	r1, #15
+# CHECK-NEXT:  1      1     0.50                        cmn	r7, #40, #2
+# CHECK-NEXT:  1      1     0.50                        cmn	r7, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        cmn	r1, r6
+# CHECK-NEXT:  1      2     1.00                        cmn	r1, r6, lsl #10
+# CHECK-NEXT:  1      2     1.00                        cmn	r1, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        cmn	sp, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        cmn	r1, r6, asr #10
+# CHECK-NEXT:  1      2     1.00                        cmn	r1, r6, ror #10
+# CHECK-NEXT:  1      2     1.00                        cmn	r7, r8, lsl r2
+# CHECK-NEXT:  1      2     1.00                        cmn	sp, r8, lsr r2
+# CHECK-NEXT:  1      2     1.00                        cmn	r7, r8, asr r2
+# CHECK-NEXT:  1      2     1.00                        cmn	r7, r8, ror r2
+# CHECK-NEXT:  1      2     1.00                        cmn	r1, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        cmp	r1, #15
+# CHECK-NEXT:  1      1     0.50                        cmp	r7, #40, #2
+# CHECK-NEXT:  1      1     0.50                        cmp	r7, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        cmp	r1, r6
+# CHECK-NEXT:  1      2     1.00                        cmp	r1, r6, lsl #10
+# CHECK-NEXT:  1      2     1.00                        cmp	r1, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        cmp	sp, r6, lsr #10
+# CHECK-NEXT:  1      2     1.00                        cmp	r1, r6, asr #10
+# CHECK-NEXT:  1      2     1.00                        cmp	r1, r6, ror #10
+# CHECK-NEXT:  1      2     1.00                        cmp	r7, r8, lsl r2
+# CHECK-NEXT:  1      2     1.00                        cmp	sp, r8, lsr r2
+# CHECK-NEXT:  1      2     1.00                        cmp	r7, r8, asr r2
+# CHECK-NEXT:  1      2     1.00                        cmp	r7, r8, ror r2
+# CHECK-NEXT:  1      2     1.00                        cmp	r1, r6, rrx
+# CHECK-NEXT:  0      0     0.00                  U     cpsie	aif
+# CHECK-NEXT:  0      0     0.00                  U     cps	#15
+# CHECK-NEXT:  0      0     0.00                  U     cpsid	if, #10
+# CHECK-NEXT:  0      0     0.00                  U     cpsid	af, #17
+# CHECK-NEXT:  0      0     0.00                  U     cpsie	f, #26
+# CHECK-NEXT:  0      0     0.00    *      *      U     dbg	#0
+# CHECK-NEXT:  0      0     0.00    *      *      U     dbg	#5
+# CHECK-NEXT:  0      0     0.00    *      *      U     dbg	#15
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	#0x0
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	oshld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	oshst
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	osh
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	#0x4
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	nshld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	nshst
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	nsh
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	#0x8
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	ishld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	ishst
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	ish
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	#0xc
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	ld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	st
+# CHECK-NEXT:  0      0     0.00    *      *      U     dmb	sy
+# CHECK-NEXT:  0      0     0.00    *      *      U     ssbb
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	oshld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	oshst
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	osh
+# CHECK-NEXT:  0      0     0.00    *      *      U     pssbb
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	nshld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	nshst
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	nsh
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	#0x8
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	ishld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	ishst
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	ish
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	#0xc
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	ld
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	st
+# CHECK-NEXT:  0      0     0.00    *      *      U     dsb	sy
+# CHECK-NEXT:  1      1     0.50                        eor	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        eor	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        eor	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        eor	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r5, r6, asr #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r5, r6, ror #5
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r5, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        eor	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        eor	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        eor	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     1.00                        eor	r4, r4, r5, rrx
+# CHECK-NEXT:  0      0     0.00    *      *      U     isb	sy
+# CHECK-NEXT:  0      0     0.00    *      *      U     isb	#0xa
+# CHECK-NEXT:  16     10    16.00   *                   ldm	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  16     10    16.00   *                   ldmib	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  16     10    16.00   *                   ldmda	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  16     10    16.00   *                   ldmdb	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  32     10    16.00   *                   ldm	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  32     10    16.00   *                   ldmib	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  32     10    16.00   *                   ldmda	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  32     10    16.00   *                   ldmdb	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  0      0     0.00    *      *      U     ldrexb	r3, [r4]
+# CHECK-NEXT:  0      0     0.00    *      *      U     ldrexh	r2, [r5]
+# CHECK-NEXT:  0      0     0.00    *      *      U     ldrex	r1, [r7]
+# CHECK-NEXT:  0      0     0.00    *             U     ldrexd	r6, r7, [r8]
+# CHECK-NEXT:  1      3     1.00                        mla	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        mlas	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        mlane	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        mlasne	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        mls	r2, r5, r6, r3
+# CHECK-NEXT:  1      3     1.00                        mlsne	r2, r5, r6, r3
+# CHECK-NEXT:  1      1     0.50                        mov	r3, #7
+# CHECK-NEXT:  1      1     0.50                        mov	r4, #4080
+# CHECK-NEXT:  1      1     0.50                        mov	r5, #16711680
+# CHECK-NEXT:  1      1     0.50                        mov	sp, #35
+# CHECK-NEXT:  1      1     0.50                        mov	r9, #240, #30
+# CHECK-NEXT:  1      1     0.50                        mov	r7, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        mov	pc, #2147483658
+# CHECK-NEXT:  1      1     0.50                        movw	r6, #65535
+# CHECK-NEXT:  1      1     0.50                        movw	r9, #65535
+# CHECK-NEXT:  1      1     0.50                        movw	sp, #1193
+# CHECK-NEXT:  1      1     0.50                        movs	r3, #7
+# CHECK-NEXT:  1      1     0.50                        movs	r11, #99
+# CHECK-NEXT:  1      1     0.50                        movs	r11, #240, #30
+# CHECK-NEXT:  1      1     0.50                        moveq	r4, #4080
+# CHECK-NEXT:  1      1     0.50                        movseq	r5, #16711680
+# CHECK-NEXT:  1      1     0.50                        mov	r2, r3
+# CHECK-NEXT:  1      1     0.50                        movs	r2, r3
+# CHECK-NEXT:  1      1     0.50                        moveq	r2, r3
+# CHECK-NEXT:  1      1     0.50                        movseq	r2, r3
+# CHECK-NEXT:  1      2     1.00                        movt	r3, #7
+# CHECK-NEXT:  1      2     1.00                        movt	r6, #65535
+# CHECK-NEXT:  1      2     1.00                        movt	sp, #3397
+# CHECK-NEXT:  1      2     1.00                        movteq	r4, #4080
+# CHECK-NEXT:  0      0     0.00    *      *      U     mrc	p14, #0, r1, c1, c2, #4
+# CHECK-NEXT:  0      0     0.00    *      *      U     mrc	p15, #7, apsr_nzcv, c15, c6, #6
+# CHECK-NEXT:  0      0     0.00                  U     mrs	r8, apsr
+# CHECK-NEXT:  0      0     0.00                  U     mrs	r8, spsr
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_g, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_nzcvq, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_nzcvq, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_nzcvqg, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_c, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_x, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fsx, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	SPSR_fc, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	SPSR_fsxc, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fsxc, #5
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_nzcvq, #2147483658
+# CHECK-NEXT:  0      0     0.00                  U     msr	SPSR_fsxc, #40, #2
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_g, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_nzcvq, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_nzcvq, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	APSR_nzcvqg, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_c, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_x, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fc, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fsx, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	SPSR_fc, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	SPSR_fsxc, r0
+# CHECK-NEXT:  0      0     0.00                  U     msr	CPSR_fsxc, r0
+# CHECK-NEXT:  1      3     1.00                        mul	r5, r6, r7
+# CHECK-NEXT:  1      3     1.00                        muls	r5, r6, r7
+# CHECK-NEXT:  1      3     1.00                        mulgt	r5, r6, r7
+# CHECK-NEXT:  1      3     1.00                        mulsle	r5, r6, r7
+# CHECK-NEXT:  1      1     0.50                        mvn	r3, #7
+# CHECK-NEXT:  1      1     0.50                        mvn	r4, #4080
+# CHECK-NEXT:  1      1     0.50                        mvn	r5, #16711680
+# CHECK-NEXT:  1      1     0.50                        mvn	r7, #40, #2
+# CHECK-NEXT:  1      1     0.50                        mvn	r7, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        mvns	r3, #7
+# CHECK-NEXT:  1      1     0.50                        mvns	r11, #240, #30
+# CHECK-NEXT:  1      1     0.50                        mvns	r11, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        mvneq	r4, #4080
+# CHECK-NEXT:  1      1     0.50                        mvnseq	r5, #16711680
+# CHECK-NEXT:  1      1     0.50                        mvn	r2, r3
+# CHECK-NEXT:  1      1     0.50                        mvns	r2, r3
+# CHECK-NEXT:  1      1     0.50                        mvn	r5, r6, lsl #19
+# CHECK-NEXT:  1      1     0.50                        mvn	r5, r6, lsr #9
+# CHECK-NEXT:  1      1     0.50                        mvn	r5, r6, asr #4
+# CHECK-NEXT:  1      1     0.50                        mvn	r5, r6, ror #6
+# CHECK-NEXT:  1      1     0.50                        mvn	r5, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        mvneq	r2, r3
+# CHECK-NEXT:  1      1     0.50                        mvnseq	r2, r3, lsl #10
+# CHECK-NEXT:  1      1     0.50                        mvn	r5, r6, lsl r7
+# CHECK-NEXT:  1      1     0.50                        mvns	r5, r6, lsr r7
+# CHECK-NEXT:  1      1     0.50                        mvngt	r5, r6, asr r7
+# CHECK-NEXT:  1      1     0.50                        mvnslt	r5, r6, ror r7
+# CHECK-NEXT:  0      0     0.00    *      *      U     nop
+# CHECK-NEXT:  0      0     0.00    *      *      U     nopgt
+# CHECK-NEXT:  1      1     0.50                        orr	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        orr	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        orr	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        orr	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r5, r6, asr #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r5, r6, ror #5
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r5, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        orr	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        orr	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        orr	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     1.00                        orr	r4, r4, r5, rrx
+# CHECK-NEXT:  1      1     0.50                        orrseq	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        orrne	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        orrseq	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        orrlo	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     1.00                        orrshi	r4, r5, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        orrhs	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        orrseq	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        orrne	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        orrslt	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     1.00                        orrsgt	r4, r4, r5, rrx
+# CHECK-NEXT:  1      2     1.00                        pkhbt	r2, r2, r3
+# CHECK-NEXT:  1      2     1.00                        pkhbt	r2, r2, r3, lsl #31
+# CHECK-NEXT:  1      2     1.00                        pkhbt	r2, r2, r3
+# CHECK-NEXT:  1      2     1.00                        pkhbt	r2, r2, r3, lsl #15
+# CHECK-NEXT:  1      2     1.00                        pkhbt	r2, r2, r3
+# CHECK-NEXT:  1      2     1.00                        pkhtb	r2, r2, r3, asr #31
+# CHECK-NEXT:  1      2     1.00                        pkhtb	r2, r2, r3, asr #15
+# CHECK-NEXT:  2      4     1.00    *                   pop	{r7}
+# CHECK-NEXT:  32     10    16.00   *                   pop	{r7, r8, r9, r10}
+# CHECK-NEXT:  2      1     1.00           *            push	{r7}
+# CHECK-NEXT:  2      2     1.00           *            push	{r7, r8, r9, r10}
+# CHECK-NEXT:  1      2     1.00                  U     qadd	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qaddne	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qadd16	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qadd16gt	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qadd8	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qadd8le	r1, r2, r3
+# CHECK-NEXT:  2      3     1.00                  U     qdadd	r6, r7, r8
+# CHECK-NEXT:  2      3     1.00                  U     qdaddhi	r6, r7, r8
+# CHECK-NEXT:  2      3     1.00                  U     qdsub	r6, r7, r8
+# CHECK-NEXT:  2      3     1.00                  U     qdsubhi	r6, r7, r8
+# CHECK-NEXT:  2      3     1.00                        qsax	r9, r12, r0
+# CHECK-NEXT:  2      3     1.00                        qsaxeq	r9, r12, r0
+# CHECK-NEXT:  1      2     1.00                  U     qsub	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qsubne	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qsub16	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qsub16gt	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qsub8	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                  U     qsub8le	r1, r2, r3
+# CHECK-NEXT:  1      1     0.50                        rbit	r1, r2
+# CHECK-NEXT:  1      1     0.50                        rbitne	r1, r2
+# CHECK-NEXT:  1      1     0.50                        rev	r1, r9
+# CHECK-NEXT:  1      1     0.50                        revne	r1, r5
+# CHECK-NEXT:  1      1     0.50                        rev16	r8, r3
+# CHECK-NEXT:  1      1     0.50                        rev16ne	r12, r4
+# CHECK-NEXT:  1      1     0.50                        revsh	r4, r9
+# CHECK-NEXT:  1      1     0.50                        revshne	r9, r1
+# CHECK-NEXT:  0      0     0.00                  U     rfeda	r2
+# CHECK-NEXT:  0      0     0.00                  U     rfedb	r3
+# CHECK-NEXT:  0      0     0.00                  U     rfeia	r5
+# CHECK-NEXT:  0      0     0.00                  U     rfeib	r6
+# CHECK-NEXT:  0      0     0.00                  U     rfeda	r4!
+# CHECK-NEXT:  0      0     0.00                  U     rfedb	r7!
+# CHECK-NEXT:  0      0     0.00                  U     rfeia	r9!
+# CHECK-NEXT:  0      0     0.00                  U     rfeib	r8!
+# CHECK-NEXT:  0      0     0.00                  U     rfeda	r2
+# CHECK-NEXT:  0      0     0.00                  U     rfedb	r3
+# CHECK-NEXT:  0      0     0.00                  U     rfeia	r5
+# CHECK-NEXT:  0      0     0.00                  U     rfeib	r6
+# CHECK-NEXT:  0      0     0.00                  U     rfeda	r4!
+# CHECK-NEXT:  0      0     0.00                  U     rfedb	r7!
+# CHECK-NEXT:  0      0     0.00                  U     rfeia	r9!
+# CHECK-NEXT:  0      0     0.00                  U     rfeib	r8!
+# CHECK-NEXT:  0      0     0.00                  U     rfeia	r1
+# CHECK-NEXT:  0      0     0.00                  U     rfeia	r1!
+# CHECK-NEXT:  1      1     0.50                        rsb	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        rsb	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        rsb	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                  U     rsb	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        rsblo	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, asr #5
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, ror #5
+# CHECK-NEXT:  1      2     1.00                        rsb	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        rsb	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        rsb	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        rsble	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r5, r6, rrx
+# CHECK-NEXT:  1      1     0.50                        rsb	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                  U     rsb	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rsbne	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        rsbgt	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        rsb	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        rsb	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        rsb	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     1.00                        rsb	r4, r4, r5, rrx
+# CHECK-NEXT:  1      1     0.50                        rsbs	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        rsbs	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        rsc	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        rsc	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        rsc	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                  U     rsc	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        rsclo	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r5, r6, asr #5
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r5, r6, ror #5
+# CHECK-NEXT:  1      2     1.00                        rsc	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        rsc	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        rsc	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        rscle	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      1     0.50                        rsc	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                  U     rsc	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rscne	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        rsc	r4, r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        rscgt	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        rsc	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        rsc	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        rsc	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      1     0.50                        rrx	r0, r1
+# CHECK-NEXT:  1      1     0.50                        rrx	sp, pc
+# CHECK-NEXT:  1      1     0.50                        rrx	pc, lr
+# CHECK-NEXT:  1      1     0.50                        rrx	lr, sp
+# CHECK-NEXT:  1      1     0.50                        rrxs	r0, r1
+# CHECK-NEXT:  1      1     0.50                        rrxs	sp, pc
+# CHECK-NEXT:  1      1     0.50                        rrxs	pc, lr
+# CHECK-NEXT:  1      1     0.50                        rrxs	lr, sp
+# CHECK-NEXT:  2      2     1.00    *      *      U     sadd16	r1, r2, r3
+# CHECK-NEXT:  2      2     1.00    *      *      U     sadd16gt	r1, r2, r3
+# CHECK-NEXT:  2      2     1.00    *      *      U     sadd8	r1, r2, r3
+# CHECK-NEXT:  2      2     1.00    *      *      U     sadd8le	r1, r2, r3
+# CHECK-NEXT:  2      3     1.00    *      *      U     sasx	r9, r12, r0
+# CHECK-NEXT:  2      3     1.00    *      *      U     sasxeq	r9, r12, r0
+# CHECK-NEXT:  1      1     0.50                        sbc	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        sbc	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        sbc	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        sbc	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r5, r6, asr #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r5, r6, ror #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      1     0.50                        sbc	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        sbc	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r4, r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        sbc	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      1     0.50                  U     sbfx	r4, r5, #16, #1
+# CHECK-NEXT:  1      1     0.50                  U     sbfxgt	r4, r5, #16, #16
+# CHECK-NEXT:  1      1     0.50    *                   sel	r9, r2, r1
+# CHECK-NEXT:  1      1     0.50    *                   selne	r9, r2, r1
+# CHECK-NEXT:  0      0     0.00                  U     setend	be
+# CHECK-NEXT:  0      0     0.00                  U     setend	le
+# CHECK-NEXT:  0      0     0.00    *      *      U     sev
+# CHECK-NEXT:  0      0     0.00    *      *      U     seveq
+# CHECK-NEXT:  1      2     1.00                        shadd16	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        shadd16gt	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        shadd8	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        shadd8gt	r4, r8, r2
+# CHECK-NEXT:  2      3     1.00                        shasx	r4, r8, r2
+# CHECK-NEXT:  2      3     1.00                        shasxgt	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        shsub16	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        shsub16gt	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        shsub8	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        shsub8gt	r4, r8, r2
+# CHECK-NEXT:  1      3     1.00                        smlabb	r3, r1, r9, r0
+# CHECK-NEXT:  1      3     1.00                        smlabt	r5, r6, r4, r1
+# CHECK-NEXT:  1      3     1.00                        smlatb	r4, r2, r3, r2
+# CHECK-NEXT:  1      3     1.00                        smlatt	r8, r3, r8, r4
+# CHECK-NEXT:  1      3     1.00                        smlabbge	r3, r1, r9, r0
+# CHECK-NEXT:  1      3     1.00                        smlabtle	r5, r6, r4, r1
+# CHECK-NEXT:  1      3     1.00                        smlatbne	r4, r2, r3, r2
+# CHECK-NEXT:  1      3     1.00                        smlatteq	r8, r3, r8, r4
+# CHECK-NEXT:  1      3     1.00                        smlad	r2, r3, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smladx	r2, r3, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smladeq	r2, r3, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smladxhi	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlal	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlals	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlaleq	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlalshi	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlalbb	r3, r1, r9, r0
+# CHECK-NEXT:  2      4     2.00                        smlalbt	r5, r6, r4, r1
+# CHECK-NEXT:  2      4     2.00                        smlaltb	r4, r2, r3, r2
+# CHECK-NEXT:  2      4     2.00                        smlaltt	r8, r3, r8, r4
+# CHECK-NEXT:  2      4     2.00                        smlalbbge	r3, r1, r9, r0
+# CHECK-NEXT:  2      4     2.00                        smlalbtle	r5, r6, r4, r1
+# CHECK-NEXT:  2      4     2.00                        smlaltbne	r4, r2, r3, r2
+# CHECK-NEXT:  2      4     2.00                        smlaltteq	r8, r3, r8, r4
+# CHECK-NEXT:  2      4     2.00                        smlald	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlaldx	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlaldeq	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlaldxhi	r2, r3, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smlawb	r2, r3, r10, r8
+# CHECK-NEXT:  1      3     1.00                        smlawt	r8, r3, r5, r9
+# CHECK-NEXT:  1      3     1.00                        smlawbeq	r2, r7, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smlawthi	r1, r3, r0, r8
+# CHECK-NEXT:  1      3     1.00                        smlsd	r2, r3, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smlsdx	r2, r3, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smlsdeq	r2, r3, r5, r8
+# CHECK-NEXT:  1      3     1.00                        smlsdxhi	r2, r3, r5, r8
+# CHECK-NEXT:  2      4     2.00                        smlsld	r2, r9, r5, r1
+# CHECK-NEXT:  2      4     2.00                        smlsldx	r4, r11, r2, r8
+# CHECK-NEXT:  2      4     2.00                        smlsldeq	r8, r2, r5, r6
+# CHECK-NEXT:  2      4     2.00                        smlsldxhi	r1, r0, r3, r8
+# CHECK-NEXT:  1      3     1.00                        smmla	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmlar	r4, r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                        smmlalo	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmlarhs	r4, r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                  U     smmls	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmlsr	r4, r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                  U     smmlslo	r1, r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmlsrhs	r4, r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                        smmul	r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmulr	r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                        smmullo	r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smmulrhs	r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                        smuad	r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smuadx	r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                        smuadlt	r2, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smuadxge	r3, r2, r1
+# CHECK-NEXT:  1      3     1.00                        smulbb	r3, r9, r0
+# CHECK-NEXT:  1      3     1.00                        smulbt	r5, r4, r1
+# CHECK-NEXT:  1      3     1.00                        smultb	r4, r2, r2
+# CHECK-NEXT:  1      3     1.00                        smultt	r8, r3, r4
+# CHECK-NEXT:  1      3     1.00                        smulbbge	r1, r9, r0
+# CHECK-NEXT:  1      3     1.00                        smulbtle	r5, r6, r4
+# CHECK-NEXT:  1      3     1.00                        smultbne	r2, r3, r2
+# CHECK-NEXT:  1      3     1.00                        smultteq	r8, r3, r4
+# CHECK-NEXT:  2      4     2.00                        smull	r3, r9, r0, r1
+# CHECK-NEXT:  2      4     2.00                        smulls	r3, r9, r0, r2
+# CHECK-NEXT:  2      4     2.00                        smulleq	r8, r3, r4, r5
+# CHECK-NEXT:  2      4     2.00                        smullseq	r8, r3, r4, r3
+# CHECK-NEXT:  1      3     1.00                        smulwb	r3, r9, r0
+# CHECK-NEXT:  1      3     1.00                        smulwt	r3, r9, r2
+# CHECK-NEXT:  1      3     1.00                        smusd	r3, r0, r1
+# CHECK-NEXT:  1      3     1.00                        smusdx	r3, r9, r2
+# CHECK-NEXT:  1      3     1.00                        smusdeq	r8, r3, r2
+# CHECK-NEXT:  1      3     1.00                        smusdxne	r7, r4, r3
+# CHECK-NEXT:  0      0     0.00                  U     srsda	sp, #5
+# CHECK-NEXT:  0      0     0.00                  U     srsdb	sp, #1
+# CHECK-NEXT:  0      0     0.00                  U     srsia	sp, #0
+# CHECK-NEXT:  0      0     0.00                  U     srsib	sp, #15
+# CHECK-NEXT:  0      0     0.00                  U     srsda	sp!, #31
+# CHECK-NEXT:  0      0     0.00                  U     srsdb	sp!, #19
+# CHECK-NEXT:  0      0     0.00                  U     srsia	sp!, #2
+# CHECK-NEXT:  0      0     0.00                  U     srsib	sp!, #14
+# CHECK-NEXT:  0      0     0.00                  U     srsda	sp, #11
+# CHECK-NEXT:  0      0     0.00                  U     srsdb	sp, #10
+# CHECK-NEXT:  0      0     0.00                  U     srsia	sp, #9
+# CHECK-NEXT:  0      0     0.00                  U     srsib	sp, #5
+# CHECK-NEXT:  0      0     0.00                  U     srsda	sp!, #5
+# CHECK-NEXT:  0      0     0.00                  U     srsdb	sp!, #5
+# CHECK-NEXT:  0      0     0.00                  U     srsia	sp!, #5
+# CHECK-NEXT:  0      0     0.00                  U     srsib	sp!, #5
+# CHECK-NEXT:  0      0     0.00                  U     srsia	sp, #5
+# CHECK-NEXT:  0      0     0.00                  U     srsia	sp!, #5
+# CHECK-NEXT:  1      2     1.00                        ssat	r8, #1, r10
+# CHECK-NEXT:  1      2     1.00                        ssat	r8, #1, r10, lsl #31
+# CHECK-NEXT:  1      2     1.00                        ssat	r8, #1, r10, asr #32
+# CHECK-NEXT:  1      2     1.00                        ssat	r8, #1, r10, asr #1
+# CHECK-NEXT:  1      2     1.00                        ssat16	r2, #1, r7
+# CHECK-NEXT:  1      2     1.00                        ssat16	r3, #16, r5
+# CHECK-NEXT:  2      3     1.00    *      *      U     ssax	r2, r3, r4
+# CHECK-NEXT:  2      3     1.00    *      *      U     ssaxlt	r2, r3, r4
+# CHECK-NEXT:  2      2     1.00    *      *      U     ssub16	r1, r0, r6
+# CHECK-NEXT:  2      2     1.00    *      *      U     ssub16ne	r5, r3, r2
+# CHECK-NEXT:  2      2     1.00    *      *      U     ssub8	r9, r2, r4
+# CHECK-NEXT:  2      2     1.00    *      *      U     ssub8eq	r5, r1, r2
+# CHECK-NEXT:  1      2     1.00           *            stm	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  1      2     1.00           *            stm	r3, {r1, r3, r4, r5, r6, lr}
+# CHECK-NEXT:  1      2     1.00           *            stmib	r4, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  1      2     1.00           *            stmda	r5, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  1      2     1.00           *            stmdb	r6, {r1, r3, r4, r5, r6, r8}
+# CHECK-NEXT:  1      2     1.00           *            stmdb	sp, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  2      2     1.00           *            stm	r8!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  2      2     1.00           *            stmib	r9!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  2      2     1.00           *            stmda	sp!, {r1, r3, r4, r5, r6}
+# CHECK-NEXT:  2      2     1.00           *            stmdb	r0!, {r1, r5, r7, sp}
+# CHECK-NEXT:  0      0     0.00    *      *      U     strexb	r1, r3, [r4]
+# CHECK-NEXT:  0      0     0.00    *      *      U     strexh	r4, r2, [r5]
+# CHECK-NEXT:  0      0     0.00    *      *      U     strex	r2, r1, [r7]
+# CHECK-NEXT:  0      0     0.00           *      U     strexd	r6, r2, r3, [r8]
+# CHECK-NEXT:  0      0     0.00           *      U     strexd	sp, r0, r1, [r0]
+# CHECK-NEXT:  1      1     0.50                        sub	r4, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        sub	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        sub	r7, r8, #40, #2
+# CHECK-NEXT:  1      1     0.50                        sub	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r5, r6, lsl #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r5, r6, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r5, r6, asr #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r5, r6, ror #5
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r7, r8, lsl r9
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r7, r8, lsr r9
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r7, r8, asr r9
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r7, r8, ror r9
+# CHECK-NEXT:  1      1     0.50                        sub	r5, r5, #61440
+# CHECK-NEXT:  1      1     0.50                        sub	r4, r4, r5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        sub	r4, r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        sub	r6, r6, r7, ror r9
+# CHECK-NEXT:  1      1     0.50                        subs	r7, r8, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        subs	r7, r8, #40, #2
+# CHECK-NEXT:  0      0     0.00                  U     svc	#16
+# CHECK-NEXT:  0      0     0.00                  U     svc	#0
+# CHECK-NEXT:  0      0     0.00                  U     svc	#16777215
+# CHECK-NEXT:  1      2     1.00                        sxtab	r2, r3, r4
+# CHECK-NEXT:  1      2     1.00                        sxtab	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        sxtablt	r6, r2, r9, ror #8
+# CHECK-NEXT:  1      2     1.00                        sxtab	r5, r1, r4, ror #16
+# CHECK-NEXT:  1      2     1.00                        sxtab	r7, r8, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        sxtab16ge	r0, r1, r4
+# CHECK-NEXT:  1      2     1.00                        sxtab16	r6, r2, r7
+# CHECK-NEXT:  1      2     1.00                        sxtab16	r3, r5, r8, ror #8
+# CHECK-NEXT:  1      2     1.00                        sxtab16	r3, r2, r1, ror #16
+# CHECK-NEXT:  1      2     1.00                        sxtab16eq	r1, r2, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        sxtah	r1, r3, r9
+# CHECK-NEXT:  1      2     1.00                        sxtahhi	r6, r1, r6
+# CHECK-NEXT:  1      2     1.00                        sxtah	r3, r8, r3, ror #8
+# CHECK-NEXT:  1      2     1.00                        sxtahlo	r2, r2, r4, ror #16
+# CHECK-NEXT:  1      2     1.00                        sxtah	r9, r3, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        sxtbge	r2, r4
+# CHECK-NEXT:  1      2     1.00                        sxtb	r5, r6
+# CHECK-NEXT:  1      2     1.00                        sxtb	r6, r9, ror #8
+# CHECK-NEXT:  1      2     1.00                        sxtblo	r5, r1, ror #16
+# CHECK-NEXT:  1      2     1.00                        sxtb	r8, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        sxtb16	r1, r4
+# CHECK-NEXT:  1      2     1.00                        sxtb16	r6, r7
+# CHECK-NEXT:  1      2     1.00                        sxtb16hs	r3, r5, ror #8
+# CHECK-NEXT:  1      2     1.00                        sxtb16	r3, r1, ror #16
+# CHECK-NEXT:  1      2     1.00                        sxtb16ge	r2, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        sxthne	r3, r9
+# CHECK-NEXT:  1      2     1.00                        sxth	r1, r6
+# CHECK-NEXT:  1      2     1.00                        sxth	r3, r8, ror #8
+# CHECK-NEXT:  1      2     1.00                        sxthle	r2, r2, ror #16
+# CHECK-NEXT:  1      2     1.00                        sxth	r9, r3, ror #24
+# CHECK-NEXT:  1      1     0.50                        teq	r5, #61440
+# CHECK-NEXT:  1      1     0.50                        teq	r7, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        teq	r7, #40, #2
+# CHECK-NEXT:  1      1     0.50                        teq	r4, r5
+# CHECK-NEXT:  1      2     1.00                        teq	r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        teq	r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        teq	r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        teq	r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        teq	r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        teq	r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        teq	r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        teq	r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        teq	r6, r7, ror r9
+# CHECK-NEXT:  1      1     0.50                        tst	r5, #61440
+# CHECK-NEXT:  1      1     0.50                        tst	r7, #-2147483638
+# CHECK-NEXT:  1      1     0.50                        tst	r7, #40, #2
+# CHECK-NEXT:  1      1     0.50                        tst	r4, r5
+# CHECK-NEXT:  1      2     1.00                        tst	r4, r5, lsl #5
+# CHECK-NEXT:  1      2     1.00                        tst	r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        tst	r4, r5, lsr #5
+# CHECK-NEXT:  1      2     1.00                        tst	r4, r5, asr #5
+# CHECK-NEXT:  1      2     1.00                        tst	r4, r5, ror #5
+# CHECK-NEXT:  1      2     1.00                        tst	r6, r7, lsl r9
+# CHECK-NEXT:  1      2     1.00                        tst	r6, r7, lsr r9
+# CHECK-NEXT:  1      2     1.00                        tst	r6, r7, asr r9
+# CHECK-NEXT:  1      2     1.00                        tst	r6, r7, ror r9
+# CHECK-NEXT:  2      2     1.00    *      *      U     uadd16	r1, r2, r3
+# CHECK-NEXT:  2      2     1.00    *      *      U     uadd16gt	r1, r2, r3
+# CHECK-NEXT:  2      2     1.00    *      *      U     uadd8	r1, r2, r3
+# CHECK-NEXT:  2      2     1.00    *      *      U     uadd8le	r1, r2, r3
+# CHECK-NEXT:  2      3     1.00    *      *      U     uasx	r9, r12, r0
+# CHECK-NEXT:  2      3     1.00    *      *      U     uasxeq	r9, r12, r0
+# CHECK-NEXT:  1      1     0.50                  U     ubfx	r4, r5, #16, #1
+# CHECK-NEXT:  1      1     0.50                  U     ubfxgt	r4, r5, #16, #16
+# CHECK-NEXT:  1      2     1.00                        uhadd16	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        uhadd16gt	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        uhadd8	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        uhadd8gt	r4, r8, r2
+# CHECK-NEXT:  2      3     1.00                        uhasx	r4, r8, r2
+# CHECK-NEXT:  2      3     1.00                        uhasxgt	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        uhsub16	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        uhsub16gt	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        uhsub8	r4, r8, r2
+# CHECK-NEXT:  1      2     1.00                        uhsub8gt	r4, r8, r2
+# CHECK-NEXT:  2      4     2.00                        umaal	r3, r4, r5, r6
+# CHECK-NEXT:  2      4     2.00                        umaallt	r3, r4, r5, r6
+# CHECK-NEXT:  2      4     2.00                        umlal	r2, r4, r6, r8
+# CHECK-NEXT:  2      4     2.00                        umlalgt	r6, r1, r2, r6
+# CHECK-NEXT:  2      4     2.00                        umlals	r2, r9, r2, r3
+# CHECK-NEXT:  2      4     2.00                        umlalseq	r3, r5, r1, r2
+# CHECK-NEXT:  2      4     2.00                        umull	r2, r4, r6, r8
+# CHECK-NEXT:  2      4     2.00                        umullgt	r6, r1, r2, r6
+# CHECK-NEXT:  2      4     2.00                        umulls	r2, r9, r2, r3
+# CHECK-NEXT:  2      4     2.00                        umullseq	r3, r5, r1, r2
+# CHECK-NEXT:  1      2     1.00                        uqadd16	r1, r2, r3
+# CHECK-NEXT:  1      2     1.00                        uqadd16gt	r4, r7, r9
+# CHECK-NEXT:  1      2     1.00                        uqadd8	r3, r4, r8
+# CHECK-NEXT:  1      2     1.00                        uqadd8le	r8, r1, r2
+# CHECK-NEXT:  2      3     1.00                        uqasx	r2, r4, r1
+# CHECK-NEXT:  2      3     1.00                        uqasxhi	r5, r2, r9
+# CHECK-NEXT:  2      3     1.00                        uqsax	r1, r3, r7
+# CHECK-NEXT:  2      3     1.00                        uqsax	r3, r6, r2
+# CHECK-NEXT:  1      2     1.00                        uqsub16	r1, r5, r3
+# CHECK-NEXT:  1      2     1.00                        uqsub16gt	r3, r2, r5
+# CHECK-NEXT:  1      2     1.00                        uqsub8	r2, r1, r4
+# CHECK-NEXT:  1      2     1.00                        uqsub8le	r4, r6, r9
+# CHECK-NEXT:  1      3     1.00                        usad8	r2, r1, r4
+# CHECK-NEXT:  1      3     1.00                        usad8le	r4, r6, r9
+# CHECK-NEXT:  1      3     1.00                        usada8	r1, r5, r3, r7
+# CHECK-NEXT:  1      3     1.00                        usada8gt	r3, r2, r5, r1
+# CHECK-NEXT:  1      2     1.00                        usat	r8, #1, r10
+# CHECK-NEXT:  1      2     1.00                        usat	r8, #4, r10
+# CHECK-NEXT:  1      2     1.00                        usat	r8, #5, r10, lsl #31
+# CHECK-NEXT:  1      2     1.00                        usat	r8, #31, r10, asr #32
+# CHECK-NEXT:  1      2     1.00                        usat	r8, #16, r10, asr #1
+# CHECK-NEXT:  1      2     1.00                        usat16	r2, #2, r7
+# CHECK-NEXT:  1      2     1.00                        usat16	r3, #15, r5
+# CHECK-NEXT:  2      3     1.00    *      *      U     usax	r2, r3, r4
+# CHECK-NEXT:  2      3     1.00    *      *      U     usaxne	r2, r3, r4
+# CHECK-NEXT:  2      2     1.00    *      *      U     usub16	r4, r2, r7
+# CHECK-NEXT:  2      2     1.00    *      *      U     usub16hi	r1, r1, r3
+# CHECK-NEXT:  2      2     1.00    *      *      U     usub8	r1, r8, r5
+# CHECK-NEXT:  2      2     1.00    *      *      U     usub8le	r9, r2, r3
+# CHECK-NEXT:  1      2     1.00                        uxtab	r2, r3, r4
+# CHECK-NEXT:  1      2     1.00                        uxtab	r4, r5, r6
+# CHECK-NEXT:  1      2     1.00                        uxtablt	r6, r2, r9, ror #8
+# CHECK-NEXT:  1      2     1.00                        uxtab	r5, r1, r4, ror #16
+# CHECK-NEXT:  1      2     1.00                        uxtab	r7, r8, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        uxtab16ge	r0, r1, r4
+# CHECK-NEXT:  1      2     1.00                        uxtab16	r6, r2, r7
+# CHECK-NEXT:  1      2     1.00                        uxtab16	r3, r5, r8, ror #8
+# CHECK-NEXT:  1      2     1.00                        uxtab16	r3, r2, r1, ror #16
+# CHECK-NEXT:  1      2     1.00                        uxtab16eq	r1, r2, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        uxtah	r1, r3, r9
+# CHECK-NEXT:  1      2     1.00                        uxtahhi	r6, r1, r6
+# CHECK-NEXT:  1      2     1.00                        uxtah	r3, r8, r3, ror #8
+# CHECK-NEXT:  1      2     1.00                        uxtahlo	r2, r2, r4, ror #16
+# CHECK-NEXT:  1      2     1.00                        uxtah	r9, r3, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        uxtbge	r2, r4
+# CHECK-NEXT:  1      2     1.00                        uxtb	r5, r6
+# CHECK-NEXT:  1      2     1.00                        uxtb	r6, r9, ror #8
+# CHECK-NEXT:  1      2     1.00                        uxtblo	r5, r1, ror #16
+# CHECK-NEXT:  1      2     1.00                        uxtb	r8, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        uxtb16	r1, r4
+# CHECK-NEXT:  1      2     1.00                        uxtb16	r6, r7
+# CHECK-NEXT:  1      2     1.00                        uxtb16hs	r3, r5, ror #8
+# CHECK-NEXT:  1      2     1.00                        uxtb16	r3, r1, ror #16
+# CHECK-NEXT:  1      2     1.00                        uxtb16ge	r2, r3, ror #24
+# CHECK-NEXT:  1      2     1.00                        uxthne	r3, r9
+# CHECK-NEXT:  1      2     1.00                        uxth	r1, r6
+# CHECK-NEXT:  1      2     1.00                        uxth	r3, r8, ror #8
+# CHECK-NEXT:  1      2     1.00                        uxthle	r2, r2, ror #16
+# CHECK-NEXT:  1      2     1.00                        uxth	r9, r3, ror #24
+# CHECK-NEXT:  0      0     0.00    *      *      U     wfe
+# CHECK-NEXT:  0      0     0.00    *      *      U     wfehi
+# CHECK-NEXT:  0      0     0.00    *      *      U     wfi
+# CHECK-NEXT:  0      0     0.00    *      *      U     wfilt
+# CHECK-NEXT:  0      0     0.00    *      *      U     yield
+# CHECK-NEXT:  0      0     0.00    *      *      U     yieldne
+# CHECK-NEXT:  0      0     0.00    *      *      U     sevl
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - A57UnitB
+# CHECK-NEXT: [1.0] - A57UnitI
+# CHECK-NEXT: [1.1] - A57UnitI
+# CHECK-NEXT: [2]   - A57UnitL
+# CHECK-NEXT: [3]   - A57UnitM
+# CHECK-NEXT: [4]   - A57UnitS
+# CHECK-NEXT: [5]   - A57UnitW
+# CHECK-NEXT: [6]   - A57UnitX
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
+# CHECK-NEXT: 8.00   148.50 148.50 161.00 527.00 12.00   -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #15
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #240
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #3840
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #983040
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #15728640
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #251658240
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #-268435456
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r1, r2, #-268435441
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adcs	r1, r2, #3840
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adcs	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adcseq	r1, r2, #3840
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adceq	r1, r2, #3840
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, lsl #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, lsl #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, lsr #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, lsr #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, lsr #32
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, asr #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, asr #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, asr #32
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, ror #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, ror #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r7, r8, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r5, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc	r5, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, lsl #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, lsl #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, lsr #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, lsr #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, lsr #32
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, asr #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, asr #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, asr #32
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, ror #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, ror #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, rrx
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r6, r6, r7, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc	r4, r4, r5, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     add	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     add	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     add	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     add	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r5, r6, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r5, r6, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r7, r8, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r5, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     add	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     add	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r6, r6, r7, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add	r4, r4, r5, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adds	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adds	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adr	r2, #3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r2, pc, #3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r1, pc, #0
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r1, pc, #301989888
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adr	r1, #301989888
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and	r10, r1, #15
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and	r10, r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r1, r6, lsl #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r1, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r1, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r1, r6, asr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r1, r6, ror #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r7, r8, lsl r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r7, r8, lsr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r7, r8, asr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r7, r8, ror r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r1, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and	r1, r1, #15
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and	r10, r10, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r10, r1, lsl #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r10, r1, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r10, r1, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r10, r1, asr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r10, r1, ror #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r6, r7, lsl r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r6, r7, lsr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r6, r7, asr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r6, r6, r7, ror r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and	r10, r10, r1, rrx
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bfc	r5, #3, #17
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bfclo	r5, #3, #17
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bfi	r5, r2, #3, #17
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bfine	r5, r2, #3, #17
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic	r10, r1, #15
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic	r10, r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r1, r6, lsl #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r1, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r1, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r1, r6, asr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r1, r6, ror #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r7, r8, lsl r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r7, r8, lsr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r7, r8, asr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r7, r8, ror r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r1, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic	r1, r1, #15
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic	r10, r10, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r10, r1, lsl #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r10, r1, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r10, r1, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r10, r1, asr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r10, r1, ror #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r6, r7, lsl r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r6, r7, lsr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r6, r7, asr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r6, r6, r7, ror r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic	r10, r10, r1, rrx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     bkpt	#10
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     bkpt	#65535
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     blx	r2
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     blxne	r2
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     blx	#32424576
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     blx	#16212288
+# CHECK-NEXT: 1.00    -      -      -      -      -      -      -     bx	r2
+# CHECK-NEXT: 1.00    -      -      -      -      -      -      -     bxne	r2
+# CHECK-NEXT: 1.00    -      -      -      -      -      -      -     bxj	r2
+# CHECK-NEXT: 1.00    -      -      -      -      -      -      -     bxjne	r2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     clrex
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     clz	r1, r2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     clzeq	r1, r2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmn	r1, #15
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmn	r7, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmn	r7, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmn	r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r1, r6, lsl #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r1, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	sp, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r1, r6, asr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r1, r6, ror #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r7, r8, lsl r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	sp, r8, lsr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r7, r8, asr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r7, r8, ror r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmn	r1, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmp	r1, #15
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmp	r7, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmp	r7, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     cmp	r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r1, r6, lsl #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r1, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	sp, r6, lsr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r1, r6, asr #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r1, r6, ror #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r7, r8, lsl r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	sp, r8, lsr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r7, r8, asr r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r7, r8, ror r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     cmp	r1, r6, rrx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     cpsie	aif
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     cps	#15
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     cpsid	if, #10
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     cpsid	af, #17
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     cpsie	f, #26
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dbg	#0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dbg	#5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dbg	#15
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	#0x0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	oshld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	oshst
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	osh
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	#0x4
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	nshld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	nshst
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	nsh
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	#0x8
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	ishld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	ishst
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	ish
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	#0xc
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	ld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	st
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dmb	sy
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     ssbb
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	oshld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	oshst
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	osh
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     pssbb
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	nshld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	nshst
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	nsh
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	#0x8
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	ishld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	ishst
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	ish
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	#0xc
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	ld
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	st
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb	sy
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r5, r6, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r5, r6, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r7, r8, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r5, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r6, r6, r7, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor	r4, r4, r5, rrx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     isb	sy
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     isb	#0xa
+# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldm	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmib	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmda	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -     16.00   -      -      -      -     ldmdb	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldm	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldmib	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldmda	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     ldmdb	r2!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrexb	r3, [r4]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrexh	r2, [r5]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrex	r1, [r7]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     ldrexd	r6, r7, [r8]
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mla	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mlas	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mlane	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mlasne	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mls	r2, r5, r6, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mlsne	r2, r5, r6, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	r3, #7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	r4, #4080
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	r5, #16711680
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	sp, #35
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	r9, #240, #30
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	r7, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	pc, #2147483658
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movw	r6, #65535
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movw	r9, #65535
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movw	sp, #1193
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movs	r3, #7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movs	r11, #99
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movs	r11, #240, #30
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     moveq	r4, #4080
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movseq	r5, #16711680
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mov	r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movs	r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     moveq	r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     movseq	r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     movt	r3, #7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     movt	r6, #65535
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     movt	sp, #3397
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     movteq	r4, #4080
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     mrc	p14, #0, r1, c1, c2, #4
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     mrc	p15, #7, apsr_nzcv, c15, c6, #6
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     mrs	r8, apsr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     mrs	r8, spsr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_g, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_nzcvq, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_nzcvq, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_nzcvqg, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_c, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_x, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fsx, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	SPSR_fc, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	SPSR_fsxc, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fsxc, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_nzcvq, #2147483658
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	SPSR_fsxc, #40, #2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_g, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_nzcvq, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_nzcvq, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	APSR_nzcvqg, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_c, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_x, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fc, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fsx, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	SPSR_fc, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	SPSR_fsxc, r0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     msr	CPSR_fsxc, r0
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mul	r5, r6, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     muls	r5, r6, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mulgt	r5, r6, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mulsle	r5, r6, r7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r3, #7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r4, #4080
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r5, #16711680
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r7, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r7, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvns	r3, #7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvns	r11, #240, #30
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvns	r11, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvneq	r4, #4080
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvnseq	r5, #16711680
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvns	r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r5, r6, lsl #19
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r5, r6, lsr #9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r5, r6, asr #4
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r5, r6, ror #6
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r5, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvneq	r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvnseq	r2, r3, lsl #10
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn	r5, r6, lsl r7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvns	r5, r6, lsr r7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvngt	r5, r6, asr r7
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvnslt	r5, r6, ror r7
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     nop
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     nopgt
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r5, r6, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r5, r6, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r7, r8, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r5, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r6, r6, r7, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr	r4, r4, r5, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrseq	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrne	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrseq	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrlo	r6, r7, r8, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrshi	r4, r5, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrhs	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrseq	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrne	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrslt	r6, r6, r7, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrsgt	r4, r4, r5, rrx
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt	r2, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt	r2, r2, r3, lsl #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt	r2, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt	r2, r2, r3, lsl #15
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt	r2, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb	r2, r2, r3, asr #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb	r2, r2, r3, asr #15
+# CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     pop	{r7}
+# CHECK-NEXT:  -     8.00   8.00   16.00   -      -      -      -     pop	{r7, r8, r9, r10}
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     push	{r7}
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     push	{r7, r8, r9, r10}
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qaddne	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd16	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd16gt	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd8	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qadd8le	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     qdadd	r6, r7, r8
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     qdaddhi	r6, r7, r8
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     qdsub	r6, r7, r8
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     qdsubhi	r6, r7, r8
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     qsax	r9, r12, r0
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     qsaxeq	r9, r12, r0
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qsub	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qsubne	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qsub16	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qsub16gt	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qsub8	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     qsub8le	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rbit	r1, r2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rbitne	r1, r2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rev	r1, r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     revne	r1, r5
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rev16	r8, r3
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rev16ne	r12, r4
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     revsh	r4, r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     revshne	r9, r1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeda	r2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfedb	r3
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeia	r5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeib	r6
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeda	r4!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfedb	r7!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeia	r9!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeib	r8!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeda	r2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfedb	r3
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeia	r5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeib	r6
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeda	r4!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfedb	r7!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeia	r9!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeib	r8!
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeia	r1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     rfeia	r1!
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsblo	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r5, r6, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r5, r6, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsble	r6, r7, r8, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r5, r6, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsbne	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsbgt	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r6, r6, r7, ror r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb	r4, r4, r5, rrx
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbs	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbs	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsclo	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r5, r6, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r5, r6, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscle	r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscne	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r4, r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscgt	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc	r6, r6, r7, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx	r0, r1
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx	sp, pc
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx	pc, lr
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx	lr, sp
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs	r0, r1
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs	sp, pc
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs	pc, lr
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs	lr, sp
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd16	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd16gt	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd8	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd8le	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sasx	r9, r12, r0
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sasxeq	r9, r12, r0
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r5, r6, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r5, r6, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r4, r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sbc	r6, r6, r7, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbfx	r4, r5, #16, #1
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbfxgt	r4, r5, #16, #16
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sel	r9, r2, r1
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     selne	r9, r2, r1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     setend	be
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     setend	le
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     sev
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     seveq
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shadd16	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shadd16gt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shadd8	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shadd8gt	r4, r8, r2
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     shasx	r4, r8, r2
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     shasxgt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shsub16	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shsub16gt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shsub8	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     shsub8gt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlabb	r3, r1, r9, r0
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlabt	r5, r6, r4, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlatb	r4, r2, r3, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlatt	r8, r3, r8, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlabbge	r3, r1, r9, r0
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlabtle	r5, r6, r4, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlatbne	r4, r2, r3, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlatteq	r8, r3, r8, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlad	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smladx	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smladeq	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smladxhi	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlal	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlals	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlaleq	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlalshi	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlalbb	r3, r1, r9, r0
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlalbt	r5, r6, r4, r1
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlaltb	r4, r2, r3, r2
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlaltt	r8, r3, r8, r4
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlalbbge	r3, r1, r9, r0
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlalbtle	r5, r6, r4, r1
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlaltbne	r4, r2, r3, r2
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlaltteq	r8, r3, r8, r4
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlald	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smlaldx	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlaldeq	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smlaldxhi	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlawb	r2, r3, r10, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlawt	r8, r3, r5, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlawbeq	r2, r7, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlawthi	r1, r3, r0, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlsd	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlsdx	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlsdeq	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smlsdxhi	r2, r3, r5, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlsld	r2, r9, r5, r1
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smlsldx	r4, r11, r2, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     smlsldeq	r8, r2, r5, r6
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smlsldxhi	r1, r0, r3, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmla	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmlar	r4, r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmlalo	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmlarhs	r4, r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmls	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmlsr	r4, r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmlslo	r1, r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmlsrhs	r4, r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmul	r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmulr	r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmullo	r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smmulrhs	r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smuad	r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smuadx	r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smuadlt	r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smuadxge	r3, r2, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smulbb	r3, r9, r0
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smulbt	r5, r4, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smultb	r4, r2, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smultt	r8, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smulbbge	r1, r9, r0
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smulbtle	r5, r6, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smultbne	r2, r3, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smultteq	r8, r3, r4
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smull	r3, r9, r0, r1
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smulls	r3, r9, r0, r2
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smulleq	r8, r3, r4, r5
+# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     smullseq	r8, r3, r4, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smulwb	r3, r9, r0
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smulwt	r3, r9, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smusd	r3, r0, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smusdx	r3, r9, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smusdeq	r8, r3, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     smusdxne	r7, r4, r3
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsda	sp, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsdb	sp, #1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsia	sp, #0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsib	sp, #15
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsda	sp!, #31
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsdb	sp!, #19
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsia	sp!, #2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsib	sp!, #14
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsda	sp, #11
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsdb	sp, #10
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsia	sp, #9
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsib	sp, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsda	sp!, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsdb	sp!, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsia	sp!, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsib	sp!, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsia	sp, #5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     srsia	sp!, #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     ssat	r8, #1, r10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     ssat	r8, #1, r10, lsl #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     ssat	r8, #1, r10, asr #32
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     ssat	r8, #1, r10, asr #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     ssat16	r2, #1, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     ssat16	r3, #16, r5
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     ssax	r2, r3, r4
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     ssaxlt	r2, r3, r4
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     ssub16	r1, r0, r6
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     ssub16ne	r5, r3, r2
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     ssub8	r9, r2, r4
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     ssub8eq	r5, r1, r2
+# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     stm	r2, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     stm	r3, {r1, r3, r4, r5, r6, lr}
+# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     stmib	r4, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     stmda	r5, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     stmdb	r6, {r1, r3, r4, r5, r6, r8}
+# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     stmdb	sp, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stm	r8!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stmib	r9!, {r1, r3, r4, r5, r6, sp}
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stmda	sp!, {r1, r3, r4, r5, r6}
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     stmdb	r0!, {r1, r5, r7, sp}
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     strexb	r1, r3, [r4]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     strexh	r4, r2, [r5]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     strex	r2, r1, [r7]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     strexd	r6, r2, r3, [r8]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     strexd	sp, r0, r1, [r0]
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r4, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r7, r8, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r5, r6, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r5, r6, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r5, r6, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r5, r6, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r7, r8, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r7, r8, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r7, r8, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r5, r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub	r4, r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r4, r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sub	r6, r6, r7, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     subs	r7, r8, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     subs	r7, r8, #40, #2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     svc	#16
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     svc	#0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     svc	#16777215
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab	r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtablt	r6, r2, r9, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab	r5, r1, r4, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab	r7, r8, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab16ge	r0, r1, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab16	r6, r2, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab16	r3, r5, r8, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab16	r3, r2, r1, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtab16eq	r1, r2, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtah	r1, r3, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtahhi	r6, r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtah	r3, r8, r3, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtahlo	r2, r2, r4, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtah	r9, r3, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtbge	r2, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb	r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb	r6, r9, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtblo	r5, r1, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb	r8, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb16	r1, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb16	r6, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb16hs	r3, r5, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb16	r3, r1, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxtb16ge	r2, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxthne	r3, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxth	r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxth	r3, r8, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxthle	r2, r2, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     sxth	r9, r3, ror #24
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     teq	r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     teq	r7, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     teq	r7, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     teq	r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     teq	r6, r7, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     tst	r5, #61440
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     tst	r7, #-2147483638
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     tst	r7, #40, #2
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     tst	r4, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r4, r5, lsl #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r4, r5, lsr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r4, r5, asr #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r4, r5, ror #5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r6, r7, lsl r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r6, r7, lsr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r6, r7, asr r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     tst	r6, r7, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uadd16	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uadd16gt	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uadd8	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uadd8le	r1, r2, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uasx	r9, r12, r0
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uasxeq	r9, r12, r0
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     ubfx	r4, r5, #16, #1
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     ubfxgt	r4, r5, #16, #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhadd16	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhadd16gt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhadd8	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhadd8gt	r4, r8, r2
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uhasx	r4, r8, r2
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uhasxgt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhsub16	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhsub16gt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhsub8	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uhsub8gt	r4, r8, r2
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umaal	r3, r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umaallt	r3, r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umlal	r2, r4, r6, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umlalgt	r6, r1, r2, r6
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umlals	r2, r9, r2, r3
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umlalseq	r3, r5, r1, r2
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umull	r2, r4, r6, r8
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umullgt	r6, r1, r2, r6
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umulls	r2, r9, r2, r3
+# CHECK-NEXT:  -      -      -      -     2.00    -      -      -     umullseq	r3, r5, r1, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqadd16	r1, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqadd16gt	r4, r7, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqadd8	r3, r4, r8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqadd8le	r8, r1, r2
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uqasx	r2, r4, r1
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uqasxhi	r5, r2, r9
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uqsax	r1, r3, r7
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     uqsax	r3, r6, r2
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqsub16	r1, r5, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqsub16gt	r3, r2, r5
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqsub8	r2, r1, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uqsub8le	r4, r6, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usad8	r2, r1, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usad8le	r4, r6, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usada8	r1, r5, r3, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usada8gt	r3, r2, r5, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usat	r8, #1, r10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usat	r8, #4, r10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usat	r8, #5, r10, lsl #31
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usat	r8, #31, r10, asr #32
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usat	r8, #16, r10, asr #1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usat16	r2, #2, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     usat16	r3, #15, r5
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     usax	r2, r3, r4
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     usaxne	r2, r3, r4
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     usub16	r4, r2, r7
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     usub16hi	r1, r1, r3
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     usub8	r1, r8, r5
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     usub8le	r9, r2, r3
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab	r2, r3, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab	r4, r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtablt	r6, r2, r9, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab	r5, r1, r4, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab	r7, r8, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab16ge	r0, r1, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab16	r6, r2, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab16	r3, r5, r8, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab16	r3, r2, r1, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtab16eq	r1, r2, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtah	r1, r3, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtahhi	r6, r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtah	r3, r8, r3, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtahlo	r2, r2, r4, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtah	r9, r3, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtbge	r2, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb	r5, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb	r6, r9, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtblo	r5, r1, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb	r8, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb16	r1, r4
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb16	r6, r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb16hs	r3, r5, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb16	r3, r1, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxtb16ge	r2, r3, ror #24
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxthne	r3, r9
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxth	r1, r6
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxth	r3, r8, ror #8
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxthle	r2, r2, ror #16
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     uxth	r9, r3, ror #24
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     wfe
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     wfehi
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     wfi
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     wfilt
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     yield
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     yieldne
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     sevl
diff --git a/llvm/test/tools/llvm-readobj/ELF/hash-table.test b/llvm/test/tools/llvm-readobj/ELF/hash-table.test
index b8d44e3cdf7191..cdb7581b1174e3 100644
--- a/llvm/test/tools/llvm-readobj/ELF/hash-table.test
+++ b/llvm/test/tools/llvm-readobj/ELF/hash-table.test
@@ -18,16 +18,17 @@
 
 --- !ELF
 FileHeader:
-  Class:   ELFCLASS[[BITS]]
+  Class:   ELFCLASS[[BITS=64]]
   Data:    ELFDATA2LSB
   Type:    ET_DYN
   Machine: [[MACHINE]]
 Sections:
-  - Name:   .hash
-    Type:   SHT_HASH
-    Flags:  [ SHF_ALLOC ]
-    Bucket: [ 1, 2 ]
-    Chain:  [ 3, 4, 5 ]
+  - Name:    .hash
+    Type:    SHT_HASH
+    Flags:   [ SHF_ALLOC ]
+    Bucket:  [ 1, 2 ]
+    Chain:   [ 3, 4, 5 ]
+    EntSize: [[ENTSIZE=4]]
   - Name:  .dynamic
     Type:  SHT_DYNAMIC
     Flags: [ SHF_ALLOC ]
@@ -42,6 +43,43 @@ ProgramHeaders:
       - Section: .hash
       - Section: .dynamic
 
+## Document that we ignore the sh_entsize value when dumping the hash section.
+## Implementation assumes that the size of entries is 4, matching the ELF specification.
+
+# RUN: yaml2obj --docnum=1 -DENTSIZE=8 -DBITS=64 -DMACHINE=EM_X86_64 %s -o %t.x64.ent8
+# RUN: yaml2obj --docnum=1 -DENTSIZE=8 -DBITS=32 -DMACHINE=EM_386 %s -o %t.x32.ent8
+
+# RUN: llvm-readobj --hash-table %t.x64.ent8 | FileCheck %s --check-prefix=HASH
+# RUN: llvm-readelf --hash-table %t.x64.ent8 | FileCheck %s --check-prefix=HASH
+# RUN: llvm-readobj --hash-table %t.x32.ent8 | FileCheck %s --check-prefix=HASH
+# RUN: llvm-readelf --hash-table %t.x32.ent8 | FileCheck %s --check-prefix=HASH
+
+## We don't support dumping hash tables on EM_S390 and EM_ALPHA platforms and report a warning.
+## On these platforms the size of entries is 8, which violates the ELF specification, which says that the size
+## of hash entries in the hash table must be 4.
+
+# RUN: yaml2obj --docnum=1 -DMACHINE=EM_S390 %s -o %t.s390
+# RUN: llvm-readobj --hash-table %t.s390 2>&1 | FileCheck %s -DFILE=%t.s390 --check-prefixes=WARN-HASH -DNAME="IBM S/390"
+# RUN: llvm-readelf --hash-table %t.s390 2>&1 | FileCheck %s -DFILE=%t.s390 --check-prefixes=WARN-HASH -DNAME="IBM S/390"
+
+# WARN-HASH:      HashTable {
+# WARN-HASH-NEXT: warning: '[[FILE]]': the hash table at 0x78 is not supported: it contains non-standard 8 byte entries on [[NAME]] platform
+# WARN-HASH-NEXT: }
+
+# RUN: yaml2obj --docnum=1 -DMACHINE=EM_ALPHA %s -o %t.alpha
+# RUN: llvm-readobj --hash-table %t.alpha 2>&1 | FileCheck %s -DFILE=%t.alpha --check-prefixes=WARN-HASH -DNAME="EM_ALPHA"
+# RUN: llvm-readelf --hash-table %t.alpha 2>&1 | FileCheck %s -DFILE=%t.alpha --check-prefixes=WARN-HASH -DNAME="EM_ALPHA"
+
+## We don't report warnings about the unsupported hash table on EM_S390 and EM_ALPHA platforms
+## when --hash-table is not requested.
+
+# RUN: llvm-readobj %t.s390 2>&1 | FileCheck %s -DFILE=%t.s390 --implicit-check-not="warning:"  --check-prefix=NOWARN
+# RUN: llvm-readelf %t.s390 2>&1 | FileCheck %s -DFILE=%t.s390 --implicit-check-not="warning:"  --check-prefix=NOWARN
+# RUN: llvm-readobj %t.alpha 2>&1 | FileCheck %s -DFILE=%t.alpha --implicit-check-not="warning:" --check-prefix=NOWARN
+# RUN: llvm-readelf %t.alpha 2>&1 | FileCheck %s -DFILE=%t.alpha --implicit-check-not="warning:" --check-prefix=NOWARN
+
+# NOWARN: warning: '[[FILE]]': string table was not found
+
 ## Check we can dump the SHT_HASH section even when an object
 ## does not have the section header table.
 
diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp
index 88437000a88f26..e7ee0793b903ab 100644
--- a/llvm/tools/llvm-readobj/ELFDumper.cpp
+++ b/llvm/tools/llvm-readobj/ELFDumper.cpp
@@ -328,6 +328,15 @@ template <typename ELFT> class ELFDumper : public ObjDumper {
   std::string describe(const Elf_Shdr &Sec) const;
 
 public:
+  unsigned getHashTableEntSize() const {
+    // EM_S390 and ELF::EM_ALPHA platforms use 8-bytes entries in SHT_HASH
+    // sections. This violates the ELF specification.
+    if (Obj.getHeader().e_machine == ELF::EM_S390 ||
+        Obj.getHeader().e_machine == ELF::EM_ALPHA)
+      return 8;
+    return 4;
+  }
+
   Elf_Dyn_Range dynamic_table() const {
     // A valid .dynamic section contains an array of entries terminated
     // with a DT_NULL entry. However, sometimes the section content may
@@ -2176,6 +2185,7 @@ void ELFDumper<ELFT>::parseDynamicTable() {
 
   SOName = getDynamicString(SONameOffset);
 
+  const bool IsHashTableSupported = getHashTableEntSize() == 4;
   if (DynSymRegion) {
     // Often we find the information about the dynamic symbol table
     // location in the SHT_DYNSYM section header. However, the value in
@@ -2191,7 +2201,7 @@ void ELFDumper<ELFT>::parseDynamicTable() {
     // equal nchain". Check to see if the DT_HASH hash table nchain value
     // conflicts with the number of symbols in the dynamic symbol table
     // according to the section header.
-    if (HashTable) {
+    if (HashTable && IsHashTableSupported) {
       if (DynSymRegion->EntSize == 0)
         reportUniqueWarning(
             createError("SHT_DYNSYM section has sh_entsize == 0"));
@@ -2219,7 +2229,7 @@ void ELFDumper<ELFT>::parseDynamicTable() {
 
   // Derive the dynamic symbol table size from the DT_HASH hash table, if
   // present.
-  if (HashTable && DynSymRegion) {
+  if (HashTable && IsHashTableSupported && DynSymRegion) {
     const uint64_t FileSize = Obj.getBufSize();
     const uint64_t DerivedSize =
         (uint64_t)HashTable->nchain * DynSymRegion->EntSize;
@@ -2653,29 +2663,43 @@ template <class ELFT> void ELFDumper<ELFT>::printNeededLibraries() {
 }
 
 template <class ELFT>
-static Error checkHashTable(const ELFFile<ELFT> &Obj,
+static Error checkHashTable(const ELFDumper<ELFT> &Dumper,
                             const typename ELFT::Hash *H,
                             bool *IsHeaderValid = nullptr) {
-  auto MakeError = [&](uint64_t Off, const Twine &Msg = "") {
-    return createError("the hash table at offset 0x" + Twine::utohexstr(Off) +
+  const ELFFile<ELFT> &Obj = *Dumper.getElfObject().getELFFile();
+  const uint64_t SecOffset = (const uint8_t *)H - Obj.base();
+  if (Dumper.getHashTableEntSize() == 8) {
+    auto It = llvm::find_if(ElfMachineType, [&](const EnumEntry<unsigned> &E) {
+      return E.Value == Obj.getHeader().e_machine;
+    });
+    if (IsHeaderValid)
+      *IsHeaderValid = false;
+    return createError("the hash table at 0x" + Twine::utohexstr(SecOffset) +
+                       " is not supported: it contains non-standard 8 "
+                       "byte entries on " +
+                       It->AltName + " platform");
+  }
+
+  auto MakeError = [&](const Twine &Msg = "") {
+    return createError("the hash table at offset 0x" +
+                       Twine::utohexstr(SecOffset) +
                        " goes past the end of the file (0x" +
                        Twine::utohexstr(Obj.getBufSize()) + ")" + Msg);
   };
 
   // Each SHT_HASH section starts from two 32-bit fields: nbucket and nchain.
   const unsigned HeaderSize = 2 * sizeof(typename ELFT::Word);
-  const uint64_t SecOffset = (const uint8_t *)H - Obj.base();
 
   if (IsHeaderValid)
     *IsHeaderValid = Obj.getBufSize() - SecOffset >= HeaderSize;
 
   if (Obj.getBufSize() - SecOffset < HeaderSize)
-    return MakeError(SecOffset);
+    return MakeError();
 
   if (Obj.getBufSize() - SecOffset - HeaderSize <
       ((uint64_t)H->nbucket + H->nchain) * sizeof(typename ELFT::Word))
-    return MakeError(SecOffset, ", nbucket = " + Twine(H->nbucket) +
-                                    ", nchain = " + Twine(H->nchain));
+    return MakeError(", nbucket = " + Twine(H->nbucket) +
+                     ", nchain = " + Twine(H->nchain));
   return Error::success();
 }
 
@@ -2706,7 +2730,7 @@ template <typename ELFT> void ELFDumper<ELFT>::printHashTable() {
     return;
 
   bool IsHeaderValid;
-  Error Err = checkHashTable(Obj, HashTable, &IsHeaderValid);
+  Error Err = checkHashTable(*this, HashTable, &IsHeaderValid);
   if (IsHeaderValid) {
     W.printNumber("Num Buckets", HashTable->nbucket);
     W.printNumber("Num Chains", HashTable->nchain);
@@ -4112,7 +4136,7 @@ void GNUStyle<ELFT>::printGnuHashTableSymbols(const Elf_GnuHash &GnuHash) {
 template <class ELFT> void GNUStyle<ELFT>::printHashSymbols() {
   if (const Elf_Hash *SysVHash = this->dumper().getHashTable()) {
     OS << "\n Symbol table of .hash for image:\n";
-    if (Error E = checkHashTable<ELFT>(this->Obj, SysVHash))
+    if (Error E = checkHashTable<ELFT>(this->dumper(), SysVHash))
       this->reportUniqueWarning(std::move(E));
     else
       printHashTableSymbols(*SysVHash);
@@ -4742,7 +4766,7 @@ void GNUStyle<ELFT>::printGnuHashHistogram(const Elf_GnuHash &GnuHashTable) {
 template <class ELFT> void GNUStyle<ELFT>::printHashHistograms() {
   // Print histogram for the .hash section.
   if (const Elf_Hash *HashTable = this->dumper().getHashTable()) {
-    if (Error E = checkHashTable<ELFT>(this->Obj, HashTable))
+    if (Error E = checkHashTable<ELFT>(this->dumper(), HashTable))
       this->reportUniqueWarning(std::move(E));
     else
       printHashHistogram(*HashTable);
diff --git a/llvm/unittests/Support/JSONTest.cpp b/llvm/unittests/Support/JSONTest.cpp
index 9f17c98b4db40c..ed9a72d36b0647 100644
--- a/llvm/unittests/Support/JSONTest.cpp
+++ b/llvm/unittests/Support/JSONTest.cpp
@@ -375,10 +375,8 @@ inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS,
 }
 bool fromJSON(const Value &E, CustomStruct &R, Path P) {
   ObjectMapper O(E, P);
-  if (!O || !O.map("str", R.S) || !O.map("int", R.I))
-    return false;
-  O.map("bool", R.B);
-  return true;
+  return O && O.map("str", R.S) && O.map("int", R.I) &&
+         O.mapOptional("bool", R.B);
 }
 
 static std::string errorContext(const Value &V, const Path::Root &R) {
@@ -392,24 +390,18 @@ TEST(JSONTest, Deserialize) {
   std::map<std::string, std::vector<CustomStruct>> R;
   CustomStruct ExpectedStruct = {"foo", 42, true};
   std::map<std::string, std::vector<CustomStruct>> Expected;
-  Value J = Object{
-      {"foo",
-       Array{
-           Object{
-               {"str", "foo"},
-               {"int", 42},
-               {"bool", true},
-               {"unknown", "ignored"},
-           },
-           Object{{"str", "bar"}},
-           Object{
-               {"str", "baz"}, {"bool", "string"}, // OK, deserialize ignores.
-           },
-       }}};
+  Value J = Object{{"foo", Array{
+                               Object{
+                                   {"str", "foo"},
+                                   {"int", 42},
+                                   {"bool", true},
+                                   {"unknown", "ignored"},
+                               },
+                               Object{{"str", "bar"}},
+                           }}};
   Expected["foo"] = {
       CustomStruct("foo", 42, true),
       CustomStruct("bar", llvm::None, false),
-      CustomStruct("baz", llvm::None, false),
   };
   Path::Root Root("CustomStruct");
   ASSERT_TRUE(fromJSON(J, R, Root));
@@ -423,7 +415,6 @@ TEST(JSONTest, Deserialize) {
   "foo": [
     /* error: expected object */
     123,
-    { ... },
     { ... }
   ]
 })";
@@ -443,6 +434,10 @@ TEST(JSONTest, Deserialize) {
   // Optional<T> must parse as the correct type if present.
   EXPECT_FALSE(fromJSON(Object{{"str", "1"}, {"int", "string"}}, V, Root));
   EXPECT_EQ("expected integer at CustomStruct.int", toString(Root.getError()));
+
+  // mapOptional must parse as the correct type if present.
+  EXPECT_FALSE(fromJSON(Object{{"str", "1"}, {"bool", "string"}}, V, Root));
+  EXPECT_EQ("expected boolean at CustomStruct.bool", toString(Root.getError()));
 }
 
 TEST(JSONTest, ParseDeserialize) {
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 4d3e9ec9cb8469..af5e213724b89d 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -786,9 +786,6 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
     IS.ParamTypeDefs.push_back(TyEl);
   }
 
-  // Set default properties to true.
-  setDefaultProperties(R, DefaultProperties);
-
   // Parse the intrinsic properties.
   ListInit *PropList = R->getValueAsListInit("IntrProperties");
   for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
@@ -799,6 +796,9 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
     setProperty(Property);
   }
 
+  // Set default properties to true.
+  setDefaultProperties(R, DefaultProperties);
+
   // Also record the SDPatternOperator Properties.
   Properties = parseSDPatternOperatorProperties(R);
 
@@ -845,7 +845,7 @@ void CodeGenIntrinsic::setProperty(Record *R) {
   else if (R->getName() == "IntrNoFree")
     isNoFree = true;
   else if (R->getName() == "IntrWillReturn")
-    isWillReturn = true;
+    isWillReturn = !isNoReturn;
   else if (R->getName() == "IntrCold")
     isCold = true;
   else if (R->getName() == "IntrSpeculatable")
diff --git a/llvm/utils/gn/secondary/clang-tools-extra/clangd/support/BUILD.gn b/llvm/utils/gn/secondary/clang-tools-extra/clangd/support/BUILD.gn
index e855accbb241b7..06a063fcbf608d 100644
--- a/llvm/utils/gn/secondary/clang-tools-extra/clangd/support/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang-tools-extra/clangd/support/BUILD.gn
@@ -13,6 +13,7 @@ static_library("support") {
     "Context.cpp",
     "Logger.cpp",
     "Markup.cpp",
+    "MemoryTree.cpp",
     "Shutdown.cpp",
     "Threading.cpp",
     "ThreadsafeFS.cpp",
diff --git a/llvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn b/llvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
index 409eaf8105a1d6..8872b36e4a8941 100644
--- a/llvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
@@ -105,6 +105,7 @@ unittest("ClangdTests") {
     "support/ContextTests.cpp",
     "support/FunctionTests.cpp",
     "support/MarkupTests.cpp",
+    "support/MemoryTreeTests.cpp",
     "support/TestTracer.cpp",
     "support/ThreadingTests.cpp",
     "support/TraceTests.cpp",
diff --git a/mlir/docs/Tutorials/QuickstartRewrites.md b/mlir/docs/Tutorials/QuickstartRewrites.md
index fbc2406a0f317f..447f8a62f91eb0 100644
--- a/mlir/docs/Tutorials/QuickstartRewrites.md
+++ b/mlir/docs/Tutorials/QuickstartRewrites.md
@@ -155,7 +155,7 @@ add_public_tablegen_target(<name-of-the-cmake-target>)
 Then you can `#include` the generated file in any C++ implementation file you
 like. (You will also need to make sure the library depends on the CMake target
 defined in the above.) The generated file will have a `populateWithGenerated(
-MLIRContext *context, OwningRewritePatternList *patterns)` function that you can
+MLIRContext *context, OwningRewritePatternList &patterns)` function that you can
 use to collect all the generated patterns inside `patterns` and then use
 `patterns` in any pass you would like.
 
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
index 2332f516c44ad4..55df0bccbb64af 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
+++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
@@ -39,7 +39,7 @@ def StructuredOpTraits : NativeOpTrait<"linalg::StructuredOpTraits">;
 def NamedStructuredOpTrait : NativeOpTrait<"linalg::NamedStructuredOpTrait">;
 
 // Base Tablegen class for Linalg ops.
-// Linalg ops that correspond to library calls operate on linalg::View as their
+// Linalg ops that correspond to library calls operate on ShapedType as their
 // first operands. These may be optionally followed by non-view operands
 // depending on the specific Linalg op.
 class LinalgStructuredBase_Op<string mnemonic, list<OpTrait> props>
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
index dbb89c73954b7b..845873ff83dfea 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
+++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
@@ -628,7 +628,9 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
     InterfaceMethod<
       /*desc=*/[{
         Clone the current operation with the given location and operands. This
-        is used to abstract away the optional underlying region creation.
+        is used to abstract away the optional underlying region creation. This 
+        does not change the balance between input, output_buffer and 
+        init_tensors operands.
       }],
       /*retTy=*/"Operation *",
       /*methodName=*/"clone",
@@ -666,6 +668,23 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       }
       return res;
     }
+    //========================================================================//
+    // Helper functions to mutate the `operand_segment_sizes` attribute.
+    // These are useful when cloning and changing operand types.
+    //========================================================================//
+    void setNumInputs(unsigned num) { setOperandSegmentAt(0, num); }
+    void setNumOutputBuffers(unsigned num) { setOperandSegmentAt(1, num); }
+    void setNumInitTensors(unsigned num) { setOperandSegmentAt(2, num); }
+
+    private:
+    void setOperandSegmentAt(unsigned idx, unsigned val) {
+      auto attr = getOperation()->getAttr("operand_segment_sizes")
+        .cast<DenseIntElementsAttr>();
+      unsigned i = 0;
+      auto newAttr = attr.mapValues(IntegerType::get(32, getContext()),
+        [&](const APInt &v) { return (i++ == idx) ? APInt(32, val) : v; });
+      getOperation()->setAttr("operand_segment_sizes", newAttr);
+    }
   }];
 }
 
diff --git a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
index 7512f69608a4b7..a2dee8c3ae6554 100644
--- a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
+++ b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
@@ -13,6 +13,7 @@
 #include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/IR/Identifier.h"
 #include "mlir/IR/PatternMatch.h"
+#include "mlir/Transforms/Bufferize.h"
 #include "llvm/ADT/SmallBitVector.h"
 
 namespace mlir {
@@ -51,8 +52,8 @@ void populateConvVectorizationPatterns(
 /// Populates the given list with patterns to convert Linalg operations on
 /// tensors to buffers.
 void populateConvertLinalgOnTensorsToBuffersPatterns(
-    MLIRContext *context, BufferAssignmentTypeConverter *converter,
-    OwningRewritePatternList *patterns);
+    MLIRContext *context, BufferAssignmentTypeConverter &converter,
+    OwningRewritePatternList &patterns);
 
 /// Performs standalone tiling of a single LinalgOp by `tileSizes`.
 /// and permute the loop nest according to `interchangeVector`
@@ -797,6 +798,46 @@ class IndexedGenericOpToLibraryCallRewrite
 void populateLinalgToStandardConversionPatterns(
     OwningRewritePatternList &patterns, MLIRContext *ctx);
 
+//===----------------------------------------------------------------------===//
+// Buffer allocation patterns.
+//===----------------------------------------------------------------------===//
+
+/// Generic BufferAssignmentConversionPattern that matches any Operation* and
+/// dispatches internally. This avoids template instantiating one pattern for
+/// each LinalgOp op.
+class LinalgOpConverter : public BufferAssignmentConversionPattern {
+public:
+  LinalgOpConverter(MLIRContext *context,
+                    BufferAssignmentTypeConverter &converter)
+      : BufferAssignmentConversionPattern(context, converter) {}
+
+  LogicalResult
+  matchAndRewrite(Operation *op, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const final;
+};
+
+class TensorConstantOpConverter
+    : public BufferAssignmentOpConversionPattern<ConstantOp> {
+public:
+  using BufferAssignmentOpConversionPattern<
+      ConstantOp>::BufferAssignmentOpConversionPattern;
+
+  LogicalResult
+  matchAndRewrite(ConstantOp op, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const final;
+};
+
+class TensorCastOpConverter
+    : public BufferAssignmentOpConversionPattern<TensorCastOp> {
+public:
+  using BufferAssignmentOpConversionPattern<
+      TensorCastOp>::BufferAssignmentOpConversionPattern;
+
+  LogicalResult
+  matchAndRewrite(TensorCastOp op, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const final;
+};
+
 //===----------------------------------------------------------------------===//
 // Support for staged pattern application.
 //===----------------------------------------------------------------------===//
diff --git a/mlir/include/mlir/Dialect/Shape/Transforms/Passes.h b/mlir/include/mlir/Dialect/Shape/Transforms/Passes.h
index 72816b72f41e6e..81f64dc3ccb3b5 100644
--- a/mlir/include/mlir/Dialect/Shape/Transforms/Passes.h
+++ b/mlir/include/mlir/Dialect/Shape/Transforms/Passes.h
@@ -41,8 +41,8 @@ void populateRemoveShapeConstraintsPatterns(OwningRewritePatternList &patterns,
 std::unique_ptr<FunctionPass> createRemoveShapeConstraintsPass();
 
 void populateShapeTypeConversionPatterns(
-    MLIRContext *ctx, BufferAssignmentTypeConverter *converter,
-    OwningRewritePatternList *patterns);
+    MLIRContext *ctx, BufferAssignmentTypeConverter &converter,
+    OwningRewritePatternList &patterns);
 // Collects a set of patterns to replace tensors as inputs and outputs to shape
 // operations with buffers. This only modifies the shape operations.
 std::unique_ptr<FunctionPass> createShapeTensorToMemrefPass();
diff --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td
index eaaf5b75230ead..c701f078750773 100644
--- a/mlir/include/mlir/IR/OpBase.td
+++ b/mlir/include/mlir/IR/OpBase.td
@@ -791,12 +791,16 @@ class Attr<Pred condition, string descr = ""> :
   // instantiation.
   // TOOD(b/132458159): deduplicate the fields in attribute wrapper classes.
   Attr baseAttr = ?;
+
+  // The fully-qualified C++ namespace where the generated class lives.
+  string cppNamespace = "";
 }
 
 // An attribute of a specific dialect.
 class DialectAttr<Dialect d, Pred condition, string descr = ""> :
     Attr<condition, descr> {
   Dialect dialect = d;
+  let cppNamespace = d.cppNamespace;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1115,16 +1119,6 @@ class EnumAttrInfo<string name, list<EnumAttrCaseInfo> cases> {
   // underlying type is not explicitly specified.
   string underlyingType = "";
 
-  // The C++ namespaces that the enum class definition and utility functions
-  // should be placed into.
-  //
-  // Normally you want to place the full namespace path here. If it is nested,
-  // use "::" as the delimiter, e.g., given "A::B", generated code will be
-  // placed in `namespace A { namespace B { ... } }`. To avoid placing in any
-  // namespace, use "".
-  // TODO: use dialect to provide the namespace.
-  string cppNamespace = "";
-
   // The name of the utility function that converts a value of the underlying
   // type to the corresponding symbol. It will have the following signature:
   //
@@ -1463,7 +1457,8 @@ class StructFieldAttr<string thisName, Attr thisType> {
 // useful when representing data that would normally be in a structure.
 class StructAttr<string name, Dialect d,
                  list<StructFieldAttr> attributes> :
-    DictionaryAttrBase<CPred<"$_self.isa<" # name # ">()">,
+    DictionaryAttrBase<CPred<"$_self.isa<" # d.cppNamespace
+                                           # "::" # name # ">()">,
         "DictionaryAttr with field(s): " #
         StrJoin<!foreach(a, attributes, "'" # a.name # "'"), ", ">.result #
         " (each field having its own constraints)"> {
@@ -1471,14 +1466,16 @@ class StructAttr<string name, Dialect d,
   string className = name;
 
   // Return type should match the name of the structure.
-  let returnType = name;
+  let returnType = d.cppNamespace # "::" # name;
 
   // Storage type should match the name of the structure.
-  let storageType = name;
+  let storageType = d.cppNamespace # "::" # name;
 
   // The dialect this StructAttr belongs to.
   Dialect dialect = d;
 
+  let cppNamespace = d.cppNamespace;
+
   // List of fields that the StructAttr contains.
   list<StructFieldAttr> fields = attributes;
 }
diff --git a/mlir/include/mlir/Transforms/Bufferize.h b/mlir/include/mlir/Transforms/Bufferize.h
index e8fffcfe492576..26452e9db51309 100644
--- a/mlir/include/mlir/Transforms/Bufferize.h
+++ b/mlir/include/mlir/Transforms/Bufferize.h
@@ -140,14 +140,28 @@ class BufferAssignmentOpConversionPattern
     : public OpConversionPattern<SourceOp> {
 public:
   explicit BufferAssignmentOpConversionPattern(
-      MLIRContext *context, BufferAssignmentTypeConverter *converter,
+      MLIRContext *context, BufferAssignmentTypeConverter &converter,
       PatternBenefit benefit = 1)
-      : OpConversionPattern<SourceOp>(context, benefit), converter(converter) {
-    assert(converter && "The type converter has not been defined");
-  }
+      : OpConversionPattern<SourceOp>(context, benefit), converter(converter) {}
+
+protected:
+  BufferAssignmentTypeConverter &converter;
+};
+
+/// Helper conversion pattern that encapsulates a BufferAssignmentTypeConverter
+/// instance and that operates on Operation* to be compatible with OpInterfaces.
+/// This allows avoiding to instantiate N patterns for ops that can be subsumed
+/// by a single op interface (e.g. Linalg named ops).
+class BufferAssignmentConversionPattern : public ConversionPattern {
+public:
+  explicit BufferAssignmentConversionPattern(
+      MLIRContext *context, BufferAssignmentTypeConverter &converter,
+      PatternBenefit benefit = 1)
+      : ConversionPattern(benefit, converter, MatchAnyOpTypeTag()),
+        converter(converter) {}
 
 protected:
-  BufferAssignmentTypeConverter *converter;
+  BufferAssignmentTypeConverter &converter;
 };
 
 /// Converts the signature of the function using BufferAssignmentTypeConverter.
@@ -191,15 +205,15 @@ class BufferAssignmentReturnOpConverter
     OpBuilder builder(returnOp);
     for (auto operand : llvm::enumerate(operands)) {
       SmallVector<Value, 2> values;
-      this->converter->tryDecomposeValue(
-          builder, loc, operand.value().getType(), operand.value(), values);
+      this->converter.tryDecomposeValue(builder, loc, operand.value().getType(),
+                                        operand.value(), values);
       Type type = returnOp.getOperand(operand.index()).getType();
       SmallVector<Type, 2> originTypes;
-      this->converter->tryDecomposeType(type, originTypes);
+      this->converter.tryDecomposeType(type, originTypes);
       for (auto value : llvm::enumerate(values)) {
         Type origin = originTypes[value.index()];
         Type converted = value.value().getType();
-        auto kind = this->converter->getResultConversionKind(origin, converted);
+        auto kind = this->converter.getResultConversionKind(origin, converted);
         if (kind == BufferAssignmentTypeConverter::KeepAsFunctionResult)
           newOperands.push_back(value.value());
         else
@@ -247,10 +261,10 @@ class BufferAssignmentCallOpConverter
 template <typename ReturnOpSourceTy, typename ReturnOpTargetTy,
           typename CopyOpTy>
 static void populateWithBufferAssignmentOpConversionPatterns(
-    MLIRContext *context, BufferAssignmentTypeConverter *converter,
-    OwningRewritePatternList *patterns) {
+    MLIRContext *context, BufferAssignmentTypeConverter &converter,
+    OwningRewritePatternList &patterns) {
   // clang-format off
-  patterns->insert<
+  patterns.insert<
     BufferAssignmentCallOpConverter,
     BufferAssignmentFuncOpConverter,
     BufferAssignmentReturnOpConverter
diff --git a/mlir/integration_test/Dialect/Linalg/CPU/test-tensor-matmul.mlir b/mlir/integration_test/Dialect/Linalg/CPU/test-tensor-matmul.mlir
new file mode 100644
index 00000000000000..2c01a688cfa02e
--- /dev/null
+++ b/mlir/integration_test/Dialect/Linalg/CPU/test-tensor-matmul.mlir
@@ -0,0 +1,27 @@
+// RUN: mlir-opt %s -convert-linalg-on-tensors-to-buffers -convert-linalg-to-loops -convert-linalg-to-llvm -convert-std-to-llvm | \
+// RUN: mlir-cpu-runner -e main -entry-point-result=void \
+// RUN:   -shared-libs=%mlir_integration_test_dir/libmlir_runner_utils%shlibext \
+// RUN: | FileCheck %s
+
+func @main() {
+  %A = constant dense<[[1.0, 2.0, 3.0], [4.0, 5.0, 6.0]]> : tensor<2x3xf32>
+  %B = constant dense<[[1.0, 2.0, 3.0, 4.0],
+                       [5.0, 6.0, 7.0, 8.0],
+                       [9.0, 10.0, 11.0, 12.0]]> : tensor<3x4xf32>
+  %C = constant dense<1000.0> : tensor<2x4xf32>
+
+  %D = linalg.matmul ins(%A, %B: tensor<2x3xf32>, tensor<3x4xf32>)
+                     init(%C: tensor<2x4xf32>) -> tensor<2x4xf32>
+
+  %unranked = tensor_cast %D : tensor<2x4xf32> to tensor<*xf32>
+  call @print_memref_f32(%unranked) : (tensor<*xf32>) -> ()
+
+  //      CHECK: Unranked Memref base@ = {{0x[-9a-f]*}}
+  // CHECK-SAME: rank = 2 offset = 0 sizes = [2, 4] strides = [4, 1] data =
+  // CHECK-NEXT: [1038,   1044,   1050,   1056]
+  // CHECK-NEXT: [1065,   1074,   1083,   1092]
+
+  return
+}
+
+func @print_memref_f32(%ptr : tensor<*xf32>)
diff --git a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
index b25c2643f52ed2..f7f5834e6351e2 100644
--- a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
+++ b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
@@ -113,10 +113,28 @@ class ConvertOpToGpuRuntimeCallPattern : public ConvertOpToLLVMPattern<OpTy> {
       }};
   FunctionCallBuilder streamCreateCallBuilder = {
       "mgpuStreamCreate", llvmPointerType /* void *stream */, {}};
+  FunctionCallBuilder streamDestroyCallBuilder = {
+      "mgpuStreamDestroy", llvmVoidType, {llvmPointerType /* void *stream */}};
   FunctionCallBuilder streamSynchronizeCallBuilder = {
       "mgpuStreamSynchronize",
       llvmVoidType,
       {llvmPointerType /* void *stream */}};
+  FunctionCallBuilder streamWaitEventCallBuilder = {
+      "mgpuStreamWaitEvent",
+      llvmVoidType,
+      {llvmPointerType /* void *stream */, llvmPointerType /* void *event */}};
+  FunctionCallBuilder eventCreateCallBuilder = {
+      "mgpuEventCreate", llvmPointerType /* void *event */, {}};
+  FunctionCallBuilder eventDestroyCallBuilder = {
+      "mgpuEventDestroy", llvmVoidType, {llvmPointerType /* void *event */}};
+  FunctionCallBuilder eventSynchronizeCallBuilder = {
+      "mgpuEventSynchronize",
+      llvmVoidType,
+      {llvmPointerType /* void *event */}};
+  FunctionCallBuilder eventRecordCallBuilder = {
+      "mgpuEventRecord",
+      llvmVoidType,
+      {llvmPointerType /* void *event */, llvmPointerType /* void *stream */}};
   FunctionCallBuilder hostRegisterCallBuilder = {
       "mgpuMemHostRegisterMemRef",
       llvmVoidType,
diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
index d11cc51d1d594f..69786823dd3202 100644
--- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
+++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
@@ -152,7 +152,7 @@ struct LowerGpuOpsToNVVMOpsPass
 
 void mlir::populateGpuToNVVMConversionPatterns(
     LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
-  populateWithGenerated(converter.getDialect()->getContext(), &patterns);
+  populateWithGenerated(converter.getDialect()->getContext(), patterns);
   patterns
       .insert<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, NVVM::ThreadIdXOp,
                                           NVVM::ThreadIdYOp, NVVM::ThreadIdZOp>,
diff --git a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
index 40cf097c9c5a9e..e9b44a9fef5289 100644
--- a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+++ b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
@@ -86,7 +86,7 @@ struct LowerGpuOpsToROCDLOpsPass
 
 void mlir::populateGpuToROCDLConversionPatterns(
     LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
-  populateWithGenerated(converter.getDialect()->getContext(), &patterns);
+  populateWithGenerated(converter.getDialect()->getContext(), patterns);
   patterns.insert<
       GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp,
                                   ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>,
diff --git a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp b/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
index f4273a44bb9ce0..ee1e4131854f09 100644
--- a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
+++ b/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
@@ -330,7 +330,7 @@ namespace {
 void mlir::populateGPUToSPIRVPatterns(MLIRContext *context,
                                       SPIRVTypeConverter &typeConverter,
                                       OwningRewritePatternList &patterns) {
-  populateWithGenerated(context, &patterns);
+  populateWithGenerated(context, patterns);
   patterns.insert<
       GPUFuncOpConversion, GPUModuleConversion, GPUReturnOpConversion,
       LaunchConfigConversion<gpu::BlockIdOp, spirv::BuiltIn::WorkgroupId>,
diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
index 895085cf79cfbd..7b46348ed0cf1a 100644
--- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
@@ -1150,6 +1150,11 @@ static LogicalResult verify(PoolingSumOp op) {
   return verifySingleInputPoolingOp(op);
 }
 
+namespace {
+struct EraseDeadLinalgOp;
+struct FoldTensorCastOp;
+} // namespace
+
 #include "mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterfaces.cpp.inc"
 
 #include "mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.cpp.inc"
@@ -1578,18 +1583,4 @@ CANONICALIZERS_AND_FOLDERS(FillOp)
 CANONICALIZERS_AND_FOLDERS(GenericOp)
 CANONICALIZERS_AND_FOLDERS(IndexedGenericOp)
 
-// TODO: Determine whether we can generate the folders and verifiers.
-CANONICALIZERS_AND_FOLDERS(BatchMatmulOp)
-CANONICALIZERS_AND_FOLDERS(DotOp)
-CANONICALIZERS_AND_FOLDERS(MatmulOp)
-CANONICALIZERS_AND_FOLDERS(MatvecOp)
-CANONICALIZERS_AND_FOLDERS(VecmatOp)
-CANONICALIZERS_AND_FOLDERS(ConvWOp)
-CANONICALIZERS_AND_FOLDERS(ConvNWCOp)
-CANONICALIZERS_AND_FOLDERS(ConvNCWOp)
-CANONICALIZERS_AND_FOLDERS(ConvHWOp)
-CANONICALIZERS_AND_FOLDERS(ConvNHWCOp)
-CANONICALIZERS_AND_FOLDERS(ConvNCHWOp)
-CANONICALIZERS_AND_FOLDERS(ConvDHWOp)
-CANONICALIZERS_AND_FOLDERS(ConvNDHWCOp)
-CANONICALIZERS_AND_FOLDERS(ConvNCDHWOp)
+// All named ops canonicalizers and folders are auto-generated in the .cpp.inc.
diff --git a/mlir/lib/Dialect/Linalg/Transforms/TensorsToBuffers.cpp b/mlir/lib/Dialect/Linalg/Transforms/TensorsToBuffers.cpp
index bb37a2ec10dfa7..650c44f9e92243 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/TensorsToBuffers.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/TensorsToBuffers.cpp
@@ -22,40 +22,37 @@
 #include "mlir/Pass/Pass.h"
 #include "mlir/Transforms/Bufferize.h"
 
-namespace {
-
 using namespace ::mlir;
 using namespace ::mlir::linalg;
 
-SmallVector<Range, 4>
-computeLoopRanges(Location loc, linalg::GenericOp linalgOp, OpBuilder *b) {
+static SmallVector<Range, 4> computeLoopRanges(Location loc, LinalgOp linalgOp,
+                                               OpBuilder &b) {
   auto indexingMaps = llvm::to_vector<4>(
       linalgOp.indexing_maps().getAsValueRange<AffineMapAttr>());
   auto inputIndexingMaps =
       llvm::makeArrayRef(indexingMaps).take_front(linalgOp.getNumInputs());
 
-  mlir::edsc::ScopedContext scope(*b, loc);
+  mlir::edsc::ScopedContext scope(b, loc);
   return emitLoopRanges(scope.getBuilderRef(), loc,
                         concatAffineMaps(inputIndexingMaps),
-                        getShape(*b, linalgOp));
+                        getShape(b, linalgOp));
 }
 
-Value maybeConvertToIndex(Location loc, Value val, OpBuilder *b) {
+static Value maybeConvertToIndex(Location loc, Value val, OpBuilder &b) {
   if (val.getType().isIndex())
     return val;
-  return b->create<IndexCastOp>(loc, val, b->getIndexType());
+  return b.create<IndexCastOp>(loc, val, b.getIndexType());
 }
 
-LogicalResult allocateBuffersForResults(Location loc,
-                                        linalg::GenericOp linalgOp,
-                                        linalg::GenericOpAdaptor &adaptor,
-                                        SmallVectorImpl<Value> *resultBuffers,
-                                        OpBuilder *b) {
+static LogicalResult
+allocateBuffersForResults(Location loc, LinalgOp linalgOp,
+                          linalg::GenericOpAdaptor &adaptor,
+                          SmallVectorImpl<Value> &resultBuffers, OpBuilder &b) {
   // Lazily compute loopRanges.
   SmallVector<Range, 4> loopRanges;
 
   // Allocate a buffer for every tensor result.
-  for (auto en : llvm::enumerate(linalgOp.getResultTypes())) {
+  for (auto en : llvm::enumerate(linalgOp.getOperation()->getResultTypes())) {
     size_t resultIndex = en.index();
     Type resultType = en.value();
 
@@ -79,24 +76,24 @@ LogicalResult allocateBuffersForResults(Location loc,
       Value initTensor = linalgOp.getInitTensor(resultIndex);
       Value initBuffer = adaptor.init_tensors()[resultIndex];
       if (initTensor.hasOneUse()) {
-        resultBuffers->push_back(initBuffer);
+        resultBuffers.push_back(initBuffer);
         continue;
       }
       SmallVector<Value, 4> dynOperands;
       for (auto dim : llvm::enumerate(tensorShape)) {
         if (dim.value() == TensorType::kDynamicSize) {
-          dynOperands.push_back(b->create<DimOp>(loc, initTensor, dim.index()));
+          dynOperands.push_back(b.create<DimOp>(loc, initTensor, dim.index()));
         }
       }
-      auto alloc = b->create<AllocOp>(loc, memrefType, dynOperands);
-      b->create<linalg::CopyOp>(loc, initBuffer, alloc);
-      resultBuffers->push_back(alloc);
+      auto alloc = b.create<AllocOp>(loc, memrefType, dynOperands);
+      b.create<linalg::CopyOp>(loc, initBuffer, alloc);
+      resultBuffers.push_back(alloc);
       continue;
     }
 
     // Allocate buffers for statically-shaped results.
     if (memrefType.hasStaticShape()) {
-      resultBuffers->push_back(b->create<AllocOp>(loc, memrefType));
+      resultBuffers.push_back(b.create<AllocOp>(loc, memrefType));
       continue;
     }
 
@@ -123,144 +120,157 @@ LogicalResult allocateBuffersForResults(Location loc,
         return failure();
       }
     }
-    resultBuffers->push_back(b->create<AllocOp>(loc, memrefType, dynOperands));
+    resultBuffers.push_back(b.create<AllocOp>(loc, memrefType, dynOperands));
   }
   return success();
 }
 
+// Specialization for `linalg::GenericOp`.
 /// A pattern to convert Generic Linalg operations which work on tensors to
 /// use buffers. A buffer is allocated using BufferAssignmentPlacer for
 /// each operation result. BufferPlacement pass should be later used to move
 /// Alloc operations to the correct positions and insert the missing Dealloc
 /// operations in the correct places.
-class GenericOpConverter
-    : public BufferAssignmentOpConversionPattern<linalg::GenericOp> {
-public:
-  using BufferAssignmentOpConversionPattern<
-      linalg::GenericOp>::BufferAssignmentOpConversionPattern;
-
-  LogicalResult
-  matchAndRewrite(linalg::GenericOp linalgOp, ArrayRef<Value> operands,
-                  ConversionPatternRewriter &rewriter) const final {
-    linalg::GenericOpAdaptor adaptor(
-        operands, linalgOp.getOperation()->getAttrDictionary());
-
-    // All inputs need to be turned into buffers first. Until then, bail out.
-    if (llvm::any_of(adaptor.inputs(),
-                     [](Value in) { return !in.getType().isa<MemRefType>(); }))
-      return failure();
-
-    // All init_tensors need to be turned into buffers first. Until then, bail
-    // out.
-    if (llvm::any_of(adaptor.init_tensors(),
-                     [](Value in) { return !in.getType().isa<MemRefType>(); }))
-      return failure();
+static void finalizeBufferAllocation(ConversionPatternRewriter &rewriter,
+                                     linalg::GenericOp genericOp,
+                                     ValueRange inputs, ValueRange outputs) {
+  // Generate a new linalg operation that works on buffers.
+  auto newGenericOp = rewriter.create<linalg::GenericOp>(
+      genericOp.getLoc(),
+      /*resultTensorTypes=*/llvm::None,
+      /*inputs=*/inputs,
+      /*outputBuffers=*/outputs,
+      /*initTensors=*/llvm::None, genericOp.indexing_maps(),
+      genericOp.iterator_types(), genericOp.docAttr(),
+      genericOp.library_callAttr(), genericOp.symbol_sourceAttr());
+
+  // Create a new block in the region of the new Generic Op.
+  Block *oldBlock = genericOp.getBody();
+  Region &newRegion = newGenericOp.region();
+  Block *newBlock = rewriter.createBlock(&newRegion, newRegion.begin(),
+                                         oldBlock->getArgumentTypes());
+
+  // Add the result arguments to the new block.
+  for (Value v : ValueRange(outputs).drop_front(genericOp.getNumInitTensors()))
+    newBlock->addArgument(v.getType().cast<MemRefType>().getElementType());
+
+  // Clone the body of the old block to the new block.
+  BlockAndValueMapping mapping;
+  mapping.map(oldBlock->getArguments(), newBlock->getArguments());
+
+  OpBuilder::InsertionGuard guard(rewriter);
+  rewriter.setInsertionPointToEnd(newBlock);
+  for (auto &op : oldBlock->getOperations()) {
+    Operation *clonedOp = rewriter.clone(op, mapping);
+    mapping.map(op.getResults(), clonedOp->getResults());
+  }
 
-    Location loc = linalgOp.getLoc();
-    SmallVector<Value, 2> newOutputBuffers(adaptor.output_buffers().begin(),
-                                           adaptor.output_buffers().end());
+  // Replace the results of the old op with the new output buffers.
+  rewriter.replaceOp(genericOp, outputs);
+}
 
-    if (failed(allocateBuffersForResults(loc, linalgOp, adaptor,
-                                         &newOutputBuffers, &rewriter))) {
-      linalgOp.emitOpError()
-          << "Failed to allocate buffers for tensor results.";
-      return failure();
-    }
+// TODO: Specialization for `linalg::IndexedGenericOp`.
+
+// Specialization for all other `linalg::LinalgOp`.
+static void finalizeBufferAllocation(ConversionPatternRewriter &rewriter,
+                                     linalg::LinalgOp linalgOp,
+                                     ValueRange inputs, ValueRange outputs) {
+  assert(!isa<linalg::GenericOp>(linalgOp.getOperation()));
+  assert(!isa<linalg::IndexedGenericOp>(linalgOp.getOperation()));
+  SmallVector<Value, 8> newOperands = inputs;
+  newOperands.append(outputs.begin(), outputs.end());
+  auto otherOperands = linalgOp.getAssumedNonShapedOperands();
+  newOperands.append(otherOperands.begin(), otherOperands.end());
+  LinalgOp res = cast<LinalgOp>(linalgOp.clone(rewriter, linalgOp.getLoc(),
+                                               /*resultTypes=*/ArrayRef<Type>{},
+                                               newOperands));
+  // Need to mutate the operands_segment_sizes in the resulting op.
+  res.setNumOutputBuffers(outputs.size());
+  res.setNumInitTensors(0);
+  // Replace the results of the old op with the new output buffers.
+  rewriter.replaceOp(linalgOp, outputs);
+}
 
-    // Generate a new linalg operation that works on buffers.
-    auto newLinalgOp = rewriter.create<linalg::GenericOp>(
-        loc,
-        /*resultTensorTypes=*/llvm::None,
-        /*inputs=*/adaptor.inputs(),
-        /*outputBuffers=*/newOutputBuffers,
-        /*initTensors=*/llvm::None, linalgOp.indexing_maps(),
-        linalgOp.iterator_types(), linalgOp.docAttr(),
-        linalgOp.library_callAttr(), linalgOp.symbol_sourceAttr());
-
-    // Create a new block in the region of the new Generic Op.
-    Block *oldBlock = linalgOp.getBody();
-    Region &newRegion = newLinalgOp.region();
-    Block *newBlock = rewriter.createBlock(&newRegion, newRegion.begin(),
-                                           oldBlock->getArgumentTypes());
-
-    // Add the result arguments to the new block.
-    for (Value v : newOutputBuffers)
-      newBlock->addArgument(v.getType().cast<MemRefType>().getElementType());
-
-    // Clone the body of the old block to the new block.
-    BlockAndValueMapping mapping;
-    mapping.map(oldBlock->getArguments(), newBlock->getArguments());
-
-    OpBuilder::InsertionGuard guard(rewriter);
-    rewriter.setInsertionPointToEnd(newBlock);
-    for (auto &op : oldBlock->getOperations()) {
-      Operation *clonedOp = rewriter.clone(op, mapping);
-      mapping.map(op.getResults(), clonedOp->getResults());
-    }
+LogicalResult mlir::linalg::LinalgOpConverter::matchAndRewrite(
+    Operation *op, ArrayRef<Value> operands,
+    ConversionPatternRewriter &rewriter) const {
+  LinalgOp linalgOp = dyn_cast<linalg::LinalgOp>(op);
+  if (!linalgOp)
+    return failure();
+
+  // We abuse the GenericOpAdaptor here.
+  // TODO: Manually create an Adaptor that captures inputs, output_buffers and
+  // init_tensors for all linalg::LinalgOp interface ops.
+  linalg::GenericOpAdaptor adaptor(operands, op->getAttrDictionary());
+
+  // All inputs need to be turned into buffers first. Until then, bail out.
+  if (llvm::any_of(adaptor.inputs(),
+                   [](Value in) { return !in.getType().isa<MemRefType>(); }))
+    return failure();
+
+  // All init_tensors need to be turned into buffers first. Until then, bail
+  // out.
+  if (llvm::any_of(adaptor.init_tensors(),
+                   [](Value in) { return !in.getType().isa<MemRefType>(); }))
+    return failure();
+
+  Location loc = linalgOp.getLoc();
+  SmallVector<Value, 2> newOutputBuffers(adaptor.output_buffers().begin(),
+                                         adaptor.output_buffers().end());
+
+  if (failed(allocateBuffersForResults(loc, linalgOp, adaptor, newOutputBuffers,
+                                       rewriter))) {
+    linalgOp.emitOpError() << "Failed to allocate buffers for tensor results.";
+    return failure();
+  }
 
-    // Replace the results of the old op with the new output buffers.
-    rewriter.replaceOp(linalgOp, newOutputBuffers);
+  // Delegate to the linalg generic pattern.
+  if (auto genericOp = dyn_cast<linalg::GenericOp>(op)) {
+    finalizeBufferAllocation(rewriter, genericOp, adaptor.inputs(),
+                             newOutputBuffers);
     return success();
   }
-};
 
-// Rewrite a tensor `constant` to a vector constant folloed by a vector store
-// and a vector.type_cast.
-class TensorConstantOpConverter
-    : public BufferAssignmentOpConversionPattern<ConstantOp> {
-public:
-  using BufferAssignmentOpConversionPattern<
-      ConstantOp>::BufferAssignmentOpConversionPattern;
-
-  LogicalResult
-  matchAndRewrite(ConstantOp op, ArrayRef<Value> operands,
-                  ConversionPatternRewriter &rewriter) const final {
-    if (!op.getType().isa<RankedTensorType>())
-      return failure();
-    auto attr = op.getValue().cast<DenseElementsAttr>();
-
-    Location loc = op.getLoc();
-    MemRefType memrefType =
-        converter->convertType(op.getType()).cast<MemRefType>();
-    VectorType vectorType =
-        VectorType::get(memrefType.getShape(), memrefType.getElementType());
-
-    // vector constant takes attributes that are compatible with tensor
-    // constant.
-    Value cstVec =
-        rewriter.create<ConstantOp>(loc, vectorType, attr.reshape(vectorType));
-
-    // Alloc a memref<vector<...>>, store the constant and typecast the vector
-    // away.
-    MemRefType memrefOfVectorType = MemRefType::get({}, vectorType);
-    Value alloc =
-        rewriter.create<AllocOp>(loc, memrefOfVectorType, ValueRange{});
-    rewriter.create<StoreOp>(loc, cstVec, alloc);
-    rewriter.replaceOpWithNewOp<vector::TypeCastOp>(op, memrefType, alloc);
+  finalizeBufferAllocation(rewriter, linalgOp, adaptor.inputs(),
+                           newOutputBuffers);
+  return success();
+}
 
-    return success();
-  }
-};
+LogicalResult mlir::linalg::TensorConstantOpConverter::matchAndRewrite(
+    ConstantOp op, ArrayRef<Value> operands,
+    ConversionPatternRewriter &rewriter) const {
+  if (!op.getType().isa<RankedTensorType>())
+    return failure();
+  auto attr = op.getValue().cast<DenseElementsAttr>();
+
+  Location loc = op.getLoc();
+  MemRefType memrefType =
+      converter.convertType(op.getType()).cast<MemRefType>();
+  VectorType vectorType =
+      VectorType::get(memrefType.getShape(), memrefType.getElementType());
+  Value cstVec =
+      rewriter.create<ConstantOp>(loc, vectorType, attr.reshape(vectorType));
+
+  MemRefType memrefOfVectorType = MemRefType::get({}, vectorType);
+  Value alloc = rewriter.create<AllocOp>(loc, memrefOfVectorType, ValueRange{});
+  rewriter.create<StoreOp>(loc, cstVec, alloc);
+  rewriter.replaceOpWithNewOp<vector::TypeCastOp>(op, memrefType, alloc);
 
-// Rewrite a `tensor_cast` as a `memref_cast` with no layout, in the 0-memory
-// space.
-class TensorCastOpConverter
-    : public BufferAssignmentOpConversionPattern<TensorCastOp> {
-public:
-  using BufferAssignmentOpConversionPattern<
-      TensorCastOp>::BufferAssignmentOpConversionPattern;
-
-  LogicalResult
-  matchAndRewrite(TensorCastOp op, ArrayRef<Value> operands,
-                  ConversionPatternRewriter &rewriter) const final {
-    if (op.getType().hasRank())
-      return failure();
-    Type t = UnrankedMemRefType::get(op.getType().getElementType(),
-                                     /*memorySpace=*/0);
-    rewriter.replaceOpWithNewOp<MemRefCastOp>(op, t, operands.front());
-    return success();
-  }
-};
+  return success();
+}
+
+LogicalResult mlir::linalg::TensorCastOpConverter::matchAndRewrite(
+    TensorCastOp op, ArrayRef<Value> operands,
+    ConversionPatternRewriter &rewriter) const {
+  if (op.getType().hasRank())
+    return failure();
+  Type t = UnrankedMemRefType::get(op.getType().getElementType(),
+                                   /*memorySpace=*/0);
+  rewriter.replaceOpWithNewOp<MemRefCastOp>(op, t, operands.front());
+  return success();
+}
+
+namespace {
 
 /// Converts Linalg operations that work on tensor-type operands or results to
 /// work on buffers.
@@ -322,11 +332,11 @@ struct ConvertLinalgOnTensorsToBuffers
         BufferAssignmentTypeConverter::AppendToArgumentsList);
 
     OwningRewritePatternList patterns;
-    populateConvertLinalgOnTensorsToBuffersPatterns(&context, &converter,
-                                                    &patterns);
+    populateConvertLinalgOnTensorsToBuffersPatterns(&context, converter,
+                                                    patterns);
     populateWithBufferAssignmentOpConversionPatterns<
-        mlir::ReturnOp, mlir::ReturnOp, linalg::CopyOp>(&context, &converter,
-                                                        &patterns);
+        mlir::ReturnOp, mlir::ReturnOp, linalg::CopyOp>(&context, converter,
+                                                        patterns);
     if (failed(applyFullConversion(this->getOperation(), target, patterns)))
       this->signalPassFailure();
   }
@@ -337,13 +347,13 @@ std::unique_ptr<OperationPass<ModuleOp>>
 mlir::createConvertLinalgOnTensorsToBuffersPass() {
   return std::make_unique<ConvertLinalgOnTensorsToBuffers>();
 }
-
 void mlir::linalg::populateConvertLinalgOnTensorsToBuffersPatterns(
-    MLIRContext *context, BufferAssignmentTypeConverter *converter,
-    OwningRewritePatternList *patterns) {
-  patterns->insert<
+
+    MLIRContext *context, BufferAssignmentTypeConverter &converter,
+    OwningRewritePatternList &patterns) {
+  patterns.insert<
       // clang-format off
-      GenericOpConverter,
+      LinalgOpConverter,
       TensorCastOpConverter,
       TensorConstantOpConverter
       // clang-format on
diff --git a/mlir/lib/Dialect/Shape/Transforms/ShapeTypeConversion.cpp b/mlir/lib/Dialect/Shape/Transforms/ShapeTypeConversion.cpp
index e281cea24e739a..83e432855f6ea9 100644
--- a/mlir/lib/Dialect/Shape/Transforms/ShapeTypeConversion.cpp
+++ b/mlir/lib/Dialect/Shape/Transforms/ShapeTypeConversion.cpp
@@ -38,7 +38,7 @@ class TypeConversionAssumingOpConverter
     newResultTypes.reserve(assumingOp.getNumResults());
     for (auto result : assumingOp.getResults()) {
       auto originalType = result.getType();
-      Type convertedType = converter->convertType(originalType);
+      Type convertedType = converter.convertType(originalType);
       newResultTypes.push_back(convertedType);
     }
 
@@ -60,7 +60,7 @@ struct ShapeTensorToMemrefPass
 
     OwningRewritePatternList patterns;
     BufferAssignmentTypeConverter converter;
-    populateShapeTypeConversionPatterns(&ctx, &converter, &patterns);
+    populateShapeTypeConversionPatterns(&ctx, converter, patterns);
 
     ConversionTarget target(getContext());
     auto isMemRefType = [](Type type) { return type.isa<BaseMemRefType>(); };
@@ -81,9 +81,9 @@ struct ShapeTensorToMemrefPass
 //
 // TODO: Change this to work generally with any type conversions.
 void mlir::populateShapeTypeConversionPatterns(
-    MLIRContext *context, BufferAssignmentTypeConverter *converter,
-    OwningRewritePatternList *patterns) {
-  patterns->insert<TypeConversionAssumingOpConverter>(context, converter);
+    MLIRContext *context, BufferAssignmentTypeConverter &converter,
+    OwningRewritePatternList &patterns) {
+  patterns.insert<TypeConversionAssumingOpConverter>(context, converter);
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/TableGen/Pattern.cpp b/mlir/lib/TableGen/Pattern.cpp
index b32775318df8e1..cfa3da2c417a47 100644
--- a/mlir/lib/TableGen/Pattern.cpp
+++ b/mlir/lib/TableGen/Pattern.cpp
@@ -219,11 +219,11 @@ std::string SymbolInfoMap::SymbolInfo::getVarDecl(StringRef name) const {
   case Kind::Operand: {
     // Use operand range for captured operands (to support potential variadic
     // operands).
-    return std::string(
-        formatv("Operation::operand_range {0}(op0->getOperands());\n", name));
+    return std::string(formatv(
+        "::mlir::Operation::operand_range {0}(op0->getOperands());\n", name));
   }
   case Kind::Value: {
-    return std::string(formatv("ArrayRef<Value> {0};\n", name));
+    return std::string(formatv("::llvm::ArrayRef<::mlir::Value> {0};\n", name));
   }
   case Kind::Result: {
     // Use the op itself for captured results.
diff --git a/mlir/lib/Transforms/BufferPlacement.cpp b/mlir/lib/Transforms/BufferPlacement.cpp
index 380c72087bbdb3..3a0d6ebd962b72 100644
--- a/mlir/lib/Transforms/BufferPlacement.cpp
+++ b/mlir/lib/Transforms/BufferPlacement.cpp
@@ -875,8 +875,8 @@ LogicalResult BufferAssignmentFuncOpConverter::matchAndRewrite(
   TypeConverter::SignatureConversion conversion(funcType.getNumInputs());
   for (auto argType : llvm::enumerate(funcType.getInputs())) {
     SmallVector<Type, 2> decomposedTypes, convertedTypes;
-    converter->tryDecomposeType(argType.value(), decomposedTypes);
-    converter->convertTypes(decomposedTypes, convertedTypes);
+    converter.tryDecomposeType(argType.value(), decomposedTypes);
+    converter.convertTypes(decomposedTypes, convertedTypes);
     conversion.addInputs(argType.index(), convertedTypes);
   }
 
@@ -885,10 +885,10 @@ LogicalResult BufferAssignmentFuncOpConverter::matchAndRewrite(
   newResultTypes.reserve(funcOp.getNumResults());
   for (Type resultType : funcType.getResults()) {
     SmallVector<Type, 2> originTypes;
-    converter->tryDecomposeType(resultType, originTypes);
+    converter.tryDecomposeType(resultType, originTypes);
     for (auto origin : originTypes) {
-      Type converted = converter->convertType(origin);
-      auto kind = converter->getResultConversionKind(origin, converted);
+      Type converted = converter.convertType(origin);
+      auto kind = converter.getResultConversionKind(origin, converted);
       if (kind == BufferAssignmentTypeConverter::AppendToArgumentsList)
         conversion.addInputs(converted);
       else
@@ -897,7 +897,7 @@ LogicalResult BufferAssignmentFuncOpConverter::matchAndRewrite(
     }
   }
 
-  if (failed(rewriter.convertRegionTypes(&funcOp.getBody(), *converter,
+  if (failed(rewriter.convertRegionTypes(&funcOp.getBody(), converter,
                                          &conversion)))
     return failure();
 
@@ -986,8 +986,8 @@ LogicalResult BufferAssignmentCallOpConverter::matchAndRewrite(
   // values if a decompose callback function has been provided by the user.
   for (auto operand : operands) {
     SmallVector<Value, 2> values;
-    this->converter->tryDecomposeValue(builder, loc, operand.getType(), operand,
-                                       values);
+    this->converter.tryDecomposeValue(builder, loc, operand.getType(), operand,
+                                      values);
     newOperands.append(values.begin(), values.end());
   }
 
@@ -998,11 +998,11 @@ LogicalResult BufferAssignmentCallOpConverter::matchAndRewrite(
   mappings.resize(callOp.getNumResults());
   for (auto result : llvm::enumerate(callOp.getResults())) {
     SmallVector<Type, 2> originTypes;
-    converter->tryDecomposeType(result.value().getType(), originTypes);
+    converter.tryDecomposeType(result.value().getType(), originTypes);
     auto &resultMapping = mappings[result.index()];
     for (Type origin : originTypes) {
-      Type converted = converter->convertType(origin);
-      auto kind = converter->getResultConversionKind(origin, converted);
+      Type converted = converter.convertType(origin);
+      auto kind = converter.getResultConversionKind(origin, converted);
       if (kind == BufferAssignmentTypeConverter::KeepAsFunctionResult) {
         newResultTypes.push_back(converted);
         // The result value is not yet available. Its index is kept and it is
@@ -1039,7 +1039,7 @@ LogicalResult BufferAssignmentCallOpConverter::matchAndRewrite(
     } else {
       // Values need to be packed using callback function. The same callback
       // that is used for materializeArgumentConversion is used for packing.
-      Value packed = converter->materializeArgumentConversion(
+      Value packed = converter.materializeArgumentConversion(
           nextBuilder, loc, callOp.getType(i), valuesToPack);
       replacedValues.push_back(packed);
     }
diff --git a/mlir/test/Dialect/Linalg/tensors-to-buffers.mlir b/mlir/test/Dialect/Linalg/tensors-to-buffers.mlir
index 7d714092cb7c7e..4d23b7e10daec5 100644
--- a/mlir/test/Dialect/Linalg/tensors-to-buffers.mlir
+++ b/mlir/test/Dialect/Linalg/tensors-to-buffers.mlir
@@ -173,3 +173,142 @@ func @bar() {
 // know that things will play nicely at the C ABI boundary).
 func @print_memref_f32(%ptr : tensor<*xf32>)
 // CHECK-LABEL: func @print_memref_f32(memref<*xf32>)
+
+// -----
+
+#accesses = [
+  affine_map<(i, j, k) -> (j, i, k)>,
+  affine_map<(i, j, k) -> (i, j)>
+]
+
+#trait = {
+  indexing_maps = #accesses,
+  iterator_types = ["parallel", "parallel", "reduction"]
+}
+
+func @generic_with_init_tensor(%arg0: tensor<2x3x4xvector<3x4xi4>>,
+  %arg1: tensor<3x2xf32>) -> (tensor<3x2xf32>) {
+
+  %0 = linalg.generic #trait
+    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
+   init(%arg1 : tensor<3x2xf32>) {
+    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
+      %f0 = constant 0.0 : f32
+      linalg.yield %f0 : f32
+  } -> tensor<3x2xf32>
+
+  return %0 : tensor<3x2xf32>
+}
+// CHECK-LABEL: func @generic_with_init_tensor
+//  CHECK-SAME: (%[[ARG0:.*]]: memref<2x3x4xvector<3x4xi4>>, %[[ARG1:.*]]: memref<3x2xf32>, %[[RESULT0:.*]]: memref<3x2xf32>) {
+//  CHECK-NEXT: linalg.generic
+//       CHECK: linalg.copy(%[[ARG1]], %[[RESULT0]])
+//  CHECK-NEXT: return
+//   CHECK-NOT: %
+
+// -----
+
+#accesses = [
+  affine_map<(i, j, k) -> (j, i, k)>,
+  affine_map<(i, j, k) -> (i, j)>
+]
+
+#trait = {
+  indexing_maps = #accesses,
+  iterator_types = ["parallel", "parallel", "reduction"]
+}
+
+func @init_tensor_with_2_uses(%arg0: tensor<2x3x4xvector<3x4xi4>>,
+  %arg1: tensor<3x2xf32>) -> (tensor<3x2xf32>, tensor<3x2xf32>) {
+
+  %0 = linalg.generic #trait
+    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
+   init(%arg1 : tensor<3x2xf32>) {
+    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
+      %f0 = constant 0.0 : f32
+      linalg.yield %f0 : f32
+  } -> tensor<3x2xf32>
+
+  %1 = linalg.generic #trait
+    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
+   init(%arg1 : tensor<3x2xf32>) {
+    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
+      %f0 = constant 0.0 : f32
+      linalg.yield %f0 : f32
+  } -> tensor<3x2xf32>
+
+  return %0, %1 : tensor<3x2xf32>, tensor<3x2xf32>
+}
+// CHECK-LABEL: func @init_tensor_with_2_uses
+//  CHECK-SAME: (%[[ARG0:.*]]: memref<2x3x4xvector<3x4xi4>>, %[[ARG1:.*]]: memref<3x2xf32>, %[[RESULT0:.*]]: memref<3x2xf32>, %[[RESULT1:.*]]: memref<3x2xf32>) {
+//  CHECK-NEXT: %[[ALLOC0:.*]] = alloc
+//  CHECK-NEXT: linalg.copy(%[[ARG1]], %[[ALLOC0]])
+//  CHECK-NEXT: linalg.generic
+//  CHECK-SAME: outs(%[[ALLOC0]]
+//  CHECK-NEXT: ^bb
+//  CHECK-NEXT:   constant
+//  CHECK-NEXT:   yield
+//  CHECK-NEXT: }
+//  CHECK-NEXT: %[[ALLOC1:.*]] = alloc
+//  CHECK-NEXT: linalg.copy(%[[ARG1]], %[[ALLOC1]])
+//  CHECK-NEXT: linalg.generic
+//  CHECK-SAME: outs(%[[ALLOC1]]
+//  CHECK-NEXT: ^bb
+//  CHECK-NEXT:   constant
+//  CHECK-NEXT:   yield
+//  CHECK-NEXT: }
+//  CHECK-NEXT: linalg.copy(%[[ALLOC0]], %[[RESULT0]])
+//  CHECK-NEXT: dealloc
+//  CHECK-NEXT: linalg.copy(%[[ALLOC1]], %[[RESULT1]])
+//  CHECK-NEXT: dealloc
+//  CHECK-NEXT: return
+//   CHECK-NOT: %
+
+// -----
+
+#accesses = [
+  affine_map<(i, j, k) -> (j, i, k)>,
+  affine_map<(i, j, k) -> (i, j)>
+]
+
+#trait = {
+  indexing_maps = #accesses,
+  iterator_types = ["parallel", "parallel", "reduction"]
+}
+
+func @init_tensor_with_1_use_def_chain(%arg0: tensor<2x3x4xvector<3x4xi4>>,
+  %arg1: tensor<3x2xf32>) -> (tensor<3x2xf32>) {
+
+  %0 = linalg.generic #trait
+    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
+   init(%arg1 : tensor<3x2xf32>) {
+    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
+      %f0 = constant 0.0 : f32
+      linalg.yield %f0 : f32
+  } -> tensor<3x2xf32>
+
+  %1 = linalg.generic #trait
+    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
+   init(%0 : tensor<3x2xf32>) {
+    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
+      %f0 = constant 0.0 : f32
+      linalg.yield %f0 : f32
+  } -> tensor<3x2xf32>
+
+  return %1 : tensor<3x2xf32>
+}
+// CHECK-LABEL: func @init_tensor_with_1_use_def_chain
+//  CHECK-SAME: (%[[ARG0:.*]]: memref<2x3x4xvector<3x4xi4>>, %[[ARG1:.*]]: memref<3x2xf32>, %[[RESULT0:.*]]: memref<3x2xf32>) {
+//  CHECK-NEXT: linalg.generic
+//  CHECK-NEXT: ^bb
+//  CHECK-NEXT:   constant
+//  CHECK-NEXT:   yield
+//  CHECK-NEXT: }
+//  CHECK-NEXT: linalg.generic
+//  CHECK-NEXT: ^bb
+//  CHECK-NEXT:   constant
+//  CHECK-NEXT:   yield
+//  CHECK-NEXT: }
+//  CHECK-NEXT: linalg.copy(%[[ARG1]], %[[RESULT0]])
+//  CHECK-NEXT: return
+//   CHECK-NOT: %
diff --git a/mlir/test/Transforms/buffer-placement-preparation.mlir b/mlir/test/Transforms/buffer-placement-preparation.mlir
index ac3ec124621182..4fcd225abc7ee4 100644
--- a/mlir/test/Transforms/buffer-placement-preparation.mlir
+++ b/mlir/test/Transforms/buffer-placement-preparation.mlir
@@ -382,141 +382,3 @@ func @decompose_tuple_typed_function_args_and_results(%arg0: tuple<i1,f32>, %arg
 // CHECK-NEXT: linalg.copy(%[[SECOND_TUPLE_SECOND_ELEM]], %[[RESULT0]])
 // CHECK-NEXT: linalg.copy(%[[ARG2]], %[[RESULT1]])
 // CHECK-NEXT: return %[[SECOND_TUPLE_FIRST_ELEM]], %[[FIRST_TUPLE_FIRST_ELEM]], %[[FIRST_TUPLE_SECOND_ELEM]]
-
-// -----
-
-#accesses = [
-  affine_map<(i, j, k) -> (j, i, k)>,
-  affine_map<(i, j, k) -> (i, j)>
-]
-
-#trait = {
-  indexing_maps = #accesses,
-  iterator_types = ["parallel", "parallel", "reduction"]
-}
-
-func @generic_with_init_tensor(
-  %arg0: tensor<2x3x4xvector<3x4xi4>>, %arg1: tensor<3x2xf32>) -> (tensor<3x2xf32>) {
-
-  %0 = linalg.generic #trait
-    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
-   init(%arg1 : tensor<3x2xf32>) {
-    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
-      %f0 = constant 0.0 : f32
-      linalg.yield %f0 : f32
-  } -> tensor<3x2xf32>
-
-  return %0 : tensor<3x2xf32>
-}
-// CHECK-LABEL: func @generic_with_init_tensor
-//  CHECK-SAME: (%[[ARG0:.*]]: memref<2x3x4xvector<3x4xi4>>, %[[ARG1:.*]]: memref<3x2xf32>, %[[RESULT0:.*]]: memref<3x2xf32>) {
-//  CHECK-NEXT: linalg.generic
-//       CHECK: linalg.copy(%[[ARG1]], %[[RESULT0]])
-//  CHECK-NEXT: return
-//   CHECK-NOT: %
-
-// -----
-
-#accesses = [
-  affine_map<(i, j, k) -> (j, i, k)>,
-  affine_map<(i, j, k) -> (i, j)>
-]
-
-#trait = {
-  indexing_maps = #accesses,
-  iterator_types = ["parallel", "parallel", "reduction"]
-}
-
-func @init_tensor_with_2_uses(
-  %arg0: tensor<2x3x4xvector<3x4xi4>>, %arg1: tensor<3x2xf32>) -> (tensor<3x2xf32>, tensor<3x2xf32>) {
-
-  %0 = linalg.generic #trait
-    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
-   init(%arg1 : tensor<3x2xf32>) {
-    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
-      %f0 = constant 0.0 : f32
-      linalg.yield %f0 : f32
-  } -> tensor<3x2xf32>
-
-  %1 = linalg.generic #trait
-    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
-   init(%arg1 : tensor<3x2xf32>) {
-    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
-      %f0 = constant 0.0 : f32
-      linalg.yield %f0 : f32
-  } -> tensor<3x2xf32>
-
-  return %0, %1 : tensor<3x2xf32>, tensor<3x2xf32>
-}
-// CHECK-LABEL: func @init_tensor_with_2_uses
-//  CHECK-SAME: (%[[ARG0:.*]]: memref<2x3x4xvector<3x4xi4>>, %[[ARG1:.*]]: memref<3x2xf32>, %[[RESULT0:.*]]: memref<3x2xf32>, %[[RESULT1:.*]]: memref<3x2xf32>) {
-//  CHECK-NEXT: %[[ALLOC0:.*]] = alloc
-//  CHECK-NEXT: linalg.copy(%[[ARG1]], %[[ALLOC0]])
-//  CHECK-NEXT: linalg.generic
-//  CHECK-SAME: outs(%[[ALLOC0]]
-//  CHECK-NEXT: ^bb
-//  CHECK-NEXT:   constant
-//  CHECK-NEXT:   yield
-//  CHECK-NEXT: }
-//  CHECK-NEXT: %[[ALLOC1:.*]] = alloc
-//  CHECK-NEXT: linalg.copy(%[[ARG1]], %[[ALLOC1]])
-//  CHECK-NEXT: linalg.generic
-//  CHECK-SAME: outs(%[[ALLOC1]]
-//  CHECK-NEXT: ^bb
-//  CHECK-NEXT:   constant
-//  CHECK-NEXT:   yield
-//  CHECK-NEXT: }
-//  CHECK-NEXT: linalg.copy(%[[ALLOC0]], %[[RESULT0]])
-//  CHECK-NEXT: linalg.copy(%[[ALLOC1]], %[[RESULT1]])
-//  CHECK-NEXT: return
-//   CHECK-NOT: %
-
-// -----
-
-#accesses = [
-  affine_map<(i, j, k) -> (j, i, k)>,
-  affine_map<(i, j, k) -> (i, j)>
-]
-
-#trait = {
-  indexing_maps = #accesses,
-  iterator_types = ["parallel", "parallel", "reduction"]
-}
-
-func @init_tensor_with_1_use_def_chain(
-  %arg0: tensor<2x3x4xvector<3x4xi4>>, %arg1: tensor<3x2xf32>) -> (tensor<3x2xf32>) {
-
-  %0 = linalg.generic #trait
-    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
-   init(%arg1 : tensor<3x2xf32>) {
-    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
-      %f0 = constant 0.0 : f32
-      linalg.yield %f0 : f32
-  } -> tensor<3x2xf32>
-
-  %1 = linalg.generic #trait
-    ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
-   init(%0 : tensor<3x2xf32>) {
-    ^bb(%v0: vector<3x4xi4>, %v1: f32) :
-      %f0 = constant 0.0 : f32
-      linalg.yield %f0 : f32
-  } -> tensor<3x2xf32>
-
-  return %1 : tensor<3x2xf32>
-}
-// CHECK-LABEL: func @init_tensor_with_1_use_def_chain
-//  CHECK-SAME: (%[[ARG0:.*]]: memref<2x3x4xvector<3x4xi4>>, %[[ARG1:.*]]: memref<3x2xf32>, %[[RESULT0:.*]]: memref<3x2xf32>) {
-//  CHECK-NEXT: linalg.generic
-//  CHECK-NEXT: ^bb
-//  CHECK-NEXT:   constant
-//  CHECK-NEXT:   yield
-//  CHECK-NEXT: }
-//  CHECK-NEXT: linalg.generic
-//  CHECK-NEXT: ^bb
-//  CHECK-NEXT:   constant
-//  CHECK-NEXT:   yield
-//  CHECK-NEXT: }
-//  CHECK-NEXT: linalg.copy(%[[ARG1]], %[[RESULT0]])
-//  CHECK-NEXT: return
-//   CHECK-NOT: %
-
diff --git a/mlir/test/lib/Dialect/Test/TestPatterns.cpp b/mlir/test/lib/Dialect/Test/TestPatterns.cpp
index 5f2b9e32dac7bf..32d618d9008e40 100644
--- a/mlir/test/lib/Dialect/Test/TestPatterns.cpp
+++ b/mlir/test/lib/Dialect/Test/TestPatterns.cpp
@@ -77,7 +77,7 @@ struct FoldingPattern : public RewritePattern {
 struct TestPatternDriver : public PassWrapper<TestPatternDriver, FunctionPass> {
   void runOnFunction() override {
     mlir::OwningRewritePatternList patterns;
-    populateWithGenerated(&getContext(), &patterns);
+    populateWithGenerated(&getContext(), patterns);
 
     // Verify named pattern is generated with expected name.
     patterns.insert<FoldingPattern, TestNamedPatternRule>(&getContext());
@@ -547,7 +547,7 @@ struct TestLegalizePatternDriver
   void runOnOperation() override {
     TestTypeConverter converter;
     mlir::OwningRewritePatternList patterns;
-    populateWithGenerated(&getContext(), &patterns);
+    populateWithGenerated(&getContext(), patterns);
     patterns.insert<
         TestRegionRewriteBlockMovement, TestRegionRewriteUndo, TestCreateBlock,
         TestCreateIllegalBlock, TestUndoBlockArgReplace, TestUndoBlockErase,
diff --git a/mlir/test/lib/Transforms/TestBufferPlacement.cpp b/mlir/test/lib/Transforms/TestBufferPlacement.cpp
index aecf99f69729c3..ead4c5d6fb3845 100644
--- a/mlir/test/lib/Transforms/TestBufferPlacement.cpp
+++ b/mlir/test/lib/Transforms/TestBufferPlacement.cpp
@@ -147,12 +147,12 @@ struct TestBufferPlacementPreparationPass
   };
 
   void populateTensorLinalgToBufferLinalgConversionPattern(
-      MLIRContext *context, BufferAssignmentTypeConverter *converter,
-      OwningRewritePatternList *patterns) {
+      MLIRContext *context, BufferAssignmentTypeConverter &converter,
+      OwningRewritePatternList &patterns) {
     populateWithBufferAssignmentOpConversionPatterns<
         mlir::ReturnOp, mlir::ReturnOp, linalg::CopyOp>(context, converter,
                                                         patterns);
-    patterns->insert<GenericOpConverter>(context, converter);
+    patterns.insert<GenericOpConverter>(context, converter);
   }
 
   void getDependentDialects(DialectRegistry &registry) const override {
@@ -230,8 +230,8 @@ struct TestBufferPlacementPreparationPass
     });
 
     OwningRewritePatternList patterns;
-    populateTensorLinalgToBufferLinalgConversionPattern(&context, &converter,
-                                                        &patterns);
+    populateTensorLinalgToBufferLinalgConversionPattern(&context, converter,
+                                                        patterns);
     if (failed(applyFullConversion(this->getOperation(), target, patterns)))
       this->signalPassFailure();
   };
diff --git a/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp b/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
index 517fc9fc18f54a..a32c37d96a4244 100644
--- a/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
+++ b/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
@@ -32,6 +32,15 @@
     llvm::errs() << "'" << #expr << "' failed with '" << name << "'\n";        \
   }(expr)
 
+// Static initialization of CUDA context for device ordinal 0.
+static auto InitializeCtx = [] {
+  CUdevice device;
+  CUDA_REPORT_IF_ERROR(cuDeviceGet(&device, /*ordinal=*/0));
+  CUcontext context;
+  CUDA_REPORT_IF_ERROR(cuCtxCreate(&context, /*flags=*/0, device));
+  return 0;
+}();
+
 extern "C" CUmodule mgpuModuleLoad(void *data) {
   CUmodule module = nullptr;
   CUDA_REPORT_IF_ERROR(cuModuleLoadData(&module, data));
@@ -63,10 +72,36 @@ extern "C" CUstream mgpuStreamCreate() {
   return stream;
 }
 
+extern "C" void mgpuStreamDestroy(CUstream stream) {
+  CUDA_REPORT_IF_ERROR(cuStreamDestroy(stream));
+}
+
 extern "C" void mgpuStreamSynchronize(CUstream stream) {
   CUDA_REPORT_IF_ERROR(cuStreamSynchronize(stream));
 }
 
+extern "C" void mgpuStreamWaitEvent(CUstream stream, CUevent event) {
+  CUDA_REPORT_IF_ERROR(cuStreamWaitEvent(stream, event, /*flags=*/0));
+}
+
+extern "C" CUevent mgpuEventCreate() {
+  CUevent event = nullptr;
+  CUDA_REPORT_IF_ERROR(cuEventCreate(&event, CU_EVENT_DISABLE_TIMING));
+  return event;
+}
+
+extern "C" void mgpuEventDestroy(CUevent event) {
+  CUDA_REPORT_IF_ERROR(cuEventDestroy(event));
+}
+
+extern "C" void mgpuEventSynchronize(CUevent event) {
+  CUDA_REPORT_IF_ERROR(cuEventSynchronize(event));
+}
+
+extern "C" void mgpuEventRecord(CUevent event, CUstream stream) {
+  CUDA_REPORT_IF_ERROR(cuEventRecord(event, stream));
+}
+
 /// Helper functions for writing mlir example code
 
 // Allows to register byte array with the CUDA runtime. Helpful until we have
diff --git a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
index 64424b4ac3d2f8..02f7dd30451961 100644
--- a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
+++ b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
@@ -994,6 +994,10 @@ class TCParser {
   void printRegionBuilder(llvm::raw_ostream &os, StringRef cppOpName,
                           ComprehensionParsingState &state);
 
+  /// Print the C++ impl for named ops canonicalizers and fodlers.
+  void printCanonicalizersAndFolders(llvm::raw_ostream &os,
+                                     StringRef cppOpName);
+
 private:
   //===--------------------------------------------------------------------===//
   // Internal bookkeeping of tensors.
@@ -1430,6 +1434,7 @@ LogicalResult TCParser::parseAndEmitODSDef(llvm::raw_ostream &os) {
     printReferenceIterators(ss, cppOpName, state);
     printReferenceIndexingMaps(ss, cppOpName, state);
     printRegionBuilder(ss, cppOpName, state);
+    printCanonicalizersAndFolders(ss, cppOpName);
     ss.flush();
     os << extraMethods << "\n";
   }
@@ -1571,6 +1576,22 @@ void TCParser::printReferenceIterators(llvm::raw_ostream &os,
   os << llvm::formatv(referenceReferenceIteratorsFmt, cppOpName, iteratorsStr);
 }
 
+void TCParser::printCanonicalizersAndFolders(llvm::raw_ostream &os,
+                                             StringRef cppOpName) {
+  const char *canonicalizersAndFoldersFmt = R"FMT(
+    void {0}::getCanonicalizationPatterns(
+        OwningRewritePatternList &results,
+        MLIRContext *context) {{
+      results.insert<EraseDeadLinalgOp>();
+      results.insert<FoldTensorCastOp>();
+    }
+    LogicalResult {0}::fold(ArrayRef<Attribute>,
+                            SmallVectorImpl<OpFoldResult> &) {{
+      return foldMemRefCast(*this);
+    })FMT";
+  os << llvm::formatv(canonicalizersAndFoldersFmt, cppOpName);
+}
+
 /// Print the C++ StructuredOpsInterface impl of `referenceIndexingMaps`.
 void TCParser::printReferenceIndexingMaps(llvm::raw_ostream &os,
                                           StringRef cppOpName,
diff --git a/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp b/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp
index 9184c9fa20fa2b..999b80c21fbc2c 100644
--- a/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp
+++ b/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp
@@ -31,6 +31,15 @@
     llvm::errs() << "'" << #expr << "' failed with '" << name << "'\n";        \
   }(expr)
 
+// Static initialization of HIP context for device ordinal 0.
+static auto InitializeCtx = [] {
+  hipDevice_t device;
+  HIP_REPORT_IF_ERROR(hipDeviceGet(&device, /*ordinal=*/0));
+  hipContext_t context;
+  HIP_REPORT_IF_ERROR(hipCtxCreate(&context, /*flags=*/0, device));
+  return 0;
+}();
+
 extern "C" hipModule_t mgpuModuleLoad(void *data) {
   hipModule_t module = nullptr;
   HIP_REPORT_IF_ERROR(hipModuleLoadData(&module, data));
@@ -58,16 +67,42 @@ extern "C" void mgpuLaunchKernel(hipFunction_t function, intptr_t gridX,
                                             stream, params, extra));
 }
 
-extern "C" void *mgpuStreamCreate() {
+extern "C" hipStream_t mgpuStreamCreate() {
   hipStream_t stream = nullptr;
   HIP_REPORT_IF_ERROR(hipStreamCreate(&stream));
   return stream;
 }
 
+extern "C" void mgpuStreamDestroy(hipStream_t stream) {
+  HIP_REPORT_IF_ERROR(hipStreamDestroy(stream));
+}
+
 extern "C" void mgpuStreamSynchronize(hipStream_t stream) {
   return HIP_REPORT_IF_ERROR(hipStreamSynchronize(stream));
 }
 
+extern "C" void mgpuStreamWaitEvent(hipStream_t stream, hipEvent_t event) {
+  HIP_REPORT_IF_ERROR(hipStreamWaitEvent(stream, event, /*flags=*/0));
+}
+
+extern "C" hipEvent_t mgpuEventCreate() {
+  hipEvent_t event = nullptr;
+  HIP_REPORT_IF_ERROR(hipEventCreateWithFlags(&event, hipEventDisableTiming));
+  return event;
+}
+
+extern "C" void mgpuEventDestroy(hipEvent_t event) {
+  HIP_REPORT_IF_ERROR(hipEventDestroy(event));
+}
+
+extern "C" void mgpuEventSynchronize(hipEvent_t event) {
+  HIP_REPORT_IF_ERROR(hipEventSynchronize(event));
+}
+
+extern "C" void mgpuEventRecord(hipEvent_t event, hipStream_t stream) {
+  HIP_REPORT_IF_ERROR(hipEventRecord(event, stream));
+}
+
 /// Helper functions for writing mlir example code
 
 // Allows to register byte array with the ROCM runtime. Helpful until we have
diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
index 5345bc598da956..3bcf0211455566 100644
--- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
@@ -487,16 +487,7 @@ void OpEmitter::genAttrGetters() {
 
   // Emit with return type specified.
   auto emitAttrWithReturnType = [&](StringRef name, Attribute attr) {
-    Dialect attrDialect = attr.getDialect();
-    // Does the current operation have a different namespace than the attribute?
-    bool differentNamespace =
-        attrDialect && opDialect && attrDialect != opDialect;
-    std::string returnType = differentNamespace
-                                 ? (llvm::Twine(attrDialect.getCppNamespace()) +
-                                    "::" + attr.getReturnType())
-                                       .str()
-                                 : attr.getReturnType().str();
-    auto *method = opClass.addMethodAndPrune(returnType, name);
+    auto *method = opClass.addMethodAndPrune(attr.getReturnType(), name);
     auto &body = method->body();
     body << "  auto attr = " << name << "Attr();\n";
     if (attr.hasDefaultValue()) {
@@ -2000,8 +1991,8 @@ void OpEmitter::genOpAsmInterface() {
   opClass.addTrait("::mlir::OpAsmOpInterface::Trait");
 
   // Generate the right accessor for the number of results.
-  auto *method = opClass.addMethodAndPrune("void", "getAsmResultNames",
-                                           "OpAsmSetValueNameFn", "setNameFn");
+  auto *method = opClass.addMethodAndPrune(
+      "void", "getAsmResultNames", "::mlir::OpAsmSetValueNameFn", "setNameFn");
   auto &body = method->body();
   for (int i = 0; i != numResults; ++i) {
     body << "  auto resultGroup" << i << " = getODSResults(" << i << ");\n"
diff --git a/mlir/tools/mlir-tblgen/RewriterGen.cpp b/mlir/tools/mlir-tblgen/RewriterGen.cpp
index e16900227759d9..ff6138f73914ec 100644
--- a/mlir/tools/mlir-tblgen/RewriterGen.cpp
+++ b/mlir/tools/mlir-tblgen/RewriterGen.cpp
@@ -221,7 +221,8 @@ void PatternEmitter::emitOpMatch(DagNode tree, int depth) {
 
   int indent = 4 + 2 * depth;
   os.indent(indent) << formatv(
-      "auto castedOp{0} = dyn_cast_or_null<{1}>(op{0}); (void)castedOp{0};\n",
+      "auto castedOp{0} = ::llvm::dyn_cast_or_null<{1}>(op{0}); "
+      "(void)castedOp{0};\n",
       depth, op.getQualCppClassName());
   // Skip the operand matching at depth 0 as the pattern rewriter already does.
   if (depth != 0) {
@@ -535,7 +536,7 @@ void PatternEmitter::emit(StringRef rewriteName) {
       os << "\n// Rewrite\n";
       emitRewriteLogic();
 
-      os << "return success();\n";
+      os << "return ::mlir::success();\n";
     }
     os << "};\n";
   }
@@ -1145,10 +1146,10 @@ static void emitRewriters(const RecordKeeper &recordKeeper, raw_ostream &os) {
   }
 
   // Emit function to add the generated matchers to the pattern list.
-  os << "void LLVM_ATTRIBUTE_UNUSED populateWithGenerated(MLIRContext "
-        "*context, OwningRewritePatternList *patterns) {\n";
+  os << "void LLVM_ATTRIBUTE_UNUSED populateWithGenerated(::mlir::MLIRContext "
+        "*context, ::mlir::OwningRewritePatternList &patterns) {\n";
   for (const auto &name : rewriterNames) {
-    os << "  patterns->insert<" << name << ">(context);\n";
+    os << "  patterns.insert<" << name << ">(context);\n";
   }
   os << "}\n";
 }
diff --git a/polly/test/Isl/CodeGen/scev_looking_through_bitcasts.ll b/polly/test/Isl/CodeGen/scev_looking_through_bitcasts.ll
index 1012e23cd3a208..321e98ab6772ce 100644
--- a/polly/test/Isl/CodeGen/scev_looking_through_bitcasts.ll
+++ b/polly/test/Isl/CodeGen/scev_looking_through_bitcasts.ll
@@ -32,6 +32,5 @@ bitmap_element_allocate.exit:
 
 
 ; CHECK:       polly.stmt.cond.end73.i:
-; CHECK-NEXT:   %0 = bitcast %structty** %b.s2a to i8**
-; CHECK-NEXT:   store i8* undef, i8** %0
+; CHECK-NEXT:   store %structty* undef, %structty** %b.s2a
 ; CHECK-NEXT:   br label %polly.exiting