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Merge pull request ARMmbed#665 from bcostm/master
Toolchain: NUCLEO_F0 - Add missing files for IAR exporter
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‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/startup_stm32f030x8.s

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;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
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;* File Name : startup_stm32f030x8.s
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;* Author : MCD Application Team
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;* Version : V2.1.0
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;* Date : 03-Oct-2014
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;* Description : STM32F030x8 devices vector table for EWARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == __iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address,
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;* - Branches to main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M0 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;*******************************************************************************
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;*
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;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;*******************************************************************************
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;
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window Watchdog
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DCD 0 ; Reserved
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DCD RTC_IRQHandler ; RTC through EXTI Line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
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DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
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DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
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DCD 0 ; Reserved
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
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DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
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DCD ADC1_IRQHandler ; ADC1
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DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD 0 ; Reserved
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM6_IRQHandler ; TIM6
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DCD 0 ; Reserved
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DCD TIM14_IRQHandler ; TIM14
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DCD TIM15_IRQHandler ; TIM15
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DCD TIM16_IRQHandler ; TIM16
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DCD TIM17_IRQHandler ; TIM17
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DCD I2C1_IRQHandler ; I2C1
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DCD I2C2_IRQHandler ; I2C2
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:NOROOT:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDG_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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WWDG_IRQHandler
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B WWDG_IRQHandler
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PUBWEAK RTC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RTC_IRQHandler
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B RTC_IRQHandler
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PUBWEAK FLASH_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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FLASH_IRQHandler
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B FLASH_IRQHandler
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PUBWEAK RCC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RCC_IRQHandler
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B RCC_IRQHandler
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PUBWEAK EXTI0_1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI0_1_IRQHandler
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B EXTI0_1_IRQHandler
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PUBWEAK EXTI2_3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI2_3_IRQHandler
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B EXTI2_3_IRQHandler
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PUBWEAK EXTI4_15_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI4_15_IRQHandler
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B EXTI4_15_IRQHandler
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PUBWEAK DMA1_Channel1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel1_IRQHandler
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B DMA1_Channel1_IRQHandler
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PUBWEAK DMA1_Channel2_3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel2_3_IRQHandler
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B DMA1_Channel2_3_IRQHandler
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PUBWEAK DMA1_Channel4_5_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel4_5_IRQHandler
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B DMA1_Channel4_5_IRQHandler
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PUBWEAK ADC1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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ADC1_IRQHandler
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B ADC1_IRQHandler
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PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_BRK_UP_TRG_COM_IRQHandler
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B TIM1_BRK_UP_TRG_COM_IRQHandler
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PUBWEAK TIM1_CC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_CC_IRQHandler
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B TIM1_CC_IRQHandler
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PUBWEAK TIM3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM3_IRQHandler
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B TIM3_IRQHandler
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PUBWEAK TIM6_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM6_IRQHandler
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B TIM6_IRQHandler
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PUBWEAK TIM14_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM14_IRQHandler
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B TIM14_IRQHandler
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PUBWEAK TIM15_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM15_IRQHandler
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B TIM15_IRQHandler
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PUBWEAK TIM16_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM16_IRQHandler
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B TIM16_IRQHandler
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PUBWEAK TIM17_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM17_IRQHandler
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B TIM17_IRQHandler
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PUBWEAK I2C1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_IRQHandler
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B I2C1_IRQHandler
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PUBWEAK I2C2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C2_IRQHandler
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B I2C2_IRQHandler
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PUBWEAK SPI1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI1_IRQHandler
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B SPI1_IRQHandler
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PUBWEAK SPI2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI2_IRQHandler
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B SPI2_IRQHandler
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PUBWEAK USART1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART1_IRQHandler
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B USART1_IRQHandler
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PUBWEAK USART2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART2_IRQHandler
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B USART2_IRQHandler
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf

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/* [ROM = 64kb = 0x10000] */
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define symbol __intvec_start__ = 0x08000000;
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define symbol __region_ROM_start__ = 0x08000000;
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define symbol __region_ROM_end__ = 0x0800FFFF;
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/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 45 vectors = 180 bytes (0xB4) to be reserved in RAM */
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define symbol __NVIC_start__ = 0x20000000;
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define symbol __NVIC_end__ = 0x200000B7; /* Add 4 more bytes to be aligned on 8 bytes */
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define symbol __region_RAM_start__ = 0x200000B8;
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define symbol __region_RAM_end__ = 0x20001FFF;
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/* Memory regions */
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
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define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
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/* Stack and Heap */
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define symbol __size_cstack__ = 0x400;
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define symbol __size_heap__ = 0x400;
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define block CSTACK with alignment = 8, size = __size_cstack__ { };
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define block HEAP with alignment = 8, size = __size_heap__ { };
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define block STACKHEAP with fixed order { block HEAP, block CSTACK };
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initialize by copy with packing = zeros { readwrite };
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do not initialize { section .noinit };
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place at address mem:__intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite, block STACKHEAP };

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