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Commits on Sep 21, 2021

• Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20210921' into staging

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• Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921' into staging

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• target/arm: Optimize MVE 1op-immediate insns

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• target/arm: Optimize MVE VSLI and VSRI

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• target/arm: Optimize MVE VSHLL and VMOVL

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• target/arm: Optimize MVE VSHL, VSHR immediate forms

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• target/arm: Optimize MVE VMVN

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• target/arm: Optimize MVE VDUP

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• target/arm: Optimize MVE VNEG, VABS

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• target/arm: Optimize MVE arithmetic ops

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• target/arm: Optimize MVE logic ops

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• target/arm: Add TB flag for "MVE insns not predicated"

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• target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration

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• target/arm: Avoid goto_tb if we're trying to exit to the main loop

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• hvf: arm: Add rudimentary PMC support

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• arm: Add Hypervisor.framework build target

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• hvf: arm: Implement PSCI handling

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• hvf: arm: Implement -cpu host

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• arm/hvf: Add a WFI handler

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• Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' into staging

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• hw/riscv: opentitan: Correct the USB Dev address

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  alistair23

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• target/riscv: csr: Rename HCOUNTEREN_CY and friends

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• target/riscv: Backup/restore mstatus.SD bit when virtual register swapped

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  Frank Chang

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Commits on Sep 20, 2021

• docs/system/riscv: sifive_u: Update U-Boot instructions

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• hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer

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  Frank Chang

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  alistair23

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• hw/dma: sifive_pdma: allow non-multiple transaction size transactions

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• hw/dma: sifive_pdma: claim bit must be set before DMA transactions

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  Frank Chang

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  alistair23

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• hw/dma: sifive_pdma: reset Next* registers when Control.claim is set

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  Frank Chang

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  alistair23

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• hw/riscv: virt: Add optional ACLINT support to virt machine

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  avpatel

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• hw/riscv: virt: Re-factor FDT generation

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  avpatel

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• hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

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  avpatel

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  alistair23

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• hw/intc: Rename sifive_clint sources to riscv_aclint sources

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  avpatel

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  alistair23

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• sifive_u: Connect the SiFive PWM device

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  alistair23

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• hw/timer: Add SiFive PWM support

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• hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines

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