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op_helper.c
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/*
* PowerPC emulation helpers for qemu.
*
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include "exec.h"
#include "host-utils.h"
#include "helper.h"
#include "helper_regs.h"
//#define DEBUG_OP
//#define DEBUG_EXCEPTIONS
//#define DEBUG_SOFTWARE_TLB
#ifdef DEBUG_SOFTWARE_TLB
# define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
#else
# define LOG_SWTLB(...) do { } while (0)
#endif
/*****************************************************************************/
/* Exceptions processing helpers */
void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
{
#if 0
printf("Raise exception %3x code : %d\n", exception, error_code);
#endif
env->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit();
}
void helper_raise_exception (uint32_t exception)
{
helper_raise_exception_err(exception, 0);
}
/*****************************************************************************/
/* SPR accesses */
void helper_load_dump_spr (uint32_t sprn)
{
qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
env->spr[sprn]);
}
void helper_store_dump_spr (uint32_t sprn)
{
qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
env->spr[sprn]);
}
target_ulong helper_load_tbl (void)
{
return cpu_ppc_load_tbl(env);
}
target_ulong helper_load_tbu (void)
{
return cpu_ppc_load_tbu(env);
}
target_ulong helper_load_atbl (void)
{
return cpu_ppc_load_atbl(env);
}
target_ulong helper_load_atbu (void)
{
return cpu_ppc_load_atbu(env);
}
target_ulong helper_load_601_rtcl (void)
{
return cpu_ppc601_load_rtcl(env);
}
target_ulong helper_load_601_rtcu (void)
{
return cpu_ppc601_load_rtcu(env);
}
#if !defined(CONFIG_USER_ONLY)
#if defined (TARGET_PPC64)
void helper_store_asr (target_ulong val)
{
ppc_store_asr(env, val);
}
#endif
void helper_store_sdr1 (target_ulong val)
{
ppc_store_sdr1(env, val);
}
void helper_store_tbl (target_ulong val)
{
cpu_ppc_store_tbl(env, val);
}
void helper_store_tbu (target_ulong val)
{
cpu_ppc_store_tbu(env, val);
}
void helper_store_atbl (target_ulong val)
{
cpu_ppc_store_atbl(env, val);
}
void helper_store_atbu (target_ulong val)
{
cpu_ppc_store_atbu(env, val);
}
void helper_store_601_rtcl (target_ulong val)
{
cpu_ppc601_store_rtcl(env, val);
}
void helper_store_601_rtcu (target_ulong val)
{
cpu_ppc601_store_rtcu(env, val);
}
target_ulong helper_load_decr (void)
{
return cpu_ppc_load_decr(env);
}
void helper_store_decr (target_ulong val)
{
cpu_ppc_store_decr(env, val);
}
void helper_store_hid0_601 (target_ulong val)
{
target_ulong hid0;
hid0 = env->spr[SPR_HID0];
if ((val ^ hid0) & 0x00000008) {
/* Change current endianness */
env->hflags &= ~(1 << MSR_LE);
env->hflags_nmsr &= ~(1 << MSR_LE);
env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
env->hflags |= env->hflags_nmsr;
qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
val & 0x8 ? 'l' : 'b', env->hflags);
}
env->spr[SPR_HID0] = (uint32_t)val;
}
void helper_store_403_pbr (uint32_t num, target_ulong value)
{
if (likely(env->pb[num] != value)) {
env->pb[num] = value;
/* Should be optimized */
tlb_flush(env, 1);
}
}
target_ulong helper_load_40x_pit (void)
{
return load_40x_pit(env);
}
void helper_store_40x_pit (target_ulong val)
{
store_40x_pit(env, val);
}
void helper_store_40x_dbcr0 (target_ulong val)
{
store_40x_dbcr0(env, val);
}
void helper_store_40x_sler (target_ulong val)
{
store_40x_sler(env, val);
}
void helper_store_booke_tcr (target_ulong val)
{
store_booke_tcr(env, val);
}
void helper_store_booke_tsr (target_ulong val)
{
store_booke_tsr(env, val);
}
void helper_store_ibatu (uint32_t nr, target_ulong val)
{
ppc_store_ibatu(env, nr, val);
}
void helper_store_ibatl (uint32_t nr, target_ulong val)
{
ppc_store_ibatl(env, nr, val);
}
void helper_store_dbatu (uint32_t nr, target_ulong val)
{
ppc_store_dbatu(env, nr, val);
}
void helper_store_dbatl (uint32_t nr, target_ulong val)
{
ppc_store_dbatl(env, nr, val);
}
void helper_store_601_batl (uint32_t nr, target_ulong val)
{
ppc_store_ibatl_601(env, nr, val);
}
void helper_store_601_batu (uint32_t nr, target_ulong val)
{
ppc_store_ibatu_601(env, nr, val);
}
#endif
/*****************************************************************************/
/* Memory load and stores */
static inline target_ulong addr_add(target_ulong addr, target_long arg)
{
#if defined(TARGET_PPC64)
if (!msr_sf)
return (uint32_t)(addr + arg);
else
#endif
return addr + arg;
}
void helper_lmw (target_ulong addr, uint32_t reg)
{
for (; reg < 32; reg++) {
if (msr_le)
env->gpr[reg] = bswap32(ldl(addr));
else
env->gpr[reg] = ldl(addr);
addr = addr_add(addr, 4);
}
}
void helper_stmw (target_ulong addr, uint32_t reg)
{
for (; reg < 32; reg++) {
if (msr_le)
stl(addr, bswap32((uint32_t)env->gpr[reg]));
else
stl(addr, (uint32_t)env->gpr[reg]);
addr = addr_add(addr, 4);
}
}
void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
{
int sh;
for (; nb > 3; nb -= 4) {
env->gpr[reg] = ldl(addr);
reg = (reg + 1) % 32;
addr = addr_add(addr, 4);
}
if (unlikely(nb > 0)) {
env->gpr[reg] = 0;
for (sh = 24; nb > 0; nb--, sh -= 8) {
env->gpr[reg] |= ldub(addr) << sh;
addr = addr_add(addr, 1);
}
}
}
/* PPC32 specification says we must generate an exception if
* rA is in the range of registers to be loaded.
* In an other hand, IBM says this is valid, but rA won't be loaded.
* For now, I'll follow the spec...
*/
void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
{
if (likely(xer_bc != 0)) {
if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
(reg < rb && (reg + xer_bc) > rb))) {
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL |
POWERPC_EXCP_INVAL_LSWX);
} else {
helper_lsw(addr, xer_bc, reg);
}
}
}
void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
{
int sh;
for (; nb > 3; nb -= 4) {
stl(addr, env->gpr[reg]);
reg = (reg + 1) % 32;
addr = addr_add(addr, 4);
}
if (unlikely(nb > 0)) {
for (sh = 24; nb > 0; nb--, sh -= 8) {
stb(addr, (env->gpr[reg] >> sh) & 0xFF);
addr = addr_add(addr, 1);
}
}
}
static void do_dcbz(target_ulong addr, int dcache_line_size)
{
addr &= ~(dcache_line_size - 1);
int i;
for (i = 0 ; i < dcache_line_size ; i += 4) {
stl(addr + i , 0);
}
if (env->reserve_addr == addr)
env->reserve_addr = (target_ulong)-1ULL;
}
void helper_dcbz(target_ulong addr)
{
do_dcbz(addr, env->dcache_line_size);
}
void helper_dcbz_970(target_ulong addr)
{
if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
do_dcbz(addr, 32);
else
do_dcbz(addr, env->dcache_line_size);
}
void helper_icbi(target_ulong addr)
{
uint32_t tmp;
addr &= ~(env->dcache_line_size - 1);
/* Invalidate one cache line :
* PowerPC specification says this is to be treated like a load
* (not a fetch) by the MMU. To be sure it will be so,
* do the load "by hand".
*/
tmp = ldl(addr);
tb_invalidate_page_range(addr, addr + env->icache_line_size);
}
// XXX: to be tested
target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
{
int i, c, d;
d = 24;
for (i = 0; i < xer_bc; i++) {
c = ldub(addr);
addr = addr_add(addr, 1);
/* ra (if not 0) and rb are never modified */
if (likely(reg != rb && (ra == 0 || reg != ra))) {
env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
}
if (unlikely(c == xer_cmp))
break;
if (likely(d != 0)) {
d -= 8;
} else {
d = 24;
reg++;
reg = reg & 0x1F;
}
}
return i;
}
/*****************************************************************************/
/* Fixed point operations helpers */
#if defined(TARGET_PPC64)
/* multiply high word */
uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
{
uint64_t tl, th;
muls64(&tl, &th, arg1, arg2);
return th;
}
/* multiply high word unsigned */
uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
{
uint64_t tl, th;
mulu64(&tl, &th, arg1, arg2);
return th;
}
uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
{
int64_t th;
uint64_t tl;
muls64(&tl, (uint64_t *)&th, arg1, arg2);
/* If th != 0 && th != -1, then we had an overflow */
if (likely((uint64_t)(th + 1) <= 1)) {
env->xer &= ~(1 << XER_OV);
} else {
env->xer |= (1 << XER_OV) | (1 << XER_SO);
}
return (int64_t)tl;
}
#endif
target_ulong helper_cntlzw (target_ulong t)
{
return clz32(t);
}
#if defined(TARGET_PPC64)
target_ulong helper_cntlzd (target_ulong t)
{
return clz64(t);
}
#endif
/* shift right arithmetic helper */
target_ulong helper_sraw (target_ulong value, target_ulong shift)
{
int32_t ret;
if (likely(!(shift & 0x20))) {
if (likely((uint32_t)shift != 0)) {
shift &= 0x1f;
ret = (int32_t)value >> shift;
if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
env->xer &= ~(1 << XER_CA);
} else {
env->xer |= (1 << XER_CA);
}
} else {
ret = (int32_t)value;
env->xer &= ~(1 << XER_CA);
}
} else {
ret = (int32_t)value >> 31;
if (ret) {
env->xer |= (1 << XER_CA);
} else {
env->xer &= ~(1 << XER_CA);
}
}
return (target_long)ret;
}
#if defined(TARGET_PPC64)
target_ulong helper_srad (target_ulong value, target_ulong shift)
{
int64_t ret;
if (likely(!(shift & 0x40))) {
if (likely((uint64_t)shift != 0)) {
shift &= 0x3f;
ret = (int64_t)value >> shift;
if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
env->xer &= ~(1 << XER_CA);
} else {
env->xer |= (1 << XER_CA);
}
} else {
ret = (int64_t)value;
env->xer &= ~(1 << XER_CA);
}
} else {
ret = (int64_t)value >> 63;
if (ret) {
env->xer |= (1 << XER_CA);
} else {
env->xer &= ~(1 << XER_CA);
}
}
return ret;
}
#endif
target_ulong helper_popcntb (target_ulong val)
{
val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
return val;
}
#if defined(TARGET_PPC64)
target_ulong helper_popcntb_64 (target_ulong val)
{
val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
return val;
}
#endif
/*****************************************************************************/
/* Floating point operations helpers */
uint64_t helper_float32_to_float64(uint32_t arg)
{
CPU_FloatU f;
CPU_DoubleU d;
f.l = arg;
d.d = float32_to_float64(f.f, &env->fp_status);
return d.ll;
}
uint32_t helper_float64_to_float32(uint64_t arg)
{
CPU_FloatU f;
CPU_DoubleU d;
d.ll = arg;
f.f = float64_to_float32(d.d, &env->fp_status);
return f.l;
}
static inline int isden(float64 d)
{
CPU_DoubleU u;
u.d = d;
return ((u.ll >> 52) & 0x7FF) == 0;
}
uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
{
CPU_DoubleU farg;
int isneg;
int ret;
farg.ll = arg;
isneg = float64_is_neg(farg.d);
if (unlikely(float64_is_nan(farg.d))) {
if (float64_is_signaling_nan(farg.d)) {
/* Signaling NaN: flags are undefined */
ret = 0x00;
} else {
/* Quiet NaN */
ret = 0x11;
}
} else if (unlikely(float64_is_infinity(farg.d))) {
/* +/- infinity */
if (isneg)
ret = 0x09;
else
ret = 0x05;
} else {
if (float64_is_zero(farg.d)) {
/* +/- zero */
if (isneg)
ret = 0x12;
else
ret = 0x02;
} else {
if (isden(farg.d)) {
/* Denormalized numbers */
ret = 0x10;
} else {
/* Normalized numbers */
ret = 0x00;
}
if (isneg) {
ret |= 0x08;
} else {
ret |= 0x04;
}
}
}
if (set_fprf) {
/* We update FPSCR_FPRF */
env->fpscr &= ~(0x1F << FPSCR_FPRF);
env->fpscr |= ret << FPSCR_FPRF;
}
/* We just need fpcc to update Rc1 */
return ret & 0xF;
}
/* Floating-point invalid operations exception */
static inline uint64_t fload_invalid_op_excp(int op)
{
uint64_t ret = 0;
int ve;
ve = fpscr_ve;
switch (op) {
case POWERPC_EXCP_FP_VXSNAN:
env->fpscr |= 1 << FPSCR_VXSNAN;
break;
case POWERPC_EXCP_FP_VXSOFT:
env->fpscr |= 1 << FPSCR_VXSOFT;
break;
case POWERPC_EXCP_FP_VXISI:
/* Magnitude subtraction of infinities */
env->fpscr |= 1 << FPSCR_VXISI;
goto update_arith;
case POWERPC_EXCP_FP_VXIDI:
/* Division of infinity by infinity */
env->fpscr |= 1 << FPSCR_VXIDI;
goto update_arith;
case POWERPC_EXCP_FP_VXZDZ:
/* Division of zero by zero */
env->fpscr |= 1 << FPSCR_VXZDZ;
goto update_arith;
case POWERPC_EXCP_FP_VXIMZ:
/* Multiplication of zero by infinity */
env->fpscr |= 1 << FPSCR_VXIMZ;
goto update_arith;
case POWERPC_EXCP_FP_VXVC:
/* Ordered comparison of NaN */
env->fpscr |= 1 << FPSCR_VXVC;
env->fpscr &= ~(0xF << FPSCR_FPCC);
env->fpscr |= 0x11 << FPSCR_FPCC;
/* We must update the target FPR before raising the exception */
if (ve != 0) {
env->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* Exception is differed */
ve = 0;
}
break;
case POWERPC_EXCP_FP_VXSQRT:
/* Square root of a negative number */
env->fpscr |= 1 << FPSCR_VXSQRT;
update_arith:
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
if (ve == 0) {
/* Set the result to quiet NaN */
ret = 0xFFF8000000000000ULL;
env->fpscr &= ~(0xF << FPSCR_FPCC);
env->fpscr |= 0x11 << FPSCR_FPCC;
}
break;
case POWERPC_EXCP_FP_VXCVI:
/* Invalid conversion */
env->fpscr |= 1 << FPSCR_VXCVI;
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
if (ve == 0) {
/* Set the result to quiet NaN */
ret = 0xFFF8000000000000ULL;
env->fpscr &= ~(0xF << FPSCR_FPCC);
env->fpscr |= 0x11 << FPSCR_FPCC;
}
break;
}
/* Update the floating-point invalid operation summary */
env->fpscr |= 1 << FPSCR_VX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
if (ve != 0) {
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
if (msr_fe0 != 0 || msr_fe1 != 0)
helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
}
return ret;
}
static inline void float_zero_divide_excp(void)
{
env->fpscr |= 1 << FPSCR_ZX;
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_ze != 0) {
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
if (msr_fe0 != 0 || msr_fe1 != 0) {
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
}
}
}
static inline void float_overflow_excp(void)
{
env->fpscr |= 1 << FPSCR_OX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_oe != 0) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
env->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
} else {
env->fpscr |= 1 << FPSCR_XX;
env->fpscr |= 1 << FPSCR_FI;
}
}
static inline void float_underflow_excp(void)
{
env->fpscr |= 1 << FPSCR_UX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_ue != 0) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
env->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
}
}
static inline void float_inexact_excp(void)
{
env->fpscr |= 1 << FPSCR_XX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_xe != 0) {
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
env->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
}
}
static inline void fpscr_set_rounding_mode(void)
{
int rnd_type;
/* Set rounding mode */
switch (fpscr_rn) {
case 0:
/* Best approximation (round to nearest) */
rnd_type = float_round_nearest_even;
break;
case 1:
/* Smaller magnitude (round toward zero) */
rnd_type = float_round_to_zero;
break;
case 2:
/* Round toward +infinite */
rnd_type = float_round_up;
break;
default:
case 3:
/* Round toward -infinite */
rnd_type = float_round_down;
break;
}
set_float_rounding_mode(rnd_type, &env->fp_status);
}
void helper_fpscr_clrbit (uint32_t bit)
{
int prev;
prev = (env->fpscr >> bit) & 1;
env->fpscr &= ~(1 << bit);
if (prev == 1) {
switch (bit) {
case FPSCR_RN1:
case FPSCR_RN:
fpscr_set_rounding_mode();
break;
default:
break;
}
}
}
void helper_fpscr_setbit (uint32_t bit)
{
int prev;
prev = (env->fpscr >> bit) & 1;
env->fpscr |= 1 << bit;
if (prev == 0) {
switch (bit) {
case FPSCR_VX:
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_ve)
goto raise_ve;
case FPSCR_OX:
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_oe)
goto raise_oe;
break;
case FPSCR_UX:
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_ue)
goto raise_ue;
break;
case FPSCR_ZX:
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_ze)
goto raise_ze;
break;
case FPSCR_XX:
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_xe)
goto raise_xe;
break;
case FPSCR_VXSNAN:
case FPSCR_VXISI:
case FPSCR_VXIDI:
case FPSCR_VXZDZ:
case FPSCR_VXIMZ:
case FPSCR_VXVC:
case FPSCR_VXSOFT:
case FPSCR_VXSQRT:
case FPSCR_VXCVI:
env->fpscr |= 1 << FPSCR_VX;
env->fpscr |= 1 << FPSCR_FX;
if (fpscr_ve != 0)
goto raise_ve;
break;
case FPSCR_VE:
if (fpscr_vx != 0) {
raise_ve:
env->error_code = POWERPC_EXCP_FP;
if (fpscr_vxsnan)
env->error_code |= POWERPC_EXCP_FP_VXSNAN;
if (fpscr_vxisi)
env->error_code |= POWERPC_EXCP_FP_VXISI;
if (fpscr_vxidi)
env->error_code |= POWERPC_EXCP_FP_VXIDI;
if (fpscr_vxzdz)
env->error_code |= POWERPC_EXCP_FP_VXZDZ;
if (fpscr_vximz)
env->error_code |= POWERPC_EXCP_FP_VXIMZ;
if (fpscr_vxvc)
env->error_code |= POWERPC_EXCP_FP_VXVC;
if (fpscr_vxsoft)
env->error_code |= POWERPC_EXCP_FP_VXSOFT;
if (fpscr_vxsqrt)
env->error_code |= POWERPC_EXCP_FP_VXSQRT;
if (fpscr_vxcvi)
env->error_code |= POWERPC_EXCP_FP_VXCVI;
goto raise_excp;
}
break;
case FPSCR_OE:
if (fpscr_ox != 0) {
raise_oe:
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
goto raise_excp;
}
break;
case FPSCR_UE:
if (fpscr_ux != 0) {
raise_ue:
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
goto raise_excp;
}
break;
case FPSCR_ZE:
if (fpscr_zx != 0) {
raise_ze:
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
goto raise_excp;
}
break;
case FPSCR_XE:
if (fpscr_xx != 0) {
raise_xe:
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
goto raise_excp;
}
break;
case FPSCR_RN1:
case FPSCR_RN:
fpscr_set_rounding_mode();
break;
default:
break;
raise_excp:
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We have to update Rc1 before raising the exception */
env->exception_index = POWERPC_EXCP_PROGRAM;
break;
}
}
}
void helper_store_fpscr (uint64_t arg, uint32_t mask)
{
/*
* We use only the 32 LSB of the incoming fpr
*/
uint32_t prev, new;
int i;
prev = env->fpscr;
new = (uint32_t)arg;
new &= ~0x60000000;
new |= prev & 0x60000000;
for (i = 0; i < 8; i++) {
if (mask & (1 << i)) {
env->fpscr &= ~(0xF << (4 * i));
env->fpscr |= new & (0xF << (4 * i));
}
}
/* Update VX and FEX */
if (fpscr_ix != 0)
env->fpscr |= 1 << FPSCR_VX;
else
env->fpscr &= ~(1 << FPSCR_VX);
if ((fpscr_ex & fpscr_eex) != 0) {
env->fpscr |= 1 << FPSCR_FEX;
env->exception_index = POWERPC_EXCP_PROGRAM;
/* XXX: we should compute it properly */
env->error_code = POWERPC_EXCP_FP;
}
else
env->fpscr &= ~(1 << FPSCR_FEX);
fpscr_set_rounding_mode();
}
void helper_float_check_status (void)
{
#ifdef CONFIG_SOFTFLOAT
if (env->exception_index == POWERPC_EXCP_PROGRAM &&
(env->error_code & POWERPC_EXCP_FP)) {
/* Differred floating-point exception after target FPR update */
if (msr_fe0 != 0 || msr_fe1 != 0)
helper_raise_exception_err(env->exception_index, env->error_code);
} else {
int status = get_float_exception_flags(&env->fp_status);
if (status & float_flag_divbyzero) {
float_zero_divide_excp();
} else if (status & float_flag_overflow) {
float_overflow_excp();
} else if (status & float_flag_underflow) {
float_underflow_excp();
} else if (status & float_flag_inexact) {
float_inexact_excp();
}
}
#else
if (env->exception_index == POWERPC_EXCP_PROGRAM &&
(env->error_code & POWERPC_EXCP_FP)) {
/* Differred floating-point exception after target FPR update */
if (msr_fe0 != 0 || msr_fe1 != 0)
helper_raise_exception_err(env->exception_index, env->error_code);
}
#endif
}
#ifdef CONFIG_SOFTFLOAT
void helper_reset_fpstatus (void)
{
set_float_exception_flags(0, &env->fp_status);
}
#endif
/* fadd - fadd. */
uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
{
CPU_DoubleU farg1, farg2;
farg1.ll = arg1;
farg2.ll = arg2;
#if USE_PRECISE_EMULATION
if (unlikely(float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d))) {
/* sNaN addition */
farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
/* Magnitude subtraction of infinities */
farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
} else {
farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
}
#else
farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
#endif
return farg1.ll;
}
/* fsub - fsub. */
uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
{
CPU_DoubleU farg1, farg2;