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translate.c
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/*
* OpenRISC translation
*
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
* Feng Gao <gf91597@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
#include "qemu-common.h"
#include "qemu-log.h"
#include "config.h"
#include "bitops.h"
#include "helper.h"
#define GEN_HELPER 1
#include "helper.h"
#define OPENRISC_DISAS
#ifdef OPENRISC_DISAS
# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
#else
# define LOG_DIS(...) do { } while (0)
#endif
typedef struct DisasContext {
TranslationBlock *tb;
target_ulong pc, ppc, npc;
uint32_t tb_flags, synced_flags, flags;
uint32_t is_jmp;
uint32_t mem_idx;
int singlestep_enabled;
uint32_t delayed_branch;
} DisasContext;
static TCGv_ptr cpu_env;
static TCGv cpu_sr;
static TCGv cpu_R[32];
static TCGv cpu_pc;
static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
static TCGv cpu_npc;
static TCGv cpu_ppc;
static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
static TCGv_i32 fpcsr;
static TCGv machi, maclo;
static TCGv fpmaddhi, fpmaddlo;
static TCGv_i32 env_flags;
#include "gen-icount.h"
void openrisc_translate_init(void)
{
static const char * const regnames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
};
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_sr = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, sr), "sr");
env_flags = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState, flags),
"flags");
cpu_pc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, pc), "pc");
cpu_npc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, npc), "npc");
cpu_ppc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, ppc), "ppc");
jmp_pc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
env_btaken = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState, btaken),
"btaken");
fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState, fpcsr),
"fpcsr");
machi = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, machi),
"machi");
maclo = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, maclo),
"maclo");
fpmaddhi = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, fpmaddhi),
"fpmaddhi");
fpmaddlo = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, fpmaddlo),
"fpmaddlo");
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, gpr[i]),
regnames[i]);
}
#define GEN_HELPER 2
#include "helper.h"
}
/* Writeback SR_F transaltion-space to execution-space. */
static inline void wb_SR_F(void)
{
int label;
label = gen_new_label();
tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
gen_set_label(label);
}
static inline int zero_extend(unsigned int val, int width)
{
return val & ((1 << width) - 1);
}
static inline int sign_extend(unsigned int val, int width)
{
int sval;
/* LSL */
val <<= TARGET_LONG_BITS - width;
sval = val;
/* ASR. */
sval >>= TARGET_LONG_BITS - width;
return sval;
}
static inline void gen_sync_flags(DisasContext *dc)
{
/* Sync the tb dependent flag between translate and runtime. */
if (dc->tb_flags != dc->synced_flags) {
tcg_gen_movi_tl(env_flags, dc->tb_flags);
dc->synced_flags = dc->tb_flags;
}
}
static void gen_exception(DisasContext *dc, unsigned int excp)
{
TCGv_i32 tmp = tcg_const_i32(excp);
gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
}
static void gen_illegal_exception(DisasContext *dc)
{
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_ILLEGAL);
dc->is_jmp = DISAS_UPDATE;
}
/* not used yet, open it when we need or64. */
/*#ifdef TARGET_OPENRISC64
static void check_ob64s(DisasContext *dc)
{
if (!(dc->flags & CPUCFGR_OB64S)) {
gen_illegal_exception(dc);
}
}
static void check_of64s(DisasContext *dc)
{
if (!(dc->flags & CPUCFGR_OF64S)) {
gen_illegal_exception(dc);
}
}
static void check_ov64s(DisasContext *dc)
{
if (!(dc->flags & CPUCFGR_OV64S)) {
gen_illegal_exception(dc);
}
}
#endif*/
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
{
TranslationBlock *tb;
tb = dc->tb;
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
likely(!dc->singlestep_enabled)) {
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_goto_tb(n);
tcg_gen_exit_tb((tcg_target_long)tb + n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
if (dc->singlestep_enabled) {
gen_exception(dc, EXCP_DEBUG);
}
tcg_gen_exit_tb(0);
}
}
static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
{
target_ulong tmp_pc;
int lab = gen_new_label();
TCGv sr_f = tcg_temp_new();
/* N26, 26bits imm */
tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
if (op0 == 0x00) { /* l.j */
tcg_gen_movi_tl(jmp_pc, tmp_pc);
} else if (op0 == 0x01) { /* l.jal */
tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
tcg_gen_movi_tl(jmp_pc, tmp_pc);
} else if (op0 == 0x03) { /* l.bnf */
tcg_gen_movi_tl(jmp_pc, dc->pc+8);
tcg_gen_brcondi_i32(TCG_COND_EQ, sr_f, SR_F, lab);
tcg_gen_movi_tl(jmp_pc, tmp_pc);
gen_set_label(lab);
} else if (op0 == 0x04) { /* l.bf */
tcg_gen_movi_tl(jmp_pc, dc->pc+8);
tcg_gen_brcondi_i32(TCG_COND_NE, sr_f, SR_F, lab);
tcg_gen_movi_tl(jmp_pc, tmp_pc);
gen_set_label(lab);
} else if (op0 == 0x11) { /* l.jr */
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
} else if (op0 == 0x12) { /* l.jalr */
tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
} else {
gen_illegal_exception(dc);
}
tcg_temp_free(sr_f);
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
gen_sync_flags(dc);
}
static void dec_calc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1, op2;
uint32_t ra, rb, rd;
op0 = extract32(insn, 0, 4);
op1 = extract32(insn, 8, 2);
op2 = extract32(insn, 6, 2);
ra = extract32(insn, 16, 5);
rb = extract32(insn, 11, 5);
rd = extract32(insn, 21, 5);
switch (op0) {
case 0x0000:
switch (op1) {
case 0x00: /* l.add */
LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
{
int lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i32 res = tcg_temp_local_new_i32();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
tcg_gen_add_i64(td, ta, tb);
tcg_gen_trunc_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 31);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab);
tcg_gen_mov_i32(cpu_R[rd], res);
tcg_temp_free_i64(ta);
tcg_temp_free_i64(tb);
tcg_temp_free_i64(td);
tcg_temp_free_i32(res);
tcg_temp_free_i32(sr_ove);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0001: /* l.addc */
switch (op1) {
case 0x00:
LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
{
int lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 tcy = tcg_temp_local_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i32 res = tcg_temp_local_new_i32();
TCGv_i32 sr_cy = tcg_temp_local_new_i32();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
tcg_gen_extu_i32_i64(tcy, sr_cy);
tcg_gen_shri_i64(tcy, tcy, 10);
tcg_gen_add_i64(td, ta, tb);
tcg_gen_add_i64(td, td, tcy);
tcg_gen_trunc_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 32);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab);
tcg_gen_mov_i32(cpu_R[rd], res);
tcg_temp_free_i64(ta);
tcg_temp_free_i64(tb);
tcg_temp_free_i64(tcy);
tcg_temp_free_i64(td);
tcg_temp_free_i32(res);
tcg_temp_free_i32(sr_cy);
tcg_temp_free_i32(sr_ove);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0002: /* l.sub */
switch (op1) {
case 0x00:
LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
{
int lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i32 res = tcg_temp_local_new_i32();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
tcg_gen_sub_i64(td, ta, tb);
tcg_gen_trunc_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 31);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab);
tcg_gen_mov_i32(cpu_R[rd], res);
tcg_temp_free_i64(ta);
tcg_temp_free_i64(tb);
tcg_temp_free_i64(td);
tcg_temp_free_i32(res);
tcg_temp_free_i32(sr_ove);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0003: /* l.and */
switch (op1) {
case 0x00:
LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb);
tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0004: /* l.or */
switch (op1) {
case 0x00:
LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb);
tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0005:
switch (op1) {
case 0x00: /* l.xor */
LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb);
tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0006:
switch (op1) {
case 0x03: /* l.mul */
LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb);
if (ra != 0 && rb != 0) {
gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
} else {
tcg_gen_movi_tl(cpu_R[rd], 0x0);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0009:
switch (op1) {
case 0x03: /* l.div */
LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
{
int lab0 = gen_new_label();
int lab1 = gen_new_label();
int lab2 = gen_new_label();
int lab3 = gen_new_label();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
if (rb == 0) {
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab0);
} else {
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb],
0x00000000, lab1);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra],
0x80000000, lab2);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
0xffffffff, lab2);
gen_set_label(lab1);
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab2);
tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
gen_set_label(lab3);
}
tcg_temp_free_i32(sr_ove);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x000a:
switch (op1) {
case 0x03: /* l.divu */
LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
{
int lab0 = gen_new_label();
int lab1 = gen_new_label();
int lab2 = gen_new_label();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
if (rb == 0) {
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab0);
} else {
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
0x00000000, lab1);
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab1);
tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
gen_set_label(lab2);
}
tcg_temp_free_i32(sr_ove);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x000b:
switch (op1) {
case 0x03: /* l.mulu */
LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb);
if (rb != 0 && ra != 0) {
TCGv_i64 result = tcg_temp_local_new_i64();
TCGv_i64 tra = tcg_temp_local_new_i64();
TCGv_i64 trb = tcg_temp_local_new_i64();
TCGv_i64 high = tcg_temp_new_i64();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
int lab = gen_new_label();
/* Calculate the each result. */
tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
tcg_gen_mul_i64(result, tra, trb);
tcg_temp_free_i64(tra);
tcg_temp_free_i64(trb);
tcg_gen_shri_i64(high, result, TARGET_LONG_BITS);
/* Overflow or not. */
tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab);
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab);
tcg_temp_free_i64(high);
tcg_gen_trunc_i64_tl(cpu_R[rd], result);
tcg_temp_free_i64(result);
tcg_temp_free_i32(sr_ove);
} else {
tcg_gen_movi_tl(cpu_R[rd], 0);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x000e:
switch (op1) {
case 0x00: /* l.cmov */
LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
{
int lab = gen_new_label();
TCGv res = tcg_temp_local_new();
TCGv sr_f = tcg_temp_new();
tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
tcg_gen_mov_tl(res, cpu_R[rb]);
tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
tcg_gen_mov_tl(res, cpu_R[ra]);
gen_set_label(lab);
tcg_gen_mov_tl(cpu_R[rd], res);
tcg_temp_free(sr_f);
tcg_temp_free(res);
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x000f:
switch (op1) {
case 0x00: /* l.ff1 */
LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_ff1(cpu_R[rd], cpu_R[ra]);
break;
case 0x01: /* l.fl1 */
LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_fl1(cpu_R[rd], cpu_R[ra]);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x0008:
switch (op1) {
case 0x00:
switch (op2) {
case 0x00: /* l.sll */
LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb);
tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
break;
case 0x01: /* l.srl */
LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb);
tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
break;
case 0x02: /* l.sra */
LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb);
tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
break;
case 0x03: /* l.ror */
LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb);
tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x000c:
switch (op1) {
case 0x00:
switch (op2) {
case 0x00: /* l.exths */
LOG_DIS("l.exths r%d, r%d\n", rd, ra);
tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]);
break;
case 0x01: /* l.extbs */
LOG_DIS("l.extbs r%d, r%d\n", rd, ra);
tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]);
break;
case 0x02: /* l.exthz */
LOG_DIS("l.exthz r%d, r%d\n", rd, ra);
tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]);
break;
case 0x03: /* l.extbz */
LOG_DIS("l.extbz r%d, r%d\n", rd, ra);
tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x000d:
switch (op1) {
case 0x00:
switch (op2) {
case 0x00: /* l.extws */
LOG_DIS("l.extws r%d, r%d\n", rd, ra);
tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]);
break;
case 0x01: /* l.extwz */
LOG_DIS("l.extwz r%d, r%d\n", rd, ra);
tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
default:
gen_illegal_exception(dc);
break;
}
break;
default:
gen_illegal_exception(dc);
break;
}
}
static void dec_misc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1;
uint32_t ra, rb, rd;
#ifdef OPENRISC_DISAS
uint32_t L6, K5;
#endif
uint32_t I16, I5, I11, N26, tmp;
op0 = extract32(insn, 26, 6);
op1 = extract32(insn, 24, 2);
ra = extract32(insn, 16, 5);
rb = extract32(insn, 11, 5);
rd = extract32(insn, 21, 5);
#ifdef OPENRISC_DISAS
L6 = extract32(insn, 5, 6);
K5 = extract32(insn, 0, 5);
#endif
I16 = extract32(insn, 0, 16);
I5 = extract32(insn, 21, 5);
I11 = extract32(insn, 0, 11);
N26 = extract32(insn, 0, 26);
tmp = (I5<<11) + I11;
switch (op0) {
case 0x00: /* l.j */
LOG_DIS("l.j %d\n", N26);
gen_jump(dc, N26, 0, op0);
break;
case 0x01: /* l.jal */
LOG_DIS("l.jal %d\n", N26);
gen_jump(dc, N26, 0, op0);
break;
case 0x03: /* l.bnf */
LOG_DIS("l.bnf %d\n", N26);
gen_jump(dc, N26, 0, op0);
break;
case 0x04: /* l.bf */
LOG_DIS("l.bf %d\n", N26);
gen_jump(dc, N26, 0, op0);
break;
case 0x05:
switch (op1) {
case 0x01: /* l.nop */
LOG_DIS("l.nop %d\n", I16);
break;
default:
gen_illegal_exception(dc);
break;
}
break;
case 0x11: /* l.jr */
LOG_DIS("l.jr r%d\n", rb);
gen_jump(dc, 0, rb, op0);
break;
case 0x12: /* l.jalr */
LOG_DIS("l.jalr r%d\n", rb);
gen_jump(dc, 0, rb, op0);
break;
case 0x13: /* l.maci */
LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11);
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i32 dst = tcg_temp_new_i32();
TCGv ttmp = tcg_const_tl(tmp);
tcg_gen_mul_tl(dst, cpu_R[ra], ttmp);
tcg_gen_ext_i32_i64(t1, dst);
tcg_gen_concat_i32_i64(t2, maclo, machi);
tcg_gen_add_i64(t2, t2, t1);
tcg_gen_trunc_i64_i32(maclo, t2);
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_i32(machi, t2);
tcg_temp_free_i32(dst);
tcg_temp_free(ttmp);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}
break;
case 0x09: /* l.rfe */
LOG_DIS("l.rfe\n");
{
#if defined(CONFIG_USER_ONLY)
return;
#else
if (dc->mem_idx == MMU_USER_IDX) {
gen_illegal_exception(dc);
return;
}
gen_helper_rfe(cpu_env);
dc->is_jmp = DISAS_UPDATE;
#endif
}
break;
case 0x1c: /* l.cust1 */
LOG_DIS("l.cust1\n");
break;
case 0x1d: /* l.cust2 */
LOG_DIS("l.cust2\n");
break;
case 0x1e: /* l.cust3 */
LOG_DIS("l.cust3\n");
break;
case 0x1f: /* l.cust4 */
LOG_DIS("l.cust4\n");
break;
case 0x3c: /* l.cust5 */
LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5);
break;
case 0x3d: /* l.cust6 */
LOG_DIS("l.cust6\n");
break;
case 0x3e: /* l.cust7 */
LOG_DIS("l.cust7\n");
break;
case 0x3f: /* l.cust8 */
LOG_DIS("l.cust8\n");
break;
/* not used yet, open it when we need or64. */
/*#ifdef TARGET_OPENRISC64
case 0x20: l.ld
LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
{
check_ob64s(dc);
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
tcg_gen_qemu_ld64(cpu_R[rd], t0, dc->mem_idx);
tcg_temp_free_i64(t0);
}
break;
#endif*/
case 0x21: /* l.lwz */
LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc->mem_idx);
tcg_temp_free(t0);
}
break;
case 0x22: /* l.lws */
LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc->mem_idx);
tcg_temp_free(t0);
}
break;
case 0x23: /* l.lbz */
LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc->mem_idx);
tcg_temp_free(t0);
}
break;
case 0x24: /* l.lbs */
LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc->mem_idx);
tcg_temp_free(t0);
}
break;
case 0x25: /* l.lhz */
LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc->mem_idx);
tcg_temp_free(t0);
}
break;
case 0x26: /* l.lhs */
LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc->mem_idx);
tcg_temp_free(t0);
}
break;
case 0x27: /* l.addi */
LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
{
int lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i32 res = tcg_temp_local_new_i32();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
tcg_gen_trunc_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 32);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab);
tcg_gen_mov_i32(cpu_R[rd], res);
tcg_temp_free_i64(ta);
tcg_temp_free_i64(td);
tcg_temp_free_i32(res);
tcg_temp_free_i32(sr_ove);
}
break;
case 0x28: /* l.addic */
LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
{
int lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i64 tcy = tcg_temp_local_new_i64();
TCGv_i32 res = tcg_temp_local_new_i32();
TCGv_i32 sr_cy = tcg_temp_local_new_i32();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
tcg_gen_shri_i32(sr_cy, sr_cy, 10);
tcg_gen_extu_i32_i64(tcy, sr_cy);
tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
tcg_gen_add_i64(td, td, tcy);
tcg_gen_trunc_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 32);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
gen_exception(dc, EXCP_RANGE);
gen_set_label(lab);
tcg_gen_mov_i32(cpu_R[rd], res);
tcg_temp_free_i64(ta);
tcg_temp_free_i64(td);
tcg_temp_free_i64(tcy);
tcg_temp_free_i32(res);
tcg_temp_free_i32(sr_cy);
tcg_temp_free_i32(sr_ove);
}
break;
case 0x29: /* l.andi */
LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16);
tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
break;
case 0x2a: /* l.ori */
LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16);
tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
break;
case 0x2b: /* l.xori */
LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16);
tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16));
break;
case 0x2c: /* l.muli */
LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16);
if (ra != 0 && I16 != 0) {
TCGv_i32 im = tcg_const_i32(I16);
gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], im);
tcg_temp_free_i32(im);
} else {
tcg_gen_movi_tl(cpu_R[rd], 0x0);
}
break;
case 0x2d: /* l.mfspr */
LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16);
{