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Merge pull request #335 from intel/EMR_cstate_addition
Adding C0/C6 state metrics to EMR and SPR
2 parents 48c0518 + 29c3a94 commit ded3a8b

7 files changed

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-8
lines changed

‎EMR/metrics/emeraldrapids_metrics.json‎

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"Header": {
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"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
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"Info": "Performance Monitoring Metrics for 5th Generation Intel(R) Xeon(R) Processor Scalable Family0",
5-
"DatePublished": "06/17/2025",
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"Version": "1.1",
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"DatePublished": "09/12/2025",
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"Version": "1.2",
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"Legend": "",
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"TmaVersion": "5.1",
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"TmaFlavor": "Full"
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"ResolutionLevels": "CHA, SOCKET, SYSTEM",
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"MetricGroup": ""
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},
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{
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"MetricName": "cpu_cstate_c0",
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"LegacyName": "metric_CPU_cstate_C0",
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"Level": 1,
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"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU).",
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"UnitOfMeasure": "",
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"Events": [
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{
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"Name": "UNC_P_CLOCKTICKS",
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"Alias": "a"
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},
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{
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"Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
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"Alias": "b"
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}
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],
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"Constants": [
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{
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"Name": "SOCKET_COUNT",
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"Alias": "socket_count"
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}
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],
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"Formula": "(b / a[0]) * socket_count",
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"Category": "Power",
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"ResolutionLevels": "SOCKET, SYSTEM",
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"MetricGroup": "cpu_cstate"
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},
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{
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"MetricName": "cpu_cstate_c6",
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"LegacyName": "metric_CPU_cstate_C6",
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"Level": 1,
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"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU).",
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"UnitOfMeasure": "",
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"Events": [
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{
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"Name": "UNC_P_CLOCKTICKS",
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"Alias": "a"
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},
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{
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"Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
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"Alias": "b"
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}
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],
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"Constants": [
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{
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"Name": "SOCKET_COUNT",
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"Alias": "socket_count"
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}
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],
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"Formula": "(b / a[0]) * socket_count",
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"Category": "Power",
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"ResolutionLevels": "SOCKET, SYSTEM",
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"MetricGroup": "cpu_cstate"
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},
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{
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"MetricName": "Bottleneck_Mispredictions",
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"LegacyName": "metric_TMA_Bottleneck_Mispredictions",

‎EMR/metrics/perf/emeraldrapids_metrics_perf.json‎

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@@ -318,5 +318,17 @@
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"MetricGroup": "",
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"MetricName": "io_bandwidth_write_l3_miss",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU)",
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"MetricExpr": "( UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / pcu_0@UNC_P_CLOCKTICKS@ ) * #num_packages",
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"MetricGroup": "cpu_cstate",
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"MetricName": "cpu_cstate_c0"
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},
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{
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"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU)",
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"MetricExpr": "( UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / pcu_0@UNC_P_CLOCKTICKS@ ) * #num_packages",
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"MetricGroup": "cpu_cstate",
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"MetricName": "cpu_cstate_c6"
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}
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]

‎SPR/metrics/perf/sapphirerapids_metrics_perf.json‎

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"MetricGroup": "",
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"MetricName": "io_bandwidth_write_l3_miss",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU)",
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"MetricExpr": "( UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / pcu_0@UNC_P_CLOCKTICKS@ ) * #num_packages",
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"MetricGroup": "cpu_cstate",
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"MetricName": "cpu_cstate_c0"
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},
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{
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"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU)",
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"MetricExpr": "( UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / pcu_0@UNC_P_CLOCKTICKS@ ) * #num_packages",
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"MetricGroup": "cpu_cstate",
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"MetricName": "cpu_cstate_c6"
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}
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]

‎SPR/metrics/perf/sapphirerapidshbm_metrics_perf.json‎

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"MetricGroup": "",
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"MetricName": "io_bandwidth_write_l3_miss",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU)",
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"MetricExpr": "( UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / pcu_0@UNC_P_CLOCKTICKS@ ) * #num_packages",
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"MetricGroup": "cpu_cstate",
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"MetricName": "cpu_cstate_c0"
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},
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{
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"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU)",
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"MetricExpr": "( UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / pcu_0@UNC_P_CLOCKTICKS@ ) * #num_packages",
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"MetricGroup": "cpu_cstate",
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"MetricName": "cpu_cstate_c6"
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}
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]

‎SPR/metrics/sapphirerapids_metrics.json‎

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"Header": {
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"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
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"Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0",
5-
"DatePublished": "06/17/2025",
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"Version": "1.1",
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"DatePublished": "09/12/2025",
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"Version": "1.2",
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"Legend": "",
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"TmaVersion": "5.1",
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"TmaFlavor": "Full"
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"ResolutionLevels": "CHA, SOCKET, SYSTEM",
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"MetricGroup": ""
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},
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{
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"MetricName": "cpu_cstate_c0",
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"LegacyName": "metric_CPU_cstate_C0",
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"Level": 1,
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"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU).",
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"UnitOfMeasure": "",
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"Events": [
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{
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"Name": "UNC_P_CLOCKTICKS",
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"Alias": "a"
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},
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{
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"Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
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"Alias": "b"
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}
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],
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"Constants": [
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{
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"Name": "SOCKET_COUNT",
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"Alias": "socket_count"
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}
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],
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"Formula": "(b / a[0]) * socket_count",
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"Category": "Power",
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"ResolutionLevels": "SOCKET, SYSTEM",
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"MetricGroup": "cpu_cstate"
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},
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{
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"MetricName": "cpu_cstate_c6",
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"LegacyName": "metric_CPU_cstate_C6",
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"Level": 1,
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"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU).",
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"UnitOfMeasure": "",
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"Events": [
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{
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"Name": "UNC_P_CLOCKTICKS",
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"Alias": "a"
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},
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{
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"Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
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"Alias": "b"
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}
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],
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"Constants": [
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{
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"Name": "SOCKET_COUNT",
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"Alias": "socket_count"
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}
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],
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"Formula": "(b / a[0]) * socket_count",
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"Category": "Power",
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"ResolutionLevels": "SOCKET, SYSTEM",
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"MetricGroup": "cpu_cstate"
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},
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{
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"MetricName": "Bottleneck_Mispredictions",
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"LegacyName": "metric_TMA_Bottleneck_Mispredictions",

‎SPR/metrics/sapphirerapidshbm_metrics.json‎

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"Header": {
33
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
44
"Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0",
5-
"DatePublished": "06/17/2025",
6-
"Version": "1.1",
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"DatePublished": "09/12/2025",
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"Version": "1.2",
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"Legend": "",
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"TmaVersion": "5.1",
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"TmaFlavor": "Full"
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"ResolutionLevels": "CHA, SOCKET, SYSTEM",
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"MetricGroup": ""
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},
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{
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"MetricName": "cpu_cstate_c0",
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"LegacyName": "metric_CPU_cstate_C0",
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"Level": 1,
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"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU).",
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"UnitOfMeasure": "",
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"Events": [
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{
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"Name": "UNC_P_CLOCKTICKS",
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"Alias": "a"
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},
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{
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"Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
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"Alias": "b"
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}
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],
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"Constants": [
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{
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"Name": "SOCKET_COUNT",
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"Alias": "socket_count"
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}
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],
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"Formula": "(b / a[0]) * socket_count",
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"Category": "Power",
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"ResolutionLevels": "SOCKET, SYSTEM",
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"MetricGroup": "cpu_cstate"
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},
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{
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"MetricName": "cpu_cstate_c6",
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"LegacyName": "metric_CPU_cstate_C6",
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"Level": 1,
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"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU).",
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"UnitOfMeasure": "",
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"Events": [
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{
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"Name": "UNC_P_CLOCKTICKS",
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"Alias": "a"
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},
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{
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"Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
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"Alias": "b"
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}
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],
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"Constants": [
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{
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"Name": "SOCKET_COUNT",
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"Alias": "socket_count"
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}
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],
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"Formula": "(b / a[0]) * socket_count",
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"Category": "Power",
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"ResolutionLevels": "SOCKET, SYSTEM",
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"MetricGroup": "cpu_cstate"
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},
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{
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"MetricName": "Bottleneck_Mispredictions",
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"LegacyName": "metric_TMA_Bottleneck_Mispredictions",

‎mapfile.csv‎

Lines changed: 2 additions & 2 deletions
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@@ -142,11 +142,11 @@ GenuineIntel-6-8D,V1.1,/TGL/metrics/tigerlake_metrics.json,metrics,,,
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GenuineIntel-6-8F,V1.34,/SPR/events/sapphirerapids_core.json,core,,,
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GenuineIntel-6-8F,V1.34,/SPR/events/sapphirerapids_uncore.json,uncore,,,
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GenuineIntel-6-8F,V1.34,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,,
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GenuineIntel-6-8F,V1.1,/SPR/metrics/sapphirerapids_metrics.json,metrics,,,
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GenuineIntel-6-8F,V1.2,/SPR/metrics/sapphirerapids_metrics.json,metrics,,,
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GenuineIntel-6-CF,V1.19,/EMR/events/emeraldrapids_core.json,core,,,
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GenuineIntel-6-CF,V1.19,/EMR/events/emeraldrapids_uncore.json,uncore,,,
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GenuineIntel-6-CF,V1.19,/EMR/events/emeraldrapids_uncore_experimental.json,uncore experimental,,,
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GenuineIntel-6-CF,V1.1,/EMR/metrics/emeraldrapids_metrics.json,metrics,,,
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GenuineIntel-6-CF,V1.2,/EMR/metrics/emeraldrapids_metrics.json,metrics,,,
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GenuineIntel-6-6A,V1.28,/ICX/events/icelakex_core.json,core,,,
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GenuineIntel-6-6A,V1.28,/ICX/events/icelakex_uncore.json,uncore,,,
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GenuineIntel-6-6A,V1.28,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,

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