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[SYCL][Doc] Host pipe design #5850

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Merged
merged 20 commits into from
Jan 16, 2023
Merged

[SYCL][Doc] Host pipe design #5850

merged 20 commits into from
Jan 16, 2023

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rho180
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@rho180 rho180 commented Mar 21, 2022

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@rho180 rho180 requested a review from a team as a code owner March 21, 2022 17:53
@rho180 rho180 changed the title [Doc] Host pipe design [Sycl][Doc] Host pipe design Mar 21, 2022
@rho180 rho180 changed the title [Sycl][Doc] Host pipe design [SYCL][Doc] Host pipe design Mar 21, 2022
Add constexpr definition for __pipe in pipe class
rho180 and others added 3 commits August 18, 2022 10:41
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rho180 commented Aug 18, 2022

@steffenlarsen @gmlueck Reviving this review as this work which was previously put on hold is now needed.

Co-authored-by: Steffen Larsen <steffen.larsen@intel.com>
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LGTM!

@rho180 rho180 requested review from bader and removed request for gmlueck December 7, 2022 19:32
@bader bader closed this Jan 10, 2023
@bader bader reopened this Jan 10, 2023
@bader bader requested a review from a team as a code owner January 10, 2023 01:08
@bader bader merged commit a982a12 into intel:sycl Jan 16, 2023
bader pushed a commit that referenced this pull request Feb 7, 2023
…8009)

Implementation of host pipes outlined in the design document in this PR:

#5850

1. Generation a unique pipe id for GVs marked with the new
"sycl-host-pipe" attribute. Id generation utilizes the same method as
used for name generation for device global.
2. Added a host pipe map to map the addresses of marked GVs with the
unique id. This host pipe map is generated by a constructor and method
calls added to the header and footer.
3. Modified the sycl-post-link tool to generate compile time properties
metadata for these GVs. This metadata contains the unique id generated
for the GV to be consumed by the device backend compiler.

PR for accompanying runtime changes:
#7468

---------

Co-authored-by: Alexey Sachkov <alexey.sachkov@intel.com>
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5 participants