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[SYCL][CUDA][libclc] Add support for generic AS in atomics #5849

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e8a0f51
add support for generic AS in atomics
t4c1 Mar 18, 2022
a37353a
fix a bug in libclc remangler
t4c1 Mar 21, 2022
0c113e0
format
t4c1 Mar 21, 2022
87afa59
Merge branch 'sycl' into ptx_generic_atomics
t4c1 Mar 22, 2022
2ea06d0
Merge branch 'sycl' into ptx_generic_atomics
t4c1 May 9, 2022
ae9663f
format
t4c1 May 9, 2022
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39 changes: 21 additions & 18 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_cmpxchg.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -70,10 +70,10 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
}

#define __CLC_NVVM_ATOMIC_CAS_IMPL( \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, OP_MANGLED, ADDR_SPACE, \
ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
_CLC_DECL TYPE \
_Z29__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_MANGLED##TYPE_MANGLED( \
FN_MANGLED, TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, ADDR_SPACE, \
ADDR_SPACE_NV) \
__attribute__((always_inline)) _CLC_DECL TYPE \
FN_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics1, \
enum MemorySemanticsMask semantics2, TYPE cmp, TYPE value) { \
Expand Down Expand Up @@ -118,21 +118,24 @@ Memory order is stored in the lowest 5 bits */
__builtin_unreachable(); \
}

#define __CLC_NVVM_ATOMIC_CAS(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, OP_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
OP_MANGLED, __global, AS1, _global_) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, OP_MANGLED, __local, AS3, _shared_)
#define __CLC_NVVM_ATOMIC_CAS(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP) \
__CLC_NVVM_ATOMIC_CAS_IMPL( \
_Z29__spirv_AtomicCompareExchange##P##TYPE_MANGLED##N5__spv5Scope4FlagENS0_19MemorySemanticsMask4FlagES4_##TYPE_MANGLED##TYPE_MANGLED, \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, , _gen_) \
__CLC_NVVM_ATOMIC_CAS_IMPL( \
_Z29__spirv_AtomicCompareExchange##PU3AS1##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_MANGLED##TYPE_MANGLED, \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, __global, _global_) \
__CLC_NVVM_ATOMIC_CAS_IMPL( \
_Z29__spirv_AtomicCompareExchange##PU3AS3##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_MANGLED##TYPE_MANGLED, \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, __local, _shared_)

__CLC_NVVM_ATOMIC_CAS(int, i, int, i, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(long, l, long, l, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(unsigned int, j, int, i, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(unsigned long, m, long, l, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(float, f, float, f, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(double, d, double, d, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(int, i, int, i, cas)
__CLC_NVVM_ATOMIC_CAS(long, l, long, l, cas)
__CLC_NVVM_ATOMIC_CAS(unsigned int, j, int, i, cas)
__CLC_NVVM_ATOMIC_CAS(unsigned long, m, long, l, cas)
__CLC_NVVM_ATOMIC_CAS(float, f, float, f, cas)
__CLC_NVVM_ATOMIC_CAS(double, d, double, d, cas)

#undef __CLC_NVVM_ATOMIC_CAS_IMPL_ORDER
#undef __CLC_NVVM_ATOMIC_CAS
Expand Down
111 changes: 56 additions & 55 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_helpers.h
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Original file line number Diff line number Diff line change
Expand Up @@ -72,62 +72,63 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
} \
}

#define __CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, NAME_MANGLED, ADDR_SPACE, \
ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
_CLC_DECL TYPE \
NAME_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE value) { \
/* Semantics mask may include memory order, storage class and other info \
Memory order is stored in the lowest 5 bits */ \
unsigned int order = semantics & 0x1F; \
switch (order) { \
case None: \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
break; \
case Acquire: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
} else { \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case Release: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _release) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
} \
break; \
case AcquireRelease: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
} \
__builtin_trap(); \
__builtin_unreachable(); \
#define __CLC_NVVM_ATOMIC_IMPL(FN_MANGLED, TYPE, TYPE_MANGLED, TYPE_NV, \
TYPE_MANGLED_NV, OP, ADDR_SPACE, ADDR_SPACE_NV) \
__attribute__((always_inline)) _CLC_DECL TYPE FN_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE value) { \
/* Semantics mask may include memory order, storage class and other info \
Memory order is stored in the lowest 5 bits */ \
unsigned int order = semantics & 0x1F; \
switch (order) { \
case None: \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
break; \
case Acquire: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
} else { \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case Release: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _release) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
} \
break; \
case AcquireRelease: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
} \
__builtin_trap(); \
__builtin_unreachable(); \
}

#define __CLC_NVVM_ATOMIC(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __global, AS1, _global_) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __local, AS3, _shared_)
#define __CLC_NVVM_ATOMIC(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED) \
__CLC_NVVM_ATOMIC_IMPL( \
NAME_MANGLED##P##TYPE_MANGLED##N5__spv5Scope4FlagENS0_19MemorySemanticsMask4FlagE##TYPE_MANGLED, \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, , _gen_) \
__CLC_NVVM_ATOMIC_IMPL( \
NAME_MANGLED##PU3AS1##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED, \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, __global, _global_) \
__CLC_NVVM_ATOMIC_IMPL( \
NAME_MANGLED##PU3AS3##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED, \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, __local, _shared_)

#endif
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