[SYCL] Fix typo in the name of the host-visible pool #5073
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Signed-off-by: Sergey V Maslov <sergey.v.maslov@intel.com>
Signed-off-by: Sergey V Maslov <sergey.v.maslov@intel.com>
againull
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Dec 3, 2021
| @@ -4761,7 +4761,7 @@ pi_result piEventCreate(pi_context Context, pi_event *RetEvent) { | |||
| if (ZeAllHostVisibleEvents) { | |||
| ZeEventDesc.signal = ZE_EVENT_SCOPE_FLAG_HOST; | |||
| } else { | |||
| ZeEventDesc.signal = ZE_EVENT_SCOPE_FLAG_DEVICE; | |||
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I don't completely understand this change. So do you basically want to change this to ZE_EVENT_SCOPE_FLAG_SUBDEVICE?
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No, the current recommendation from L0 GPU RT is that "0" scope should be used. The ZE_EVENT_SCOPE_FLAG_SUBDEVICE is "1".
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Hm, but per specification it looks like ZE_EVENT_SCOPE_FLAG_SUBDEVICE is "0" and ZE_EVENT_SCOPE_FLAG_DEVICE is "1".
https://spec.oneapi.io/level-zero/latest/core/api.html?highlight=ze_event_scope_flag_device#_CPPv426ZE_EVENT_SCOPE_FLAG_DEVICE
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ZE_BIT(0) = 1 << 0 = 1
againull
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Dec 3, 2021
alexbatashev
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Dec 11, 2021
* upstream/sycl: (725 commits) [SYCL] Translate ZE_RESULT_ERROR_INVALID_ARGUMENT error code from L0 RT (intel#5122) [SYCL][L0][Plugin] Call ZeCommandQueueCreate on demand (intel#5109) [SYCL] Switch to using blocking USM free for OpenCL GPU (intel#4928) [CI] Disable pack and upload steps (intel#5119) [SYCL] Disable submission of AssertInfoCopier for FPGA (intel#4780) [SYCL][SPIRV] Implement islessgreater with FOrdNotEqual instead (intel#5076) [SYCL] Fix typo in the name of the host-visible pool (intel#5073) [SYCL] Only call shutdown when DLL is being unloaded, not when process is terminating (intel#4983) [SYCL][CUDA][PI] Fix infinite loop when parallel_for range exceeds INT_MAX (intel#5095) [SYCL] Translate out-of-memory error codes from L0 RT (intel#5107) [SYCL] Fix a few warnings during build scripts configuration (intel#5082) [SYCL] Fix amdgpu openmp test (intel#5103) [SYCL] [FPGA] Create experimental headers for FPGA latency control (intel#5066) [SYCL][CUDA] Don't enqueue an event wait on same CUDA stream (intel#5099) Remove PR disable template (intel#5102) [BuildBot]Uplift CPU/FPGAEMU RT version (intel#5078) [SYCL] Fix the test to not depend on a specific line. (intel#5092) [CI] Provide libclc targets to build and test (intel#5091) Fix build of `check-llvm-spirv` target after 8f8001a Force opt to use new pass manager in pr52289 test after c34d157 ...
alexbatashev
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Dec 12, 2021
* upstream/sycl: [CI] Add container users to video group (intel#5101) [CI] More typo fixes in Nightly build (intel#5088) Revert "[CI] Disable pack and upload steps (intel#5119)" (intel#5125) [SYCL] Translate ZE_RESULT_ERROR_INVALID_ARGUMENT error code from L0 RT (intel#5122) [SYCL][L0][Plugin] Call ZeCommandQueueCreate on demand (intel#5109) [SYCL] Switch to using blocking USM free for OpenCL GPU (intel#4928) [CI] Disable pack and upload steps (intel#5119) [SYCL] Disable submission of AssertInfoCopier for FPGA (intel#4780) [SYCL][SPIRV] Implement islessgreater with FOrdNotEqual instead (intel#5076) [SYCL] Fix typo in the name of the host-visible pool (intel#5073) [SYCL] Only call shutdown when DLL is being unloaded, not when process is terminating (intel#4983) [SYCL][CUDA][PI] Fix infinite loop when parallel_for range exceeds INT_MAX (intel#5095) [SYCL] Translate out-of-memory error codes from L0 RT (intel#5107) [SYCL] Fix a few warnings during build scripts configuration (intel#5082) [SYCL] Fix amdgpu openmp test (intel#5103) [SYCL] [FPGA] Create experimental headers for FPGA latency control (intel#5066) [SYCL][CUDA] Don't enqueue an event wait on same CUDA stream (intel#5099) Remove PR disable template (intel#5102) [BuildBot]Uplift CPU/FPGAEMU RT version (intel#5078)
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Signed-off-by: Sergey V Maslov sergey.v.maslov@intel.com