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[SYCL] [FPGA] Add experimental latency control feature to FPGA extension docs #5027

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merged 1 commit into from
Dec 3, 2021

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Introducing experimental latency control API for pipe and LSU.

One other minor change in FPGALsu.md: removing the cl:: namespace according to the SYCL 2020 spec.

@shuoniu-intel shuoniu-intel requested a review from a team as a code owner November 24, 2021 21:18
@shuoniu-intel shuoniu-intel requested a review from gmlueck December 2, 2021 17:23
@shuoniu-intel shuoniu-intel force-pushed the br-latency_control-experimental branch from 81849ae to 5d3dbed Compare December 2, 2021 20:56
gmlueck
gmlueck previously approved these changes Dec 2, 2021
@bader bader merged commit 5ab3cd3 into intel:sycl Dec 3, 2021
@shuoniu-intel shuoniu-intel deleted the br-latency_control-experimental branch December 3, 2021 14:01
romanovvlad pushed a commit that referenced this pull request Dec 8, 2021
…5066)

Create experimental header files that provide user API for
FPGA latency control feature.

experimental/fpga_lsu.hpp and experimental/pipes.hpp are
simply the original version plus latency control API
described in the extension documents.

experimental/fpga_utils.hpp provides utility functions used
by experimental LSU and pipe headers.
fpga_extensions.hpp will include new experimental LSU and
pipe headers.

Related PR for extension documents: #5027

Test: intel/llvm-test-suite#596
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