[SYCL] Enable native FP atomics by default #3869
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Since Intel GPU and CPU support the target, pass the required macro by default during device FE compilation for SPIR non-FPGA targets. This alleviates the users of the native FP atomic functionality from passing the macro explicitly. Signed-off-by: Artem Gindinson <artem.gindinson@intel.com>
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Pennycook
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Jun 9, 2021
Pennycook
previously approved these changes
Jun 9, 2021
dm-vodopyanov
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Jun 10, 2021
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@dm-vodopyanov Done; an uplift of CPU RT version had been the only thing required. @mdtoguchi, could you please review now that CI is fine? |
mdtoguchi
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Jun 21, 2021
Signed-off-by: Artem Gindinson <artem.gindinson@intel.com>
AGindinson
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AaronBallman,
elizabethandrews and
premanandrao
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I have no idea if the Jenkins failures are related to this patch or not. There's basically no useful information in this failure that I can find: |
Thanks for highlighting - these probably shouldn't be related, but I'll make sure to check by restarting the CI via a stylistic fix. |
Signed-off-by: Artem Gindinson <artem.gindinson@intel.com>
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/summary:run |
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@bader, could you please merge the PR once convenient? Thanks! |
AGindinson
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Jun 23, 2021
Also includes a relevant stylistic fix suggested in intel#3869 (comment). Signed-off-by: Artem Gindinson <artem.gindinson@intel.com>
alexbatashev
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* upstream/sycl: (489 commits) [SYCL][NFC] Lower overhead of making plugin calls (intel#3982) [SYCL][NFC] Use default macro initialization where applicable (intel#3979) [SYCL] Enable SPV_INTEL_fpga_invocation_pipelining_attributes extension (intel#3864) [SYCL] Disable reassociate pass to reduce register pressure (intel#3615) [Driver][SYCL][FPGA] Restrict -O0 for FPGA with hardware (intel#3966) [SYCL][NFC] Fix warnings coming out of SYCL headers. (intel#3978) [SYCL] Fix bugs with recursion in SYCL kernel (intel#3958) [SYCL][LevelZero] Add support to detect host->device and device->host transfers for USM (intel#3975) [SYCL] Enable native FP atomics by default (intel#3869) [sycl-post-link] Avoid copying from nullptr (intel#3963) [SYCL-PTX] Add warp-reduce path in sub-group reduce (intel#3949) [BuildBot] Uplift CPU/FPGAEMU RT version for CI Process (intel#3946) Fix handling of complex constant expressions Handle OpSpecConstantOp with CompositeExtract and CompositeInsert Handle OpSpecConstantOp with VectorShuffle [FuncSpec] Don't specialise functions with NoDuplicate instructions. [mlir][linalg] Support low padding in subtensor(pad_tensor) lowering [gn build] Port 208332d [AMDGPU] Add Optimize VGPR LiveRange Pass. [mlir][Linalg] NFC - Drop unused variable definition. ...
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Since Intel GPU and CPU support the target, pass the required
macro by default during device FE compilation for SPIR non-FPGA
targets. This alleviates the users of the native FP atomic
functionality from passing the macro explicitly.
Tested in intel/llvm-test-suite#308.