[SYCL] Follow-up fixes for stream class #254
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* Enable constant propagation for stream manipulators * Enable LIT test on all devices except CPU * Remove unused builtins.hpp include Signed-off-by: Artur Gainullin <artur.gainullin@intel.com>
bader
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Jun 26, 2019
vladimirlaz
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iclsrc
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Apr 6, 2024
…ndling (#76644)
Fold BICi if all destination bits are already known to be zeroes
```llvm
define <8 x i16> @haddu_known(<8 x i8> %a0, <8 x i8> %a1) {
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
ret <8 x i16> %res
}
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
```
```
haddu_known: // @haddu_known
ushll v0.8h, v0.8b, #0
ushll v1.8h, v1.8b, #0
uhadd v0.8h, v0.8h, v1.8h
bic v0.8h, #254, lsl #8 <-- this one will be removed as we know high bits are zero extended
ret
```
Fixes #53881
Fixes #53622
coldav
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[vecz] Provide more context when CFG conversion fails
coldav
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Aug 26, 2025
[vecz] Provide more context when CFG conversion fails
coldav
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Aug 29, 2025
[vecz] Provide more context when CFG conversion fails
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Signed-off-by: Artur Gainullin artur.gainullin@intel.com