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@Naghasan Naghasan commented Jun 9, 2020

The NVPTX backend supports half and handle the insertion of conversion operations when required.

Resolves #1799

Signed-off-by: Victor Lomuller victor@codeplay.com

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@premanandrao premanandrao left a comment

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Please fix the code format errors.

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@Fznamznon Fznamznon left a comment

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Could you please also revert a4f4fa9 ?

@Naghasan Naghasan force-pushed the cuda_native_float_16 branch 2 times, most recently from 96b3e79 to b1ffe4a Compare June 10, 2020 16:48
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Fznamznon previously approved these changes Jun 10, 2020
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LGTM, thanks!

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bader commented Jun 11, 2020

@Naghasan, could you apply clang-format to the patch, please?

Naghasan added 2 commits June 11, 2020 09:48
The NVPTX backend supports half and handle the insertion of conversion operations when required.

Signed-off-by: Victor Lomuller <victor@codeplay.com>
This reverts commit a4f4fa9.

Signed-off-by: Victor Lomuller <victor@codeplay.com>
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I think we should submit this patch to the community.
@Naghasan, could you do that, please?

@bader bader added the cuda CUDA back-end label Jun 11, 2020
@bader bader merged commit bc5be46 into intel:sycl Jun 11, 2020
KornevNikita pushed a commit to KornevNikita/llvm that referenced this pull request Feb 20, 2023
This specifies the right operand types for GetKernelWorkGroupSize,
GetKernelPreferredWorkGroupSizeMultiple,
GetKernelNDrangeMaxSubGroupSize,
and GetKernelNDrangeSubGroupCount to fix a function signature mismatch
bug on reverse translation.

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@f0366a6
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FP16 types are reported as unsupported for CUDA BE on compile time after cf6cc662
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