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[Bitcode] Remove auto-detection for typed pointers
Always read bitcode according to the -opaque-pointers mode. Do not perform auto-detection to implicitly switch to typed pointers. This is a step towards removing typed pointer support, and also eliminates the class of problems where linking may fail if a typed pointer module is loaded before an opaque pointer module. (The latest place where this was encountered is D139924, but this has previously been fixed in other places doing bitcode linking as well.) Differential Revision: https://reviews.llvm.org/D139940
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‎llvm/docs/OpaquePointers.rst

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -287,10 +287,12 @@ The following typed pointer functionality has already been removed:
287287
* The ``CLANG_ENABLE_OPAQUE_POINTERS`` cmake flag is no longer supported.
288288
* C APIs that do not support opaque pointers (like ``LLVMBuildLoad``) are no
289289
longer supported.
290+
* Typed pointer bitcode is implicitly upgraded to use opaque pointers, unless
291+
``-opaque-pointers=0`` is passed.
290292

291293
The following typed pointer functionality is still to be removed:
292294

293295
* The ``-no-opaque-pointers`` cc1 flag, ``-opaque-pointers=0`` opt flag and
294296
``-plugin-opt=no-opaque-pointers`` lto flag.
295-
* Auto-detection of typed pointers in bitcode and textual IR.
297+
* Auto-detection of typed pointers in textual IR.
296298
* Support for typed pointers in LLVM libraries.

‎llvm/lib/Bitcode/Reader/BitcodeReader.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2359,18 +2359,14 @@ Error BitcodeReader::parseTypeTableBody() {
23592359
if (!ResultTy ||
23602360
!PointerType::isValidElementType(ResultTy))
23612361
return error("Invalid type");
2362-
if (LLVM_UNLIKELY(!Context.hasSetOpaquePointersValue()))
2363-
Context.setOpaquePointers(false);
23642362
ContainedIDs.push_back(Record[0]);
23652363
ResultTy = PointerType::get(ResultTy, AddressSpace);
23662364
break;
23672365
}
23682366
case bitc::TYPE_CODE_OPAQUE_POINTER: { // OPAQUE_POINTER: [addrspace]
23692367
if (Record.size() != 1)
23702368
return error("Invalid opaque pointer record");
2371-
if (LLVM_UNLIKELY(!Context.hasSetOpaquePointersValue())) {
2372-
Context.setOpaquePointers(true);
2373-
} else if (Context.supportsTypedPointers())
2369+
if (Context.supportsTypedPointers())
23742370
return error(
23752371
"Opaque pointers are only supported in -opaque-pointers mode");
23762372
unsigned AddressSpace = Record[0];

‎llvm/test/Bitcode/Inputs/invalid-call-mismatched-explicit-type.bc

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‎llvm/test/Bitcode/Inputs/invalid-gep-mismatched-explicit-type.bc

-448 Bytes
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‎llvm/test/Bitcode/Inputs/invalid-gep-operator-mismatched-explicit-type.bc

-492 Bytes
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‎llvm/test/Bitcode/Inputs/invalid-load-mismatched-explicit-type.bc

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‎llvm/test/Bitcode/alloca-addrspace.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,14 @@
22

33
target datalayout = "A2"
44

5-
; CHECK-LABEL: define i8 addrspace(2)* @alloca_addrspace_2() {
5+
; CHECK-LABEL: define ptr addrspace(2) @alloca_addrspace_2() {
66
; CHECK: %alloca = alloca i8, align 1, addrspace(2)
77
define i8 addrspace(2)* @alloca_addrspace_2() {
88
%alloca = alloca i8, addrspace(2)
99
ret i8 addrspace(2)* %alloca
1010
}
1111

12-
; CHECK-LABEL: define i8 addrspace(5)* @alloca_addrspace_5() {
12+
; CHECK-LABEL: define ptr addrspace(5) @alloca_addrspace_5() {
1313
; CHECK: %alloca = alloca i8, align 1, addrspace(5)
1414
define i8 addrspace(5)* @alloca_addrspace_5() {
1515
%alloca = alloca i8, addrspace(5)

‎llvm/test/Bitcode/arm-intrinsics.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
11
; RUN: llvm-dis < %S/arm-intrinsics.bc | FileCheck %s
22

33
define void @f(i32* %p) {
4-
; CHECK: call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32)
4+
; CHECK: call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32)
55
%a = call i32 @llvm.arm.ldrex.p0i32(i32* %p)
6-
; CHECK: call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32)
6+
; CHECK: call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32)
77
%c = call i32 @llvm.arm.strex.p0i32(i32 0, i32* %p)
88

9-
; CHECK: call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32)
9+
; CHECK: call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32)
1010
%a2 = call i32 @llvm.arm.ldaex.p0i32(i32* %p)
11-
; CHECK: call i32 @llvm.arm.stlex.p0i32(i32 0, i32* elementtype(i32)
11+
; CHECK: call i32 @llvm.arm.stlex.p0(i32 0, ptr elementtype(i32)
1212
%c2 = call i32 @llvm.arm.stlex.p0i32(i32 0, i32* %p)
1313
ret void
1414
}

‎llvm/test/Bitcode/atomic-no-syncscope.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3,15 +3,15 @@
33
; Backwards compatibility test: make sure we can process bitcode without
44
; synchronization scope names encoded in it.
55

6-
; CHECK: load atomic i32, i32* %x unordered, align 4
7-
; CHECK: load atomic volatile i32, i32* %x syncscope("singlethread") acquire, align 4
8-
; CHECK: store atomic i32 3, i32* %x release, align 4
9-
; CHECK: store atomic volatile i32 3, i32* %x syncscope("singlethread") monotonic, align 4
10-
; CHECK: cmpxchg i32* %x, i32 1, i32 0 syncscope("singlethread") monotonic monotonic
11-
; CHECK: cmpxchg volatile i32* %x, i32 0, i32 1 acq_rel acquire
12-
; CHECK: cmpxchg i32* %x, i32 42, i32 0 acq_rel monotonic
13-
; CHECK: cmpxchg weak i32* %x, i32 13, i32 0 seq_cst monotonic
14-
; CHECK: atomicrmw add i32* %x, i32 10 seq_cst
15-
; CHECK: atomicrmw volatile xchg i32* %x, i32 10 monotonic
6+
; CHECK: load atomic i32, ptr %x unordered, align 4
7+
; CHECK: load atomic volatile i32, ptr %x syncscope("singlethread") acquire, align 4
8+
; CHECK: store atomic i32 3, ptr %x release, align 4
9+
; CHECK: store atomic volatile i32 3, ptr %x syncscope("singlethread") monotonic, align 4
10+
; CHECK: cmpxchg ptr %x, i32 1, i32 0 syncscope("singlethread") monotonic monotonic
11+
; CHECK: cmpxchg volatile ptr %x, i32 0, i32 1 acq_rel acquire
12+
; CHECK: cmpxchg ptr %x, i32 42, i32 0 acq_rel monotonic
13+
; CHECK: cmpxchg weak ptr %x, i32 13, i32 0 seq_cst monotonic
14+
; CHECK: atomicrmw add ptr %x, i32 10 seq_cst
15+
; CHECK: atomicrmw volatile xchg ptr %x, i32 10 monotonic
1616
; CHECK: fence syncscope("singlethread") release
1717
; CHECK: fence seq_cst

‎llvm/test/Bitcode/atomic.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,16 @@
33

44
define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
55
cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
6-
; CHECK: cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
6+
; CHECK: cmpxchg ptr %addr, i32 %desired, i32 %new seq_cst seq_cst
77

88
cmpxchg volatile i32* %addr, i32 %desired, i32 %new seq_cst monotonic
9-
; CHECK: cmpxchg volatile i32* %addr, i32 %desired, i32 %new seq_cst monotonic
9+
; CHECK: cmpxchg volatile ptr %addr, i32 %desired, i32 %new seq_cst monotonic
1010

1111
cmpxchg weak i32* %addr, i32 %desired, i32 %new acq_rel acquire
12-
; CHECK: cmpxchg weak i32* %addr, i32 %desired, i32 %new acq_rel acquire
12+
; CHECK: cmpxchg weak ptr %addr, i32 %desired, i32 %new acq_rel acquire
1313

1414
cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new syncscope("singlethread") release monotonic
15-
; CHECK: cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new syncscope("singlethread") release monotonic
15+
; CHECK: cmpxchg weak volatile ptr %addr, i32 %desired, i32 %new syncscope("singlethread") release monotonic
1616

1717
ret void
1818
}

‎llvm/test/Bitcode/atomicrmw-upgrade.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
; before the IR change on this file.
66

77
; CHECK: @atomicrmw
8-
; CHECK: %b = atomicrmw add i32* %a, i32 %i acquire
8+
; CHECK: %b = atomicrmw add ptr %a, i32 %i acquire
99
define void @atomicrmw(i32* %a, i32 %i) {
1010
%b = atomicrmw add i32* %a, i32 %i acquire
1111
ret void

‎llvm/test/Bitcode/attributes-3.3.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ define void @f4(i8 inreg %0)
3030
}
3131

3232
define void @f5(i8* sret(i8) %0)
33-
; CHECK: define void @f5(i8* sret(i8) %0)
33+
; CHECK: define void @f5(ptr sret(i8) %0)
3434
{
3535
ret void;
3636
}
@@ -42,19 +42,19 @@ define void @f6() nounwind
4242
}
4343

4444
define void @f7(i8* noalias %0)
45-
; CHECK: define void @f7(i8* noalias %0)
45+
; CHECK: define void @f7(ptr noalias %0)
4646
{
4747
ret void;
4848
}
4949

5050
define void @f8(i8* byval(i8) %0)
51-
; CHECK: define void @f8(i8* byval(i8) %0)
51+
; CHECK: define void @f8(ptr byval(i8) %0)
5252
{
5353
ret void;
5454
}
5555

5656
define void @f9(i8* nest %0)
57-
; CHECK: define void @f9(i8* nest %0)
57+
; CHECK: define void @f9(ptr nest %0)
5858
{
5959
ret void;
6060
}
@@ -108,7 +108,7 @@ define void @f17(i8 align 4 %0)
108108
}
109109

110110
define void @f18(i8* nocapture %0)
111-
; CHECK: define void @f18(i8* nocapture %0)
111+
; CHECK: define void @f18(ptr nocapture %0)
112112
{
113113
ret void;
114114
}

‎llvm/test/Bitcode/byval-upgrade.test

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,5 +3,5 @@ RUN: llvm-dis %p/Inputs/byval-upgrade.bc -o - | FileCheck %s
33
Make sure we upgrade old-stile IntAttribute byval records to a fully typed
44
version correctly.
55

6-
CHECK: call void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr)
7-
CHECK: invoke void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr)
6+
CHECK: call void @bar(ptr byval({ ptr, i8 }) %ptr)
7+
CHECK: invoke void @bar(ptr byval({ ptr, i8 }) %ptr)

‎llvm/test/Bitcode/callbr.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
1-
; RUN: llvm-dis < %s.bc | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED
1+
; RUN: llvm-dis < %s.bc | FileCheck %s
22
; callbr.ll.bc was generated by passing this file to llvm-as.
33

4-
; RUN: llvm-as < %s | llvm-dis | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED
5-
; RUN: llvm-as -opaque-pointers < %s | llvm-dis -opaque-pointers | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE
4+
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
65

76
define i32 @test_asm_goto(i32 %x){
87
entry:
@@ -30,8 +29,7 @@ fail2:
3029

3130
define i32 @test_asm_goto3(i32 %x){
3231
entry:
33-
; CHECK-TYPED: callbr void asm "", "r,i,!i"(i32 %x, i8* blockaddress(@test_asm_goto3, %unrelated))
34-
; CHECK-OPAQUE: callbr void asm "", "r,i,!i"(i32 %x, ptr blockaddress(@test_asm_goto3, %unrelated))
32+
; CHECK: callbr void asm "", "r,i,!i"(i32 %x, ptr blockaddress(@test_asm_goto3, %unrelated))
3533
; CHECK-NEXT: to label %normal [label %fail]
3634
callbr void asm "", "r,i,!i"(i32 %x, i8* blockaddress(@test_asm_goto3, %unrelated)) to label %normal [label %fail]
3735
normal:

‎llvm/test/Bitcode/cmpxchg-upgrade.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,19 +6,19 @@
66

77
define void @test(i32* %addr) {
88
cmpxchg i32* %addr, i32 42, i32 0 monotonic
9-
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 monotonic monotonic
9+
; CHECK: cmpxchg ptr %addr, i32 42, i32 0 monotonic monotonic
1010

1111
cmpxchg i32* %addr, i32 42, i32 0 acquire
12-
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 acquire acquire
12+
; CHECK: cmpxchg ptr %addr, i32 42, i32 0 acquire acquire
1313

1414
cmpxchg i32* %addr, i32 42, i32 0 release
15-
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 release monotonic
15+
; CHECK: cmpxchg ptr %addr, i32 42, i32 0 release monotonic
1616

1717
cmpxchg i32* %addr, i32 42, i32 0 acq_rel
18-
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 acq_rel acquire
18+
; CHECK: cmpxchg ptr %addr, i32 42, i32 0 acq_rel acquire
1919

2020
cmpxchg i32* %addr, i32 42, i32 0 seq_cst
21-
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 seq_cst seq_cst
21+
; CHECK: cmpxchg ptr %addr, i32 42, i32 0 seq_cst seq_cst
2222

2323
ret void
2424
}

‎llvm/test/Bitcode/cmpxchg.3.6.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ entry:
55
br label %a
66
b:
77
cmpxchg i32* %x, i32 %y, i32 %z acquire acquire
8-
; CHECK: cmpxchg i32* %x, i32 %y, i32 %z acquire acquire
8+
; CHECK: cmpxchg ptr %x, i32 %y, i32 %z acquire acquire
99
ret void
1010
a:
1111
%y = add i32 %y.orig, 1

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