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[SYCL] [FPGA] Create experimental headers for FPGA latency control (#5066)
Create experimental header files that provide user API for FPGA latency control feature. experimental/fpga_lsu.hpp and experimental/pipes.hpp are simply the original version plus latency control API described in the extension documents. experimental/fpga_utils.hpp provides utility functions used by experimental LSU and pipe headers. fpga_extensions.hpp will include new experimental LSU and pipe headers. Related PR for extension documents: #5027 Test: intel/llvm-test-suite#596
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‎sycl/include/sycl/ext/intel/experimental/fpga_lsu.hpp

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//==-------------- fpga_lsu.hpp --- SYCL FPGA LSU Extensions ---------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#pragma once
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#include "fpga_utils.hpp"
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#include <CL/sycl/detail/defines.hpp>
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#include <CL/sycl/pointers.hpp>
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__SYCL_INLINE_NAMESPACE(cl) {
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namespace sycl {
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namespace ext {
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namespace intel {
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namespace experimental {
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constexpr uint8_t BURST_COALESCE = 0x1;
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constexpr uint8_t CACHE = 0x2;
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constexpr uint8_t STATICALLY_COALESCE = 0x4;
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constexpr uint8_t PREFETCH = 0x8;
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template <int32_t _N> struct burst_coalesce_impl {
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static constexpr int32_t value = _N;
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static constexpr int32_t default_value = 0;
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};
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template <int32_t _N> struct cache {
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static constexpr int32_t value = _N;
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static constexpr int32_t default_value = 0;
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};
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template <int32_t _N> struct prefetch_impl {
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static constexpr int32_t value = _N;
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static constexpr int32_t default_value = 0;
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};
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template <int32_t _N> struct statically_coalesce_impl {
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static constexpr int32_t value = _N;
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static constexpr int32_t default_value = 1;
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};
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template <bool _B> using burst_coalesce = burst_coalesce_impl<_B>;
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template <bool _B> using prefetch = prefetch_impl<_B>;
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template <bool _B> using statically_coalesce = statically_coalesce_impl<_B>;
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template <class... _mem_access_params> class lsu final {
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public:
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lsu() = delete;
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template <class... _Params, typename _T, access::address_space _space>
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static _T load(sycl::multi_ptr<_T, _space> Ptr) {
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check_space<_space>();
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check_load();
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#if defined(__SYCL_DEVICE_ONLY__) && __has_builtin(__builtin_intel_fpga_mem)
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static constexpr auto _anchor_id =
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_GetValue<int32_t, latency_anchor_id, _Params...>::value;
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static constexpr auto _constraint =
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_GetValue3<int32_t, type, int32_t, latency_constraint,
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_Params...>::value;
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static constexpr int32_t _target_anchor = std::get<0>(_constraint);
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static constexpr type _control_type = std::get<1>(_constraint);
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static constexpr int32_t _cycle = std::get<2>(_constraint);
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int32_t _type = 0; // Default: _control_type == type::none
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if constexpr (_control_type == type::exact) {
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_type = 1;
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} else if constexpr (_control_type == type::max) {
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_type = 2;
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} else if constexpr (_control_type == type::min) {
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_type = 3;
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}
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return *__latency_control_mem_wrapper((_T *)Ptr, _anchor_id, _target_anchor,
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_type, _cycle);
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#else
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return *Ptr;
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#endif
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}
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template <class... _Params, typename _T, access::address_space _space>
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static void store(sycl::multi_ptr<_T, _space> Ptr, _T Val) {
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check_space<_space>();
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check_store();
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#if defined(__SYCL_DEVICE_ONLY__) && __has_builtin(__builtin_intel_fpga_mem)
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static constexpr auto _anchor_id =
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_GetValue<int32_t, latency_anchor_id, _Params...>::value;
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static constexpr auto _constraint =
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_GetValue3<int32_t, type, int32_t, latency_constraint,
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_Params...>::value;
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static constexpr int32_t _target_anchor = std::get<0>(_constraint);
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static constexpr type _control_type = std::get<1>(_constraint);
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static constexpr int32_t _cycle = std::get<2>(_constraint);
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int32_t _type = 0; // Default: _control_type == type::none
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if constexpr (_control_type == type::exact) {
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_type = 1;
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} else if constexpr (_control_type == type::max) {
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_type = 2;
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} else if constexpr (_control_type == type::min) {
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_type = 3;
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}
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*__latency_control_mem_wrapper((_T *)Ptr, _anchor_id, _target_anchor, _type,
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_cycle) = Val;
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#else
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*Ptr = Val;
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#endif
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}
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private:
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static constexpr int32_t _burst_coalesce_val =
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_GetValue<int32_t, burst_coalesce_impl, _mem_access_params...>::value;
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static constexpr uint8_t _burst_coalesce =
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_burst_coalesce_val == 1 ? BURST_COALESCE : 0;
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static constexpr int32_t _cache_val =
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_GetValue<int32_t, cache, _mem_access_params...>::value;
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static constexpr uint8_t _cache = (_cache_val > 0) ? CACHE : 0;
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static constexpr int32_t _statically_coalesce_val =
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_GetValue<int32_t, statically_coalesce_impl,
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_mem_access_params...>::value;
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static constexpr uint8_t _dont_statically_coalesce =
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_statically_coalesce_val == 0 ? STATICALLY_COALESCE : 0;
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static constexpr int32_t _prefetch_val =
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_GetValue<int32_t, prefetch_impl, _mem_access_params...>::value;
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static constexpr uint8_t _prefetch = _prefetch_val ? PREFETCH : 0;
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static_assert(_cache_val >= 0, "cache size parameter must be non-negative");
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template <access::address_space _space> static void check_space() {
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static_assert(_space == access::address_space::global_space ||
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_space == access::address_space::global_device_space ||
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_space == access::address_space::global_host_space,
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"lsu controls are only supported for global_ptr, "
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"device_ptr, and host_ptr objects");
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}
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static void check_load() {
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static_assert(_cache == 0 || _burst_coalesce == BURST_COALESCE,
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"unable to implement a cache without a burst coalescer");
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static_assert(_prefetch == 0 || _burst_coalesce == 0,
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"unable to implement a prefetcher and a burst coalescer "
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"simulataneously");
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static_assert(
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_prefetch == 0 || _cache == 0,
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"unable to implement a prefetcher and a cache simulataneously");
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}
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static void check_store() {
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static_assert(_cache == 0, "unable to implement a store LSU with a cache.");
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static_assert(_prefetch == 0,
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"unable to implement a store LSU with a prefetcher.");
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}
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#if defined(__SYCL_DEVICE_ONLY__) && __has_builtin(__builtin_intel_fpga_mem)
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// FPGA BE will recognize this function and extract its arguments.
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// TODO: Pass latency control params via __builtin_intel_fpga_mem when ready.
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template <typename _T>
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static _T *__latency_control_mem_wrapper(_T *Ptr, int32_t AnchorID,
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int32_t TargetAnchor, int32_t Type,
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int32_t Cycle) {
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return __builtin_intel_fpga_mem(
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Ptr, _burst_coalesce | _cache | _dont_statically_coalesce | _prefetch,
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_cache_val);
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}
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#endif
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};
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} // namespace experimental
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} // namespace intel
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} // namespace ext
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} // namespace sycl
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} // __SYCL_INLINE_NAMESPACE(cl)

‎sycl/include/sycl/ext/intel/experimental/fpga_utils.hpp

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//==------------- fpga_utils.hpp --- SYCL FPGA Reg Extensions --------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#pragma once
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#include <CL/sycl/detail/defines.hpp>
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#include <CL/sycl/detail/stl_type_traits.hpp>
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#include <CL/sycl/stl.hpp>
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#include <tuple>
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__SYCL_INLINE_NAMESPACE(cl) {
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namespace sycl {
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namespace ext {
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namespace intel {
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namespace experimental {
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enum class type {
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none, // default
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exact,
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max,
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min
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};
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template <int32_t _N> struct latency_anchor_id {
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static constexpr int32_t value = _N;
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static constexpr int32_t default_value = -1;
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};
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template <int32_t _N1, type _N2, int32_t _N3> struct latency_constraint {
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static constexpr std::tuple<int32_t, type, int32_t> value = {_N1, _N2, _N3};
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static constexpr std::tuple<int32_t, type, int32_t> default_value = {
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0, type::none, 0};
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};
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using ignoreParam_int_t = int32_t;
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constexpr ignoreParam_int_t IgnoreParamInt{};
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using ignoreParam_enum_t = type;
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constexpr ignoreParam_enum_t IgnoreParamEnum{};
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template <class _VType, class _T> struct _ValueExtractorImp {
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static constexpr auto _First = _T::value;
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static constexpr auto _Second = IgnoreParamEnum;
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static constexpr auto _Third = IgnoreParamInt;
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};
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template <class _VTypeFirst, class _VTypeSecond, class _VTypeThird, class _T>
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struct _ValueExtractorImp<
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const std::tuple<_VTypeFirst, _VTypeSecond, _VTypeThird>, _T> {
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static constexpr auto _First = std::get<0>(_T::value);
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static constexpr auto _Second = std::get<1>(_T::value);
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static constexpr auto _Third = std::get<2>(_T::value);
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};
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template <class _T>
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struct _ValueExtractor : _ValueExtractorImp<decltype(_T::value), _T> {};
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template <class _VTypeFirst, class _VTypeSecond, class _VTypeThird,
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template <_VTypeFirst, _VTypeSecond, _VTypeThird> class _Type,
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class _T>
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struct _MatchType
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: std::is_same<
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_Type<_ValueExtractor<_T>::_First, _ValueExtractor<_T>::_Second,
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_ValueExtractor<_T>::_Third>,
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_T> {};
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template <class _VTypeFirst, class _VTypeSecond, class _VTypeThird,
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template <_VTypeFirst, _VTypeSecond, _VTypeThird> class _Type,
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class... _T>
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struct _GetValue3 {
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static constexpr auto value =
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_Type<_VTypeFirst{}, _VTypeSecond{}, _VTypeThird{}>::default_value;
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};
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template <class _VTypeFirst, class _VTypeSecond, class _VTypeThird,
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template <_VTypeFirst, _VTypeSecond, _VTypeThird> class _Type,
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class _T1, class... _T>
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struct _GetValue3<_VTypeFirst, _VTypeSecond, _VTypeThird, _Type, _T1, _T...> {
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static constexpr auto value = std::conditional<
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_MatchType<_VTypeFirst, _VTypeSecond, _VTypeThird, _Type, _T1>::value,
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_T1, _GetValue3<_VTypeFirst, _VTypeSecond, _VTypeThird, _Type, _T...>>::
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type::value;
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};
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template <class _VType, template <_VType> class _Type, class... _T>
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struct _GetValue {
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private:
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template <_VType _V1, ignoreParam_enum_t, ignoreParam_int_t>
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using _Type2 = _Type<_V1>;
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public:
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static constexpr auto value =
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_GetValue3<_VType, ignoreParam_enum_t, ignoreParam_int_t, _Type2,
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_T...>::value;
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};
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} // namespace experimental
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} // namespace intel
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} // namespace ext
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} // namespace sycl
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} // __SYCL_INLINE_NAMESPACE(cl)

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