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21 | 21 |
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22 | 22 | /// -fintelfpga -fsycl-link tests
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23 | 23 | // RUN: touch %t.o
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24 |
| -// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link %t.o -o libfoo.a 2>&1 \ |
| 24 | +// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga -fsycl-link %t.o -o libfoo.a 2>&1 \ |
25 | 25 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK,CHK-FPGA-EARLY %s
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26 |
| -// RUN: %clangxx -### -O2 -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.o -o libfoo.a 2>&1 \ |
| 26 | +// RUN: %clangxx -### -O2 -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.o -o libfoo.a 2>&1 \ |
27 | 27 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK,CHK-FPGA-EARLY %s
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28 |
| -// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=image %t.o -o libfoo.a 2>&1 \ |
| 28 | +// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga -fsycl-link=image %t.o -o libfoo.a 2>&1 \ |
29 | 29 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK,CHK-FPGA-IMAGE %s
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30 | 30 | // CHK-FPGA-LINK-NOT: clang-offload-bundler{{.*}} "-check-section"
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31 | 31 | // CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]]" "-unbundle"
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58 | 58 |
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59 | 59 | /// -fintelfpga -fsycl-link clang-cl specific
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60 | 60 | // RUN: touch %t.obj
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61 |
| -// RUN: %clang_cl -### -fsycl -fintelfpga -fno-sycl-device-lib=all -fsycl-link %t.obj -Folibfoo.lib 2>&1 \ |
| 61 | +// RUN: %clang_cl -### -fsycl -fno-sycl-dead-args-optimization -fintelfpga -fno-sycl-device-lib=all -fsycl-link %t.obj -Folibfoo.lib 2>&1 \ |
62 | 62 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-WIN %s
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63 |
| -// RUN: %clang_cl -### -fsycl -fintelfpga -fno-sycl-device-lib=all -fsycl-link %t.obj -o libfoo.lib 2>&1 \ |
| 63 | +// RUN: %clang_cl -### -fsycl -fno-sycl-dead-args-optimization -fintelfpga -fno-sycl-device-lib=all -fsycl-link %t.obj -o libfoo.lib 2>&1 \ |
64 | 64 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-WIN %s
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65 | 65 | // CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]]" "-unbundle"
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66 | 66 | // CHK-FPGA-LINK-WIN-NOT: clang-offload-bundler{{.*}}
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121 | 121 |
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122 | 122 | /// -fintelfpga with AOCR library and additional object
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123 | 123 | // RUN: touch %t2.o
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124 |
| -// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fno-sycl-device-lib=all -fsycl -fintelfpga %t-aocr.a %t2.o 2>&1 \ |
| 124 | +// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fno-sycl-device-lib=all -fsycl -fno-sycl-dead-args-optimization -fintelfpga %t-aocr.a %t2.o 2>&1 \ |
125 | 125 | // RUN: | FileCheck -check-prefixes=CHK-FPGA %s
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126 | 126 | // CHK-FPGA: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr-intel-unknown-sycldevice" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]]" "-unbundle"
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127 | 127 | // CHK-FPGA: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" {{.*}} "-g"
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174 | 174 | // CHK-FPGA-AOCX-WIN: link{{.*}} "[[LIBINPUT]]" "[[LLCOUT2]]"
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175 | 175 |
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176 | 176 | /// AOCX with source
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177 |
| -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -fno-sycl-device-lib=all %s %t_aocx.a -### 2>&1 \ |
| 177 | +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-dead-args-optimization -fintelfpga -fno-sycl-device-lib=all %s %t_aocx.a -### 2>&1 \ |
178 | 178 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-SRC,CHK-FPGA-AOCX-SRC-LIN %s
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179 |
| -// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga %s %t_aocx.a -### 2>&1 \ |
| 179 | +// RUN: %clang_cl -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga %s %t_aocx.a -### 2>&1 \ |
180 | 180 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-SRC,CHK-FPGA-AOCX-SRC-WIN %s
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181 | 181 | // CHK-FPGA-AOCX-SRC: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle"
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182 | 182 | // CHK-FPGA-AOCX-SRC: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]"
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197 | 197 |
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198 | 198 | /// AOCX with object
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199 | 199 | // RUN: touch %t.o
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200 |
| -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga %t.o %t_aocx.a -### 2>&1 \ |
| 200 | +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga %t.o %t_aocx.a -### 2>&1 \ |
201 | 201 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-OBJ,CHK-FPGA-AOCX-OBJ-LIN %s
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202 |
| -// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga %t.o %t_aocx.a -### 2>&1 \ |
| 202 | +// RUN: %clang_cl -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga %t.o %t_aocx.a -### 2>&1 \ |
203 | 203 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-OBJ,CHK-FPGA-AOCX-OBJ-WIN %s
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204 | 204 | // CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle"
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205 | 205 | // CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]"
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219 | 219 |
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220 | 220 | /// -fintelfpga -fsycl-link from source
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221 | 221 | // RUN: touch %t.cpp
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222 |
| -// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ |
| 222 | +// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ |
223 | 223 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-SRC %s
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224 |
| -// RUN: %clang_cl -### --target=x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ |
| 224 | +// RUN: %clang_cl -### --target=x86_64-unknown-linux-gnu -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ |
225 | 225 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-SRC %s
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226 | 226 | // CHK-FPGA-LINK-SRC: 0: input, "[[INPUT:.+\.cpp]]", c++, (host-sycl)
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227 | 227 | // CHK-FPGA-LINK-SRC: 1: preprocessor, {0}, c++-cpp-output, (host-sycl)
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314 | 314 |
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315 | 315 | /// -fintelfpga dependency file use from object phases test
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316 | 316 | // RUN: touch %t-1.o
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317 |
| -// RUN: %clangxx -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases -### %t-1.o 2>&1 \ |
| 317 | +// RUN: %clangxx -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases -### %t-1.o 2>&1 \ |
318 | 318 | // RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES-OBJ-PHASES %s
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319 |
| -// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases -### %t-1.o 2>&1 \ |
| 319 | +// RUN: %clang_cl -fsycl -fno-sycl-dead-args-optimization -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases -### %t-1.o 2>&1 \ |
320 | 320 | // RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES-OBJ-PHASES %s
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321 | 321 | // CHK-FPGA-DEP-FILES-OBJ-PHASES: 0: input, "{{.*}}-1.o", object, (host-sycl)
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322 | 322 | // CHK-FPGA-DEP-FILES-OBJ-PHASES: 1: clang-offload-unbundler, {0}, object, (host-sycl)
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