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[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions Differential Revision: https://reviews.llvm.org/D155668
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‎clang/lib/Sema/SemaChecking.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5405,7 +5405,7 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
54055405
!TI.hasFeature("zve64x"))
54065406
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
54075407
if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
5408-
!TI.hasFeature("experimental-zvfh"))
5408+
!TI.hasFeature("zvfh"))
54095409
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfh";
54105410
if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
54115411
!TI.hasFeature("zve32f"))

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c

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Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c

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@@ -1,7 +1,7 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c

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@@ -1,7 +1,7 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c

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@@ -1,7 +1,7 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c

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@@ -1,7 +1,7 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c

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Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c

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@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c

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@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c

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@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c

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11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c

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@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfh -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

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