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[InlineAsm] wrap Kind in enum class NFC
Should add some minor type safety to the use of this information, since there's quite a bit of metadata being laundered through an `unsigned`. I'm looking to potentially add more bitfields to that `unsigned`, but I find InlineAsm's big ol' bag of enum values and usage of `unsigned` confusing, type-unsafe, and un-ergonomic. These can probably be better abstracted. I think the lack of static_cast outside of InlineAsm indicates the prior code smell fixed here. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D159242
1 parent cdd5b16 commit 2fad6e6

16 files changed

+135
-135
lines changed

‎llvm/include/llvm/IR/InlineAsm.h

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -200,14 +200,14 @@ class InlineAsm final : public Value {
200200
// in the backend.
201201
//
202202
// The encoding of the flag word is currently:
203-
// Bits 2-0 - A Kind_* value indicating the kind of the operand.
203+
// Bits 2-0 - A Kind::* value indicating the kind of the operand.
204204
// Bits 15-3 - The number of SDNode operands associated with this inline
205205
// assembly operand.
206206
// If bit 31 is set:
207207
// Bit 30-16 - The operand number that this operand must match.
208-
// When bits 2-0 are Kind_Mem, the Constraint_* value must be
208+
// When bits 2-0 are Kind::Mem, the Constraint_* value must be
209209
// obtained from the flags for this operand number.
210-
// Else if bits 2-0 are Kind_Mem:
210+
// Else if bits 2-0 are Kind::Mem:
211211
// Bit 30-16 - A Constraint_* value indicating the original constraint
212212
// code.
213213
// Else:
@@ -218,12 +218,12 @@ class InlineAsm final : public Value {
218218
Op_InputChain = 0,
219219
Op_AsmString = 1,
220220
Op_MDNode = 2,
221-
Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
221+
Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
222222
Op_FirstOperand = 4,
223223

224224
// Fixed operands on an INLINEASM MachineInstr.
225225
MIOp_AsmString = 0,
226-
MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
226+
MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
227227
MIOp_FirstOperand = 2,
228228

229229
// Interpretation of the MIOp_ExtraInfo bit field.
@@ -234,17 +234,6 @@ class InlineAsm final : public Value {
234234
Extra_MayStore = 16,
235235
Extra_IsConvergent = 32,
236236

237-
// Inline asm operands map to multiple SDNode / MachineInstr operands.
238-
// The first operand is an immediate describing the asm operand, the low
239-
// bits is the kind:
240-
Kind_RegUse = 1, // Input register, "r".
241-
Kind_RegDef = 2, // Output register, "=r".
242-
Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
243-
Kind_Clobber = 4, // Clobbered register, "~r".
244-
Kind_Imm = 5, // Immediate.
245-
Kind_Mem = 6, // Memory operand, "m", or an address, "p".
246-
Kind_Func = 7, // Address operand of function call
247-
248237
// Memory constraint codes.
249238
// These could be tablegenerated but there's little need to do that since
250239
// there's plenty of space in the encoding to support the union of all
@@ -290,21 +279,35 @@ class InlineAsm final : public Value {
290279
Flag_MatchingOperand = 0x80000000
291280
};
292281

293-
static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
282+
// Inline asm operands map to multiple SDNode / MachineInstr operands.
283+
// The first operand is an immediate describing the asm operand, the low
284+
// bits is the kind:
285+
enum class Kind {
286+
RegUse = 1, // Input register, "r".
287+
RegDef = 2, // Output register, "=r".
288+
RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
289+
Clobber = 4, // Clobbered register, "~r".
290+
Imm = 5, // Immediate.
291+
Mem = 6, // Memory operand, "m", or an address, "p".
292+
Func = 7, // Address operand of function call
293+
};
294+
295+
static unsigned getFlagWord(Kind Kind, unsigned NumOps) {
294296
assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
295-
assert(Kind >= Kind_RegUse && Kind <= Kind_Func && "Invalid Kind");
296-
return Kind | (NumOps << 3);
297+
return static_cast<unsigned>(Kind) | (NumOps << 3);
297298
}
298299

299-
static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
300-
static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
301-
static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
302-
static bool isFuncKind(unsigned Flag) { return getKind(Flag) == Kind_Func; }
300+
static bool isRegDefKind(unsigned Flag) {
301+
return getKind(Flag) == Kind::RegDef;
302+
}
303+
static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind::Imm; }
304+
static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind::Mem; }
305+
static bool isFuncKind(unsigned Flag) { return getKind(Flag) == Kind::Func; }
303306
static bool isRegDefEarlyClobberKind(unsigned Flag) {
304-
return getKind(Flag) == Kind_RegDefEarlyClobber;
307+
return getKind(Flag) == Kind::RegDefEarlyClobber;
305308
}
306309
static bool isClobberKind(unsigned Flag) {
307-
return getKind(Flag) == Kind_Clobber;
310+
return getKind(Flag) == Kind::Clobber;
308311
}
309312

310313
/// getFlagWordForMatchingOp - Augment an existing flag word returned by
@@ -348,9 +351,7 @@ class InlineAsm final : public Value {
348351
return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
349352
}
350353

351-
static unsigned getKind(unsigned Flags) {
352-
return Flags & 7;
353-
}
354+
static Kind getKind(unsigned Flags) { return static_cast<Kind>(Flags & 7); }
354355

355356
static unsigned getMemoryConstraintID(unsigned Flag) {
356357
assert((isMemKind(Flag) || isFuncKind(Flag)) &&
@@ -411,24 +412,23 @@ class InlineAsm final : public Value {
411412
return Result;
412413
}
413414

414-
static StringRef getKindName(unsigned Kind) {
415+
static StringRef getKindName(Kind Kind) {
415416
switch (Kind) {
416-
case InlineAsm::Kind_RegUse:
417+
case Kind::RegUse:
417418
return "reguse";
418-
case InlineAsm::Kind_RegDef:
419+
case Kind::RegDef:
419420
return "regdef";
420-
case InlineAsm::Kind_RegDefEarlyClobber:
421+
case Kind::RegDefEarlyClobber:
421422
return "regdef-ec";
422-
case InlineAsm::Kind_Clobber:
423+
case Kind::Clobber:
423424
return "clobber";
424-
case InlineAsm::Kind_Imm:
425+
case Kind::Imm:
425426
return "imm";
426-
case InlineAsm::Kind_Mem:
427-
case InlineAsm::Kind_Func:
427+
case Kind::Mem:
428+
case Kind::Func:
428429
return "mem";
429-
default:
430-
llvm_unreachable("Unknown operand kind");
431430
}
431+
llvm_unreachable("Unknown operand kind");
432432
}
433433

434434
static StringRef getMemConstraintName(unsigned Constraint) {

‎llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -380,7 +380,7 @@ void AsmPrinter::emitInlineAsm(const MachineInstr *MI) const {
380380
if (!MO.isImm())
381381
continue;
382382
unsigned Flags = MO.getImm();
383-
if (InlineAsm::getKind(Flags) == InlineAsm::Kind_Clobber) {
383+
if (InlineAsm::getKind(Flags) == InlineAsm::Kind::Clobber) {
384384
Register Reg = MI->getOperand(I + 1).getReg();
385385
if (!TRI->isAsmClobberable(*MF, Reg))
386386
RestrRegs.push_back(Reg);

‎llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -380,7 +380,7 @@ bool InlineAsmLowering::lowerInlineAsm(
380380

381381
// Add information to the INLINEASM instruction to know about this
382382
// output.
383-
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
383+
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
384384
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
385385
Inst.addImm(OpFlags);
386386
ArrayRef<Register> SourceRegs =
@@ -406,8 +406,8 @@ bool InlineAsmLowering::lowerInlineAsm(
406406
// Add information to the INLINEASM instruction to know that this
407407
// register is set.
408408
unsigned Flag = InlineAsm::getFlagWord(
409-
OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
410-
: InlineAsm::Kind_RegDef,
409+
OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
410+
: InlineAsm::Kind::RegDef,
411411
OpInfo.Regs.size());
412412
if (OpInfo.Regs.front().isVirtual()) {
413413
// Put the register class of the virtual registers in the flag word.
@@ -470,7 +470,7 @@ bool InlineAsmLowering::lowerInlineAsm(
470470
}
471471

472472
// Add Flag and input register operand (In) to Inst. Tie In to Def.
473-
unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
473+
unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, 1);
474474
unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx);
475475
Inst.addImm(Flag);
476476
Inst.addReg(In);
@@ -502,7 +502,7 @@ bool InlineAsmLowering::lowerInlineAsm(
502502

503503
// Add information to the INLINEASM node to know about this input.
504504
unsigned OpFlags =
505-
InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
505+
InlineAsm::getFlagWord(InlineAsm::Kind::Imm, Ops.size());
506506
Inst.addImm(OpFlags);
507507
Inst.add(Ops);
508508
break;
@@ -520,7 +520,7 @@ bool InlineAsmLowering::lowerInlineAsm(
520520

521521
unsigned ConstraintID =
522522
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
523-
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
523+
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
524524
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
525525
Inst.addImm(OpFlags);
526526
ArrayRef<Register> SourceRegs =
@@ -563,7 +563,7 @@ bool InlineAsmLowering::lowerInlineAsm(
563563
return false;
564564
}
565565

566-
unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs);
566+
unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, NumRegs);
567567
if (OpInfo.Regs.front().isVirtual()) {
568568
// Put the register class of the virtual registers in the flag word.
569569
const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
@@ -581,7 +581,7 @@ bool InlineAsmLowering::lowerInlineAsm(
581581
unsigned NumRegs = OpInfo.Regs.size();
582582
if (NumRegs > 0) {
583583
unsigned Flag =
584-
InlineAsm::getFlagWord(InlineAsm::Kind_Clobber, NumRegs);
584+
InlineAsm::getFlagWord(InlineAsm::Kind::Clobber, NumRegs);
585585
Inst.addImm(Flag);
586586

587587
for (Register Reg : OpInfo.Regs) {

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -924,14 +924,14 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx,
924924

925925
unsigned Flag = getOperand(FlagIdx).getImm();
926926
unsigned RCID;
927-
if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
928-
InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
929-
InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
927+
if ((InlineAsm::getKind(Flag) == InlineAsm::Kind::RegUse ||
928+
InlineAsm::getKind(Flag) == InlineAsm::Kind::RegDef ||
929+
InlineAsm::getKind(Flag) == InlineAsm::Kind::RegDefEarlyClobber) &&
930930
InlineAsm::hasRegClassConstraint(Flag, RCID))
931931
return TRI->getRegClass(RCID);
932932

933933
// Assume that all registers in a memory operand are pointers.
934-
if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
934+
if (InlineAsm::getKind(Flag) == InlineAsm::Kind::Mem)
935935
return TRI->getPointerRegClass(MF);
936936

937937
return nullptr;

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1318,8 +1318,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
13181318
++i; // Skip the ID value.
13191319

13201320
switch (InlineAsm::getKind(Flags)) {
1321-
default: llvm_unreachable("Bad flags!");
1322-
case InlineAsm::Kind_RegDef:
1321+
case InlineAsm::Kind::RegDef:
13231322
for (unsigned j = 0; j != NumVals; ++j, ++i) {
13241323
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
13251324
// FIXME: Add dead flags for physical and virtual registers defined.
@@ -1328,26 +1327,26 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
13281327
MIB.addReg(Reg, RegState::Define | getImplRegState(Reg.isPhysical()));
13291328
}
13301329
break;
1331-
case InlineAsm::Kind_RegDefEarlyClobber:
1332-
case InlineAsm::Kind_Clobber:
1330+
case InlineAsm::Kind::RegDefEarlyClobber:
1331+
case InlineAsm::Kind::Clobber:
13331332
for (unsigned j = 0; j != NumVals; ++j, ++i) {
13341333
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
13351334
MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
13361335
getImplRegState(Reg.isPhysical()));
13371336
ECRegs.push_back(Reg);
13381337
}
13391338
break;
1340-
case InlineAsm::Kind_RegUse: // Use of register.
1341-
case InlineAsm::Kind_Imm: // Immediate.
1342-
case InlineAsm::Kind_Mem: // Non-function addressing mode.
1339+
case InlineAsm::Kind::RegUse: // Use of register.
1340+
case InlineAsm::Kind::Imm: // Immediate.
1341+
case InlineAsm::Kind::Mem: // Non-function addressing mode.
13431342
// The addressing mode has been selected, just add all of the
13441343
// operands to the machine instruction.
13451344
for (unsigned j = 0; j != NumVals; ++j, ++i)
13461345
AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
13471346
/*IsDebug=*/false, IsClone, IsCloned);
13481347

13491348
// Manually set isTied bits.
1350-
if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1349+
if (InlineAsm::getKind(Flags) == InlineAsm::Kind::RegUse) {
13511350
unsigned DefGroup = 0;
13521351
if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
13531352
unsigned DefIdx = GroupIdx[DefGroup] + 1;
@@ -1357,7 +1356,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
13571356
}
13581357
}
13591358
break;
1360-
case InlineAsm::Kind_Func: // Function addressing mode.
1359+
case InlineAsm::Kind::Func: // Function addressing mode.
13611360
for (unsigned j = 0; j != NumVals; ++j, ++i) {
13621361
SDValue Op = Node->getOperand(i);
13631362
AddOperand(MIB, Op, 0, nullptr, VRBaseMap,

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -989,7 +989,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
989989
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
990990
}
991991

992-
void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
992+
void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
993993
unsigned MatchingIdx, const SDLoc &dl,
994994
SelectionDAG &DAG,
995995
std::vector<SDValue> &Ops) const {
@@ -1012,7 +1012,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
10121012
SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
10131013
Ops.push_back(Res);
10141014

1015-
if (Code == InlineAsm::Kind_Clobber) {
1015+
if (Code == InlineAsm::Kind::Clobber) {
10161016
// Clobbers should always have a 1:1 mapping with registers, and may
10171017
// reference registers that have illegal (e.g. vector) types. Hence, we
10181018
// shouldn't try to apply any sort of splitting logic to them.
@@ -9279,7 +9279,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
92799279
"Failed to convert memory constraint code to constraint id.");
92809280

92819281
// Add information to the INLINEASM node to know about this output.
9282-
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
9282+
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
92839283
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
92849284
AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
92859285
MVT::i32));
@@ -9301,8 +9301,8 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
93019301
// Add information to the INLINEASM node to know that this register is
93029302
// set.
93039303
OpInfo.AssignedRegs.AddInlineAsmOperands(
9304-
OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
9305-
: InlineAsm::Kind_RegDef,
9304+
OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
9305+
: InlineAsm::Kind::RegDef,
93069306
false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
93079307
}
93089308
break;
@@ -9349,9 +9349,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
93499349
SDLoc dl = getCurSDLoc();
93509350
// Use the produced MatchedRegs object to
93519351
MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, &Call);
9352-
MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
9353-
true, OpInfo.getMatchedOperand(), dl,
9354-
DAG, AsmNodeOperands);
9352+
MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, true,
9353+
OpInfo.getMatchedOperand(), dl, DAG,
9354+
AsmNodeOperands);
93559355
break;
93569356
}
93579357

@@ -9395,7 +9395,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
93959395

93969396
// Add information to the INLINEASM node to know about this input.
93979397
unsigned ResOpType =
9398-
InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
9398+
InlineAsm::getFlagWord(InlineAsm::Kind::Imm, Ops.size());
93999399
AsmNodeOperands.push_back(DAG.getTargetConstant(
94009400
ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
94019401
llvm::append_range(AsmNodeOperands, Ops);
@@ -9416,7 +9416,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
94169416
"Failed to convert memory constraint code to constraint id.");
94179417

94189418
// Add information to the INLINEASM node to know about this input.
9419-
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
9419+
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
94209420
ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
94219421
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
94229422
getCurSDLoc(),
@@ -9431,12 +9431,12 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
94319431
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
94329432
"Failed to convert memory constraint code to constraint id.");
94339433

9434-
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
9434+
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
94359435

94369436
SDValue AsmOp = InOperandVal;
94379437
if (isFunction(InOperandVal)) {
94389438
auto *GA = cast<GlobalAddressSDNode>(InOperandVal);
9439-
ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Func, 1);
9439+
ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Func, 1);
94409440
AsmOp = DAG.getTargetGlobalAddress(GA->getGlobal(), getCurSDLoc(),
94419441
InOperandVal.getValueType(),
94429442
GA->getOffset());
@@ -9481,15 +9481,15 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
94819481
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue,
94829482
&Call);
94839483

9484-
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
9485-
dl, DAG, AsmNodeOperands);
9484+
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, false,
9485+
0, dl, DAG, AsmNodeOperands);
94869486
break;
94879487
}
94889488
case InlineAsm::isClobber:
94899489
// Add the clobbered value to the operand list, so that the register
94909490
// allocator is aware that the physreg got clobbered.
94919491
if (!OpInfo.AssignedRegs.Regs.empty())
9492-
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
9492+
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::Clobber,
94939493
false, 0, getCurSDLoc(), DAG,
94949494
AsmNodeOperands);
94959495
break;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -787,7 +787,7 @@ struct RegsForValue {
787787
/// Add this value to the specified inlineasm node operand list. This adds the
788788
/// code marker, matching input operand index (if applicable), and includes
789789
/// the number of values added into it.
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void AddInlineAsmOperands(unsigned Code, bool HasMatching,
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void AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
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unsigned MatchingIdx, const SDLoc &dl,
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SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
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