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[SYCL] Reverse logic of how we add SPIR-V extensions (#3642)
New extensions no longer passed to the translator by default, so we can wait until they are supported by devices' SPIR-V consumers. Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
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+75
-28
lines changed

4 files changed

+75
-28
lines changed

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 31 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8446,28 +8446,47 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
84468446
TranslatorArgs.push_back("-spirv-allow-extra-diexpressions");
84478447
TranslatorArgs.push_back("-spirv-allow-unknown-intrinsics=llvm.genx.");
84488448

8449-
// Disable SPV_INTEL_usm_storage_classes by default since it adds new
8450-
// storage classes that represent global_device and global_host address
8451-
// spaces, which are not supported for all targets. With the extension
8452-
// disable the storage classes will be lowered to CrossWorkgroup storage
8453-
// class that is mapped to just global address space. The extension is
8454-
// supposed to be enabled only for FPGA hardware.
8455-
std::string ExtArg("-spirv-ext=+all,-SPV_INTEL_usm_storage_classes");
8449+
// Disable all the extensions by default
8450+
std::string ExtArg("-spirv-ext=-all");
8451+
std::string DefaultExtArg =
8452+
",+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float_min_max"
8453+
",+SPV_KHR_no_integer_wrap_decoration,+SPV_KHR_float_controls";
8454+
std::string INTELExtArg =
8455+
",+SPV_INTEL_subgroups,+SPV_INTEL_media_block_io"
8456+
",+SPV_INTEL_device_side_avc_motion_estimation"
8457+
",+SPV_INTEL_fpga_loop_controls,+SPV_INTEL_fpga_memory_attributes"
8458+
",+SPV_INTEL_fpga_memory_accesses"
8459+
",+SPV_INTEL_unstructured_loop_controls,+SPV_INTEL_fpga_reg"
8460+
",+SPV_INTEL_blocking_pipes,+SPV_INTEL_function_pointers"
8461+
",+SPV_INTEL_kernel_attributes,+SPV_INTEL_io_pipes"
8462+
",+SPV_INTEL_inline_assembly,+SPV_INTEL_arbitrary_precision_integers"
8463+
",+SPV_INTEL_optimization_hints,+SPV_INTEL_float_controls2"
8464+
",+SPV_INTEL_vector_compute,+SPV_INTEL_fast_composite"
8465+
",+SPV_INTEL_fpga_buffer_location"
8466+
",+SPV_INTEL_arbitrary_precision_fixed_point"
8467+
",+SPV_INTEL_arbitrary_precision_floating_point"
8468+
",+SPV_INTEL_arbitrary_precision_floating_point"
8469+
",+SPV_INTEL_variable_length_array,+SPV_INTEL_fp_fast_math_mode"
8470+
",+SPV_INTEL_fpga_cluster_attributes,+SPV_INTEL_loop_fuse"
8471+
",+SPV_INTEL_long_constant_composite";
8472+
ExtArg = ExtArg + DefaultExtArg + INTELExtArg;
84568473
if (getToolChain().getTriple().getSubArch() ==
84578474
llvm::Triple::SPIRSubArch_fpga) {
84588475
for (auto *A : TCArgs) {
84598476
if (A->getOption().matches(options::OPT_Xs_separate) ||
84608477
A->getOption().matches(options::OPT_Xs)) {
84618478
StringRef ArgString(A->getValue());
8479+
// Enable SPV_INTEL_usm_storage_classes only for FPGA hardware,
8480+
// since it adds new storage classes that represent global_device and
8481+
// global_host address spaces, which are not supported for all
8482+
// targets. With the extension disabled the storage classes will be
8483+
// lowered to CrossWorkgroup storage class that is mapped to just
8484+
// global address space.
84628485
if (ArgString == "hardware" || ArgString == "simulation")
8463-
ExtArg = "-spirv-ext=+all";
8486+
ExtArg += ",+SPV_INTEL_usm_storage_classes";
84648487
}
84658488
}
84668489
}
8467-
// Temporary disable SPV_INTEL_optnone & SPV_KHR_linkonce_odr &
8468-
// SPV_INTEL_memory_access_aliasinguntil some targets support it.
8469-
ExtArg += ",-SPV_INTEL_optnone,-SPV_KHR_linkonce_odr"
8470-
",-SPV_INTEL_memory_access_aliasing";
84718490
TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg));
84728491
}
84738492
for (auto I : Inputs) {

‎clang/test/Driver/sycl-offload.c

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -636,21 +636,21 @@
636636

637637
/// Ahead of Time compilation for fpga, gen, cpu - tool invocation
638638
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s -### 2>&1 \
639-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
639+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-EMU
640640
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga %s -### 2>&1 \
641-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
641+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-EMU
642642
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xshardware %s -### 2>&1 \
643-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
643+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-HW
644644
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %s -### 2>&1 \
645-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
645+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-HW
646646
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xssimulation %s -### 2>&1 \
647-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
647+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-HW
648648
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xssimulation %s -### 2>&1 \
649-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
649+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-HW
650650
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xsemulator %s -### 2>&1 \
651-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
651+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-EMU
652652
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xsemulator %s -### 2>&1 \
653-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
653+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-EMU
654654
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \
655655
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN
656656
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s -### 2>&1 \
@@ -666,12 +666,11 @@
666666
// CHK-TOOLS-AOTx: "-o" "[[OUTPUT1:.+\.bc]]"
667667
// CHK-TOOLS-AOT: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2:.+\.bc]]"
668668
// CHK-TOOLS-AOT: sycl-post-link{{.*}} "-o" "[[OUTPUT2_1:.+\.bc]]" "[[OUTPUT2]]"
669-
// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes,-SPV_INTEL_optnone,-SPV_KHR_linkonce_odr,-SPV_INTEL_memory_access_aliasing" "[[OUTPUT2_1]]"
670-
// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes,-SPV_INTEL_optnone,-SPV_KHR_linkonce_odr,-SPV_INTEL_memory_access_aliasing" "[[OUTPUT2_1]]"
671-
// CHK-TOOLS-FPGA-USM-DISABLE: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes,-SPV_INTEL_optnone,-SPV_KHR_linkonce_odr,-SPV_INTEL_memory_access_aliasing" "[[OUTPUT2_1]]"
672-
// CHK-TOOLS-FPGA-USM-ENABLE: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." "-spirv-ext=+all,-SPV_INTEL_optnone,-SPV_KHR_linkonce_odr,-SPV_INTEL_memory_access_aliasing" "[[OUTPUT2_1]]"
673-
// CHK-TOOLS-FPGA-USM-ENABLE: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]"
674-
// CHK-TOOLS-FPGA-USM-DISABLE: opencl-aot{{.*}} "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]"
669+
// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
670+
// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
671+
// CHK-TOOLS-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
672+
// CHK-TOOLS-FPGA-HW: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]"
673+
// CHK-TOOLS-FPGA-EMU: opencl-aot{{.*}} "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]"
675674
// CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]"
676675
// CHK-TOOLS-CPU: opencl-aot{{.*}} "-o=[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]"
677676
// CHK-TOOLS-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga{{.*}}" "-kind=sycl" "[[OUTPUT4]]"

‎clang/test/Driver/sycl-spirv-ext.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64-unknown-unknown-sycldevice %s -### 2>&1 \
2+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
3+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s -### 2>&1 \
4+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
5+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %s -### 2>&1 \
6+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
7+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xshardware %s -### 2>&1 \
8+
// RUN: | FileCheck %s -check-prefixes=CHECK-FPGA-HW
9+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -Xshardware %s -### 2>&1 \
10+
// RUN: | FileCheck %s -check-prefixes=CHECK-FPGA-HW
11+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xssimulation %s -### 2>&1 \
12+
// RUN: | FileCheck %s -check-prefixes=CHECK-FPGA-HW
13+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -Xssimulation %s -### 2>&1 \
14+
// RUN: | FileCheck %s -check-prefixes=CHECK-FPGA-HW
15+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xsemulator %s -### 2>&1 \
16+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
17+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -Xsemulator %s -### 2>&1 \
18+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
19+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \
20+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
21+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s -### 2>&1 \
22+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
23+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \
24+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
25+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s -### 2>&1 \
26+
// RUN: | FileCheck %s -check-prefixes=CHECK-DEFAULT
27+
28+
// CHECK-DEFAULT: llvm-spirv{{.*}}"-spirv-ext=-all,+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float_min_max,+SPV_KHR_no_integer_wrap_decoration,+SPV_KHR_float_controls,+SPV_INTEL_subgroups,+SPV_INTEL_media_block_io,+SPV_INTEL_device_side_avc_motion_estimation,+SPV_INTEL_fpga_loop_controls,+SPV_INTEL_fpga_memory_attributes,+SPV_INTEL_fpga_memory_accesses,+SPV_INTEL_unstructured_loop_controls,+SPV_INTEL_fpga_reg,+SPV_INTEL_blocking_pipes,+SPV_INTEL_function_pointers,+SPV_INTEL_kernel_attributes,+SPV_INTEL_io_pipes,+SPV_INTEL_inline_assembly,+SPV_INTEL_arbitrary_precision_integers,+SPV_INTEL_optimization_hints,+SPV_INTEL_float_controls2,+SPV_INTEL_vector_compute,+SPV_INTEL_fast_composite,+SPV_INTEL_fpga_buffer_location,+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_variable_length_array,+SPV_INTEL_fp_fast_math_mode,+SPV_INTEL_fpga_cluster_attributes,+SPV_INTEL_loop_fuse,+SPV_INTEL_long_constant_composite"
29+
// CHECK-FPGA-HW: llvm-spirv{{.*}}"-spirv-ext=-all,+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float_min_max,+SPV_KHR_no_integer_wrap_decoration,+SPV_KHR_float_controls,+SPV_INTEL_subgroups,+SPV_INTEL_media_block_io,+SPV_INTEL_device_side_avc_motion_estimation,+SPV_INTEL_fpga_loop_controls,+SPV_INTEL_fpga_memory_attributes,+SPV_INTEL_fpga_memory_accesses,+SPV_INTEL_unstructured_loop_controls,+SPV_INTEL_fpga_reg,+SPV_INTEL_blocking_pipes,+SPV_INTEL_function_pointers,+SPV_INTEL_kernel_attributes,+SPV_INTEL_io_pipes,+SPV_INTEL_inline_assembly,+SPV_INTEL_arbitrary_precision_integers,+SPV_INTEL_optimization_hints,+SPV_INTEL_float_controls2,+SPV_INTEL_vector_compute,+SPV_INTEL_fast_composite,+SPV_INTEL_fpga_buffer_location,+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_variable_length_array,+SPV_INTEL_fp_fast_math_mode,+SPV_INTEL_fpga_cluster_attributes,+SPV_INTEL_loop_fuse,+SPV_INTEL_long_constant_composite,+SPV_INTEL_usm_storage_classes"

‎clang/test/Driver/sycl.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,11 +43,11 @@
4343
// DEFAULT: "-internal-isystem" "{{.*}}bin{{[/\\]+}}..{{[/\\]+}}include{{[/\\]+}}sycl"
4444
// DEFAULT: "-internal-isystem" "{{.*lib.*clang.*include}}"
4545
// DEFAULT: "-std=c++17"
46-
// DEFAULT-NOT: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.3"{{.*}} "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes,-SPV_INTEL_optnone,-SPV_KHR_linkonce_odr,-SPV_INTEL_memory_access_aliasing"
46+
// DEFAULT-NOT: "{{.*}}llvm-spirv"{{.*}}
4747
// DEFAULT-NOT: "-std=c++11"
4848
// DEFAULT-NOT: "-std=c++14"
4949
// NO-BITCODE: "-triple" "spir64-unknown-{{.*}}-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
50-
// NO-BITCODE: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.3"{{.*}} "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes,-SPV_INTEL_optnone,-SPV_KHR_linkonce_odr,-SPV_INTEL_memory_access_aliasing"
50+
// NO-BITCODE: "{{.*}}llvm-spirv"{{.*}}
5151
// TARGET: "-triple" "spir64-unknown-linux-sycldevice"{{.*}} "-emit-llvm-bc"
5252
// COMBINED: "-triple" "spir64-unknown-{{.*}}-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
5353
// TEXTUAL: "-triple" "spir64-unknown-{{.*}}-sycldevice{{.*}}" "-fsycl-is-device"{{.*}} "-emit-llvm"

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