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Merge remote-tracking branch 'my_remote/sycl' into AddNewDiagAttr
2 parents f4f08ec + f9241e0 commit 1f06268

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‎clang/include/clang/Basic/Attr.td

Lines changed: 0 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -1282,14 +1282,6 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
12821282
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12831283
let Subjects = SubjectList<[Function], ErrorDiag>;
12841284
let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
1285-
let AdditionalMembers = [{
1286-
static unsigned getMinValue() {
1287-
return 0;
1288-
}
1289-
static unsigned getMaxValue() {
1290-
return 1024*1024;
1291-
}
1292-
}];
12931285
}
12941286

12951287
def SYCLIntelMaxWorkGroupSize : InheritableAttr {
@@ -1349,14 +1341,6 @@ def SYCLIntelLoopFuse : InheritableAttr {
13491341
let Accessors = [Accessor<"isIndependent",
13501342
[CXX11<"intel", "loop_fuse_independent">]>];
13511343
let Documentation = [SYCLIntelLoopFuseDocs];
1352-
let AdditionalMembers = [{
1353-
static unsigned getMinValue() {
1354-
return 0;
1355-
}
1356-
static unsigned getMaxValue() {
1357-
return 1024*1024;
1358-
}
1359-
}];
13601344
}
13611345

13621346
def C11NoReturn : InheritableAttr {
@@ -2019,14 +2003,6 @@ def IntelFPGABankWidth : Attr {
20192003
Field], ErrorDiag>;
20202004
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20212005
let Documentation = [IntelFPGABankWidthAttrDocs];
2022-
let AdditionalMembers = [{
2023-
static unsigned getMinValue() {
2024-
return 1;
2025-
}
2026-
static unsigned getMaxValue() {
2027-
return 1024*1024;
2028-
}
2029-
}];
20302006
}
20312007

20322008
def IntelFPGANumBanks : Attr {
@@ -2037,14 +2013,6 @@ def IntelFPGANumBanks : Attr {
20372013
Field], ErrorDiag>;
20382014
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20392015
let Documentation = [IntelFPGANumBanksAttrDocs];
2040-
let AdditionalMembers = [{
2041-
static unsigned getMinValue() {
2042-
return 1;
2043-
}
2044-
static unsigned getMaxValue() {
2045-
return 1024*1024;
2046-
}
2047-
}];
20482016
}
20492017

20502018
def IntelFPGAPrivateCopies : InheritableAttr {
@@ -2054,14 +2022,6 @@ def IntelFPGAPrivateCopies : InheritableAttr {
20542022
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20552023
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
20562024
let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
2057-
let AdditionalMembers = [{
2058-
static unsigned getMinValue() {
2059-
return 0;
2060-
}
2061-
static unsigned getMaxValue() {
2062-
return 1024*1024;
2063-
}
2064-
}];
20652025
}
20662026

20672027
// Two string arguments.
@@ -2083,14 +2043,6 @@ def IntelFPGAMaxReplicates : Attr {
20832043
Field], ErrorDiag>;
20842044
let LangOpts = [SYCLIsDevice, SYCLIsHost];
20852045
let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
2086-
let AdditionalMembers = [{
2087-
static unsigned getMinValue() {
2088-
return 1;
2089-
}
2090-
static unsigned getMaxValue() {
2091-
return 1024*1024;
2092-
}
2093-
}];
20942046
}
20952047

20962048
def IntelFPGASimpleDualPort : Attr {
@@ -2126,14 +2078,6 @@ def IntelFPGABankBits : Attr {
21262078
Field], ErrorDiag>;
21272079
let LangOpts = [SYCLIsDevice, SYCLIsHost];
21282080
let Documentation = [IntelFPGABankBitsDocs];
2129-
let AdditionalMembers = [{
2130-
static unsigned getMinValue() {
2131-
return 0;
2132-
}
2133-
static unsigned getMaxValue() {
2134-
return 1024*1024;
2135-
}
2136-
}];
21372081
}
21382082

21392083
def IntelFPGAForcePow2Depth : Attr {

‎clang/include/clang/Driver/Action.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,6 @@ class Action {
7878
SPIRVTranslatorJobClass,
7979
SPIRCheckJobClass,
8080
SYCLPostLinkJobClass,
81-
PartialLinkJobClass,
8281
BackendCompileJobClass,
8382
FileTableTformJobClass,
8483
StaticLibJobClass,
@@ -747,18 +746,6 @@ class SYCLPostLinkJobAction : public JobAction {
747746
bool RTSetsSpecConsts = true;
748747
};
749748

750-
class PartialLinkJobAction : public JobAction {
751-
void anchor() override;
752-
753-
public:
754-
PartialLinkJobAction(Action *Input, types::ID OutputType);
755-
PartialLinkJobAction(ActionList &Input, types::ID OutputType);
756-
757-
static bool classof(const Action *A) {
758-
return A->getKind() == PartialLinkJobClass;
759-
}
760-
};
761-
762749
class BackendCompileJobAction : public JobAction {
763750
void anchor() override;
764751

‎clang/include/clang/Driver/ToolChain.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,6 @@ class ToolChain {
148148
mutable std::unique_ptr<Tool> SPIRVTranslator;
149149
mutable std::unique_ptr<Tool> SPIRCheck;
150150
mutable std::unique_ptr<Tool> SYCLPostLink;
151-
mutable std::unique_ptr<Tool> PartialLink;
152151
mutable std::unique_ptr<Tool> BackendCompiler;
153152
mutable std::unique_ptr<Tool> FileTableTform;
154153

@@ -165,7 +164,6 @@ class ToolChain {
165164
Tool *getSPIRVTranslator() const;
166165
Tool *getSPIRCheck() const;
167166
Tool *getSYCLPostLink() const;
168-
Tool *getPartialLink() const;
169167
Tool *getBackendCompiler() const;
170168
Tool *getTableTform() const;
171169

‎clang/include/clang/Sema/Sema.h

Lines changed: 35 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -10206,12 +10206,10 @@ class Sema final {
1020610206
void AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
1020710207
Expr **Exprs, unsigned Size);
1020810208
template <typename AttrType>
10209-
void addIntelSYCLSingleArgFunctionAttr(Decl *D, const AttributeCommonInfo &CI,
10210-
Expr *E);
10209+
void addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI, Expr *E);
1021110210
template <typename AttrType>
10212-
void addIntelSYCLTripleArgFunctionAttr(Decl *D, const AttributeCommonInfo &CI,
10213-
Expr *XDimExpr, Expr *YDimExpr,
10214-
Expr *ZDimExpr);
10211+
void addIntelTripleArgAttr(Decl *D, const AttributeCommonInfo &CI,
10212+
Expr *XDimExpr, Expr *YDimExpr, Expr *ZDimExpr);
1021510213
/// AddAlignedAttr - Adds an aligned attribute to a particular declaration.
1021610214
void AddAlignedAttr(Decl *D, const AttributeCommonInfo &CI, Expr *E,
1021710215
bool IsPackExpansion);
@@ -13059,9 +13057,8 @@ class Sema final {
1305913057
};
1306013058

1306113059
template <typename AttrType>
13062-
void Sema::addIntelSYCLSingleArgFunctionAttr(Decl *D,
13063-
const AttributeCommonInfo &CI,
13064-
Expr *E) {
13060+
void Sema::addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI,
13061+
Expr *E) {
1306513062
assert(E && "Attribute must have an argument.");
1306613063

1306713064
if (!E->isInstantiationDependent()) {
@@ -13071,30 +13068,45 @@ void Sema::addIntelSYCLSingleArgFunctionAttr(Decl *D,
1307113068
return;
1307213069
E = ICE.get();
1307313070
int32_t ArgInt = ArgVal.getSExtValue();
13074-
if (CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize) {
13071+
if (CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize ||
13072+
CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
1307513073
if (ArgInt <= 0) {
1307613074
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13077-
<< CI.getAttrName() << /*positive*/ 0;
13075+
<< CI << /*positive*/ 0;
1307813076
return;
1307913077
}
1308013078
}
1308113079
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim ||
1308213080
CI.getParsedKind() == ParsedAttr::AT_SYCLIntelNumSimdWorkItems) {
1308313081
if (ArgInt < 0) {
1308413082
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13085-
<< CI.getAttrName() << /*non-negative*/ 1;
13083+
<< CI << /*non-negative*/ 1;
1308613084
return;
1308713085
}
1308813086
}
1308913087
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim) {
1309013088
if (ArgInt > 3) {
1309113089
Diag(E->getBeginLoc(), diag::err_attribute_argument_out_of_range)
13092-
<< CI.getAttrName() << 0 << 3 << E->getSourceRange();
13090+
<< CI << 0 << 3 << E->getSourceRange();
13091+
return;
13092+
}
13093+
}
13094+
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelSchedulerTargetFmaxMhz ||
13095+
CI.getParsedKind() == ParsedAttr::AT_IntelFPGAPrivateCopies) {
13096+
if (ArgInt < 0) {
13097+
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13098+
<< CI << /*non-negative*/ 1;
1309313099
return;
1309413100
}
1309513101
}
1309613102
}
1309713103

13104+
if (CI.getParsedKind() == ParsedAttr::AT_IntelFPGAPrivateCopies) {
13105+
if (!D->hasAttr<IntelFPGAMemoryAttr>())
13106+
D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
13107+
Context, IntelFPGAMemoryAttr::Default));
13108+
}
13109+
1309813110
D->addAttr(::new (Context) AttrType(Context, CI, E));
1309913111
}
1310013112

@@ -13130,10 +13142,9 @@ static Expr *checkMaxWorkSizeAttrExpr(Sema &S, const AttributeCommonInfo &CI,
1313013142
}
1313113143

1313213144
template <typename WorkGroupAttrType>
13133-
void Sema::addIntelSYCLTripleArgFunctionAttr(Decl *D,
13134-
const AttributeCommonInfo &CI,
13135-
Expr *XDimExpr, Expr *YDimExpr,
13136-
Expr *ZDimExpr) {
13145+
void Sema::addIntelTripleArgAttr(Decl *D, const AttributeCommonInfo &CI,
13146+
Expr *XDimExpr, Expr *YDimExpr,
13147+
Expr *ZDimExpr) {
1313713148

1313813149
assert((XDimExpr && YDimExpr && ZDimExpr) &&
1313913150
"argument has unexpected null value");
@@ -13166,13 +13177,6 @@ void Sema::AddOneConstantValueAttr(Decl *D, const AttributeCommonInfo &CI,
1316613177
return;
1316713178
E = ICE.get();
1316813179
}
13169-
13170-
if (IntelFPGAPrivateCopiesAttr::classof(&TmpAttr)) {
13171-
if (!D->hasAttr<IntelFPGAMemoryAttr>())
13172-
D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
13173-
Context, IntelFPGAMemoryAttr::Default));
13174-
}
13175-
1317613180
D->addAttr(::new (Context) AttrType(Context, CI, E));
1317713181
}
1317813182

@@ -13183,12 +13187,15 @@ void Sema::AddOneConstantPowerTwoValueAttr(Decl *D,
1318313187
AttrType TmpAttr(Context, CI, E);
1318413188

1318513189
if (!E->isValueDependent()) {
13186-
ExprResult ICE;
13187-
if (checkRangedIntegralArgument<AttrType>(E, &TmpAttr, ICE))
13190+
llvm::APSInt Value;
13191+
ExprResult ICE = VerifyIntegerConstantExpression(E, &Value);
13192+
if (ICE.isInvalid())
1318813193
return;
13189-
Expr::EvalResult Result;
13190-
E->EvaluateAsInt(Result, Context);
13191-
llvm::APSInt Value = Result.Val.getInt();
13194+
if (!Value.isStrictlyPositive()) {
13195+
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
13196+
<< CI << /*positive*/ 0;
13197+
return;
13198+
}
1319213199
if (!Value.isPowerOf2()) {
1319313200
Diag(CI.getLoc(), diag::err_attribute_argument_not_power_of_two)
1319413201
<< &TmpAttr;

‎clang/lib/CodeGen/CodeGenModule.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6037,6 +6037,9 @@ void CodeGenModule::EmitTopLevelDecl(Decl *D) {
60376037
// File-scope asm is ignored during device-side OpenMP compilation.
60386038
if (LangOpts.OpenMPIsDevice)
60396039
break;
6040+
// File-scope asm is ignored during device-side SYCL compilation.
6041+
if (LangOpts.SYCLIsDevice)
6042+
break;
60406043
auto *AD = cast<FileScopeAsmDecl>(D);
60416044
getModule().appendModuleInlineAsm(AD->getAsmString()->getString());
60426045
break;

‎clang/lib/Driver/Action.cpp

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,6 @@ const char *Action::getClassName(ActionClass AC) {
5151
return "llvm-no-spir-kernel";
5252
case SYCLPostLinkJobClass:
5353
return "sycl-post-link";
54-
case PartialLinkJobClass:
55-
return "partial-link";
5654
case BackendCompileJobClass:
5755
return "backend-compiler";
5856
case FileTableTformJobClass:
@@ -477,14 +475,6 @@ void SYCLPostLinkJobAction::anchor() {}
477475
SYCLPostLinkJobAction::SYCLPostLinkJobAction(Action *Input, types::ID Type)
478476
: JobAction(SYCLPostLinkJobClass, Input, Type) {}
479477

480-
void PartialLinkJobAction::anchor() {}
481-
482-
PartialLinkJobAction::PartialLinkJobAction(Action *Input, types::ID Type)
483-
: JobAction(PartialLinkJobClass, Input, Type) {}
484-
485-
PartialLinkJobAction::PartialLinkJobAction(ActionList &Inputs, types::ID Type)
486-
: JobAction(PartialLinkJobClass, Inputs, Type) {}
487-
488478
void BackendCompileJobAction::anchor() {}
489479

490480
BackendCompileJobAction::BackendCompileJobAction(ActionList &Inputs,

‎clang/lib/Driver/ToolChain.cpp

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -354,12 +354,6 @@ Tool *ToolChain::getSYCLPostLink() const {
354354
return SYCLPostLink.get();
355355
}
356356

357-
Tool *ToolChain::getPartialLink() const {
358-
if (!PartialLink)
359-
PartialLink.reset(new tools::PartialLink(*this));
360-
return PartialLink.get();
361-
}
362-
363357
Tool *ToolChain::getBackendCompiler() const {
364358
if (!BackendCompiler)
365359
BackendCompiler.reset(buildBackendCompiler());
@@ -423,9 +417,6 @@ Tool *ToolChain::getTool(Action::ActionClass AC) const {
423417
case Action::SYCLPostLinkJobClass:
424418
return getSYCLPostLink();
425419

426-
case Action::PartialLinkJobClass:
427-
return getPartialLink();
428-
429420
case Action::BackendCompileJobClass:
430421
return getBackendCompiler();
431422

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 0 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -8417,54 +8417,3 @@ void FileTableTform::ConstructJob(Compilation &C, const JobAction &JA,
84178417
TCArgs.MakeArgString(getToolChain().GetProgramPath(getShortName())),
84188418
CmdArgs, Inputs));
84198419
}
8420-
8421-
// For Linux, we have initial support for fat archives (archives which
8422-
// contain bundled objects). We will perform partial linking against the
8423-
// specific offload target archives which will be sent to the unbundler to
8424-
// produce a list of target objects.
8425-
void PartialLink::ConstructJob(Compilation &C, const JobAction &JA,
8426-
const InputInfo &Output,
8427-
const InputInfoList &Inputs,
8428-
const llvm::opt::ArgList &TCArgs,
8429-
const char *LinkingOutput) const {
8430-
// Construct simple partial link command.
8431-
assert(isa<PartialLinkJobAction>(JA) && "Expecting Partial Link job!");
8432-
8433-
// The partial linking command resembles this:
8434-
// ld -r -o <output> <inputs>
8435-
ArgStringList LinkArgs;
8436-
LinkArgs.push_back("-r");
8437-
LinkArgs.push_back("-o");
8438-
LinkArgs.push_back(Output.getFilename());
8439-
8440-
const ToolChain *HTC = C.getSingleOffloadToolChain<Action::OFK_Host>();
8441-
// Add crt objects
8442-
LinkArgs.push_back(TCArgs.MakeArgString(HTC->GetFilePath("crt1.o")));
8443-
LinkArgs.push_back(TCArgs.MakeArgString(HTC->GetFilePath("crti.o")));
8444-
// Add -L<dir> search directories.
8445-
TCArgs.AddAllArgs(LinkArgs, options::OPT_L);
8446-
HTC->AddFilePathLibArgs(TCArgs, LinkArgs);
8447-
8448-
// Input files consist of fat libraries and the object(s) to be unbundled.
8449-
// We add the needed --whole-archive/--no-whole-archive when appropriate.
8450-
bool IsWholeArchive = false;
8451-
for (const auto &I : Inputs) {
8452-
if (I.getType() == types::TY_WholeArchive && !IsWholeArchive) {
8453-
LinkArgs.push_back("--whole-archive");
8454-
IsWholeArchive = true;
8455-
} else if (I.getType() == types::TY_Archive && IsWholeArchive) {
8456-
LinkArgs.push_back("--no-whole-archive");
8457-
IsWholeArchive = false;
8458-
}
8459-
LinkArgs.push_back(I.getFilename());
8460-
}
8461-
// Disable whole archive if it was enabled for the previous inputs.
8462-
if (IsWholeArchive)
8463-
LinkArgs.push_back("--no-whole-archive");
8464-
8465-
// Add crt objects
8466-
LinkArgs.push_back(TCArgs.MakeArgString(HTC->GetFilePath("crtn.o")));
8467-
const char *Exec = TCArgs.MakeArgString(getToolChain().GetLinkerPath());
8468-
C.addCommand(std::make_unique<Command>(
8469-
JA, *this, ResponseFileSupport::AtFileCurCP(), Exec, LinkArgs, Inputs));
8470-
}

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