Merge branch 'sycl' into victor/kernel-fusion-amd

Author: Naghasan

.github/CODEOWNERS

@@ -70,6 +70,7 @@ llvm/test/Transforms/SPMDTransforms/ @intel/ocl-cpu-rt-write
 clang/**/OffloadBundler.h @intel/dpcpp-tools-reviewers
 clang/**/OffloadBundler.cpp @intel/dpcpp-tools-reviewers
 clang/tools/clang-offload-*/ @intel/dpcpp-tools-reviewers
+clang/tools/clang-linker-wrapper/ @intel/dpcpp-tools-reviewers
 
 # Explicit SIMD
 ESIMD/ @intel/dpcpp-esimd-reviewers

.github/new-issues-labeler.yml

@@ -1,6 +1,3 @@
-'new issue':
-  - '/.*/'
-
 'clang':
   - '/\bclang(?!\-)\b/i'
 

.github/new-prs-labeler.yml

@@ -110,16 +110,26 @@ mlir:
   - mlir/**
 
 mlir:core:
-  - mlir/**/Support/**
-  - mlir/**/Parser/**
-  - mlir/**/IR/**
-  - mlir/**/Bytecode/**
-  - mlir/**/AsmParser/**
-  - mlir/**/Pass/**
-  - mlir/**/tools/**
-  - mlir/**/Reducer/**
-  - mlir/**/Transforms/**
-  - mlir/**/Debug/**
+  - mlir/include/mlir/Support/**
+  - mlir/lib/Support/**
+  - mlir/include/mlir/Parser/**
+  - mlir/lib/Parser/**
+  - mlir/include/mlir/IR/**
+  - mlir/lib/IR/**
+  - mlir/include/mlir/Bytecode/**
+  - mlir/lib/Bytecode/**
+  - mlir/include/mlir/AsmParser/**
+  - mlir/lib/AsmParser/**
+  - mlir/include/mlir/Pass/**
+  - mlir/lib/Pass/**
+  - mlir/include/mlir/Tools/**
+  - mlir/lib/Tools/**
+  - mlir/include/mlir/Reducer/**
+  - mlir/lib/Reducer/**
+  - mlir/include/mlir/Transforms/**
+  - mlir/lib/Transforms/**
+  - mlir/include/mlir/Debug/**
+  - mlir/lib/Debug/**
   - mlir/tools/**
 
 mlir:ods:
@@ -222,6 +232,11 @@ mlir:scf:
 
 mlir:spirv:
   - mlir/**/SPIRV/**
+  - mlir/**/SPIRVTo*/**
+  - mlir/**/*ToSPIRV/**
+  - mlir/tools/mlir-spirv-cpu-runner/**
+  - mlir/tools/mlir-vulkan-runner/**
+  - mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
 
 mlir:shape:
   - mlir/**/Shape/**
@@ -295,7 +310,10 @@ vectorizers:
   - llvm/include/llvm/Transforms/Vectorize/**
 
 clang:
-  - clang/**
+  - any:
+    - clang/**
+    - '!clang/**/Format/**'
+    - '!clang/tools/clang-format/**'
 
 testing-tools:
   - llvm/include/llvm/FileCheck/**
@@ -362,6 +380,11 @@ debuginfo:
 github:workflow:
   - .github/workflows/**
 
+cmake:
+  - cmake/**
+  - llvm/cmake/**
+  - runtimes/**
+
 flang:driver:
   - flang/tools/flang-driver/**
   - flang/unittests/Frontend/**
@@ -381,15 +404,12 @@ backend:m68k:
 
 libc++:
   - libcxx/**
-  - runtimes/**
 
 libc++abi:
   - libcxxabi/**
-  - runtimes/**
 
 libunwind:
   - libunwind/**
-  - runtimes/**
 
 objectyaml:
   - llvm/include/llvm/ObjectYAML/**
@@ -503,6 +523,12 @@ llvm:analysis:
   - llvm/test/Analysis/**
   - llvm/unittests/Analysis/**
 
+llvm:adt:
+  - llvm/**/ADT/*
+
+llvm:support:
+  - llvm/**/Support/**
+
 llvm:transforms:
   - llvm/lib/Transforms/**
   - llvm/include/llvm/Transforms/**
@@ -540,12 +566,19 @@ llvm:SelectionDAG:
   - llvm/include/llvm/CodeGen/ISDOpcodes.h
 
 backend:DirectX:
-  - llvm/lib/Target/DirectX/**
-  - llvm/test/CodeGen/DirectX/**
-  - llvm/tools/dxil-dis
-  - llvm/test/tools/dxil-dis
-  - clang/lib/Basic/Targets/DirectX*
-  - llvm/include/llvm/IR/IntrinsicsDirectX.td
+  - '**/*DirectX*'
+  - '**/*DXIL*'
+  - '**/*dxil*'
+  - '**/*DirectX*/**'
+  - '**/*DXIL*/**'
+  - '**/*dxil*/**'
+
+backend:SPIR-V:
+  - clang/lib/Driver/ToolChains/SPIRV.*
+  - llvm/lib/Target/SPIRV/**
+  - llvm/test/CodeGen/SPIRV/**
+  - llvm/test/Frontend/HLSL/**
+  - llvm/docs/SPIRVUsage.rst
 
 mlgo:
   - llvm/lib/Analysis/ML*

.github/workflows/issue-release-workflow.yml

@@ -70,7 +70,7 @@ jobs:
     if: >-
       (github.repository == 'llvm/llvm-project') &&
       !startswith(github.event.comment.body, '<!--IGNORE-->') &&
-      contains(github.event.comment.body, '/branch')
+      contains(github.event.comment.body, '/branch ')
 
     steps:
       - name: Fetch LLVM sources

.github/workflows/new-issues.yml

@@ -13,7 +13,7 @@ jobs:
     runs-on: ubuntu-latest
     if: github.repository == 'llvm/llvm-project'
     steps:
-      - uses: github/issue-labeler@v3.2
+      - uses: llvm/actions/issue-labeler@main
         with:
           repo-token: ${{ secrets.GITHUB_TOKEN }}
           configuration-path: .github/new-issues-labeler.yml

.github/workflows/pr-receive.yml

@@ -10,7 +10,12 @@ permissions:
 jobs:
   pr-target:
     runs-on: ubuntu-latest
-    if: github.repository == 'llvm/llvm-project'
+    # Ignore PRs with more than 10 commits.  Pull requests with a lot of
+    # commits tend to be accidents usually when someone made a mistake while trying
+    # to rebase.  We want to ignore these pull requests to avoid excessive
+    # notifications.
+    if: github.repository == 'llvm/llvm-project' &&
+        github.event.pull_request.commits < 10
     steps:
       - name: Store PR Information
         run: |

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -170,6 +170,7 @@ class MCPlusBuilder {
   /// MCPlusBuilder classes must use convert/lower/create* interfaces instead.
   void setTailCall(MCInst &Inst);
 
+public:
   /// Transfer annotations from \p SrcInst to \p DstInst.
   void moveAnnotations(MCInst &&SrcInst, MCInst &DstInst) const {
     assert(!getAnnotationInst(DstInst) &&
@@ -182,7 +183,6 @@ class MCPlusBuilder {
     removeAnnotationInst(SrcInst);
   }
 
-public:
   /// Return iterator range covering def operands.
   iterator_range<MCInst::iterator> defOperands(MCInst &Inst) const {
     return make_range(Inst.begin(),
@@ -437,7 +437,7 @@ class MCPlusBuilder {
   virtual bool isUnsupportedBranch(const MCInst &Inst) const { return false; }
 
   /// Return true of the instruction is of pseudo kind.
-  bool isPseudo(const MCInst &Inst) const {
+  virtual bool isPseudo(const MCInst &Inst) const {
     return Info->get(Inst.getOpcode()).isPseudo();
   }
 

bolt/include/bolt/Passes/FixRISCVCallsPass.h

@@ -6,9 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the FixRISCVCallsPass class, which sets the JALR immediate
-// to 0 for AUIPC/JALR pairs with a R_RISCV_CALL(_PLT) relocation. This is
-// necessary since MC expects it to be zero in order to or-in fixups.
+// This file declares the FixRISCVCallsPass class, which replaces all types of
+// calls with PseudoCALL pseudo instructions. This ensures that relaxed calls
+// get expanded to auipc/jalr pairs so that BOLT can freely reassign function
+// addresses without having to worry about the limited range of relaxed calls.
+// Using PseudoCALL also ensures that the RISC-V backend inserts the necessary
+// relaxation-related relocations to allow JITLink to relax instruction back to
+// shorter versions where possible.
 //===----------------------------------------------------------------------===//
 
 #ifndef BOLT_PASSES_FIXRISCVCALLSPASS_H

bolt/lib/Core/BinaryContext.cpp

@@ -131,7 +131,7 @@ BinaryContext::createBinaryContext(const ObjectFile *File, bool IsPIC,
   case llvm::Triple::riscv64:
     ArchName = "riscv64";
     // RV64GC
-    FeaturesStr = "+m,+a,+f,+d,+zicsr,+zifencei,+c";
+    FeaturesStr = "+m,+a,+f,+d,+zicsr,+zifencei,+c,+relax";
     break;
   default:
     return createStringError(std::errc::not_supported,

bolt/lib/Core/BinaryFunction.cpp

@@ -3156,6 +3156,10 @@ void BinaryFunction::dumpGraphToFile(std::string Filename) const {
 }
 
 bool BinaryFunction::validateCFG() const {
+  // Skip the validation of CFG after it is finalized
+  if (CurrentState == State::CFG_Finalized)
+    return true;
+
   bool Valid = true;
   for (BinaryBasicBlock *BB : BasicBlocks)
     Valid &= BB->validateSuccessorInvariants();