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[SYCL] [FPGA] Create latency control E2E emulator tests #596
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/verify with intel/llvm#5066 |
MrSidims
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Dec 6, 2021
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/verify with intel/llvm#5066 |
romanovvlad
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…5066) Create experimental header files that provide user API for FPGA latency control feature. experimental/fpga_lsu.hpp and experimental/pipes.hpp are simply the original version plus latency control API described in the extension documents. experimental/fpga_utils.hpp provides utility functions used by experimental LSU and pipe headers. fpga_extensions.hpp will include new experimental LSU and pipe headers. Related PR for extension documents: #5027 Test: intel/llvm-test-suite#596
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@romanovvlad Could you please review and merge? |
I cannot merge, the pre-commit fails, maybe @vladimirlaz can help. |
vladimirlaz
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Dec 13, 2021
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@romanovvlad your approve is needed to enable merge button. CI failure should not block merge. |
romanovvlad
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Dec 14, 2021
Co-authored-by: Romanov Vlad <vlad.romanov@intel.com>
shuoniu-intel
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romanovvlad
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vladimirlaz
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aelovikov-intel
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Create E2E emulator tests for newly added latency control headers.
The corresponding SYCL PR: intel/llvm#5066