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YuriPlyakhinigcbot
YuriPlyakhin
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igcbot
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More lit tests for memory optimizations
Improve code coverage for Predicated Memory optimizations in Memory Optimization passes: MemOpt2, AdvMemOpt, and PrepareLoadsStoresPass.
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‎IGC/Compiler/CISACodeGen/MemOpt2.h

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@@ -37,10 +37,6 @@ class MemInstCluster {
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MemInstCluster() {}
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~MemInstCluster() {}
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MemInstCluster(IGC::CodeGenContext *pCTX, const DataLayout *pDL,
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AliasAnalysis *pAA, TargetLibraryInfo* pTLI, unsigned MLT) {
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init(pCTX, pDL, pAA, pTLI, MLT);
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}
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void init(IGC::CodeGenContext *pCTX, const DataLayout *pDL,
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AliasAnalysis *pAA, TargetLibraryInfo* pTLI, unsigned MLT) {
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CTX = pCTX;

‎IGC/Compiler/tests/AdvMemOpt/basic-predicated-break.ll

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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;
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; RUN: igc_opt --typed-pointers -igc-advmemopt -S < %s 2>&1 | FileCheck %s
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; ------------------------------------------------
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; AdvMemOpt - checks early exit due to memory writes
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; ------------------------------------------------
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; CHECK-LABEL: @test(
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; CHECK: bb:
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; CHECK: call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* [[B:%[A-z0-9]*]], i64 4, i1 true, i32 42){{.*}}, !uniform [[TRUE_MD:![0-9]*]]
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; CHECK-NEXT: br label %bb1
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; CHECK: bb1:
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; CHECK-NEXT: store i32 0, i32* [[B]], align 4
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; CHECK-NEXT: call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* [[B]], i64 4, i1 true, i32 43){{.*}}, !uniform [[TRUE_MD]]
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; CHECK: ret void
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define void @test(i32 %a, i32* %b) {
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entry:
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%0 = icmp slt i32 %a, 13
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br i1 %0, label %bb, label %end
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bb:
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%1 = phi i32 [ 0, %entry ], [ %3, %bb1 ]
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%2 = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* %b, i64 4, i1 true, i32 42), !uniform !4
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br label %bb1
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bb1:
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store i32 0, i32* %b, align 4
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%c = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* %b, i64 4, i1 true, i32 43), !uniform !4
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%3 = add i32 %1, %2
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%4 = add i32 %c, %3
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%5 = icmp slt i32 %3, %a
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br i1 %5, label %bb, label %end
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end:
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%6 = phi i32 [ %a, %entry ], [ %4, %bb1 ]
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call void @llvm.genx.GenISA.PredicatedStore.p0i32.i32(i32* %b, i32 %6, i64 4, i1 true)
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ret void
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}
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; Function Attrs: nounwind readonly
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declare i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32*, i64, i1, i32) #0
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declare void @llvm.genx.GenISA.PredicatedStore.p0i32.i32(i32*, i32, i64, i1)
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attributes #0 = { nounwind readonly }
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; CHECK: [[TRUE_MD]] = !{i1 true}
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!igc.functions = !{!0}
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!0 = !{void (i32, i32*)* @test, !1}
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!1 = !{!2, !3}
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!2 = !{!"function_type", i32 0}
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!3 = !{!"implicit_arg_desc"}
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!4 = !{i1 true}

‎IGC/Compiler/tests/AdvMemOpt/basic-predicated-non-uniform.ll

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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;
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; RUN: igc_opt --typed-pointers -igc-advmemopt -S < %s 2>&1 | FileCheck %s
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; ------------------------------------------------
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; AdvMemOpt - check that only uniform load will be hoisted
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; ------------------------------------------------
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; CHECK-LABEL: @test_uniformness(
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; CHECK: bb:
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; CHECK: call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* [[B:%[A-z0-9]*]], i64 4, i1 true, i32 42){{.*}}
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; CHECK-NEXT: call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* [[B]], i64 4, i1 true, i32 43){{.*}}
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; CHECK-NEXT: br label %bb1
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; CHECK: bb1:
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; CHECK: [[ARRAYIDX1:%[A-z0-9]*]] = getelementptr inbounds i32, i32* [[B]], i64
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; CHECK-NEXT: call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* [[ARRAYIDX1]], i64 4, i1 true, i32 44){{.*}}
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; CHECK: ret void
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define spir_kernel void @test_uniformness(i32* %b, i32 %a, float addrspace(1)* %sf, i16 %localIdX, i16 %localIdY, i16 %localIdZ) {
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entry:
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%conv.i.i = zext i16 %localIdX to i64
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%0 = icmp slt i32 %a, 13
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br i1 %0, label %bb, label %end
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bb: ; preds = %bb1, %entry
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%1 = phi i32 [ 0, %entry ], [ %3, %bb1 ]
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%2 = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* %b, i64 4, i1 true, i32 42)
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br label %bb1
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bb1: ; preds = %bb
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%arrayidx1 = getelementptr inbounds i32, i32* %b, i64 %conv.i.i
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%cnu = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* %arrayidx1, i64 4, i1 true, i32 44)
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%c = call i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32* %b, i64 4, i1 true, i32 43)
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%3 = add i32 %1, %2
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%4 = add i32 %c, %3
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%5 = icmp slt i32 %3, %a
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br i1 %5, label %bb, label %end
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end: ; preds = %bb1, %entry
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%6 = phi i32 [ %a, %entry ], [ %4, %bb1 ]
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call void @llvm.genx.GenISA.PredicatedStore.p0i32.i32(i32* %b, i32 %6, i64 4, i1 true)
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ret void
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}
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; Function Attrs: nounwind readonly
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declare i32 @llvm.genx.GenISA.PredicatedLoad.i32.p0i32.i32(i32*, i64, i1, i32) #0
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declare void @llvm.genx.GenISA.PredicatedStore.p0i32.i32(i32*, i32, i64, i1)
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attributes #0 = { nounwind readonly }
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!IGCMetadata = !{!0}
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!igc.functions = !{!347}
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!0 = !{!"ModuleMD", !78}
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!78 = !{!"FuncMD", !79, !80}
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!79 = !{!"FuncMDMap[0]", void (i32*, i32, float addrspace(1)*, i16, i16, i16)* @test_uniformness}
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!80 = !{!"FuncMDValue[0]", !87, !114, !166}
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!87 = !{!"functionType", !"KernelFunction"}
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!114 = !{!"resAllocMD", !115, !116, !117, !118, !134}
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!115 = !{!"uavsNumType", i32 3}
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!116 = !{!"srvsNumType", i32 0}
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!117 = !{!"samplersNumType", i32 0}
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!118 = !{!"argAllocMDList", !119, !123, !125, !127, !130, !131, !132, !133}
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!119 = !{!"argAllocMDListVec[0]", !120, !121, !122}
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!120 = !{!"type", i32 1}
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!121 = !{!"extensionType", i32 -1}
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!122 = !{!"indexType", i32 0}
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!123 = !{!"argAllocMDListVec[1]", !120, !121, !124}
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!124 = !{!"indexType", i32 1}
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!125 = !{!"argAllocMDListVec[2]", !120, !121, !126}
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!126 = !{!"indexType", i32 2}
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!127 = !{!"argAllocMDListVec[3]", !128, !121, !129}
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!128 = !{!"type", i32 0}
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!129 = !{!"indexType", i32 -1}
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!130 = !{!"argAllocMDListVec[4]", !128, !121, !129}
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!131 = !{!"argAllocMDListVec[5]", !128, !121, !129}
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!132 = !{!"argAllocMDListVec[6]", !128, !121, !129}
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!133 = !{!"argAllocMDListVec[7]", !128, !121, !129}
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!134 = !{!"inlineSamplersMD"}
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!166 = !{!"m_OpenCLArgTypeQualifiers", !167, !168, !169}
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!167 = !{!"m_OpenCLArgTypeQualifiersVec[0]", !""}
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!168 = !{!"m_OpenCLArgTypeQualifiersVec[1]", !""}
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!169 = !{!"m_OpenCLArgTypeQualifiersVec[2]", !""}
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!347 = !{void (i32*, i32, float addrspace(1)*, i16, i16, i16)* @test_uniformness, !348}
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!348 = !{!349, !350}
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!349 = !{!"function_type", i32 0}
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!350 = !{!"implicit_arg_desc", !351, !352, !353, !354, !355}
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!351 = !{i32 0}
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!352 = !{i32 1}
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!353 = !{i32 8}
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!354 = !{i32 9}
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!355 = !{i32 10}

‎IGC/Compiler/tests/AdvMemOpt/basic-predicated.ll

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@@ -1,6 +1,6 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2022 Intel Corporation
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;

‎IGC/Compiler/tests/PeepholeTypeLegalizer/must-legalize-scratch.ll

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; Test verifies EnableScratchMessageD64WA flag
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; REQUIRES: regkeys
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; RUN: igc_opt --typed-pointers --regkey EnableScratchMessageD64WA=1 -igc-int-type-legalizer -S %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
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define void @src(i64* %in, i64* %out) {
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%a = load i64, i64* %in, align 8
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store i64 %a, i64* %out, align 8
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ret void
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}
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; CHECK-LABEL: define void @src(
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; CHECK: load <2 x i32>, <2 x i32>
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; CHECK: store <2 x i32>

‎IGC/Compiler/tests/PrepareLoadsStores/basic-predicated.ll

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@@ -75,3 +75,18 @@ define void @test_store_v2i64(<2 x i64> addrspace(1)* %a, <2 x i64> %b) {
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declare void @llvm.genx.GenISA.PredicatedStore.p1i64.i64(i64 addrspace(1)*, i64, i64, i1)
7777
declare void @llvm.genx.GenISA.PredicatedStore.p1v2i64.v2i64(<2 x i64> addrspace(1)*, <2 x i64>, i64, i1)
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; Verify that no transformations are applied to the aggregate type
80+
define void @test_load_aggregate({i64, i64} addrspace(1)* %a) {
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; CHECK-LABEL: @test_load_aggregate
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; CHECK: call { i64, i64 } @llvm.genx.GenISA.PredicatedLoad.s.p1s.s({ i64, i64 } addrspace(1)* %a, i64 8, i1 true, { i64, i64 } { i64 3, i64 4 })
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; CHECK: call void @llvm.genx.GenISA.PredicatedStore.p1s.s({ i64, i64 } addrspace(1)* %a, { i64, i64 }
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; CHECK: ret void
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;
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%1 = call { i64, i64 } @llvm.genx.GenISA.PredicatedLoad.s.p1s.s({ i64, i64 } addrspace(1)* %a, i64 8, i1 true, { i64, i64 } { i64 3, i64 4 })
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call void @llvm.genx.GenISA.PredicatedStore.p1s.s({ i64, i64 } addrspace(1)* %a, { i64, i64 } %1, i64 8, i1 true)
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ret void
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}
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declare { i64, i64 } @llvm.genx.GenISA.PredicatedLoad.s.p1s.s({ i64, i64 } addrspace(1)*, i64, i1, { i64, i64 }) #0
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declare void @llvm.genx.GenISA.PredicatedStore.p1s.s({ i64, i64 } addrspace(1)*, { i64, i64 }, i64, i1)

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