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6 | 6 | ;
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7 | 7 | ;============================ end_copyright_notice =============================
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8 | 8 |
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9 |
| -; RUN: igc_opt --typed-pointers %s -S -o - -igc-constant-coalescing -instcombine -dce | FileCheck %s --check-prefixes=CHECK,%LLVM_DEPENDENT_CHECK_PREFIX% |
| 9 | +; RUN: igc_opt --typed-pointers %s -S -o - -igc-constant-coalescing -instcombine -dce | FileCheck %s |
10 | 10 |
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11 | 11 | target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f80:128:128-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a:64:64-f80:128:128-n8:16:32:64"
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12 | 12 |
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@@ -91,14 +91,12 @@ exitBB:
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91 | 91 |
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92 | 92 | ; CHECK-LABEL: define <4 x float> @f2
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93 | 93 | ; CHECK: %1 = call <1 x float> @llvm.genx.GenISA.ldrawvector.indexed.v1f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %src, i32 4, i1 false)
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94 |
| - ; CHECK-LLVM-14: %2 = extractelement <1 x float> %1, {{i[0-9]+}} 0 |
95 |
| - ; CHECK-LLVM-15: %2 = extractelement <1 x float> %1, {{i[0-9]+}} 0 |
| 94 | + ; CHECK: %2 = extractelement <1 x float> %1, {{i[0-9]+}} 0 |
96 | 95 | ; CHECK: br label %storeBB
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97 | 96 | ; CHECK-LABEL: storeBB:
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98 | 97 | ; CHECK: call void @llvm.genx.GenISA.storeraw.indexed.p2490368i8.f32(i8 addrspace(2490373)* %0, i32 %src, float 0.000000e+00, i32 4, i1 false)
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99 | 98 | ; CHECK: br label %exitBB
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100 | 99 | ; CHECK-LABEL: exitBB:
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101 |
| - ; CHECK-LLVM-16: %2 = extractelement <1 x float> %1, {{i[0-9]+}} 0 |
102 | 100 | ; CHECK: %3 = add i32 %src, 4
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103 | 101 | ; CHECK: %4 = call <16 x float> @llvm.genx.GenISA.ldrawvector.indexed.v16f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %3, i32 4, i1 false)
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104 | 102 | ; CHECK: %5 = extractelement <16 x float> %4, {{i[0-9]+}} 11
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