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6 | 6 | //
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7 | 7 | //===----------------------------------------------------------------------===//
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8 | 8 |
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| 9 | +#include "gc/Analysis/TargetDescriptionAnalysis.h" |
9 | 10 | #include "gc/Transforms/Passes.h"
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10 | 11 | #include "mlir/Analysis/TopologicalSortUtils.h"
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11 | 12 | #include "mlir/Dialect/DLTI/Traits.h"
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@@ -579,62 +580,6 @@ static LogicalResult isSelfTiledOp(Operation *targetOp) {
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579 | 580 | return success(walkResult.wasInterrupted());
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580 | 581 | }
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581 | 582 |
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582 |
| -struct SystemDesc { |
583 |
| - // get runtime OMP_NUM_THREADS |
584 |
| - uint32_t getNumThreads() { |
585 |
| - std::optional<Attribute> numThreads = layout.getDevicePropertyValue( |
586 |
| - Builder(ctx).getStringAttr("CPU" /* device ID*/), |
587 |
| - Builder(ctx).getStringAttr("num_threads")); |
588 |
| - if (numThreads && isa<IntegerAttr>(*numThreads)) { |
589 |
| - return dyn_cast<IntegerAttr>(*numThreads).getInt(); |
590 |
| - } |
591 |
| - return 1; |
592 |
| - } |
593 |
| - // get cache size by cacheLevel |
594 |
| - size_t getCacheSize(uint8_t cacheLevel) { |
595 |
| - if (cacheLevel == 1) { |
596 |
| - std::optional<Attribute> cacheSize = layout.getDevicePropertyValue( |
597 |
| - Builder(ctx).getStringAttr("CPU" /* device ID*/), |
598 |
| - Builder(ctx).getStringAttr("L1_cache_size_in_bytes")); |
599 |
| - if (cacheSize && isa<IntegerAttr>(*cacheSize)) { |
600 |
| - return dyn_cast<IntegerAttr>(*cacheSize).getInt(); |
601 |
| - } |
602 |
| - } else if (cacheLevel == 2) { |
603 |
| - std::optional<Attribute> cacheSize = layout.getDevicePropertyValue( |
604 |
| - Builder(ctx).getStringAttr("CPU" /* device ID*/), |
605 |
| - Builder(ctx).getStringAttr("L2_cache_size_in_bytes")); |
606 |
| - if (cacheSize && isa<IntegerAttr>(*cacheSize)) { |
607 |
| - return dyn_cast<IntegerAttr>(*cacheSize).getInt(); |
608 |
| - } |
609 |
| - } else if (cacheLevel == 3) { |
610 |
| - std::optional<Attribute> cacheSize = layout.getDevicePropertyValue( |
611 |
| - Builder(ctx).getStringAttr("CPU" /* device ID*/), |
612 |
| - Builder(ctx).getStringAttr("L3_cache_size_in_bytes")); |
613 |
| - if (cacheSize && isa<IntegerAttr>(*cacheSize)) { |
614 |
| - return dyn_cast<IntegerAttr>(*cacheSize).getInt(); |
615 |
| - } |
616 |
| - } |
617 |
| - return 0; |
618 |
| - } |
619 |
| - |
620 |
| - // get the maximum vector length in bits |
621 |
| - size_t getMaxVectorLength() { |
622 |
| - std::optional<Attribute> maxVectorLength = layout.getDevicePropertyValue( |
623 |
| - Builder(ctx).getStringAttr("CPU" /* device ID*/), |
624 |
| - Builder(ctx).getStringAttr("max_vector_width")); |
625 |
| - if (maxVectorLength && isa<IntegerAttr>(*maxVectorLength)) { |
626 |
| - return dyn_cast<IntegerAttr>(*maxVectorLength).getInt(); |
627 |
| - } |
628 |
| - return 512; |
629 |
| - } |
630 |
| - |
631 |
| - SystemDesc(ModuleOp m) : layout(m), ctx(m->getContext()) {} |
632 |
| - |
633 |
| -private: |
634 |
| - DataLayout layout; |
635 |
| - MLIRContext *ctx; |
636 |
| -}; |
637 |
| - |
638 | 583 | using OpTileSizeMap = std::unordered_map<std::string, SmallVector<int64_t>>;
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639 | 584 |
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640 | 585 | template <typename OpTy>
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@@ -806,7 +751,8 @@ struct IterativeTilingAndFusion
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806 | 751 | // Get funcOp
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807 | 752 | func::FuncOp func = getOperation();
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808 | 753 | // Get system descriptor
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809 |
| - SystemDesc sysDesc(func->getParentOfType<ModuleOp>()); |
| 754 | + CPUTargetDescriptionAnalysis sysDesc = |
| 755 | + getAnalysis<CPUTargetDescriptionAnalysis>(); |
810 | 756 | // Flexible options to control which candidate slice would be selected from
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811 | 757 | // the view of both validity and performance.
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812 | 758 | CandidateSliceOptions sliceOptions;
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