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WW7'22 source code update [7baca577]
Fix IPLDT hits and copyright check Fix processing of the first window of exponent in crypto_mb exponent functions Fix AES-CTR skipping last partial block issue Fixed the problem with SM3 MB APIs, that incorrectly process the length of the streaming message fixed SM4 CBC|ECB mode by VS2019 comiler Added missed boundary checks for AES-GCM
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‎.clang-format‎

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#===============================================================================
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# Copyright 2022 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#===============================================================================
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BasedOnStyle: WebKit
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AlignAfterOpenBracket: Align
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AlignConsecutiveAssignments: true
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AlignEscapedNewlines: Left
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AlignOperands: true
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AlignTrailingComments: true
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AllowAllParametersOfDeclarationOnNextLine: false
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BinPackArguments: false
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BinPackParameters: false
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BreakBeforeBinaryOperators: None
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ColumnLimit: 150
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ContinuationIndentWidth: 3
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IndentWidth: 3
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MaxEmptyLinesToKeep: 3
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PointerAlignment: Right

‎DEPRECATION_NOTES.md‎

Lines changed: 5 additions & 5 deletions
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@@ -23,7 +23,7 @@ The deprecated API means it is obsolete and will be removed in one of future Int
2323
| ippsHashUpdate, ippsHashGetTag,ippsHashFinal | ippsHashUpdate_rmf,ippsHashGetTag_rmf,ippsHashFinal_rmf |
2424
| ippsHashMessage \*\* | ippsHashMessage_rmf \* |
2525

26-
>\* To choose hash algorithm, specify [IppsHashMethod parameter](#ippshashalgid-to-ippshashmethod-parameter-map)
26+
>\* To choose hash algorithm, specify [IppsHashMethod parameter](#ippshashalgid-to-ippshashmethod-parameter-map)
2727
>\*\* IppsHashAlgId parameter used in 'ippsHMAC_Init' and in ippsHMAC_Message for choosing hash algorithm is deprecated (see Recommended replacement column for alternative in [IppsHashAlgId to IppsHashMethod parameter map](#ippshashalgid-to-ippshashmethod-parameter-map)
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2929
### Keyed HMAC Functionality
@@ -36,7 +36,7 @@ The deprecated API means it is obsolete and will be removed in one of future Int
3636
| ippsHMAC_Update, ippsHMAC_Final, ippsHMAC_GetTag | ippsHMAC_Update_rmf, ippsHMAC_Final_rmf, ippsHMAC_GetTag_rmf |
3737
| ippsHMAC_Message \*\* | ippsHMAC_Message_rmf \* |
3838

39-
>\* To choose hash algorithm, specify [IppsHashMethod parameter](#ippshashalgid-to-ippshashmethod-parameter-map)
39+
>\* To choose hash algorithm, specify [IppsHashMethod parameter](#ippshashalgid-to-ippshashmethod-parameter-map)
4040
>\*\* IppsHashAlgId parameter used in 'ippsHMAC_Init' and in ippsHMAC_Message for choosing hash algorithm is deprecated (see Recommended replacement column for alternative in [IppsHashAlgId to IppsHashMethod parameter map](#ippshashalgid-to-ippshashmethod-parameter-map)
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@@ -76,9 +76,9 @@ The deprecated API means it is obsolete and will be removed in one of future Int
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| Algorithm | IppsHashAlgId (deprecated) | IppsHashMethod(recommended) | Note |
7878
| :--------: | :------------------------: | :---------------------------------------------------------------------------: | :--------------------------------------------------------------------------------------------------: |
79-
| SHA1 | ippsHashAlg_SHA1 | ippsHashMethod_SHA1<br>ippsHashMethod_SHA1_NI<br>ippsHashMethod_SHA1_TT | SHA-NI not supported<br>SHA-NI only supported<br>Automatic switch on SHA-NI, if possible (tick-tock) |
80-
| SHA224 | ippsHashAlg_SHA224 | ippsHashMethod_SHA224<br>ippsHashMethod_SHA224_NI<br>ippsHashMethod_SHA224_TT | SHA-NI not supported<br>SHA-NI only supported<br>Automatic switch on SHA-NI, if possible supported |
81-
| SHA256 | ippsHashAlg_SHA256 | ippsHashMethod_SHA256<br>ippsHashMethod_SHA256_NI<br>ippsHashMethod_SHA256_TT | SHA-NI not supported<br>SHA-NI only supported<br>Automatic switch on SHA-NI, if possible supported |
79+
| SHA1 | ippsHashAlg_SHA1 | ippsHashMethod_SHA1<br>ippsHashMethod_SHA1_NI<br>ippsHashMethod_SHA1_TT | Intel® Secure Hash Algorithm - New Instructions (Intel® SHA-NI) not supported<br>Intel SHA-NI only supported<br>Automatic switch on Intel SHA-NI, if possible (tick-tock) |
80+
| SHA224 | ippsHashAlg_SHA224 | ippsHashMethod_SHA224<br>ippsHashMethod_SHA224_NI<br>ippsHashMethod_SHA224_TT | Intel SHA-NI not supported<br>Intel SHA-NI only supported<br>Automatic switch on Intel SHA-NI, if possible supported |
81+
| SHA256 | ippsHashAlg_SHA256 | ippsHashMethod_SHA256<br>ippsHashMethod_SHA256_NI<br>ippsHashMethod_SHA256_TT | Intel SHA-NI not supported<br>Intel SHA-NI only supported<br>Automatic switch on Intel SHA-NI, if possible supported |
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| SHA384 | ippsHashAlg_SHA384 | ippsHashMethod_SHA384 | - |
8383
| SHA512 | ippsHashAgl_SHA512 | ippsHashMethod_SHA512 | - |
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| SM3 | ippsHashAlg_SM3 | ippsHashMethod_SM3 | - |

‎OVERVIEW.md‎

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@@ -96,7 +96,7 @@ List of CPU feature subsets that the library has special optimizations for:
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- Intel ADX (ADCX, ADOX)
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- Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
99-
- Intel SHA-NI
99+
- Intel® Secure Hash Algorithm - New Instructions (Intel® SHA-NI)
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- RDRAND
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- RDSEED
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- CLMUL

‎include/ippcpdefs.h‎

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Original file line numberDiff line numberDiff line change
@@ -337,7 +337,7 @@ typedef enum {
337337
#define ippCPUID_MPX 0x10000000 /* Intel® Memory Protection Extensions */
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#define ippCPUID_AVX512_4FMADDPS 0x20000000 /* Intel® Advanced Vector Extensions 512 DL floating-point single precision */
339339
#define ippCPUID_AVX512_4VNNIW 0x40000000 /* Intel® Advanced Vector Extensions 512 DL enhanced word variable precision */
340-
#define ippCPUID_KNC 0x80000000 /* Intel® Xeon Phi(TM) Coprocessor */
340+
#define ippCPUID_KNC 0x80000000 /* Intel® Xeon® Phi(TM) Coprocessor */
341341
#if defined( _WIN32 ) || defined ( _WIN64 )
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#define INT64_SUFFIX(name) name##L
343343
#else

‎sources/include/dispatcher.h‎

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@@ -14,7 +14,7 @@
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* limitations under the License.
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*******************************************************************************/
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17-
//
17+
//
1818
// Intel® Integrated Performance Primitives Cryptography (Intel® IPP Cryptography)
1919
//
2020

@@ -129,7 +129,7 @@ extern "C" {
129129
#define LIB_SSE42 LIB_P8
130130
#define LIB_AVX LIB_G9
131131
#define LIB_AVX2 LIB_H9
132-
#define LIB_AVX3M LIB_H9 /* no ia32 library for Intel® Xeon Phi(TM) processor (formerly Knight Landing) */
132+
#define LIB_AVX3M LIB_H9 /* no ia32 library for Intel® Xeon® Phi(TM) processor (formerly Knight Landing) */
133133
#define LIB_AVX3X LIB_H9 /* no ia32 library for Intel® Xeon® processor (formerly Skylake) */
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#define LIB_AVX3I LIB_H9 /* no ia32 library for Intel® Xeon® processor (formerly Icelake) */
135135
#else
@@ -143,7 +143,7 @@ extern "C" {
143143
#define LIB_SSE42 LIB_P8
144144
#define LIB_AVX LIB_G9
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#define LIB_AVX2 LIB_H9
146-
#define LIB_AVX3M LIB_H9 /* no ia32 library for Intel® Xeon Phi(TM) processor (formerly Knight Landing) */
146+
#define LIB_AVX3M LIB_H9 /* no ia32 library for Intel® Xeon® Phi(TM) processor (formerly Knight Landing) */
147147
#define LIB_AVX3X LIB_H9 /* no ia32 library for Intel® Xeon® processor (formerly Skylake) */
148148
#define LIB_AVX3I LIB_H9 /* no ia32 library for Intel® Xeon® processor (formerly Icelake) */
149149
#endif

‎sources/include/owndefs.h‎

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@@ -82,29 +82,29 @@
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#endif
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/* ia32 */
85-
#define _IPP_PX 0 /* pure C-code */
86-
#define _IPP_M5 1 /* Intel® Quark(TM) processor */
87-
#define _IPP_W7 8 /* Intel® Streaming SIMD Extensions 2 (Intel® SSE2) */
88-
#define _IPP_T7 16 /* Intel® Streaming SIMD Extensions 3 (Intel® SSE3) */
89-
#define _IPP_V8 32 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) */
90-
#define _IPP_S8 33 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) + MOVBE instruction */
91-
#define _IPP_P8 64 /* Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) */
92-
#define _IPP_G9 128 /* Intel® Advanced Vector Extensions (Intel® AVX) */
93-
#define _IPP_H9 256 /* Intel® Advanced Vector Extensions 2 (Intel® AVX2) */
94-
#define _IPP_I0 512 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon Phi(TM) Processor (formerly Knights Landing) */
95-
#define _IPP_S0 1024 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Processor (formerly codenamed Skylake) */
85+
#define _IPP_PX 0 /* pure C-code */
86+
#define _IPP_M5 1 /* Intel® Quark(TM) processor */
87+
#define _IPP_W7 8 /* Intel® Streaming SIMD Extensions 2 (Intel® SSE2) */
88+
#define _IPP_T7 16 /* Intel® Streaming SIMD Extensions 3 (Intel® SSE3) */
89+
#define _IPP_V8 32 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) */
90+
#define _IPP_S8 33 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) + MOVBE instruction */
91+
#define _IPP_P8 64 /* Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) */
92+
#define _IPP_G9 128 /* Intel® Advanced Vector Extensions (Intel® AVX) */
93+
#define _IPP_H9 256 /* Intel® Advanced Vector Extensions 2 (Intel® AVX2) */
94+
#define _IPP_I0 512 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Phi(TM) Processor (formerly Knights Landing) */
95+
#define _IPP_S0 1024 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Processor (formerly codenamed Skylake) */
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9797
/* intel64 */
98-
#define _IPP32E_PX _IPP_PX /* pure C-code */
99-
#define _IPP32E_M7 32 /* Intel® Streaming SIMD Extensions 3 (Intel® SSE3) */
100-
#define _IPP32E_U8 64 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) */
101-
#define _IPP32E_N8 65 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) + MOVBE instruction */
102-
#define _IPP32E_Y8 128 /* Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) */
103-
#define _IPP32E_E9 256 /* Intel® Advanced Vector Extensions (Intel® AVX) */
104-
#define _IPP32E_L9 512 /* Intel® Advanced Vector Extensions 2 (Intel® AVX2) */
105-
#define _IPP32E_N0 1024 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon Phi(TM) Processor (formerly Knights Landing) */
106-
#define _IPP32E_K0 2048 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Processor (formerly codenamed Skylake) */
107-
#define _IPP32E_K1 4096 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Processor (formerly codenamed Icelake) */
98+
#define _IPP32E_PX _IPP_PX /* pure C-code */
99+
#define _IPP32E_M7 32 /* Intel® Streaming SIMD Extensions 3 (Intel® SSE3) */
100+
#define _IPP32E_U8 64 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) */
101+
#define _IPP32E_N8 65 /* Supplemental Streaming SIMD Extensions 3 (SSSE3) + MOVBE instruction */
102+
#define _IPP32E_Y8 128 /* Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) */
103+
#define _IPP32E_E9 256 /* Intel® Advanced Vector Extensions (Intel® AVX) */
104+
#define _IPP32E_L9 512 /* Intel® Advanced Vector Extensions 2 (Intel® AVX2) */
105+
#define _IPP32E_N0 1024 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Phi(TM) Processor (formerly Knights Landing) */
106+
#define _IPP32E_K0 2048 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Processor (formerly codenamed Skylake) */
107+
#define _IPP32E_K1 4096 /* Intel® Advanced Vector Extensions 512 (Intel® AVX512) - Intel® Xeon® Processor (formerly codenamed Icelake) */
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110110
#if defined(__INTEL_COMPILER) || defined(__INTEL_LLVM_COMPILER) || (_MSC_VER >= 1300)

‎sources/ippcp/aes_cfb_vaes_mb16.c‎

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Original file line numberDiff line numberDiff line change
@@ -119,21 +119,22 @@ IPP_OWN_DEFN(void, aes_cfb16_enc_vaes_mb16, (const Ipp8u* const source_pa[16], I
119119
__mmask8 mbMask128[16] = { 0x03, 0x0C, 0x30, 0xC0, 0x03, 0x0C, 0x30, 0xC0, 0x03, 0x0C, 0x30, 0xC0, 0x03, 0x0C, 0x30, 0xC0 };
120120
__mmask8 mbMask[16] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
121121

122-
// - Local copy of length, soure and target pointers, maxLen calculation
122+
// - Local copy of length, source and target pointers, maxLen calculation
123123
for (i = 0; i < 16; i++) {
124-
loc_src[i] = (Ipp8u*)source_pa[i];
125-
loc_dst[i] = (Ipp8u*)dst_pa[i];
126-
int len64 = arr_len[i] / (Ipp32s)sizeof(Ipp64u); // legth in 64-bit chunks
127-
loc_len64[i] = len64;
128-
129124
// The case of the empty input buffer
130125
if (arr_len[i] == 0)
131126
{
132127
mbMask128[i] = 0;
133-
mbMask[i] = 0;
128+
mbMask[i] = 0;
129+
loc_len64[i] = 0;
134130
continue;
135131
}
136132

133+
loc_src[i] = (Ipp8u*)source_pa[i];
134+
loc_dst[i] = (Ipp8u*)dst_pa[i];
135+
int len64 = arr_len[i] / (Ipp32s)sizeof(Ipp64u); // length in 64-bit chunks
136+
loc_len64[i] = len64;
137+
137138
if (len64 < 8)
138139
mbMask[i] = (__mmask8)(((1 << len64) - 1) & 0xFF);
139140
if (len64 > maxLen)
@@ -165,6 +166,7 @@ IPP_OWN_DEFN(void, aes_cfb16_enc_vaes_mb16, (const Ipp8u* const source_pa[16], I
165166
{
166167
k = 0;
167168
for (j = 0; j < 16; j += 4) {
169+
tmpKeyMb = _mm512_setzero_si512();
168170
tmpKeyMb = _mm512_mask_expandloadu_epi64(tmpKeyMb, mbMask128[j], (const void *)(enc_keys[j] + (Ipp32u)i * sizeof(Ipp32u)));
169171
tmpKeyMb = _mm512_mask_expandloadu_epi64(tmpKeyMb, mbMask128[j + 1], (const void *)(enc_keys[j + 1] + (Ipp32u)i * sizeof(Ipp32u)));
170172
tmpKeyMb = _mm512_mask_expandloadu_epi64(tmpKeyMb, mbMask128[j + 2], (const void *)(enc_keys[j + 2] + (Ipp32u)i * sizeof(Ipp32u)));

‎sources/ippcp/aes_cfb_vaes_mb4.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -63,18 +63,18 @@ IPP_OWN_DEFN (void, aes_cfb16_enc_vaes_mb4, (const Ipp8u* const source_pa[4], Ip
6363
__mmask8 mbMask[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
6464

6565
for (i = 0; i < 4; i++) {
66-
loc_src[i] = (Ipp8u*)source_pa[i];
67-
loc_dst[i] = (Ipp8u*)dst_pa[i];
68-
int len64 = arr_len[i] / (Ipp32s)sizeof(Ipp64u); // legth in 64-bit chunks
69-
loc_len64[i] = len64;
70-
7166
// The case of the empty input buffer
7267
if (arr_len[i] == 0)
7368
{
7469
mbMask128[i] = 0;
75-
mbMask[i] = 0;
70+
mbMask[i] = 0;
71+
loc_len64[i] = 0;
7672
continue;
7773
}
74+
loc_src[i] = (Ipp8u*)source_pa[i];
75+
loc_dst[i] = (Ipp8u*)dst_pa[i];
76+
int len64 = arr_len[i] / (Ipp32s)sizeof(Ipp64u); // length in 64-bit chunks
77+
loc_len64[i] = len64;
7878

7979
if (len64 < 8)
8080
mbMask[i] = (__mmask8)(((1 << len64) - 1) & 0xFF);

‎sources/ippcp/aes_cfb_vaes_mb8.c‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -90,19 +90,20 @@ IPP_OWN_DEFN (void, aes_cfb16_enc_vaes_mb8, (const Ipp8u* const source_pa[8], Ip
9090
__mmask8 mbMask[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
9191

9292
for (i = 0; i < 8; i++) {
93-
loc_src[i] = (Ipp8u*)source_pa[i];
94-
loc_dst[i] = (Ipp8u*)dst_pa[i];
95-
int len64 = arr_len[i] / (Ipp32s)sizeof(Ipp64u); // legth in 64-bit chunks
96-
loc_len64[i] = len64;
97-
9893
// The case of the empty input buffer
9994
if (arr_len[i] == 0)
10095
{
101-
mbMask128[i] = 0;
102-
mbMask[i] = 0;
96+
mbMask128[i] = 0;
97+
mbMask[i] = 0;
98+
loc_len64[i] = 0;
10399
continue;
104100
}
105101

102+
loc_src[i] = (Ipp8u*)source_pa[i];
103+
loc_dst[i] = (Ipp8u*)dst_pa[i];
104+
int len64 = arr_len[i] / (Ipp32s)sizeof(Ipp64u); // length in 64-bit chunks
105+
loc_len64[i] = len64;
106+
106107
if (len64 < 8)
107108
mbMask[i] = (__mmask8)(((1 << len64) - 1) & 0xFF);
108109
if (len64 > maxLen)

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