Skip to content

Commit 3aa5679

Browse files
pConstpConst
committed
README update
1 parent d046210 commit 3aa5679

File tree

1 file changed

+100
-79
lines changed

1 file changed

+100
-79
lines changed

‎README.md

Lines changed: 100 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -1,85 +1,106 @@
11
Must-have verilog systemverilog modules
2-
---------------------------------------
2+
=======================================
3+
Originally published as part of https://github.com/pConst/basic_verilog
4+
by Konstantin Pavlov, pavlovconst@gmail.com
35

4-
Hello! This is a collection of verilog systemverilog synthesizable modules.<br>
5-
All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.<br>
6-
Please feel free to contact me in case you found any code issues.<br>
7-
Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!<br>
6+
Hi! This is a collection of Verilog SystemVerilog synthesizable modules.
87

9-
Konstantin Pavlov, pavlovconst@gmail.com
8+
All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.
109

11-
The code is licensed under CC BY-SA 4_0.<br>
12-
You can remix, transform, and build upon the material for any purpose, even commercially<br>
13-
You must provide the name of the creator and distribute your contributions under the same license as the original<br>
10+
Please feel free to make pull requests or contact me in case you spot any code issues.
1411

15-
Directories description:
16-
-----------------------
17-
18-
| DIRECTORY | DESCRIPTION |
19-
|-----------|-------------|
20-
| Advanced Synthesis Cookbook/ | useful code from Altera's cookbook |
21-
| KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processo |
22-
| pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices |
23-
| example_projects/ | FPGA project examples |
24-
| benchmark_projects/ | compilation time benchmarks for a dosen of FPGA types |
25-
| scripts/ | useful TCL scripts |
26-
27-
Scripts description:
28-
--------------------
29-
30-
| SCRIPT | DESCRIPTION |
31-
|--------|-------------|
32-
| scripts/allow_undefined_ports.tcl | allows generation of test projects with undefined pins for Vivado IDE |
33-
| scripts/compile_quartus.tcl | boilerplate script for commandline project compilation in Quartus IDE |
34-
| scripts/convert_sof_to_jam.bat | Altera/Intel FPGA configuration file converter |
35-
| scripts/convert_sof_to_rbf.bat | another Altera/Intel FPGA configuration file converter |
36-
| scripts/iverilog_compile.tcl | complete script to compile Verilog sources with iverilog tool and run simulation in gtkwave tool |
37-
| scripts/modelsim_compile.tcl | Modelsim no-project-mode compilation script |
38-
| scripts/post_flow_quartus.tcl | custom reporting or report analisys for Intel Quartus IDE |
39-
| scripts/post_flow_vivado.tcl | custom reporting or report analisys for Xilinx Vivado IDE |
40-
| scripts/program_all.bat | command line programmer example for Altera/Intel FPGAs |
41-
| scripts/project_version_auto_increment.tcl | project version autoincrement script for Quartus IDE |
42-
| scripts/quartus_system_console_init.tcl | initialization script for reading/writing Avalon-MM through JTAG-to-Avalon-MM bridge IP |
43-
| scripts/set_project_directory.tcl | changes current directory to match project directory in Vivado IDE |
44-
| scripts/write_avalon_mm_from_file.tcl | writing bulk binary data from binary file to Avalon-MM through JTAG-to-Avalon-MM bridge IP |
45-
46-
Modules description:
12+
Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!
13+
14+
Licensing
15+
---------
16+
The code is licensed under CC BY-SA 4_0
17+
That means, that you can remix, transform, and build upon the material for any purpose, even commercially.
18+
However, YOU MUST provide the name of the creator and distribute your contributions under the same license as the original.
19+
20+
Contents description
4721
--------------------
48-
49-
| MODULE | DESCRIPTION |
50-
|--------|-------------|
51-
| ActionBurst.v | multichannel one-shot triggering module |
52-
| ActionBurst2.v | multichannel one-shot triggering with variable steps |
53-
| adder_tree.sv | adding multiple values together in parallel |
54-
| bin2gray.sv | combinational Gray code to binary converter |
55-
| bin2pos.sv | converts binary coded value to positional (one-hot) code |
56-
| clk_divider.sv | wide reference clock divider |
57-
| debounce.v | two-cycle debounce for input buttons |
58-
| delay.sv | useful module to make static delays or to synchronize across clock domains |
59-
| dynamic_delay.sv | dynamic delay for arbitrary input signal |
60-
| edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
61-
| encoder.v | digital encoder input logic module |
62-
| fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation |
63-
| gray2bin.sv | combinational binary to Gray code converter |
64-
| leave_one_hot.sv | combinational module that leaves only lowest hot bit |
65-
| lifo.sv | single-clock LIFO buffer (stack) implementation |
66-
| main_tb.sv | basic testbench template |
67-
| NDivide.v | primitive integer divider |
68-
| pos2bin.sv | converts positional (one-hot) value to binary representation |
69-
| pos2bin.sv | converts positional (one-hot) value to binary representation |
70-
| prbs_gen_chk.sv | PRBS pattern generator or checker |
71-
| pulse_gen.sv | generates pulses with given width and delay |
72-
| pulse_stretch.sv | configurable pulse stretcher/extender module |
73-
| reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
74-
| reverse_bytes.sv | reverses bytes order within multi-byte array |
75-
| reverse_vector.sv | reverses signal order within multi-bit bus |
76-
| set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
77-
| spi_master.sv | universal spi master module |
78-
| UartRx.v | straightforward yet simple UART receiver |
79-
| UartTx.v | straightforward yet simple UART transmitter |
80-
| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
81-
| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
82-
| UartRxExtreme.v | extreme minimal UART receiver implementation |
83-
| UartTxExtreme.v | extreme minimal UART transmitter implementation |
84-
85-
Also added testbenches for selected modules
22+
For your convinience I`ve tagged some sources by their "difficulty":
23+
:green_circle: - for the most basic tasks
24+
:red_circle: - for advanced or special purpose routines
25+
26+
If you are a beginner in HW design - you may want to start exploring :green_circle: code first.
27+
Almost every source file in the repository contains detailed description and instantiation template!
28+
29+
| USAGE | DIRECTORY | DESCRIPTION |
30+
|---------------|--------------|-------------|
31+
| | Advanced Synthesis Cookbook/ | useful code from Altera's cookbook |
32+
| | KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processor sources |
33+
| :red_circle: | XilinxBoardStore_with_Alveo_cards_support | board definitions for Xilinx Alveo accelerator cards |
34+
| | pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices |
35+
| | avalon_mm_master_templates/ | Avalon-MM component templates from Altera |
36+
| | axi_master_slave_templates/ | AXI componet templates generated by Vivado |
37+
| | benchmark_projects/ | benchmarking various IDEs to compile exact same Verilog project |
38+
| | dual_port_ram_templates/ | Block RAM templates |
39+
| | example_projects/ | FPGA project boilerplates and examples |
40+
| | gitignores/ | gitignore files for FPGA projects |
41+
| | scripts/ | useful TCL, batch and shell scripts |
42+
| :red_circle: | scripts_for_intel_hls/ | useful scripts for compiling for Intel HLS |
43+
| :red_circle: | scripts_for_xilinx_hls/ | useful scripts for compiling for Xilinx HLS |
44+
| | xpm | Xilinx parametrizable macros sources |
45+
46+
| USAGE | FILE | DESCRIPTION |
47+
|----------------|--------------------|-------------|
48+
| | adder_tree.sv | adding multiple values together in parallel |
49+
| | axi4l_logger.sv | |
50+
| :green_circle: | bin2gray.sv | combinational Gray code to binary converter |
51+
| | bin2pos.sv | converts binary coded value to positional (one-hot) code |
52+
| | cdc_data.sv | |
53+
| | cdc_strobe.sv | |
54+
| :green_circle: | clk_divider.sv | wide reference clock divider |
55+
| | clogb2.svh | |
56+
| :green_circle: | debounce.v | two-cycle debounce for input buttons |
57+
| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains |
58+
| | delayed_event.sv | |
59+
| | dynamic_delay.sv | dynamic delay for arbitrary input signal |
60+
| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
61+
| | encoder.v | digital encoder input logic module |
62+
| :red_circle: | fast_counter.sv | |
63+
| | fifo_combiner.sv | |
64+
| | fifo_operator.sv | |
65+
| :red_circle: | fifo_single_clock_ram_*.sv | single-clock FIFO buffer (queue) implementation |
66+
| :red_circle: | fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation |
67+
| :green_circle: | gray2bin.sv | combinational binary to Gray code converter |
68+
| :red_circle: | gray_functions.vh | |
69+
| :green_circle: | hex2ascii.sv | |
70+
| | leave_one_hot.sv | combinational module that leaves only lowest hot bit |
71+
| | lifo.sv | single-clock LIFO buffer (stack) implementation |
72+
| | main_tb.sv | basic testbench template |
73+
| | moving_average.sv | |
74+
| | pack_unpack_array.v | |
75+
| | pattern_detect.sv | |
76+
| | pdm_modulator.sv | |
77+
| | pos2bin.sv | converts positional (one-hot) value to binary representation |
78+
| | prbs_gen_chk.sv | PRBS pattern generator or checker |
79+
| | preview_fifo.sv | |
80+
| | priority_enc.sv | |
81+
| | pulse_gen.sv | generates pulses with given width and delay |
82+
| | pulse_stretch.sv | configurable pulse stretcher/extender module |
83+
| | pwm_modulator.sv | |
84+
| :red_circle: | read_ahead_buf.sv | |
85+
| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
86+
| | reset_set_comb.sv | |
87+
| | reverse_bytes.sv | reverses bytes order within multi-byte array |
88+
| | reverse_dimensions.sv | |
89+
| | reverse_vector.sv | reverses signal order within multi-bit bus |
90+
| | round_robin_enc.sv | |
91+
| | round_robin_performance_enc.sv | |
92+
| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
93+
| | set_reset_comb.sv | |
94+
| | sim_clk_gen.sv | |
95+
| :red_circle: | soft_latch.sv | |
96+
| | spi_master.sv | universal spi master module |
97+
| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | |
98+
| :red_circle: | true_single_port_write_first_ram.sv | |
99+
| | uart_debug_printer.sv | |
100+
| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver |
101+
| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
102+
| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter |
103+
| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs |
104+
105+
Also added testbenches for selected modules.
106+

0 commit comments

Comments
 (0)