diff --git a/lib/Conversion/ExportVerilog/ExportVerilogInternals.h b/lib/Conversion/ExportVerilog/ExportVerilogInternals.h
index 28a0fa089b6b..38f4f153c59d 100644
--- a/lib/Conversion/ExportVerilog/ExportVerilogInternals.h
+++ b/lib/Conversion/ExportVerilog/ExportVerilogInternals.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef TRANSLATION_EXPORT_VERILOG_EXPORTVERILOGINTERNAL_H
-#define TRANSLATION_EXPORT_VERILOG_EXPORTVERILOGINTERNAL_H
+#ifndef CONVERSION_EXPORTVERILOG_EXPORTVERILOGINTERNAL_H
+#define CONVERSION_EXPORTVERILOG_EXPORTVERILOGINTERNAL_H
 
 #include "circt/Dialect/HW/HWOps.h"
 #include "circt/Dialect/SV/SVOps.h"
@@ -162,4 +162,4 @@ GlobalNameTable legalizeGlobalNames(ModuleOp topLevel);
 
 } // namespace circt
 
-#endif // TRANSLATION_EXPORT_VERILOG_EXPORTVERILOGINTERNAL_H
+#endif // CONVERSION_EXPORTVERILOG_EXPORTVERILOGINTERNAL_H
diff --git a/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp b/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
index d6ec2fcaf1f9..bdd267cc3050 100644
--- a/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
+++ b/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
@@ -1456,7 +1456,7 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
 
         // A helper function that returns the indeces of the "data", "rdata",
         // and "wdata" fields in the bundle corresponding to a memory port.
-        auto dataFieldIndices = [](MemOp::PortKind kind) {
+        auto dataFieldIndices = [](MemOp::PortKind kind) -> ArrayRef<unsigned> {
           static const unsigned indices[] = {3, 5};
           switch (kind) {
           case MemOp::PortKind::Read: