This repository has been archived by the owner on Jan 22, 2018. It is now read-only.
forked from MAVProxyUser/spray-system
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathuser_interrupt.lst
9537 lines (9537 loc) · 374 KB
/
user_interrupt.lst
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
L 1 "drivers\user_interrupt.c"
N
N#include "LPC17xx.h"
L 1 "drivers\LPC17xx.h" 1
N/******************************************************************************
N * @file: LPC17xx.h
N * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
N * NXP LPC17xx Device Series
N * @version: V1.09
N * @date: 17. March 2010
N *----------------------------------------------------------------------------
N *
N * Copyright (C) 2008 ARM Limited. All rights reserved.
N *
N * ARM Limited (ARM) is supplying this software for use with Cortex-M3
N * processor based microcontrollers. This file can be freely distributed
N * within development tools that are supporting such ARM based processors.
N *
N * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
N * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
N * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
N * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
N * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
N *
N ******************************************************************************/
N
N
N#ifndef __LPC17xx_H__
N#define __LPC17xx_H__
N
N/*
N * ==========================================================================
N * ---------- Interrupt Number Definition -----------------------------------
N * ==========================================================================
N */
N
Ntypedef enum IRQn
N{
N/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
N NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
N MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
N BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
N UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
N SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
N DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
N PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
N SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
N
N/****** LPC17xx Specific Interrupt Numbers *******************************************************/
N WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
N TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
N TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
N TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
N TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
N UART0_IRQn = 5, /*!< UART0 Interrupt */
N UART1_IRQn = 6, /*!< UART1 Interrupt */
N UART2_IRQn = 7, /*!< UART2 Interrupt */
N UART3_IRQn = 8, /*!< UART3 Interrupt */
N PWM1_IRQn = 9, /*!< PWM1 Interrupt */
N I2C0_IRQn = 10, /*!< I2C0 Interrupt */
N I2C1_IRQn = 11, /*!< I2C1 Interrupt */
N I2C2_IRQn = 12, /*!< I2C2 Interrupt */
N SPI_IRQn = 13, /*!< SPI Interrupt */
N SSP0_IRQn = 14, /*!< SSP0 Interrupt */
N SSP1_IRQn = 15, /*!< SSP1 Interrupt */
N PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
N RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
N EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
N EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
N EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
N EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
N ADC_IRQn = 22, /*!< A/D Converter Interrupt */
N BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
N USB_IRQn = 24, /*!< USB Interrupt */
N CAN_IRQn = 25, /*!< CAN Interrupt */
N DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
N I2S_IRQn = 27, /*!< I2S Interrupt */
N ENET_IRQn = 28, /*!< Ethernet Interrupt */
N RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
N MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
N QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
N PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
N USBActivity_IRQn = 33, /* USB Activity interrupt */
N CANActivity_IRQn = 34, /* CAN Activity interrupt */
N} IRQn_Type;
N
N
N/*
N * ==========================================================================
N * ----------- Processor and Core Peripheral Section ------------------------
N * ==========================================================================
N */
N
N/* Configuration of the Cortex-M3 Processor and Core Peripherals */
N#define __MPU_PRESENT 1 /*!< MPU present or not */
N#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
N#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
N
N
N#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
L 1 ".\cstartup\core_cm3.h" 1
N/******************************************************************************
N * @file: core_cm3.h
N * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
N * @version: V1.20
N * @date: 22. May 2009
N *----------------------------------------------------------------------------
N *
N * Copyright (C) 2009 ARM Limited. All rights reserved.
N *
N * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
N * processor based microcontrollers. This file can be freely distributed
N * within development tools that are supporting such ARM based processors.
N *
N * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
N * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
N * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
N * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
N * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
N *
N ******************************************************************************/
N
N#ifndef __CM3_CORE_H__
N#define __CM3_CORE_H__
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
N#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
N#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
N
N#define __CORTEX_M (0x03) /*!< Cortex core */
N
N/**
N * Lint configuration \n
N * ----------------------- \n
N *
N * The following Lint messages will be suppressed and not shown: \n
N * \n
N * --- Error 10: --- \n
N * register uint32_t __regBasePri __asm("basepri"); \n
N * Error 10: Expecting ';' \n
N * \n
N * --- Error 530: --- \n
N * return(__regBasePri); \n
N * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
N * \n
N * --- Error 550: --- \n
N * __regBasePri = (basePri & 0x1ff); \n
N * } \n
N * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
N * \n
N * --- Error 754: --- \n
N * uint32_t RESERVED0[24]; \n
N * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
N * \n
N * --- Error 750: --- \n
N * #define __CM3_CORE_H__ \n
N * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
N * \n
N * --- Error 528: --- \n
N * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
N * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
N * \n
N * --- Error 751: --- \n
N * } InterruptType_Type; \n
N * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
N * \n
N * \n
N * Note: To re-enable a Message, insert a space before 'lint' * \n
N *
N */
N
N/*lint -save */
N/*lint -e10 */
N/*lint -e530 */
N/*lint -e550 */
N/*lint -e754 */
N/*lint -e750 */
N/*lint -e528 */
N/*lint -e751 */
N
N
N#include <stdint.h> /* Include standard types */
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h" 1
N/* Copyright (C) ARM Ltd., 1999,2014 */
N/* All rights reserved */
N
N/*
N * RCS $Revision$
N * Checkin $Date$
N * Revising $Author: agrant $
N */
N
N#ifndef __stdint_h
N#define __stdint_h
N#define __ARMCLIB_VERSION 5060019
N
N #ifdef __INT64_TYPE__
S /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */
S #define __INT64 __INT64_TYPE__
N #else
N /* armcc has builtin '__int64' which can be used in --strict mode */
N #define __INT64 __int64
N #define __INT64_C_SUFFIX__ ll
N #endif
N #define __PASTE2(x, y) x ## y
N #define __PASTE(x, y) __PASTE2(x, y)
N #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
N #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
N #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__))
X #if 0L || (1L && !0L)
N /* armclang and non-strict armcc allow 'long long' in system headers */
N #define __LONGLONG long long
N #else
S /* strict armcc has '__int64' */
S #define __LONGLONG __int64
N #endif
N
N #ifndef __STDINT_DECLS
N #define __STDINT_DECLS
N
N #undef __CLIBNS
N
N #ifdef __cplusplus
S namespace std {
S #define __CLIBNS std::
S extern "C" {
N #else
N #define __CLIBNS
N #endif /* __cplusplus */
N
N
N/*
N * 'signed' is redundant below, except for 'signed char' and if
N * the typedef is used to declare a bitfield.
N */
N
N /* 7.18.1.1 */
N
N /* exact-width signed integer types */
Ntypedef signed char int8_t;
Ntypedef signed short int int16_t;
Ntypedef signed int int32_t;
Ntypedef signed __INT64 int64_t;
Xtypedef signed __int64 int64_t;
N
N /* exact-width unsigned integer types */
Ntypedef unsigned char uint8_t;
Ntypedef unsigned short int uint16_t;
Ntypedef unsigned int uint32_t;
Ntypedef unsigned __INT64 uint64_t;
Xtypedef unsigned __int64 uint64_t;
N
N /* 7.18.1.2 */
N
N /* smallest type of at least n bits */
N /* minimum-width signed integer types */
Ntypedef signed char int_least8_t;
Ntypedef signed short int int_least16_t;
Ntypedef signed int int_least32_t;
Ntypedef signed __INT64 int_least64_t;
Xtypedef signed __int64 int_least64_t;
N
N /* minimum-width unsigned integer types */
Ntypedef unsigned char uint_least8_t;
Ntypedef unsigned short int uint_least16_t;
Ntypedef unsigned int uint_least32_t;
Ntypedef unsigned __INT64 uint_least64_t;
Xtypedef unsigned __int64 uint_least64_t;
N
N /* 7.18.1.3 */
N
N /* fastest minimum-width signed integer types */
Ntypedef signed int int_fast8_t;
Ntypedef signed int int_fast16_t;
Ntypedef signed int int_fast32_t;
Ntypedef signed __INT64 int_fast64_t;
Xtypedef signed __int64 int_fast64_t;
N
N /* fastest minimum-width unsigned integer types */
Ntypedef unsigned int uint_fast8_t;
Ntypedef unsigned int uint_fast16_t;
Ntypedef unsigned int uint_fast32_t;
Ntypedef unsigned __INT64 uint_fast64_t;
Xtypedef unsigned __int64 uint_fast64_t;
N
N /* 7.18.1.4 integer types capable of holding object pointers */
N#if __sizeof_ptr == 8
X#if 4 == 8
Stypedef signed __INT64 intptr_t;
Stypedef unsigned __INT64 uintptr_t;
N#else
Ntypedef signed int intptr_t;
Ntypedef unsigned int uintptr_t;
N#endif
N
N /* 7.18.1.5 greatest-width integer types */
Ntypedef signed __LONGLONG intmax_t;
Xtypedef signed long long intmax_t;
Ntypedef unsigned __LONGLONG uintmax_t;
Xtypedef unsigned long long uintmax_t;
N
N
N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
X#if !0L || 0L
N
N /* 7.18.2.1 */
N
N /* minimum values of exact-width signed integer types */
N#define INT8_MIN -128
N#define INT16_MIN -32768
N#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */
N#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */
N
N /* maximum values of exact-width signed integer types */
N#define INT8_MAX 127
N#define INT16_MAX 32767
N#define INT32_MAX 2147483647
N#define INT64_MAX __INT64_C(9223372036854775807)
N
N /* maximum values of exact-width unsigned integer types */
N#define UINT8_MAX 255
N#define UINT16_MAX 65535
N#define UINT32_MAX 4294967295u
N#define UINT64_MAX __UINT64_C(18446744073709551615)
N
N /* 7.18.2.2 */
N
N /* minimum values of minimum-width signed integer types */
N#define INT_LEAST8_MIN -128
N#define INT_LEAST16_MIN -32768
N#define INT_LEAST32_MIN (~0x7fffffff)
N#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)
N
N /* maximum values of minimum-width signed integer types */
N#define INT_LEAST8_MAX 127
N#define INT_LEAST16_MAX 32767
N#define INT_LEAST32_MAX 2147483647
N#define INT_LEAST64_MAX __INT64_C(9223372036854775807)
N
N /* maximum values of minimum-width unsigned integer types */
N#define UINT_LEAST8_MAX 255
N#define UINT_LEAST16_MAX 65535
N#define UINT_LEAST32_MAX 4294967295u
N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
N
N /* 7.18.2.3 */
N
N /* minimum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MIN (~0x7fffffff)
N#define INT_FAST16_MIN (~0x7fffffff)
N#define INT_FAST32_MIN (~0x7fffffff)
N#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)
N
N /* maximum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MAX 2147483647
N#define INT_FAST16_MAX 2147483647
N#define INT_FAST32_MAX 2147483647
N#define INT_FAST64_MAX __INT64_C(9223372036854775807)
N
N /* maximum values of fastest minimum-width unsigned integer types */
N#define UINT_FAST8_MAX 4294967295u
N#define UINT_FAST16_MAX 4294967295u
N#define UINT_FAST32_MAX 4294967295u
N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615)
N
N /* 7.18.2.4 */
N
N /* minimum value of pointer-holding signed integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define INTPTR_MIN INT64_MIN
N#else
N#define INTPTR_MIN INT32_MIN
N#endif
N
N /* maximum value of pointer-holding signed integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define INTPTR_MAX INT64_MAX
N#else
N#define INTPTR_MAX INT32_MAX
N#endif
N
N /* maximum value of pointer-holding unsigned integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define UINTPTR_MAX UINT64_MAX
N#else
N#define UINTPTR_MAX UINT32_MAX
N#endif
N
N /* 7.18.2.5 */
N
N /* minimum value of greatest-width signed integer type */
N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
N
N /* maximum value of greatest-width signed integer type */
N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll)
N
N /* maximum value of greatest-width unsigned integer type */
N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
N
N /* 7.18.3 */
N
N /* limits of ptrdiff_t */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define PTRDIFF_MIN INT64_MIN
S#define PTRDIFF_MAX INT64_MAX
N#else
N#define PTRDIFF_MIN INT32_MIN
N#define PTRDIFF_MAX INT32_MAX
N#endif
N
N /* limits of sig_atomic_t */
N#define SIG_ATOMIC_MIN (~0x7fffffff)
N#define SIG_ATOMIC_MAX 2147483647
N
N /* limit of size_t */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define SIZE_MAX UINT64_MAX
N#else
N#define SIZE_MAX UINT32_MAX
N#endif
N
N /* limits of wchar_t */
N /* NB we have to undef and redef because they're defined in both
N * stdint.h and wchar.h */
N#undef WCHAR_MIN
N#undef WCHAR_MAX
N
N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4)
X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4)
S #define WCHAR_MIN 0
S #define WCHAR_MAX 0xffffffffU
N#else
N #define WCHAR_MIN 0
N #define WCHAR_MAX 65535
N#endif
N
N /* limits of wint_t */
N#define WINT_MIN (~0x7fffffff)
N#define WINT_MAX 2147483647
N
N#endif /* __STDC_LIMIT_MACROS */
N
N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
X#if !0L || 0L
N
N /* 7.18.4.1 macros for minimum-width integer constants */
N#define INT8_C(x) (x)
N#define INT16_C(x) (x)
N#define INT32_C(x) (x)
N#define INT64_C(x) __INT64_C(x)
N
N#define UINT8_C(x) (x ## u)
N#define UINT16_C(x) (x ## u)
N#define UINT32_C(x) (x ## u)
N#define UINT64_C(x) __UINT64_C(x)
N
N /* 7.18.4.2 macros for greatest-width integer constants */
N#define INTMAX_C(x) __ESCAPE__(x ## ll)
N#define UINTMAX_C(x) __ESCAPE__(x ## ull)
N
N#endif /* __STDC_CONSTANT_MACROS */
N
N #ifdef __cplusplus
S } /* extern "C" */
S } /* namespace std */
N #endif /* __cplusplus */
N #endif /* __STDINT_DECLS */
N
N #ifdef __cplusplus
S #ifndef __STDINT_NO_EXPORTS
S using ::std::int8_t;
S using ::std::int16_t;
S using ::std::int32_t;
S using ::std::int64_t;
S using ::std::uint8_t;
S using ::std::uint16_t;
S using ::std::uint32_t;
S using ::std::uint64_t;
S using ::std::int_least8_t;
S using ::std::int_least16_t;
S using ::std::int_least32_t;
S using ::std::int_least64_t;
S using ::std::uint_least8_t;
S using ::std::uint_least16_t;
S using ::std::uint_least32_t;
S using ::std::uint_least64_t;
S using ::std::int_fast8_t;
S using ::std::int_fast16_t;
S using ::std::int_fast32_t;
S using ::std::int_fast64_t;
S using ::std::uint_fast8_t;
S using ::std::uint_fast16_t;
S using ::std::uint_fast32_t;
S using ::std::uint_fast64_t;
S using ::std::intptr_t;
S using ::std::uintptr_t;
S using ::std::intmax_t;
S using ::std::uintmax_t;
S #endif
N #endif /* __cplusplus */
N
N#undef __INT64
N#undef __LONGLONG
N
N#endif /* __stdint_h */
N
N/* end of stdint.h */
L 86 ".\cstartup\core_cm3.h" 2
N
N#if defined (__ICCARM__)
X#if 0L
S #include <intrinsics.h> /* IAR Intrinsics */
N#endif
N
N
N#ifndef __NVIC_PRIO_BITS
S #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
N#endif
N
N
N
N
N/**
N * IO definitions
N *
N * define access restrictions to peripheral registers
N */
N
N#ifdef __cplusplus
S#define __I volatile /*!< defines 'read only' permissions */
N#else
N#define __I volatile const /*!< defines 'read only' permissions */
N#endif
N#define __O volatile /*!< defines 'write only' permissions */
N#define __IO volatile /*!< defines 'read / write' permissions */
N
N
N
N/*******************************************************************************
N * Register Abstraction
N ******************************************************************************/
N
N
N/* System Reset */
N#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
N#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
N#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
N#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
N
N/* Core Debug */
N#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
N#define ITM_TCR_ITMENA 1 /*!< ITM enable */
N
N
N
N
N/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
Ntypedef struct
N{
N __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
X volatile uint32_t ISER[8];
N uint32_t RESERVED0[24];
N __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
X volatile uint32_t ICER[8];
N uint32_t RSERVED1[24];
N __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
X volatile uint32_t ISPR[8];
N uint32_t RESERVED2[24];
N __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
X volatile uint32_t ICPR[8];
N uint32_t RESERVED3[24];
N __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
X volatile uint32_t IABR[8];
N uint32_t RESERVED4[56];
N __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
X volatile uint8_t IP[240];
N uint32_t RESERVED5[644];
N __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
X volatile uint32_t STIR;
N} NVIC_Type;
N
N
N/* memory mapping struct for System Control Block */
Ntypedef struct
N{
N __I uint32_t CPUID; /*!< CPU ID Base Register */
X volatile const uint32_t CPUID;
N __IO uint32_t ICSR; /*!< Interrupt Control State Register */
X volatile uint32_t ICSR;
N __IO uint32_t VTOR; /*!< Vector Table Offset Register */
X volatile uint32_t VTOR;
N __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
X volatile uint32_t AIRCR;
N __IO uint32_t SCR; /*!< System Control Register */
X volatile uint32_t SCR;
N __IO uint32_t CCR; /*!< Configuration Control Register */
X volatile uint32_t CCR;
N __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
X volatile uint8_t SHP[12];
N __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
X volatile uint32_t SHCSR;
N __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
X volatile uint32_t CFSR;
N __IO uint32_t HFSR; /*!< Hard Fault Status Register */
X volatile uint32_t HFSR;
N __IO uint32_t DFSR; /*!< Debug Fault Status Register */
X volatile uint32_t DFSR;
N __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
X volatile uint32_t MMFAR;
N __IO uint32_t BFAR; /*!< Bus Fault Address Register */
X volatile uint32_t BFAR;
N __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
X volatile uint32_t AFSR;
N __I uint32_t PFR[2]; /*!< Processor Feature Register */
X volatile const uint32_t PFR[2];
N __I uint32_t DFR; /*!< Debug Feature Register */
X volatile const uint32_t DFR;
N __I uint32_t ADR; /*!< Auxiliary Feature Register */
X volatile const uint32_t ADR;
N __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
X volatile const uint32_t MMFR[4];
N __I uint32_t ISAR[5]; /*!< ISA Feature Register */
X volatile const uint32_t ISAR[5];
N} SCB_Type;
N
N
N/* memory mapping struct for SysTick */
Ntypedef struct
N{
N __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
X volatile uint32_t CTRL;
N __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
X volatile uint32_t LOAD;
N __IO uint32_t VAL; /*!< SysTick Current Value Register */
X volatile uint32_t VAL;
N __I uint32_t CALIB; /*!< SysTick Calibration Register */
X volatile const uint32_t CALIB;
N} SysTick_Type;
N
N
N/* memory mapping structur for ITM */
Ntypedef struct
N{
N __O union
X volatile union
N {
N __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
X volatile uint8_t u8;
N __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
X volatile uint16_t u16;
N __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
X volatile uint32_t u32;
N } PORT [32]; /*!< ITM Stimulus Port Registers */
N uint32_t RESERVED0[864];
N __IO uint32_t TER; /*!< ITM Trace Enable Register */
X volatile uint32_t TER;
N uint32_t RESERVED1[15];
N __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
X volatile uint32_t TPR;
N uint32_t RESERVED2[15];
N __IO uint32_t TCR; /*!< ITM Trace Control Register */
X volatile uint32_t TCR;
N uint32_t RESERVED3[29];
N __IO uint32_t IWR; /*!< ITM Integration Write Register */
X volatile uint32_t IWR;
N __IO uint32_t IRR; /*!< ITM Integration Read Register */
X volatile uint32_t IRR;
N __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
X volatile uint32_t IMCR;
N uint32_t RESERVED4[43];
N __IO uint32_t LAR; /*!< ITM Lock Access Register */
X volatile uint32_t LAR;
N __IO uint32_t LSR; /*!< ITM Lock Status Register */
X volatile uint32_t LSR;
N uint32_t RESERVED5[6];
N __I uint32_t PID4; /*!< ITM Product ID Registers */
X volatile const uint32_t PID4;
N __I uint32_t PID5;
X volatile const uint32_t PID5;
N __I uint32_t PID6;
X volatile const uint32_t PID6;
N __I uint32_t PID7;
X volatile const uint32_t PID7;
N __I uint32_t PID0;
X volatile const uint32_t PID0;
N __I uint32_t PID1;
X volatile const uint32_t PID1;
N __I uint32_t PID2;
X volatile const uint32_t PID2;
N __I uint32_t PID3;
X volatile const uint32_t PID3;
N __I uint32_t CID0;
X volatile const uint32_t CID0;
N __I uint32_t CID1;
X volatile const uint32_t CID1;
N __I uint32_t CID2;
X volatile const uint32_t CID2;
N __I uint32_t CID3;
X volatile const uint32_t CID3;
N} ITM_Type;
N
N
N/* memory mapped struct for Interrupt Type */
Ntypedef struct
N{
N uint32_t RESERVED0;
N __I uint32_t ICTR; /*!< Interrupt Control Type Register */
X volatile const uint32_t ICTR;
N#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
X#if ((0L) && (__CM3_REV >= 0x200))
S __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
N#else
N uint32_t RESERVED1;
N#endif
N} InterruptType_Type;
N
N
N/* Memory Protection Unit */
N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
X#if 1L && (1 == 1)
Ntypedef struct
N{
N __I uint32_t TYPE; /*!< MPU Type Register */
X volatile const uint32_t TYPE;
N __IO uint32_t CTRL; /*!< MPU Control Register */
X volatile uint32_t CTRL;
N __IO uint32_t RNR; /*!< MPU Region RNRber Register */
X volatile uint32_t RNR;
N __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
X volatile uint32_t RBAR;
N __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
X volatile uint32_t RASR;
N __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
X volatile uint32_t RBAR_A1;
N __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
X volatile uint32_t RASR_A1;
N __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
X volatile uint32_t RBAR_A2;
N __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
X volatile uint32_t RASR_A2;
N __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
X volatile uint32_t RBAR_A3;
N __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
X volatile uint32_t RASR_A3;
N} MPU_Type;
N#endif
N
N
N/* Core Debug Register */
Ntypedef struct
N{
N __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
X volatile uint32_t DHCSR;
N __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
X volatile uint32_t DCRSR;
N __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
X volatile uint32_t DCRDR;
N __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
X volatile uint32_t DEMCR;
N} CoreDebug_Type;
N
N
N/* Memory mapping of Cortex-M3 Hardware */
N#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
N#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
N#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
N#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
N#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
N#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
N
N#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
N#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
N#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
N#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
N#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
N#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
N
N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
X#if 1L && (1 == 1)
N #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
N #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
N#endif
N
N
N
N/*******************************************************************************
N * Hardware Abstraction Layer
N ******************************************************************************/
N
N
N#if defined ( __CC_ARM )
X#if 1L
N #define __ASM __asm /*!< asm keyword for ARM Compiler */
N #define __INLINE __inline /*!< inline keyword for ARM Compiler */
N
N#elif defined ( __ICCARM__ )
S #define __ASM __asm /*!< asm keyword for IAR Compiler */
S #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
S
S#elif defined ( __GNUC__ )
S #define __ASM __asm /*!< asm keyword for GNU Compiler */
S #define __INLINE inline /*!< inline keyword for GNU Compiler */
S
S#elif defined ( __TASKING__ )
S #define __ASM __asm /*!< asm keyword for TASKING Compiler */
S #define __INLINE inline /*!< inline keyword for TASKING Compiler */
S
N#endif
N
N
N/* ################### Compiler specific Intrinsics ########################### */
N
N#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
X#if 1L
N/* ARM armcc specific functions */
N
N#define __enable_fault_irq __enable_fiq
N#define __disable_fault_irq __disable_fiq
N
N#define __NOP __nop
N#define __WFI __wfi
N#define __WFE __wfe
N#define __SEV __sev
N#define __ISB() __isb(0)
N#define __DSB() __dsb(0)
N#define __DMB() __dmb(0)
N#define __REV __rev
N#define __RBIT __rbit
N#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
N#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
N#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
N#define __STREXB(value, ptr) __strex(value, ptr)
N#define __STREXH(value, ptr) __strex(value, ptr)
N#define __STREXW(value, ptr) __strex(value, ptr)
N
N
N/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
N/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
N/* intrinsic void __enable_irq(); */
N/* intrinsic void __disable_irq(); */
N
N
N/**
N * @brief Return the Process Stack Pointer
N *
N * @param none
N * @return uint32_t ProcessStackPointer
N *
N * Return the actual process stack pointer
N */
Nextern uint32_t __get_PSP(void);
N
N/**
N * @brief Set the Process Stack Pointer
N *
N * @param uint32_t Process Stack Pointer
N * @return none
N *
N * Assign the value ProcessStackPointer to the MSP
N * (process stack pointer) Cortex processor register
N */
Nextern void __set_PSP(uint32_t topOfProcStack);
N
N/**
N * @brief Return the Main Stack Pointer
N *
N * @param none
N * @return uint32_t Main Stack Pointer
N *
N * Return the current value of the MSP (main stack pointer)
N * Cortex processor register
N */
Nextern uint32_t __get_MSP(void);
N
N/**
N * @brief Set the Main Stack Pointer
N *
N * @param uint32_t Main Stack Pointer
N * @return none
N *
N * Assign the value mainStackPointer to the MSP
N * (main stack pointer) Cortex processor register
N */
Nextern void __set_MSP(uint32_t topOfMainStack);
N
N/**
N * @brief Reverse byte order in unsigned short value
N *
N * @param uint16_t value to reverse
N * @return uint32_t reversed value
N *
N * Reverse byte order in unsigned short value
N */
Nextern uint32_t __REV16(uint16_t value);
N
N/*
N * @brief Reverse byte order in signed short value with sign extension to integer
N *
N * @param int16_t value to reverse
N * @return int32_t reversed value
N *
N * Reverse byte order in signed short value with sign extension to integer
N */
Nextern int32_t __REVSH(int16_t value);
N
N
N#if (__ARMCC_VERSION < 400000)
X#if (5060422 < 400000)
S
S/**
S * @brief Remove the exclusive lock created by ldrex
S *
S * @param none
S * @return none
S *
S * Removes the exclusive lock which is created by ldrex.
S */
Sextern void __CLREX(void);
S
S/**
S * @brief Return the Base Priority value
S *
S * @param none
S * @return uint32_t BasePriority
S *
S * Return the content of the base priority register
S */
Sextern uint32_t __get_BASEPRI(void);
S
S/**
S * @brief Set the Base Priority value
S *
S * @param uint32_t BasePriority
S * @return none
S *
S * Set the base priority register
S */
Sextern void __set_BASEPRI(uint32_t basePri);
S
S/**
S * @brief Return the Priority Mask value
S *
S * @param none
S * @return uint32_t PriMask
S *
S * Return the state of the priority mask bit from the priority mask
S * register
S */
Sextern uint32_t __get_PRIMASK(void);
S
S/**
S * @brief Set the Priority Mask value
S *
S * @param uint32_t PriMask
S * @return none
S *
S * Set the priority mask bit in the priority mask register
S */
Sextern void __set_PRIMASK(uint32_t priMask);
S
S/**
S * @brief Return the Fault Mask value
S *
S * @param none
S * @return uint32_t FaultMask
S *
S * Return the content of the fault mask register
S */
Sextern uint32_t __get_FAULTMASK(void);
S
S/**
S * @brief Set the Fault Mask value
S *
S * @param uint32_t faultMask value
S * @return none
S *
S * Set the fault mask register
S */
Sextern void __set_FAULTMASK(uint32_t faultMask);
S
S/**
S * @brief Return the Control Register value
S *
S * @param none
S * @return uint32_t Control value
S *
S * Return the content of the control register
S */
Sextern uint32_t __get_CONTROL(void);
S
S/**