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bitmanip.cpp
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bitmanip.cpp
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#include "Hart.hpp"
using namespace WdRiscv;
template <typename URV>
void
Hart<URV>::execClz(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
if (v1 == 0)
v1 = mxlen_;
else
{
if (mxlen_ == 32)
v1 = __builtin_clz(v1);
else
v1 = __builtin_clzl(v1);
}
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execCtz(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
if (mxlen_ == 32)
v1 = __builtin_ctz(v1);
else
v1 = __builtin_ctzl(v1);
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execCpop(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
if (mxlen_ == 32)
v1 = __builtin_popcount(v1);
else
v1 = __builtin_popcountl(v1);
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execClzw(const DecodedInst* di)
{
if (not isRv64() or not isRvzbb())
{
illegalInst(di);
return;
}
uint32_t v1 = intRegs_.read(di->op1());
if (v1 == 0)
v1 = 32;
else
v1 = __builtin_clz(v1);
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execCtzw(const DecodedInst* di)
{
if (not isRv64() or not isRvzbb())
{
illegalInst(di);
return;
}
uint32_t v1 = intRegs_.read(di->op1());
v1 = __builtin_ctz(v1);
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execCpopw(const DecodedInst* di)
{
if (not isRv64() or not isRvzbb())
{
illegalInst(di);
return;
}
uint32_t v1 = intRegs_.read(di->op1());
URV res = __builtin_popcount(v1);
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execAndn(const DecodedInst* di)
{
if (not isRvzbb() and not isRvzbp())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
URV v2 = intRegs_.read(di->op2());
URV res = v1 & ~v2;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execOrn(const DecodedInst* di)
{
if (not isRvzbb() and not isRvzbp())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
URV v2 = intRegs_.read(di->op2());
URV res = v1 | ~v2;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execXnor(const DecodedInst* di)
{
if (not isRvzbb() and not isRvzbp())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
URV v2 = intRegs_.read(di->op2());
URV res = v1 ^ ~v2;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execMin(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
SRV v1 = intRegs_.read(di->op1());
SRV v2 = intRegs_.read(di->op2());
SRV res = v1 < v2? v1 : v2;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execMax(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
SRV v1 = intRegs_.read(di->op1());
SRV v2 = intRegs_.read(di->op2());
SRV res = v1 > v2? v1 : v2;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execMinu(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
URV v2 = intRegs_.read(di->op2());
URV res = v1 < v2? v1 : v2;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execMaxu(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
URV v2 = intRegs_.read(di->op2());
URV res = v1 > v2? v1 : v2;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execRol(const DecodedInst* di)
{
if (not isRvzbb() and not isRvzbp())
{
illegalInst(di);
return;
}
URV mask = shiftMask();
URV rot = intRegs_.read(di->op2()) & mask; // Rotate amount
URV v1 = intRegs_.read(di->op1());
URV res = (v1 << rot) | (v1 >> ((mxlen_ - rot) & mask));
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execRor(const DecodedInst* di)
{
if (not isRvzbb() and not isRvzbp())
{
illegalInst(di);
return;
}
URV mask = shiftMask();
URV rot = intRegs_.read(di->op2()) & mask; // Rotate amount
URV v1 = intRegs_.read(di->op1());
URV res = (v1 >> rot) | (v1 << ((mxlen_ - rot) & mask));
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execRori(const DecodedInst* di)
{
if (not isRvzbb() and not isRvzbp())
{
illegalInst(di);
return;
}
URV rot = di->op2();
if (not checkShiftImmediate(di, rot))
return;
URV v1 = intRegs_.read(di->op1());
URV res = (v1 >> rot) | (v1 << ((mxlen_ - rot) & shiftMask()));
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execRolw(const DecodedInst* di)
{
if (not isRv64() or (not isRvzbb() and not isRvzbp()))
{
illegalInst(di);
return;
}
unsigned len = 32;
unsigned mask = len - 1;
unsigned rot = intRegs_.read(di->op2()) & mask; // Rotate amount
uint32_t v1 = intRegs_.read(di->op1());
uint32_t res32 = (v1 << rot) | (v1 >> ((len - rot) & mask));
uint64_t res64 = int32_t(res32); // Sign extend to 64-bits.
intRegs_.write(di->op0(), res64);
}
template <typename URV>
void
Hart<URV>::execRorw(const DecodedInst* di)
{
if (not isRv64() or (not isRvzbb() and not isRvzbp()))
{
illegalInst(di);
return;
}
unsigned len = 32;
unsigned mask = len - 1;
unsigned rot = intRegs_.read(di->op2()) & mask; // Rotate amount
uint32_t v1 = intRegs_.read(di->op1());
uint32_t res32 = (v1 >> rot) | (v1 << ((len - rot) & mask));
uint64_t res64 = int32_t(res32); // Sign extend to 64-bits.
intRegs_.write(di->op0(), res64);
}
template <typename URV>
void
Hart<URV>::execRoriw(const DecodedInst* di)
{
if (not isRv64() or (not isRvzbb() and not isRvzbp()))
{
illegalInst(di);
return;
}
unsigned len = 32;
unsigned mask = len - 1;
unsigned rot = di->op2();
uint32_t v1 = intRegs_.read(di->op1());
uint32_t res32 = (v1 >> rot) | (v1 << ((len - rot) & mask));
uint64_t res64 = int32_t(res32); // Sign extend to 64-bits.
intRegs_.write(di->op0(), res64);
}
template <typename URV>
void
Hart<URV>::execRev8(const DecodedInst* di)
{
// Byte swap.
if (not isRvzbb())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
if (mxlen_ == 32)
v1 = __builtin_bswap32(v1);
else
v1 = __builtin_bswap64(v1);
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execSext_b(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
int8_t byte = intRegs_.read(di->op1());
SRV value = byte;
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execSext_h(const DecodedInst* di)
{
if (not isRvzbb())
{
illegalInst(di);
return;
}
int16_t half = intRegs_.read(di->op1());
SRV value = half;
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execPack(const DecodedInst* di)
{
// Zext.h is a zbb pseudo-inst that maps to pack: pack rd, rs1, zero.
bool zext_h = (di->op2() == 0);
bool legal = isRvzbe() or isRvzbf() or isRvzbp();
legal = legal or (isRv64() and isRvzbm());
if (zext_h)
legal = legal or isRvzbb();
if (not legal)
{
illegalInst(di);
return;
}
unsigned halfXlen = mxlen_ >> 1;
URV lower = (intRegs_.read(di->op1()) << halfXlen) >> halfXlen;
URV upper = intRegs_.read(di->op2()) << halfXlen;
URV res = upper | lower;
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execSlli_uw(const DecodedInst* di)
{
if (not isRv64() or not isRvzba())
{
illegalInst(di);
return;
}
uint32_t amount(di->op2());
if (amount > 0x3f)
{
illegalInst(di); // Bits 6 of immediate must be zero.
return;
}
URV v1 = uint32_t(intRegs_.read(di->op1()));
URV value = v1 << amount;
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execPackh(const DecodedInst* di)
{
if (not isRvzbe() and not isRvzbf() and not isRvzbp())
{
illegalInst(di);
return;
}
URV lower = intRegs_.read(di->op1()) & 0xff;
URV upper = (intRegs_.read(di->op2()) & 0xff) << 8;
URV value = lower | upper;
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execPacku(const DecodedInst* di)
{
bool legal = isRvzbp() or (isRv64() and isRvzbm());
if (not legal)
{
illegalInst(di);
return;
}
unsigned halfXlen = mxlen_ >> 1;
URV lower = intRegs_.read(di->op1()) >> halfXlen;
URV upper = (intRegs_.read(di->op2()) >> halfXlen) << halfXlen;
URV value = lower | upper;
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execPackw(const DecodedInst* di)
{
// zext.h is an alias for packw and is part of zbb.
if (not isRv64() or (not isRvzbe() and not isRvzbf() and not isRvzbp()))
{
illegalInst(di);
return;
}
uint32_t v1 = intRegs_.read(di->op1());
uint32_t v2 = intRegs_.read(di->op2());
uint32_t lower = (v1 << 16) >> 16;
uint32_t upper = v2 << 16;
uint32_t value = lower | upper;
int64_t res = int32_t(value); // Sign extend.
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execPackuw(const DecodedInst* di)
{
if (not isRv64() or not isRvzbp())
{
illegalInst(di);
return;
}
uint32_t v1 = intRegs_.read(di->op1());
uint32_t v2 = intRegs_.read(di->op2());
uint32_t lower = v1 >> 16;
uint32_t upper = (v2 >> 16) << 16;
uint32_t value = lower | upper;
int64_t res = int32_t(value); // sign extend.
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execGrev(const DecodedInst* di)
{
if (not isRvzbp())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
URV v2 = intRegs_.read(di->op2());
if (mxlen_ == 32)
{
unsigned shamt = v2 & 31;
if (shamt & 1)
v1 = ((v1 & 0x55555555) << 1) | ((v1 & 0xaaaaaaaa) >> 1);
if (shamt & 2)
v1 = ((v1 & 0x33333333) << 2) | ((v1 & 0xcccccccc) >> 2);
if (shamt & 4)
v1 = ((v1 & 0x0f0f0f0f) << 4) | ((v1 & 0xf0f0f0f0) >> 4);
if (shamt & 8)
v1 = ((v1 & 0x00ff00ff) << 8) | ((v1 & 0xff00ff00) >> 8);
if (shamt & 16)
v1 = ((v1 & 0x0000ffff) << 16) | ((v1 & 0xffff0000) >> 16);
}
else
{
int shamt = v2 & 63;
if (shamt & 1)
v1 = ((v1 & 0x5555555555555555ll) << 1) | ((v1 & 0xaaaaaaaaaaaaaaaall) >> 1);
if (shamt & 2)
v1 = ((v1 & 0x3333333333333333ll) << 2) | ((v1 & 0xccccccccccccccccll) >> 2);
if (shamt & 4)
v1 = ((v1 & 0x0f0f0f0f0f0f0f0fll) << 4) | ((v1 & 0xf0f0f0f0f0f0f0f0ll) >> 4);
if (shamt & 8)
v1 = ((v1 & 0x00ff00ff00ff00ffll) << 8) | ((v1 & 0xff00ff00ff00ff00ll) >> 8);
if (shamt & 16)
v1 = ((v1 & 0x0000ffff0000ffffll) << 16) | ((v1 & 0xffff0000ffff0000ll) >> 16);
if (shamt & 32)
v1 = ((v1 & 0x00000000ffffffffll) << 32) | ((v1 & 0xffffffff00000000ll) >> 32);
}
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execGrevi(const DecodedInst* di)
{
URV shamt = di->op2();
bool zbb = false; // True if variant is also a zbb instruction.
if (isRv64())
zbb = shamt == 0x38; // rev8 is also in zbb
else
zbb = shamt == 0x18; // rev8 is also in zbb
bool illegal = not isRvzbp();
if (zbb)
illegal = not isRvzbb() and not isRvzbp();
if (illegal)
{
illegalInst(di);
return;
}
if (not checkShiftImmediate(di, shamt))
return;
URV v1 = intRegs_.read(di->op1());
if (mxlen_ == 32)
{
if (shamt & 1)
v1 = ((v1 & 0x55555555) << 1) | ((v1 & 0xaaaaaaaa) >> 1);
if (shamt & 2)
v1 = ((v1 & 0x33333333) << 2) | ((v1 & 0xcccccccc) >> 2);
if (shamt & 4)
v1 = ((v1 & 0x0f0f0f0f) << 4) | ((v1 & 0xf0f0f0f0) >> 4);
if (shamt & 8)
v1 = ((v1 & 0x00ff00ff) << 8) | ((v1 & 0xff00ff00) >> 8);
if (shamt & 16)
v1 = ((v1 & 0x0000ffff) << 16) | ((v1 & 0xffff0000) >> 16);
}
else
{
if (shamt & 1)
v1 = ((v1 & 0x5555555555555555ll) << 1) | ((v1 & 0xaaaaaaaaaaaaaaaall) >> 1);
if (shamt & 2)
v1 = ((v1 & 0x3333333333333333ll) << 2) | ((v1 & 0xccccccccccccccccll) >> 2);
if (shamt & 4)
v1 = ((v1 & 0x0f0f0f0f0f0f0f0fll) << 4) | ((v1 & 0xf0f0f0f0f0f0f0f0ll) >> 4);
if (shamt & 8)
v1 = ((v1 & 0x00ff00ff00ff00ffll) << 8) | ((v1 & 0xff00ff00ff00ff00ll) >> 8);
if (shamt & 16)
v1 = ((v1 & 0x0000ffff0000ffffll) << 16) | ((v1 & 0xffff0000ffff0000ll) >> 16);
if (shamt & 32)
v1 = ((v1 & 0x00000000ffffffffll) << 32) | ((v1 & 0xffffffff00000000ll) >> 32);
}
intRegs_.write(di->op0(), v1);
}
template <typename URV>
void
Hart<URV>::execGrevw(const DecodedInst* di)
{
if (not isRvzbp() or not isRv64())
{
illegalInst(di);
return;
}
URV v1 = intRegs_.read(di->op1());
uint32_t v2 = intRegs_.read(di->op2());
unsigned shamt = v2 & 31;
if (shamt & 1)
v1 = ((v1 & 0x55555555) << 1) | ((v1 & 0xaaaaaaaa) >> 1);
if (shamt & 2)
v1 = ((v1 & 0x33333333) << 2) | ((v1 & 0xcccccccc) >> 2);
if (shamt & 4)
v1 = ((v1 & 0x0f0f0f0f) << 4) | ((v1 & 0xf0f0f0f0) >> 4);
if (shamt & 8)
v1 = ((v1 & 0x00ff00ff) << 8) | ((v1 & 0xff00ff00) >> 8);
if (shamt & 16)
v1 = ((v1 & 0x0000ffff) << 16) | ((v1 & 0xffff0000) >> 16);
int64_t res = int32_t(v1); // Sign extend 32-bit to 64-bit.
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execGreviw(const DecodedInst* di)
{
URV shamt = di->op2();
bool zbb = false; // True if variant is also a zbb instruction.
if (isRv64())
zbb = shamt == 0x38; // rev8 is also in zbb
else
zbb = shamt == 0x18; // rev8 is also in zbb
bool illegal = not isRvzbp();
if (zbb)
illegal = not isRvzbb() and not isRvzbp();
if (illegal)
{
illegalInst(di);
return;
}
if (not checkShiftImmediate(di, shamt))
return;
unsigned v1 = intRegs_.read(di->op1());
if (shamt & 1)
v1 = ((v1 & 0x55555555) << 1) | ((v1 & 0xaaaaaaaa) >> 1);
if (shamt & 2)
v1 = ((v1 & 0x33333333) << 2) | ((v1 & 0xcccccccc) >> 2);
if (shamt & 4)
v1 = ((v1 & 0x0f0f0f0f) << 4) | ((v1 & 0xf0f0f0f0) >> 4);
if (shamt & 8)
v1 = ((v1 & 0x00ff00ff) << 8) | ((v1 & 0xff00ff00) >> 8);
if (shamt & 16)
v1 = ((v1 & 0x0000ffff) << 16) | ((v1 & 0xffff0000) >> 16);
int64_t res = int32_t(v1); // Sign extend 32-bit to 64-bit.
intRegs_.write(di->op0(), res);
}
template <typename URV>
void
Hart<URV>::execGorci(const DecodedInst* di)
{
URV shamt = di->op2();
bool orc_b = (shamt == 0x7); // orc.b is also in zbb
bool legal = isRvzbp();
if (orc_b)
legal = legal or isRvzbb();
if (not legal)
{
illegalInst(di);
return;
}
if (not checkShiftImmediate(di, shamt))
return;
URV v1 = intRegs_.read(di->op1());
if (mxlen_ == 32)
{
if (shamt & 1)
v1 |= ((v1 & 0xaaaaaaaa) >> 1) | ((v1 & 0x55555555) << 1);
if (shamt & 2)
v1 |= ((v1 & 0xcccccccc) >> 2) | ((v1 & 0x33333333) << 2);
if (shamt & 4)
v1 |= ((v1 & 0xf0f0f0f0) >> 4) | ((v1 & 0x0f0f0f0f) << 4);
if (shamt & 8)
v1 |= ((v1 & 0xff00ff00) >> 8) | ((v1 & 0x00ff00ff) << 8);
if (shamt & 16)
v1 |= ((v1 & 0xffff0000) >> 16) | ((v1 & 0x0000ffff) << 16);
intRegs_.write(di->op0(), v1);
return;
}
if constexpr (sizeof(URV) == 8)
{
if (shamt & 1)
v1 |= ((v1 & 0xaaaaaaaaaaaaaaaa) >> 1) | ((v1 & 0x5555555555555555) << 1);
if (shamt & 2)
v1 |= ((v1 & 0xcccccccccccccccc) >> 2) | ((v1 & 0x3333333333333333) << 2);
if (shamt & 4)
v1 |= ((v1 & 0xf0f0f0f0f0f0f0f0) >> 4) | ((v1 & 0x0f0f0f0f0f0f0f0f) << 4);
if (shamt & 8)
v1 |= ((v1 & 0xff00ff00ff00ff00) >> 8) | ((v1 & 0x00ff00ff00ff00ff) << 8);
if (shamt & 16)
v1 |= ((v1 & 0xffff0000ffff0000) >> 16) | ((v1 & 0x0000ffff0000ffff) << 16);
if (shamt & 32)
v1 |= ((v1 & 0xffffffff00000000) >> 32) | ((v1 & 0x00000000ffffffff) << 32);
intRegs_.write(di->op0(), v1);
}
else
assert(0 and "mxlen is 64 in rv32");
}
template <typename URV>
void
Hart<URV>::execGorciw(const DecodedInst* di)
{
URV shamt = di->op2();
bool orc_b = (shamt == 0x7); // orc.b is also in zbb
bool legal = isRvzbp() and isRv64();
if (orc_b)
legal = legal or isRvzbb();
if (not legal)
{
illegalInst(di);
return;
}
if (not checkShiftImmediate(di, shamt))
return;
uint32_t v1 = intRegs_.read(di->op1());
if (shamt & 1)
v1 |= ((v1 & 0xaaaaaaaa) >> 1) | ((v1 & 0x55555555) << 1);
if (shamt & 2)
v1 |= ((v1 & 0xcccccccc) >> 2) | ((v1 & 0x33333333) << 2);
if (shamt & 4)
v1 |= ((v1 & 0xf0f0f0f0) >> 4) | ((v1 & 0x0f0f0f0f) << 4);
if (shamt & 8)
v1 |= ((v1 & 0xff00ff00) >> 8) | ((v1 & 0x00ff00ff) << 8);
if (shamt & 16)
v1 |= ((v1 & 0xffff0000) >> 16) | ((v1 & 0x0000ffff) << 16);
int64_t res = int32_t(v1); // Sign extend 32-bit result to 64-bits.
intRegs_.write(di->op0(), res);
}
static
uint32_t
shuffleStage32(uint32_t src, uint32_t maskL, uint32_t maskR, unsigned n)
{
uint32_t x = src & ~(maskL | maskR);
x |= ((src << n) & maskL) | ((src >> n) & maskR);
return x;
}
static
uint32_t
shuffle32(uint32_t x, unsigned shamt)
{
if (shamt & 8)
x = shuffleStage32(x, 0x00ff0000, 0x0000ff00, 8);
if (shamt & 4)
x = shuffleStage32(x, 0x0f000f00, 0x00f000f0, 4);
if (shamt & 2)
x = shuffleStage32(x, 0x30303030, 0x0c0c0c0c, 2);
if (shamt & 1)
x = shuffleStage32(x, 0x44444444, 0x22222222, 1);
return x;
}
static
uint32_t
unshuffle32(uint32_t x, unsigned shamt)
{
if (shamt & 1)
x = shuffleStage32(x, 0x44444444, 0x22222222, 1);
if (shamt & 2)
x = shuffleStage32(x, 0x30303030, 0x0c0c0c0c, 2);
if (shamt & 4)
x = shuffleStage32(x, 0x0f000f00, 0x00f000f0, 4);
if (shamt & 8)
x = shuffleStage32(x, 0x00ff0000, 0x0000ff00, 8);
return x;
}
static
uint64_t
shuffleStage64(uint64_t src, uint64_t maskL, uint64_t maskR, unsigned n)
{
uint64_t x = src & ~(maskL | maskR);
x |= ((src << n) & maskL) | ((src >> n) & maskR);
return x;
}
static
uint64_t
shuffle64(uint64_t x, unsigned shamt)
{
if (shamt & 16)
x = shuffleStage64(x, 0x0000ffff00000000LL, 0x00000000ffff0000LL, 16);
if (shamt & 8)
x = shuffleStage64(x, 0x00ff000000ff0000LL, 0x0000ff000000ff00LL, 8);
if (shamt & 4)
x = shuffleStage64(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL, 4);
if (shamt & 2)
x = shuffleStage64(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL, 2);
if (shamt & 1)
x = shuffleStage64(x, 0x4444444444444444LL, 0x2222222222222222LL, 1);
return x;
}
static
uint64_t
unshuffle64(uint64_t x, unsigned shamt)
{
if (shamt & 1)
x = shuffleStage64(x, 0x4444444444444444LL, 0x2222222222222222LL, 1);
if (shamt & 2)
x = shuffleStage64(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL, 2);
if (shamt & 4)
x = shuffleStage64(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL, 4);
if (shamt & 8)
x = shuffleStage64(x, 0x00ff000000ff0000LL, 0x0000ff000000ff00LL, 8);
if (shamt & 16)
x = shuffleStage64(x, 0x0000ffff00000000LL, 0x00000000ffff0000LL, 16);
return x;
}
template <typename URV>
void
Hart<URV>::execBset(const DecodedInst* di)
{
if (not isRvzbs())
{
illegalInst(di);
return;
}
URV mask = shiftMask();
unsigned bitIx = intRegs_.read(di->op2()) & mask;
URV value = intRegs_.read(di->op1()) | (URV(1) << bitIx);
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execBclr(const DecodedInst* di)
{
if (not isRvzbs())
{
illegalInst(di);
return;
}
URV mask = shiftMask();
unsigned bitIx = intRegs_.read(di->op2()) & mask;
URV value = intRegs_.read(di->op1()) & ~(URV(1) << bitIx);
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execBinv(const DecodedInst* di)
{
if (not isRvzbs())
{
illegalInst(di);
return;
}
URV mask = shiftMask();
unsigned bitIx = intRegs_.read(di->op2()) & mask;
URV value = intRegs_.read(di->op1()) ^ (URV(1) << bitIx);
intRegs_.write(di->op0(), value);
}
template <typename URV>
void
Hart<URV>::execBext(const DecodedInst* di)
{
if (not isRvzbs())
{