Skip to content

Commit 2143b3b

Browse files
authored
Merge pull request #1283 from stlankes/toolchain
switch to the lastest nightly compiler
2 parents ad9bdc1 + a9a7906 commit 2143b3b

File tree

5 files changed

+14
-8
lines changed

5 files changed

+14
-8
lines changed

rust-toolchain.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
[toolchain]
2-
channel = "nightly-2024-06-01"
2+
channel = "nightly-2024-06-18"
33
components = [
44
"llvm-tools",
55
"rust-src",

src/arch/riscv64/kernel/scheduler.rs

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,8 @@ impl TaskStacks {
160160
unsafe {
161161
ptr::write_bytes(
162162
(virt_addr
163-
+ KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
163+
+ KERNEL_STACK_SIZE
164+
+ DEFAULT_STACK_SIZE
164165
+ 3 * BasePageSize::SIZE as usize)
165166
//(virt_addr + KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE)
166167
.as_mut_ptr::<u8>(),
@@ -198,7 +199,8 @@ impl TaskStacks {
198199
TaskStacks::Boot(_) => VirtAddr::zero(),
199200
TaskStacks::Common(stacks) => {
200201
stacks.virt_addr
201-
+ KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
202+
+ KERNEL_STACK_SIZE
203+
+ DEFAULT_STACK_SIZE
202204
+ 3 * BasePageSize::SIZE as usize
203205
//stacks.virt_addr + KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
204206
}
@@ -280,7 +282,7 @@ impl TaskTLS {
280282
// Yes, it does, so we have to allocate TLS memory.
281283
// Allocate enough space for the given size and one more variable of type usize, which holds the tls_pointer.
282284
let tls_allocation_size = tls_size.align_up(32usize); // + mem::size_of::<usize>();
283-
// We allocate in 128 byte granularity (= cache line size) to avoid false sharing
285+
// We allocate in 128 byte granularity (= cache line size) to avoid false sharing
284286
let memory_size = tls_allocation_size.align_up(128usize);
285287
let layout =
286288
Layout::from_size_align(memory_size, 128).expect("TLS has an invalid size / alignment");

src/arch/x86_64/kernel/apic.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -825,7 +825,8 @@ pub fn ipi_tlb_flush() {
825825
local_apic_write(
826826
IA32_X2APIC_ICR,
827827
destination
828-
| APIC_ICR_LEVEL_ASSERT | APIC_ICR_DELIVERY_MODE_FIXED
828+
| APIC_ICR_LEVEL_ASSERT
829+
| APIC_ICR_DELIVERY_MODE_FIXED
829830
| u64::from(TLB_FLUSH_INTERRUPT_NUMBER),
830831
);
831832
}

src/drivers/pci.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,8 @@ impl<T: ConfigRegionAccess> fmt::Display for PciDevice<T> {
283283
};
284284

285285
#[cfg(not(feature = "pci-ids"))]
286-
let (class_name, vendor_name, device_name) = ("Unknown Class", "Unknown Vendor", "Unknown Device");
286+
let (class_name, vendor_name, device_name) =
287+
("Unknown Class", "Unknown Vendor", "Unknown Device");
287288

288289
// Output detailed readable information about this device.
289290
write!(

src/fd/socket/tcp.rs

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -172,8 +172,10 @@ impl ObjectInterface for Socket {
172172
self.with(|socket| match socket.state() {
173173
tcp::State::Closed | tcp::State::Closing | tcp::State::CloseWait => {
174174
let available = PollEvent::POLLOUT
175-
| PollEvent::POLLWRNORM | PollEvent::POLLWRBAND
176-
| PollEvent::POLLIN | PollEvent::POLLRDNORM
175+
| PollEvent::POLLWRNORM
176+
| PollEvent::POLLWRBAND
177+
| PollEvent::POLLIN
178+
| PollEvent::POLLRDNORM
177179
| PollEvent::POLLRDBAND;
178180

179181
let ret = event & available;

0 commit comments

Comments
 (0)