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Commits on Jan 27, 2016

• tools: Fixed missing bang in launch_vivado

  mbr0wn

  committed
  b8b512d

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Commits on Jan 19, 2016

• x300: Updated ZPU firmware image

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  achaudhari

  committed
  2eef78e

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Commits on Jan 13, 2016

• n230: Updated firmware to compat 32

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  achaudhari

  committed
  9f2f5e9

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Commits on Jan 11, 2016

• tools: Modified setupenv to include searching soft links for Modelsim

  jpendlum

  committed
  c768ca3

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• sim: Moved simulation library system verilog (.sv) files to system verilog header (.svh) files

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  jpendlum

  committed
  2c9f5f9

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Commits on Jan 6, 2016

• n230: Cleaned up miniSAS connector interface

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  achaudhari

  committed
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Commits on Jan 5, 2016

• n230: Bumped FPGA compat number to 32

  achaudhari

  committed
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• usrp3: Added reset counter to sfc to make it tolerant to bubbles

  achaudhari

  committed
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Commits on Jan 4, 2016

• n230: SRAM buffer can sustain 2Gb/s throughput

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  achaudhari

  committed
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Commits on Jan 2, 2016

• n230: Redistributed buffering around ext sram FIFO

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  achaudhari

  committed
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Commits on Dec 31, 2015

• n230: Ethernet activity LED is now functional

  achaudhari

  committed
  0fcf8a1

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• n230: Updated image with latest firmware

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  achaudhari

  committed
  e107485

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• n230: Added dual SRAM FIFO

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  achaudhari

  committed
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• n230: Rewrote n230_core for dual-eth support

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  achaudhari

  committed
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Commits on Dec 28, 2015

• n230: Moved extfifo to its own module outside the core

  achaudhari

  committed
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Commits on Dec 26, 2015

• n230,x300: Added bootloader and RAM module in ZPU lib

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  achaudhari

  committed
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Commits on Dec 24, 2015

• n230: WIP: Wired PHY status signals to ZPU

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  achaudhari

  committed
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Commits on Dec 23, 2015

• n230: Added combined ethernet and jesd PHY

  achaudhari

  committed
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Commits on Dec 22, 2015

• n230: WIP: Checkpoint: Ethernet port0 working with dual PHY

  achaudhari

  committed
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• n230: Renamed gige_sfp0 IP to gige_phy

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  achaudhari

  committed
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Commits on Dec 21, 2015

• n230: Consolidate XDCs and always instantiate ext SRAM FIFO

  achaudhari

  committed
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• usrp3: Forked extramfifo and opencores spi sources to usrp3

  achaudhari

  committed
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• b2xx,n230: Moved radio to common location

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  achaudhari

  committed
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• n230: First checking for N230 device support

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  achaudhari

  committed
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• usrp3: Added wishbone ICAP module for 7-Series FPGAs

  achaudhari

  committed
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• cap_gen: Added AD936X LVDS capture and generation modules

  achaudhari

  committed
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• usrp3: Added flush capability to source_flow_control module

  achaudhari

  committed
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• Merge branch 'maint'

  achaudhari

  committed
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• Fix digital DC truncation bias in DDC chain.

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  ryanvolz

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  jpendlum

  committed
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Commits on Dec 18, 2015

• tools: Script usability improvements

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  achaudhari

  committed
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• usrp3, usrp2: Fixed inequal path delay in TX & RX I/Q balance compensation

  jpendlum

  committed
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Commits on Dec 15, 2015

• b2xx,e3xx,x300: Bumped FPGA compat numbers after incompatible maint merge

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  achaudhari

  committed
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• Merge branch 'maint'

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  achaudhari

  committed
  256d701

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• b2xx,e3xx,x300: Bumped FPGA compat nums: time-sync and SG3 support

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  achaudhari

  committed
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• e3xx: xdc: Fix overlap in .xdc files

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  Moritz Fischer

  authored and

  achaudhari

  committed
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