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STOP after a NACK
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+12
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+12
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src/i2c_core.sv

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -206,14 +206,20 @@ begin
206206
sda_internal <= 1'b1; // Should help reduce slave rise time
207207
end
208208
// See Section 3.1.6. Transmitter got an acknowledge bit or receiver sent it.
209-
// transaction continues immediately in the next LOW, latch now
209+
// transfer continues immediately in the next LOW, latch now
210+
// refuses to continue the transfer if receiver got a NACK
210211
else if (transaction_progress == 4'd10 && latched_transfer_continues)
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begin
212-
transaction_progress <= 4'd1;
213-
latched_mode <= mode;
214-
// if (!mode) // Mode doesn't matter, save some logic cells
215-
latched_data <= data_tx;
216-
latched_transfer_continues <= transfer_continues;
213+
if (!mode && nack)
214+
transaction_progress <= 4'd11; // TODO: if user set transfer_start when there's a NACK (they shouldn't) then there will be a repeated start
215+
else
216+
begin
217+
transaction_progress <= 4'd1;
218+
latched_mode <= mode;
219+
// if (!mode) // Mode doesn't matter, save some logic cells
220+
latched_data <= data_tx;
221+
latched_transfer_continues <= transfer_continues;
222+
end
217223
end
218224
// STOP condition
219225
else if (transaction_progress == 4'd11 && !transfer_start)

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