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sameersameer
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Several changes prior to first synthesis:
- Remove unneccessary busy in master if statements - Correct some one-off timing numbers - Fix clock testbench - Implement arbitration error for start by another master at the correct time
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5 files changed

+90
-87
lines changed

5 files changed

+90
-87
lines changed

‎README.md‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ Implementation of Inter-IC (I2C) bus master and slave, covering almost all edge
1010
- [x] SCL
1111
- [x] Clock stretching
1212
- [x] Clock synchronization (multi-master)
13+
- [ ] Handle early counter reset
1314
- [x] Stuck LOW line detection (bus clear via HW reset or Power-On Reset)
1415
- [x] Release line when bus is free / in use by another master
1516
- [x] Conformity to stop/repeated start setup & hold times
@@ -18,15 +19,15 @@ Implementation of Inter-IC (I2C) bus master and slave, covering almost all edge
1819
- [x] Receive
1920
- [x] Arbitration (multi-master)
2021
- [x] Basic Implementation
21-
- [ ] ~~Detect slower masters changing the value by looking at the value exactly at negedge(scl)~~
22+
- [x] Detect other masters triggering start before this master
2223
- [ ] Hotloading (not from i2c spec)
2324
- [ ] Self
2425
- compensating for jitter of wires connecting/disconnecting... (Schmitt enough?)
2526
- listen for WAIT_TIME_END to see if the clock is driven LOW
2627
- if no: bus is free
2728
- if yes: keep listening until a STOP or START
2829
- [x] Other masters
29-
- erroneous starts detected w/ start_err
30+
- [x] erroneous starts detected w/ start_err
3031
- [x] Port map
3132
- Slave
3233
- [ ] SCL
@@ -41,5 +42,5 @@ Implementation of Inter-IC (I2C) bus master and slave, covering almost all edge
4142

4243
## Reference Documents
4344

44-
* [I2C Specification](https://www.nxp.com/docs/en/user-guide/UM10204.pdf)
45-
* [Understanding the I2C Bus](http://www.ti.com/lit/an/slva704/slva704.pdf)
45+
- [I2C Specification](https://www.nxp.com/docs/en/user-guide/UM10204.pdf)
46+
- [Understanding the I2C Bus](http://www.ti.com/lit/an/slva704/slva704.pdf)

‎src/clock.sv‎

Lines changed: 22 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -19,15 +19,11 @@ module clock #(
1919
logic scl_internal = 1'b1;
2020
assign scl = scl_internal ? (PUSH_PULL ? 1'b1 : 1'bz) : 1'b0;
2121

22-
logic scl_held_low;
23-
assign scl_held_low = !scl && counter > COUNTER_HIGH + COUNTER_RISE && !PUSH_PULL;
24-
2522
logic last_scl = 1'b1;
26-
`ifdef MODEL_TECH
2723
always @(posedge clk_in)
24+
`ifdef MODEL_TECH
2825
last_scl <= scl === 1'bz;
2926
`else
30-
always @(posedge clk_in) // Last observed scl value, assuming scl noise was smoothed with a Schmitt trigger
3127
last_scl <= scl;
3228
`endif
3329

@@ -43,30 +39,28 @@ begin
4339
wait_counter <= WAIT_WIDTH'(0);
4440
scl_internal <= 1'b1;
4541
end
42+
// See Figure 7, counter reset. SCL becomes LOW prematurely.
43+
// Detects a falling edge during a counter-sized interval
44+
else if (last_scl && !scl && (counter == COUNTER_WIDTH'(0) || counter >= COUNTER_HIGH + COUNTER_RISE) && MULTI_MASTER)
45+
begin
46+
counter <= COUNTER_WIDTH'(1);
47+
wait_counter <= WAIT_WIDTH'(0);
48+
scl_internal <= 1'b0;
49+
end
50+
// See Figure 7, wait state. SCL is being held LOW by another device after SCL should have risen.
51+
else if (!scl && (counter == COUNTER_HIGH + COUNTER_RISE) && !PUSH_PULL && (CLOCK_STRETCHING || MULTI_MASTER))
52+
begin
53+
counter <= COUNTER_HIGH + COUNTER_RISE;
54+
if (wait_counter < WAIT_END) // Saturates to indicate bus clear condition
55+
wait_counter <= wait_counter + 1'd1;
56+
scl_internal <= 1'b1;
57+
end
4658
else if (counter >= COUNTER_HIGH)
4759
begin
48-
// See Figure 7, counter reset. SCL becomes LOW prematurely.
49-
// TODO: how to detect a falling edge during the allocated rise time?
50-
if (last_scl && scl_held_low && MULTI_MASTER)
51-
begin
52-
counter <= COUNTER_WIDTH'(0);
53-
wait_counter <= WAIT_WIDTH'(0);
54-
scl_internal <= 1'b0;
55-
end
56-
// See Figure 7, wait state. SCL is being held LOW by another device.
57-
if (scl_held_low && (CLOCK_STRETCHING || MULTI_MASTER))
58-
begin
59-
counter <= counter;
60-
if (wait_counter < WAIT_END) // Saturates to indicate bus clear condition
61-
wait_counter <= wait_counter + 1'd1;
62-
scl_internal <= 1'b1;
63-
end
64-
else // See Figure 7, counting HIGH period
65-
begin
66-
counter <= counter == COUNTER_END ? COUNTER_WIDTH'(0) : counter + 1'd1;
67-
wait_counter <= WAIT_WIDTH'(0);
68-
scl_internal <= 1'b1;
69-
end
60+
// See Figure 7, counting HIGH period
61+
counter <= counter == COUNTER_END ? COUNTER_WIDTH'(0) : counter + 1'd1;
62+
wait_counter <= WAIT_WIDTH'(0);
63+
scl_internal <= 1'b1;
7064
end
7165
else // LOW period counting
7266
begin
@@ -76,4 +70,4 @@ begin
7670
end
7771
end
7872

79-
endmodule
73+
endmodule

‎src/master.sv‎

Lines changed: 33 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -49,25 +49,26 @@ module master #(
4949
localparam MODE = $unsigned(TARGET_SCL_RATE) <= 100000 ? 0 : $unsigned(TARGET_SCL_RATE) <= 400000 ? 1 : $unsigned(TARGET_SCL_RATE) <= 1000000 ? 2 : -1;
5050

5151
localparam COUNTER_WIDTH = $clog2($unsigned(INPUT_CLK_RATE) / $unsigned(TARGET_SCL_RATE));
52-
localparam COUNTER_END = COUNTER_WIDTH'($unsigned(INPUT_CLK_RATE) / $unsigned(TARGET_SCL_RATE) - 1);
52+
localparam COUNTER_END = COUNTER_WIDTH'($ceil($unsigned(INPUT_CLK_RATE) / $unsigned(TARGET_SCL_RATE)) - 1);
5353
// Conforms to Table 10 tLOW, tHIGH for SCL clock.
5454
localparam COUNTER_HIGH = COUNTER_WIDTH'(MODE == 0 ? ( (COUNTER_WIDTH + 1)'(COUNTER_END) + 1) / 2 : (( (COUNTER_WIDTH + 2)'(COUNTER_END) + 1) * 2) / 3);
5555
// Conforms to Table 10 tr (rise time) for SCL clock.
5656
localparam COUNTER_RISE = COUNTER_WIDTH'($ceil($unsigned(INPUT_CLK_RATE) / 1.0E9 * $unsigned(MODE == 0 ? 1000 : MODE == 1 ? 300 : MODE == 2 ? 120 : 0)));
5757

5858
// Bus clear event counter
59-
localparam WAIT_WIDTH = $clog2(2 * $unsigned(INPUT_CLK_RATE) / $unsigned(SLOWEST_DEVICE_RATE));
60-
localparam WAIT_END = WAIT_WIDTH'(2 * $unsigned(INPUT_CLK_RATE) / $unsigned(SLOWEST_DEVICE_RATE) - 1);
59+
localparam WAIT_WIDTH = $clog2($unsigned(INPUT_CLK_RATE) / $unsigned(SLOWEST_DEVICE_RATE));
60+
localparam WAIT_END = WAIT_WIDTH'($ceil($unsigned(INPUT_CLK_RATE) / $unsigned(SLOWEST_DEVICE_RATE)) - 1);
6161

6262
logic [COUNTER_WIDTH-1:0] counter;
63-
// stick counter
63+
// stick counter used to meet timing requirements
6464
logic [COUNTER_WIDTH-1:0] countdown = COUNTER_WIDTH'(0);
65+
6566
// assume bus is free
6667
logic busy = 1'b0;
6768
logic [3:0] transaction_progress = 4'd0;
6869

6970
logic release_line;
70-
assign release_line = (!busy && transaction_progress == 4'd0) || countdown > 0 || (busy && transaction_progress == 4'd0 && MULTI_MASTER);
71+
assign release_line = transaction_progress == 4'd0 || countdown > 0;
7172

7273
clock #(
7374
.COUNTER_WIDTH(COUNTER_WIDTH),
@@ -120,13 +121,13 @@ end
120121
// Conforms to Table 10 minimum setup/hold/bus free times.
121122
localparam TLOW_MIN = MODE == 0 ? 4.7 : MODE == 1 ? 1.3 : MODE == 2 ? 0.5 : 0; // in microseconds
122123
localparam THIGH_MIN = MODE == 0 ? 4.0 : MODE == 1 ? 0.6 : MODE == 2 ? 0.26 : 0; // in microseconds
123-
localparam COUNTER_SETUP_REPEATED_START = COUNTER_WIDTH'($ceil($unsigned(INPUT_CLK_RATE)/1E6 * TLOW_MIN));
124-
localparam COUNTER_HOLD_REPEATED_START = COUNTER_WIDTH'($ceil($unsigned(INPUT_CLK_RATE)/1E6 * THIGH_MIN));
125-
localparam COUNTER_SETUP_STOP = COUNTER_HOLD_REPEATED_START;
124+
localparam COUNTER_SETUP_REPEATED_START = COUNTER_WIDTH'($floor($unsigned(INPUT_CLK_RATE) / 1.0E6 * TLOW_MIN));
126125
localparam COUNTER_BUS_FREE = COUNTER_SETUP_REPEATED_START;
126+
localparam COUNTER_HOLD_REPEATED_START = COUNTER_WIDTH'($floor($unsigned(INPUT_CLK_RATE) / 1.0E6 * THIGH_MIN));
127+
localparam COUNTER_SETUP_STOP = COUNTER_HOLD_REPEATED_START;
127128

128129
localparam COUNTER_TRANSMIT = COUNTER_WIDTH'(COUNTER_HIGH / 2);
129-
localparam COUNTER_RECEIVE = COUNTER_WIDTH'((COUNTER_END - COUNTER_HIGH + 1) / 2 + COUNTER_HIGH);
130+
localparam COUNTER_RECEIVE = COUNTER_WIDTH'(COUNTER_HIGH + COUNTER_RISE);
130131

131132
logic latched_mode;
132133
logic [7:0] latched_data;
@@ -140,11 +141,13 @@ always @(posedge clk_in)
140141
begin
141142
start_err = start_by_another_master;
142143

143-
// transmitter listens for loss of arbitration on receive
144-
// treats a start by another master as no loss of arbitration
145-
arbitration_err = counter == COUNTER_RECEIVE && busy && transaction_progress >= 4'd2 && transaction_progress < 4'd10 && !latched_mode && MULTI_MASTER && sda != latched_data[4'd9 - transaction_progress] && !start_by_another_master;
144+
// transmitter listens for loss of arbitration
145+
// either another master won during a tranmission
146+
// or another master issued a start condition before this master could
147+
arbitration_err = MULTI_MASTER && ((counter == COUNTER_RECEIVE && transaction_progress >= 4'd2 && transaction_progress < 4'd10 && !latched_mode && sda != latched_data[4'd9 - transaction_progress] && !start_by_another_master)
148+
|| (counter == COUNTER_RECEIVE && countdown == COUNTER_WIDTH'(0) && transaction_progress == 4'd1 && busy && transfer_start));
146149

147-
transaction_complete = counter == COUNTER_RECEIVE - 1 && busy && transaction_progress == 4'd10 && !start_by_another_master;
150+
transaction_complete = counter == COUNTER_RECEIVE - 1 && transaction_progress == 4'd10 && !start_by_another_master;
148151
// transmitter notes whether ACK/NACK was received
149152
// receiver notes whether ACK/NACK was sent
150153
// treats a start by another master as as an ACK
@@ -161,20 +164,21 @@ begin
161164
begin
162165
sda_internal <= 1'b1; // release line
163166
transaction_progress <= 4'd0;
164-
start_by_another_master <= 1'b0; // synchronous reset
167+
start_by_another_master <= 1'b0; // synchronous reset of flag
165168
countdown <= COUNTER_WIDTH'(0);
166169
end
167-
// Keep current state to meet setup/hold constraints
168-
else if (countdown > 0)
170+
// Keep current state to meet setup/hold constraints in Table 10.
171+
else if (countdown != COUNTER_WIDTH'(0))
169172
begin
170173
countdown <= countdown - 1'b1;
171174
end
172175
else if (counter == COUNTER_HIGH)
173176
begin
174-
// TODO: what if the user saw transfer_ready and put in some stuff, but then busy went high before COUNTER_RECEIVE and now the transaction can't start? user thinks transaction began but it didn't, and there should be an arbitration error later on
175-
if (((!busy && transaction_progress == 4'd0) || (busy && transaction_progress == 4'd11)) && transfer_start)
177+
if ((transaction_progress == 4'd0 || transaction_progress == 4'd11) && transfer_start)
176178
begin
177-
transaction_progress <= 4'd1;
179+
if (transaction_progress == 4'd0)
180+
transaction_progress <= 4'd1;
181+
178182
latched_mode <= mode;
179183
// if (!mode) // Mode doesn't matter, save some logic cells
180184
latched_data <= data_tx;
@@ -191,29 +195,30 @@ begin
191195
// "The data on the SDA line must be stable during the HIGH period of the clock."
192196
else if (counter == COUNTER_RECEIVE)
193197
begin
194-
if (transaction_progress > 0)
198+
// Another master is doing a transaction (void messages tolerated, see Note 5 in Section 3.1.10)
199+
if (transaction_progress == 4'd0 && MULTI_MASTER)
200+
sda_internal <= 1'b1;
195201
// START or repeated START condition
196-
if (!busy && (transaction_progress == 4'd1 || transaction_progress == 4'd11))
202+
else if ((transaction_progress == 4'd1 || transaction_progress == 4'd11) && transfer_start)
197203
begin
198204
sda_internal <= 1'b0;
199205
if (transaction_progress == 4'd11) // Hold time padding
200206
countdown <= COUNTER_HOLD_REPEATED_START - (COUNTER_END - COUNTER_RECEIVE);
201207
end
202208
// See Section 3.1.5. Shift in data.
203-
else if (busy && transaction_progress >= 4'd2 && transaction_progress < 4'd10 && latched_mode)
209+
else if (transaction_progress >= 4'd2 && transaction_progress < 4'd10 && latched_mode)
204210
begin
205211
`ifdef MODEL_TECH
206212
latched_data[4'd9 - transaction_progress] <= sda === 1'bz;
207213
`else
208214
latched_data[4'd9 - transaction_progress] <= sda;
209215
`endif
210-
sda_internal <= 1'b1; // Helps reduce slave rise time
216+
sda_internal <= 1'b1; // Should help reduce slave rise time
211217
end
212218
// See Section 3.1.6. Transmitter got an acknowledge bit or receiver sent it.
213-
// sda value must be ACK, agnostic of transmit/receive
214219
// transaction continues immediately in the next LOW, latch now
215220
// delayed by a clock here so that user input after transaction_complete can be ready
216-
else if (busy && transaction_progress == 4'd10 && latched_transfer_continue && !sda)
221+
else if (transaction_progress == 4'd10 && latched_transfer_continue)
217222
begin
218223
transaction_progress <= 4'd1;
219224
latched_mode <= mode;
@@ -222,18 +227,15 @@ begin
222227
latched_transfer_continue <= transfer_continue;
223228
end
224229
// STOP condition
225-
else if (busy && transaction_progress == 4'd11 && !sda)
230+
else if (transaction_progress == 4'd11 && !transfer_start)
226231
begin
227232
sda_internal <= 1'b1;
228233
transaction_progress <= 4'd0;
229234
countdown <= COUNTER_BUS_FREE - (COUNTER_END - COUNTER_RECEIVE);
230235
end
231-
// Another master is doing a transaction (void messages tolerated, see Note 5 in Section 3.1.10)
232-
else if (busy && transaction_progress == 4'd0 && MULTI_MASTER)
233-
sda_internal <= 1'b1;
234236
end
235237
// "The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW"
236-
else if (counter == COUNTER_TRANSMIT && busy && transaction_progress != 4'd0)
238+
else if (counter == COUNTER_TRANSMIT && transaction_progress != 4'd0)
237239
begin
238240
transaction_progress <= transaction_progress + 4'd1;
239241
// See Section 3.1.5. Shift out data.
@@ -246,12 +248,10 @@ begin
246248
end
247249
// See Section 3.1.6. Expecting an acknowledge bit transfer in the next HIGH.
248250
else if (transaction_progress == 4'd9)
249-
sda_internal <= !(latched_mode && latched_transfer_continue); // receiver sends ACK / NACK, transmitter releases line
251+
sda_internal <= !latched_mode || !latched_transfer_continue; // receiver sends ACK / NACK, transmitter releases line
250252
// See Section 3.1.4
251253
else if (transaction_progress == 4'd10)
252-
begin
253254
sda_internal <= transfer_start; // prepare for repeated START condition or STOP condition
254-
end
255255
end
256256
end
257257

‎test/clock_tb.sv‎

Lines changed: 28 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@ module clock_tb();
22

33

44

5-
localparam INPUT_CLK_RATE = $unsigned(500000);
5+
localparam INPUT_CLK_RATE = $unsigned(400000);
66
localparam TARGET_SCL_RATE = $unsigned(100000);
7-
localparam SLOWEST_MASTER_RATE = $unsigned(10000);
7+
localparam SLOWEST_DEVICE_RATE = $unsigned(10000);
88

99
logic scl_in = 1'bz; // Initially, no other master present
1010

@@ -16,18 +16,25 @@ logic clk_in = 1'b0;
1616
always #2 clk_in = ~clk_in;
1717
logic bus_clear;
1818

19-
localparam COUNTER_WIDTH = $clog2(INPUT_CLK_RATE / TARGET_SCL_RATE);
20-
localparam COUNTER_END = COUNTER_WIDTH'(INPUT_CLK_RATE / TARGET_SCL_RATE - 1);
19+
localparam MODE = $unsigned(TARGET_SCL_RATE) <= 100000 ? 0 : $unsigned(TARGET_SCL_RATE) <= 400000 ? 1 : $unsigned(TARGET_SCL_RATE) <= 1000000 ? 2 : -1;
20+
localparam COUNTER_WIDTH = $clog2($unsigned(INPUT_CLK_RATE) / $unsigned(TARGET_SCL_RATE));
21+
localparam COUNTER_END = COUNTER_WIDTH'($unsigned(INPUT_CLK_RATE) / $unsigned(TARGET_SCL_RATE) - 1);
2122
// Conforms to Table 10 tLOW, tHIGH for SCL clock.
22-
localparam COUNTER_HIGH = COUNTER_WIDTH'(COUNTER_END / 2);
23-
localparam WAIT_WIDTH = $clog2(2 * INPUT_CLK_RATE / SLOWEST_MASTER_RATE);
24-
localparam WAIT_END = WAIT_WIDTH'(2 * INPUT_CLK_RATE / SLOWEST_MASTER_RATE - 1);
25-
logic [$clog2(COUNTER_END)-1:0] counter;
26-
clock #(.COUNTER_WIDTH(COUNTER_WIDTH), .COUNTER_END(COUNTER_END), .COUNTER_HIGH(COUNTER_HIGH), .COUNTER_RISE(0), .MULTI_MASTER(1), .CLOCK_STRETCHING(1), .WAIT_WIDTH(WAIT_WIDTH), .WAIT_END(WAIT_END)) clock(.scl(scl), .clk_in(clk_in), .release_line(1'b0), .bus_clear(bus_clear), .counter(counter));
23+
localparam COUNTER_HIGH = COUNTER_WIDTH'(MODE == 0 ? ( (COUNTER_WIDTH + 1)'(COUNTER_END) + 1) / 2 : (( (COUNTER_WIDTH + 2)'(COUNTER_END) + 1) * 2) / 3);
24+
// Conforms to Table 10 tr (rise time) for SCL clock.
25+
localparam COUNTER_RISE = COUNTER_WIDTH'($ceil($unsigned(INPUT_CLK_RATE) / 1.0E9 * $unsigned(MODE == 0 ? 1000 : MODE == 1 ? 300 : MODE == 2 ? 120 : 0)));
2726

27+
// Bus clear event counter
28+
localparam WAIT_WIDTH = $clog2(2 * $unsigned(INPUT_CLK_RATE) / $unsigned(SLOWEST_DEVICE_RATE));
29+
localparam WAIT_END = WAIT_WIDTH'(2 * $unsigned(INPUT_CLK_RATE) / $unsigned(SLOWEST_DEVICE_RATE) - 1);
30+
logic [COUNTER_WIDTH-1:0] counter;
31+
clock #(.COUNTER_WIDTH(COUNTER_WIDTH), .COUNTER_END(COUNTER_END), .COUNTER_HIGH(COUNTER_HIGH), .COUNTER_RISE(1), .MULTI_MASTER(1), .CLOCK_STRETCHING(1), .WAIT_WIDTH(WAIT_WIDTH), .WAIT_END(WAIT_END)) clock(.scl(scl), .clk_in(clk_in), .release_line(1'b0), .bus_clear(bus_clear), .counter(counter));
32+
33+
logic [COUNTER_WIDTH-1:0] last_counter = COUNTER_HIGH;
2834
always @(posedge clk_in)
2935
begin
30-
if (clock.counter < COUNTER_HIGH)
36+
last_counter <= counter;
37+
if (last_counter < COUNTER_HIGH)
3138
assert (scl === 1'b0) else $fatal(1, "High when counter hasn't risen: %b", scl);
3239
else if (!inoutmode)
3340
begin
@@ -37,29 +44,30 @@ end
3744

3845
initial
3946
begin
40-
assert(COUNTER_WIDTH == 3) else $fatal(1, "Counter width should be 3 but was %d", COUNTER_WIDTH);
41-
assert(COUNTER_END == 4) else $fatal(1, "Counter end should be 4 but was %d", COUNTER_END);
47+
assert(COUNTER_WIDTH == 2) else $fatal(1, "Counter width should be 3 but was %d", COUNTER_WIDTH);
48+
assert(COUNTER_END == 3) else $fatal(1, "Counter end should be 4 but was %d", COUNTER_END);
4249
#100ns;
4350
$display("Testing bus clear");
44-
wait (scl == 1'b0 && clk_in == 1'b0);
51+
wait (!scl && !clk_in && counter == COUNTER_HIGH);
4552
scl_in <= 1'b0;
4653
inoutmode <= 1'b1;
47-
#400ps;
54+
#310ps;
4855
assert (!clock.bus_clear) else $fatal(1, "Bus clear asserted early");
49-
#12ps;
56+
#50ps;
5057
assert (clock.bus_clear) else $fatal(1, "Bus clear not asserted when SCL line stuck");
5158
scl_in <= 1'bz;
52-
inoutmode <= 1'b1;
5359
#6ps;
5460
assert (!clock.bus_clear) else $fatal(1, "Bus clear asserted after SCL line released");
61+
inoutmode <= 1'b0;
5562

63+
#1ns;
5664
$display("Testing reset");
57-
#10ns;
58-
wait (scl === 1'bz && clk_in == 1'b0);
65+
wait (scl === 1'bz && !clk_in && counter == 0);
5966
scl_in <= 1'b0;
6067
inoutmode <= 1'b1;
61-
#4ps;
62-
assert (clock.counter == 0) else $fatal(1, "Counter did not reset after early drive to low");
68+
wait (clk_in);
69+
wait (!clk_in);
70+
assert (counter == 1) else $fatal(1, "Counter did not reset after early drive to low");
6371
scl_in <= 1'bz;
6472
inoutmode <= 1'b0;
6573

‎test/master_tb.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ module master_tb();
22

33
localparam INPUT_CLK_RATE = 400000;
44
localparam TARGET_SCL_RATE = 100000;
5-
localparam SLOWEST_MASTER_RATE = 10000;
5+
localparam SLOWEST_DEVICE_RATE = 10000;
66

77
logic sda_in = 1'bz;
88
logic inoutmode = 1'b0;
@@ -32,7 +32,7 @@ master #(
3232
.TARGET_SCL_RATE(TARGET_SCL_RATE),
3333
.CLOCK_STRETCHING(0),
3434
.MULTI_MASTER(0),
35-
.SLOWEST_MASTER_RATE(SLOWEST_MASTER_RATE),
35+
.SLOWEST_DEVICE_RATE(SLOWEST_DEVICE_RATE),
3636
.FORCE_PUSH_PULL(0)
3737
) master (
3838
.scl(scl),

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