TinyUSB does not build on CM4 core inside RT117x

[mastupristi]

I have a custom FW very similar to the examples/device/cdc_uac2 example that runs well on the CM7 core of RT117x.
If I try to compile it on CM4 it fails the build though. The compile fails because for the CM4 core the functions SCB_CleanDCache_by_Addr, SCB_InvalidateDCache_by_Addr and SCB_CleanInvalidateDCache_by_Addr are not defined.
Is this a bug or a new feature (I mean the one to allow execution on the non-primary core of multicore socs)?
If you want, there is the __DCACE_PRESENT symbol that might help.
For the CM7 core it is defined 1 (in the file MIMXRT1175_cm7.h), while for the CM4 core (in the file MIMXRT1175_cm4.h) it is not defined at all.
Could you give me a suggestion to move forward in my work? is it enough to simply comment the inside of the functions that cause the error?

best regards
Max

[HiFiPhile]

The compile fails because for the CM4 core the functions SCB_CleanDCache_by_Addr, SCB_InvalidateDCache_by_Addr and SCB_CleanInvalidateDCache_by_Addr are not defined.

It's a issue with cache management functions, since DCACHE is not present on CM4 these functions are not available.

You can try to comment out these lines.

PS: I'd like to remove these cache functions and instead provide a MPU example setting to mark USB buffer sections non-cacheable. Since frequent cache clean invalidate hurt performance and prone to data synchronization issues. But I can only theorycrafting since I don't have dev board...

[mastupristi]

It's a issue with cache management functions, since DCACHE is not present on CM4 these functions are not available.

Are you in charge of entering this issue into the issue tracking system?

best regards
Max

[HiFiPhile]

It could depend on your testing, if it's trial to fix with something like #ifd __DCACE_PRESENT you (or me) can make a PR, otherwise I'd like to left it for someone with dev board.

[mastupristi]

I will be able to test #if __DCACE_PRESENT using my (custom) app on my custom hw. However I am not sufficiently skilled on cache issues. If I see something working I will not know if it will work in every condition.

[mastupristi]

It seems that it is not so simple.
CM7 has both L1 and L2 caches, and CM4 has only L1 cache.
SCB_*DCache_by_Addr() on CM7 are equivalent to L1CACHE_*DCacheByRange() (see https://github.com/nxp-mcuxpresso/mcux-sdk/blob/main/devices/MIMXRT1175/drivers/cm7/fsl_cache.h#L227).
As said CM4 lacks the functions SCB_*DCache_by_Addr() but has L1CACHE_*DCacheByRange() (I cannot figure out why mxrt_dcache_*() functions call SCB_*DCache_by_Addr() and not L1CACHE_*DCacheByRange()), so I patched src/portable/chipidea/ci_hs/ci_hs_imxrt.h to call L1CACHE_*DCacheByRange() instead of SCB_*DCache_by_Addr().
However this on CM4 still does not work. Tinyusb only trace bus reset events.
Note that to check the “goodness” of the code I also ran it on CM7 (I'm not talking about recompiling for CM7, but just running on CM7 the code compiled for CM4). Well, on CM7 it works perfectly.
NXP's SDK contains an example of USB running on CM4 and (obviously) it works. I tried to follow its execution step-by-step, and found no obvious differences from what tinyusb does.
Thats why I opened a feature request (#2849)

best regards
Max