datapath_tb1.vcd

$date
	Thu Oct 26 23:49:55 2023
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module data_path_tb $end
$var wire 8 ! z [7:0] $end
$var wire 1 " done_yn $end
$var wire 1 # done_write_wn $end
$var wire 1 $ done_wn1 $end
$var wire 1 % done_read_Xn $end
$var wire 1 & done_read_Dn $end
$var wire 1 ' done_en $end
$var reg 8 ( Dn [7:0] $end
$var reg 8 ) Wn [7:0] $end
$var reg 8 * Xn [7:0] $end
$var reg 1 + clock $end
$var reg 8 , data_in [7:0] $end
$var reg 1 - e_active $end
$var reg 1 . memory_Dn_active $end
$var reg 1 / memory_Xn_active $end
$var reg 1 0 memory_bobot_active $end
$var reg 1 1 sys_reset_active $end
$var reg 1 2 w_active $end
$var reg 1 3 y_active $end
$var integer 32 4 dn_file [31:0] $end
$var integer 32 5 line_num [31:0] $end
$var integer 32 6 wn_file [31:0] $end
$var integer 32 7 xn_file [31:0] $end
$scope module uut $end
$var wire 8 8 Dn [7:0] $end
$var wire 8 9 Wn [7:0] $end
$var wire 8 : Xn [7:0] $end
$var wire 1 + clock $end
$var wire 1 - e_active $end
$var wire 8 ; keluaran_Dn [7:0] $end
$var wire 8 < keluaran_Wn [7:0] $end
$var wire 8 = keluaran_Xn [7:0] $end
$var wire 8 > keluaran_pembaruan_bobot [7:0] $end
$var wire 1 . memory_Dn_active $end
$var wire 1 / memory_Xn_active $end
$var wire 1 0 memory_bobot_active $end
$var wire 1 1 sys_reset_active $end
$var wire 1 2 w_active $end
$var wire 1 3 y_active $end
$var wire 8 ? z [7:0] $end
$var wire 16 @ keluaran_vedic [15:0] $end
$var wire 8 A keluaran_memory [7:0] $end
$var wire 8 B keluaran_en [7:0] $end
$var wire 1 " done_yn $end
$var wire 1 # done_write_wn $end
$var wire 1 $ done_wn1 $end
$var wire 1 % done_read_Xn $end
$var wire 1 & done_read_Dn $end
$var wire 1 ' done_en $end
$scope module delapan_bit_gabung_coba_1 $end
$var wire 16 C Output_SO [15:0] $end
$var wire 16 D Output_buff [15:0] $end
$var wire 2 E Sign_OP_Check [1:0] $end
$var wire 9 F a_extd [8:0] $end
$var wire 8 G aa [7:0] $end
$var wire 9 H add_SO [8:0] $end
$var wire 8 I b [7:0] $end
$var wire 1 J cin $end
$var wire 1 + clock $end
$var wire 1 K done_cout $end
$var wire 1 " done_delapanbitgabungcoba $end
$var wire 1 3 enable $end
$var wire 1 1 reset $end
$var wire 1 L s8 $end
$var wire 9 M twosc [8:0] $end
$var wire 1 N untukmemory_cout $end
$var wire 16 O untukmemory [15:0] $end
$var wire 8 P s9 [7:0] $end
$var wire 8 Q s7 [7:0] $end
$var wire 8 R s6 [7:0] $end
$var wire 8 S s5 [7:0] $end
$var wire 8 T s4 [7:0] $end
$var wire 8 U s3 [7:0] $end
$var wire 8 V s2 [7:0] $end
$var wire 8 W s1 [7:0] $end
$var wire 16 X q [15:0] $end
$var wire 1 Y done_q $end
$var wire 1 Z cout_s6 $end
$var wire 1 [ cout_s5 $end
$var wire 1 \ cout $end
$var wire 16 ] c [15:0] $end
$var wire 8 ^ bb [7:0] $end
$var wire 8 _ a [7:0] $end
$scope begin g_sign_op[0] $end
$upscope $end
$scope begin g_sign_op[1] $end
$upscope $end
$scope begin g_sign_op[2] $end
$upscope $end
$scope begin g_sign_op[3] $end
$upscope $end
$scope begin g_sign_op[4] $end
$upscope $end
$scope begin g_sign_op[5] $end
$upscope $end
$scope begin g_sign_op[6] $end
$upscope $end
$scope module MCC_8bit_1 $end
$var wire 8 ` Sum [7:0] $end
$var wire 8 a P [7:0] $end
$var wire 8 b G [7:0] $end
$var wire 1 [ Cout $end
$var wire 9 c C [8:0] $end
$var wire 8 d B [7:0] $end
$var wire 8 e A [7:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope begin genblk1[4] $end
$upscope $end
$scope begin genblk1[5] $end
$upscope $end
$scope begin genblk1[6] $end
$upscope $end
$scope begin genblk1[7] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 f A $end
$var wire 1 g B $end
$var wire 1 h G $end
$var wire 1 i P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 j A $end
$var wire 1 k B $end
$var wire 1 l G $end
$var wire 1 m P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 n A $end
$var wire 1 o B $end
$var wire 1 p G $end
$var wire 1 q P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 r A $end
$var wire 1 s B $end
$var wire 1 t G $end
$var wire 1 u P $end
$upscope $end
$scope module GP[4] $end
$var wire 1 v A $end
$var wire 1 w B $end
$var wire 1 x G $end
$var wire 1 y P $end
$upscope $end
$scope module GP[5] $end
$var wire 1 z A $end
$var wire 1 { B $end
$var wire 1 | G $end
$var wire 1 } P $end
$upscope $end
$scope module GP[6] $end
$var wire 1 ~ A $end
$var wire 1 !" B $end
$var wire 1 "" G $end
$var wire 1 #" P $end
$upscope $end
$scope module GP[7] $end
$var wire 1 $" A $end
$var wire 1 %" B $end
$var wire 1 &" G $end
$var wire 1 '" P $end
$upscope $end
$upscope $end
$scope module MCC_8bit_2 $end
$var wire 8 (" A [7:0] $end
$var wire 8 )" B [7:0] $end
$var wire 8 *" Sum [7:0] $end
$var wire 8 +" P [7:0] $end
$var wire 8 ," G [7:0] $end
$var wire 1 Z Cout $end
$var wire 9 -" C [8:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope begin genblk1[4] $end
$upscope $end
$scope begin genblk1[5] $end
$upscope $end
$scope begin genblk1[6] $end
$upscope $end
$scope begin genblk1[7] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 ." A $end
$var wire 1 /" B $end
$var wire 1 0" G $end
$var wire 1 1" P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 2" A $end
$var wire 1 3" B $end
$var wire 1 4" G $end
$var wire 1 5" P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 6" A $end
$var wire 1 7" B $end
$var wire 1 8" G $end
$var wire 1 9" P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 :" A $end
$var wire 1 ;" B $end
$var wire 1 <" G $end
$var wire 1 =" P $end
$upscope $end
$scope module GP[4] $end
$var wire 1 >" A $end
$var wire 1 ?" B $end
$var wire 1 @" G $end
$var wire 1 A" P $end
$upscope $end
$scope module GP[5] $end
$var wire 1 B" A $end
$var wire 1 C" B $end
$var wire 1 D" G $end
$var wire 1 E" P $end
$upscope $end
$scope module GP[6] $end
$var wire 1 F" A $end
$var wire 1 G" B $end
$var wire 1 H" G $end
$var wire 1 I" P $end
$upscope $end
$scope module GP[7] $end
$var wire 1 J" A $end
$var wire 1 K" B $end
$var wire 1 L" G $end
$var wire 1 M" P $end
$upscope $end
$upscope $end
$scope module MCC_8bit_3 $end
$var wire 8 N" A [7:0] $end
$var wire 8 O" Sum [7:0] $end
$var wire 8 P" P [7:0] $end
$var wire 8 Q" G [7:0] $end
$var wire 1 N Cout $end
$var wire 9 R" C [8:0] $end
$var wire 8 S" B [7:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope begin genblk1[4] $end
$upscope $end
$scope begin genblk1[5] $end
$upscope $end
$scope begin genblk1[6] $end
$upscope $end
$scope begin genblk1[7] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 T" A $end
$var wire 1 U" B $end
$var wire 1 V" G $end
$var wire 1 W" P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 X" A $end
$var wire 1 Y" B $end
$var wire 1 Z" G $end
$var wire 1 [" P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 \" A $end
$var wire 1 ]" B $end
$var wire 1 ^" G $end
$var wire 1 _" P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 `" A $end
$var wire 1 a" B $end
$var wire 1 b" G $end
$var wire 1 c" P $end
$upscope $end
$scope module GP[4] $end
$var wire 1 d" A $end
$var wire 1 e" B $end
$var wire 1 f" G $end
$var wire 1 g" P $end
$upscope $end
$scope module GP[5] $end
$var wire 1 h" A $end
$var wire 1 i" B $end
$var wire 1 j" G $end
$var wire 1 k" P $end
$upscope $end
$scope module GP[6] $end
$var wire 1 l" A $end
$var wire 1 m" B $end
$var wire 1 n" G $end
$var wire 1 o" P $end
$upscope $end
$scope module GP[7] $end
$var wire 1 p" A $end
$var wire 1 q" B $end
$var wire 1 r" G $end
$var wire 1 s" P $end
$upscope $end
$upscope $end
$scope module gabung_coba_1 $end
$var wire 4 t" a [3:0] $end
$var wire 4 u" b [3:0] $end
$var wire 1 v" cin $end
$var wire 1 w" s8 $end
$var wire 4 x" s9 [3:0] $end
$var wire 4 y" s7 [3:0] $end
$var wire 4 z" s6 [3:0] $end
$var wire 4 {" s5 [3:0] $end
$var wire 4 |" s4 [3:0] $end
$var wire 4 }" s3 [3:0] $end
$var wire 4 ~" s2 [3:0] $end
$var wire 4 !# s1 [3:0] $end
$var wire 1 "# cout_s6 $end
$var wire 1 ## cout_s5 $end
$var wire 1 $# cout $end
$var wire 8 %# c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 &# Sum [3:0] $end
$var wire 4 '# P [3:0] $end
$var wire 4 (# G [3:0] $end
$var wire 1 ## Cout $end
$var wire 5 )# C [4:0] $end
$var wire 4 *# B [3:0] $end
$var wire 4 +# A [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 ,# A $end
$var wire 1 -# B $end
$var wire 1 .# G $end
$var wire 1 /# P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 0# A $end
$var wire 1 1# B $end
$var wire 1 2# G $end
$var wire 1 3# P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 4# A $end
$var wire 1 5# B $end
$var wire 1 6# G $end
$var wire 1 7# P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 8# A $end
$var wire 1 9# B $end
$var wire 1 :# G $end
$var wire 1 ;# P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 <# A [3:0] $end
$var wire 4 =# B [3:0] $end
$var wire 4 ># Sum [3:0] $end
$var wire 4 ?# P [3:0] $end
$var wire 4 @# G [3:0] $end
$var wire 1 "# Cout $end
$var wire 5 A# C [4:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 B# A $end
$var wire 1 C# B $end
$var wire 1 D# G $end
$var wire 1 E# P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 F# A $end
$var wire 1 G# B $end
$var wire 1 H# G $end
$var wire 1 I# P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 J# A $end
$var wire 1 K# B $end
$var wire 1 L# G $end
$var wire 1 M# P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 N# A $end
$var wire 1 O# B $end
$var wire 1 P# G $end
$var wire 1 Q# P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 R# A [3:0] $end
$var wire 4 S# Sum [3:0] $end
$var wire 4 T# P [3:0] $end
$var wire 4 U# G [3:0] $end
$var wire 1 $# Cout $end
$var wire 5 V# C [4:0] $end
$var wire 4 W# B [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 X# A $end
$var wire 1 Y# B $end
$var wire 1 Z# G $end
$var wire 1 [# P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 \# A $end
$var wire 1 ]# B $end
$var wire 1 ^# G $end
$var wire 1 _# P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 `# A $end
$var wire 1 a# B $end
$var wire 1 b# G $end
$var wire 1 c# P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 d# A $end
$var wire 1 e# B $end
$var wire 1 f# G $end
$var wire 1 g# P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 h# a [1:0] $end
$var wire 2 i# b [1:0] $end
$var wire 4 j# temp [3:0] $end
$var wire 4 k# c [3:0] $end
$scope module z1 $end
$var wire 1 l# a $end
$var wire 1 m# b $end
$var wire 1 n# carry $end
$var wire 1 o# sum $end
$upscope $end
$scope module z2 $end
$var wire 1 p# a $end
$var wire 1 q# b $end
$var wire 1 r# carry $end
$var wire 1 s# sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_2 $end
$var wire 2 t# a [1:0] $end
$var wire 2 u# b [1:0] $end
$var wire 4 v# temp [3:0] $end
$var wire 4 w# c [3:0] $end
$scope module z1 $end
$var wire 1 x# a $end
$var wire 1 y# b $end
$var wire 1 z# carry $end
$var wire 1 {# sum $end
$upscope $end
$scope module z2 $end
$var wire 1 |# a $end
$var wire 1 }# b $end
$var wire 1 ~# carry $end
$var wire 1 !$ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_3 $end
$var wire 2 "$ a [1:0] $end
$var wire 2 #$ b [1:0] $end
$var wire 4 $$ temp [3:0] $end
$var wire 4 %$ c [3:0] $end
$scope module z1 $end
$var wire 1 &$ a $end
$var wire 1 '$ b $end
$var wire 1 ($ carry $end
$var wire 1 )$ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 *$ a $end
$var wire 1 +$ b $end
$var wire 1 ,$ carry $end
$var wire 1 -$ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_4 $end
$var wire 2 .$ a [1:0] $end
$var wire 2 /$ b [1:0] $end
$var wire 4 0$ temp [3:0] $end
$var wire 4 1$ c [3:0] $end
$scope module z1 $end
$var wire 1 2$ a $end
$var wire 1 3$ b $end
$var wire 1 4$ carry $end
$var wire 1 5$ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 6$ a $end
$var wire 1 7$ b $end
$var wire 1 8$ carry $end
$var wire 1 9$ sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module gabung_coba_2 $end
$var wire 4 :$ a [3:0] $end
$var wire 4 ;$ b [3:0] $end
$var wire 1 <$ cin $end
$var wire 1 =$ s8 $end
$var wire 4 >$ s9 [3:0] $end
$var wire 4 ?$ s7 [3:0] $end
$var wire 4 @$ s6 [3:0] $end
$var wire 4 A$ s5 [3:0] $end
$var wire 4 B$ s4 [3:0] $end
$var wire 4 C$ s3 [3:0] $end
$var wire 4 D$ s2 [3:0] $end
$var wire 4 E$ s1 [3:0] $end
$var wire 1 F$ cout_s6 $end
$var wire 1 G$ cout_s5 $end
$var wire 1 H$ cout $end
$var wire 8 I$ c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 J$ Sum [3:0] $end
$var wire 4 K$ P [3:0] $end
$var wire 4 L$ G [3:0] $end
$var wire 1 G$ Cout $end
$var wire 5 M$ C [4:0] $end
$var wire 4 N$ B [3:0] $end
$var wire 4 O$ A [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 P$ A $end
$var wire 1 Q$ B $end
$var wire 1 R$ G $end
$var wire 1 S$ P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 T$ A $end
$var wire 1 U$ B $end
$var wire 1 V$ G $end
$var wire 1 W$ P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 X$ A $end
$var wire 1 Y$ B $end
$var wire 1 Z$ G $end
$var wire 1 [$ P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 \$ A $end
$var wire 1 ]$ B $end
$var wire 1 ^$ G $end
$var wire 1 _$ P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 `$ A [3:0] $end
$var wire 4 a$ B [3:0] $end
$var wire 4 b$ Sum [3:0] $end
$var wire 4 c$ P [3:0] $end
$var wire 4 d$ G [3:0] $end
$var wire 1 F$ Cout $end
$var wire 5 e$ C [4:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 f$ A $end
$var wire 1 g$ B $end
$var wire 1 h$ G $end
$var wire 1 i$ P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 j$ A $end
$var wire 1 k$ B $end
$var wire 1 l$ G $end
$var wire 1 m$ P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 n$ A $end
$var wire 1 o$ B $end
$var wire 1 p$ G $end
$var wire 1 q$ P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 r$ A $end
$var wire 1 s$ B $end
$var wire 1 t$ G $end
$var wire 1 u$ P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 v$ A [3:0] $end
$var wire 4 w$ Sum [3:0] $end
$var wire 4 x$ P [3:0] $end
$var wire 4 y$ G [3:0] $end
$var wire 1 H$ Cout $end
$var wire 5 z$ C [4:0] $end
$var wire 4 {$ B [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 |$ A $end
$var wire 1 }$ B $end
$var wire 1 ~$ G $end
$var wire 1 !% P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 "% A $end
$var wire 1 #% B $end
$var wire 1 $% G $end
$var wire 1 %% P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 &% A $end
$var wire 1 '% B $end
$var wire 1 (% G $end
$var wire 1 )% P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 *% A $end
$var wire 1 +% B $end
$var wire 1 ,% G $end
$var wire 1 -% P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 .% a [1:0] $end
$var wire 2 /% b [1:0] $end
$var wire 4 0% temp [3:0] $end
$var wire 4 1% c [3:0] $end
$scope module z1 $end
$var wire 1 2% a $end
$var wire 1 3% b $end
$var wire 1 4% carry $end
$var wire 1 5% sum $end
$upscope $end
$scope module z2 $end
$var wire 1 6% a $end
$var wire 1 7% b $end
$var wire 1 8% carry $end
$var wire 1 9% sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_2 $end
$var wire 2 :% a [1:0] $end
$var wire 2 ;% b [1:0] $end
$var wire 4 <% temp [3:0] $end
$var wire 4 =% c [3:0] $end
$scope module z1 $end
$var wire 1 >% a $end
$var wire 1 ?% b $end
$var wire 1 @% carry $end
$var wire 1 A% sum $end
$upscope $end
$scope module z2 $end
$var wire 1 B% a $end
$var wire 1 C% b $end
$var wire 1 D% carry $end
$var wire 1 E% sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_3 $end
$var wire 2 F% a [1:0] $end
$var wire 2 G% b [1:0] $end
$var wire 4 H% temp [3:0] $end
$var wire 4 I% c [3:0] $end
$scope module z1 $end
$var wire 1 J% a $end
$var wire 1 K% b $end
$var wire 1 L% carry $end
$var wire 1 M% sum $end
$upscope $end
$scope module z2 $end
$var wire 1 N% a $end
$var wire 1 O% b $end
$var wire 1 P% carry $end
$var wire 1 Q% sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_4 $end
$var wire 2 R% a [1:0] $end
$var wire 2 S% b [1:0] $end
$var wire 4 T% temp [3:0] $end
$var wire 4 U% c [3:0] $end
$scope module z1 $end
$var wire 1 V% a $end
$var wire 1 W% b $end
$var wire 1 X% carry $end
$var wire 1 Y% sum $end
$upscope $end
$scope module z2 $end
$var wire 1 Z% a $end
$var wire 1 [% b $end
$var wire 1 \% carry $end
$var wire 1 ]% sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module gabung_coba_3 $end
$var wire 4 ^% a [3:0] $end
$var wire 4 _% b [3:0] $end
$var wire 1 `% cin $end
$var wire 1 a% s8 $end
$var wire 4 b% s9 [3:0] $end
$var wire 4 c% s7 [3:0] $end
$var wire 4 d% s6 [3:0] $end
$var wire 4 e% s5 [3:0] $end
$var wire 4 f% s4 [3:0] $end
$var wire 4 g% s3 [3:0] $end
$var wire 4 h% s2 [3:0] $end
$var wire 4 i% s1 [3:0] $end
$var wire 1 j% cout_s6 $end
$var wire 1 k% cout_s5 $end
$var wire 1 l% cout $end
$var wire 8 m% c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 n% Sum [3:0] $end
$var wire 4 o% P [3:0] $end
$var wire 4 p% G [3:0] $end
$var wire 1 k% Cout $end
$var wire 5 q% C [4:0] $end
$var wire 4 r% B [3:0] $end
$var wire 4 s% A [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 t% A $end
$var wire 1 u% B $end
$var wire 1 v% G $end
$var wire 1 w% P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 x% A $end
$var wire 1 y% B $end
$var wire 1 z% G $end
$var wire 1 {% P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 |% A $end
$var wire 1 }% B $end
$var wire 1 ~% G $end
$var wire 1 !& P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 "& A $end
$var wire 1 #& B $end
$var wire 1 $& G $end
$var wire 1 %& P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 && A [3:0] $end
$var wire 4 '& B [3:0] $end
$var wire 4 (& Sum [3:0] $end
$var wire 4 )& P [3:0] $end
$var wire 4 *& G [3:0] $end
$var wire 1 j% Cout $end
$var wire 5 +& C [4:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 ,& A $end
$var wire 1 -& B $end
$var wire 1 .& G $end
$var wire 1 /& P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 0& A $end
$var wire 1 1& B $end
$var wire 1 2& G $end
$var wire 1 3& P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 4& A $end
$var wire 1 5& B $end
$var wire 1 6& G $end
$var wire 1 7& P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 8& A $end
$var wire 1 9& B $end
$var wire 1 :& G $end
$var wire 1 ;& P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 <& A [3:0] $end
$var wire 4 =& Sum [3:0] $end
$var wire 4 >& P [3:0] $end
$var wire 4 ?& G [3:0] $end
$var wire 1 l% Cout $end
$var wire 5 @& C [4:0] $end
$var wire 4 A& B [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 B& A $end
$var wire 1 C& B $end
$var wire 1 D& G $end
$var wire 1 E& P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 F& A $end
$var wire 1 G& B $end
$var wire 1 H& G $end
$var wire 1 I& P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 J& A $end
$var wire 1 K& B $end
$var wire 1 L& G $end
$var wire 1 M& P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 N& A $end
$var wire 1 O& B $end
$var wire 1 P& G $end
$var wire 1 Q& P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 R& a [1:0] $end
$var wire 2 S& b [1:0] $end
$var wire 4 T& temp [3:0] $end
$var wire 4 U& c [3:0] $end
$scope module z1 $end
$var wire 1 V& a $end
$var wire 1 W& b $end
$var wire 1 X& carry $end
$var wire 1 Y& sum $end
$upscope $end
$scope module z2 $end
$var wire 1 Z& a $end
$var wire 1 [& b $end
$var wire 1 \& carry $end
$var wire 1 ]& sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_2 $end
$var wire 2 ^& a [1:0] $end
$var wire 2 _& b [1:0] $end
$var wire 4 `& temp [3:0] $end
$var wire 4 a& c [3:0] $end
$scope module z1 $end
$var wire 1 b& a $end
$var wire 1 c& b $end
$var wire 1 d& carry $end
$var wire 1 e& sum $end
$upscope $end
$scope module z2 $end
$var wire 1 f& a $end
$var wire 1 g& b $end
$var wire 1 h& carry $end
$var wire 1 i& sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_3 $end
$var wire 2 j& a [1:0] $end
$var wire 2 k& b [1:0] $end
$var wire 4 l& temp [3:0] $end
$var wire 4 m& c [3:0] $end
$scope module z1 $end
$var wire 1 n& a $end
$var wire 1 o& b $end
$var wire 1 p& carry $end
$var wire 1 q& sum $end
$upscope $end
$scope module z2 $end
$var wire 1 r& a $end
$var wire 1 s& b $end
$var wire 1 t& carry $end
$var wire 1 u& sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_4 $end
$var wire 2 v& a [1:0] $end
$var wire 2 w& b [1:0] $end
$var wire 4 x& temp [3:0] $end
$var wire 4 y& c [3:0] $end
$scope module z1 $end
$var wire 1 z& a $end
$var wire 1 {& b $end
$var wire 1 |& carry $end
$var wire 1 }& sum $end
$upscope $end
$scope module z2 $end
$var wire 1 ~& a $end
$var wire 1 !' b $end
$var wire 1 "' carry $end
$var wire 1 #' sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module gabung_coba_4 $end
$var wire 4 $' a [3:0] $end
$var wire 4 %' b [3:0] $end
$var wire 1 &' cin $end
$var wire 1 '' s8 $end
$var wire 4 (' s9 [3:0] $end
$var wire 4 )' s7 [3:0] $end
$var wire 4 *' s6 [3:0] $end
$var wire 4 +' s5 [3:0] $end
$var wire 4 ,' s4 [3:0] $end
$var wire 4 -' s3 [3:0] $end
$var wire 4 .' s2 [3:0] $end
$var wire 4 /' s1 [3:0] $end
$var wire 1 0' cout_s6 $end
$var wire 1 1' cout_s5 $end
$var wire 1 2' cout $end
$var wire 8 3' c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 4' Sum [3:0] $end
$var wire 4 5' P [3:0] $end
$var wire 4 6' G [3:0] $end
$var wire 1 1' Cout $end
$var wire 5 7' C [4:0] $end
$var wire 4 8' B [3:0] $end
$var wire 4 9' A [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 :' A $end
$var wire 1 ;' B $end
$var wire 1 <' G $end
$var wire 1 =' P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 >' A $end
$var wire 1 ?' B $end
$var wire 1 @' G $end
$var wire 1 A' P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 B' A $end
$var wire 1 C' B $end
$var wire 1 D' G $end
$var wire 1 E' P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 F' A $end
$var wire 1 G' B $end
$var wire 1 H' G $end
$var wire 1 I' P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 J' A [3:0] $end
$var wire 4 K' B [3:0] $end
$var wire 4 L' Sum [3:0] $end
$var wire 4 M' P [3:0] $end
$var wire 4 N' G [3:0] $end
$var wire 1 0' Cout $end
$var wire 5 O' C [4:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 P' A $end
$var wire 1 Q' B $end
$var wire 1 R' G $end
$var wire 1 S' P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 T' A $end
$var wire 1 U' B $end
$var wire 1 V' G $end
$var wire 1 W' P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 X' A $end
$var wire 1 Y' B $end
$var wire 1 Z' G $end
$var wire 1 [' P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 \' A $end
$var wire 1 ]' B $end
$var wire 1 ^' G $end
$var wire 1 _' P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 `' A [3:0] $end
$var wire 4 a' Sum [3:0] $end
$var wire 4 b' P [3:0] $end
$var wire 4 c' G [3:0] $end
$var wire 1 2' Cout $end
$var wire 5 d' C [4:0] $end
$var wire 4 e' B [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 f' A $end
$var wire 1 g' B $end
$var wire 1 h' G $end
$var wire 1 i' P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 j' A $end
$var wire 1 k' B $end
$var wire 1 l' G $end
$var wire 1 m' P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 n' A $end
$var wire 1 o' B $end
$var wire 1 p' G $end
$var wire 1 q' P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 r' A $end
$var wire 1 s' B $end
$var wire 1 t' G $end
$var wire 1 u' P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 v' a [1:0] $end
$var wire 2 w' b [1:0] $end
$var wire 4 x' temp [3:0] $end
$var wire 4 y' c [3:0] $end
$scope module z1 $end
$var wire 1 z' a $end
$var wire 1 {' b $end
$var wire 1 |' carry $end
$var wire 1 }' sum $end
$upscope $end
$scope module z2 $end
$var wire 1 ~' a $end
$var wire 1 !( b $end
$var wire 1 "( carry $end
$var wire 1 #( sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_2 $end
$var wire 2 $( a [1:0] $end
$var wire 2 %( b [1:0] $end
$var wire 4 &( temp [3:0] $end
$var wire 4 '( c [3:0] $end
$scope module z1 $end
$var wire 1 (( a $end
$var wire 1 )( b $end
$var wire 1 *( carry $end
$var wire 1 +( sum $end
$upscope $end
$scope module z2 $end
$var wire 1 ,( a $end
$var wire 1 -( b $end
$var wire 1 .( carry $end
$var wire 1 /( sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_3 $end
$var wire 2 0( a [1:0] $end
$var wire 2 1( b [1:0] $end
$var wire 4 2( temp [3:0] $end
$var wire 4 3( c [3:0] $end
$scope module z1 $end
$var wire 1 4( a $end
$var wire 1 5( b $end
$var wire 1 6( carry $end
$var wire 1 7( sum $end
$upscope $end
$scope module z2 $end
$var wire 1 8( a $end
$var wire 1 9( b $end
$var wire 1 :( carry $end
$var wire 1 ;( sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_4 $end
$var wire 2 <( a [1:0] $end
$var wire 2 =( b [1:0] $end
$var wire 4 >( temp [3:0] $end
$var wire 4 ?( c [3:0] $end
$scope module z1 $end
$var wire 1 @( a $end
$var wire 1 A( b $end
$var wire 1 B( carry $end
$var wire 1 C( sum $end
$upscope $end
$scope module z2 $end
$var wire 1 D( a $end
$var wire 1 E( b $end
$var wire 1 F( carry $end
$var wire 1 G( sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module memory16bit_1 $end
$var wire 1 + clock $end
$var wire 16 H( d [15:0] $end
$var wire 1 3 enable $end
$var wire 1 1 reset $end
$var wire 16 I( q [15:0] $end
$var wire 1 Y done $end
$var reg 1 Y done_reg $end
$var reg 16 J( q_reg [15:0] $end
$upscope $end
$scope module memory1bit_1 $end
$var wire 1 + clock $end
$var wire 1 N d $end
$var wire 1 K done $end
$var wire 1 3 enable $end
$var wire 1 \ q $end
$var wire 1 1 reset $end
$var reg 1 K( d_reg $end
$upscope $end
$upscope $end
$scope module error_check_1 $end
$var wire 1 + clock $end
$var wire 8 L( d [7:0] $end
$var wire 1 ' done_errorcheck $end
$var wire 1 - enable $end
$var wire 8 M( q [7:0] $end
$var wire 1 1 reset $end
$var wire 8 N( untukmemory_e [7:0] $end
$var wire 8 O( untukmemory_w [7:0] $end
$var wire 8 P( untukmemory_z [7:0] $end
$var wire 16 Q( y [15:0] $end
$var wire 8 R( z [7:0] $end
$var wire 8 S( y_8bitconv [7:0] $end
$var wire 16 T( y_8bit [15:0] $end
$var wire 8 U( e [7:0] $end
$var wire 1 V( done_z $end
$var wire 1 W( done_e $end
$scope module memory_e $end
$var wire 8 X( a [7:0] $end
$var wire 1 + clock $end
$var wire 1 - enable $end
$var wire 1 1 reset $end
$var wire 8 Y( w [7:0] $end
$var reg 8 Z( d [7:0] $end
$var reg 1 W( done $end
$var reg 8 [( q [7:0] $end
$upscope $end
$scope module memory_z $end
$var wire 8 \( a [7:0] $end
$var wire 1 + clock $end
$var wire 1 - enable $end
$var wire 1 1 reset $end
$var wire 8 ]( w [7:0] $end
$var reg 8 ^( d [7:0] $end
$var reg 1 V( done $end
$var reg 8 _( q [7:0] $end
$upscope $end
$scope module your_instance_name $end
$var wire 8 `( A [7:0] $end
$var wire 8 a( B [7:0] $end
$var wire 8 b( S [7:0] $end
$upscope $end
$upscope $end
$scope module memory_Dn $end
$var wire 8 c( a [7:0] $end
$var wire 1 + clock $end
$var wire 1 . enable $end
$var wire 1 1 reset $end
$var wire 8 d( w [7:0] $end
$var reg 8 e( d [7:0] $end
$var reg 1 & done $end
$var reg 8 f( q [7:0] $end
$upscope $end
$scope module memory_Xn $end
$var wire 8 g( a [7:0] $end
$var wire 1 + clock $end
$var wire 1 / enable $end
$var wire 1 1 reset $end
$var wire 8 h( w [7:0] $end
$var reg 8 i( d [7:0] $end
$var reg 1 % done $end
$var reg 8 j( q [7:0] $end
$upscope $end
$scope module memory_bobot $end
$var wire 8 k( a [7:0] $end
$var wire 1 + clock $end
$var wire 1 0 enable $end
$var wire 1 1 reset $end
$var wire 8 l( w [7:0] $end
$var reg 8 m( d [7:0] $end
$var reg 1 # done $end
$var reg 8 n( q [7:0] $end
$upscope $end
$scope module pembaruan_bobot_1 $end
$var wire 1 + clock $end
$var wire 8 o( e [7:0] $end
$var wire 1 2 enable $end
$var wire 8 p( keluaran [7:0] $end
$var wire 1 1 reset $end
$var wire 8 q( untukmemory [7:0] $end
$var wire 8 r( untukmemory_w [7:0] $end
$var wire 8 s( w [7:0] $end
$var wire 8 t( x [7:0] $end
$var wire 8 u( xemiu_conv [7:0] $end
$var wire 16 v( xemiu [15:0] $end
$var wire 16 w( xe [15:0] $end
$var wire 1 $ done_pembaruanbobot $end
$var wire 1 x( done_8bit $end
$scope module delapan_bit_gabung_coba_1 $end
$var wire 16 y( Output_SO [15:0] $end
$var wire 16 z( Output_buff [15:0] $end
$var wire 2 {( Sign_OP_Check [1:0] $end
$var wire 8 |( a [7:0] $end
$var wire 9 }( a_extd [8:0] $end
$var wire 8 ~( aa [7:0] $end
$var wire 9 !) add_SO [8:0] $end
$var wire 8 ") b [7:0] $end
$var wire 1 #) cin $end
$var wire 1 + clock $end
$var wire 1 $) done_cout $end
$var wire 1 x( done_delapanbitgabungcoba $end
$var wire 1 2 enable $end
$var wire 1 1 reset $end
$var wire 1 %) s8 $end
$var wire 9 &) twosc [8:0] $end
$var wire 1 ') untukmemory_cout $end
$var wire 16 () untukmemory [15:0] $end
$var wire 8 )) s9 [7:0] $end
$var wire 8 *) s7 [7:0] $end
$var wire 8 +) s6 [7:0] $end
$var wire 8 ,) s5 [7:0] $end
$var wire 8 -) s4 [7:0] $end
$var wire 8 .) s3 [7:0] $end
$var wire 8 /) s2 [7:0] $end
$var wire 8 0) s1 [7:0] $end
$var wire 16 1) q [15:0] $end
$var wire 1 2) done_q $end
$var wire 1 3) cout_s6 $end
$var wire 1 4) cout_s5 $end
$var wire 1 5) cout $end
$var wire 16 6) c [15:0] $end
$var wire 8 7) bb [7:0] $end
$scope begin g_sign_op[0] $end
$upscope $end
$scope begin g_sign_op[1] $end
$upscope $end
$scope begin g_sign_op[2] $end
$upscope $end
$scope begin g_sign_op[3] $end
$upscope $end
$scope begin g_sign_op[4] $end
$upscope $end
$scope begin g_sign_op[5] $end
$upscope $end
$scope begin g_sign_op[6] $end
$upscope $end
$scope module MCC_8bit_1 $end
$var wire 8 8) Sum [7:0] $end
$var wire 8 9) P [7:0] $end
$var wire 8 :) G [7:0] $end
$var wire 1 4) Cout $end
$var wire 9 ;) C [8:0] $end
$var wire 8 <) B [7:0] $end
$var wire 8 =) A [7:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope begin genblk1[4] $end
$upscope $end
$scope begin genblk1[5] $end
$upscope $end
$scope begin genblk1[6] $end
$upscope $end
$scope begin genblk1[7] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 >) A $end
$var wire 1 ?) B $end
$var wire 1 @) G $end
$var wire 1 A) P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 B) A $end
$var wire 1 C) B $end
$var wire 1 D) G $end
$var wire 1 E) P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 F) A $end
$var wire 1 G) B $end
$var wire 1 H) G $end
$var wire 1 I) P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 J) A $end
$var wire 1 K) B $end
$var wire 1 L) G $end
$var wire 1 M) P $end
$upscope $end
$scope module GP[4] $end
$var wire 1 N) A $end
$var wire 1 O) B $end
$var wire 1 P) G $end
$var wire 1 Q) P $end
$upscope $end
$scope module GP[5] $end
$var wire 1 R) A $end
$var wire 1 S) B $end
$var wire 1 T) G $end
$var wire 1 U) P $end
$upscope $end
$scope module GP[6] $end
$var wire 1 V) A $end
$var wire 1 W) B $end
$var wire 1 X) G $end
$var wire 1 Y) P $end
$upscope $end
$scope module GP[7] $end
$var wire 1 Z) A $end
$var wire 1 [) B $end
$var wire 1 \) G $end
$var wire 1 ]) P $end
$upscope $end
$upscope $end
$scope module MCC_8bit_2 $end
$var wire 8 ^) A [7:0] $end
$var wire 8 _) B [7:0] $end
$var wire 8 `) Sum [7:0] $end
$var wire 8 a) P [7:0] $end
$var wire 8 b) G [7:0] $end
$var wire 1 3) Cout $end
$var wire 9 c) C [8:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope begin genblk1[4] $end
$upscope $end
$scope begin genblk1[5] $end
$upscope $end
$scope begin genblk1[6] $end
$upscope $end
$scope begin genblk1[7] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 d) A $end
$var wire 1 e) B $end
$var wire 1 f) G $end
$var wire 1 g) P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 h) A $end
$var wire 1 i) B $end
$var wire 1 j) G $end
$var wire 1 k) P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 l) A $end
$var wire 1 m) B $end
$var wire 1 n) G $end
$var wire 1 o) P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 p) A $end
$var wire 1 q) B $end
$var wire 1 r) G $end
$var wire 1 s) P $end
$upscope $end
$scope module GP[4] $end
$var wire 1 t) A $end
$var wire 1 u) B $end
$var wire 1 v) G $end
$var wire 1 w) P $end
$upscope $end
$scope module GP[5] $end
$var wire 1 x) A $end
$var wire 1 y) B $end
$var wire 1 z) G $end
$var wire 1 {) P $end
$upscope $end
$scope module GP[6] $end
$var wire 1 |) A $end
$var wire 1 }) B $end
$var wire 1 ~) G $end
$var wire 1 !* P $end
$upscope $end
$scope module GP[7] $end
$var wire 1 "* A $end
$var wire 1 #* B $end
$var wire 1 $* G $end
$var wire 1 %* P $end
$upscope $end
$upscope $end
$scope module MCC_8bit_3 $end
$var wire 8 &* A [7:0] $end
$var wire 8 '* Sum [7:0] $end
$var wire 8 (* P [7:0] $end
$var wire 8 )* G [7:0] $end
$var wire 1 ') Cout $end
$var wire 9 ** C [8:0] $end
$var wire 8 +* B [7:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope begin genblk1[4] $end
$upscope $end
$scope begin genblk1[5] $end
$upscope $end
$scope begin genblk1[6] $end
$upscope $end
$scope begin genblk1[7] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 ,* A $end
$var wire 1 -* B $end
$var wire 1 .* G $end
$var wire 1 /* P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 0* A $end
$var wire 1 1* B $end
$var wire 1 2* G $end
$var wire 1 3* P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 4* A $end
$var wire 1 5* B $end
$var wire 1 6* G $end
$var wire 1 7* P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 8* A $end
$var wire 1 9* B $end
$var wire 1 :* G $end
$var wire 1 ;* P $end
$upscope $end
$scope module GP[4] $end
$var wire 1 <* A $end
$var wire 1 =* B $end
$var wire 1 >* G $end
$var wire 1 ?* P $end
$upscope $end
$scope module GP[5] $end
$var wire 1 @* A $end
$var wire 1 A* B $end
$var wire 1 B* G $end
$var wire 1 C* P $end
$upscope $end
$scope module GP[6] $end
$var wire 1 D* A $end
$var wire 1 E* B $end
$var wire 1 F* G $end
$var wire 1 G* P $end
$upscope $end
$scope module GP[7] $end
$var wire 1 H* A $end
$var wire 1 I* B $end
$var wire 1 J* G $end
$var wire 1 K* P $end
$upscope $end
$upscope $end
$scope module gabung_coba_1 $end
$var wire 4 L* a [3:0] $end
$var wire 4 M* b [3:0] $end
$var wire 1 N* cin $end
$var wire 1 O* s8 $end
$var wire 4 P* s9 [3:0] $end
$var wire 4 Q* s7 [3:0] $end
$var wire 4 R* s6 [3:0] $end
$var wire 4 S* s5 [3:0] $end
$var wire 4 T* s4 [3:0] $end
$var wire 4 U* s3 [3:0] $end
$var wire 4 V* s2 [3:0] $end
$var wire 4 W* s1 [3:0] $end
$var wire 1 X* cout_s6 $end
$var wire 1 Y* cout_s5 $end
$var wire 1 Z* cout $end
$var wire 8 [* c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 \* Sum [3:0] $end
$var wire 4 ]* P [3:0] $end
$var wire 4 ^* G [3:0] $end
$var wire 1 Y* Cout $end
$var wire 5 _* C [4:0] $end
$var wire 4 `* B [3:0] $end
$var wire 4 a* A [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 b* A $end
$var wire 1 c* B $end
$var wire 1 d* G $end
$var wire 1 e* P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 f* A $end
$var wire 1 g* B $end
$var wire 1 h* G $end
$var wire 1 i* P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 j* A $end
$var wire 1 k* B $end
$var wire 1 l* G $end
$var wire 1 m* P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 n* A $end
$var wire 1 o* B $end
$var wire 1 p* G $end
$var wire 1 q* P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 r* A [3:0] $end
$var wire 4 s* B [3:0] $end
$var wire 4 t* Sum [3:0] $end
$var wire 4 u* P [3:0] $end
$var wire 4 v* G [3:0] $end
$var wire 1 X* Cout $end
$var wire 5 w* C [4:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 x* A $end
$var wire 1 y* B $end
$var wire 1 z* G $end
$var wire 1 {* P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 |* A $end
$var wire 1 }* B $end
$var wire 1 ~* G $end
$var wire 1 !+ P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 "+ A $end
$var wire 1 #+ B $end
$var wire 1 $+ G $end
$var wire 1 %+ P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 &+ A $end
$var wire 1 '+ B $end
$var wire 1 (+ G $end
$var wire 1 )+ P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 *+ A [3:0] $end
$var wire 4 ++ Sum [3:0] $end
$var wire 4 ,+ P [3:0] $end
$var wire 4 -+ G [3:0] $end
$var wire 1 Z* Cout $end
$var wire 5 .+ C [4:0] $end
$var wire 4 /+ B [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 0+ A $end
$var wire 1 1+ B $end
$var wire 1 2+ G $end
$var wire 1 3+ P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 4+ A $end
$var wire 1 5+ B $end
$var wire 1 6+ G $end
$var wire 1 7+ P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 8+ A $end
$var wire 1 9+ B $end
$var wire 1 :+ G $end
$var wire 1 ;+ P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 <+ A $end
$var wire 1 =+ B $end
$var wire 1 >+ G $end
$var wire 1 ?+ P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 @+ a [1:0] $end
$var wire 2 A+ b [1:0] $end
$var wire 4 B+ temp [3:0] $end
$var wire 4 C+ c [3:0] $end
$scope module z1 $end
$var wire 1 D+ a $end
$var wire 1 E+ b $end
$var wire 1 F+ carry $end
$var wire 1 G+ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 H+ a $end
$var wire 1 I+ b $end
$var wire 1 J+ carry $end
$var wire 1 K+ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_2 $end
$var wire 2 L+ a [1:0] $end
$var wire 2 M+ b [1:0] $end
$var wire 4 N+ temp [3:0] $end
$var wire 4 O+ c [3:0] $end
$scope module z1 $end
$var wire 1 P+ a $end
$var wire 1 Q+ b $end
$var wire 1 R+ carry $end
$var wire 1 S+ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 T+ a $end
$var wire 1 U+ b $end
$var wire 1 V+ carry $end
$var wire 1 W+ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_3 $end
$var wire 2 X+ a [1:0] $end
$var wire 2 Y+ b [1:0] $end
$var wire 4 Z+ temp [3:0] $end
$var wire 4 [+ c [3:0] $end
$scope module z1 $end
$var wire 1 \+ a $end
$var wire 1 ]+ b $end
$var wire 1 ^+ carry $end
$var wire 1 _+ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 `+ a $end
$var wire 1 a+ b $end
$var wire 1 b+ carry $end
$var wire 1 c+ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_4 $end
$var wire 2 d+ a [1:0] $end
$var wire 2 e+ b [1:0] $end
$var wire 4 f+ temp [3:0] $end
$var wire 4 g+ c [3:0] $end
$scope module z1 $end
$var wire 1 h+ a $end
$var wire 1 i+ b $end
$var wire 1 j+ carry $end
$var wire 1 k+ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 l+ a $end
$var wire 1 m+ b $end
$var wire 1 n+ carry $end
$var wire 1 o+ sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module gabung_coba_2 $end
$var wire 4 p+ a [3:0] $end
$var wire 4 q+ b [3:0] $end
$var wire 1 r+ cin $end
$var wire 1 s+ s8 $end
$var wire 4 t+ s9 [3:0] $end
$var wire 4 u+ s7 [3:0] $end
$var wire 4 v+ s6 [3:0] $end
$var wire 4 w+ s5 [3:0] $end
$var wire 4 x+ s4 [3:0] $end
$var wire 4 y+ s3 [3:0] $end
$var wire 4 z+ s2 [3:0] $end
$var wire 4 {+ s1 [3:0] $end
$var wire 1 |+ cout_s6 $end
$var wire 1 }+ cout_s5 $end
$var wire 1 ~+ cout $end
$var wire 8 !, c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 ", Sum [3:0] $end
$var wire 4 #, P [3:0] $end
$var wire 4 $, G [3:0] $end
$var wire 1 }+ Cout $end
$var wire 5 %, C [4:0] $end
$var wire 4 &, B [3:0] $end
$var wire 4 ', A [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 (, A $end
$var wire 1 ), B $end
$var wire 1 *, G $end
$var wire 1 +, P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 ,, A $end
$var wire 1 -, B $end
$var wire 1 ., G $end
$var wire 1 /, P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 0, A $end
$var wire 1 1, B $end
$var wire 1 2, G $end
$var wire 1 3, P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 4, A $end
$var wire 1 5, B $end
$var wire 1 6, G $end
$var wire 1 7, P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 8, A [3:0] $end
$var wire 4 9, B [3:0] $end
$var wire 4 :, Sum [3:0] $end
$var wire 4 ;, P [3:0] $end
$var wire 4 <, G [3:0] $end
$var wire 1 |+ Cout $end
$var wire 5 =, C [4:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 >, A $end
$var wire 1 ?, B $end
$var wire 1 @, G $end
$var wire 1 A, P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 B, A $end
$var wire 1 C, B $end
$var wire 1 D, G $end
$var wire 1 E, P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 F, A $end
$var wire 1 G, B $end
$var wire 1 H, G $end
$var wire 1 I, P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 J, A $end
$var wire 1 K, B $end
$var wire 1 L, G $end
$var wire 1 M, P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 N, A [3:0] $end
$var wire 4 O, Sum [3:0] $end
$var wire 4 P, P [3:0] $end
$var wire 4 Q, G [3:0] $end
$var wire 1 ~+ Cout $end
$var wire 5 R, C [4:0] $end
$var wire 4 S, B [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 T, A $end
$var wire 1 U, B $end
$var wire 1 V, G $end
$var wire 1 W, P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 X, A $end
$var wire 1 Y, B $end
$var wire 1 Z, G $end
$var wire 1 [, P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 \, A $end
$var wire 1 ], B $end
$var wire 1 ^, G $end
$var wire 1 _, P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 `, A $end
$var wire 1 a, B $end
$var wire 1 b, G $end
$var wire 1 c, P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 d, a [1:0] $end
$var wire 2 e, b [1:0] $end
$var wire 4 f, temp [3:0] $end
$var wire 4 g, c [3:0] $end
$scope module z1 $end
$var wire 1 h, a $end
$var wire 1 i, b $end
$var wire 1 j, carry $end
$var wire 1 k, sum $end
$upscope $end
$scope module z2 $end
$var wire 1 l, a $end
$var wire 1 m, b $end
$var wire 1 n, carry $end
$var wire 1 o, sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_2 $end
$var wire 2 p, a [1:0] $end
$var wire 2 q, b [1:0] $end
$var wire 4 r, temp [3:0] $end
$var wire 4 s, c [3:0] $end
$scope module z1 $end
$var wire 1 t, a $end
$var wire 1 u, b $end
$var wire 1 v, carry $end
$var wire 1 w, sum $end
$upscope $end
$scope module z2 $end
$var wire 1 x, a $end
$var wire 1 y, b $end
$var wire 1 z, carry $end
$var wire 1 {, sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_3 $end
$var wire 2 |, a [1:0] $end
$var wire 2 }, b [1:0] $end
$var wire 4 ~, temp [3:0] $end
$var wire 4 !- c [3:0] $end
$scope module z1 $end
$var wire 1 "- a $end
$var wire 1 #- b $end
$var wire 1 $- carry $end
$var wire 1 %- sum $end
$upscope $end
$scope module z2 $end
$var wire 1 &- a $end
$var wire 1 '- b $end
$var wire 1 (- carry $end
$var wire 1 )- sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_4 $end
$var wire 2 *- a [1:0] $end
$var wire 2 +- b [1:0] $end
$var wire 4 ,- temp [3:0] $end
$var wire 4 -- c [3:0] $end
$scope module z1 $end
$var wire 1 .- a $end
$var wire 1 /- b $end
$var wire 1 0- carry $end
$var wire 1 1- sum $end
$upscope $end
$scope module z2 $end
$var wire 1 2- a $end
$var wire 1 3- b $end
$var wire 1 4- carry $end
$var wire 1 5- sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module gabung_coba_3 $end
$var wire 4 6- a [3:0] $end
$var wire 4 7- b [3:0] $end
$var wire 1 8- cin $end
$var wire 1 9- s8 $end
$var wire 4 :- s9 [3:0] $end
$var wire 4 ;- s7 [3:0] $end
$var wire 4 <- s6 [3:0] $end
$var wire 4 =- s5 [3:0] $end
$var wire 4 >- s4 [3:0] $end
$var wire 4 ?- s3 [3:0] $end
$var wire 4 @- s2 [3:0] $end
$var wire 4 A- s1 [3:0] $end
$var wire 1 B- cout_s6 $end
$var wire 1 C- cout_s5 $end
$var wire 1 D- cout $end
$var wire 8 E- c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 F- Sum [3:0] $end
$var wire 4 G- P [3:0] $end
$var wire 4 H- G [3:0] $end
$var wire 1 C- Cout $end
$var wire 5 I- C [4:0] $end
$var wire 4 J- B [3:0] $end
$var wire 4 K- A [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 L- A $end
$var wire 1 M- B $end
$var wire 1 N- G $end
$var wire 1 O- P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 P- A $end
$var wire 1 Q- B $end
$var wire 1 R- G $end
$var wire 1 S- P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 T- A $end
$var wire 1 U- B $end
$var wire 1 V- G $end
$var wire 1 W- P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 X- A $end
$var wire 1 Y- B $end
$var wire 1 Z- G $end
$var wire 1 [- P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 \- A [3:0] $end
$var wire 4 ]- B [3:0] $end
$var wire 4 ^- Sum [3:0] $end
$var wire 4 _- P [3:0] $end
$var wire 4 `- G [3:0] $end
$var wire 1 B- Cout $end
$var wire 5 a- C [4:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 b- A $end
$var wire 1 c- B $end
$var wire 1 d- G $end
$var wire 1 e- P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 f- A $end
$var wire 1 g- B $end
$var wire 1 h- G $end
$var wire 1 i- P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 j- A $end
$var wire 1 k- B $end
$var wire 1 l- G $end
$var wire 1 m- P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 n- A $end
$var wire 1 o- B $end
$var wire 1 p- G $end
$var wire 1 q- P $end
$upscope $end
$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 r- A [3:0] $end
$var wire 4 s- Sum [3:0] $end
$var wire 4 t- P [3:0] $end
$var wire 4 u- G [3:0] $end
$var wire 1 D- Cout $end
$var wire 5 v- C [4:0] $end
$var wire 4 w- B [3:0] $end
$scope begin genblk1[0] $end
$upscope $end
$scope begin genblk1[1] $end
$upscope $end
$scope begin genblk1[2] $end
$upscope $end
$scope begin genblk1[3] $end
$upscope $end
$scope module GP[0] $end
$var wire 1 x- A $end
$var wire 1 y- B $end
$var wire 1 z- G $end
$var wire 1 {- P $end
$upscope $end
$scope module GP[1] $end
$var wire 1 |- A $end
$var wire 1 }- B $end
$var wire 1 ~- G $end
$var wire 1 !. P $end
$upscope $end
$scope module GP[2] $end
$var wire 1 ". A $end
$var wire 1 #. B $end
$var wire 1 $. G $end
$var wire 1 %. P $end
$upscope $end
$scope module GP[3] $end
$var wire 1 &. A $end
$var wire 1 '. B $end
$var wire 1 (. G $end
$var wire 1 ). P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 *. a [1:0] $end
$var wire 2 +. b [1:0] $end
$var wire 4 ,. temp [3:0] $end
$var wire 4 -. c [3:0] $end
$scope module z1 $end
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$var wire 1 /. b $end
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$var wire 1 1. sum $end
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$var wire 1 3. b $end
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$var wire 1 5. sum $end
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$upscope $end
$scope module vedicmcc_2 $end
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$scope module z1 $end
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$var wire 1 ;. b $end
$var wire 1 <. carry $end
$var wire 1 =. sum $end
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$scope module vedicmcc_3 $end
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$var wire 2 C. b [1:0] $end
$var wire 4 D. temp [3:0] $end
$var wire 4 E. c [3:0] $end
$scope module z1 $end
$var wire 1 F. a $end
$var wire 1 G. b $end
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$var wire 1 K. b $end
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$scope module vedicmcc_4 $end
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$var wire 4 P. temp [3:0] $end
$var wire 4 Q. c [3:0] $end
$scope module z1 $end
$var wire 1 R. a $end
$var wire 1 S. b $end
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$var wire 1 U. sum $end
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$var wire 1 Y. sum $end
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$upscope $end
$scope module gabung_coba_4 $end
$var wire 4 Z. a [3:0] $end
$var wire 4 [. b [3:0] $end
$var wire 1 \. cin $end
$var wire 1 ]. s8 $end
$var wire 4 ^. s9 [3:0] $end
$var wire 4 _. s7 [3:0] $end
$var wire 4 `. s6 [3:0] $end
$var wire 4 a. s5 [3:0] $end
$var wire 4 b. s4 [3:0] $end
$var wire 4 c. s3 [3:0] $end
$var wire 4 d. s2 [3:0] $end
$var wire 4 e. s1 [3:0] $end
$var wire 1 f. cout_s6 $end
$var wire 1 g. cout_s5 $end
$var wire 1 h. cout $end
$var wire 8 i. c [7:0] $end
$scope module MCC_4bit_1 $end
$var wire 4 j. Sum [3:0] $end
$var wire 4 k. P [3:0] $end
$var wire 4 l. G [3:0] $end
$var wire 1 g. Cout $end
$var wire 5 m. C [4:0] $end
$var wire 4 n. B [3:0] $end
$var wire 4 o. A [3:0] $end
$scope begin genblk1[0] $end
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$scope begin genblk1[1] $end
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$scope begin genblk1[2] $end
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$scope begin genblk1[3] $end
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$scope module GP[0] $end
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$var wire 1 s. P $end
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$scope module GP[1] $end
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$scope module GP[2] $end
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$var wire 1 z. G $end
$var wire 1 {. P $end
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$scope module GP[3] $end
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$var wire 1 !/ P $end
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$upscope $end
$scope module MCC_4bit_2 $end
$var wire 4 "/ A [3:0] $end
$var wire 4 #/ B [3:0] $end
$var wire 4 $/ Sum [3:0] $end
$var wire 4 %/ P [3:0] $end
$var wire 4 &/ G [3:0] $end
$var wire 1 f. Cout $end
$var wire 5 '/ C [4:0] $end
$scope begin genblk1[0] $end
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$scope begin genblk1[2] $end
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$scope begin genblk1[3] $end
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$scope module GP[3] $end
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$var wire 1 6/ G $end
$var wire 1 7/ P $end
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$upscope $end
$scope module MCC_4bit_3 $end
$var wire 4 8/ A [3:0] $end
$var wire 4 9/ Sum [3:0] $end
$var wire 4 :/ P [3:0] $end
$var wire 4 ;/ G [3:0] $end
$var wire 1 h. Cout $end
$var wire 5 </ C [4:0] $end
$var wire 4 =/ B [3:0] $end
$scope begin genblk1[0] $end
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$scope begin genblk1[2] $end
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$scope begin genblk1[3] $end
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$var wire 1 >/ A $end
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$scope module GP[1] $end
$var wire 1 B/ A $end
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$scope module GP[2] $end
$var wire 1 F/ A $end
$var wire 1 G/ B $end
$var wire 1 H/ G $end
$var wire 1 I/ P $end
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$scope module GP[3] $end
$var wire 1 J/ A $end
$var wire 1 K/ B $end
$var wire 1 L/ G $end
$var wire 1 M/ P $end
$upscope $end
$upscope $end
$scope module vedicmcc_1 $end
$var wire 2 N/ a [1:0] $end
$var wire 2 O/ b [1:0] $end
$var wire 4 P/ temp [3:0] $end
$var wire 4 Q/ c [3:0] $end
$scope module z1 $end
$var wire 1 R/ a $end
$var wire 1 S/ b $end
$var wire 1 T/ carry $end
$var wire 1 U/ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 V/ a $end
$var wire 1 W/ b $end
$var wire 1 X/ carry $end
$var wire 1 Y/ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_2 $end
$var wire 2 Z/ a [1:0] $end
$var wire 2 [/ b [1:0] $end
$var wire 4 \/ temp [3:0] $end
$var wire 4 ]/ c [3:0] $end
$scope module z1 $end
$var wire 1 ^/ a $end
$var wire 1 _/ b $end
$var wire 1 `/ carry $end
$var wire 1 a/ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 b/ a $end
$var wire 1 c/ b $end
$var wire 1 d/ carry $end
$var wire 1 e/ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_3 $end
$var wire 2 f/ a [1:0] $end
$var wire 2 g/ b [1:0] $end
$var wire 4 h/ temp [3:0] $end
$var wire 4 i/ c [3:0] $end
$scope module z1 $end
$var wire 1 j/ a $end
$var wire 1 k/ b $end
$var wire 1 l/ carry $end
$var wire 1 m/ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 n/ a $end
$var wire 1 o/ b $end
$var wire 1 p/ carry $end
$var wire 1 q/ sum $end
$upscope $end
$upscope $end
$scope module vedicmcc_4 $end
$var wire 2 r/ a [1:0] $end
$var wire 2 s/ b [1:0] $end
$var wire 4 t/ temp [3:0] $end
$var wire 4 u/ c [3:0] $end
$scope module z1 $end
$var wire 1 v/ a $end
$var wire 1 w/ b $end
$var wire 1 x/ carry $end
$var wire 1 y/ sum $end
$upscope $end
$scope module z2 $end
$var wire 1 z/ a $end
$var wire 1 {/ b $end
$var wire 1 |/ carry $end
$var wire 1 }/ sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module memory16bit_1 $end
$var wire 1 + clock $end
$var wire 16 ~/ d [15:0] $end
$var wire 1 2 enable $end
$var wire 1 1 reset $end
$var wire 16 !0 q [15:0] $end
$var wire 1 2) done $end
$var reg 1 2) done_reg $end
$var reg 16 "0 q_reg [15:0] $end
$upscope $end
$scope module memory1bit_1 $end
$var wire 1 + clock $end
$var wire 1 ') d $end
$var wire 1 $) done $end
$var wire 1 2 enable $end
$var wire 1 5) q $end
$var wire 1 1 reset $end
$var reg 1 #0 d_reg $end
$upscope $end
$upscope $end
$scope module memory_1 $end
$var wire 8 $0 a [7:0] $end
$var wire 1 + clock $end
$var wire 1 x( enable $end
$var wire 1 1 reset $end
$var wire 8 %0 w [7:0] $end
$var reg 8 &0 d [7:0] $end
$var reg 1 $ done $end
$var reg 8 '0 q [7:0] $end
$upscope $end
$scope module your_instance_name $end
$var wire 8 (0 A [7:0] $end
$var wire 8 )0 B [7:0] $end
$var wire 8 *0 S [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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x#0
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xe/
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x`/
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bx Q/
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bx O/
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