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chleroygregkh
chleroy
authored and
gregkh
committed
powerpc/32s: fix suspend/resume when IBATs 4-7 are used
commit 6ecb78e upstream. Previously, only IBAT1 and IBAT2 were used to map kernel linear mem. Since commit 63b2bc6 ("powerpc/mm/32s: Use BATs for STRICT_KERNEL_RWX"), we may have all 8 BATs used for mapping kernel text. But the suspend/restore functions only save/restore BATs 0 to 3, and clears BATs 4 to 7. Make suspend and restore functions respectively save and reload the 8 BATs on CPUs having MMU_FTR_USE_HIGH_BATS feature. Reported-by: Andreas Schwab <schwab@linux-m68k.org> Cc: stable@vger.kernel.org Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent d0c4b05 commit dae64e9

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-13
lines changed

2 files changed

+128
-13
lines changed

‎arch/powerpc/kernel/swsusp_32.S‎

Lines changed: 65 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -23,11 +23,19 @@
2323
#define SL_IBAT2 0x48
2424
#define SL_DBAT3 0x50
2525
#define SL_IBAT3 0x58
26-
#define SL_TB 0x60
27-
#define SL_R2 0x68
28-
#define SL_CR 0x6c
29-
#define SL_LR 0x70
30-
#define SL_R12 0x74 /* r12 to r31 */
26+
#define SL_DBAT4 0x60
27+
#define SL_IBAT4 0x68
28+
#define SL_DBAT5 0x70
29+
#define SL_IBAT5 0x78
30+
#define SL_DBAT6 0x80
31+
#define SL_IBAT6 0x88
32+
#define SL_DBAT7 0x90
33+
#define SL_IBAT7 0x98
34+
#define SL_TB 0xa0
35+
#define SL_R2 0xa8
36+
#define SL_CR 0xac
37+
#define SL_LR 0xb0
38+
#define SL_R12 0xb4 /* r12 to r31 */
3139
#define SL_SIZE (SL_R12 + 80)
3240

3341
.section .data
@@ -112,6 +120,41 @@ _GLOBAL(swsusp_arch_suspend)
112120
mfibatl r4,3
113121
stw r4,SL_IBAT3+4(r11)
114122

123+
BEGIN_MMU_FTR_SECTION
124+
mfspr r4,SPRN_DBAT4U
125+
stw r4,SL_DBAT4(r11)
126+
mfspr r4,SPRN_DBAT4L
127+
stw r4,SL_DBAT4+4(r11)
128+
mfspr r4,SPRN_DBAT5U
129+
stw r4,SL_DBAT5(r11)
130+
mfspr r4,SPRN_DBAT5L
131+
stw r4,SL_DBAT5+4(r11)
132+
mfspr r4,SPRN_DBAT6U
133+
stw r4,SL_DBAT6(r11)
134+
mfspr r4,SPRN_DBAT6L
135+
stw r4,SL_DBAT6+4(r11)
136+
mfspr r4,SPRN_DBAT7U
137+
stw r4,SL_DBAT7(r11)
138+
mfspr r4,SPRN_DBAT7L
139+
stw r4,SL_DBAT7+4(r11)
140+
mfspr r4,SPRN_IBAT4U
141+
stw r4,SL_IBAT4(r11)
142+
mfspr r4,SPRN_IBAT4L
143+
stw r4,SL_IBAT4+4(r11)
144+
mfspr r4,SPRN_IBAT5U
145+
stw r4,SL_IBAT5(r11)
146+
mfspr r4,SPRN_IBAT5L
147+
stw r4,SL_IBAT5+4(r11)
148+
mfspr r4,SPRN_IBAT6U
149+
stw r4,SL_IBAT6(r11)
150+
mfspr r4,SPRN_IBAT6L
151+
stw r4,SL_IBAT6+4(r11)
152+
mfspr r4,SPRN_IBAT7U
153+
stw r4,SL_IBAT7(r11)
154+
mfspr r4,SPRN_IBAT7L
155+
stw r4,SL_IBAT7+4(r11)
156+
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
157+
115158
#if 0
116159
/* Backup various CPU config stuffs */
117160
bl __save_cpu_setup
@@ -277,27 +320,41 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
277320
mtibatu 3,r4
278321
lwz r4,SL_IBAT3+4(r11)
279322
mtibatl 3,r4
280-
#endif
281-
282323
BEGIN_MMU_FTR_SECTION
283-
li r4,0
324+
lwz r4,SL_DBAT4(r11)
284325
mtspr SPRN_DBAT4U,r4
326+
lwz r4,SL_DBAT4+4(r11)
285327
mtspr SPRN_DBAT4L,r4
328+
lwz r4,SL_DBAT5(r11)
286329
mtspr SPRN_DBAT5U,r4
330+
lwz r4,SL_DBAT5+4(r11)
287331
mtspr SPRN_DBAT5L,r4
332+
lwz r4,SL_DBAT6(r11)
288333
mtspr SPRN_DBAT6U,r4
334+
lwz r4,SL_DBAT6+4(r11)
289335
mtspr SPRN_DBAT6L,r4
336+
lwz r4,SL_DBAT7(r11)
290337
mtspr SPRN_DBAT7U,r4
338+
lwz r4,SL_DBAT7+4(r11)
291339
mtspr SPRN_DBAT7L,r4
340+
lwz r4,SL_IBAT4(r11)
292341
mtspr SPRN_IBAT4U,r4
342+
lwz r4,SL_IBAT4+4(r11)
293343
mtspr SPRN_IBAT4L,r4
344+
lwz r4,SL_IBAT5(r11)
294345
mtspr SPRN_IBAT5U,r4
346+
lwz r4,SL_IBAT5+4(r11)
295347
mtspr SPRN_IBAT5L,r4
348+
lwz r4,SL_IBAT6(r11)
296349
mtspr SPRN_IBAT6U,r4
350+
lwz r4,SL_IBAT6+4(r11)
297351
mtspr SPRN_IBAT6L,r4
352+
lwz r4,SL_IBAT7(r11)
298353
mtspr SPRN_IBAT7U,r4
354+
lwz r4,SL_IBAT7+4(r11)
299355
mtspr SPRN_IBAT7L,r4
300356
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
357+
#endif
301358

302359
/* Flush all TLBs */
303360
lis r4,0x1000

‎arch/powerpc/platforms/powermac/sleep.S‎

Lines changed: 63 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,18 @@
3737
#define SL_IBAT2 0x48
3838
#define SL_DBAT3 0x50
3939
#define SL_IBAT3 0x58
40-
#define SL_TB 0x60
41-
#define SL_R2 0x68
42-
#define SL_CR 0x6c
43-
#define SL_R12 0x70 /* r12 to r31 */
40+
#define SL_DBAT4 0x60
41+
#define SL_IBAT4 0x68
42+
#define SL_DBAT5 0x70
43+
#define SL_IBAT5 0x78
44+
#define SL_DBAT6 0x80
45+
#define SL_IBAT6 0x88
46+
#define SL_DBAT7 0x90
47+
#define SL_IBAT7 0x98
48+
#define SL_TB 0xa0
49+
#define SL_R2 0xa8
50+
#define SL_CR 0xac
51+
#define SL_R12 0xb0 /* r12 to r31 */
4452
#define SL_SIZE (SL_R12 + 80)
4553

4654
.section .text
@@ -125,6 +133,41 @@ _GLOBAL(low_sleep_handler)
125133
mfibatl r4,3
126134
stw r4,SL_IBAT3+4(r1)
127135

136+
BEGIN_MMU_FTR_SECTION
137+
mfspr r4,SPRN_DBAT4U
138+
stw r4,SL_DBAT4(r1)
139+
mfspr r4,SPRN_DBAT4L
140+
stw r4,SL_DBAT4+4(r1)
141+
mfspr r4,SPRN_DBAT5U
142+
stw r4,SL_DBAT5(r1)
143+
mfspr r4,SPRN_DBAT5L
144+
stw r4,SL_DBAT5+4(r1)
145+
mfspr r4,SPRN_DBAT6U
146+
stw r4,SL_DBAT6(r1)
147+
mfspr r4,SPRN_DBAT6L
148+
stw r4,SL_DBAT6+4(r1)
149+
mfspr r4,SPRN_DBAT7U
150+
stw r4,SL_DBAT7(r1)
151+
mfspr r4,SPRN_DBAT7L
152+
stw r4,SL_DBAT7+4(r1)
153+
mfspr r4,SPRN_IBAT4U
154+
stw r4,SL_IBAT4(r1)
155+
mfspr r4,SPRN_IBAT4L
156+
stw r4,SL_IBAT4+4(r1)
157+
mfspr r4,SPRN_IBAT5U
158+
stw r4,SL_IBAT5(r1)
159+
mfspr r4,SPRN_IBAT5L
160+
stw r4,SL_IBAT5+4(r1)
161+
mfspr r4,SPRN_IBAT6U
162+
stw r4,SL_IBAT6(r1)
163+
mfspr r4,SPRN_IBAT6L
164+
stw r4,SL_IBAT6+4(r1)
165+
mfspr r4,SPRN_IBAT7U
166+
stw r4,SL_IBAT7(r1)
167+
mfspr r4,SPRN_IBAT7L
168+
stw r4,SL_IBAT7+4(r1)
169+
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
170+
128171
/* Backup various CPU config stuffs */
129172
bl __save_cpu_setup
130173

@@ -325,22 +368,37 @@ grackle_wake_up:
325368
mtibatl 3,r4
326369

327370
BEGIN_MMU_FTR_SECTION
328-
li r4,0
371+
lwz r4,SL_DBAT4(r1)
329372
mtspr SPRN_DBAT4U,r4
373+
lwz r4,SL_DBAT4+4(r1)
330374
mtspr SPRN_DBAT4L,r4
375+
lwz r4,SL_DBAT5(r1)
331376
mtspr SPRN_DBAT5U,r4
377+
lwz r4,SL_DBAT5+4(r1)
332378
mtspr SPRN_DBAT5L,r4
379+
lwz r4,SL_DBAT6(r1)
333380
mtspr SPRN_DBAT6U,r4
381+
lwz r4,SL_DBAT6+4(r1)
334382
mtspr SPRN_DBAT6L,r4
383+
lwz r4,SL_DBAT7(r1)
335384
mtspr SPRN_DBAT7U,r4
385+
lwz r4,SL_DBAT7+4(r1)
336386
mtspr SPRN_DBAT7L,r4
387+
lwz r4,SL_IBAT4(r1)
337388
mtspr SPRN_IBAT4U,r4
389+
lwz r4,SL_IBAT4+4(r1)
338390
mtspr SPRN_IBAT4L,r4
391+
lwz r4,SL_IBAT5(r1)
339392
mtspr SPRN_IBAT5U,r4
393+
lwz r4,SL_IBAT5+4(r1)
340394
mtspr SPRN_IBAT5L,r4
395+
lwz r4,SL_IBAT6(r1)
341396
mtspr SPRN_IBAT6U,r4
397+
lwz r4,SL_IBAT6+4(r1)
342398
mtspr SPRN_IBAT6L,r4
399+
lwz r4,SL_IBAT7(r1)
343400
mtspr SPRN_IBAT7U,r4
401+
lwz r4,SL_IBAT7+4(r1)
344402
mtspr SPRN_IBAT7L,r4
345403
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
346404

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