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Commits on Jul 16, 2020

• Added ALTERA_TAPS delay type

  pConst

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Commits on Jul 9, 2020

• Updated delay module. Added block RAM implementation

  pConst

  committed
  b57c3a9

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• Added preview FIFO testbench

  pConst

  committed
  d2f436d

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• Added preview FIFO

  pConst

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Commits on May 22, 2020

• Updated edge_detect to v.3

  pConst

  committed
  bb246b3

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• Added DSE launch script

  pConst

  committed
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• Added Quartus project cleaning script

  pConst

  committed
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Commits on May 6, 2020

• Added testbench screenshots

  pConst

  committed
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• Added PDM modulator

  pConst

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Commits on May 5, 2020

• Added PWM modulator module and a testbench

  pConst

  committed
  380f3a1

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• Updated pulse_gen to ver.2

  pConst

  committed
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Commits on Apr 23, 2020

• Added JTAG server setup script

  pConst

  committed
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Commits on Apr 16, 2020

• Minor fixes

  pConst

  committed
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Commits on Apr 7, 2020

• Updated readme

  pConst

  committed
  4da5e8b

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• Merge branch 'master' of https://github.com/pConst/basic_verilog

  pConst

  committed
  d82a3bc

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• added script to set project directory in Vivado

  

  Konstantin Pavlov

  committed
  8d3ea38

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• Added benchmark project for Vivado IDE

  

  Konstantin Pavlov

  committed
  573cc6e

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• Updated post flow script for Vivado

  

  Konstantin Pavlov

  committed
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Commits on Feb 28, 2020

• Two random generators with different seed values

  pConst

  committed
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Commits on Feb 27, 2020

• Added test project template

  pConst

  committed
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Commits on Feb 25, 2020

• Added gray code converters

  pConst

  committed
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• Fixed header info in some testbenches

  pConst

  committed
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Commits on Feb 11, 2020

• Added PRBS test sequence generator and chekker

  pConst

  committed
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Commits on Feb 6, 2020

• Added more scripts for Quartus IDE

  pConst

  committed
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• Added pulse generator module

  pConst

  committed
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Commits on Dec 13, 2019

• Added adder_tree module and testbench

  pConst

  committed
  4682b7e

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• Updated delay module to support LENGTH=0

  pConst

  committed
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• Updated SR trigger variation modules

  pConst

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Commits on Nov 15, 2019

• Restored testbenches

  pConst

  committed
  51f484b

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• Added pulse_stretch.sv and testbench

  pConst

  committed
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Commits on Nov 14, 2019

• Deleted obsolete files

  pConst

  committed
  99eaebc

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• Added pulse_stretch.sv module

  pConst

  committed
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Commits on Oct 17, 2019

• Added module to convert data from big-endian to little-endian and back

  pConst

  committed
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• Added module to pack Verilog-2001 arrays

  pConst

  committed
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Commits on Oct 2, 2019

• Added script to program Altera/Intel devices

  pConst

  committed
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