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Support for ARM SVE2. #8051

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merged 51 commits into from
Mar 15, 2024
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77ea0a0
Checkpoint SVE2 restart.
Dec 14, 2023
c203d1e
Remove dead code. Add new test.
Dec 14, 2023
27ee93e
Update cmake for new file.
Dec 14, 2023
bf0e925
Checkpoint progress on SVE2.
Dec 16, 2023
f40eeb5
Merge branch 'main' into arm_sve_redux
Jan 9, 2024
deb5fbc
Checkpoint ARM SVE2 support. Passes correctness_simd_op_check_sve2 te…
Jan 18, 2024
51c4568
Merge branch 'main' into arm_sve_redux
Jan 18, 2024
5f98675
Remove an opportunity for RISC V codegen to change due to SVE2 support.
Jan 18, 2024
1b8a75e
Ensure SVE intrinsics get vscale vectors and non-SVE ones get fixed v…
Jan 19, 2024
5eeef77
Checkpoint SVE2 work. Generally passes test, though using both NEON
Jan 26, 2024
f57f1d3
Remove an unfavored implementation possibility.
Jan 26, 2024
da3c259
Fix opcode recognition in test to handle some cases that show up.
Jan 29, 2024
06fa66c
Merge branch 'main' into arm_sve_redux
Jan 29, 2024
a069e6e
Formatting fixes.
Jan 29, 2024
1e8a540
Formatting fix.
Jan 29, 2024
93fb752
Limit SVE2 test to LLVM 19.
Jan 30, 2024
de11e8f
Fix a degenerate case asking for zero sized vectors via a HAlide type
Jan 31, 2024
9b2897c
Merge branch 'main' into arm_sve_redux
Feb 6, 2024
2bc10e3
Merge branch 'main' into arm_sve_redux
steven-johnson Feb 7, 2024
c598c9d
Merge branch 'main' into arm_sve_redux
Feb 7, 2024
bb73c00
Fix confusion about Neon64/Neon128 and make it clear this is just the
Feb 11, 2024
65fff76
Merge branch 'arm_sve_redux' of https://github.com/halide/Halide into…
Feb 11, 2024
93d7ba9
REmove extraneous commented out line.
Feb 11, 2024
ba934e9
Address some review feedback. Mostly comment fixes.
Feb 11, 2024
00cb4ce
Merge branch 'main' into arm_sve_redux
Feb 11, 2024
229bb60
Fix missed conflict resolution.
Feb 11, 2024
42206a5
Fix some TODOs in SVE code. Move utility function to Util.h and common
Feb 12, 2024
90186ad
Formatting.
Feb 12, 2024
bc149bc
Add missed refactor change.
Feb 12, 2024
79776e0
Add issue to TODO comment.
Feb 12, 2024
c3ca689
Remove TODOs that don't seem necessary.
Feb 13, 2024
b0e4f99
Add issue for TODO.
Feb 13, 2024
417d762
Add issue for TODO.
Feb 13, 2024
6e6e491
Merge branch 'main' into arm_sve_redux
Feb 15, 2024
e25a947
Merge branch 'main' into arm_sve_redux
Feb 21, 2024
fe30990
Remove dubious looking FP to int code that was ifdef'ed out. Doesn't
Feb 21, 2024
dc3be8a
Add issues for TODOs.
Feb 22, 2024
7627e0d
Merge branch 'main' into arm_sve_redux
Feb 22, 2024
4a269bd
Merge branch 'main' into arm_sve_redux
Feb 23, 2024
6afdcff
Update simd_op_check_sve2.cpp
steven-johnson Feb 23, 2024
b03b3c7
Merge branch 'main' into arm_sve_redux
steven-johnson Feb 23, 2024
f8952c2
Make a deep copy of each piece of test IR so that we can parallelize
abadams Feb 23, 2024
eaed2ef
Merge branch 'arm_sve_redux' of https://github.com/halide/Halide into…
Mar 5, 2024
2ac96c8
Merge branch 'main' into arm_sve_redux
steven-johnson Mar 5, 2024
4324bc5
Fix two clang-tidy warnings
steven-johnson Mar 5, 2024
a63439b
Remove try/catch block from simd-op-check-sve2
steven-johnson Mar 5, 2024
f84c764
Merge branch 'arm_sve_redux' of https://github.com/halide/Halide into…
Mar 6, 2024
210e5d7
Don't try to run SVE2 code if vector_bits doesn't match host.
Mar 6, 2024
9d8e2c6
Add support for fcvtm/p, make scalars go through pattern matching too…
abadams Mar 13, 2024
32d1fcb
Merge remote-tracking branch 'origin/main' into arm_sve_redux
abadams Mar 13, 2024
9dbfcd5
Don't do arm neon instruction selection on scalars
abadams Mar 14, 2024
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Remove dubious looking FP to int code that was ifdef'ed out. Doesn't
look like a TODO is needed anymore.
  • Loading branch information
Z Stern committed Feb 21, 2024
commit fe30990eb4493baeb7581d29d5b961b6b41a5a4e
14 changes: 0 additions & 14 deletions src/CodeGen_ARM.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1153,27 +1153,13 @@ void CodeGen_ARM::visit(const Cast *op) {
}
}

// TODO(<issue needed>): Resolve whether this is still needed.
#if 1
// LLVM fptoui generates fcvtzs or fcvtzu in inconsistent way
if (op->value.type().is_float() && op->type.is_int_or_uint()) {
if (Value *v = call_overloaded_intrin(op->type, "fp_to_int", {op->value})) {
value = v;
return;
}
}
#else
// LLVM fptoui generates fcvtzs if src is fp16 scalar else fcvtzu.
// To avoid that, we use neon intrinsic explicitly.
if (is_float16_and_has_feature(op->value.type())) {
if (op->type.is_int_or_uint() && op->type.bits() == 16) {
value = call_overloaded_intrin(op->type, "fp_to_int", {op->value});
if (value) {
return;
}
}
}
#endif

CodeGen_Posix::visit(op);
}
Expand Down
2 changes: 1 addition & 1 deletion src/CodeGen_LLVM.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4771,7 +4771,7 @@ Value *CodeGen_LLVM::call_intrin(const llvm::Type *result_type, int intrin_lanes
bool formal_is_fixed = isa<FixedVectorType>(formal_param_type);

// Apparently the bitcast in the else branch below can
// change the scalar type and vector length togehter so
// change the scalar type and vector length together so
// long as the total bits are the same. E.g. on HVX,
// <128 x i16> to <64 x i32>. This is probably a bug, but
// it seems to be allowed so it is also supported in the
Expand Down