PicoRV32 - A Size-Optimized RISC-V CPU

IC design and development should be faster，simpler and more reliable

Must-have verilog systemverilog modules

HDL libraries and projects

SERV - The SErial RISC-V CPU

synthesiseable ieee 754 floating point library in verilog

Verilog UART

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

IEEE 754 floating point unit in Verilog

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

一个FPGA核心板设计，体积小、低成本、易用、扩展性强。

A small SoC with a pipeline 32-bit RISC-V CPU.

FFT generator using Chisel

HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one

Single Cycle Processor based on the RISC-V ISA. Supports R-type, lw, sw, and beq instructions.

Last-in-First-out Buffer

Implementation of the RISC V Single-Cycle Processor