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@hVHDL

hVHDL

README.md

High level synthesisable VHDL (hVHDL) is a set of coding patterns for standard VHDL which are designed to greatly increase abstraction level of VHDL source code using standard synthesis tools. The coding patterns are designed to support incremental design, testing and development of the VHDL source code. All code has been tested with an FPGA using Xilinx Vivado, Lattice Diamond and Radiant or Efinix Efinity tools.

hVHDL project libraries found in repositories are written to be imported as git submodules to any (V)HDL project. To use the submodules, just add them to your project using Git, add sources to your project compile script, use them for an application, simulate and build. All of the syntesizable code is written in VHDL2008, so they should be useable with any modern tool.

Code in all modules is used through an abstracted interface which is implemented with records, functions and procedures. Code is written using records to specify the registers and a procedure is used to create the logic for the registers as well as accessing the functionality. Most code is thus used with just a signal of module record type and subroutines that then take this signal as argument.

The key idea behind the patterns are 1) all code should be shareable 2) all code should be changeable when needed. To accomplish these two almost opposite ideas we have designed specific patterns for coding

  • all functionality should be behind abstract interfaces
  • all code modules should have the possibility to exert backpressure - there should be no need to time code
  • Use any IP from any vendor, add abstract interface if not already given by vendor

For a quick start there is an example project that uses the main features of hVHDL libraries. The test project creates a noisy sine wave that is then filtered using fixed and floating point filters that are written in using hVHDL modules. Running the test_app.py reads and writes registers in the FPGA and prints out the results to the console and additionally requests a 200 000 data point stream from the FPGA that is then plotted using pyplot.

There is an in-depth explanation which goes through the VHDL source code of the design.

The example project has been built with Lattice Diamond, Xilinx Vivado and Efinix Efinity and tested with lattice ECP5 and Spartan 7 FPGAs. The build scripts can be found in the example projects repository.

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  1. hVHDL_example_project hVHDL_example_project Public

    An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs

    VHDL 24 3

Repositories

Showing 10 of 12 repositories
  • hVHDL_dynamic_model_verification_library Public

    Synthesizable VHDL models for HiL Simulation

    hVHDL/hVHDL_dynamic_model_verification_library’s past year of commit activity
    VHDL 9 MIT 1 0 0 Updated Oct 20, 2024
  • hVHDL_uart Public

    VHDL library for uart with abstracted interface for easy application.

    hVHDL/hVHDL_uart’s past year of commit activity
    VHDL 3 MIT 0 0 0 Updated Aug 24, 2024
  • .github Public
    hVHDL/.github’s past year of commit activity
    0 MIT 0 0 0 Updated Aug 15, 2024
  • hVHDL_fixed_point Public

    VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.

    hVHDL/hVHDL_fixed_point’s past year of commit activity
    VHDL 22 MIT 4 0 0 Updated Aug 9, 2024
  • hVHDL_fpga_interconnect Public

    interconnecting bus written in VHDL for accessing data in FPGA modules

    hVHDL/hVHDL_fpga_interconnect’s past year of commit activity
    VHDL 5 MIT 1 0 0 Updated Aug 2, 2024
  • hVHDL_microprogam_processor Public

    VHDL module for running operations from memory with the software also written in vhdl

    hVHDL/hVHDL_microprogam_processor’s past year of commit activity
    VHDL 6 MIT 0 0 0 Updated Jul 20, 2024
  • hVHDL_memory_library Public

    Memory library written in VHDL for synthesis

    hVHDL/hVHDL_memory_library’s past year of commit activity
    VHDL 6 MIT 1 0 0 Updated Jul 20, 2024
  • hVHDL_floating_point Public

    high level VHDL floating point library for synthesis in fpga

    hVHDL/hVHDL_floating_point’s past year of commit activity
    VHDL 15 MIT 2 0 0 Updated Jul 15, 2024
  • hVHDL_example_project Public

    An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs

    hVHDL/hVHDL_example_project’s past year of commit activity
    VHDL 24 MIT 3 0 0 Updated Jun 26, 2024
  • hVHDL Public

    documentation pages for High Level Synthesizable VHDL (hVHDL) libraries

    hVHDL/hVHDL’s past year of commit activity
    Python 10 0 0 0 Updated Jan 4, 2024
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