A cross clock domain queue.
class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3, safe: Boolean = true) extends Crossing[T]
- I/O, type and Paramter
name | type | direction | description |
---|---|---|---|
T | Data | type | payload type |
gen | T | param | type parameter |
depth | Int = 8 | param | size of queue |
sync | Int = 3 | param | depth of clock synchronizer |
safe | Boolean = true | param | whether enforce self-satble |
enq_clock | Clock | I | source side clock |
enq_reset | Bool | I | source side reset |
enq | DecoupledIO[T] | I | source side write port |
deq_clock | Clock | I | sink side clock |
deq_reset | Bool | I | sink side reset |
deq | DecoupledIO[T] | O | sink side write port |
It is better to set safe
to true if source and sink do not share the same reset.
A gray counter
- apply
(bits: Int, increment: Bool = Bool(true), clear: Bool = Bool(false), name: String = "binary") => UInt
The actual register is binary formated.
A register FIFO chain.
- apply
(in: UInt, sync: Int, name: String = "gray") => UInt
sync
: the depth of the FIFO.
A 1-bit FIFO chain.
class AsyncValidSync(sync: Int, desc: String) extends Module
- I/O and Paramter
name | type | direction | description |
---|---|---|---|
sync | Int | param | depth of the FIFO |
desc | String | param | name of the FIFO |
in | Bool | I | input |
out | Bool | O | output |
A corss clock-domain queue, the part on the soruce side.
class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean = true) extends Module
- I/O, type and Paramter
name | type | direction | description |
---|---|---|---|
T | Data | type | payload type |
gen | T | param | type parameter |
depth | Int | param | size of queue |
sync | Int | param | depth of clock synchronizer |
safe | Boolean | param | whether enforce self-satble |
enq | DecoupledIO[T] | I | write port for source |
ridx | UInt | I | read pointer from sink (grey code) |
widx | UInt | O | write pointer for source (grey code) |
mem | Vec[T] | O | queue content for sink to read |
sink_reset_n | Bool | I | sink side reset (active low) |
ridx_valid | Bool | I | sink side read pointer valid |
widx_valid | Bool | O | source side write pointer valid |
When safe is set high, source side is able to write when the read pointer is valid and synchronoized (sync+1 cycle delay).
A corss clock-domain queue, the part on the sink side.
class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean = true) extends Module
- I/O, type and Paramter
name | type | direction | description |
---|---|---|---|
T | Data | type | payload type |
gen | T | param | type parameter |
depth | Int | param | size of queue |
sync | Int | param | depth of clock synchronizer |
safe | Boolean | param | whether enforce self-satble |
deq | DecoupledIO[T] | O | read port for sink |
ridx | UInt | O | read pointer for sink (grey code) |
widx | UInt | I | write pointer from source (grey code) |
mem | Vec[T] | I | queue content for sink to read |
source_reset_n | Bool | I | sink side reset (active low) |
ridx_valid | Bool | O | sink side read pointer valid |
widx_valid | Bool | I | source side write pointer valid |
When safe is set high, sink side is able to read when the write pointer is valid and synchronoized (sync+1 cycle delay).
Last updated: 09/07/2017
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