aarch64: Add optimized local/argument read defines

```

.global _start
_start:
ldr x0,[x17,8]
ldr x0,[x17,16]
ldr x0,[x17,24]
ldr x0,[x17,32]
ldr x0,[x17,40]
ldr x0,[x17,48]
ldr x0,[x17,56]
ldr x0,[x17,64]
ldr x0,[x17,72]
ldr x0,[x17,80]
ldr x0,[x17,88]
ldr x0,[x17,96]
ldr x0,[x17,104]
ldr x0,[x17,112]
ldr x0,[x17,120]
ldr x0,[x17,128]

sub x0,x17,8
sub x0,x17,16
sub x0,x17,24
sub x0,x17,32
sub x0,x17,40
sub x0,x17,48
sub x0,x17,56
sub x0,x17,64
sub x0,x17,72
sub x0,x17,80
sub x0,x17,88
sub x0,x17,96
sub x0,x17,104
sub x0,x17,112
sub x0,x17,120
sub x0,x17,128

sub x0,x13,8
sub x0,x13,16
sub x0,x13,24
sub x0,x13,32
sub x0,x13,40
sub x0,x13,48
sub x0,x13,56
sub x0,x13,64
sub x0,x13,72
sub x0,x13,80
sub x0,x13,88
sub x0,x13,96
sub x0,x13,104
sub x0,x13,112
sub x0,x13,120
sub x0,x13,128

```

```

/tmp/main-aarch64:     file format elf64-littleaarch64

Disassembly of section .text:

0000000000400078 <_start>:
  400078:	f9400620 	ldr	x0, [x17, oriansj#8]
  40007c:	f9400a20 	ldr	x0, [x17, oriansj#16]
  400080:	f9400e20 	ldr	x0, [x17, oriansj#24]
  400084:	f9401220 	ldr	x0, [x17, oriansj#32]
  400088:	f9401620 	ldr	x0, [x17, oriansj#40]
  40008c:	f9401a20 	ldr	x0, [x17, oriansj#48]
  400090:	f9401e20 	ldr	x0, [x17, oriansj#56]
  400094:	f9402220 	ldr	x0, [x17, oriansj#64]
  400098:	f9402620 	ldr	x0, [x17, oriansj#72]
  40009c:	f9402a20 	ldr	x0, [x17, oriansj#80]
  4000a0:	f9402e20 	ldr	x0, [x17, oriansj#88]
  4000a4:	f9403220 	ldr	x0, [x17, oriansj#96]
  4000a8:	f9403620 	ldr	x0, [x17, oriansj#104]
  4000ac:	f9403a20 	ldr	x0, [x17, #112]
  4000b0:	f9403e20 	ldr	x0, [x17, #120]
  4000b4:	f9404220 	ldr	x0, [x17, #128]
  4000b8:	d1002220 	sub	x0, x17, #0x8
  4000bc:	d1004220 	sub	x0, x17, #0x10
  4000c0:	d1006220 	sub	x0, x17, #0x18
  4000c4:	d1008220 	sub	x0, x17, #0x20
  4000c8:	d100a220 	sub	x0, x17, #0x28
  4000cc:	d100c220 	sub	x0, x17, #0x30
  4000d0:	d100e220 	sub	x0, x17, #0x38
  4000d4:	d1010220 	sub	x0, x17, #0x40
  4000d8:	d1012220 	sub	x0, x17, #0x48
  4000dc:	d1014220 	sub	x0, x17, #0x50
  4000e0:	d1016220 	sub	x0, x17, #0x58
  4000e4:	d1018220 	sub	x0, x17, #0x60
  4000e8:	d101a220 	sub	x0, x17, #0x68
  4000ec:	d101c220 	sub	x0, x17, #0x70
  4000f0:	d101e220 	sub	x0, x17, #0x78
  4000f4:	d1020220 	sub	x0, x17, #0x80
  4000f8:	d10021a0 	sub	x0, x13, #0x8
  4000fc:	d10041a0 	sub	x0, x13, #0x10
  400100:	d10061a0 	sub	x0, x13, #0x18
  400104:	d10081a0 	sub	x0, x13, #0x20
  400108:	d100a1a0 	sub	x0, x13, #0x28
  40010c:	d100c1a0 	sub	x0, x13, #0x30
  400110:	d100e1a0 	sub	x0, x13, #0x38
  400114:	d10101a0 	sub	x0, x13, #0x40
  400118:	d10121a0 	sub	x0, x13, #0x48
  40011c:	d10141a0 	sub	x0, x13, #0x50
  400120:	d10161a0 	sub	x0, x13, #0x58
  400124:	d10181a0 	sub	x0, x13, #0x60
  400128:	d101a1a0 	sub	x0, x13, #0x68
  40012c:	d101c1a0 	sub	x0, x13, #0x70
  400130:	d101e1a0 	sub	x0, x13, #0x78
  400134:	d10201a0 	sub	x0, x13, #0x80

```

Author: gtker

aarch64/aarch64_defs.M1

@@ -181,6 +181,56 @@ DEFINE ldr_x8,[sp,32] e81340f9
 DEFINE ldr_x8,[sp,40] e81740f9
 DEFINE ldr_x8,[sp,48] e81b40f9
 
+DEFINE ldr_x0,[x17,8] 200640f9
+DEFINE ldr_x0,[x17,16] 200a40f9
+DEFINE ldr_x0,[x17,24] 200e40f9
+DEFINE ldr_x0,[x17,32] 201240f9
+DEFINE ldr_x0,[x17,40] 201640f9
+DEFINE ldr_x0,[x17,48] 201a40f9
+DEFINE ldr_x0,[x17,56] 201e40f9
+DEFINE ldr_x0,[x17,64] 202240f9
+DEFINE ldr_x0,[x17,72] 202640f9
+DEFINE ldr_x0,[x17,80] 202a40f9
+DEFINE ldr_x0,[x17,88] 202e40f9
+DEFINE ldr_x0,[x17,96] 203240f9
+DEFINE ldr_x0,[x17,104] 203640f9
+DEFINE ldr_x0,[x17,112] 203a40f9
+DEFINE ldr_x0,[x17,120] 203e40f9
+DEFINE ldr_x0,[x17,128] 204240f9
+
+DEFINE sub_x0,x13,8 a02100d1
+DEFINE sub_x0,x13,16 a04100d1
+DEFINE sub_x0,x13,24 a06100d1
+DEFINE sub_x0,x13,32 a08100d1
+DEFINE sub_x0,x13,40 a0a100d1
+DEFINE sub_x0,x13,48 a0c100d1
+DEFINE sub_x0,x13,56 a0e100d1
+DEFINE sub_x0,x13,64 a00101d1
+DEFINE sub_x0,x13,72 a02101d1
+DEFINE sub_x0,x13,80 a04101d1
+DEFINE sub_x0,x13,88 a06101d1
+DEFINE sub_x0,x13,96 a08101d1
+DEFINE sub_x0,x13,104 a0a101d1
+DEFINE sub_x0,x13,112 a0c101d1
+DEFINE sub_x0,x13,120 a0e101d1
+DEFINE sub_x0,x13,128 a00102d1
+
+DEFINE sub_x0,x17,8 202200d1
+DEFINE sub_x0,x17,16 204200d1
+DEFINE sub_x0,x17,24 206200d1
+DEFINE sub_x0,x17,32 208200d1
+DEFINE sub_x0,x17,40 20a200d1
+DEFINE sub_x0,x17,48 20c200d1
+DEFINE sub_x0,x17,56 20e200d1
+DEFINE sub_x0,x17,64 200201d1
+DEFINE sub_x0,x17,72 202201d1
+DEFINE sub_x0,x17,80 204201d1
+DEFINE sub_x0,x17,88 206201d1
+DEFINE sub_x0,x17,96 208201d1
+DEFINE sub_x0,x17,104 20a201d1
+DEFINE sub_x0,x17,112 20c201d1
+DEFINE sub_x0,x17,120 20e201d1
+DEFINE sub_x0,x17,128 200202d1
 
 # Move data between registers
 DEFINE mov_x0,x2 e00302aa