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circuits look more sane now
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4 files changed

+65
-24
lines changed

4 files changed

+65
-24
lines changed

‎src/atoms/sky130_mux.cc

Lines changed: 18 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1283,7 +1283,7 @@ void GenerateOutput2To1MuxLayout(
12831283
Rectangle met2_bb = met2_bar->GetBoundingBox();
12841284
main_layout->AddPort(geometry::Port(
12851285
met2_bb.centre(), met2_bb.Height(), met2_bb.Height(),
1286-
met2_bar->layer(), "Y"));
1286+
met2_bar->layer(), "Z"));
12871287

12881288
main_layout->SavePoint(
12891289
"output_mux_met2_bar_left_contact",
@@ -2248,16 +2248,19 @@ bfg::Circuit *Sky130Mux::GenerateCircuit() {
22482248
Wire S2 = circuit->AddSignal("S2");
22492249
Wire S2_B = circuit->AddSignal("S2_B");
22502250

2251-
Wire X0 = circuit->AddSignal("X0");
2252-
Wire X1 = circuit->AddSignal("X1");
2253-
Wire X2 = circuit->AddSignal("X2");
2254-
Wire X3 = circuit->AddSignal("X3");
2255-
Wire X4 = circuit->AddSignal("X4");
2256-
Wire X5 = circuit->AddSignal("X5");
2257-
Wire X6 = circuit->AddSignal("X6");
2258-
Wire X7 = circuit->AddSignal("X7");
2251+
// TODO(aryap): It would be nice if the layout code consistently refered to
2252+
// these as "Xi", not "input_i", but in fairness that is much harder to keep
2253+
// in your head.
2254+
Wire X0 = circuit->AddSignal("input_0");
2255+
Wire X1 = circuit->AddSignal("input_1");
2256+
Wire X2 = circuit->AddSignal("input_2");
2257+
Wire X3 = circuit->AddSignal("input_3");
2258+
Wire X4 = circuit->AddSignal("input_4");
2259+
Wire X5 = circuit->AddSignal("input_5");
2260+
Wire X6 = circuit->AddSignal("input_6");
2261+
Wire X7 = circuit->AddSignal("input_7");
22592262

2260-
Wire Y = circuit->AddSignal("Y");
2263+
Wire Z = circuit->AddSignal("Z");
22612264

22622265
Wire VPWR = circuit->AddSignal("VPWR");
22632266
Wire VGND = circuit->AddSignal("VGND");
@@ -2282,7 +2285,7 @@ bfg::Circuit *Sky130Mux::GenerateCircuit() {
22822285
circuit->AddPort(X5);
22832286
circuit->AddPort(X6);
22842287
circuit->AddPort(X7);
2285-
circuit->AddPort(Y);
2288+
circuit->AddPort(Z);
22862289
circuit->AddPort(VPWR);
22872290
circuit->AddPort(VGND);
22882291

@@ -2416,7 +2419,7 @@ bfg::Circuit *Sky130Mux::GenerateCircuit() {
24162419
A3,
24172420
S2,
24182421
S2_B,
2419-
Y,
2422+
Z,
24202423
VPWR,
24212424
VGND));
24222425
circuit->AddCircuit(*output_mux_circuit, "output_mux2");
@@ -3528,7 +3531,7 @@ bfg::Circuit *Sky130Mux::GenerateMux2Circuit(
35283531
parameters.s1_b_wire.value_or(circuit->AddSignal("S1_B"));
35293532

35303533
// Output.
3531-
Wire Y = parameters.y_wire.value_or(circuit->AddSignal("Y"));
3534+
Wire Z = parameters.y_wire.value_or(circuit->AddSignal("Z"));
35323535

35333536
// Intermediate signals.
35343537
Wire A0 = circuit->AddSignal("A0");
@@ -3569,8 +3572,8 @@ bfg::Circuit *Sky130Mux::GenerateMux2Circuit(
35693572
fet_2->Connect({{"d", X3}, {"g", S0}, {"s", A0}, {"b", VB}});
35703573
fet_1->Connect({{"d", A1}, {"g", S0_B}, {"s", X0}, {"b", VB}});
35713574
fet_3->Connect({{"d", X1}, {"g", S0}, {"s", A1}, {"b", VB}});
3572-
fet_4->Connect({{"d", Y}, {"g", S1_B}, {"s", A1}, {"b", VB}});
3573-
fet_5->Connect({{"d", A0}, {"g", S1}, {"s", Y}, {"b", VB}});
3575+
fet_4->Connect({{"d", Z}, {"g", S1_B}, {"s", A1}, {"b", VB}});
3576+
fet_5->Connect({{"d", A0}, {"g", S1}, {"s", Z}, {"b", VB}});
35743577

35753578
// Assign model parameters from configuration struct.
35763579
std::array<circuit::Instance*, 6> fets = {

‎src/circuit.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,7 @@ ::vlsir::circuit::ExternalModule Circuit::ToVLSIRExternalModule() const {
323323
}
324324

325325
std::string Circuit::GenerateDefaultName() {
326-
std::string name = absl::StrCat("unnamed_", unnamed_net_count_);
326+
std::string name = absl::StrCat(kDefaultNetPrefix, unnamed_net_count_);
327327
unnamed_net_count_++;
328328
return name;
329329
}

‎src/circuit.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,8 @@ class Circuit {
105105
bool IsPowerOrGround(const circuit::Signal &signal) const;
106106

107107
private:
108+
static constexpr std::string_view kDefaultNetPrefix = "n_";
109+
108110
std::string GenerateDefaultName();
109111

110112
bfg::Cell *parent_cell_;

‎src/tiles/lut_b.cc

Lines changed: 44 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -118,11 +118,13 @@ Cell *LutB::GenerateIntoDatabase(const std::string &name) {
118118
circuit->AddPort(circuit->AddSignal("CONFIG_IN"));
119119
circuit->AddPort(circuit->AddSignal("CONFIG_OUT"));
120120

121-
// FIXME(aryap): There's actually one of these per bank.
122121
// Clock, power, ground in.
123122
circuit->AddPort(circuit->AddSignal("CLK"));
124-
circuit->AddPort(circuit->AddSignal("VPWR"));
125-
circuit->AddPort(circuit->AddSignal("VGND"));
123+
// TODO(aryap): For now there's actually one of these per bank.
124+
circuit->AddPort(circuit->AddSignal("VPWR_0"));
125+
circuit->AddPort(circuit->AddSignal("VPWR_1"));
126+
circuit->AddPort(circuit->AddSignal("VGND_0"));
127+
circuit->AddPort(circuit->AddSignal("VGND_1"));
126128

127129
// Layout.
128130
// ---------------------------------------------------------------------------
@@ -539,6 +541,10 @@ void LutB::RouteClockBuffers(RoutingGrid *routing_grid,
539541
.instance = clk_buf,
540542
.port_name = "A"
541543
});
544+
545+
// This matches the input port name, so that the connecting net label
546+
// matches the incoming port label.
547+
clk_inputs.net_name = "CLK";
542548
}
543549
auto result = AddMultiPointRoute(clk_inputs, routing_grid, circuit, layout);
544550
AccumulateAnyErrors(result);
@@ -677,6 +683,7 @@ void LutB::RouteMuxInputs(
677683
circuit->GetOrAddSignal(net_names.primary(), 1);
678684
memory->circuit_instance()->Connect("Q", *signal);
679685
mux->circuit_instance()->Connect(input_name, *signal);
686+
LOG(INFO) << input_name << " <- " << signal->name();
680687
} else {
681688
// FIXME(aryap): I am stupid. The set of names given to the router to
682689
// determine which shapes are connectable is different to the target
@@ -692,6 +699,7 @@ void LutB::RouteMuxInputs(
692699

693700
circuit::Signal *signal = circuit->GetOrAddSignal(target_net, 1);
694701
mux->circuit_instance()->Connect(input_name, *signal);
702+
LOG(INFO) << input_name << " <- " << signal->name();
695703
}
696704
if (route_result.ok()) {
697705
path_found = true;
@@ -744,7 +752,7 @@ void LutB::RouteRemainder(
744752
}, {
745753
.port_keys = {{mux_order_[1], "Z"}, {active_mux2s_[0], "A1"}},
746754
}, {
747-
.port_keys = {{active_mux2s_[0], "X"}, {buf_order_[3], "A"}},
755+
.port_keys = {{active_mux2s_[0], "X"}, {buf_order_[3], "P"}},
748756
}
749757
};
750758

@@ -753,16 +761,24 @@ void LutB::RouteRemainder(
753761
collection, routing_grid, circuit, layout);
754762
AccumulateAnyErrors(result);
755763
}
764+
765+
// FIXME(aryap): Make circuit-only connections (this is fake).
766+
for (size_t i = 0; i < buf_order_.size(); ++i) {
767+
std::string port_name = absl::StrCat("S", i);
768+
circuit::Signal *signal = circuit->GetOrAddSignal(port_name, 1);
769+
770+
buf_order_[i]->circuit_instance()->Connect("A", *signal);
771+
}
756772
}
757773

758774
// TODO(aryap): This clearly needs to be factored out of this class.
759775
absl::Status LutB::AddMultiPointRoute(const PortKeyCollection &collection,
760776
RoutingGrid *routing_grid,
761777
Circuit *circuit,
762778
Layout *layout) const {
763-
circuit::Wire internal_wire = circuit->AddSignal(
764-
collection.net_name ? *collection.net_name : "");
765-
std::string net = internal_wire.signal().name();
779+
circuit::Signal *internal_signal = circuit->GetOrAddSignal(
780+
collection.net_name ? *collection.net_name : "", 1);
781+
std::string net = internal_signal->name();
766782

767783
std::vector<std::vector<geometry::Port*>> route_targets;
768784
for (auto &port_key : collection.port_keys) {
@@ -771,7 +787,7 @@ absl::Status LutB::AddMultiPointRoute(const PortKeyCollection &collection,
771787
geometry::Instance *instance = port_key.instance;
772788

773789
circuit::Instance *circuit_instance = instance->circuit_instance();
774-
circuit_instance->Connect(port_key.port_name, internal_wire);
790+
circuit_instance->Connect(port_key.port_name, *internal_signal);
775791

776792
std::vector<geometry::Port*> matching_ports;
777793
instance->GetInstancePorts(port_key.port_name, &matching_ports);
@@ -900,6 +916,9 @@ void LutB::AddClockAndPowerStraps(
900916
static const std::array<std::string, 4> kNets =
901917
{"vpwr", "vgnd", "clk", "clk_i"};
902918

919+
static const std::array<std::string, 2> kCircuitOnlyPorts = {"VPB", "VNB"};
920+
static const std::array<std::string, 2> kCircuitOnlyPortNets = {"vpwr", "vgnd"};
921+
903922
constexpr int64_t kOffsetNumPitches = 0;
904923

905924
// FIXME(aryap): We are leaking technology-specific concerns into what was
@@ -986,6 +1005,23 @@ void LutB::AddClockAndPowerStraps(
9861005
layout);
9871006
routing_grid->AddBlockages(new_shapes);
9881007
}
1008+
1009+
// Connect circuit-only ports.
1010+
for (size_t i = 0; i < kCircuitOnlyPorts.size(); ++i) {
1011+
std::string net = absl::StrCat(kCircuitOnlyPortNets[i], "_", bank);
1012+
circuit::Signal *signal = circuit->GetOrAddSignal(net, 1);
1013+
const std::string &port_name = kCircuitOnlyPorts[i];
1014+
1015+
for (const auto &row : banks_.at(bank).instances()) {
1016+
for (geometry::Instance *instance : row) {
1017+
circuit::Instance *circuit_instance = instance->circuit_instance();
1018+
if (!circuit_instance) {
1019+
continue;
1020+
}
1021+
circuit_instance->Connect(port_name, *signal);
1022+
}
1023+
}
1024+
}
9891025
}
9901026
}
9911027

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