From b8fd6dc635ab332df3cba6b8c70cd4602882b3e2 Mon Sep 17 00:00:00 2001
From: Greta Yorsh <45005955+gretay-js@users.noreply.github.com>
Date: Tue, 31 Dec 2024 10:42:37 +0000
Subject: [PATCH] ASR 64-bit lane not available in sse instruction (#3413)

---
 backend/amd64/simd_selection.ml | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/backend/amd64/simd_selection.ml b/backend/amd64/simd_selection.ml
index 2955d27e6de..526d37d3f11 100644
--- a/backend/amd64/simd_selection.ml
+++ b/backend/amd64/simd_selection.ml
@@ -589,13 +589,14 @@ let vectorize_operation (width_type : Vectorize_utils.Width_in_bits.t)
       let sse_op =
         match width_type with
         | W128 -> assert false
-        | W64 -> assert false
-        | W32 -> SRA_i32
-        | W16 -> SRA_i16
-        | W8 -> assert false
+        | W64 -> None
+        | W32 -> Some SRA_i32
+        | W16 -> Some SRA_i16
+        | W8 -> None
       in
-      Operation.Specific (Isimd (SSE2 sse_op))
-      |> make_default ~arg_count ~res_count
+      Option.bind sse_op (fun sse_op ->
+          Operation.Specific (Isimd (SSE2 sse_op))
+          |> make_default ~arg_count ~res_count)
     | Icomp (Isigned intcomp) -> (
       match intcomp with
       | Ceq ->