initial commit

ALU/ALU.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:37:38 10/06/2015 
+// Design Name: 
+// Module Name:    ALU 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ALU(output [W-1:0] R1,
+			  output c_out,
+			  output zero,
+			  input [2:0] ALUOp,
+			  input [W-1:0] R2,
+			  input [W-1:0] R3);
+
+	parameter W = 32;
+
+	//	R1 = R2							MOV
+	wire [W-1:0] w1;	//	R1 = ~R2							NOT
+	wire [W-1:0] w2;	//	R1 = R2 + R3					ADD
+	wire c2;
+	wire [W-1:0] w3;	//	R1 = R2 - R3					SUB
+	wire c3;
+	wire [W-1:0] w4;	//	R1 = R2 | R3					OR
+	wire [W-1:0] w5;	//	R1 = R2 & R3					AND
+	wire [W-1:0] w7;	//	R1 = 1 if R2 < R3, else 0	SLT (signed)
+
+	Para_Not		#(.W(W))	PN		(w1, R2);
+	Para_Adder	#(.W(W))	PAdd1	(c2, w2, R2, R3, 1'b0);
+	Para_Adder	#(.W(W))	PAdd2	(c3, w3, R2, ~R3, 1'b1);
+	Para_Or		#(.W(W))	PO		(w4, R2, R3);
+	Para_And		#(.W(W))	PAnd	(w5, R2, R3);
+	Para_SLT		#(.W(W)) SLT	(w7, R2, R3, 1'b0);
+
+	Para_Mux		#(.W(W))	mux0	(R1, ALUOp, R2, w1, w2, w3, w4, w5, 32'd0, w7);
+	Para_Mux		#(.W(1))	mux1	(c_out, ALUOp, 1'b0, 1'b0, c2, c3, 1'b0, 1'b0, 1'b0, 1'b0);
+
+	assign zero = (R1 == 32'd0) ? 1'd1 : 1'd0;
+
+endmodule

ALU/ALU_tb.v

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+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   18:28:26 10/06/2015
+// Design Name:   ALU
+// Module Name:   /ad/eng/users/g/m/gmerritt/Desktop/tmp/Lab5/ALU_tb.v
+// Project Name:  Lab5
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: ALU
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module ALU_tb;
+
+	parameter W = 16;
+
+	// Inputs
+	reg [2:0] ALUOp;
+	reg [W-1:0] R2;
+	reg [W-1:0] R3;
+
+	reg clk;
+
+	// Outputs
+	wire [W-1:0] R1;
+	wire c_out;
+	//wire c2, c3;
+
+	// Instantiate the Unit Under Test (UUT)
+	ALU 
+	#(.W(W))
+	uut (
+		.R1(R1),
+		.c_out(c_out),
+		.ALUOp(ALUOp), 
+		.R2(R2), 
+		.R3(R3)
+	);
+
+	always #5 clk = ~clk;
+	always #50 R2 = R2 + 1'b1;
+
+	initial begin
+		// Initialize Inputs
+		clk = 0;
+
+		ALUOp = 3'd0;
+		R2 = 16'd0;
+		R3 = 16'd0;
+
+		// Wait 100 ns for global reset to finish
+		#200;
+		ALUOp = 3'd3;
+		R2 = 16'hFFFF;
+		R3 = 16'd1;
+
+		// Add stimulus here
+
+	end
+
+endmodule
+

ALU/ALU_topmodule.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:00:53 10/07/2015 
+// Design Name: 
+// Module Name:    ALU_topmodule 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ALU_topmodule(output [W-1:0] R0,
+							output c_out,
+							input [2:0] ALUOp,
+							input [W-1:0] R2,
+							input [W-1:0] R3,
+							input clk);
+
+	parameter W = 32;
+
+	wire [W-1:0] R1;
+	wire tmp_c_out;
+
+	ALU			#(.W(W))		alu	(R1, tmp_c_out, ALUOp, R2, R3);
+	Para_Reg		#(.W(W))		reg0	(clk, R1, R0);
+	Para_Reg		#(.W(1))		reg1	(clk, tmp_c_out, c_out);
+
+endmodule

ALU/ALU_topmodule_tb.v

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+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   14:21:54 10/07/2015
+// Design Name:   ALU_topmodule
+// Module Name:   /ad/eng/users/g/m/gmerritt/Desktop/tmp/Lab5/ALU_topmodule_tb.v
+// Project Name:  Lab5
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: ALU_topmodule
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module ALU_topmodule_tb;
+
+	parameter W = 8;
+
+	// Inputs
+	reg [2:0] ALUOp;
+	reg [W-1:0] R2;
+	reg [W-1:0] R3;
+	reg clk;
+
+	// Outputs
+	wire [W-1:0] R0;
+	wire c_out;
+	wire c_out_verify;
+	wire [W-1:0] R0_verify;
+	wire error_flag;
+
+	// Instantiate the Unit Under Test (UUT)
+	ALU_topmodule
+	#(.W(W))
+	uut (
+		.R0(R0), 
+		.c_out(c_out), 
+		.ALUOp(ALUOp), 
+		.R2(R2), 
+		.R3(R3), 
+		.clk(clk)
+	);
+
+	// Verification module
+	Verification_ALU 
+	#(.W(W))
+	Verification 
+	(
+		.R0(R0_verify), 
+		.c_out(c_out_verify),
+		.ALUOp(ALUOp), 
+		.R2(R2), 
+		.R3(R3),
+		.clk(clk)
+	);
+
+	// Assign Error_flag
+	assign error_flag = (c_out != c_out_verify || R0 != R0_verify);
+
+	// Verification logic
+	always@(posedge clk)
+		begin
+		if(error_flag)
+			$display("Error occurs when R2 = %d, R3 = %d\n", R2, R3);
+		end
+
+	// Define clk signal for Verfication purpose
+	always #5 clk = ~clk;
+	//always #50 assign ALUOp = ALUOp + 1'b1;
+
+	initial begin
+		// Initialize Inputs
+		ALUOp = 3'd0;
+		R2 = 0;
+		R3 = 0;
+		clk = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		ALUOp = 3'd6;
+
+		R2 = 8'hFA;
+		R3 = 8'h3A;
+
+		#40;
+		R2 = 8'h3A;
+		R3 = 8'hFA;
+
+		#40;
+		R2 = 8'h00;
+		R3 = 8'hFA;
+
+		#40;
+		R2 = 8'h00;
+		R3 = 8'h3A;
+
+		#40;
+		R2 = 8'hFA;
+		R3 = 8'h00;
+
+		#40;
+		R2 = 8'h3A;
+		R3 = 8'h00;
+
+
+		// Add stimulus here
+
+	end
+
+endmodule
+

ALU/Compare_1Bit.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    19:29:29 10/06/2015 
+// Design Name: 
+// Module Name:    Compare_1Bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Compare_1Bit(L_out, a, b, L_in);
+
+	output L_out;
+	input a, b, L_in;
+
+	wire not_a;
+	wire nota_b;
+	wire lin_nota;
+	wire lin_b;
+
+	not	not0	(not_a, a);
+
+	and	and0	(nota_b, not_a, b);
+	and	and1	(lin_nota, L_in, not_a);
+	and	and2	(lin_b, L_in, b);
+
+	or		or0	(L_out, nota_b, lin_nota, lin_b);
+
+endmodule

ALU/Custom_XOR.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:33:35 10/06/2015 
+// Design Name: 
+// Module Name:    Custom_XOR 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Custom_XOR(out, a, b);
+	input a, b;
+	output out;
+
+	wire w0, w1, w2, w3, w4, w5, w6;
+
+	and	and0	(w0, a, b);
+	and	and1	(w2, w1, a);
+	and	and2	(w3, w1, b);
+	and	and3	(w6, w4, w5);
+
+	not	not0	(w1, w0);
+	not	not1	(w4, w2);
+	not	not2	(w5, w3);
+	not	not3	(out, w6);
+
+
+endmodule